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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10147-2E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90820B Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90820B Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
Thank you for purchasing Fujitsu semiconductor products.
The MB90820B series was developed as a group of general-purpose models in the F2MC-16LX series,
which is a family of original 16-bit single-chip microcontrollers that can be used for application specific
IC(ASIC).
This manual is intended for engineers who design products using the MB90820B series of microcontrollers.
The manual describes the functions and operation of the MB90820B series.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■ Organization of this manual
This manual consists of the following 23 chapters and 3 appendices:
CHAPTER 1 OVERVIEW
This chapter describes the main features and basic specifications of the MB90820B series.
CHAPTER 2 CPU
This chapter describes memory space for the MB90820B series.
CHAPTER 3 RESET
This chapter describes the function and operation of the reset for the MB90820B series microcontrollers.
CHAPTER 4 CLOCK
This chapter describes the function and operation of the clock used by MB90820B series
microcontrollers.
CHAPTER 5 CLOCK SUPERVISOR
This chapter describes the functions and operations of the clock supervisor.
CHAPTER 6 LOW-POWER CONSUMPTION MODE
This chapter describes the low-power consumption mode of MB90820B series microcontrollers.
CHAPTER 7 INTERRUPT
This chapter explains the function and operation of the interrupt and extended intelligent I/O service
(EI2OS) in the MB90820B series.
CHAPTER 8 MODE SETTING
This chapter describes the operating modes and memory access modes supported by the MB90820B
series.
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CHAPTER 9 I/O PORTS
This chapter describes the functions and operation of the I/O ports.
CHAPTER 10 TIME-BASE TIMER
This chapter describes the functions and operation of the time-base timer.
CHAPTER 11 WATCHDOG TIMER
This chapter describes the functions and operation of the watchdog timer.
CHAPTER 12 16-BIT RELOAD TIMER
This chapter describes the functions and operations of the 16-bit reload timer.
CHAPTER 13 PWC Timer
This chapter explains the activation and operations of the PWC timer.
CHAPTER 14 16-BIT PPG TIMER
This chapter describes the activation and operation of the 16-bit PPG Timer.
CHAPTER 15 MULTI-FUNCTIONAL TIMER
This chapter describes the functions and operation of the multi-functional timer.
CHAPTER 16 DELAYED INTERRUPT GENERATOR MODULE
This chapter describes the functions and operation of the delayed interrupt generator module.
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
This chapter describes the functions and operation of the DTP/external interrupt circuit.
CHAPTER 18 8/10-Bit A/D Converter
This chapter explains the function and operation of the A/D converter.
CHAPTER 19 D/A CONVERTER
This chapter explains the functions and operation of the digital/analog (D/A) converter.
CHAPTER 20 UART
This chapter explains the functions and operation of UART.
CHAPTER 21 ROM CORRECTION FUNCTION
This chapter describes the functions and operation of the ROM correction function.
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
This chapter explains the function and operation of the MB90820B series ROM mirroring function
selection module.
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
The following explains the functions and operations of the 512K / 1024K bit flash memory.
APPENDIX
APPENDIX A I/O MAP
APPENDIX B EXAMPLE OF F²MC-16LX MB90F822B/F823B CONNECTION FOR SERIAL
WRITING
APPENDIX C INSTRUCTIONS
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.8
2.9
2.9.1
2.9.2
2.9.3
2.9.4
CPU ............................................................................................................ 25
CPU ..................................................................................................................................................
Memory Space ..................................................................................................................................
Memory Maps ...................................................................................................................................
Addressing ........................................................................................................................................
Address Specification by Linear Addressing ...............................................................................
Address Specification by Bank Addressing .................................................................................
Memory Location of Multibyte Data ..................................................................................................
Registers ...........................................................................................................................................
Dedicated Registers .........................................................................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointers (USP, SSP) .........................................................................................................
Processor Status (PS) .................................................................................................................
Condition Code Register (PS: CCR) ..........................................................................................
Register Bank Pointer (PS: RP) ..................................................................................................
Interrupt Level Mask Register (PS: ILM) .....................................................................................
Program Counter (PC) .................................................................................................................
Direct Page Register (DPR) ........................................................................................................
Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................
General-purpose Registers ...............................................................................................................
Prefix Codes .....................................................................................................................................
Bank Select Prefix (PCB, DTB, ADB, SPB) .................................................................................
Common Register Bank Prefix (CMR) .........................................................................................
Flag Change Suppression Prefix (NCC) ......................................................................................
Restrictions on Prefix Codes .......................................................................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.6
OVERVIEW ................................................................................................... 1
MB90820B Series Features ................................................................................................................ 2
MB90820B Series Product Line-up .................................................................................................... 5
Block Diagram of MB90820B Series .................................................................................................. 7
Pin Assignment ................................................................................................................................... 8
Package Dimensions ........................................................................................................................ 10
I/O Pins and Pin Functions ............................................................................................................... 13
I/O Circuit Types ............................................................................................................................... 17
Notes on Handling Devices .............................................................................................................. 21
26
27
29
31
32
33
35
37
38
40
43
46
47
49
50
51
52
53
54
56
57
59
60
61
RESET ........................................................................................................ 63
Reset ................................................................................................................................................
Reset Causes and Oscillation Stabilization Wait Intervals ...............................................................
External Reset Pin ............................................................................................................................
Reset Operation ................................................................................................................................
Reset Cause Bits ..............................................................................................................................
Status of Pins in a Reset ..................................................................................................................
v
64
66
68
69
71
73
CHAPTER 4
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.5
4.6
Clock .................................................................................................................................................
Block Diagram of the Clock Generation Block ..................................................................................
Clock Selection Registers .................................................................................................................
Clock Selection Register (CKSCR) .............................................................................................
PLL Clock Control Register (PCKCR) .........................................................................................
Clock Mode .......................................................................................................................................
Oscillation Stabilization Wait Interval ................................................................................................
Connection of an Oscillator or an External Clock to the Microcontroller ...........................................
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.4
5.5
7.1
7.2
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
7.6.1
7.6.2
90
91
93
94
96
99
LOW-POWER CONSUMPTION MODE ................................................... 101
Low-Power Consumption Mode ......................................................................................................
Block Diagram of the Low-Power Consumption Control Circuit .....................................................
Low-Power Consumption Mode Control Register (LPMCR) ...........................................................
CPU Intermittent Operation Mode ..................................................................................................
Standby Mode .................................................................................................................................
Sleep Mode ...............................................................................................................................
Time-base Timer Mode .............................................................................................................
Stop Mode .................................................................................................................................
State Change Diagram ...................................................................................................................
State of Pins in Standby Mode and During Reset ..........................................................................
Usage Notes on Low-Power Consumption Mode ...........................................................................
CHAPTER 7
76
78
80
81
83
85
87
88
CLOCK SUPERVISOR ............................................................................... 89
Overview of Clock Supervisor ...........................................................................................................
Configuration of Clock Supervisor ....................................................................................................
Registers of Clock Supervisor ..........................................................................................................
Clock Supervisor Control Register (CSVCR) ..............................................................................
Operations of Clock Supervisor ........................................................................................................
Precautions when Using Clock Supervisor .......................................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.6
6.7
6.8
CLOCK ....................................................................................................... 75
102
105
107
110
111
112
115
117
119
122
123
INTERRUPT ............................................................................................. 127
Interrupt ..........................................................................................................................................
Interrupt Causes and Interrupt Vectors ...........................................................................................
Interrupt Control Registers and Peripheral Functions .....................................................................
Interrupt Control Registers (ICR00 to ICR15) ............................................................................
Interrupt Control Register Functions ..........................................................................................
Hardware Interrupt ..........................................................................................................................
Operation of Hardware Interrupt ................................................................................................
Processing for Interrupt Operation ............................................................................................
Procedure for Using Hardware Interrupt ....................................................................................
Multiple Interrupts ......................................................................................................................
Hardware Interrupt Processing Time .........................................................................................
Software Interrupt ...........................................................................................................................
Interrupt of Extended Intelligent I/O Service (EI2OS) .....................................................................
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ........................................................
Registers of EI2OS Descriptor (ISD) .........................................................................................
vi
128
130
133
135
137
140
143
145
146
147
149
151
153
155
156
7.6.3
Operation of the Extended Intelligent I/O Service (EI2OS) ........................................................
7.6.4
Procedure for Using the Extended Intelligent I/O Service (EI2OS) ............................................
7.6.5
Processing Time of the Extended Intelligent I/O Service (EI2OS) .............................................
7.7
Exception Processing Interrupt .......................................................................................................
7.8
Stack Operations for Interrupt Processing ......................................................................................
CHAPTER 8
8.1
8.2
8.3
159
160
161
163
164
MODE SETTING ....................................................................................... 167
Mode Setting ................................................................................................................................... 168
Mode Pins (MD2 to MD0) ............................................................................................................... 169
Mode Data ...................................................................................................................................... 170
CHAPTER 9
I/O PORTS ................................................................................................ 173
9.1
Overview of I/O Ports ......................................................................................................................
9.2
Registers of I/O Ports .....................................................................................................................
9.3
Port 0 .............................................................................................................................................
9.3.1
Port 0 Registers (PDR0, DDR0, and RDR0) .............................................................................
9.3.2
Operation of Port 0 ....................................................................................................................
9.4
Port 1 ..............................................................................................................................................
9.4.1
Port 1 Registers (PDR1, DDR1, and RDR1) .............................................................................
9.4.2
Operation of Port 1 ....................................................................................................................
9.5
Port 2 ..............................................................................................................................................
9.5.1
Port 2 Registers (PDR2, DDR2, and RDR2) .............................................................................
9.5.2
Operation of Port 2 ....................................................................................................................
9.6
Port 3 ..............................................................................................................................................
9.6.1
Port 3 Registers (PDR3, DDR3, and RDR3) .............................................................................
9.6.2
Operation of Port 3 ....................................................................................................................
9.7
Port 4 ..............................................................................................................................................
9.7.1
Port 4 Registers (PDR4 and DDR4) ..........................................................................................
9.7.2
Operation of Port 4 ....................................................................................................................
9.8
Port 5 ..............................................................................................................................................
9.8.1
Port 5 Registers (PDR5 and DDR5) ..........................................................................................
9.8.2
Operation of Port 5 ....................................................................................................................
9.9
Port 6 ..............................................................................................................................................
9.9.1
Port 6 Registers (PDR6, DDR6, and ADER0) ...........................................................................
9.9.2
Operation of Port 6 ....................................................................................................................
9.10 Port 7 ..............................................................................................................................................
9.10.1 Port 7 Registers (PDR7, DDR7, and ADER1) ...........................................................................
9.10.2 Operation of Port 7 ....................................................................................................................
9.11 Port 8 ..............................................................................................................................................
9.11.1 Port 8 Registers (PDR8 and DDR8) ..........................................................................................
9.11.2 Operation of Port 8 ....................................................................................................................
174
176
177
180
182
184
187
189
191
194
196
198
201
203
205
208
209
211
214
215
217
219
221
223
228
230
232
235
236
CHAPTER 10 TIME-BASE TIMER .................................................................................. 239
10.1
10.2
10.3
10.4
Overview of the Time-base Timer ...................................................................................................
Configuration of the Time-base Timer ............................................................................................
Time-base Timer Control Register (TBTC) .....................................................................................
Time-base Timer Interrupts ............................................................................................................
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240
242
244
246
10.5
10.6
Operation of the Time-base Timer .................................................................................................. 247
Usage Notes on the Time-base Timer ............................................................................................ 249
CHAPTER 11 WATCHDOG TIMER ................................................................................ 251
11.1
11.2
11.3
11.4
11.5
Overview of the Watchdog Timer ...................................................................................................
Configuration of the Watchdog Timer .............................................................................................
Watchdog Timer Control Register (WDTC) ....................................................................................
Operation of the Watchdog Timer ...................................................................................................
Usage Notes on the Watchdog Timer .............................................................................................
252
253
255
257
259
CHAPTER 12 16-BIT RELOAD TIMER ........................................................................... 261
12.1 Overview of 16-Bit Reload Timer ....................................................................................................
12.2 Block Diagram of 16-Bit Reload Timer ...........................................................................................
12.3 Pins of 16-Bit Reload Timer ............................................................................................................
12.4 Registers of 16-Bit Reload Timer ....................................................................................................
12.4.1 Upper Bits of Timer Control Status Registers (TMCSRH0/TMCSRH1) .....................................
12.4.2 Lower Bits of Timer Control Status Registers (TMCSRL0/TMCSRL1) ......................................
12.4.3 16-Bit Timer Registers (TMR0/TMR1) .......................................................................................
12.4.4 16-Bit Reload Registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) ...........................................
12.5 Interrupts of 16-Bit Reload Timer ....................................................................................................
12.6 Operation of 16-Bit Reload Timer ...................................................................................................
12.6.1 Internal Clock Mode (Reload Mode) ..........................................................................................
12.6.2 Internal Clock Mode (One-Shot Mode) ......................................................................................
12.6.3 Event Count Mode .....................................................................................................................
12.7 Notes on Using the 16-Bit Reload Timer ........................................................................................
262
265
267
268
269
271
273
274
275
276
278
281
284
286
CHAPTER 13 PWC Timer ............................................................................................... 287
13.1 Overview of the PWC Timer ...........................................................................................................
13.2 Block Diagram of the PWC Timer ...................................................................................................
13.3 PWC Timer Pins .............................................................................................................................
13.4 PWC Timer Registers .....................................................................................................................
13.4.1 PWC Control Status Register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) ................................
13.4.2 PWC Data Buffer Register (PWC0/PWC1) ...............................................................................
13.4.3 Division Ratio Control Register (DIV0/DIV1) .............................................................................
13.5 PWC Timer Interrupts .....................................................................................................................
13.6 Operation of the PWC Timer ..........................................................................................................
13.6.1 Operation Mode Selection .........................................................................................................
13.6.2 Starting and Stopping the Timer and Pulse-width Measurement and Clearing the Timer .........
13.6.3 Timer Mode Operation ...............................................................................................................
13.6.4 Pulse Width Measurement Mode Operation ..............................................................................
13.7 Usage Notes on the PWC Timer ....................................................................................................
288
289
290
293
294
299
301
302
304
307
309
311
314
319
CHAPTER 14 16-BIT PPG TIMER .................................................................................. 321
14.1
14.2
14.3
14.4
Overview of 16-bit PPG Timer ........................................................................................................
Block Diagram of 16-bit PPG Timer ................................................................................................
16-bit PPG Timer Pins ....................................................................................................................
16-bit PPG Timer Registers ............................................................................................................
viii
322
323
324
326
14.4.1 PPG Down Counter Register (PDCR0 to PDCR2) ....................................................................
14.4.2 PPG Period Setting Buffer Register (PCSR0 to PCSR2) ..........................................................
14.4.3 PPG Duty Setting Buffer Register (PDUT0 to PDUT2) .............................................................
14.4.4 PPG Control Status Register (PCNTL0 to PCNTL2, PCNTH0 to PCNTH2) .............................
14.5 16-bit PPG Timer Interrupts ............................................................................................................
14.6 Operation of 16-bit PPG Timer .......................................................................................................
14.7 Usage Notes on the 16-bit PPG Timer ...........................................................................................
328
329
330
331
336
338
342
CHAPTER 15 MULTI-FUNCTIONAL TIMER .................................................................. 343
15.1 Overview of Multi-functional Timer .................................................................................................
15.2 Block Diagram of Multi-functional Timer .........................................................................................
15.3 Multi-functional Timer Pins .............................................................................................................
15.4 Registers of Multi-functional Timer .................................................................................................
15.4.1 Compare Clear Buffer Register (CPCLRB) and Compare Clear Register (CPCLR) .................
15.4.2 Timer Data Register (TCDT) .....................................................................................................
15.4.3 Timer Control Status Register (TCCSH, TCCSL) ......................................................................
15.4.4 Output Compare Buffer Registers (OCCPB0 to OCCPB5)/Output Compare Registers
(OCCP0 to OCCP5) ..................................................................................................................
15.4.5 Compare Control Registers (OCS0 to OCS5) ...........................................................................
15.4.6 Input Capture Register (IPCP0 to IPCP3) .................................................................................
15.4.7 Input Capture Control Status Registers (ICS23, PICS01) .........................................................
15.4.8 16-bit Timer Register (TMRR0 to TMRR2) ................................................................................
15.4.9 16-bit Timer Control Register (DTCR0 to DTCR2) ....................................................................
15.4.10 Waveform Control Register (SIGCR) ........................................................................................
15.5 Multi-functional Timer Interrupts .....................................................................................................
15.6 Operation of Multi-functional Timer .................................................................................................
15.6.1 Operation of 16-bit Free-run Timer ............................................................................................
15.6.2 Operation of 16-bit Output Compare .........................................................................................
15.6.3 Operation of 16-bit Input Capture ..............................................................................................
15.6.4 Operation of Waveform Generator ............................................................................................
15.7 Usage Notes on the Multi-functional Timer .....................................................................................
344
346
350
353
357
358
359
364
366
371
372
380
381
385
387
391
392
398
403
405
416
CHAPTER 16 DELAYED INTERRUPT GENERATOR MODULE ................................... 419
16.1
16.2
16.3
16.4
Overview of the Delayed Interrupt Generator Module ....................................................................
Delayed Interrupt Generator Module Register ................................................................................
Operation of the Delayed Interrupt Generator Module ...................................................................
Usage Notes on the Delayed Interrupt Generator Module .............................................................
420
421
422
423
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 425
17.1 Overview of the DTP/External Interrupt Circuit ...............................................................................
17.2 Block Diagram of the DTP/External Interrupt Circuit ......................................................................
17.3 DTP/External Interrupt Circuit Pins .................................................................................................
17.4 DTP/External Interrupt Circuit Registers .........................................................................................
17.4.1 DTP/external interrupt cause register (EIRR) ............................................................................
17.4.2 DTP/external interrupt enable register (ENIR) ...........................................................................
17.4.3 Request Level Setting Register (ELVR) ....................................................................................
17.5 Operation of the DTP/External Interrupt Circuit ..............................................................................
ix
426
428
430
432
433
434
436
438
17.5.1 External Interrupt Function ........................................................................................................ 441
17.5.2 DTP Function ............................................................................................................................. 442
17.6 Usage Notes on the DTP/External Interrupt Circuit ........................................................................ 444
CHAPTER 18 8/10-Bit A/D Converter ............................................................................ 447
18.1 Overview of 8/10-Bit A/D Converter ................................................................................................
18.2 Block Diagram of 8/10-Bit A/D Converter .......................................................................................
18.3 Configuration of 8/10-Bit A/D Converter .........................................................................................
18.3.1 A/D Control Status Registers High Order (ADCS1) ...................................................................
18.3.2 A/D Control Status Register Low Order (ADCS0) .....................................................................
18.3.3 A/D Data Register (ADCR0/ADCR1) .........................................................................................
18.3.4 A/D Setting Register (ADSR0/ADSR1) ......................................................................................
18.3.5 Analog Input Enable Resister (ADER0/ADER1) ........................................................................
18.4 Interrupt of 8/10-Bit A/D Converter .................................................................................................
18.5 Operation of 8/10-Bit A/D Converter ...............................................................................................
18.5.1 Single Conversion Mode ...........................................................................................................
18.5.2 Continuous Conversion Mode ...................................................................................................
18.5.3 Stop Conversion Mode ..............................................................................................................
18.5.4 Conversion Using EI2OS ...........................................................................................................
18.5.5 A/D Converted Data Protection Function ..................................................................................
18.6 Precautions for Using the 8/10-Bit A/D Converter ..........................................................................
448
450
453
455
459
461
462
467
468
469
470
472
474
476
478
482
CHAPTER 19 D/A CONVERTER .................................................................................... 483
19.1 Overview of D/A Converter .............................................................................................................
19.2 Block Diagram of D/A Converter .....................................................................................................
19.3 D/A Converter Pins .........................................................................................................................
19.4 D/A Converter Registers .................................................................................................................
19.4.1 D/A Converter Register 1 (DAT1) ..............................................................................................
19.4.2 D/A Converter Register 0 (DAT0) ..............................................................................................
19.4.3 D/A Control Register 1 (DACR1) ...............................................................................................
19.4.4 D/A Control Register 0 (DACR0) ...............................................................................................
484
485
486
487
488
489
490
491
CHAPTER 20 UART ........................................................................................................ 493
20.1 Overview of UART ..........................................................................................................................
20.2 Block Diagram of UART ..................................................................................................................
20.3 UART Pins ......................................................................................................................................
20.4 UART Registers ..............................................................................................................................
20.4.1 Serial Control Register (SCR0/SCR1) .......................................................................................
20.4.2 Serial Mode Register (SMR0/SMR1) .........................................................................................
20.4.3 Serial Status Register (SSR0/SSR1) .........................................................................................
20.4.4 Serial Input Data Register (SIDR0/SIDR1) and Serial Output Data Register (SODR0/SODR1)
....................................................................................................................................................
20.4.5 Communication Prescaler Control Register (CDCR) .................................................................
20.5 UART Interrupts ..............................................................................................................................
20.5.1 Reception Interrupt Request Generation and Flag Set Timing ..................................................
20.5.2 Transmission Interrupt Request Generation and Flag Set Timing ............................................
20.6 UART Baud Rates ..........................................................................................................................
x
494
496
499
502
503
505
508
510
512
514
516
518
520
20.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ........................................
20.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer) ..................................
20.6.3 Baud Rates Determined Using the External Clock ....................................................................
20.7 Operation of UART .........................................................................................................................
20.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................
20.7.2 Operation in Clock Synchronous Mode (Operation Mode 2) .....................................................
20.7.3 Bidirectional Communication Function (Normal Mode) .............................................................
20.7.4 Master-slave Communication Function (Multiprocessor Mode) .................................................
20.8 Usage Notes on UART ...................................................................................................................
522
525
527
528
530
532
534
536
539
CHAPTER 21 ROM CORRECTION FUNCTION ............................................................. 541
21.1 Overview of the ROM Correction Function .....................................................................................
21.2 Block Diagram of ROM Correction Function ...................................................................................
21.3 ROM Correction Function Registers ...............................................................................................
21.3.1
Program Address Detection Register (PADR0/PADR1) ...........................................................
21.3.2
Program Address Detection Control Status Register (PACSR) ...............................................
21.4 Operation of the ROM Correction Function ....................................................................................
21.5 Example of Using ROM Correction Function ..................................................................................
542
543
544
545
546
548
549
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 553
22.1
22.2
Overview of the ROM Mirroring Function Selection Module ........................................................... 554
ROM Mirroring Function Selection Register (ROMM) .................................................................... 555
CHAPTER 23 512K / 1024K BIT FLASH MEMORY ....................................................... 557
23.1 Overview of the 512K / 1024K Bit Flash Memory ...........................................................................
23.2 512K / 1024K Bit Flash Memory Sector Configuration ...................................................................
23.3 Flash Memory Control Status Register (FMCS) .............................................................................
23.4 Method of Starting the Automatic Algorithm in Flash Memory ........................................................
23.5 Verifying Automatic Algorithm Execution Status .............................................................................
23.5.1 Data Polling Flag (DQ7) ............................................................................................................
23.5.2 Toggle Bit Flag (DQ6) ................................................................................................................
23.5.3 Time limit Exceeded Flag (DQ5) ...............................................................................................
23.5.4 Sector Deletion Timer Flag (DQ3) .............................................................................................
23.6 Detailed Explanation on the Flash Memory Write/Delete ...............................................................
23.6.1 Setting the Read/Reset Status ..................................................................................................
23.6.2 Writing the Data .........................................................................................................................
23.6.3 Deleting All Data (Chip Deletion) ...............................................................................................
23.6.4 Deleting Arbitrary Data (Sector Deletion) ..................................................................................
23.6.5 Temporarily Stopping the Sector Deletion .................................................................................
23.6.6 Restarting the Sector Deletion ...................................................................................................
23.7 Flash Security Feature ....................................................................................................................
558
559
560
563
564
566
568
570
571
572
573
574
576
577
579
580
581
APPENDIX ......................................................................................................................... 583
APPENDIX A I/O Map ................................................................................................................................
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for Serial Writing ........................
B.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard) .........................................
B.2 Example of Connection for Serial Writing (When Power Supplied by User) ..................................
xi
584
590
591
594
B.3
B.4
Example of Connection for Serial Writing (When Power Supplied from Writer) .............................
Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied by User) ....................................................................................................
B.5 Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied from Writer) ..............................................................................................
APPENDIX C Instructions ...........................................................................................................................
C.1 Instruction Types ............................................................................................................................
C.2 Addressing .....................................................................................................................................
C.3 Direct Addressing ...........................................................................................................................
C.4 Indirect Addressing ........................................................................................................................
C.5 Execution Cycle Count ...................................................................................................................
C.6 Effective address field ....................................................................................................................
C.7 How to Read the Instruction List ....................................................................................................
C.8 F2MC-16LX Instruction List ............................................................................................................
C.9 Instruction Map ...............................................................................................................................
596
598
600
602
603
604
606
612
620
623
624
627
641
INDEX................................................................................................................................... 663
xii
Main changes in this edition
Page
-
7
CHAPTER 1 OVERVIEW
1.3 Block Diagram of
MB90820B Series
64
CHAPTER 3 RESET
3.1 Reset
65
Changes (For details, refer to main body.)
Added Part number (MB90F828B)
Added "CHAPTER 5 CLOCK SUPERVISOR"
Changed Package
("FPT-80P-M05" → "FPT-80P-M21")
("FPT-80P-M11" → "FPT-80P-M22")
Changed "Figure 1.3-1 MB90820B Series Overall Block Diagram"
Changed "Table3.1-1 Reset causes"
(Added "Clock supervisor reset")
Changed "■ Reset Causes"
(Added "● Clock supervisor reset")
66
CHAPTER 3 RESET
3.2 Reset causes and
oscillation stabilization
wait intervals
Changed "Table3.2-1 Reset causes and oscillation stabilization wait intervals"
(Added "Clock supervisor reset")
69
CHAPTER 3 RESET
3.4 Reset Operation
Changed "Figure 3.4-1 Reset Operation flow"
(Added "Clock supervisor reset")
71
72
Changed "Figure 3.5-1 Block Diagram of reset cause bits"
CHAPTER 3 RESET
3.5 Reset Cause Bits
Changed "Table3.5-1 Correspondence between reset cause flag bits and reset causes"
(Added "Clock supervisor reset")
CHAPTER 4 CLOCK
4.1 Clock
Changed "Figure 4.1-1 Clock Supply Map"
CHAPTER 4 CLOCK
4.2 Block Diagram of
the Clock Generation
Block
Changed "• Clock selector → • Operating Clock selector"
Changed "Figure 4.2-1 Block Diagram of the clock generation block"
Changed "Figure 6.2-1 Block Diagram of the low-power consumption control
circuit"
105
CHAPTER 6 LOWPOWER CONSUMPTION MODE
6.2 Block Diagram of
the Low-Power Consumption Control Circuit
Changed "■ Operation of the ROM Correction Function"
(Added "Notes")
548
CHAPTER 21 ROM
CORRECTION FUNCTION
21.4 Operation of the
ROM Correction Function
77
78
79
Changed "● Clock selector → ● Operating Clock selector"
xv
Page
Changes (For details, refer to main body.)
Changed Table(Address 1, Address 2) in "■ ROM mirroring function selection
register (ROMM)"
556
CHAPTER 22 ROM
NIRRORING FUNCTION SELECTION
MODULE
22.2 ROM mirroring
function selection register(ROMM)
587
APPENDIX
APPENDIX A I/O Map
Changed "Address 00008AH" in "TableA-1 I/O map"
602
to
662
APPENDIX
APPENDIX C
Instructions
Changed the entire part of "APPENDIX C Instructions"
The vertical lines marked in the left side of the page show the changes.
xvi
CHAPTER 1
OVERVIEW
This chapter describes the main features and basic
specifications of the MB90820B series.
CM44-10147-2E
1.1
MB90820B Series Features
1.2
MB90820B Series Product Line-up
1.3
Block Diagram of MB90820B Series
1.4
Pin Assignment
1.5
Package Dimensions
1.6
I/O Pins and Pin Functions
1.7
I/O Circuit Types
1.8
Notes on Handling Devices
FUJITSU MICROELECTRONICS LIMITED
1
CHAPTER 1 OVERVIEW
1.1
1.1
MB90820B Series
MB90820B Series Features
The MB90820B series is a line of general-purpose, 16-bit microcontrollers designed for
those applications which require high-speed real-time processing, proving to be
suitable for various industrial machines and motor control (AC induction motor and
brushless DC motor). These microcontrollers consist of a multi-functional timer for AC/
DC motor control and a multi-pulse generator for DC motor control, which can generate
various type of waveform.
The instruction set is designed to be optimized for controller applications which
inheriting the AT architecture of F2MC-16LX series and allow a wide range of control
tasks to be processed efficiently at high speed.
■ MB90820B Series Features
● Clock
• Embedded PLL clock multiplication circuit
• Operating clock (PLL clock) can selected from divided-by-2 of oscillation, one to four times or six
times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz or 24MHz)
• Minimum instruction execution time of 42 ns (at oscillation of 4 MHz, six times the PLL clock,
operation at Vcc of 5.0 V)
● CPU addressing space of 16 Mbytes
• Internal 24-bit addressing
● Instruction set optimized for controller applications
• Rich data types (bit, byte, word, long word)
• Rich addressing mode (23 types)
• High code efficiency
• Enhanced precision calculation realized by the 32-bit accumulator
● Instruction set designed for H level language (C) and multi-task operations
• Adoption of system stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
● Program patch function (2 address pointer)
● Improved execution speed
4-byte instruction queue
2
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.1
MB90820B Series
● Powerful interrupt function
• Priority level programmable: 8 levels
• 32 factors of stronger interrupt function
● Automatic data transmission function independent of CPU operation
• Extended intelligent I/O service function (EI2OS)
• Maximum 16 channels
● Low-power consumption (standby) mode
• Sleep mode (mode in which CPU operating clock is stopped)
• Time-base timer mode (mode in which other than oscillation and time-base timer are stopped)
• Stop mode (mode in which oscillation is stopped)
• CPU intermittent operation mode
● Package
• LQFP-80 (FPT-80P-M21: 0.50 mm pitch)
• LQFP-80 (FPT-80P-M22: 0.65 mm pitch)
• QFP-80 (FPT-80P-M06: 0.80 mm pitch)
● Process
CMOS technology
■ Internal Peripheral Features
● I/O port
Maximum of 66 ports
● 18-bit time-base counter/watchdog timer: 1 channel
● Watchdog timer: 1 channel
● PWC: 2 channels
● 16-bit reload timer: 2 channels
● 16-bit PPG timer: 3 channels
● Multi-functional timer (for AC/DC motor control): 1 channel
• 16-bit free-run timer with up or up-down mode selection and buffer: 1 channel
• 16-bit output compare with buffer: 6 channels
• 16-bit input capture: 4 channels
• 16-bit PPG timer: 1 channel
• Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
3
CHAPTER 1 OVERVIEW
1.1
MB90820B Series
● UART: 2 channels
• With full-duplex double buffer (8-bit length)
• Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively
used
● DTP/External interrupt circuit: 8 channels
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt
triggered by an external input
● Delayed interrupt generation module
Generates an interrupt request for switching tasks
● 8/10-bit A/D converter: 16 channels
Selectable 8/10-bit resolution
● 8-bit D/A converter: 2 channels
● Clock supervisor
4
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.2
MB90820B Series
1.2
MB90820B Series Product Line-up
The MB90820B series contains 3 different devices. Table 1.2-1 lists the product line-up.
■ MB90820B Series Product Line-up
Table 1.2-1 MB90820B Series Product Line-up (1 / 2)
Part number
MB90V820B
MB90F822B
MB90F823B
MB90F828B
MB90822B
MB90823B
Item
Classification
Development /
evaluation
product
ROM size
—
RAM size
16K Bytes
CPU function
I/O port
PWC
UART
16-bit reload
timer
16-bit PPG
timer
Mass-produced products
(Flash ROM with flash security)
64K Bytes
128K Bytes
4K Bytes
Mass-produced product
(Mask ROM)
128K Bytes
64K Bytes
8K Bytes
Number of instruction
Minimum execution time
Addressing mode
Data bit length
Maximum memory space
I/O port (CMOS)
: 351
: 42 ns / 4 MHz (PLL: 4MHz x 6)
: 23
: 1, 8, 16 bits
: 16 MBytes
: 66
Pulse width counter timer
: 2 channels
4K Bytes
Timer function (select the counter timer from three internal clocks)
Various pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period,
falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period)
UART
: 2 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selected and
used.
Transmission can be one-to-one (bidirectional commuication) or one-to-n (master-slave communication)
Reload timer
: 2 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer
: 3 channels
PWM mode or single-shot mode selectable
Channel 0 can be worked with multi-functional timer or individually
16-bit free-run timer with up or up-down mode selection and buffer: 1 channel
Multi-functional
16-bit output compare
: 6 channels
timer
16-bit input capture
: 4 channels
(for AC/DC
16-bit PPG timer
: 1 channel
motor control)
Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
8/10-bit A/D
converter
Clock supervisor
8-bit D/A
converter
CM44-10147-2E
8/10-bit resolution (16 channels)
Conversion time
No
: Min. 3 µs (24 MHz internal clock, including sampling time)
Yes
No
8-bit resolution (2 channels)
FUJITSU MICROELECTRONICS LIMITED
5
CHAPTER 1 OVERVIEW
1.2
MB90820B Series
Table 1.2-1 MB90820B Series Product Line-up (2 / 2)
Part number
MB90V820B
MB90F822B
MB90F823B
MB90F828B
MB90822B
MB90823B
Item
DTP/External
interrupt
8 independent channels
Selectable causes
Low-power
consumption
Stop mode / Sleep mode / CPU intermittent operation mode
Package
Power supply
voltage for
operation
PGA299
4.5 V to 5.5
Process
Emulator power
supply*2
V*1
: Rising edge, falling edge, "L" level or "H" level
LQFP-80 (FPT-80P-M21 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M22 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
3.5 V to 5.5 V : other than conditions listed below
4.0 V to 5.5 V : if A/D converter is used
4.5 V to 5.5 V : if D/A converter is used / writing to FLASH
CMOS
Yes
—
*1: The guaranteed operating temperature range for the MB90V820B is 0 to +25 .
*2: These are the jumper switch (TOOL, VCC) settings for using the emulator (MB2147-01). See "3.3 Selecting the Power Supply for the
Emulator" in the hardware manual for the MB2147-01 and MB2147-20 for details.
6
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.3
MB90820B Series
1.3
Block Diagram of MB90820B Series
Figure 1.3-1 show the MB90820B series overall block diagram.
■ MB90820B Series Block Diagram
Figure 1.3-1 MB90820B Series Overall Block Diagram
CR oscillator circuit*2
CPU
F2MC-16LX series core
X0
Clock control / monitor circuit
X1
Other pins
Vss x 2, Vcc x 2, MD2 to MD0, C
*2
Time-base timer
RSTX
Reset circuit
(Watchdog timer)
Delayed interrupt generator
Interrupt controller
Multi-functional timer
7
P37/PPG0
16-bit PPG
(ch.0)
P51/INT7
6
P45/SIN0
P44/SOT0
P43/SCK0
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P40/PPG1
P50/PPG2
P46/PWI1
P47/PWO1
8
DTP/External interrupt
16-bit input capture
(ch.0 to ch.3)
4
4
16-bit free-run
timer
P75/FRCK/AN13
UART1
16-bit PPG
(ch.1)
16-bit PPG
(ch.2)
PWC1
P82/RTO0 (U)*1
P83/RTO1 (X)*1
P84/RTO2 (V)*1
P85/RTO3 (Y)*1
P86/RTO4 (W)*1
P87/RTO5 (Z)*1
16-bit output
compare
(ch.0 to ch.5)
Waveform
generator
P10/INT0/DTTI
P17
P06/PWI0*1
P07/PWO0*1
PWC0
6
CMOS I/O port 0, 1, 3, 7, 8
P42/TO0
P41/TIN0
P21/TO1
P20/TIN1
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
UART0
F2MC-16LX bus
P16/INT6 to
P11/INT1
P30 to P36
P00 to P05*1
16-bit reload timer 0
CMOS I/O port 6
16-bit reload timer 1
A/D converter
CMOS I/O port 1, 2, 4, 5, 7
16
(8/10 bit)
RAM
AVR
AVCC
ROM
ROM correction
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVSS
8-bit D/A converter
P70/DA0/AN8
P71/DA1/AN9
ROM mirroring
CMOS I/O port 7
*1: High current drive pin.
*2: MB90F828B
Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With selectable built-in registers that can be used as input pull-up resistors.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
7
CHAPTER 1 OVERVIEW
1.4
1.4
MB90820B Series
Pin Assignment
Figure 1.4-1, Figure 1.4-2 show the pin assignment diagrams for the MB90820B series.
■ FPT-80P-M06 Pin Assignment
P87/RTO5(Z)*
P86/RTO4(W)*
P85/RTO3(Y)*
P84/RTO2(V)*
P83/RTO1(X)*
P82/RTO0(U)*
P81/IN3
P80/IN2
P77/IN1/AN15
P76/IN0/AN14
P75/FRCK/AN13
P74/SCK1/AN12
P73/SOT1/AN11
P72/SIN1/AN10
P71/DA1/AN9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P70/DA0/AN8
Figure 1.4-1 FPT-64P-M06 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
QFP-80
(TOP VIEW)
(FPT-80P-M06)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C
Vss
Vcc
P00*
P01*
P02*
P03*
P04*
P05*
P06/PWI0*
P07/PWO0*
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
Vcc
P23
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVR
AVcc
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
X0
X1
*:High current pin
8
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.4
MB90820B Series
■ FPT-80P-M21/FPT-80P-M22 Pin Assignment
Vss
C
P87/RTO5(Z)*
P86/RTO4(W)*
P85/RTO3(Y)*
P84/RTO2(V)*
P83/RTO1(X)*
P82/RTO0(U)*
P81/IN3
P80/IN2
P77/IN1/AN15
P76/IN0/AN14
P75/FRCK/AN13
P74/SCK1/AN12
P73/SOT1/AN11
P72/SIN1/AN10
P71/DA1/AN9
P70/DA0/AN8
AVR
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AVcc
Figure 1.4-2 FPT-80P-M21/FPT-80P-M22 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LQFP-80
(TOP VIEW)
(FPT-80P-M21)
(FPT-80P-M22)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Vcc
P00*
P01*
P02*
P03*
P04*
P05*
P06/PWI0*
P07/PWO0*
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
X0
X1
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
Vcc
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
*:High current pin
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
9
CHAPTER 1 OVERVIEW
1.5
1.5
MB90820B Series
Package Dimensions
Three types of packages are available for MB90820B series.
Figure 1.5-1 to Figure 1.5-3 show the package dimensions.
■ FPT-80P-M21 Package Dimensions
Figure 1.5-1 FPT-80P-M21 Package Dimensions
80-pin plastic LQFP
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
Lead pitch
0.50 mm
Package width ×
package length
12 mm × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.47 g
Code
(Reference)
P-LFQFP80-12×12-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
61
40
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
0˚~8˚
80
(Mounting height)
0.10±0.05
(.004±.002)
(Stand off)
21
"A"
LEAD No.
1
20
0.50(.020)
0.20±0.05
(.008±.002)
0.08(.003)
©2006-2008
FUJITSU MICROELECTRONICS LIMITED F80035S-c-2-3
C
2006 FUJITSU LIMITED F80035S-c-2-2
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
10
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.5
MB90820B Series
■ FPT-80P-M06 Package Dimensions
Figure 1.5-2 FPT-80P-M06 Package Dimensions
80-pin plastic QFP
Lead pitch
0.80 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP80-14×20-0.80
(FPT-80P-M06)
80-pin plastic QFP
(FPT-80P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
64
41
40
65
0.10(.004)
17.90±0.40
(.705±.016)
* 14.00±0.20
(.551±.008)
INDEX
Details of "A" part
25
80
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
0.37±0.05
(.015±.002)
0.16(.006)
0~8°
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
"A"
C
2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
11
CHAPTER 1 OVERVIEW
1.5
MB90820B Series
■ FPT-80P-M22 Package Dimensions
Figure 1.5-3 FPT-80P-M22 Package Dimensions
80-pin plastic LQFP
(FPT-80P-M22)
80-pin plastic LQFP
(FPT-80P-M22)
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.62 g
Code
(Reference)
P-LFQFP80-14×14-0.65
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
40
61
0.10(.004)
Details of "A" part
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
21
80
1
"A"
20
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
©2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2
C
2007 FUJITSU LIMITED F80036S-c-1-1
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
12
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.6
MB90820B Series
1.6
I/O Pins and Pin Functions
Table 1.6-1 lists the MB90820B series I/O pins and their functions. Table 1.7-1 lists the I/O circuit types.
The letter in the “I/O circuit type” column in Table 1.6-1 refers to the letter in the “Type” column in Table 1.7-1.
■ I/O Pins and Pin Functions
Table 1.6-1 Pin Description (1 / 4)
Pin no.
Pin name
I/O
circuit
Pin status
during
reset
Function
LQFP*1
QFP*2
21, 22
23, 24
X0, X1
A
Oscillating Oscillation input pins.
17
19
RST
B
Reset input External reset input pin.
59 to 54
61 to 56
P00 to P05
C
53
55
P06
General-purpose I/O ports.
C
PWI0
PWC 0 signal input pin.
P07
52
54
General-purpose I/O ports.
C
PWO0
PWC 0 signal output pin.
P10
51
53
INT0
General-purpose I/O ports.
D
Can be used as interrupt request input channel 0. Input is
enabled when 1 is set in EN0 in standby mode.
RTO0 to RTO5 pins for fixed-level input. This function is
enabled when the waveform generator enables its input bits.
DTTI
P11 to P16
General-purpose I/O ports.
50 to 45
52 to 47
INT1 to
INT6
D
44
46
P17
D
43
45
P20
Can be used as interrupt request input channels 1 to 6. Input is
enabled when 1 is set in EN1 to EN6 in standby mode.
Port input General-purpose I/O ports.
General-purpose I/O ports.
D
TIN1
External clock input pin for reload timer 1.
P21
42
General-purpose I/O ports.
44
General-purpose I/O ports.
D
TO1
Event output pin for reload timer 1.
41, 39 to
35
43, 41 to
37
P22 to P27
D
General-purpose I/O ports.
34 to 28
36 to 30
P30 to P36
E
General-purpose I/O ports.
P37
27
29
General-purpose I/O ports.
E
PPG0
P40
26
28
CM44-10147-2E
General-purpose I/O ports.
F
PPG1
Output pins for PPG channel 0. This function is enabled when
PPG channel 0 enables output.
Output pins for PPG channel 1. This function is enabled when
PPG channel 1 enables output.
FUJITSU MICROELECTRONICS LIMITED
13
CHAPTER 1 OVERVIEW
1.6
MB90820B Series
Table 1.6-1 Pin Description (2 / 4)
Pin no.
Pin name
LQFP*1
QFP*2
19
21
I/O
circuit
Pin status
during
reset
P41
General-purpose I/O ports.
F
TIN0
External clock input pin for reload timer 0.
P42
18
16
20
General-purpose I/O ports.
F
TO0
Event output pin for reload timer 0.
P43
General-purpose I/O ports.
18
F
Serial clock I/O pin for UART0. This function is enabled when
UART0 enables clock output.
SCK0
P44
15
17
General-purpose I/O ports.
F
Serial data output pin for UART0. This function is enabled
when UART 0 enables data output.
SOT0
P45
14
16
General-purpose I/O ports.
G
SIN0
Serial data input pin for UART0. While UART0 is operating
Port Input for input, the input of this pin is used as required and must not
be used for any other input.
CMOS input can be selected by user program.
P46
13
15
General-purpose I/O ports.
F
PWI1
PWC 1 signal input pin.
P47
12
14
General-purpose I/O ports.
F
PWO1
PWC 1 signal output pin.
P50
11
13
General-purpose I/O ports.
F
Output pins for PPG channel 2. This function is enabled when
PPG channel 2 enables output.
PPG2
P51
10
12
General-purpose I/O ports.
F
Usable as interrupt request input channel 7. Input is enabled
when 1 is set in EN7 in standby mode.
INT7
P60 to P67
9 to 2
11 to 4
AN0 to
AN7
General-purpose I/O ports.
H
P70, P71
78, 77
80, 79
DA0, DA1
AN8, AN9
14
Function
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER0).
Analog
input
I
General-purpose I/O ports.
D/A converter analog output pins. This function is enabled
when D/A converter is enabled.
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.6
MB90820B Series
Table 1.6-1 Pin Description (3 / 4)
Pin no.
Pin name
LQFP*1
76
QFP*2
78
I/O
circuit
Pin status
during
reset
P72
General-purpose I/O ports.
SIN1
Serial data input pin for UART1. While UART1 is operating
for input, the input of this pin is used as required and must not
be used for any other input.
CMOS input can be selected by user program.
J
Analog
input
AN10
P73
75
77
SOT1
Serial data output pin for UART1. This function is enabled
when UART1 enables data output.
K
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
P74
76
SCK1
General-purpose I/O ports.
Serial clock I/O pin for UART1. This function is enabled when
UART1 enables clock output.
K
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
AN12
P75
73
75
FRCK
General-purpose I/O ports.
K
AN13
72, 71
74, 73
IN0, IN1
Trigger input pins for input capture channels 0 to 1.
When input capture channels 0 to 1 are used for input
operation, these pins are enabled as required and must not be
used for any other input capture.
72, 71
K
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
General-purpose I/O ports.
F
IN2, IN3
P82 to P87
70 to 65
CM44-10147-2E
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
General-purpose I/O ports.
P80, P81
68 to 63
External clock input pin for free-run timer.
Analog
input
P76, P77
AN14,
AN15
70, 69
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
General-purpose I/O ports.
AN11
74
Function
RTO0 to
RTO5
Trigger input pins for input capture channels 2 to 3.
When input capture channels 2 to 3 are used for input
operation, these pins are enabled as required and must not be
Port input used for any other input capture.
General-purpose I/O ports.
L
Waveform generator output pins. These pins output the
waveforms specified at the waveform generator. Output is
generated when waveform generator output is enabled.
FUJITSU MICROELECTRONICS LIMITED
15
CHAPTER 1 OVERVIEW
1.6
MB90820B Series
Table 1.6-1 Pin Description (4 / 4)
Pin no.
LQFP*1
QFP*2
23
25
Pin name
I/O
circuit
MD0
M
Pin status
during
reset
Mode
input
Function
Input pin for operation mode specification. Connect this pin
directly to Vcc or Vss.
24, 25
26, 27
MD1, MD2
N
Input pins for operation mode specification. Connect these
pins directly to Vcc or Vss.
80
2
AVCC
–
Vcc power input pin for analog circuits.
79
1
AVR
–
1
3
AVSS
–
20, 61
22, 63
Vss
–
Power
Vref+ input pin for the A/D converter. This voltage must not
exceed AVcc. Vref- is fixed to AVss.
Vss power input pin for analog circuits.
Power (0 V) input pin.
Power
40, 60
42, 62
Vcc
–
62
64
C
–
Power (5 V) input pin.
–
Capacity pin for power stabilization. Please connect to an
approximately 0.1 µF ceramic capacitor.
*1: FPT-80P-M21, FPT-80P-M22
*2: FPT-80P-M06
*3: See Section "1.7 I/O Circuit Types" for information on the circuit types.
16
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.7
MB90820B Series
1.7
I/O Circuit Types
Table 1.7-1 summarize the I/O circuit types of MB90820B series
■ I/O Circuit Types
Table 1.7-1 I/O Circuit Type (1 / 4)
Type
A
Circuit
Remarks
X1
Xout
N-ch P-ch
Main clock (main clock crystal
oscillator)
• Oscillation feedback resistor of
approximately 1 MΩ
P-ch
X0
N-ch
Standby control signal
B
R
C
R
P-ch
•
•
Hysteresis input
Resistor approximately
50 kΩ
•
•
•
CMOS output
Hysteresis input
Selectable pull-up resistor
approximately 50 kΩ
IOL = 12 mA
Pull-up control signal
P-ch
N-ch
Pout
Nout
•
Hysteresis input
Standby control signal
D
R
P-ch
Pull-up control signal
P-ch
N-ch
Pout
Nout
•
•
•
•
Hysteresis input
CMOS output
Hysteresis input
Selectable pull-up resistor
approximately 50 kΩ
IOL = 4 mA
Standby control signal
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
17
CHAPTER 1 OVERVIEW
1.7
MB90820B Series
Table 1.7-1 I/O Circuit Type (2 / 4)
Type
E
Circuit
R
P-ch
Remarks
Pull-up control
P-ch
N-ch
Pout
Nout
•
•
•
•
CMOS output
CMOS input
Selectable pull-up resistor
approximately 50 kΩ
IOL = 4 mA
•
•
•
CMOS output
Hysteresis input
IOL = 4 mA
•
•
•
•
CMOS output
Hysteresis input
CMOS input(selectable for
UART 0 data input pin)
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
Analog input
IOL = 4 mA
CMOS input
Standby control signal
F
P-ch
N-ch
Pout
Nout
Hysteresis input
Standby control signal
G
P-ch
N-ch
Pout
Nout
Hysteresis input
CMOS input
Standby control signal
H
P-ch
N-ch
Pout
Nout
CMOS input
Analog input control
Analog input
18
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.7
MB90820B Series
Table 1.7-1 I/O Circuit Type (3 / 4)
Type
Circuit
Remarks
I
P-ch
Pout
Nout
N-ch
CMOS input
Analog I/O control
•
•
•
•
•
CMOS output
CMOS input
Analog output
Analog input
IOL = 4 mA
•
•
•
•
•
CMOS output
Hysteresis input
CMOS input (selectable for
UART1 data input pin)
IOL = 4 mA
Analog input
•
•
•
•
CMOS output
Hysteresis input
Analog input
IOL= 4 mA
•
•
•
CMOS output
Hysteresis input
IOL= 12 mA
Analog output
Analog input
J
P-ch
N-ch
Pout
Nout
Hysteresis input
CMOS input
Analog input control
Analog input
K
P-ch
N-ch
Pout
Nout
CMOS input
Analog input control
Analog input
L
P-ch
N-ch
Pout
Nout
Hysteresis input
Standby mode control
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
19
CHAPTER 1 OVERVIEW
1.7
MB90820B Series
Table 1.7-1 I/O Circuit Type (4 / 4)
Type
Circuit
Remarks
M
Hysteresis input
N
Hysteresis input
20
FUJITSU MICROELECTRONICS LIMITED
Mask ROM/evaluation product
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
Flash ROM
• CMOS input
• No pull-down resistor
Mask ROM/evaluation product
• Hysteresis input
Flash ROM
• CMOS input
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.8
MB90820B Series
1.8
Notes on Handling Devices
When handling devices, pay special attention to the following items or procedures:
• Preventing latch-up
• Stabilization of supply voltage
• Notes on energization
• Handing unused pins
• Connection of unused pins of A/D converter and D/A converter
• External clock
• Power supply pin (VCC/VSS)
• Turning-on sequence of A/D converter and D/A converter
• Initialization
• Return from standby state
■ Notes on Handling Devices
● Be sure that the maximum rated voltage is not exceeded (latch-up prevention)
CMOS ICs may cause latch-up in the following situations:
•
When a voltage higher than VCC or lower than VSS is applied to input or output pins.
•
When a voltage exceeding the rating is applied between VCC and VSS.
•
When the AVCC power supply is applied before the VCC voltage.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of
the device. Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage exceed the digital powersupply voltage.
● Stabilize the supply voltages
If the power supply voltage varies acutualy even within the operation assurance range of the VCC power
supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized.
As stabilization guidelines, stabilize the power supply voltage so that Vcc ripple fluctuations (peak to peak
value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply
voltage and transient fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power
supply switching.
● Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization
at 50 µs or more.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
21
CHAPTER 1 OVERVIEW
1.8
MB90820B Series
● Handling unused pins
Unused input pins left open may cause abnormal operations, or latch-up leading to permanent damage.
Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
If any output pins are unused, set them to open.
● Connection of unused pins of A/D converter and D/A converter
When the A/D converter and D/A converter are not used, connect the pins as follows: AVcc = Vcc, AVss =
AVR = Vss.
● Notes on external clock
To use an external clock, drive only the X0 pin and leave the X1 pin open (See the illustration below).
Figure 1.8-1 Sample application of external clock
X0
MB90820B series
Open
X1
● Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the
device to avoid abnormal operations including latch-up. However, you must connect the pins to external
power supply and a ground lines to lower the electro-magnetic emission level, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current
rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low
impendace.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS
near this device.
● Turning-on sequence of A/D converter and D/A converter
Make sure to turn on the A/D converter and D/A converter power supply (AVCC, AVSS, AVR) and analog
inputs (AN0 to AN15) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter and D/A converter supply and analog inputs.
In this case, make sure that the voltage of AVR does not exceed AVCC.
22
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 1 OVERVIEW
1.8
MB90820B Series
● Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these
registers turning on the power again.
● Return from standby state
If the power supply voltage goes below the standby RAM holding voltage in the standby state, the device
may fail to return from the standby state. In this case, reset the device via the external reset pin to return to
the normal state.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
23
CHAPTER 1 OVERVIEW
1.8
24
MB90820B Series
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 2
CPU
This chapter describes memory space for the MB90820B
series.
CM44-10147-2E
2.1
CPU
2.2
Memory Space
2.3
Memory Maps
2.4
Addressing
2.5
Memory Location of Multibyte Data
2.6
Registers
2.7
Dedicated Registers
2.8
General-purpose Registers
2.9
Prefix Codes
FUJITSU MICROELECTRONICS LIMITED
25
CHAPTER 2 CPU
2.1
2.1
MB90820B Series
CPU
The F²MC-16LX CPU is a 16-bit CPU designed for use in applications, such as welfare
and mobile equipment, which require high-speed real-time processing. The instruction
set of the F²MC-16LX was designed for controllers so that it can perform various types
of control at high speed and efficiency.
The F²MC-16LX CPU process not only 16-bit data but also 32-bit data using a built-in 32bit accumulator. Memory space, which can be extended up to 16M bytes, can be
accessed in either linear or bank access mode. The instruction set inherits the AT
architecture of F²MC-8L, and has additional instructions supporting high-level
languages. In addition, it has an extended addressing mode, enhanced multiply/divide
instructions and reinforced bit manipulation instructions. The features of the F²MC16LX CPU are shown below:
■ CPU
● Minimum instruction execution time: 42 ns (when the source oscillation is 4 MHz and the PLL clock is
multiplied by 6)
● Maximum memory address space: 16M bytes. Access in linear or bank addressing mode
● Instruction set optimum for controller applications
Many data types (bit, byte, word and long word)
As many as 23 addressing modes
Enhanced high-precision arithmetic operation by a 32-bit accumulator
Enhanced signed multiply/divide instructions and RETI instruction function
● Enhanced interrupt function
Eight programmable priority levels
● Automatic transfer function independent on CPU
Extended intelligent I/O service using up to 16 channels
● Instruction set supporting high-level language (C) and multitasking
System stack pointer, instruction set symmetry and barrel shift instructions
● Increased execution speed: 4-byte instruction queue
Note :
The MB90820B series runs only in single-chip mode so only internal ROM and RAM and internal
peripheral address space can be accessed.
26
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 2 CPU
2.2
MB90820B Series
2.2
Memory Space
All I/O, programs and data are located in the 16-megabyte memory space of the F2MC16LX. A part of the memory space is used for special purposes, such as extended
intelligent I/O service (EI2OS) descriptors, general-purpose registers and vector tables.
■ Memory Space
All I/O, programs, and data are located in the 16-megabyte memory space of the F2MC-16LX CPU. The
CPU is able to access each resource through an address indicated by the 24-bit address bus.
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and the memory map.
Figure 2.2-1 Sample relationship between the F2MC-16LX system and the memory map
FFFFFFH
Vector table area
⎧ FFFC00H
Programs
⎨
Program area
⎩ FF0000H*1
ROM
area
Data
F2MC-16LX
CPU
Internal bus
010000H
ROM area
(FF bank image)
008000H
EI2OS
Peripheral circuits
Interrupts
004000H
*2
⎧001100H
⎪ 000380H
⎪
⎨
⎧ ⎪⎪ 000180H
⎨
⎩ ⎩ 000100H
Peripheral circuits
⎧ 0000F0H
General-purpose
ports
⎧
⎨
⎩
F2MC-16LX device
Data area
General-purpose
register
RAM
area
EI2OS descriptor area
⎨
⎩ 0000C0H
0000B0H
⎧⎪
⎨
⎪
⎩ 000000H
External area*3
peripheral function
control register
Interrupt controller
I/O port and
peripheral function
control register
I/O
area
*1: The size of internal ROM differs for each model.
*2: The size of internal RAM differs for each model.
*3: There is no access in single-chip mode.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
27
CHAPTER 2 CPU
2.2
MB90820B Series
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
• This area is used as a vector table for vector call instructions, interrupt vectors and reset vectors.
• This area is allocated at the highest addresses of the ROM area. The start address of the corresponding
processing routine is set as data in each vector table address.
● Program area (address: up to FFFBFFH)
• ROM is built in as an internal program area.
• The size of internal ROM differs for each model.
■ RAM Area
● Data area (address: from 000100H)
• The static RAM is built in as an internal data area.
• The size of internal RAM differs for each model.
● General-purpose register area (address: 000180H to 00037FH)
• Auxiliary registers used for 8-bit, 16-bit and 32-bit arithmetic operations and transfer are allocated in
this area.
• Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
• When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions.
● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
• This area retains the transfer modes, I/O addresses, transfer count and buffer addresses.
• Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFH)
The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an
interrupt function. These registers set interrupt levels and control the extended intelligent I/O service
(EI2OS).
● Peripheral function control register area (address: 000020H to 0000AFH, 0000C0H to 0000EFH)
These registers control the built-in peripheral functions, input and output data. Instruction using I/O
addressing e.g. MOV A, io, is not supported for registers area 003FE0H to 003FFFH
● I/O port control register area (address: 000000H to 00001FH)
These registers controls I/O ports, input and output data.
28
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 2 CPU
2.3
MB90820B Series
2.3
Memory Maps
This section shows the memory map for each MB90820B series model.
■ Memory Maps
Figure 2.3-1 shows the memory maps for the MB90820B series.
Figure 2.3-1 Memory Maps
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
Address #1 - 1H
010000H
00FFFFH
ROM area *
Address #2 (FF bank image)
Address #2 - 1H
Address #3 + 1H
Address #3
RAM
area
Register
000100H
0000FFH
0000F0H
0000EFH
000000H Peripheral area
: Internal access memory
: Access not allowed
Model
Address #1
Address #2
Address #3
MB90822B
FF0000H
008000H
0010FFH
MB90F822B
FF0000H
008000H
0010FFH
MB90F823B
FE0000H
008000H
0010FFH
MB90V820B
(FE0000H)
008000H
0040FFH
MB90F828B
FE0000H
008000H
0020FFH
*: In single chip mode, the mirror function is supported.
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CHAPTER 2 CPU
2.3
MB90820B Series
Reference:
When the single-chip mode (without ROM mirroring function), see "CHAPTER 22 ROM MIRRORING
FUNCTION SELECTION MODULE".
Note :
The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the
C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the
table on the ROM without stating “far”. For example, if an attempt has been made to access
00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the
FF bank exceeds 32K bytes, the whole area cannot be reflected in the image for the 00 bank. The
ROM data at FF8000H to FFFFFFH looks, therefore, as if it were the image for 008000H to 00FFFFH.
Thus, it is recommended that the ROM data table be stored in the area of FF8000H to FFFFFFH.
30
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CHAPTER 2 CPU
2.4
MB90820B Series
2.4
Addressing
The methods for generating addresses are linear addressing and bank addressing.
In linear addressing, the complete 24-bit address is specified directly by an instruction.
In bank addressing, the upper 8 bits of the address are specified by a bank register for
the required purpose, and the lower 16 bits of the address are specified by the
instruction.
The F2MC-16LX series generally uses bank addressing.
■ Linear Addressing and Bank Addressing
In linear addressing, the 16-megabyte space is accessed as consecutive address spaces. In bank addressing,
the 16-megabyte space is divided into and managed as 256 64-kilobyte banks.
Figure 2.4-1 is an overview of linear addressing and bank addressing memory management.
Figure 2.4-1 Linear addressing and bank addressing memory management
Linear addressing
Bank addressing
FF bank
64 kilobytes
FE bank
FD bank
12 bank
04 bank
03 bank
02 bank
01 bank
00 bank
Specified entirely by an instruction
CM44-10147-2E
Specified by an instruction
Specified by a bank register for the required purpose
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CHAPTER 2 CPU
2.4
2.4.1
MB90820B Series
Address Specification by Linear Addressing
The two types of address specification by linear addressing are specification of a 24-bit
address directly in the operand and specification of the lower 24 bits of a 32-bit generalpurpose register.
■ Linear Addressing by 24-bit Operand Specification
Figure 2.4-2 Example of direct specification of a 24-bit physical address in linear addressing
JMPP 123456H
Old program counter
+ program bank
17
New program counter
+ program bank
12
17452DH
JMPP 123456H
123456H
Next instruction
452D
3456
■ Addressing by Indirect Specification with a 32-bit Register
Figure 2.4-3 Example of indirect specification with a 32-bit general-purpose register
in linear addressing
MOV A,@RL1+7
Old AL
090700H
XXXX
3AH
+7
New AL
003A
RL1
240906F9H
(Upper 8 bits are ignored)
RL1: 32-bit (long-word) general-purpose register
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CM44-10147-2E
CHAPTER 2 CPU
2.4
MB90820B Series
2.4.2
Address Specification by Bank Addressing
In address specification by bank addressing, the 16-megabyte memory space is divided
into 256 64-kilobyte banks. A bank address that corresponds to each space is specified
in the bank register to determine the upper 8 bits of the address. The lower 16 bits of
the address are specified by the instruction.
The five types of bank registers classified by function are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Registers and Access Space
Table 2.4-1 lists the access space and main function of each bank register.
Table 2.4-1 Access space and main function of each bank register
Bank register
name
Access
space
Main function
Initial value after
a reset
Program bank
register (PCB)
Program Instruction codes, vector tables and immediate-value
(PC) space data are stored.
FFH
Data bank
register (DTB)
Read/write data is stored. Internal or external
Data (DT)
peripheral control registers and data registers are
space
accessed.
00H
User stack bank
register (USB)
This area is used for stack accesses such as when
PUSH/POP instructions and interrupt registers are
Stack (SP) saved. The SSB is used when the stack flag in the
space
condition register (CCR: S) is 1. The USB is used
when the stack flag in the condition register (CCR: S)
is 0. *
System stack
bank register
(SSB) *
Additional bank
register (ADB)
Additional Data that overflows from the data (DT) space is
(AD) space stored.
00H
00H
00H
* : The SSB is always used as an interrupt stack.
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CHAPTER 2 CPU
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Figure 2.4-4 shows the relationship between the memory space divisions and each register.
See Section "2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB)", for details.
Figure 2.4-4 Sample bank addressing
FFFFFFH
Program space
FF0000H
Physical address
0FFFFFH
: ADB (Additional Bank Register)
0DH
: USB (User Stack Bank Register)
0BH
: DTB (Data Bank Register)
07H
: SSB (System Stack Bank Register)
Data space
0B0000H
7FFFFFH
0FH
User stack space
0D0000H
0BFFFFH
: PCB (Program Bank Register)
Additional space
0F0000H
0DFFFFH
FFH
System stack space
070000H
000000H
■ Bank Addressing and Default Space
To improve instruction coding efficiency, each instruction has a defined default space for each addressing
method, as shown in Table 2.4-2 . To use a space other than the default space, specify a prefix code for a
bank before the instruction. This enables the bank space that corresponds to the specified prefix code to be
accessed. See Section "2.9 Prefix Codes", for details about prefix codes.
Table 2.4-2 Addressing and default spaces
Default space
Addressing
Program space
PC indirect, program access, branching
Data space
Addressing using @RW0, @RW1, @RW4, and @RW5, @A,
addr16, dir
Stack space
Addressing using PUSHW, POPW, @RW3, and @RW7
Additional space Addressing using @RW2 and @RW6
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CHAPTER 2 CPU
2.5
MB90820B Series
2.5
Memory Location of Multibyte Data
Multibyte data is written to memory sequentially from the lower address. If multibyte
data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits.
If an external signal is input immediately after the low-order data is written, the highorder data may not be written.
■ Storage of Multibyte Data on Memory
Figure 2.5-1 shows the data configuration of multibyte data in memory. The lower 8 bits of the data is
located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3 and so on,
in this sequence.
Figure 2.5-1 Storage of multibyte data in RAM
MSB
01010101B
H
LSB
11001100B
11111111B
00010100B
01010101B
11001100B
11111111B
Address ‘n’
00010100B
L
■ Storage of Multibyte Operand
Figure 2.5-2 shows the configuration of a multibyte operand in memory.
Figure 2.5-2 Configuration of a multibyte operand in memory
JMPP 123456H
H
JMPP 12 34 56H
12H
34H
Address ‘n’
56H
63H
L
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CHAPTER 2 CPU
2.5
MB90820B Series
■ Storage of Multibyte Data in a Stack
Figure 2.5-3 shows the configuration of multibyte data in a stack.
Figure 2.5-3 Configuration of multibyte data in a stack
PUSHW RW1, RW3
H
PUSHW RW1, RW3
(35A4H) (6DF0H)
SP
6DH
F0H
35H
Address ‘n’
A4H
L
RW1: 35A4H
RW3: 6DF0H
*: Stack status after execution of the PUSHW instruction
■ Multibyte Data Access
Accessing is generally performed within a bank. For an instruction that accesses to multibyte data, the
address following FFFFH is 0000H in the same bank.
Figure 2.5-4 shows an example of executing an instruction that accesses multibyte data on a bank
boundary.
Figure 2.5-4 Multibyte data access on a bank boundary
H
01H
……..
80FFFFH
800000H
AL before execution
??
??
AL after execution
23H
01H
23H
L
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CM44-10147-2E
CHAPTER 2 CPU
2.6
MB90820B Series
2.6
Registers
F2MC-16LX registers are classified into internal dedicated CPU registers and built-in
RAM general-purpose registers.
■ Dedicated Registers and General-purpose Registers
Dedicated registers are dedicated hardware inside the CPU with limited use in the CPU architecture.
General-purpose registers exist together with RAM in the CPU address space. Just like dedicated registers,
general-purpose registers can be accessed without addressing. Just like ordinary memory, the user can
specify how the register is used.
Figure 2.6-1 shows the location of the dedicated registers and general-purpose registers in the device.
Figure 2.6-1 Dedicated registers and general-purpose registers
Dedicated register
General-purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
Internal data bus
System stack pointer
System stack bank register
Additional data bank register
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CHAPTER 2 CPU
2.7
2.7
MB90820B Series
Dedicated Registers
The following 11 registers are dedicated registers in the CPU.
• Accumulator (A)
• System stack pointer (SSP)
• Program counter (PC)
• Program bank register (PCB)
• User stack bank register (USB)
• Additional data bank register (ADB)
• User stack pointer (USP)
• Processor status (PS)
• Direct page register (DPR)
• Data bank register (DTB)
• System stack bank register (SSB)
■ Configuration of Dedicated Registers
Figure 2.7-1 shows the configuration of dedicated registers; Table 2.7-1 lists the initial values of the
dedicated registers.
Figure 2.7-1 Configuration of dedicated registers
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register (PBR)
DTB
Data Bank Register (DTB)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8 bits
16 bits
32 bits
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CHAPTER 2 CPU
2.7
MB90820B Series
Table 2.7-1 Initial values of the dedicated registers
Dedicated register
Initial value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
bit 15
Program counter (PC)
13 12
0
PS
ILM
RP
CCR
Default value →
000
00000
-01xxxxx
Value in reset vector (Values of FFFFDCH, FFFFDDH)
Direct page register (DPR)
Program bank register (PCB)
8 7
01H
Value in reset vector (Value of FFFFDEH)
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
- : Not used
x: Undefined
Note :
The above initial values are the initial values for the device.
(emulator, etc.) values.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
They are different from the ICE
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CHAPTER 2 CPU
2.7
2.7.1
MB90820B Series
Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL).
The accumulator is used to temporarily store the results of an arithmetic operation and
data.The A register can be used as a 32-bit, 16-bit or 8-bit register. Various arithmetic
operations can be performed between memory and other registers or between the AH
register and the AL register. The A register has a data retention function that
automatically transfers pre-transfer data from the AL register to the AH register when
data of word length or less is transferred to the AL register. (Data is not retained with
some instructions.)
■ Accumulator (A)
● Data transfer to the accumulator
The accumulator can process 32-bit (long word), 16-bit (word) and 8-bit (byte) data. The 4-bit data transfer
instruction (MOVN) is an exception. The explanation of 8-bit data also applies to 4-bit data.
• For 32-bit data processing, the AH register and AL register are combined.
• For 16-bit data and 8-bit data, only the AL register is used.
• When data of byte length or less is transferred to the AL register, data becomes 16 bits long by sign
extension or zero extension, and is stored in the AL register. Data in the AL register can be handled as
word-length or byte-length data.
Figure 2.7-2 shows data transfer to the accumulator. Figure 2.7-3 to Figure 2.7-6 show specific transfer
examples.
Figure 2.7-2 Data transfer to the accumulator
32-bit
32-bit data transfer
Data transfer Data transfer
16-bit data transfer
Data save
Data transfer
8-bit data transfer
Data save
00H or FFH (*1)
Data transfer
(Zero extension or sign extension)
*1 Becomes 000H or FFFH for a 4-bit transfer instruction.
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CHAPTER 2 CPU
2.7
MB90820B Series
Figure 2.7-3 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension)
MOV A, 3000H
(An instruction that zero-extends the contents at address 3000H and
stores the result in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
0088H
AL
Figure 2.7-4 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension)
MOVX A, 3000H
(An instruction that stores the contents at address 3000H
in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
FF88H
AL
Figure 2.7-5 Example of 32-bit data transfer to the accumulator (A) (register indirect)
MOVL A,@RW1+6
(Instruction that perform a long-word-length read using the result
of the RW1 contents + an 8-bit offset as the address and stores
the read value in the A register)
Memory space
MSB
A before execution
XXXXH
XXXXH
DTB
A after execution
CM44-10147-2E
8F74H
AH
A6H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
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CHAPTER 2 CPU
2.7
MB90820B Series
Figure 2.7-6 Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect)
MOVW A,@RW1+6
(Instruction that performs a word-length read using the result of
the RW1 contents + an 8-bit offset as the address and stores the
read value in the A register)
Memory space
MSB
A before execution
XXXXH
1234H
DTB
A after execution
1234H
AH
A6H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
● Accumulator byte-processing arithmetic operation
When a byte-processing arithmetic operation instruction is executed for the AL register, the upper 8 bits of
the AL register before the arithmetic operation is executed are ignored. The upper 8 bits of the arithmetic
operation results are all zeros.
● Initial value of the accumulator
The initial value after a reset is undefined.
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CHAPTER 2 CPU
2.7
MB90820B Series
2.7.2
Stack Pointers (USP, SSP)
There are two types of stack pointers: a user stack pointer (USP) and a system stack
pointer (SSP). Each stack pointer is a register that indicates the memory address of the
location of the destination for saved data or a return address when PUSH instructions,
POP instructions and subroutines are executed. The upper 8 bits of the stack address
(24 bits) are specified by the user stack bank register (USB) or system stack bank
register (SSB).
When the S flag of the condition code register (CCR) is "0", the USP and USB registers
are valid. When the S flag is "1", the SSP and SSB registers are valid.
■ Stack Selection
The F2MC-16LX uses two types of stack: a system stack and a user stack.
The stack address is determined, as shown in Table 2.7-2 , by the S flag in the processor status register (PS:
CCR).
Table 2.7-2 Stack address specification
Stack address
S flag
Upper 8 bits
Lower 16 bits
0
User stack bank register (USB)
1
System stack bank register (SSB) System stack pointer (SSP)
User stack pointer (USP)
: Initial value
Because the S flag is initialized to "1" by a reset, the system stack is used as the default.
Ordinarily, the system stack is used for interrupt routine stack operations, and the user stack is used for all
other types of stack operation. When separation of the stack space is not particularly necessary, only the
system stack should be used.
Note :
Since the S flag is set to "1" when an interrupt is accepted, the system stack is always used for
interrupts.
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CHAPTER 2 CPU
2.7
MB90820B Series
Figure 2.7-7 shows an example of stack operation instruction and stack pointer.
Figure 2.7-7 Stack operation instruction and stack pointer
PUSHW A with the S flag set to "0"
Before execution ⇒
AL
A624H
S flag
After execution ⇒
AL
MSB
0
A624H
S flag
0
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F326H
SSB 56H
SSP
1234H
C6F326H
LSB
XXH
XXH
⇐ User stack is used
because S flag is "0"
C6F326H
A6H
24H
PUSHW A with the S flag set to "1"
MSB
Before execution ⇒
AL
A624H
S flag
After execution ⇒
AL
1
A624H
S flag
1
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F328H
SSB 56H
SSP
1232H
LSB
561232H
XXH
XXH
561232H
A6H
24H
⇐ User stack is used
because S flag is "1"
References:
• To set the stack address for the stack pointer, generally use an even-numbered address. If an
odd-numbered address is used, a word access is split into two parts, lowering efficiency.
• The initial values of the USP register and SSP register after a reset are undefined.
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CHAPTER 2 CPU
2.7
MB90820B Series
■ System Stack Pointer (SSP)
To use the system stack pointer (SSP), set the S flag in the condition code register (CCR) of the processor
status (PS) to "1". The upper 8 bits of the address that will be used for the stack operation are indicated by
the system stack bank register (SSB).
■ User Stack Pointer (USP)
To use the user stack pointer (USP), set the S flag in the condition code register (CCR) of the processor
status (PS) to "0". The upper 8 bits of the address that will be used for the stack operation are indicated by
the user stack bank register (USB).
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CHAPTER 2 CPU
2.7
2.7.3
MB90820B Series
Processor Status (PS)
The processor status (PS) consists of CPU control bits and bits that indicate the CPU
status. The PS register consists of the following three registers:
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor Status (PS) Configuration
The processor status (PS) consists of CPU control bits and bits that indicate the CPU status.
Figure 2.7-8 shows the configuration of the processor status (PS).
Figure 2.7-8 Processor status (PS) configuration
bit 15
PS
Default value ⇒
13 12
ILM
000
8 7
0
RP
00000
CCR
-01xxxxx
7
6
5
4
3
2
1
0
−
Default value ⇒ −
I
0
S
1
T
x
N
x
Z
x
V
x
C : CCR
x
B4 B3 B2 B1 B0 : RP
Default value ⇒ 0 0 0 0 0
Default value ⇒
ILM2
0
ILM1
0
ILM0
0
: ILM
− : Not used
● Interrupt level mask register (ILM)
This register indicates the level of the interrupt currently accepted by the CPU. The value is compared with
the value of the interrupt level setting bits (ICR: IL0 to IL2) in the interrupt control register set for the
peripheral resource interrupt request.
● Register bank pointer (RP)
This pointer points to the first address of the memory block (register bank) used as the general-purpose
register in the RAM area.
There are 32 banks for general-purpose registers. Values 0 to 31 are set in the RP to specify a bank.
● Condition code register (CCR)
This register consists of flags that are set to "1" or reset to "0" by instruction execution results and by
interrupt outputs.
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CM44-10147-2E
CHAPTER 2 CPU
2.7
MB90820B Series
2.7.4
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register that consists of the bits that
indicate the results of an arithmetic operation and the contents of transfer data and bits
that control interrupt request acceptance.
■ Condition Code Register (CCR) Configuration
Refer to the "F2MC-16LX Family Programming Manual" for details about the status of the condition code
register (CCR) during instruction execution. Figure 2.7-9 shows the configuration of the CCR register.
Figure 2.7-9 Condition code register (CCR) configuration
bit
Default value ⇒
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
–
0
1
x
x
x
x
x
Interrupt enable flag
Stack flag
Sticky flag
Negative flag
Zero flag
Overflow flag
Carry flag
: CCR
- : Not used
x : Undefined
● Interrupt enable flag (I)
In response to all interrupt requests other than software interrupts, when the I flag is "1", interrupt requests
are enabled. When the I flag is "0", interrupt requests are disabled. Cleared to "0" by a reset.
● Stack flag (S)
This flag indicates the pointer used for a stack operation.
When the S flag is "0", the user stack pointer (USP) is valid. When the S flag is "1", the system stack
pointer (SSP) is valid. Set to "1" when an interrupt is accepted or when a reset occurs.
● Sticky bit flag (T)
Set to "1" when the data shifted out by the carry contains at least one "1" during execution of a logical right
shift instruction or arithmetic right shift instruction. Otherwise, set to "0". Also set to "0" when the shift
amount is zero.
● Negative flag (N)
Set to "1" when the MSB is "1" as the result of an arithmetic calculation. Cleared to "0" when the MSB is
"0".
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CHAPTER 2 CPU
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MB90820B Series
● Zero flag (Z)
Set to "1" when the result of an arithmetic calculation is all zeros. Otherwise, set to "0".
● Overflow flag (V)
Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Cleared to "0" if no
overflow occurs.
● Carry flag (C)
Set to "1" when there is an overflow from the MSB or an underflow from the LSB because of an arithmetic
calculation. Cleared to "0" when there is no overflow or underflow because of an arithmetic calculation.
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CHAPTER 2 CPU
2.7
MB90820B Series
2.7.5
Register Bank Pointer (PS: RP)
The register bank pointer (RP) is a register that indicates the first address of the
general-purpose register bank currently being used. The RP is used for real address
conversion when general-purpose register addressing is used.
■ Register Bank Pointer (RP)
Figure 2.7-10 shows the configuration of the register bank pointer (RP) register.
Figure 2.7-10 Configuration of the register bank pointer (RP)
B4 B3 B2 B1 B0 : RP
Default value ⇒ 0 0 0 0 0
■ General-purpose Register Area and Register Bank Pointer (RP)
The register bank pointer points to the relationship between the general-purpose register of the F2MC16LX and the address in internal RAM where the general-purpose register exists. Figure 2.7-11 shows the
conversion rules used for the relationship between the contents of the RP and the real address.
Figure 2.7-11 Conversion rules for physical address of general-purpose register area
Conversion formula [000180H + (RP) X 10H]
When RP = 10H
000370H
000280H
000180H
Register bank 31
Register bank 16
Register bank 0
• Since the RP takes a value from 00H to 1FH, the first address of the register bank can be set in the range
from 000180H to 00037H.
• Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to
the RP, in actuality only the lower 5 bits of the data are used.
• The initial value of the RP register after a reset is 00H.
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CHAPTER 2 CPU
2.7
2.7.6
MB90820B Series
Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the
interrupt currently accepted by the CPU.
■ Interrupt Level Mask Register (ILM)
Figure 2.7-12 shows the configuration of the interrupt level mask register (ILM). See "CHAPTER 7
INTERRUPT", for details about interrupts.
Figure 2.7-12 Configuration of the interrupt level mask register (ILM)
ILM2
0
Default value ⇒
ILM1
0
ILM0
0
: ILM
The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by the CPU.
The level is compared with the value of the IL0 to IL2 bits of the interrupt control register (ICR00 to
ICR15) set according to the interrupt request from the peripheral function. If the interrupt enable flag has
been set to enable (CCR: I = 1), the CPU processes the instruction only when the value (interrupt level) of
the interrupt request is smaller than the value indicated by these bits.
• When an interrupt is accepted, the interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, interrupts with the same or lower level are not accepted.
• The interrupt level is set to the highest level, which is the interrupts disabled status, because the interrupt
level mask register (ILM) is initialized to all 0’s by a reset.
• Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to
the interrupt level mask register (ILM), only the lower 3 bits of the data are enabled.
Table 2.7-3 Interrupt level mask register (ILM) and interrupt level priority
50
ILM2
ILM1
ILM0
Interrupt level
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Interrupt level priority
Highest (interrupts disabled)
FUJITSU MICROELECTRONICS LIMITED
Lowest
CM44-10147-2E
CHAPTER 2 CPU
2.7
MB90820B Series
2.7.7
Program Counter (PC)
The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the
memory address of the next instruction code to be executed by the CPU.
■ Program Counter (PC)
The program bank register (PCB) specifies the upper 8 bits of the address where the next instruction code
to be executed by the CPU is stored. The PC specifies the lower 16 bits. Before being used, the actual
address is combined to become 24 bits, as shown in Figure 2.7-13 .
The contents of the PC are updated by conditional branch instructions, subroutine call instructions,
interrupts and resets.
The PC can be used as a bus pointer for reading operands.
Figure 2.7-13 Program counter (PC)
Upper 8 bits
Upper 16 bits
PCB
PC ABCDH
FEH
FEABCDH
Next instruction
to be executed
Note :
The PC and PCB cannot be rewritten directly by a program (such as by MOV PC and #FF).
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CHAPTER 2 CPU
2.7
2.7.8
MB90820B Series
Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to
addr15) of the operand address when a short direct addressing instruction is executed.
■ Direct Page Register (DPR)
As shown in Figure 2.7-14 , the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a
short direct addressing instruction is executed. The DPR is 8-bits length. The DPR is initialized to 01H by
a reset. The DPR can be read and written using an instruction.
Figure 2.7-14 Physical address generation by the direct page register (DPR)
ββββββββ
MSB
24-bit physical address
Direct address in instruction
γγγγγγγγ
⎧
⎪
⎪
⎨
⎪
⎪
⎩
αααααααα
⎧
⎪
⎪
⎨
⎪
⎪
⎩
DDR register
⎧
⎪
⎪
⎨
⎪
⎪
⎩
DTB register
LSB
ααααααααββββββββγγγγγγγγ
Figure 2.7-15 shows an example of direct page register (DPR) setting and data access.
Figure 2.7-15 Example of direct page register (DPR) setting and data access
Instruction execution results
Memory space
MOV S:56H, #5AH
Upper
8 bits
DTB register
12H
123458H
123456H
DPR register
34H
5AH
123454H
MSB
52
Lower
8 bits
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LSB
CM44-10147-2E
CHAPTER 2 CPU
2.7
MB90820B Series
2.7.9
Bank Registers (PCB, DTB, USB, SSB, ADB)
Bank registers specify the highest 8-bit address by bank addressing. The five bank
registers are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
The PCB, DTB, USB, SSB and ADB registers indicate the individual memory banks
where the program space, data space, user stack space, system stack space and
additional space are located.
■ Bank Registers (PCB, DTB, USB, SSB, ADB)
● Program bank register (PCB)
The PCB is a bank register that specifies the program (PC) space.
The PCB is rewritten when a software interrupt instruction is executed, when the JMPP, CALLP, RETP
and RETI instructions that branch anywhere within the 16-megabyte space are executed, or when a
hardware interrupt or exception occurs.
● Data bank register (DTB)
The DTB is a bank register that specifies the data (DT) space.
● User stack bank register (USB), system stack bank register (SSB)
The USB and SSB are bank registers that specify the stack (SP) space. Whether the USB or the SSB is
used depends on the S flag value in the processor status (PS: CCR). See Section "2.7.2 Stack Pointers
(USP, SSP)", for details.
● Additional bank register (ADB)
The ADB is a bank register that specifies the additional (AD) space.
● Bank setting and data access
All bank registers are byte length. The PCB is initialized to FFH by a reset. The other bank registers are
initialized to 00H by a reset. The PCB can be read, but cannot be written to.
The other bank registers can be read and written to.
Note :
The MB90820B series supports up to the memory space contained in the device.
See Section "2.4.2 Address Specification by Bank Addressing", for the operation of each register.
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CHAPTER 2 CPU
2.8
2.8
MB90820B Series
General-purpose Registers
The general-purpose registers are a memory block allocated in RAM at 000180H to
00037FH as banks, each of which consists of eight 16-bit segments.
The general-purpose registers can be used as general-purpose 8-bit registers (byte
registers R0 to R7), 16-bit registers (word registers RW0 to RW7) or 32-bit registers
(long-word registers RL0 to RL3).
General-purpose registers can access RAM with a short instruction at high speed.
Since general-purpose registers are blocked into register banks, protection of register
contents and division into function units can readily be performed. When a generalpurpose register is used as a long-word register, it can be used as a linear pointer that
directly accesses the entire space.
■ Configuration of a General-purpose Register
All general-purpose registers exist in RAM at 000180H to 00037FH and are configured as 32 banks. The
register bank pointer (RP) specifies the bank that is to be used for a general-purpose register. The RP
points to the bank currently being used.
The RP determines the first address of each bank with the following formula:
Address of first general-purpose register = 000180H + RP x 10H
Figure 2.8-1 shows the location and configuration of the general-purpose register banks in the memory
space.
Figure 2.8-1 Location and configuration of the general-purpose register banks in the memory space
Built-in RAM
Register bank 31
Byte address
Byte address
Register bank 30
Register bank 21
Register bank 20
Register bank 19
Register bank 2
Register bank 1
Register bank 0
54
Conversion formula [000180H + RP x 10H]
R0 to R7:
RW0 to RW7:
RL0 to RL3:
MSB:
LSB:
Byte registers
Word registers
Long-word registers
Most Significant Bit
Least Significant Bit
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CM44-10147-2E
CHAPTER 2 CPU
2.8
MB90820B Series
Note :
The register bank pointer (RP) is initialized to 00H after a reset.
■ Register Bank
A register bank can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to
RW7, long-word registers RL0 to RL3) for various arithmetic operations and pointers. A long-word
register can be used as a linear pointer that directly accesses the entire memory space.
The contents of the register bank, like ordinary RAM, are not initialized by a reset. The status before a
reset is retained. At power-on reset, however, the contents are undefined.
Table 2.8-1 lists the typical functions of general-purpose registers.
Table 2.8-1 Typical functions of general-purpose registers
Register name
R0 to R7
RW0 to RW7
Function
Used as an operand in various instructions
Note :
R0 is also used as a barrel shift counter and an instruction
normalization counter
Used as a pointer
Used as an operand in various instructions
Note :
RW0 is used also as a string instruction counter
RL0 to RL3
CM44-10147-2E
Used as a long pointer
Used as an operand in various instructions
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CHAPTER 2 CPU
2.9
2.9
MB90820B Series
Prefix Codes
Prefix codes are placed before an instruction to partially change the operation of the
instruction. The three types of prefix codes are as follows:
• Bank select prefix (PCB, DTB, ADB, SPB)
• Common register bank prefix (CMR)
• Flag change suppression prefix (NCC)
■ Prefix Codes
● Bank select prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space to be accessed by the
instruction regardless of the addressing method.
● Common register bank prefix (CMR)
The common register bank prefix is placed before an instruction that accesses a register bank to change the
register accessed by the instruction to the common bank (register bank selected when RP =00H) at 000180H
to 00018FH regardless of the current register bank pointer (RP) value.
● Flag change suppression prefix (NCC)
The flag change suppression prefix code is placed before an instruction to suppress a flag change
accompanying the execution of the instruction.
56
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CM44-10147-2E
CHAPTER 2 CPU
2.9
MB90820B Series
2.9.1
Bank Select Prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space
accessed by the instruction regardless of the addressing method.
■ Bank Select Prefixes (PCB, DTB, ADB, SPB)
The memory space used for data access is defined for each addressing method. If a bank select prefix is
placed before an instruction, the memory space accessed by the instruction can be selected regardless of the
addressing method. Table 2.9-1 lists the bank select prefix codes and selected memory spaces.
Table 2.9-1 Bank select prefix codes and selected memory spaces
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the value of the S flag in the condition code register (CCR) is
0, the user stack space is used, when the S flag is 1, the system
stack space is used.
If a bank select prefix is used, some instructions perform an unexpected operation.
Table 2.9-2 lists the instructions that are not affected by bank select prefix codes. Table 2.9-3 lists
instructions that require caution when they are used.
Table 2.9-2 Instructions not affected by bank select prefixes
Instruction
type
Instruction
Effect of bank select prefix
MOVS MOVSW
SCEQ SCWEQ
FILS
FILSW
The bank register specified by the
operand is used whether or not a prefix is
used.
Stack
operation
PUSHW POPW
When the S flag is 0, the user stack bank
(USB) is used whether or not there is a
prefix. When the S flag is 1, the system
stack bank (SSB) is used regardless of
whether a prefix is used.
I/O access
instruction
MOV
MOVW
MOV
MOV
MOVB
SETB
BBC
WBTC
Interrupt
return
instruction
RETI
String
instruction
CM44-10147-2E
A
A, io
io, A
io, #imm8
A, io : bp
io : bp
io : bp, rel
io, bp
MOVX A, io
MOVW
MOVW
MOVB
CLRB
BBS
WBTS
io, A
The I/O space (000000H to 0000FFH) is
io, #imm16
accessed whether or not there is a
io : bp, A
prefix.
io : bp
io : bp, rel
io : bp
The system stack bank (SSB) is used
whether or not a prefix is used.
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CHAPTER 2 CPU
2.9
MB90820B Series
Table 2.9-3 Instructions whose use requires caution when bank select prefixes are used
Instruction type
58
Instruction
Explanation
Flag change instruction
AND
OR
CCR, #imm8
CCR, #imm8
The effect of the prefix extends to the next
instruction.
ILM setting instruction
MOV
ILM, #imm8
The effect of the prefix extends to the next
instruction.
PS return instruction
POPW PS
Do not place a bank select prefix before the
PS return instruction.
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CM44-10147-2E
CHAPTER 2 CPU
2.9
MB90820B Series
2.9.2
Common Register Bank Prefix (CMR)
The common register bank prefix (CMR) is placed before an instruction that accesses a
register bank to change the register accessed by the instruction to the common bank
(register bank selected when RP = 0) at 000180H to 00018FH regardless of the current
register bank pointer (RP) value.
■ Common Register Bank Prefix (CMR)
To facilitate data exchange between multiple tasks, a relatively simple means of accessing a fixed register
bank regardless of the current register bank pointer (RP) value is necessary. This is the reason that the
F2MC-16LX provides a common register bank for tasks, which is called the common bank. The common
bank is located at address 000180H to 00018FH.
If the common register bank prefix (CMR) is placed before an instruction that accesses a register bank,
registers accessed by the instruction can be changed to the common bank (register bank selected when RP =
0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value.
Note that caution is required when this prefix is used with the instructions listed in Table 2.9-4 .
Table 2.9-4 Instructions whose use requires caution when the common register bank
prefix (CMR) is used
Instruction
type
Instruction
String
instruction
MOVS
SCEQ
FILS
Flag change
instruction
AND
PS return
instruction
POPW PS
The effect of the prefix extends to the next
instruction.
ILM setting
instruction
MOV
The effect of the prefix extends to the next
instruction.
CM44-10147-2E
MOVSW
SCWEQ
FILSW
Explanation
CCR, #imm8
ILM, #imm8
OR CCR, #imm8
Do not place the CMR prefix before the
string instruction.
The effect of the prefix extends to the next
instruction.
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CHAPTER 2 CPU
2.9
2.9.3
MB90820B Series
Flag Change Suppression Prefix (NCC)
The flag change suppression prefix (NCC) code is placed before an instruction to
suppress a flag change accompanying the execution of the instruction.
■ Flag Change Suppression Prefix (NCC)
The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes. If a flag change
suppression prefix code is placed before an instruction, a flag change accompanying the execution of the
instruction is suppressed. Changes of the T, N, Z, V and C flags are suppressed.
Note that caution is required when this prefix is used with the instructions listed in Table 2.9-5 .
Table 2.9-5 Instructions whose use requires caution when the flag change suppression
prefix (NCC) is used
Instruction
type
Instruction
MOVS MOVSW
SCEQ SCWEQ
FILS
FILSW
Do not place the NCC prefix before the
string instruction.
AND CCR, #imm8 OR CCR, #imm8
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
The effect of prefix extends to the next
instruction.
PS return
instruction
POPW PS
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
The effect of prefix extends to the next
instruction.
ILM setting
instruction
MOV
The effect of prefix extends to the next
instruction.
String
instruction
Flag change
instruction
Interrupt
INT
instruction
INT
Interrupt return
RETI
instruction
Context switch
JCTX
instruction
60
Explanation
ILM, #imm8
#vct8
adder16
@A
INT9
INTP
addr24
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 2 CPU
2.9
MB90820B Series
2.9.4
Restrictions on Prefix Codes
The following three restrictions are imposed on the use of prefix codes:
• Interrupt/hold requests are not accepted during the execution of prefix codes and
interrupt/hold suppression instructions.
• If a prefix code is placed before an interrupt/hold instruction, the effect of the prefix
code is delayed.
• If consecutively placed prefix codes conflict, the last prefix code is valid.
■ Prefix Codes and Interrupt/hold Suppression Instructions
Table 2.9-6 lists the interrupt/hold suppression instructions and prefix codes that have restrictions.
Table 2.9-6 Prefix codes and interrupt suppression instructions sub sleep mode
Prefix codes
Interrupt/hold suppression instructions (instructions that
delay the effect of prefix codes)
PCB
DTB
ADB
SPB
CMR
NCC
Instructions that do not
accept interrupt and hold
requests
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Interrupt/hold suppression
As shown in Figure 2.9-1 , an interrupt or hold request generated during the execution of prefix codes and
interrupt/hold instructions is not accepted. The interrupt/hold is not processed until the first instruction that
is not governed by a prefix code or that is not an interrupt/hold suppression instruction is executed.
Figure 2.9-1 Interrupt/hold suppression
Interrupt/hold suppression instruction
…………
↑
Interrupt request generated
(a) Ordinary instruction
……
(a)
↑
Interrupt accepted
● Delay of the effect of prefix codes
As shown in Figure 2.9-2 , if a prefix code is placed before an interrupt/hold suppression instruction, the
prefix code takes effect with the first instruction executed after the interrupt/hold suppression instruction.
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CHAPTER 2 CPU
2.9
MB90820B Series
Figure 2.9-2 Interrupt/hold suppression instructions and prefix codes
Interrupt suppression instructions
MOV A, FFH
NCC
…
MOV ILM, #imm8
CCR: XXX10XXB
ADD A, 01H
CCR: XXX10XXB
CCR is not changed due to NCC prefix
■ Consecutive Prefix Codes
As shown in Figure 2.9-3 , when consecutive conflicting prefix codes (PCB, ADB, DTB and SPB) are
specified, the last prefix code is valid.
Figure 2.9-3 Consecutive prefix codes
Prefix codes
……
ADB
DTB
PCB
ADD A, 01H
……
↑ The PCB prefix code is valid
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CM44-10147-2E
CHAPTER 3
RESET
This chapter describes the function and operation of the
reset for the MB90820B series microcontrollers.
CM44-10147-2E
3.1
Reset
3.2
Reset Causes and Oscillation Stabilization Wait Intervals
3.3
External Reset Pin
3.4
Reset Operation
3.5
Reset Cause Bits
3.6
Status of Pins in a Reset
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CHAPTER 3 RESET
3.1
3.1
MB90820B Series
Reset
If a reset cause is generated, the CPU immediately stops the current execution process
and waits for the reset to be cleared. When the reset is cleared, the CPU begins
processing at the address indicated by the reset vector.
There are five causes of a reset:
• Power-on reset
• Watchdog timer overflow
• External reset request via the RST pin
• Software reset request
• Clock supervisor reset request (MB90F828B only)
■ Reset Causes
Table 3.1-1 on page 64 lists the reset causes.
Table 3.1-1 Reset causes
Type of reset
Cause
Machine clock
Watchdog
timer
Oscillation
stabilization
wait
External pin
L level input to RST pin
Previous state
retained
Previous state
retained
No
Software
“0” is written to the internal
reset signal generation bit
(RST) bit of the low-power
consumption mode control
register (LPMCR)
Previous state
retained
Previous state
retained
No
Watchdog timer
Watchdog timer overflow
MCLK
Stop count
Yes
Power-on
When the power is turned on
MCLK
Stop count
Yes
Clock
Supervisor reset*
Main clock failure detected
Internal CR
oscillator clock
Stop
No
MCLK: Main clock frequency (oscillation clock frequency divided by 2)
*:MB90F828B only
64
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CM44-10147-2E
CHAPTER 3 RESET
3.1
MB90820B Series
● External reset
An external reset is generated by the "L" level input to an external reset pin (RST pin). The minimum
required period of the "L" level input to the RST pin is 16 machine cycles (16/φ). The oscillation
stabilization wait interval is not required for external resets.
Reference:
For external reset requests via the RST pin, if the reset cause is generated during a write operation
(during the execution of a transfer instruction such as MOV), the CPU waits for the reset to be
cleared after the instruction is completed. The normal write operation is therefore completed even
though a reset is input concurrently.
Note, however, that waiting for the reset to be cleared may start before the transfer of the contents
for a counter specified by a string-processing instruction is completed.
● Software reset
A software reset is an internal reset of three machine cycles (3/φ) generated by writing 0 to the RST bit of
the low-power consumption mode control register (LPMCR). The oscillation stabilization wait interval is
not required for software resets.
● Watchdog reset
A watchdog reset is generated by a watchdog timer overflow that occurs when 0 is not written to the
watchdog control bit (WTE) bit of the watchdog timer control register (WDTC) within a given time after
the watchdog timer is activated. The oscillation stabilization wait interval can be set by the clock selection
register (CKSCR).
● Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait interval is
fixed at 216 oscillation clock cycles (216/HCLK). After the oscillation stabilization wait interval has
elapsed, the reset is executed.
See Section "4.1 Clock", for details.
● Clock supervisor reset
A reset is generated upon detecting a main clock failure.
Clock supervisor reset does not wait for elapsing of the oscillation stabilization wait time.
Reference:
• Definition of clocks
HCLK: Oscillation clock frequency (clock supplied from oscillation pin)
MCLK: Main clock frequency (clock of oscillation clock divided by 2)
φ: Machine clock (CPU operating clock) frequency
1/φ: Machine cycle (CPU operating clock cycle)
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CHAPTER 3 RESET
3.2
3.2
MB90820B Series
Reset Causes and Oscillation Stabilization Wait Intervals
The F2MC-16LX has five reset causes. The oscillation stabilization wait interval for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Intervals
Table 3.2-1 summarizes reset causes and oscillation stabilization wait intervals.
Table 3.2-1 Reset causes and oscillation stabilization wait intervals
Oscillation stabilization wait interval
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Reset cause
Power-on reset
216/HCLK (approximately 16.39 ms)
Watchdog timer
216/HCLK (approximately 16.39 ms)
External reset via the RST pin
None. (However the WS1 & WS0 bits are initialized to “11”.)
Software reset
None. (However the WS1 & WS0 bits are initialized to “11”.)
Clock supervisor reset*
None. (However the WS1 & WS0 bits are initialized to “11”.)
HCLK:Oscillation clock frequency
*: MB90F828B only
Figure 3.2-1 shows the oscillation stabilization wait interval of the product at power-on reset.
Figure 3.2-1 Oscillation stabilization wait interval at power-on reset
Vcc
2 15 /HCLK
2 15 /HCLK
CLK
CPU operation
Regulator stabilization
wait interval
Oscillation stabilization
wait interval
HCLK: oscillation clock
Note :
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to
several dozen milliseconds after the start of oscillation until they stabilize at their natural frequency.
Be sure to set a proper oscillation stabilization wait interval for the specific oscillator used.
See Section "3.2 Oscillation Stabilization Wait Interval", for detail about oscillation stabilization wait
interval.
66
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CM44-10147-2E
CHAPTER 3 RESET
3.2
MB90820B Series
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other externally activated resets during stop mode is
performed after the oscillation stabilization wait interval has elapsed. This time interval is generated by the
time-base timer. If the external reset input has not been cleared after the interval, the reset operation is
performed after the external reset is cleared.
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CHAPTER 3 RESET
3.3
3.3
MB90820B Series
External Reset Pin
The external reset pin (RST pin) is a dedicated pin for inputting, with an L level signal, a
reset and generating an internal reset by the L level input.
For MB90820B series microcontrollers, resets are generated in synchronization with the
CPU operating clock. Asynchronous resets are generated only for the external
terminals.
■ Block Diagram of the External Reset Pin
Figure 3.3-1shows a block diagram of the external reset pin.
Figure 3.3-1 Block diagram of external reset
R
RST
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplier circuit with a frequency of HCLK divided by 2)
Synchronization
circuit
HCLK: Oscillation clock frequency
Internal reset signal
Input buffer
Note :
Inputs to the RST pin are accepted during cycles in which memory is not affected to prevent memory
from being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external clock
requires clock input together with reset input.
68
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CM44-10147-2E
CHAPTER 3 RESET
3.4
MB90820B Series
3.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vector are read are selected according to the setting of the mode pins, and the mode
setting data is fetched. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends.
For power-on or recovery from stop mode by a reset, the mode is fetched after the
oscillation stabilization wait time has elapsed.
■ Overview of Reset Operation
Figure 3.4-1shows the reset operation flow.
Figure 3.4-1 Reset operation flow
Power-on reset
Stop mode reset
Watchdog timer reset
External reset
Software reset
Clock supervisor reset*
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
Normal operation
(Run state)
CPU executes an instruction,
fetching instruction from
the address indicates by the
reset vector
*: MB90F828B only
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See Section "8.1 Mode Setting", for
details about mode pins.
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CHAPTER 3 RESET
3.4
MB90820B Series
■ Mode Data Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data stored in the hardware
memory to the appropriate registers in the CPU core. The reset vector and mode data are allocated to the
four bytes from FFFFDCH to FFFFDFH. The CPU outputs these addresses to the bus immediately after the
reset is cleared and fetches the reset vector and mode data. Using mode fetching, the CPU can begin
processing at the address indicated by the reset vector.
Figure 3.4-2 shows the transfer of the reset vector and mode data.
Figure 3.4-2 Transfer of reset vector and mode data
F2MC-16LX CPU
Memory space
FFFFDFH
Mode
register
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDDH
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
Micro-ROM
Reset sequence
PCB
PC
● Mode data (address: FFFFDFH)
Only the reset operation changes the contents of the mode register. The mode register setting is valid after
a reset operation. See Section "8.1 Mode Setting", for details about mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector. Execution starts at
the address contained in the reset vector.
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CM44-10147-2E
CHAPTER 3 RESET
3.5
MB90820B Series
3.5
Reset Cause Bits
A reset cause can be identified by reading the flag in the watchdog timer control
register (WDTC).
■ Reset Cause Bits
As shown in Figure 3.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If it is necessary to identify the cause of
a reset after the reset has been cleared, the value read from the WDTC should be processed by the software
and a branch should be made to the appropriate program.
Figure 3.5-1 Block diagram of reset cause bits
Pin
RST
RST = L
Without periodic clear
Power-on
RST bit set
Power-on
detection circuit
Clock
supervisor
circuit*
External reset
request detection
circuit
Watchdog timer
reset detection circuit
LPMCR: RST bit
write detection circuit
Watchdog timer
control register
(WDTC)
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
WDTC register
Delay
circuit
WDTC register read
F2MC-16LX internal bus
S : Set
R : Reset
Q : Output
F/F : Flip-flop
CM44-10147-2E
*: MB90F828B only
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CHAPTER 3 RESET
3.5
MB90820B Series
■ Correspondence Between Reset Cause Bits and Reset Causes
Figure 3.5-2 shows the configuration of the reset cause flag bits of the watchdog timer control register
(WDTC). Table 3.5-1 on page 72 shows the correspondence between the reset cause flag bits and reset
causes.
Figure 3.5-2 Configuration of reset cause flag bits (watchdog timer control register)
Watchdog timer control register (WDTC)
bit
7
Address : 0000A8H
PONR
(R)
Read/write ⇒
(X)
Default value ⇒
6
(-)
(X)
5
4
WRST ERST
(R)
(R)
(X)
(X)
3
SRST
(R)
(X)
2
WTE
(W)
(1)
1
WT1
(W)
(1)
0
WT0
(W)
(1)
Table 3.5-1 Correspondence between reset cause flag bits and reset causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watchdog timer overflow
*
1
*
*
External reset request via RST pin
Clock supervisor reset
(MB90F828B only)
*
*
1
*
Software reset request
*
*
*
1
*:Previous state retained
X: Undefined
■ Notes About Reset Cause Bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are set to "1".
If, for example, an external reset request via the RST pin and the watchdog timer overflow occur at the
same time, both the ERST bit and the WRST bit are set to "1".
● Power-on reset
For a power-on reset, the PONR bit is set to "1", but all other reset cause bits are undefined.
Consequently, program the software so that it will ignore all reset cause bits except the PONR bit if it is
"1".
● Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
that corresponds to a reset cause that has already been generated once is not cleared even though another
reset is generated (its setting of "1" is retained).
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CM44-10147-2E
CHAPTER 3 RESET
3.6
MB90820B Series
3.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of Pins During a Reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = 011B).
● When internal vector mode has been set:
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
■ Status of Pins After Mode Data is Read
The status of pins after mode data has been read depends on the mode data (M1 and M0 = 00B).
● When single-chip mode has been selected (M1, M0 = 00B):
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
Note :
For those pins that change to high impedance when a reset cause is generated, take care that
devices connected to them do not malfunction.
See Table 5.7-1 for information about the state of pins during a reset.
CM44-10147-2E
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CHAPTER 3 RESET
3.6
74
MB90820B Series
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 4
CLOCK
This chapter describes the function and operation of the
clock used by MB90820B series microcontrollers.
CM44-10147-2E
4.1
Clock
4.2
Block Diagram of the Clock Generation Block
4.3
Clock Selection Registers
4.4
Clock Mode
4.5
Oscillation Stabilization Wait Interval
4.6
Connection of an Oscillator or an External Clock to the
Microcontroller
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CHAPTER 4 CLOCK
4.1
4.1
MB90820B Series
Clock
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock (φ). One internal clock cycle is regarded as one machine cycle.
Other clocks include a clock generated by source oscillation, called an oscillation clock,
and a clock generated by the internal PLL oscillation, called a PLL clock.
■ Clock
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external
clock to the clock generation block.
The clock generation block also contains the PLL clock multiplier circuit, which generates five clocks that
are multiples of the oscillation clock.
The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication
as well as controls internal clock operation by changing the clock with a clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
input of an external clock.
● Main clock (MCLK)
The main clock, which is the oscillation clock divided by 2, supplies the clock input to the time-base timer
and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock with the internal PLL multiplier circuit
(PLL oscillation circuit). Selection can be made from among four different PLL clocks.
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock that is
generated from the source clock frequency divided by 2 and the five clocks that are multiples of the source
clock frequency.
Note :
Although an oscillation clock of 3 MHz to 48 MHz can be generated when the operating voltage is
5 V, the maximum operating frequency for the CPU and peripheral functions is 24 MHz.
If a frequency multiplier rate exceeding the maximum operating frequency is specified, devices will
not operate correctly.
If, for example, a source oscillation of 12 MHz is generated, only a multiplier of 2 can be specified.
A PLL clock oscillation of 4 to 24 MHz is possible, but this range depends on the operating voltage and
multiplier. See "Data Sheet", for details.
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CM44-10147-2E
CHAPTER 4 CLOCK
4.1
MB90820B Series
■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls
operation of the CPU and peripheral functions, the operation of the CPU and peripheral functions is
affected by switching of the main clock and the PLL clock (clock mode) and a changing in the PLL clock
multiplier rate.
Since some peripheral functions receive frequency-divided output from the time-base timer, a peripheral
unit can select the clock best suited for its operation.
Figure 4.1-1 shows the clock supply map.
Figure 4.1-1 Clock supply map
Peripheral function
4
Watchdog timer
16-bit PPG
timer 0
16-bit PPG
timer 1
X0
Pin
Time-base timer
X1
Pin
16-bit PPG
timer 2
Clock generation block
16-bit reload
timer 0
1 2 3 4 6
PLL multiplier circuit
System clock
generation circuit
Clock
selector
Divide-by-2
HCLK
Internal CR
oscillator clock
φ
UART0
MCLK
UART1
Clock supervisor
PPG1
Pin
PPG2
Pin
TIN0
Pin
TO0
Pin
SCK0, SIN0
Pin
PCLK
Clock selector
PPG0
Pin
CPU
16-bit reload
timer 1
Waveform
generator
SOT0
Pin
SCK1, SIN1
Pin
SOT1
Pin
TIN1
Pin
TO1
Pin
DTTI
Pin
RTO0 to RTO5
Pin
16-bit output
compare ch.0 to ch.5
16-bit free-run timer
16-bit input capture
ch.0 to ch.3
HCLK:
MCLK:
PCLK:
φ :
8/10-bit A/D
converter
Oscillation clock
Main clock
PLL clock
Machine clock
8-bit D/A
converter
DTP / external
interrupt
FRCK
Pin
IN0 to IN3
Pin
DA0
Pin
DA1
Pin
INT0 to INT7
Pin
PWI0, PWI1
Pin
PWC0, PWC1
3
CM44-10147-2E
PWO0, PWO1
Pin
Oscillation stabilization
wait control
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CHAPTER 4 CLOCK
4.2
MB90820B Series
Block Diagram of the Clock Generation Block
4.2
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Operating clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
■ Block Diagram of the Clock Generation Block
Figure 4.2-1 shows a block diagram of the clock generation block.
Figure 4.2-1 also includes the standby control circuit and time-base timer circuit.
Figure 4.2-1 Block diagram of the clock generation block
Low-power consumption mode control register (LPMCR)
STP
SLP
SPL
RST TMDX CG1
CG0 RESV
RST Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selector
Select intermittent cycles
CPU clock
control circuit
Release reset
3
CPU clock
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Clock generator
Machine clock
Peripheral clock
control circuit
Oscillation stabilization wait time is passed
Peripheral clock
Operating clock selector
Oscillation stabilization
wait interval selector
3
2
x1 x2 x3 x4 x6
PLL multiplier
circuit
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
System clock
generation circuit
X0
Pin
X1
Pin
Internal CR oscillator clock
78
Clock
selector
Divideby-2
Divideby-512
Divideby-2
CS2
PLL clock control
register (PCKCR)
Clock selection register (CKSCR)
Divideby-4
Main clock
Divideby-2
Divideby-2
Time-base timer
Cock supervisor
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CM44-10147-2E
CHAPTER 4 CLOCK
4.2
MB90820B Series
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock (HCLK) through PLL oscillation and supplies a
clock that is a multiple of the frequency to the CPU clock selector.
● Operating clock selector
From among the main clock and five different PLL clocks, the operating clock selector selects the clock
that is supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR) and PLL clock control register (PCKCR)
The clock selection register and PLL clock control register are used to set switching between the oscillation
clock and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a PLL clock
multiplier rate.
● Oscillation stabilization wait interval selector
This selector selects an oscillation stabilization wait interval for the oscillation clock when stop mode is
released or when a watchdog timer reset occurs. Selection is made from among three kinds of time-base
timer output. In all other cases, an oscillation stabilization wait interval is not selected.
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CHAPTER 4 CLOCK
4.3
4.3
MB90820B Series
Clock Selection Registers
The clock selection registers consist of clock selection register (CKSCR) and PLL clock
control register (PCKCR).
■ Clock Selection Registers
Figure 4.3-1 shows the clock selection register (CKSCR) and PLL clock control register (PCKCR).
Figure 4.3-1 Clock selection registers
CKSCR
Bit bit 15
Address: 0000A1H RESV
Read/write (R)
bit 14
MCM
(R)
bit 13
WS1
(R/W)
bit 12
WS0
(R/W)
bit 11
RESV
(R/W)
bit 10
MCS
(R/W)
bit 9
CS1
(R/W)
bit 14
bit 13
bit 12
−
−
−
−
−
−
bit 11 bit 10
bit 9
RESV RESV RESV
(W)
(W)
(W)
bit 8
CS0 Initial value: 11111100B
(R/W)
PCKCR
Bit bit 15
Address: 00002FH
−
Read/write
−
bit 8
CS2
(W)
Initial value : xxxx0000B
(R): Read only
(W): Write only
(R/W): Read / write
-: Undefined
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CM44-10147-2E
CHAPTER 4 CLOCK
4.3
MB90820B Series
4.3.1
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to set switching between the main clock
and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a
PLL clock multiplier rate.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 4.3-2 shows the configuration of the clock selection register (CKSCR). Table 4.3-1 describes the
function of each bit in the clock selection register (CKSCR).
Figure 4.3-2 Configuration of the clock selection register (CKSCR)
Address
0000A1H
bit15
bit14
bit10
bit9
bit8
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
R/W
R/W
R/W
R/W
R
bit13
R/W
bit12
bit11
R/W
R/W
bit7
bit0
(LPMCR)
Initial value
11111100B
bit 9 bit 8
CS1 CS0
Multiplier rate selection bits
0
0
0
1
Refer to PLL clock control register
1
0
(PCKCR)
1
1
bit 10
MCS
Machine clock selection bit
0
PLL clock selected.
1
Main clock selected.
bit 13 bit 12
WS1 WS0
CM44-10147-2E
10
0
0
2 / HCLK (Approx. 0.256ms)
0
1
2 / HCLK (Approx. 2.05ms)
1
0
2 / HCLK (Approx. 4.10ms)
1
1
2 / HCLK (Approx. 8.19ms)*
13
14
15
bit 14
MCM
Machine clock indication bit
0
A PLL clock is used as the machine clock.
1
The main clock is used as the machine clock.
RESV
HCLK: Oscillation clock frequency
R/W: Read/write
R:
Read only
: Initial value
Oscillation stabilization wait interval selection bits
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Reserved bit
1 must always be written to these bits.
* At power-on reset, the oscillation stabilization wait interval is 216/HCLK.
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CHAPTER 4 CLOCK
4.3
MB90820B Series
Note :
If the machine clock selection bit is not set, the main clock is used as the machine clock.
Table 4.3-1 Function description of each bit in the clock selection register (CKSCR)
Bit name
bit15,
bit11
Function
RESV:
Reserved bits
Note :
• "1" must always be written to these bits.
•
bit14
MCM:
Machine clock
indication bit
Indicates whether the main clock or PLL clock is used as the machine clock.
MCM = "0": PLL clock is selected
MCM = "1": Main clock is selected
•
•
If MCS = "0" and MCM = "1", this indicates the PLL clock oscillation
stabilization wait state.
Writing has no effect on the operation.
•
bit13,
bit12
WS1, WS0:
Oscillation
stabilization wait
interval
selection bits
These bits select an oscillation stabilization wait interval of the oscillation clock
after stop mode has been released.
• These bits are initialized to "11B" by all reset causes.
Note :
The oscillation stabilization wait interval must be set to a value appropriate for the
oscillator used. See Section "3.2 Reset Causes and Oscillation Stabilization Wait
Intervals".
The oscillation stabilization wait period for all PLL clocks is fixed at 214/HCLK.
•
bit10
bit9,
bit8
82
MCS:
Machine clock
selection bit
CS1, CS0:
Multiplier rate
selection bits
This bit specifies whether the main clock or a PLL clock is selected as the
machine clock.
• When this bit is "0", a PLL clock is selected. When this bit is "1", the main clock
is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization
wait interval for the PLL clock starts. As a result, the time-base timer is
automatically cleared, and the TBOF bit of the time-base timer control register
(TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization wait period is fixed at 214/HCLK (the
oscillation stabilization wait interval is approx. 2 ms for an oscillation clock
frequency of 4 MHz).
• When the main clock has been selected, the operating clock frequency is the
frequency of the oscillation clock divided by 2 (e.g., the operating clock is 2 MHz
when the oscillation clock frequency is 4 MHz).
• This bit is initialized to "1" by power-on or watchdog reset.
Note :
When the MCS bit is "1", write "0" to it only when the time-base timer interrupt is
masked by the TBIE bit of the time-base timer control register (TBTC) or the
interrupt level register (ILM).
•
•
•
•
These bits, combine with CS2 bit of PCKCR, select a PLL clock multiplier rate.
Selection can be made from among five different multiplier rates.
These bits are initialized to 00B by all reset causes.
Refer to PCKCR for the relationship between setting CS2, CS1 and CS0 bits and
the PLL clock multiplier rate selection,
Note :
When the MCS bit is "0", writing to these bits is not allowed. Write to the CS1
and CS0 bits only after setting the MCS bit to "1" (main clock mode).
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 4 CLOCK
4.3
MB90820B Series
4.3.2
PLL Clock Control Register (PCKCR)
The PLL clock control register (PCKCR), combine with CS1 and CS0 bits in CKSCR, is
used to select a PLL clock multiplier rate.
■ Configuration of the PLL Clock Control Register (PCKCR)
Figure 4.3-3 shows the configuration of the PLL clock control register (PCKCR). Table 4.3-2 describes the
function of each bit in the PLL clock control register (PCKCR).
Figure 4.3-3 Configuration of the PLL clock control register (PCKCR)
PCKCR
bit 15
Address: 00002FH
bit 14
bit 13
bit 12
-
-
-
-
-
-
-
-
bit 11
bit 10
bit 9
RESV RESV RESV
(W)
(W)
bit 8
CS2
(W)
Initial value:
xxxx0000B
(W)
bit 8
CS2
(W)
: Write only
-
: Undefined
Multiplier rate selection bit
0
Select PLL clock as 1 to 4 times the oscillator clock
depending on CS1 and CS0 bit of CKSCR.
1
Possible to select six times the oscillator clock as
PLL clock depending on CS1 and CS0 bit of CKSCR.
: Initial value
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CHAPTER 4 CLOCK
4.3
MB90820B Series
Table 4.3-2 Function description of each bit in the PLL clock control register (PCKCR)
Bit name
Function
bit 15
to
Not used bits
bit 12
•
•
When read, the value is undefined.
Writing has no effect on operation.
bit 11
to
Reserved bits
bit 9
•
•
When read, the value is undefined.
Always write "0" to these bits
•
•
•
•
•
These bits, and CS2 bit of PCKCR, select a PLL clock multiplier rate.
Selection can be made from among five different multiplier rates.
This bit is initialized to "0" by all reset causes.
The read value is undefined.
Recommended setting of CS2, CS1 and CS0 bits:
bit8
CS2:
Multiplier rate
selection bit
CS2
CS1
CS0
0
0
0
1 × HCLK (4 MHz)
0
0
1
2 × HCLK (8 MHz)
0
1
0
3 × HCLK (12 MHz)
0
1
1
4 × HCLK (16 MHz)
1
1
0
6 × HCLK (24 MHz)
( other )
PLL clock multiplex time
Setting not allowed
Note :
When the MCS bit of CKSCR is "0", writing to this bit is not allowed.
Write to the CS2 bits only after setting the MCS bit of CKSCR to "1"
(main clock mode).
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CM44-10147-2E
CHAPTER 4 CLOCK
4.4
MB90820B Series
4.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■ Main Clock Mode and PLL Clock Mode
● Main clock mode
In main clock mode, the main clock, whose frequency is the oscillation clock (HCLK) divided by 2, is used
as the operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier rate is selected with the clock selection register (CKSCR: CS1 and CS0) and PLL
clock control register(PCKCR: CS2).
■ Clock Mode Transition
Switching between main clock mode and PLL clock mode is done by writing to the MCS bit of the clock
selection register (CKSCR).
● Switching from main clock mode to PLL clock mode
When the MCS bit of CKSCR is "1" and "0" is written to it, the switch from the main clock to a PLL clock
occurs after the PLL clock oscillation stabilization wait period (214/HCLK).
● Switching from PLL clock mode to main clock mode
When the MCS bit of CKSCR is "0" and "1" is written to it, the switch from the PLL clock to the main
clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 12 PLL clocks).
Note :
Even though the MCS bit of CKSCR is rewritten, machine clock switching does not occur
immediately. When operating a resource that depends on the machine clock, make sure that
machine clock switching has been done by referring to the MCM bit of CKSCR before operating the
resource.
■ Selection of a PLL Clock Multiplier Rate
Writing a value from "000B" to "011B" or "110B" to the CS2 bit of PCKCR, the CS1 and CS0 bits of
CKSCR selects one to the five PLL clock multiplier rates.
■ Machine Clock
The machine clock may be either a PLL clock output from the PLL multiplier circuit or the clock that is the
source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions.
Either the main clock or a PLL clock can be selected by writing to the MCS bit of CKSCR.
Figure 4.4-1 shows the status change caused by the machine clock switching.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 4 CLOCK
4.4
MB90820B Series
Figure 4.4-1 Status change diagram for machine clock selection
Power-on
(1)
Main
MCS = 1
MCM = 1
Main
PLLx
MCS = 0
MCM = 1
CS2, CS1, CS0 = xxx
(7)
CS2, CS1, CS0 = xxx
(2)
(3)
(4)
(5)
(6)
PLL1
Main
(8) MCS = 1
MCM = 0
CS2, CS1, CS0 = 000
PLL1: Multiplied
by 1
MCS = 0
(7) MCM = 0
CS2, CS1, CS0 = 000
(8)
PLL2
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 001
(8)
PLL3
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 010
(8)
PLL4
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 011
(8)
PLL6
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 110
PLL2: Multiplied
by 2
(7) MCS = 0
MCM = 0
CS2, CS1, CS0 = 001
PLL3: Multiplied
by 3
(7) MCS = 0
MCM = 0
CS2, CS1, CS0 = 010
(7)
PLL4: Multiplied
by 4
MCS = 0
MCM = 0
CS2, CS1, CS0 = 011
PLL6: Multiplied
by 6
MCS = 0
(7) MCM = 0
CS2, CS1, CS0 = 110
(1) The MCS bit is cleared.
(2) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 000.
(3) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 001.
(4) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 010.
(5) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 011.
(6) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 110.
(7) The MCS bit is set (including also hardware standby and watchdog timer resets).
(8) PLL clock frequency and main clock frequency synchronization timing.
Machine clock selection bit of CKSCR
MCS:
Machine clock indication bit of CKSCR
MCM:
CS1, CS0: Multiplier rate selection bits of CKSCR
Multiplier rate selection bit of PCKCR
CS2:
Note :
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
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CM44-10147-2E
CHAPTER 4 CLOCK
4.5
MB90820B Series
4.5
Oscillation Stabilization Wait Interval
When the power is turned on, when stop mode is released, or when a watchdog timer
reset occurs, the oscillation clock starts, oscillation is unstable initially. Therefore, an
oscillation stabilization wait interval is required. When the switch from the main clock to
a PLL clock occurs, an oscillation stabilization wait interval is also required after PLL
oscillation starts.
■ Oscillation Stabilization Wait Interval
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to several
dozen milliseconds until they stabilize at their natural frequency when oscillation starts.
For this reason, CPU operation is not allowed as soon as oscillation starts and is allowed only after full
stabilization of oscillation. After the oscillation stabilization wait interval has elapsed, the clock is supplied
to the CPU.
Because the oscillation stabilization wait time depends on the type of the oscillator (crystal, ceramic, etc.),
the proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation
stabilization wait interval is selected by setting the clock selection register (CKSCR).
In a switch from the main clock to a PLL clock, the CPU continues to operate on the main clock during the
oscillation stabilization wait interval of the PLL. After this interval, the operating clock switches to the PLL
clock.
Figure 4.5-1 shows the operation immediately after oscillation starts.
Figure 4.5-1 Operation immediately after oscillation starts
Oscillator-activated Oscillation stabilization Normal operation start
wait interval
oscillation time
or change to PLL clock
Start of oscillation
CM44-10147-2E
Stable oscillation
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CHAPTER 4 CLOCK
4.6
4.6
MB90820B Series
Connection of an Oscillator or an External Clock to the
Microcontroller
The F2MC-16LX microcontroller contains a system clock generation circuit. Connecting
an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the microcontroller.
■ Connection of an Oscillator or an External Clock to the Microcontroller
● Example of connecting a crystal or ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 4.6-1.
Figure 4.6-1 Example of connecting a crystal or ceramic oscillator to the microcontroller
X0
MB90820B series
X1
● Example of connecting an external clock to the microcontroller
As shown in Figure 4.6-2, connect an external clock to pin X0. Pin X1 must be open.
Figure 4.6-2 Example of connecting an external clock to the microcontroller
X0
MB90820B series
Open
88
X1
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CM44-10147-2E
CHAPTER 5
CLOCK SUPERVISOR
This chapter describes the functions and operations of
the clock supervisor.
(This feature is available for MB90F828B only )
5.1 Overview of Clock Supervisor
5.2 Configuration of Clock Supervisor
5.3 Registers of Clock Supervisor
5.4 Operations of Clock Supervisor
5.5 Precautions when Using Clock Supervisor
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CHAPTER 5 CLOCK SUPERVISOR
5.1
5.1
MB90820B Series
Overview of Clock Supervisor
The clock supervisor prevents the situation which is out of control, when main clock
oscillation has halted. This function switches to an CR clock generated with internal CR
oscillator circuit, if main clock oscillation has halted.
■ Overview of Clock Supervisor
• The clock supervisor monitors the main clock oscillation and generates an internal reset if it detects that
the oscillation has halted. In this case, the clock supervisor switches to the internal CR clock.
The reset source register (RSRR) can be used to determine whether a reset was triggered by the clock
supervisor.
• A main clock oscillation halt is detected if the rising edge of the main clock is not detected for 4 CR
clock cycles. The clock supervisor may detect incorrectly, if main clock is longer than 4 CR clock
cycles.
• Setting registers enable to prohibit the reset output.
• While the clock stops in main clock stop mode, clock monitoring is disabled.
Note:
Refer to the data sheet for the period and other details about the CR clock.
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CM44-10147-2E
CHAPTER 5 CLOCK SUPERVISOR
5.2
MB90820B Series
5.2
Configuration of Clock Supervisor
The clock supervisor consists of the following blocks:
• Control circuit
• CR oscillator circuit
• Main clock monitor
• Main clock selector
• CSV control register (CSVCR)
■ Block Diagram of Clock Supervisor
Figure 5.2-1 shows a block diagram of the clock supervisor.
Figure 5.2-1 Block Diagram of Clock Supervisor
Internal bus
CSV control register (CSVCR)
Control circuit
Enable
Enable
CR oscillator
circuit
CR clock
Main clock
(From X0/X1)
CM44-10147-2E
Detect
Internal reset
Select
main clock
Main clock
monitor
Main
clock
selector
FUJITSU MICROELECTRONICS LIMITED
Internal
main clock
PLL
circuit
Selector
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CHAPTER 5 CLOCK SUPERVISOR
5.2
MB90820B Series
● Control circuit
This block controls the clocks, resets, and other settings based on the information in the CSV control
register (CSVCR).
● CR oscillator circuit
This block is a internal CR oscillator circuit. The oscillation can be turned on or off via a control signal
from the control circuit. This also serves as an internal clock after a clock halt is detected.
● Main clock monitor
This block monitors whether the main clock halts.
● Main clock selector
This block outputs the CR clock as the internal main clock upon detection of a main clock halt.
● CSV control register (CSVCR)
This block is used to control clock monitoring and CR clock and to check information on halt detection.
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CM44-10147-2E
CHAPTER 5 CLOCK SUPERVISOR
5.3
MB90820B Series
5.3
Registers of Clock Supervisor
This section describes the clock supervisor registers.
■ Clock Supervisor Register
Figure 5.3-1 shows the register of the clock supervisor.
Figure 5.3-1 Clock Supervisor Register
Clock supervisor control register (CSVCR)
bit
Address
00008AH
7
6
5
4
3
Reserved
MM
Reserved
RCE
MSVE
-
R
-
R/W
R/W
2
1
0
Reserved Reserved Reserved
-
-
Initial value
00011100B
R/W
R/W: Readable/writable
R:
Read only
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CHAPTER 5 CLOCK SUPERVISOR
5.3
5.3.1
MB90820B Series
Clock Supervisor Control Register (CSVCR)
The clock supervisor control register (CSVCR) is used to enable the various functions
and to check the status.
■ Clock Supervisor Control Register (CSVCR)
Figure 5.3-2 Clock Supervisor Control Register (CSVCR)
bit
7
Address
Reserved
00008A H
-
6
5
4
MM
Reserved
RCE
R
-
R/W
Reserved
0
Reserved
0
Reserved
0
MSVE
0
1
RCE
0
1
Reserved
0
MM
0
1
Reserved
0
3
2
1
0
MSVE Reserved Reserved Reserved
R/W
-
-
Initial value
00011100B
R/W
Reserved bit
Be sure to set this bit to "0".
Reserved bit
Be sure to set this bit to "0".
Reserved bit
Be sure to set this bit to "0".
Main clock monitoring enable bit
Disables main clock monitoring.
Enables main clock monitoring.
CR clock oscillation enable bit
Disables CR clock oscillation.
Enables CR clock oscillation.
Reserved bit
Be sure to set this bit to "0".
Main clock halt detection bit
Main clock halt not detected.
Main clock halt detected.
Reserved bit
Be sure to set this bit to "0".
R/W
: Readable/writable
R
: Read only
Reserved : Reserved bit
: Initial value
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CM44-10147-2E
CHAPTER 5 CLOCK SUPERVISOR
5.3
MB90820B Series
Table 5.3-1 Functions of Bits in Clock Supervisor Control Register (CSVCR)
Bit name
Function
bit7
Reserved bit
This bit is reserved.
Write "0" to this bit. The read value is always "0".
bit6
MM:
Main clock halt
detection bit
This bit is read-only, and this bit indicates that a main clock oscillation halt has been detected.
When set to "1": The bit indicates that a main clock oscillation halt has been detected.
When set to "0": The bit indicates that no main clock oscillation halt has been detected.
Writing "1" to this bit does not affect the operation.
bit5
Reserved bit
This bit is reserved.
Write "0" to this bit. The read value is always "0".
bit4
RCE:
CR clock oscillation
enable bit
This bit enables CR oscillation.
When set to "1": The bit enables oscillation.
When set to "0": The bit disables oscillation.
Before writing "0" to this bit, make sure that the clock monitor function has been disabled with the
MM and SM bits set to "0".
bit3
This bit enables the monitoring of main clock oscillation.
MSVE:
When set to "1": The bit enables main clock monitoring.
Main clock monitoring
When set to "0": The bit disables main clock monitoring.
enable bit
This bit is set to "1" only when a power-on reset occurs.
bit2 to bit0 Reserved bit
This bit is reserved.
Write "0" to this bit. The read value is always "0".
Note:
When the power is turned on, the clock supervisor starts monitoring after the oscillation stabilization
wait time for the main clock elapses. The oscillation stabilization wait time of the main clock must
therefore be longer than the time required for the clock supervisor to start operating.
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CHAPTER 5 CLOCK SUPERVISOR
5.4
5.4
MB90820B Series
Operations of Clock Supervisor
This section describes the operations of the clock supervisor.
■ Operations of Clock Supervisor
The clock supervisor monitors the main clock oscillation. If main clock oscillation has halted, the device
switches to an CR clock and generates a reset.
The following describes the operation in each clock mode.
● Main clock oscillation halt in main clock mode
The clock supervisor detect that main clock oscillation has halted, if no rising edge is detected on the main
clock for 4 CR clock cycles in main clock mode.
If a main clock halt is detected, a reset is generated and the main clock switches to the CR clock.
The clock supervisor may detect incorrectly, if main clock is a low speed (longer than 4 CR clock cycles).
It results from using the CR clock for detecting that main clock oscillation have halted.
The clock supervisor does not detect the main clock during stop mode.
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CM44-10147-2E
CHAPTER 5 CLOCK SUPERVISOR
5.4
MB90820B Series
■ Example Operation Flowchart for the Clock Supervisor
Figure 5.4-1 Example Operation Flowchart for the Clock Supervisor
Power on
Has the main
oscillation started?
No
(2)
(1)
Wait for reset state
(oscillation
stabilization wait)
Yes
Oscillation
restarts
Main clock
operation
(4)
No
CR clock
operation
Yes
(3)
Oscillation
halted?
CSV reset
generated
Reset is cleared
(CR clock operation)
External reset
generated
(5)
CSV : Clock supervisor
1. After the power is turned on, the main clock operation starts after the oscillation stabilization wait time
generated by the main oscillation has elapsed.
2. If the main clock halts at power on, the device remains in the reset state (oscillation stabilization wait
state). The operation changes to the main clock, after the oscillation restarts and the oscillation
stabilization wait time elapsed.
3. If an oscillation halt is detected during main clock operation, the operating clock is switched to the CR
clock and a reset is generated.
4. If the main oscillation continues (oscillation does not halt), the device continues to run using the main
clock.
5. If an external reset occurs during the CR clock operation, operation changes to the main clock.
However, if the oscillation is halted at this time, another CSV reset is generated and the device returns
to CR clock operation.
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CHAPTER 5 CLOCK SUPERVISOR
5.4
MB90820B Series
■ Example Startup Flowchart when using the Clock Supervisor
Inserting checking process of the main clock stop detection bit (CSVCR:MM) enables user programs to
control the Fail Safe routine.
Figure 5.4-2 shows the example startup flowchart when using the clock supervisor.
Figure 5.4-2 Example Startup Flowchart when using the Clock Supervisor
Reset generated
CSVCR:MM=1 ?
No
Yes
Yes
Fail Safe routine
(PLL use prohibited)
Use PLL?
NO
Main routine
(PLL clock)
98
Main routine
(main clock)
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CM44-10147-2E
CHAPTER 5 CLOCK SUPERVISOR
5.5
MB90820B Series
5.5
Precautions when Using Clock Supervisor
Take note of the following points when using the clock supervisor.
■ Precautions when using the Clock Supervisor
● Operation of the clock supervisor at power on
When the power is turned on, the clock supervisor starts monitoring after the oscillation stabilization wait
time for the main clock has elapsed. Therefore, unless the operation continues for longer than the
oscillation stabilization wait time for the main clock, the clock supervisor will not operate.
● Transition to CR clock mode
Do not turn on the PLL after changing to CR clock mode.
As the frequency is below the lower limit for the input frequency of the PLL circuit, the PLL operation will
not be guaranteed.
● Disabling the CR oscillation
Do not use the CR oscillation enable bit (CSVCR:RCE) to disable the CR oscillation during CR clock
mode.
As this halts the internal clock, it may result in deadlock.
● Initializing the main clock halt detection bit
The main clock halt detection bit (CSVCR:MM) is initialized by a power-on reset nor external reset only.
The bit is not initialized by neither a watchdog reset, software reset, nor CSV reset. Accordingly, the device
remains in CR clock mode if one of these resets occurs during CR clock mode.
● Verifying reset execution using clock supervisor function
To verify if a reset was executed using the clock monitoring function, read the WDTC register with
software to check the reset factor. When the ERST (bit 4 of WDTC) is set, generation of a reset via the
external pin or clock supervisor reset can be verified.
If the MM bit (bit 6 of CSVCR) is "0", the reset factor is external reset. When the MM is "1", it is the loss
of main clock.
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5.5
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MB90820B Series
CM44-10147-2E
CHAPTER 6
LOW-POWER
CONSUMPTION MODE
This chapter describes the low-power consumption
mode of MB90820B series microcontrollers.
CM44-10147-2E
6.1
Low-Power Consumption Mode
6.2
Block Diagram of the Low-Power Consumption Control Circuit
6.3
Low-Power Consumption Mode Control Register (LPMCR)
6.4
CPU Intermittent Operation Mode
6.5
Standby Mode
6.6
State Change Diagram
6.7
State of Pins in Standby Mode and During Reset
6.8
Usage Notes on Low-Power Consumption Mode
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1
6.1
MB90820B Series
Low-Power Consumption Mode
F2MC-16LX microcontrollers have the following CPU operating modes, any of which can
be used depending on the operating clock selection and clock operation control:
• Clock mode (PLL clock mode and main clock mode)
• CPU intermittent operation mode (PLL clock intermittent operation mode and main
clock intermittent operation mode)
• Standby mode (sleep, time-base timer and stop modes)
All modes other than PLL clock mode are low-power consumption mode.
■ CPU Operating Modes and Current Consumption
Figure 6.1-1 shows the relation between the CPU operating modes and current consumption
Figure 6.1-1 CPU operating modes and current consumption
Current consumption
Several tens
of mA
CPU operating
mode
Multiplied-by-six clock
PLL clock mode
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Multiplied-by-six clock
PLL clock intermittent
operation mode
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Main clock mode (1/2 clock mode)
Main clock intermittent operation mode
Several mA
Standby mode
Sleep mode
Time-base timer mode
Stop mode
Several µA
Low power consumption mode
Note:
This figure is only an indication of the degree for power consumption in each mode. Actual current consumption values
may not agree with those in the figure.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1
MB90820B Series
■ Clock Mode
● PLL clock mode
A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and
peripheral functions.
● Main clock mode
The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU
and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive.
Reference:
See Section "4.1 Clock", for details about clock mode.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses
are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode,
intermittent clock pulses are only applied to the CPU when it is accessing a register, an internal memory, a
peripheral function, or an external unit.
■ Standby Mode
In standby mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep
mode) or the CPU and peripheral functions (time-base timer mode), or stops the oscillation clock itself
(stop mode), reducing power consumption.
● PLL sleep mode
PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock
mode; other components continue to operate on the PLL clock.
● Main sleep mode
Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock
mode; other components continue to operate on the main clock.
● PLL time-base timer mode
PLL time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
PLL clock, and time-base timer, to stop. All functions other than the time-base timer are deactivated.
● Main time-base timer mode
Main time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
main clock, and the time-base timer, to stop. All functions other than the time-base timer are deactivated.
● Stop mode
Stop mode causes the source oscillation (HCLK) to stop. All functions are deactivated.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1
MB90820B Series
Note :
Because stop mode turns the oscillation clock off, this mode saves most power while data is being
retained.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2
MB90820B Series
6.2
Block Diagram of the Low-Power Consumption Control
Circuit
The low-power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby clock control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of the Low-Power Consumption Control Circuit
Figure 6.2-1 shows the block diagram of the low-power consumption control circuit.
Figure 6.2-1 Block diagram of the low-power consumption control circuit
Low-power consumption mode control register (LPMCR)
STP
SLP
SPL
RST TMDX CG1
CG0 RESV
RST Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selector
Select intermittent cycles
CPU clock
control circuit
Release reset
3
CPU clock
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Clock generator
Machine clock
Peripheral clock
control circuit
Oscillation stabilization wait time is passed
Peripheral clock
Operating clock selector
Oscillation stabilization
wait interval selector
3
2
x1 x2 x3 x4 x6
PLL multiplier
circuit
RESV MCM WS1 WS0 RESV MCS
CS1
CS0
System clock
generation circuit
X0
Pin
X1
Pin
Internal CR oscillator clock
CM44-10147-2E
Clock
selector
Divideby-2
Divideby-512
Divideby-2
CS2
PLL clock control
register (PCKCR)
Clock selection register (CKSCR)
Divideby-4
Main clock
Divideby-2
Divideby-2
Time-base timer
Cock supervisor
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2
MB90820B Series
● CPU intermittent operation selector
This selector selects the number of clock pulses the CPU is to be halted during CPU intermittent operation
mode.
● Standby control circuit
The standby control circuit controls the CPU clock control circuit and the peripheral clock control circuit,
and turns the low-power consumption mode on and off.
● CPU clock control circuit
This circuit controls the clocks supplied to the CPU. This circuit controls the clocks supplied to peripheral
functions for the peripheral clock control.
● Peripheral clock control circuit
This circuit controls the clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes the external pins high-impedance when the microcontroller enters time-base timer mode
and stop mode.
For the pins with the pull-up option, this circuit disconnects the pull-up resistor when the microcontroller
enters stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register is used to switch to and release standby mode and to set the CPU intermittent operation
function.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3
MB90820B Series
6.3
Low-Power Consumption Mode Control Register (LPMCR)
The low-power consumption mode control register (LPMCR) switches to or releases
low-power consumption mode. It is also used to set the number of CPU clock pulses
the CPU is to be halted during CPU intermittent mode.
■ Low-Power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of the low-power consumption mode control register (LPMCR)
bit15
Address
0000A0H
(CKSCR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
STP
SLP
SPL
RST
TMDX
CG1
CG0 RESV
W
W
R/W
W
W
R/W
R/W
Initial value
00011000B
R/W
bit 0
RESV
Reserved bit
"1" must always be written to this bit.
bit 2
bit 1
CPU halt clock pulses selection bits
CG1 CG0
0
0
0 clock cycles (CPU clock = Peripheral clock)
0
1
9 clock cycles (CPU clock: Peripheral clock = 1: 3 to 4 approx.)
1
0
17 clock cycles (CPU clock: Peripheral clock = 1: 5 to 6 approx.)
1
1
33 clock cycles (CPU clock: Peripheral clock = 1: 9 to 10 approx.)
bit 3
TMDX
Time-base timer mode bit
0
Switch to time-base timer mode
1
No change, no effect on operation
bit 4
RST
Internal reset signal generation bit
0
Generates an internal reset signal of 3 machine cycles.
1
No change, no effect on operation
bit 5
SPL
Pin state setting bit (for time-base timer mode and stop mode)
0
Retained
1
High-impedance
bit 6
SLP
Sleep mode bit
0
No change, no effect on operation
1
Switch to sleep mode
bit 7
STP
R/W:
W:
CM44-10147-2E
Readable/Writable
Write only
: Initial value
Stop mode bit
0
No change, no effect on operation
1
Switch to stop mode
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3
MB90820B Series
Table 6.3-1 Function description of each bit in the low-power consumption mode control
register (LPMCR)
Bit name
Function
STP:
Stop mode bit
• This bit indicates switching to stop mode.
When "1" is written to this bit: the mode switches to stop mode.
Writing "0" to this bit: no effect on operation.
• This bit is cleared to "0" by a reset or by release of stop state.
• The read value of this bit is always "0".
bit6
SLP:
Sleep mode bit
• This bit indicates switching to sleep mode.
When "1" is written to this bit: the mode switches to sleep mode.
Writing "0" to this bit: no effect on operation.
• This bit is cleared to "0" by a reset or by release of sleep mode.
• The read value of this bit is always "0".
bit5
SPL:
Pin state setting bit (for
time-base timer mode
and stop mode)
bit4
RST:
Internal reset signal
generation bit
bit7
•
This bit is enabled while either time-base timer mode or stop
mode is in effect.
When this bit is "0": the level of the external pins is retained.
When this bit is "1": the status of the external pins changes to
high-impedance.
• This bit is initialized to "0" by a reset.
•
•
•
•
•
bit3
TMDX:
Time-base timer mode
bit
•
•
•
•
When "0" is written to this bit, an internal reset signal of 3
machine cycles is generated.
Writing "1" to this bit has no effect on operation.
The read value of this bit is always "1".
This bit indicates switching to time-base timer mode.
When "0" is written to this bit, the mode switches to time-base
timer mode.
Writing "1" to this bit has no effect on operation.
This bit is set to "1" by a reset or by release of time-base timer
mode.
The read value of this bit is always "1".
These bits set the number of CPU halt clock pulses for the CPU
intermittent operation function.
The clock supplied to the CPU is stopped after the execution of
every instruction for the specified number of clock pulses.
Selection can be made from among four different clock pulses.
These bits are initialized to "00B" by a power-on or watchdog
timer reset. Other resets do not initialize these bits.
bit2,
bit1
CG1, CG0:
CPU halt clock pulses
selection bits
•
bit0
RESV:
Reserved bit
Note:
"1" must always be written to this bit.
•
•
Note:
If "1" is written to the STP bit and SLP bit, and "0" is written to TMDX bit at the same time, switching
to stop mode takes the highest priority, then time-base timer mode and sleep mode have the lowest
priority.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3
MB90820B Series
■ Access to the Low-Power Consumption Mode Control Register
Writing to the low-power consumption mode control register causes a change to a low-power consumption
mode (stop mode, sleep mode, time-base timer mode, or watch mode). In this case, please use one of the
instructions specified in Table 6.3-2.
Always insert the following instructions (indicated by the box below) immediately after the instruction
from Table 6.3-2 for switching to a low-power consumption mode.
MOV LPMCR,#H’xx
NOP
NOP
JMP $+3
MOV A,#H’10
; Instruction from Table 6.3-2 for switching to a low-power consumption mode
; Jump to next instruction
; Next instruction
The operation when recovering from low-power consumption mode is not guaranteed unless the
instructions shown in the box above are used.
If accessing the low-power consumption control register from a C program, refer to the notes in "■ Points
to Note when Accessing the Low-power Consumption Mode Control Register (LPMCR) to Switch to
Standby Mode" in "6.8 Usage Notes on Low-Power Consumption Mode".
When writing to the low-power consumption mode control register (LPMCR) using a word-length
instruction, ensure that you write to an even-numbered address. Writing to an odd-numbered address to
switch to low-power consumption mode may result in misoperation.
No restrictions apply on what instructions to use when performing operations on functions other than those
listed in Table 6.3-2.
Table 6.3-2 Instructions to be used for switching to low-power consumption mode
MOV io, #imm8
MOV io, A
MOV @RLi+disp8, A
MOVW io, #imm16
MOVW io, A
MOVW @RLi+disp8, A
SETB io:bp
CLRB io:bp
CM44-10147-2E
MOV dir, #imm8
MOV dir, A
MOV eam, #imm8
MOV addr16, A
MOV eam, Ri
MOV eam, A
MOVW dir, #imm16
MOVW dir, A
MOVW eam, #imm16
MOVW addr16, A
MOVW eam, RWi
MOVW eam, A
SETB dir:bp
CLRB dir:bp
SETB addr16:bp
CLRB addr16:bp
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6.4
6.4
MB90820B Series
CPU Intermittent Operation Mode
CPU intermittent operation mode is used for intermittent operation of the CPU while
external buses and peripheral functions continue to operate at high speed. Its purpose
is to reduce power consumption.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period. The halt
occurs after the execution of every instruction that accesses a register, internal memory (ROM and RAM),
I/O, peripheral functions, and the external bus. Internal bus cycle activation is therefore delayed. While a
high rate of peripheral clock pulses are supplied to the peripheral functions, the rate of CPU execution is
reduced, enabling processing with low-power consumption.
• The CG1 and CG0 bits of the low-power consumption mode control register (LPMCR) are used to
select the number for clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the number of times instructions that access a register, internal memory,
peripheral functions, and the external bus are executed by the number of clock pulses per halt cycle.
Add this correction value to the normal execution time.
Figure 6.4-1 shows the operating clock pulses during CPU intermittent operation mode.
Figure 6.4-1 Clock pulses during CPU intermittent operation
Peripheral clock
CPU clock
Halt cycle
One instruction
execution cycle
Internal bus activation cycle
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5
MB90820B Series
6.5
Standby Mode
Standby mode includes the sleep (PLL sleep and main sleep), time-base timer, and stop
modes.
■ Operating Status During Standby Mode
Figure 6.5-1 summarizes the operating statuses during standby mode.
Table 6.5-1 Operation statuses during standby mode
Standby mode
Sleep
mode
PLL sleep
mode
MCS = 0
SLP = 1
Main sleep
mode
MCS = 1
SLP = 1
PLL time-base
timer mode
(SPL = 0)
PLL time-base
timer mode
(SPL = 1)
Time-base
timer
mode
Main timebase timer
mode
(SPL = 0)
Main timebase timer
mode
(SPL = 1)
Main/PLL stop
mode
(SPL = 0)
Stop
mode
Condition
for switch
Main/PLL stop
mode
(SPL = 1)
Oscillation
Clock
CPU
Peripheral
Pin
Active
Active
Releas
e event
Hold
MCS = 0
TMDX = 0
Active
Hi-Z
Active
Inactive *
Inactive
Hold
Reset or
Interrupt
MCS = 1
STP = 1
Hi-Z
Hold
MCS = x
STP = 1
Inactive
Inactive
Inactive
Hi-Z
*:
Only the time-base timer is active.
SPL:
Pin state setting bit of low-power consumption mode control register (LPMCR)
SLP:
Sleep mode bit of LPMCR
STP:
Stop mode bit of LPMCR
TMDX: Time-base timer mode bit of LPMCR
MCS:
Machine clock selection bit of clock selection register (CKSCR)
Hi-Z:
High-impedance
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6.5
6.5.1
MB90820B Series
Sleep Mode
Sleep mode causes the CPU operating clock to stop while other components continue
to operate.
When the low-power consumption mode control register (LPMCR) indicates a switch to
sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set.
Alternatively, a switch to main sleep mode occurs if main clock mode has been set.
■ Switching to Sleep Mode
Writing "1" to the SLP and TMDX bits of LPMCR and "0" to the STP bit of LPMCR triggers a switch to
sleep mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
sleep mode. If the MCS bit of CKSCR is "1", the microcontroller enters main sleep mode.
Note :
Since the STP/TMDX bit setting overrides the SLP bit setting when "1" is written to the SLP and
STP, and "0" to TMDX bit at the same time, the mode switches to stop/time-base timer mode.
● Data retention function
In sleep mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
● Operation during an interrupt request
Writing "1" to the SLP bit of LPMCR during an interrupt request does not trigger a switch to sleep mode.
If the CPU does not accept the interrupt, the CPU executes the next instruction. If the CPU accepts the
interrupt, CPU operation immediately branches to the interrupt processing routine.
● Status of pins
During sleep mode, all pins retain the state they had immediately before the switch to sleep mode. The
once exceptions are the pins used for bus input/output or bus control.
■ Release of Sleep Mode
The low-power consumption control circuit releases sleep mode. Releasing is caused by the input of a reset
or by an interrupt.
● Return to normal mode by a reset
When sleep mode is released by a reset, the microcontroller is placed in the reset state on release from sleep
mode.
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MB90820B Series
● Return to normal mode by an interrupt
If an interrupt request higher than interrupt level 7 is issued from a peripheral circuit during sleep mode,
sleep mode is released. After release, the CPU handles the interrupt as it would any other interrupt. The
CPU executes processing according to the settings of the I flag of the condition code register (CCR),
interrupt level mask register (ILM), and interrupt control register (ICR). If that interrupt is accepted, the
CPU executes interrupt processing. If the interrupt is not accepted, the CPU resumes execution with the
instruction that follows the instruction in which switching to sleep mode was specified.
Figure 6.5-1 shows the release of sleep mode for an interrupt.
Figure 6.5-1 Release of sleep mode for an interrupt
Interrupt from a peripheral circuit
Enable flag is set
INT occurs
(IL < 7)
NO
Sleep mode is not
released
YES
Execution of the
next instruction
Sleep mode is not
released
YES
I=0
Sleep mode is
released
NO
YES
ILM < IL
Execution of the
next instruction
NO
Interrupt execution
Note :
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to sleep mode was specified. The CPU then proceeds to interrupt
processing.
● Return to normal mode from PLL sleep mode by an external reset
During PLL sleep mode, the main clock and the PLL clock generate clock pulses. Since an external reset
does not initialize the MCS bit in the clock selection register (CKSCR) to "1", PLL clock mode remains
selected (MCS of CKSCR = 0). On return from PLL sleep mode by an external reset, the CPU starts
operation using the PLL clock immediately after PLL sleep mode is released as shown in Figure 6.5-2.
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Figure 6.5-2 Release of PLL sleep mode (by external reset)
RST pin
Sleep mode
Main clock
Oscillating
PLL clock
Oscillating
PLL clock
CPU clock
CPU operation
Inactive
Sleep mode released.
114
Reset sequence
Execution
Reset cleared.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5
MB90820B Series
6.5.2
Time-base Timer Mode
Time-base timer mode causes the microcontroller operation to stop with the exception
of the source oscillation and the time-base timer. All functions other than time-base
timer are deactivated.
■ Switching to Time-base Timer Mode
Writing "0" to the TMDX and STP bits of LPMCR triggers a switch to time-base timer mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
time-base timer mode. If the MCS bit of CKSCR is "1", the microcontroller enters main time-base timer
mode.
Note :
Since the STP bit setting overrides the TMDX bit setting when "0" is written to the TMDX and STP
bits at the same time, the mode switches to stop mode.
● Data retention function
In time-base timer mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
● Operation during an interrupt request
Writing "0" to the TMDX bit of LPMCR during an interrupt request does not trigger switching to time-base
timer mode.
● Status of pins
Selection of whether the external pins retain the state they had immediately before switching to time-base
timer mode or go to high-impedance with switching to this mode can be controlled by the SPL bit of
LPMCR.
■ Release of Time-base Timer Mode
The low-power consumption control circuit releases time-base timer mode. Release is caused by input of a
reset or an interrupt. If time-base timer mode is released by a reset, the microcontroller is placed in the
reset state after its release from time-base timer mode.
● Return to normal mode by a reset
If time-base timer mode is released by a reset, the microcontroller is placed in the reset state after release
from time-base timer mode. The timerbase timer mode is initialized to the main clock mode by a reset.
Figure 6.5-3 shows the operation for return to normal mode from time-base timer mode triggered by an
external reset.
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MB90820B Series
Figure 6.5-3 Release of time-base timer mode (by an external reset)
RST pin
Time-base timer
mode
Main clock
Oscillating
PLL clock
Main clock
CPU clock
CPU operation
Inactive
Reset sequence
Execution
Reset cleared.
Time-base timer mode released.
● Return to normal mode by an interrupt
If an interrupt request higher interrupt than level 7 is issued from a peripheral circuit in time-base timer
mode (when IL2, IL1 and IL0 of the interrupt control register (ICR) are set to a value other than "111B"),
the low-power consumption control circuit releases time-base timer mode. After the release, the CPU
handles the interrupt as it would normal interrupt. The CPU executes processing according to the settings
of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control
register (ICR). If the interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not
accepted, the CPU resumes execution with the instruction that follows the instruction in which switching to
time-base timer mode was specified.
Note :
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to sleep mode was specified. The CPU then proceeds to interrupt
processing.
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6.5
MB90820B Series
6.5.3
Stop Mode
Stop mode causes the source oscillation to stop and deactivates all functions. It
therefore saves the most power saving while data is being retained.
■ Switching to Stop Mode
Writing "1" to the STP bit of LPMCR triggers a switch to stop mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
stop mode. If the MCS bit of CKSCR is "1", the microcontroller enters main stop mode.
● Data retention function
In stop mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
● Operation during an interrupt request
Writing "1" to the STP bit of LPMCR during an interrupt request does not trigger switching to stop mode.
● Pin state setting
Selection of whether the external pins retain the state they had immediately before switching to stop mode
or go to high-impedance with switching to stop mode can be controlled by the SPL bit of LPMCR.
■ Release of Stop Mode
The low-power consumption control circuit releases stop mode. The release is caused by input of a reset or
by an interrupt.
Because the oscillation of the operating clock is halted before return to normal mode from stop mode, the
low-power consumption control circuit puts the microcontroller into the oscillation stabilization wait state,
then releases stop mode.
● Return to normal mode by a reset
When stop mode is released by a reset cause, the microcontroller is placed in the oscillation stabilization
wait and reset state after release from stop mode. The reset sequence proceeds after the oscillation
stabilization wait interval has elapsed.
● Return to normal mode by a interrupt
If an interrupt request higher than interrupt level 7 is issued from a peripheral circuit during stop mode
(when IL2, IL1, and IL0 of the interrupt control register (ICR) are set to a value other than "111B"), the
low-power consumption control circuit releases stop mode. After release, the CPU handles the interrupt as
it would any other interrupts. However, the CPU starts after the main clock oscillation stabilization wait
interval specified by the WS1 and WS0 bits of the clock selection register (CKSCR) has elapsed. The CPU
executes processing according to the settings of the I flag in the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the CPU
executes interrupt processing. If the interrupt is not accepted, the CPU resumes the execution with the
instruction that follows the instruction in which switching to stop mode was specified.
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MB90820B Series
Note :
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to stop mode was specified. The CPU then proceeds to interrupt
processing.
Figure 6.5-4 shows the operation of return to normal mode from stop mode.
Figure 6.5-4 Release of stop mode (by external reset)
RST pin
Stop mode
Main clock
Oscillation stabilization wait time
Oscillating
PLL clock
Oscillation stabilization wait time
Oscillating
CPU clock
Main/PLL clock
CPU operation
Inactive
Stop mode released
118
Reset
sequence
Execution
Reset cleared
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.6
MB90820B Series
6.6
State Change Diagram
Figure 6.6-1 shows the state change diagram of F²MC-16LX operation and gives change
conditions.
■ State Change Diagram
Figure 6.6-1 State change diagram of low-power consumption mode
Power-on
Main clock mode
Source Osc.
stabilization wait
and reset state
[9]
Main clock
reset state
[1]
[4]
[13]
Source clock osc.
stabilization wait
state
[8]
[2]
Main stop
state
PLL stop
state
[16]
[18]
[6]
[11]
[5]
Main run
state
[19]
[14]
[3]
[10]
[7]
Source clock osc.
stabilization wait
state
Main timebase timer
state
[12]
Source Osc.
stabilization wait
and reset state
[15]
[23]
[6]
Main sleep
state
[22]
[20]
PLL run
state
<10>
[21]
[7]
<1>
<3>
PLL sleep
state
<7>
<4>
<5>
PLL clock
reset state
<8>
PLL timebase timer
[17]
Main clock
reset state
PLL clock mode
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6.6
MB90820B Series
■ Low-Power Consumption Mode Operating States
Table 6.6-1 lists the operating states of low-power consumption mode.
Table 6.6-1 Low-power consumption mode operating states
Low-power
consumption
mode
Condition
for
transition
Oscillation
Clock
CPU
Peripheral
Pin
Release
event
Main sleep
MCS = 1
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
PLL sleep
MCS = 0
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
Main/PLL
time-base timer
(SPL = 0)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL
time-base timer
(SPL = 1)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hi-Z
Reset or
interrupt
Main/PLL stop
(SPL = 0)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL stop
(SPL = 1)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hi-Z
Reset or
interrupt
● Clock mode switching and release (excluding standby mode)
Table 6.6-2 lists clock mode switching and release.
Table 6.6-2 Clock mode switching and release
Transition
Conditions
After power-on, transition to
the main run state
[1] Source clock oscillation stabilization wait interval ends. (Timebase timer output)
[2] Reset input has been cleared.
Reset during main run state
[3] External reset, software reset, or watchdog timer reset
Transition from main run
state to PLL run state
[19] MCS = 0 (After PLL clock oscillation stabilization wait interval,
switch to PLL clock) *
Return to main run state from
PLL run state
[20] MCS = 1 (PLL clock deactivated)
Reset during PLL run state
[6] External reset or software reset ([7] After reset, return to PLL run
state)
[13] Watchdog reset ([2] After reset, return to main run state)
*: The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state.
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6.6
MB90820B Series
● Switching to and release of standby mode
Table 6.6-3 lists switching to and release of standby mode.
Table 6.6-3 Switching to and release of standby mode
Transition
Conditions
Transition to main sleep
mode
[21] SLP = 1, MCS = 1 (Transition from main run state)
[2] SLP =1, MCS = 1 (Transition from PLL run state)
Release of main sleep mode
[22] Interrupt input
[4] External reset
Transition to main stop mode
[5] STP =1, MCS = 1 (Transition from main run state)
Transition to PLL stop mode
<10>STP =1, MCS = 0 (Transition from PLL run state)
Release of main stop mode
[7] Interrupt input ([10] indicates return to main run state after
oscillation stabilization wait)
[8] External reset ([9] indicates external reset during oscillation
stabilization wait state)
Release of PLL stop mode
[14] Interrupt input ([15] indicates return to PLL run state after
oscillation stabilization wait)
[16] External reset ([18] indicates external reset during oscillation
stabilization wait state)
Transition to PLL sleep
mode
<1> SLP = 1, MCS = 0 (Transition from PLL run state)
<2> SLP = 1, MCS = 0 (Transition from main run state, switch to PLL
clock after PLL clock oscillation stabilization wait) *
Release of PLL sleep mode
<3> Interrupt input
<4> External reset
Transition to main time-base
timer mode
[6] STP = 1, MCS = 1 (Transition from main run state)
Transition to PLL time-base
timer mode
<5> STP = 1, MCS = 0 (Transition from PLL run state)
Release of main time-base
timer mode
[11] Interrupt input
[12] External reset ([2] After reset, return to main run state)
Release of PLL time-base
timer mode
<7> Interrupt input
<8> External reset ([7] After reset, return to PLL run state)
* The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state.
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6.7
6.7
MB90820B Series
State of Pins in Standby Mode and During Reset
The state of pins in standby mode and during reset is summarized below for each
memory access mode.
■ Software Pull-up Resistor
For pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during "L" level
output.
■ State of Pins in Single-chip Mode
Table 6.7-1 lists the state of pins in single-chip mode.
Table 6.7-1 State of pins in single-chip mode
Standby mode
Pin name
Stop mode
When reset
Sleep
SPL = 0
P00 to P07,
P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50,
P60 to P63,
P70 to P77,
P80 to P87
P10 to P16
P63
The preceding
state is retained*2
The preceding
state is
retained*2
SPL = 1
Input shut
off*3 / output
Hi-Z
output Hi-Z
Input enabled*1
*1 "Input enabled" means that the input function is enabled when corresponding external interrupt pin is enable. Select
either the pull-up or the pull-down option. Alternatively, an external input is required. Pins used as output ports are
the same as other ports.
*2 "The preceding state is retained" means that the state of the pin output existing immediately before switching to this
mode is retained. Note that input is disabled if the preceding state was input.
• "State of the pin output is retained" means that the pin retains the value output from an operating internal
peripheral unit or the value output from the port if the pin is used as a port.
• "Input disabled" means that the input to the pin is not accepted because the internal circuit is inactive, although
operation of the input gate adjacent to the pin is enabled.
*3 When in the input shut off state, an "L" level is passed to the internal circuit. "Output Hi-Z" means that the pin state
is high-impedance because driving of the pin driving transistor is disabled.
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6.8
MB90820B Series
6.8
Usage Notes on Low-Power Consumption Mode
Note the following six items to use low-power consumption mode:
• Switching to standby mode and interrupts
• Release of standby mode by an interrupt
• Setting of standby mode
• Release of stop mode
• Release of time-base timer mode
• Oscillation stabilization wait time
• Points to note when accessing the low-power consumption mode control register
(LPMCR) to switch to standby mode
■ Notes on Standby Mode
● Switching to standby mode and interrupts
During an interrupt request to the CPU from a peripheral function, the CPU ignores the STP and SLP bits
of the low-power consumption mode control register (LPMCR) even though "1" has been written to these
bits. Thus, switching to any standby mode is disabled (even after processing the interrupt is completed,
there is no switch to standby mode). If the interrupt level is higher than 7, this action does not depend on
whether the interrupt request is accepted by the CPU.
However, during execution of interrupt processing by the CPU, if the interrupt request flag bit is cleared
and no other interrupt requests have been issued, switching to standby mode can be done.
● Release of standby mode caused by an interrupt
If an interrupt request higher than interrupt level 7 is issued from a peripheral function during the sleep,
time-base timer, or stop modes, the standby mode is released. This action does not depend on whether the
CPU accepts that interrupt.
After the release of standby mode, normal interrupt processing is performed. The CPU branches to the
interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level
setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM); and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled). If the interrupt is not
accepted, the CPU starts the execution with the instruction that follows the instruction in which switching
to standby mode was specified.
When interrupt processing is executed normally, the CPU first executes the instruction that follows the
instruction in which switching to standby mode was specified. The CPU then proceeds to interrupt
processing. Depending on the condition when switching to standby mode was performed, however, the
CPU may proceed to interrupt processing before executing the next instruction.
If the CPU should not branch to the interrupt processing routine immediately after return to normal mode
from standby mode, action must be taken to disable interrupts before standby mode is set.
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MB90820B Series
● Setting of standby mode
When "1" is written to the STP bit and SLP bit of LPMCR at the same time, switching to standby mode is
performed. If the MCS bit of the clock selection register (CKSCR) is "0", switching to time-base timer
mode is performed; if this bit is "1", switching to stop mode is performed.
■ Release of Stop Mode
To use an external interrupt for releasing stop mode, use an input that has been set as an interrupt input
cause before the system enters stop mode. As an input cause, "H" level, "L" level, rising edge, or falling
edge can be selected.
■ Release of Time-base Timer Mode
When time-base timer mode is released, the microcontroller is placed in the PLL clock oscillation
stabilization wait state. If the PLL clock is not used, change the MCS bit of the clock selection register
(CKSCR) to "1" with the instruction that is to be executed immediately after a reset or on return from an
interrupt.
If an external interrupt is used to release time-base timer mode, the input cause can be selected as "H" level,
"L" level, rising edge, or falling edge.
■ Oscillation Stabilization Wait Interval
● Source clock oscillation stabilization wait interval
Because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization wait interval
is required. A time period selected by the WS1 and WS0 bits of CKSCR is used as the oscillation
stabilization wait interval.
● PLL clock oscillation stabilization wait interval
The CPU may be working with the main clock, and the PLL clock may be stopped. If the microcontroller
will enter a mode in which the CPU and peripheral functions work with the PLL clock, the PLL clock
initially enters the oscillation stabilization wait state. In this state, the CPU still operates using the main
clock.
The PLL clock oscillation stabilization wait interval is fixed at 214/HCLK (HCLK: oscillation clock
frequency).
However, this interval may range from 214/HCLK to 2 x 214/HCLK depending on the status of the timebase timer, if the time-base timer is not cleared before the PLL clock oscillation stabilization wait state is
entered. (For example, return to the PLL run state from time-base timer mode occurs because of an
external reset.)
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■ Points to Note when Accessing the Low-power Consumption Mode Control Register
(LPMCR) to Switch to Standby Mode
● When using assembly language to access the low-power consumption mode control register (LPMCR)
When using the low-power consumption mode control register (LPMCR) to switch to a low-power
consumption mode, use one of the instructions listed in Table 6.3-2.
Always insert the instructions enclosed in the box below immediately after the instruction from Table 6.3-2
for switching to a low-power consumption mode.
MOV LPMCR,#H’xx
NOP
NOP
JMP $+3
MOV A,#H’10
; Instruction from Table 6.3-2 for switching to a low-power consumption mode
; Jump to next instruction
; Next instruction
The operation when recovering from low-power consumption mode is not guaranteed if instructions other
than those shown in the box are used.
● When accessing the low-power consumption control register (LPMCR) from a C program
Use one of the methods listed in (1) to (3) below to set the low-power consumption mode control register
(LPMCR) to switch to standby mode.
(1) Implement the instructions for switching to the standby mode in a function and insert two calls to the
_wait_nop() function immediately after the instruction that switches to standby mode. If it is possible
that an interrupt for recovering from standby mode may occur while the function is executing, use
optimization when compiling and prevent generation of the LINK and ULINK instructions.
Example: (function for switching to watch mode or time-base timer mode)
void enter_watch(){
IO_LPMCR.byte = 0x10:
/* Set the TMDX bit in the LPMCR register to 0 */
_wait_nop();
_wait_nop();
}
(2)
Use _asm statements for the instructions for switching to standby mode and insert two NOP
instructions and a JMP instruction after the instruction for switching to standby mode.
Example: (switching to sleep mode)
CM44-10147-2E
_asm("
MOV I:_IO_LPMCR, #H’58"); /* Set the SLP bit in the LPMCR register to 1 */
_asm("
NOP");
_asm("
NOP");
_asm("
JMP $+3");
/* Jump to next instruction */
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.8
MB90820B Series
(3) Enclose the instructions for switching to standby mode between "#pragma asm" and "#pragma
endasm" and insert two NOP instructions and a JMP instruction after the instruction for switching to
standby mode.
Example: (switching to stop mode)
#pragma asm
MOV I:_IO_LPMCR, #H’98
/* Set the STP bit in the LPMCR register to 1 */
NOP
NOP
JMP $+3
/* Jump to next instruction */
#pragma endasm
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CM44-10147-2E
CHAPTER 7
INTERRUPT
This chapter explains the function and operation of the
interrupt and extended intelligent I/O service (EI2OS) in
the MB90820B series.
CM44-10147-2E
7.1
Interrupt
7.2
Interrupt Causes and Interrupt Vectors
7.3
Interrupt Control Registers and Peripheral Functions
7.4
Hardware Interrupt
7.5
Software Interrupt
7.6
Interrupt of Extended Intelligent I/O Service (EI2OS)
7.7
Exception Processing Interrupt
7.8
Stack Operations for Interrupt Processing
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CHAPTER 7 INTERRUPT
7.1
7.1
MB90820B Series
Interrupt
This chapter explains the function and operatin of the interrupt and extended intelligent
I/O service (EI2OS) in the MB90820B series.
• Hardware interrupt
• Software interrupt
• Interrupt from extended intelligent I/O service (EI2OS)
• Exception processing
■ Interrupt Types and Functions
● Hardware interrupt
A hardware interrupt transfers control to a user-defined interrupt processing program in response to an
interrupt request from a peripheral function.
● Software interrupt
A software interrupt transfers control to a user-defined interrupt processing program triggered by the
execution of a dedicated software interrupt instruction (such as the INT instruction).
● Interrupt from extended intelligent I/O service (EI2OS)
The EI2OS function automatically transfers data between a peripheral function and memory. Data transfer,
which has ordinarily been executed by an interrupt processing program, can be handled like a direct
memory access (DMA). When the specified number of data transfers has been terminated, the interrupt
processing program is automatically executed.
An instruction from EI2OS is a type of hardware interrupt.
● Exception processing
Exception processing is basically the same as an interrupt. When an exception event (execution of an
undefined instruction) is detected on the instruction boundary, ordinary processing is interrupted and
exception processing is performed. This is equivalent to software interrupt instruction INT10.
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CHAPTER 7 INTERRUPT
7.1
MB90820B Series
■ Interrupt Operation
Figure 6.1-1 shows the activation and return processing for the four types of interrupt functions.
Figure 7.1-1 Overall flow of interrupt operation
Main program
Is there
a valid hardware
interrupt
request?
Interrupt activation/return
processing
String type*
instruction being
executed
EI2OS?
Fetch the next instruction and decode
INT instruction?
EI2OS
EI²OS processing
Software
interrupt/
exception
processing
Save the dedicated
register on the system
stack
Disable acceptance of
hardware interrupts
(I = 0)
Hardware
interrupt
Specified
count terminated?
Alternatively, is there
an end request from the
peripheral
function?
Save the dedicated
register on the system
stack
Update the CPU interrupt processing level
(ILM)
RETI instruction?
Interrupt
return
processing
Return the dedicated
register from the system
stack, call the interrupt
routine, and return to
the previous routine
Execute ordinary
instruction
Read the interrupt
vector, update PC and
PCB, and branch to
the interrupt routine
Repetition
of string type* instruction completed?
Move the pointer to the
next instruction by PC
update
* : When a string type instruction is being executed, the interrupt is evaluated in each step.
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CHAPTER 7 INTERRUPT
7.2
7.2
MB90820B Series
Interrupt Causes and Interrupt Vectors
The F2MC-16LX has functions for handling 256 types of interrupt causes. The 256
interrupt vector tables are allocated to the memory at the highest addresses. These
interrupt vectors are shared by all interrupts.
Software interrupt can use all these interrupt vectors (INT0 to INT255). Software
interrupt shares same interrupt vectors with the hardware interrupt and exception
processing interrupt. Hardware interrupt uses a fixed interrupt vector and interrupt
control register (ICR) for each peripheral function.
■ Interrupt Vectors
● Interrupt vectors
Interrupt vector tables referred during interrupt processing are allocated to the highest addresses in the
memory area (FFFC00H to FFFFFFH). Interrupt vectors share the same area with EI2OS, exception
processing, hardware, and software interrupt.
Table 6.2-1 shows the assignment of interrupt numbers and interrupt vectors.
Table 7.2-1 Interrupt vectors
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
Interrupt
Mode data
address H
no.
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Not used
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception
processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
Hardware interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
Hardware interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
Hardware interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
Hardware interrupt
Reference:
Unused interrupt vectors should be set as the exception processing address.
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CM44-10147-2E
CHAPTER 7 INTERRUPT
7.2
MB90820B Series
■ Interrupt Causes and Interrupt Vectors/Interrupt Control Registers
Table 6.2-2 shows the relationship among interrupt causes (excluding software interrupt), interrupt vectors,
and interrupt control registers.
Table 7.2-2 Interrupt causes, interrupt vectors, and interrupt control registers
Interrupt cause
Reset
INT9 instruction
Exception processing
A/D converter conversion termination
Output compare channel 0 match
End of measurement by PWC timer 0 /
PWC timer 0 overflow
16-bit PPG timer 0
Output compare channel 1 match
16-bit PPG timer 1
Output compare channel 2 match
16-bit reload timer 1 underflow
Output compare channel 3 match
DTP/ext. interrupt channels 0/1 detection
DTTI
Output compare channel 4 match
DTP/ext. interrupt channels 2/3 detection
Output compare channel 5 match
End of measurement by PWC timer 1 /
PWC timer 1 overflow
DTP/ext. interrupt channel 4 detection
DTP/ext. interrupt channel 5 detection
DTP/ext. interrupt channel 6 detection
DTP/ext. interrupt channel 7 detection
Waveform generator 16-bit timer 0/1/2
underflow
16-bit reload timer 0 underflow
16-bit free-run timer 0 detect
16-bit PPG timer 2
Input capture channels 0/1
16-bit free-run timer compare clear
Input capture channels 2/3
Time-base timer
UART1 receive completed
UART1 send start
UART0 receive completed
UART0 send start
Flash memory status
Delayed interrupt generator module
O:
X:
EI2OS
support
Interrupt vector
Number
Address
ICR
Address
-
-
ICR00
0000B0H*1
ICR01
0000B1H*1
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*1
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
X
X
X
O
O
#08
#09
#10
#11
#12
08H
09H
0AH
0BH
0CH
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
O
#13
0DH
FFFFC8H
O
O
O
O
O
O
O
∆
O
O
O
#14
#15
#16
#17
#18
#19
0EH
0FH
10H
11H
12H
13H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
#20
14H
FFFFACH
#21
#22
#23
15H
16H
17H
FFFFA8H
FFFFA4H
FFFFA0H
O
#24
18H
FFFF9CH
O
O
O
O
#25
#26
#27
#28
19H
1AH
1BH
1CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
∆
#29
1DH
FFFF88H
O
∆
O
O
∆
O
∆
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
∆
∆
∆
∆
Interrupt control
register
Priority
*2
High
Low
Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
Cannot be used.
: Can be used and support the EI2OS stop request.
∆: Usable when an interrupt cause that shares the ICR is not used.
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CHAPTER 7 INTERRUPT
7.2
MB90820B Series
*1: - For peripheral functions that share the ICR register, the interrupt level will be the same.
- If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with
another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported,
both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is
recommended to mask either of the interrupt requests during the use of EI2OS.
- EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is
masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of
EI2OS.
*2: This priority is applied when interrupts of the same level occur simultaneously.
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
7.3
Interrupt Control Registers and Peripheral Functions
Interrupt control registers (ICR00 to ICR15) are located inside the interrupt controller.
The interrupt control registers correspond to all peripheral functions that have the
interrupt function. These registers control interrupts and the extended intelligent I/O
service (EI2OS).
■ Interrupt Control Registers
Table 6.3-1 lists the interrupt control registers and corresponding peripheral functions.
Table 7.3-1 Interrupt control registers
Address
Register
Abbreviation
Corresponding peripheral function
0000B0H Interrupt control register 00
ICR00
A/D converter conversion termination, Output compare
channel 0 match
0000B1H Interrupt control register 01
ICR01
End of measurement by PWC timer 0 /PWC timer 0
overflow
0000B2H Interrupt control register 02
ICR02
Output compare channel 1 match, 16-bit PPG timer 1
0000B3H Interrupt control register 03
ICR03
Output compare channel 2 match, 16-bit reload timer 1
underflow
0000B4H Interrupt control register 04
ICR04
Output compare channel 3 match, DTP/ext. interrupt
channels 0/1 detection, DTTI
0000B5H Interrupt control register 05
ICR05
Output compare channel 4 match, DTP/ext. interrupt
channels 2/3 detection
0000B6H Interrupt control register 06
ICR06
Output compare channel 5 match, End of measurement by
PWC timer 1 /PWC timer 1 overflow
0000B7H Interrupt control register 07
ICR07
DTP/ext. interrupt channels 4 detection, DTP/ext. interrupt
channels 5 detection
0000B8H Interrupt control register 08
ICR08
DTP/ext. interrupt channels 6 detection, DTP/ext. interrupt
channels 7 detection
0000B9H Interrupt control register 09
ICR09
Waveform generator 16-bit reload timer 0/1/2 underflow,
16-bit reload timer 0 underflow
0000BAH Interrupt control register 10
ICR10
16-bit free-run timer zero detect, 16-bit PPG timer 2
0000BBH Interrupt control register 11
ICR11
Input capture channels 0/1, 16-bit free-run timer compare
clear
0000BCH Interrupt control register 12
ICR12
Input capture channels 2/3, Time-base timer
0000BDH Interrupt control register 13
ICR13
UART1 receive, UART1 send
0000BEH Interrupt control register 14
ICR14
UART0 receive, UART0 send
0000BFH Interrupt control register 15
ICR15
Flash memory status, Delayed interrupt generator module
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
■ Interrupt Control Register Functions
All interrupt control registers (ICR) do the following:
• Set the interrupt level of the corresponding peripheral function
• Select ordinary interrupt or the extended intelligent I/O service as interrupt of the corresponding
peripheral function
• Select an extended intelligent I/O service (EI2OS) channel
• Display the status of the extended intelligent I/O service (EI2OS)
Some of the functions for the interrupt control registers (ICR) differ during writing and reading, as shown
in Figure 7.3-1 and Figure 7.3-2 .
Note:
Do not use a read-modify-write instruction to access the interrupt control registers (ICR), since
operation will not be correct.
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CM44-10147-2E
CHAPTER 7 INTERRUPT
7.3
MB90820B Series
7.3.1
Interrupt Control Registers (ICR00 to ICR15)
Interrupt control registers correspond to all peripheral functions that have the interrupt
function. The interrupt control registers control the processing when an interrupt
request occurs. The functions of these registers partially differ at writing and reading.
■ Interrupt Control Registers (ICR00 to ICR15)
Figure 7.3-1 Interrupt control registers (ICR00 to ICR15) during writing
Writing
Address
0000B0H
to
0000BFH
bit7
bit6
bit5
bit4
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
W
W
W
R/W
R/W
R/W
R/W
W
bit3
bit2
bit1
bit0
Initial value
00000111B
bit 2 bit 1 bit 0
IL2
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level 7 (no interrupt)
bit 3
EI2OS enable bit
ISE
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
bit 7 bit 6
bit 5 bit 4
EI2OS channel selection bit
ICS3 ICS2 ICS1 ICS0
R/W:
W:
CM44-10147-2E
Readable/Writable
Write only
: Initial value
Channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
000138H
000140H
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
Figure 7.3-2 Interrupt control registers (ICR00 to ICR15) during reading
Reading
bit6
bit5
bit4
-
-
S1
S0
ISE
IL2
IL1
IL0
-
-
R
R
R/W
R/W
R/W
R/W
bit7
Address
0000B0H
to
0000BFH
bit3
bit2
bit1
bit0
Initial value
XX000111B
bit 2 bit 1 bit 0
IL2
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level 7 (no interrupt)
bit 3
EI2OS enable bit
ISE
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
bit 5 bit 4
S0
EI2OS status bit
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
S1
R/W: Readable/Writable
R: Read only
- : Not used
X:
Undefined
: Initial value
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
7.3.2
Interrupt Control Register Functions
The interrupt control registers (ICR00 to ICR15) consist of the following four functional
bits:
• Interrupt level setting bits (IL2 to IL0)
• Extended intelligent I/O service (EI2OS) enable bit (ISE)
• Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
• Extended intelligent I/O service (EI2OS) status bits (S1, S0)
■ Bit Configuration of Interrupt Control Registers (ICR)
Figure 7.3-3 shows the configuration of the interrupt control register (ICR) bits.
Figure 7.3-3 Configuration of interrupt control registers (ICR)
Writing to interrupt control register (ICR)
Address
bit7
bit6
bit5
bit4
ICS3 ICS2
ICS1 ICS0
0000B0H
to
W
W
W
W
0000BFH
Reading of interrupt control register (ICR)
Address
0000B0H
to
0000BFH
R: Read only
W: Write only
- : Undefined
bit7
bit6
−
−
−
−
bit5
S1
R
bit4
S0
R
bit3
ISE
W
bit2
IL2
W
bit1
IL1
W
bit0
IL0
W
Initial value
00000111B
bit3
ISE
R
bit2
IL2
R
bit1
IL1
R
bit0
IL0
R
Initial value
XX000111B
Reference:
• The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI2OS) has been
activated. To activate EI2OS, set the ISE bit to "1". To not activate EI2OS, set the ISE bit to 0.
When EI2OS is not activated, setting ICS3 to ICS0 is optional.
• ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading.
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
■ Interrupt Control Register Functions
● Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt level of the corresponding peripheral function. These bits are initialized to level
7 (no interrupt) by a reset.
Table 7.3-2 shows the correspondence between the interrupt level setting bits and interrupt levels.
Table 7.3-2 Correspondence between the interrupt level setting bits and interrupt levels
IL2
IL1
IL0
Interrupt level
0
0
0
0 (highest priority)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (lowest priority)
1
1
1
7 (no interrupt)
● Extended intelligent I/O service (EI2OS) enable bit (ISE)
If this bit is "1" when an interrupt request is generated, EI2OS is activated. If this bit is "0" when an
interrupt request is generated, the interrupt sequence is activated. When the EI2OS termination condition is
met (when the S1 and S0 bits are not "00B"), the ISE bit is cleared. If the corresponding peripheral
function does not have the EI2OS function, the ISE bit must be set to "0" by software. The ISE bit is
initialized to "0" by a reset.
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CHAPTER 7 INTERRUPT
7.3
MB90820B Series
● Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
These write-only bits specify the EI2OS channel. The EI2OS descriptor address is determined based on the
value set here. The ICS bit is initialized to "0000B" by a reset.
Table 7.3-3 shows the correspondence between the EI2OS channel selection bits and descriptor addresses.
Table 7.3-3 Correspondence between the EI2OS channel selection bits and descriptor
addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
● Extended intelligent I/O service (EI2OS) status bits (S1 and S0)
These are read-only bits. When this value is checked at EI2OS termination, the operating status and
termination status can be distinguished. These bits are initialized to "00B" by a reset.
Table 7.3-4 shows the relationship between the S0 and S1 bits and the EI2OS status.
Table 7.3-4 Relationship between EI2OS status bits and the EI2OS status
CM44-10147-2E
S1
S0
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
EI2OS status
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CHAPTER 7 INTERRUPT
7.4
7.4
MB90820B Series
Hardware Interrupt
The hardware interrupt function temporarily interrupts the program being executed by
the CPU and transfers control to a user-defined interrupt processing program in
response to an interrupt signal from a peripheral function.
The extended intelligent I/O service (EI2OS) and external interrupt are executed as a
type of hardware interrupt.
■ Hardware Interrupt
● Hardware interrupt function
The hardware interrupt function compares the interrupt level of the interrupt request signal output by a
peripheral function with the interrupt level mask register (ILM) in the CPU processor status (PS). The
function then refers the contents of the I flag in the processor status (PS) through the hardware and decides
if the interrupt can be accepted.
When the hardware interrupt is accepted, the CPU internal registers are automatically saved on the system
stack. The currently requested interrupt level is stored in the interrupt level mask register (ILM), and the
function branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be activated.
● Extended intelligent I/O service (EI2OS)
EI2OS is an automatic transfer function between memory and I/O. When the specified transfer count has
been completed, a hardware interrupt is activated. Multiple EI2OS activation does not occur. During
EI2OS processing, all other interrupt requests and EI2OS requests are held.
● External interrupt
An external interrupt (including wake-up interrupt) is accepted from a peripheral function (interrupt request
detection circuit) as a hardware interrupt.
● Interrupt vector
Interrupt vector tables referred during interrupt processing are allocated to memory at FFFC00H to
FFFFFFH. These tables are shared by software interrupts.
See Section "7.2 Interrupt Causes and Interrupt Vectors", for more information about the allocation of
interrupt numbers and interrupt vectors.
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CHAPTER 7 INTERRUPT
7.4
MB90820B Series
■ Hardware Interrupt Structure
Table 6.4-1 lists four mechanisms used for hardware interrupt. These four mechanisms must be included in
the program before hardware interrupt can be used.
Table 7.4-1 Mechanisms used for hardware interrupt
Hardware interrupt
mechanism
Function
Peripheral function
Interrupt enable bit, interrupt
request bit
Controls interrupt requests from a peripheral
function
Interrupt controller
Interrupt control register (ICR)
Sets the interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies the interrupt enable status
Interrupt level mask register
(ILM)
Compares the request interrupt level and
current interrupt level
Microcode
Executes the interrupt processing routine
Interrupt vector table
Stores the branch destination address for
interrupt processing
CPU
FFFC00H to FFFFFFH
in memory
■ Hardware Interrupt Suppression
Acceptance of hardware interrupt requests is suppressed under the following conditions.
● Hardware interrupt suppression during writing to the peripheral function control register area
When data is being written to the peripheral function control register area, hardware interrupt requests are
not accepted. This prevents the CPU from making operational mistakes. The mistakes may be caused if an
interrupt request is generated during data is written to the interrupt control registers for a resource. The
peripheral function control register area is not the I/O addressing area at 000000H to 0000FFH, but the area
allocated to the peripheral function control register and data register.
Figure 6.4-1 shows hardware interrupt operation during writing to built-in resource area.
Figure 7.4-1 Hardware interrupt request while writing to the peripheral function
control register area
Instruction that writes to the peripheral function control register area
MOV A, #08
MOV io, A
An interrupt request
is generated here
MOV A, 2000H
Does not branch
to the interrupt
Interrupt processing
Branches to
the interrupt
● Hardware interrupt suppression by interrupt suppression instruction
The ten types of hardware interrupt suppression instructions listed in Table 6.4-2 ignore interrupt requests
without detecting whether a hardware interrupt request exists.
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Table 7.4-2 Hardware interrupt suppression instruction
Prefix code
Instructions that do not
accept interrupt and hold
requests
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/hold suppression
instructions (instructions that delay
the effect of the prefix code)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
Even if a valid hardware interrupt request is generated during execution for one of these instructions, the
interrupt is not processed until the first time an instruction of a different type is executed.
● Hardware interrupt suppression during execution of software interrupt
When a software interrupt is activated, the I flag is cleared to "0". In this state, other interrupt requests
cannot be accepted.
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CHAPTER 7 INTERRUPT
7.4
MB90820B Series
7.4.1
Operation of Hardware Interrupt
This section explains hardware interrupt operation from generation of a hardware
interrupt request to the completion of interrupt processing.
■ Hardware Interrupt Activation
● Peripheral function operation (generation of an interrupt request)
A peripheral function that has a hardware interrupt request function also has an interrupt request flag that
indicates the presence of interrupt requests and an interrupt enable flag that determines whether CPU
interrupt requests are enabled or disabled. The interrupt request flag is set when an event specific to the
peripheral function occurs.
● Interrupt controller operation (interrupt request control)
The interrupt controller compares the interrupt levels (IL) of interrupt requests received at the same time.
The interrupt controller selects the request with the highest level (with the smallest IL value) and posts it to
the CPU. When multiple requests have the same interrupt level, the request with the smallest interrupt
number has the highest priority.
● CPU operation (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 to IL0) and the interrupt level mask register
(ILM). If IL < ILM and interrupts are enabled (PS: CCR: I = 1), the CPU activates the interrupt
processing microcode after the instruction currently being executed terminates.
At the beginning of the interrupt processing microcode, the CPU referes the ISE bit. If ISE = 0, the CPU
continues the execution of interrupt processing. (If ISE = 1, EI2OS is activated.)
Interrupt processing saves the contents of the dedicated registers (12 bytes including A, DPR, ADB, DTB,
PCB, PC, and PS) on the system stack (the system stack space indicated by the SSB and SSP).
The CPU then loads data into the interrupt vector program counters (PCB and PC), updates the ILM, and
sets the stack flag (S) (sets CCR: S = 1 and activates the system stack).
■ Returning from a Hardware Interrupt
In an interrupt processing program, when the interrupt request flag of the peripheral function that generates
the interrupt cause is cleared and the RETI instruction is executed, 12-byte data saved on the system stack
is restored to the dedicated registers and the processing that was being executed before branching for the
interrupt is resumed.
When the interrupt request flag is cleared, interrupt requests output by the peripheral function to the
interrupt controller are automatically canceled.
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■ Hardware Interrupt Operation
Figure 7.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion
of interrupt processing.
Figure 7.4-2 Hardware interrupt operation
Internal bus
Microcode
Check
Comparator
X
Other peripheral
functions
Peripheral function that generated
the interrupt request
Enable FF
Level
comparator
Interrupt
level IL
Factor FF
Interrupt controller
IL:
PS:
I:
ILM:
IR:
FF:
Interrupt level setting bit in the interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
(1) An interrupt request is generated within the peripheral function.
(2) The interrupt enable bit of the peripheral function is referred. If the interrupt is enabled, the interrupt
request is output from the peripheral function to the interrupt controller.
(3) The interrupt controller that receives the interrupt request determines the priority of simultaneous
interrupt requests, then transfers the interrupt level (IL) that matches the corresponding interrupt
request to the CPU.
(4) The CPU compares the interrupt level (IL) requested by the interrupt controller with the interrupt level
mask register (ILM).
(5) If the comparison indicates a higher priority than the current interrupt processing level, the CPU
checks the contents of the I flag in the condition code register (CCR).
(6) If in the check in (5) the I flag is interrupt enabled (I = 1), the CPU waits until the execution of the
instruction currently being executed terminates. At termination, the CPU sets the requested level (IL)
in the ILM.
(7) Registers are saved, and processing branches to the interrupt processing routine.
(8) The interrupt cause that was generated in (1) is cleared by software in the interrupt processing routine.
Execution of the RETI instruction terminates the interrupt processing.
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CHAPTER 7 INTERRUPT
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MB90820B Series
7.4.2
Processing for Interrupt Operation
When an interrupt request is generated by the peripheral function, the interrupt
controller transmits the interrupt level to the CPU. If the CPU is able to accept interrupt,
the interrupt controller temporarily interrupts the instruction currently being executed.
The interrupt controller then executes the interrupt processing routine or activates the
extended intelligent I/O service (EI2OS).
If a software interrupt is generated by the INT instruction, the interrupt processing
routine is executed regardless of the CPU status. In this case, hardware interrupt is not
allowed.
■ Processing for Interrupt Operation
Figure 7.4-3 shows the flow of processing for interrupt operation.
Figure 7.4-3 Flow of interrupt processing
START
Main program
String type*
instruction in
progress
I&IF&IF=1
AND
LM>IL
YES
Interrupt activation/return processing
NO
YES
ISE = 1
Fetch the next instruction
and decode
EI2OS
NO
INT
instruction?
YES
NO
EI2OS processing
Software interrupt/exception
processing
Save the dedicated registers
to the system stack
I <- 0 (Disable hardware
interrupts)
Hardware
interrupt
YES
Specified
count terminated? Alternatively, is there a termination
request from the peripheral
function?
Save the dedicated
registers to the system stack
NO
ILM <- IL (Transfer the
interrupt level of the accepted
interrupt request to the ILM)
RETI
instruction?
YES
NO
Execute ordinary instruction
(including interrupt processing)
NO
Return
processing
Return the dedicated
registers from the system
stack, call the interrupt
routine, and return to the
previous routine
S <- 1 (Activates the
system stack)
PCB, PC <- interrupt
vector (Branch to the
interrupt processing routine)
Repetition
of string type* instruction
completed?
YES
Move the pointer to the next
instruction by PC update
*:
I:
IF:
IE:
ILM:
ISE:
IL:
CM44-10147-2E
When a string type instruction is being executed, the interrupt is evaluated in each step.
Interrupt enable flag of the condition code register (CCR)
S:
Stack flag of the condition code register (CCR)
Interrupt request flag of the peripheral function
PCB: Program bank register
Interrupt enable flag of the peripheral function
PC: Program counter
Interrupt level mask register (in the PS)
EI²OS enable flag of the interrupt control register (ICR)
Interrupt level setting bit of the interrupt control register (ICR)
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7.4.3
MB90820B Series
Procedure for Using Hardware Interrupt
Before hardware interrupt can be used, the system stack area, peripheral function, and
interrupt control register (ICR) must be set.
■ Procedure for Using Hardware Interrupt
Figure 7.4-4 shows an example of the procedure for using hardware interrupt.
Figure 7.4-4 Procedure for using hardware interrupt
Start
(1)
(2)
(3)
Set the system stack area
Initialize the interrupt of
the peripheral function
Set the ICR in the interrupt
controller
Interrupt processing program
Stack processing branches to
the interrupt vector
(8) Processing for interrupt to the
peripheral function (execute the
interrupt processing routine)
(7)
(4)
(5)
Set operation start for the
peripheral function. Set the
interrupt enable bit to enable
Hardware
processing
Set the ILM and I in the PS
(9)
(10)
Clear the interrupt request
Interrupt return instruction
(RETI)
Main program
(6)
Interrupt request
generated
Main program
(1) Set the system stack area.
(2) Initialize a peripheral function that can generate interrupt requests.
(3) Set the interrupt control register (ICR) in the interrupt controller.
(4) Set the peripheral function to the operation start status and set the interrupt enable bit to enable.
(5) Set the interrupt level mask register (ILM) and interrupt enable flag (I) to interrupt acceptable.
(6) An interrupt generated in the peripheral function causes a hardware interrupt request.
(7) The interrupt processing hardware saves the registers and branches to the interrupt processing
program.
(8) The interrupt processing program processes the peripheral function in response to the generated
interrupt.
(9) Clear the interrupt request from peripheral function.
(10) Execute the interrupt return instruction and return to the program before branching.
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MB90820B Series
7.4.4
Multiple Interrupts
Multiple hardware interrupts can be implemented by setting different interrupt levels in
the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in
response to multiple interrupt requests from peripheral functions. Use of multiple
interrupts, however, is not possible with the extended intelligent I/O service.
■ Multiple Interrupts
● Operation of multiple interrupts
During execution of an interrupt processing routine, if an interrupt request with a higher-priority interrupt
level is generated, the current interrupt processing is interrupted and the interrupt request with the higherpriority interrupt level is accepted. When the interrupt request with the higher-priority interrupt level
terminates, the CPU returns to the previous interrupt processing.
0 to 7 can be set as the interrupt level (IL). If level 7 is set, the CPU does not accept interrupt requests.
During execution of interrupt processing, if an interrupt request with the same or lower-priority interrupt
level is generated, the new interrupt request is held until the current interrupt returns unless the I flag in the
code condition register (CCR) or ILM is changed.
Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag
in the condition code register (CCR) in the interrupt processing routine to interrupts not allowed (CCR: I =
0) or the interrupt level mask register (ILM) to interrupts not allowed (ILM = 000B).
Note :
The extended intelligent I/O service (EI2OS) cannot be used for the activation of multiple interrupts.
During processing of the extended intelligent I/O service (EI2OS), all other interrupt requests and
extended intelligent I/O service requests are held.
● Example of multiple interrupts
This example of multiple interrupt processing assumes that a timer interrupt is given a higher priority than
an A/D converter interrupt. In this example, the A/D converter interrupt level is set to 2, and the timer
interrupt level is set to 1. If a timer interrupt is generated during processing of the A/D converter interrupt,
the processing shown in Figure 7.4-5 is performed.
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Figure 7.4-5 Example of multiple interrupts
Main program
A/D interrupt processing
Interrupt level 2
(ILM = 010)
Interrupt level 1
(ILM = 001)
Peripheral initialization
A/D interrupt generated
Interrupted
Timer interrupt processing
Timer interrupt
generated
Timer interrupt processing
Restart
Main processing restarts
A/D interrupt
processing
Timer interrupt return
A/D interrupt return
148
1)
A/D interrupt generated
When the A/D converter interrupt processing starts, the interrupt level mask register (ILM)
automatically has the same value (2 in the example) as the A/D converter interrupt level (ICR: IL2 to
IL0). If a level-1 or level-0 interrupt request is generated, this interrupt processing has priority.
2)
Interrupt processing terminated
When the interrupt processing terminates and the return instruction (RETI) is executed, the values of
the dedicated registers (A, DPR, ADB, DTB, PCB, PC, and PS) are returned from the stack, and the
interrupt level mask register (ILM) has the value that it had before the interrupt.
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CHAPTER 7 INTERRUPT
7.4
MB90820B Series
7.4.5
Hardware Interrupt Processing Time
From the generation of a hardware interrupt request to the execution of an interrupt
processing routine, the time for the instruction currently being executed to terminate
and the time required to handle an interrupt are necessary.
■ Hardware Interrupt Processing Time
From the generation of a hardware interrupt request to the acceptance of the interrupt and to the execution
of an interrupt processing routine, the time to wait for sampling of an interrupt request and the time
required to handle an interrupt (time to prepare for interrupt processing) are necessary. Figure 7.4-6 shows
the interrupt processing time.
Figure 7.4-6 Hardware interrupt processing time
CPU operation
Ordinary instruction
execution
Interrupt handling
Interrupt wait time
Interrupt request
sampling wait time
Interrupt handling time
(θ machine cycle) (*)
Interrupt processing
routine
Interrupt request generation
: The final instruction cycle samples the interrupt request here.
: One machine cycle corresponds to one machine clock (φ).
● Interrupt request sampling wait time
The interrupt request sampling wait time is the time from the generation of interrupt request and to the
termination of the instruction currently being executed.
Whether an interrupt request has been generated is determined by sampling the instruction for an interrupt
request in the final cycle of the instruction. Consequently, the CPU cannot identify an interrupt request
during execution of each instruction creating a delay time.
The interrupt request sampling wait time is the maximum when an interrupt request is generated as soon as
the POPW RW0, ... RW7 instructions (45 machine cycles), which takes the longest to execute, starts.
● Interrupt handling time (φ machine cycle)
The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it receives an
interrupt request. The required interrupt time for this processing is φ machine cycles. The interrupt
handling time is calculated with the following formula:
When an interrupt is activated: θ = 24 + 6 + Z machine cycles
When control is returned from an interrupt: θ = 11 + 6 + Z machine cycles (RETI instruction)
The interrupt handling time is different for each address pointed to by the stack pointer.
Table 7.4-3 shows the interpolation values (Z) for the interrupt handling time.
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Table 7.4-3 Interpolation values (Z) for the interrupt handling time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
Reference:
One machine cycle corresponds to one clock cycle of the machine clock (φ).
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CHAPTER 7 INTERRUPT
7.5
MB90820B Series
7.5
Software Interrupt
When the software interrupt instruction (INT instruction) is executed, the software
interrupt function transfers control from the program being executed by the CPU to the
user-defined interrupt processing program. Hardware interrupt is disabled during
execution of a software interrupt.
■ Software Interrupt Activation
● Software interrupt activation
The INT instruction is used to activate a software interrupt. There is no interrupt request flag or enable flag
for software interrupt requests. When the INT instruction is executed, an interrupt request is always
generated.
● Hardware interrupt suppression
Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) is not
updated. During the execution of the INT instruction, the I flag of the condition code register (CCR) is set
to "0", and hardware interrupts are masked.
To enable hardware interrupts during software interrupt processing, set the I flag to "1" in the software
interrupt processing routine.
● Software interrupt operation
When the CPU fetches the INT instruction, the software interrupt processing microcode is activated. This
microcode saves the internal CPU registers on the system stack, masks hardware interrupts (CCR: I = 0),
and branches to the corresponding interrupt vector.
■ Returning from a Software Interrupt
In the interrupt processing program, when the interrupt return instruction (RETI instruction) is executed,
the 12-byte data saved to the system stack is restored to the dedicated registers and the processing that was
being executed before branching for the interrupt is resumed.
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■ Software Interrupt Operation
Figure 6.5-1 shows software interrupt operation from the generation of a software interrupt to the
completion of interrupt processing.
Figure 7.5-1 Software interrupt operation
(1)
PS
Register file
(2)
Microcode
I
S
B unit
IR
Queue
F2 MC-16LX CPU
Fetch
(3)
Save
F2MC-16LX bus
Instruction bus
RAM
PS: Processor status
I:
Interrupt enable flag
IR:
Instruction register
B unit: Bus interface unit
(1) A software interrupt instruction is executed.
(2) The dedicated registers are saved according to the microcode that corresponds to the software interrupt
instruction, and other necessary processing is performed. Branch processing is then executed.
(3) The RETI instruction in the user interrupt processing routine terminates the interrupt processing.
Note :
When the program bank register (PCB) is FFH, the vector area of the CALLV instruction overlaps the
INT #vct8 instruction table. When creating the software, be careful of the duplicated address of the
CALLV instruction and INT #vct8 instruction.
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CHAPTER 7 INTERRUPT
7.6
MB90820B Series
7.6
Interrupt of Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) automatically transfers data between a
peripheral function (I/O) and memory. When the data transfer terminates, a hardware
interrupt is generated.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service is a type of hardware interrupt. It automatically transfers data between
a peripheral function (I/O) and a memory. Traditionally, data transfer between a peripheral function (I/O)
and a memory has been performed by the interrupt processing program. EI2OS performs this data transfer
in the same way as direct memory access (DMA). At termination, EI2OS sets the termination condition
and automatically branches to the interrupt processing routine. The user creates programs only for EI2OS
activation and termination. Data transfer programs in between are not required.
● Advantages of extended intelligent I/O service (EI2OS)
Compared to data transfer performed by the interrupt processing routine, EI2OS has the following
advantages.
• Coding a data transfer program is not necessary, reducing program size.
• Because data transfer can be stopped depending on the peripheral function (I/O) status, unnecessary data
transfer can be eliminated.
• Update or no update can be selected for the buffer address.
• Update or no update can be selected for the I/O register address.
● Extended intelligent I/O service (EI2OS) termination interrupt
When data transfer by EI2OS terminates, a termination condition is set in the S1 and S0 bits in the interrupt
control register (ICR). Processing then automatically branches to the interrupt processing routine.
The EI2OS termination factor can be determined by checking the EI2OS status (ICR: S1 and S0) with the
interrupt processing program.
Interrupt numbers and interrupt vectors are permanently set for each peripheral. See Section "7.2 Interrupt
Causes and Interrupt Vectors", in "CHAPTER 7 INTERRUPT" for more information.
● Interrupt control register (ICR)
This register, which is located in the interrupt controller, activates EI2OS, specifies the EI2OS channel, and
displays the EI2OS termination status.
● Extended intelligent I/O service (EI2OS) descriptor (ISD)
This descriptor, which is located in internal RAM at 000100H to 00017FH, is an eight-byte data that retains
the transfer mode, I/O address, transfer count, and buffer address. The descriptor handles 16 channels. The
channel is specified by the interrupt control register (ICR).
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Note:
When the extended intelligent I/O service (EI2OS) is operating, execution of the CPU program stops.
■ Operation of the Extended Intelligent I/O Service (EI2OS)
Figure 6.6-1 shows EI2OS operation.
Figure 7.6-1 Extended intelligent I/O service (EI2OS) operation
Memory space
2
F MC-16LX
CPU
Specified
by IOA
I/O register
••• ••• ••• ••• •••
Peripheral
function (I/O)
(5)
Interrupt request (1)
I/O register
(3)
ISD
(3)
Specified
by ICS
(2)
Interrupt control register (ICR)
Interrupt controller
Specified by BAP
(4)
Buffer
Indicated
by
DCT
ISD: EI2OS descriptor
IOA: I/O address pointer
BAP: Buffer address pointer
ICS: EI2OS channel selection bit in ICR
DCT: Data counter
(1) I/O requests transfer.
(2) The interrupt controller selects the descriptor.
(3) The transfer source and transfer destination are read from the descriptor.
(4) Transfer is performed between I/O and memory.
(5) The interrupt cause is automatically cleared.
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CHAPTER 7 INTERRUPT
7.6
MB90820B Series
7.6.1
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) resides in internal RAM at
000100H to 00017FH. The ISD consists of 8 bytes x 16 channels.
■ Configuration of the Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The ISD consists of 8 bytes x 16 channels. Each ISD has the structure shown in Figure 7.6-2 . Table 7.6-1
shows the correspondence between channel numbers and ISD addresses.
Figure 7.6-2 Configuration of EI2OS descriptor (ISD)
High-order 8 bits of data counter (DCTH)
H
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI2OS status register (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100H + 8 x ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
Table 7.6-1 Correspondence between channel
numbers and ISD addresses
CM44-10147-2E
Channel
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
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Registers of EI2OS Descriptor (ISD)
7.6.2
• Data counter (DCT)
• I/O register address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
Note that the initial value of each register is undefined after a reset.
■ Data Counter (DCT)
The DCT is a 16-bit register that serves as a counter for the data transfer count. After each data transfer,
the counter is decremented by 1. When the counter reaches zero, EI2OS terminates.
Figure 7.6-3 shows the configuration of the DCT.
Figure 7.6-3 Configuration of DCT
DCTH
bit
Upper byte of data counter
15
B15
14
B14
13
B13
12
B12
11
B11
10
B10
9
B09
8
B08
Initial value:
xxxxxxxxB
7
B07
6
B06
5
B05
4
B04
3
B03
2
B02
1
B01
0
B00
Initial value:
xxxxxxxxB
DCTL
bit
Lower byte of data counter
■ I/O Register Address Pointer (IOA)
The IOA is a 16-bit register that indicates the lower address (A15 to A00) of the I/O register used to
transfer data to and from the buffer. The upper address (A23 to A16) is all zeros. Any I/O from 000000H
to 00FFFFH can be specified by address.
Figure 7.6-4 shows the configuration of the IOA.
Figure 7.6-4 Configuration of I/O register address pointer (IOA)
IOAH
bit
Upper address pointer
15
A15
14
A14
13
A13
12
A12
11
A11
10
A10
9
A09
8
A08
Initial value:
xxxxxxxxB
IOAL
bit
Lower address pointer
156
7
6
5
4
3
2
1
0
Initial value:
A07
A06
A05
A04
A03
A02
A01
A00
xxxxxxxxB
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CHAPTER 7 INTERRUPT
7.6
MB90820B Series
■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS)
The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O
register address pointer, transfer data format (byte or word), and transfer direction.
Figure 7.6-5 shows the configuration of the ISCS.
Figure 7.6-5 Configuration of EI2OS status register (ISCS)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IF
BW
BF
DIR
SE
R/W
R/W
R/W
R/W
R/W
RESV RESV RESV
R/W
R/W
R/W
Initial value
XXXXXXXXB
bit 0
EI2OS termination control bit
SE
0
Not terminated by a request from the peripheral function.
1
Terminated by a request from the peripheral function.
bit 1
Data transfer direction specification bit
DIR
0
I/O register address pointer → buffer address pointer.
1
Buffer address pointer → I/O register address pointer
bit 2
BF
BAP update/fixed selection bit
0
After data transfer, the buffer address pointer is updated. *1
1
After data transfer, the buffer address pointer is not
updated.
bit 3
Transfer data length specification bit
BW
0
Byte
1
Word
bit 4
IOA update/fixed selection bit
IF
0
After data transfer, the I/O address pointer is updated. *2
1
After data transfer, the I/O address pointer is not updated.
bit 5 to bit 7
RESV
Reserved bits
"0" must be written to these bits
R/W : Readable/Writeble
X
: Undefined
*1
: Only the lower 16 bits of the buffer address pointer charge. The buffer address pointer can only be incremented.
*2
: The I/O address pointer can only be incremented.
■ Buffer address Pointer (BAP)
The BAP is a 24-bit register that retains the address used by EI2OS for the next transfer. Since one
independent BAP exists for each EI2OS channel, each EI2OS channel can transfer data between any
address in the 16-megabyte space and the I/O. If the BF bit (BAP update/fixed selection bit) in the EI2OS
status register (ISCS) is set to "update yes, " only the lower 16 bits (BAPM and BAPL) of the BAP change;
the upper 8 bits (BAPH) do not change. Figure 7.6-6 shows the configuration of the BAP.
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MB90820B Series
Figure 7.6-6 Configuration of buffer address pointer (BAP)
bit23
BAP
to
BAPH
(R/W)
bit16
bit15
to
BAPM
(R/W)
bit8
bit7
to
BAPL
(R/W)
bit0
Initial value
xxxxxxH
R/W: Readable/Writeble
x: Undefined
References:
• The area that can be specified by the I/O address pointer (IOA) extends from 000000H to
00FFFFH.
• The area that can be specified with the buffer address pointer (BAP) extends from 000000H to
FFFFFFH.
• The maximum transfer count that can be specified by the data counter (DCT) is 65536 (64
kilobytes).
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7.6
MB90820B Series
7.6.3
Operation of the Extended Intelligent I/O Service (EI2OS)
If an interrupt request is generated by a peripheral function, EI2OS activation is set in
the corresponding interrupt control register (ICR) that the CPU uses EI2OS to transfer
data. When the specified data transfer count terminates, the hardware interrupt is
automatically processed.
■ Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Figure 7.6-7 shows the flow of EI2OS operation based on the internal microcode of the CPU.
Figure 7.6-7 Flow of extended intelligent I/O service (EI2OS) operation
Interrupt request generated
by peripheral function
NO
ISE = 1
YES
Interrupt sequence
Read ISD/ISCS
Termination
request from peripheral
function
YES
YES
SE = 1
NO
NO
YES
DIR = 1
NO
Data indicated by IOA
(data transfer)
Memory indicated by BAP
Data indicated by BAP
(data transfer)
Memory indicated by IOA
YES
IF = 0
NO
Update value
by BW
Update IOA
Update value
by BW
Update BAP
YES
BF = 0
NO
Decrement DCT
(-1)
YES
DCT = 00
EI2OS termination processing
NO
Set S1 and S0 to "00"
Clear interrupt request from
the peripheral function
Return to CPU operation
ISD:
ISCS:
IF:
BW:
BF:
DIR:
SE:
CM44-10147-2E
Set S1 and S0 to "11"
Set S1 and S0 to "01"
EI2OS descriptor
EI2OS status register
IOA update/fixed selection bit in the EI2OS status register (ISCS)
Transfer data length specification bit in the EI2OS status register (ISCS)
BAP update/fixed selection bit in the EI2OS status register (ISCS)
Data transfer direction specification bit in the EI2OS status register (ISCS)
EI2OS termination control bit in the EI2OS status register (ISCS)
Clear ISE to "0"
Interrupt sequence
DCT:
IOA:
BAP:
ISE:
Data counter
I/O register address pointer
Buffer address pointer
EI2OS enable bit in the interrupt control
register (ICR)
S1, S0: EI2OS status bit in the interrupt control
register (ICR)
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7.6
7.6.4
MB90820B Series
Procedure for Using the Extended Intelligent I/O Service
(EI2OS)
Before the extended intelligent I/O service (EI2OS) can be used, the system stack area,
extended intelligent I/O service (EI2OS) descriptor, interrupt function, and interrupt
control register (ICR) must be set.
■ Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Figure 7.6-8 shows the EI2OS software and hardware processing.
Figure 7.6-8 Procedure for using the extended intelligent I/O service (EI2OS)
Software processing
Hardware processing
Start
Set the system stack area
Set the EI2OS descriptor
Initialization
Initialize the peripheral
function
Set the interrupt control
register (ICR)
Set built-in resource to
start operation. Set the
interrupt enable bit
Set the ILM and I in the PS
(Interrupt request)
and (ISE = 1)
Execute the user program
S1, S0 = 00
Transfer data
(Branch to interrupt vector)
Decide whether to end
counting or to branch to an
interrupt requested by the
resource
NO
YES
Set the extended intelligent
I/O service again (switch
channels)
S1, S0 = 01 or
S1, S0 = 11
Process data in the buffer
RETI
ISE: EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status bit of the interrupt control register (ICR)
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7.6
MB90820B Series
7.6.5
Processing Time of the Extended Intelligent I/O Service
(EI2OS)
The time required for processing the extended intelligent I/O service (EI2OS) changes
according to the following factors:
•
•
•
•
•
EI2OS status register (ISCS) setting
Address (area) pointed to by the I/O register address pointer (IOA)
Address (area) pointed to by the buffer address pointer (BAP)
External data bus length for external access
Transfer data length
Because the hardware interrupt is activated when data transfer by EI2OS terminates, the
interrupt handling time is added.
■ Processing Time (One Transfer Time) of the Extended Intelligent I/O Service (EI2OS)
● When data transfer continues
The EI2OS processing time for data transfer continuation is shown in Table 7.6-2 based on the EI2OS status
register (ISCS) setting.
Table 7.6-2 Extended intelligent I/O service execution time
Terminates due to Ignores termination
termination request
request from the
from the peripheral peripheral function
function
EI2OS termination control bit (SE) setting
IOA update/fixed selection bit (IF) setting
BAP address update/fixed selection bit
(BF) setting
Fixed
Update
Fixed
Update
Fixed
32
34
33
35
Update
34
36
35
37
Unit: Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock, φ).
As shown in Table 7.6-3 , interpolation is necessary depending on the EI2OS execution condition.
Table 7.6-3 Data transfer interpolation value for EI2OS execution time
Internal access
External access
I/O register address pointer
Internal access
Buffer address
pointer
External access
B:
8:
CM44-10147-2E
B/Even
Odd
B/Even
8/Odd
B/Even
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/Even
+1
+3
+2
+5
8/Odd
+4
+6
+5
+8
Byte data transfer
External bus width using the 8-bit word transfer
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MB90820B Series
Even: Even-numbered address word transfer
Odd: Odd-numbered address word transfer
● When the data counter (DCT) count terminates (final data transfer)
Because the hardware interrupt is activated when data transfer by EI2OS terminates, the interrupt handling
time is added. The EI2OS processing time when counting terminates is calculated with the following
formula:
EI2OS processing time when counting terminates = EI2OS processing time when data is
transferred + (21 + 6 × Z) Machine cycles
Interrupt handling time
The interrupt handling time is different for each address pointed to by the stack pointer. Table 7.6-4 shows
the interpolation value (Z) for the interrupt handling time.
Table 7.6-4 Interpolation value (Z) for the interrupt handling time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
● For termination by a termination request from the peripheral function (I/O)
When data transfer by EI2OS is terminated before completion due to a termination request from the
peripheral function (I/O) (ICR: S1, S0 = 11B), the data transfer is not performed and a hardware interrupt
is activated. The EI2OS processing time is calculated with the following formula. Z in the formula
indicates the interpolation value for the interrupt handling time (Table 6.6.5-3).
EI2OS processing time for termination of data transfer = 36 + 6 × Z Machine cycle
Reference:
One machine cycle corresponds to one clock cycle of the machine clock (φ).
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7.7
MB90820B Series
7.7
Exception Processing Interrupt
In the F2MC-16LX, the execution of an undefined instruction results in exception
processing.
Exception processing is basically the same as an interrupt. When the generation of an
exception processing is detected on the instruction boundary, ordinary processing is
interrupted and exception processing is executed.
Generally, exception processing occurs as the result of an unexpected operation.
Exception processing should be used only to activate recovery software required for
debugging or an emergency.
■ Exception Processing
● Exception processing operation
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions.
When an undefined instruction is executed, processing equivalent to the INT #10 software interrupt
instruction is executed.
The following processing is executed before exception processing branches to the interrupt routine:
• The A, DPR, ADB, DTB, PCB, PC, and PS registers are saved to the system stack.
• The I flag of the condition code register (CCR) is cleared to "0", and hardware interrupts are masked.
• The S flag of the condition code register (CCR) is set to "1", and the system stack is activated.
The program counter (PC) value saved to the system stack is the exact address where the undefined
instruction is stored. For 2-byte or longer instruction codes, the code identified as undefined is stored at
this address. When the exception factor type must be determined within the exception processing routine,
use this PC value.
● Return from exception processing
When the RETI instruction returns control from exception processing, exception processing restarts
because the PC is pointing to the undefined instruction. Provide a solution such as resetting the software.
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7.8
7.8
MB90820B Series
Stack Operations for Interrupt Processing
Once an interrupt is accepted, the contents of the dedicated registers are automatically
saved to the system stack before a branch to interrupt processing. When the interrupt
processing terminates, the previous processing is automatically restored from the
system stack.
■ Stack Operations at the Start of Interrupt Processing
Once an interrupt is accepted, the CPU automatically saves the contents of the current dedicated registers to
the system stack in the order given below:
• Accumulator (A)
• Direct page register (DPR)
• Additional data bank register (ADB)
• Data bank register (DTB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Figure 7.8-1 shows the stack operations at the start of interrupt processing.
Figure 7.8-1 Stack operations at the start of interrupt processing
Immediately before interrupt
Immediately after interrupt
Memory
Address
Memory
Address
before update
SP after update
Byte
Byte
■ Stack Operations on Return from Interrupt Processing
When the interrupt return instruction (RETI) is executed at the termination of interrupt processing,
dedicated register (the PS, PC, PCB, DTB, ADB, DPR, and A) values are returned from the stack in reverse
order from the order they were placed on the stack. The dedicated registers are restored to the status they
had immediately before the start of interrupt processing.
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7.8
MB90820B Series
■ Stack Area
● Stack area allocation
The stack area is used for saving and restoring the program counter (PC) when the subroutine call
instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt processing.
The stack area is used for temporary saving and restoring of registers by the PUSHW and POPW
instructions.
The stack area is allocated together with the data area in RAM.
Figure 7.8-2 shows the stack area.
Figure 7.8-2 Stack area
Vector table
(interrupt vector call
instruction for a reset)
FFFFFFH
FFFC00H
ROM area
FF0000H*1
001100H*2
Built-in
RAM area
Stack
area 000380H
000180H
General-purpose
register bank area
000100H
0000F0H
000000H
*1
*2
Built-in I/O area
The internal ROM is different for each model.
The internal RAM is different for each model.
Notes:
• Generally set an even-numbered address in the stack pointers (SSP and USP).
• Allocate the system stack area, user stack area, and data area so that they do not overlap.
● System stack and user stack
The system stack area is used for interrupt processing. When an interrupt occurs, the user stack area being
used is forcibly switched to the system stack. The system stack area must be set correctly even in a system
that mainly uses the user stack area.
If division of the stack space is not particularly necessary, use only the system stack.
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7.8
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CHAPTER 8
MODE SETTING
This chapter describes the operating modes and
memory access modes supported by the MB90820B
series.
CM44-10147-2E
8.1
Mode Setting
8.2
Mode Pins (MD2 to MD0)
8.3
Mode Data
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CHAPTER 8 MODE SETTING
8.1
8.1
MB90820B Series
Mode Setting
The F2MC-16LX supports the modes for access method and access areas. A mode is
determined based on the settings by the mode pin at a reset as well as the mode data
fetched.
■ Mode Setting
The F2MC-16LX supports the modes for access method and access areas, classified as shown in
Figure 8.1-1 in this module.
Figure 8.1-1 Mode classification
Operating mode
RUN mode
FLASH WRITE mode
Bus mode
Single-chip mode
■ Operating Modes
The operating modes control the operating state of the device and are specified by the mode setting pin
(MDx) and Mx bit contents in mode data.
● Bus mode
The bus mode controls the operation of internal ROM and external access functions and is specified by the
mode setting pin (MDx) and Mx bit contents in mode data. The mode setting pin (MDx) specifies bus
mode when reset vector and mode data are read. The Mx bit in mode data specifies bus mode during
normal operation.
● RUN mode
The RUN mode means CPU operating mode. The RUN mode includes main clock mode, PLL clock mode,
and various low-power consumption modes. See "CHAPTER 6 LOW-POWER CONSUMPTION
MODE", for details.
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CHAPTER 8 MODE SETTING
8.2
MB90820B Series
8.2
Mode Pins (MD2 to MD0)
Three external pins, MD2 to MD0, are supported as the mode pins. These are used to
specify how the reset vector and mode data are fetched.
■ Mode Pins (MD2 to MD0)
The mode pins are used to select the data bus (external or internal) used for reading the reset vector and to
specify the bus width when the external data bus is selected.
For built-in FLASH memory, the mode pins are also used to specify FLASH programming mode, which is
used to write programs and other data to internal FLASH memory.
Table 7.2-1 shows the mode pin settings.
Table 8.2-1 Mode pin settings
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
Mode name
Reset vector
access area
External data
bus width
Remarks
Setting not allowed
Internal vector mode
Internal
Mode data
The reset
sequence and
subsequent
sequences are
controlled by
mode data.
0
1
1
1
0
0
1
0
1
1
1
0
FLASH serial write
mode
-
-
-
1
1
1
FLASH memory
mode
-
-
Mode when the
parallel writer
is used.
Setting not allowed
MD2 to MD0: Connect the pins to Vss for "0" and to Vcc for "1".
*: The flash serial write mode cannot be executed by just setting the mode pins. Other terminal also need to be set. For
details, see "APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for Serial Writing".
Note:
Because the MB90820B series is only used in single-chip mode, set MD2, MD1, and MD0 to "011B"
and set M1 and M0 to "00B".
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CHAPTER 8 MODE SETTING
8.3
8.3
MB90820B Series
Mode Data
The mode data is at memory location FFFFDFH and is used to specify the operation
after a reset sequence. The mode data is automatically fetched to the CPU.
■ Mode Data
During a reset sequence, the mode data at address FFFFDFH is fetched to the mode data register in the
CPU. The CPU uses the mode data to set the memory access mode.
The contents of the mode data register can only be changed during the reset sequence. The memory access
mode set by the mode data takes effect after the reset sequence.
Figure 7.3-1 shows the mode data configuration.
Figure 8.3-1 Mode data configuration
bit
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bits (reserved area)
Bus mode setting bits
■ Bus Mode Setting Bits
The bus mode setting bits specify operating mode after a reset sequence. Table 7.3-1 lists the relationship
between the bits and functions.
Table 8.3-1 Bus mode setting bits and functions
M1
M0
Function
0
0
Single-chip mode
0
1
1
0
1
1
(Setting not allowed)
Note:
Because the MB90820B series is only used in single-chip mode, set MD2, MD1, and MD0 to "011B"
and set M1 and M0 to "00B".
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CHAPTER 8 MODE SETTING
8.3
MB90820B Series
Figure 7.3-2 shows the correspondence between access areas and physical addresses in single-chip mode.
Figure 8.3-2 Correspondence between access areas and physical addresses in single-chip mode
FFFFFFH
ROM
Model #1
FF0000H
00FFFFH
ROM
When ROM mirroring function is selected
Model #2
Model #3
RAM
000100H
0000F0H
000000H
: No access
: Internal access
I/O
Note: Model #x becomes the model-dependent address.
■ Relationship Between Mode Pins and Mode Data
Table 7.3-2 lists the relationship between mode pins and mode data.
Table 8.3-2 Relationship between mode pins and mode data
Mode pins
Mode data
Mode
Single-chip mode
MD2
MD1
MD0
M1
M0
0
1
1
0
0
Note :
Because the MB90820B series is only used in single-chip mode, set MD2, MD1, and MD0 to "011B"
and set M1 and M0 to "00B".
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8.3
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CHAPTER 9
I/O PORTS
This chapter describes the functions and operation of
the I/O ports.
9.1
Overview of I/O Ports
9.2
Registers of I/O Ports
9.3
Port 0
9.4
Port 1
9.5
Port 2
9.6
Port 3
9.7
Port 4
9.8
Port 5
9.9
Port 6
9.10 Port 7
9.11 Port 8
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CHAPTER 9 I/O PORTS
9.1
9.1
MB90820B Series
Overview of I/O Ports
All I/O ports can be used as general-purpose I/O ports (parallel I/O ports). The
MB90820B series has 9 ports (66 pins). The ports are also used for resource I/O pins
(peripheral function I/O pins).
■ I/O Ports Functions
Each I/O port outputs data from CPU to I/O pins or inputs signals from I/O pins to CPU through port data
register (PDR). Direction of the data flow (input or output) for each I/O pin can be designated in bit unit by
port direction register (DDR). The function of each port and the resource I/O multiplexed with it are
described below:
• Port 0 : General-purpose I/O port/resource (PWC)
• Port 1 : General-purpose I/O port/resources (DTP / Multi-functional timer)
• Port 2 : General-purpose I/O port/resource (16-bit reload timer)
• Port 3 : General-purpose I/O port/resource (16-bit PPG timer)
• Port 4 : General-purpose I/O port/resources (16-bit PPG timer / 16-bit reload timer / UART / PWC)
• Port 5 : General-purpose I/O port/resources (16-bit PPG timer / DTP)
• Port 6 : General-purpose I/O port/resource (8/10-bit A/D converter)
• Port 7 : General-purpose I/O port/resources (8/10-bit A/D converter / 8-bit D/A converter / UART / 16bit free-run timer / 16-bit input capture)
• Port 8 : General-purpose I/O port/resources (16-bit input capture / Multi-functional timer)
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CHAPTER 9 I/O PORTS
9.1
MB90820B Series
Table 9.1-1 summarizes the functions of individual port.
Table 9.1-1 Functions of individual port
Port
Pin
Port 0
P00 to
P07/
PWO0
Input Output Function
type
type
General I/O port
Resource
General I/O port
Port 1
Port 2
P10/INT0/
CMOS
DTTI to
(hysteresis) CMOS Resource
P17
pull-up
P30
to P37/
PPG0
Port 3
Resource
General I/O port
CMOS
Resource
P40/PPG1
Port 4
to P47/
PWO1
CMOS
P50/PPG2 (hysteresis)
Port 5
to P51/
INT7
Port 6
P60/AN0
to P67/
AN7
P70/DA0/
AN8
Port 7
to
P77/IN1/
CMOS
AN15 (hysteresis)
Port 8
P80/IN2
to P87/
RTO5
–
–
–
–
–
–
–
P07
P06
PWO0 PWI0
P05
P04
P03
P02
P01
P00
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P17
P16
P15
P14
P13
P12
P11
P10
–
–
–
–
–
–
–
–
INT0
INT6 INT5 INT4 INT3 INT2 INT1
DTTI
–
–
–
–
–
–
–
–
P21
P20
–
–
–
–
–
–
–
–
P27
P26
P25
P24
P23
P22
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P37
P36
P35
P34
P33
P32
P31
P30
–
–
–
–
–
–
TO1 TIN1
–
–
PPG0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
General I/O port
–
–
–
–
–
–
–
–
P47
P46
P45
P44
P43
P42
P41
P40
Analog output
–
–
–
–
–
–
–
–
PWO1 PWI1 SIN0* SOT0 SCK0 TO0 TIN0 PPG1
General I/O port
–
–
–
–
–
–
P51
P50
–
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
INT7 PPG2
–
–
–
–
–
–
–
–
General I/O port
–
–
–
–
–
–
–
P67
P66
P65
P64
P63
P62
P61
P60
AN0
CMOS
CMOS
–
–
resistor
selectable General I/O port
P20/TIN1
to P27
bit bit bit bit bit bit bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
15 14 13 12 11 10
Analog Input
–
–
–
–
–
–
–
–
–
AN7
AN6
AN5
AN4
AN3
AN2
AN1
General I/O port
P77
P76
P75
P74
P73
P72
P71
P70
–
–
–
–
–
–
–
–
Resource
IN1
IN0
FRCK SCK1 SOT1 SIN1*
–
–
–
–
–
–
–
–
–
–
–
–
–
Analog output
Analog input
–
–
–
–
AN15 AN14 AN13 AN12 AN11 AN10
DA1
DA0
–
–
–
–
–
–
–
AN9
AN8
–
–
–
–
–
–
–
–
P87
P86
P85
P84
P83
P82
P81
P80
IN3
IN2
General I/O port
–
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
–
–
RTO5 RTO4 RTO3 RTO2 RTO1 RTO0
*: UART0, UART1 data input pins SIN0 and SIN1 can be selected as CMOS input by user program.
Note :
Port 6, Port 7 are also used as analog signal input pins. To use the port as a general-purpose I/O
port, be sure to set the corresponding bit of the analog input enable register (ADER0 and ADER1) to
"0". Resetting the MCU sets the ADER0 / ADER1 register bits to "1".
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CHAPTER 9 I/O PORTS
9.2
9.2
MB90820B Series
Registers of I/O Ports
This section provides a list of the registers related to the I/O port settings.
■ Registers for I/O Ports
Table 9.2-1 is a list of the registers corresponding to individual port.
Table 9.2-1 Registers of corresponding port
Register name
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
XXXXXXXXB
Port 0 direction register (DDR0)
R/W
000010H
00000000B
Port 1 direction register (DDR1)
R/W
000011H
00000000B
Port 2 direction register (DDR2)
R/W
000012H
00000000B
Port 3 direction register (DDR3)
R/W
000013H
00000000B
Port 4 direction register (DDR4)
R/W
000014H
00000000B
Port 5 direction register (DDR5)
R/W
000015H
XXXXXX00B
Port 6 direction register (DDR6)
R/W
000016H
00000000B
Port 7 direction register (DDR7)
R/W
000017H
00000000B
Port 8 direction register (DDR8)
R/W
000018H
00000000B
Analog input enable register 0 (ADER0)
R/W
0000C5H
11111111B
Analog input enable register 1 (ADER1)
R/W
0000D0H
11111111B
Port 0 pull-up resistor setting register (RDR0)
R/W
00008CH
00000000B
Port 1 pull-up resistor setting register (RDR1)
R/W
00008DH
00000000B
Port 2 pull-up resistor setting register (RDR2)
R/W
00008EH
00000000B
Port 3 pull-up resistor setting register (RDR3)
R/W
00008FH
00000000B
R/W :Readable and writable
X
176
:Undefined
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MB90820B Series
9.3
Port 0
Port 0 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function, also provides the configuration of port 0, lists of pins, shows
a block diagram of the pins, and describes the corresponding registers.
■ Port 0 Configuration
Port 0 consists of the following:
• General-purpose I/O pins/resources I/O pins (P00 to P07/PWO0)
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up resistor setting register (RDR0)
■ Port 0 Pins
The port 0 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as generalpurpose I/O port pins when they are used as resource I/O pins. Table 9.3-1 lists the port 0 pins.
Table 9.3-1 Port 0 pins
Port
Pin
I/O form
Port function
(single-chip mode)
Resource function
P00
P00
–
–
P01
P01
–
–
P02
P02
–
–
P03
P03
–
–
P04
P04
–
–
P05
P05
–
–
P06/PWI0
P06
PWI0
PWC0 input
P07/PWO0
P07
PWO0
PWC0 output
Port 0
Generalpurpose I/O
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
C
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 0 Pins
Figure 9.3-1shows the block diagram of the P00 to P06/PWI0 pins.
Figure 9.3-1 Block diagram of P00 to P06/PWI0 pins
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 9.3-2 shows the block diagram of the P07/PWO0 pin.
Figure 9.3-2 Block diagram of P07/PWO0 pin
Standby control (SPL=1)
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR0 register.
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■ Port 0 Registers
Port 0 registers are PDR0, DDR0, and RDR0. The bits making up each register correspond to the port 0
pins on a one-to-one basis. Table 8.3-2 lists the port 0 pins and their corresponding register bits.
Table 9.3-2 Port 0 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR0, DDR0, RDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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9.3
9.3.1
MB90820B Series
Port 0 Registers (PDR0, DDR0, and RDR0)
This section describes the port 0 registers.
■ Functions of Port 0 Registers
● Port 0 data register (PDR0)
The PDR0 register indicates the state of each pin for port 0.
● Port 0 direction register (DDR0)
The DDR0 register specifies the direction of a data flow (input or output) at each pin (bit) of port 0. When
a DDR0 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Note :
• When a resource having output pins is used, the port functions as resource output pins regardless of the
value in the DDR0 register as long as the resource output enable bit corresponding to the pins is set to
enable.
• To use a resource having input pins, set the port 0 direction register bit corresponding to each resource
input pin to "0" to place the port in input mode.
Table 9.3-3 lists the functions of the port 0 registers.
Reference:
When the MCU is reset, the DDR0 register is cleared to "0" for general I/O port input.
● Port 0 pull-up resistor setting register (RDR0)
The RDR0 register specifies the selection of a pull-up resistor at each pin (bit) of port 0. When a RDR0
register bit is “1”, a pull-up resistor is selected for the corresponding port (pin). When the bit is “0”, the
pull-up resistor is deselected.
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Table 9.3-3 lists the functions of the port 0 registers.
Table 9.3-3 Port 0 register functions
Register
name
Data
During reading
During writing
0
The pin is at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The direction latch is
"0".
The output buffer is turned off to
place the port in input mode.
1
The direction latch is
"1".
The output buffer is turned on to
place the port in output mode.
0
The setting latch is
"0".
The pull-up resistor is cut and the
port is placed in the Hi-Z state in
input mode.
The setting latch is
"1".
The pull-up resistor is selected and
the port is held at the "H" level in
input mode.
Port 0 data
register
(PDR0)
Port 0
direction
register
(DDR0)
Port 0 pullup resistor
setting
register
(RDR0)
1
Read/
Write
Address
Initial
value
R/W
000000H
XXXXXXXXB
R/W
000010H
00000000B
R/W
00008CH
00000000B
R/W : Readable and writable
X
: Undefined
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9.3.2
MB90820B Series
Operation of Port 0
This section describes the operation of port 0.
■ Operation of Port 0
● Port operation in output mode
• Setting a bit of the DDR0 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR0 register in output mode is held in the output latch of the PDR0 and output to
the port pins.
• The PDR0 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR0).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port 0 data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write the output data to the PDR
register, then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR0 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pin is in high-impedance state.
• However, when the corresponding bit in RDR0 register is set to "1" to select a pull-up resistor, the pin is
held at the H level.
• Data written to the PDR0 register in input mode is held in the output latch of the PDR0 but is not output
to the port pins.
• The PDR0 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR0
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the corresponding bit in DDR0 register to "0" to place the
port in input mode.
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● Port operation after a reset
• When the MCU is reset, the DDR0 and RDR0 registers are initialized to "0". As a result, the output
buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a
high-impedance state.
• The PDR0 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR0 register after the output data is set in the PDR0 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR0 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.3-4 lists the states of the port 0 pins.
Table 9.3-4 States of port 0 pins
Normal
operation
Pin
P00 to P07/
PWO0
SPL
General-purpose
I/O port
Sleep mode
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL = 0)
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL = 1,
RDR = 0)
Input disabled/
output in Hi-Z
Stop mode or
time-base timer
mode (SPL = 1,
RDR = 1)
Input disabled/held
at H level
: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
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9.4
MB90820B Series
Port 1
Port 1 is a general-purpose I/O port. It can also be used for resource input. Individual
port pin can be switched between the general-purpose I/O port and resource input. This
section focuses on the general I/O port function. The section also provides the
configuration of port 1, lists its pins, shows a block diagram of the pins, and describes
the corresponding registers.
■ Port 1 Configuration
Port 1 consists of the following:
• General-purpose I/O pins/resources input pins (P10/INT0/DTTI to P17)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up resistor setting register (RDR1)
■ Port 1 Pins
The port 1 I/O pins are also used as resource input pins. Therefore, the pins cannot be used as generalpurpose I/O port when they are used as resource input pins. Table 9.4-1 lists the port 1 pins.
Table 9.4-1 Port 1 pins
I/O form
Port
Port 1
Pin
Port function
Resource function
P10/INT0/
DTTI
P10
INT0/
DTTI
External interrupt
input / waveform
generator input
P11/INT1
P11
INT1
External interrupt
input
P12/INT2
P12
INT2
External interrupt
input
P13/INT3
P13
INT3
External interrupt
input
P14/INT4
P14
INT4
External interrupt
input
P15/INT5
P15
INT5
External interrupt
input
P16/INT6
P16
INT6
External interrupt
input
P17
P17
Generalpurpose I/O
–
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
D
–
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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MB90820B Series
■ Block Diagram of Port 1 Pins
Figure 9.4-1shows the block diagram of P10/INT0/DTTI to P16/INT6 pins.
Figure 9.4-1 Block diagram of P10/INT0/DTTI to P16/INT6 pins
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 9.4-2 shows the block diagram of P17 pin.
Figure 9.4-2 Block diagram of P17 pin
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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■ Port 1 Registers
Port 1 registers are PDR1, DDR1, and RDR1. The bits making up each register correspond to the port 1
pins on a one-to-one basis. Table 9.4-2 lists the port 1 pins and their corresponding register bits.
Table 9.4-2 Port 1 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR1, DDR1, RDR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
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9.4
MB90820B Series
9.4.1
Port 1 Registers (PDR1, DDR1, and RDR1)
This section describes the port 1 registers.
■ Functions of Port 1 Registers
● Port 1 data register (PDR1)
The PDR1 register indicates the state of each pin for port 1.
● Port 1 direction register (DDR1)
The DDR1 register specifies the direction of a data flow (input or output) at each pin (bit) of port 1. When
a DDR1 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Note :
To use a resource having input pins, reset the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
Reference :
When the MCU is reset, the DDR1 register is cleared to “0” for general I/O port.
● Port 1 pull-up resistor setting register (RDR1)
The RDR1 register specifies the selection of a pull-up resistor at each pin (bit) of port 1. When a RDR1
register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the
pull-up resistor is deselected.
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Table 9.4-3 lists the functions of the port 1 registers.
Table 9.4-3 Port 1 register functions
Register name
Data
During
reading
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
The output buffer is turned on to
place the port in output mode.
0
The setting
latch is "0".
The pull-up resistor is cut and the
port is placed in the Hi-Z state in
input mode.
The setting
latch is "1".
The pull-up resistor is selected and
the port is held at the "H" level in
input mode.
Port 1 data
register (PDR1)
Port 1 direction
register (DDR1)
Port 1 pull-up
resistor setting
register (RDR1)
1
Read/
Write
Address
Initial value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
R/W
00008DH
00000000B
R/W : Readable and writable
X
188
: Undefined
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CHAPTER 9 I/O PORTS
9.4
MB90820B Series
9.4.2
Operation of Port 1
This section describes the operation of port 1.
■ Operation of Port 1
● Port operation in output mode
• Setting a bit of the DDR1 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR1 register in output mode is held in the output latch of the PDR1 and output to
the port pins.
• The PDR1 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR1).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write the output data to the PDR
register, then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR1 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pin is in high-impedance state.
• However, when the corresponding bit in RDR1 register is set to "1" to select a pull-up resistor, the pin is
held at the H level.
• Data written to the PDR1 register in input mode is held in the output latch of the PDR1 but not output to
the port pins.
• The PDR1 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs. To
use an external signal for the resource, set the corresponding bit in DDR1 register to "0" to place the port in
input mode.
● Port operation after a reset
• When the MCU is reset, the DDR1 registers is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high-impedance state.
• The PDR1 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR1 register after the output data is set in the PDR1 register.
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● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR1 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.4-4 lists the states of the port 1 pins.
Table 9.4-4 States of port 1 pins
Pin
Normal
operation
Sleep mode
Stop mode or
time-base timer
mode (SPL =0)
Stop mode or
time-base timer
mode (SPL=1,
RDR =0)
Stop mode or
time-base timer
mode (SPL=1,
RDR =1)
P10/INT0/
DTTI to
P16/INT6
General-purpose
I/O port
General-purpose
I/O port
General-purpose
I/O port
Input enabled */
output in Hi-Z
Input enabled */
held at "H" level
P17
General-purpose
I/O port
General-purpose
I/O port
General-purpose
I/O port
Input disabled/
output in Hi-Z
Input disabled/
held at "H" level
SPL
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
* : Only when P10/INT0/DTTI to P16/INT6 are configured as external interrupt pins, otherwise, input is disabled.
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9.5
MB90820B Series
9.5
Port 2
Port 2 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function. The section provides the configuration of port 2, lists its pins,
shows a block diagram of the pins, and describes the corresponding registers.
■ Port 2 Configuration
Port 2 consists of the following:
• General-purpose I/O port/resource I/O pins (P20/TIN1 to P27)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• Port 2 pull-up resistor setting register (RDR2)
■ Port 2 Pins
The port 2 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as generalpurpose I/O port when they are used as resource I/O pins. Table 9.5-1 lists the port 2 pins.
Table 9.5-1 Port 2 pins
I/O form
Port
Port 2
Pin
Port function
Resource function
P20/TIN1
P20
TIN1
16-bit reload timer 1
input
P21/TO1
P21
TO1
16-bit reload timer 1
output
P22
P22
Generalpurpose I/O
–
–
–
–
P23
P23
P24
P24
–
–
P25
P25
–
–
P26
P26
–
–
P27
P27
–
–
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
D
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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9.5
MB90820B Series
■ Block Diagram of Port 2 Pins
Figure 9.5-1 shows the block diagram of port 2 (excluding P21/TO1) pins.
Figure 9.5-1 Block diagram of port 2 (excluding P21/TO1) pins
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 9.5-2 shows the block diagram of P21/TO1 pin.
Figure 9.5-2 Block diagram of P21/TO1 pin
Standby control (SPL=1)
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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9.5
MB90820B Series
When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR2 register.
■ Port 2 Registers
Port 2 registers are PDR2, DDR2, and RDR2. The bits making up each register correspond to the port 2
pins on a one-to-one basis. Table 9.5-2 lists the port 2 pins and their corresponding register bits.
Table 9.5-2 Port 2 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR2, DDR2, RDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
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9.5.1
MB90820B Series
Port 2 Registers (PDR2, DDR2, and RDR2)
This section describes the port 2 registers.
■ Functions of Port 2 Registers
● Port 2 data register (PDR2)
The PDR2 register indicates the state of each pin for port 2.
● Port 2 direction register (DDR2)
The DDR2 register specifies the direction of a data flow (input or output) at each pin (bit) of port 2. When
a DDR2 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is 0, the port
(pin) is set as an input port.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR2 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, set the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
● Port 2 pull-up resistor setting register (RDR2)
The RDR2 register specifies the selection of a pull-up resistor at each pin (bit) of port 2. When a RDR2
register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the
pull-up resistor is deselected.
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Table 9.5-3 lists the functions of the port 2 registers.
Table 9.5-3 Port 2 register functions
Register name
Data
During
reading
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
The output buffer is turned on to
place the port in output mode.
0
The setting
latch is "0".
The pull-up resistor is cut and the
port is placed in the Hi-Z state in
input mode.
The setting
latch is "1".
The pull-up resistor is selected and
the port is held at the "H" level in
input mode.
Port 2 data
register (PDR2)
Port 2 direction
register (DDR2)
Port 2 pull-up
resistor setting
register (RDR2)
1
Read/
Write
Address
Initial value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
R/W
00008EH
00000000B
R/W : Readable and writable
X
: Undefined
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9.5.2
MB90820B Series
Operation of Port 2
This section describes the operation of port 2.
■ Operation of Port 2
● Port operation in output mode
• Setting a bit of the DDR2 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR2 register in output mode is held in the output latch of the PDR2 and output to
the port pins.
• The PDR2 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR2).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write the output data to the PDR
register, then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR2 register to “0” places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pin is in high-impedance state.
• However, when the corresponding bit in RDR2 register is set to “1” to select a pull-up resistor, the pin is
held at the H level.
• Data written to the PDR2 register in input mode is held in the output latch of the PDR2 but not output to
the port pins.
• The PDR2 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR2
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the corresponding bit in DDR2 register to "0" to place the
port in input mode.
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● Port operation after a reset
• When the MCU is reset, the DDR2 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input) and the pins are placed in a high-impedance state.
• The PDR2 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR2 register after the output data is set in the PDR2 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR2 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.5-4 lists the states of the port 2 pins.
Table 9.5-4 States of port 2 pins
Normal
operation
Pin
P20/TIN1
to P27
SPL
General-purpose
I/O port
Sleep mode
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL =0)
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL =1,
RDR =0)
Input disabled/
output in Hi-Z
Stop mode or
time-base timer
mode (SPL =1,
RDR =1)
Input disabled/
held at "H" level
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
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9.6
MB90820B Series
Port 3
Port 3 is a general-purpose I/O port. It can also be used for resource output. Individual
port pin can be switched between the I/O port and resource output. This section
focuses on the general I/O port function. The section provides the configuration of port
3, lists its pins, shows a block diagram of the pins, and describes the corresponding
registers.
■ Port 3 Configuration
Port 3 consists of the following:
• General-purpose I/O pins/resources output pin (P30 to P37/PPG0)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
• Port 3 pull-up resistor setting register (RDR3)
■ Port 3 pins
The port 3 is also used as resource output pin. Therefore, the pins cannot be used as general-purpose I/O
port pins when they are used as resource output pin. Table 9.6-1 lists the port 3 pins.
Table 9.6-1 Port 3 pins
I/O form
Port
Pin
Port function
Resource function
P30
P30
–
–
P31
P31
–
–
P32
P32
–
–
P33
P33
–
–
P34
P34
–
–
P35
P35
–
–
P36
P36
–
–
P37/PPG0
P37
PPG0
Port 3
Generalpurpose I/O
Input
Output
CMOS
CMOS
Circuit
type
E
PPG0 output
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 3 Pins
Figure 9.6-1 shows the block diagram of port 3 (excluding P37/PPG0) pins.
Figure 9.6-1 Block diagram of port 3 (excluding P37/PPG0) pins
Standby control (SPL=1)
RDR
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 9.6-2 shows the block diagram of P37/PPG0 pin.
Figure 9.6-2 Block diagram of P37/PPG0 pin
Standby control (SPL=1)
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR3 register.
■ Port 3 Registers
Port 3 registers are PDR3, DDR3, and RDR3. The bits making up each register correspond to the port 3
pins on a one-to-one basis. Table 9.6-2 lists the port 3 pins and their corresponding register bits.
Table 9.6-2 Port 3 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR3, DDR3, RDR3
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P37
P36
P35
P34
P33
P32
P31
P30
Port 3
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9.6.1
Port 3 Registers (PDR3, DDR3, and RDR3)
This section describes the port 3 registers.
■ Functions of Port 3 Registers
● Port 3 data register (PDR3)
The PDR3 register indicates the state of each pin for port 3.
● Port 3 direction register (DDR3)
The DDR3 register specifies the direction of a data flow (input or output) at each pin (bit) of port 3. When
a DDR3 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Note :
When a resource having output pins is used, the port functions as resource output pins regardless of
the value in the DDR3 register as long as the resource output enable bit corresponding to the pins is
set.
● Port 3 pull-up resistor setting register (RDR3)
The RDR3 register specifies the selection of a pull-up resistor at each pin (bit) of port 3. When a RDR3
register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the
pull-up resistor is deselected. Table 9.6-3 lists the functions of the port 3 registers.
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Table 9.6-3 Port 3 register functions
Register name
Data
During
reading
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
The output buffer is turned on to
place the port in output mode.
0
The setting
latch is "0".
The pull-up resistor is cut and the
port is placed in the Hi-Z state in
input mode.
The setting
latch is "1".
The pull-up resistor is selected and
the port is held at the "H" level in
input mode.
Port 3 data
register (PDR3)
Port 3 direction
register (DDR3)
Port 3 pull-up
resistor setting
register (RDR3)
1
Read
/Write
Address
Initial value
R/W
000003H
XXXXXXXXB
R/W
000013H
00000000B
R/W
00008FH
00000000B
R/W : Readable and writable
X
202
: Undefined
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9.6.2
Operation of Port 3
This section describes the operation of port 3.
■ Operation of Port 3
● Port operation in output mode
• Setting a bit of the DDR3 register to “1” places the corresponding port pin in output mode.
• Data written to the PDR3 register in output mode is held in the output latch of the PDR3 and output to
the port pins.
• The PDR3 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR3).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write the output data to the PDR
register, then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR3 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pin is in high-impedance state.
• However, when the corresponding bit in RDR3 register is set to “1” to select a pull-up resistor, the pin is
held at the H level.
• Data written to the PDR3 register in input mode is held in the output latch of the PDR3 but not output to
the port pins.
• The PDR3 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR3
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation after a reset
• When the MCU is reset, the DDR3 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input) and the pins are placed in a high-impedance state.
• The PDR3 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR3 register after the output data is set in the PDR3 register.
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● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR3 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.6-4 lists the states of the port 3 pins.
Table 9.6-4 States of port 3 pins
Pin
P30 to
P37/PPG0
SPL
Normal
operation
General-purpose
I/O port
Sleep mode
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL =0)
General-purpose
I/O port
Stop mode or
time-base timer
mode (SPL =1,
RDR =0)
Input disabled/
output in Hi-Z
Stop mode or
time-base timer
mode (SPL =1,
RDR =1)
Input disabled/
held at "H" level
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
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MB90820B Series
9.7
Port 4
Port 4 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function, also provides the configuration of port 4, lists of pins, shows
a block diagram of the pins, and describes the corresponding registers.
■ Port 4 Configuration
Port 4 consists of the following:
• General-purpose I/O pins/resources I/O pins (P40/PPG1 to P47/PWO1)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Port 4 Pins
The port 4 is also used as resource I/O pins. Therefore, the pins cannot be used as general-purpose I/O port
when they are used as resource I/O pins. Table 9.7-1 lists the port 4 pins.
Table 9.7-1 Port 4 pins
I/O form
Port
Pin
Port function
Resource function
Input
Port 4
P40/PPG1
P40
PPG1
PPG1 output
P41/TIN0
P41
TIN0
16-bit reload timer 0
input
P42/TO0
P42
TO0
16-bit reload timer 0
output
P43/SCK0
P43
SCK0
UART0 serial clock I/O
P44/SOT0
P44
SOT0
UART0 data output
P45/SIN0
P45
SIN0
UART0 data input
P46/PWI1
P46
PWI1
PWC1 input
P47/PWO1
P47
PWO1
PWC1 output
Generalpurpose I/O
Output
Circuit
type
F
CMOS
(hysteresis)
CMOS
G
F
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 4 Pins
Figure 9.7-1shows the block diagram of port 4 pins (excluding P41/TIN0, P45/SIN0, P46/PWI1).
Figure 9.7-1 Block diagram of port 4 (excluding P41/TIN0, P45/SIN0, P46/PWI1) pins
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR4 register.
Figure 9.7-2 shows the block diagram of P41/TIN0 and P46/PWI1 pins.
Figure 9.7-2 Block diagram of P41/TIN0 and P46/PWI1 pins
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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Figure 9.7-3 shows the block diagram of P45/SIN0 pin.
Figure 9.7-3 Block diagram of P45/SIN0 pin
UART0 data input
UART0 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
■ Port 4 Registers
Port 4 registers are PDR4 and DDR4. The bits making up each register correspond to the port 4 pins on a
one-to-one basis. Table 9.7-2 lists the port 4 pins and their corresponding register bits.
Table 9.7-2 Port 4 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
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9.7.1
MB90820B Series
Port 4 Registers (PDR4 and DDR4)
This section describes the port 4 registers.
■ Functions of Port 4 registers
● Port 4 data register (PDR4)
The PDR4 register indicates the state of each pin for port 4.
● Port 4 direction register (DDR4)
The DDR4 register specifies the direction of a data flow (input or output) at each pin (bit) of port 4. When
a DDR4 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR4 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, set the port direction register bit corresponding to each
resource input pin to “0” to place the port in input mode.
Table 9.7-3 lists the functions of the port 4 register.
Table 9.7-3 Port 4 register functions
Register name
Data
During
reading
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
Port 4 data
register (PDR4)
Port 4 direction
register (DDR4)
Read
/Write
Address
Initial value
R/W
000004H
XXXXXXXXB
R/W
000014H
00000000B
The output buffer is turned on to
place the port in output mode.
R/W : Readable and writable
X
208
: Undefined
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9.7.2
Operation of Port 4
This section describes the operation of port 4.
■ Operation of Port 4
● Port operation in output mode
• Setting a bit of the DDR4 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR4 register in output mode is held in the output latch of the PDR4 and output to
the port pins.
• The PDR4 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR4).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before switching
the mode for the bits from input to output, therefore, write output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR4 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high-impedance state.
• Data written to the PDR4 register in input mode is held in the output latch of the PDR4 but not output to
the port pins.
• The PDR4 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR4
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the corresponding bit in DDR4 register to "0" to place the
port in input mode.
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● Port operation after a reset
• When the MCU is reset, the DDR4 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input) and the pins are placed in a high-impedance state.
• The PDR4 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR4 register after the output data is set in the PDR4 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already 1 when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR4 register. Note that the inputs are fixed at"H" level or "L" level to prevent leakage due to an open
circuit.
Table 9.7-4 lists the states of the port 4 pins.
Table 9.7-4 States of port 4 pins
Pin
P40/PPG1 to P47/
PWO1
SPL
Normal operation
General-purpose I/O
port
Sleep mode
Stop mode or timebase timer mode
(SPL = 0)
General-purpose I/O port
General-purpose I/O
port
Stop mode or
time-base timer
mode (SPL = 1)
Input disabled/
output in Hi-Z
: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
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MB90820B Series
9.8
Port 5
Port 5 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function, also provides the configuration of port 5, lists of pins, shows
a block diagram of the pins, and describes the corresponding registers.
■ Port 5 Configuration
Port 5 consists of the following:
• General-purpose I/O pins/resources I/O pins (P50/PPG2 and P51/INT7)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
■ Port 5 Pins
The port 5 is also used as resource I/O pins. Therefore, the pins cannot be used as general-purpose I/O port
when they are used as resource I/O pins. Table 9.8-1 lists the port 5 pins.
Table 9.8-1 Port 5 pins
I/O form
Port
Pin
P50/PPG2
Port function
P50
Port 5
P51/INT7
P51
Generalpurpose I/O
Resource function
PPG2
PPG2 output
INT7
External interrupt
input
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 5 Pins
Figure 9.8-1shows the block diagram of P50/PPG2 pin.
Figure 9.8-1 Block diagram of P50/PPG2 pin
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 9.8-2shows the block diagram of P51/INT7 pin.
Figure 9.8-2 Block diagram of P51/INT7 pin
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
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When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR5 register.
■ Port 5 Registers
Port 5 registers are PDR5 and DDR5. The bits making up each register correspond to the port 5 pins on a
one-to-one basis. Table 9.8-2 lists the port 5 pins and their corresponding register bits.
Table 9.8-2 Port 5 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR5, DDR5
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
-
-
-
-
-
-
P51
P50
Port 5
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9.8.1
MB90820B Series
Port 5 Registers (PDR5 and DDR5)
This section describes the port 5 registers.
■ Functions of Port 5 registers
● Port 5 data register (PDR5)
The PDR5 register indicates the state of each pin for port 5.
● Port 5 direction register (DDR5)
The DDR5 register specifies the direction of a data flow (input or output) at each pin (bit) of port 5. When
a DDR5 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR5 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, set the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
Table 9.8-3 lists the functions of the port 5 registers.
Table 9.8-3 Port 5 register functions
Register name
Data
During
reading
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
Port 5 data
register (PDR5)
Port 5 direction
register (DDR5)
Read
/Write
Address
Initial value
R/W
000005H
XXXXXXXXB
R/W
000015H
XXXXXX00B
The output buffer is turned on to
place the port in output mode.
R/W : Readable and writable
X
214
: Undefined
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9.8.2
Operation of Port 5
This section describes the operation of port 5.
■ Operation of Port 5
● Port operation in output mode
• Setting a bit of the DDR5 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR5 register in output mode is held in the output latch of the PDR5 and output to
the port pins.
• The PDR5 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR5).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been specified
for output using the DDR register are not affected, but for the bits that have been specified for input,
a value input from the pins is written to the output latch and output as it is. Before switching the
mode for the bits from input to output, therefore, write output data to the PDR register, then specify
output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR5 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high-impedance state.
• Data written to the PDR5 register in input mode is held in the output latch of the PDR5 but not output to
the port pins.
• The PDR5 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR5
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the corresponding bit in DDR5 register to "0" to place the
port in input mode.
● Port operation after a reset
• When the MCU is reset, the DDR5 register is initialized to "0". As a result, the output buffer is turned
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off (I/O mode changes to input), and the pins are placed in a high-impedance state.
• The PDR5 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR5 register after the output data is set in the PDR5 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR5 register. Note that the inputs are fixed at "H"level or "L" level to prevent leakage due to an open
circuit. Table 9.8-4 lists the states of the port 5 pins.
Table 9.8-4 States of port 5 pins
Pin
Normal operation
Sleep mode
Stop mode or timebase timer mode
(SPL = 0)
Stop mode or time-base
timer mode (SPL = 1)
P50/PPG2
General-purpose
I/O port
General-purpose
I/O port
General-purpose I/O
port
Input disabled/output in
Hi-Z
P51/INT7
General-purpose
I/O port
General-purpose
I/O port
General-purpose I/O
port
Input enabled*/output in
Hi-Z
SPL
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
*
216
: Only when P51/INT7 are configured as external interrupt pins, otherwise, input is disabled.
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MB90820B Series
9.9
Port 6
Port 6 is a general-purpose I/O port. It can also be used for A/D converter analog input.
Individual port pin can be switched between the I/O port and A/D converter analog
input. This section focuses on the general I/O port function. It provides the
configuration of port 6, lists its pins, shows a block diagram of the pins, and describes
the corresponding registers.
■ Port 6 Configuration
Port 6 consists of the following:
• General-purpose I/O port/analog input pins (P60/AN0 to P67/AN7)
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Analog input enable register 0 (ADER0)
■ Port 6 Pins
The port 6 I/O is also used as analog input pins. Therefore, the pins cannot be used as general-purpose I/O
port pins when they are used as analog input pins. Table 9.9-1 lists the port 6 pins.
Table 9.9-1 Port 6 pins
I/O form
Port
Pin
Port function
Resource function
P60/AN0
P60
AN0
Analog input 0
P61/AN1
P61
AN1
Analog input 1
P62/AN2
P62
AN2
Analog input 2
P63/AN3
P63
AN3
Analog input 3
P64/AN4
P64
AN4
Analog input 4
P65/AN5
P65
AN5
Analog input 5
P66/AN6
P66
AN6
Analog input 6
P67/AN7
P67
AN7
Analog input 7
Port 6
Generalpurpose
I/O
Input
Output
Analog/
CMOS
CMOS
Circuit
type
H
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 6 Pins
Figure 9.9-1shows the block diagram of P60/AN0 to P67/AN7.
Figure 9.9-1 Block diagram of P60/AN0 to P67/AN7
Analog input
A/D converter channel selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
When the anlog input enable bit is set to enable, the port is forcibly caused to function as A/D converter
input pin regardless of the value in the DDR6 register.
■ Port 6 Registers
Port 6 registers are PDR6, DDR6, and ADER0. The bits making up PDR6, DDR6, and ADER0 registers
correspond to the port 6 pin on one-to-one basis. Table 9.9-2 lists the port 6 pins and their corresponding
register bits.
Table 9.9-2 Port 6 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR6, DDR6, ADER0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P67
P66
P65
P64
P63
P62
P61
P60
Port 6
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9.9.1
Port 6 Registers (PDR6, DDR6, and ADER0)
This section describes the port 6 registers.
■ Functions of Port 6 Registers
● Port 6 data register (PDR6)
The PDR6 register indicates the state of each pin for port 6.
● Port 6 direction register (DDR6)
The DDR6 register specifies the direction of a data flow (input or output) at each pin (bit) of port 6.
When a DDR6 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is 0,
the port (pin) is set as an input port.
Notes:
• When A/D input enable bit is set, the corresponding port functions as A/D converter input pins
regardless of the value in the DDR6 register.
• To use as general-purpose I/O port, set the corresponding A/D converter input enable register bit
to "0" to place the port in general-purpose I/O mode.
● Analog input enable register 0 (ADER0)
Each bit of the ADER0 register specifies whether the corresponding port 6 pin is to be used as a generalpurpose I/O port or an analog input pin. Setting an ADE bit to "1" enables the corresponding pin for analog
input. Setting the bit to 0 enables the pin for general-purpose I/O.
Note :
If a signal at an intermediate level is input in port I/O mode, input leak current flows. Therefore, for a
pin used for analog input, be sure to set the corresponding ADE bits to "1".
Reference:
When the MCU is reset, the DDR6 register is cleared to "0" and the ADER0 register is set to "1"
(used as the analog input).
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Table 9.9-3 lists the functions of the port 6 registers.
Table 9.9-3 Port 6 register functions
Register
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
0
Port I/O mode
1
Analog input mode
Port 6 data
register (PDR6)
Port 6 direction
register (DDR6)
A/D input enable
register 0
(ADER0)
During
reading
Data
Read
/Write
Address
Initial value
R/W
000006H
XXXXXXXXB
R/W
000016H
00000000B
R/W
0000C5H
11111111B
The output buffer is turned on to
place the port in output mode.
R/W : Readable and writable
X
220
: Undefined
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9.9.2
Operation of Port 6
This section describes the operation of port 6.
■ Operation of Port 6
● Port operation in output mode
• Setting a bit of the ADER0 register to "0" places the corresponding port pin in port I/O mode.
• Setting a bit of the DDR6 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR6 register in output mode is held in the output latch of the PDR6 and output to
the port pins.
• The PDR6 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR6).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write output data to the PDR register,
then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the ADER0 register to "0" places the corresponding port pin in port I/O mode.
• Setting a bit of the DDR6 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high-impedance state.
• Data written to the PDR6 register in input mode is held in the output latch of the PDR6 but not output to
the port pins.
• The PDR6 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for analog input
To use a port pin for analog input, write "1" to the corresponding ADE bit. Doing so disables the pin from
operating as a general-purpose port pin and enables it to function as an analog input pin. When PDR6
register is accessed in read mode in this situation, a value of "0" is read.
● Port operation after a reset
• When the MCU is reset, the DDR6 register is initialized to "0" and the ADER0 register is initialized to
"1" to place the port in analog input mode. To use the port as a general-purpose port, write "0" to the
ADER0 register in advance to place the port in port I/O mode.
• When the MCU is reset, the DDR6 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high-impedance state.
• The PDR6 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR6 register after the output data is set in the PDR6 register.
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● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR6 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit.
Table 9.9-4 lists the states of the port 6 pins.
Table 9.9-4 States of port 6 pins
Pin
P60/AN0 to
P67/AN7
SPL
Normal operation
Sleep mode
Stop mode or time-base
timer mode (SPL = 0)
Stop mode or time-base
timer mode (SPL = 1)
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O port
Input disabled/output in
Hi-Z
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
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MB90820B Series
9.10
Port 7
Port 7 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function. It provides the configuration of port 7, lists its pins, shows a
block diagram of the pins, and describes the corresponding registers.
■ Port 7 Configuration
Port 7 consists of the following:
• General-purpose I/O pins/resource I/O pins (P70/DA0/AN8 to P77/IN1/AN15)
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Analog input enable register 1 (ADER1)
■ Port 7 Pins
The port 7 I/O is also used as resource I/O pins. Therefore, the pins cannot be used as general-purpose I/O
port when they are used as resource I/O pins. Table 9.10-1 lists the port 7 pins.
Table 9.10-1 Port 7 pins
I/O form
Port
Pin
Port function
Resource function
Input
P70/DA0/
AN8
P70
DA0/
AN8
D/A converter output 0 /
A/D converter channel 8 input
P71/DA1/
AN9
P71
DA1/
AN9
D/A converter output 1 /
A/D converter channel 9 input
P72/SIN1/
AN10
P72
SIN1/
AN10
UART1 data input /
A/D converter channel 10
input
P73/SOT1/
AN11
P73
SOT1/
AN11
UART1 data output /
A/D converter channel 11
input
SCK1/
AN12
UART1 serial clock input /
A/D converter channel 12
input
Output
Circuit
type
I
Port 7
Generalpurpose I/O
P74/SCK1/
AN12
P74
P75/
FRCK/
AN13
P75
FRCK/
AN13
Free-run timer clock input /
A/D converter channel 13
input
P76/IN0/
AN14
P76
IN0/
AN14
Input capture channel 0 input /
A/D converter channel 14
input
P77/IN1/
AN15
P77
IN1/
AN15
Input capture channel 1 input /
A/D converter channel 15
input
J
CMOS
(hysteresis)/
Analog
CMOS
K
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 7 Pins
Figure 9.10-1shows the block diagram of P70/DA0/AN8 and P71/DA1/AN9 pins.
Figure 9.10-1 Block diagram of P70/DA0/AN8 and P71/DA1/AN9 pins
A/D converter channel selection bit/
A/D converter input
Internal data bus
Port data register (PDR)
D/A converter output
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
DA converter output enable bit
When the D/A converter output enable bit or analog input enable bit is set to enable, the port is forcibly
caused to function as D/A converter output pin or A/D converter input pin regardless of the value in the
DDR7 register.
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Figure 9.10-2 shows the block diagram of P72/SIN1/AN10 pin.
Figure 9.10-2 Block diagram of P72/SIN1/AN10 pin
A/D converter channel selection bit
A/D converter input
UART1 data input
UART1 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
When analog input enable bit is set to enable, the port is forcibly caused to function as A/D converter input
pin regardless of the value in the DDR7 register.
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Figure 9.10-3 shows the block diagram of port 7 (P73/SOT1/AN11 to P74/SCK1/AN12) pins.
Figure 9.10-3 Block diagram of P73/SOT1/AN11 to P74/SCK1/AN12 pins
A/D converter input
A/D converter channel selection bit
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
When the resource output enable bit is set to enable, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR7 register.
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Figure 9.10-4 shows the block diagram of P75/FRCK/AN13 to P77/IN1/AN15 pins.
Figure 9.10-4 Block diagram of P75/FRCK/AN13 to P77/IN1/AN15 pins
A/D converter input
A/D converter channel selection bit
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
■ Port 7 Registers
Port 7 registers are PDR7, DDR7, and ADER1. The bits making up each register correspond to the port 7
pins on a one-to-one basis. Table 9.10-2 lists the port 7 pins and their corresponding register bits.
Table 9.10-2 Port 7 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR7, DDR7
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ADER1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
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9.10.1
MB90820B Series
Port 7 Registers (PDR7, DDR7, and ADER1)
This section describes the port 7 registers.
■ Functions of Port 7 Registers
● Port 7 data register (PDR7)
The PDR7 register indicates the state of each pin for port 7.
● Port 7 direction register (DDR7)
The DDR7 register specifies the direction of a data flow (input or output) at each pin (bit) of port 7. When
a DDR7 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Notes:
• When D/A converter output enable bit or A/D input enable bit is set, the corresponding port
functions as D/A converter output pin or A/D converter input pin regardless of the value in the
DDR7 register.
• To use as general-purpose I/O port, set the corresponding A/D converter input enable register bit
to “0” to place the port in general-purpose I/O mode.
● Analog input enable register 1 (ADER1)
Each bit of the ADER1 register specifies whether the corresponding port 7 pin is to be used as a generalpurpose I/O port or an analog input pin. Setting an ADE bit to "1" enables the corresponding pin for analog
input. Setting the bit to "0" enables the pin for general-purpose I/O.
Note:
If a signal at an intermediate level is input in port I/O mode, input leak current flows. Therefore, for a
pin used for analog input, be sure to set the corresponding ADE bits to “1”.
Reference:
When the MCU is reset, the DDR7 register is cleared to “0” and the ADER1 register is set to “1”
(used as the analog input).
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Table 9.10-3 lists the functions of the port 7 registers.
Table 9.10-3 Port 7 register functions
Register
During writing
0
The pin is
at the "L"
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "L" level.
1
The pin is
at the "H"
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the "H" level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
0
Port I/O mode
1
Analog input mode
Port 7 data
register (PDR7)
Port 7 direction
register (DDR7)
A/D input enable
register 1
(ADER1)
During
reading
Data
Read
/Write
Address
Initial value
R/W
000007H
XXXXXXXXB
R/W
000017H
00000000B
R/W
0000D0H
11111111B
The output buffer is turned on to
place the port in output mode.
R/W : Readable and writable
X
: Undefined
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9.10.2
MB90820B Series
Operation of Port 7
This section describes the operation of port 7.
■ Operation of Port 7
● Port operation in output mode
• Setting a bit of the ADER1 register to "0" places the corresponding port pin in port I/O mode.
• Setting a bit of the DDR7 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR7 register in output mode is held in the output latch of the PDR7 and output to
the port pins.
• The PDR7 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR7).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as it is. Before
switching the mode for the bits from input to output, therefore, write output data to the PDR register,
then specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the ADER1 register to "0" places the corresponding port pin in port I/O mode.
• Setting a bit of the DDR7 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high-impedance state.
• Data written to the PDR7 register in input mode is held in the output latch of the PDR7 but not output to
the port pins.
• The PDR7 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for analog input
To use a port pin for analog input, write "1" to the corresponding ADE bit. Doing so disables the pin from
operating as a general-purpose port pin and enables it to function as an analog input pin. When PDR7
register is accessed in read mode in this situation, a value of "0" is read.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR7
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
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● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the DDR7 register to "0" to place the port in input mode.
● Port operation after a reset
• When the MCU is reset, the DDR7 register is initialized to "0" and the ADER1 register is initialized to
"1" to place the port in analog input mode. To use the port as a general-purpose port, write "0" to the
ADER1 register in advance to place the port in port I/O mode.
• When the MCU is reset, the DDR7 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high-impedance state.
• The PDR7 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR7 register after the output data is set in the PDR7 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR7 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.10-4 lists the states of the port 7 pins.
Table 9.10-4 States of port 7 pins
Pin
P70/DA0/AN8 to
P77/IN1/AN15
SPL
Normal operation
General-purpose
I/O port
Sleep mode
General-purpose
I/O port
Stop mode or timebase timer mode
(SPL = 0)
Stop mode or time-base
timer mode (SPL = 1)
General-purpose I/O
port
Input disabled/output in
Hi-Z
: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z : High impedance
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9.11
MB90820B Series
Port 8
Port 8 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function. This section also provides the configuration of port 8, lists its
pins, shows a block diagram of the pins, and describes the corresponding registers.
■ Port 8 Configuration
Port 8 consists of the following:
• General-purpose I/O pins/resource I/O pins (P80/IN2 to P87/RTO5)
• Port 8 data register (PDR8)
• Port 8 direction register (DDR8)
■ Port 8 Pins
The port 8 I/O is also used as resource I/O pins. Therefore, the pins cannot be used as general-purpose I/O
port when they are used as resource I/O pins. Table 9.11-1 lists the port 8 pins.
Table 9.11-1 Port 8 pins
I/O form
Port
Pin
Port function
Resource function
Input
P80/IN2
P80
IN2
Input capture channel 2
P81/IN3
P81
IN3
Input capture channel 3
P82/RTO0
P82
RTO0
Waveform generator output 0
P83/RTO1
P83
RTO1
Waveform generator output 1
P84/RTO2
P84
RTO2
Waveform generator output 2
P85/RTO3
P85
RTO3
Waveform generator output 3
P86/RTO4
P86
RTO4
Waveform generator output 4
P87/RTO5
P87
RTO5
Waveform generator output 5
Output
Circuit
type
F
Port 8
Generalpurpose I/O
CMOS
(hysteresis)
CMOS
L
See Section "1.7 I/O Circuit Types", for information on the circuit types.
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■ Block Diagram of Port 8 Pins
Figure 9.11-1 shows the block diagram of P80/IN2 and P81/IN3 pins.
Figure 9.11-1 Block diagram of P80/IN2 and P81/IN3 pins
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 9.11-2 shows the block diagram of P82/RTO0 to P87/RTO5 pins.
Figure 9.11-2 Block diagram of P82/RTO0 to P87/RTO5 pins
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pin
regardless of the value in the DDR8 register.
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■ Port 8 Registers
Port 8 registers are PDR8 and DDR8. The bits making up each register correspond to the port 8 pins on a
one-to-one basis. Table 9.11-2 lists the port 8 pins and their corresponding register bits.
Table 9.11-2 Port 8 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR8, DDR8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P87
P86
P85
P84
P83
P82
P81
P80
Port 8
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MB90820B Series
9.11.1
Port 8 Registers (PDR8 and DDR8)
This section describes the port 8 registers.
■ Functions of Port 8 registers
● Port 8 data register (PDR8)
The PDR8 register indicates the state of each pin for port 8.
● Port 8 direction register (DDR8)
The DDR8 register specifies the direction of a data flow (input or output) at each pin (bit) of port 8. When a
DDR8 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port
(pin) is set as an input port.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR8 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, set the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
Table 9.11-3 lists the functions of the port 8 registers.
Table 9.11-3 Port 8 register functions
Register name
Data
During
reading
During writing
0
The pin is at
the "L" level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the "“L" level.
Port 8 data
register (PDR8)
1
The pin is at
the "H" level.
The output buffer is turned off to
place the port in input mode.
0
The direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The direction
latch is "1".
The output buffer is turned off to
place the port in input mode.
Port 8 direction
register (DDR8)
Read
/Write
Address
Initial value
R/W
000008H
XXXXXXXXB
R/W
000018H
00000000B
R/W : Readable and writable
X
: Undefined
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CHAPTER 9 I/O PORTS
9.11
9.11.2
MB90820B Series
Operation of Port 8
This section describes the operation of port 8.
■ Operation of Port 8
● Port operation in output mode
• Setting a bit of the DDR8 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR8 register in output mode is held in the output latch of the PDR8 and output to
the port pins.
• The PDR8 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR8).
Note :
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been specified
for output using the DDR register are not affected, but for the bits that have been specified for input,
a value input from the pins is written to the output latch and output as it is. Before switching the
mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Setting a bit of the DDR8 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high-impedance state.
• Data written to the PDR8 register in input mode is held in the output latch of the PDR8 but not output to
the port pins.
• The PDR8 register can be accessed in read mode to read the level value ("0" or "1") at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR8
register bit is "1", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, set the PDR8 register to "0" to place the port in input mode.
● Port operation after a reset
• When the MCU is reset, the DDR8 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high-impedance state.
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• The PDR8 register is not initialized when the MCU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR8 register after the output data is set in the PDR8 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
PDR8 register. Note that the inputs are fixed at "H" level or "L" level to prevent leakage due to an open
circuit. Table 9.11-4 lists the states of the port 8 pins.
Table 9.11-4 States of port 8 pins
Pin
P80/IN2 to P87/
RTO5
SPL
Normal operation
General-purpose I/O
port
Sleep mode
Stop mode or timebase timer mode
(SPL = 0)
General-purpose I/O port
General-purpose I/O
port
Stop mode or
time-base timer
mode (SPL = 1)
Input disabled/
output in Hi-Z
: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
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CHAPTER 10
TIME-BASE TIMER
This chapter describes the functions and operation of
the time-base timer.
10.1 Overview of the Time-base Timer
10.2 Configuration of the Time-base Timer
10.3 Time-base Timer Control Register (TBTC)
10.4 Time-base Timer Interrupts
10.5 Operation of the Time-base Timer
10.6 Usage Notes on the Time-base Timer
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CHAPTER 10 TIME-BASE TIMER
10.1
10.1
MB90820B Series
Overview of the Time-base Timer
The time-base timer is an 18-bit free-run counter (time-base counter) that counts up in
synchronization with the internal count clock (one-half of the source oscillation). The
timer has an interval timer function that can select four interval times.
The time-base timer also has functions for timer of the oscillation stabilization wait time
and for supplying the clocks for the watchdog timer.
■ Interval Timer Function
The interval timer function repeatedly generates an interrupt request at a given interval.
• An interrupt request is generated when the interval timer bit for the time-base counter overflows.
The interval time bit (interval) can be selected from four types. Table 9.1-1 lists the interval time for the
time-base timer.
Table 10.1-1 Interval time for the time-base timer
Internal count clock cycle
Interval time
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
2 / HCLK (0.5 µs)
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock frequency
Values in parentheses are for a 4 MHz oscillation clock frequency.
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MB90820B Series
■ Clock Supply Function
The clock supply function supplies clocks to the oscillation stabilization wait time timer and to some
peripheral functions.
Table 9.1-2 lists the cycle times of clocks supplied from the time-base timer to each peripheral.
Table 10.1-2 Clock cycle time supplied from the time-base timer
Clock supply
destination
Clock cycle time
213 / HCLK (Approx. 2.0 ms)
Oscillation
stabilzation wait
time
215 / HCLK (Approx. 8.2 ms)
218 / HCLK (Approx. 65.4 ms)
Remarks
Oscillation stabilization wait time for ceramic
vibrator
Oscillation stabilization wait time for crystal
vibrator
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
Watchdog timer
Count-up clock for watchdog timer
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock frequency
Values in parentheses occurs during operation of the 4 MHz oscillation clock frequency.
Reference:
The oscillation stabilization wait time is the yardstick because the oscillation cycle time is unstable as
soon as oscillation starts.
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CHAPTER 10 TIME-BASE TIMER
10.2
10.2
MB90820B Series
Configuration of the Time-base Timer
The time-base timer consists of the following four blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of the Time-base Timer
Figure 9.2-1 shows the block diagram of the time-base timer.
Figure 10.2-1 Block diagram of the time-base timer
To watchdog timer
Time-base
timer counter
Divide-by
-two HCLK
×21 ×22
×23
...
...
×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
OF
OF
OF
Counter
clear circuit
TBOF clear
OF
⎞ To the oscillation
⎟ setting time selector in the clock con⎠ trol section
Counter clear
Power-on reset
Stop mode start
CKSCR: MCS = 1 to 0(*1)
OF
Interval
timer selector
TBOF set
Time-base timer
interrupt signal
#36 (24H)(*2)
—
—
—
TBIE TBOF
OF:Overflow
HCLK: Oscillation clock
*1 Switching of the machine clock from the oscillation clock to the PLL clock
*2 Interrupt number
TBR TBC1 TBC0
Time-base timer control
register (TBTC)
● Time-base timer counter
This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count clock.
● Counter clear circuit
Used to clear the counter by writing "0" to the TBTC:TBR bit, by a power-on reset, or by transition to stop
mode (LPMCR: STP = 1).
● Interval timer selector
Selects one of four outputs for the time-base timer counter. An overflow of the selected bit becomes an
interrupt cause.
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MB90820B Series
● Time-base timer control register (TBTC)
Selects the interval time, clears the counter of the time-base timer, controls an interrupt request, and checks
the status.
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CHAPTER 10 TIME-BASE TIMER
10.3
10.3
MB90820B Series
Time-base Timer Control Register (TBTC)
The time-base timer control register (TBTC) selects the interval time, clears the counter,
controls interrupts, and checks the status.
■ Time-base Timer Control Register (TBTC)
Figure 10.3-1 Time-base timer control register (TBTC)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
Address
0000A9H
bit8
RESV
-
-
TBIE TBOF TBR TBC1 TBC0
R/W
-
-
R/W
R/W
W
R/W
bit7
bit0
Initial value
(WDTC)
1XX00100B
R/W
bit 9 bit 8
TBC1 TBC0
Interval time selection bit
0
0
212/HCLK (Approx. 1.0 ms)
0
1
214/HCLK (Approx. 4.1 ms)
1
0
216/HCLK (Approx. 16.4 ms)
1
1
219/HCLK (Approx. 131 ms)
Values in parentheses are for a 4 MHz oscillation clock frequency.
bit 10
Time-base timer initialization bit
TBR
During reading
During writing
Clearing of the time-base timer
counter and TBOF bit
0
-
1
The read value is always 1.
No change, no effect on other bits.
bit 11
TBOF
Interrupt request flag bit
During reading
During writing
0
No overflow from the
specified bit
Clearing of this bit
1
Overflow from the specified
bit
No change, no effect on other bits.
bit 12
TBIE
Interrupt request enable bit
0
Interrupt request output disabled
1
Interrupt request output enabled
bit 15
RESV
Reserved bit
Always write 1 to this bit.
R/W:
W:
-:
x:
244
Readable/writable
Write only
Undefined
Undefined
Initial value
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CHAPTER 10 TIME-BASE TIMER
10.3
MB90820B Series
Table 10.3-1 Function description of each bit in the time-base timer control register (TBTC)
Bit name
Function
bit15
RESV:
Reserved bit
Note :
Always write "1" to this bit.
bit14,
bit13
Not used bits
•
•
When read, the value is undefined.
Writing has no effect on operation.
bit12
TBIE:
Interrupt request
enable bit
•
•
Used to enable or disable an interrupt request to the CPU.
When this bit and the interrupt request flag bit (TBOF) are "1", an
interrupt request is output.
•
bit11
CM44-10147-2E
TBOF:
Interrupt request flag
bit
bit10
TBR:
Time-base timer
initialization bit
bit9,
bit8
TBC1, TBC0:
Interval time
selection bit
This bit is set to "1" when the bit specifying the time-base timer
counter overflows.
• When this bit and the interrupt request enable bit (TBIE) are "1",
an interrupt request is generated.
• During writing, this bit is cleared with "0". If "1" is written, the
bit does not change and there is no effect.
Note :
- To clear the TBOF bit, disable the time-base timer interrupt
by specifying the TBIE bit or ILM bit of processor status
(PS).
- The TBOF bit is cleared by writing "0", by a transition to stop
mode, by clearing of the time-base timer with the TBR bit, or
by a reset.
•
•
Used to clear the time-base timer counter.
When "0" is written to this bit, the counter is cleared and the
TBOF bit is cleared. If "1" is written, the bit does not change and
there is no effect.
Reference:
The read value is always "1".
•
•
•
Used to select an interval time.
The bit for the interval timer of the time-base timer time is
specified.
Four types of interval time can be selected.
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CHAPTER 10 TIME-BASE TIMER
10.4
10.4
MB90820B Series
Time-base Timer Interrupts
The time-base timer can generate an interrupt request when the bit specifying the timebase timer counter overflows.
■ Time-base Timer Interrupts
The interrupt request flag bit (TBTC: TBOF) is set to "1" when the time-base timer counter counts up with
the internal count clock and when the selected interval timer bit overflows. In this case, if the interrupt
request enable bit has been enabled (TBTC: TBIE = 1), an interrupt request (#36) is generated in the CPU.
Write "0" to the TBOF bit in the interrupt handling routine to clear the interrupt request. When the
specified bit overflows, the TBOF bit is set to "1" regardless of the TBIE bit value.
Note :
Clear the interrupt request flag bit (TBTC: TBOF) while a time-base timer interrupt is disabled by
setting the TBIE bit or ILM bit of the processor status (PS).
Reference:
When the TBOF bit is "1", if the TBIE bit status is switched from disable to enable (0 → 1), an
interrupt request occurs immediately.
■ Time-base Timer Interrupts and EI2OS
Table 9.4-1 lists the time-base timer interrupt and EI2OS.
Table 10.4-1 Time-base timer interrupts and EI2OS
Interrupt
number
#36 (24H)
Interrupt level setting
register
Vector table address
EI2OS
Register name
Address
Lower
Medium
Upper
ICR12
0000BCH
FFFF6CH
FFFF6DH
FFFF6EH
∆
∆: Usable when an interrupt cause that shares the ICR is not used.
Note :
ICR12 is common to the time-base timer interrupt and input capture channels 2/3 interrupt.
Interrupts can be used for two applications, but the interrupt level is the same.
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10.5
MB90820B Series
10.5
Operation of the Time-base Timer
The time-base timer provides the interval timer function and the clock supply function
that supplies clocks to some peripheral functions.
■ Operation of the Interval Timer Function (Time-base Timer)
The interval timer function generates an interrupt request for each interval.
The setting in Figure 9.5-1 is required to all the timer to operate as an interval timer.
Figure 10.5-1 Setting of the time-base timer
TBTC
bit15
RESV
1
bit14
−
bit13
−
bit12
TBIE
bit11
TBOF
0
bit10
TBR
0
bit9
TBC1
bit8
TBC0
bit7
bit0
(WDTC)
: Used
0: Set 0.
1: Set 1.
• The time-base timer counter continues counting up in synchronization with the internal count clock
(one-half of the oscillation clock) as long as the clock is being oscillated.
• When the counter is cleared (TBR = 0), it counts up from "0". When the interval timer bit overflows,
the interrupt request flag bit (TBOF) is set to"1". At this time, if interrupt request output has been
enabled (TBIE = 1), an interrupt is generated for each selected interval based on the cleared time.
• The interval time may become longer than the time set because of time-base timer clearing.
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CHAPTER 10 TIME-BASE TIMER
10.5
MB90820B Series
■ Oscillation Stabilizationi Time Timer Function
The time-base timer is also used as the oscillation wait time timer for oscillation and the PLL clocks.
The oscillation stabilization time is set for the interval time from the time the counter counts up from "0"
(count clear) until the oscillation wait time bit overflows. When control returns from time-base timer mode
to PLL clock mode, the oscillation wait time starts from the middle of counting because the time-base timer
counter has not been cleared. Table 9.5-1 shows the clearing of the time-base counter and the oscillation
wait times.
Table 10.5-1 Time-base timer counter clearing and stabilization wait times
Counter
clear
TBOF
clear
Oscillation stabilization wait time
O
O
-
O
O
Oscillation clock oscillation stabilization wait
time
Releasing of stop mode
O
O
Oscillation clock oscillation stabilization wait
time (at return to main clock mode)
Transition from oscillation
clock mode to PLL clock
mode (MCS = 1 → 0)
O
O
PLL clock oscillation stabilization wait time
Releasing of time-base
timer mode
X
X
PLL clock oscillation stabilization wait time (at
return to PLL clock mode)
Releasing of sleep mode
X
X
Not available
Operation
TBTC: Writing of "0" to
TBR
Power-on reset
Watchdog reset
O: Available
X: Not available
■ Supply of Operation Clock
The time-base timer supplies clocks to the watchdog timer. Clearing of the time-base counter affects
operation of the watchdog timer.
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CHAPTER 10 TIME-BASE TIMER
10.6
MB90820B Series
10.6
Usage Notes on the Time-base Timer
Notes about the effects on peripheral functions of clearing interrupt requests and the
time-base timer counter are given below.
■ Time-base Timer Usage Notes
● Clearing interrupt requests
The TBOF bit of the time-base timer control register must be cleared while a time-base timer interrupt is
masked by the TBIE bit or the interrupt level mask register (ILM) of the processor status (PS).
● Effects of time-base timer clearing
Clearing of the time-base timer counter affects the following operations:
• When the time-base timer is using the interval timer function (interval interrupt)
• When the watchdog timer is being used
● Use of the time-base timer as the oscillation stabilization wait time timer
At power-on, the source oscillation of the main clock stops in main stop mode. After oscillator operation
starts, the operating clock supplied by the time-base timer is used to take the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected based on the
type of oscillating element connected to the main clock oscillator (clock generation section). See Section
"4.5 Oscillation Stabilization Wait Interval", for details.
● Notes on peripheral functions to which clocks are supplied from the time-base timer
In the mode in which the main clock source oscillation stops, the time-base timer counter is cleared and
time-base timer operation stops. When the time-base timer counter is cleared, the clock supplied from the
time-base timer is supplied from its initial state. As a result, the "H" level is shortened and the "L" level
lengthened 1/2 cycle. Although the clock for the watchdog timer is also supplied from its initial state; the
watchdog timer operates in normal cycles because the watchdog timer counter is cleared at the same time
as the time-base timer counter is cleared.
■ Operation of the Time-base Timer
The following operations are shown in Figure 9.6-1:
• A power-on reset occurs.
• Sleep mode is entered during operation of the interval timer function.
• A counter clear request is issued.
When stop mode is entered, the time-base timer is cleared and its operation stops. On return from stop
mode, the time-base timer immediately counts the oscillation stabilization wait time.
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CHAPTER 10 TIME-BASE TIMER
10.6
MB90820B Series
Figure 10.6-1 Time-base timer operations
Counter value
3FFFFH
Cleared by transition to
stop mode.
Oscillation stabilization
delay overflow
00000H
CPU operation starts
Power-on reset
(optional)
Counter clear
(TBTC: TBR = 0)
Interval cycle
(TBTC: TBC1, TBC0 = 11B)
Cleared by the interrupt
handling routine.
TBOF bit
Sleep mode
TBIE bit
SLP bit
(LPMCR register)
Stop
Releasing of sleep by interval interrupt
STP bit
(LPMCR register)
Releasing of stop by an external interrupt
When 11B has been set in the interval selection bit
(TBTC:TBC1 and TBC0) of the time-base timer control register
: Indicates the oscillation stabilization wait time.
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CHAPTER 11
WATCHDOG TIMER
This chapter describes the functions and operation of
the watchdog timer.
11.1 Overview of the Watchdog Timer
11.2 Configuration of the Watchdog Timer
11.3 Watchdog Timer Control Register (WDTC)
11.4 Operation of the Watchdog Timer
11.5 Usage Notes on the Watchdog Timer
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CHAPTER 11 WATCHDOG TIMER
11.1
11.1
MB90820B Series
Overview of the Watchdog Timer
The watchdog timer is a 2-bit counter that uses the time-base timer supply clock as the
count clock. After activation, if the watchdog timer is not cleared within a given time,
the CPU is reset.
■ Watchdog Timer Function
The watchdog timer is a counter for handling program crashes. Once the watchdog timer is activated, it
must be regularly cleared within a given time. If the program results in an endless loop and the watchdog
timer is not cleared over a given time, a watchdog reset is generated for the CPU.
Table 10.1-1 lists the watchdog timer interval times. If the watchdog timer is not cleared, a watchdog reset
is generated between the minimum time and maximum time. Clear the counter within the minimum time
listed in this table.
Table 11.1-1 Interval times for the watchdog timer
Interval time
Minimum*
Maximum*
Oscillation clock cycle count
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215
Approx. 458.75 ms
Approx. 589.82 ms
221 ±218
* Value during operation of the 4 MHz oscillation clock frequency
The maximum and minimum watchdog timer interval times and the oscillation clock cycle count depend on
the clear timing of the watchdog timer.
The interval time is 3.5 to 4.5 times longer than the cycle of the count clock (time-base timer supply clock).
See Section "11.4 Operation of the Watchdog Timer".
Note :
The watchdog timer consists of a 2-bit counter that uses the carry signals of the time-base timer as
count clocks. Therefore, if the time-base timer is cleared, the watchdog reset generation time may
become longer than the time set.
Reference:
At activation, the watchdog timer is initialized by a power-on or watchdog reset and is placed in
stopped status. The watchdog timer is cleared by an external pin reset, software reset, writing to the
WTE bit (watchdog timer control register), transition to sleep mode or stop mode. However, It is not
stopped.
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CHAPTER 11 WATCHDOG TIMER
11.2
MB90820B Series
11.2
Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of the Watchdog Timer
Figure 10.2-1 shows the block diagram of the watchdog timer.
Figure 11.2-1 Block diagram of the watchdog timer
Watchdog timer control register (WDTC)
PONR
-
WRST ERST SRST WTE
Watchdog timer
WT1
WT0
2
Activation
with clear
Start of sleep mode
Start of hold status
Start of stop mode
Counter
clear control
circuit
Count
clock
selector
2-bit
counter
Overflow
clear
Watchdog
reset generator
To the internal
reset generator
CLR
Clear
4
(Time-base timer counter)
One-half of HCLK
×21 ×22 … ×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
HCLK: Oscillation clock
● Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of time-base timer
outputs. This determines the watchdog reset generation time.
● Watchdog counter (2-bit counter)
This 2-bit up counter uses the time-base timer output as the count clock.
● Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
● Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
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MB90820B Series
● Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
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CHAPTER 11 WATCHDOG TIMER
11.3
MB90820B Series
11.3
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates and clears the watchdog timer
and displays the reset cause.
■ Watchdog Timer Control Register (WDTC)
Figure 10.3-1 shows the watchdog timer control register (WDTC). Table 10.3-1 describes the function of
each bit in the watchdog timer control register (WDTC).
Figure 11.3-1 Watchdog timer control register (WDTC)
bit15
Address
0000A8H
bit8 bit7
(TBTC)
bit6
PONR
-*
R
-*
bit5
bit4
bit3
bit2
WRST ERST SRST WTE
R
R
R
bit 1
bit 0
bit1
bit0
WT1
WT0
W
W
W
Initial value
XXXXX111B
Interval time selection bit (for 4 MHz HCLK)
WT1
Interval time
WT0
Minimum
Maximum
Oscillation clock
cycle count
0
0
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211
0
1
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213
1
0
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215
1
1
Approx. 458.75 ms Approx. 589.82 ms
HCLK: Oscillation clock
bit 2
Watchdog timer control bit
WTE
0
- Activation of the watchdog timer
(At first write after reset)
- Clearing of the watchdog timer
(At second or subsequent write after reset)
1
No operation
bit 7
221 ±218
bit 5
bit 4
bit 3
Reset cause flag bit
Reset cause
PONR WRST ERST SRST
R: Read only
W: Write only
X: Undefined bit
*: Retains the previous status.
: Initial value
1
X
X
X
Power-on reset
*
*
1
*
*
Watchdog timer reset
*
1
*
*
External pin (RST input)
*
*
1
RST bit (software reset)
The interval time becomes 3.5 to 4.5 times longer than the count clock (time-base timer output value)
cycle. For details, see Section "11.4 Operation of the Watchdog Timer".
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11.3
MB90820B Series
Table 11.3-1 Function description of each bit in the watchdog timer control register
(WDTC)
Bit name
Function
•
bit7
to
bit3
PONR, WRST,
ERST, SRST:
Reset cause bits
bit6
unused
bit2
WTE:
Watchdog timer
control bit
bit1,
bit0
256
WT1, WT0:
Interval time
selection bits
•
•
Read-only bits for indicating the reset cause. If more than one
reset cause occurs, the bit for each reset cause occurring is set to
"1".
These bits are all cleared to "0" after the watchdog timer control
register (WDTC) is read.
At power-on, the contents of the bits other than the PONR bit are
not guaranteed. Therefore, when the PONR bit is "1", ignore the
contents of the bits other than the PONR bit.
•
When read, the value is undefined. Writing has no effect on
operation.
•
When" 0" is written to this bit, the watchdog timer is activated
(first write after reset) or the 2-bit counter is cleared (second or
subsequent write after reset).
Writing "1" does not affect operation.
•
•
•
•
Used to select the watchdog timer interval time.
Only data at watchdog timer activation is valid.
Data written after watchdog timer activation is ignored.
These bits are write-only.
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CHAPTER 11 WATCHDOG TIMER
11.4
MB90820B Series
11.4
Operation of the Watchdog Timer
The watchdog timer generates a watchdog reset by an overflow of the watchdog
counter.
■ Watchdog Timer Operation
Operation of the watchdog timer requires the setting in Figure 10.4-1.
Figure 11.4-1 Setting of the watchdog timer
bit15
WDTC
bit8
TBTC
bit7
PONR
bit6
−
bit5
bit4
WRST ERST
bit3
SRST
bit2
WTE
0
bit1
WT1
bit0
WT0
: Used
0: Set 0
1: Set 1
● Activating the watchdog timer
• The watchdog timer is activated when the first "0" after reset is written to the WTE bit of the watchdog
timer control register (WDTC). Specify the interval time by specifying the WT1 and WT0 bits of the
watchdog timer control register at the same time.
• When watchdog timer activation starts, it can be stopped only by a power-on or its own reset.
● Clearing the watchdog timer
• When a second or subsequent "0" is written to the WTE bit, the 2-bit counter of the watchdog timer is
cleared. If the counter is not cleared within the specified interval time, it overflows and a watchdog
reset occurs.
• The watchdog counter is cleared by reset generation, transition to sleep mode, stop mode, or clock
mode.
● Intervals for the watchdog timer
Figure 10.4-2 shows the relationship between the clear timing of the watchdog timer and interval times.
The interval time changes according to the clear timing of the watchdog timer and requires 3.5 to 4.5 times
longer than the count clock cycle.
● Checking a reset cause
A reset cause can be determined by checking the PONR, WRST, ERST, and SRST bits of the watchdog
timer control register (WDTC) after a reset.
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CHAPTER 11 WATCHDOG TIMER
11.4
MB90820B Series
Figure 11.4-2 Clear timing and interval times of watchdog timer
[Watchdog timer block diagram]
2-bit counter
Clock
selector
Divide-bytwo circuit
Divide-bytwo circuit
Reset
circuit
Reset signal
Count enabling and clearing
WTE bit
Count enable
output circuit
[Minimum interval time] When the WTE bit is cleared immediately before the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
7 x (count clock cycle/2)
WTE bit clearing
Watchdog reset generation
[Maximum interval time] When the WTE bit is cleared immediately after the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
9 x (count clock cycle/2)
WTE bit clearing
258
Watchdog reset generation
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CHAPTER 11 WATCHDOG TIMER
11.5
MB90820B Series
11.5
Usage Notes on the Watchdog Timer
Notes on using the watchdog timer are given below.
■ Usage Notes on the Watchdog Timer
● Stopping the watchdog timer
Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. The
watchdog timer counter is cleared by an external reset or software reset; however, the watchdog timer does
not stop.
● Interval times
Since a carry signal of the time-base timer is used as the count clock for the interval, the watchdog timer
interval time may become longer than the setting time when the time-base timer is cleared.
● Selecting the interval time
The interval can be set when the watchdog timer is activated. Data written during operations other than
activation is ignored.
● Notes on program creation
When a program that repeatedly clears the watchdog timer in the main loop is created, the processing time
of the main loop including the interrupt processing must be equal to or less than the minimum watchdog
timer interval time.
● Watchdog timer operation in time-base timer mode
The time-base timer operates while the time-base timer mode is set. The watchdog timer, however, is
temporarily stopped.
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CHAPTER 11 WATCHDOG TIMER
11.5
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CHAPTER 12
16-BIT RELOAD TIMER
This chapter describes the functions and operations of
the 16-bit reload timer.
12.1 Overview of 16-Bit Reload Timer
12.2 Block Diagram of 16-Bit Reload Timer
12.3 Pins of 16-Bit Reload Timer
12.4 Registers of 16-Bit Reload Timer
12.5 Interrupts of 16-Bit Reload Timer
12.6 Operation of 16-Bit Reload Timer
12.7 Notes on Using the 16-Bit Reload Timer
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CHAPTER 12 16-BIT RELOAD TIMER
12.1
12.1
MB90820B Series
Overview of 16-Bit Reload Timer
The 16-bit reload timer has two modes: Internal clock mode (with countdown performed
in synchronization with three types of internal clock), and event count mode (with
countdown performed by detecting any pulse edge input to the external pin). Either
mode may be selected. The timer defines an underflow when the counter value is in the
range from "0000H" to "FFFFH". In other words, an underflow occurs at a count of
[reload register’s setting value +1].
The counter can be used to select either reload mode, in which an underflow causes the
count set value to be reloaded for repeated counting, or one-shot mode, in which
counting is stopped when an underflow occurs. Counter underflow may generate an
interrupt and supports the extended intelligent I/O service (EI2OS).
■ Operation Mode of 16-bit Reload Timer
Table 12.1-1 lists the operation modes of the 16-bit reload timer.
Table 12.1-1 Operation Modes of 16-bit Reload Timer
Clock mode
Counter operation mode
Reload mode
Internal clock mode
One-Shot mode
Event count mode
(External clock mode)
Operation mode
Software trigger operation
External trigger input operation
External gate input operation
Reload mode
Software trigger operation
One-Shot mode
■ Internal Clock Mode
One type of count clock is selected among three types of internal clock modes to operate as follows:
● Software trigger operation
Sets the timer control status register (TMCSR0/TMCSR1): TRG bit to "1" to start count operation. Trigger
input by using the TRG bit is also enabled for external trigger input and external gate input.
● External trigger operation
Starts counting when the edge selected (leading, trailing, or both edges) is input to the TIN0/TIN1 pins.
● External gate input operation
Continues counting when the signal level selected ("L" or "H") is input to the TIN0/TIN1.
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CHAPTER 12 16-BIT RELOAD TIMER
12.1
MB90820B Series
■ Event Count Mode (External Clock Mode)
Event count mode provides a function for starting countdown when a valid edge selected (leading, trailing,
or both edges) is input to the TIN0/TIN1 pins. It is also used as an interval timer when using an external
clock with a constant interval.
■ Counter Operation
● Reload mode
If the countdown causes an underflow, and a transfer of the type 0000H --> FFFFH occurs, the setting value
for counting is reloaded so that counting can continue. An underflow can trigger an interrupt request, which
may be used for providing an interval timer. A toggled waveform, which reverses itself at every underflow,
is output from the TO0/TO1 pins. Table 12.1-2 lists the interval time for the 16-bit reload timer.
Table 12.1-2 Interval Time of 16-bit Reload Timer
Count clock
Internal count clock
External clock
Count clock interval
Interval time
21/φ (0.125 µs)
0.125 µs to 8.192 ms
23/φ (0.5 µs)
0.5 µs to 32.768 ms
25/φ (2.0 µs)
2.0 µs to 131.1 ms
23/φ or more (0.5 µs)
0.5 µs or more
φ: Machine clock. The parenthesized value indicates the clock interval time applied when the machine
clock frequency is 16 MHz and the FSEL bit is "1".
Table 12.1-3
Interval Time of 16-bit Reload Timer
Count clock
Internal count clock
External count clock
Count clock interval
Interval time
21/φ (0.167 µs)
0.167 µs to 10.923 ms
23/φ (0.667 µs)
0.667 µs to 43.690 ms
25/φ (2.667 µs)
2.667 µs to 174.760 ms
23/φ or more (0.667 µs)
0.667 µs or more
φ: Machine clock. The parenthesized value indicates the clock interval time applied when the machine
clock frequency is 24 MHz and the FSEL bit is "0".
● One-shot mode
If countdown leads to an underflow (0000H --> FFFFH), count operation will stop. Underflow may also
trigger an interrupt. During counter operation, the square wave that indicates counting is output from the
TO0/TO1 pins.
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CHAPTER 12 16-BIT RELOAD TIMER
12.1
MB90820B Series
References:
• The 16-bit reload timer is used to generate the UART baud rate.
• The 16-bit reload timer is used to trigger A/D converter operation.
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CHAPTER 12 16-BIT RELOAD TIMER
12.2
MB90820B Series
12.2
Block Diagram of 16-Bit Reload Timer
The 16-bit reload timer consists of the following seven blocks:
• Count clock generation circuit
• Reload control circuit
• Output control circuit
• Operation control circuit
• 16-bit timer registers (TMRL0/TMRL1, TMRH0/TMRH1)
• 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1)
• Timer control status registers (TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1)
■ Block Diagram of 16-bit Reload Timer
Figure 12.2-1 shows a block diagram of the 16-bit reload timer.
Figure 12.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRD0*1
TMRD1*2
16-bit reload timer
Reload signal
TMR0*1
TMR1*2
16-bit timer register (down-counter)
CLK
1
Clock
selector
Reload
control
circuit
UF
1-bit
down-counter
0
FSEL: Initial value "1"
Machine
clock
φ
Gate
input
Prescaler
3
Clock
judgement
circuit
Clear
Input
control
circuit
P41/TIN0*1
P20/TIN1*2
Output control circuit
Clock
selector
Reversed
Output signal
generation
circuit
Pin
_
_
2
Select
signal
FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Operation
control
circuit
UF CNTE TRG
Timer control status register (TMCSR0) *1
(TMCSR1) *2
*1: Used for channel 0
*2: Used for channel 1
CM44-10147-2E
P42/TO0*1
P21/TO1*2
EN
External clock
Count clock generation circuit
3
Function select
_
UART0*1
UART1, A/D converter*2
CLK
Internal
clock
Pin
Wait signal
FUJITSU MICROELECTRONICS LIMITED
Interrupt request signal
Interrupt number #30*1
#18*2
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CHAPTER 12 16-BIT RELOAD TIMER
12.2
MB90820B Series
● Count clock generation circuit
The count clock generation circuit generates the count clock for the 16-bit reload timer from the machine
clock or external input clock.
● Reload control circuit
Controls reload operation when the timer starts and when underflow occurs.
● Output control circuit
Controls the reversal of TO0/TO1 pin output due to 16-bit reload timer underflow and the enable or disable
states of TO0/TO1 pin output.
● Operation control circuit
Controls starting and stopping of the16-bit reload timer.
● 16-bit timer registers (TMRL0/TMRL1, TMRH0/TMRH1)
These registers are used to read the current counter value for the 16-bit down counter.
● 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1)
These registers are used to set the interval time of the 16-bit reload timer. The set value of the registers is
loaded into the 16-bit timer registers for countdown.
● Timer control status registers (TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1)
These registers are used to select the count clock and operation mode of the 16-bit reload timer, set
operating conditions, activate a trigger by software, enable/disable count operation, select reload or oneshot mode, select the pin output level, enable or disable timer output, control clock division, control
interrupt, and check the state of operation.
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CHAPTER 12 16-BIT RELOAD TIMER
12.3
MB90820B Series
12.3
Pins of 16-Bit Reload Timer
This section describes the pins of the 16-bit reload timer.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer can also be used for general-purpose I/O ports. Table 12.3-1 lists the pin
functions, type of I/O, and settings for using the 16-bit reload timer.
Table 12.3-1 Pins of the 16-bit Reload Timer
Pin name
Pin function
P41/TIN0
I/O and timer
input of port 4
P42/TO0
I/O and timer
output of port 4
Type of I/O
Pull-up
operation
Standby
control
Set to input port.
(DDR4:bit1=0)
Not used
I/O and timer
input of port 2
P20/TIN1
Setting to use pin
CMOS output
and CMOS
hysteresis
input
Setting to timer output enabled
(TMCSRL0:OUTE=1)
Sound generator output disabled
Provided
Set to input port
(DDR2:bit0=0)
PPG1 output disabled
Selectable
Setting to timer output enabled
(TMCSRL1:OUTE=1)
PPG4 output disabled
I/O and timer
output of port 2
P21/TO1
Reference:
For pin block diagrams, refer to "CHAPTER 9 I/O PORTS".
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CHAPTER 12 16-BIT RELOAD TIMER
12.4
12.4
MB90820B Series
Registers of 16-Bit Reload Timer
This section lists the registers of the 16-bit reload timer.
■ List of Registers for 16-bit Reload Timer
Figure 12.4-1 lists the registers of the 16-bit reload timer.
Figure 12.4-1 Registers of 16-bit Reload Timer
Address
16-Bit Reload Timer 0
16-Bit Reload Timer 1
bit15
bit8
bit7
000082H, 000083H
TMCSR0 (Timer control status register)
000084H, 000085H
TMR0/TMRD0
000086H, 000087H
TMCSR1 (Timer control status register)
000088H, 000089H
TMR1/TMRD1
bit0
(16-bit timer register/16-bit reload register)∗
(16-bit timer register/16-bit reload register)∗
∗: Functions as a 16-bit timer register (TMR) for reading and as a 16-bit reload register (TMRLR) for writing.
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CHAPTER 12 16-BIT RELOAD TIMER
12.4
MB90820B Series
12.4.1
Upper Bits of Timer Control Status Registers
(TMCSRH0/TMCSRH1)
Upper bits 12 to 8 and lower bit 7 in the timer control status registers (TMCSRH0/
TMCSRH1) are used to select the 16-bit reload timer operation mode and set the
operating conditions. Use of the last lower bit 7 (MOD0 bit) is also described here.
■ Upper Bits and Bit 7 of Timer Control Status Registers (TMCSRH0/TMCSRH1)
Figure 12.4-2 Upper Bits and Bit 7 of Timer Control Status Registers (TMCSRH0/TMCSRH1)
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6
bit0
TMCSRH0
(TMCSRL)
FSEL CSL1 CSL0 MOD2 MOD1 MOD0
000083H
TMCSRH1 R/W R/W R/W R/W R/W R/W
Initial value
XXX100000B
000087H
bit 9
bit 8
bit 7
MOD2 MOD1 MOD0
Input pin function
Trigger prohibited
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
bit 9
bit 8
bit 7
Trigger input
Gate input
MOD2 MOD1 MOD0
X
0
0
X
0
1
X
1
0
X
1
bit 11 bit 10
CSL1 CSL0
0
0
0
1
1
0
1
bit 12
1
Operation mode selection bit
(in internal clock mode)
Valid edge, level
Leading edge
Trailing edge
Both edges
L level
H level
Operation mode selection bit
(in event count mode)
Input pin function
Valid edge
Trigger input
1
Leading edge
Trailing edge
Both edges
Count clock selection bit
Count clock
Function
21/φ (0.125 µs)
Internal clock mode
23/φ (0.5 µs)
25/φ (2.0 µs)
Event count mode
External event input
Count clock division control bit
Division by two
R/W : Reading and writing permitted
: Undefined
Division by one
x : Unspecified value
: Initial value
φ : Machine clock. The parenthesized value indicates the count clock applied when the machine
clock frequency is 16 MHz and the count clock division ratio is 1 (FSEL bit is "1").
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Table 12.4-1 Function of the Upper Bits and Bit 7 in Timer Control Status Registers:
(TMCSRH0, TMCSRH1)
Bit name
bit15
to
bit13
Undefined bits
bit12
FSEL:
Count clock division
control
bit11,
bit10
bit9
to
bit7
270
Function
CSL1, CSL0:
Count clock selection
bits
MOD2, MOD1,
MOD0:
Operation mode
selection bits
•
•
Value at reading is not specified.
If write, the bit value is always "1".
•
•
Specifies the count clock division ratio.
If the FSEL bit is set to "0", the count clock specified by the count clock
selection bits (CSL1 and CSL0) is divided by two.
•
•
Selects the count clock of the 16-bit reload timer.
Internal clock mode to count the internal clock is selected if the CSL1 and
CSL0 bits are other than "11B".
Event count mode to count external clock edges is selected if the CSL1 and
CSL0 bits are "11B".
•
<Internal clock mode>
• The MOD2 bit is used to select the function of the input pin.
When the MOD2 bit is set to "0", the input pin is used as a trigger input
pin. When a valid edge is input, the 16-bit reload register data is loaded
into the counter to continue with count operation. Valid edge types are
selected by using the MOD1/0 bits.
• With the MOD2 bit set to "1", the input pin is used for gate input for
counting only when a valid level signal is being input. The MOD0 bit
enables selection of a valid level.
• Because the value of the MOD1 bit has no effect on operation, either value
(0 or 1) can be set.
<Event count mode>
• Because the value of the MOD2 bit has no effect on operation, either value
(0 or 1) can be set.
• The input pin is used as a trigger input pin for event input. A valid edge is
selected by using the MOD1/MOD0 bits.
Note :
The operation mode selection must be counter operation stop mode
(TMCSRL0/TMCSRL1: CNTE=0).
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12.4
MB90820B Series
12.4.2
Lower Bits of Timer Control Status Registers
(TMCSRL0/TMCSRL1)
Bit 7 of the timer control status registers (TMCSRL0/TMCSRL1), which is part of the
lower bits, is used to set the operating conditions of the 16-bit reload timer, enable or
disable count operation, control interrupts, and check the state of operation.
■ Lower Bits of Timer Control Status Registers (TMCSRL0/TMCSRL1)
Figure 12.4-3 Lower Bits of Timer Control Status Registers (TMCSRL0/TMCSRL1)
Address
bit8 bit7*
bit15
TMCSRL0
000082H
(TMCSRH)
TMCSRL1
bit6
bit5
bit4
bit3
MOD0 OUTE OUTL RELD INTE
R/W
R/W
R/W
R/W
R/W
bit2
bit1
bit0
UF CNTE TRG
R/W
R/W
Initial value
00000000B
R/W
000086H
bit 0
Software trigger bit
TRG
0
1
Does not change and has no effect
Starts counting after reload
bit 1
CNTE
0
1
Count enable bit
Count stop
Count enabled (waiting for start trigger)
bit 2
Underflow flag bit for interrupt request
Reading
Writing
UF
0
No counter underflow
Bit cleared
1
Counter underflow generated
Does not change and has
no effect
bit 3
INTE
0
1
Enable bit for interrupt requests
Interrupt request output disabled
Interrupt request output enabled
bit 4
RELD
0
1
Reload selection bit
One-shot mode
Reload mode
bit 5
Selection bit for pin output level
OUTL
0
1
OUTE
One-shot mode
(RELD=0)
Reload mode
(RELD=1)
Rectangle wave at H level
during counting
Rectangle wave at L level
during counting
bit 6
Toggle output at L level when
counting starts
Toggle output at H level when
counting starts
Timer output enable bit
Register and pin for each channel
Pin function
TMCSRL0
R/W : Reading and writing permitted
: Initial value
TMCSRL1
0
General-purpose
I/O port
P42
P21
1
Timer output
TO0
TO1
* : For details about the MOD0 (bit 7), see Section "11.4.1 Upper Bits of Timer Control Status Registers (TMCSRH0,
TMCSRH1)".
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Table 12.4-2 Function of the Lower Bits in the Timer Control Status Registers (TMCSRL0/TMCSRL1)
Bit name
Function
•
bit6
OUTE:
Timer output enable bit
bit5
OUTL:
Selection bit for pin
output level
•
•
•
Bit used to select the output level to the timer output pin.
Toggle this bit to "0" or "1" to reverse the pin output level.
•
Enables reload operation.
Reload mode is entered when this bit is set to "1". If underflow occurs,
16-bit reload register data is loaded into the 16-bit counter to continue
count operation.
One-shot mode is entered when this bit is se to "0". If underflow occurs,
count operation will stop.
bit4
RELD:
Reload selection bit
bit3
INTE:
Enable bit for interrupt
requests
•
•
Enables or disables interrupt requests to the CPU.
When this bit and the flag bit for interrupt request (UF) are set to "1", an
interrupt request is output.
UF:
Underflow flag bit for
interrupt request
•
bit2
Set to "1" if 16-bit counter underflow occurs.
Cleared by writing "0". Writing "1" has no effect.
Also cleared at EI2OS startup.
bit1
bit0
CNTE:
Count enable bit
TRG:
Software trigger bit
•
•
Enables or disables count operation.
When this bit is set to "1", start trigger wait state is entered. As soon as
the start trigger occurs, the actual counting will begin.
•
Used to start the interval timer function or counter function by software.
Set this bit to "1" to activate the software trigger and load the 16-bit
reload register value into the counter to start counting. Writing "0" has no
effect.
When CNTE=1, trigger input is always enabled by this but regardless of
the mode.
Reading always returns "0".
•
•
272
Enables or disables output via the timer output pin.
When this bit is "0", the pin is used as a general-purpose I/O port; when
this bit is "1", the pin is used as a timer output pin.
The waveform output from the timer output pin becomes toggle
waveform output in reload mode. In one-shot mode, a rectangular wave
is output, which indicates that counting is in progress.
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12.4
MB90820B Series
12.4.3
16-Bit Timer Registers (TMR0/TMR1)
The 16-bit timer registers (TMR0/TMR1) are used to continuously read the current count
value of the 16-bit down counter.
■ 16-bit Timer Registers (TMR0/TMR1)
Figure 12.4-4 shows the bit configuration of the 16-bit timer registers (TMR0/TMR1).
Figure 12.4-4 Bit Configuration of 16-bit Timer Registers (TMR0/TMR1)
Address
TMR0: 000053H
TMR1: 000057H
Address
TMR0: 000052H
TMR1: 000056H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D15
D14
D13
D12
D11
D10
D9
D8
XXXXXXXXB
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
R: Read only
X: Undefined value
These registers are used to read the current count value of the 16-bit down counter. When count operation
is allowed (TMCSR0/TMCSR1: CNTE=1) to start counting, the value written to the 16-bit reload register
is loaded into these registers to start the countdown. In counter stop mode (CNTE=0 for TMCSR0/
TMCSR1), the register value is retained.
Note:
These registers may be read in counter operation mode by using a word transfer instruction (MOVW
A, 003AH, etc).
The 16-bit timer registers (TMR0/TMR1) are read-only registers and assigned the same address as
the write-only 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1). Therefore, writing
does not affect TMR register values, though writing is performed to TMRDL0/TMRDL1 and
TMRDH0/TMRDH1.
Be sure to perform word-access to the TMR0/TMR1 registers.
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12.4.4
MB90820B Series
16-Bit Reload Registers (TMRDL0/TMRDL1,
TMRDH0/TMRDH1)
The 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) are used to set a
reload value to the 16-bit down counter. The value written to these registers is loaded
into the down counter for countdown.
■ 16-Bit Reload Registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1)
Figure 12.4-5 shows the bit configuration of the 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/
TMRDH1).
Figure 12.4-5 Bit Configuration of 16-bit Reload Registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1)
Address
TMRDH0: 000085H
TMRDH1: 000089H
Address
TMRDL0: 000084H
TMRDL1: 000088H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D15
D14
D13
D12
D11
D10
D9
D8
XXXXXXXXB
W
W
W
W
W
W
W
W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
W
W
W
W
W
W
W
R: Read only
X: Undefined value
Regardless of the 16-bit reload timer operation mode, if counter operation is prohibited (TMCSR0/
TMCSR1: CNTE=0), these registers are set to the initial value of the counter. When counter operation is
allowed (TMCSR0/TMCSR1: CNTE=1) to start the counter, the countdown starts from the value written to
these registers.
The value set in the 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) is reloaded into the
counter in reload mode if underflow occurs, then the countdown continues. In one-shot mode, the counter
stops at "FFFFH" if underflow occurs.
Writing to the registers is always performed in counter stop mode (TMCSR0/TMCSR1: CNTE=0). Write
operations always using a word transfer instruction (MOVW 003AH, A).
The 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) are functionally write-only
registers that are allocated under the same address as the read-only 16-bit timer registers (TMR0/TMR1).
Therefore, the value read is the value of TMR0/TMR1. Consequently, an instruction such as INC/DEC for
read-modify-write (RMW) operation cannot be used.
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12.5
MB90820B Series
12.5
Interrupts of 16-Bit Reload Timer
The16-bit reload timer may generate an interrupt due to 16-bit down counter underflow.
The timer also supports the extended intelligent I/O service (EI2OS).
■ Interrupts Generated by 16-bit Reload Timer
Table 12.5-1 lists the interrupt control bits and interrupt sources of the 16-bit reload timer.
Table 12.5-1 Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer
Lower bits of timer control status register (TMCSRL0/TMCSRL1)
Interrupt source
Underflow of 16-bit down
counter (TMR0/1)
("0000H" --> "FFFFH")
Interrupt flag bit
Interrupt enable bit
UF
INTE
Clearance of interrupt flag
•
•
•
Writing "0" to the UF bit
Resetting
Starting EI2OS
If the interrupt source listed in Table 12.5-1 is generated, the interrupt flag bit of the 16-bit reload timer is
set to "1". If the interrupt enable bit of the 16-bit reload timer is "1" when the interrupt flag bit is set to "1",
the 16-bit reload timer outputs an interrupt request to the interrupt controller.
■ Interrupts of 16-bit Reload Timer and EI2OS
Table 12.5-2 lists the interrupts of the 16-bit reload timer and their relationship to EI2OS.
Table 12.5-2 Interrupts of 16-bit Reload Timer and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower bits
Upper bits
Bank
16-Bit Reload Timer 0
#30(1EH)
ICR09
0000B9H
FFFF84H
FFFF85H
FFFF86H
*
16-Bit Reload Timer 1
#18(12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
*
*: Available when not using interrupt sources sharing ICR03, ICR09, or the interrupt vector.
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer has a circuit supporting EI2OS. Therefore, a counter underflow will start EI2OS.
Note that EI2OS is only available when no other peripheral function that shares the interrupt control
register (ICR) uses an interrupt. To use EI2OS by 16-bit reload timer 0, interrupts of waveform generator
must be prohibited. To use EI2OS by 16-bit reload timer 1, interrupts of output compare 2 must be
prohibited.
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12.6
12.6
MB90820B Series
Operation of 16-Bit Reload Timer
This section describes how to set the 16-bit teload timer and counter operation state.
■ 16-bit Reload Timer Settings
● Setting internal clock mode
To operate the interval timer, the settings listed in Figure 12.6-1 are required.
Figure 12.6-1 Internal Clock Mode Settings
TMCSR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
−
−
−
FSEL
CSL1
CSL0
MOD
2
MOD
1
MOD
0
bit6
bit5
bit4
OUTE OUTL RELD
bit3
bit2
bit1
bit0
INTE
UF
CNTE
TRG
1
Other than "11"
TMRD
Setting of the initial counter value (reload value)
: Bit used
1: Set to "1".
● Setting event count mode
To operate the event counter, the settings listed in Figure 12.6-2 are required.
Figure 12.6-2 Event Count Mode Settings
TMCSR
TMRD
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
−
−
−
FSEL
CSL1
CSL0
MOD
2
MOD
1
MOD
0
1
1
bit6
bit5
bit4
OUTE OUTL RELD
bit3
bit2
bit1
bit0
INTE
UF
CNTE
TRG
1
Setting of the initial counter value (reload value)
DDR5
DDR0
: Bit used
1: Set to "1".
: Set the bit corresponding to the pin used to "0".
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MB90820B Series
■ States of Counter Operation
The counter’s operation state is determined by the CNTE bit of the timer control status registers
(TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1) and the internal WAIT signal. States that can be set
include the stop state (STOP state), start trigger wait state (WAIT state), and operation state (RUN state).
Figure 12.6-3 shows a state transition diagram for the counter.
Figure 12.6-3 State Transition Diagram of Counter Operation
STOP state CNTE=0, WAIT=1
TIN pin: Input disabled
TO pin: General-purpose I/O port
Counter: Retains the value at stop.
Not specified immediately
after reset
Reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
WAIT state CNTE=1, WAIT=1
TIN pin: Valid for trigger input only
TO pin: Initial value output
Counter: Retains the value at stop.
Not specified until loading
immediately after reset
CNTE=1
TRG=1
UF=1 &
RELD=0
(One-shot mode)
RUN state CNTE=1, WAIT=0
TIN pin: Functions as TIN pin.
TO pin: Functions as TO pin.
Counter: operating
UF=1 &
RELD=1
TRG=1
(Reload mode)
TRG=1
(Software trigger)
(Software trigger)
LOAD
CNTE=1, WAIT=0
Loads
the
reload
register value into
Load end
External trigger from TIN pin the counter.
: State transition by hardware
WAIT
TRG
CNTE
UF
RELD
CM44-10147-2E
: State transition by register access
: WAIT signal (internal signal)
: Software trigger bit of timer control status register (TMCSR)
: Count enable bit of timer control status register (TMCSR)
: Underflow flag bit for interrupt request of timer control status register (TMCSR)
: Reload selection bit of timer control status register (TMCSR)
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CHAPTER 12 16-BIT RELOAD TIMER
12.6
12.6.1
MB90820B Series
Internal Clock Mode (Reload Mode)
The counter operates in sync with the internal count clock to count down the 16-bit
counter and generate an interrupt request to the CPU in case of counter underflow. The
counter also outputs a toggle waveform from the timer output pin.
■ Operation in Internal Clock Mode (Reload Mode)
When count operation is allowed (TMCSR0/TMCSR1: CNTE=1) and the timer is started by the software
trigger bit (TMCSR: TRG) or external trigger, counter operation will start by reloading the data of the 16bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) into the 16-bit down counter. When both
the count enable bit and software trigger bit are set to "1", counting will begin as soon as the counter is
enabled.
If the 16-bit counter value causes an underflow ("0000H" --> "FFFFH"), the value of the16-bit reload
registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) is reloaded into the 16-bit counter to continue
counting. Note that if the underflow flag bit for interrupt request (UF) and enable bit for interrupt request
(INTE) are set to "1", an interrupt request is generated.
The TO pin outputs a toggle waveform that is reversed at every underflow.
● Software trigger operation
When the TRG bit of the timer control status registers (TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1) is
set to "1", the counter starts operation. Figure 12.6-4 shows the software trigger operation in reload mode.
Figure 12.6-4 Count Operation (Software Trigger Operation) in Reload Mode
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
1
TO pin
T : Machine cycle
* : It takes 1T from trigger input to loading reload data.
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● External trigger input operation
When a valid edge (leading, trailing, or both edges can be selected) is input to the TIN pin, the count will
start operation. Figure 12.6-5 shows the external trigger operation in reload mode.
Figure 12.6-5 Count Operation in Reload Mode (External Trigger Input Operation)
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T
TO pin
T: Machine cycle
* : It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The width of trigger pulses input to the TIN pin must be 2/φ (φ: machine clock) or more.
● Gate input operation
As soon as a valid level ("H" level or "L" level can be selected) is input to the TIN pin, the count will start
operation. Figure 12.6-6 shows the gate input operation in reload mode.
Figure 12.6-6 Count Operation in Reload Mode (Software Trigger and Gate Input Operation)
Count clock
Counter
Reload data
-1
-1
-1
0000H
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
TIN pin
TO pin
T : Machine cycle
* : It takes 1T from trigger input to loading reload data.
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Note:
The width of trigger pulses input to TIN pin must be 2/φ (φ: machine clock) or more.
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12.6
MB90820B Series
12.6.2
Internal Clock Mode (One-Shot Mode)
The counter is in synchronization with the internal count clock in this mode to count
down the 16-bit counter and generate an interrupt request to the CPU at counter
underflow. It also outputs a square wave from the TO0/TO1 pin to indicate that counting
is in progress.
■ Operation of Internal Clock Mode (One-shot Mode)
When count operation is allowed (TMCSR0/1: CNTE=1) and the timer is started by the software trigger bit
(TMCSR0/TMCSR1: TRG) or external trigger, count operation will start. When both the count enable bit
and software trigger bit are set to "1", counting will start at the same time counting becomes enabled. If the
16-bit counter value causes an underflow ("0000H" --> "FFFFH"), the counter stops at "FFFFH", and the
underflow flag bit for interrupt requests (UF) is set to "1". If the enable bit for interrupt request (INTE) is
set to "1", an interrupt request is generated.
The TO pin outputs a square wave to indicate that counting is in progress.
● Software trigger operation
The count will start as soon as the TRG bit of the timer control status registers (TMCSRL0/TMCSRL1,
TMCSRH0/TMCSRH1) is set to "1". Figure 12.6-7 shows the software trigger operation in one-shot mode.
Figure 12.6-7 Count Operation in One-shot Mode (Software Trigger Operation)
Count clock
Reload
data
Counter
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
1
TO pin
Waiting for start trigger input
T : Machine cycle
* : It takes 1T from trigger input to loading reload data.
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● External trigger input operation
When a valid edge (leading, trailing, or both edges can be selected) is input to the TIN0/TIN1 pins, the
count will start operation. Figure 12.6-8 shows the external trigger operation in one-shot mode.
Figure 12.6-8 Count Operation in One-shot Mode (External Trigger Operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T
TO pin
Waiting for start trigger input
T: Machine cycle
* : It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The width of trigger pulses input to the TIN pin must be 2/φ (φ: machine clock) or more.
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● Gate input operation
When a valid level ("H" or "L" level can be selected) is input to the TIN pin, the count starts operation.
Figure 12.6-9 shows the gate input operation in one-shot mode.
Figure 12.6-9 Count Operation in One-shot Mode (Software Trigger and External Gate Input Operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Waiting for start trigger input
T : Machine cycle
* : It takes 1T from trigger input to loading reload data.
Note:
The width for trigger pulse input to the TIN pin must be 2/φ (φ: machine clock) or more.
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12.6
12.6.3
MB90820B Series
Event Count Mode
In this mode, the counter counts input edges from the TIN pin to count down the 16-bit
counter and generate an interrupt request to the CPU when a counter underflow occurs.
The TO0/1 pin can output either a toggle waveform or a square wave.
■ Event Count Mode
When count operation is allowed (TMCSR0/TMCSR1: CNTE=1) to start the counter (TMCSR0/TMCSR1:
TRG=1), data from the 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) is loaded into
the counter for a countdown whenever a valid edge (leading, trailing, or both edges can be selected) of
pulses (external count clock) input to the TIN0/TIN1 pin is detected. When both the count enable bit and
software trigger bit are set to "1", counting will start as soon as counting becomes enabled.
Operation in reload mode
If the counter value has an underflow ("0000H" --> "FFFFH"), data from the 16-bit reload registers
(TMRDL0/TMRDL1, TMRDH0/TMRDH1) is loaded into the counter to continue counting. In this case,
an interrupt request is issued when the underflow flag bit for interrupt requests (UF) and enable bit for
interrupt requests (TMCSR0/TMCSR1: INTE) are both set to "1". The TO0/TO1 pin outputs a toggle
waveform, which is reversed at every occurrence of underflow. Figure 12.6-10 shows the counting
operation in reload mode.
Figure 12.6-10 Count Operation in Reload Mode (Event Count Mode)
TIN pin
Reload
data
Counter
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
*
1T
TO pin
T: Machine cycle
* : It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width of clock input to TIN pin must be 4/φ (φ: machine clock) or more.
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CHAPTER 12 16-BIT RELOAD TIMER
12.6
MB90820B Series
● Operation in one-shot mode
If the counter value causes an underflow ("0000H" --> "FFFFH"), the 16-bit counter stops at "FFFFH". In
this case, the underflow interrupt request flag bit (UF) is set to "1". If the interrupt request enable bit
(INTE) is also set to "1", an interrupt request is generated. The TO0/TO1 pin outputs a square wave that
indicates counting in progress. Figure 12.6-11 shows the counter operation in one-shot mode.
Figure 12.6-11 Counter Operation in One-shot Mode (Event Count Mode)
TIN pin
Reload
data
Counter
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
1T*
TO pin
Waiting for start trigger input
T : Machine cycle
* : It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width for the clock input to TIN pin must be 4/φ (machine clock) or more.
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CHAPTER 12 16-BIT RELOAD TIMER
12.7
12.7
MB90820B Series
Notes on Using the 16-Bit Reload Timer
This section provides notes on using the 16-bit reload timer.
■ Notes on Using the 16-bit Reload Timer
● Notes on setup by program
Writing a value to the 16-bit reload registers (TMRDL0/TMRDL1, TMRDH0/TMRDH1) must be
performed in counter operation stop (TMCSR0/TMCSR1: CNTE=0) mode. Reading of the 16-bit timer
registers (TMR0/TMR1) may be performed while the counter is in operation, but a word transfer
instruction (MOVW A, dir, etc) must be used in this case.
The contents of the FSEL/CSL1/CSL0/MOD2/MOD1/MOD0 bits in the timer control status registers
(TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1) can only be changed in counter operation stop mode
(TMCSRL0/TMCSRL1: CNTE=0).
● Notes on interrupts
If the UF bit of the timer control status registers (TMCSRL0/TMCSRL1, TMCSRH0/TMCSRH1) is set to
"1" in interrupt request enabled state (TMCSRL0/TMCSRL1:INTE=1), return from interrupt handling
cannot be performed. Ensure that the UF bit is always cleared.
Since the 16-bit reload timer, waveform generator and output compare 2 share the same interrupt vector,
interrupt sources must be checked in the interrupt-handling routine to enable using interrupts.
If the 16-bit reload timer uses EI2OS, "shared resource interrupts must be disabled".
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CHAPTER 13
PWC Timer
This chapter explains the activation and operations of
the PWC timer.
13.1 Overview of the PWC Timer
13.2 Block Diagram of the PWC Timer
13.3 PWC Timer Pins
13.4 PWC Timer Registers
13.5 PWC Timer Interrupts
13.6 Operation of the PWC Timer
13.7 Usage Notes on the PWC Timer
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CHAPTER 13 PWC Timer
13.1
13.1
MB90820B Series
Overview of the PWC Timer
The PWC timer (pulse-width measurement) is the multi-functional 16-bit up counter with
the reload function and also has a function that calculates the pulse width of the input
signal.
The PWC timer consists of a 16-bit counter, an input pulse divider, a division rate
control register, a count input pin, a pulse output pin, and a 16-bit control register.
■ PWC Timer
The MB90820B series contains two PWC timer channels. The PWC timer has the following characteristics:
● Timer function
• Generates an interrupt request at the specified time interval.
• Outputs the pulse signal that is synchronized with the timer period.
• Selects the counter clock from three internal clocks.
● Pulse-width measurement function
• Measures the time between external pulse input events.
• Selects the counter clock from three internal clocks.
• Count mode
- H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge)
- Rising edge period (rising edge to falling edge) / falling edge period (falling edge to rising edge)
- Intermediate edge count (rising or falling edge to falling or rising edge)
• Uses the 8-bit input divider to divide the input pulse by 22, 24, 26, and 28 to enable period measurement.
• Generates an interrupt request at completion of count.
• Selects single count or continuous count.
■ PWC Timer Operation
This block is a multi-functional timer that is based on the 16-bit up-count timer and contains a count input
pin and an 8-bit input divider. The block has two main functions, a timer function and a pulse-width
measurement function, both of which enable the selection for two types of count clocks.
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CHAPTER 13 PWC Timer
13.2
MB90820B Series
13.2
Block Diagram of the PWC Timer
Figure 13.2-1 shows the PWC timer block diagram.
■ Block Diagram of the PWC Timer
Figure 13.2-1 Block diagram of the PWC timer
PWC read
Error
detection
ERR
16
PWC
16
Write enabled
16
Overflow
Reload
P07/PWO0
P47/PWO1
F.F.
Data transfer
16
Clock
Overflow
22
16-bit up-count timer
23
Timer clear
F2MC-16LX bus
Count
enabled
CKS1, CKS0,
Divider clear
Count bit
output
Flag setting
Control circuit
Start edge
selection
Count end
edge
Count start edge
End edge
selection
Overflow interrupt request
15
P06/PWI0
P46/PWI1
PWCS
8-bit
divider
CKS1
ERR CKS0
Division
ratio
selection
2
CM44-10147-2E
Internal clock
(machine clock / 4)
Divider ON/OFF
Edge
detection
Count end interrupt request
Clock
Clock
divider
DIV1,
DIV0
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CHAPTER 13 PWC Timer
13.3
13.3
MB90820B Series
PWC Timer Pins
This section describes the pins of the PWC timer and provides a pin block diagram.
■ PWC Timer Pins
The pins of the PWC timer are shared with the general-purpose I/O ports. Table 13.3-1 lists the functions
of the pins, I/O format, and settings required to use the PWC timer.
Table 13.3-1 16-bit PWC timer pins
Pin name
Pin function
P06/PWI0
Port 0 input-output /
timer input
P07/PWO0
Port 0 input-output /
timer output
P46/PWI1
Port 4 input-output /
timer input
I/O format
CMOS
output /
CMOS
input
Pull-up
option
Standby
control
Setting for the input
port (DDR0: bit 6 = 0)
Selectable
Setting for timer enable
(PWCSL0: MOD2 to
MOD0 not equal "0")
Available
P47/PWO1
Port 4 input-output /
timer output
CMOS
output /
CMOS
hysteresis
input
Settings required for
pins
Not
provided
Setting for the input
port
(DDR4: bit 6 = 0)
Setting for timer enable
(PWCSL1: MOD2 to
MOD0 not equal "0")
■ Block Diagram of the PWC Timer Pins
Figure 13.3-1 shows the block diagram of the PWC timer 0 input pin.
Figure 13.3-1 Block diagram of the PWC timer 0 input pin (PWI0)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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CHAPTER 13 PWC Timer
13.3
MB90820B Series
Figure 13.3-2 shows the block diagram of the PWC timer 0 output pin.
Figure 13.3-2 Block diagram of the PWC timer 0 output pin (PWO0)
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 12.3-3 shows the block diagram of the PWC timer 1 input pin.
Figure 13.3-3 Block diagram of the PWC timer 1 input pin (PWI1)
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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CHAPTER 13 PWC Timer
13.3
MB90820B Series
Figure 13.3-4 shows the block diagram of the PWC timer 1 output pin.
Figure 13.3-4 Block diagram of the PWC timer 1 output pin (PWO1)
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
13.4
PWC Timer Registers
Following are the PWC timer registers.
■ PWC Timer Registers
Figure 13.4-1 PWC timer registers
PWCSH0, PWCSH1
PWC control status register (Upper)
Address: ch.0 0000C1H
ch.1 000029H
Read/write ⇒
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value:
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
00000000B
R/W
R/W
R
R/W
R/W
R/W
R
R/W
bit 7
bit 6
bit 2
bit 1
bit 0
CKS0
R/W
R/W
bit 4
Reser
ved
R/W
bit 3
CKS1
bit 5
Reser
ved
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value:
PW15
PW14 PW13 PW12
PW08
xxxxxxxxB
PWCSL0, PWCSL1
PWC control status register (Lower)
Address: ch.0 0000C0H
ch.1 000028H
Read/write ⇒
S/C
MOD2 MOD1 MOD0
Initial value:
00000000B
PWC0, PWC1
PWC data buffer register (Upper)
Address: ch.0 0000C3H
ch.1 00002BH
Read/write ⇒
R/W
PW11 PW10 PW09
R/W
R
R/W
R/W
R/W
R
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value:
PW00
xxxxxxxxB
PWC0, PWC1
PWC data buffer register (Lower)
bit 7
Address: ch.0 0000C2H
ch.1 00002AH
Read/write ⇒
PW07
R/W
PW06 PW05 PW04
PW03 PW02 PW01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value:
−
−
−
−
−
−
DIV1
DIV0
xxxxxx00B
−
−
−
−
−
−
R/W
R/W
DIV0, DIV1
Division ratio control register
Address: ch.0 0000C4H
ch.1 00002CH
Read/write ⇒
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CHAPTER 13 PWC Timer
13.4
13.4.1
MB90820B Series
PWC Control Status Register (PWCSH0/PWCSH1,
PWCSL0/PWCSL1)
The PWC control status register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) controls the
PWC timer operation and reads the PWC timer state.
■ PWC Control Status Register, Upper Byte (PWCSH0/PWCSH1)
Figure 13.4-2 PWC control status register (PWCSH0/PWCSH1)
Address
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch.0: 0000C1H STRT STOP EDIR
ch.1: 000029H R/W
R/W
R
bit15
bit14
EDIE
OVIR
OVIE
ERR
POUT
00000000B
R/W
R/W
R/W
R
R/W
bit 8
POUT
Pulse output bit
0
When previous value is 1 and timer overflows
1
When previous value is 0 and timer overflows
bit 9
ERR
Error flag bit
0
Count result is not overwritten
1
Count result is overwritten before previous value is read
bit 10
OVIE
Overflow interrupt request enable bit
0
Disables overflow interrupt request
1
Enables overflow interrupt request
bit 11
Overflow interrupt request bit
OVIR
Read
Write
0
No timer overflow
Clear this bit
1
Timer overflows
No effect
bit 12
EDIE
Measurement end interrupt enable bit
0
Disables measurement end interrupt request
1
Enables measurement end interrupt request
bit 13
EDIR
Measurement end interrupt request flag bit
0
Pulse-width measurement is operating
1
Pulse-width measurement is terminated
bit 15 bit 14
Operation status indication
STRT STOP
Read
X
R
0
Timer stops (the timer is not No function. Operation is not
started or count ends)
affected
0
1
No meaning
Starts or restarts the timer
(enables count)
1
0
No meaning
Starts or restarts the timer
operation (enables count)
1
1
Timer count operation in
progress (counting)
No function. The operation is not
affected
: Read only
: Initial value
294
0
: Undefined value
R/W : Read and write
Write
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
Table 13.4-1 PWC control status register (PWCSH0/PWCSH1) (1 / 2)
Bit name
Function
•
•
•
bit15,
bit14
STRT, STOP:
Start and Stop bits
•
•
•
bit13
EDIR:
•
Measurement end
interrupt request flag •
bit
•
•
•
bit12
EDIE:
Measurement end
interrupt enable bit
•
•
These bits are used to start, restart, and stop the 16-bit up-count timer.
When these bits are read, the timer operation status is returned.
These bits can be read and written. The meaning of bits depends on whether
they are read or written.
In read-modify-write operation, "11B" is always read.
When the STRT and STOP bits are written to start and stop the timer, a bit
manipulation instruction (such as bit clear instruction) can be used.
However, when the operation status (which always indicates that the timer
is operating, for example) is read, a bit manipulation instruction cannot be
used.
This bit indicates that measurement terminated in pulse-width measurement
mode.
When pulse-width measurement terminates, the bit is set (PWC0/PWC1
contains the measurement result).
This bit is cleared automatically when the measurement result in PWC data
buffer register and PWC0/PWC1 are read.
In timer mode, this bit is meaningless.
This bit is read-only, writing this bit is meaningless.
This bit is used to control a measurement termination interrupt request in
pulse-width count mode.
When this bit is "1" and EDIR bit is set to "1", the measurement end
interrupt request will be generated to CPU.
Always set "0" in timer mode.
•
bit11
OVIR:
Overflow interrupt
request bit
bit10
OVIE:
Overflow interrupt
request enable bit
CM44-10147-2E
This bit is used to specify when the 16-bit up-count timer overflows. The
operation affects all modes.
• When timer overflow occurs ("FFFFH" to "0000H"), the bit is set.
Writing "0" will clear the bit.
Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
Note:
In H/L pulse-width count mode, do not use this bit for pulse-width time
measurement.
•
•
This bit is used to enable timer overflow interrupt request.
When this bit is "1" and OVIR is set to "1", the overflow interrupt request
will be generated to CPU.
Note:
In the H/L pulse-width count mode, set this bit to "0".
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
Table 13.4-1 PWC control status register (PWCSH0/PWCSH1) (2 / 2)
Bit name
Function
•
bit9
ERR:
Error flag bit
•
•
•
•
•
•
bit8
POUT:
Pulse output bit
•
•
296
This bit is used to execute a continuous count in the pulse-width count
mode. This flag indicates that the next count has been completed before the
previous count result is read from PWC0/PWC1 register. If this state
occurs, PWC0/PWC1 register is overwritten by new count result and the
previous result is lost. The count operation continues regardless of the value
for this bit.
The bit is read-only. Writing to this bit is meaningless.
When the count result that has not been read is overwritten by the next
result, the bit is set.
This bit is cleared automatically when the measurement result in PWC data
buffer register and PWC0/PWC1 are read.
When the 16-bit up-count timer overflows in timer mode, this bit is
reversed.
In the pulse-width count mode, this bit is meaningless.
The bit can be read and written. However, the bit can be written only if the
timer stops (both bit 15: STRT and bit 14: STOP are set to "0"). If the bit is
written during timer operation (both bit 15: STRT and bit 14: STOP are set
to "1"), the bit value remains unchanged.
When the POUT value is "0" and the timer overflows in the range from
"FFFFH" to "0000H" or the timer stops and "1" is written, the bit is set.
When the POUT value is "1" and the timer overflows in the range from
"FFFFH" to "0000H" or the timer stops and "0" is written, the bit is cleared.
The bit is also cleared by reset.
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
■ PWC Control Status Register, Lower Byte (PWCSL0/PWCSL1)
Figure 13.4-3 PWC control status register, lower byte (PWCSL0/PWCSL1)
Address
bit7
bit6
bit5
bit4
bit3
ch.0: 0000C0H CKS1 CKS0 Reserved Reserved
ch.1: 000028H R/W
R/W
R/W
R/W
S/C
bit2
bit1
bit0
Initial value
MOD2 MOD1 MOD0 00000000B
R/W
bit 2
R/W
bit 1
R/W
R/W
bit 0
MOD2 MOD1 MOD0
Operation mode / count edge selection
0
0
0
Timer mode and no pulse output
0
0
1
Timer mode and pulse output (PWO pin valid):
reload mode only
0
1
0
All edge-to-edge pulse-width measurement
mode (rising edge or falling edge to falling edge
or rising edge)
0
1
1
Division period measurement mode (when the
input divider is used)
1
0
0
Rising edge-to-rising edge period measurement
mode (rising edge to rising edge)
1
0
1
H pulse-width measurement mode (rising edge
to falling edge)
1
1
0
L pulse-width measurement mode (falling edge
to rising edge)
1
1
1
Falling edge-to-falling edge period measurement
mode (falling edge to falling edge)
bit 3
Count mode
selection
S/C
Single
Stop after single
No reload (one shot)
measurement mode
measurement
1
Reload (reload
Continuous
timer)
measurement mode Buffer register is
valid
bit 7
: Undefined value
Pulse-width count
mode
0
Continuous
measurement:
Buffer register is
valid
bit 6
CKS1 CKS0
X
Timer mode
Count clock selection
0
0
Machine clock divided by 4 (0.17µs for machine cycle at
24 MHz)
0
1
Machine clock divided by 16 (0.67 µs for machine cycle
at 24 MHz)
1
0
Machine clock divided by 32 (1.33 µs for machine cycle
at 24 MHz)
1
1
Setting prohibited (Output is undefined)
R/W : Read and write
: Initial value
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13.4
MB90820B Series
Table 13.4-2 PWC control status register (PWCSL0/PWCSL1)
Bit name
Function
•
•
bit7,
bit6
CKS1, CKS0:
Clock select bits
CKS1 and CKS0 bits are used to select the internal count clock.
After reset, the bits are initialized to "00B". The bits can be read and
written. However, "11B" cannot be set.
Note:
After the timer is started, changing the setting is prohibited. Write these
bits before the timer is started or after the timer is stopped.
bit5,
bit4
Reserved bits
•
bit3
S/C:
Single/continuous
bit
• The S/C bit is used to select the count mode.
• After reset, the bit is initialized to "0". The bit can be read and written.
Note:
After the timer is started, changing the setting is prohibited. Write this bit
before the timer is started or after the timer is stopped.
There bits are undefined. Always write "00B" to these bits.
•
bit2
to
bit0
MOD2, MOD1,
MOD0:
Operation mode bits
Setting these bits enables selection of the operating mode and the pulse
edge that fits the pulse-width count.
• After reset, these bits are initialized to "000B". These bits can be read and
written.
Note:
After the timer is started, changing the setting is prohibited. Write these
bits before the timer is started or after the timer is stopped.
•
298
If the continuous measurement mode is set for the setting marked *, the
number of edges are totaled and the divider for the internal count clock is
not cleared at the end of count. In all other modes, the divider for the
internal count clock is cleared at the end of the count.
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
13.4.2
PWC Data Buffer Register (PWC0/PWC1)
The PWC data buffer register (PWC0/PWC1) has functions that depend on the operation
mode of the PWC timer.
■ PWC Data Buffer Register (PWC0/PWC1)
Figure 13.4-4 PWC data buffer register (PWC0/PWC1)
PWC0/PWC1
PWC data buffer register (Upper)
Address: ch.0 0000C3H
ch.1 00002BH
Read/write ⇒
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PW15
PW14
PW13 PW12 PW11
R/W
R/W
R
R/W
R/W
R/W
R
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PW07
PW06
R/W
R/W
PW10 PW09 PW08
Initial value:
xxxxxxxxB
PWC0/PWC1
PWC data buffer register (Lower)
Address: ch.0 0000C2H
ch.1 00002AH
Read/write ⇒
PW05 PW04 PW03
R/W
R/W
R/W
PW02 PW01 PW00
R/W
R/W
Initial value:
xxxxxxxxB
R/W
● Timer mode
In the reload timer operation mode (PWCSL0/PWCSL1:S/C = 1), this register contains the reload value.
The register can be read or written.
In the single timer operation mode (PWCSL0/PWCSL1:S/C = 0), direct access to this register accesses the
up-count timer. In this mode, this register can be read or written. However, the register is written only
when the timer stops. The register can always be read, and the current timer value is read.
● Pulse-width measurement mode (read only)
In the continuous measurement mode (PWCSL0/PWCSL1:S/C = 1), this register functions as the buffer
register and contains the previous count result. This register is read only. Writing to this register has no
effect.
In the single measurement mode (PWCSL0/PWCSL1:S/C = 0), direct access to this register accesses the
up-count timer. In this mode, the register is also read only. Writing to this register has no effect. The
register can always be read, and the current timer value is read. After the count, the register contains the
count results.
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
Note:
To access this register, always use the word transfer instruction.
After reset, this register is initialized to "0000H".
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CHAPTER 13 PWC Timer
13.4
MB90820B Series
13.4.3
Division Ratio Control Register (DIV0/DIV1)
The division ratio control register (DIV0/DIV1) is used in the division period
measurement mode (PWCSL:MOD2, MOD1, and MOD0 = 011B). This register has no
meaning in other modes.
■ Division Ratio Control Register (DIV0/DIV1)
Figure 13.4-5 Division ratio control register (DIV0/DIV1)
Address
ch.0: 0000C4H
ch.1: 00002CH
X
bit7
bit6
bit5
bit4
bit3
bit2
−
−
−
−
−
—
—
—
—
—
:Undefined value
R/W : Readable/Writable
—
bit1
bit0
−
DIV1
DIV0 XXXXXX00B
Initial value
—
R/W
R/W
DIV1
DIV0
0
0
22 = divided by 4
0
1
24 = divided by 16
1
0
26 = divided by 64
1
1
28 = divided by 256
Division ratio selection bits
: Undefined
: Initial value
Table 13.4-3 Division ratio control register (DIV0/DIV1)
Bit name
bit7
to
bit2
Unused bits
Function
•
•
The read value is undefined.
Writing to these bits has no effect on the operation.
•
bit1,
bit0
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DIV1, DIV0:
Division ratio
selection bits
In the division range measurement mode, this register is used to divide the
pulse input from the measurement pin and measure the one-period width
after division.
• After reset, these bits are initialized to "00B". These bits can be read and
written.
Note:
After the timer starts, the setting cannot be changed. Write these bits
before the timer has started or after the timer has stopped.
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PWC Timer Interrupts
The PWC timer is enabled to generate an interrupt request in an overflow of the counter
or measurement terminated in pulse-width measurement mode. It is also coordinated
with the extended intelligent I/O service (EI2OS).
■ PWC Timer Interrupts
Table 13.5-1 lists the interrupt control bits and interrupt causes of the PWC timer.
Table 13.5-1 Interrupt control bits and interrupt causes of the PWC timer
PWC timer 0
PWC timer 1
Interrupt request flag bit
PWCSL0: OVIR
PWCSL0: EDIR
PWCSL1: OVIR
PWCSL1: EDIR
Interrupt request
enable bit
PWCSL0: OVIE
PWCSL0: EDIE
PWCSL1: OVIE
PWCSL1: EDIE
Overflow of the
16-bit up counter
Measurement
terminated in
pulse-width
measurement
mode
Overflow of the
16-bit up
counter
Measurement
terminated in
pulse-width
measurement
mode
Interrupt cause
In the PWC timer, the OVIR bit of the PWC control status register (PWCSL) is set to "1" by an overflow
(from "FFFFH" to "0000H") of the up counter. If an interrupt request is enabled (PWCSL:OVIE = 1) in this
operation, the interrupt request is output to the interrupt controller.
The EDIR bit of the PWC control status register (PWCSL) is set to "1" by measurement terminated in
pulse-width measurement mode. If an interrupt request is enabled (PWCSL:EDIE = 1) in this operation,
the interrupt request is output to the interrupt controller.
■ PWC Timer Interrupts and EI2OS
Table 13.5-2 lists the PWC timer interrupts and EI2OS.
Table 13.5-2 16-bit PWC timer interrupts and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
PWC timer 0*1
#13 (0DH)
ICR01
0000B1H
FFFFC8H
FFFFC9H
FFFFCAH
PWC timer 1*2
#24 (18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
O
*1: The same interrupt number as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt number as that for output compare channel 5 match is assigned to PWC timer 1.
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■ EI2OS Function of the PWC Timer
Since the PWC timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when an
overflow or measurement termination occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when PWC timer 0 uses EI2OS, interrupts of the 16-bit PPG
timer 0 must be disabled.
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Operation of the PWC Timer
The PWC timer is the multi-functional timer based on the 16-bit up-count timer and
contains the count input pin and 8-bit input divider. The block has two main functions:
timer function and pulse-width measurement function. Both the timer function and the
pulse-width measurement function enable the selection for two types of count clocks.
■ Timer Function
The timer function is the up-count timer that enables selection of the operation in single mode or reload
mode.
When the timer is started, a timer count is performed at each count clock.
When an overflow occurs in the range from "FFFFH" to "0000H", an interrupt request is issued.
If an overflow occurs, the following occurs:
During single mode, count is discontinued (see Figure 13.6-1).
During reload mode, the reload register contents are reloaded to the timer, and the count is restarted (see
Figure 13.6-2).
Figure 13.6-1 Timer operation (single mode)
Timer count value
Overflow
Overflow
FFFFH
Write to
PWC
(Restart is invalid)
0000H
Timer starts
Timer starts
OVIR flag setting, Timer stops
OVIR flag setting, Timer stops
Time
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Figure 13.6-2 Timer operation (reload mode)
Timer count value
Overflow
Overflow
Overflow
Overflow
Overflow
FFFFH
(Restart is invalid)
PWC write value
Reload
Reload
0000H
Reload
Reload
Reload Reload
Write to PWC
Timer starts
Restart
Reload
Timer stops
OVIR flag setting
Time
POUT bit
If the timer is started at L level, the level is not toggled when the timer is restarted
(except when an overflow occurs simultaneously)
■ Pulse Width Measurement Function
The pulse-width measurement function calculates the time between the specified events related to the input
pulse.
When this function is activated, a count is started after the specified count start edge is input. If the counter
is cleared to "0000H", a count is started when the start edge is detected, then the stop edge is detected. The
count value during this period is held in the register as the pulse width.
When the measurement terminates or an overflow occurs, an interrupt request can be generated. When the
measurement is completed, the following occurs:
• Single measurement mode
The operation is discontinued (see Figure 13.6-3).
• Continuous measurement mode
The timer value is transferred to the buffer register, and the timer is in free-run state until the next edge
is input (see Figure 13.6-4).
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Figure 13.6-3 Pulse-width measurement operation
(single measurement mode, H width measurement mode)
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
FFFFH
Timer
clears
0000H
Start of
Timer
measurement starts
Timer
stops
EDIR flag setting (termination of measurement)
Time
Figure 13.6-4 Pulse-width measurement operation
(continuous measurement mode, H-width measurement mode)
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
Data transfer
to PWC
FFFFH
0000H
Timer
clears
Data transfer
to PWC
Timer
clears
Start of
Timer
measurement starts
OVIR flag Timer
setting
starts
EDIR flag setting
OVIR flag
setting
EDIR flag setting
(termination of measurement)
Time
*
*: The timer value during this period is not guaranteed (a timer overflow may result in OVIR being set)
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13.6.1
Operation Mode Selection
Operation modes and count modes are selected according to the setting of PWCSL
register.
■ Operation Mode Selection
The following registers are used to set the selection of operation modes and count modes:
● Operation mode setting: PWCSL:MOD2, MOD1, and MOD0 bits
Select the timer mode or pulse-width measurement mode to specify control of the count operation.
● Count mode setting: PWCSL:S/C bit
Select single measurement, continuous measurement, reload operation, or one-shot operation.
Table 13.6-1 lists the operation modes selected using the operation mode bits.
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Table 13.6-1 Operation mode selection
Operation mode
Timer
S/C
MOD2
MOD1
MOD0
One-shot timer
0
0
0
0
Reload timer
1
0
0
0/1
Setting prohibited
0
0
0
1
Single measurement: Buffer invalid
0
0
1
0
Continuous measurement: Buffer
valid
1
0
1
0
Single measurement: Buffer invalid
0
0
1
1
Continuous measurement: Buffer
valid
1
0
1
1
Rising edge to rising
edge:
Rising edge to rising
edge period
measurement
Single measurement: Buffer invalid
0
1
0
0
Continuous measurement: Buffer
valid
1
1
0
0
Rising edge to falling
edge:
H pulse-width
measurement
Single measurement: Buffer invalid
0
1
0
1
Continuous measurement: Buffer
valid
1
1
0
1
Falling edge to rising
edge:
L pulse-width
measurement
Single measurement: Buffer invalid
0
1
1
0
Continuous measurement: Buffer
valid
1
1
1
0
Falling edge to falling
edge:
Falling edge to falling
edge period
measurement
Single measurement: Buffer invalid
0
1
1
1
Continuous measurement: Buffer
valid
1
1
1
1
Rising edge or falling
edge to falling edge or
rising edge:
All edge-to-edge
measurement
Division count:
Divide by 4 to 256
Pulse-width
measurement
After reset, the one-shot timer is selected as an initial value.
Note:
Before the timer starts, always selects the operation mode.
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13.6.2
Starting and Stopping the Timer and Pulse-width
Measurement and Clearing the Timer
To start, restart, and forcibly stop the timer and pulse-width measurement, use the
PWCSH0/PWCSH1:STRT and PWCSH0/PWCSH1:STOP.
The 16-bit up-count timer is cleared to "0000H" at reset, when the measurement start
edge is detected, and the count is started in the pulse-width measurement mode.
■ Starting and Stopping Timer and Pulse Width Measurement
Writing "0" to the PWCSH0/PWCSH1:STRT bit starts or restarts the operation, and writing "0" to the
PWCSH0/PWCSH1:STOP bit stops the operation. However, unless the value is written to these two bits
are different, none of the bits executes operations. If an instruction (byte or word instruction) other than the
bit manipulation instruction is being used, a value is written to the following bit combinations only.
Table 13.6-2
Pulse-width measurement operation (single measurement mode, H width
measurement mode)
Function
STRT
STOP
Starts and restarts the timer or pulse-width measurement
0
1
Stops the timer or pulse-width measurement
1
0
If a bit manipulation instruction (clear bit instruction) is being used, the hardware automatically writes the
above combination of values. The user need not know which value is to be written.
● Operation after start
Timer mode: The count operation is started immediately.
Pulse-width measurement mode: Measurement is started after the measurement start edge is input. After
the measurement start edge is detected, the 16-bit up-count timer is cleared to "0000H" and the count is
started.
● Restarting the timer
While the timer operation continues after the timer is started in the timer mode or pulse-width measurement
mode, restarting the timer (writing "0" to the PWCSH0/PWCSH1:STRT bit) is called timer restart. The
operations to be executed during restart are dependent on the following modes:
One-shot mode: The operation is not affected.
Reload timer mode: Reload is executed and the operation is continued. If the timer is restarted when an
overflow occurs, the overflow flag (PWCSH0/PWCSH1:OVIR) is set and the POUT bit is reversed.
Pulse-width measurement mode: In the measurement start edge wait state, the operation is not affected.
During measurement, the count stops and the timer state returns to the "measurement start edge wait" state.
When the timer is restarted on termination of measurement, the measurement termination flag (PWCSH0/
PWCSH1:EDIR) is set and the measurement results are transferred to PWC in continuous measurement
mode.
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● Stopping the timer
In one-shot timer mode or single measurement mode, measurement is automatically discontinued when the
timer overflows or at the end of a count. The user need not know if the timer has stopped. However, in
other modes, the timer must be stopped. This is also true when the timer is to be stopped before the timer
automatically stops.
● Checking operation state
The previously described STRT and STOP bits function as bits that indicate the operation state of the timer
during a read operation. Table 13.6-3 lists the functions of operation state indication bits.
Table 13.6-3 Functions of operation state indication bits
STRT
STOP
Operation state
0
0
Timer is stopping (except measurement start edge wait state).
The bits indicate that the timer has not started or a measurement has
terminated.
1
1
Measurement start edge wait state or timer count operation
During a read operation, both the STRT bit and the STOP bit have the same value. However, during a read
operation using the read modify write instruction the values of the bits are always "11B". Do not use this
instruction to read the values of the bits.
■ Clearing the Timer
In the following cases, the 16-bit up-count timer is cleared to "0000H":
• During reset
• When a count has started after the count start edge is detected in the pulse-width measurement mode
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13.6.3
Timer Mode Operation
The timer mode includes the one-shot operation mode and reload operation mode.
■ One-shot Operation Mode
When the timer is started in this mode, a counter is incremented at each count clock. The timer
automatically stops when an overflow occurs from "FFFFH" to "0000H".
If PWC0/PWC1 is set before the timer has started, the count is started from this set value. After overflow,
the set value is deleted and the current count value remains in PWC0/PWC1.
PWCSH0/PWCSH1:POUT is reversed if an overflow occurs.
■ Reload Operation Mode
When the timer is started in this mode, the reload value in PWC0/PWC1 is set in the timer and the counter
is incremented at each count clock. If an overflow occurs when the timer counts from "FFFFH" to
"0000H", the reload value in PWC0/PWC1 is set in the timer again, the PWCSH0/PWCSH1:POUT bit is
reversed, and the count operation is repeated. The timer does not stop until a value is written to the
PWCSH0/PWCSH1:STOP bit to stop the timer or it is reset. The port bit will output to pin PWO0/PWO1
if pulse output mode is specified.
The reload value (set in PWC0/PWC1 before the timer is started) is stored during a count. When the timer
is started or restarted and an overflow occurs, the reload value is always set in the timer. If the value that is
set during a count is to be changed, a new reload value becomes valid when the next overflow occurs or the
timer is restarted.
■ Timer Value and Reload Value
In one-shot operation mode, direct access to PWC register accesses the up-count timer. When a value is
written to PWC0/PWC1, the value is directly written to the timer. When PWC0/PWC1 is read during a
count operation, the current timer value is read. If the value is set in PWC before the timer is started, the
timer starts a count from the specified value.
In reload operation mode, the up-count timer cannot be accessed and PWC0/PWC1 functions as a reload
register (stores the reload value). When the timer is started or restarted and an overflow occurs, the value
written to PWC is always set in the timer. When PWC0/PWC1 is read, the stored reload value is read.
The PWC value and timer value are undefined if the timer is set in one-shot mode after the operation is
discontinued in reload mode. Therefore, always set the values before the timer is used.
The PWC value is undefined if the timer is set in reload mode after the operation is forcibly discontinued in
one-shot mode. Therefore, always set the value before the timer is used.
■ Interrupt Request Generation
During operation in timer mode, an overflow enables the generation of an interrupt request. If the
increment of a timer count causes an overflow, the overflow flag is set, an overflow interrupt request is
enabled, and an interrupt request is generated.
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■ Timer Period
If the timer is started in one-shot mode after "0000H" is set in PWC0/PWC1, a timer overflow occurs and
the count is discontinued if the count exceeds "65536". The following formula is used to calculate the time
from start to stop of the timer.
T1 = (65536-n1) x t
{
T1 ...... Time from start to stop of timer (µs)
n1 ...... Timer value set in PWC when the timer is started
t ...... Count clock period (µs)
If the timer is started after "0000H" is set in PWC0/PWC1, a timer overflow occurs every time the count
exceeds "65536". The following formula is used to calculate the reload period and the PWO pin output
pulse period.
TR...... Reload period (overflow period) (µs)
TR = (65536-NR) x t
{
TPOUT ...... PWO0/PWO1 pin output pulse period (µs)
NR ...... Reload value stored in PWC0/PWC1 (µs)
t ...... Time from start to stop of timer (µs)
■ Count Clock Period and Maximum Period
In timer mode, when "0000H" is set in PWC0/PWC1, the maximum period results.
Table 13.6-4 lists the count clock period and maximum timer period corresponding to the machine clock
(indicated by φ in the table) at 24 MHz.
Table 13.6-4 Count clock period and maximum period
Count clock selection
Count clock period
Maximum timer period
312
When CKS1, 0=00B
(φ/4)
When CKS1, 0=01B
(φ/16)
When CKS1, 0=10B
(φ/32)
0.17 µs
0.67 µs
1.33 µs
10.92 ms
43.69 ms
87.38 ms
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■ Flowchart of Timer Mode Operation
Figure 13.6-5 Flowchart of timer mode operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
-Set pulse output initial value
Set value in PWC
Restart
Start by STRT bit
Reload operation mode
Single operation mode
Reload PWC value to timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Discontinue count
Discontinue operation
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13.6.4
MB90820B Series
Pulse Width Measurement Mode Operation
The signal for pulse-width measurement is input from the PWI pin.
The pulse-width measurement mode includes the single measurement mode in which
the count is performed only once and continuous measurement mode in which the
pulse width is continuously measured.
■ Single Measurement Mode and Continuous Measurement Mode
The differences between the single measurement mode and continuous measurement mode are as follows:
● Single measurement mode
When the first count end edge is input, the timer discontinues the count, the count end flag (EDIR) of
PWCSH0/PWCSH1 register is set, and the subsequent measurement is not performed. However, if a timer
restart is also specified, the timer state changes to measurement start edge wait state.
● Continuous measurement mode
[H/L pulse-width measurement mode]
When the count end edge is input, the count end flag (EDIR) of PWCSH0/PWCSH1 is set, the timer count
result is transferred to PWC0/PWC1, and the timer may continue incrementing the count in a free-run state.
When the next count start edge is input, the timer is cleared to "0000H" and the pulse-width count is started.
Note:
When the count end edge is input and the timer enters a free-run state, the timer may overflow and
the OVIR flag may be set. In the H/L pulse-width measurement mode, do not use the OVIR flag to
measure the pulse-width time.
[All edge-to-edge pulse-width measurement mode, division period measurement mode, rising edgeto-rising edge period measurement mode, and falling edge-to-falling edge period measurement mode]
When the count end edge (count start edge) is input, the count end flag (EDIR) of PWCSH0/PWCSH1
register is set, the timer count result is transferred to PWC0/PWC1, the timer is cleared to "0000H", and the
count is restarted.
■ Measurement Result Data
Handling of the measurement result, timer value, and PWC0/PWC1 function varies with the single
measurement mode and continuous measurement mode as follows:
● Single measurement mode
When PWC0/PWC1 is read during timer operation, the current timer value is read.
When PWC0/PWC1 is read after termination of measurement, the measurement results are read.
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● Continuous measurement mode
At termination of measurement, the timer measurement results are transferred to PWC0/PWC1.
When PWC is read, the previous measurement results are read. While measurement is in progress, the
previous measurement results are stored in PWC0/PWC1. During measurement, the timer value cannot be
read.
In continuous measurement mode, unless the previous measurement results are read before completion of
the next measurement, a new measurement result overwrites the existing value. The error flag bit (ERR) of
PWCSH0/PWCSH1 register is set. When PWC0/PWC1 is read, the error flag bit (ERR) is cleared
automatically.
■ Minimum Input Pulse Width
The pulse must be input to the pulse-width count input pin (PWI0/PWI1) longer than the following
minimum input pulse width.
Pulse width: 2 machine cycles (83.3 ns or more for the machine clock at 24 MHz)
However, the input pulse that is shorter than the above specification may also be recognized as a valid
pulse.
■ Calculating Pulse Width/Period
The pulse width or pulse period of the measurement object is calculated based on the count result read from
PWC0/PWC1 at the end of a count as follows.
TW...... Measured pulse width or pulse period (µs)
TW = n x t / Div (µs)
{
n ...... Measurement result contained in PWC0/PWC1
t ...... Count clock period (µs)
Div ...... Division ratio set in the division ratio register (DIV0/DIV1)
(a value of 1 is used in a mode other than the division count mode)
■ Pulse Width/Period Measurement Range
The range of the pulse width/period that can be measured depends on the count clock and division ratio of
an input divider.
Table 13.6-5 lists the measurement range for the machine cycle (indicated by φ) at 24 MHz.
Table 13.6-5 Pulse width measurement range
Division
ratio
DIV1,
DIV1
CKS1, 0=00B (φ/4)
CKS1, 0=01B (φ/16)
CKS1, 0=10B (φ/32)
No division
-
83.3 ns to 10.92 ms [0.17 µs]
83.3 ns to 43.7 ms [0.67 µs]
83.3 ns to 87.38 ms [1.33 µs]
Divide-by 4
00B
83.3 ns to 2.73 ms [41.7 ns]
83.3 ns to 10.92 ms [0.17 µs]
083.3 ns to 21.85 ms [333 ns ]
Divide-by 16
01B
83.3 ns to 682.7 µs [10.4 ns]
83.3 ns to 2.73 ms [41.7 ns]
83.3 ns to 5.46 ms [83.3 ns]
Divide-by 64
10B
83.3 ns to 170.7 µs [2.60 ns]
83.3 ns to 682.7 µs [10.4 ns]
83.3 ns to 1.37 ms [20.83 ns]
Divide-by 256
11B
83.3 ns to 42.7 µs [0.65 ns]
83.3 ns to 170.7 µs [2.60 ns]
83.3 ns to 0.34 ms [5.21 ns]
Note : The number in [ ] indicates the resolution per bit.
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■ Interrupt Request Generation
In the pulse-width measurement mode, the following two interrupt requests can be generated:
● Timer overflow interrupt request
If an overflow occurs during a count, the overflow flag is set. When the overflow interrupt request is
enabled, an interrupt request is generated.
● Measurement termination interrupt request
When the measurement termination edge is detected, the count end flag (EDIR) of PWCSH0/PWCSH1
register is set. If the measurement termination interrupt is enabled, an interrupt request is generated.
The measurement termination interrupt request flag bit (EDIR) is automatically cleared when PWC0/
PWC1 is read.
■ Measurement Mode and Measurement Operation
Table 13.6-6 lists measurement mode operations.
Table 13.6-6 Measurement mode operation (1 / 2)
Measurement
mode
MOD2
MOD1
MOD0
Measurement operation
w
H pulse-width
measurement
1
0
1
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The H period width is measured.
Start of measurement:
Termination of measurement:
When the rising edge is detected
When the falling edge is detected
w
L pulse-width
measurement
1
1
0
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The L period width is measured.
Start of measurement:
End of measurement:
w
Start of
measurement
Rising edge-torising edge period
measurement
1
0
When the falling edge is detected
When the rising edge is detected
w
Termination of
measurement
Start
0
w
Termination
Start
Termination
The rising edge-to-rising edge time is measured.
Start of measurement:
Termination of measurement:
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When the rising edge is detected
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Table 13.6-6 Measurement mode operation (2 / 2)
Measurement
mode
MOD2
MOD1
MOD0
Measurement operation
w
Start of
measurement
Falling edge-tofalling edge period
measurement
1
1
w
Termination of
measurement
Start
w
Termination
Termination
Start
1
The falling edge-to-falling edge time is measured.
Start of measurement:
Termination of measurement:
w
Start of
measurement
All edge pulsewidth measurement
0
1
When the falling edge is detected
When the falling edge is detected
w
w
Termination of
measurement
Start
0
Termination
Start
Termination
The width between continuous input edges is measured.
Start of measurement:
Termination of measurement:
When the edge is detected
When the edge is detected
φ
w
Start of
measurement
Division
measurement
0
1
w
Termination of
measurement
Start
w
Termination
1
(Divided by 4 in the above example.)
The input pulse is divided by the division ratio set in the division ratio
register (DIV0/DIV1), and the measurement period is obtained as a result.
Start of measurement:
The falling edge is detected after the
operation is started.
Termination of measurement:
One period of division signal ends.
W: Pulse width being measured
In all modes, the timer does not start count during the period from the start of measurement to input of
measurement start edge. After the measurement start edge is input, the timer is cleared to "0000H", and the
count is incremented at each count clock until the measurement termination edge is input.
When the measurement termination edge is input, the following operations are executed:
CM44-10147-2E
(1)
The count end flag (EDIR) of PWCSH0/PWCSH1 register is set.
(2)
The timer stops count operation (except if the timer is restarted at the same time the measurement
end edge is input or continuous measurement mode of the H/L pulse-width measurement is used).
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CHAPTER 13 PWC Timer
13.6
MB90820B Series
(3)
Continuous measurement mode: The timer value (measurement result) is transferred to PWC0/
PWC1.
(4)
Single measurement mode: Measurement is terminated (except if the timer is restarted at the
same time the measurement end edge is input).
If all edge-to-edge pulse-width measurement, period measurement, falling edge-to-falling edge period
measurement, or rising edge-to-rising edge period measurement is done in continuous measurement mode,
the termination edge becomes the next measurement start edge.
■ Flowchart of Pulse Width Measurement Operation
Figure 13.6-6 Flowchart of pulse-width measurement mode operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
Restart
Start by STRT bit
Continuous measurement mode
Detect count start edge
Single operation mode
Detect count start edge
Clear timer
Clear timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Overflow occurs
Set OVIR flag
Detect count end edge
Set EDIR flag
Discontinue count*
Transfer timer value to PWC
Detect count end edge
Set EDIR flag
Discontinue count*
Discontinue operation
*: Except continuous measurement mode of H/L pulse-width measurement
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CHAPTER 13 PWC Timer
13.7
MB90820B Series
13.7
Usage Notes on the PWC Timer
Notes on using the PWC timer are given below.
■ Usage Notes on the PWC Timer
● Notes about using a program for setting
• Changing the following PWCS0/PWCS1 register bit values is prohibited during timer operation. The
bit values are changed only before the timer is started or after the operation is discontinued.
[bit7, bit6] CKS1 and CKS0: Count clock selection bits
[bit3] S/C: Measurement mode (single or continuous) selection bit
[bit2 to bit0] MOD2, MOD1, and MOD0: Operation mode and measurement edge selection bits
Note that the value of pulse output level indication bit (POUT: bit 8) remains unchanged even if the bit is
written during timer operation.
• Changing the DIV0/DIV1 value is prohibited during timer operation. Change the DIV0/DIV1 register
value before the timer is started or after the operation has stopped.
• Setting the clock selection bits (CKS1 and CKS0) of PWC control status register (PWCSL0/PWCSL1)
to "11B" is prohibited.
• The PWC0/PWC1 and timer values are determined when the timer is set in the one-shot mode or after
the operation is terminated in reload timer mode. Therefore, always set the values after the timer is
used.
• The PWC0/PWC1 value is undefined if the timer is set in reload timer mode after the operation is
discontinued in the one-shot mode. Therefore, always set the value before the timer is used.
• To change the mode from pulse-width measurement mode to timer mode, always set the value in
PWC0/PWC1 before the timer has started.
• When division period measurement mode is used in pulse-width measurement mode, the input pulse is
divided. Note that the pulse width calculated from the count result becomes a mean value.
• During continuous measurement in pulse-width measurement mode, the division circuit for an internal
count clock is not cleared, and the number of edges smaller than the count clock is added to the count
result.
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CHAPTER 13 PWC Timer
13.7
MB90820B Series
● Notes about using a program for status checking
• In timer mode, the value of the measurement termination interrupt request flag bit (EDIR) of PWCSH0/
PWCSH1 register is insignificant. Therefore, always set "0" in the measurement end interrupt enable bit
(EDIE) of PWCSH0/PWCSH1 register.
• The STRT and STOP bits of upper byte in PWC control status register (PWCSH0/PWCSH1) are
dependent on whether they are read or written (see the details of registers). Read modify write
instruction always reads the bits as "11B". So bit manipulation instruction cannot be used to read the
operation state.
However, a bit manipulation instruction (bit clear instruction) can be used to start or stop the timer by
writing the STRT or STOP bit.
• In the pulse-width measurement mode, the measurement start edge causes the timer to be cleared, and
the previous timer data is insignificant.
● Notes about pulse input to the pulse width measurement input pin
• Minimum pulse width is divide-by 2 of machine cycle (83.33 ns or more for the machine cycle at 24
MHz)
• Maximum input frequency is divide-by 4 of machine cycle (4 MHz or less for the machine clock at 24
MHz)
If a pulse width smaller than the above or a frequency larger than the above is input, the timer operation
is not guaranteed. A noise violating the above constraint and appearing in the input signal must be
reduced.
● Notes about restart the timer during operation
• When an overflow occurs in reload timer mode, the timer is restarted but the overflow flag (OVIR) is set
and the POUT bit is reversed (that is, the same operation as the normal overflow is executed).
• When the measurement termination edge is detected in one-shot pulse-width measurement mode, the
timer is restarted and enters measurement start edge wait state, but the measurement termination flag
(EDIR) is also set.
• When the measurement termination edge is detected in continuous pulse-width measurement mode, the
timer is restarted and enters the measurement start edge wait state, the count termination flag (EDIR) is
set, and the measurement results are transferred to PWC0/ PWC1.
• To restart the timer during operation, note the flag bit (OVIR, EDIR) operations to generate interrupts
and exercise other controls.
● Notes about interrupts
• When the OVIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:OVIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• When the EDIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:EDIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• Since the PWC timer shares an interrupt vector with other resource, interrupt causes must be checked
carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the PWC timer, shared resource interrupts must be disabled.
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CM44-10147-2E
CHAPTER 14
16-BIT PPG TIMER
This chapter describes the activation and operation of
the 16-bit PPG Timer.
14.1 Overview of 16-bit PPG Timer
14.2 Block Diagram of 16-bit PPG Timer
14.3 16-bit PPG Timer Pins
14.4 16-bit PPG Timer Registers
14.5 16-bit PPG Timer Interrupts
14.6 Operation of 16-bit PPG Timer
14.7 Usage Notes on the 16-bit PPG Timer
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CHAPTER 14 16-BIT PPG TIMER
14.1
14.1
MB90820B Series
Overview of 16-bit PPG Timer
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting
register, 16-bit duty setting register, 16-bit control register, and PPG output pin.
■ 16-bit PPG Timer (x 3)
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty
setting register, 16-bit control register, and PPG output pin. This module can be used to output pulses
synchronized by software trigger or GATE signal from multi-functional timer, refer to "CHAPTER 15
MULTI-FUNCTIONAL TIMER".
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected
(φ is the machine clock).
• An interrupt is generated when there is a trigger, an counter borrow, or when PPG rising (normal
polarity) / PPG falling (inverted polarity).
• PPG output operation
The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be
used as D/A converter in conjunction with an external circuit.
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CHAPTER 14 16-BIT PPG TIMER
14.2
MB90820B Series
14.2
Block Diagram of 16-bit PPG Timer
This section shows the block diagram of 16-bit PPG timer.
■ Block Diagram of 16-bit PPG Timer
Figure 14.2-1 Block diagram of 16-bit PPG Timer
Period Setting Buffer Register 0/1/2
Duty Setting Buffer Register 0/1/2
Prescaler
CKS2
CKS1
CKS0
Period Setting Register 0/1/2
F2MC-16LX bus
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Duty Setting Register 0/1/2
Comparator
CLK
LOAD
16-bit down counter
MDSE PGMS OSEL POEN
STOP
START
BORROW
P37/PPG0
or
P40/PPG1
or
P50/PPG2
Machine clock φ
Pin
Down Counter Register 0/1/2
S
Q
PPG0 (multi-functional timer)
or
PPG1 (multi-pulse generator)
or
PPG2
R
Interrupt
selection
Interrupt
#14/#16/#32
GATE - from multi-functional
timer (for PPG ch. 0 only)
IRS1
Edge detection
IRS0
IRQF
IREN
(for PPG ch. 1 & 2)
STGR CNTE RTRG
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CHAPTER 14 16-BIT PPG TIMER
14.3
14.3
MB90820B Series
16-bit PPG Timer Pins
This section describes the pins of the 16-bit PPG timer and provides a pin block
diagram.
■ 16-bit PPG Timer Pins
The pins of the 16-bit PPG timer are shared with the general-purpose I/O ports. Table 14.3-1 lists the
functions of the pins, I/O format, and settings required to use the 16-bit PPG timer.
Table 14.3-1 16-bit PPG timer pins
Pin name
Pin function
I/O format
Pull-up
option
P37/PPG0
Port 3 inputoutput / PPG0
output
CMOS output /
CMOS input
Selectable
P40/PPG1
Port 4 inputoutput / PPG1
output
P50/PPG2
Port 5 inputoutput / PPG2
output
CMOS output /
CMOS
hysteresis input
Standby
control
Settings required for pins
Setting for the PPG timer 0
output (PNCTL0:POEN=1)
Available
Setting for PPG timer 1 output
enable (PNCTL1:POEN=1)
Not provided
Setting for PPG timer 2 output
enable (PNCTL2:POEN=1)
■ Block Diagram of the 16-bit PPG Timer Pins
Figure 14.3-1 Block diagram of the 16-bit PPG timer pins (PPG1, PPG2)
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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CHAPTER 14 16-BIT PPG TIMER
14.3
MB90820B Series
Figure 14.3-2 Block diagram of the 16-bit PPG timer 0 pin (PPG0)
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
About 50 kΩ
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
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CHAPTER 14 16-BIT PPG TIMER
14.4
14.4
MB90820B Series
16-bit PPG Timer Registers
This section shows the register of the 16-bit PPG timer.
■ 16-bit PPG Timer Registers
Figure 14.4-1 Registers of 16-bit PPG timer
PDCR0 to PDCR2
PPG Down Counter Register (Upper)
Address: ch.0 000039H
ch.1 000041H
ch.2 000049H
Read/write
bit 15
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value:
11111111B
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
R
PDCR0 to PDCR2
PPG Down Counter Register (Lower)
Address: ch.0 000038H
ch.1 000040H
ch.2 000048H
bit1 4
R
bit 7
R
bit 6
R
bit 5
R
bit 4
R
bit 3
R
bit 2
bit 1
bit 0
Initial value:
11111111B
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
Read/write
R
R
R
R
R
R
R
R
PCSR0 to PCSR2
PPG Period Setting Buffer Register (Upper)
bit 15 bit1 4 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address: ch.0 00003BH
ch.1 000043H
ch.2 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
Read/write
W
W
W
W
W
W
W
Initial value:
XXXXXXXXB
W
PCSR0 to PCSR2
PPG Period Setting Buffer Register (Lower)
bit 7
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
Address: ch.0 00003AH
Initial value:
ch.1 000042H
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
XXXXXXXXB
ch.2 00004AH
Read/write
W
W
W
W
W
W
W
W
PDUT0 to PDUT2
PPG Duty Setting Buffer Register (Upper)
bit 15 bit1 4 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address: ch.0 00003DH
ch.1 000045H
ch.2 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
Read/write
W
PDUT0 to PDUT2
PPG Duty Setting Buffer Register (Lower)
Address: ch.0 00003CH
ch.1 000044H
ch.2 00004CH
Read/write
W
W
W
W
W
W
bit 7
bit 6
bit 5
bit 4
bit 3
W
bit 2
bit 1
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
W
W
W
W
W
Initial value:
XXXXXXXXB
W
bit 0
Initial value:
XXXXXXXXB
W
(continued)
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
(continued)
PCNTH0 to PCNTH2
PPG Control Status Register (Upper)
Address: ch.0 00003FH
ch.1 000047H
ch.2 00004FH
bit 15
R/W
PCNTL0 to PCNTL2
PPG Control Status Register (Lower)
R/W
bit 7
Address: ch.0 00003EH
ch.1 000046H
ch.2 00004EH
CM44-10147-2E
bit 13
bit 12
bit 11
CNTE STGR MDSE RTRG CKS2
Read/write
Read/write
bit1 4
-
-
R/W
bit 6
R/W
bit 5
R/W
bit 4
bit 10
bit 9
bit 8
CKS1 CKS0 PGMS
R/W
bit 3
IREN
IRQF
IRS1
IRS0
R/W
R/W
R/W
R/W
R/W
bit 2
R/W
bit 1
POEN OSEL
R/W
FUJITSU MICROELECTRONICS LIMITED
Initial value:
00000000B
bit 0
Initial value:
XX000000B
R/W
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CHAPTER 14 16-BIT PPG TIMER
14.4
14.4.1
MB90820B Series
PPG Down Counter Register (PDCR0 to PDCR2)
PPG down counter registers (PDCR0 to PDCR2) are 16-bit registers, which are used to
read the count value of the 16-bit PPG down counter.
■ PPG Down Counter Register (PDCR0 to PDCR2)
Figure 14.4-2 PPG down counter register (PDCR0 to PDCR2)
PDCR0 to PDCR2
PPG Down Counter Register (Upper)
Address: ch.0 000039H
ch.1 000041H
ch.3 000049H
Read/write
bit 15
DC15
bit1 4
DC14
R
bit 13
bit 12
DC13 DC12
bit 11
bit 10
bit 9
DC11
DC10
DC09
DC08
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 8
Initial value:
11111111B
PDCR0 to PDCR2
PPG Down Counter Register (Lower)
Address: ch.0 000038H
ch.1 000040H
ch.3 000048H
Read/write
DC07
DC06
R
R
DC05 DC04
R
R
DC03
R
bit 2
DC02
R
bit 1
DC01
R
DC00
bit 0
Initial value:
11111111B
R
These are 16-bit registers that are used to store the values of the 16-bit down counter. The initial value of
them are all 1. Word access instruction to these register are recommended. These registers are read only.
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
14.4.2
PPG Period Setting Buffer Register (PCSR0 to PCSR2)
PPG period setting buffer register is used to set the period of the output pulses
generated by PPG.
Figure 14.4-3 PPG period setting buffer register (PCSR0 to PCSR2)
PCSR0 to PCSR2
PPG Period Setting Buffer Register (Upper)
bit 15 bit1 4
Address: ch.0 00003B
ch.1
ch.3
H
000043H
00004BH
Read/write
CS15
W
CS14
W
bit 13
bit 12
CS13 CS12
W
W
bit 11
bit 10
bit 9
CS11
CS10
CS09
CS08
W
W
W
W
bit 8
Initial value:
XXXXXXXXB
PCSR0 to PCSR2
PPG Period Setting Buffer Register (Lower)
bit 7
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
Address: ch.0 00003AH
ch.1 000042H
ch.3 00004AH
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
Read/write
W
W
W
W
W
W
W
Initial value:
XXXXXXXXB
W
These are 16-bit registers that are used to set the period of the output pulses generated by PPG. The initial
value of them are undetermined, so that these registers must be written before starting an operation. Word
access instruction to these registers are recommended. These registers are write-only.
Data transfer from PPG period setting buffer register to period setting register will be at counter borrow,
trigger, or retrigger, if enabled.
Note :
In case of updating PPG period setting buffer register, duty setting buffer register must be written
after writing to PPG period setting buffer register. Only updating PPG period setting buffer register is
prohibited.
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CHAPTER 14 16-BIT PPG TIMER
14.4
14.4.3
MB90820B Series
PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
PPG duty setting buffer register is used to control the duty ratio of the output pulses
generated by PPG.
Figure 14.4-4 PPG duty setting buffer register (PDUT0 to PDUT2)
PDUT0 to PDUT2
PPG Duty Setting Buffer Register (Upper)
Address: ch.0 00003DH
ch.1 000045H
ch.3 00004DH
Read/write
bit 15
DU15
W
bit1 4
DU14
W
bit 13
bit 12
DU13 DU12
W
W
bit 11
bit 10
bit 9
bit 8
DU11
DU10
DU09
DU08
W
W
W
W
Initial value:
XXXXXXXXB
PDUT0 to PDUT2
PPG Duty Setting Buffer Register (Lower)
bit 7
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
Address: ch.0 00003CH
ch.1 000044H
ch.3 00004CH
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
Read/write
W
W
W
W
W
W
W
Initial value:
XXXXXXXXB
W
These are 16-bit registers that are used to control the duty ratio of the output pulses generated by PPG. The
initial value of them are undetermined, so that these registers must be set a value before starting an
operation. Word access instruction to these registers are recommended. These registers are write-only.
Data transfer from PPG duty setting buffer register to duty setting register is at counter borrow, trigger, or
retrigger if enabled.
Setting the same value in both the PPG period setting register and duty setting register outputs all "H"s for
normal polarity and all "L"s for inverted polarity.
The output of the PPG is undefined if PCSR < PDUT.
Note :
PPG duty setting buffer register can be written in the case of not updating PPG period setting buffer
register.
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
14.4.4
PPG Control Status Register (PCNTL0 to PCNTL2,
PCNTH0 to PCNTH2)
PPG control status register is used to set operating conditions for 16-bit PPG timer
enable or disable operation, software trigger, retrigger control interrupt, and output
polarity and check the status
■ PPG Control Status Register, Upper Byte (PCNTH0 to PCNTH2)
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
Figure 14.4-5 PPG control register, upper byte (PCNTH0 to PCNTH2)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch.0: 00003FH
ch.1: 000047H
ch.2: 00004FH
CNTE
STGR
MDSE
RTRG
CKS2
CKS1
CKS0
PGMS
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 8
PGMS
PPG output mask enable bit
0
PPG output masking disabled
1
PPG output masking enabled
bit 11 bit 10 bit 9
CKS2 CKS1 CKS0
0
0
Counter clock selection bits
φ (41.7 ns, φ = 24 MHz)
0
0
0
1
φ/2 (83.3 ns, φ = 24 MHz)
0
1
0
φ/4 (167 ns, φ = 24 MHz)
0
1
1
φ/8 (333 ns, φ = 24 MHz)
1
0
0
φ/16 (0.67 µs, φ = 24 MHz)
1
0
1
φ/32 (1.33 µs, φ = 24 MHz)
1
1
0
φ/64 (2.67 µs, φ = 24 MHz)
1
1
1
φ/128 (5.33 µs, φ = 24 MHz)
bit 12
φ: Machine clock
RTRG
Retrigger enable bit
0
Retriggering disabled
1
Retriggering enabled
bit 13
MDSE
Mode selection bit
0
PWM mode
1
Single-shot mode
bit 14
Software trigger bit
STGR
write
0
No software trigger
1
Software trigger
read
Always read “0”
bit 15
R/W : Read and Write
: Initial value
332
CNTE
Timer enable bit
0
Stop the PPG timer
1
Enable the PPG timer
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
Table 14.4-1 PPG control status register, upper byte (PCNTH0 to PCNTH2) bit
Bit name
Function
•
This bit is used to enable the PPG timer operation.
Writing "1" will enable the PPG operation and wait for trigger to
start PPG operation.
Writing "0" will stop the operation.
This bit is the software trigger bit for PPG.
Writing "1" to this bit triggers the PPG by software.
This bit is always read as "0".
bit15
CNTE:
Timer enable
bit
STGR:
Software trigger
bit
•
bit14
bit13
MDSE:
Mode selection bit
When this bit is "0", PPG operates in PWM mode.
When this bit is "1", PPG operates in single-shot mode.
bit12
RTRG:
Retrigger enable
bit
bit11
to
bit9
CKS2, CKS1,
CKS0:
Counter clock
selection bits
•
•
This bit is used to enable retriggering function of PPG during
operation.
When this bit is "0", retriggering function is disabled.
When this bit is "1", retriggering function is enabled.
•
These bits are used to select the operation clock for 16-bit PPG
timer.
•
bit8
CM44-10147-2E
PGMS: PPG
output mask
enable bit
This bit is used to mask the PPG output to specific level regardless
of the mode setting (PCNTH:MDSE), period setting (PCSR), or
duty setting (PDUT).
Write "0" will disable PPG output masking function.
Writing "1" to this bit masks the PPG output to always "L" when
polarity setting is “Normal” (PCNTL:OSEL=0).
Writing "1" to this bit masks the PPG output to always "H" when
polarity setting is "Inverted" (PCNTL:OSEL=1).
Note:
By setting PPG period setting buffer register (PCSR) and PPG duty
setting buffer register (PDUT) with same value, all "H" in normal
polarity or all "L" in inverted polarity can be outputted when this
bit is "1".
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CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
■ PPG Control Status Register, Lower Byte (PCNTL1 to PCNTL3)
Figure 14.4-6 PPG control register (PCNTL1 to PCNTL3)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0: 00003EH
ch.1: 000046H
ch.2: 00004EH
−
−
IREN
IRQF
IRS1
IRS0
POEN
OSEL
XX000000B
R/W
R/W
R/W
R/W
R/W
R/W
bit 0
OSEL
Output inversion bit
0
Normal polarity
1
Inverted polarity
bit 1
POEN
Output enable bit
0
General-purpose I/O pin (P37/P40/P50)
1
PPG output pin (PPG0/PPG1/PPG2)
bit 3
bit 2
IRS1
IRS0
Interrupt type
0
0
Gate trigger (channel 0 only) / Software trigger /
Retrigger
0
1
Counter borrow
1
0
PPG output rising in normal polarity or PPG output
falling in inverted polarity (duty match)
1
1
Counter borrow, PPG output rising in normal
polarity, or PPG output falling in inverted polarity
bit 4
PPG interrupt request flag
IRQF
R/W : Read and Write
-
: Undefined
: Initial value
334
Read
Write
0
No PPG interrupt generated
Clear this bit
1
PPG interrupt generated
No effect
bit 5
IREN
PPG interrupt request enable bit
0
Interrupt request disabled
1
Interrupt request enabled
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CM44-10147-2E
CHAPTER 14 16-BIT PPG TIMER
14.4
MB90820B Series
Table 14.4-2 PPG control status register (PCNTL1 to PCNTL3)
Bit name
CM44-10147-2E
bit7,
bit6
Undefined bits
bit5
IREN:
PPG interrupt
request enable
bit
bit4
IRQF:
PPG interrupt flag
bit
bit3,
bit2
IRS1, IRS0:
Interrupt
selection bits
bit1
POEN:
Output
enable bit
bit0
OSEL:
Output
inversion bit
Function
These read value are undefined.
Writing to these bits has no effect on the operation.
•
•
This bit enables or disables PPG interrupt request to the CPU.
When this bit and the interrupt flag (IRQF) bit are "1", PPG outputs
an interrupt request.
•
•
•
This bit is set to 1 when PPG interrupt occurs.
Writing "0" will clear this bit.
Writing 1 has no effect.
In read-modify-write operation, "1" is always read.
This bit is also cleared when EI2OS is activated.
•
These bits are used to select interrupt operation of the PPG timer.
•
This bit enables or disables output from the PPG output pin.
When this bit is "0", the pin functions as a general-purpose port.
When this bit is "1", the pin functions as a PPG timer output pin.
•
This bit selects the polarity of PPG output pin.
When this bit is "0", normal polarity is selected. PPG outputs "L"
when 16-bit down count vlaue is greater than PDUT, and outputs
"H" when smaller than or equals to PDUT.
When this bit is "1", the PPG output is inverted.
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CHAPTER 14 16-BIT PPG TIMER
14.5
14.5
MB90820B Series
16-bit PPG Timer Interrupts
The 16-bit PPG timer is enabled to generate an interrupt request when trigger or counter
borrow, PPG rising in normal polarity, or PPG falling in inverted polarity depending on
PCNTL : IRS1 and IRS0 setting. It is also coordinated with the extended intelligent I/O
service (EI2OS).
■ 16-bit PPG Timer Interrupts
Table 14.5-1 lists the interrupt control bits and interrupt causes of the 16-bit PPG timer.
Table 14.5-1 Interrupt control bits and interrupt causes of the 16-bit PPG timer
16-bit PPG timer 0
Interrupt flag bit
16-bit PPG timer 1
16-bit PPG timer 2
PCNTL0:IRQF
PCNTL1:IRQF
PCNTL2:IRQF
Interrupt request enable bit PCNTL0:IREN
PCNTL1:IREN
PCNTL2:IREN
Interrupt type selection bits PCNTL0:IRS1, IRS0
PCNTL1:IRS1, IRS0
PCNTL2:IRS1, IRS0
PCNTL0:IRS1, IRS0=00
gate trigger/software
trigger/retrigger of 16-bit
down counter 0
PCNTL1:IRS1, IRS0=00
software trigger/retrigger
of 16-bit down counter 1
PCNTL2:IRS1, IRS0=00
software trigger/retrigger
of 16-bit down counter 2
PCNTL0:IRS1, IRS0=01
counter borrow of 16-bit
down counter 0
PCNTL1:IRS1, IRS0=01
counter borrow of 16-bit
down counter 1
PCNTL2:IRS1, IRS0=01
counter borrow of 16-bit
down counter 2
PCNTL0:IRS1, IRS0=10
PPG0 output rising in
normal polarity or PPG0
output falling in inverted
polarity
PCNTL1:IRS1, IRS0=10
PPG1 output rising in
normal polarity or PPG1
output falling in inverted
polarity
PCNTL2:IRS1, IRS0=10
PPG2 output rising in
normal polarity or PPG2
output falling in inverted
polarity
PCNTL0:IRS1, IRS0=11
Counter borrow of 16-bit
down counter 0, PPG0
output rising in normal
polarity, or PPG0 output
falling in inverted polarity
PCNTL0:IRS1, IRS0=11
Counter borrow of 16-bit
down counter 1, PPG1
output rising in normal
polarity, or PPG1 output
falling in inverted polarity
PCNTL0:IRS1, IRS0=11
Counter borrow of 16-bit
down counter 2, PPG2
output rising in normal
polarity, or PPG2 output
falling in inverted polarity
Interrupt cause
In the 16-bit PPG timer, the IRQF bit of the PPG control status register (PCNTL) is set to "1" and an
interrupt request is enabled (PCNTL: IREN=1), the interrupt request is outputted to the interrupt controller.
336
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CM44-10147-2E
CHAPTER 14 16-BIT PPG TIMER
14.5
MB90820B Series
■ 16-bit PPG Timer Interrupts and EI2OS
Table 14.5-2 lists the 16-bit PPG timer interrupts and EI2OS.
Table 14.5-2 16-bit PPG timer interrupts and EI2OS
Channel
Interrupt control
register
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
16-bit PPG
timer 0*1
#14 (0EH)
ICR01
0000B1H
FFFFC4H
FFFFC5H
FFFFC6H
16-bit PPG
timer 1*2
#16 (10H)
ICR02
0000B2H
FFFFBCH
FFFFBDH
FFFFBEH
16-bit PPG
timer 2*3
#32 (20H)
ICR10
0000BAH
FFFF7CH
FFFF7DH
FFFF7EH
O
*1: The same interrupt control register as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt control register as that for 16-bit PPG timer 1 is assigned to 16-bit output compare channel 1 match.
*3: The same interrupt control register as that for 16-bit PPG timer 2 is assigned to 16-bit free-run timer zero detection.
■ EI2OS Function of the 16-bit PPG Timer
Since the 16-bit PPG timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when
PPG interrupt occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts . For example, when 16-bit PPG timer 0 uses EI2OS, the output compare
channel 0 match must be disabled.
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CHAPTER 14 16-BIT PPG TIMER
14.6
14.6
MB90820B Series
Operation of 16-bit PPG Timer
The 16-bit PPG timer operates in either PWM mode or single-shot mode. And
Retriggering can be enabled.
■ PWM Mode (PCNTL: MDSE = 0)
For PWM opertion, the 16-bit down counter will be loaded with PCSR value, starts counting after a valid
trigger is detected. And once the 16-bit down counter reached zero, it is reloaded with PCSR value and
repeat counting again. PPG output is toggled when 16-bit down counter is reloaded. The period of the
output pulses can be controlled by setting PCSR register, and the duty ratio controlled by setting PDUT.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Figure 14.6-1 Retriggering is disabled in PWM mode
Counter value
m
n
0
Time
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
(inverted polarity)
(1)
(2)
(1) = (n+1) × T ns
(2) = (m+1) × T ns
338
T: Count clock period
m: PCSR value
n: PDUT value
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CHAPTER 14 16-BIT PPG TIMER
14.6
MB90820B Series
b) Retriggering is enabled (PCNTH: RTRG = 1)
Figure 14.6-2 Retriggering is enabled in PWM mode
Counter value
m
n
Time
0
Rising edge detected
Restarted by trigger
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
(1) = (n+1) × T ns
(2) = (m+1) × T ns
■ Single-shot Mode (PCNTL: MDSE = 1)
For single-shot opertion, a single pulse of specified width can be output by a valid trigger. When
retriggering is enabled, the counter is reloaded if an edge is detected during operation.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Figure 14.6-3 Retriggering is disabled in single-shot mode
Counter value
m
n
Time
0
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
(1) = (n+1) × T ns
(2) = (m+1) × T ns
CM44-10147-2E
T: Count clock period
m: PCSR value
n: PDUT value
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CHAPTER 14 16-BIT PPG TIMER
14.6
MB90820B Series
b) Retriggering is enabled (PCNTH: RTRG = 1)
Figure 14.6-4 Retriggering is enabled in single-shot mode
Counter value
m
n
Time
0
Software trigger
Rising edge detected
Restarted by trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(1) = (n+1) × T ns
(2) = (m+1) × T ns
(2)
T: Count clock period
m: PCSR value
n: PDUT value
■ Gate Trigger (PPG channel 0 only)
When gate trigger is used, PPG starts operation when rising edge of gate trigger is detected and stops when
falling is detected. In next rising edge, PPG restarts operation.
Figure 14.6-5 Gate trigger in PWM mode when retriggering is enable
Counter value
m
n
0
Time
Rising edge detected
Falling edge detected
Gate trigger
PPG
(normal polarity)
(inverted polarity)
(1)
(2)
(1) = (n+1) × T ns
(2) = (m+1) × T ns
340
T: Count clock period
m: PCSR value
n: PDUT value
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CM44-10147-2E
CHAPTER 14 16-BIT PPG TIMER
14.6
MB90820B Series
■ PPG Interrupts
There are four types of interrupts sharing one interrupt flag (PCNTL:IRQF) selected by interrupt type
selection bits (PCNTL:IRS1 and IRS0).
• Gate trigger (for PPG channel 0 only), software trigger, or retrigger
• Counter borrow
• Duty match occurs when PPG output rising in normal polarity or PPG output falling in inverted polarity
• Counter borrow or duty match
Figure 14.6-6 PPG interrupt timing
Software trigger
Load
Count clock
Counter value
0002H
0001H
0000H
0002H
PPG output
(normal polarity)
Interrupt
(by software trigger)
Interrupt
(by duty match)
Interrupt
(by counter borrow)
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CHAPTER 14 16-BIT PPG TIMER
14.7
14.7
MB90820B Series
Usage Notes on the 16-bit PPG Timer
Notes on using the 16-bit PPG timer are given below.
■ Usage Notes on the 16-bit PPG Timer
● Notes on using a program for setting
• When write a value to the PPG period setting buffer register (PCSR), PPG duty setting buffer register
(PDUT) must be written after writing to PCSR. Only updating PCSR is prohibited. Be sure to use a
word transfer instruction (MOVW A, dir, etc.) to access PCSR and PDUT.
• Always set the value of PPG duty setting buffer register (PDUT) not greater than PPG period setting
buffer register (PCSR), otherwise the output of PPG is undefined.
• Change the CKS2, CKS1 and CKS0 bits of the PPG control status register (PCNTH) when the PPG is
stopped (PCNTH: CNTE=0).
● Notes about interrupts
• When the IRQF bit of the PPG control status register (PCNTL) is set to "1" and an interrupt request is
enabled (PCNTL: IREN = 1), control cannot be returned from interrupt processing. Always clear the
IRQF bit.
• Since the 16-bit PPG timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit PPG timer, shared resource interrupts must be disabled.
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CM44-10147-2E
CHAPTER 15
MULTI-FUNCTIONAL TIMER
This chapter describes the functions and operation of
the multi-functional timer.
15.1 Overview of Multi-functional Timer
15.2 Block Diagram of Multi-functional Timer
15.3 Multi-functional Timer Pins
15.4 Registers of Multi-functional Timer
15.5 Multi-functional Timer Interrupts
15.6 Operation of Multi-functional Timer
15.7 Usage Notes on the Multi-functional Timer
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.1
15.1
MB90820B Series
Overview of Multi-functional Timer
The multi-functional timer consists of a 16-bit free-run timer, six 16-bit output compare,
four 16-bit input capture, 1 channel of 16-bit PPG timer, and a waveform generator. By
using this waveform generator, 12 independent waveform can be outputted through 16bit free-run timer. Furthermore, input pulse width measurement and external clock cycle
measurement can be done.
■ 16-bit Free-run Timer (x 1)
• The 16-bit free-run timer consists of a 16-bit up/up-down counter, timer control status register, 16-bit
compare clear register (with buffer register) and a prescaler.
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected (φ is the
machine clock).
• Compare clear interrupt is generated when there is a compare match with compare clear register and 16bit free-run timer. Zero detection interrupt is generated while 16-bit free-run timer is detected as zero in
count value.
• The compare clear register has a selectable buffer register, into which data is written for transfer to the
compare clear register. When 16-bit free-run the timer is stopped, transfer occurs immediately when the
data is written to the buffer. When the timer is in operation, data transfer from the buffer occurs when
the timer value is detected to be zero.
• Reset, software clear, compare match with compare clear register in up-count mode will reset the
counter value to “0000H”.
• The output value of this counter can be used as the count clock of the output compares and input
captures in multi-functional timer.
■ 16-bit Output Compare (x 6)
• The 16-bit output compare consists of six 16-bit output compare registers (with selectable buffer
register), compare output latch, and compare control registers. An interrupt is generated and output level
is inverted when the value of 16-bit free-run timer and output compare register are matched.
• 6 output compare registers can be operated independently.
Output pins and interrupt flag are corresponding to each output compare register.
• 2 output compare registers can be paired to control the output pins.
Inverts output pins by using 2 output compare registers together.
• Setting the initial value for each output pin is possible.
• An interrupt is generated when output compare register is matched with 16-bit free-run timer.
■ 16-bit Input Capture (x 4)
Input capture consists of 4 independent external input pins, the corresponding input capture register, and
input capture control register. By detecting any edge of the input signal from the external pin, the value of
the 16-bit free-run timer can be stored in the capture register and an interrupt is generated simultaneously.
• 3 types of trigger edge (rising edge, falling edge, and both edges) of the external input signal can be
selected and there is indication bit to show the trigger edge is rising or falling.
• 4 input captures can be operated independently.
• An interrupt is generated by detecting a valid edge from external input.
• Channel 0 and 1 share interrupt #33.
• Channel 2 and 3 share interrupt #35.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.1
MB90820B Series
■ 16-bit PPG Timer (x 1)
The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. The detail of 16-bit PPG
timer 0 is described in "CHAPTER 14 16-BIT PPG TIMER".
■ Waveform Generator
The waveform generator consists of three 16-bit timer registers, three timer control registers, and one 16-bit
waveform control register.
With waveform generator, it is possible to generate realtime output, 16-bit PPG waveform output, nonoverlap 3-phase waveform output for inverter control and DC chopper waveform output.
• It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time
timer function)
• It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel
mode. (Dead-time timer function)
• By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated
to start or stop PPG timer operation. (GATE function)
• When a match is detected by realtime output compare, the 16-bit timer is activated. The PPG timer can
be started or stopped easily by generating a GATE signal for PPG operation. (GATE function)
• Forced stop control using DTTI pin input
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.2
15.2
MB90820B Series
Block Diagram of Multi-functional Timer
The block diagram of the multi-functional timer will be described in the following
sections.
■ Block Diagram of Multi-functional Timer
Figure 15.2-1 Block diagram of multi-functional timer
Real time I/O
16-bit output
compare
Interrupt #12
Interrupt #15
Interrupt #17
Interrupt #19
Interrupt #21
Interrupt #23
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
Waveform
generator
F2MC-16LX bus
16-bit freerun timer
A/D trigger
Zero detect
Compare clear
RTO1
Pin
P83/RTO1 (X)
RTO2
Pin
P84/RTO2 (V)
RTO3
Pin
P85/RTO3 (Y)
RTO4
Pin
P86/RTO4 (W)
RTO5
Pin
P87/RTO5 (Z)
DTTI
Pin
P10/INT0/DTTI
16-bit timer 0/1/2
underflow
Interrupt #20
DTTI falling edge detect
PPG0
PPG0
GATE
GATE
Pin
P75/FRCK/AN13
IN0
Pin
P76/IN0/AN14
IN1
Pin
P77/IN1/AN15
IN2
Pin
P80/IN2
IN3
Pin
P81/IN3
Interrupt #33
Interrupt #35
16-bit input
capture
Interrupt #29
A/D trigger
EXCK
346
P82/RTO0 (U)
Counter value
Interrupt #31
Interrupt #34
Counter value
Pin
RT0 to RT5
RT0 to RT5
Data transfer
from buffer
RTO0
Input capture 0/1
Input capture 2/3
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.2
MB90820B Series
■ Block Diagram of 16-bit Free-run Timer
Figure 15.2-2 Block diagram of 16-bit free-run timer
φ
STOP
STOP
MODE
SCLR
UP/UP-DOWN
CLK2
CLK1
CLK0
Prescaler
CLR
Zero detect
circuit
16-bit free-run
timer
Zero detect (to output compare)
CK
To input capture &
output compare
transfer
F2MC-16LX bus
16-bit compare
clear register
Compare circuit
Compare clear match (to output compare)
16-bit compare clear
buffer register
I0
I1
I1
I0
O
Interrupt #34 (22H)
Selector
Selector
O
I0
I1
O
Interrupt #31 (1FH)
Selector
Mask circuit
A/D trigger
MSI2
MSI1
MSI0
ICLR
ICRE
IRQZF
IRQZE
I1
I0
O
Selector
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.2
MB90820B Series
■ Block Diagram of 16-bit Output Compare
Figure 15.2-3 Block diagram of 16-bit output compare
Count value from free-run timer
BTS0
BUF0
Output compare buffer register
0/2/4
O
Output compare register 0/2/4
F2MC-16LX bus
Zero detect from
free-run timer
Compare clear match from
free-run timer
I0
transfer
I1
Selector
BTS1
BUF1
Compare circuit
I0
O
Output compare buffer register
1/3/5
Selector
transfer
Output compare register 1/3/5
I1
CMOD
Compare circuit
IOP1
IOP0
IOE1
T
Q
RT0/2/4
(Waveform
generator)
T
Q
RT1/3/5
(Waveform
generator)
IOE0
Interrupt
#12, #17, #21
#15, #19, #23
■ Block Diagram of 16-bit Input Capture
Figure 15.2-4 Block diagram of 16-bit input capture
Count value from free-run timer
F2MC-16LX bus
IN0/IN2
Edge detect
Input capture register 0/2
EG11
EG10 EG01 EG00
Edge detect
Input capture register 1/3
ICP0
ICP1
ICE0
IEI1
IEI0
IN1/IN3
ICE1
Interrupt
#33, #35
#33, #35
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.2
MB90820B Series
■ Block Diagram of Waveform Generator
Figure 15.2-5 Block Diagram of Waveform Generator
DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0
φ
DTTI control circuit
Divider
PICSH01
DTCR0 TMD2
TMD1
TMD0
SIGCR
Noise cancellation
DTTI
PGEN1 PGEN0
GTEN1 GTEN0
GATE 0/1
GATE
(to PPG0)
TO0
Waveform control
RT0
Selector
16-bit timer 0
Compare circuit
Selector
Output control
TO1
RT1
RTO1 (X)
U
16-bit timer register 0
RTO0 (U)
Dead time generator
X
DTCR1 TMD2
TMD1
TMD0
F2MC-16LX bus
PICSH01
GTEN1 GTEN0
GATE 2/3
PGEN3 PGEN2
TO2
Waveform control
RT2
Selector
16-bit timer 1
Compare circuit
Selector
Output control
TO3
RT3
RTO3 (Y)
V
16-bit timer register 1
RTO2 (V)
Dead time generator
Y
DTCR2 TMD2
TMD1
TMD0
GTEN1 GTEN0
GATE 4/5
PICSH01 PGEN5 PGEN4
TO4
Waveform control
RT4
Selector
16-bit timer 2
Compare circuit
Selector
W
16-bit timer register 2
Output control
TO5
RT5
RTO4 (W)
RTO5 (Z)
Dead time generator
PPG0
Z
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.3
15.3
MB90820B Series
Multi-functional Timer Pins
This section describes the pins of the multi-functional timer and provides a pin block
diagram.
■ Multi-functional Timer Pins
Table 15.3-1 Multi-functional timer pins
Standby
control
Pin function
P10/INT0/
DTTI
Port 1 inputoutput/external
interrupt input/
DTTI
P75/FRCK/
AN13
Port 7 inputoutput/external
clock
Set the pin as an input port
(DDR7:bit 13 = 0)
P76/IN0/
AN14
Port 7 inputoutput/input
capture 0
Set the pin as an input port
(DDR7:bit 14 = 0)
P77/IN1/
AN15
Port 7 inputoutput/input
capture 1
Set the pin as an input port
(DDR7:bit 15 = 0)
P80/IN2
Port 8 inputoutput/input
capture 2
P81/IN3
Port 8 inputoutput/input
capture 3
P82/RTO0
(U)
Port 8 inputoutput/RTO0
Set RTO0 output
(OCS1:OTE0 = 1)
P83/RTO1
(X)
Port 8 inputoutput/RTO1
Set RTO1 output
(OCS1:OTE1 = 1)
P84/RTO2
(V)
Port 8 inputoutput/RTO2
Set RTO2 output
(OCS3:OTE0 = 1)
P85/RTO3
(Y)
Port 8 inputoutput/RTO3
Set RTO3 output
(OCS3:OTE1 = 1)
P86/RTO4
(W)
Port 8 inputoutput/RTO4
Set RTO4 output
(OCS5:OTE0 = 1)
P87/RTO5
(Z)
Port 8 inputoutput/RTO5
Set RTO5 output
(OCS5:OTE1 = 1)
350
I/O format
Pull-up
option
Pin Name
Set the pin as an input port
(DDR1:bit 8 = 0)
Selectable
CMOS
output/
CMOS
hysteresis
input
Setting required for pins
Set the pin as an input port
(DDR8:bit 0 = 0)
Provided
Not provided
FUJITSU MICROELECTRONICS LIMITED
Set the pin as an input port
(DDR8:bit 1 = 0)
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.3
MB90820B Series
■ Block Diagram of Multi-functional Timer Pins
Figure 15.3-1 Block diagram of P10/INT0/DTTI
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50kΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 15.3-2 Block diagram of P75/FRCK/AN13 to P77/IN1/AN15
A/D converter input
A/D converter channel selection bit
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
351
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.3
MB90820B Series
Figure 15.3-3 Block diagram of P80/IN2 to P81/IN3
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 15.3-4 Block diagram of P82/RTO0 to P87/RTO5
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
352
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4
Registers of Multi-functional Timer
This section describes registers of multi-functional timer.
■ 16-bit Free-run Timer Registers
Figure 15.4-1 Registers of 16-bit free-run timer
Compare Clear Buffer Register / Compare Clear Register (Upper)
bit
Address: 00005BH
Read/write ⇒
Initial value ⇒
15
CL15
R/W
1
14
CL14
R/W
1
13
CL13
R/W
1
12
CL12
R/W
1
11
CL11
R/W
1
10
CL10
R/W
1
9
CL09
R/W
1
8
CL08
R/W
1
CPCLRB/CPCLR
Compare Clear Buffer Register / Compare Clear Register (Lower)
bit
Address: 00005AH
Read/write ⇒
Initial value ⇒
7
CL07
R/W
1
6
CL06
R/W
1
5
CL05
R/W
1
4
CL04
R/W
1
3
CL03
R/W
1
2
CL02
R/W
1
1
CL01
R/W
1
0
CL00
R/W
1
14
T14
R/W
0
13
T13
R/W
0
12
T12
R/W
0
11
T11
R/W
0
10
T10
R/W
0
9
T09
R/W
0
8
T08
R/W
0
6
T06
R/W
0
5
T05
R/W
0
4
T04
R/W
0
3
T03
R/W
0
2
T02
R/W
0
1
T01
R/W
0
0
T00
R/W
0
12
MSI2
R/W
0
11
MSI1
R/W
0
10
MSI0
R/W
0
9
ICLR
R/W
0
8
ICRE
R/W
0
5
4
3
STOP MODE SCLR
R/W
R/W
R/W
1
0
0
2
CLK2
R/W
0
1
CLK1
R/W
0
0
CLK0
R/W
0
CPCLRB/CPCLR
Timer Data Register (Upper)
bit
Address: 00005DH
Read/write ⇒
Initial value ⇒
15
T15
R/W
0
TCDT
Timer Data Register (Lower)
bit
Address: 00005CH
Read/write ⇒
Initial value ⇒
7
T07
R/W
0
TCDT
Timer Control Status Register (Upper)
bit
Address: 00005FH
Read/write ⇒
Initial value ⇒
15
14
13
ECKE IRQZF IRQZE
R/W
R/W
R/W
0
0
0
TCCSH
Timer Control Status Register (Lower)
bit
Address: 00005EH
Read/write ⇒
Initial value ⇒
CM44-10147-2E
7
−
−
X
6
BFE
R/W
0
FUJITSU MICROELECTRONICS LIMITED
TCCSL
353
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ 16-bit Output Compare Registers
Figure 15.4-2 Registers of 16-bit output compare
Output Compare Buffer Register / Output Compare Register (Upper)
Address: ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
000071H
000073H
000075H
000077H
000079H
00007BH
Read/write
Initial value
bit 15
OP15
R/W
X
14
13
12
11
10
OP14 OP13
OP12
OP11 OP10
R/W
X
R/W
X
R/W
X
R/W
X
9
8
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
OP09 OP08
R/W
X
R/W
X
R/W
X
Output Compare Buffer Register / Output Compare Register (Lower)
Address: ch.0 000070H
ch.1 000072H
ch.2 000074H
ch.3 000076H
ch.4 000078H
ch.5 00007AH
Read/write
Initial value
7
bit
OP07
6
5
OP06 OP05
R/W
X
R/W
X
4
OP04
R/W
X
R/W
X
3
2
OP03 OP02
R/W
X
1
OP01
R/W
X
0
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
OP00
R/W
X
R/W
X
9
8
Compare Control Register (Upper)
bit
15
Address: ch.1 00007DH
ch.3 00007FH
ch.5 000081H
Read/write
Initial value
14
13
12
11
10
BTS1 BTS0 CMOD OTE1 OTE0
R/W
1
X
R/W
1
R/W
0
R/W
0
OCS1/3/5
OTD1 OTD0
R/W
0
R/W
0
R/W
0
Compare Control Register (Lower)
bit
Address: ch.0 00007CH
ch.2 00007EH
ch.4 000080H
Read/write
Initial value
354
7
6
5
4
3
2
1
IOP0
IOE1
IOE0
BUF1
BUF0 CST1
0
OCS0/2/4
IOP1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
FUJITSU MICROELECTRONICS LIMITED
R/W
0
CST0
R/W
0
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Input Capture Registers
Figure 15.4-3 Registers of 16-bit input capture
Input Capture Data Register (Upper)
Address: ch.0
ch.1
ch.2
ch.3
000061H
000063H
000065H
000067H
15
bit
14
13
12
11
10
9
8
IPCP0 to IPCP3
CP15
Read/write
Initial value
CP14
CP13
CP12
R
X
R
X
R
X
R
X
CP11 CP10
CP09
CP08
R
X
R
X
2
1
CP01
CP00
R
X
R
X
R
X
R
X
Input Capture Data Register (Lower)
Address: ch.0
ch.1
ch.2
ch.3
000060H
000062H
000064H
000066H
bit
7
6
5
4
3
CP07
CP06
CP05
CP04
CP03 CP02
R
X
R
X
R
X
0
IPCP0 to IPCP3
Read/write
Initial value
R
X
R
X
R
X
Input Capture Control Status Register (2/3) (Upper)
bit
Address: 00006BH
Read/write ⇒
Initial value ⇒
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
−
−
−
−
X
X
X
X
X
X
IEI3
R
0
IEI2
R/W
0
3
EG31
R/W
0
2
EG30
R/W
0
1
EG21
R/W
0
0
EG20
R/W
0
8
IEI0
R/W
0
0
EG00
R/W
0
ICSH23
Input Capture Control Status Register (2/3) (Lower)
bit
Address: 00006AH
Read/write ⇒
Initial value ⇒
7
ICP3
R/W
0
6
ICP2
R/W
0
5
ICE3
R/W
0
4
ICE2
R/W
0
ICSL23
PPG output control/ Input Capture Control Status Register (0/1) (Upper)
bit
Address: 000069H
Read/write ⇒
Initial value ⇒
15
14
13
12
11
10
R/W
0
R/W
0
R/W
0
9
IEI1
R/W
0
4
ICE0
R/W
0
3
EG11
R/W
0
2
EG10
R/W
0
1
EG01
R/W
0
PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0
R/W
0
R/W
0
R/W
0
PICSH01
Input Capture Control Register (0/1) (Lower)
bit
Address: 000068H
Read/write ⇒
Initial value ⇒
CM44-10147-2E
7
ICP1
R/W
0
6
ICP0
R/W
0
5
ICE1
R/W
0
FUJITSU MICROELECTRONICS LIMITED
PICSL01
355
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Waveform Generator Registers
Figure 15.4-4 Registers of waveform generator
16-bit Timer Register (Upper)
bit
Address: ch.0 000051H
ch.1 000053H
ch.2 000055H
15
14
13
12
11
10
9
8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
TMRR0/1/2
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
16-bit Timer Register (Lower)
bit
Address: ch.0 000050H
ch.1 000052H
ch.2 000054H
7
6
5
4
3
2
1
0
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
14
13
12
11
10
TMRR0/1/2
Read/write
Initial value
R/W
X
R/W
X
9
8
16-bit Timer Control Register
bit
Address: ch.1 000057H
15
DTCR1
DMOD GTEN1 GTEN0 TMIF
Read/write
Initial value
R/W
0
R/W
0
R/W
0
TMIE
R/W
0
TMD2 TMD1 TMD0
R/W
0
R/W
0
R/W
0
R/W
0
16-bit Timer Control Register
7
bit
Address: ch.0 000056H
ch.2 000058H
Read/write
Initial value
6
5
4
3
DMOD GTEN1 GTEN0 TMIF
R/W
0
R/W
0
R/W
0
R/W
0
2
TMIE
R/W
0
1
0
TMD2 TMD1 TMD0
R/W
0
R/W
0
DTCR0/2
R/W
0
Waveform Control Register
bit
Address: 000059H
Read/write ⇒
Initial value ⇒
356
15
DTIE
R/W
0
14
DTIF
R/W
0
13
NRSL
R/W
0
12
DCK2
R/W
0
11
DCK1
R/W
0
10
DCK0
R/W
0
9
EG21
R/W
0
FUJITSU MICROELECTRONICS LIMITED
8
EG21
R/W
0
SIGCR
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4.1
Compare Clear Buffer Register (CPCLRB) and Compare
Clear Register (CPCLR)
Compare clear buffer register (CPCLRB) is a 16-bit buffer register of compare clear
register (CPCLR). Both CPCLRB and CPCLR registers are located in the same address.
■ Compare Clear Buffer Register (CPCLRB)
Figure 15.4-5 Compare clear buffer register (CPCLRB)
Compare Clear Buffer Register (Upper)
bit
Address: 00005BH
Read/write ⇒
Initial value ⇒
15
CL15
W
1
14
CL14
W
1
13
CL13
W
1
12
CL12
W
1
11
CL11
W
1
10
CL10
W
1
9
CL09
W
1
8
CL08
W
1
5
CL05
W
1
4
CL04
W
1
3
CL03
W
1
2
CL02
W
1
1
CL01
W
1
0
CL00
W
1
CPCLRB
Compare Clear Buffer Register (Lower)
bit
Address: 00005AH
Read/write ⇒
Initial value ⇒
7
CL07
W
1
6
CL06
W
1
CPCLRB
Compare clear buffer register is the buffer register for compare clear register. When buffer function is
disabled (TCCSL:BFE=0) or when free-run timer is stopped, value in compare clear buffer register is
transferred to compare clear register immediately. When buffer function is enabled, value is transferred to
the register when the count value of 16-bit free-run timer is detected as zero.
Word access instruction to this register is recommended.
■ Compare Clear Register (CPCLR)
Figure 15.4-6 Compare clear register (CPCLR)
Compare Clear Register (Upper)
bit
Address: 00005BH
Read/write ⇒
Initial value ⇒
15
CL15
R
1
14
CL14
R
1
13
CL13
R
1
12
CL12
R
1
11
CL11
R
1
10
CL10
R
1
9
CL09
R
1
8
CL08
R
1
6
CL06
R
1
5
CL05
R
1
4
CL04
R
1
3
CL03
R
1
2
CL02
R
1
1
CL01
R
1
0
CL00
R
1
CPCLR
Compare Clear Register (Lower)
bit
Address: 00005AH
Read/write ⇒
Initial value ⇒
7
CL07
R
1
CPCLR
The Compare Clear Register is used to compare with the count value of the 16-bit free-run timer. In upcount mode, when this register is matched with the count value of 16-bit free-run timer, timer will be reset
to “0000H”. In up-down count mode, when this register is matched with the count value of the 16-bit freerun timer, the timer changes from up-count to down-count or changes from down-count to up-count at zero
detect.
Word access instruction to this register is recommended.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
357
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
15.4.2
MB90820B Series
Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of 16-bit free-run timer.
■ Timer Data Register (TCDT)
Figure 15.4-7 Timer data register
Timer Data Register (Upper)
bit
Address: 00005DH
Read/write ⇒
Initial value ⇒
15
T15
R/W
0
14
T14
R/W
0
13
T13
R/W
0
12
T12
R/W
0
11
T11
R/W
0
10
T10
R/W
0
9
T09
R/W
0
8
T08
R/W
0
6
T06
R/W
0
5
T05
R/W
0
4
T04
R/W
0
3
T03
R/W
0
2
T02
R/W
0
1
T01
R/W
0
0
T00
R/W
0
TCDT
Timer Data Register (Lower)
bit
Address: 00005CH
Read/write ⇒
Initial value ⇒
7
T07
R/W
0
TCDT
The timer data register is used to read the count value of the 16-bit free-run timer. The counter value is
cleared to “0000H” upon a reset. The timer value can be set by writing a value to this register. However,
ensure that the value is written while the operation is stopped (STOP = 1). Word access instruction to the
timer data register is recommended.
The 16-bit free-run timer is initialized upon the following factors:
• Reset
• Clear bit (SCLR) of timer control status register
• A match between compare clear register and the timer counter value in up-count mode
(TCCSL:MODE=0)
358
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4.3
Timer Control Status Register (TCCSH, TCCSL)
The timer control status register (TCCS) is a 16-bit register and is used to control the
operation of 16-bit free-run timer.
■ Timer Control Status Register, Upper Byte (TCCSH)
Figure 15.4-8 Timer control status register, upper byte(TCCSH)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
Initial value
00005FH ECKE IRQZFIRQZE MSI2 MSI1 MSI0 ICLR ICRE 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICRE
Compare clear interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Compare clear interrupt flag bit
ICLR
Read
Write
0
No compare-clear match
Clear this bit
1
Compare-clear match
No effect
MSI2 MSI1 MSI0
Interrupt masking selection bits
0
0
0
Interrupt is generated when 1st match
0
0
1
Interrupt is generated when 2nd match
0
1
0
Interrupt is generated when 3rd match
0
1
1
Interrupt is generated when 4th match
1
0
0
Interrupt is generated when 5th match
1
0
1
Interrupt is generated when 6th match
1
1
0
Interrupt is generated when 7th match
1
1
1
Interrupt is generated when 8th match
IRQZE
Zero detect interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Zero detect interrupt flag bit
IRQZF
R/W : Read and Write
: Initial value
CM44-10147-2E
Read
Write
0
No zero detect
Clear this bit
1
Zero detect
No effect
ECKE
Clock selection bit
0
Internal clock
1
External clock
FUJITSU MICROELECTRONICS LIMITED
359
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-1 Timer control status register, upper byte (TCCSH)
Bit name
Function
•
This bit is used to select internal or external clock as count clock for 16-bit
free-run timer.
• Writing "0" selects internal clock. The clock frequency selection bits (CLK2
to CLK0) should also be set to select the count clock frequency.
• Writing "1" selects external clock. External clock is input from pin "P75/
FRCK/AN13", so DDR1:7 should be set as "0" to enable external clock
input.
Note:
The count clock is changed immediately after this bit is set. So change this
bit while the output compare and input capture units are stopped.
bit15
ECKE:
Clock selection bit
bit 14
• This bit is an interrupt flag for zero detect.
• When the count value of 16-bit free-run timer is 0000H, this bit is set to "1".
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
Notes:
IRQZF:
- In software clear, (writing TCCSL:SCLR "1") will not set this bit.
Zero detect interrupt flag bit
- In up-down count mode (MODE=1) and the interrupt is generated by
setting interrupt mask selection bit is selected (MSI2 to MSI0 not equals
000B), this bit will only be set to "1". When the interrupt is not
generated, this bit does not’ set "1".
- In up-count mode (MODE=0), this bit is set at every zero detect
disregarding the value of MSI2 to MSI0.
bit 13
IRQZE:
•
Zero detect interrupt request •
enable bit
This is the interrupt request enable bit for the zero detect.
When this bit is "1" and the interrupt flag bit (bit 14: IRQZF) is set to "1", an
interrupt request will be generated to CPU.
•
bit12
to
bit10
These bits are used to set the number of times for masking the compare clear
interrupt in up-count mode (MODE=0) or zero detect interrupt in up-down
count mode (MODE=1).
MSI2 to MSI0:
• No interrupt cause is masked when MSI2 to MSI0 equals zero.
Interrupt mask selection bits Note:
To mask the interrupt cause twice and perform interrupt processing at the
third times, MSI2 to MSI0 should be set as 010B.
•
•
360
bit9
This bit is an interrupt flag for compare clear.
When the compare clear value and 16-bit free-run timer value are matched,
this bit is set to "1".
• Writing "0" will clear this bit.
• Writing "1" has no effect.
ICLR:
• In read-modify-write operation, "1" is always read.
Compare clear interrupt flag Notes:
- In up-count mode (MODE=0) and the interrupt is generated by setting
bit
interrupt mask selection bit is selected (MSI2 to MSI0 not equals 000B),
this bit will only be set to "1". When the interrupt is not generated, this
bit does not’ set "1".
- In up-down count mode (MODE=1), this bit is set at every compare
clear disregarding the value of MSI2 to MSI0.
bit8
ICRE:
Compare clear interrupt
request enable bit
• This is the interrupt request enable bit for the compare clear.
• When this bit is "1" and the compare clear interrupt flag bit (bit 9: ICLR) is set
to "1", an interrupt request will be generated to CPU.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Timer Control Status Register, Lower Byte (TCCSL)
Figure 15.4-9 Timer control status register, lower byte (TCCSL)
Address
bit7
00005EH
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
BFE STOP MODE SCLR CLK2 CLK1 CLK0 X0100000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock frequency selection bit
CLK2 CLK1 CLK0
φ=
24MHz
Count
clock
φ=
8MHz
φ=
16MHz
φ=
4MHz
φ=
1MHz
0
0
0
φ
41.7 ns 62.5 ns 125 ns 0.25 µs
1 µs
0
0
1
φ/2
83.3 ns 125 ns 0.25 µs 0.5 µs
2 µs
0
1
0
φ/4
0.17 µs 0.25 µs 0.5 µs
1 µs
4 µs
0
1
1
φ/8
0.33 µs 0.5 µs
1 µs
2 µs
8 µs
1
0
0
φ/16
0.67 µs
1 µs
2 µs
4 µs
16 µs
1
0
1
φ/32
1.33 µs
2 µs
4 µs
8 µs
32 µs
1
1
0
φ/64
2.67 µs
4 µs
8 µs
16 µs
64 µs
1
1
1
φ/128
5.33 µs
8 µs
16 µs
32 µs 128 µs
φ: Machine cycle
Timer clear bit
SCLR
Write
0
Clear SCLR bit
1
Initialize counter to “0000H”
MODE
R/W : Read and write
: Initial value
—
: Not used
CM44-10147-2E
Read
Always read as ”0”
Timer counting mode bit
0
Up-count mode
1
Up-down count mode
STOP
Timer enable bit
0
Counting is enabled (operation)
1
Counting is disabled (stop)
BFE
Compare clear buffer enable bit
0
Disable compare clear buffer
1
Enable compare clear buffer
FUJITSU MICROELECTRONICS LIMITED
361
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-2 Timer control status register, lower byte (TCCSL) (1 / 2)
Bit name
bit7
bit6
bit5
Unused bit
Function
•
•
The read value is undefined.
Writing to this bit has no effect on the operation.
•
•
This bit is used to enable compare clear buffer.
Writing "0" disables compare clear buffer. Directly write in compare
clear register is possible.
Writing "1" enables compare clear buffer. Data written in compare
clear buffer register will be held and transfer to compare clear
register when the count value of 16-bit free-run timer is detected as
zero.
BFE:
Compare clear buffer •
enable bit
STOP:
Timer enable bit
• This bit is used to stop/start the counting of the 16-bit free-run timer.
• Writing "0" starts the counting of the 16-bit free-run timer.
• Writing "1" stops the counting of the 16-bit free-run timer.
Note:
When the 16-bit free-run timer is stopped, the output compare
operation will also be stopped.
•
•
bit4
362
MODE:
Timer counting
mode bit
This bit is used to select the count mode of the 16-bit free-run timer.
Writing "0" selects up-count mode. Timer counts up until counter
value matches with compare clear register and resets to "0000H" and
then counts up again.
• Writing "1" selects up-down count mode.
In up-down count mode, whenever zero in the counter data register is
detected, the timer count mode will always be reseted to upcounting.
The timer will reverse its count mode whenever the counter value
matches with compare clear register.
• This bit can be written at any time whether the timer is operating or
stopped. The value written to this bit is buffered during the timer is
operating and the count mode will be changed when timer value is
"0000H".
Note:
Becasue the timer will reverse its count mode when compare-match
is detected in up-down count mode (MODE = 1), it should be careful
to set the compare clear register and timer data register when the
timer is being counted down.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-2 Timer control status register, lower byte (TCCSL) (2 / 2)
Bit name
Function
This bit is used to initialize the 16-bit free-run timer to "0000H".
Writing "0" will clear the SCLR bit if it is "1".
Writing "1" initializes 16-bit free-run timer to "0000H" at the next
count clock.
• Read value is always "0".
Notes:
- This bit cannot be used to initialize the timer when timer stops
(STOP=1). Writing "0000H" to timer data register (TCDT) can
initialize the timer.
- Writng "1" will not generate zero detect interrupt.
- This bit will be cleared by hardware after the timer is initialized
to "0000". If "0" is written to the bit before timer initialization,
the bit is cleared and the timer did not initialized.
•
•
•
bit3
SCLR:
Timer clear bit
bit2
to
bit0
CLK2 to CLK0:
Clock frequency
selection bits
•
CM44-10147-2E
•
This bit is used to select count clock frequency for the 16-bit freerun timer.
The count clock is changed immediately after these bits are set. So
change them while the output compare and input capture units are
stopped.
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
15.4.4
MB90820B Series
Output Compare Buffer Registers (OCCPB0 to OCCPB5)/
Output Compare Registers (OCCP0 to OCCP5)
Output compare buffer register (OCCPB) is a 16-bit buffer register of output compare
register (OCCP). Both OCCPB and OCCP registers are located in the same address.
■ Output Compare Buffer Registers (OCCPB0 to OCCPB5)
Figure 15.4-10 Output compare buffer registers (OCCPB0 to OCCPB5)
Output Compare Buffer Register (Upper)
Address: ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
000071H
000073H
000075H
000077H
000079H
00007BH
Read/write
Initial value
bit
15
OP15
14
13
OP14 OP13
W
X
W
X
12
OP12
W
X
11
10
OP11 OP10
W
X
9
8
OP09
OP08
W
X
W
X
W
X
W
X
5
4
3
2
1
OP04
OP03 OP02
OCCPB0 to
OCCPB5
Output Compare Buffer Register (Lower)
Address: ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
000070H
000072H
000074H
000076H
000078H
00007AH
Read/write
Initial value
bit
OP07
W
X
7
6
OP06 OP05
W
X
W
X
W
X
W
X
0
OP01 OP00
W
X
W
X
OCCPB0 to
OCCPB5
W
X
Output compare buffer register is the buffer register of output compare register (OCCP). When buffer
function is disabled (OCS0/2/4:BUF0/1=1) or when free-run timer is stopped, value in output compare
buffer register is transferred to output compare register immediately. When buffer function is enabled
(OCS0/2/4:BUF0/1=0), value is transferred at compare clear match or zero detection depending on transfer
selection bit (BTs) in compare control register (OCS1/3/5).
Word access to instruction this register is recommended.
364
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Output Compare Registers (OCCP0 to OCCP5)
Figure 15.4-11 Output compare registers (OCCP0 to OCCP5)
Output Compare Register (Upper)
Address: ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
000071H
000073H
000075H
000077H
000079H
00007BH
Read/write
Initial value
bit
15
OP15
14
13
OP14 OP13
R
X
R
X
12
OP12
R
X
11
10
OP11 OP10
R
X
R
X
9
8
OP09
OP08
R
X
R
X
2
1
R
X
OCCP0 to
OCCP5
Output Compare Register (Lower)
Address: ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
000070H
000072H
000074H
000076H
000078H
00007AH
Read/write
Initial value
bit
OP07
R
X
7
6
OP06 OP05
R
X
R
X
5
4
OP04
OP03 OP02
R
X
3
R
X
0
OP01 OP00
R
X
R
X
OCCP0 to
OCCP5
R
X
The output compare register is a 16-bit register which is used to compare the count value of 16-bit free-run
timer. The initial value of the output compare register is undetermined, so output compare buffer register
(OCCPB) must be set with a value before enabling the timer operation.
When the value of the output compare register matches the count value of 16-bit free-run timer, a compare
signal is generated to set the output compare interrupt flag bit (OCS0/OCS2/OCS4:IOP0/IOP1). If output
level is set (OCS1/OCS3/OCS5:OTD0/OTD1), the output level waveform generator RT0 to RT5
corresponding to the output compare register (OCCP0 to OCCP5) can be reversed.
Word access instruction to this register is recommended.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
15.4.5
MB90820B Series
Compare Control Registers (OCS0 to OCS5)
Compare control register is used to control the output level, output enable, output level
reverse mode, compare operation enable, compare match interrupt enable, and
compare match interrupt flag for RTO0 to RTO5.
■ Compare Control Register, Upper Byte (OCS1/3/5)
Figure 15.4-12 Compare control register, upper byte (OCS1/3/5)
Address
bit15 bit14 bit13 bit12 bit11 bit10
ch.1: 00007DH
ch.3: 00007FH
ch.5: 000081H
—
—
bit9
bit8
Initial value
BTS1 BTS0 CMOD OTE1 OTE0 OTD1 OTD0 X1100000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output level bit
OTD0
Write
Read
0
Output “0” for RT0/RT2/RT4
1
Output “1” for RT0/RT2/RT4
Current output value of RT0/
RT2/RT4
Output level bit
OTD1
Write
Read
0
Output “0” for RT1/RT3/RT5
1
Output “1” for RT1/RT3/RT5
Current output value of RT1/
RT3/RT5
OTE0
Output enable bit
0
General-purpose I/O port (P82/P84/P86)
1
Output compare output pin (RTO0/RTO2/RTO4)
OTE1
Output enable bit
0
General-purpose I/O port (P83/P85/P87)
1
Output compare output pin (RTO1/RTO3/RTO5)
CMOD
Output level reverse mode bit
0
RT0/2/4: The level is reversed upon a match with compare register 0/2/4
RT1/3/5: The level is reversed upon a match with compare register 1/3/5 respectively
1
RT0/2/4: The level is reversed upon a match with compare register 0/2/4
RT1/3/5: The level is reversed upon a match with compare register (0or1)/(2or3)/(4or5)
BTS0
R/W : Read and write
—
: Undefind
: Initial value
366
Buffer transfer select bit
0
Transfer at zero detect ( channel 0/2/4)
1
Transfer at compare clear match (channel 0/2/4)
BTS1
Buffer transfer select bit
0
Transfer at zero detect (channel 1/3/5)
1
Transfer at compare clear match (channel 1/3/5)
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-3 Compare control register, upper byte (OCS1/3/5) (1 / 2)
Bit name
bit15
bit14
Function
Undefind bit
BTS1: Buffer
transfer select
bit
•
•
The read value is undefined.
Writing to this bit has no effect on the operation.
•
This bit is used to select when data transfer from output compare buffer
register (OCCPB1/3/5) to output compare register (OCCP1/3/5).
When BTS1=0, data transfer is occurred when count value of 16-bit free-run
timer is detected as zero.
When BTS1=1, data transfer is occurred when compare clear match is
occurred in 16-bit free-run timer.
•
•
•
bit13
BTS0: Buffer
transfer select
bit
•
•
•
•
bit12
CMOD:
Output level
reverse mode
bit
•
This bit is used to select when data transfer from output compare buffer
register (OCCPB0/2/4) to output compare register (OCCP0/2/4).
When BTS0=0, data transfer is occurred when count value of 16-bit free-run
timer is detected as zero.
When BTS0=1, data transfer is occurred when compare clear match is
occurred in 16-bit free-run timer.
CMOD is used to switch the pin output level reverse mode upon a match
while pin output is enabled (OTE1 = 1 or OTE0 = 1).
When CMOD = 0, the output level of the pin is reversed upon a match with
corresponding compare register.
RT0/2/4: The level is reversed upon a match between the 16-bit free-run
timer and compare register 0/2/4.
RT1/3/5: The level is reversed upon a match between the 16-bit free-run
timer and compare register 1/3/5.
When CMOD = 1, the output level of the pin RT0/2/4 corresponding to
compare register is reversed as same as when CMOD = 0. However, the
output level of the pin (RT1/3/5) corresponding to compare register 1/3/5 is
reversed when a match is detected in compare register 0/2/4 or 1/3/5. If
compare registers 0/2/4 and 1/3/5 have the same value, the same operation as
when only one compare register is used.
RT0/2/4: The level is reversed upon a match between the 16-bit free-run
timer and compare register 0/2/4.
RT1/3/5: The level is reversed upon a match between the 16-bit free-run
timer and compare register (0 or 1)/(2 or 3)/(4 or 5).
•
bit11
This bit is used to enable waveform generator output (RTO1/3/5 to P83/P85/
P87) to the port.
OTE1:
• The initial value for this bit is "0".
Output enable
Note:
bit
If waveform generator is disabled (DTCR:TMD2 to TMD0=000B), RTO1/3/
5 outputs the same value in output compare RT1/3/5.
•
bit10
CM44-10147-2E
This bit is used to enable waveform generator output (RTO0/2/4 to P82/P84/
P86) to the port.
OTE0:
• The initial value for this bit is "0".
Output enable
Note:
bit
If waveform generator is disabled (DTCR:TMD2 to TMD0=000B), RTO0/2/
4 outputs the same value in output compare RT0/2/4.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-3 Compare control register, upper byte (OCS1/3/5) (2 / 2)
Bit name
Function
•
bit9
OTD1:
Output level
bit
bit8
OTD0:
Output level
bit
•
•
•
368
•
•
This bit is used to change the pin output level for output compare 1/3/5
(RT1/3/5).
The initial value of the compare pin output is "0".
Ensure that the compare operation is stopped before a value is written. When
reading this bit, this bit indicates the output compare value in RT1/3/5.
This bit is used to change the pin output level for output compare 0/2/4
(RT0/2/4).
The initial value of the compare pin output is "0".
Ensure that the compare operation is stopped before a value is written. When
reading this bit, this bit indicates the output compare value in RT0/2/4.
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Compare Control Register, Lower Byte (OCS0/2/4)
Figure 15.4-13 Compare control register, lower byte (OCS0/2/4)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0: 00007CH IOP1 IOP0 IOE1 IOE0 BUF1 BUF0 CST1 CST0 00001100B
ch.2: 00007EH R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.4: 000080H
CST0
Compare operation enable bit
0
Disable compare operation for compare register 0/2/4
1
Enable compare operation for compare register 0/2/4
CST1
Compare operation enable bit
0
Disable compare operation for compare register 1/3/5
1
Enable compare operation for compare register 1/3/5
BUF0
Compare buffer disable bit
0
Enable compare buffer for compare register 0/2/4
1
Disable compare buffer for compare register 0/2/4
BUF1
Compare buffer disable bit
0
Enable compare buffer for compare register 1/3/5
1
Disable compare buffer for compare register 1/3/5
IOE0
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 0/2/4
1
Enable compare match interrupt for compare register 0/2/4
IOE1
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 1/3/5
1
Enable compare match interrupt for compare register 1/3/5
Compare match interrupt flag bit
IOP0
Read
Write
0
No compare match interrupt for
compare register 0/2/4
Clear this bit
1
Compare match interrupt for
compare register 0/2/4
No effect
Compare match interrupt flag bit
IOP1
Read
Write
0
No compare match interrupt for
compare register 1/3/5
Clear this bit
1
Compare match interrupt for
compare register 1/3/5
No effect
R/W : Read and Write
: Initial value
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-4 Compare control register, lower byte (OCS0/2/4)
Bit name
Function
•
•
bit7
IOP1:
Compare match
interrupt flag bit
•
•
•
•
•
•
bit6
IOP0:
Compare match
interrupt flag bit
•
•
•
•
This bit is an interrupt flag when compare register 1/3/5 is matched with the
value of 16-bit free-run timer.
"1" is set to this bit when the compare register value matches the 16-bit freerun timer value.
While the compare match interrupt enable bits (IOE1) is enabled, an output
compare interrupt occurs when the IOP1 bit is set.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
This bit is an interrupt flag when compare register 0/2/4 is matched with the
value of 16-bit free-run timer.
"1" is set to this bit when the compare register value matches the 16-bit freerun timer value.
While the compare match interrupt enable bits (IOE0) is enabled, an output
compare interrupt occurs when the IOP0 bit is set.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
•
bit5
IOE1:
Compare match
interrupt enable bit
•
bit4
IOE0:
Compare match
interrupt enable bit
bit3
BUF1:
Compare buffer
disable bit
•
•
This bit is used to disable buffer function for output compare register 1/3/5.
Writing "0" will enable the buffer function.
bit2
BUF0:
Compare buffer
disable bit
•
•
This bit is used to disable buffer function for output compare register 0/2/4.
Writing "0" will enable the buffer function.
•
•
This bit is used to enable output compare interrupt for compare register 1/3/
5.
While the "1" is written to this bit, an output compare interrupt occurs when
an compare match interrupt flag bit (IOP1) is set.
This bit is used to enable output compare interrupt for compare register 0/2/
4.
While the "1" is written to this bit, an output compare interrupt occurs when
an compare match interrupt flag bit (IOP0) is set.
•
bit1
CST1:
Compare operation
enable bit
This bit is used to enable the compare operation between 16-bit free-run
timer and compare register 1/3/5.
• Ensure that a value is written into the compare register and timer data
register before the compare operation is enabled.
Note:
Since output compare is synchronized with the 16-bit free-run timer clock,
stopping the 16-bit free-run timer stops compare operation.
•
bit0
370
CST0:
Compare operation
enable bit
This bit is used to enable the compare operation between 16-bit free-run
timer and compare register 0/2/4.
• Ensure that a value is written into the compare register and timer data
register before the compare operation is enabled.
Note:
Since output compare is synchronized with the 16-bit free-run timer clock,
stopping the 16-bit free-run timer stops zero detect and compare operation.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4.6
Input Capture Register (IPCP0 to IPCP3)
Input capture registers are used to hold the count value of 16-bit timer when a valid
edge of the input waveform is detected.
■ Input Capture Register (IPCP0 to IPCP3)
Figure 15.4-14 Input capture data registers (IPCP0 to IPCP3)
Input Capture Data Register (Upper)
Address: ch.0
ch.1
ch.2
ch.3
000061H
000063H
000065H
000067H
Read/write
Initial value
bit 15
CP15
14
CP14
12
CP13
CP12
R
X
R
X
R
X
R
X
13
11
10
CP11 CP10
8
IPCP0 to
IPCP3
CP09
CP08
R
X
R
X
2
1
CP01
CP00
R
X
R
X
R
X
R
X
9
Input Capture Data Register (Lower)
Address: ch.0
ch.1
ch.2
ch.3
000060H
000062H
000064H
000066H
Read/write
Initial value
bit
7
6
5
4
CP07
CP06
CP05
CP04
CP03 CP02
R
X
R
X
R
X
R
X
3
R
X
R
X
0
IPCP0 to
IPCP3
This register is used to store the value of the 16-bit timer when a valid edge of the corresponding external
pin input waveform is detected. (Word access instruction to this register is recommended. No data can be
written to this register.)
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Input Capture Control Status Registers (ICS23, PICS01)
15.4.7
Input capture control status registers (ICS23, PICS01) are used to control edge
selection, interrupt request enable, and interrupt request flag and to indicate valid edge
detected for input capture 0 to 3.
■ Input Capture Control Status Register, Upper Byte (ICSH23)
Figure 15.4-15 Input capture control status register, upper byte (ICSH23)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
Initial value
00006BH
IEI3
IEI2
XXXXXX00B
R
R
R
: Read-only
-
: Undefind
: Initial value
372
IEI2
Valid edge indication bit (input capture 2)
0
Falling edge detected
1
Rising edge detected
IEI3
Valid edge indication bit (input capture 3)
0
Falling edge detected
1
Rising edge detected
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-5 Input capture control status register, upper byte (ICSH23)
Bit name
bit15
to
bit10
Undefind bits
Function
•
•
The read value is undefined.
Writing to these bits have no effect on the operation.
•
bit9
IEI3:
Valid edge
indication bit
(input capture 3)
This bit is an valid edge indication bit for capture register 3, to
indicate a rising or falling edge is detected.
• "0" is written to this bit when falling edge is detected.
• "1" is written to this bit when rising edge is detected.
• This bit is read-only.
Note:
The read value is meaningless when EG31, EG30 = 00B.
•
bit8
CM44-10147-2E
IEI2:
Valid edge
indication bit
(input capture 2)
This bit is an valid edge indication bit for capture register 2, to
indicate a rising or falling edge is detected.
• "0" is written to this bit when falling edge is detected.
• "1" is written to this bit when rising edge is detected.
• This bit is read-only.
Note:
The read value is meaningless when EG21, EG20 = 00B.
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Input Capture Control Status Register, Lower Byte (ICSL23)
Figure 15.4-16 Input capture control status register, lower byte (ICSL23)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00006AH ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG21
EG20
Edge selection bit (input capture 2)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG31
EG30
Edge selection bit (input capture 3)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE2
Interrupt request enable bit (input capture 2)
0
Disable interrupt request
1
Enable interrupt request
ICE3
Interrupt request enable bit (input capture 3)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 2)
ICP2
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
Interrupt request flag bit (input capture 3)
ICP3
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
374
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-6 Input capture control status register, lower byte (ICSL23)
Bit name
Function
•
•
bit7
ICP3:
Interrupt request
flag bit
(Input capture 3)
•
•
•
•
•
•
bit6
CM44-10147-2E
ICP2:
Interrupt request
flag bit
(Input capture 2)
•
•
•
•
•
bit5
ICE3:
Interrupt request
enable bit
(Input capture 3)
•
bit4
ICE2:
Interrupt request
enable bit
(Input capture 2)
bit3,
bit2
EG31, EG30:
Edge selection
bits
(Input capture 3)
bit1,
bit0
EG21, EG20:
Edge selection
bits
(Input capture 2)
•
•
•
•
•
•
This bit is used as interrupt request flag for input capture 3.
"1" is set to this bit upon detection of a valid edge in an external
input pin.
While the interrupt enable bit (ICE3) is set, an interrupt can be
generated upon detection of a valid edge.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
This bit is used as interrupt request flag for input capture 2.
"1" is set to this bit upon detection of a valid edge in an external
input pin.
While the interrupt enable bit (ICE2) is set, an interrupt can be
generated upon detection of a valid edge.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
This bit is used to enable input capture interrupt request for input
capture 3.
While "1" is written to this bit, an input capture interrupt is
generated when the interrupt flag (ICP3) is set.
This bit is used to enable input capture interrupt request for input
capture 2.
While "1" is written to this bit, an input capture interrupt is
generated when the interrupt flag (ICP2) is set.
These bits are used to specify the valid edge polarity of an external
input for input capture 3.
These bits are also used to enable input capture operation.
These bits are used to specify the valid edge polarity of an external
input for input capture 2.
These bits are also used to enable input capture operation.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ PPG Output Control / Input Capture Control Status Register, Upper Byte (PICSH01)
Figure 15.4-17 PPG output control/input capture control status register, upper byte (PICSH01)
Address
bit15
bit9
bit8
Initial value
000069H PGEN5 PGEN4PGEN3 PGEN2 PGEN1 PGEN0 IEI1
IEI0
00000000B
R/W
R
bit14
R/W
: Read-only
R/W : Read and Write
bit13
R/W
bit12
R/W
bit11
R/W
bit10
R/W
R
R
IEI0
Valid edge indication bit (input capture 0)
0
Falling edge detected
1
Rising edge detected
IEI1
Valid edge indication bit (input capture 1)
0
Falling edge detected
1
Rising edge detected
PGEN0
PPG output enable bit
0
Disable PPG0 output to RTO0
1
Enable PPG0 output to RTO0
PGEN1
PPG output enable bit
0
Disable PPG0 output to RTO1
1
Enable PPG0 output to RTO1
PGEN2
PPG output enable bit
0
Disable PPG0 output to RTO2
1
Enable PPG0 output to RTO2
PGEN3
PPG output enable bit
0
Disable PPG0 output to RTO3
1
Enable PPG0 output to RTO3
PGEN4
PPG output enable bit
0
Disable PPG0 output to RTO4
1
Enable PPG0 output to RTO4
PGEN5
PPG output enable bit
0
Disable PPG0 output to RTO5
1
Enable PPG0 output to RTO5
: Initial value
376
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-7 PPG output control/input capture control status register, upper byte
(PICSH01)
Bit name
bit15
to
bit10
PGEN5 to PGEN0:
PPG output
enable bits
Function
•
These bits are used to select PPG0 output to RTO0/1/2/3/4/5.
•
bit9
IEI1:
Valid edge
indication bit
(input capture 1)
This bit is an valid edge indication bit for capture register 1, to
indicate a rising or falling edge is detected.
• "0" is written to this bit when falling edge is detected.
• "1" is written to this bit when rising edge is detected.
• This bit is read-only.
Note:
The read value is meaningless when EG11, EG10 = 00B.
•
bit8
CM44-10147-2E
IEI0:
Valid edge
indication bit
(input capture 0)
This bit is an value edge indication bit for capture register 0, to
indicate a rising or falling edge is detected.
• "0" is written to this bit when falling edge is detected.
• "1” is written to this bit when rising edge is detected.
• This bit is read-only.
Note:
The read value is meaningless when EG01, EG00 = 00B.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ Input Capture Control Status Register, Lower Byte (PICSL01)
Figure 15.4-18 Input capture control status register, lower byte (PICSL01)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000068H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG01
EG00
Edge selection bit (input capture 0)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG11
EG10
Edge selection bit (input capture 1)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE0
Interrupt request enable bit (input capture 0)
0
Disable interrupt request
1
Enable interrupt request
ICE1
Interrupt request enable bit (input capture 1)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 0)
ICP0
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
Interrupt request flag bit (input capture 1)
ICP1
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
378
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-8 Input capture control status register, lower byte (PICSL01)
Bit name
Function
•
•
bit7
ICP1:
Interrupt request
flag bit
(Input capture 1)
•
•
•
•
•
•
bit6
CM44-10147-2E
ICP0:
Interrupt request
flag bit
(Input capture 0)
•
•
•
•
•
bit5
ICE1:
Interrupt request
enable bit
(Input capture 1)
•
bit4
ICE0:
Interrupt request
enable bit
(Input capture 0)
bit3,
bit2
EG11, EG10:
Edge selection
bits
(Input capture 1)
bit1,
bit0
EG01, EG00:
Edge selection
bits
(Input capture 0)
•
•
•
•
•
•
This bit is used as interrupt request flag for input capture 1.
"1" is set to this bit upon detection of a valid edge for an external
input pin.
While the interrupt enable bit (ICE1) is set, an interrupt can be
generated upon detection of a valid edge.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
This bit is used as interrupt request flag for input capture 0.
"1" is set to this bit upon detection of a valid edge for an external
input pin.
While the interrupt enable bit (ICE0) is set, an interrupt can be
generated upon detection of a valid edge.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, "1" is always read.
This bit is used to enable input capture interrupt request for input
capture 1.
While "1" is written to this bit, an input capture1 interrupt is
generated when the interrupt flag (ICP1) is set.
This bit is used to enable input capture interrupt request for input
capture 0.
While "1" is written to this bit, an input capture0 interrupt is
generated when the interrupt flag (ICP0) is set.
These bits are used to specify the valid edge polarity of an external
input for input capture 1.
These bits are also used to enable input capture1 operation.
These bits are used to specify the valid edge polarity of an external
input for input capture 0.
These bits are also used to enable input capture0 operation.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
15.4.8
MB90820B Series
16-bit Timer Register (TMRR0 to TMRR2)
16-bit timer registers hold the compare value of 16-bit timers.
■ 16-bit Timer Registers (TMRR0 to TMRR2)
Figure 15.4-19 16-bit timer registers (TMRR0 to TMRR2)
16-bit Timer Register (Upper)
bit
Address: ch.0 000051H
ch.1 000053H
ch.2 000055H
Read/write
Initial value
15
14
13
12
11
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
TR07
TR06
TR05
TR03
TR02
TR01
TR00
R/W
X
R/W
X
TR15
R/W
X
R/W
X
10
9
8
TMRR0 to
TMRR2
16-bit Timer Register (Lower)
bit
Address: ch.0 000050H
ch.1 000052H
ch.2 000054H
Read/write
Initial value
R/W
X
TR04
R/W
X
R/W
X
R/W
X
R/W
X
0
TMRR0 to
TMRR2
R/W
X
These registers are used to store the comparison value of 16-bit timers. The value in these registers will be
reloaded when the 16-bit timer is started to operate. Therefore, if the value is re-written into these registers
during timer operation, this value will be valid at the next timer initiation/operation.
In dead-time timer mode, these registers are used to set the non-overlap time.
• Non-overlap time = (set value + 1) x selected clock.
Notes:
• The value of "0000H" cannot be set.
• The maximum offset of non-overlap time is counter value of set value-1.
In timer mode, these registers are used to set the GATE time for PPG timer 0 operation.
• GATE time = (set value + 1) x selected clock.
Notes:
• The value of "0000H" cannot be set and maximum offset is counter value of set value-1.
• The maximum offset of GATE time is counter value of set value-1.
380
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4.9
16-bit Timer Control Register (DTCR0 to DTCR2)
16-bit timer control registers (DTCR0 to DTCR2) are used to control the operation mode,
interrupt request enable, interrupt request flag, GATE signal enable, and output level
polarity for the waveform generator.
■ 16-bit Timer Control Register (DTCR0/DTCR2)
Address
Figure 15.4-20 16-bit timer control register (DTCR0/DTCR2)
bit 7
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
ch.0: 000056H DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
ch.2: 000058H R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 outputs pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 outputs pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable / software trigger bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
: Initial value
CM44-10147-2E
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT0/4 (asynchronous mode)
1
GATE signal is controlled by RT0/4 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT1/5 (asynchronous mode)
1
GATE signal is controlled by RT1/5 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-9 16-bit timer control registers (DTCR0/DTCR2)
Bit name
Function
bit7
DMOD:
Output polarity
control bit
• This bit is used to set the output polarity of U/V/W in dead-time timer mode.
• By setting this bit, the output polarity of U/V/W is inverted.
Note:
This bit is meaningless when dead-time timer mode is not selected (bit 2:
TMD2 = 0).
bit6
GTEN1:
GATE signal
control bit 1
•
This bit is used to control the GATE signal output for PPG timer 0 by RT1/5.
bit5
GTEN0:
GATE signal
control bit 0
•
This bit is used to control the GATE signal output of PPG timer 0 by RT0/4.
TMIF:
Interrupt request
flag bit
• This bit is used as an interrupt request flag for 16-bit timers.
• This bit will be set to "1" when 16-bit timer 0/2 is underflow.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
Notes:
- This bit functions only in mode TMD2 to TMD0=000B or 001B. In other
modes, this bit is always "0".
- If both software clear (writing "0") and hardware set (16-bit timer 0/2
underflow) occurs simultaneously, software clear takes the higher
priority to clear this bit.
bit4
•
bit3
TMIE:
Interrupt request
enable / software
trigger bit
This bit is used as the software trigger bit and interrupt enable bit for the 16bit timer 0/2.
• When TMD2 to TMD0=000B or 001B, this bit is used as software trigger for
16-bit timer. Setting this bit from "0" to "1" triggers the 16-bit timer to
reload and starts down-counting.
• When this bit is "1" and the interrupt request flag bit (bit 4: TMIF) is "1", an
interrupt request is sent to CPU.
Note:
To retrigger the 16-bit timer, be sure to write "0" before write "1" to this bit.
•
•
bit2
to
bit0
382
TMD2 to TMD0:
Operation mode
bits
These bits are used to select the operation mode of the waveform generator.
When TMD2 to TMD0=000B, output compare RT0/4 and RT1/5 output to
RTO0/4 and RTO1/5 respectively. And 16-bit timer can be used as reload
timer.
• When TMD2 to TMD0=001B, output compare RT0/4 and RT1/5 output to
RTO0/4 and RTO1/5 respectively if PPG0 output is disabled
(PICSH01:PGEN0/4=0, PGEN1/5=0). And 16-bit timer can be used as
reload timer.
Notes:
- To operate the waveform generator in dead-time timer mode, be sure to
select 2-channel mode for RT1/5 (OCS1/5:CMOD=1)
- When TMD2 to TMD0=111B is selected, RTO0/4 and RTO1/5 output
are independent of setting in PICSH01:PGEN0/4, PGEN1/5.
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CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
■ 16-bit Timer Control Register (DTCR1)
Figure 15.4-21 16-bit timer control register (DTCR1)
Address
ch.1: 000057H
bit 15 bit 14
bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 Initial value
DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 outputs pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 outputs pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable / software trigger bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT2 (asynchronous mode)
1
GATE signal is controlled by RT2 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT3 (asynchronous mode)
1
GATE signal is controlled by RT3 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
: Initial value
CM44-10147-2E
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
Table 15.4-10 16-bit timer control registers (DTCR1)
Bit name
Function
bit15
DMOD:
Output polarity
control bit
• This bit is used to set the output polarity of U/V/W in dead-time timer mode.
• By setting this bit, the output polarity of U/V/W is inverted.
Note:
This bit is meaningless when dead-time timer mode is not selected (bit10:
TMD2 = 0).
bit14
GTEN1:
GATE signal
control bit 1
•
This bit is used to control the GATE signal output for PPG timer 0 by RT3.
bit13
GTEN0:
GATE signal
control bit 0
•
This bit is used to control the GATE signal output of PPG timer 0 by RT2.
TMIF:
Interrupt request
flag bit
• This bit is used as an interrupt request flag for 16-bit timers.
• This bit will be set to "1" when 16-bit timer 1 is underflow.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
Notes:
- This bit functions only in mode TMD2 to TMD0=000B or 001B. In other
modes, this bit is always "0".
- If both software clear (writing "0") and hardware set (16-bit timer 1
underflow) occurs simultaneously, software clear takes the higher
priority to clear this bit.
bit12
•
bit11
TMIE:
Interrupt request
enable / software
trigger bit
This bit is used as the software trigger bit and interrupt enable bit for the 16bit timer.
• When TMD2 to TMD0=000B or 001B, this bit is used as software trigger for
16-bit timer. Setting this bit from "0" to "1" triggers the 16-bit timer to
reload and starts down-counting.
• When this bit is "1" and the interrupt request flag bit (bit12: TMIE) is "1",
an interrupt request is sent to CPU.
Note:
To retrigger the 16-bit timer, be sure to write "0" before write "1" to this bit.
•
•
bit10
to
bit8
384
TMD2 to TMD0:
Operation mode
bits
These bits are used to select the operation mode of the waveform generator.
When TMD2 to TMD0=000B, output compare RT2 and RT3 output to
RTO2 and RTO3 respectively. And 16-bit timer can be used as reload timer.
• When TMD2 to TMD0=001B, output compare RT2 and RT3 output to
RTO2 and RTO3 respectively if PPG0 output is disabled
(PICSH01:PGEN2=0, PGEN3=0). And 16-bit timer can be used as reload
timer.
Notes:
- To operate the waveform generator in dead-time timer mode, be sure to
select 2-channel mode for RT3 (OCS3:CMOD=1)
- When TMD2 to TMD0=111B is selected, RTO2 and RTO3 outputs are
independent of setting in PICSH01:PGEN2, 3.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
MB90820B Series
15.4.10
Waveform Control Register (SIGCR)
Waveform control register is used to control how the operating clock frequencies, noise
cancellation function enable, DTTI input enable, and DTTI interrupt.
■ Waveform Control Register (SIGCR)
Figure 15.4-22 Waveform control register (SIGCR)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
Initial value
000059H DTIE DTIF NRSL DCK2 DCK1 DCK0 NWS1 NWS0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
NWS1
R/W
R/W
NWS0
DTTI Noise width selection bits
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
DCK2 DCK1 DCK0
Operating clock selection bit
0
0
0
φ (41.7 ns, φ = 24 MHz)
0
0
1
φ/2 (83.3 ns, φ = 24 MHz)
0
1
0
φ/4 (167 ns, φ = 24 MHz)
0
1
1
φ/8 (333 ns, φ = 24 MHz)
1
0
0
φ/16 (0.67 µs, φ = 24 MHz)
1
0
1
φ/32 (1.33 µs, φ = 24 MHz)
1
1
0
φ/64 (2.67 µs, φ = 24 MHz)
1
1
1
Prohibited
φ: Machine cycle
NRSL
Noise cancellation function enable bit
0
DTTI input does not go thru the noise cancellation circuit.
1
DTTI input goes thru the noise cancellation circuit.
DTTI interrupt flag bit
DTIF
R/W : Read and Write
Read
Write
0
No interrupt request
Clear this bit
1
Has interrupt request
No effect
DTIE
DTTI input enable bit
0
Disable DTTI input
1
Enable DTTI input
: Initial value
CM44-10147-2E
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.4
Table 15.4-11
MB90820B Series
Waveform control register (SIGCR)
Bit name
bit15
DTIE:
DTTI input
enable bit
Function
•
This bit is used to enable the DTTI pin to control the output level of
RTO0 to 5 pins.
•
•
bit14
DTIF:
DTTI interrupt
flag bit
This bit is an interrupt flag for DTTI.
When DTTI input is enabled (DTIE=1) and L level of DTTI is
detected, this bit will be set, and interrupt request will send to CPU.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
Notes:
- If noise cancellation function is enabled (NRSL=1), this bit will
be set to "1" when noise pulse width is passed.
- If both software clear (writing "0") and hardware set (L level of
DTTI is detected) occurs simultaneously, software clear takes the
higher priority to clear this bit.
•
•
386
bit13
NRSL:
Noise
cancellation
function
enable bit
This bit is used to enable the noise cancellation function.
Noise cancellation circuit will receive DTTI input signal when the L
level is held until the counter overflows. The counter is n-bit counter
which is operated by the L level input. The value of n can be 2, 3, 4
and 5 which depends on the setting of NWS1 and NWS0 bits.
Notes:
- To cancel the noise pulse width, it takes approximately 2n
machine cycles.
- When the noise cancellation circuit is selected, the input will
become invalid in a mode such as STOP mode in which the
internal clock is stopped.
bit12
to
bit10
DCK2 to DCK0:
Operating clock
selection bits
•
These bits are used to select the operating clock for the 16-bit timer.
bit9,
bit8
NWS1 and NWS0:
DTTI Noise
width selection
bits
•
These bits are used to select the noise pulse width to be removed for
DTTI pin.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.5
MB90820B Series
15.5
Multi-functional Timer Interrupts
The multi-functional timer is enabled to generate interrupts in 16-bit free-run timer, 16bit output compare, 16-bit input capture, and waveform generator.
■ 16-bit Free-run Timer Interrupts
Table 15.5-1 lists the interrupt control bits and interrupt causes of the 16-bit free-run timer.
Table 15.5-1 Interrupt control bits and interrupt causes of the 16-bit free-run timer
16-bit free-run timer
Compare Clear
Zero Detect
Interrupt request flag bit
TCCSH:ICLR
TCCSH:IRQZF
Interrupt request enable bit
TCCSH:ICRE
TCCSH:IRQZE
Interrupt cause
16-bit free-run timer value
matches with compare clear
register (CPCLR)
16-bit free-run timer value equals
zero
In the 16-bit free-run timer, the ICLR bit of the timer control status register (TCCSH) is set to "1" when
timer value matches compare clear register (CPCLR). If an interrupt request is enabled (TCCSH:ICRE =
1) in this operation, the interrupt request is output to the interrupt controller.
The IRQZF bit of the timer control status register (TCCSH) is set to "1" when timer value equals 0000H. If
an interrupt request is enabled (TCCSH:IRQZE = 1) in this operation, the interrupt request is output to the
interrupt controller.
■ 16-bit Free-run Timer Interrupts and EI2OS
Table 15.5-2 lists the 16-bit free-run timer interrupts and EI2OS.
Table 15.5-2 16-bit free-run timer interrupts and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Compare clear *1
#34 (22H)
ICR11
0000BBH
FFFF74H
FFFF75H
FFFF76H
Zero detect *2
#31 (1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
∆
*1: The same interrupt control register as that for 16-bit free-run timer compare clear is assigned to 16-bit input capture
channels 0/1.
*2: The same interrupt control register as that for 16-bit free-run timer zero detect is assigned to 16-bit PPG timer 2.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.5
MB90820B Series
■ 16-bit Output Compare Interrupts
Table 15.5-3 lists the interrupt control bits and interrupt causes of the 16-bit output compare.
Table 15.5-3 Interrupt control bits and interrupt causes of the 16-bit output compare 0 to 5
16-bit output compare
0/1
16-bit output compare
2/3
16-bit output compare
4/5
Interrupt request flag
bit
OCS0:IOP0/IOP1
OCS2:IOP0/IOP1
OCS4:IOP0/IOP1
Interrupt request
enable bit
OCS0:IOE0/IOE1
OCS2:IOE0/IOE1
OCS4:IOE0/IOE1
Interrupt cause
16-bit free-run timer
value matches with
output compare register
(OCCP0/OCCP1)
16-bit free-run timer
value matches with
output compare register
(OCCP2/OCCP3)
16-bit free-run timer
value matches with
output compare register
(OCCP4/OCCP5)
The IOP0/IOP1 bit of the compare control register, lower byte (OCS0/OCS2/OCS4) is set to "1" when 16bit free-run timer value matches output compare register (OCCP0 to OCCP5). If an interrupt request is
enabled (OCS0/OCS2/OCS4:IOE0/IOE1 = 1) in this operation, the interrupt request is output to the
interrupt controller.
■ 16-bit Output Compare Interrupts and EI2OS
Table 15.5-4 lists the 16-bit output compare interrupts and EI2OS
Table 15.5-4 16-bit output compare interrupts and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Output compare 0 match *1
#12 (0CH)
ICR00
0000B0H
FFFFCCH
FFFFCDH
FFFFCEH
Output compare 1 match *2
#15 (0FH)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
Output compare 2 match *3
#17 (11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
Output compare 3 match *4
#19 (13H)
ICR04
0000B4H
FFFFB0H
FFFFB1H
FFFFB2H
Output compare 4 match *5
#21 (15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
Output compare 5 match *6
#23 (17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
O
*1:
*2:
*3:
*4:
The same interrupt control register as that for 16-bit output compare 0 is assigned to A/D conversion termination.
The same interrupt control register as that for 16-bit output compare 1 is assigned to 16-bit PPG timer 1.
The same interrupt control register as that for 16-bit output compare 2 is assigned to 16-bit reload timer 1 underflow.
The same interrupt control register as that for 16-bit output compare 3 is assigned to DTP/external interrupt channels 0/1
detection / DTTI.
*5: The same interrupt control register as that for 16-bit output compare 4 is assigned to DTP/external interrupt channels 2/3
detection / DTTI.
*6: The same interrupt control register as that for 16-bit output compare 5 is assigned to PWC timer 1.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.5
MB90820B Series
■ 16-bit Input Capture Interrupts
Table 15.5-5 lists the interrupt control bits and interrupt causes of the 16-bit input capture.
Table 15.5-5 Interrupt control bits and interrupt causes of the 16-bit input capture 0 to 3
16-bit input capture 0/1
16-bit input capture 2/3
Interrupt request flag bit
PICSL01:ICP0/ICP1
ICSL23:ICP2/ICP3
Interrupt request enable bit
PICSL01:ICE0/ICE1
ICSL23:ICE2/ICE3
Interrupt cause
Valid edge is detected in IN0/IN1
pins
Valid edge is detected in IN2/IN3
pins
In the 16-bit input capture, the ICP0/ICP1/ICP2/ICP3 bit of the input capture control status register
(PICSL01/ICSL23) is set to "1" when valid edge is detected in IN0/IN1/IN2/IN3 pins. If an interrupt
request is enabled (PICSL01/ICSL23:ICE0/ICE1 = 1) in this operation, the interrupt request is output to the
interrupt controller.
■ 16-bit Input Capture Interrupts and EI2OS
Table 15.5-6 lists the 16-bit input capture interrupts and EI2OS.
Table 15.5-6 16-bit input capture interrupts and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Input capture 0/1 *1
#33 (21H)
ICR11
0000BBH
FFFF78H
FFFF79H
FFFF7AH
Input capture 2/3 *2
#35 (23H)
ICR12
0000BCH
FFFF70H
FFFF71H
FFFF72H
O
*1: The same interrupt control register as that for 16-bit input capture 0/1 is assigned to 16-bit free-run timer compare
clear.
*2: The same interrupt control register as that for 16-bit input capture 2/3 is assigned to time-base timer.
■ Waveform Generator Interrupts
Table 15.5-7 lists the interrupt control bits and interrupt causes of the waveform generator.
Table 15.5-7 Interrupt control bits and interrupt causes of the waveform generator
Waveform generator
16-bit timer 0/1/2
DTTI
Interrupt request flag bit
DTCR0/DTCR1/DTCR2:TMIF
SIGCR:DTIF
Interrupt request enable bit
DTCR0/DTCR1/DTCR2:TMIE
--
Interrupt cause
16-bit timer 0/1/2 underflow
L level is detected in DTTI
In the waveform generator, the TMIF bit of the 16-bit timer control register (DTCR0/DTCR1/DTCR2) is
set to "1" when 16-bit timer underflow and DTCR0/DTCR1/DTCR2:TMD2 to TMD0=000B or 001B. If an
interrupt request is enabled (DTCR0/DTCR1/DTCR2:TMIE = 1) in this operation, the interrupt request is
output to the interrupt controller.
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■ Waveform Generator Interrupts and EI2OS
Table 15.5-8 lists the waveform generator interrupts and EI2OS.
Table 15.5-8 Waveform generator interrupts and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
16-bit timer 0/1/2
underflow *1
#29 (1DH)
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8AH
DTTI *2
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
∆
*1: The same interrupt control register as that for 16-bit timer 0/1/2 underflow is assigned to 16-bit reload timer 0
underflow.
*2: The same interrupt control register as that for DTTI is assigned to DTP/external interrupt channels 0/1 detection and
16-bit output compare 3.
■ EI2OS Function of the Multi-functional Timer
Since the multi-functional timer has a circuit that coordinates with EI2OS, when the interrupt is generated,
it can start EI2OS.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when 16-bit free-run timer compare clear uses EI2OS, interrupts
of 16-bit input capture channels 0/1 must be disabled.
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
MB90820B Series
15.6
Operation of Multi-functional Timer
This section describes the operation of the multi-functional timer.
■ Operation of Multi-functional Timer
● 16-bit free-run timer
The 16-bit free-run timer starts counting up from value set in timer data register (TCDT) after a reset has
been completed. The counter value is used as the reference time for 16-bit output compare and 16-bit input
capture.
● 16-bit output compare
The 16-bit output compare is used to compare the value set in the specified output compare register with
the value of the 16-bit free-run timer. If a match is detected, the interrupt flag is set and the output level is
inverted.
● 16-bit input capture
The 16-bit input capture is used to detect a specified valid edge. If a valid edge is detected, the interrupt
flag is set, and the value of 16-bit free-run timer is fetched and stored into the input capture data register.
● Waveform generator
Waveform generator can produce various waveform such as dead-time, by using the realtime outputs
(RTO0 to RTO5), 16-bit PPG timer 0, and 16-bit timers.
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15.6.1
MB90820B Series
Operation of 16-bit Free-run Timer
The 16-bit free-run timer starts counting up from counter value specified in timer data
register (TCDT) after a reset has been completed. The counter value is used as the
reference time for 16-bit output compare and 16-bit input capture.
■ Timer Clear
The counter value of 16-bit free-run timer is cleared in the following conditions:
• When a match with compare clear register is detected in up-count mode (TCCSL:MODE=0)
• When "1" is written to the SCLR bit of the TCCSL register during operation, the timer will be cleared at
the valid edge of count clock.
Note : If writing "0" to the SCLR bit before a valid edge of count clock, the SCLR bit is cleared and the
timer would not be cleared to "0000H"
• When "0000H" is written to the TCDT register during stop.
• Reset
By a reset, the counter is immediately cleared. By a software clear or a match with compare clear register,
the counter is cleared in synchronization with the count timing.
Figure 15.6-1 16-bit free-run timer clear timing
φ
Compare
register value
N
Compare match
cleared by hardware
writing “1”
writing “0”
writing “0”
TCCSL : SCLR
Counter value
N -1
N
0000
0001
0000
0001
0002
■ Timer Mode
Two count modes can be selected in 16-bit free-run timer:
• up-count mode (TCCSL:MODE=0)
• up-down count mode (TCCSL:MODE=1)
In up-count mode, counter starts counting from pre-set timer data register (TCDT), counts up until counter
value matches value of compare clear register (CPCLR), then counter is cleared to 0000H, and counts up
again.
In up-down count mode, counter starts counting from pre-set timer data register (TCDT), counts up until
counter value matches value of compare clear register (CPCLR), then counter changes from up-count to
down-count, counts down until counter value reaches "0000H" and then counts up again.
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MB90820B Series
There is a buffer in mode bit, TCCSL:MODE, it can be written at any time no matter the timer is operating
or stopped. While the timer is operating, value written to this bit is buffered and the count mode will be
changed when timer value is "0000H".
Figure 15.6-2 Change timer mode while timer is operating
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Timer starts
Change to up-down mode
Compare clear
buffer register
Change to up mode
BFFFH
TCCSL:MODE
■ Compare Clear Buffer
There is a selected buffer function on compare clear register (CPCLR). In buffer enable (TCCSL:BFE=1),
data written in compare clear buffer register (CPCLRB) will transfer to CPCLR at zero detection of the 16bit free-run timer. In buffer disable (TCCSL:BFE=0), CPCLRB is transparent, data can directly be written
into CPCLR.
Figure 15.6-3 Operation in up-count mode with compare clear buffer is disabled (TCCSL:BFE=0)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Reset
Compare clear
buffer register
value
Compare clear
register value
CM44-10147-2E
Zero detect
Zero detect
BFFFH
BFFFH
7FFFH
7FFFH
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FFFFH
FFFFH
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15.6
MB90820B Series
Figure 15.6-4 Operation in up-count mode with compare clear buffer is enabled (TCCSL:BFE=1)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Zero detect
Zero detect
Reset
Compare clear
buffer register
value
Compare clear
register value
FFFFH
7FFFH
BFFFH
FFFFH
7FFFH
BFFFH
Figure 15.6-5 Operation in up-down count mode with compare clear buffer enabled (TCCSL:BFE=1)
Counter value
FFFFH
Compare clear match
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
Reset
Compare clear
buffer register
value
Compare clear
register value
394
Zero detect
BFFFH
7FFFH
BFFFH
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FFFFH
7FFFH
FFFFH
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
MB90820B Series
■ Timer Interrupts
Two interrupts can be generated from 16-bit free-run timer:
• Compare clear interrupt
• Zero detect interrupt
Compare clear interrupt is generated when the timer value matches compare clear register (CPCLR). Zero
detect interrupt is generated when the timer value reaches "0000H".
Note:
Software clear (TCCSL:SCLR=1) will not generate zero detect interrupt.
Figure 15.6-6 Interrupts generated in up-count mode (TCCSL:MODE=0)
Counter
N-1
N
0
1
Compare clear
Zero detect
Figure 15.6-7 Interrupts generated in up-down count mode (TCCSL:MODE=1)
Counter
N-1
N
N-1
0
Compare clear
Zero detect
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MB90820B Series
■ Interrupt Mask Function
The interrupt request can be masked by setting TCCSH:MSI2 to MSI0. MSI2 to MSI0 configure a 3-bit
reload down counter, which reloads when its count value reaches "000B". Count value can also be loaded
by writing directly to MSI2 to MSI0. The mask count equals the value set in MSI2 to MSI0 and there is no
interrupt source will be masked when MSI2 to MSI0 equals "000B"
The interrupt source depends on the count mode (TCCSL:MODE). In up-count mode, only compare clear
interrupt can be masked, zero detect interrupt is generated in every zero detection. In up-down count mode,
only zero detect interrupt can be masked, compare clear interrupt is generated in every compare clear.
Note:
Software clear (TCCSL:SCLR=1) will not generate zero detection.
Figure 15.6-8 Compare clear interrupt masked in up-count mode
Counter value
2nd
1st
FFFFH
Compare clear match
3rd
4th
5th
6th
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
Reset
Zero detect interrupt
Compare
clear
interrupt
Software
clear
TCCSH:MSI[2:0]=000B
TCCSH:MSI[2:0]=001B
TCCSH:MSI[2:0]=010B
* Both zero detect interrupt and compare clear interrupt are cleared by software.
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MB90820B Series
Figure 15.6-9 Zero detect interupt masked in up-down count mode
Counter value
FFFFH
Compare clear match
3rd
4th
2nd
1st
6th
5th
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
1st
Reset
2nd
Zero detect
3rd
4th
6th
5th
Compare clear interrupt
Zero
detect
interrupt
TCCSH:MSI[2:0]=000B
Software
clear
TCCSH:MSI[2:0]=001B
TCCSH:MSI[2:0]=010B
* Both zero detect interrupt and compare clear interrupt are cleared by software.
■ External Count Clock Selected
The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When
external clock is selected, the 16-bit free-run timer counts up at a rising edge when the initial value of
external input is “1” or at a falling edge when initial value of external clock input is “0” after external clock
mode is selected (TCCSH:ECKE=1).
Figure 15.6-10 16-bit free-run timer count timing
φ
External clock
input
TCCSH:ECKE
Count clock
Counter value
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N
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N+1
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
15.6.2
MB90820B Series
Operation of 16-bit Output Compare
The output compare unit is used to compare the value set in the specified compare
register with the value of the 16-bit free-run timer. If a match is detected, the interrupt
flag is set and the output level is inverted.
■ 16-bit Output Compare Operation
a) Compare operation can be performed for individual channel (OCS1/3/5:CMOD = 0)
Figure 15.6-11 Sample output waveform when compare registers 0 and 1 are used individually when the
initial output value is "0" (free-run timer in up-count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
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MB90820B Series
Figure 15.6-12 Sample output waveform when compare registers 0 and 1 are used individually when the
initial output value is "0" (free-run timer in up-down count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
b) Output level can be changed by using a pair of compare registers (OCS1/3/5:CMOD = 1)
Figure 15.6-13 Sample output waveform when compare registers 0 and 1 are used in a pair when the
initial output value is "0" (free-run timer in up-count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0
value
Compare register 1
value
RT0
BFFFH
7FFFH
associated with
compare 0
associated with
compare 0 & 1
RT1
Compare 0
interrupt
Compare 1
interrupt
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Figure 15.6-14 Sample output waveform when compare register 0 and 1 are used in a pair when the initial
output value is "0" (free-run timer in up-down count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
associated with
compare 0
RT1
associated with
compare 0 & 1
Compare 0
interrupt
Compare 1
interrupt
c) Output level when compare buffer is disabled
Figure 15.6-15 Sample output waveform when compare buffer is disabled
(free-run timer in up-count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Reset
Compare clear match
Compare clear match
Compare buffer
register 0 value
BFFFH
3FFFH
BFFFH
Compare
register 0 value
BFFFH
3FFFH
BFFFH
RT0
Interrupt
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MB90820B Series
d) Output level when compare buffer is selected at compare clear match
Figure 15.6-16 Sample output waveform when compare buffer is enable
(free-run timer in up-down count mode).
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Zero detection
Timer starts
Reset
Compare buffer
register 0 value
Compare
register 0 value
Compare clear match
BFFFH
BFFFH
3FFFH
BFFFH
3FFFH
BFFFH
3FFFH
RT0
Interrupt
■ 16-bit Output Compare Timing
When the free-run timer matches the value set in the compare register, the output compare unit generates a
compare match signal to invert the output and generates an interrupt. When a compare match occurs, the
output is inverted in synchronization with the count timing of the counter.
Note:
When the compare register is updated, comparison with the counter value is not performed.
Figure 15.6-17 Compare operation upon update of compare registers
Counter value
Compare
register 0 value
Compare
register 0 write
Compare
register 1 value
Compare
register 1 write
CM44-10147-2E
N
N+1
N+2
N+3
No match signal is generated.
M
N+1
N+3
L
Compare 0 stop
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Compare 1 stop
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15.6
MB90820B Series
Figure 15.6-18 Compare interrupt timing
φ
Counter value
N
N+1
Compare
register
value
N
Compare
match
Interrupt
Figure 15.6-19 Output pin change timing
Counter value
Compare
register
value
N
N+1
N
N+1
N
Compare
match
signal
Pin output
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
MB90820B Series
15.6.3
Operation of 16-bit Input Capture
The input capture unit is used to detect a specified valid edge. If a valid edge is
detected, the interrupt flag is set and the value of 16-bit free-run timer is loaded into the
capture register.
■ 16-bit Input Capture Operation
Figure 15.6-20 Sample input capture timing
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0
IN1
IN example
Capture register 0
Undefined
Capture register 1
Capture register
example
Capture 0 interrupt
Undefined
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Capture 1 interrupt
Capture example
interrupt
Interrupt is generated
with another valid edge
Note: Capture 0: Rising edge
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Interrupt is cleared
by software
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MB90820B Series
■ 16-bit Input Capture Input Timing
Figure 15.6-21 16-bit input capture timing for input signals
φ
Machine clock
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
404
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
MB90820B Series
15.6.4
Operation of Waveform Generator
Waveform generator can produce various waveform such as dead-time, by using the
realtime outputs (RT0 to RT5), 16-bit PPG timer 0, and 16-bit timers 0/1/2.
■ Output Condition of RTO0 to RTO5 and GATE
Table 15.6-1 Output condition of RTO0 to RTO5, GATE and register bit setting
TMD2 TMD1 TMD0 GTENx PGENx
RTOx *2
GATE
0
0
0
X
X
Realtime output, RTx
Always "0"
0
0
1
X
0
Realtime output, RTx
OR(RTx & GTENx)
0
0
1
0
1
PPG0 output pulse when RTx is high
Always "0"
0
0
1
1
1
Gate triggered PPG0 output pulse when RTx is high
OR(RTx)
Output "H" from rising edge of RTx to 16-bit timer 0
underflow (x=0, 1)
0
1
0
X
0
Output "H" from rising edge of RTx to 16-bit timer 1
underflow (x=2, 3)
OR(RTOx & GTENx)
Output "H" from rising edge of RTx to 16-bit timer 2
underflow (x=4, 5)
PPG0 output pulse from rising edge of RTx to 16-bit timer
0 underflow (x=0, 1)
0
1
0
0
1
PPG0 output pulse from rising edge of RTx to 16-bit timer
Always "0"
1 underflow (x=2, 3)
PPG0 output pulse from rising edge of RTx to 16-bit timer
2 underflow (x=4, 5)
0
1
0
1
1
Gate triggered PPG0 output pulse from rising edge of RTx
OR(output “H” from
to 16-bit timer 0 underflow (x=0, 1)
RTx/y/z rising edge to
Gate triggered PPG0 output pulse from rising edge of RTx timer 0/1/2 underflow)
to 16-bit timer 1 underflow (x=2, 3)
x=0, 1
y=2, 3
Gate triggered PPG0 output pulse from rising edge of RTx z=4, 5
to 16-bit timer 2 underflow (x=4, 5)
Generate non-overlap signal by RT1 (x=0, 1) *1
1
0
0
X
X
Generate non-overlap signal by RT3 (x=2, 3) *1
Always "0"
Generate non-overlap signal by RT5 (x=4, 5) *1
1
1
1
0
X
Generate non-overlap signal by PPG0
Always "0"
1
1
1
1
X
Generate non-overlap signal by gate triggered PPG0
OR(RTx)
Always "0"
Always "0"
Others
*1 In order to generate non-overlap signal, be sure to select 2-channel mode for RT1/3/5 (OCS1/3/5:CMOD=1)
*2 RTO0/1 is controlled by DTCR0:TMD2 to TMD0, RTO2/3 is controlled by DTCR1:TMD2 to TMD0 and RTO4/5 is controlled
by DTCR2:TMD2 to TMD0.
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MB90820B Series
■ PPG0 Output Control
PPG0 output to RTO0 to RTO5 can be enabled by PGEN0 to PGEN5 in PPG output control/input capture
control status register (PICSH01).
■ Gate Triggered PPG0 Output
In waveform generator, a GATE signal can be generated by using realtime outputs RT0 to RT5 or cope
with 16-bit timers 0/1/2 to trigger PPG0 counting. When 16-bit timer is used, two real-time outputs (RT0/2/
4 and RT1/3/5) is operated with one 16-bit timer 0/1/2 to generate six individual gate signal. And these six
gate signals are logically OR to generate a GATE signal to trigger PPG0 counting.
If PGEN0 to PGEN5 signals are is also used, six different waveforms can be output to RTO0 to RTO5 by
using one PPG0 only.
■ Generating GATE Signal During Each RTx is at "H" Level When GTENx is Active
(DTCR0/1/2:TMD2 to TMD0=001B or 111B)
Figure 15.6-22 Generating GATE signal during RTx is at "H" level
16-bit free-run timer
FFFFH
BFFFH
Count value
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
GATE
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MB90820B Series
■ Generating GATE Signal from Rising Edge of Each RTx until 16-bit Timer 0/1/2
Underflow When GTENx is Active (DTCR0/1/2:TMD2 to TMD0=010B)
Figure 15.6-23 Generating GATE signal from rising edge of RTx until 16-bit timer underflow
16-bit free-run timer
FFFFH
BFFFH
Count value
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
Time of
16-bit timer 0
Time of
16-bit timer 0
GATE
Note:
Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is
used for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and
attempt to start the corresponding timer that is already operating. Doing so may cause that the
outputting GATE signal will be extended and malfunction will be occurred.
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15.6.4.1
MB90820B Series
Operation in Timer Mode
With RT0 to RT5 rising edge, the 16-bit timer is reloaded and starts down-counting, and
the PPG timer 0 keeps outputting to RTO0 to RTO5 until the 16-bit timer is underflow.
■ PPG0 Output Pulse from Rising Edge of RT to 16-bit Timer Underflow
(DTCR0/1/2:TMD2 to TMD0=010B)
Figure 15.6-24 Waveform generated when TMD2 to TMD0=010B
Setting up registers:
• PCSR
: XXXXH
• TCDT
: 0000H
• PDUT
: XXXXH
• TCCSL
: XXXXXXXXXX0X0XXXB
• PCNT
: XXXXH
• CPCLR
: XXXXH (Cycle setting)
• PICS01
: XXH (PPG0 output selection)
• OCCP0 to OCCP5: XXXXH (Compare value)
• OCS0 to OCS5 : -XX0XXXXXXXXXX11B
• DTCR0 to DTCR2 : 011XX010B
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXX00B (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit free-run timer
FFFFH
Count
value
BFFFH
7FFFH
3FFFH
0000H
Time
PPG0
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE
RTO0
RTO1
Time of
16-bit timer 0
408
Time of
16-bit timer 0
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15.6
Note:
Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is
used for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and
attempt to start PPG0 which is under operation. Doing so may cause that the outputting GATE signal
will be extended and malfunction will be occurred.
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15.6
15.6.4.2
MB90820B Series
Operation in Dead-time Timer Mode
The dead-time generator will input the realtime output (RT1/3/5), input PPG timer 0 pulse,
and output non-overlap signals (inverted signals) to external pins (RTO0 to RTO5).
■ Making Non-overlap Signals by Using RT1/3/5 in Normal Polarity
(DTCR0/1/2:TMD2 to TMD0=100B)
When selecting non-overlap signal for an active level “0” (normal polarity) in DTCR0/1/2:DMOD, a delay
corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is applied. The delay
is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is smaller than the set nonoverlap time, the 16-bit timer will restart down-counting from TMRR0/1/2 value at the next RT’s edge.
Figure 15.6-25 Non-overlap signal generation by RT1/3/5 in normal polarity
Setting up registers:
• CPCLR:
XXXXH (Cycle setting)
• TCDT:
0000H
•
OCS0
to
OCS5:
-XX1XXXXXXXXXX11B
• TCCS:
X--XXXXXX0X0XXXB
• DTCR0 to DTCR2 : 0XXXX100B
• OCCP0 to OCCP5:XXXXH (Compare value)
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR:
XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
410
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at RT1 rising edge
RTO2 (V)
Signal with delay is applied at RT3 rising edge
RTO4 (W)
Signal with delay is applied at RT5 rising edge
RTO1 (X)
Inverted signal with delay is applied at RT1 falling edge
RTO3 (Y)
Inverted signal with delay is applied at RT3 falling edge
RTO5 (Z)
Inverted signal with delay is applied at RT5 falling edge
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MB90820B Series
■ Making Non-overlap Signals by using RT1/3/5 in Inverted Polarity
(DTCR0/1/2:TMD2 to TMD0=100B)
When selecting non-overlap signal for an active level “1” (inverted polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is
smaller than the set non-overlap time, the 16-bit timer will restart down-counting from TMRR0/1/2 value at
the next RT’s edge.
Figure 15.6-26 Non-overlap signal generation by RT1/3/5 in inverted polarity
Setting up registers:
• TCDT:
0000H
• CPCLR:
XXXXH (Cycle setting)
• TCCS:
XXXXXXXXXX0X0XXXB
• OCS0 to OCS5: -XX1XXXXXXXXXX11B
• OCCP0 to OCCP5: XXXXH (Compare value)
• DTCR0 to DTCR2: 1XXXX100B
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR:
XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
CM44-10147-2E
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at RT1 rising edge
RTO2 (V)
Inverted signal with delay is applied at RT3 rising edge
RTO4 (W)
Inverted signal with delay is applied at RT5 rising edge
RTO1 (X)
Signal with delay is applied at RT1 falling edge
RTO3 (Y)
Signal with delay is applied at RT3 falling edge
RTO5 (Z)
Signal with delay is applied at RT5 falling edge
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MB90820B Series
■ Making Non-overlap Signals by Using PPG in Normal Polarity
(DTCR0/1/2:TMD2 to TMD0=111B)
When selecting non-overlap signal for an active level “0” (normal polarity) in DTCR0/1/2:DMOD, a delay
corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is applied. The
delay is applied at a rising edge of PPG timer 0 pulse signal or its inverted signal. If PPG timer pulse width
is smaller than the set non-overlap time, the 16-bit timer will restart down-counting from TMMR0/1/2
value at the next edge of PPG0 pulse.
Figure 15.6-27 Non-overlap signal generation by PPG timer0 in normal polarity
Setting up registers:
• PCSR : XXXXH
• TCDT:
0000H
• PDUT : XXXXH
• TCCS:
XXXXXXXXXX0X0XXXB
• PCNT : XXXXH
• CPCLR:
XXXXH (Cycle setting)
• OCCP0 to OCCP5: XXXXH (Compare value)
• OCS0 to OCS5:
-XX1XXXXXXXXXX11B
• DTCR0 to DTCR2: 0XXXX111B
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR:
XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
412
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at PPG0 rising edge
RTO2 (V)
Signal with delay is applied at PPG0 rising edge
RTO4 (W)
Signal with delay is applied at PPG0 rising edge
RTO1 (X)
Inverted signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Inverted signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Inverted signal with delay is applied at PPG0 falling edge
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MB90820B Series
■ Making Non-overlap Signals by Using PPG in Inverted Polarity
(DTCR0/1/2:TMD2 to TMD0=111B)
When selecting non-overlap signal for an active level “1” (inverted polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of PPG timer 0 pulse signal or its inverted signal. If PPG timer
0 pulse width is smaller than the set non-overlap time, the 16-bit timer will restart down-counting from
TMMR0/1/2 value at the next edge of PPG0 pulse.
Figure 15.6-28 Non-overlap signal generation by PPG timer0 in inverted polarity
Setting up registers:
• PCSR : XXXXH
• TCDT:
0000H
• PDUT : XXXXH
• TCCS:
XXXXXXXXXX0X0XXXB
• PCNT : XXXXH
• CPCLR:
XXXXH (Cycle setting)
• OCCP0 to OCCP5:XXXXH (Compare value)
• OCS0 to OCS5:
-XX1XXXXXXXXXX11B
• DTCR0 to DTCR2: 1XXXX111B
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR:
XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
CM44-10147-2E
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at PPG0 rising edge
RTO2 (V)
Inverted signal with delay is applied at PPG0 rising edge
RTO4 (W)
Inverted signal with delay is applied at PPG0 rising edge
RTO1 (X)
Signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Signal with delay is applied at PPG0 falling edge
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15.6.4.3
MB90820B Series
Operation of DTTI Pin Control
By setting “1” to waveform control register, SIGCR: bit 15 (DTIE), the output of RTO0 to
RTO5 can be controlled by the DTTI pin. When “L” level in DTTI pin is detected, the output
of RTO0 to RTO5 will be fixed to an inactive level until the interrupt flag, SIGCR: bit 14 (DTIF) is
cleared. The inactive level of RTO0 to RTO5 can be set by PDR8 in port 8 by software.
■ DTTI pin Input Operation
Even when the "L" level of DTTI pin input is detected, the timer will keep running for the waveform
generator operation, but no waveform will be outputted to external pins P82/RTO0 to P87/RTO5.
Figure 15.6-29 Operation when DTTI input is enabled
Setting up registers:
• TCDT:
0000H
• CPCLR:
XXXXH (Cycle setting)
• TCCS:
XXXXXXXXXX0X0XXXB
• OCS0 to OCS5:
-XX1XXXXXXXXXX11B
• OCCP0 to OCCP5: XXXXH (Compare value)
• DTCR0 to DTCR2: 0XXXX100B
• PDR3:
XXXXXX00B (Inactive level setting)
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
• SIGCR:
1XXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit free-run timer
FFFFH
Count value
BFFFH
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT1
RTO0
RTO1
DTTI
DTIF
Output inactive
Software clear
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CHAPTER 15 MULTI-FUNCTIONAL TIMER
15.6
MB90820B Series
■ DTTI Pin Noise Cancellation Function
By setting bit 13 (NRSL) of the waveform control register (SIGCR) to “1”, the noise cancellation function
for DTTI pin input is enabled. When noise cancellation function is enabled, the time for fixing an output
pin (RTO0 to RTO5) to inactive level is delayed for about 4, 8, 16 or 32 machine cycles (selected by
SIGCR:NWS1, NWS0). Since the noise cancellation circuit uses a peripheral function, input is invalidated
even if the DTTI input is enabled in a mode such as STOP mode in which the oscillation stops.
■ DTTI Interrupt
When L level of DTTI is detected, DTTI interrupt flag (SIGCR:DTIF) is set to “1” after noise cancellation
time is passed and an interrupt request is sent to interrupt controller.
Figure 15.6-30 DTTI interrupt timing
DTTI
SIGCR: DTIF
Noise cancellation time controlled
by SIGCR:NWS1, NWS0
Software write “0” in SIGCR: DTIF
Notes:
• If SIGCR:NWS1, NWS0 is changed within noise cancellation time, the larger value of NWS1,
NWS0 will take effect.
• SIGCR:DTIF can only be cleared by software.
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15.7
15.7
MB90820B Series
Usage Notes on the Multi-functional Timer
Notes on using the multi-functional timer are given below.
■ Usage Notes on the 16-bit Free-run Timer
● Notes about using a program for setting
• After reset, the timer value is 0000H, zero detect interrupt flag will be set to “1” in next count clock after
timer enable (TCCSL:STOP=0).
• Since the timer mode bit (TCCSL:MODE) has a buffer, changing timer mode will take effect in next
count cycle. Zero detect interrupt is always generated when timer mode is changed from up-count to updown count mode.
• Software clear (TCCSL:SCLR=1) will initialize the timer but not generate zero detect interrupt.
● Notes about interrupts
• When the IRQZF bit of the timer control status register (TCCSH) is set to 1 and an interrupt request is
enabled (TCCSH:IRQZE=1), control cannot be returned from interrupt processing. Always clear the
IRQZF bit.
• When the ICLR bit of the timer control status register (TCCSH) is set to 1 and an interrupt request is
enabled (TCCSH:ICRE=1), control cannot be returned from interrupt processing. Always clear the
ICLR bit.
• Since the 16-bit free-run timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit free-run timer, shared resource interrupts must be disabled.
■ Usage Notes on the 16-bit Output Compare
● Notes about interrupts
• When the IOP bit of the compare control register (OCS0/2/4) is set to 1 and an interrupt request is
enabled (OCS0/2/4:IOE=1), control cannot be returned from interrupt processing. Always clear the IOP
bit.
• Since the 16-bit output compare shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit output compare, shared resource interrupts must be disabled.
■ Usage Notes on the 16-bit Input Capture
● Notes about interrupts
• When the ICP bit of the input capture control status register (PICSL01/ICSL23) is set to 1 and an
interrupt request is enabled (PICSL01/ICSL23:ICE=1), control cannot be returned from interrupt
processing. Always clear the ICP bit.
• If input capture pins (IN) level is toggled after ICP bit is set but before interrupt routine is processed, the
valid edge indication bit (ICSH23:IEI3, IEI2 or PICSH01:IEI1, IEI0) will show the latest edge detected.
• Since the 16-bit input capture shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit input capture, shared resource interrupts must be disabled.
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MB90820B Series
■ Usage Notes on the Waveform Generator
● Notes on using a program for setting
• Change the TMD2, TMD1 and TMD0 bits of the 16-bit timer control register (DTCR0/1/2) when the
waveform generator is under operation (DTCR0/1/2: TMD2 to TMD0=001B, 010B, 100B or 111B),
always be sure no trigger source and 16-bit timer are not counting. Otherwise unexpected waveform in
RTO will be occurred due to prescheduled output by previous trigger. But RTO output becomes normal
once after timer is underflow or retriggered by new trigger source in new mode setting.
Trigger source is H level of RT when DTCR0/1/2: TMD2 to TMD0=001B, rising edge of RT when
TMD2 to TMD0=010B, rising/falling edge of RT when TMD2 toTMD0=100B or rising/falling edge of
PPG0 when TMD2 to TMD0=111B.
For example, changing TMD2 to TMD0 from 100B to 111B, you can set infollowing procedures
1) set TMRR0/1/2 to a very small value like 0001H
2) set RT1/3/5 to output “L”/”H” and wait until timer 0/1/2 underflow
3) change mode bits TMD2, TMD1 and TMD0 and corresponding setting
4) corrected output waveform will appear in RTO pins one machine cycle later
• Writing a value in 16-bit timer register (TMRR0/1/2) during timer counting, new value will be valid at
the next timer trigger. And always be sure to use a word transfer instruction (MOVW A, dir, etc.) to
access timer register.
• Change the DCK2, DCK1 and DCK0 bits of the waveform control register (SIGCR) when the timer is
not counting.
• Change the NWS1 and NWS0 bits of waveform control register (SIGCR) when the noise cancellation
function is disabled (SIGCR: NRSL=0).
● Notes about interrupts
• When the TMIF bit of the 16-bit timer control register (DTCR0/1/2) is set to 1 and an interrupt request
is enabled (DTCR0/1/2:TMIE=1), control cannot be returned from interrupt processing. Always clear
the TMIF bit.
• When the DTIF bit of the waveform control register (SIGCR) is set to 1, control cannot be returned
from interrupt processing. Always clear the DTIF bit.
• Since the waveform generator shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the waveform generator, shared resource interrupts must be disabled.
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CHAPTER 16
DELAYED INTERRUPT
GENERATOR MODULE
This chapter describes the functions and operation of
the delayed interrupt generator module.
16.1 Overview of the Delayed Interrupt Generator Module
16.2 Delayed Interrupt Generator Module Register
16.3 Operation of the Delayed Interrupt Generator Module
16.4 Usage Notes on the Delayed Interrupt Generator Module
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CHAPTER 16 DELAYED INTERRUPT GENERATOR MODULE
16.1
16.1
MB90820B Series
Overview of the Delayed Interrupt Generator Module
The delayed interrupt generator module generates interrupts for task switching. By
using this module, software can issue and cancel interrupt requests for the F²MC-16LX
CPU.
■ Block Diagram of the Delayed Interrupt Generator Module
Figure16.1-1 shows the block diagram of the delayed interrupt generator module.
F2MC-16LX bus
Figure 16.1-1 Block diagram of the delayed interrupt generator module
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Delayed interrupt cause issuance/cancellation decoder
Interrupt cause latch
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16.2
MB90820B Series
16.2
Delayed Interrupt Generator Module Register
This section lists the delayed interrupt generator module register.
■ Delayed Interrupt Generator Module Register (DIRR)
Figure 16.2-1 Delayed interrupt generator module register (DIRR)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00009FH
—
—
—
—
—
—
—
R0
XXXXXXX0B
—
—
—
—
—
—
—
R/W
bit8
X
: Undefined value
R/W : Read and write
R0
Delayed interrupt request
0
Clears delayed interrupt request
1
Generates delayed interrupt request
: Initial value
—
: Not used
Table 16.2-1 Function of delayed interrupt request output/cancellation register (DIRR)
Bit name
bit15
to
bit9
bit8
CM44-10147-2E
Reserved bits
R0:
Delayed interrupt
request bit
Function
•
Both "0" and "1" may be written to the reserved bits, writing to these
bits has no effect on the operation.
•
This bit is used to controls the generation or clearing of a delayed
interrupt request.
Writing "0" to this bit clears the delayed interrupt request.
Writing "1" to this bit generates a delayed interrupt request.
The register is cleared at reset.
Both "0" and "1" may be written to the reserved bit area. However,
the set bit and clear bit instructions should be used to access this
register to prepare for future expansion.
•
•
•
•
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CHAPTER 16 DELAYED INTERRUPT GENERATOR MODULE
16.3
16.3
MB90820B Series
Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write 1 to the R0 bit of DIRR, the request latch in the
delayed interrupt generator module is set and an interrupt request is generated to the
interrupt controller.
■ Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write 1 to the R0 bit of DIRR, the request latch in the delayed interrupt
generator module is set and an interrupt request is generated to the interrupt controller. If the priority of
other interrupt requests is lower than that of this interrupt or no other interrupt request is generated, the
interrupt controller generates an interrupt request to the F²MC-16LX CPU. The F²MC-16LX CPU
compares the ILM bit of the internal CCR register and the interrupt request. When the request level is
higher than that of the ILM bit, the CPU starts the delayed interrupt processing microprogram immediately
after execution of the current instruction ends. As a result, the interrupt processing routine for this interrupt
is executed. This interrupt request is cleared and task switching is done by writing 0 to the R0 bit of user
program in the interrupt processing routine. Figure 16.3-1 Operation of the delayed interrupt generator
module shows the operation of the delayed interrupt generator module.
Figure 16.3-1 Operation of the delayed interrupt generator module
Delayed interrupt generator module
Delayed interrupt controller
WRITE
F2MC-16LX CPU
Other interrupt
requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
INTA
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16.4
CHAPTER 16 DELAYED INTERRUPT GENERATOR MODULE
16.4
Usage Notes on the Delayed Interrupt Generator Module
Notes on using the delayed interrupt generator module are given below.
■ Usage Notes on the Delayed Interrupt Request Latch
This latch is set by writing "1" to the R0 bit of DIRR and cleared by writing "0" to the same bit. Note that
interrupt processing is restarted at the moment control returns from interrupt processing unless software is
created to clear the cause in the interrupt processing routine.
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16.4
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CHAPTER 17
DTP/EXTERNAL INTERRUPT
CIRCUIT
This chapter describes the functions and operation of
the DTP/external interrupt circuit.
17.1 Overview of the DTP/External Interrupt Circuit
17.2 Block Diagram of the DTP/External Interrupt Circuit
17.3 DTP/External Interrupt Circuit Pins
17.4 DTP/External Interrupt Circuit Registers
17.5 Operation of the DTP/External Interrupt Circuit
17.6 Usage Notes on the DTP/External Interrupt Circuit
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.1
17.1
MB90820B Series
Overview of the DTP/External Interrupt Circuit
The data transfer peripheral (DTP)/external interrupt circuit is located between external
peripherals and the F2MC-16LX CPU. It receives interrupt requests and data transfer
requests from external peripherals and passes them to the CPU to generate interrupt
requests or activate the extended intelligent I/O service (EI2OS).
■ DTP/External Interrupt Functions
The DTP/external interrupt circuit detects the interrupt request which external peripherals generate. The
interrupt request is output to the CPU using the same procedure it uses for peripheral function interrupts
and generates interrupts or activates the extended intelligent I/O service (EI2OS).
If the extended intelligent I/O service (EI2OS) is disabled by the interrupt control register (ICR:ISE=0)
when an interrupt request is accepted by the CPU, the circuit executes its external interrupt function and
branches to an interrupt processing. If EI2OS is enabled (ICR: ISE=1), the circuit executes its DTP
function, which performs automatic data transfer using EI2OS and branches to an interrupt processing
routine after the data transfer has been performed a specified number of times.
Table 17.1-1 provides an overview of the DTP/external interrupt circuit.
Table 17.1-1 Overview of the DTP/external interrupt circuit
External interrupt function
Input pins
DTP function
Eight (P10/INT0/DTTI to P16/INT6, P51/INT7)
By using the request level setting register (ELVR), the level or edge to be
detected can be selected for each pin
Interrupt cause
Input of H level, L level, rising
edge or falling edge
Input of H level or L level
Interrupt number
#20 (14H), #22 (16H), #25 (19H), #26 (1AH), #27 (1BH), #28 (1CH)
Interrupt control
The output of interrupt requests is enabled and disabled using the DTP/
external interrupt enable register (ENIR)
Interrupt flag
Interrupt causes are stored in the DTP/external interrupt cause register
(EIRR)
Processing selection
EI2OS is disabled (ICR: ISE = 0)
EI2OS is enabled (ICR: ISE = 1)
Processing
The circuit branches to an external
interrupt processing
The circuit performs automatic data
transfer using EI2OS for a specified
number of times and then branches to
an interrupt processing
ICR: Interrupt control register
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.1
MB90820B Series
■ Interrupt of the DTP/External Interrupt Circuit and EI2OS
Table 17.1-2 Interrupt of the DTP/external interrupt circuit and EI2OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
INT0/INT1
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
INT2/INT3
#22 (16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
INT4
#25 (19H)
FFFF98H
FFFF99H
FFFF9AH
INT5
#26
(1AH)
FFFF94H
FFFF95H
FFFF96H
INT6
#27
(1BH)
FFFF90H
FFFF91H
FFFF92H
INT7
#28
(1CH)
FFFF8CH
FFFF8DH
FFFF8EH
ICR07
ICR08
0000B7H
Ο
0000B8H
Ο: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.2
17.2
MB90820B Series
Block Diagram of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit consists of four blocks, and the block diagram is
shown in Figure 17.2-1.
■ Block Diagram of the DTP/External Interrupt Circuit
Figure 17.2-1 Block diagram of the DTP/external interrupt circuit
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
Pin
2
2
2
2
2
2
Selector
Selector
P51/INT7
Pin
P10/INT0/DTTI
Selector
Pin
Selector
P16/INT6
Pin
P11/INT1
Pin
Internal data bus
2
Selector
Selector
P15/INT5
Pin
P12/INT2
Pin
Selector
Selector
Pin
P14/INT4
P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#20(14H)
#22(16H)
#25(19H)
#26(1AH)
#27(1BH)
#28(1CH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
● DTP/external interrupt input detection circuit
Upon detecting the level or edge selected for each pin by the interrupt request level setting register
(ELVR), this circuit sets "1" to the IR bit of the DTP/external interrupt cause register (EIRR) that
corresponds to the pin.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.2
MB90820B Series
● Request level setting register (ELVR)
This register selects the effective level or edge for each pin.
● DTP/external interrupt cause register (EIRR)
This register stores DTP/external interrupt causes. It contains DTP/external interrupt request flag bit for
each pin. The bit is set to "1" if a valid signal is input to the corresponding pin.
● DTP/external interrupt enable register (ENIR)
This register enables and disables DTP/external interrupt request of external peripherals.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.3
17.3
MB90820B Series
DTP/External Interrupt Circuit Pins
This section describes the DTP/external interrupt circuit pins and provides a pin block
diagram.
■ DTP/External Interrupt Circuit Pins
The DTP/external interrupt circuit pins are also used as general-purpose I/O ports. Table 17.3-1 lists the
pin functions, I/O formats, and settings required to use the DTP/external interrupt circuit.
Table 17.3-1 DTP/external interrupt circuit pins
Pin name
Pin function
Pull-up
operation
Standby
control
Setting required
to use pins
P10/
INT0/
DTTI
Set the pin as an
input port
(DDR1: bit8 = 0)
P11/INT1
Set the pin as an
input port
(DDR1: bit9 = 0)
P12/INT2
Set the pin as an
input port
(DDR1: bit10 = 0)
P13/INT3
Port 1 inputoutput/external
interrupt input/
resource inputoutput
P14/INT4
Set the pin as an
input port
(DDR1: bit11 = 0)
Selectable
CMOS output /
CMOS hysteresis
input
Provided
Set the pin as an
input port
(DDR1: bit12 = 0)
P15/INT5
Set the pin as an
input port
(DDR1: bit13 = 0)
P16/INT6
Set the pin as an
input port
(DDR1: bit14 = 0)
P51/INT7
430
I/O format
Port 5 inputoutput/external
interrupt input
Not
provided
FUJITSU MICROELECTRONICS LIMITED
Set the pin as an
input port
(DDR5: bit9 = 0)
CM44-10147-2E
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.3
MB90820B Series
■ Block Diagram of the DTP/External Interrupt Circuit Pins
Figure 17.3-1 Block diagram of the DTP/external interrupt circuit pins (INT0 to INT6)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
About 50 kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 17.3-2 Block diagram of the DTP/external interrupt circuit pins (INT7)
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
17.4
MB90820B Series
DTP/External Interrupt Circuit Registers
This section describes DTP/external interrupt circuit registers.
Figure 17.4-1 DTP/external interrupt circuit registers
DTP / Interrupt Cause Register
bit
Address: 000031H
Read/write ⇒
Initial value ⇒
15
ER7
R/W
X
14
ER6
R/W
X
13
ER5
R/W
X
12
ER4
R/W
X
11
ER3
R/W
X
10
ER2
R/W
X
9
ER1
R/W
X
8
ER0
R/W
X
6
EN6
R/W
0
5
EN5
R/W
0
4
EN4
R/W
0
3
EN3
R/W
0
2
EN2
R/W
0
1
EN1
R/W
0
0
EN0
R/W
0
13
LB6
R/W
0
12
LA6
R/W
0
11
LB5
R/W
0
10
LA5
R/W
0
9
LB4
R/W
0
8
LA4
R/W
0
5
LB2
R/W
0
4
LA2
R/W
0
3
LB1
R/W
0
2
LA1
R/W
0
1
LB0
R/W
0
0
LA0
R/W
0
EIRR
DTP / Interrupt Enable Register
bit
Address: 000030H
Read/write ⇒
Initial value ⇒
7
EN7
R/W
0
ENIR
Request Level Setting Register (Upper)
bit
Address: 000033H
Read/write ⇒
Initial value ⇒
15
LB7
R/W
0
14
LA7
R/W
0
ELVRH
Request Level Setting Register (Lower)
bit
Address: 000032H
Read/write ⇒
Initial value ⇒
432
7
LB3
R/W
0
6
LA3
R/W
0
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CM44-10147-2E
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
MB90820B Series
17.4.1
DTP/external interrupt cause register (EIRR)
The DTP/external interrupt cause register (EIRR) stores and clears interrupt causes.
■ DTP/External Interrupt Cause Register (EIRR)
Figure 17.4-2 DTP/external interrupt cause register (EIRR)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9
000031H
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
R/W R/W
R/W
R/W R/W R/W R/W
ER7
to
ER0
0
: Read/write
1
Table 17.4-1
bit8 bit7
bit0
(ENIR)
Initial value
XXXXXXXXB
R/W R/W
External interrupt request flag bit
Read
Write
No DTP/external interrupt is input
These bits are cleared
A DTP/external interrupt is input
No effect
Function description of each bit in the DTP/interrupt cause register (EIRR)
Bit name
Function
•
bit15
to
bit8
CM44-10147-2E
ER7 to ER0:
DTP/External
interrupt request flag
bits
Each of these bits is set to "1" if a signal with the edge or level
selected by bits LB7, LA7 to LB0, LA0 of the request level
setting register (ELVR) is input to the DTP/external external
interrupt pin (stores an interrupt cause).
• If these bits and corresponding bits EN7 to EN0 of the DTP/
external interrupt enable register (ENIR) are "1", an interrupt
request is output to the CPU.
• Writing "0" to these bits clears the bit. Writing "1" to these bits
does not change the bit value and has no effect on other bits.
Note:
If more than one external interrupt request output is enabled
(ENIR: EN7 to EN0 = 1), clear only the bit that caused the CPU
to accept an interrupt (bits ER7 to ER0 set to "1"). Do not clear
the other bits without a reason.
Reference:
When the extended intelligent I/O service (EI2OS) is activated,
the corresponding external interrupt request flag bit is
automatically cleared when the transfer of one data ends.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
17.4.2
MB90820B Series
DTP/external interrupt enable register (ENIR)
The DTP/external interrupt enable register (ENIR) enables and disables the output of
DTP/external interrupt requests of external peripherals to the CPU.
■ DTP/External Interrupt Interrupt Enable Register (ENIR)
Figure 17.4-3 DTP/external interrupt enable register (ENIR)
Address
000030H
bit15
bit8 bit7
(EIRR)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Read/write enabled
: Initial value
EN7
to
EN0
0
An external interrupt request is disabled.
1
An external interrupt request is enabled.
External interrupt request enable bits
Table 17.4-2 Function description of each bit in the DTP/external interrupt enable register
(ENIR)
Bit name
bit7
to
bit0
EN7 to EN0:
DTP/External
interrupt request
enable bits
Function
Each of these bits enables and disables the output of interrupt requests
to the CPU. If these bits and corresponding bits ER7 to ER0 of the
DTP/external interrupt cause register (EIRR) are "1", an interrupt
request is output to the CPU.
Reference:
- To use a DTP/external interrupt pin, write "0" to the
corresponding bit of the port direction register to set the pin as
an input port.
- The states of the DTP/external interrupt pins can be read
directly using the port data register regardless of the states of
external interrupt request enable bits.
- Bits ER7 to ER0 of the DTP/external interrupt cause register
(EIRR) are set to "1" if an interrupt cause is detected regardless
of the values of external interrupt request enable bits.
Notes:
• The value of a DTP/external interrupt request flag bits (EIRR:ER) is only valid if the corresponding
DTP/external interrupt request enable bit (ENIR:EN) is set to "1". When DTP/external interrupts
are disabled (ENIR:EN=0), it is possible for the DTP/external interrupt cause bit to be set
regardless of whether a DTP/external interrupt cause is present.
• Always clear the corresponding DTP/external interrupt request flag bits (EIRR:ER) immediately
before enabling DTP/external interrupts (ENIR:EN=1).
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
MB90820B Series
Table 17.4-3 Correspondence among the DTP/external interrupt pin, interrupt request flag
bit, and interrupt enable bit
DTP/external interrupt
pin
Interrupt number
DTP/external
interrupt request flag
bit
DTP/external interrupt
request enable bit
P51/INT7
#28 (1CH)
ER7
EN7
P16/INT6
#27 (1BH)
ER6
EN6
P15/INT5
#26 (1AH)
ER5
EN5
P14/INT4
#25 (19H)
ER4
EN4
ER3
EN3
ER2
EN2
ER1
EN1
ER0
EN0
P13/INT3
#22 (16H)
P12/INT2
P11/INT1
P10/INT0/DTTI
CM44-10147-2E
#20 (14H)
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
17.4.3
MB90820B Series
Request Level Setting Register (ELVR)
The request level setting register (ELVR) selects the level or edge of the signal input to
each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause.
■ Request Level Setting Register (ELVR)
Figure 17.4-4 Request level setting register (ELVR)
Address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Initial value
000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B
R/W:Read/write enabled
LB 7 to
LB 0
LA 7 to
LA 0
0
0
0
1
1
0
:Initial value
1
1
External interrupt request detection selection bits
L level is to be detected.
H level is to be detected.
Rising edge is to be detected.
Falling edge is to be detected.
Table 17.4-4 Function description of each bit in the request level setting register (ELVR)
Bit name
Function
•
bit15
to
bit0
LB7 to LB0,
LA7 to LA0:
Request detection
selection bits
Each of these bits selects the level or edge of the signal input to
the DTP/external interrupt pin to be detected as a DTP/external
interrupt cause.
• The external interrupt is selected from two types of level or edge,
and the EI2OS is selected from two types of level.
Reference:
If the selected detection signal is input to a DTP/external
interrupt pin, the DTP/external interrupt request flag bit is set to
"1" regardless of the settings of the DTP/external interrupt enable
register (ENIR:EN=0).
Note:
Always clear the corresponding DTP/external interrupt request flag bits (EIRR:ER) immediately
before enabling DTP/external interrupts (ENIR:EN=1).
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
MB90820B Series
Table 17.4-5 Correspondence between request level setting register (ELVR) and each
channel
DTP/external interrupt pin
Interrupt number
Bit name
P51/INT7
#28 (1CH)
LB7, LA7
P16/INT6
#27 (1BH)
LB6, LA6
P15/INT5
#26 (1AH)
LB5, LA5
P14/INT4
#25 (19H)
LB4, LA4
P13/INT3
LB3, LA3
#22 (16H)
P12/INT2
P11/INT1
LB1, LA1
P10/INT0/DTTI
CM44-10147-2E
LB2, LA2
#20 (14H)
LB0, LA0
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
MB90820B Series
Operation of the DTP/External Interrupt Circuit
17.5
The DTP/external interrupt circuit provides the external interrupt function and the DTP
function. This section describes the settings required for each function and the
operation of the circuit.
■ Setting the DTP/External Interrupt Circuit
Figure 17.5-1 shows the settings required to operate the DTP/external interrupt circuit.
Figure 17.5-1 DTP/external interrupt circuit
ICR08/ICR07
or
ICR05/ICR04
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
0
1
0
1
For the external interrupt
function
For the DTP function
EIRR / ENIR ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR
DDR1
DDR5
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
P16 P15 P14 P13 P12 P11 P10
∆
∆
∆
∆
∆
∆
∆
P51
∆
: Used bit
: Set the bit corresponding to the pin used to 1
∆ : Set the bit corresponding to the pin used to 0
0: Specifies 0
1: Specifies 1
● Setting procedure
Set the DTP/external interrupt circuit registers with the following procedure:
1. Set the general-purpose I/O ports that share pins with external interrupt inputs to input port.
2. Set the target bit of the DTP/interrupt enable register (ENIR) to disable interrupts.
3. Set the target bit of the request level setting register (ELVR).
4. Clear the target bit of the DTP/interrupt cause register (EIRR).
5. Set the target bit of the DTP/interrupt enable register (ENIR) to enable interrupts.
The procedure for setting the DTP/external interrupt circuit registers must start with disabling the output of
external interrupt requests (ENIR:EN7 to EN0 = 0). Before the output of DTP/external interrupt requests
can be enabled (ENIR:EN7 to EN0 = 1), the corresponding DTP/external interrupt request flag bits must be
cleared (ENIR:EN7 to EN0 = 0).
This is in order to avoid interrupt requests from being generated accidentally while the registers are being
set.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
MB90820B Series
● Switching between the external interrupt function and the DTP function
Switching between the external interrupt function and the DTP function is accomplished by the ISE bit of
the corresponding interrupt control register (ICR). If the ISE bit is "1", the extended intelligent I/O service
(EI2OS) is enabled and the circuit executes its DTP function. If it is "0", EI2OS is disabled and the circuit
executes the its external interrupt function.
Note :
If multiple interrupt requests are assigned to a single ICR register, the interrupt level (IL2 to IL0) is
common to all of the interrupt requests. As a rule, when one interrupt request uses EI2OS, the other
interrupt requests cannot use it.
■ Operation of the DTP/External Interrupt Circuit
Table 17.5-1 shows the control bits and interrupt causes of the DTP/external interrupt circuit.
Table 17.5-1 Control bit and interrupt cause of the DTP/external interrupt circuit
DTP/external interrupt circuit
Interrupt request flag bit
EIRR: ER7 to ER0
Interrupt request enable bit
ENIR: EN7 to EN0
Interrupt cause
Input of an effective edge or level to pin INT7 to INT0
If the interrupt request of the DTP/external intrrupt is outputted to the interrupt microcontroller and if the
ISE bit of the ICR is "0", the interrupt processing microprogram is executed. If it is "1", the extended
intelligent I/O service (EI2OS) microprogram is executed.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
MB90820B Series
Figure 17.5-2 shows the operation of the DTP/external interrupt circuit.
Figure 17.5-2 Operation of the DTP/external interrupt circuit
DTP/external interrupt circuit
Another request
Interrupt controller
CPU
ELVR
ICRYY
EIRR
IL
CMP
ICRXX
ENIR
CMP
ILM
Interrupt processing
microprogram
Cause
DTP handling routine
(EI2OS is started)
Generation of DTP/
external interrupt request
Transfer data between memory
and peripheral
Determined
the acceptance of interrupt
controller
Update descriptor
Descriptor
data counter
Determined
the acceptance of CPU
interrupt
=0
Interrupt processing routine
≠0
Set again or stop
Return from DTP handling routine
Start interrupt processing
microprogram
Return to CPU processing
1
ICR: ISE
0
Start external interrupt flag.
Processing. Clear interrupt flag.
Return from external interrupt
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
MB90820B Series
17.5.1
External Interrupt Function
The DTP/external interrupt circuit has an external interrupt function that generates an
interrupt request when a selected signal (edge or level) is input to a DTP/external
interrupt pin.
■ External Interrupt Function
• When the signal (edge or level) specified in the request level setting register (ELVR) is detected on a
DTP/external interrupt pin, the corresponding interrupt request flag bit in the DTP/external interrupt
cause register (EIRR: ER7 to ER0) is set to "1".
• If the interrupt request enable bit in the DTP/external interrupt enable register is set to enable (ENIR:
EN7 to EN0 = 1) when the corresponding interrupt request flag bit is set to "1", an interrupt request is
issued to the interrupt controller.
• The interrupt controller checks whether the interrupt has a higher priority than any other interrupt
request and, if so, generates an interrupt request.
• CPU compares the interrupt level mask register (PS:ILM) and the interrupt request level (ICR:IL) for
the processor status (PS), and if the interrupt request level is higher than ILM, and if the interrupt
request enable bit is set to enabled (PS:CCR:I=1), then the interrupt processing is carried out after the
current instruction has been finished to branch to the interrupt processing.
• The interrupt handler must set the corresponding DTP/external interrupt request flag bit to "0" to clear
the DTP/external interrupt request.
Notes :
• An ER bit is set to "1" if a DTP/external interrupt start cause is generated, regardless of the state
of the corresponding EN bit.
• When the interrupt processinsg is activated, the ER bit that caused the routine to be activated
must be cleared. If the ER bit is kept at "1", control cannot return from the interrupt. Only clear the
flag bit that caused the interrupt; do not clear the other bits without reason.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
17.5.2
MB90820B Series
DTP Function
The DTP/external interrupt circuit has a DTP function that detects a signal supplied to a
DTP/external interrupt pin from an external peripheral and activates the extended
intelligent I/O service.
■ Operation of the DTP Function
The DTP function detects a data transfer request signal from an external peripheral to automatically transfer
data between memory and the peripheral.
The extended intelligent I/O service (EI2OS) is activated by the external interrupt function using level
detection. The operation of the DTP function is the same as that of the external interrupt function up to the
point that the CPU accepts an interrupt request. If the operation of EI2OS is enabled (ICR:ISE = 1), EI2OS
is activated to start data transfer when an interrupt request is accepted. When the transfer of one data unit
ends, the descriptor is updated and the interrupt request flag bit is cleared to wait for the next request from
the pin. When the entire transfer using EI2OS is completed, control is transferred to the interrupt processing
routine.
The external peripheral must remove only the level of the data transfer request signal (DTP external
interrupt cause) within three machine cycles of the first transfer.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
MB90820B Series
Figure 17.5-3 Example of interfacing to the external peripheral
Rising edge request or H level request (ELVR: LB0, LA0 = 01B)
Input to the INTO pin
(DTP/external interrupt cause)
*Intelligent I/O service data transfer
Internal operation of
the CPU (microprogram)
Descriptor selection
and reading
from I/O register to memory.
Descriptor updating
Write address
Read address
Address bus pin
Data bus pin
Read data
Write data
Read signal
Write signal
*1
Internal bus
Register
External peripheral
Data, address bus
IRQ
Data
transfer
request
Write
opration*3
Read operation*1
DTP/external
interrupt cause*2
INT DTP/external
Interrupt
request
interrupt circuit
CPU
(EI2OS)
Internal
Memory
MB90820B series
*1, *2 : It must be removed within three machine cycles of transfer.
*3
: If the extended intelligent I/O service is in peripheral -> memory transfer mode.
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.6
17.6
MB90820B Series
Usage Notes on the DTP/External Interrupt Circuit
Notes on using the DTP/external interrupt is given below.
■ Usage Notes on the DTP/External Interrupt Circuit
● Conditions for external peripherals using the DTP function
To support the DTP function, external peripherals must be able to clear data transfer requests automatically
in response to transfer operations. If a transfer request is within three machine cycles of the start for
transfer, the DTP/external interrupt circuit interprets the request as another transfer request.
● Input polarities of external interrupts
• If the request level setting register (ELVR) is set so that an edge is detected, the pulse width must be at
least three machine cycles for the edge to be detected.
• If the register is set for level detection, and the level to be detected as an interrupt cause is input, cause
F/F in the DTP/external interrupt cause register (EIRR) is set to "1" to store the cause, as shown in
Figure 17.6-1. Even if the cause is retained and the DTP/external interrupt request is removed, the
request to the interrupt controller remains active provided the output of interrupt requests is enabled
(ENIR:EN=1). Thus, to cancel the request to the interrupt controller, clear the external interrupt request
flag bit (ENIR:ER) and cause F/F, as shown in Figure 17.6-2.
Figure 17.6-1 Clearing the cause retention circuit when a level is specified
DTP/external
interrupt cause
DTP/interrupt input
detection circuit
Cause flip-flop
(in the EIRR register)
Enable gate
To interrupt
controller
(interrupt
request)
The cause is stored until the register is cleared
Figure 17.6-2 DTP/external interrupt cause and interrupt request when the output
of interrupt requests is enabled
DTP/external interrupt
cause (when the H level
is detected)
"H" level
Removal of the interrupt cause
Interrupt request to the
interrupt controller
Request becomes inactive when
cause flip-flop is cleared
444
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CM44-10147-2E
MB90820B Series
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.6
● Notes about interrupts
When the external interrupt function is used, control cannot return from the interrupt processing if the DTP/
external interrupt request flag bit is "1" (EIRR:ER) and the output of DTP/external interrupt requests is
enabled (ENIR:EN=1). In the interrupt processing routine, the DTP/external external interrupt request flag
bit must be set to "0". (EIRR:ER). For level detection in the request level setting register, the DTP/external
interrupt request flag bit is set again as soon as it is cleared (EIRR:ER=0) if the level assumed as an
interrupt cause continues to be input. Either disable the output of DTP/external interrupt requests
(ENIR:EN=0) or remove the interrupt cause, if required.
CM44-10147-2E
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CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.6
446
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MB90820B Series
CM44-10147-2E
CHAPTER 18
8/10-Bit A/D Converter
This chapter explains the function and operation of the
8/10-bit A/D converter.
18.1 Overview of 8/10-Bit A/D Converter
18.2 Block Diagram of 8/10-Bit A/D Converter
18.3 Configuration of 8/10-Bit A/D Converter
18.4 Interrupt of 8/10-Bit A/D Converter
18.5 Operation of 8/10-Bit A/D Converter
18.6 Precautions for Using the 8/10-Bit A/D Converter
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CHAPTER 18 8/10-Bit A/D Converter
18.1
18.1
MB90820B Series
Overview of 8/10-Bit A/D Converter
The 8/10-bit A/D converter converts analog input voltages to 8-bit or 10-bit digital values
by means of the RC sequential compare conversion.
• The input signal is selected from up to 16 channels analog input pins.
• The activation trigger can be selected from software trigger, internal timer output, or
external trigger.
■ Features of 8/10-bit A/D converter
The 8/10-bit A/D converter converts analog input voltages to 8-bit or 10-bit digital values (A/D
conversion).
The 8/10-bit A/D converter has the following functions:
• The A/D conversion time is 1.9µs * minimum per channel including the sampling time.
• The sampling time is 0.5µs * minimum per channel.
• The conversion method is RC sequential compare conversion with sample and hold circuit.
• The resolution can be set to 8-bit or 10-bit.
• Up to 16 channels can be used for the analog input pin.
• Interrupt requests can be generated by storing the A/D conversion result in the A/D data register.
• The interrupt request can start EI2OS.
• The activation can be selected from software or internal timer output (16-bit reload timer 1, 16-bit freerun timer zero detection, or compare clear).
*: When operating with 24-MHz machine clock frequency and AVCC ≥ 4.5V
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CHAPTER 18 8/10-Bit A/D Converter
18.1
MB90820B Series
■ Conversion Mode of 8/10-bit A/D Converter
The 8/10-Bit A/D converter has the following conversion modes.
Table 18.1-1 Conversion Mode of 8/10-Bit A/D Converter
Conversion mode
CM44-10147-2E
Description
Single mode
A/D conversion is done from the start channel to the end channel sequential and
stopped after the conversion of the end channel.
Continuous mode
A/D conversion is done from the start channel to the end channel sequential and
returned to the start channel after the conversion of the end channel. Then A/D
conversion is repeated.
Stop mode
A/D conversion is done for each one channel and stopped after the conversion of
the channel. A/D conversion is returned to the start channel after the conversion
of the end channel. Then the process of conversion and stop is repeated.
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CHAPTER 18 8/10-Bit A/D Converter
18.2
18.2
MB90820B Series
Block Diagram of 8/10-Bit A/D Converter
The 8/10-bit A/D converter is configured with the following blocks.
■ Block diagram of 8/10-bit A/D converter
Figure 18.2-1 Block Diagram of 8/10-Bit A/D Converter
Interrupt request
A/D control
status
register
BUSY INT INTE PAUS STS1 STS0 STRT
MD1 MD0 S10
(ADCS0/
ADCS1)
2
16-bit
free-run timer
zero detection
IRQZF
TO1
From
16-bit reload timer 1
Start
selector
Software
start
Reserved
2
Sample and
hold circuit
AN0 to AN7
AN15 to AN8
Internal data bus
φ
Comparator
Control circuit
Analog
channel
selector
AVR
AVcc
AVss
D/A converter
Sequential compare
circuit SAR
3
3
A/D data
register
(ADCR0/
ADCR1)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Decoder
10
A/D setting
register
(ADSR0/ ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0
ADSR1)
TO
: Internal timer output
: Not specified
Reserved : Always set to 0
φ
: Machine clock
450
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CM44-10147-2E
CHAPTER 18 8/10-Bit A/D Converter
18.2
MB90820B Series
● Pins detail in the block diagram
Table 17.2-1 shows the actual pin name and the interrupt request number of the 8/10-bit A/D converter.
Table 18.2-1 Pin Name and Interrupt Request Number in Block Diagram
Pin name / interrupt request number in the block diagram
Actual pin name / interrupt request number
TO1
Internal timer output
16-bit reload timer 1 output
IRQZF
Internal timer output
16-bit free-run timer zero detection or compare
clear
AN0 to AN7
Analog input pins ch.0 to ch.7
P60/AN0 to P67/AN7
AN8 to AN15
Analog input pins ch.8 to ch.15
P70/AN8 to P77/AN15
AVR
Vref input pin
AVR
AVCC
VCC input pin
AVCC
AVSS
VSS input pin
AVSS
Interrupt request output
Interrupt request output
#29 (1DH)
● A/D control status register (ADCS)
The A/D control status register activates the A/D conversion with a software, selects the activation trigger
of A/D conversion, selects the conversion mode, enables/disables the interrupt request, confirms/clears the
interrupt request flag, suspends the A/D conversion operation, confirms the ongoing conversion status, and
selects the resolution.
● Sequential compare circuit (SAR)
The sequential compare circuit performs the sequential comparison for each one bit and stores the result.
The A/D conversion result in this circuit is cleared when the next A/D conversion starts.
● A/D data register (ADCR)
The A/D conversion result is stored in the sequential compare circuit for each bit, and stored in this A/D
data register when the A/D conversion finishes with the defined conversion results. The A/D conversion
results can be read by this register.
● A/D setting register (ADSR)
The A/D setting register sets the start channel and the end channel of A/D conversion, the compare time of
A/D conversion, and the sampling time of A/D conversion.
● Activation selector
The activation selector selects the activation trigger of A/D conversion. The activation trigger can be set
from the internal timer output or the external pin input.
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CHAPTER 18 8/10-Bit A/D Converter
18.2
MB90820B Series
● Decoder
The decoder selects the analog input pins for A/D conversion from the A/D conversion start channel bit
(ADSR: ANS3 to ANS0) and the A/D conversion end channel bit (ADSR: ANE3 to ANE0) selected by the
A/D setting register.
● Analog channel selector
The analog channel selector selects the pins for A/D conversion from the 16 channel analog input pins
according to the signal from decoder.
● Sample and hold circuit
The sample and hold circuit holds the input voltage selected by the analog channel selector. Hold of the
input voltage just after starting A/D conversion enables the conversion without an effect of input voltage
variation.
● D/A converter
The D/A converter generates the reference voltage to compare it to the input voltage held in the sample and
hold circuit.
● Comparator
The comparator compares the input voltage held in the sample and hold circuit with the output voltage from
D/A converter to determine the large/small.
● Control circuit
The control circuit defines the A/D conversion value with the large/small signal from the comparator, and
stores the conversion result data in the A/D data register after the definition of the conversion result. An
interrupt occurs if the interrupt request is enabled.
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CM44-10147-2E
CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
18.3
Configuration of 8/10-Bit A/D Converter
This section shows pins, registers, and interrupt factors of the A/D converter.
■ Pins of 8/10-bit A/D converter
Pins of the 8/10-bit A/D converter are also used as general purpose I/O ports. Table 17.3-1 shows the pin
functions and the setting for 8/10-bit A/D converter.
Table 18.3-1 8/10-Bit A/D Converter Pins
Channel
Pin name
Channel 0
P60/AN0
Channel 1
P61/AN1
Channel 2
P62/AN2
Channel 3
P63/AN3
Channel 4
P64/AN4
Channel 5
P65/AN5
Channel 6
P66/AN6
Channel 7
P67/AN7
Channel 8
P70/DA0/AN8
Channel 9
P71/DA1/AN9
Channel 10
P72/SIN1/AN10
Channel 11
P73/SOT1/AN11
Channel 12
P74/SCK1/AN12
Channel 13
P75/FRCK/AN13
Channel 14
P76/IN0/AN14
Channel 15
P77/IN1/AN15
CM44-10147-2E
Pin function
General purpose I/O port /
Analog input
Setting for 8/10-bit A/D converter
Analog signal input enabled (ADER0: set the
bits corresponding to ADE7 to ADE0 to "1")
General purpose I/O port /
Analog input /
D/A converter output
General purpose I/O port /
Analog input /
UART1 I/O
Analog signal input enabled (ADER1: set the
bits corresponding to ADE15 to ADE8 to "1")
General purpose I/O port /
Analog input /
Free-run timer clock input
General purpose I/O port /
Analog input /
External interrupt input
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
■ Registers of the 8/10-bit A/D converter and their initial value
Figure 18.3-1 Registers of the 8/10-Bit A/D Converter and Their Initial Value
A/D control status registers high order ADCS1
15
14
13
12
BUSY INT
R/W
11
10
9
8
Initial value
0000000XB
INTE PAUS STS1 STS0 STRT
R/W
R/W
R/W
R/W
R/W
4
3
2
A/D control status registers low order ADCS0
7
5
6
W
1
0
MD1 MD0
S10
Reserved
R/W
R/W
R/W
R/W
Data registers high order ADCR1
15
14
Data registers low order ADCR0
7
13
12
11
10
9
8
D9
R
D8
R
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
ST2
R/W
ST1
R/W
A/D setting registers low order ADSR0
7
6
12
ST0
R/W
R/W
5
R/W
10
CT2 CT1
R/W R/W
ANS2 ANS1 ANS0
R/W
11
4
Reserved
R/W
3
9
8
CT0
R/W
Reserved
2
1
R/W
ANS3
R/W R/W
R/W
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
0
ANE3 ANE2 ANE1 ANE0
R/W
000XXXX0B
Initial value
D7
A/D setting registers high order ADSR1
15
14
13
Initial value
00000000B
Initial value
00000000B
R/W
R/W : Read and write
R
: Read only
W : Write only
: Undefined bit
X : Undefined
454
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CM44-10147-2E
CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
18.3.1
A/D Control Status Registers High Order (ADCS1)
The following functions can be set by the A/D control status registers high order (ADCS1).
• Activation of the A/D conversion with software
• Selection of the activation trigger for the A/D conversion function
• Enabling and disabling the interrupt request by storing the A/D conversion results in
the A/D data register
• Confirmation and clearing the interrupt request by storing the A/D conversion results
in the A/D data register
• Suspend of the A/D conversion and confirmation of ongoing conversion status
■ A/D control status registers high order (ADCS1)
Figure 18.3-2 A/D Control Status Registers High Order (ADCS1)
15
14
13
12
11
10
9
BUSY INT INTE PAUS STS1 STS0 STRT
R/W R/W R/W R/W R/W R/W
W
8
Initial value
-
0000000X B
bit8
-
Undefined bit
Read value is always 1
bit9
STRT
0
1
A/D conversion software activation bit
Not start A/D conversion
Start A/D conversion
bit11 bit10
A/D conversion activation trigger select bit
STS1 STS0
0
0 By software
0
1 By software, 16-bit free-run timer zero detection,
or compare clear
1
0
By software or 16-bit reload timer 1
1
1
By software, 16-bit free-run timer zero detection,
or 16-bit reload timer
bit12
PAUS
Pause flag bit
(Enabled only when EI2OS is used)
Read
0
1
bit13
INTE
0
1
Conversion not paused
Conversion paused
Write
Clear this bit to "0"
Disable the setting
Interrupt request enable bit
Interrupt request disabled
Interrupt request enabled
bit14
INT
0
1
Interrupt request flag bit
Read
A/D conversion not ends
Write
Clear this bit to "0"
A/D conversion ends
No effect
bit15
BUSY
R/W
W
X
CM44-10147-2E
: Read and write
: Write only
: Undefined bit
: Undefined value
: Initial value
0
1
A/D conversion operation flag bit
Read
A/D conversion ends (not started)
Write
End forcibly the A/D conversion
A/D conversion is ongoing
No effect
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
Table 18.3-2 Function of A/D Control Status Register High Order (ADCS1) (1 / 3)
Bit name
BUSY:A/D
conversion
operation flag bit
The 8/10-bit A/D conversion stops forcibly.
When read, this bit indicates an operation or a stop of the 8/10-bit A/D converter.
Set to "0": 8/10-bit A/D converter stops forcibly.
Set to "1": No effect
When read: "1" is read when the 8/10-bit A/D converter is ongoing, "0" when stopped.
"1" is read in "stop status" in the stop mode.
Notes:
• "1" is read from this bit when an RMW instruction is used.
• In the single mode, this bit is cleared when A/D conversion ends.
• In the continuous or stop mode, this bit is not cleared until writing "0" to this bit to
stop the A/D conversion.
• Do not perform the forced stop (BUSY = 0) and the starting of the A/D conversion
concurrently (using software (STRT = 1), or timer).
INT:Interrupt
request flag bit
This bit indicates that an interrupt request is generated.
• After the A/D conversion, when the converted data is stored in A/D data register
(ADCR), INT bit is set to "1".
• With the interrupt request enabled (INTE=1), if the interrupt request flag bit is set
(INT=1), an interrupt request is generated.
• This bit is cleared when "0" is written. This bit is automatically cleared after EI2OS
data transmission of A/D conversion result.
Set to "0": Cleared
Set to "1": No effect
Note:
• "1" is read from this bit when an RMW instruction is used.
INTE:Interrupt
request enable bit
This bit sets enabling/disabling of interrupts.
• With the interrupt request enabled (INTE=1), if the interrupt request flag bit is set
(INT=1), an interrupt request is generated.
Note:
When using EI2OS to transmit the A/D converted result, set this bit to "1".
bit 15
bit 14
bit 13
456
Function
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
MB90820B Series
CHAPTER 18 8/10-Bit A/D Converter
18.3
Table 18.3-2 Function of A/D Control Status Register High Order (ADCS1) (2 / 3)
Bit name
PAUS:
Pause flag bit
bit 12
CM44-10147-2E
Function
PAUS bit indicates that the A/D conversion data protection function is set off. PAUS bit is
valid only when the interrupt request output is set enabled (ADCS: INTE=1).
A/D conversion data protection function is set off:
set to "1"
When set to "0": Cleared to "0"
When set to "1": Set to "1"
• When the interrupt request output is enabled (ADCS: INTE=1) and A/D conversion is
performed, after one A/D conversion the interrupt request flag bit (ADCS: INT) is set
and the interrupt request is generated simultaneously. If the next A/D conversion
finishes with the interrupt request flag bit (ADCS:INT) not cleared, the A/D conversion
pauses to prevent previous data from being overwritten (A/D conversion data
protection function).
PAUS bit is set to "1" when the A/D conversion pauses.
• When interrupt request flag bit (ADCS:INT) is cleared, 8/10-bit A/D converter returns
from the pause state and resumes the A/D conversion.
• Interrupt request flag bit (ADCS:INT) is cleared by writing "0". When EI2OS is used to
transmit the A/D converted result from A/D resister, the interrupt request flag bit
(ADCS:INT) is cleared by EI2OS.
Notes:
• See "18.5.5 A/D Converted Data Protection Function1" for the A/D conversion data
protection function.
• PAUS bit is not cleared automatically even after returning from the pause state. Write
"0" to clear PAUS bit.
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
Table 18.3-2 Function of A/D Control Status Register High Order (ADCS1) (3 / 3)
Bit name
STS1, STS0:
A/D conversion
activation trigger
select bits
STRT:
A/D conversion
software activation
bit
bit 9
458
This bit selects the activation trigger of 8/10-bit A/D converter.
• 00B: By software
• 01B: By 16-bit free-run timer zero detection or compare clear / software
• 10B: By 16-bit reload timer / software
• 11B: 16 bit free-run timer zero detection or compare clear / 16-bit reload timer /
software
Notes:
• With the 16-bit free-run timer zero detection or compare clear selected (01B or 11B),
when the 16-bit free-run timer zero detection, A/D conversion starts.
• With the 16-bit reload timer selected (10B or 11B), when the 16-bit reload timer 1 is
"1", A/D conversion starts.
Notes:
• When multiple activation triggers are set, (other than that both STS1 and STS0 are
"00B"), 8/10-bit A/D converter starts with the activation trigger generated first.
• Change of the activation trigger setting should be performed when the peripheral
functions which generate an activation trigger stops (trigger is inactive)
bit 11,
bit 10
bit 8
Function
Undefined bit
This bit activates the 8/10-bit A/D converter by software.
Set to "1": 8/10-bit A/D converter is activated.
• When the A/D conversion pauses in stop mode, the A/D conversion is resumed by
writing "1" to STRT bit.
Set to "0": No effect
Notes:
• "0" is read from this bit when an RMW instruction is used.
• Not the written value, bit "1" is read from this bit when any instructions other than
RMW are used.
• Forced end of the 8/10-bit A/D converter (BUSY=0) and software activation
(STRT=1) must not be performed simultaneously.
• Read: Always "1" is read.
• Write: No effect
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CM44-10147-2E
CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
18.3.2
A/D Control Status Register Low Order (ADCS0)
The following functions can be set by the A/D control status registers low order
(ADCS0).
• Select of the A/D conversion mode
• Select of start channel and end channel of the A/D conversion
■ A/D control status registers low order (ADCS0)
Figure 18.3-3 A/D Control Status Register Low Order (ADCS0)
bit
7
6
5
4
3
2
1
0
MD1 MD0 S10
-
-
-
-
Reserved
R/W R/W R/W
-
-
-
-
Initial value
0 0 0 X X X X 0B
R/W
bit0
Reserved bit
Always write "0" in this bit
Reserved
0
bit5
S10
0
1
R/W : Read and write
: Undefined bit
X : Undefined value
: Initial value
CM44-10147-2E
Resolution select bit
Set the resolution of the A/D conversion to 10-bit
Set the resolution of the A/D conversion to 8-bit
bit7 bit6
MD1 MD0
0
0
0
1
1
0
1
1
A/D conversion mode select bit
Single conversion mode 1
Single conversion mode 2
Continuous conversion mode
Stop conversion mode
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
Table 18.3-3 Function of A/D Control Status Register Low Order (ADCS0)
Bit name
MD1, MD0:
A/D conversion
mode selection bits
These bits set the A/D conversion mode.
For detailed usage of each mode, see 17.5 8/10-Bit A/D Converter Operation.
Single conversion mode 1 and single conversion mode 2:
• A/D conversion is continuously performed for analog inputs from the start channel
(ADSR0/1: ANS3 to ANS0) to the end channel (ADSR0/1: ANE3 to ANE0).
• After the A/D conversion of the end channel, the A/D conversion stops.
• For the difference between the single conversion 1 and the single conversion 2, see
17.5 8/10-Bit A/D Converter Operation.
Continuous conversion mode:
• A/D conversion is continuously performed for analog inputs from the start channel
(ADSR0/1: ANS3 to ANS0) to the end channel (ADSR0/1: ANE3 to ANE0).
• After the A/D conversion of the end channel, the A/D conversion continues repeatedly
from analog input of the start channel.
Stop conversion mode:
• A/D conversion is performed from the start channel (ADSR0/1: ANS3 to ANS0). After
the A/D conversion for one channel, the A/D conversion stops. The next A/D
conversion starts when the activation trigger is input during the A/D conversion stop
state.
• After the A/D conversion of the end channel, the A/D conversion stops. When the
activation trigger is input during the A/D conversion stop state, the A/D conversion
returns to the start channel and continues.
Note:
• Change of the conversion mode should be performed when the conversion is in the
stop state before start.
S10:
Resolution select
bit
This bit selects the resolution of 8/10-bit A/D converter.
Set to "0": The resolution of A/D conversion is set to 10 bits of A/D conversion data bit
D9 to D0.
Set to "1": The resolution of A/D conversion is set to 8 bits of A/D conversion data bit
D7 to D0.
Note:
Any change of S10 bit should be done in stopped state of A/D conversion, before the
conversion starts. If S10 bit is changed after the A/D conversion starts, the converted
result stored in the A/D conversion data bits (D9 to D0) become void.
bit 7,
bit 6
bit 5
460
Function
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CM44-10147-2E
CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
18.3.3
A/D Data Register (ADCR0/ADCR1)
The A/D data register (ADCR0, ADCR1) is used to store digital values generated as a
result of conversion. ADCR0 stores lower 8 bits, and ADCR1 stores most significant 2
bits of the conversion result. These registers' values are rewritten every time
conversion ends. Normally, the last converted value is stored in these registers' bits.
■ A/D data register (ADCR0/ADCR1)
Figure 18.3-4 A/D Data Register (ADCR0/ADCR1)
A/D data register (Upper)
ADCR1
A/D data register (lower)
ADCR0
15
14
13
12
11
10
9
8
Initial value
-
-
-
-
-
-
D9
D8
XXXXXXXXB
R
R
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
R : Read only
X : Undefined value
- : Undefined bit
Table 18.3-4 Function of A/D Data Register (ADCR0/ADCR1)
Bit name
bit 15
to
bit 10
Function
Undefined bits
Reading these bits always reads "1".
D9 to D0:
A/D conversion
data bits
These bits store the A/D conversion result.
When the 10-bit mode is established (S10 bit of ADCS0 is "0"):
Converted data is stored in 10 bits of D9 to D0.
When the 8-bit mode is established (S10 bit of ADCS0 is "1"):
Converted data is stored in 8 bits of D7 to D0. In this case, reading D9 to D8 always
returns "1".
bit 9
to
bit 0
Notes:
• Do not write in these registers.
• To read the converted-data in the A/D conversion data bits (D9 to D0), use a word
instruction (MOVW).
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CHAPTER 18 8/10-Bit A/D Converter
18.3
18.3.4
MB90820B Series
A/D Setting Register (ADSR0/ADSR1)
The A/D setting register (ADSR0/ADSR1) is used for:
• A/D conversion time (sampling time and compare time) setting
• Sampling channels (start channel and end channel) setting
• Current sampling channel indication
■ A/D setting register (ADSR0/ADSR1)
Figure 18.3-5 A/D Setting Register (ADSR0/ADSR1)
bit 15
14
13
12
11
10
9
7
8
6
5
4
3
2
1
0
Initial value
ST2 ST1 ST0 CT2 CT1 CT0 Reserved ANS3 ANS2 ANS1 ANS0 Reserved ANE3 ANE2 ANE1 ANE0 0000000000000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit3 to bit0
ANE3 to ANE0
1111B to 0000B
(Initial value: 0000B)
bit4
Reserved
0
A/D conversion end channel select bit
Pin AN15 to Pin AN0
Reserved bit
Always write "0" in this bit
bit8 to bit5
A/D conversion start channel select bit
ANS3 to ANS0
Write
(not started)
Reading
during
conversion
Reading in the
pause state in
stop mode
1111B to 0000B
Pin AN15 to
Pin AN0
Channel number
of current
conversion
Channel number
of the last
conversion
(Initial value: 0000B)
bit9
Reserved
0
Reserved bit
Always write "0" in this bit
bit12 bit11 bit10
CT2 CT1 CT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
bit15 bit14 bit13
ST2 ST1 ST0
R/W
φ
462
: Read and write
: Machine clock
: Initial value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Compare time selection bit
22/φ (φ =20MHz: 1.1 µs)
33/ φ (φ =24MHz: 1.4 µs)
44/ φ (φ =24MHz: 1.8 µs)
66/ φ (φ =24MHz: 2.75 µs)
88/ φ (φ = 8MHz:11.0 µs)
132/ φ (φ =16MHz: 8.25 µs)
176/ φ (φ =20MHz: 8.8 µs)
264/ φ (φ =24MHz:11.0 µs)
Sampling time selection bit
4/ φ (φ = 8MHz:0.5 µs)
6/ φ (φ = 8MHz:0.75 µs)
8/ φ (φ =16MHz:0.5 µs)
12/ φ (φ =24MHz:0.5 µs)
24/ φ (φ = 8MHz:3.0 µs)
36/ φ (φ =16MHz:2.25 µs)
48/ φ (φ =16MHz:3.0 µs)
128/ φ (φ =24MHz:5.3 µs)
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MB90820B Series
Table 18.3-5 Function of A/D Setting register (ADSR0/ADSR1) (1 / 2)
Bit name
bit 15
to
bit 13
bit 12
to
bit 10
Function
ST2, ST1, ST0:
Sampling time
selection bits
These bits set the sampling time of the A/D conversion.
• These bits set the time from start of the A/D conversion to sampling and holding the
input analog voltage in the sample and hold circuit.
• See the table 17.3-6 for the setting of these bits.
CT2, CT1, CT0:
Compare time
selection bits
These bits set the compare time of the A/D conversion.
• Set the time from start of the A/D conversion to storing the analog input into the data
bits (D9 to D0).
• See the table 17.3-7 for the setting of these bits.
ANS3 to ANS0:
A/D conversion
start channel
selection bits
These bits set the start channel of the A/D conversion. When the A/D conversion is
ongoing, read values of these bits indicate the channel number of the current conversion.
When the A/D conversion stops or after the A/D conversion ends, these bits indicates the
channel number of the last A/D conversion.
Even if these bits are set to any values, read values indicates not the set value, but the
channel number of the last A/D conversion until the A/D conversion starts. When these
bits are reset, return to "0000B".
Start channel < end channel:
A/D conversion starts from the channel set in the A/D conversion start channel
selection bits (ANS3 to ANS0), and ends at the channel set in the A/D conversion end
channel selection bits (ANE3 to ANE 0).
Start channel = end channel:
The A/D conversion is performed for only one channel set in the A/D conversion start
channel selection bits (ANS3 to ANS0=NE3 to ANE 0).
In the continuous conversion mode or the stop mode:
After the A/D conversion of the channel set in the A/D conversion end channel
selection bits (ANE3 to ANE 0), the A/D conversion returns to the channel set in the A/D
conversion start channel selection bits (ANS3 to ANS0).
Reading these bits (in other than the stop mode):
The channel number (15 to 0) of the current A/D conversion is read.
Reading these bits (in the stop mode):
The last channel number just before the stop is read.
Notes:
• The number of the start channel must not be larger than the number of the end
channel.
• Do not set the A/D conversion start channel selection bits (ANS3 to ANS 0) during
the A/D conversion.
• Writing in these bits should be performed with Word access. If with Byte writing or
bit control, the A/D conversion may start from an unintended channel.
bit 8
to
bit 5
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Table 18.3-5 Function of A/D Setting register (ADSR0/ADSR1) (2 / 2)
Bit name
ANE3 to ANE0:
A/D conversion
end channel
selection bits
bit 3
to
bit 0
464
Function
These bits set the end channel of the A/D conversion.
Start channel < end channel:
A/D conversion starts from the channel set in the A/D conversion start channel
selection bits (ANS3 to ANS0), and ends at the channel set in the A/D conversion end
channel selection bits (ANE3 to ANE 0).
Start channel = end channel:
The A/D conversion is performed for only one channel set in the A/D conversion start
channel selection bits (ANS3 to ANS0=ANE3 to ANE 0).
In the continuous conversion mode or the stop mode:
After the A/D conversion of the channel set in the A/D conversion end channel
selection bits (ANE3 to ANE 0), the A/D conversion returns to the channel set in the A/D
conversion start channel selection bits (ANS3 to ANS0).
Notes:
• The number of the start channel must not be larger than the number of the end
channel.
• Do not set the A/D conversion end channel selection bits (ANE3 to ANE0) during
the A/D conversion.
• After setting of the A/D conversion start channel selection bits (ANS3, ANS2,
ANS1, ANS0), the sampling time selection bits (ST2, ST1, ST0), the compare time
selection bits (CT2, CT1, CT0), and the A/D conversion end channel selection bits
(ANE3, ANE2, ANE1, ANE0) should not be set using the read modify write
instructions. Because reading of ANS3, ANS2, ANS1 and ANS0 are the last
conversion channel until the A/D conversion starts, if ST2, ST1, ST0, and CT2, CT1,
CT0, and ANE3, ANE2, ANE1, ANE0 are set using the read modify instructions
after setting of ANS3, ANS2, ANS1, and ANS0, the values of ANS3, ANS2, ANS1,
and ANS0 may be overwritten.
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
■ Sampling time setting (ST2 to ST0)
Table 18.3-6 Reference between Bits ST2 to ST0 and Sampling Time
ST2
ST1
ST0
Sampling time setting
Setting example (φ: internal operating frequency)
0
0
0
4 machine cycles
φ= 8MHz: 0.5µs
0
0
1
6 machine cycles
φ= 8MHz: 0.75µs
0
1
0
8 machine cycles
φ= 16MHz: 0.5µs
0
1
1
12 machine cycles
φ= 24MHz: 0.5µs
1
0
0
24 machine cycles
φ= 8MHz: 3µs
1
0
1
36 machine cycles
φ= 16MHz: 2.25µs
1
1
0
48 machine cycles
φ= 16MHz: 3.0µs
1
1
1
128 machine cycles
φ= 24MHz: 5.3µs
The sampling time needs to be set according to the driving impedance Rext for the analog input pin. When
the following condition is not met, the A/D conversion precision is not assured:
• When Rext is 1.5 kΩ or less:
• 4.5V ≤ AVCC < 5.5V: Set the sampling time so as to be 0.5µs or more.
• 4.0V ≤ AVCC < 4.5V: Set the sampling time so as to be 1.2µs or more.
• When Rext is more than 1.5 kΩ: Set the sampling time Tsamp to the value obtained using the following
expression or more:
Flash memories
• 4.5V ≤ AVCC < 5.5V: Tsamp = (2kΩ+Rext) × 16pF × 7
• 4.0V ≤ AVCC < 4.5V: Tsamp = (8.2kΩ+Rext) × 16pF × 7
Mask ROMs
• 4.5V ≤ AVCC < 5.5V: Tsamp = (2kΩ+Rext) × 14.4pF × 7
• 4.0V ≤ AVCC < 4.5V: Tsamp = (8.2kΩ+Rext) × 14.4pF × 7
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MB90820B Series
■ Compare time setting (CT2 to CT0)
Table 18.3-7 Reference between Bits CT2 to CT0 and Compare Time
CT2
CT1
CT0
Compare time setting
Setting example (φ: internal operating frequency)
0
0
0
22 machine cycles
φ= 20MHz: 1.1µs
0
0
1
33 machine cycles
φ= 24MHz: 1.4µs
0
1
0
44 machine cycles
φ= 24MHz: 1.8µs
0
1
1
66 machine cycles
φ= 24MHz: 2.75µs
1
0
0
88 machine cycles
φ= 8MHz: 11.0µs
1
0
1
132 machine cycles
φ= 16MHz: 8.25µs
1
1
0
176 machine cycles
φ= 20MHz: 8.8µs
1
1
1
264 machine cycles
φ= 24MHz: 11.0µs
The compare time needs to be set according to the analog power AVCC. When the following condition is
not met, the A/D conversion precision is not assured:
• 4.5V ≤ AVCC < 5.5V: Set the compare time so as to be 1.00µs or more.
• 4.0V ≤ AVCC < 4.5V: Set the compare time so as to be 2.00µs or more.
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CHAPTER 18 8/10-Bit A/D Converter
18.3
MB90820B Series
18.3.5
Analog Input Enable Resister (ADER0/ADER1)
This register enables or disables the analog input pins used in the 8/10-bit A/D
converter.
■ Analog input enable registers
Figure 18.3-6 Analog Input Enable Register (ADER0/ADER1)
7
6
5
4
3
2
1
0
Initial value
ADER1 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 11111111B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 to bit0
ADE15 to ADE8 Analog input enable bits 7 to 0 (AN15 to AN8)
Disables the analog input
0
Enables the analog input
1
7
6
5
4
3
2
1
0
Initial value
ADER0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Read and Write
: Initial value
bit7 to bit0
ADE7 to ADE0
0
1
Analog input enable bits 7 to 0 (AN7 to AN0)
Disables the analog input
Enables the analog input
Table 18.3-8 Function of Port 6 Analog Input Enable Register (ADER1)
Bit name
bit7
to
bit0
ADE15 to ADE8:
Analog input
enable bits 7 to 0
Function
These bits enable or disable the analog input of the A/D conversion analog input pins
AN15 to AN8 on port 5.
When set to "0": Disables the analog input.
When set to "1": Enables the analog input.
Table 18.3-9 Function of Port 6 Analog Input Enable Register (ADER0)
Bit name
bit7
to
bit0
ADE7 to ADE0:
Analog input
enable bits 7 to 0
Function
These bits enable or disable the analog input of the A/D conversion analog input pins AN7
to AN0 on port 6.
When set to "0": Disables the analog input.
When set to "1": Enables the analog input.
Notes:
• When used as an analog input for the A/D converter, the bits of corresponding analog input
enable register (ADER0/ADER1) should be set to "1" to establish the analog input.
• For analog signal input, do not set the analog input pin so as to ADEx=0. Always set ADEx to "1".
• Every analog input pin is used as both general purpose I/O port and peripheral function I/O. Pins
set to ADEx= 1 are forcibly established as analog input pins regardless of the port direction
registers (DDR6/DDR7) and I/O settings of the peripheral functions. In this case, the pins cannot
be used as others.
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CHAPTER 18 8/10-Bit A/D Converter
18.4
18.4
MB90820B Series
Interrupt of 8/10-Bit A/D Converter
For the 8/10-bit A/D converter, after the A/D conversion ends and the converted result is
stored in the A/D data register (ADCR), an interrupt request is generated. In this case,
the extended intelligent I/O service (EI2OS) can be used.
■ Interrupt of A/D converter
After the A/D conversion of the analog input voltage ends and the A/D converted result is stored in the A/D
data register (ADCR), the interrupt request flag bit (ADCS: INT) of the A/D control status register is set to
"1". If the interrupt request flag bit is set (ADCS: INT=1) with the interrupt request output enabled (ADCS:
INTE=1), an interrupt request is generated.
■ Interrupt of 8/10-bit A/D converter and EI2OS
Reference:
For the interrupt number, interrupt control register, and interrupt vector address, see Chapter 6
Interrupt.
■ EI2OS of 8/10-bit A/D converter
For 8/10-bit A/D converter, the A/D converted result can be transmitted from the A/D data register
(ADCR) to the memory. For the usage of EI2OS function, see "18.5.4 Conversion Using EI2OS" and
"18.5.5 A/D Converted Data Protection Function".
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
18.5
Operation of 8/10-Bit A/D Converter
A/D conversion of the 8/10-bit A/D converter includes the following conversion modes.
These mode settings are established by setting of the A/D conversion mode selection
bits (ADCS: MD1, MD0) of the A/D control status register.
• Single conversion mode
• Continuous conversion mode
• Stop conversion mode
■ Single Conversion Mode (ADCS: MD1, MD0=00B or 01B)
• In this mode, when an activation trigger is input, analog inputs from the start channel (ADSR: ANS3 to
ANS0) to the end channel (ADSR: ANE3 to ANE0) are sequentially A/D converted.
• After the A/D conversion of the end channel, the A/D conversion stops.
Notes:
• In the single conversion mode 1 (ADCS: MD1, MD0=00B), do not input an activation trigger during
the A/D conversion and the pause state*. If do so, the 8/10-bit A/D converter may restart.
In the single conversion mode 2 (ADCS: MD1, MD0=01B), the 8/10-bit A/D converter does not
restarts even if an activation trigger is input during the A/D conversion and the pause state*.
• In both single conversion mode 1 and single conversion mode 2, a restart shall be performed
according to "18.5.1 Single Conversion Mode".
*: The pause state means that the A/D conversion protection function sets off. For the detail, see
"18.5.5 A/D Converted Data Protection Function".
■ Continuous conversion mode (ADCS: MD1, MD0=10B)
• In this mode, when an activation trigger is input, analog inputs from the start channel (ADSR: ANS3 to
ANS0) to the end channel (ADSR: ANE3 to ANE0) are sequentially A/D converted.
• After the A/D conversion of the end channel, the A/D conversion returns to the start channel and repeats
the conversion.
■ Stop conversion mode (ADCS: MD1, MD0=11B)
• In this mode, when an activation trigger is input, A/D conversion of the start channel (ADSR: ANS3 to
ANS0) starts. After the A/D conversion for one channel, the conversion operation stops. This is called
as "Stop state". When an activation trigger is input in the stop state, the A/D conversion of the next
channel starts.
• After the A/D conversion of the end channel, the A/D conversion stops. When an activation trigger is
input in the stop state, the A/D conversion returns to the start channel and repeats the conversion.
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CHAPTER 18 8/10-Bit A/D Converter
18.5
18.5.1
MB90820B Series
Single Conversion Mode
In this mode, the A/D conversion is performed from the start channel to the end channel
sequentially. After the A/D conversion of the end channel, the A/D conversion stops.
■ Setting of Single Conversion Mode
To establish the single conversion mode of the 8/10-bit A/D converter, the setting as shown in Figure 18.51 is needed.
Figure 18.5-1 Setting of Single Conversion Mode
bit15 14 13 12 11 10
ADCS
9 bit8 bit7 6
BUSY INT INTE PAUS STS1 STS0 STRT
5
4
3
MD1 MD0 S10
2
1 bit0
Reserved
0
ADCR
ADSR
0
D9 to D0 (holds the converted result)
ST2 ST1 ST0 CT2 CT1 CT0 Reserved ANS3 ANS2 ANS1 ANS0 Reserved ANE3 ANE2 ANE1 ANE0
0
ADER1
ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8
ADER0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
0
: Undefined
: Used bit
: The bits corresponding to the pins used as analog input pins are set to "1"
0 : Set to "0"
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18.5
MB90820B Series
■ Operation and Usage of the Single Conversion Mode
• When an activation trigger is input, the A/D conversion is performed sequentially from the channel set
by the A/D conversion start channel selection bits (ANS3 to ANS0) to the channel set by the A/D
conversion end channel selection bits (ANE3 to ANE0).
• After the A/D conversion of the channel set by the A/D conversion end channel selection bits (ANE3 to
ANE0), the A/D conversion stops.
• To forcibly end the A/D conversion, write "0" in the A/D conversion ongoing operation flag bit (ADCS:
BUSY).
[If the start channel and the end channel are same:]
• If the start channel and the end channel are set to same (ADSRS: ANS3 to ANS0=ADSR: ANE3 to
ANE0), the A/D conversion is performed once only for the start channel (= end channel), then the A/D
conversion ends.
[Conversion sequence in the single conversion mode]
Examples of the conversion sequence in the single conversion mode are shown in Table 18.5-1 .
Table 18.5-1 Conversion Sequence in Single Conversion Mode
Start channel
End channel
Conversion sequence in the single conversion mode
Pin AN0
(ADSR: ANS=0000B)
Pin AN3
(ADSR: ANE=0011B)
AN0 -> AN1 -> AN2 -> AN3 -> End
Pin AN3
(ADSR: ANS=0011B)
Pin AN3
(ADSR: ANE=0011B)
AN3 -> End
[Restart]
To restart the A/D conversion during the A/D conversion or in the stop state, forcibly end the conversion
and restart with the following method:
1) Clear the A/D conversion ongoing operation flag bit (ADCS:BUSY).
2) Clear the interrupt request flag bit (ADCS:INT).
3) Set the A/D conversion software activation bit (ADCS:STRT).
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CHAPTER 18 8/10-Bit A/D Converter
18.5
18.5.2
MB90820B Series
Continuous Conversion Mode
In this mode, the A/D conversion is performed from the start channel to the end channel
sequentially. After the A/D conversion of the end channel, the A/D conversion returns to
the start channel and repeats the conversion.
■ Setting of Continuous Conversion Mode
To establish the continuous conversion mode of the 8/10-bit A/D converter, the setting as shown in Figure
17.5-4 is needed.
Figure 18.5-2 Setting of Continuous Conversion Mode
bit15 14 13 12 11 10
ADCS
9 bit8 bit7 6
BUSY INT INTE PAUS STS1 STS0 STRT
ADSR
4
3
2
1 bit0
MD1 MD0 S10
1
ADCR
5
Reserved
0
0
D9 to D0 (holds the converted result)
ST2 ST1 ST0 CT2 CT1 CT0 Reserved ANS3 ANS2 ANS1 ANS0 Reserved ANE3 ANE2 ANE1 ANE0
0
ADER1
ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8
ADER0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
0
: Undefined
: Used bit
: The bits corresponding to the pins used as analog input pins are set to "1"
1 : Set to "1"
0 : Set to "0"
■ Operation and Usage of the Continuous Conversion Mode
• When an activation trigger is input, the A/D conversion is performed sequentially from the channel set
by the A/D conversion start channel selection bits (ANS3 to ANS0) to the channel set by the A/D
conversion end channel selection bits (ANE3 to ANE0).
• After the A/D conversion of the channel set by the A/D conversion end channel selection bits (ANE3 to
ANE0), the A/D conversion returns to the channel set by the A/D conversion start channel selection bits
(ANS3 to ANS0) and repeats the conversion.
• To forcibly end the A/D conversion, write "0" in the A/D conversion ongoing operation flag bit (ADCS:
BUSY).
[If the start channel and the end channel are same:]
• If the start channel and the end channel are set to same (ADSR: ANS3 to ANS0=ADSR: ANE3 to
ANE0), the A/D conversion is performed once only for the start channel (= end channel) repeatedly.
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18.5
MB90820B Series
[Conversion sequence in the continuous conversion mode]
Examples of the conversion sequence in the continuous conversion mode are shown in Table 18.5-2 .
Table 18.5-2 Conversion Sequence in Continuous Conversion Mode
Start channel
End channel
Conversion sequence in the continuous conversion mode
Pin AN0
(ADSR: ANS=0000B)
Pin AN3
(ADSR: ANE=0011B)
AN0 -> AN1 -> AN2 -> AN3 -> AN0 -> Repeat
Pin AN3
(ADSR: ANS=0011B)
Pin AN3
(ADSR: ANE=0011B)
AN3 -> AN3 -> Repeat
[Restart]
To restart the A/D conversion during the A/D conversion or in the stop state, forcibly end the conversion
and restart with the following method:
1) Clear the A/D conversion ongoing operation flag bit (ADCS:BUSY).
2) Clear the interrupt request flag bit (ADCS:INT).
3) Set the A/D conversion software activation bit (ADCS:STRT).
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CHAPTER 18 8/10-Bit A/D Converter
18.5
18.5.3
MB90820B Series
Stop Conversion Mode
In this mode, the A/D conversion starts and stops every one channel. When an
activation trigger is input in the stop state after the end channel, the A/D conversion
returns to the start channel and repeats the conversion.
■ Setting of Stop Conversion Mode
To establish the stop conversion mode of the 8/10-bit A/D converter, the setting as shown in Figure 18.5-3
is needed.
Figure 18.5-3 Setting of Stop Conversion Mode
bit15 14 13 12 11 10
ADCS
9 bit8 bit7 6
BUSY INT INTE PAUS STS1 STS0 STRT
ADSR
4
3
MD1 MD0 S10
1
ADCR
5
2
1 bit0
Reserved
1
0
D9 to D0 (Holds the converted result)
ST2 ST1 ST0 CT2 CT1 CT0 Reserved ANS3 ANS2 ANS1 ANS0 Reserved ANE3 ANE2 ANE1 ANE0
0
ADER1
ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8
ADER0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
0
: Undefined
: Used bit
: The bits corresponding to the pins used as analog input pins are set to "1"
1 : Set to "1"
0 : Set to "0"
■ Operation and Usage of the Stop Conversion Mode
• When an activation trigger is input, the A/D conversion is performed from the channel set by the A/D
conversion start channel selection bits (ANS3 to ANS0). After the A/D conversion of one channel, the
A/D conversion stops. When an activation trigger is input in the stop state, the A/D conversion of the
next channel starts.
•
After the A/D conversion of the channel set by the A/D conversion end channel selection bits (ANE3 to
ANE0), the A/D conversion stops. When an activation trigger is input in the stop state, the A/D
conversion returns to the channel set by the A/D conversion start channel selection bits (ANS3 to
ANS0) and repeats the conversion.
• To forcibly end the A/D conversion, write "0" in the A/D conversion ongoing operation flag bit (ADCS:
BUSY).
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
[If the start channel and the end channel are same:]
If the start channel and the end channel are set to same (ADSRS: ANS3 to ANS0=ADSR: ANE3 to ANE0),
the A/D conversion is performed only for the start channel (= end channel) repeatedly.
[Conversion sequence in the stop conversion mode]
Examples of the conversion sequence in the stop conversion mode are shown in Table 18.5-3 .
Table 18.5-3 Conversion Sequence in Stop Conversion Mode
Start channel
End channel
Conversion sequence in the single conversion mode
Pin AN0
(ADSR: ANS=0000B)
Pin AN3
(ADSR: ANE=0011B)
AN0 -> stop/start -> AN1 -> stop/start -> AN2 -> stop/start
-> AN3 -> stop/start -> AN0 -> repeat
Pin AN3
(ADSR: ANS=0011B)
Pin AN3
(ADSR: ANE=0011B)
AN3 -> stop/start -> AN3 -> stop/start -> repeat
[Restart]
To restart the A/D conversion during the A/D conversion or in the stop state, forcibly end the conversion
and restart with the following method:
1) Clear the A/D conversion ongoing operation flag bit (ADCS:BUSY).
2) Clear the interrupt request flag bit (ADCS:INT).
3) Set the A/D conversion software activation bit (ADCS:STRT).
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CHAPTER 18 8/10-Bit A/D Converter
18.5
18.5.4
MB90820B Series
Conversion Using EI2OS
The 8/10-bit A/D converter can transmit the A/D converted result to the memory using
EI2OS function.
■ Conversion Using EI2OS
The flow of conversion using EI2OS is shown in Figure 18.5-4 .
Figure 18.5-4 Flow of Conversion Using EI2OS
A/D converter activated
Sample and hold
A/D conversion start
A/D conversion end
Interrupt generated
EI2OS activated
Converted result transmitted
Determined number of
times* finished?
NO
Interrupt cleared
YES
Interrupt
*: determined in EI2OS setting
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
[Restriction on using EI2OS]
In the following cases, do not use EI2OS to transmit the A/D converted result data. Use the CPU data
reading instruction to the A/D converted result data.
1) In the case that the A/D conversion is performed in the single conversion mode for sequential three
or more channels.
2) In the case that the A/D conversion is performed in the continuous conversion mode.
3) In the case that the A/D conversion is performed in the stop conversion mode with the external
trigger activation or 16-bit reload timer activation for sequential three or more channels
(ADSR:ANE-ADSR:ANS≥2).
[Software activation from the stop state in the stop conversion mode]
In the case that the A/D conversion is performed in the stop mode with the software activation for
sequential three or more channels (ADSR:ANE-ADSR:ANS≥2), the activation from the stop state
should be the following steps.
1) Wait for the A/D conversion time passing from start of the A/D conversion.
2) Read the interrupt request flag bit (ADCS:INT). When the bit is "0", go to step 3). If "1", go to 2).
3) Write "1" in ADCS:STRT bit to software-activate the A/D conversion.
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CHAPTER 18 8/10-Bit A/D Converter
18.5
18.5.5
MB90820B Series
A/D Converted Data Protection Function
When the A/D conversion is performed with the interrupt request output enabled, the
data protection function sets off.
■ The A/D converted data protection function of the 8/10-bit A/D converter
The A/D converted data protection function is designed for preventing from failing the A/D converted data.
The 8/10-bit A/D converter includes one A/D data register (ADCR1/ADCR0) for storing the converted data
and one sequential compare circuit for storing the ongoing A/D converted data.
During the A/D conversion, the 8/10-bit A/D converter stores the converted data in the sequential compare
circuit for every one bit. After the A/D conversion, the A/D converted result is stored in the A/D data
register.
The 8/10-bit A/D converter operates as the followings depending on use or no use of the A/D converted
data protection function.
• To disable the data protection function, set the interrupt request enable bit (ADCS:INTE) to "0". In this
case, during the sequential A/D conversion, the 8/10-bit A/D converter stores the converted result each
time the A/D conversion ends. (Always the latest converted data is stored.)
• To enable the data protection function, set the interrupt request enable bit (ADCS:INTE) to "1". In this
case, when the A/D conversion is performed sequentially, the interrupt request flag bit (ADCS:INT) is
set to "1" after the first conversion ends. Then the next conversion is performed. If the conversion ends
with INT=1, the 8/10-bit A/D converter pauses just before the converted result is transmitted from the
sequential compare circuit to the A/D data register, therefore this prevents the converted data from
overwritten. At this point, the pause flag bit (ADCS:PAUS) of the A/D control status register is set to
"1". In this pause state, when the interrupt request flag bit (ADCS:INT) is cleared to zero, the data
stored in the sequential compare circuit is transmitted to the A/D data register. (See Figure 18.5-5 .)
Figure 18.5-5 Operation of A/D Converted Data Protection Function
A/D (1) conversion time
Sampling time Compare time
A/D conversion data register ADCR
A/D (2) conversion time
Sampling time Compare time
478
A/D (3) conversion time
Sampling time
A/D (2) conversion result
A/D (1) conversion result
A/D conversion interrupt (INT bit) INT = 0 INT = 1
A/D conversion data protection function
(PAUS bit)
A/D conversion
data protection
function operating
Clear INT
PAUS = 0
PAUS = 1
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
● A/D converted data protection function for CPU reading
• After the analog input is A/D converted, when the A/D converted result is stored in the A/D data register
(ADCR), the interrupt request flag (ADCS: INT) of the A/D control status register is set to "1".
• At the time the next A/D conversion ends, if the interrupt request flag bit (ADCS: INT) remains the
value set at the end of the last A/D conversion with the interrupt request enabled (ADCS: INTE=1), the
A/D conversion pauses just before the A/D data register is overwritten by the new data in order to
protect the data.
• Because the interrupt request of the A/D control status register is enabled (ADCS: INTE=1), the
interrupt request is generated when INT bit is set. When the INT bit is cleared, the pause state of the A/
D conversion is released.
• During the sequential A/D conversion, the 8/10-bit A/D converter starts the next A/D conversion. In this
case, the pause flag bit (ADCS: PAUS) is not cleared to zero automatically. To clear this, write zero in
the bit.
Notes:
• If the interrupt request output is set to disabled (ADCS:INTE=0) in the pause state, the A/D
conversion may start and overwrite the A/D data register.
• When multiple A/D conversions are performed sequentially, the data stored in the A/D data
register must be read before the interrupt request flag bit (ADCS: INT) is cleared. If the interrupt
request flag (ADCS: INT) is cleared before the data stored in the A/D data register is read in the
pause state, the converted data stored first is overwritten by the next converted data.
● A/D converted data protection function for transmitting the A/D converted result using EI2OS
After the A/D conversion, during transmitting the A/D converted result from the A/D data register to the
memory using EI2OS, if the next A/D conversion ends, the A/D conversion pauses to protect data just
before the A/D register is overwritten by the new data. When the A/D conversion stops, the pause flag bit
of the A/D control status register (ADCS: PAUS) is set to "1".
After the A/D converted result is transmitted to the memory using EI2OS, the pause state of the A/D
conversion is released. In the case of the sequential A/D conversion, the A/D conversion resumes. At this
point, the pause flag bit (ADCS: PAUS) is not cleared to zero automatically. To clear this, write zero in the
bit.
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
Notes:
• In case that the A/D converted result is transmitted to the memory using EI2OS, the interrupt
request flag bit should not be cleared (ADCS: INT=0) by CPU. The data of the A/D data register in
transmission may be overwritten.
• In case that the A/D converted result is transmitted to the memory using EI2OS, the interrupt
request output should not be disabled. If the interrupt request output is disabled (ADCS: INTE=0)
in pause state, the A/D conversion starts and the data of the A/D data register in transmission
may be overwritten.
• In case that the A/D converted result is transmitted to the memory using EI2OS, do not restart.
Restarting in the pause state of the A/D conversion may destruct the converted result.
● Process flow of the A/D converted data protection function using EI2OS
The process flow diagram of the A/D converted data protection function using EI2OS is shown in Figure
18.5-6 .
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CHAPTER 18 8/10-Bit A/D Converter
18.5
MB90820B Series
Figure 18.5-6 Process Flow of A/D Converted Data Protection Function Using EI2OS
EI2OS set
A/D sequential conversion activated
First conversion ends
Stored in A/D data register
EI2OS activates
Second conversion ends
EI2OS ends
NO
A/D pause
YES
Stored in A/D data register
Third conversion
EI2OS activates
Continued
All conversions end
EI2OS ends
NO
A/D pause
YES
EI2OS activates
Interrupt process
A/D conversion stops
<Note> The flow for the A/D converter stopping is omitted.
CM44-10147-2E
End
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CHAPTER 18 8/10-Bit A/D Converter
18.6
18.6
MB90820B Series
Precautions for Using the 8/10-Bit A/D Converter
Precautions for using the 8/10-bit A/D converter are as the followings:
■ Precautions for using the 8/10-bit A/D converter
● Analog input pins
• An analog input pin is also used as the general I/O port of port 6 and 7. To use this pin as the analog
input pin, set the analog input enable register (ADER0/ADER1) to switch the pin to the analog input
pin.
• To use this pin as the analog input pin, write "1" in the bit of the analog input enable register (ADER0/
ADER1) corresponding to the used pin and set the analog input enabled.
• If a middle level signal is input to the pin remaining as the general purpose I/O port, the input leak
current flows to the gate. Always set the analog input enabled before using this pin as the analog input
pin.
● Precautions for activation with an internal timer or an external trigger.
• To set the A/D activation trigger selection bit (ADCS: STS1, STS0) so as to activate the 8/10-bit A/D
converter using an internal timer output or an external trigger, set the level of the timer output or the
external trigger to inactive ("H" for an external trigger). If the input level of the activation trigger is set
active, the operation may start simultaneously with setting the A/D activation trigger selection bit
(ADCS: STS1, STS0) of the A/D control status register.
● Order for turning on the 8/10-bit A/D converter and applying an analog input
• The digital power source (VCC) must be turned on before turning on the 8/10-bit A/D converter and
applying an analog input (AN0 to AN15).
• The digital power source must be turned off after turning off the 8/10-bit A/D converter and applying an
analog input.
• AVR must be turned on/off so that AVCC is not exceeded. (Turning on/off the analog power source and
the digital power source simultaneously is not a problem.)
● Power voltage of the 8/10-bit A/D converter
• To prevent a latchup, power source of the 8/10-bit A/D converter (AVCC) must not exceed voltage of
the digital power source (VCC).
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CHAPTER 19
D/A CONVERTER
This chapter explains the functions and operation of the
digital/analog (D/A) converter.
19.1 Overview of D/A Converter
19.2 Block Diagram of D/A Converter
19.3 D/A Converter Pins
19.4 D/A Converter Registers
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CHAPTER 19 D/A CONVERTER
19.1
19.1
MB90820B Series
Overview of D/A Converter
The digital/analog (D/A) converter converts an 8-bit digital input into an analog output
by using R-2R method. The D/A converter has two channels. Output control can be
individually executed for each channel by using its D/A control register .
■ Function and Operation of the D/A Converter
This circuit is used to generate an analog output from an 8-bit digital input. By setting the enable bit in the
D/A control register (DACR) to "1", it will enable the corresponding D/A output channel. Hence, setting
this bit to "0" will disable that channel.
If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is
turned off. In the D/A converter, the bit is cleared to "0" and the direct-current path is shut off. The above
is also true in the stop mode.
The output voltage of the D/A converter ranges from 0 V to 255/256 × AVCC. To change the output
voltage range, adjust the AVCC voltage externally.
The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100 Ω) is
inserted to the output in series. To apply load to the output externally, estimate a sufficient stabilizing time.
Table 19.1-1 lists the theoretical values of output voltage for the D/A converter.
Table 19.1-1 Theoretical values of output voltage for the D/A converter
484
Value written to DA07 to DA00 and
DA17 to DA10
Theoretical value of output voltage
00H
0/256 × AVCC (=0 V)
01H
1/256 × AVCC
02H
2/256 × AVCC
:
:
FDH
253/256 × AVCC
FEH
254/256 × AVCC
FFH
255/256 × AVCC
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CHAPTER 19 D/A CONVERTER
19.2
MB90820B Series
19.2
Block Diagram of D/A Converter
This section shows the block diagram of D/A converter
■ D/A Converter Block Diagram
Figure 19.2-1 Block diagram of D/A converter
F2MC-16LX bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
DVR
DVR
DA17
DA07
2R
2R
R
DA16
R
DA06
2R
2R
R
R
DA15
DA05
DA11
DA01
2R
2R
R
DA10
R
DA00
2R
2R
2R
CM44-10147-2E
2R
DAE1
DAE0
Standby control
Standby control
D/A output ch.1
D/A output ch.0
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CHAPTER 19 D/A CONVERTER
19.3
19.3
MB90820B Series
D/A Converter Pins
This section describes the pins of the D/A converter and provides a pin block diagram.
■ D/A Converter Pins
The pins of the D/A converter are shared with the general-purpose I/O ports. Table 19.3-1 lists the
functions of the pins, I/O format, and settings required to use the D/A converter.
Table 19.3-1 D/A converter pins
Pin name
Pin function
I/O format
P70/DA0/AN8
Port 7 inputoutput / Analog
D/A converter
pins
Analog/CMOS
output / CMOS
hysteresis input
P71/DA1/AN9
Pull-up option
Standby
Settings required for pins
DACR0:DAE0=1
Not provided
Provided
DACR1:DAE1=1
■ Block Diagram of the D/A Converter Pins
Figure 19.3-1 Block diagram of the D/A converter pins.
A/D converter channel selection bit
A/D converter input
D/A converter output
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
D/A converter output enable bit
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CHAPTER 19 D/A CONVERTER
19.4
MB90820B Series
19.4
D/A Converter Registers
The D/A converter has the following two types of registers :
• D/A converter registers (DAT0 and DAT1)
• D/A control registers (DACR0 and DACR1)
■ D/A Converter Registers
Figure 19.4-1 D/A converter registers
D/A data register 1
bit
15
DA17
Address: 0000CDH
Read/write ⇒ R/W
Initial value ⇒
X
14
DA16
R/W
X
13
DA15
R/W
X
12
DA14
R/W
X
11
DA13
R/W
X
10
DA12
R/W
X
9
DA11
R/W
X
8
DA10
R/W
X
6
5
4
3
2
1
0
DA06
R/W
X
DA05
R/W
X
DA04
R/W
X
DA03
R/W
X
DA02
R/W
X
DA01
R/W
X
DA00
R/W
X
15
14
13
12
11
10
9
8
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
DAE1
R/W
0
7
−
−
X
6
−
−
X
5
−
−
X
4
−
−
X
3
−
−
X
2
−
−
X
1
−
−
X
0
DAE0
R/W
0
DAT1
D/A data register 0
bit
7
Address: 0000CCH
DA07
Read/write ⇒ R/W
Initial value ⇒
X
DAT0
D/A control register 1
bit
Address: 0000CFH
Read/write ⇒
Initial value ⇒
DACR1
D/A control register 0
bit
Address: 0000CEH
Read/write ⇒
Initial value ⇒
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DACR0
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CHAPTER 19 D/A CONVERTER
19.4
19.4.1
MB90820B Series
D/A Converter Register 1 (DAT1)
The D/A converter register 1 (DAT1) is used to set the digital input data for channel 1,
which will be converted into an analog output.
■ D/A Converter Register 1 (DAT1)
Figure 19.4-2 D/A converter register 1 (DAT1)
D/A converter register 1
Bit
15
DA17
Address: 0000CDH
Read/write ⇒ R/W
Initial value ⇒
X
14
DA16
R/W
X
13
DA15
R/W
X
12
DA14
R/W
X
11
DA13
R/W
X
10
DA12
R/W
X
9
DA11
R/W
X
8
DA10
R/W
X
DAT1
R/W: Read and write
X: Unknown
The D/A converter register 1 (DAT1) is used to set the digital input data for channel 1, which will be
converted into an analog output.
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CM44-10147-2E
CHAPTER 19 D/A CONVERTER
19.4
MB90820B Series
19.4.2
D/A Converter Register 0 (DAT0)
The D/A converter register 0 (DAT0) is used to set the digital input data for channel 0,
which will be converted into an analog output.
■ D/A Converter Register 0 (DAT0)
Figure 19.4-3 D/A converter register 0 (DAT0)
D/A converter register 0
Bit
7
DA07
Address: 0000CCH
Read/write ⇒ R/W
Initial value ⇒
X
6
DA06
R/W
X
5
DA05
R/W
X
4
DA04
R/W
X
3
DA03
R/W
X
2
DA02
R/W
X
1
DA01
R/W
X
0
DA00
R/W
X
DAT0
R/W: Read and write
X: Unknown
The D/A converter register 0 (DAT0) is used to set the digital input data for channel 0, which will be
converted into an analog output.
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CHAPTER 19 D/A CONVERTER
19.4
19.4.3
MB90820B Series
D/A Control Register 1 (DACR1)
The D/A control register 1 is used to keep the output enable signal for channel 1.
■ D/A Control Register 1 (DACR1)
Figure 19.4-4 D/A control register 1 (DACR1)
Address
0000CFH
Read/write
Initial value
bit15
bit14 bit13 bit12 bit11 bit10
-
-
-
-
-
-
bit9
-
bit8
Initial value
DAE1 XXXXXXX0B
-
-
-
-
-
-
-
R/W
X
X
X
X
X
X
X
0
R/W : Read and write
-
: Undefind
X
: Unknown
DAE1
D/A output enable bit for channel 1
0
Disable
1
Enable
: Initial value
Table 19.4-1 D/A control register 1 (DACR1)
Bit name
bit15
to
bit 9
bit 8
490
Function
Undefind bits
DAE1 :
D/A output enable
bit for channel 1
•
•
The read value is undefined.
Writing to these bits have no effect on the operation.
•
This bit is used to determine if D/A converter output is enabled or disabled.
DAE1 is responsible for channel 1.
Writing "1" to this bit enables D/A output; similarly "0" disables D/A
output.
This bit is initialized to "0" at reset.
This bit can be read and written.
•
•
•
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CM44-10147-2E
CHAPTER 19 D/A CONVERTER
19.4
MB90820B Series
19.4.4
D/A Control Register 0 (DACR0)
The D/A control register 0 is used to keep the output enable signal for channel 0.
■ D/A Control Register 0 (DACR0)
Figure 19.4-5 D/A control register 0 (DACR0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Address 0000CEH
Read/write
Initial value
bit0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
X
X
X
X
X
X
X
0
Initial value
DAE0 XXXXXXX0B
R/W : Read and write
-
: Undefind
DAE0
D/A output enable bit for channel 0
X
: Unknown
0
Disable
1
Enable
: Initial value
Table 19.4-2 D/A control register 0 (DACR0)
Bit name
bit 7
to
bit 1
bit 0
CM44-10147-2E
Function
Undefind bits
DAE0 :
D/A output enable
bit for channel 0
•
•
The read value is undefined.
Writing to these bits have no effect on the operation.
•
This bit is used to determine if D/A converter output is enabled or disabled.
DAE0 is responsible for channel 0.
Writing "1" to this bit enables D/A output; similarly "0" disables D/A
output.
This bit is initialized to "0" at reset.
This bit can be read and written.
•
•
•
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CHAPTER 19 D/A CONVERTER
19.4
492
MB90820B Series
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 20
UART
This chapter explains the functions and operation of
UART.
20.1 Overview of UART
20.2 Block Diagram of UART
20.3 UART Pins
20.4 UART Registers
20.5 UART Interrupts
20.6 UART Baud Rates
20.7 Operation of UART
20.8 Usage Notes on UART
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CHAPTER 20 UART
20.1
20.1
MB90820B Series
Overview of UART
UART is a general-purpose serial data communication interface for performing
synchronous or asynchronous (start-stop synchronization) communication with
external devices. The UART has a clock synchronous and bidirectional communication
function (normal mode), additionally the master-slave communication function
(multiprocessor mode) is only available for the master system.
■ UART Functions (x 2)
● UART functions
UART is a general-purpose serial data communication interface for transmitting serial data to and receiving
data from another CPU and external peripheral devices. It has the functions listed in Table 20.1-1.
Table 20.1-1 UART functions
Function
Data buffer
Full-duplex, double buffering
Transfer mode
•
•
Clock synchronous
Clock asynchronous (start-stop synchronization)
•
Baud rate
•
•
A dedicated baud rate generator is provided. Eight settings can be
selected
An external clock can be input
Internal clock (From 16-bit reload timer 0 and 1, the clock of 16-bit
reload timer 0 is supplied to UART0, and the clock of 16 bit reload timer
1 is supplied to UART1. )
Data length
•
•
7 bits (in asynchronous normal mode only)
8 bits
Signal mode
•
Non-return to zero (NRZ)
Reception error detection
•
•
•
Framing error
Overrun error
Parity error (cannot be detected in multiprocessor mode)
•
•
•
Reception interrupt (reception completion and reception error detection)
Transmission interrupt (transmission completion)
Extended intelligent I/O service (EI2OS) is available for both
transmission and reception interrupts
Interrupt request
Master-slave
communication function
(multiprocessor mode)
494
One-to-n communication (one master to n slaves) can be performed (this
function is supported only for the master system)
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CM44-10147-2E
CHAPTER 20 UART
20.1
MB90820B Series
Note :
During clock synchronous transfer, start and stop bits are not added so only data is transferred in
UART.
Table 20.1-2 ART operation mode
Data length
Operation mode
When parity is
enabled
When parity
is disabled
Synchronization
mode
0
Normal mode
7 or 8 bits
1
Multiprocessor
8+1*1 bits
–
Asynchronous
2
Normal mode
8 bits
–
Synchronous
Stop bit length
Asynchronous
1 or 2 bits *2
None
– : Setting not possible.
*1 : "+1" indicates the address/data selection bit (A/D) for communication control.
*2 : During reception, only one stop bit can be detected.
■ UART Interrupt and EI2OS
Table 20.1-3 UART interrupt and EI2OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Upper
Bank
UART1 reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
UART1
transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
UART0 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
UART0
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
∆
∆
: Provided with a function that detects a UART reception error and stops EI2OS
∆ : Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used
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CHAPTER 20 UART
20.2
20.2
MB90820B Series
Block Diagram of UART
The block diagram of the UART is shown in Figure 20.2-1.
■ Block Diagram of UART
Figure 20.2-1 Block diagram of UART
From
communication
prescaler
Reception interrupt
#39 (27H)*
<#37 (25H)*>
P43/SCK0
<P74/SCK1>
Reception clock
External clock
P45/SIN0
<P72/SIN1>
Reception status
judgment circuit
Reception control
circuit
Transmission control
circuit
Start bit detect
circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission
parity counter
Reception shift
register
End of reception
Clock
selection
circuit
16-bit reload timer
Transmission
interrupt
#40 (28H)*
<#38 (26H)*>
Transmission clock
Start of transmission
Control bus
Dedicated
baud rate
generator
P44/SOT0
<P73/SOT1>
Transmission shift
register
SIDR0/SIDR1
SODR0/SODR1
EI2OS reception error
generation signal (to CPU)
F2MC-16LX bus
SMR0/SMR1
register
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
SCR0/SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/SSR1
register
*: Interrupt number
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
● Clock selector
The clock selector selects the dedicated baud rate generator, external input clock, or internal timer output
clock (clock supplied from the 16-bit reload timer) as the transmitting and receiving clocks.
496
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CHAPTER 20 UART
20.2
MB90820B Series
● Reception control circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts receive datas. When reception of one data item for the
specified data length is complete, the received bit counter generates a reception interrupt request. The start
bit detection circuit detects start bits from the serial input signal. When the circuit detects a start bit, it
writes data in the SIDR0/SIDR1 register by shifting per bit at the specified transfer rate. The received
parity counter calculates the parity bit of the receive data.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission datas. When transmission of
one data item for the specified data length is complete, the transmission bit counter generates a
transmission interrupt request. The transmission start circuit starts transmission when data is written to
SIDR0/SIDR1. The transmission parity counter generates a parity bit for data to be transmitted when parity
is enabled.
● Reception shift register
The reception shift register fetches receive data input from the SIN pin, shifting the data bit by bit. When
reception is complete, the reception shift register transfers receive data to the SIDR0/ SIDR1 register.
● Transmission shift register
The transmission shift register transfers data written to the SODR0/SODR1 register to itself and outputs the
data to the SOT pin, shifting the data bit by bit.
● Mode control register (SMR0/SMR1)
This register performs the following operations:
• Selecting a UART operation mode
• Selecting a clock input source
• Setting up the dedicated baud rate generator
• Selecting a clock rate (clock division value) when using the dedicated baud rate generator
• Specifying whether to enable or disable serial data output to the corresponding pin
• Specifying whether to enable or disable clock output to the corresponding pin
● Control register (SCR0/SCR1)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing an error flag
• Specifying whether to enable or disable transmission
• Specifying whether to enable or disable reception
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CHAPTER 20 UART
20.2
MB90820B Series
● Serial status register (SSR0/SSR1)
This register checks the transmission and reception status and error status, and enables and disables
transmission and reception interrupt requests.
● Serial input data register (SIDR0/SIDR1)
This register retains receive data. Serial input data is converted and stored in this register.
● Serial output data register (SODR0/SODR1)
This register sets transmission data. Data written to this register is converted to serial data and output.
498
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CM44-10147-2E
CHAPTER 20 UART
20.3
MB90820B Series
20.3
UART Pins
This section describes the UART pins and provides a pin block diagram.
■ UART Pins
The UART pins also serve as general-purpose I/O ports. Table 20.3-1 lists the pin functions, I/O formats
and settings required to use UART.
Table 20.3-1 UART pins
Pin name
Pin function
I/O format
Pull-up
Standby
control
Setting required to use pin
P45/SIN0
Port 4 I/O or serial
data input
Set as an input port
(DDR4: bit 5 = 0)
P44/SOT0
Port 4 I/O or serial
data output
Set to output enable mode
(SMR0: SOE = 1)
CMOS output and
CMOS hysteresis
input
P43/SCK0
Not
provided
Provided
Port 4 I/O or serial
clock input/output
Set as an input port when a
serial clock is input
(DDR4: bit 3 = 0 )
Set to output enable mode
when a serial clock is output
(SMR0: SCKE = 1)
P72/SIN1
Port 7 I/O or serial
data input
Set as an input port
(DDR7: bit 10 = 0)
P73/SOT1
Port 7 I/O or serial
data output
Set to output enable mode
(SMR1: SOE = 1)
CMOS output and
CMOS hysteresis
input
P74/SCK1
CM44-10147-2E
Not
provided
Provided
Port 7 I/O or serial
clock input/output
Set as an input port when a
serial clock is input
(DDR7: bit 12 = 0)
Set to output enable mode
when a serial clock is output
(SMR1:SCKE = 1)
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CHAPTER 20 UART
20.3
MB90820B Series
■ Block Diagram of UART Pins
Figure 20.3-1 Block diagram of UART serial data input pin(P45)
UART0 data input
UART0 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 20.3-2 Block diagram of UART serial clock input/output pin(P43) & serial data output pin(P44)
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
500
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CHAPTER 20 UART
20.3
MB90820B Series
Figure 20.3-3 Block diagram of UART serial data input pin(P72))
A/D converter channel selection bit
A/D converter input
UART1 data input
UART1 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 20.3-4 Block diagram of UART serial data input/output pin(P74) & serial data output pin(P73)
A/D converter input
A/D converter channel selection bit
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
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CHAPTER 20 UART
20.4
20.4
MB90820B Series
UART Registers
The following figure shows the UART registers.
■ UART Registers
Figure 20.4-1 UART registers
Serial Control Register
15
bit
Address: ch.0 000021H
ch.1 000025H
14
13
12
11
10
9
8
SCR0/SCR1
PEN
P
R/W
0
R/W
0
Read/write
Initial value
SBL
CL
R/W
0
AD
R/W
0
REC
RXE
TXE
W
1
R/W
0
R/W
0
R/W
0
Serial Mode Register
bit
7
6
5
4
3
2
1
0
MD0
CS2
CS1
CS0
RST
SCKE SOE
SMR0/SMR1
Address: ch.0 000020H
ch.1 000024H
MD1
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
R/W
0
R/W
0
9
8
Serial Status Register
bit
Address: ch.0 000023H
ch.1 000027H
Read/write
Initial value
15
SSR0/SSR1
PE
ORE
R
0
R
0
FRE
RDRF TDRE
R
0
R
0
R
1
BDS
RIE
TIE
R/W
0
R/W
0
R/W
0
3
2
Serial Input Data Register / Serial Output Data Register
7
bit
Address: ch.0 000022H
ch.1 000026H
Read/write
Initial value
6
5
4
1
0
SIDR0, SODR0/
SIDR1, SODR1
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Clock Division Control Register
bit 15
502
Address: ch.0 000035H
ch.1 000037H
MD
ILS
Read/write
Initial value
R/W
0
R/W
0
14
13
12
11
10
9
8
CDCR0/CDCR1
X
X
X
DIV2
DIV1
DIV0
R/W
0
R/W
0
R/W
0
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CHAPTER 20 UART
20.4
MB90820B Series
20.4.1
Serial Control Register (SCR0/SCR1)
This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
or disable transmission and reception.
■ Serial Control Register (SCR0/SCR1)
Figure 20.4-2 Serial control register (SCR0/SCR1)
Address
bit15bit14bit13bit12bit11bit10bit9bit8bit7bit0
SCR0:000021 H
SCR1:000025 H PEN
P
SBL
CL
AD
Initial value
(SMR)
REC RXE TXE
0 0 0 0 0 1 0 0B
R/WR/WR/WR/WR/WWR/WR/W
TXE
Transmission enable bit
0
Disables transmission
1
Enables transmission
RXE
Reception enable bit
0
Disables reception
1
Enables reception
REC
Reception error flag clear bit
0
Clears the FRE, ORE, and PE bits
1
Has no effect on the others
AD
Address/data selection bit
0
Data frame
1
Address frame
CL
7 bits
1
8 bits
SBL
1-bit length
1
2-bit length
Parity selection bit
Enabled only when parity is provided (PEN=1)
0
Even parity
1
Odd parity
PEN
CM44-10147-2E
Stop bit length selection bit
0
P
R/W : Read/Write
W : Write only
: Initial value
Data length selection bit
0
Parity enable bit
0
Provides no parity bit
1
Provides a parity bit
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CHAPTER 20 UART
20.4
MB90820B Series
Table 20.4-1 Function of Serial control register (SCR0/SCR1)
Bit name
Function
•
bit15
PEN:
Parity enable bit
bit14
P:
Parity selection bit
bit13
SBL:
Stop bit length selection
bit
bit12
CL:
Data length selection bit
bit11
A/D:
Address/data selection
bit
This bit selects whether to add a parity bit during transmission or to
detect it during reception.
Note :
No parity can be used in operation modes 1 and 2. Therefore, fix
this bit to 0.
•
When parity is provided (PEN = 1), this bit selects an even or odd
parity.
•
This bit selects the length of the stop bits or the frame end mark bit
of send data in asynchronous transfer mode.
Note :
During reception, only the first bit of the stop bits is detected.
• This bit specifies the length of send and receive data.
Note :
Seven bits can be selected in operation mode 0 (asynchronous)
only. Be sure to select eight bits (CL = 1) in operation mode 1
(multiprocessor mode) and operation mode 2 (synchronous).
•
•
Specify the data format of a frame to be sent or received in
multiprocessor mode (mode 1).
Select usual data frame when this bit is 0, and select address data
frame when the bit is 1.
•
bit10
REC:
Reception error flag
clear bit
This bit clears the FRE, ORE and PE flags of the serial status
register (SSR0/SSR1) to 0.
• Write 0 to this bit to clear the FRE, ORE and PE flags. Writing 1
to this bit has no effect on the others.
Note :
If UART is active and a reception interrupt is enabled, clear the
REC bit to 0 only when the FRE, DRE or PE flag indicates 1.
•
•
bit9
RXE:
Reception enable bit
This bit controls to enable or disable UART reception.
When this bit is 0, reception is disabled. When it is 1, reception is
enabled.
Note :
If this bit is cleared during reception, reception can only be
disabled until the reception of current frame is completed and the
reception data is stored in the serial input data register (SIDR0/
SIDR1).
•
•
bit8
504
TXE:
Transmission enable bit
This bit controls to enable or disable UART transmission.
When this bit is 0, transmission is disabled. When the bit is 1,
transmission is enabled.
Note :
If this bit is cleared during transmission, transmission can only be
disabled until all data in the serial output data register (SODR0/
SODR1) has been transmitted.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 20 UART
20.4
MB90820B Series
20.4.2
Serial Mode Register (SMR0/SMR1)
This register selects an operation mode and baud rate clock and specifies whether to
enable or disable output of serial data and clocks to the corresponding pin.
■ Serial Mode Register (SMR0/SMR1)
Figure 20.4-3 Serial mode register (SMR0/SMR1)
Address
SMR0:000020H
SMR1:000024H
bit15
bit8 bit7
bit6
bit5
bit4
bit3
bit1
bit0
Initial value
MD1 MD0 CS2 CS1 CS0 RST SCKE SOE 0 0 0 0 0 0 0 0 B
(SCR)
R/W R/W R/W R/W R/W
SOE
0
1
Uses the pin as the serial data output pin of UART
Serial clock input/output enable bit
0
Uses the pin as a general I/O port or clock input pin of UART
1
Uses the pin as the clock output pin of UART
RST
UART reset bit
0
No effect
1
Resets UART
CS2 to CS0
Clock selection bit
"000B" to "100B"
Baud rate by dedicated baud rate generator
"101B"
Disables setting.
"110B"
Baud rate by internal timer
( 16-bit reload timer )
"111B"
Baud rate by external clock
Operation mode selection bit
MD1 MD0
R/W : Enables read and write.
: Initial value
R/W R/W R/W
Serial data output enable bit
Uses the pin as a general I/O port
SCKE
CM44-10147-2E
bit2
Operation mode
0
0
0
Asynchronous (normal mode)
0
1
1
1
0
2
Asynchronous (multiprocessor mode)
Synchronous (normal mode)
1
1
-
Disables setting.
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CHAPTER 20 UART
20.4
MB90820B Series
Table 20.4-2 Function of Serial mode register (SMR0/SMR1) (1 / 2)
Bit name
bit7,
bit6
bit5
to
bit3
bit2
506
Function
MD1, MD0: Operation
mode selection bits
• These bits select an operation mode.
Note :
Operation mode 1 (multiprocessor mode) can be used only from
the master system during master-slave communication. UART
cannot be used from the slave system because it has no address/
data detection function during reception.
CS2 to CS0:
Clock input source
selection bits
These bits select the baud rate clock source. If selecting the dedicated
baud rate generator, also set the baud rate.
• When selecting the dedicated baud rate generator, specify one of
the six available baud rates, and set synchronous or asynchronous
transfer mode. A total of eight baud rate settings are available if the
baud rate is generated from an internal or external timer.
• The available clock input sources are an external clock (SCK0/
SCK1 pins), the 16-bit reload timer0, and the dedicated baud rate
generator.
Note :
The following settings are prohibited if using the dedicated baud
rate generator in synchronous transfer mode:
1) CS2 to CS0 = 000B
2) CS2 to CS0 = 001B to DIV2 to DIV0 = 000B
RST:
UART reset bit
This bit resets the UART and registers CDCR0/CDCR1, SSR0/SSR1,
SCR0/SCR1.
• Writing 0 to this bit has no effect.
• Writing 1 to this bit resets the UART and registers CDCR0/
CDCR1, SSR0/SSR1, SCR0/SCR1. If will auto-clear after the
reset operation.
• Always read as 0.
Note :
After writing 1 to this bit, it is necessary to initiarize the setting of
UART and registers CDCR0/CDCR1, SSR0/SSR1, SCR0/SCR1
again.
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CHAPTER 20 UART
20.4
MB90820B Series
Table 20.4-2 Function of Serial mode register (SMR0/SMR1) (2 / 2)
Bit name
Function
•
bit1
SCKE:
Serial clock input/
output enable bit
This bit controls the serial clock input-output ports of the SCK0/
SCK1 pin.
• When this bit is 0, the P43/SCK0 and P74/SCK1 pins operate as
general input-output ports (P43 and P74) or serial clock input pins.
When this bit is 1, the pins operate as serial clock output pins.
Note :
- When using the P43/SCK0 and P74/SCK1 pins as serial clock
input (SCKE = 0) pins, set the P43 and P74 as input ports.
Also, select external clocks (SMR0/SMR1: CS2 to CS0 =
111B) using the clock selection bits.
- When using the pins as serial clock output (SCKE = 1) pins,
select bits other than external timer (other than SMR0/SMR1:
CS2 to CS0 = 111B).
[Reference]
When the SCK0/SCK1 pin is assigned to serial clock output
(SCKE = 1) pins, it functions as the serial clock output pin
regardless of the status for the general input-output ports.
•
•
bit0
CM44-10147-2E
SOE:
Serial data output
enable bit
This bit enables or disables the output of serial data.
When this bit is 0, the P44/SOT0 and P73/SOT1 pins operate as
general input-output ports (P44 and P73). When this bit is 1, the
P44/SOT0 and P73/SOT1 pins operate as serial data output pins
(SOT0/SOT1).
[Reference]
When serial data output pin is set (SOE=1), the P44/SOT0 and
P73/SOT1pins function as SOT0/SOT1 pins regardless of the
status of general input-output ports (P44 and P73).
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CHAPTER 20 UART
20.4
20.4.3
MB90820B Series
Serial Status Register (SSR0/SSR1)
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
■ Serial Status Register (SSR0/SSR1)
Figure 20.4-4 Serial status register (SSR0/SSR1)
Address
SSR0:000023H
SSR1:000027H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PE ORE FRE RDRF TDRE BDS RIE
R
R
R
R
R
bit8 bit7
TIE
bit0
(SIDR/SODR)
Initial value
00001000B
R/W R/W R/W
TIE
Transmission interrupt request enable bit
0
Disables output of transmission interrupt request
1
Enables output of transmission interrupt request
RIE
Reception interrupt request enable bit
0
Disables output of reception interrupt request
1
Enables output of reception interrupt request
BDS
Transfer/reception direction selection bit
0
LSB first (transfer from the least significant bit)
1
MSB first (transfer from the most significant bit)
TDRE
Transmission data empty flag bit
0
Transmission data exists
(Writing transmission data is not allowed)
1
Transmission data does not exist.
(Writing transmission data is allowed)
RDRF
Receive data full flag bit
0
No receive data exists
1
Receive data exists
Framing error flag bit
FRE
0
No framing error occurred
1
ORE
X
508
Overrun error flag bit
0
No overrun error occurred
1
An overrun error occurred
PE
R/W : Read/Write
R : Read only
A framing error occurred
Parity error flag bit
0
No parity error occurred
1
A parity error occurred
: Undefined
: Undefined
: Initial value
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CM44-10147-2E
CHAPTER 20 UART
20.4
MB90820B Series
Table 20.4-3 Functions of each bit in serial status register (SSR0/SSR1)
Bit name
bit15
bit14
bit13
bit12
Function
PE:
Parity error flag bit
This flag indicates whether the parity error is performed during reception.
• This bit is set to 1 when a parity error occurs during reception and is cleared to 0
when 0 is written to the REC bit of the serial control register (SCR0/SCR1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in serial input data register (SIDR0/SIDR1) is invalid when this bit is set.
ORE:
Overrun error flag bit
This flag indicates whether the overrun error is generated during reception.
• This bit is set to 1 when an overrun error occurs during reception and is cleared
to 0 when 0 is written to the REC bit of the serial control register (SCR0/SCR1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in the serial input data register (SIDR0/SIDR1) is invalid when this bit is set.
FRE:
Framing error flag bit
This flag indicates whether the framing error occures during reception.
• This bit is set to 1 when a framing error occurs during reception and is cleared to
0 when 0 is written to the REC bit of the serial control register (SCR0/SCR1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in the serial input data register (SIDR0/SIDR1) is invalid when this bit is set.
RDRF:
Receive data full flag bit
•
•
•
This flag indicates the status of the serial input data register (SIDR0/SIDR1).
This bit is set to 1 when receive data is loaded into SIDR0/SIDR1 and is cleared
to 0 when SIDR0/SIDR1 is read.
A reception interrupt request is output when the data is loaded to the SIDR and
the RIE bit are 1.
•
•
bit11
TDRE:
Transmission data
empty flag bit
This flag indicates the status of serial output data register (SODR0/SODR1).
This bit is cleared to 0 when transmission data is written to SODR0/SODR1 and
is set to 1 when data is loaded into the transmission shift register and
transmission starts.
• A transmission interrupt request is output when the data set in the SODR is
transferred and the TIE bit are 1.
Note :
This bit is set to 1 (SODR0/SODR1 empty) as its initial value.
•
This bit selects whether to transfer serial data from the least significant bit (LSB
first, BDS = 0) or the most significant bit (MSB first, BDS = 1).
Note :
The high-order and low-order sides of serial data are interchanged with each
other during reading from or writing to the serial data register. If this bit is set to
another value after the data is written to the SODR register, the data becomes
invalid.
bit10
BDS:
Transfer direction
selection bit
bit9
RIE:
Reception interrupt
request enable bit
•
•
This bit enables or disables input of a request for reception interrupt to the CPU.
A reception interrupt request is output when this bit and the RDRF are 1 and one
or more error flag bits (PE, ORE and FRE) are 1.
TIE:
Transmission interrupt
request enable bit
•
bit8
This bit enables or disables output of a request for transmission interrupt to the
CPU.
A transmission interrupt request is output when this bit and the TDRE bit are 1.
CM44-10147-2E
•
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CHAPTER 20 UART
20.4
20.4.4
MB90820B Series
Serial Input Data Register (SIDR0/SIDR1) and Serial
Output Data Register (SODR0/SODR1)
The serial input data register (SIDR0/SIDR1) is a serial data reception register. The
serial output data register (SODR0/SODR1) is a serial data transmission register. Both
SIDR0/SIDR1 and SODR0/SODR1 registers are located in the same address.
■ Serial Input Data Register (SIDR0/SIDR1)
Figure 20.4-5 shows the bit configuration of serial input data register.
Figure 20.4-5 Serial input data register (SIDR0/SIDR1)
Serial input data register
Address : bit 7
SIDR0 000022H
D7
SIDR1 000026H
Read/write ⇒
(R)
Initial value ⇒
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Initial value
XXXXXXXXB
SIDR0/SIDR1 is a register that contains receive data. The serial data signal transmitted to the SIN0/SIN1
pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7)
contains invalid data. When receive data is stored in this register, the receive data full flag bit (SSR0/
SSR1: RDRF) is set to 1. If a reception interrupt request is enabled at this point (SSR0/SSR1: RIE=1), a
reception interrupt occurs.
Read SIDR0/SIDR1 when the RDRF bit of the serial status register (SSR0/SSR1) is 1. The RDRF bit is
cleared automatically to 0 when SIDR0/SIDR1 is read.
Data in SIDR0/SIDR1 is invalid when a reception error occurs (SSR0/SSR1: PE, ORE or FRE = 1).
■ Serial Output Data Register (SODR0/SODR1)
Figure 20.4-6 shows the bit configuration of the serial output data register.
Figure 20.4-6 Serial output data register (SODR0/SODR1)
Serial output data register
Address : bit 7
SODR0 000022H
D7
SODR1 000026H
Read/write ⇒ (W)
Initial value ⇒
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
Initial value
XXXXXXXXB
This register is a data buffer register for the serial data transmission.
When data to be transmitted is written to this register in transmission enable state, it is transferred to the
transmission shift register, then converted to serial data, and transmitted from the serial data output (SOT0/
SOT1 pin). When the data length is 7 bits, the uppermost bit (D7) contains invalid data.
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When transmission data is written to this register, the transmission data empty flag bit (SSR0/SSR1:
TDRE) is cleared to "0". When transfer to the transmission shift register is complete, the bit is set to "1".
When the TDRE bit is "1", the next piece of transmission data can be written. If output transmission
interrupt requests have been enabled, a transmission interrupt is generated. Write the next piece of
transmission data when a transmission interrupt is generated or the TDRE bit is "1".
Note :
SODR0/SODR1 is a write-only register and SIDR0/SIDR1 is a read-only register. These registers are
located in the same address, so the read value is different from the write value. Therefore, instructions
that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be
used.
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CHAPTER 20 UART
20.4
MB90820B Series
Communication Prescaler Control Register (CDCR)
20.4.5
This register controls the division ratio of machine clocks.
■ Communication Prescaler Control Register (CDCR)
The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain
certain baud rates for various machine clock using this communication prescaler. Output from the
communication prescaler is used for the operation clocks of I/O extended serial interfaces.
Figure 20.4-7 Communication prescaler control register (CDCR)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000035H
000037H
MD
ILS
—
—
—
DIV2
DIV1
DIV0
0XXXX000B
R/W
R/W
—
—
—
R/W
R/W
R/W
DIV2
DIV1
DIV0
Communication prescaler division ratio
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
ILS
Select data input (SIN) as hysteresis level
1
Select data input (SIN) as CMOS level
MD
R/W : Read and write
X
—
SIN input level select
0
Machine clock divide mode select
0
Stops the communication prescaler.
1
Operates the communication prescaler.
: Undefined
: Undefined
: Initial value
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Table 20.4-4 Communication prescaler control register (CDCR)
Bit name
bit15
MD:
Machine clock
divide mode select
bit
• This bit enables or stops the operation of the communication prescaler.
• When "0" is set, the communication prescaler stops.
• When "1" is set, the communication prescaler operates.
bit 14
ILS:
SIN input level
select bit
• This bit selects input level of UART data input pin (SIN)
• Write "0" selects hysteresis input level.
• Write "1" selects CMOS input level.
bit13,
bit12
Reserved bits
• Always read as "0".
DIV2 to DIV0:
Communication
prescaler division
ratio bits
These bits set the divide ratio for the machine clock.
The divide ratio can only be set when the MD bit is set to "1".
• Once the divide ratio has been altered, 2 cycle wait is generated before
starting the communication.
Note:
The following settings are prohibited if using the dedicated baud rate
generator in synchronous transfer mode:
1) CS2 to CS0 = 000B
2) CS2 to CS0 = 001B and DIV2 to DIV0 = 000B
bit10
to
bit8
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CHAPTER 20 UART
20.5
20.5
MB90820B Series
UART Interrupts
UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the receive data is set in the serial input data register (SIDR0/
SIDR1), or a reception error occurs and transmission data is transferred from serial
output data register (SODR0/SODR1) to the transmission shift register.
The extended intelligent I/O service (EI2OS) is available for these interrupts.
■ UART Interrupts
Table 20.5-1 lists the interrupt control bits and causes of UART.
Table 20.5-1 Interrupt control bits and interrupt causes of UART
Reception/
transmission
Reception
Transmission
Interrupt
request flag bit
Operation mode
Interrupt cause
0
1
2
RDRF
O
O
O
Loading receive
data into buffers
(SIDR0/SIDR1)
ORE
O
O
O
Overrun error
FRE
O
O
X
Framing error
PE
O
X
X
Parity error
TDRE
O
O
O
Empty transmission
buffer
(SODR0/SODR1)
Interrupt output
enable bit
When interrupt
request flag is
cleared
Receive data is read
SSR0/SSR1:RIE
SSR0/SSR1:TIE
“0” is written to the
reception error flag
clear bit
(SSR0/SSR1: REC)
Transmission data
is written
O : Used
X : Not used
● Reception interrupt
The interrupt request is generated if one of the following events occurs in reception mode, the
corresponding flag bit of the serial status register is set to 1:
• Data reception is complete (SSR0/SSR1: RDRF)
• Overrun error (SSR0/SSR1: ORE)
• Framing error (SSR0/SSR1: FRE)
• Parity error (SSR0/SSR1: PE)
When at least one of the flag bits is 1 and the reception interrupts are enabled (SSR0/SSR1: RIE = 1), a
reception interrupt request is output to the interrupt controller.
When the serial input data register (SIDR0/SIDR1) is read, the receive data full flag (SSR0/SSR1: RDRF)
is automatically cleared to “0”. When “0” is written to the REC bit of the serial control register (SCR0/
SCR1), all the reception error flags (SSR0/SSR1: PE, ORE and FRE) are cleared to “0”.
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● Transmission interrupt
When transmission data is transferred from the serial output data register (SODR0/SODR1) to the transfer
shift register, the TDRE bit of the serial status register (SSR0/SSR1) is set to 1. When the transmission
interrupts have been enabled (SSR0/SSR1: TIE = 1), a transmission interrupt request is output to the
interrupt controller.
■ UART Interrupts and EI2OS
Table 20.5-2 UART interrupts and EI2OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
UART1 reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
UART1
transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
UART0 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
UART0
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
∆
∆
: Provided with a function that detects a UART reception error and stops EI2OS
∆ : Usable when interrupt causes that share the ICR13 and ICR14 or the interrupt vectors are not used
■ UART EI2OS Functions
UART has a circuit for operating EI2OS, which can be started up for either reception or transmission
interrupts.
● For reception
EI2OS can be used regardless of the status of other resources.
● For transmission
UART shares the interrupt control registers (ICR13 and ICR14) with the UART reception interrupts.
Therefore, EI2OS can be started up only when no UART reception interrupts are used.
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CHAPTER 20 UART
20.5
20.5.1
MB90820B Series
Reception Interrupt Request Generation and Flag Set
Timing
The following are the reception interrupt causes: completion of reception (SSR0/SSR1:
RDRF) and occurrence of a reception error (SSR0/SSR1: PE, ORE, or FRE).
■ Reception Interrupt Request Generation and Flag Set Timing
Receive data is stored in serial input data register (SIDR0/SIDR1) if a stop bit is detected (in operation
mode 0 or 1) or the last bit (D7) of data is detected (in operation mode 2) during reception. At that time, if
a reception error is detected, the error flags (SSR0/SSR1: PE, ORE and FRE) are set, then the receive data
full flag (SSR0/SSR1: RDRF) is set to 1. If one of the error flags is 1 in each mode, the SIDR0/SIDR1
register contains invalid data.
● Operation mode 0 (asynchronous, normal mode)
The RDRF bit is set to 1 when a stop bit is detected. If a reception error is detected, the error flags (PE,
ORE and FRE) are set to 1.
● Operation mode 1 (asynchronous, multiprocessor mode)
The RDRF bit is set to 1 when a stop bit is detected. If a reception error is detected, the error flags (ORE
and FRE) are set to 1. Parity errors cannot be detected.
● Operation mode 2 (synchronous, normal mode)
The RDRF bit is set to 1 when the last bit of receive data (D7) is detected. If a reception error is detected,
the error flag (ORE) is set. Parity and framing errors cannot be detected. Figure 20.5-1 below shows the
reception operation and flag set timing.
Figure 20.5-1 Reception operation and flag set timing
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7/P
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
A reception interrupt occurs.
*
: The PE flag cannot be used in operation mode 1
The PE and PRE flags cannot be used in operation mode 2
ST : Start bit
SP : Stop bit
A/D : Operaion Mode 2 (multiprocessor mode) address/data selection bit
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● Reception interrupt request generation timing
When the RDRF, PE, ORE or FRE flag is set to 1 in the reception interrupt enable state (SSR0/SSR1:RIE =
1), reception interrupt requests (#37 and #39) are generated.
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CHAPTER 20 UART
20.5
20.5.2
MB90820B Series
Transmission Interrupt Request Generation and Flag Set
Timing
A transmission interrupt request is generated when the next piece of data is ready to be
written to the serial output data register (SODR0/SODR1).
■ Transmission Interrupt Request Generation and Flag Set Timing
The transmission data empty flag bit (SSR0/SSR1: TDRE) is set to 1 when data written to the serial output
data register (SODR0/SODR1) is transferred to the transmission shift register, and the next piece of data is
ready to be written. TDRE is cleared to 0 when transmission data is written to SODR0/SODR1. Figure
20.5-2 shows the transmission operation and flag set timing.
Figure 20.5-2 Transmission operation and flag set timing
[Operation modes 0 and 1]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
SOT output
ST D0
D1 D2
D3
D4 D5
D6 D7
SP SP ST D0
AD
D1 D2
D3
[Operation mode 2]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
SOT output
ST: Start bit
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 to D7: Data bits
SP: Stop bit
AD: Address/data multiplexer
● Transmission interrupt request generation timing
If the TDRE flag is set to 1 when a transmission interrupt is enabled (SSR0/SSR1: TIE = 1), transmission
interrupt requests (#38 and #40) are generated.
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Note :
A transmission completion interrupt is generated immediately after the transmission interrupts are
enabled (TIE = 1) because the TDRE bit is set to 1 as its initial value. TDRE bit is a read-only bit
that can be cleared only by writing new data to the serial output data register (SODR0/SODR1).
Carefully specify the transmission interrupt enable timing.
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CHAPTER 20 UART
20.6
20.6
MB90820B Series
UART Baud Rates
One of the following can be selected as the UART transmitting/receiving clocks:
• Dedicated baud rate generator
• Internal clock (16-bit reload timer)
• External clock (clock of SCK pin input)
■ UART Baud Rate Selection
The baud rate selection circuit is designed as shown below. One of the following three types for baud rates
can be selected:
● Baud rates determined using the dedicated baud rate generator
UART has an internal dedicated baud rate generator. One of eight baud rates can be selected using the
mode control register (SMR0/SMR1).
An asynchronous or synchronous baud rate is selected using the machine clock frequency and setting the
CS2 to CS0 bits of the mode control register (SMR0/SMR1) .
● Baud rates determined using the internal timer
The internal clock supplied from 16-bit reload timer is used as it is (synchronous) or by dividing it by 16
(asynchronous) for the baud rate. Any baud rate can be set by setting the reload value.
● Baud rates determined using the external clock
The clock input from the UART clock input pins (P43/SCK0 and P74/SCK1) is used as it is (synchronous)
or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set externally.
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Figure 20.6-1 UART baud rate selection circuit
SMR0/SMR1 : CS2 to CS0
(Clock selection bits)
[Dedicated baud rate generator]
3
Clock selector
CDCR0/CDCR1 : MD, DIV2 to DIV0
(Prescaler enable and selection bits)
When the bits
are 000B to101B
4
φ
Frequency divider
(synchronous)
Frequency divider
(asynchronous)
Selects the internal fixed
division ratios
Machine clock prescaler
[Internal timer]
TMCSR0/TMCSR1 : CSL1, CSL0
2
When the bits
are 110B
Clock selector
φ
Down
counter
UF
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SCKI
φ/21 φ/23 φ/25
Prescaler
16-bit reload timer
When the bits
are 111B
[External clock]
P43/SCK0, P74/SCK1
Pin
1/1 (synchronous)
1/16 (asynchronous)
SMR0/SMR1 : MD1, MD0
(Synchronous or asynchronous clock selection)
φ : Machine clock frequency
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20.6
20.6.1
MB90820B Series
Baud Rates Determined Using the Dedicated Baud Rate
Generator
This section describes the baud rates that can be set when the clock from the dedicated
baud rate generator is selected as the UART Transmission/reception clock.
■ Baud Rates Determined Using the Dedicated Baud Rate Generator
When the transmission/reception clock is generated using the dedicated baud rate generator, the machine
clock is divided with the machine clock prescaler. The divided machine clock is then divided by the
transfer clock division ratio selected with the clock selector again. The machine clock division ratios are
common to the asynchronous and synchronous baud rates, but different values set internally are selected as
the transfer clock division ratio for the asynchronous and synchronous baud rates.
The actual transfer rate can be calculated using the following formulas:
asynchronous baud rate = φ x (prescaler division ratio) x (asynchronous transfer clock division ratio)
synchronous baud rate = φ x (prescaler division ratio) x (synchronous transfer clock division ratio)
φ : Machine clock frequency
● Division ratios for the communication prescaler (common to asynchronous and synchronous baud
rates)
Each machine clock division ratio is selected using the DIV2 to DIV0 bits of the CDCR register as listed in
Table 20.6-1.
Table 20.6-1 Output frequency of communication prescaler
522
MD
DIV2
DIV1
DIV0
Division ratio
0
–
–
–
Stops
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
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● Synchronous baud rate division ratios
A division ratio for synchronous baud rates is selected using the CS2 to CS0 bits of the serial mode control
register (SMR0/SMR1) as listed in Table 20.6-2
Table 20.6-2 Selection of synchronous baud rate division ratios
CS2
CS1
CS0
CLK synchronization
Calculation formula
0
0
0
2 MHz
( φ ÷ div) / 1
0
0
1
1 MHz
( φ ÷ div) / 2
0
1
0
500 kHz
( φ ÷ div) / 4
0
1
1
250 kHz
( φ ÷ div) / 8
1
0
0
125 kHz
( φ ÷ div) / 16
1
0
1
62.5 kHz
( φ ÷ div) / 32
Note that the calculation is supposing that φ (machine clock) = 16 MHz and div (machine clock division
ratio) = 8. The maximum baud rate is 1/8 machine clock.
● Asynchronous baud rate division ratios
A division ratio for asynchronous baud rates is selected using the CS2 to CS0 bits of the serial mode
control register (SMR0/SMR1) as listed in Table 20.6-3
Table 20.6-3 Selection of asynchronous baud rate division ratios
CS2
CS1
CS0
Asynchronous
(start-stop synchronization)
Calculation formula
0
0
0
76923 Hz
( φ ÷ div) / (8 × 13 × 2)
0
0
1
38461 Hz
( φ ÷ div) / (8 × 13 × 4)
0
1
0
19230 Hz
( φ ÷ div) / (8 × 13 × 8)
0
1
1
9615 Hz
( φ ÷ div) / (8 × 13 × 16)
1
0
0
500 kHz
( φ ÷ div) / (8 × 2 × 2)
1
0
1
250 kHz
( φ ÷ div) / (8 × 2 × 4)
Note that the calculation is supposing that φ (machine clock) = 16 MHz,
div (machine clock division ratio) = 1.
● Internal timer
When CS2 to CS0 are set to 110B and the internal timer is selected, the formulas for calculating baud rates
(when using the reload timer) are as follows:
Asynchronous (start-stop synchronization): ( φ ÷ N) / (16 × 2 × (n + 1))
CLK synchronization: ( φ ÷ N) / (2 × (n + 1))
N: Division ratio for the prescaler of 16-bit reload timer
n: Reload value of the 16-bit reload timer
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Note :
In mode 2 (CLK synchronization mode), SCK0/SCK1 is up to three clocks later than SCKI. A
logically attainable transfer rate is 1/3 of the system clock frequency. However, 1/4 of the system
clock frequency is recommended as taken from the actual specifications.
● External clock
When CS2 to CS0 are set to 111B and the external timer is selected, note the following:
If the external clock frequency is specified as f, the following baud rates are assumed:
Asynchronous (start-stop synchronization): f/16
CLK synchronization: f
Note that the maximum external clock frequency f is 2 MHz.
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20.6.2
Baud Rates Determined Using the Internal Timer
(16-bit Reload Timer)
This section describes the settings used when the internal clock supplied from 16-bit
reload timer is selected as the UART transmission/reception clock. It also shows the
baud rate calculation formulas.
■ Baud Rates Determined Using the Internal Timer (16-bit Reload Timer)
Writing 110B to the CS2 to CS0 bits of the serial mode control register (SMR0/SMR1) selects the baud rate
determined using the internal timer. Any baud rate can be set by specifying a prescaler division ratio and
reload value for 16-bit reload timer. Figure 20.6-2 shows the baud rate selection circuit for the internal
timer.
Figure 20.6-2 Baud rate selection circuit for the internal timer (16-bit reload timer output)
SMR0/SMR1 : CS2 to CS0 = 110B
(Selects the internal timer)
Clock selector
16-bit reload timer output
(the frequency is specified with
a prescaler division ratio and
reload value)
1/1 (clock synchronous)
1/16 (asynchronous)
Baud rate
SCKI
SMR0/SMR1 : MD1, MD0
(Synchronous or asynchronous clock selection)
● Baud rate calculation formulas
φ
Asynchronous baud rate =
X (n + 1) × 2 × 16
bps
φ
Synchronous baud rate =
X (n + 1) × 2
bps
φ: Machine clock frequency
X: Division ratio for the prescaler of 16-bit reload timer (21, 23, 25)
n: Reload value for 16-bit reload timer (0 to 65535)
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● Examples of setting baud rate and reload register values (machine clock: 7.3728 MHz)
Table 20.6-4 Baud rates and reload register values
Reload value
Baud rate
(bps)
Clock asynchronous
(start-stop synchronization)
Clock synchronous
X=21(machine
clock divided by 2)
X=23 (machine
clock divided by 8)
X=21(machine clock
divided by 2)
X=23 (machine
clock divided by 8)
38400
2
–
47
11
19200
5
–
95
23
9600
11
2
191
47
4800
23
5
383
95
2400
47
11
767
191
1200
95
23
1535
383
600
191
47
9071
767
300
383
95
6143
1535
X : Division ratio for the prescaler of 16-bit reload timer
– : Setting not allowed
Note :
The following settings are prohibited in clock synchronous mode.
N=1, n=0
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20.6.3
Baud Rates Determined Using the External Clock
This section describes the settings used when the external clock is selected as the
UART transmission and reception clock. It also shows the baud rate calculation
formulas.
■ Baud Rates Determined Using the External Clock
The following three settings are required to select the baud rate determined by using the external clock
input:
• Write 111B to the CS2 to CS0 bits of the serial mode control register (SMR0/SMR1) to select the baud
rate determined by using the external clock input.
• Set the P43/SCK0 and P74/SCK1 pins as input ports (DDR4: bit 3 = 0 and DDR7: bit 12 = 0).
• Write 0 to the SCKE bit of the serial mode control register (SMR0/SMR1) to set the pin as an external
clock input pin.
As shown in Figure 19.6.3-1, a baud rate is selected using the external clock input from the SCK1 pin. To
change the baud rate, the external input clock cycle must be changed because the internal division ratio is
fixed.
Figure 20.6-3 Baud rate selection circuit for the external clock
SMR0/SMR1 : CS2 to CS0 = 111B
(Selects the external timer)
Clock selector
P43/SCK0
P74/SCK1
1/1 (clock synchronous)
1/16 (asynchronous)
Pin
Baud rate
SCKI
SMR0/SMR1 : MD1, MD0
(Synchronous or asynchronous clock selection)
● Baud rate calculation formulas
Asynchronous baud rate = f/16
Synchronous baud rate = f
f: External clock frequency (up to 2 MHz)
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CHAPTER 20 UART
20.7
20.7
MB90820B Series
Operation of UART
UART operates in operation modes 0 and 2 for bidirectional serial communication and
in operation mode 1 for master-slave communication.
■ Operation of UART
● Operation modes
There are three UART operation modes: modes 0 to 2. As listed in Table 19.7-1, an operation mode can be
selected according to the inter-CPU connection method and data communication mode.
Table 20.7-1 UART operation mode
Data length
Operation mode
0
Normal mode
1
Multiprocessor mode
2
Normal mode
When parity is
disabled
When parity
is enabled
7 or 8 bits
8+1*1
bits
8 bits
Synchronization
mode
Stop bit
Asynchronous
–
Asynchronous
–
Synchronous
1 or 2 bits *2
None
– : Setting not possible.
*1 : "+1" indicates the address/data selection bit (A/D) for communication control.
*2 : During reception, only one stop bit can be detected.
Note :
Operation mode 1 of UART is used only from the master system during master-slave connection.
● Inter-CPU connection method
One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected.
For either connection method, the data length, whether to enable parity, and the synchronization method
must be common to all CPUs. Select an operation mode as follows:
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select
operation mode 0 for asynchronous mode and operation mode 2 for clock synchronous mode.
• Select operation mode 1 for the master-slave connection method and use it from the master system.
Select "When parity is disabled" for this connection method.
● Synchronization method
Asynchronous mode (start-stop synchronization) or clock synchronous mode can be selected in different
operation modes.
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● Signal mode
UART can treat data only in NRZ (Non-return to Zero) format.
● Operation enable bit
UART controls both transmission and reception using the operation enable bit for TXE (transmission) and
that for RXE (reception). If each of the operations is disabled, stop it as follows:
• If reception operation is disabled during reception (data is input to the reception shift register), finish
frame reception and store the received data in the serial input data register (SIDR0/SIDR1). Then stop
the reception operation.
• If the transmission operation is disabled during transmission (data is output from the transmission shift
register), wait until there is no data in the serial output data register (SODR0/SODR1) before stopping
the transmission operation.
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CHAPTER 20 UART
20.7
20.7.1
MB90820B Series
Operation in Asynchronous Mode
(Operation Modes 0 and 1)
When UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous mode is selected.
■ Operation in Asynchronous Mode
● Transmission/reception data format
Transmission/reception data begins with the start bit (L level) and ends with the stop bit (H level). The data
of the specified data bit length is transferred in LSB first mode.
• The data length can be set to 7 or 8 bits in normal mode for operation mode 0.
• In operation mode 1, the length of data is fixed to 8 bits with an address/data (A/D) selection bit added
instead of parity.
Figure 20.7-1 shows the transmission/reception data format in asynchronous mode.
Figure 20.7-1 Transmission/reception data format (operation modes 0 and 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
*
D6 D7/P SP
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP
* : D7 (bit 7) when parity is not provided
P (parity) when parity is provided
ST : Start bit
SP : Stop bit
AD : Address/data selection bit in operation mode 1 (multiprocessor mode)
● Transmission operation
Transmission data is written to the serial output data register (SODR0/SODR1) when the transmission data
empty flag bit (SSR0/SSR1: TDRE) is 1. This data is transmitted if the transmission operation is enabled
(SCR0/SCR1: TXE = 1).
The TDRE flag is again set to 1 when the transmission data is transferred to the transmission shift register
and its transmission starts. Then, the next piece of transmission data gets ready to be set. At this point, a
transmission interrupt request is output requesting that the next piece of transmission data be set in the
SODR0/SODR1 register if that request is enabled (SSR0/SSR1: TIE = 1). The TDRE flag is cleared to 0
when the transmission data is written to SODR0/SODR1.
● Reception operation
Reception operation is performed every time it is enabled (SCR0/SCR1: RXE = 1). When a start bit is
detected, a frame of data is received according to the data format specified by the control register (SCR0/
SCR1). After the frame has been received, the error flag is set if an error occurs, then the receive data full
flag bit (SSR0/SSR1: RDRF) is set to 1. At this point, a reception interrupt request is output if it is enabled
(SSR0/SSR1: TIE = 1).
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MB90820B Series
Check each flag of the input data register (SIDR0/SIDR1). If the reception is normal, read the input data
register (SIDR0/SIDR1). If an error is found, proceed to error handling. The RDRF flag is cleared to 0
every time receive data is read from SIDR0/SIDR1.
● Stop bit
For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only one that is
always checked.
● Error detection
• In operation mode 0, parity, overrun and framing errors can be detected.
• In operaion mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
● Parity bit
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide parity can
be specified using the PEN bit of the control register (SCR0/SCR1). Even or odd parity can also be
specified using the P bit of the control register (SCR0/SCR1). In operation mode 1 bit (asynchronous,
multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. Figure
20.7-2 shows both transmission and receive datas when parity bit is enabled.
Figure 20.7-2 Transmission and reception datas when parity bit is enabled
SIN0/SIN1
ST
SP
A parity error occurs
during reception with even parity
(SCR0/SCR1: P=0)
SP
Transmission with even parity
(SCR0/SCR1: P=0)
SP
Transmission with odd parity
(SCR0/SCR1: P=1)
1 0 1 1 0 0 0
SOT0/SOT1
ST
1 0 1 1 0 0 1
SOT0/SOT1
ST
1 0 1 1 0 0 0
Data
ST : Start bit
SP : Stop bit
Note : Parity is disabled in operation modes 1 and 2
CM44-10147-2E
Parity
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CHAPTER 20 UART
20.7
20.7.2
MB90820B Series
Operation in Clock Synchronous Mode (Operation Mode 2)
The clock synchronous method is used for UART operation mode 2.
■ Operation in Clock Synchronous Mode (Operation Mode 2)
● Transmission and reception data format
In clock synchronous mode, 8-bit data is transmitted and received using the LSB first method, in which
start and stop bits are not added. Figure 20.7-3 shows the transmission and reception data format in clock
synchronous mode.
Figure 20.7-3 Transmission and reception data format (operation mode 2)
Transmission data writing
Mark level
Transmitting and reception
clock
RXE, TXE
Transmission and reception
data
1
0
1
1
0
0
1
LSB
0
MSB
(Mode 2)
01001101B is transferred.
● Clock supply
In clock synchronous mode (I/O extended serial), as many clocks as the number of transmission and
reception bits must be supplied.
• When the internal clock (dedicated baud rate generator or internal timer) is selected, the data receiving
synchronous clocks is generated automatically if data is transmitted.
• When the external clock is selected, confirm that the transmission side UART output data register
(SODR0/SODR1) contains data (SSR0/SSR1: TDRE = 0). Then, clocks for just 1 byte must be
supplied from outside.
The mark level (H) must be retained before transmission starts and after it is complete.
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
● Initialization
The following shows the set values of each control register using the synchronous mode:
[Serial mode control register (SMR0/SMR1)]
MD1, MD0:10B
CS2, CS1, CS0:Specify clock input using the clock selector.
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SCKE:1 for dedicated baud rate generator or internal timer
0 for clock output and external clock (clock input)
SOE:1 for transmission; 0 for reception only
[Serial control register (SCR0/SCR1)]
PEN:0
P, SBL, ADThese bits make no sense.
CL1 (8-bit data)
REC:0 (the error flag is cleared for initialization.)
RXE, TXE:At least one of the two bits is set to 1.
[Serial status register (SSR0/SSR1)]
RIE:1 when using interrupts; 0 when using no interrupts.
TIE:1 when using interrupts; 0 when using no interrupts.
● Starting communication
Write data to the serial output data register (SODR0/SODR1) to start communication. Temporary data
must be written to SODR0/SODR1 to start communication for reception.
● Ending communication
The RDRF flag of the serial status register (SSR0/SSR1) is set to 1 when transmission or reception of a
data frame is completed. During reception, check the overrun error flag bit (SSR0/SSR1: ORE) to see if
communication is performing normally.
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CHAPTER 20 UART
20.7
20.7.3
MB90820B Series
Bidirectional Communication Function (Normal Mode)
In operation mode 0 or 2, normal serial bidirectional communication (one-to-one
connection) is available. Select operation mode 0 for asynchronous communication
and operation mode 2 for clock synchronous communication.
■ Bidirectional Communication Function
The settings shown in Figure 20.7-4 are required to operate UART in normal mode (operation mode 0 or
2).
Figure 20.7-4 Settings for UART operation mode 0 or 2
SCR0/SCR1,
SMR0/SMR1
Mode 0 ⇒
Mode 2 ⇒
SSR0/SSR1,
SIDR0/SIDR1,
SODR0/SODR1
Mode 0 ⇒
Mode 2 ⇒
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN
P
SBL
CL
AD
REC
RXE
TXE
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
1
X
X
0
0
0
1
0
0
0
X
X
PE
ORE
FRE
X
RDRF TDRE
BDS
RIE
TIE
X
X
Set conversion data (during writing).
Retain receive data (during reading).
X
DDR4 (UART0)
DDR6 (UART1)
: Bit used
X : Bit not used
1 : Set 1
0 : Set 0
● Inter-CPU connection
Figure 20.7-5shows interconnect two CPU’s.
Figure 20.7-5 Connection example of UART bidirectional communication
SOT
SOT
SIN
SCK
Ouput
Input
SCK
CPU-2
CPU-1
534
SIN
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CHAPTER 20 UART
20.7
MB90820B Series
● Communication procedure
Communication starts from the transmitting system at an optional timing when transmission data has been
prepared. An ANS is returned periodically (byte by byte in this example) when the receiving system
receives transmission data. Figure 20.7-6 shows an example of a bidirectional communication flowchart.
Figure 20.7-6 Example of bidirectional communication flowchart
(Transmitting system)
(Receiving system)
Start
Start
Set operation mode
(0 or 2)
Set operation mode(same mode
as that for the transmitting side)
Set 1-byte data in UODR
and perform communication
Data transmission
Any received data?
NO
YES
Any received data?
NO
Read and process received data.
YES
Data transmission
Read and process received data.
(ANS)
CM44-10147-2E
Transmit 1-byte data
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CHAPTER 20 UART
20.7
20.7.4
MB90820B Series
Master-slave Communication Function (Multiprocessor
Mode)
With UART, communication with multiple CPUs connected in master-slave mode is available
in operation mode 1. However, UART can be used only from the master system.
■ Master-slave Communication Function
The settings shown in Figure 20.7-7 are required to operate UART in multiprocessor mode (operation
mode 1).
Figure 20.7-7 Settings for UART operation mode 1
SCR0/SCR1,
SMR0/SMR1
SSR0/SSR1,
SIDR0/SIDR1,
SODR0/SOD1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN
P
SBL
CL
AD
REC
RXE
TXE
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
0
X
0
0
PE
ORE
0
1
FRE
RDRF TDRE
BDS
RIE
TIE
X
Set transmission data (during writing).
Retain receive data (during reading).
X
DDR4 (UART0)
DDR6 (UART1)
:
X:
1:
0:
:
Bit used
Bit not used
Set 1
Set 0
Set 0 to use an input pin
● Inter-CPU connection
As shown in Figure 20.7-8 , a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. UART can be used only from the master CPU.
Figure 20.7-8 Connection example of UART master-slave communication
SOT0/SOT1
SIN0/SIN1
Master CPU
SOT
SIN
Slave CPU #0
536
SOT
SIN
Slave CPU #1
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CHAPTER 20 UART
20.7
MB90820B Series
● Function selection
Select the operation mode and communication mode for master-slave communication as shown in Table
20.7-2 .
Table 20.7-2 Selection of the master-slave communication function
Operation mode
Data
Master CPU
Address
transmission
and reception
Data
transmission
and reception
Operaiton
Mode 1
Parity
Synchronizatio
n method
Stop bit
None
Asynchronous
1 or 2 bits
Slave CPU
AD =1
+
8-bit address
–
AD =0
+
8-bit data
● Communication procedure
When the master CPU transmits address data, communication starts. The AD bit in the address data is set
to 1, and the communication destination slave CPU is selected. Each slave CPU checks the address data
using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU
communicates with the master CPU (ordinary data).
Figure 20.7-9 shows a flowchart of master-slave communication (multiprocessor mode).
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CHAPTER 20 UART
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MB90820B Series
Figure 20.7-9 Master-slave communication flowchart
(Master CPU)
Start
Select operation mode 1
Set the data for selecting the slave
CPUs in D0 to D7 and set “1” in AD
to transfer one byte
Set “0” in AD
Reception is enabled
Communication with the slave CPU
NO
End communication?
YES
Communicate with
other slave CPU?
NO
YES
Reception is disabled
End
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CHAPTER 20 UART
20.8
MB90820B Series
20.8
Usage Notes on UART
Notes on using UART are given below.
■ Notes on Using UART
● Enabling operations
In UART, the serial control register (SCR0/SCR1) has both TXE (transmission) and RXE (reception)
operation enable bits. Both transmission and reception operations must be enabled before the transfer starts
because they have been disabled as the default value (initial value). The transfer can also be canceled by
disabling its operation as required.
● Operation mode setting
Set the operation mode while the system is not operating after the operation enable bit is set to disabled. If
the mode is set during transmission or reception, the transmission or reception data is not guaranteed.
● Synchronous mode
UART clock synchronous mode (operation mode 2) uses clock control (I/O extended serial) mode, in
which start and stop bits are not added to the data.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR0/SSR1: TRE) is 1 (no transmission
data and transmission data write enable state). A transmission interrupt request is generated as soon as the
transmission interrupt requests are enabled (SSR0/SSR1: TIE = 1). Be sure to set the TIE flag to 1 after
setting the transmission data.
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CHAPTER 20 UART
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CHAPTER 21
ROM CORRECTION
FUNCTION
This chapter describes the functions and operation of
the ROM correction function.
21.1 Overview of the ROM Correction Function
21.2 Block Diagram of ROM Correction Function
21.3 ROM Correction Function Registers
21.4 Operation of the ROM Correction Function
21.5 Example of Using ROM Correction Function
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CHAPTER 21 ROM CORRECTION FUNCTION
21.1
21.1
MB90820B Series
Overview of the ROM Correction Function
An instruction code to be read by the CPU is forcibly replaced with an INT9 instruction
code (01H) when the corresponding address is equal to the value set in a program
address detect register. A program patch application function can be implemented by
processing with the INT #9 interrupt routine.
■ Program Address Detection Registers (x 2)
There are two program address detection registers (PADR0/PADR1), each is provided with an interrupt
enable bit and interrupt flag.
■ ROM Correction Interrupts
When the interrupt enable bit is "1", the value set in the program address detection register is compared
with the address. If the value matches the addresss, "1" is set in the interrupt flag bit and the instruction
code to be read to the CPU is forcibly replaced with an INT9 instruction code.
The interrupt flag bit is cleared to "0" by writing "0" to it using an instruction.
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CHAPTER 21 ROM CORRECTION FUNCTION
21.2
MB90820B Series
21.2
Block Diagram of ROM Correction Function
The block diagram of ROM correction function is shown as below.
■ Block Diagram of ROM Correction Function
Figure 21.2-1 Block diagram of ROM correction function
Program
address latch
Comparator
INT9
command
F2MC-16LX bus
Address detection register 0/1
CM44-10147-2E
F2MC-16LX
AD0E/AD1E AD0D/AD1D
PACSR
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CPU
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CHAPTER 21 ROM CORRECTION FUNCTION
21.3
21.3
MB90820B Series
ROM Correction Function Registers
The section lists the ROM correction function registers.
■ ROM Correction Function Registers
Figure 21.3-1 Registers of ROM Correction Function
Program Address Detection Register 0/1
Upper Byte
Middle Byte
Lower Byte
PADRH0
PADRM0
PADRL0
PADRH1
PADRM1
PADRL1
(R/W)
(R/W)
(R/W)
(XXXXXXXXB) (XXXXXXXXB) (XXXXXXXXB)
Address : 1FF2H/1FF1H/1FF0H
Address : 1FF5H/1FF4H/1FF3H
Read/write ⇒
Initial value ⇒
PADR0
PADR1
Program Address Detection Control Status Register
Address:
bit
PACSR 009EH
Read/write ⇒
544
7
−
(−)
6
−
(−)
5
−
(−)
4
−
(− )
3
AD1E
(R/W)
2
AD1D
(R/W)
1
AD0E
(R/W)
FUJITSU MICROELECTRONICS LIMITED
0
AD0D
(R/W)
Initial value
XXXX0000B
CM44-10147-2E
CHAPTER 21 ROM CORRECTION FUNCTION
21.3
MB90820B Series
21.3.1
Program Address Detection Register (PADR0/PADR1)
The program address detection register (PADR0/PADR1) is a 24-bit register and used to
store the address to be compared with internal address bus.
■ Program Address Detection Register 0/1 (PADR0/PADR1)
Figure 21.3-2 Program address detection register
Program Address Detection Register 0/1
Address : 1FF2H/1FF1H/1FF0H
Address : 1FF5H/1FF4H/1FF3H
Read/write ⇒
Initial value ⇒
Upper Byte
Middle Byte
Lower Byte
PADRH0
PADRM0
PADRL0
PADRH1
PADRM1
PADRL1
(R/W)
(R/W)
(R/W)
(XXXXXXXXB) (XXXXXXXXB) (XXXXXXXXB)
PADR0
PADR1
The value written to this register is compared with a target address. If the value matches the address, and
the corresponding interrupt enable bit of the PACSR register is "1", the corresponding interrupt bit is set to
"1" to request the CPU to generate an INT9 instruction. If the corresponding interrupt enable bit is "0", no
operation is performed.
Table 21.3-1 lists the correspondence between the program address detection register and PACSR.
Table 21.3-1 Correspondence between program address detection register and PACSR
CM44-10147-2E
Program address detection register
Interrupt enable bit
Interrupt bit
PADR0
AD0E
AD0D
PADR1
AD1E
AD1D
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CHAPTER 21 ROM CORRECTION FUNCTION
21.3
MB90820B Series
Program Address Detection Control Status Register
(PACSR)
21.3.2
The program address detection control status register (PACSR) is an 8-bit register and
used to control the operation of ROM correction function.
■ Program Address Detection Control Status Register (PACSR)
Figure 21.3-3 Program address detection control status register
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00009EH
—
—
—
—
AD1E
AD1D
AD0E
AD0D
XXXX0000B
—
—
—
—
R/W
R/W
R/W
R/W
Address detection flag 0 bit
AD0D
Read
Write
0
No address compare match
Clear this bit to "0"
1
Address compare match
No effect
AD0E
Address detection register 0 enable bit
0
Disable interrupt request
1
Enable interrupt request
Address detection flag 1 bit
AD1D
X
Read
Write
0
No address compare match
Clear this bit to "0"
1
Address compare match
No effect
AD1E
Address detection register 1 enable bit
0
Disable interrupt request
1
Enable interrupt request
: Undefined
R/W : Readable and writable
—
: Undefined
: Initial value
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CHAPTER 21 ROM CORRECTION FUNCTION
21.3
MB90820B Series
Table 21.3-2 Program address detection control status register
Bit name
CM44-10147-2E
bit7
to
bit4
Reserved bits
bit3
AD1E:
Address detection
register 1 enable bit
bit2
AD1D:
Address detection
flag 1 bit
bit1
AD0E:
Address detection
register 0 enable bit
bit0
AD0D:
Address detection
flag 0 bit
Function
•
Always write "0" to these bits.
•
•
PADR1 operation enable bit.
When this bit is "1", the value set in the PADR1 register is compared
with the address. If the two values are equal, an INT9 instruction is
generated and the AD1D bit is set to "1".
•
•
PADR1 address match detection bit.
This bit is set to "1" to indicate that the value set in the PADR1
register matches the address. It is cleared to "0" by writing "0" to it.
It is left unchanged by writing "1" to it.
•
•
PADR0 operation enable bit.
When this bit is "1", the value set in the PADR0 register is compared
to the address. If the two values are equal, an INT9 instruction is
generated and the AD0D bit is set to "1".
•
•
PADR0 address match detection bit.
This bit is set to "1" to indicate that the value set in the PADR0
register is equal to the address. It is cleared to "0" by writing "0" to
it. It is left unchanged by writing "1" to it.
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CHAPTER 21 ROM CORRECTION FUNCTION
21.4
21.4
MB90820B Series
Operation of the ROM Correction Function
If the program counter specifies the same address as that in program address detection
register (PADR), the INT9 instruction is executed. The ROM correction function can be
done by processing the INT9 instruction routine.
■ Operation of the ROM Correction Function
An instruction code to be read by the CPU is forcibly replaced with an INT9 instruction code (01H) when
the corresponding address is equal to the value set in an address detection register. Therefore, the CPU
executes the INT9 instruction when executing the set instruction.
A program patch application function can be implemented by processing with the INT #9 interrupt routine.
There are two address detection registers, of which each is provided with an interrupt enable bit and
interrupt flag. When the address is equal to the value set in the address detection register, and the interrupt
enable bit is "1", assume the following: the interrupt flag is set to "1", and the instruction code to be read
by the CPU is forcibly replaced with the INT9 instruction code. The interrupt flag is cleared to "0" by
writing "0" to it using an instruction.
Notes:
• The address match detection function fails if an address later than the first byte of the instruction
is set in the address detection register. The value in the set address is replaced with "01H", so a
wrong instruction is executed or an invalid address is accessed. Before changing the value set in
the address detection register, set the interrupt enable bit to "0". If data is written while the
interrupt enable bit is "1", the address may be wrongly detected during writing, causing a
malfunction.
• The program address detection register exists at 001FF0H to 001FF5H that overlaps with the
RAM area of MB90F828B, preventing RAM access when using this feature on MB90F828B.
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CHAPTER 21 ROM CORRECTION FUNCTION
21.5
MB90820B Series
21.5
Example of Using ROM Correction Function
This section contains example of using the address match detection function.
■ System Configuration
Figure 21.5-1 System configuration example
E2PROM
MCU
F2MC-16LX
Pull-up resistor
Connector (UART)
SIN
■ E2PROM Memory Map
Table 20.5-1 lists the E2PROM memory map.
Table 21.5-1 E2PROM memory map
Address
0000H
Number of bytes for patch program No. 0
(0 for no program error)
0001H
Bit 7 to bit 0 of program address No. 0
0002H
Bit 15 to bit 8 of program address No. 0
0003H
Bit 24 to bit 16 of program address No. 0
0004H
Number of bytes for patch program No. 1
(0 for no program error)
0005H
Bit 7 to bit 0 of program address No. 1
0006H
Bit 15 to bit 8 of program address No. 1
0007H
Bit 24 to bit 16 of program address No. 1
to 0010H+
Number of bytes for patch program No. 0
CM44-10147-2E
Meaning
Original of patch program No. 0
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CHAPTER 21 ROM CORRECTION FUNCTION
21.5
MB90820B Series
■ Initial State
The contents of E2PROM are all 0’s.
■ If a Program Error Occurs
The original of a patch program and its address is transferred to the MCU via the connector (UART). The
MCU writes the information to E2PROM.
■ Reset Sequence
After the reset sequence is completed, the MCU reads the value of E2PROM. If the number of bytes for the
patch program is not 0, the MCU reads the original patch program and writes it to RAM. Then, the MCU
sets the program address to PADR0 or PADR1 and enables the program to run. The first address of the
program written to RAM is saved in RAM as specified for each address detection register.
■ INT9 Interrupt
During execution of an interrupt routine, control checks the interrupt flag for an address in which an
interrupt was enabled and branches to the corresponding program. The information stacked by the interrupt
is deleted. The interrupt flag is also cleared.
Figure 21.5-2 System configuration example
MB90820B series
FFFFFFH
(3)
Abnormal program
(1)
PC = Trigger address
ROM
External E2PROM
· Number of program byte
· Interrupt trigger address
· Corrected program
Register setting
for ROM correction
Data sent via UART
RAM
Corrected program
(2)
000000H
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CM44-10147-2E
CHAPTER 21 ROM CORRECTION FUNCTION
21.5
MB90820B Series
Figure 21.5-3 Flowchart of program patch processing
Reset
Read the 00H of E2PROM
INT9
YES
2
0000H (E PROM) = 0
NO
Clear interrupt program
Read the address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
To patch program
JMP 000400H
Read the patch program
0010H to 0090H (E2PROM)
MOV
000400H to 000480H (MCU)
Patch program execution
000400H to 000480H
Enable comparison
End of patch program
JMP FF0050H
MOV PACSR, #02H
Normal program execution
MB90820B
FFFFFFH
PC = PADR0
NO
YES
INT9
FF0050H
E2PROM
ROM
Abnormal program
FFFFH
FF0000H
0090H
FE0000H
Patch program
0010H
001100H
Stack area
Lower program address: 00
RAM area
0003H
Middle program address: 00
0002H
RAM
Upper program address: 00
0001H
0000H
CM44-10147-2E
Size of patch
program in byte: 80
FUJITSU MICROELECTRONICS LIMITED
000480H
Patch program
000400H
RAM / register area
000100H
I/O area
000000H
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CHAPTER 21 ROM CORRECTION FUNCTION
21.5
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MB90820B Series
CM44-10147-2E
CHAPTER 22
ROM MIRRORING FUNCTION
SELECTION MODULE
This chapter explains the function and operation of the
MB90820B series ROM mirroring function selection
module.
22.1 Overview of the ROM Mirroring Function Selection Module
22.2 ROM Mirroring Function Selection Register (ROMM)
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CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.1
22.1
MB90820B Series
Overview of the ROM Mirroring Function Selection Module
The ROM mirroring function selection module can access bank FF located in ROM from
bank 00 by setting the register.
■ ROM Mirroring Function Selection Module Register
ROM Mirror Function Selection Register
Address:
bit
ROMM 0006FH
Read/write ⇒
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
(–)
(–)
(–)
(–)
(–)
(–)
(–)
MI
(W)
Initial value
XXXXXXX1B
■ ROM Mirroring Function Selection Module Block Diagram
Figure 22.1-1 ROM mirroring function selection module block diagram
F2MC-16LX bus
ROM mirroring register
Address area
FF bank
00 bank
ROM
554
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CM44-10147-2E
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.2
MB90820B Series
22.2
ROM Mirroring Function Selection Register (ROMM)
The ROM mirroring function selection register (ROMM) is used to enable mirroring
function.
■ ROM Mirroring Function Selection Register (ROMM)
Figure 22.2-1 ROM mirroring function selection register (ROMM)
Address
00006FH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
—
—
—
—
—
—
—
MI
XXXXXXX1B
—
—
—
—
—
—
—
W
MI
X
: Undefined
R/W : Readable and writable
—
Mirroring enable bit
0
Disable mirroring function
1
Enable mirroring function
: Undefined
: Initial value
Table 22.2-1 Function of ROM mirroring function selection register (ROMM)
Bit name
CM44-10147-2E
bit15
to
bit9
Undefind bits
bit8
MI:
Mirroring enable
bit
Function
•
•
The read value is undefined.
Always write "0" to these bits.
•
When "1" has been written to this bit, the ROM data in bank FF can
be read from bank 00.
When "0" has been written to this bit, the function is disabled in
bank 00. This bit is write only.
•
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CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.2
MB90820B Series
Note :
Bank 00 accesses FF8000H to FFFFFFH from 008000H to 00FFFFH. Therefore, FFF000H to FF7FFFH
cannot be accessed even by selecting the ROM mirroring function.
MB90822B
MB90823B
MB90F822B
MB90F823B
MB90F828B
MB90V820B
Address 1
FF0000H
FE0000H
FF0000H
FE0000H
FE0000H
FE0000H
Address 2
0010FFH
0010FFH
0010FFH
0010FFH
0020FFH
0040FFH
Figure 22.2-2 Memory space
Address
FFFFFFH
Address 1
ROM area
ROM area
010000H
ROM area
008000H
Address 2
RAM area
RAM area
I/O area
I/O area
When MI = 1
When MI = 0
000100H
0000F0H
000000H
556
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Internal
area
CM44-10147-2E
CHAPTER 23
512K / 1024K BIT FLASH
MEMORY
The following explains the functions and operations of
the 512K / 1024K bit flash memory.
23.1 Overview of the 512K / 1024K Bit Flash Memory
23.2 512K / 1024K Bit Flash Memory Sector Configuration
23.3 Flash Memory Control Status Register (FMCS)
23.4 Method of Starting the Automatic Algorithm in Flash Memory
23.5 Verifying Automatic Algorithm Execution Status
23.6 Detailed Explanation on the Flash Memory Write/Delete
23.7 Flash Security Feature
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.1
23.1
MB90820B Series
Overview of the 512K / 1024K Bit Flash Memory
Three methods of data writing/deleting to the 512K/1024K bit flash memory are
provided:
Parallel writer (MODEL1890A made by Minato Electronics)
Serial dedicated writer (AF-200 made by Yokogawa Digital Computer)
Write/delete operation by program execution
This chapter provides an explanation for the above item "3. Write/delete operation by
program execution".
■ Overview of the 512K/1024K Bit Flash Memory
The 512K bit flash memory is allocated in the FF bank on the CPU memory map while 1024K bit flash
memory is allocated in FE and FF bank. The function of the flash memory interface circuit enables the
read/access or program access from the CPU to the flash memory, same as the mask ROM. The write/
delete operation to the flash memory can be executed through the flash memory interface circuit by
executing an instruction issued from the CPU. Therefore, the flash memory mounted can be rewritten
under the control of the internal CPU, so that the program or data can be upgraded or updated more
efficiently. However, no selector operation such as the enable sector protect can be used.
■ Characteristics of the 512K / 1024K Bit Flash Memory
• 512K Bit: 64K words × 8 bits/32K words × 16 bits (16K+8K+8K+32K) sector configuration
• 1024K Bit: 128K words × 8 bits/64K words × 16 bits (64K+16K+8K+8K+32K) sector configuration
• Automatic program algorithm (same as the Embedded Algorithm : MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (Sectors can be freely combined)
• Number of write/delete operations 10,000 times guaranteed
• Flash security feature
"Embedded Algorithm" is the trademark of Advanced Micro Device
■ Procedure for Writing/Deleting the Data to the Flash Memory
The write/delete operation of the flash memory cannot be executed simultaneously. In executing the data
write/delete operation in the flash memory, only the write operation can be executed, by copying a program
on the flash memory to RAM and executing the program.
■ Register on the Flash Memory
Figure 23.1-1 Flash memory control status register (FMCS)
bit
Address:0000AEH
Read/write
558
7
6
5
4
3
2
1
0
Initial value
INTE
RDYINT
WE
RDY
Reserved
Reserved
Reserved
Reserved
000x0000B
(R/W)
(R/W)
(R/W)
(R)
−
−
−
−
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CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.2
MB90820B Series
23.2
512K / 1024K Bit Flash Memory Sector Configuration
Figure 23.2-1 and figure 23.2-2 shows the sector configuration in the 512K bit flash
memory. The address indicated in figure 23.2-1 and figure 23.2-2 is classified into the
upper address and lower address of each sector.
■ Sector Configuration
When accessing the 512Kbit flash memory from the CPU, four sector addresses, SA0 to SA3, are allocated
in the FF bank register.
Figure 23.2-1 512K Bit Flash Memory Sector Configuration
Flash memory
SA3 (16 Kbytes)
SA2 (8 Kbytes)
SA1 (8 Kbytes)
SA0 (32 Kbytes)
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
70000H
When accessing the 1024Kbit flash memory from the CPU, five sector addresses, SA0 to SA4, are
allocated in the FE and FF bank register.
Figure 23.2-2 1024K Bit Flash Memory Sector Configuration
Flash memory
SA4 (16 Kbytes)
SA3 (8 Kbytes)
SA2 (8 Kbytes)
SA1 (32 Kbytes)
CPU address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
77FFFH
FF7FFFH
FF0000H
SA0 (64 Kbytes)
*Writer address
FEFFFFH
70000H
6FFFFH
FE0000H
60000H
* Writer address
The writer address is equivalent to the CPU address when writing the data to the flash memory using the
parallel writer. If the write/delete operation is executed using the general-purpose writer, the write/delete
operation is executed using this address.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.3
23.3
MB90820B Series
Flash Memory Control Status Register (FMCS)
Figure 22.3-1 shows the function of the flash memory control status register (FMCS).
■ Flash Memory Control Status Register (FMCS)
Figure 23.3-1 Flash memory control status register (FMCS)
Address
bit7
bit6
bit5
bit4
0000C6H INTE RDYINT
WE
RDY
R/W
R/W
R
R/W
bit3
bit2
bit1
RESV RESV RESV RESV
−
−
−
0
Always write “0” to these bits.
Flash memory write/delete status bit
0
Flash in write/delete operation.
1
Write/delete operation terminated.
WE
Flash memory write/delete enable bit
0
Disable flash memory area write/delete
1
Enable flash memory area write/delete
RDYINT
—
: Undefind
Flash memory operation flag bit
0
Flash memory in write/delete operation
1
Flash memory write/delete operation terminated.
INTE
: Read only
000X0000B
Reserved bits.
RDY
R
Initial value
−
RESV
R/W : Read and write
bit0
Flash memory write/delete interrupt enable bit
0
Disable interrupt
1
Enable interrupt
: Initial value
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CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.3
MB90820B Series
Table 23.3-1 Function of flash memory control status register (FMCS)
Bit name
Function
INTE:
Flash memory
interrupt/delete
Interrupt Enable
bit
This bit generates an interrupt to the CPU when the write/delete operation to the flash
memory is terminated.
When the INTE bit is "1" and the RDYINT bit is "1", an interrupt is generated and sent to the
CPU. If the INTE bit is "0", no interrupt is generated:
0: Interrupt disabled when the write/delete operation is terminated.
1: Interrupt enabled when the write/delete operation is terminated.
RDYINT:
Flash memory
operation flag bit
This bit indicates the flash memory operating status.
After the write/delete to the flash memory is terminated, this bit is set to "1". While this bit is
"0" after the end of write/delete operation to the flash memory, the flash memory cannot be
written or deleted. After the write/delete operation is terminated and this bit is set to "1", the
flash memory can be written or deleted. This bit is cleared to "0" by writing "0" and the
writing of "1" is ignored. At the termination time of the automatic algorithm in the flash
memory (see Section "23.4 Method of Starting the Automatic Algorithm in Flash Memory"),
this bit is set to "1". While using the read modify write (RMW) instruction, "1" can be read
at any time.
0: During the write/delete operation
1: Write/delete operation terminated (An interrupt request is generated)
bit5
WE:
Flash memory
write/delete
enable bit
This bit is the write enable bit for the flash memory area.
When this bit is "1", the write instruction after issuing command sequence to FF bank (see
Section "23.4 Method of Starting the Automatic Algorithm in Flash Memory") is equivalent to
writing to the flash memory area. When this bit is "0", no write/delete signal is generated.
This bit is used when the flash memory write/delete command is started.
0: Flash memory write/delete disabled
1: Flash memory write/delete enabled
bit4
RDY:
Flash memory
write/delete status
bit
This bit is the flash memory write/delete permission bit.
While this bit is "0", the write/delete cannot be executed to the flash memory. Even in this
state, however, suspend commands such as the read/reset command and the sector deletion
temporary stop can be accepted.
0: During the write/delete operation
1: Write/delete operation terminated (Next data write/delete operation permitted)
bit3
to
bit0
RESV:
Reserved bits
Always write "0" to these bits.
bit7
bit6
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.3
MB90820B Series
Note :
The RDYINT and RDY bits do not change at the same time. Creat a program to determine the
termination of write/delete operation using either of bits.
Automatic algorithm
Termination time
RDYINT bit
RDY bit
1 machine cycle
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.4
MB90820B Series
23.4
Method of Starting the Automatic Algorithm in Flash Memory
There are four types of commands for starting the automatic algorithm in the flash
memory, i.e., the read/reset command, write command, and chip deletion command. In
addition, the sector deletion command can be temporarily stopped and restarted.
■ Command Sequence Table
Table 23.4-1 lists the commands to be used for writing/deleting the data to the flash memory. All the data
is written to the command register in units of bytes, though it should be accessed and written in units of
words.
In this case, the data in the upper bytes written in units of word is ignored.
Table 23.4-1 Command Sequence Table
Bus
write
access
1st bus write cycle
2nd bus write cycle
Address
Address
Data
Address
Data
Address
Read/reset*
1
YYYXXXH XXF0H
-
-
-
-
Read/reset*
4
YYYAAAH XXAAH
YYY554H
XX55H
YYYAAAH
Write
4
YYYAAAH XXAAH
YYY554H
XX55H
Chip erase
6
YYYAAAH XXAAH
YYY554H
Sector erase
6
YYYAAAH XXAAH
YYY554H
Command
sequence
Data
3rd bus write cycle
4th bus write cycle
5th bus write cycle
6th bus write cycle
Data
Address
Data
Address
Data
-
-
-
-
-
-
XXF0H
RA
RD
-
-
-
-
YYYAAAH
XXA0H
PA
PD
-
-
-
-
XX55H
YYYAAAH
XX80H
YYYAAAH
XXAAH
YYY554H
XX55H
YYYAAAH
XX10H
XX55H
YYYAAAH
XX80H
YYYAAAH
XXAAH
YYY554H
XX55H
SA
XX30H
Sector erase suspend
Entering address YYYXXXH and data "XXB0H" suspends during sector erasing.
Sector erase resume
Entering address YYYXXXH annd data "XX30H" resumes suspended sector erasing.
RA:
PA:
SA:
RD:
PD:
YYY:
*:
Read address
Write address
Sector address (specify an arbitray address in sector)
Read data
Write data
Upper 12 bits of an arbitrary address in the flash memory area
Both of the two types of read/reset command can reset the flash memory to read mode
Note :
Addresses in the table are the values in the CPU memory map. All addresses and data are
hexadecimal values. However, "X" is an arbitrary value.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
23.5
MB90820B Series
Verifying Automatic Algorithm Execution Status
The flash memory contains the hardware for posting the internal flash memory
operating status or the flash memory operation completion, because the automatic
algorithm executes the sequence of data writing/deleting procedures. This automatic
algorithm can verify the internal flash memory operating status, depending on the
following hardware sequence.
■ Hardware Sequence Flag
The hardware sequence flag consists of the four flag bits, DQ7, DQ6, DQ5, and DQ3. These flag bits have
the data polling flag (DQ7) function, toggle bit flag (DQ6) function, time limit exceeded flag (DQ5)
function, and sector deletion timer flag (DQ3) function, respectively. These functions can verify whether
the write/chip sector deletion is terminated or whether the deletion code write is valid.
The hardware sequence flag can be referred by accessing/reading the address of the target sector in the
flash memory, after setting the command sequence (see Section "23.4 Method of Starting the Automatic
Algorithm in Flash Memory"). Table 23.5-1 indicates the hardware sequence flag bit allocation.
Table 23.5-1 Hardware Sequence Flag Bit Allocation
Bit no.
Hardware
sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
-
-
-
It can be determined whether automatic write/chip sector deletion is being performed, depending on the end
of write processing, by checking the hardware sequence flag or the RDY bit in the flash memory control
status register (FMCS). After the write/delete operation is terminated, the flash memory is returned to the
read/reset status. To actually create a program, it should be verified whether automatic write/delete
operation is terminated, depending on any flag, and the next operation such as the data reading should be
executed. Also, it can be verified whether the second sector deletion code write command or later
commands are valid, depending on the hardware sequence flag. The following explains the hardware
sequence flags. Table 23.5-2 lists the hardware sequence flag functions.
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CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
MB90820B Series
Table 23.5-2 Hardware Sequence Flag Function List
State
Status
transition
during
normal
operation
Abnormal
operation
CM44-10147-2E
DQ7
DQ6
DQ5
DQ3
Write operation -->
Write completion
(when the write address
is specified)
DQ7 -->
DATA:7
Toggle -->
DATA:6
0 -->
DATA:5
0 -->
DATA:3
Chip/sector deletion
operation --> Deletion
completion
0 --> 1
Toggle -->
Stop
0 --> 1
1
Sector deletion wait -->
Deletion start
0
Toggle
0
0 --> 1
Deletion processing -->
Sector deletion
temporary stop (sector
being deleted)
0 --> 1
Toggle --> 1
0
1 --> 0
Sector deletion
temporary stop -->
Deletion restart (sector
being deleted)
1 --> 0
1 --> Toggle
0
0 --> 1
While the sector
deletion is being
temporarily stopped -->
(sector not being
deleted)
DATA:7
DATA:6
DATA:5
DATA:3
Write operation
DQ7
Toggle
1
0
Chip/sector deletion
operation
0
Toggle
1
1
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
23.5.1
MB90820B Series
Data Polling Flag (DQ7)
The data polling flag (DQ7) indicates whether the automatic algorithm is being executed
or has been terminated, using the data polling function. Table 23.5-3 shows the data
polling flag status transition.
■ When the Write Operation is Executed.
When the read/access is executed during automatic write algorithm execution, the flash memory outputs the
reverse data of bit 7 in the last-written data, irrespective of the specified address. When the read/access is
executed at the end of the automatic write algorithm, the flash memory outputs the data of bit 7 in the
specified read address.
■ When the Chip/Sector Deletion Operation is Executed.
When the read/access is executed during the chip/sector deletion algorithm execution, the flash memory
outputs "0" from the sector being deleted, or irrespective of the specified address during the chip deletion.
Similarly, the flash memory outputs "1" at the end of chip/sector deletion algorithm.
■ When the Sector Deletion Temporary Stop is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address is the sector being deleted. However, the flash memory outputs the data
of bit 7 (DATA:7) for the specified read address, if the specified address is not the sector being deleted. By
referring this together with the toggle bit flag (DQ6), it can be determined whether the current sector is in
the temporary stop state or which sector is being deleted.
Note :
When the automatic algorithm is started, the read/access to the specified address is ignored. As for
the data reading, the end of data polling flag (DQ7) is posted, and then other data bit can be output.
Therefore, the data read operation after the end of the automatic algorithm should be executed next
to the read/access after verifying the end of data polling flag.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
MB90820B Series
Table 23.5-3 shows the data polling flag status transition.
Table 23.5-3 Data Polling Flag Station Transition
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ7
DQ7-->DATA:7
0-->1
0
0-->1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:7
- Status transition during abnormal operation
CM44-10147-2E
Operating
status
Write operation
Chip/sector
deletion
operation
DQ7
DQ7
0
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
23.5.2
MB90820B Series
Toggle Bit Flag (DQ6)
The toggle bit flag (DQ6) specifies whether the automatic algorithm is being executed or
has been terminated, using the toggle bit function, the same as the data polling flag.
Table 23.5-4 shows the toggle bit flag status transition.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the continuous read/access is executed during the automatic write algorithm or chip/sector deletion
algorithm execution, the flash memory outputs the toggle status, in which "1" and "0" are alternately output
for each read operation, irrespective of the specified address. If the continuous read/access is executed at
the end of the automatic write algorithm or chip/sector deletion algorithm, the flash memory stops the
toggle operation in bit 6 and outputs the data of bit 6 (DATA:6) in the specified read address.
■ When the Sector Deletion Temporary Stop is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address belongs to the sector being deleted. The flash memory outputs the data
of bit 6 (DATA:6) in the specified read address unless the specified address belongs to the sector being
deleted.
Reference:
When executing the write operation, the toggle bit executes the toggle operation for about 2 µs, then
terminates it without rewriting the data, if the sector to be written is write-protected.
When executing the deletion operation, the toggle bit executes the toggle operation for about 100 µs,
then returns to the read/reset status without rewriting the data, if all the selected sectors are
protected from rewriting.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
MB90820B Series
Table 23.5-4 shows the toggle bit flag status transition.
Table 23.5-4 Toggle Bit Flag Status Transition
- Status transition during normal operation
Operating Write operation
status
--> Completion
DQ6
Toggle
-->DATA:6
Sector deletion
Sector deletion -->Deletion
Chip/sector
wait-->Start
deletion
temporary stop
-->Completion
(Sector being
deleted)
Toggle-->Stop
Toggle
Toggle-->1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->Toggle
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:6
- Status transition during abnormal operation
Operating Write operation
status
DQ6
CM44-10147-2E
Toggle
Chip/sector
deletion
operation
Toggle
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
23.5.3
MB90820B Series
Time limit Exceeded Flag (DQ5)
The time limit exceeded flag (DQ5) indicates that the automatic algorithm execution time
has exceeded the time defined within the flash memory (i.e., internal pulse count).
Table 23.5-5 shows the transition of the time limit exceeded flag status.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the read/access is executed after starting the write or chip/sector deletion automatic algorithm, this
flag is set to "0" if the execution time is within the defined time (required for writing/deletion), or it outputs
"1" if this execution time exceeds the defined time. This is not related to the state in which the automatic
algorithm is being executed or has been terminated, so it can be determined whether the write/delete has
succeeded or failed. Thus, when this flag is set to "1", it indicates that the write operation has failed if the
automatic algorithm is being performed by the data polling function or toggle bit function.
For example, a fail occurs if an attempt is made to write "1" to the flash memory with "0" written. In this
case, the flash memory is locked and the automatic algorithm is not terminated. Therefore, no valid data is
set in data polling flag (DQ7). The toggle bit flag (DQ6) does not stop the toggle operation, so the
execution time exceeds the time limit. Then, the time limit exceeded flag (DQ5) outputs "1". This event
indicates that the flash memory has not been correctly used, but does not indicate that the flash memory is
not good. If this event occurs, the reset command should be executed.
Table 23.5-5 shows the time limit exceeded flag status taransition.
Table 23.5-5 Transition of the Time Limit Exceeded Flag Status
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ5
0-->DATA:5
0-->1
0
0
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:5
- Status transition during abnormal operation
Operating
status
DQ5
570
Write operation
1
Chip/sector
deletion
operation
1
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
MB90820B Series
23.5.4
Sector Deletion Timer Flag (DQ3)
After starting the sector deletion command, the sector deletion timer flag (DQ3)
indicates whether it is "during the sector deletion waiting period". Table 23.5-6 shows
the sector deletion timer flag status transition.
■ When the Sector Deletion Operation is Executed.
When the read/access is executed after starting the sector deletion command, the flash memory outputs "0"
if this flag indicates "during the sector deletion waiting period", irrespective of the address specified by the
address signal from the sector having issued the command. However, the flash memory outputs "1" if this
flag exceeds the defined sector deletion waiting period.
When the deletion algorithm is being executed by the data polling function or toggle bit function, the
internally-controlled deletion operation is started if this flag is "1". The succeeding commands except the
sector deletion temporary stop command are ignored until deletion is terminated.
If this flag is "0", the flash memory accepts the additional sector deletion command. To verify this event, it
is recommended that this flag status be checked before writing the succeeding sector deletion command. If
this flag is "1" the additional sector deletion command that is temporary stopped may not be accepted.
■ When the Sector Deletion Temporary Stop Operation is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address belongs to the sector being deleted. However, unless the specified
address belongs to the sector being deleted, the flash memory outputs the data of bit 3 (DATA:3) for the
specified read address.
Table 23.5-6 shows the sector deletion timer flag status transition.
Table 23.5-6 Sector Deletion Timer Flag Status Transition
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ3
0-->DATA:3
1
0-->1
1-->0
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0-->1
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:3
- Status transition during abnormal operation
Operating
status
DQ3
CM44-10147-2E
Write operation
0
Chip/sector
deletion
operation
1
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
23.6
MB90820B Series
Detailed Explanation on the Flash Memory Write/Delete
This section explains the procedures for issuing the command to start the automatic
algorithm, reading/resetting the flash memory, writing the data to the flash memory,
deleting the chip, deleting the sector, temporarily stopping the sector deletion, and
restarting the sector deletion.
■ Detailed Explanation on the Flash Memory Write/Delete
The read/reset, write, chip deletion, sector deletion, sector deletion temporary stop, or deletion restart
operation can be performed by the automatic algorithm which can be started by setting the command
sequence (see Section "23.4 Method of Starting the Automatic Algorithm in Flash Memory") to the flash
memory from the CPU. The write cycles to the flash memory from the CPU must be executed
continuously. The ending time of the automatic algorithm can be notified by the data polling function and
so on. After the normal end of the automatic algorithm, the flash memory returns to the read/reset status.
The following describes the operations of flash memory write/delete.
• Setting the Read/Reset Status
• Writing the Data
• Deleting All Data (Chip Deletion)
• Deleting Arbitrary Data (Sector Deletion)
• Temporarily Stopping the Sector Deletion
• Restarting the Sector Deletion
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FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
MB90820B Series
23.6.1
Setting the Read/Reset Status
This section explains the procedure of issuing the read/reset command and setting the
flash memory to the read/reset status.
■ Setting the Read/Reset Status
When the flash memory is set to the read/reset status, the read/reset command can be executed by
continuously sending the read/reset command, listed in the command sequence table (see Section "23.4
Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory
from the CPU.
There are two types of read/reset command sequences, one is that the bus operation is executed once and
the other is that the bus operations are executed three times. However, these command sequences have no
essential difference.
The read/reset status is the initial status of the flash memory. When the power supply is turned on, or when
the command is normally terminated, the flash memory is always set to the read/reset status. The read/reset
status means the status of the flash memory that is waiting for another command to be input.
In the read/reset status, data can be read from the flash memory by executing a usual read/access command.
The data can be program-accessed from CPU same as the mask ROM. This command is not required for
usual data reading. This command should be mainly used for initializing the automatic algorithm if the
command has not been normally terminated for any reason.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
23.6.2
MB90820B Series
Writing the Data
This section explains the procedure of issuing the write command and writing the data
to the flash memory. Figure 23.6-1 shows an example of procedure for writing data to
the flash memory.
■ Writing the Data
The automatic algorithm for writing the data to the flash memory can be performed by continuously
sending the write command, listed in the command sequence table (see Section "23.4 Method of Starting
the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory from the CPU. When
the data write operation to the target address in the 4th cycle has been terminated, the automatic algorithm
is started for automatic writing.
■ How to Specify the Address
Only even addresses can be specified as the write address in the write data cycle. If an odd address is
specified, data cannot be correctly written. That is, it is necessary to write the data in units of words to
even addresses.
Data can be written to the flash memory, and any address sequence may be specified, even if data has been
written across the sector boundary. However, only one-word data can be written by executing the write
command once.
■ Notes on Writing the Data
By writing the data, data "0" cannot be returned to data "1". If data "1" is written to data "0", the data
polling algorithm (DQ7) or toggle operation (DQ6) is not terminated and the flash memory element is
determined to be bad. Then, the time limit exceeded flag (DQ5) error may be determined by the excess of
the write defined time, or data "1" may be apparently written but is not actually done. However, if data is
read from the flash memory in the read/reset status, data remains "0". Only the deletion operation enables
data "0" to be changed to data "1".
All commands are ignored while automatic writing is being performed. Note that the data at the address for
writing is not assured if the hardware is reset during automatic writing.
■ Procedure of Writing the Data to the Flash Memory
Figure 23.6-1 shows an example of procedure for writing the data to the flash memory. Using the hardware
sequence flag (see Section "23.5 Verifying Automatic Algorithm Execution Status"), the status of the
automatic algorithm within the flash memory can be determined. Here, the data polling flag (DQ7) is used
for verifying the end of writing.
The data reading for checking the flag is started from the last-written address. The data polling flag (DQ7)
is changed at the same time when the time limit exceeded flag (DQ5) is changed, so the data polling flag
(DQ7) must be rechecked even if the time limit exceeded flag (DQ5) is "1".
Similarly, the toggle bit flag (DQ6) stops the toggle operation at the same time when the time limit
exceeded flag (DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked.
574
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
MB90820B Series
Figure 23.6-1 Example of Procedure for Writing the Data to the Flash Memory
Start the write
FMCS:WE (bit5)
Flash memory write
enabled
Write command sequence
1.YYYAAA
XXAA
2.YYY554
XX55
3.YYYAAA
XXA0
4.Write address
Write data
Next address
Internal address read
Data
Data polling (DQ7)
Data
0
Time limit (DQ5)
1
Internal address read
Data
Data polling (DQ7)
Data
Last address
Write error
FMCS:WE(bit5)
Verification using
the hardware sequence flag
Flash memory write disabled
Write completion
CM44-10147-2E
YYY: Upper 12 bits of an arbitrary
address not set to ì0 ” (neither
write-inhabited nor write-protected)
in flash memory write control
register FWR0/FWR1 in the flash
memory area
X:
Arbitrary value
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
23.6.3
MB90820B Series
Deleting All Data (Chip Deletion)
This section explains the procedure of issuing the chip deletion command and deleting
all the data in the flash memory.
■ Deleting the Data (Chip Deletion)
All the data can be deleted from the flash memory by continuously sending the chip deletion command,
listed in the command sequence table (see Section "23.4 Method of Starting the Automatic Algorithm in
Flash Memory"), to the target sector in the flash memory from the CPU.
The chip deletion command is executed by executing the bus operation six times. When the 6th-cycle write
operation has been completed, the chip deletion operation is started. The user need not write the data to the
flash memory before chip deletion operation. During the automatic deletion algorithm execution, the flash
memory writes data "0" to all the cells and verifies them before they are automatically deleted.
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CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
MB90820B Series
23.6.4
Deleting Arbitrary Data (Sector Deletion)
This section explains the procedure of issuing the sector deletion command and
deleting any sector from the flash memory (sector deletion). This command enables
each sector to be deleted, and two or more sectors to be specified at the same time.
■ Deleting Arbitrary Data (Sector Deletion)
Any sector can be deleted from the flash memory by continuously sending the sector deletion command,
listed in the command sequence table (see Section "23.4 Method of Starting the Automatic Algorithm in
Flash Memory"), to the target sector in the flash memory from the CPU.
Method of Specifying a Sector
The sector deletion command is executed by executing the bus operation six times. The sector deletion
wait of 50 µs is started by writing the sector deletion code (30H) to any accessible even address in the target
sector in the 6th-cycle bus operation. To delete two or more sectors, the deletion code (30H) should be
written to the address in the target sector just after the above operation.
■ Notes on Specifying Two or More Sectors
The deletion operation is started after the last sector deletion code is written and the sector deletion wait
period of 50 µs is terminated. Thus, the next deletion sector address and deletion code (i.e. in the 6th cycle
of the command sequence) must be input each within 50 µs to delete two or more sectors simultaneously,
which may not be accepted later than 50 µs. It can be checked whether the succeeding sector deletion code
write operation is valid, using the sector deletion timer flag (DQ3). In this case, the address from which the
sector deletion timer flag (DQ3) is read must indicate the sector to be deleted.
■ Procedure of Deleting a Sector
Using the hardware sequence flag (see Section "23.5 Verifying Automatic Algorithm Execution Status"), the
status of the automatic algorithm within the flash memory can be determined. Figure 23.6-2 shows an
example of procedure for deleting the sector from the flash memory. Here, the toggle bit flag (DQ6) is
used for verifying the end of deletion. Note that data to be used for checking the flag is read from the
sector to be deleted.
The toggle bit flag (DQ6) stops the toggle operation at the same time when the time limit exceeded flag
(DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked even if the time limit exceeded
flag (DQ5) is "1".
Similarly, the data polling flag (DQ7) is changed at the same time when the time limit exceeded flag (DQ5)
is changed, so the data polling flag (DQ7) must be rechecked.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
MB90820B Series
Figure 23.6-2 Example of Procedure for Deleting the Sector from the Flash Memory
Start the deletion.
FMCS:WE(bit5)
Flash memory deletion enabled
Deletion command sequence
XXAA
1. YYYAAA
XX55
2. YYY554
XX80
3. YYYAAA
XXAA
4. YYYAAA
XX55
5. YYY554
1
Sector deletion timer (DQ3)
0
Input the code to the sector to be
deleted. (30H)
YES
Internal address read
Is there another sector
to be deleted?
NO
Internal address read 1
Internal address read 2
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
Next sector
YES
NO
O
Time limit (DQ5)
1
Internal address read 1
Internal address read 2
NO
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
YES
Delete error
Last sector
YES
FMCS:WE(bit15)
Flash memory deletion disabled
Verification using
the hardware sequence flag
578
Deletion completion
NO
YYY: Upper 12 bits of an arbitrary
address not set to “0”
(neither write-inhabited nor
write-protected) in flash
memory write control register
FWR0/FWR1 in the flash
memory area
X:
Arbitrary value
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
MB90820B Series
23.6.5
Temporarily Stopping the Sector Deletion
This section explains the procedure of issuing the sector deletion temporary stop
command and temporarily stopping the deletion of a sector from the flash memory.
This command can read the data from the sector not being deleted.
■ Temporarily Stopping the Sector Deletion
The sector deletion from the flash memory can be temporarily stopped by continuously sending the sector
deletion temporary stop command, listed in the command sequence table (see Section "23.4 Method of
Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory from the
CPU.
The sector deletion temporary stop command stops the sector deletion operation temporarily, and enables
the data reading from the sector not being deleted. In this case, only the read operation can be executed,
but the write operation cannot be done. This command is valid only during the sector deletion operation
including the deletion waiting time, but it is ignored during the chip deletion operation or the write
operation.
This command is executed by writing the deletion temporary stop code (B0H). In this case, the address
must indicate any address within the flash memory. During the deletion temporary stop operation, the
reissued deletion temporary stop command is ignored.
If the sector deletion temporary stop command is input during the sector deletion waiting period, the sector
deletion wait is immediately terminated to stop the deletion operation, and the flash memory enters the
deletion stop status. If the sector deletion temporary stop command is input during the sector deletion
operation after the sector deletion waiting period, the flash memory enters the deletion temporary stop
status after a lapse of up to 15 µs.
■ Note
Before issuing a suspend command, wait for at least 20ms after issuing the sector erase command or sector
erase resume command. The suspend command should not be issued too many times.
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
23.6.6
MB90820B Series
Restarting the Sector Deletion
This section explains the procedure of issuing the sector deletion restart command and
restarting the operation of deleting a sector from the flash memory, which has been
temporarily stopped.
■ Restarting the Sector Deletion
The sector deletion operation which has been temporarily stopped can be restarted by continuously sending
the sector deletion restart command, listed in the command sequence table (see Section "23.4 Method of
Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory from the
CPU.
The sector deletion restart command is used to restart the sector deletion operation when the flash memory
is in the sector deletion temporary stop status caused by the sector deletion temporary stop command. This
command is executed by writing the deletion restart code (30H). In this case, the address must indicate any
address within the flash memory area.
However, the sector deletion restart command issued during the sector deletion operation is ignored.
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FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.7
MB90820B Series
23.7
Flash Security Feature
The flash security controller provides possibilities to protect the content of the flash
memory from being read from external pins.
• One predefined address of the flash memory is assigned to the flash security controller (MB90F822B:
FF0001H; MB90F823B: FE0001H). If the protection code of “01H” is written in this address, access to
the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation
only can unlock the function otherwise read/write access to the flash memory from any external pins is
not generally possible.
• This function is suitable for applications requiring security of self-containing program and data stored in
the flash memory. If the target application requires any part of the program to locate outside the
microcontroller, the flash security controller can not offer the intended features. For this reason, the
external vector fetch mode should not be used when the protection code is set.
• Programming of the flash microcontroller by standard parallel programmer may require unique set-up.
For example, with the programmer from Minato Electronics, the device checking should be turned off.
Writing the protection code is generally recommended to take place at the end of the flash
programming. This is to avoid unnecessary protection during the programming.
• In order to re-program the once protected flash memory, the chip erase operation should be preformed.
For further information, please contact Fujitsu Microelectronics.
CM44-10147-2E
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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.7
582
FUJITSU MICROELECTRONICS LIMITED
MB90820B Series
CM44-10147-2E
APPENDIX
APPENDIX A I/O Map
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection
for Serial Writing
APPENDIX C Instructions
CM44-10147-2E
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APPENDIX
APPENDIX A I/O Map
MB90820B Series
APPENDIX A I/O Map
Table A-1 lists the addresses assigned to the registers for peripheral functions in the
MB90820B series.
■ I/O Map
Table A-1 I/O map (1 / 6)
Address Abbreviation
Byte
Word
access access
Register
Resource name
Initial value
000000H
PDR0
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
XXXXXXXXB
000009H
to
00000FH
Prohibited area
000010H
DDR0
Port 0 data direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 data direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 data direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 data direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 data direction register
R/W
R/W
Port 4
00000000B
000015H
DDR5
Port 5 data direction register
R/W
R/W
Port 5
XXXXXX00B
000016H
DDR6
Port 6 data direction register
R/W
R/W
Port 6
00000000B
000017H
DDR7
Port 7 data direction register
R/W
R/W
Port 7
00000000B
000018H
DDR8
Port 8 data direction register
R/W
R/W
Port 8
00000000B
000019H
to
00001FH
Prohibited area
000020H
SMR0
Serial mode register 0
R/W
R/W
000021H
SCR0
Serial control register 0
R/W
R/W
000022H
SIDR0 / SODR0
Serial Input data register 0 / Serial Output data
register 0
R/W
R/W
00000000B
00000100B
UART0
XXXXXXXXB
000023H
SSR0
Serial status register 0
R/W
R/W
00001000B
000024H
SMR1
Serial mode register 1
R/W
R/W
00000000B
000025H
SCR1
Serial control register 1
R/W
R/W
000026H
000027H
584
Serial Input data register 1 / Serial Output data
SIDR1 / SODR1
register 1
SSR1
Status register 1
R/W
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
00000100B
UART1
XXXXXXXXB
00001000B
CM44-10147-2E
APPENDIX
APPENDIX A I/O Map
MB90820B Series
Table A-1 I/O map (2 / 6)
Address Abbreviation
000028H
PWCSL1
000029H
PWCSH1
00002AH
00002BH
00002CH
Register
PWC control status register 1
PWC1
PWC data buffer register 1
DIV1
Divide ratio control register 1
00002DH,
00002EH
Byte
Word
access access
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
PCKCR
W
W
000030H
ENIR
DTP / Interrupt enable register
R/W
R/W
000031H
EIRR
DTP / Interrupt cause register
R/W
R/W
000032H
ELVRL
Request level setting register (lower byte)
R/W
R/W
000033H
PLL clock control register
ELVRH
Request level setting register (higher byte)
R/W
R/W
000034H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
CDCR0
Clock division control register 0
CDCR1
Clock division control register 1
PDCR0
PPG0 down counter register 0
PCSR0
PDUT0
00003FH
PCNTH0
000042H
000043H
000044H
000045H
PDCR1
PCSR1
PDUT1
PCNTL1
000047H
PCNTH1
000049H
00004AH
00004BH
00004CH
00004DH
XXXXXX00B
PLL
XXXX0000B
00000000B
DTP/external interrupt
XXXXXXXXB
00000000B
00000000B
R/W
R/W
Communication prescaler 0
00XXX000B
R/W
R/W
Communication prescaler 1
00XXX000B
-
R
PPG0 period setting register 0
-
11111111B
11111111B
XXXXXXXXB
W
PPG0 duty setting register 0
PPG0 control status register 0
PPG1 down counter register 1
PPG1 period setting register 1
-
W
R/W
R/W
R/W
R/W
-
-
PDCR2
PCSR2
PPG1 duty setting register 1
00000000B
11111111B
11111111B
XXXXXXXXB
W
PPG1 control status register 1
PPG2 down counter register 2
PPG2 period setting register 2
W
R/W
R/W
R/W
R/W
-
-
00004EH
PCNTL2
00004FH
PCNTH2
CM44-10147-2E
PPG2 duty setting register 2
PPG2 control status register 2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
00000000B
11111111B
R
11111111B
XXXXXXXXB
W
16-bit PPG timer 2
PDUT2
XXXXXXXXB
XX000000B
R
-
XXXXXXXXB
XXXXXXXXB
16-bit PPG timer 1
000046H
000048H
XXXXXXXXB
XXXXXXXXB
16-bit PPG timer 0
PCNTL0
000041H
00000000B
PWC timer 1
Prohibited area
00003EH
000040H
00000000B
Prohibited area
000036H
000037H
Initial value
Prohibited area
00002FH
000035H
Resource name
XXXXXXXXB
XXXXXXXXB
-
W
R/W
R/W
XX000000B
R/W
R/W
00000000B
FUJITSU MICROELECTRONICS LIMITED
XXXXXXXXB
585
APPENDIX
APPENDIX A I/O Map
MB90820B Series
Table A-1 I/O map (3 / 6)
Address Abbreviation
000050H
000051H
000052H
000053H
000054H
TMRR0
TMRR1
16-bit timer register 0
16-bit timer register 2
000056H
DTCR0
000057H
000058H
000059H
00005AH
00005BH
00005CH
000065H
000066H
000067H
XXXXXXXXB
XXXXXXXXB
00000000B
DTCR1
16-bit timer control register 1
R/W
R/W
00000000B
DTCR2
16-bit timer control register 2
R/W
R/W
00000000B
SIGCR
Waveform control register
R/W
R/W
CPCLRB /
CPCLR
Compare clear buffer register /
Compare clear register (lower)
-
Waveform generator
XXXXXXXXB
00000000B
11111111B
R/W
11111111B
16-bit free-run timer
TCCSH
000064H
R/W
R/W
00005FH
000063H
XXXXXXXXB
XXXXXXXXB
R/W
TCCSL
000062H
XXXXXXXXB
R/W
16-bit timer control register 0
00005EH
000061H
Initial value
R/W
Timer data register (lower)
000060H
-
Resource name
-
TCDT
00005DH
-
16-bit timer register 1
TMRR2
000055H
Byte
Word
access access
Register
-
R/W
Timer control status register (lower)
R/W
R/W
Timer control status register (upper)
R/W
R/W
IPCP0
Input capture data register 0
-
R
IPCP1
Input capture data register 1
-
R
IPCP2
Input capture data register 2
-
R
IPCP3
Input capture data register 3
-
R
00000000B
00000000B
00000000B
16-bit free-run timer
X0000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit input capture
(0 to 3)
XXXXXXXXB
XXXXXXXXB
000068H
PICSL01
Input capture control status register 01 (lower)
R/W
R/W
00000000B
000069H
PICSH01
PPG output control / Input capture control status
register 01 (upper)
R/W
R/W
00000000B
00006AH
ICSL23
Input capture control status register 23 (lower)
R/W
R/W
00000000B
ICSH23
Input capture control status register 23
(upper)
R
R
XXXXXX00B
00006BH
00006CH
to
00006EH
00006FH
586
Prohibited area
ROMM
ROM mirroring function selection register
W
W
FUJITSU MICROELECTRONICS LIMITED
ROM mirroring function
XXXXXXX1B
CM44-10147-2E
APPENDIX
APPENDIX A I/O Map
MB90820B Series
Table A-1 I/O map (4 / 6)
Address Abbreviation
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
OCCPB0 /OCCP0
OCCPB1 /OCCP1
OCCPB2 /OCCP2
OCCPB3 /OCCP3
OCCPB4 /OCCP4
OCCPB5 /OCCP5
Byte
Word
access access
Register
Output compare buffer register / Output
compare register 0
-
Output compare buffer register / Output
compare register 1
-
Output compare buffer register / Output
compare register 2
-
Output compare buffer register / Output
compare register 3
-
Output compare buffer register / Output
compare register 4
-
Output compare buffer register / Output
compare register 5
Resource name
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
Output compare
(0 to 5)
R/W
-
R/W
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00007CH
OCS0
Compare control register 0
R/W
R/W
00000000B
00007DH
OCS1
Compare control register 1
R/W
R/W
X0000000B
00007EH
OCS2
Compare control register 2
R/W
R/W
00000000B
00007FH
OCS3
Compare control register 3
R/W
R/W
X0000000B
000080H
OCS4
Compare control register 4
R/W
R/W
00000000B
000081H
OCS5
Compare control register 5
R/W
R/W
X0000000B
000082H
TMCSRL0
Timer control status register 0 (lower)
R/W
R/W
00000000B
000083H
TMCSRH0
Timer control status register 0 (upper)
R/W
R/W
000084H
000085H
TMR0 / TMRD0
16 bit timer register 0 / 16-bit reload
register 0
-
R/W
000086H
TMCSRL1
Timer control status register 1 (lower)
R/W
R/W
000087H
TMCSRH1
Timer control status register 1 (upper)
R/W
R/W
000088H
000089H
00008AH
TMR1 / TMRD1
CSVCR
16 bit timer register 1 / 16-bit reload
register 1
Clock supervisor control register *
00008BH
16-bit reload timer 0
XXXX0000B
XXXXXXXXB
XXXXXXXXB
00000000B
16-bit reload timer 1
XXXX0000B
XXXXXXXXB
-
R/W
R, R/W
-
Clock supervisor
00011100B
XXXXXXXXB
Prohibited area
00008CH
RDR0
Port 0 pull-up resistor setting register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting register
R/W
R/W
Port 1
00000000B
00008EH
RDR2
Port 2 pull-up resistor setting register
R/W
R/W
Port 2
00000000B
00008FH
RDR3
Port 3 pull-up resistor setting register
R/W
R/W
Port 3
00000000B
000090H
to
00009DH
Prohibited area
Program address detect control status
register
R/W
R/W
Address match detection
00000000B
Delayed interrupt reset cause / clear register
R/W
R/W
Delayed interrupt input
generation
XXXXXXX0B
LPMCR
Low-power consumption mode control register
R/W
R/W
CKSCR
Clock selection register
R/W
R/W
00009EH
PACSR
00009FH
DIRR
0000A0H
0000A1H
0000A2H
to
0000A7H
0000A8H
Low-power consumption mode
00011000B
11111100B
Prohibited area
WDTC
CM44-10147-2E
Watchdog timer control register
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
Watchdog timer
XXXXX111B
587
APPENDIX
APPENDIX A I/O Map
MB90820B Series
Table A-1 I/O map (5 / 6)
Address Abbreviation
0000A9H
TBTC
Register
Time-base timer control register
0000AAH
to
0000ADH
Byte
Word
access access
R/W
Resource name
Initial value
R/W
Time-base timer
1XX00100B
R/W
Flash memory interface circuit
000X0000B
Prohibited area
FMCS
Flash memory control status register
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000AEH
0000AFH
R/W
Prohibited area
00000111B
Interrupt controller
00000111B
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
0000C0H
PWCSL0
0000C1H
PWCSH0
0000C2H
PWC control status register 0
PWC0
PWC data buffer register 0
0000C4H
DIV0
0000C5H
0000C6H
0000C3H
R/W
R/W
00000111B
R/W
R/W
00000000B
R/W
R/W
XXXXXXXXB
-
R/W
Divide ratio control register 0
R/W
R/W
ADER0
A/D input enable register 0
R/W
R/W
ADCS0
A/D control status register 0
R/W
R/W
000XXXX0B
0000000XB
0000C7H
ADCS1
A/D control status register 1
R/W
R/W
0000C8H
ADCR0
A/D data register 0
R
R
0000C9H
ADCR1
A/D data register 1
R/W
R/W
0000CAH
ADSR0
A/D setting register 0
R/W
R/W
0000CBH
ADSR1
0000CCH
DAT0
XXXXXXXXB
XXXXXX00B
Port 6, A/D
11111111B
8/10-bit A/D converter
00000000B
XXXXXX00B
00000000B
A/D setting register 1
R/W
R/W
00000000B
D/A data register 0
R/W
R/W
XXXXXXXXB
0000CDH
DAT1
D/A data register 1
R/W
R/W
0000CEH
DACR0
D/A control register 0
R/W
R/W
0000CFH
DACR1
D/A control register 1
R/W
R/W
0000D0H
ADER1
A/D input enable register 1
R/W
R/W
0000D1H
to
0000EFH
Prohibited area
0000F0H
to
0000 FFH
External area
588
00000000B
PWC timer 0
FUJITSU MICROELECTRONICS LIMITED
8-bit D/A converter
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Port 7, A/D
11111111B
CM44-10147-2E
APPENDIX
APPENDIX A I/O Map
MB90820B Series
Table A-1 I/O map (6 / 6)
Address Abbreviation
Register
Byte
Word
access access
Resource name
Initial value
001FF0H
PADRL0
Program address detection register 0
(lower byte)
R/W
R/W
XXXXXXXXB
001FF1H
PADRM0
Program address detection register 0
(middle byte)
R/W
R/W
XXXXXXXXB
001FF2H
PADRH0
Program address detection register 0
(higher byte)
R/W
R/W
XXXXXXXXB
Address match detection
001FF3H
PADRL1
Program address detection register 1
(lower byte)
R/W
R/W
XXXXXXXXB
001FF4H
PADRM1
Program address detection register 1
(middle byte)
R/W
R/W
XXXXXXXXB
001FF5H
PADRH1
Program address detection register 1
(higher byte)
R/W
R/W
XXXXXXXXB
*: MB90F828B only. Prohibited for the other product types.
● Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R:
Read-only
W:
Write-only
● Explanation of initial values
0: The bit is initialized to 0.
1: The bit is initialized to 1.
X: The initial value of the bit is undefined.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
589
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
MB90820B Series
APPENDIX B Example of F2MC-16LX MB90F822B/F823B
Connection for Serial Writing
This chapter describes examples of F2MC-16LX MB90F822B/F823B connections for serial
writing.
B.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard)
B.2 Example of Connection for Serial Writing (When Power Supplied by User)
B.3 Example of Connection for Serial Writing (When Power Supplied from Writer)
B.4 Example of Minimum Connection with Flash Microcontroller Programmer (When Power Supplied by
User)
B.5 Example of Minimum Connection with Flash Microcontroller Programmer (When Power Supplied
from Writer)
590
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
MB90820B Series
B.1
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
Standard Configuration for Serial On-board Writing (Fujitsu
Standard)
MB90F822B/F823B supports serial on-board writing (Fujitsu standard) to flash ROM.
This describes the specifications for serial on-board writing.
■ Standard Configuration for Fujitsu Standard Serial On-board Writing
The AF220/AF210/AF120/AF110 flash microcontroller programmer of Yokogawa Digital Computer Co.,
Ltd. is used for Fujitsu standard serial on-board writing.
General-purpose common cable (AZ210)
Host interface cable
RS232C
AF200
flash
microcontroller
programmer
+
memory card
Clock
synchronous
serial
Microcontroller on-board
user system
Operable in stand-alone mode
Note :
Contact Yokogawa Digital Computer Co., Ltd. for the functionality and operation of the flash
microcontroller programmer and information on the general-purpose common cable (AZ210) and
connectors.
Table B.1-1 Pins used for Fujitsu standard serial on-board writing (1 / 2)
Pin
Description
MD2,
MD1,
MD0
Mode pins
Used to enable write mode for the flash microcontroller
programmer.
X0, X1
Oscillator pins
In write mode, since the operation clock is one times the CPU clock,
the oscillation clock frequency is the internal operation clock.
The resonator used for serial rewriting is therefore 1 MHz to 16 MHz.
P00, P01
CM44-10147-2E
Function
Programing
activation pins
P00
P01
Function
0
0
Asynchronous mode
Machine clock = 16 MHz
Baud rate = 19200 bps
0
1
Asynchronous mode
Machine clock = 20 MHz
Baud rate = 19200 bps
1
0
Synchronous mode
1
1
Reserved
FUJITSU MICROELECTRONICS LIMITED
591
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
Table B.1-1 Pins used for Fujitsu standard serial on-board writing (2 / 2)
MB90820B Series
Pin
Function
Description
RSTX
Reset pin
–
SIN0
Serial data input pin
SOT0
Serial data output
pin
SCK0
Serial clock input
pin
C
C pin
Capacitance pin for power stabilization. Connect a ceramic
capacitor of about 0.1 µF to the outside.
VCC
Power supply pin
If write voltage (5 V ± 10%) is supplied from the user system, this
pin need not be connected to the flash microcontroller
programmer. If the pin is connected to the flash microcontroller
programmer, do not connect it to the power of the user system.
VSS
Ground pin
Used also as the ground pin for the flash microcontroller
programmer.
UART0 is used in CLK synchronous mode.
Note:
When the P00, P01, SIN0, SOT0, SCK0 pins are also used by the user system, the control circuit
shown below is required. (The /TICS signal of the flash microcontroller programmer can separate the
user circuit during serial writing. See the connection example shown later.)
Figure B.1-1 Control circuit
Flash microcontroller
write control pin
Microcontroller
write control pin
10kΩ
Flash microcontroller
/TICS pin
User
See the following four serial writing examples in Appendix B.2 to B.5.
• Example of serial write connection when power supplied by user
• Example of serial write connection when power supplied from writer
• Example of minimum connection to flash microcontroller programmer when power supplied by user
• Example of minimum connection to flash microcontroller programmer when power supplied from
writer
592
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
MB90820B Series
Table B.1-2
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
System configuration of AF200 flash microcontroller programmer
(Yokogawa Digital Computer Co., Ltd.)
Model
Main
unit
Function
AF220/ AC4P
Ethernet interface built-in model and 100 to 220 V AC power adapter
AF210/ AC4P
Standard model and 100 to 220 V AC power adapter
AF120/ AC4P
Single-key Ethernet interface built-in model and 100 to 220 V AC
power adapter
AF110/ AC4P
Single-key model and 100 to 220 V AC power adapter
AZ221
PC/AT RS232C cable for programmer
AZ210
Standard target probe (a) with a 1 m cable
FF201
Fujitsu F2MC-16LX flash microcontroller control module
AZ290
Remote controller
/P2
2MB PC card (optional) for flash memory sizes up to 128 KB
/P4
4MB PC card (optional) for flash memory sizes up to 512 KB
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
Although the flash microcontroller programmer is no longer manufactured, the programmer still can
be used in combination with the FF201 control module.
Examples of serial programming connection are given in “Oscillating clock frequency and serial clock
input frequency”.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
593
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
B.2
MB90820B Series
Example of Connection for Serial Writing
(When Power Supplied by User)
Figure B.2-1 is an example of serial write connection when power is supplied by the
user.
MD2=1 and MD0=0 are input from TAUX3 and TMODE respectively in AF200 flash
microcontroller programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Connection for Serial Writing (When Power Supplied by User)
Figure B.2-1 Example of connection for serial writing in Single chip mode (when power supplied by user)
flash
microcontroller
programmer
User system
Connector
DX10-28S
Flash memory products
(19)
TAUX3
MD2
MD1
TMODE
MD0
(12)
X0
4MHz-16MHz
X1
(23)
TAUX
P00
(10)
/TICS
User
/TRES
(5)
RSTX
P01
User
C
TTXD
TRXD
TCK
TVcc
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
(2)
(7,8,
14,15,
21,22,
1,28)
Vcc
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S, right-angle type
594
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
• When the user system also uses pins SIN0, SOT0 and SCK0, the control circuit shown below is
necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash
microcontroller programmer /TICS signal.)
MB90820B Series
• Before connecting the Flash microcontroller, turn off the power supplied by the user.
Figure B.2-2 Control circuit
Flash microcontroller
write control pin
Microcontroller
write control pin
Flash microcontroller
/TICS pin
User
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
595
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
B.3
MB90820B Series
Example of Connection for Serial Writing
(When Power Supplied from Writer)
Figure B.3-1 is an example of serial write connection when power is supplied from the writer.
MD2=1 and MD0 are input from TAUX3 and TMODE respectively in flash microcontroller
programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Connection for Serial Writing (When Power Supplied from Writer)
Figure B.3-1 Example of connection for serial writing in Single chip mode
(when power supplied from writer)
Flash
microcontroller
programmer
User system
Connector
DX10-28S
Flash memory products
(19)
TAUX3
MD2
MD1
TMODE
MD0
(12)
X0
4MHz-16MHz
X1
(23)
TAUX
P00
(10)
/TICS
User
/TRES
(5)
RSTX
P01
User
C
TTXD
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
(2)
(3)
(16)
TRXD
TCK
TVcc
Vcc
TVPP1
Vcc
(7,8,
14,15,
21,22,
1,28)
Vss
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S, right-angle type
596
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
• When the SIN0, SOT0 and SCK0 pins are also used by the user system, the control circuit shown below
is necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash
microcontroller /TICS signal.)
MB90820B Series
• Before connecting the Flash microcontroller programmer, turn off the power supplied by the user.
• When supplying write power from Flash microcontroller, do not create a short with the power supplied
by the user.
Figure B.3-2 Control circuit
Flash microcontroller
write control pin
Microcontroller
write control pin
Flash microcontroller
/TICS pin
User
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
597
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
B.4
MB90820B Series
Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied by User)
Figure B.4-1 is an example of the minimum connection with the flash microcontroller
programmer when power is supplied by the user.
Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied by User)
If the pins are set as shown in Figure B.4-1 during writing to flash memory, MD2, MD1, MD0, P00 and
flash microcontroller programmer connection is unnecessary.
Figure B.4-1 Example of minimum connection with flash microcontroller programmer
(when power supplied by user)
flash
microcontroller
programmer
User system
Serial write 1
Flash memory products
MD2
Serial
rewriting
MD1
MD0
X0
4MHz-16MHz
X1
Serial
write 0
P00
User circuit
Serial write 1
User circuit
P01
C
Connector
DX10-28S
(5)
RSTX
(13)
(6)
SIN0
SOT0
SCK0
(2)
Vcc
/TRES
TTXD
TRXD
TCK
TVcc
(27)
GND
(7,8,
14,15,
21,22,
1,28)
Pins 3, 4, 9, 10, 11,
12, 16, 17, 18, 19,
20, 23, 24, 25, and
26 are open.
DX10-28S, right-angle type
598
User power supply Vss
Pin 14
Pin 1
DX10-28S
Pin 15
Pin 28
Connector (made by Hirose Electric) pin layout
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
• When the user system also uses the SIN0, SOT0 and SCK0 pins, the control circuit shown below is
necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller
programmer /TICS signal.)
MB90820B Series
• Before connecting the Flash microcontroller programmer, turn off the power supplied by the user.
Figure B.4-2 Conrorl circuit
Flash microcontroller programmaer
write control pin
Microcontroller
write control pin
10kΩ
Flash
microcontroller programmaer
/TICS pin
CM44-10147-2E
User
FUJITSU MICROELECTRONICS LIMITED
599
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
B.5
MB90820B Series
Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied from Writer)
Figure B.5-1 is an example of the minimum connection with the flash microcontroller
programmer when power is supplied from the writer.
■ Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied from Writer)
If the pins are set as shown in Figure B.5-1 during writing to flash memory, MD2, MD1, MD0, P00 and
flash microcontroller programmer connection is unnecessary.
Figure B.5-1 Example of minimum connection with flash microcontroller programmer
(when power supplied from writer)
flash
Microcontroller
programmer
User system
Flash memory products
Serial write1
MD2
MD1
Serial
write1
MD0
Serial write0
X0
4MHz-16MHz
X1
P00
Serial
write0
User circuit
Serial write1
User
circuit
P01
C
Connector
DX10-28S
(5)
(13)
(27)
(6)
(2)
(3)
(16)
(7,8,
14,15,
21,22,
1,28)
/TRES
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
Pins 4, 9, 10, 11, 12,
17, 18, 19, 20, 23, 24,
25, and 26 are open.
DX10-28S, right-angle type
600
RSTX
SIN0
SOT0
SCK0
Vcc
Vss
Pin 14
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX B Example of F2MC-16LX MB90F822B/F823B Connection for
Serial Writing
• When the user system also uses the SIN0, SOT0, SCK0 pins, the control circuit shown below is
necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller
programmer /TICS signal.)
MB90820B Series
• Before connecting Flash microcontroller programmer, turn off the power supplied by the user.
• When write power is supplied from Flash microcontroller programmer, do not create a short with the
power supplied by user.
Figure B.5-2 Control circuit
Flash microcontroller programmer
write control pin
Microcontroller
write control pin
10kΩ
Flash
microcontroller programmer
/TICS pin
User
CM44-10147-2E
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APPENDIX
APPENDIX C Instructions
MB90820B Series
APPENDIX C Instructions
APPENDIX C describes the instructions used by the F2MC-16LX.
C.1 Instruction Types
C.2 Addressing
C.3 Direct Addressing
C.4 Indirect Addressing
C.5 Execution Cycle Count
C.6 Effective address field
C.7 How to Read the Instruction List
C.8 F2MC-16LX Instruction List
C.9 Instruction Map
Code: CM44-00202-1E
602
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APPENDIX
APPENDIX C Instructions
MB90820B Series
C.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
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APPENDIX
APPENDIX C Instructions
C.2
MB90820B Series
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
604
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
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CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
■ Effective Address Field
Table C.2-1 lists the address formats specified by the effective address field.
Table C.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
CM44-10147-2E
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
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APPENDIX
APPENDIX C Instructions
C.3
MB90820B Series
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure C.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table C.3-1 lists the registers that can be specified. Figure C.32 shows an example of register direct addressing.
Table C.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
606
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APPENDIX
APPENDIX C Instructions
MB90820B Series
Figure C.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure C.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
CM44-10147-2E
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
FUJITSU MICROELECTRONICS LIMITED
JMP 3B20H
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APPENDIX
APPENDIX C Instructions
MB90820B Series
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure C.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure C.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
608
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
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CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure C.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure C.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
CM44-10147-2E
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
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APPENDIX
APPENDIX C Instructions
MB90820B Series
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure C.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure C.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure C.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
610
DTB 5 5
552222H
FUJITSU MICROELECTRONICS LIMITED
01
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure C.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table C.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table C.3-2 ).
CM44-10147-2E
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APPENDIX
APPENDIX C Instructions
C.4
MB90820B Series
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure C.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
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CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Figure C.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure C.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
CM44-10147-2E
DTB 7 8
Memory space
DTB 7 8
FUJITSU MICROELECTRONICS LIMITED
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APPENDIX
APPENDIX C Instructions
MB90820B Series
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure C.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure C.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
614
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure C.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
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APPENDIX
APPENDIX C Instructions
MB90820B Series
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure C.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure C.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
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FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Figure C.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure C.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
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APPENDIX
APPENDIX C Instructions
MB90820B Series
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure C.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure C.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
618
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
FUJITSU MICROELECTRONICS LIMITED
JMP @@RW0
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure C.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
619
APPENDIX
APPENDIX C Instructions
C.5
MB90820B Series
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
620
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
■ Calculating the Execution Cycle Count
Table C.5-1 lists execution cycle counts and Table C.5-2 and Table C.5-3 summarize correction value
data.
Table C.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "C.8 F2MC-16LX Instruction List".
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
621
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "C.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table C.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
622
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
C.6
Effective address field
Table C.6-1 shows the effective address field.
■ Effective Address Field
Table C.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "C.8 F2MC-16LX
Instruction List".
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
623
APPENDIX
APPENDIX C Instructions
C.7
MB90820B Series
How to Read the Instruction List
Table C.7-1 describes the items used in "C.8 F2MC-16LX Instruction List", and Table
C.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table C.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table C.2-1 for the alphabetical letters in items.
RG
B
Operation
624
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table C.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
CM44-10147-2E
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
FUJITSU MICROELECTRONICS LIMITED
625
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
626
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
C.8
F2MC-16LX Instruction List
Table C.8-1 to Table C.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table C.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table C.5-1 and Table C.5-2 for information on (a) and (b) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
627
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
Note:
See Table C.5-1 and Table C.5-2 for information on (a), (c), and (d) in the table.
628
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (d) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
629
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (d) in the table.
Table C.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (d) in the table.
630
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (c) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
631
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table C.5-1 and Table C.5-2 for information on (a) to (c) in the table.
632
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (c) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
633
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table C.5-1 and Table C.5-2 for information on (a) and (d) in the table.
Table C.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (c) in the table.
Table C.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
634
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table C.5-1 and Table C.5-2 for information on (a) and (b) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
635
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (d) in the table.
636
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table C.5-1 and Table C.5-2 for information on (a) to (d) in the table.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
637
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table C.5-1 and Table C.5-2 for information on (a) and (c) in the table.
638
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table C.5-1 and Table C.5-2 for information on (b) in the table.
Table C.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
CM44-10147-2E
Operation
FUJITSU MICROELECTRONICS LIMITED
639
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table C.5-1 and Table C.5-2 for information on (b) and (c) in the table.
640
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
APPENDIX
APPENDIX C Instructions
MB90820B Series
C.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table C.9-2 to Table C.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure C.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure C.9-2
shows the correspondence between an actual instruction code and instruction map.
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
641
APPENDIX
APPENDIX C Instructions
MB90820B Series
Figure C.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table C.9-1 .
Table C.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
642
FUJITSU MICROELECTRONICS LIMITED
CM44-10147-2E
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-2 Basic Page Map
643
644
FUJITSU MICROELECTRONICS LIMITED
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-3 Bit Operation Instruction Map (First Byte = 6CH)
CM44-10147-2E
CM44-10147-2E
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
PCB, DTB
+1
+2
MOVSI
MOVSD
PCB, PCB
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-4 Character String Operation Instruction Map (First Byte = 6EH)
FUJITSU MICROELECTRONICS LIMITED
645
646
40
FUJITSU MICROELECTRONICS LIMITED
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+F
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
+D
+E
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-5 2-byte Instruction Map (First Byte = 6FH)
CM44-10147-2E
CM44-10147-2E
50
90
B0
D0
FUJITSU MICROELECTRONICS LIMITED
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-6 ea Instruction 1 (First Byte = 70H)
647
648
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
FUJITSU MICROELECTRONICS LIMITED
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
+6
+7
+8
+9
+A
+B
+C
+D
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
+5
+F
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
+4
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
+3
+E
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
+2
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-7 ea Instruction 2 (First Byte = 71H)
CM44-10147-2E
CM44-10147-2E
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-8 ea Instruction 3 (First Byte = 72H)
FUJITSU MICROELECTRONICS LIMITED
649
650
FUJITSU MICROELECTRONICS LIMITED
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-9 ea Instruction 4 (First Byte = 73H)
CM44-10147-2E
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-10 ea Instruction 5 (First Byte = 74H)
651
652
NOT
NOT
R2 @RW2+d8
FUJITSU MICROELECTRONICS LIMITED
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-11 ea Instruction 6 (First Byte = 75H)
CM44-10147-2E
CM44-10147-2E
FUJITSU MICROELECTRONICS LIMITED
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-12 ea Instruction 7 (First Byte = 76H)
653
654
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
FUJITSU MICROELECTRONICS LIMITED
SUBCW A,
SUBW
SUBW
@RW2+, A @PC+d16,A
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW3+, A addr16, A
+E
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-13 ea Instruction 8 (First Byte = 77H)
CM44-10147-2E
CM44-10147-2E
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
FUJITSU MICROELECTRONICS LIMITED
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
+3
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
+2
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-14 ea Instruction 9 (First Byte = 78H)
655
656
FUJITSU MICROELECTRONICS LIMITED
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
CM44-10147-2E
CM44-10147-2E
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
FUJITSU MICROELECTRONICS LIMITED
657
658
FUJITSU MICROELECTRONICS LIMITED
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
RW0, @RW1+
+9
+A
+B
+C
+D
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
+E
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
CM44-10147-2E
CM44-10147-2E
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
FUJITSU MICROELECTRONICS LIMITED
+F
+E
+D
+C
+B
+A
+9
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW0, R1 @RW0+d16, R1
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
+7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
+6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
+5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
+4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
+3
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
+2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
MB90820B Series
APPENDIX
APPENDIX C Instructions
Table C.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
659
660
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+8
+9
+A
+B
FUJITSU MICROELECTRONICS LIMITED
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
+7
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
+6
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
+5
MOVW
[email protected]
@RW0, RW4 +d16, RW4
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
+4
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
+3
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
+2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX
APPENDIX C Instructions
MB90820B Series
Table C.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
CM44-10147-2E
CM44-10147-2E
40
50
60
70
80
90
A
B0
C0
D0
E0
F0
XCH
XCH
FUJITSU MICROELECTRONICS LIMITED
XCH
XCH
R1,
XCH
XCH
R2,
XCH
XCH
R3,
XCH
XCH
R4,
XCH
XCH
R5,
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+