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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10150-1E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90930 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90930 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
Preface
■ Objectives and Intended Reader
Thank you very much for your continued patronage of Fujitsu Microelectronics products.
The MB90930 series has been developed as one of the general-purpose products of the F2MC16LX family, which is an original 16-bit single-chip microcontroller compatible with the
Application Specific IC (ASIC).
This manual describes the functions and operations of the MB90930 series for engineers who
actually use this semiconductor to design products. Please read this manual first.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
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■ Organization of this manual
This manual consists of the following 27 chapters and 1 appendices:
CHAPTER 1 OVERVIEW
This chapter describes features and provides the basic specification of the MB90930
series.
CHAPTER 2 CPU
This chapter describes F2MC-16LX CPU.
CHAPTER 3 INTERRUPT
This chapter describes the relationships between interrupts and the extended intelligent I/O
service (EI2OS).
CHAPTER 4 RESET
This chapter describes the reset operation.
CHAPTER 5 CLOCK
This chapter describes the clock.
CHAPTER 6 LOW-POWER CONSUMPTION MODE
This chapter explains the low-power consumption mode.
CHAPTER 7 MODE SETTING
This chapter explains the operation mode and memory access mode.
CHAPTER 8 I/O PORTS
This chapter describes the functions and operations of the I/O ports.
CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER
(Sub clock)
This chapter describes the functions and operations of the watchdog timer / time-base
timer / watch timer (sub clock).
CHAPTER 10 INPUT CAPTURE
This chapter describes the input capture operation.
CHAPTER 11 16-BIT RELOAD TIMER
This chapter describes the functions and operations of the 16-bit reload timer.
CHAPTER 12 PPG TIMER
This chapter describes the operations of PPG timer.
CHAPTER 13 REAL-TIME WATCH TIMER
This chapter describes the functions and operations of the real-time watch timer.
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
This chapter describes the functions and operations of the delay interrupt generation
module.
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
This chapter describes the functions and operations of the DTP/external interrupt circuit.
CHAPTER 16 8-/10-BIT A/D CONVERTER
This chapter describes the functions and operations of the 8-/10-bit A/D converter.
CHAPTER 17 LIN-UART
This chapter explains the functions and operations of the LIN-UART.
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CHAPTER 18 CAN CONTROLLER
This chapter describes an overview of the CAN controller and its functions.
CHAPTER 19 LCD CONTROLLER/DRIVER
This chapter describes the functions and operations of the LCD controller/driver.
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
This chapter describes the functions and operations of the low-voltage/CPU operation
detection reset circuit.
CHAPTER 21 STEPPING MOTOR CONTROLLER
This chapter explains the function and operation of a stepping motor controller.
CHAPTER 22 SOUND GENERATOR
This chapter describes the functions and operations of the sound generator.
CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE
This chapter describes the ROM mirror function select module.
CHAPTER 24 1M-BIT FLASH MEMORY
This chapter describes the functions and operations of the 1M-bit flash memory.
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
This chapter gives the examples of connection for serial programming using the AF220/
AF210/AF120/AF110 Flash Microcontroller Programmer manufactured by Yokogawa
Digital Computer Corporation.
CHAPTER 26 ROM SECURITY FUNCTION
This chapter explains the ROM security function.
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
This chapter describes the functions and operations of the address match detection
function.
APPENDIX
The appendix provides the I/O map and describes the available instructions.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS
device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use
based on such information. When you develop equipment incorporating the device based on such information, you
must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS
assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS
warrant non-infringement of any third-party's intellectual property right or other right by using such information.
FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any
claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance
with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control
laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
Copyright ©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.8
2.9
CPU ................................................................................................ 25
Outline of CPU ...................................................................................................................
Memory Space ..................................................................................................................
Memory Map ......................................................................................................................
Addressing .........................................................................................................................
Addressing with Linear Scheme ...................................................................................
Addressing with Bank Scheme .....................................................................................
Allocation of Multiple-Byte Data in the Memory .................................................................
Registers . ..........................................................................................................................
Dedicated Registers ..........................................................................................................
Accumulator (A) ............................................................................................................
Stack Pointers (USP, SSP) ..........................................................................................
Processor Status (PS) ..................................................................................................
Program Counter (PC) ..................................................................................................
Direct Page Register (DPR) .........................................................................................
Bank Registers (PCB, DTB, USB, SSB, ADB) ................. ............................................
General-purpose Register .................................................................................................
Prefix Codes ......................................................................................................................
CHAPTER 3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.6
3.6.1
3.6.2
OVERVIEW ...................................................................................... 1
Overview of MB90930 Series .............................................................................................. 2
Features .. ............................................................................................................................ 3
Block Diagram ..................................................................................................................... 5
Package Dimension ............................................................................................................. 6
Pin Assignment .................................................................................................................... 7
Pin Functions ....................................................................................................................... 8
I/O Circuit Types ................................................................................................................ 17
Precautions for Handling Device ....................................................................................... 21
26
28
30
32
33
34
36
38
39
41
44
46
50
51
52
53
55
INTERRUPT ................................................................................... 61
Outline of Interrupts ...........................................................................................................
Interrupt Sources and Interrupt Vectors ............................................................................
Interrupt Control Registers and Peripheral Functions .......................................................
Interrupt Control Registers (ICR00 to ICR15) ...............................................................
Functions of Interrupt Control Registers .......................................................................
Hardware Interrupt .............................................................................................................
Hardware Interrupt Operation .......................................................................................
Operation Flow of Hardware Interrupt ..........................................................................
Procedure for Using Hardware Interrupt .......................................................................
Multiple Interrupts .........................................................................................................
Hardware Interrupt Processing Time ............................................................................
Software Interrupt ..............................................................................................................
Interrupt by Extended Intelligent I/O Service (EI2OS) . ......................................................
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ...........................................
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) Registers ...........................
v
62
64
66
67
69
72
75
77
78
79
81
82
84
86
87
3.6.3
Operation of the Extended intelligent I/O Service (EI2OS) .. .........................................
3.6.4
Extended Intelligent I/O Service (EI2OS) Procedure ....................................................
3.6.5
Extended Intelligent I/O Service (EI2OS) Processing Time ..........................................
3.7
Exception Handling Interrupt by Execution of Undefined Instruction .................................
3.8
Stack Operations of Interrupt Handling .............................................................................
3.9
Example Program for Interrupt Handling ...........................................................................
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.2.1
5.3
5.4
5.5
5.6
5.7
7.1
7.2
7.3
118
121
123
124
128
130
134
135
LOW-POWER CONSUMPTION MODE ....................................... 137
Overview of the Low-power Consumption Mode .............................................................
Block Diagram of Low-power Consumption Circuit .........................................................
Low-power Consumption Mode Control Register (LPMCR) ............................................
CPU Intermittent Operation Mode ...................................................................................
Standby Mode .................................................................................................................
Sleep Mode ................................................................................................................
Time-base Timer Mode ..............................................................................................
Watch Mode ...............................................................................................................
Stop Mode ..................................................................................................................
State Transition Diagram .................................................................................................
Pin State in the Standby Mode and at the Time of Reset ................................................
Notes on Using the Low-power Consumption Mode .......................................................
CHAPTER 7
104
107
109
110
112
116
CLOCK ......................................................................................... 117
Clock ................................................................................................................................
Block Diagram of the Clock Generation Block .................................................................
Register in the Clock Generation Block ......................................................................
Clock Selection Register (CKSCR) .................................................................................
PLL/Sub clock Control Register (PSCCR) .......................................................................
Clock Mode ......................................................................................................................
Oscillation Stabilization Wait Time ..................................................................................
Connection of Oscillator and External Clock ...................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.6
6.7
6.8
RESET .......................................................................................... 103
Outline of Reset ...............................................................................................................
Reset Sources and Oscillation Stabilization Wait Time ...................................................
External Reset Pin ...........................................................................................................
Reset Operation ..............................................................................................................
Reset Source Bit ..............................................................................................................
State of Each Pin by Reset ..............................................................................................
CHAPTER 5
90
92
93
95
96
98
138
141
143
146
147
149
152
154
156
159
161
163
MODE SETTING .......................................................................... 167
Mode Setting ................................................................................................................... 168
Mode Pins (MD2 to MD0) ................................................................................................ 169
Mode Data ....................................................................................................................... 170
CHAPTER 8
I/O PORTS .................................................................................... 173
8.1
I/O Ports ..........................................................................................................................
8.2
Assignment of Registers and Pins Shared with External Pins ........................................
8.3
Port 0 ...............................................................................................................................
8.3.1
Port 0 Registers (PDR0, DDR0) .................................................................................
vi
174
177
179
181
8.3.2
Description of Port 0 Operation ..................................................................................
8.4
Port 1 ...............................................................................................................................
8.4.1
Port 1 Registers (PDR1, DDR1) .................................................................................
8.4.2
Description of Port 1 Operation ..................................................................................
8.5
Port 2 ...............................................................................................................................
8.5.1
Port 2 Data Register (PDR2, DDR2) ..........................................................................
8.5.2
Description of Port 2 Operation ..................................................................................
8.6
Port 3 ...............................................................................................................................
8.6.1
Port 3 Registers (PDR3, DDR3) .................................................................................
8.6.2
Description of Port 3 Operation ..................................................................................
8.7
Port 4 ...............................................................................................................................
8.7.1
Port 4 Registers (PDR4, DDR4) .................................................................................
8.7.2
Description of Port 4 Operation ..................................................................................
8.8
Port 5 ...............................................................................................................................
8.8.1
Port 5 Registers (PDR5, DDR5) .................................................................................
8.8.2
Description of Port 5 Operation ..................................................................................
8.9
Port 6 ...............................................................................................................................
8.9.1
Port 6 Registers (PDR6, DDR6, ADER6) ...................................................................
8.9.2
Description of Port 6 Operation ..................................................................................
8.10 Port 7 ...............................................................................................................................
8.10.1 Port 7 Registers (PDR7, DDR7, ADER7) ...................................................................
8.10.2 Description of Port 7 Operation ..................................................................................
8.11 Port 8 ...............................................................................................................................
8.11.1 Port 8 Registers (PDR8, DDR8, ADER8) ...................................................................
8.11.2 Description of Port 8 Operation ..................................................................................
8.12 Port 9 ...............................................................................................................................
8.12.1 Registers for Port 9 (PDR9, DDR9) ............................................................................
8.12.2 Description of Port 9 Operation ..................................................................................
8.13 Port C ..............................................................................................................................
8.13.1 Registers for Port C (PDRC, DDRC) ..........................................................................
8.13.2 Description of Port C Operation ..................................................................................
8.14 Port D ..............................................................................................................................
8.14.1 Registers for Port D (PDRD, DDRD) ..........................................................................
8.14.2 Description of Port D Operation ..................................................................................
8.15 Port E ...............................................................................................................................
8.15.1 Registers for Port E (PDRE, DDRE) ...........................................................................
8.15.2 Description of Port E Operation ..................................................................................
8.16 Input Level Select Registers (PIL0 to PIL2) .....................................................................
8.17 Sample Program for I/O Ports .........................................................................................
CHAPTER 9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.4
182
184
186
187
189
191
192
194
196
197
199
201
202
204
207
208
210
212
213
215
218
220
222
225
227
229
231
232
234
237
238
241
244
245
247
249
250
252
255
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER
(Sub clock) .................................................................................. 257
Outline of Watchdog Timer/Time-base Timer/Watch Timer ............................................
Block Diagrams of Watchdog Timer/Time-base Timer/Watch Timer ...............................
List of Registers for Watchdog Timer/Time-base Timer/Watch Timer .............................
Watchdog Timer Control Register (WDTC) ................................................................
Time-base Timer Control Register (TBTC) .................................................................
Watch Timer Control Register (WTC) .........................................................................
Operation of Watchdog Timer/Time-base Timer/Watch Timer ........................................
vii
258
259
260
261
263
265
267
9.4.1
Watchdog Timer Operation ........................................................................................
9.4.2
Operation of Time-base Timer ....................................................................................
9.4.3
Operation of Watch Timer ..........................................................................................
9.5
Notes on Using the Watchdog Timer/Time-base Timer ..................................................
9.6
Program Example for Watchdog Timer/Time-base Timer ...............................................
268
270
273
275
278
CHAPTER 10 INPUT CAPTURE ......................................................................... 281
10.1 Outline of Input Capture ..................................................................................................
10.1.1 Block Diagram of Input Capture .................................................................................
10.2 List of Input Capture Registers ........................................................................................
10.2.1 Detailed Description of the Input Capture Registers ..................................................
10.2.2 Input Capture Edge Register (ICE) .............................................................................
10.2.3 Detailed Description of 16-Bit Free-run Timer Register ..............................................
10.3 Description of Operations ................................................................................................
10.3.1 16-bit Input Capture ....................................................................................................
10.3.2 16-bit Free-run Timer ..................................................................................................
282
283
285
288
291
295
300
301
302
CHAPTER 11 16-BIT RELOAD TIMER .............................................................. 305
11.1 Overview of 16-bit Reload Timer .....................................................................................
11.2 Configuration of 16-bit Reload Timer ...............................................................................
11.3 Pins of 16-bit Reload Timer .............................................................................................
11.4 Registers of 16-bit Reload Timer .....................................................................................
11.4.1 Timer Control Status Registers, Upper (TMCSR0H to TMCSR3H) ..........................
11.4.2 Timer Control Status Registers, Lower (TMCSR0L to TMCSR3L) .............................
11.4.3 16-bit Timer Registers (TMR0 to TMR3) ....................................................................
11.4.4 16-bit Reload Registers (TMRLR0 to TMRLR3) .........................................................
11.5 Interrupts of 16-bit Reload Timer .....................................................................................
11.6 Operation of 16-bit Reload Timer ....................................................................................
11.6.1 Internal Clock Mode (Reload Mode) ...........................................................................
11.6.2 Internal Clock Mode (One Shot Mode) .......................................................................
11.6.3 Event Count Mode ......................................................................................................
11.7 Notes on Using 16-bit Reload Timer ...............................................................................
11.8 Sample Program for 16-bit Reload Timer ........................................................................
306
309
311
313
314
316
318
319
320
321
323
325
327
329
330
CHAPTER 12 PPG TIMER .................................................................................. 333
12.1 Overview of PPG Timer ...................................................................................................
12.2 Block Diagram of PPG Timer ..........................................................................................
12.3 Registers of PPG Timer ...................................................................................................
12.3.1 List of PPG Timer Registers .......................................................................................
12.3.2 Detailed Description of PPG Timer .............................................................................
12.4 Interrupt of PPG Timer ....................................................................................................
12.5 PPG Timer Operation ......................................................................................................
12.5.1 PWM Operation ..........................................................................................................
12.5.2 One Shot Operation ....................................................................................................
12.5.3 Interrupt Source and Timing .......................................................................................
334
335
336
337
339
346
348
349
351
352
CHAPTER 13 REAL-TIME WATCH TIMER ........................................................ 353
13.1
13.2
Overview of Real-Time Watch Timer ............................................................................... 354
Registers of Real-Time Watch Timer .............................................................................. 355
viii
13.2.1 Real-Time Watch Timer Control Register ...................................................................
13.2.2 Sub-Second Data Register .........................................................................................
13.2.3 Second/Minute/Hour/Day Data Registers ...................................................................
13.3 Interrupts of Real-Time Watch Timer ..............................................................................
357
359
360
362
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE .......................... 363
14.1
14.2
Overview of Delay Interrupt Generation Module ............................................................. 364
Operation of Delay Interrupt Generation Module ............................................................. 365
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT ..................................... 367
15.1 Overview of DTP/External Interrupt Circuit ......................................................................
15.2 Configuration of DTP/External Interrupt Circuit ...............................................................
15.3 Pins of DTP/External Interrupt Circuit ..............................................................................
15.4 Registers of DTP/External Interrupt Circuit .....................................................................
15.4.1 External Interrupt Source Register (EIRR) .................................................................
15.4.2 External Interrupt Enable Register (ENIR) .................................................................
15.4.3 External Interrupt Level Setting Register (ELVRH/ELVRL) ........................................
15.5 Operations of DTP/External Interrupt Circuit ...................................................................
15.5.1 External Interrupt Function .........................................................................................
15.5.2 DTP Function ..............................................................................................................
15.6 Notes on Using the DTP/External Interrupt Circuit ..........................................................
15.7 Sample Programs of DTP/External Interrupt Circuit ........................................................
368
370
372
373
374
375
376
377
380
381
382
384
CHAPTER 16 8-/10-BIT A/D CONVERTER ........................................................ 387
16.1 Overview of 8-/10-bit A/D Converter ................................................................................
16.2 Block Diagram of 8-/10-bit A/D Converter .......................................................................
16.3 Configuration of 8-/10-bit A/D Converter .........................................................................
16.3.1 Upper bits in the A/D control status register (ADCS1) ................................................
16.3.2 Lower Bits in the A/D Control Status Register (ADCS0) ............................................
16.3.3 A/D Data Registers (ADCR0/ADCR1) ........................................................................
16.3.4 A/D Setting Registers (ADSR0/ADSR1) .....................................................................
16.3.5 Analog Input Enable Registers (ADER6,7,8) ..............................................................
16.4 Interrupts of 8-/10-bit A/D Converter ...............................................................................
16.5 Explanation of 8-/10-bit A/D Converter Operations .........................................................
16.5.1 Single Conversion Mode ............................................................................................
16.5.2 Continuous Conversion Mode ....................................................................................
16.5.3 Stop Conversion Mode ...............................................................................................
16.5.4 Conversion Operation by EI2OS Function ..................................................................
16.5.5 A/D Conversion Data Protection Function ..................................................................
16.6 Precautions when Using 8-/10-bit A/D Converter ............................................................
388
390
393
396
401
403
404
408
410
411
413
415
417
419
420
424
CHAPTER 17 LIN-UART ..................................................................................... 425
17.1 Overview of LIN-UART ....................................................................................................
17.2 Configuration of LIN-UART ..............................................................................................
17.3 Pins of LIN-UART ............................................................................................................
17.4 LIN-UART Registers ........................................................................................................
17.4.1 Serial Control Register (SCR) ....................................................................................
17.4.2 LIN-UART Serial Mode Register (SMR) .....................................................................
17.4.3 Serial Status Register (SSR) ......................................................................................
ix
426
429
434
436
437
439
441
17.4.4 Reception Data Register and Transmission Data Register (RDR/TDR) ....................
17.4.5 Extended Status Control Register (ESCR) .................................................................
17.4.6 Extended Communication Control Register (ECCR) ..................................................
17.4.7 Baud Rate Generator Registers 0 and 1 (BGRn0/BGRn1) ........................................
17.5 Interrupts of LIN-UART ....................................................................................................
17.5.1 Timing of Reception Interrupt Generation and Flag Set .............................................
17.5.2 Timing of Transmission Interrupt Generation and Flag Set ........................................
17.6 LIN-UART Baud Rates ....................................................................................................
17.6.1 Setting the Baud Rate ................................................................................................
17.6.2 Reload counter ...........................................................................................................
17.7 Operation of LIN-UART ...................................................................................................
17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ..................................
17.7.2 Operation in Synchronous Mode (Operating Mode 2) ................................................
17.7.3 Operation with LIN Function (Operation Mode 3) .......................................................
17.7.4 Serial Pin Direct Access .............................................................................................
17.7.5 Bidirectional Communication Function (Normal Mode) ..............................................
17.7.6 Master/Slave Type Communication Function (Multiprocessor Mode) ........................
17.7.7 LIN Communication Function .....................................................................................
17.7.8 Sample Flowcharts for LIN-UART in LIN Communication (Operation Mode 3) ..........
17.8 Notes on Using LIN-UART ..............................................................................................
443
445
447
449
450
453
455
457
459
462
464
466
470
473
476
477
479
482
483
485
CHAPTER 18 CAN CONTROLLER .................................................................... 487
18.1 Features of CAN Controller .............................................................................................
18.2 Block Diagram of CAN Controller ....................................................................................
18.3 Classification of CAN Controller Registers ......................................................................
18.3.1 Control Status Register (CSR) ...................................................................................
18.3.2 Last Event Indication Register (LEIR) ........................................................................
18.3.3 Receive and Transmit Error Counters (RTEC) ...........................................................
18.3.4 Bit Timing Register (BTR) ...........................................................................................
18.3.5 Message Buffer Valid Register (BVALR) ....................................................................
18.3.6 IDE Register (IDER) ...................................................................................................
18.3.7 Transmission Request Register (TREQR) .................................................................
18.3.8 Transmission RTR register (TRTRR) .........................................................................
18.3.9 Remote Frame Receive Wait Register (RFWTR) .......................................................
18.3.10 Transmission Cancel Register (TCANR) ....................................................................
18.3.11 Transmission Complete Register (TCR) .....................................................................
18.3.12 Transmission Interrupt Enable Register (TIER) ..........................................................
18.3.13 Receive Complete Register (RCR) .............................................................................
18.3.14 Remote Request Receive Register (RRTRR) ............................................................
18.3.15 Receive Overrun Register (ROVRR) ..........................................................................
18.3.16 Receive Interrupt Enable Register (RIER) ..................................................................
18.3.17 Acceptance Mask Selection Register (AMSR) ...........................................................
18.3.18 Acceptance Mask Registers 0 and 1 (AMR0/AMR1) ..................................................
18.3.19 Message Buffers .........................................................................................................
18.3.20 ID Register x (x = 0 to 15) (IDRx) ...............................................................................
18.3.21 DLC Register x (x = 0 to 15) (DLCRx) ........................................................................
18.3.22 Data Register x (x = 0 to 15) (DTRx) ..........................................................................
18.4 CAN Controller Transmission ..........................................................................................
18.5 CAN Controller Reception ...............................................................................................
x
488
489
490
499
503
505
506
509
510
511
512
513
514
515
516
517
518
519
520
521
523
525
526
530
531
533
536
18.6
18.7
18.8
18.9
18.10
18.11
18.12
Using CAN Controller ......................................................................................................
Procedure of Transmission via Message Buffer (x) .........................................................
Procedure of Reception Via Message Buffer (x) .............................................................
Specifying the Multi-level Message Buffer Configuration ................................................
CAN WAKE UP Function .................................................................................................
Precautions When Using CAN Controller ........................................................................
Sample Program of CAN .................................................................................................
540
541
543
545
547
548
549
CHAPTER 19 LCD CONTROLLER/DRIVER ...................................................... 551
19.1 Overview of LCD Controller/Driver ..................................................................................
19.2 Configuration of LCD Controller/Driver ............................................................................
19.2.1 Internal Divided Resistor of LCD Controller/Driver .....................................................
19.2.2 External Divided Resistor of LCD Controller/Driver ....................................................
19.3 LCD Controller/Driver Pins ..............................................................................................
19.4 Registers of LCD Controller/Driver ..................................................................................
19.4.1 Lower Bits in the LCD Control Register (LCRL) .........................................................
19.4.2 Upper Bits in the LCD Control Register (LCRH) .........................................................
19.4.3 LCD Output Control Register 2/1 (LOCR2/LOCR1) ...................................................
19.4.4 LCD Output Control Register 3 (LOCR3) ...................................................................
19.5 LCD Controller/Driver Display RAM ................................................................................
19.6 Operation of LCD Controller/Driver .................................................................................
19.6.1 Output Waveform during the LCD Controller/Driver Operation (1/2 Duty) .................
19.6.2 Output Waveform during the LCD Controller/Driver Operation (1/3 Duty) .................
19.6.3 Output Waveform during the LCD Controller/Driver Operation (1/4 Duty) .................
552
553
555
557
559
561
562
564
566
569
570
574
576
579
582
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
.................................................................................................... 585
20.1
20.2
20.3
20.4
20.5
20.6
Overview of the Low-voltage/CPU Operation Detection Reset .......................................
Configuration of the Low-Voltage/CPU Operation Detection ...........................................
Register of the Low-voltage/CPU Operation Detection Reset Circuit ..............................
Operation of the Low-voltage/CPU Operation Detection Reset Circuit ...........................
Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit ......................
Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit ...............
586
588
590
592
593
594
CHAPTER 21 STEPPING MOTOR CONTROLLER ........................................... 595
21.1 Overview of Stepping Motor Controller ............................................................................
21.2 Registers for Stepping Motor Controller ..........................................................................
21.2.1 PWM Control Register ................................................................................................
21.2.2 PWM1&2 Compare Registers ....................................................................................
21.2.3 PWM1&2 Selection Registers ....................................................................................
21.3 Operation of Stepping Motor Controller ...........................................................................
21.4 Cautions when Using Stepping Motor Controller .............................................................
596
597
598
600
602
605
607
CHAPTER 22 SOUND GENERATOR ................................................................. 609
22.1 Outline of the Sound Generator .......................................................................................
22.2 Registers of the Sound Generator ...................................................................................
22.2.1 Sound Control Register(SGCRH0/SGCRH1, SGCRL0/SGCRL1) .............................
22.2.2 Frequency Data Register(SGFR0/SGFR1) ................................................................
22.2.3 Amplitude Data Register(SGAR0/SGAR1) .................................................................
xi
610
611
613
615
616
22.2.4
22.2.5
Decrement Grade Register(SGDR0/SGDR1) ............................................................ 617
Tone Count Register(SGTR0/SGTR1) ....................................................................... 618
CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE .......................... 619
23.1
23.2
Outline of the ROM Mirror Function Select Module ......................................................... 620
ROM Mirror Function Select Register (ROMM) ............................................................... 621
CHAPTER 24 1M-BIT FLASH MEMORY ............................................................ 623
24.1 Overview of 1M-bit Flash Memory ...................................................................................
24.2 Sector Configuration of 1M-bit Flash Memory .................................................................
24.3 Flash Memory Control Status Register (FMCS) ..............................................................
24.4 Flash Memory Write Control Registers (FWR0/FWR1) ...................................................
24.5 Starting the Flash Memory Automatic Algorithm .............................................................
24.6 Confirming the Automatic Algorithm Execution State ......................................................
24.6.1 Data Polling Flag (DQ7) .............................................................................................
24.6.2 Toggle Bit Flag (DQ6) .................................................................................................
24.6.3 Timing Limit Exceeded Flag (DQ5) ............................................................................
24.6.4 Sector Erase Timer Flag (DQ3) ..................................................................................
24.7 Writing/Erasing Flash Memory ........................................................................................
24.7.1 Setting Flash Memory to the Read/Reset State .........................................................
24.7.2 Writing Data to Flash Memory ....................................................................................
24.7.3 Erasing All Data of Flash Memory (Chip Erase) .........................................................
24.7.4 Erasing Arbitrary Data of Flash Memory (Sector Erase) ............................................
24.7.5 Suspending Sector Erase of Flash Memory ...............................................................
24.7.6 Restarting Sector Erase of Flash Memory ..................................................................
24.8 Flash Security Function ...................................................................................................
624
625
626
628
633
634
635
636
637
638
639
640
641
643
644
646
647
648
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ....... 649
25.1
25.2
25.3
Basic Configuration for Serial Programming Connection ................................................ 650
Example of Connection in Single-Chip Mode (Using Power from User System) ............. 654
Example of Connection with Flash Microcontroller Programmer
(Using Power from the User System) .............................................................................. 656
CHAPTER 26 ROM SECURITY FUNCTION ....................................................... 659
26.1
Overview of ROM Security Function ............................................................................... 660
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION ............................. 661
27.1 Outline of the Address Match Detection Function ...........................................................
27.2 Sample Application of the Address Match Detection Function ........................................
27.2.1 Example of Program Error Correction ........................................................................
27.2.2 Example of Correction Processing .............................................................................
662
665
667
668
APPENDIX ............................................................................................................. 671
APPENDIX A I/O Maps ...............................................................................................................
APPENDIX B Instructions ............................................................................................................
B.1 Instruction Types .............................................................................................................
B.2 Addressing . .....................................................................................................................
B.3 Direct Addressing ............................................................................................................
B.4 Indirect Addressing .........................................................................................................
xii
672
702
703
704
706
712
B.5
B.6
B.7
B.8
B.9
Execution Cycle Count ....................................................................................................
Effective address field .....................................................................................................
How to Read the Instruction List .....................................................................................
F2MC-16LX Instruction List .............................................................................................
Instruction Map ................................................................................................................
720
723
724
727
741
INDEX ......................................................................................................................763
xiii
xiv
Main changes in this edition.
Page
-
Changes (For details, refer to main body.)
First edition
xv
xvi
CHAPTER 1
OVERVIEW
This chapter describes features and provides
the basic specification of the MB90930 series.
1.1 Overview of MB90930 Series
1.2 Features
1.3 Block Diagram
1.4 Package Dimension
1.5 Pin Assignment
1.6 Pin Functions
1.7 I/O Circuit Types
1.8 Precautions for Handling Device
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
1
CHAPTER 1 OVERVIEW
1.1 Overview of MB90930 Series
1.1
MB90930 Series
Overview of MB90930 Series
This section outlines MB90930 series products.
■ Overview of MB90930 Series
Table 1.1-1 gives an outline of MB90930 series products.
Table 1.1-1 Outline of MB90930 Series Products
Features
MB90V930- MB90V930102
101
Models available
Evaluation product
MB90F931
MB90F931S
MB90931
Flash memory product
MB90931S
Mask ROM product
CPU
F2MC-16LX CPU
Clock
Single clock / Dual clock (Optional selection: Single clock product uses X0A/X1A as ports)
System clock
On-chip PLL clock multiplication scheme
(×1, ×2, ×3, ×4, ×6, ×8, and 1/2 for PLL stop)
Minimum instruction execution time: 31.25ns (4 MHz oscillation ×8)
Sub clock pins
(X0A, X1A)
Yes
No
Yes
No
Yes
ROM
External
128Kbyte
RAM
30Kbyte
8Kbyte
No
Yes
PGA-299
LQFP-120
No
-
Low-voltage/CPU
operation
detection reset
Package
Emulatordedicated power
supply
2
FUJITSU MICROELECTRONICS LIMITED
No
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.2 Features
MB90930 Series
1.2
Features
This section describes the features of MB90930 series.
■ Features
Table 1.2-1 shows the features of MB90930 series.
Table 1.2-1 Features of MB90930 Series (1 / 2)
Function
Features
16-bit reload timer
(4 channels)
Allows 16-bit reload timer operations (e.g. toggle output and one shot output
selectable) and the selection of the event count function.
16-bit free-run timer
(1 channel)
Outputs an interrupt signal when an overflow occurs.
Operation clock frequency:
fsys, fsys/2, fsys/4, fsys/8, fsys/16, fsys/32, fsys/64, fsys/128
(fsys = system clock frequency)
16-bit input capture
(8 channels)
Detects a rising edge, falling edge or both edges.
16-bit capture register × 8
Latches the counter value of the 16-bit free-run timer upon edge detection of pin
input and generates an interrupt request.
PPG timer
(6 channels)
Output pin × 3, external trigger input pin × 1
Operation clock frequency: FCP, FCP/22, FCP/24, FCP/26
LIN UART
(4 channels)
Uses a dedicated reload timer to allow a wide range of communication speeds to be
set.
The LIN function can be used as the LIN master or a LIN slave.
LCD controller
(1 channel)
Segment driver and common driver can drive an LCD panel (liquid crystal display)
directly.
A/D converter
(24 channels)
Resolution of 10 bits or 8 bits × 24 channels (input multiplex)
Conversion time: 3 μs or less (fcp=32MHz)
Allows external trigger activation (P50/INT0/ADTG).
Can be activated by an internal timer (16-bit reload timer 1)
CAN
(1 channel)
Conforms to CAN specification version 2.0 part A and part B.
Automatic retransmission is executed if an error occurs.
Automatic transmission is executed in response to a remote frame.
Supports data and multiple messages for 16 prioritized message buffers for ID.
Flexible configuration of acceptance filter:
All bit compare/all bit mask/two partial bit masks
Supports up to 1 Mbps.
CAN wake up function
Note:
Stepping motor
controller
(4 channels)
CM44-10150-1E
CAN1 share the transmission/reception pin and the interrupt control
registers; therefore, simultaneous transmission/reception can be performed at
2 channels. These CAN’s can be used as if 2 channels of 32-message buffer
CAN were available.
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
FUJITSU MICROELECTRONICS LIMITED
3
CHAPTER 1 OVERVIEW
1.2 Features
MB90930 Series
Table 1.2-1 Features of MB90930 Series (2 / 2)
Function
4
Features
Sound generator
(2 channels)
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter.
PWM frequency: 125kHz, 62.5kHz, 31.2kHz, 15.6kHz (when fcp = 32 MHz)
Tone frequency: PWM frequency /2/ (reload value +1)
External interrupt
(8 channels)
8 independent channels
Interrupt sources: "L" → "H" edge/"H" → "L" edge/"L" level/"H" level can be selected.
Real time watch timer
(1 channel)
Directly driven by the oscillation clock.
Supports the correction of oscillation deviations.
Built-in subsecond/second/minute/hour/day registers
Signal interrupt
Low-voltage /CPU
operation detection
reset
Automatically reset if low-voltage is detected.
CPU operation detection function
Input level
Automotive (0.8Vcc/0.5Vcc) (initial value)
CMOS Hysteresis (0.8Vcc/0.2Vcc)
CMOS (0.7Vcc/0.3Vcc) (SIN only) can be selected
Input/output port
Push-pull output and Schmitt trigger input
Programmable in units of individual bits as input/output or peripheral signal.
Flash memory
Supports automatic programming, Embedded Algorithm™, write/delete/delete
suspend/delete resume commands.
Flag for indicating completion of algorithm processing.
Number of delete cycles: 10,000 cycles
Data retention period: 10 years
Boot block configuration
Can execute a delete operation for each block.
External programming voltage is used to protect the blocks.
Flash Security Feature for protecting the content of the Flash memory.
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.3 Block Diagram
MB90930 Series
1.3
Block Diagram
This section shows a block diagram of MB90930 series products.
■ Block Diagram
Figure 1.3-1 shows a block diagram of MB90930 series products.
Figure 1.3-1 Block Diagram of MB90930 Series
Clock control circuit
CPU
F2MC-16LX core
Watchdog timer
Time-base timer
Interrupt controller
Watch timer (sub)
Low-voltage reset
Sound generator 0
Sound generator 1
CPU operation
detection reset
CAN controller 1
External interrupt
(8 channels)
16-bit PPG timer 0
16-bit PPG timer 1
16-bit PPG timer 2
16-bit PPG timer 3
16-bit PPG timer 4
16-bit PPG timer 5
16-bit reload timer 0
16-bit reload timer 1
16-bit reload timer 2
16-bit reload timer 3
Stepping motor controller 1
Stepping motor controller 2
F2MC-16LX BUS
LIN-UART 0
Prescaler 0
LIN-UART 1
Prescaler 1
LIN-UART 2
Prescaler 2
LIN-UART 3
Prescaler 3
Stepping motor controller 0
Stepping motor controller 3
A/D converter
(24 channels)
LCD controller/driver
(32 SEG/4 COM)
RAM
(8 Kbytes)*
Flash/ROM
(128 Kbytes)
Real-time watch timer
16-bit ICU 0 (2 channels)
16-bit ICU 1 (2 channels)
16-bit ICU 2 (2 channels)
16-bit ICU 3 (2 channels)
16-bit free-run timer
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
5
CHAPTER 1 OVERVIEW
1.4 Package Dimension
1.4
MB90930 Series
Package Dimension
This section shows a package dimension of MB90930 series products.
■ Package Dimension
Figure 1.4-1 shows a package dimension.
Figure 1.4-1 Package Dimension
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
18.00±0.20(.709±.008)SQ
16.00±0.10(.630±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
INDEX
120
LEAD No.
1
30
0.50(.020)
C
0~8°
"A"
31
0.22±0.05
(.009±.002)
+0.05
0.08(.003)
M
2001-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-3-4
0.145 –0.03
+.002
.006 –.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
6
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
MB90930 Series
1.5
Pin Assignment
CHAPTER 1 OVERVIEW
1.5 Pin Assignment
This section shows the pin assignment of MB90930 series products.
■ Pin Assignment
Figure 1.5-1 shows the pin assignment.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
DVSS
DVCC
P87/PWM2M3/AN23
P86/PWM2P3/AN22
P85/PWM1M3/AN21
P84/PWM1P3/AN20
P83/PWM2M2/AN19
P82/PWM2P2/AN18
P81/PWM1M2/AN17
P80/PWM1P2/AN16
DVSS
DVCC
P77/PWM2M1/AN15
P76/PWM2P1/AN14
P75/PWM1M1/AN13
P74/PWM1P1/AN12
P73/PWM2M0/AN11
P72/PWM2P0/AN10
P71/PWM1M0/AN09
P70/PWM1P0/AN08
DVSS
DVCC
PE2/SGO1/IN3R
P55/INT2
RSTO
P54/SGA1/IN2R
P94/V0
P95/V1
P96/V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PC0/SIN0/INT4
PC1/SOT0/INT5/IN3
PC2/SCK0/INT6/IN2
PC3/SIN1/INT7
PC4/SOT1
PC5/SCK1/TRG
PC6/PPG0/TOT1/IN7
PC7/PPG1/TIN1/IN6
PE0/TOT3/IN7R
PE1/TIN3IN6R
P51/INT1/RX1
P52/TX1
P53/INT3
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P30/SEG06
P31/SEG07
P32/SEG08
P33/SEG09
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P92/X0A*1
P93/X1A*2
VCC
VSS
C
P44/SEG18
P45/SEG19
P46/SEG20
P47/SEG21
P90/SEG22
P91/SEG23
PD0/SIN2
PD1/SOT2
PD2/SCK2
PD3/SIN3
PD4/SOT3
PD5/SCK3
PD6/TOT2
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/SEG05
P26/SEG04
P25/SEG03
P24/SEG02
P23/SEG01
P22/SEG00
COM3
COM2
COM1
COM0
P15/IN0
P14/TIN2/IN1
X0
X1
VSS
VCC
P13/PPG5
P12/TIN0/PPG4
P11/TOT0/PPG3/IN4
P10/PPG2/IN5
P07/SEG31
P06/EG30
P05/SEG29
P04/SEG28
P03/SEG27
P02/SEG26
P01/SEG25
P00/SEG24
P57/SGA0/IN4R
P56/SGO0/FRCK/IN5R
Figure 1.5-1 Pin Assignment
*1: X0A pin is optional (dual clock products only).
*2: X1A pin is optional (dual clock products only).
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
7
CHAPTER 1 OVERVIEW
1.6 Pin Functions
1.6
MB90930 Series
Pin Functions
This section describes the pin functions of MB90930 series products.
■ Description of Pin Functions
Table 1.6-1 describes the pin functions.
Table 1.6-1 Pin Functions (1 / 9)
Pin no.
108
Pin name
I/O Circuit
type *1
X0
Description
High speed oscillator input pin.
A
107
X1
High speed oscillator output pin.
X0A
B
Low speed oscillator input pin. *2
P92
I
General-purpose I/O port.
X1A
B
Low speed oscillator output pin.*3
P93
I
General-purpose I/O port.
RST
C
Reset input pin.
13
14
90
P00
93
General-purpose I/O port.
F
SEG24
LCD controller/driver segment output pin.
P01
94
General-purpose I/O port.
F
SEG25
LCD controller/driver segment output pin.
P02
95
General-purpose I/O port.
F
SEG26
LCD controller/driver segment output pin.
P03
96
General-purpose I/O port.
F
SEG27
LCD controller/driver segment output pin.
P04
97
General-purpose I/O port.
F
SEG28
LCD controller/driver segment output pin.
P05
98
General-purpose I/O port.
F
SEG29
LCD controller/driver segment output pin.
P06
99
General-purpose I/O port.
F
SEG30
LCD controller/driver segment output pin.
P07
100
101
SEG31
LCD controller/driver segment output pin.
P10
General-purpose I/O port.
PPG2
IN5
8
General-purpose I/O port.
F
I
16-bit PPG ch.2 output pin.
Input capture ch.5 trigger input pin.
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (2 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P11
General-purpose I/O port.
TOT0
102
103
16-bit reload timer ch.0 TOT output pin.
I
PPG3
16-bit PPG ch.3 output pin.
IN4
Input capture ch.4 trigger input pin.
P12
General-purpose I/O port.
TIN0
I
PPG4
16-bit reload timer ch.0 TIN input pin.
16-bit PPG ch.4 output pin.
P13
104
109
Description
General-purpose I/O port.
I
PPG5
16-bit PPG ch.5 output pin.
P14
General-purpose I/O port.
TIN2
I
IN1
Input capture ch.1 trigger input pin.
P15
110
16-bit reload timer ch.2 TIN input pin.
General-purpose I/O port.
I
IN0
Input capture ch.0 trigger input pin.
111
COM0
P
LCD controller/driver common output pin.
112
COM1
P
LCD controller/driver common output pin.
113
COM2
P
LCD controller/driver common output pin.
114
COM3
P
LCD controller/driver common output pin.
P22
115
General-purpose I/O port.
F
SEG00
LCD controller/driver segment output pin.
P23
116
General-purpose I/O port.
F
SEG01
LCD controller/driver segment output pin.
P24
117
General-purpose I/O port.
F
SEG02
LCD controller/driver segment output pin.
P25
118
General-purpose I/O port.
F
SEG03
LCD controller/driver segment output pin.
P26
119
General-purpose I/O port.
F
SEG04
LCD controller/driver segment output pin.
P27
120
General-purpose I/O port.
F
SEG05
LCD controller/driver segment output pin.
P30
1
General-purpose I/O port.
F
SEG06
CM44-10150-1E
LCD controller/driver segment output pin.
FUJITSU MICROELECTRONICS LIMITED
9
CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (3 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P31
2
General-purpose I/O port.
F
SEG07
LCD controller/driver segment output pin.
P32
3
General-purpose I/O port.
F
SEG08
LCD controller/driver segment output pin.
P33
4
General-purpose I/O port.
F
SEG09
LCD controller/driver segment output pin.
P34
5
General-purpose I/O port.
F
SEG10
LCD controller/driver segment output pin.
P35
6
General-purpose I/O port.
F
SEG11
LCD controller/driver segment output pin.
P36
7
General-purpose I/O port.
F
SEG12
LCD controller/driver segment output pin.
P37
8
General-purpose I/O port.
F
SEG13
LCD controller/driver segment output pin.
P40
9
General-purpose I/O port.
F
SEG14
LCD controller/driver segment output pin.
P41
10
General-purpose I/O port.
F
SEG15
LCD controller/driver segment output pin.
P42
11
General-purpose I/O port.
F
SEG16
LCD controller/driver segment output pin.
P43
12
General-purpose I/O port.
F
SEG17
LCD controller/driver segment output pin.
P44
18
General-purpose I/O port.
F
SEG18
LCD controller/driver segment output pin.
P45
19
General-purpose I/O port.
F
SEG19
10
Description
LCD controller/driver segment output pin.
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (4 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P46
20
General-purpose I/O port.
F
SEG20
LCD controller/driver segment output pin.
P47
21
37
58
General-purpose I/O port.
F
SEG21
LCD controller/driver segment output pin.
P50
General-purpose I/O port.
INT0
I
A/D converter external trigger input pin.
P51
General-purpose I/O port.
INT1
I
INT1 external interrupt input pin.
CAN interface 1 RX input pin.
P52
59
General-purpose I/O port.
I
TX1
CAN interface 1 TX output pin.
P53
60
General-purpose I/O port.
I
INT3
INT3 external interrupt input pin.
P54
General-purpose I/O port.
SGA1
I
IN2R
Sound generator ch.1 SGA output pin.
Input capture ch.2 trigger input pin.
P55
63
General-purpose I/O port.
I
INT2
INT2 external interrupt input pin.
P56
General-purpose I/O port.
SGO0
91
92
INT0 external interrupt input pin.
ADTG
RX1
61
Description
Sound generator ch.0 SGO output pin.
I
FRCK
Free-run timer clock input pin.
IN5R
Input capture ch.5 trigger input pin.
P57
General-purpose I/O port.
SGA0
I
IN4R
Input capture ch.4 trigger input pin.
P60
39
Sound generator ch.0 SGA output pin.
General-purpose I/O port.
H
AN0
A/D converter input pin.
P61
40
General-purpose I/O port.
H
AN1
A/D converter input pin.
P62
41
General-purpose I/O port.
H
AN2
CM44-10150-1E
A/D converter input pin.
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (5 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P63
42
General-purpose I/O port.
H
AN3
A/D converter input pin.
P64
43
General-purpose I/O port.
H
AN4
A/D converter input pin.
P65
44
General-purpose I/O port.
H
AN5
A/D converter input pin.
P66
45
General-purpose I/O port.
H
AN6
A/D converter input pin.
P67
46
67
68
69
70
71
72
73
General-purpose I/O port.
H
AN7
A/D converter input pin.
P70
General-purpose output-only port.
PWM1P0
L
Stepping motor controller ch.0 output pin.
AN8
A/D converter input pin.
P71
General-purpose output-only port.
PWM1M0
L
Stepping motor controller ch.0 output pin.
AN9
A/D converter input pin.
P72
General-purpose output-only port.
PWM2P0
L
Stepping motor controller ch.0 output pin.
AN10
A/D converter input pin.
P73
General-purpose output-only port.
PWM2M0
L
Stepping motor controller ch.0 output pin.
AN11
A/D converter input pin.
P74
General-purpose output-only port.
PWM1P1
L
Stepping motor controller ch.1 output pin.
AN12
A/D converter input pin.
P75
General-purpose output-only port.
PWM1M1
L
Stepping motor controller ch.1 output pin.
AN13
A/D converter input pin.
P76
General-purpose output-only port.
PWM2P1
AN14
12
Description
L
Stepping motor controller ch.1 output pin.
A/D converter input pin.
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (6 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P77
74
77
78
79
80
81
82
83
84
PWM2M1
Description
General-purpose output-only port.
L
Stepping motor controller ch.1 output pin.
AN15
A/D converter input pin.
P80
General-purpose output-only port.
PWM1P2
L
Stepping motor controller ch.2 output pin.
AN16
A/D converter input pin.
P81
General-purpose output-only port.
PWM1M2
L
Stepping motor controller ch.2 output pin.
AN17
A/D converter input pin.
P82
General-purpose output-only port.
PWM2P2
L
Stepping motor controller ch.2 output pin.
AN18
A/D converter input pin.
P83
General-purpose output-only port.
PWM2M2
L
Stepping motor controller ch.2 output pin.
AN19
A/D converter input pin.
P84
General-purpose output-only port.
PWM1P3
L
Stepping motor controller ch.3 output pin.
AN20
A/D converter input pin.
P85
General-purpose output-only port.
PWM1M3
L
Stepping motor controller ch.3 output pin.
AN21
A/D converter input pin.
P86
General-purpose output-only port.
PWM2P3
L
Stepping motor controller ch.3 output pin.
AN22
A/D converter input pin.
P87
General-purpose output-only port.
PWM2M3
L
AN23
A/D converter input pin.
P90
22
Stepping motor controller ch.3 output pin.
General-purpose I/O port.
F
SEG22
LCD controller/driver segment output pin.
P91
23
General-purpose I/O port.
F
SEG23
LCD controller/driver segment output pin.
P94
31
General-purpose I/O port.
G
V0
CM44-10150-1E
LCD controller/driver reference power supply pin.
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (7 / 9)
Pin no.
Pin name
I/O Circuit
type *1
P95
32
General-purpose I/O port.
G
V1
LCD controller/driver reference power supply pin.
P96
33
General-purpose I/O port.
G
V2
34
V3
LCD controller/driver reference power supply pin.
-
PC0
48
SIN0
General-purpose I/O port.
J
PC1
General-purpose I/O port.
UART ch.0 serial data output pin.
I
INT5
INT5 external interrupt input pin.
IN3
Input capture ch.3 trigger input pin.
PC2
General-purpose I/O port.
SCK0
50
UART ch.0 serial clock I/O pin.
I
INT6
INT6 external interrupt input pin.
IN2
Input capture ch.2 trigger input pin.
PC3
General-purpose I/O port.
SIN1
J
INT7
UART ch.1 serial data input pin.
INT7 external interrupt input pin.
PC4
52
General-purpose I/O port.
I
SOT1
UART ch.0 serial data output pin.
PC5
General-purpose I/O port.
SCK1
I
UART ch.1 serial clock I/O pin.
TRG
16-bit PPG ch.0 to ch5 external trigger input pin.
PC6
General-purpose I/O port.
PPG0
54
16-bit PPG ch.0 output pin.
I
TOT1
16-bit reload timer ch.1 TOT output pin.
IN7
Input capture ch.7 trigger input pin.
PC7
General-purpose I/O port.
PPG1
55
14
UART ch.0 serial data input pin.
INT4 external interrupt input pin.
SOT0
53
LCD controller/driver reference power supply pin.
INT4
49
51
Description
16-bit PPG ch.1 output pin.
I
TIN1
16-bit reload timer ch.1 TIN input pin.
IN6
Input capture ch.6 trigger input pin.
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (8 / 9)
Pin no.
Pin name
I/O Circuit
type *1
PD0
24
General-purpose I/O port.
J
SIN2
UART ch.2 serial data input pin.
PD1
25
General-purpose I/O port.
I
SOT2
UART ch.2 serial data output pin.
PD2
26
General-purpose I/O port.
F
SCK2
UART ch2 serial clock I/O pin.
PD3
27
General-purpose I/O port.
J
SIN3
UART ch.3 serial data input pin.
PD4
28
General-purpose I/O port.
I
SOT3
UART ch.3 serial data output pin.
PD5
29
General-purpose I/O port.
F
SCK3
UART ch.3 serial clock I/O pin.
PD6
30
56
57
64
Description
General-purpose I/O port.
I
TOT2
16-bit reload timer ch.2 TOT output pin.
PE0
General-purpose I/O port.
TOT3
I
16-bit reload timer ch.3 TOT output pin.
IN7R
Input capture ch.7 trigger input pin.
PE1
General-purpose I/O port.
TIN3
I
16-bit reload timer ch.3 TIN input pin.
IN6R
Input capture ch.6 trigger input pin.
PE2
General-purpose I/O port.
SGO1
I
IN3R
Sound generator ch.1 SGO output pin.
Input capture ch.3 trigger input pin.
62
RSTO
N
Internal reset output pin.
65,75,85
DVCC
-
Dedicated power supply input pins for high current output buffer
66,76,86
DVSS
-
Dedicated GND power supply pins for high current output buffer
35
AVCC
-
Dedicated power supply input pin for A/D converter
38
AVSS
-
Dedicated GND power supply pin for A/D converter
36
AVRH
-
A/D converter Vref+ input pin. Vref- is fixed to AVSS.
89
MD0
D
Mode setting input pin. Connect to VCC.
88
MD1
D
Mode setting input pin. Connect to VCC.
87
MD2
D/E *4
Mode setting input pin. Connect to VSS.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.6 Pin Functions
MB90930 Series
Table 1.6-1 Pin Functions (9 / 9)
I/O Circuit
type *1
Description
C
-
External capacitor pin. Connect an 0.1 μF capacitor between this pin
and VSS.
15,105
VCC
-
Power supply input pins.
16,47,106
VSS
-
GND power supply pins.
Pin no.
17
Pin name
*1 : For the I/O circuit type, refer to "1.7 I/O Circuit Types".
*2 : X0A pin is optional (dual clock products only).
*3 : X1A pin is optional (dual clock products only).
*4 : The I/O circuit type is D for Flash memory products/Mask ROM products and E for evaluation products.
16
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB90930 Series
1.7
I/O Circuit Types
This section describes the types of the input/output circuits for each pin.
■ I/O Circuit Types
Table 1.7-1 shows the types of input/output circuits for each pin.
Table 1.7-1 I/O Circuit Types (1 / 4)
Type
A
Circuit
Remarks
High speed oscillator pin
(flash memory product/mask ROM
product)
X1
Xout
• Oscillation feedback resistance:
approx. 1MΩ
X0
Standby control
signal
X1
Xout
High speed oscillator pin
(evaluation product)
• Oscillation feedback resistance:
approx. 1MΩ
X0
Standby control
signal
B
Low speed oscillator pin
X1A
Xout
• Oscillation feedback resistance:
approx. 10MΩ
X0A
Standby control signal
C
Input-only pin
(pull-up resistor attached)
Pull-up resistor
• Pull-up resistor value:
approx. 50kΩ
CMOS hysteresis
input
CM44-10150-1E
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB90930 Series
Table 1.7-1 I/O Circuit Types (2 / 4)
Type
Circuit
Remarks
D
Input-only pin
CMOS hysteresis
input
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
Note: The MD2 pin of the Flash
memory products uses this
circuit type.
E
Input-only pin (pull-down resistor
attached)
CMOS hysteresis input
Pull-down resistor
• Pull-down resistor value: approx.
50kΩ
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
Note: For the mask ROM and
evaluation products only, the
MD2 pin uses this circuit.
F
LCD output/general-purpose port
P-ch
Pout
N-ch
Nout
• CMOS output (IOH / IOL = ±4 mA)
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
LCD output
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
CMOS hysteresis input
Standby control signal or L
enable signal
Automotive input
Standby control signal or L
enable signal
G
P-ch
LCDC reference power supply/
general-purpose port
Pout
CMOS hysteresis input
N-ch
Nout
LCDC reference power
supply input
• CMOS output
(IOH / IOL = ±4 mA)
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
CMOS hysteresis input
Standby control signal or
LCD output switching
signal
Automotive input
Standby control signal or
LCD output switching signal
18
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB90930 Series
Table 1.7-1 I/O Circuit Types (3 / 4)
Type
Circuit
Remarks
H
A/D converter input/general-purpose
port
P-ch
Pout
N-ch
Nout
• CMOS output (IOH / IOL = ±4 mA)
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
Analog input
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
• Analog input
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
I
General-purpose port
P-ch
Pout
N-ch
Nout
• CMOS output (IOH / IOL = ±4 mA)
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
CMOS hysteresis input
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
Standby control signal
Automotive input
Standby control signal
J
General-purpose port (Serial input)
P-ch
Pout
• CMOS output (IOH / IOL = ±4 mA)
N-ch
Nout
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
CMOS hysteresis input
Standby control signal
• CMOS input (SIN)
(VIH / VIL=0.7Vcc / 0.3Vcc)
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB90930 Series
Table 1.7-1 I/O Circuit Types (4 / 4)
Type
Circuit
L
Remarks
High current output port and high
current (SMC pin)
Pout
P-ch
High current
N-ch
• CMOS output
(IOH / IOL = ±30 mA)
Nout
• A/D converter input
Analog input
M
LCDC output/general-purpose port
(Serial input)
Pout
P-ch
• CMOS output
(IOH / IOL = ±4 mA)
Nout
N-ch
LCDC output
• CMOS hysteresis input
(VIH / VIL=0.8Vcc / 0.2Vcc)
CMOS hysteresis input
• CMOS input (SIN)
(VIH / VIL=0.7Vcc / 0.3Vcc)
Standby control signal or
LCDC output switching signal
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
Automotive input
Standby control signal or
LCDC output switching signal
CMOS input (SIN)
Standby control signal or
LCDC output switching signal
N
Flash memory product/
mask ROM product
Evaluation product
N-ch open drain pin
IOL=4mA
P-ch
N-ch
Nout
N-ch
O
Nout
Input-only pin
Automotive input
P
• Automotive input
(VIH / VIL=0.8Vcc / 0.5Vcc)
LCDC output pin (COM pin)
P-ch
LCDC output
N-ch
20
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.8 Precautions for Handling Device
MB90930 Series
1.8
Precautions for Handling Device
When handling the device, pay special attention to the following 11 points:
• Strict observance of the maximum voltage rating (for latch-up prevention)
• Stabilization of supplied voltage
• Voltage start up time at power-on
• Processing of unused pins
• Processing of A/D converter power supply pins
• Use of external clocks
• Processing of power supply pins
• Power-on sequence for A/D converter power supply/analog input
• Handling of power supply for high current output buffer pins (DVCC, DVSS)
• Pull-up/pull-down resistor
• Precautions for PLL clock mode operation
■ Strict Observance of the Maximum Voltage Rating (for Latch-up Prevention)
Do not apply a voltage higher than VCC or lower than VSS to input pins and output pins of
MB90930 series products. Moreover, do not apply a voltage exceeding the rating range
between VCC and VSS. When a voltage exceeding the rating is applied, a latch-up may occur.
During a latch-up, the power supply current increases rapidly, which can result in heat-induced
damage to elements. Ensure that the voltage applied does not exceed the maximum rating.
Be careful not to exceed the voltage rating of the digital power supply (VCC) when turning on
or turning off the analog power (AVCC, AVRH), the power supply to high current output
buffer pins (DVCC) and the power to the analog input.
There is no distinction regarding the power-on sequence of analog power (AVCC, AVRH) and
the power supply to high current output buffer pins (DVCC) once the digital power supply
(VCC) is supplied.
■ Stabilization of Supplied Voltage
Be sure to stabilize the VCC power supply voltage since a rapid change in voltage may lead to
incorrect operation. As a reference for the stabilization, note that the VCC ripple fluctuations
(p-p value) for commercial frequency (50 Hz to 60 Hz) must be within 10% of the VCC supply
voltage, and the transient fluctuation rate caused by the power switching must not exceed
0.1 V/ms.
■ Voltage Start Up Time at Power-on
To prevent incorrect operation of the built-in step-down circuit, the voltage start up time at
power-on must be 50μs or more (0.2V to 2.7V).
■ Processing of Unused Pins
Leaving an unused input pin open may result in incorrect operation because of external noise.
In these cases, pull-up or pull-down via a resistor of at least 2kΩ or more must be applied.
An I/O pin that is not in use must be either set to output status and "open", or set to input status
and handled as an input pin.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.8 Precautions for Handling Device
MB90930 Series
■ Processing of A/D Converter Power Supply Pins
If not used, the A/D converter must be connected so that AVCC= VCC and AVSS=AVRH=
VSS.
■ Use of External Clock
When an external clock is used, oscillation stabilization wait time shall be applied at recovery
from power-on reset, sub clock mode and stop mode.
If an external clock is used, as shown in Figure 1.8-1, drive only the X0A pin and leave the X1A
pin open.
The high-speed oscillation pins (X0, X1) cannot use the external clock input.
Figure 1.8-1 Example of Using External Clock
X0A
OPEN
X1A
■ Processing of Power Supply Pins
To prevent a latch-up, multiple VCC and VSS power pins are connected within the device.
However, VCC and VSS power pins must be connected externally to the same power supply to
decrease unnecessary radiation, prevent an incorrect operation of the strobe signal due to rising
ground level and maintain the total output current standard. (See Figure 1.8-1.)
Figure 1.8-2 Power Supply Pins (VCC/VSS)
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
Use low impedance from the current supply source to connect with the VCC and VSS power
pins of the device. Connect a bypass capacitor of approximately 0.1μF between VCC and VSS
of the device, near the VCC and VSS power pins.
22
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 1 OVERVIEW
1.8 Precautions for Handling Device
MB90930 Series
■ Power-on Sequence for A/D Converter Power Supply and Analog Input
Apply the voltage to the A/D converter power pins (AVCC, AVRH) and analog input pins
(AN0 to AN23) always after turning on the digital power supply (VCC). To turn off the device,
turn off the digital power (VCC) after turning off the A/D converter and analog input power. In
this case, AVRH shall not exceed AVCC. When using a pin which is also used as an analog
input as an input port, make sure that the input voltage does not exceed AVCC.
■ Handling of Power Supply for High-current Output Buffer Pins (DVCC, DVSS)
• Flash memory products / mask ROM product
(MB90F931/MB90F931S/MB90931/MB90931S)
As the high-current output buffer power supply (DVCC/DVSS) and the digital power supply
(VCC) are isolated from each other, DVCC can be set to a potential higher than VCC.
Note that, if the power supply for high-current output buffer pin (DVCC/DVCC) is turned on
prior to the digital power supply (VCC), however, port 7 or 8 for stepping motor output may
momentarily output an "H" or "L" level signal at the rise of DVCC.
To prevent this, turn on the digital power supply (VCC) prior to the power supply for highcurrent output buffer pin.
Apply a voltage to the power supply for high-current output buffer pin (DVCC/DVSS) even
when the high-current output buffer pin is used as a general-purpose port.
• Evaluation product (MB90V930-102, MB90V930-101)
As it does not have the power supply for high-current output buffer (DVCC/DVSS) and
digital power supply (VCC) isolated from each other, set DVCC to a potential equal to or
lower than VCC.
Before turning on the power supply for high-current output buffer pin (DVCC/DVSS), be
sure to turn on the digital power supply (VCC). Also, turn off the digital power supply
(VCC) after turning off the power supply for high-current output buffer pin. (It is acceptable
to turn on or off the power supply for high-current output buffer pin and the digital power
supply at the same time.)
Apply a voltage to the power supply for high-current output buffer pin (DVCC/DVSS) even
when the high-current output buffer pin is used as a general-purpose port.
■ Pull-up/Pull-down Resistor
The MB90930 series supports neither internal pull-up nor pull-down resistors. Use external
components if necessary.
■ Precautions when Sub Clock Mode is not Used
If no oscillator is connected to the X0A and X1A pins, apply pull-down processing to the X0A
pin and leave the X1A pin open.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.8 Precautions for Handling Device
MB90930 Series
■ Precautions for PLL Clock Mode Operation
If the PLL clock mode is selected on MB90930 series, it may attempt to be working with the
free-run frequency of self-oscillating circuit in the PLL when the resonator is disconnected or
clock input is stopped. Performance of this operation, however, cannot be guaranteed.
■ Initialization
The device contains internal registers that are initialized only by power-on reset. If such
initialization is expected, turn on the power again.
■ Flash Security Function
The security bit is located in the flash memory area. When the protection code 01H is written to
the security bit, the security function becomes active. Therefore, if not using the security
function, do not write 01H at this address.
For the address of the security bit, see the following table.
MB90F931/MB90F931S
24
Flash memory size
Security bit address
Built-in 1Mbit flash memory
FE0001H
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 2
CPU
This chapter describes F2MC-16LX CPU.
2.1 Outline of CPU
2.2 Memory Space
2.3 Memory Map
2.4 Addressing
2.5 Allocation of Multiple-Byte Data in the Memory
2.6 Registers
2.7 Dedicated Registers
2.8 General-purpose Register
2.9 Prefix Codes
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
25
CHAPTER 2 CPU
2.1 Outline of CPU
2.1
MB90930 Series
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications in which
high speed real-time processing is required, such as for various consumer
devices and in vehicles. The F2MC-16LX instruction set is designed for
application in device controllers and is supporting a variety of control
operations with high-speed and high efficiency processing.
■ CPU Features
The F2MC-16LX CPU core supports not only 16-bit data but has also a 32-bit accumulator for
32-bit operations. The memory space can be a maximum of 16 MB, and can be accessed either
with a linear or bank scheme. The instruction system is based on the F2MC-8L A-T
architecture but was further improved with the addition of high-level language compatible
instructions, extensions of the addressing mode, as well as by extended instruction for
multiplication, division and bit operations. The F2MC-16LX CPU has the features listed below.
● Minimum instruction execution time
31.25ns (4MHz oscillation, multiply-by-8)
● Maximum memory space
16 MB, access by linear/bank schemes
● Instruction system optimized for application in controllers
• Various data types:
bit/byte/word/long word
• Extended addressing mode: 23 types
• Using 32-bit accumulator for more powerful high-precision operations (support of 32-bit
data), signed multiplication/division and extended RETI instruction
● Powerful interrupt functions
Eight priority levels (programmable)
● CPU-independent automatic transfer function
Extended intelligent I/O service up to 16 channels
● Support for high-level languages (C language)/Instruction system supporting multi-task
processing
Using system stack pointer/symmetric instruction sets/barrel shift instruction
● Increased execution speed
4-byte queuing
26
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 2 CPU
2.1 Outline of CPU
MB90930 Series
Note:
MB90930 series uses only single-chip mode, accessing only memory space of built-in
ROM, built-in RAM and built-in circuits for peripherals.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 2 CPU
2.2 Memory Space
2.2
MB90930 Series
Memory Space
F2MC-16LX CPU has a memory space of 16 MB. The F2MC-16LX CPU controls
general-purpose data, program data and I/O data, all of which are allocated
within the 16 MB memory space. A part of the memory space is used for
special applications, such as for extended intelligent I/O service (EI2OS)
descriptors, general-purpose registers and vector tables.
■ Memory Space
General-purpose data, programs, and I/O data is allocated anywhere within the 16 MB memory
space of the F2MC-16LX CPU. The CPU indicates such addresses using a 24-bit address bus to
access each peripheral function.
Figure 2.2-1 shows the relationship between the F2MC-16LX system and the memory map.
Figure 2.2-1 Example of Relationship Between F2MC-16LX system and Memory Map
F2MC-16LX system
FFFFFFH
Vector table area
Programs
FFFC00H
F2MC-16LX
CPU
Internal Data Bus
FF0000H *1
ROM area
Program area
100000H
External area*4
010000H
*2
Data
EI 2OS
Interrupt
Peripheral
circuit
Generalpurpose port
004000H
002000H
000D00H*3
000380H
000180H
000100H
0000C0H
0000B0H
000020H
000000H
ROM area
(FF bank image)
External area*4
Data area
General-purpose register
RAM area
EI 2OS
Descriptor area
External area*4
Interrupt control
register area
Peripheral function control
register area
I/O area
I/O port control register area
*1: Internal ROM capacity differs depending on the product type.
*2: Image access area differs depending on the product type.
*3: Internal RAM capacity differs depending on the product type.
*4: No access occurs in the single chip mode.
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CHAPTER 2 CPU
2.2 Memory Space
MB90930 Series
■ ROM Area
● Vector table area (Address: FFFC00H to FFFFFFH)
• Used as vector tables for vector call instructions, interrupt vectors and reset vectors.
• Assigned to the highest portion of ROM area
for setting the start address of the corresponding routine to address data in the applicable
vector table.
● Program area (Address: Up to FFFBFFH)
• ROM is built in as an internal program area.
• The internal ROM capacity differs depending on the product type.
■ RAM Area
● Data area (Address: from 000100H)
• Static RAM is built-in as an internal data area.
• The internal RAM capacity differs depending on the product type.
● General-purpose register area (address: 000180H to 00037FH)
• Supplemental registers are provided for 8-bit, 16-bit and 32-bit operations and transfer.
• Since this area is allocated to a part of the RAM area, it can also be used as ordinary RAM.
• When used as a general-purpose register, it allows a high-speed access with short
instructions by general-purpose register addressing.
● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
• Stores transfer mode, I/O address, transfer count and buffer address.
• Since this area is allocated to a part of the RAM area, it can also be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFH)
Interrupt control register (ICR00 to ICR15) supports all peripheral functions that have interrupt
functions,
providing interrupt level settings and extended intelligent I/O service (EI2OS) control.
● Peripheral function control register area (address: 0000C0H to 0000EFH)
Provides control of built-in peripheral functions and data input/output.
● I/O port control register area (Address: 000000H to 00001FH)
Provides I/O port control and data input/output.
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CHAPTER 2 CPU
2.3 Memory Map
2.3
MB90930 Series
Memory Map
This section describes the memory map for the different types of MB90930
series products.
■ Memory Map
Figure 2.3-1 shows the memory map of MB90930 series.
Figure 2.3-1 Memory Map
MB90V930-102/
MB90V930-101
000000H
MB90F931/MB90F931S
MB90931/MB90931S
000000H
Peripheral area
0000F0H
000100H
Register
RAM area
(13.5 Kbytes)
003700H
004000H
Peripheral area
0000F0H
Peripheral area
000100H
002100H
003700H
004000H
Register
RAM area
(8 Kbytes)
Peripheral area
RAM area
(16 Kbytes)
008000H
008000H
ROM area
(FF bank image)
ROM area
(FF bank image)
010000H
010000H
F80000H
ROM decoding area
FFFFFFH
FE0000H
FFFFFFH
Flash / ROM area
(128 Kbytes)
: Internal access prohibited
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CHAPTER 2 CPU
2.3 Memory Map
MB90930 Series
Notes:
• If "no RO M mir ror f unction" is sele cted, see "C HAPTER 23 ROM MIRROR
FUNCTION SELECT MODULE".
• The upp er 00 ban k allows re ferencing RO M d ata in th e FF ban k as an imag e f or
effectively using the C c ompiler's small mo del. Be cause t he FF bank's lower 16-bit
address is set t o t he same va lue, t he t able in ROM can be referenced wit hout
specifying "f ar" wit h a poin ter. Fo r e xample, wh en acce ssing "00 C000H", t he RO M
content a t "FF C000H" is act ually a ccessed. Sin ce t he ROM ar ea in t he F F ba nk
exceeds 32 K bytes, the wh ole area ca n not be referenced via th e 00 b ank imag e.
Therefore, t he ROM data in "FF 8000H" to "FF FFFFH" is r eferenced a s an image in
"008000H" to "00FFFFH", and the ROM data table is then stored in the area "FF8000H"
to "FFFFFFH".
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CHAPTER 2 CPU
2.4 Addressing
2.4
MB90930 Series
Addressing
Both linear and bank address generation schemes are available.
The linear scheme is used to directly specify all 24-bit addresses within the
instruction.
The bank scheme is used to specify upper 8-bit addresses via the bank register
depending on how the data will be used and to specify the lower 16-bit
addresses with instructions.
The F2MC-16LX series basically uses bank addressing.
■ Linear Addressing and Bank Addressing
Linear scheme addressing is used to access the 16 MB space as a continuous address space.
The bank scheme is used to divide and control the 16 MB space by dividing it into 256 banks
of 64 K bytes each.
An outline of memory control with linear and bank schemes is shown in Figure 2.4-1.
Figure 2.4-1 Memory Control with Linear and Bank Schemes
Linear scheme
FFFFFFH
123456H
123456H
000000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H
123456H
All specified by instruction
32
Bank scheme
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FF bank
64KB
FE bank
FD bank
12 bank
04 bank
03 bank
02 bank
01 bank
00 bank
123456H
Specified by instruction
Specified by bank register
according to the use
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
MB90930 Series
2.4.1
Addressing with Linear Scheme
CHAPTER 2 CPU
2.4 Addressing
There are two types of linear addressing: Directly addressing 24-bit addresses
with an operand, and using the lower 24 bits of 32-bit general-purpose
registers as address.
■ Specification with 24-bit Operand
Figure 2.4-2 Example of Linear Addressing (Specification with 24-bit Operand)
JMPP 123456H
Old program counter
+ program bank
17
452D
17452DH
New program counter
+ program bank
12
3456
123456 H
JMPP 123456H
Next instruction
■ Indirect Specification with 32-bit Register
Figure 2.4-3 Example of Linear Addressing (Indirect Specification with 32-bit Register)
MOV A,@RL1+7
Old AL
XXXX
090700H
3AH
+7
New AL
003A
RL1
240906F9H
(Upper 8 bits are ignored)
RL1: 32-bit (long word) general-purpose register
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CHAPTER 2 CPU
2.4 Addressing
2.4.2
MB90930 Series
Addressing with Bank Scheme
When applying the bank scheme, the 16 MB memory space is divided into 256
banks of 64 K bytes each, and the bank address corresponding to each space
is specified via a bank register. The upper 8 bits of the address are specified
with the bank address and the lower 16 bits are specified with an instruction.
Five bank register types are available depending on use, as listed below.
• Program Counter Bank Register (PCB)
• Data Bank Register (DTB)
• User Stack Bank Register (USB)
• System Stack Bank Register (SSB)
• Additional Data Bank Register (ADB)
■ Bank Register and Access Space
Table 2.4-1 shows the access space and major use of each bank register.
Table 2.4-1 Access Space and Major Application for Each Bank Register
Bank register name
Access space
Program counter bank register
(PCB)
Stores instruction code, vector table and
immediate data.
FFH
Data (DT) space
Stores readable/writable data and accesses
the control register/data register for builtin/external peripheral components.
00H
Stack (SP) space
Area used for PUSH/POP instructions and
stack accesses for storing interrupt
registers. Use SSB if the stack flag
(S in CCR) within the condition register is
set to "1", or USB if set to "0".
Additional (AD) space
Stores data that cannot be fully entered in
the data (DT) space.
Program (PC) space
Data bank register (DTB)
User stack bank register (USB)
System stack bank register (SSB) *
Additional data bank register (ADB)
Initial value
at reset
Main use
00H
00H
00H
*: SSB is used always for stacks if an interrupt occurs.
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2.4 Addressing
MB90930 Series
Figure 2.4-4 shows the relationship between the memory space divided into banks and each
register. Refer to Section "2.7.6 Bank Registers (PCB, DTB, USB, SSB, ADB)" for details.
Figure 2.4-4 Physical Address of Each Bank Register
FFFFFFH
FF0000H
0FFFFFH
Physical address
0F0000H
0DFFFFH
0D0000H
0BFFFFH
0B0000H
07FFFFH
070000H
Program
space
Additional
space
User stack
space
FFH : PCB (Program counter bank register)
0FH : ADB (Additional data bank register)
0DH : USB (User stack bank register)
Data space
0BH : DTB (Data bank register)
System stack
space
07H : SSB (System stack bank register)
000000H
■ Bank Addressing and Default Space
In order to improve the efficiency of instruction code processing, a default address space is
defined for each addressing scheme, as shown in Table 2.4-2. To use a space other than the
default space, specify the prefix code corresponding to the bank at the beginning of the
instruction; this enables accessing an arbitrary bank space corresponding to the prefix code. For
the details of the prefix code, see Section "2.9 Prefix Codes".
Table 2.4-2 Addressing and Default Space
Default space
Addressing
Program space
PC indirect, program access, branch system
Data space
Addressing using @RW0, @RW1, @RW4 and @RW5, @A, addr16, dir
Stack space
Addressing using PUSHW, POPW, @RW3 and @RW7
Additional space
Addressing using @RW2 and @RW6
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CHAPTER 2 CPU
2.5 Allocation of Multiple-Byte Data in the Memory
2.5
MB90930 Series
Allocation of Multiple-Byte Data in the Memory
Multiple-byte data is written to memory, starting from the lower address in
sequence. For 32-bit data, first the lower 16 bits are transferred, then the upper
16 bits.If a reset signal is input immediately after writing the lower part of the
data, the upper part of the data sometimes cannot be written.
■ Allocating Multi-byte Data in RAM
Figure 2.5-1 shows the placement of multiple-byte data in memory. The lower 8 bits of a data
item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.5-1 Allocating Multi-byte Data in RAM
MSB
H
LSB
01010101B 11001100B 11111111B 00010100B
01010101B
11001100B
11111111B
Address
n
00010100B
L
MSB: Most Significant Bit
LSB: Least Significant Bit
■ Allocating Multi-byte Operand
Figure 2.5-2 shows the placement of a multiple-byte operand in memory.
Figure 2.5-2 Allocating Multi-byte Operand
JMPP 123456H
H
JMPP 1 2 3 4 5 6H
12 H
34 H
56 H
Address
n
63 H
L
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CM44-10150-1E
CHAPTER 2 CPU
2.5 Allocation of Multiple-Byte Data in the Memory
MB90930 Series
■ Allocating Multi-byte Data on the Stack
Figure 2.5-3 shows the allocation of multiple-byte data on the stack.
Figure 2.5-3 Allocating Multi-byte Data on the Stack
PUSHW RW1,RW3
H
PUSHW RW1
RW3
(35A4 H) (6DF0H)
SP
6DH
F0H
35H
A4H
Address
n
L
RW1: 35A4H
RW3: 6DF0H
■ Accessing Multiple-Byte Data
Basically, all accesses are executed within the current bank, and the next multi-byte access
instruction after the address "FFFFH" has been accessed will access the address "0000H" in the
same bank. Figure 2.5-4 shows an example for the execution of an multiple-byte data access
instruction.
Figure 2.5-4 Example for Execution of Multiple-byte Data Access Instruction
H
AL before execution
80FFFFH
•
•
•
800000 H
??
??
01H
23H
MOVW A, 080FFFFH
AL after execution
23H
01H
L
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CHAPTER 2 CPU
2.6 Registers
2.6
MB90930 Series
Registers
The F2MC-16LX registers mostly has two types: CPU-internal dedicated
registers, and general-purpose registers in the built-in RAM.
■ Dedicated Registers and General-purpose Registers
Dedicated registers consist of dedicated hardware in the CPU and their use is limited by the
CPU architecture. General-purpose registers are allocated in the RAM within the same CPU
address space. In addition to accessing without address specification, in the same way as a
dedicated register, the use of these registers may be specified by the user in the same way as
for normal memory. Figure 2.6-1 shows the allocation of the dedicated registers and the
general-purpose registers in the device.
Figure 2.6-1 Dedicated Registers and General-purpose Registers
CPU
Dedicated registers
RAM
RAM
General purpose
register
Accumulator
User stack pointer
System stack pointer
Program counter
Direct page register
Program counter bank register
Internal bus
Processor status
Data bank register
User stack bank register
System stack bank register
Additional data bank register
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MB90930 Series
2.7
Dedicated Registers
CHAPTER 2 CPU
2.7 Dedicated Registers
The CPU contains the following 11 types of dedicated registers:
• Accumulator (A)
• User stack pointer (USP)
• System stack pointer (SSP)
• Processor status (PS)
• Program counter (PC)
• Direct page register (DPR)
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Configuration of Dedicated Register
Figure 2.7-1 shows the configuration of the dedicated registers, and Table 2.7-1 shows the
initial values of the dedicated registers.
Figure 2.7-1 Configuration of Dedicated Registers
AH
AL
: Accumulator (A)
Two 16-bit registers used for storing operation results.
Continuously accessible as a single 32-bit register.
USP
: User stack pointer (USP)
16-bit pointer indicating a user stack address.
SSP
: System stack pointer (SSP)
16-bit pointer indicating a system stack address.
PS
: Processor status (PS)
16-bit register indicating the system status.
PC
: Program counter (PC)
16-bit register indicating the storage location of the
current instruction.
: Direct page register (DPR)
8-bit register specifying bits 8 to 15 of an operand address
when abbreviated direct addressing is used.
DPR
PCB
: Program counter bank register (PCB)
8-bit register indicating the program space.
DTB
: Data bank register (DTB)
8-bit register indicating the data space.
USB
: User stack bank register (USB)
8-bit register indicating the user stack space.
SSB
: System stack bank register (SSB)
8-bit register indicating the system stack space.
ADB
8 bits
: Additional data bank register (ADB)
8-bit register indicating the additional space.
16 bits
32 bits
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
Table 2.7-1 Initial Values of Dedicated Registers
Dedicated register
Initial value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
bit15 to bit13 bit12
Processor status (PS)
PS
ILM
0
0
0
0
to
bit8 bit7
RP
0 0 0 0 - 0
to
bit0
CCR
1
x
x
x
x
x
- : Undefined
X: Undefined value
Program counter (PC)
Direct page register (DPR)
Program counter bank register
(PCB)
Value stored in the reset vector (contents of address "FFFFDCH" and "FFFFDDH")
01H
Value stored in the reset vector (contents of address "FFFFDEH")
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank
register (ADB)
00H
Note:
The initial values above are used for controlling devices. Different values are to be used
for ICEs (such as an emulator.)
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
2.7.1
Accumulator (A)
The accumulator (A) consists of two 16-bit registers (AH and AL) to temporarily
store operation results or other data items.
The A register is used as a 32-/16-/8-bit register, for the purpose of executing a
variety of operations between memory and other registers, or between AH and
AL registers. If the data in the word length or less is transferred to the AL
register, data in the AL register before transfer is automatically transferred to
the AH register by the data save function (some instructions do not save data).
■ Accumulator (A)
● Data transfer to the accumulator
The accumulator is used to handle 32-bit (long word), 16-bit (word) and 8-bit (byte) data. There are
exceptions in which it is also used for 4-bit data transfer instructions (MOVN). The explanation of
8-bit data handling also applies to these cases.
• AH and AL registers are coupled for handling 32-bit data.
• Only the AL register is used for 16-bit or 8-bit data.
• If data of less than byte length is transferred to the AL register, it is stored in the AL register
as 16-bit data by code extension or zero extension. Data in the AL register may also be
handled as either word or byte data.
Data transfer to the accumulator is shown in Figure 2.7-2. An example of the actual transfer
operation is shown in Figure 2.7-3 to Figure 2.7-6.
Figure 2.7-2 Data Transfer to Accumulator
32 bits
AH
AL
32-bit data transfer
Data transfer Data transfer
AH
16-bit data transfer
AL
Data migration
Data transfer
AH
8-bit data transfer
AL
Data migration
Data transfer
00H or FFH*
(Zero extension or code extension)
*: 000H or FFFH for 4-bit transfer instruction.
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
● Byte-based arithmetic operations of the accumulator
When executing a byte-based arithmetic operation instruction for the AL register, the upper 8
bits of the AL register before the operation are ignored, and the upper 8 bits of the operation
result are all set to "0".
● Initial value of accumulator
The initial value after a reset is undefined.
Figure 2.7-3 Example of Accumulator (A) Transfers Between AL and AH (8-bit Immediate Data, Zero
Extension)
(Instruction to perform zero extension on the contents of address
3000H and store them in the AL register)
MOV A,3000H
MSB
Before
execution
AH
AL
XXXXH
2456H
B53000H
2456H
77H
LSB
88H
B5H
DTB
After
execution
Memory space
X:
Undefined
MSB : Most Significant Bit
LSB : Least Significant Bit
DTB : Data bank register
0088H
Figure 2.7-4 Example of Accumulator (A) Transfers Between AL and AH (8-bit Immediate Data, Code
Extension)
MOVW A,3000H
(Instruction to store the contents of address 3000H in the AL register)
MSB
Before
execution
AH
AL
XXXXH
2456H
2456H
77H
B53000H
LSB
88H
B5H
DTB
After
execution
Memory space
X:
Undefined
MSB : Most Significant Bit
LSB : Least Significant Bit
DTB : Data bank register
7788H
Figure 2.7-5 Example of 32-bit Data Transfer to Accumulator (A) (Register Indirect)
(Instruction to read long-word data from the address calculated as
RW1 content + 8-bit offset, then writing the result to the A register)
MOVL A,@RW1+6
Before
execution
AH
XXXXH
DTB
After
execution
8F74H
MSB
AL
XXXXH
2B52H
A61540H
A6H
A6153EH
Memory space
8FH
2BH
74H
52H
15H
38H
LSB
+6
RW1
X:
Undefined
MSB : Most Significant Bit
LSB : Least Significant Bit
DTB : Data bank register
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
Figure 2.7-6 Example of Accumulator (A) Transfers Between AL and AH (16-bit, Register
Indirect)
MOVW A,@RW1+6
Before
execution
AH
XXXXH
(Instruction to read long-word data from the address calculated as
RW1 content + 8-bit offset, then writing the result to the A register)
1234H
DTB
After
execution
1234H
MSB
AL
2B52H
A61540H
A6H
A6153EH
Memory space
8FH
2BH
74H
52H
15H
38H
LSB
+6
RW1
X:
Undefined
MSB : Most Significant Bit
LSB : Least Significant Bit
DTB : Data bank register
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CHAPTER 2 CPU
2.7 Dedicated Registers
2.7.2
MB90930 Series
Stack Pointers (USP, SSP)
There are two types of stack pointers: a user stack pointer (USP) and a system
stack pointer (SSP). These are registers used to indicate the destination
address in memory for data relocation or recovery when executing the PUSH
instruction, POP instruction, or subroutines. The upper 8 bits of the stack
address are specified by either the user stack bank register (USB) or the
system stack bank register (SSB).
If the S flag in the condition code register (CCR) is set to "0", the USP and USB
registers become enabled. If the S flag is set to "1", SSP and SSB registers are
enabled.
■ Stack Selection
The F2MC-16LX uses two types of stacks: system stacks and user stacks. The stack address is
specified with an S flag in the processor status register (PS: CCR), as shown in Table 2.7-2.
Table 2.7-2 Specifying Stack Address
Stack address
S flag
0
1
Upper 8 bits
Lower 16 bits
User stack bank register (USB)
User stack pointer (USP)
System stack bank register (SSB)
System stack pointer (SSP)
: Initial value
Resetting initializes the S flag to "1", after which the system stack is used by default. Normally,
stack operations in an interrupt routine use the system stack, and in stack operations other than
operation by an interrupt routine, the user stack is used. Especially in cases when stack space
does not need to be divided, use the system stack only.
Note:
Once an interrupt is a ccepted, the S f lag is set to "1 ". Thus, the system stack is always
used in case of an interrupt.
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
Figure 2.7-7 shows an example of stack operations when the system stack is used.
Figure 2.7-7 Stack Operation Instructions and Stack Pointers
PUSHW A if the S flag is set to "0"
Before
execution
AL
A624H
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
A624H
USB C6H
USP F326H
SSB 56H
SSP 1234H
S flag
After
execution
AL
MSB
S flag
0
C6F326H
AL
USP F328H
1
SSB 56H
SSP 1234H
A624H
USB C6H
USP F328H
SSB 56H
SSP 1232H
S flag
After
execution
AL
S flag
1
X:
Undefined
MSB : Most Significant Bit
LSB : Least Significant Bit
XXH
C6F326H
A6H
24H
MSB
USB C6H
A624H
XXH
User stack is used because
the S flag is set to "0"
PUSHW A if the S flag is set to "1"
Before
execution
LSB
LSB
561232H
XXH
XXH
561232H
A6H
24H
System stack is used because
the S flag is set to "1"
Note:
In o rdinary cases, set t he st ack po inter t o a n e ven-numbered ad dress. I f it is set to an
odd-numbered address, wor d accesses a re p erformed in two st eps, whi ch d egrades
processing efficiency.
The initial value after resetting the USP register and SSP register is undefined.
■ System Stack Pointer (SSP)
Using the system stack pointer (SSP) requires setting the S flag in the condition code register
(CCR) within the processor status register (PS) to "1". In this case, the upper 8 bits of the
address used in the stack operation are indicated in the system stack bank register (SSB).
■ User Stack Pointer (USP)
Using the user stack pointer (USP) requires setting the S flag in the condition code register
(CCR) within the processor status register (PS) to "0". In this case, the upper 8 bits of the
address used in the stack operation are indicated in the user stack bank register (USB).
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CHAPTER 2 CPU
2.7 Dedicated Registers
2.7.3
MB90930 Series
Processor Status (PS)
The processor status register (PS) consists of CPU control bits and a variety of
bits indicating the CPU state.
■ Bit Configuration of Processor Status (PS)
The PS register consists of three registers listed below.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
Figure 2.7-8 shows the bit configuration of the processor status register (PS).
Figure 2.7-8 Bit Configuration of Processor Status (PS)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS ILM2 ILM1 ILM0 B4
B3
B2
B1
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
B0
-
I
0
S
1
T
N
Z
V
C
X
X
X
X
X
- : Undefined
X : Undefined value
● Interrupt level mask register (ILM)
Indicates the interrupt level which is currently accepted by the CPU. It is compared with the
interrupt level setting bit (ICR: IL0 to IL2) in the interrupt control register, which is set
corresponding to an interrupt request provided by each peripheral function.
● Register bank pointer (RP)
This pointer is used to specify the start address of the memory block (register bank) that is used
as a general-purpose register in the RAM area.
The general-purpose register consists of 32 banks in total, and a bank can be specified by
setting RP to a value of 0 to 31.
● Condition code register (CCR)
This register consists of a variety of flags, which are set "1" or reset "0" by the execution result
of instructions and interrupt generation.
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CM44-10150-1E
CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
■ Condition Code Register (PS:CCR)
This register consists of 8 bits including bits to represent operation result and the contents of
data transfers as well as the bits to control the acceptance of interrupt requests.
Figure 2.7-9 shows the bit configuration of the CCR register. For the status of the condition
code register (CCR) after an instruction is executed, see the "Programming Manual".
Figure 2.7-9 Bit Configuration of Condition Code Register (CCR)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS ILM2 ILM1 ILM0 B4
B3
B2
B1
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CCR Initial
value
B0
-
I
S
T
N
Z
V
C
-01XXXXXB
-
0
1
X
X
X
X
X
Interrupt enable flag
Stack flag
Sticky bit flag
Negative flag
Zero flag
Overflow flag
- : Undefined
X : Undefined value Carry flag
● Interrupt enable flag (I)
For interrupt requests other than software interrupts, the following applies: if the I flag is set to
"1", the interrupt is permitted, and if the flag is set to "0", the interrupt is prohibited. This flag
is cleared by reset.
● Stack flag (S)
This flag indicates that a pointer is used for a stack operation. If the S flag is set to "0", the user
stack pointer (USP) is enabled, and if it is set to "1", the system stack pointer (SSP) is enabled.
This flag is set when an interrupt is accepted or reset is performed.
● Sticky bit flag (T)
Executing a logical right shift instruction or arithmetic right shift instruction sets this flag to
"1" if at least one "1" was shifted out over the carry bit.; otherwise, this flag is set to "0". This
flag is also set to "0" if the shifting distance is "0".
● Negative flag (N)
Set to "1" if the highest bit of an operation result is "1". Otherwise, cleared to "0".
● Zero flag (Z)
Set to "1" if all bits of an operation result are zeroes. Otherwise, cleared to "0".
● Overflow flag (V)
Set to "1" if a signed-value overflow occurs when an operation is executed. Otherwise, cleared
to "0".
CM44-10150-1E
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CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
● Carry flag (C)
Set to "1" if, when an operation is executed, either carry-up from the highest bit or carry-down
to the highest bit occurs. Otherwise, cleared to "0".
■ Register Bank Pointer (PS:RP)
Used to indicate the start address in the general-purpose register bank currently used. This
pointer is used to convert the actual address at the general-purpose register addressing.
Figure 2.7-10 shows the bit configuration of the register bank pointer (RP).
Figure 2.7-10 Bit Configuration of Register Bank Pointer (RP)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS ILM2 ILM1 ILM0 B4
B3
B2
B1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RP Initial
value
-
I
S
T
N
Z
V
C
00000B
-
0
1
X
X
X
X
X
bit8
bit7
B0
- : Undefined
X : Undefined value
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer is to indicate the relationship between the general-purpose registers
in the F2MC-16LX and the internal RAM addresses. For the relationship between the RP
content and the actual address it indicates, see the conversion rule in Figure 2.7-11.
Figure 2.7-11 Physical Address Conversion Rule for General-purpose Register Area
Conversion formula [000180H + (RP) x 10H]
When RP=10H
000370H
Register bank 31
:
:
000280H
Register bank 16
:
:
000180H
Register bank 0
• RP can have a value from "00H" to "1FH". Thus, the start address of register banks can be
set to a value in the range "000180H" to "00037FH".
• There are assembler instructions for immediate data transfer of 8 bit data to RP, but only the
lower 5 bits are used in actual operation.
• The initial value of the RP register after a reset is "00H".
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CM44-10150-1E
CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
■ Interrupt Level Mask Register (PS:ILM)
The interrupt level mask register (ILM) is a 3-bit register used to indicate the interrupt level the
CPU can accept.
Figure 2.7-12 shows the bit configuration of the interrupt level mask register (ILM). For the
details of the interrupt, see "CHAPTER 3 INTERRUPTS".
Figure 2.7-12 Bit Configuration of Interrupt Level Mask Register (ILM)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS ILM2 ILM1 ILM0 B4
B3
B2
B1
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ILM Initial
value
B0
-
I
S
T
N
Z
V
C
000B
-
0
1
X
X
X
X
X
- : Undefined
X : Undefined value
The interrupt level mask register (ILM) indicates the interrupt level currently accepted by the
CPU, which is compared with the values of the bits IL0 to IL2 in the interrupt control register
(ICR00 to ICR15) that are set in accordance with the interrupt request of each peripheral
function. The CPU will perform interrupt processing, only if the interrupt enable flag indicates
that interrupts are enabled (CCR: I=1) and the interrupt request has a value lower than
indicated in these bits (the interrupt level).
• If the interrupt is accepted, the interrupt level value is set in the interrupt level mask register
(ILM), and any subsequent interrupt that has the same or a lower level is not accepted.
• The interrupt level mask register (ILM) is initialized to "0" by a reset. After that, the
interrupt level will be set to the highest level, indicating interrupt prohibit state.
• There are assembler instructions for immediate transfer of 8-bit data to the interrupt level
mask register (ILM), but only the lower 3 bits will be used during the operation.
Table 2.7-3 Interrupt Level Mask Register (ILM) and Interrupt Level Priority
CM44-10150-1E
ILM2
ILM1
ILM0
Interrupt level
Interrupt level priority
0
0
0
0
High (interrupt prohibited)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
FUJITSU MICROELECTRONICS LIMITED
Low
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CHAPTER 2 CPU
2.7 Dedicated Registers
2.7.4
MB90930 Series
Program Counter (PC)
The program counter (PC) is a 16-bit counter that indicates the lower 16-bits of
the address in memory at which the instruction code that the CPU will execute
next is stored.
■ Program Counter (PC)
The address at which the instruction code that will be executed next by the CPU is stored
consists of the upper 8 bits, specified by the program bank register (PCB), and the lower 16
bits specified by the program counter (PC). The actual address is created by combining these
two parts to 24 bits, as shown in Figure 2.7-13. The content of the PC is updated by a condition
branch instruction, subroutine call instruction, interrupts or resets. The PC is also used as the
base pointer for reading an operand.
Figure 2.7-13 Program Counter (PC)
Upper 8 bits
PCB FEH
Lower 16 bits
PC ABCDH
FEABCDH
Next instruction to
be executed
Note:
Neither PC no r PCB can b e d irectly re written b y a pr ogram (e .g. b y a MO V PC, #F F
instruction).
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CM44-10150-1E
CHAPTER 2 CPU
2.7 Dedicated Registers
MB90930 Series
2.7.5
Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register used to specify bits 8 to 15
(addr8 to addr15) at the operand address when an instruction applying the
abbreviated direct addressing scheme is executed.
■ Direct Page Register (DPR)
The DPR is used to specify bits 8 to 15 (addr8 to addr15) in the operand address when an
instruction of the abbreviated direct addressing scheme is executed as shown in Figure 2.7-14.
The DPR has a length of eight bits, and is initialized to "01H" at a reset. Instructions can be
used to read and write the register.
Figure 2.7-14 Generating Physical Address from Direct Page Register (DPR)
DTB register
AAAAAAAA
DPR register
BBBBBBBB
24-bit
MSB
physical address A A A A A A A A
bit24
bit16
Direct address in instruction
CCCCCCCC
LSB
BBBBBBBB
bit15
CCCCCCCC
bit8
bit7
bit0
MSB : Most Significant Bit
LSB : Least Significant Bit
An example of setting and accessing the direct page register (DPR) is shown in Figure 2.7-15.
Figure 2.7-15 Example of Setting and Accessing Direct Page Register (DPR)
MOV S:56H, #5AH
Execution result of instruction
Upper 8 bits Lower 8 bits
DTB register
12H
123458H
5AH
123456H
DPR register
34H
MSB : Most Significant Bit
LSB : Least Significant Bit
CM44-10150-1E
123454H
MSB
FUJITSU MICROELECTRONICS LIMITED
LSB
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CHAPTER 2 CPU
2.7 Dedicated Registers
2.7.6
MB90930 Series
Bank Registers (PCB, DTB, USB, SSB, ADB)
The bank registers are used to specify the upper 8-bit address for bank scheme
addressing. They consist of the 5 registers listed below.
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
Each bank register indicates a memory bank in which program space, data
space, user stack space, system stack space, or additional space are allocated.
■ Bank Registers (PCB, DTB, USB, SSB, ADB)
● Program counter bank register (PCB)
The PCB is a bank register to specify a program (PC) space. The PCB is rewritten if a JMPP,
CALLP, RETP, or RETI instruction which branches over the entire 16 MB space are executed, a
software interrupt instruction is executed, a hardware interrupt occurs or an exception is
generated.
● Data bank register (DTB)
The DTB is a bank register used to specify a data (DT) space.
● User stack bank register (USB)/system stack bank register (SSB)
USB and SSB are bank registers used to specify stack (SP) space. Whether USB or SSB is used
depends on the value of the S flag in the processor status register (PS: CCR). Refer to Section
"2.7.2 Stack Pointers (USP, SSP)" for details.
● Additional data bank register (ADB)
The ADB is a bank register used to specify an additional (AD) space.
● Setting each bank and data accessing
All of the bank registers have a length of bytes. PCB is initialized to "FFH" by resetting, while
others are initialized to "00H". The PCB can be read but not written. Reading and writing is
allowed for all bank registers other than the PCB.
Note:
The MB90930 series supports only the device built-in memory space.
For information about the operations of each register, see Section "2.4.2 Addressing with
Bank Scheme".
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CM44-10150-1E
CHAPTER 2 CPU
2.8 General-purpose Register
MB90930 Series
2.8
General-purpose Register
The general-purpose register is a memory block located in RAM at the
addresses 000180H to 00037FH, where 16 bits × 8 are allocated per bank. It may
be used as either general-purpose 8-bit register (byte register R0 to R7), 16-bit
register (word register RW0 to RW7) or 32-bit register (long word register RL0
to RL3).
The general-purpose register allows high-speed RAM accesses via shorter
instructions. It is allocated in blocks within the register bank, which facilitates
protection of register contents and division in units of functions.
When used as a long word register, it can be used as a linear pointer for
directly accessing the entire space.
■ Configuration of General-purpose Register
The general-purpose register contains 32 banks in total which are allocated in RAM at the
addresses 000180H to 00037FH. The register bank pointer (RP) specifies which bank to use.
Similarly, the bank currently in use can be identified by reading RP. The start address of each
bank can be determined from RP as follows:
Start address of general-purpose register = 000180H + RP × 10H
Figure 2.8-1 shows the allocation and configuration of the general-purpose register bank within
the memory space.
Figure 2.8-1 Allocation and Configuration of General-purpose Register Bank in Memory Space
Built-in RAM
000380H
000370H
000360H
0002E0H
0002D0H
0002C0H
0002B0H
0001B0H
0001A0H
000190H
000180H
CM44-10150-1E
:
Byte
address
Byte
address
Register bank 31
Register bank 30
02CEH
R6
:
:
:
02CCH
R4
R2
Register bank 21
02C8H
Register bank 20
02C6H
Register bank 19
02C4H
:
:
:
:
:
02C2H
02CAH
RP
Register bank 2
Register bank 1
Register bank 0
:
14H
02C0H
LSB
R7
02CFH RW7
R5
R3
R0
R1
RW3
02CDH RW6
RW2
RW1
RW0
16bit
02CBH RW5
02C9H RW4
02C7H
02C5H
02C3H
02C1H
RL3
RL2
RL1
RL0
MSB
Conversion formula [000180H + RP x 10H]
R0 to R7: Byte register
RW0 to RW7: Word register
RL0 to RL3: Long word register
MSB : Most Significant Bit
LSB : Least Significant Bit
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CHAPTER 2 CPU
2.8 General-purpose Register
MB90930 Series
Note:
The register bank pointer (RP) is initialized to "00H" after a reset.
■ Register Bank
The register bank consists of general-purpose registers (byte register R0 to R7, word register
RW0 to RW7, long word register RL0 to RL3) used for a variety of operations and as pointers.
The long word register is used as a linear pointer for directly accessing the entire memory
space. The contents of the registers in the register bank is not initialized by resetting, as similar
to the normal RAM, and registers retain their state before the reset. The contents of the
registers at the time of power-on are undefined. Table 2.8-1 shows typical functions of the
general-purpose registers.
Table 2.8-1 Typical Functions of General-purpose Registers
Register name
R0 to R7
Function
Used as an operand for various instructions.
Note: R0 is also used as a counter for barrel shift and normalize instructions.
RW0 to RW7
Used as a pointer.
Used as an operand for various instructions.
Note: RW0 is also used as a counter for string instructions.
RL0 to RL3
Used as a long pointer.
Used as an operand for various instructions.
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CM44-10150-1E
CHAPTER 2 CPU
2.9 Prefix Codes
MB90930 Series
2.9
Prefix Codes
Placing a prefix code before an instruction changes some of the operations.
The MB90930 series has three types of prefix codes:
• Bank Select Prefix (PCB, DTB, ADB, SPB)
• Common Register Bank Prefix (CMR)
• Flag Change Suppress Prefix (NCC)
■ Prefix Codes
● Bank select prefix (PCB, DTB, ADB, SPB)
Placing the bank select prefix before an instruction allows selecting of the memory space
accessed by the instruction, irrespective of the addressing scheme.
● Common register bank prefix (CMR)
Placing the common register bank prefix before an instruction for accessing the register bank
changes a register access of the instruction to the common bank located at the addresses
"000180H" to "00018FH" (register bank selected when RP=0), irrespective of the current
register bank pointer (RP) value.
● Flag Change Suppress Prefix (NCC)
Placing the prefix code for the flag change suppress flag before an instruction will avoid flag
changes caused by executing the instruction.
■ Bank Select Prefix (PCB, DTB, ADB, SPB)
The memory space used for data access is specified individually for each addressing scheme.
Placing the bank select prefix before an instruction allows selection of the memory space
accessed by the instruction, irrespective of the addressing scheme. Table 2.9-1 shows the bank
select prefixes and the corresponding memory spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Space selected
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
The user stack space is used if the S flag in the condition code register (CCR) is set to "0". The
system stack space is used if the flag is set to "1".
If the bank select prefix is used, some instructions may execute irregular operations. Table 2.92 shows instructions not affected by the bank select prefix and Table 2.9-3 shows instructions
that require caution when they are used with bank select prefix.
CM44-10150-1E
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CHAPTER 2 CPU
2.9 Prefix Codes
MB90930 Series
Table 2.9-2 Instructions Not Affected by Bank Select Prefix
Instruction type
Instruction
MOVS
SCEQ
FILS
String instruction
Stack operation
Instruction
PUSHW
I/O access instruction
MOV
MOVW
MOV
MOV
MOVB
SETB
BBC
WBTC
Interrupt return
instruction
RETI
Effect of bank select prefix
MOVSW
SCWEQ
FILSW
The bank register specified by the operand is
used irrespective of whether a prefix is
present.
POPW
The user stack bank (USB) is used if the S flag
is set to "0". The system stack bank (SSB) is
used if the flag is set to "1", irrespective of
whether the prefix is present.
A, io
A, io
io, A
io, #imm8
A, io:bp
io:bp
io:bp, rel
io, bp
MOVX
A, io
MOVW
MOVW
MOVB
CLRB
BBS
WBTS
io, A
io, #imm16
io:bp, A
io:bp
io:bp, rel
io:bp
The I/O space (Address "000000H" to
"0000FFH") is accessed irrespective of
whether the prefix is present.
The system stack bank (SSB) is used
irrespective of whether the prefix is present.
Table 2.9-3 Instructions Requiring Caution When Bank Select Prefix is Used
Instruction type
Instruction
Description
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
The prefix also affects the subsequent instruction.
ILM setting instruction
MOV ILM, #imm8
The prefix also affects the subsequent instruction.
PS recovery instruction
POPW PS
Do not use a bank select prefix to the PS recovery instruction.
■ Common Register Bank Prefix (CMR)
To facilitate the data exchange between multiple tasks, a method must be provided for easily
accessing the same register bank no matter what the value of the register bank pointer (RP) is.
For this purpose, the F2MC -16LX series provides a register bank that can be commonly used
for each task. This is called the common bank. The common bank is located in the area from
address 000180H to 00018FH.
Placing the common register bank prefix (CMR) before an instruction for accessing a register
bank allows changing register access by the instruction to the common bank located at address
000180H to 00018FH (i.e. the register bank selected when RP=0) no matter what the value of
the register bank pointer (RP) is. However, the instructions listed in Table 2.9-4 should be
handled with caution.
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CM44-10150-1E
CHAPTER 2 CPU
2.9 Prefix Codes
MB90930 Series
Table 2.9-4 Instructions Requiring Caution When Common Register Bank Prefix (CMR) is Used
Instruction type
Instruction
Description
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
Flag change instruction
AND CCR, #imm8
PS recovery instruction
POPW PS
The prefix also affects the subsequent instruction.
ILM setting instruction
MOV ILM, #imm8
The prefix also affects the subsequent instruction.
Do not add the CMR prefix to string instructions.
OR CCR, #imm8
The prefix also affects the subsequent instruction.
■ Flag Change Suppress Prefix (NCC)
The flag change suppress prefix (NCC) is used to suppress unnecessary flag changes. Placing
an NCC prefix before the instruction for which you want to suppress the flag change will
prevent a flag change due to execution of the instruction. Changes can be suppressed for the
flags T, N, Z, V and C. However, the instructions listed in Table 2.9-5 should be handled with
caution.
Table 2.9-5 Instructions Requiring Caution When Flag Change Suppress Prefix (NCC) is Used
Instruction type
Instruction
String instruction
MOVS
SCEQ
FILS
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
The condition code register (CCR) changes according to
the instruction specification regardless of the prefix. The
prefix also affects the subsequent instruction.
PS recovery instruction
POPW PS
The condition code register (CCR) changes according to
the instruction specification regardless of the prefix. The
prefix also affects the subsequent instruction.
ILM Setting Instruction
MOV ILM, #imm8
The prefix also affects the subsequent instruction.
Interrupt instruction
Interrupt return instruction
INT #vct8
INT9
INT adder16 INTP addr24
RETI
The condition code register (CCR) changes according to
the instruction specification regardless of the prefix.
Contextual switch instruction
JCTX @A
The condition code register (CCR) changes according to
the instruction specification regardless of the prefix.
CM44-10150-1E
MOVSW
SCWEQ
FILSW
Description
Do not add the NCC prefix to string instructions.
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CHAPTER 2 CPU
2.9 Prefix Codes
MB90930 Series
■ Restrictions on Prefix Codes
The three restrictions listed below are applied when using prefix codes.
• No interrupt/hold request is accepted when a prefix code or an interrupt/hold suppress
instruction is used.
• The effect of a prefix code is delayed if the prefix is placed before an interrupt/hold
instruction.
• If conflicting prefix codes are placed in sequence, only the last one is effective.
Table 2.9-6 shows restrictions applying to prefix codes and interrupt/hold suppress
instructions.
Table 2.9-6 Prefix Codes and Interrupt/Hold Suppress Instructions
Prefix code
Interrupt/hold suppress instruction
(Instruction that delays the effect of the prefix code)
PCB
DTB
ADB
SPB
CMR
NCC
Instruction that accepts
neither interrupt nor hold
requests
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Suppressing interrupt/hold
As shown in Figure 2.9-1, while prefix code or interrupt/hold instruction are executed, any
generated interrupt hold requests are not accepted. In such cases, interrupt/hold processing is
not performed until another instruction has been executed after the one with the prefix code or
the interrupt/hold suppress instruction.
Figure 2.9-1 Suppressing Interrupt/Hold
Interrupt/hold suppress instruction
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(a)
•
•
•
(a) Normal instruction
Interrupt request generated
58
Interrupt accepted
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 2 CPU
2.9 Prefix Codes
MB90930 Series
● Delayed effect of prefix codes
If, as shown in Figure 2.9-2, a prefix code is placed before an interrupt/hold suppress
instruction, the prefix code becomes effective with the first instruction after the interrupt/hold
suppress instruction is issued.
Figure 2.9-2 Interrupt/Hold Suppress Instruction and Prefix Code
Interrupt/hold suppress instruction
MOV A,FFH
NCC
MOV ILM,#imm8
•
•
•
ADD A,01H
•
CCR: XXX10XXB
CCR: XXX10XXB
CCR will not change because of NCC
● Prefix codes in succession
If, as shown in Figure 2.9-3, conflicting prefix codes (PCB, ADB, DTB, SPB) are specified in
sequence, only the last one is effective.
Figure 2.9-3 Prefix Codes in Succession
Prefix code
•
•
•
ADB
DTB
PCB
ADD A,01H
•
•
•
The effective prefix
code is PCB.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 2 CPU
2.9 Prefix Codes
60
MB90930 Series
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 3
INTERRUPT
This chapter describes the relationships
between interrupts and the extended intelligent
I/O service (EI2OS).
3.1 Outline of Interrupts
3.2 Interrupt Sources and Interrupt Vectors
3.3 Interrupt Control Registers and Peripheral Functions
3.4 Hardware Interrupt
3.5 Software Interrupt
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.7 Exception Handling Interrupt by Execution of Undefined
Instruction
3.8 Stack Operations of Interrupt Handling
3.9 Example Program for Interrupt Handling
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
61
CHAPTER 3 INTERRUPT
3.1 Outline of Interrupts
3.1
MB90930 Series
Outline of Interrupts
F2MC-16LX has 4 types of interrupt functions to interrupt the processing
currently being performed and transferring the control to a separately defined
program if an event occurs.
• Hardware interrupt
• Software Interrupt
• Extended intelligent I/O service (EI2OS) interrupt
• Exception handling
■ Types of Interrupts and Corresponding Functions
● Hardware interrupt
Transfers control to a user-defined interrupt handling program in response to an interrupt
request from a peripheral function.
● Software Interrupt
Transfers control to a user-defined interrupt-handling program by executing a software
interrupt dedicated instruction (e.g. INT instruction).
● Extended intelligent I/O service (EI2OS) interrupt
EI2OS is a function for automatic data transfer between a peripheral function and memory.
Data transfer as far as previously performed by the interrupt-handling program is provided in
the same way as via DMA (direct memory access). After the completion of data transfer of the
specified count, the interrupt handling program is automatically executed.
Interrupts from EI2OS are a type of hardware interrupt.
● Exception handling
Exception handling is basically performed in the same way as interrupt handling. If an
exception event (execution of an undefined function) is detected at the instruction boundary,
the normal course of processing is interrupted. This is equivalent to an "INT10" software
interrupt instruction.
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CHAPTER 3 INTERRUPT
3.1 Outline of Interrupts
MB90930 Series
■ Interrupt Operation
F2MC-16LX has 4 types of interrupt functions for starting and returning processing, as shown
in Figure 3.1-1.
Figure 3.1-1 Overall Operational Flow of Interrupt Processing
START
Main program
YES
Valid
hardware interrupt
request
String type instrucNO
tion being executed*
Interrupt start/return processing
YES
EI2OS?
Reading and decoding
next instruction
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software interrupt/exception
handling
Dedicated registers
saved to system stack
Hardware
interrupt
Hardware interrupt
acceptance prohibited
(I=0)
YES
Dedicated registers
saved to system stack
Specified
count completed?
Or, completion request
from peripheral
function issued
?
NO
Update of CPU interrupt
handling level (ILM)
YES
RETI instruction?
NO
Return of dedicated register
from system stack and to
routine before calling
interrupt routine
Executing normal
instruction
NO
Processing
for return
from interrupt
Reading interrupt
vector to update PC
and PCB, then branching
to interrupt routine
Reiteration of string
type instruction completed?*
YES
Setting pointer to next
instruction by updating PC
*: When a string type instruction is being executed, checks for interrupts are made in each step.
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CHAPTER 3 INTERRUPT
3.2 Interrupt Sources and Interrupt Vectors
MB90930 Series
Interrupt Sources and Interrupt Vectors
3.2
F2MC-16LX has functions corresponding to 256 types of interrupt sources.
There are 256 interrupt vector tables allocated starting with the highest
address in memory. The interrupt vectors are shared by all interrupts.
Software interrupts may use all of the above interrupts (INT0 to INT256), but
some of these interrupt vectors will be shared by hardware interrupts and
exception handling interrupts. Only specific interrupt vectors and a interrupt
control register (ICR) are available for setting the hardware interrupts for each
peripheral function.
■ Interrupt Vector
Interrupt vector tables, which are referenced for interrupt handling, are allocated starting with
the highest address of the memory area (FFFC00H to FFFFFFH). The interrupt vectors for
EI2OS, exception handling, hardware interrupts, and software interrupts share the same area.
The allocation of interrupt numbers and interrupt vectors in memory is shown in Table 3.2-1.
Table 3.2-1 List of Interrupt Vectors
Software interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode data
Interrupt No.
Hardware interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception handling>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Hardware interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Hardware interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Hardware interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Note:
Assign an unused interrupt vector to an address such as exception handling.
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CM44-10150-1E
CHAPTER 3 INTERRUPT
3.2 Interrupt Sources and Interrupt Vectors
MB90930 Series
■ Interrupt Sources and Interrupt Vectors/Interrupt Control Registers
Table 3.2-2 shows the relationship between interrupt sources and the interrupt vectors/interrupt
control registers except for software interrupts.
Table 3.2-2 Interrupt Sources and Interrupt Vectors/Interrupt Control Registers
EI2OS
support
Interrupt source
Reset
INT9 instruction
Exception handling
CAN1 RX
CAN1 TX/NS
Input capture 0
DTP/external interrupt - ch.0/ch.1 detected
Reload timer 0
Reload timer 2
Input capture 1
DTP/external interrupt - ch.2/ch.3 detected
Input capture 2
Reload timer 3
Input capture 3/4/5/6/7
DTP/external interrupt - ch.4/ch.5 detected,
UART3 RX
PPG timer 0
DTP/external interrupt - ch.6/ch.7 detected,
UART3 TX
PPG timer 1
Reload timer 1
PPG timer 2/3/4/5
Real time watch timer/
Watch Timer (sub clock)
Free-run timer overflow/clear
A/D converter conversion completed
Sound generator 0/1
Time-base timer
UART2 received
UART2 transmitted
UART1 received
UART1 transmitted
UART0 received
UART0 transmitted
Flash memory status
Delayed interrupt generator module
Interrupt vector
Number
08H
#08
09H
#09
#10 0AH
#11 0BH
#12 0CH
#13 0DH
#14 0EH
0FH
#15
10H
#16
11H
#17
12H
#18
13
#19
H
14H
#20
15H
#21
16H
#22
17H
#23
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
#24
18H
FFFF9CH
#25
19H
FFFF98H
#26
1AH
FFFF94H
#27
#28
#29
1BH
1CH
1DH
FFFF90H
FFFF8CH
FFFF88H
×
#30
1EH
FFFF84H
×
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
×
×
×
×
×
×
×
×
×
×
×
Interrupt control register
Priority
ICR
Address
*2
-
-
High
ICR00
0000B0H*1
ICR01
0000B1H*1
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*1
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
Low
: Available with EI2OS stop function, : Available, ×: Not available
: Available only if no interrupt sources that share ICR are used
*1: • Peripheral functions that share ICR register have the same interrupt level.
• When sharing ICR registers while using the extended intelligent I/O service (EI2OS) for peripheral functions, either a
normal interrupt or an extended intelligent I/O service can be used.
• If, in case of peripheral functions that share an ICR register, one of the functions specifies an extended intelligent I/O
service (EI2OS), the other is not allowed to use an interrupt.
*2: Priority assigned if interrupts with the same level occur.
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CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
3.3
MB90930 Series
Interrupt Control Registers and Peripheral
Functions
Interrupt control registers (ICR00 to ICR15) are located in the interrupt
controller corresponding to all the peripheral functions that include interrupt
functions. These registers control the interrupt and extended intelligent I/O
service (EI2OS).
■ List of Interrupt Control Registers
Table 3.3-1 shows a list of interrupt control registers and the corresponding peripheral
functions.
Table 3.3-1 List of Interrupt Control Registers
Address
Register
Abbreviation
0000B0H
Corresponding peripheral function
Interrupt control register 00
ICR00
Not available
0000B1H
Interrupt control register 01
ICR01
CAN1
Input capture 0, DTP/external interrupt 0/1
0000B2H
Interrupt control register 02
ICR02
0000B3H
Interrupt control register 03
ICR03
Reload timer 0/2
0000B4H
Interrupt control register 04
ICR04
Input capture 1, DTP/external interrupt 2/3
0000B5H
Interrupt control register 05
ICR05
Reload timer 3
0000B6H
Interrupt control register 06
ICR06
Input capture 3/4/5/6/7, DTP/external interrupt 4/5, UART3
0000B7H
Interrupt control register 07
ICR07
PPG timer 0, DTP/external interrupt 6/7, UART3
PPG timer 1, reload timer 1
0000B8H
Interrupt control register 08
ICR08
0000B9H
Interrupt control register 09
ICR09
PPG timer 2/3/4/5, real time watch timer, watch timer
0000BAH
Interrupt control register 10
ICR10
Free-run timer, A/D converter
0000BBH
Interrupt control register 11
ICR11
Time-base timer, sound generator 0/1
0000BCH
Interrupt control register 12
ICR12
UART2
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
UART0
0000BFH
Interrupt control register 15
ICR15
Flash memory, delayed interrupt generator module
■ Functions of Interrupt Control Registers
The interrupt control registers (ICR) have the 4 functions listed below.
• Setting the interrupt level for the corresponding peripheral function
• Selecting whether the interrupt for the corresponding peripheral function is set to either
normal interrupt or extended intelligent I/O service (EI2OS)
• Selecting the channel of extended intelligent I/O service (EI2OS)
• Indicating the status of extended intelligent I/O service (EI2OS)
Some functions of interrupt control registers (ICR) differ depending on the time of either a read
or a write operation, as shown in Figure 3.3-1 and Figure 3.3-2.
Note:
Do not access the interrupt control register (ICR) with read-modify-write (RMW) instructions
as it might cause a malfunction.
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CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
MB90930 Series
3.3.1
Interrupt Control Registers (ICR00 to ICR15)
The interrupt control registers correspond to all of the peripheral functions that
use interrupt functions and control processing at interrupt request generation.
Some functions of these registers differ depending on the time of either a read
or a write operation.
■ Interrupt Control Registers (ICR00 to ICR15)
Figure 3.3-1 Interrupt Control Registers (ICR00 to ICR15) during Write Operations
Write Operation
Address
MSB
0000B0H
to
ICS3 ICS2 ICS1 ICS0
0000BFH
ISE
IL2
LSB
Initial value
IL0
00000111B
IL1
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
ISE
EI2OS enable bit
0
Starts interrupt sequence when an interrupt occurs
1
Starts EI2OS when an interrupt occurs
ICS3 ICS2 ICS1 ICS0
MSB : Most Singnificant Bit
LSB : Least Singnificant Bit
: Initial value
CM44-10150-1E
EI2OS channel selection bits
Channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
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CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
MB90930 Series
Figure 3.3-2 Interrupt Control Registers (ICR00 to ICR15) during Read Operations
Read Operation
Address
MSB
to
−
0000B0H
0000BFH
LSB
−
S1
MSB : Most Singnificant Bit
LSB : Least Singnificant Bit
−
: Undefined
: Initial value
68
S0
ISE
IL2
IL1
IL0
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Initial value
--000111B
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
2
ISE
EI OS enable bit
0
Starts interrupt sequence when an interrupt occurs
1
Starts EI2OS when an interrupt occurs
EI2OS status
S1
S0
0
0
Whether EI2OS is in operation or has not started
0
1
In stop state due to the end of counting
1
0
Reserved
1
1
In stop state due to request from peripheral function
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
MB90930 Series
3.3.2
Functions of Interrupt Control Registers
The interrupt control registers (ICR00 to ICR15) consist of bits with the
following 4 functions:
• Interrupt level setting bits (IL2 to IL0)
• Extended intelligent I/O service (EI2OS) enable bit (ISE)
• Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
• Extended intelligent I/O service (EI2OS) status bits (S1, S0)
■ Configuration of Interrupt Control Register (ICR)
Figure 3.3-3 shows the bit configuration of the interrupt control register (ICR).
Figure 3.3-3 Configuration of Interrupt Control Register (ICR)
Interrupt control register (ICR) during write operations
Address
0000B0H to 0000BFH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICS3
W
ICS2
W
ICS1
W
ICS0
W
ISE
R/W
IL2
R/W
IL1
R/W
IL0
R/W
00000111B
Initial value
--000111B
Interrupt control register (ICR) during read operations
Address
0000B0H to 0000BFH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
S1
R
S0
R
ISE
R/W
IL2
R/W
IL1
R/W
IL0
R/W
R/W: Readable/Writable
R: Read only
W: Write only
-:
Undefined
Bits ICS3 to ICS0 are valid only if the extended intelligent I/O service (EI2OS) has been
started. To start EI2OS, set the ISE bit to "1", otherwise, set it to "0". If EI2OS is not started,
ICS3 to ICS0 do not need to be set.
ICS1 and ICS0 are valid only in write operations, and S1 and S0 are valid only in read
operations.
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CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
MB90930 Series
■ Functions of Interrupt Control Registers
● Interrupt level setting bits (IL2 to IL0)
These bits specify the interrupt level of the corresponding peripheral function. The interrupt level
is initialized to level 7 (no interrupt) at reset. The interrupt level setting bits correspond to each
interrupt level as shown in Table 3.3-2.
Table 3.3-2 Relationship between Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt level
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 (Highest interrupt)
1
0
1
1
1
1
1
0
1
6 (Lowest interrupt)
7 (No interrupt)
● Extended intelligent I/O service (EI2OS) enable bit (ISE)
If, when an interrupt request is generated, this bit is set to "1", EI2OS starts. If it is set to "0",
an interrupt sequence starts. If the EI2OS end condition is satisfied (i.e., the S1 and S0 bits are
other than 00B), the ISE bit is cleared. If the corresponding peripheral function does not use
any EI2OS functions, the ISE bit must be set to "0" by software. The ISE bit is initialized to "0"
at reset.
● Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
The EI2OS channel is specified by these write-only bits. The value set by these bits determines the
EI2OS descriptor address. The ICS bits are initialized to "0000B" at reset. Table 3.3-3 shows the
relationship between the EI2OS channel selection bits and the descriptor address.
Table 3.3-3 Relationship between EI2OS Channel Selection Bits and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Channel selected
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
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CM44-10150-1E
CHAPTER 3 INTERRUPT
3.3 Interrupt Control Registers and Peripheral Functions
MB90930 Series
● Extended intelligent I/O service (EI2OS) status bits (S1, S0)
These bits are read-only bits. Their value is checked at the end of EI2OS operation to determine
the operational status (in operation or ended). They are initialized to "00B" at reset. Table 3.3-4
shows the relationship between the S0/S1 bits and the EI2OS status.
Table 3.3-4 Relationship between EI2OS Status Bits and EI2OS Status
EI2OS status
S1
S0
0
0
EI2OS is in operation or not active
0
1
In stop state because of the end of counting
1
0
Reserved
1
1
In stop state because of a request from a peripheral function
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
3.4
MB90930 Series
Hardware Interrupt
Hardware interrupts are used to temporarily stop the execution of program that
is being executed by the CPU in response to an interrupt request signal from a
peripheral function and then transfer control to a user-defined interrupt
handling program. The extended intelligent I/O service (EI2OS) or an external
interrupt may also be executed as a kind of hardware interrupt.
■ Functions of Hardware Interrupt
● Functions of Hardware Interrupt
During the processing for hardware interrupts, the interrupt level of an interrupt request signal
output by the peripheral function is compared with the value of the interrupt level mask register
(ILM) in the CPU processor status register (PS). The I flag in the processor status register (PS)
is then referenced to determine whether the interrupt is acceptable.
If the hardware interrupt is accepted, the register contents in the CPU are automatically saved
to the system stack and the interrupt level currently requested is stored in the interrupt level
mask register (ILM). After that, the control branches to the corresponding interrupt vector.
● Multiple Interrupts
Hardware interrupts can be generated in multiple.
● Extended intelligent I/O service (EI2OS)
EI2OS is a function for automatic transfer between memory and I/O, generating a hardware
interrupt when the number of transfers reaches a pre-defined count. EI2OS cannot start multiple
times concurrently: While one EI2OS processing is running, all other interrupt requests and
EI2OS requests are retained.
● External Interrupt
External interrupts are accepted as hardware interrupts transferred via a peripheral function
(interrupt request detection circuit).
● Interrupt Vector
The interrupt vector table to be referenced for interrupt handling is allocated at the memory
addresses "FFFC00H" to "FFFFFFH", which are shared with software interrupts.
For the allocation of interrupt numbers and interrupt vectors, see Section "3.2
Sources and Interrupt Vectors".
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Interrupt
CM44-10150-1E
CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
■ Structure of Hardware Interrupt
The hardware interrupt unit exists in the four separate sections, as shown in Table 3.4-1. To use
hardware interrupts, these four sections must be set using the program.
Table 3.4-1 Hardware Interrupt Unit
Hardware interrupt unit
Function
Peripheral functions
Interrupt enable bit, interrupt request bit
Controls interrupt requests from peripheral functions
Interrupt controller
Interrupt control register (ICR)
Sets interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies whether interrupts are enabled
Interrupt level mask register (ILM)
Compares request interrupt level and current interrupt
level
Microcode
Executes interrupt handling routine
Interrupt vector table
Stores branch addresses for interrupt handling
CPU
Addresses
FFFC00H to FFFFFFH in
memory
■ Suppressing Hardware Interrupt
Acceptance of hardware interrupt requests is suppressed under the following conditions.
● Suppressing hardware interrupts when writing to peripheral function control register area
When writing to the peripheral function control register area, hardware interrupt requests are
not accepted. This avoids incorrect interrupt-related operations by the CPU when rewriting the
interrupt control registers with each peripheral function. The peripheral function control
register area is not the I/O addressing area from "000000H" to "0000FFH", but the area allocated
for the control registers among the peripheral function control registers and data register.
Figure 3.4-1 shows the hardware interrupt operations when writing to the peripheral function
control register area.
Figure 3.4-1 Hardware Interrupt Requests when Writing to the Peripheral Function Control
Register Area
Instruction for writing to peripheral function control register area
.....
MOV A, #08
MOV io, A
Interrupt request
occurs at this point
CM44-10150-1E
MOV A, 2000H
Not branch to
interrupt
FUJITSU MICROELECTRONICS LIMITED
Interrupt process
Branch to
interrupt
73
CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
● Suppressing hardware interrupts by interrupt suppress instructions
The 10 types of hardware interrupt suppress instructions shown in Table 3.4-2 will suppress
detection of hardware interrupt requests and ignore any such interrupt request. Even if a valid
hardware interrupt request is issued when these instructions are being executed, interrupt
handling is not executed until another type of instruction is executed.
Table 3.4-2 Hardware Interrupt Suppress Instructions
Prefix code
Instruction that accepts
neither interrupt nor hold
requests
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/hold suppress instruction
(Instruction that delays the effect of the prefix code)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Hardware interrupt suppression during the execution of software interrupts
When software interrupt processing starts, other interrupt requests are not acceptable by the
reason of clearing the I flag to "0".
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CM44-10150-1E
MB90930 Series
3.4.1
Hardware Interrupt Operation
CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
This section describes the operation from generation of a hardware interrupt
request to the completion of interrupt handling.
■ Starting Hardware Interrupt
● Operation of peripheral function (generating an interrupt request)
A peripheral function that uses hardware interrupt requests has an "interrupt request flag" to
indicate whether an interrupt request is present and an "interrupt enable flag" to enable or
disable interrupt requests to the CPU. The interrupt request flag is set when a peripheral
function-specific event is generated, and an interrupt request is issued to the interrupt controller
if the interrupt enable flag is set to "enable".
● Operation of interrupt controller (control of interrupt requests)
The interrupt controller compares interrupt levels (IL) in interrupt requests that are received at
the same time, selects the request with the highest priority level (the lowest IL value) and
reports it to the CPU. If multiple requests have the same priority level, the request with the
smallest interrupt number has the priority.
● CPU operation (acceptance of interrupt requests and interrupt handling)
The CPU compares the interrupt level (ICR: IL2 to IL0) received with the interrupt level mask
register (ILM). If IL < ILM and interrupts are enabled (I bit in the PS register is set to "1"),
processing of the interrupt handling microcode starts after the instruction currently being
executed is completed. If the ISE bit of the interrupt control register (ICR) is referenced and
found to be "0" during processing of the start of the interrupt handling microcode, the
execution of interrupt handling will continue (If ISE is set to "1", EI2OS will start).
During interrupt handling, the contents of dedicated registers (12 bytes of A, DPR, ADB, DTB,
PCB, PC and PS) are first saved to the system stack (into the system stack area indicated by
SSB and SSP). Then, the interrupt vector is loaded into the program counter (PCB, PC), ILM is
updated and the stuffing (S) flag is set (i.e., the CCR's S flag is set to "1" and the system stack
becomes enabled).
■ Return from Hardware Interrupt
If, in the interrupt handling program, the interrupt request flag of the peripheral function, which
is an interrupt source, is cleared and the RETI instruction is executed, the 12 bytes of data
saved to the system stack are returned to the dedicated registers to restart the processing that
was being executed before the interrupt branch. By clearing the interrupt request flag, the
interrupt request that was output to the interrupt controller by a peripheral function is
automatically canceled.
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
■ Hardware Interrupt Operation
Figure 3.4-2 shows the operation from the generation of a hardware interrupt to the completion
of interrupt handling.
Figure 3.4-2 Hardware Interrupt Operation
Internal data bus
(7)
PS, PC ⋅
Microcode
F2MC-16LX
⋅
PS
IR
CPU
(6)
I
ILM
Check
(5)
Comparator
(4)
(3)
Other peripheral
function
⋅⋅
⋅
Peripheral function that
generates an interrupt request
Enable FF
(8)
Source FF
(1)
AND
Level
Interrupt
comparator level IL
(2)
Interrupt controller
RAM
IL
PS
I
ILM
IR
FF
: Interrupt level setting bit in interrupt controller register (ICR)
: Processor status register
: Interrupt enable flag
: Interrupt level mask register
: Instruction register
: Flip-flop
(1) An interrupt source is generated by the peripheral function.
(2) If a reference to the interrupt enable bit by the peripheral function indicates that interrupts
are enabled, the interrupt request is issued from the peripheral to the interrupt controller.
(3) The interrupt controller that receives the interrupt request checks the priority of interrupt
requests generated at the same time, then transfers the interrupt level (IL) corresponding to
the interrupt request to the CPU.
(4) The CPU compares the interrupt level (IL) requested from the interrupt controller with the
interrupt level mask register (ILM).
(5) If the comparison shows that the priority of the interrupt is higher than the current interrupt
handling level, the I flag of the condition code register (CCR) is checked.
(6) If the check in (5) indicates that the I flag is set to interrupt enabled (I bit set to "1"), ILM
is set to the requested level (IL) after the instruction currently being executed is completed.
(7) The register content is saved and processing branches to the interrupt handling routine.
(8) The user's interrupt handling routine clears the interrupt source generated in (1) for
executing the RETI instruction. This completes interrupt handling.
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
3.4.2
Operation Flow of Hardware Interrupt
If an interrupt request is generated from a peripheral function, the interrupt
controller transfers the respective interrupt level to the CPU. If the CPU state
allows the acceptance of interrupts, the instruction currently being executed is
temporarily suspended to execute the interrupt handling routine or start the
extended intelligent I/O service (EI2OS). If a software interrupt is generated by the
INT instruction, the interrupt handling routine is executed irrespective of the CPU
state. Moreover, if a software interrupt is generated by an INT instruction,
hardware interrupts are disabled.
■ Operation Flow of Hardware Interrupt
Figure 3.4-3 shows the operation flow of hardware interrupts.
Figure 3.4-3 Operation Flow of Hardware Interrupt
START
Main program
YES
I&IF&IE = 1
AND
ILM > IL
String type instruction being executed* NO
Interrupt start/return processing
YES
ISE = 1
Reading and decoding
next instruction
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software interrupt/exception
handling
Hardware
interrupt
Dedicated registers
saved to system stack
I←0
YES
Dedicated registers
saved to system stack
(Hardware interrupt
prohibited)
Specified count
completed?
Or, completion request from
peripheral function
issued?
NO
ILM ← IL
(transfer to ILM the interrupt
level of the accepted
interrupt request)
YES
RETI instruction?
NO
Executing normal instruction
(including interrupt handling)
NO
Processing
for return
from interrupt
Return from dedicated
register from system stack
and, to routine before calling
interrupt routine
S←1
(Enabling system
stack)
PCB, PC ← Interrupt vector
(Branch to interrupt
handling routine)
Reiteration of
string type instruction
completed?*
YES
Setting pointer to next
instruction by updating PC
*:
I:
IF :
IE :
ILM :
ISE :
IL :
CM44-10150-1E
When a string type instruction is being executed,
checks for interrupts are made in each step.
Interrupt enable flag in condition code register (CCR)
Interrupt request flag of peripheral function
Interrupt enable flag of peripheral function
Interrupt level mask register (in PS)
EI2OS enable flag in interrupt control register (ICR)
Interrupt level setting bit in interrupt control register (ICR)
S:
Stack flag in condition code register (CCR)
PCB : Program bank register
PC : Program counter
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
Procedure for Using Hardware Interrupt
3.4.3
To use an hardware interrupt, the system stack area, peripheral function, and
interrupt control register (ICR) must be specified in advance.
■ Procedure for Using Hardware Interrupt
An example procedure for using hardware interrupts is shown in Figure 3.4-4.
Figure 3.4-4 Procedure for Using Hardware Interrupt
Start
(1)
(2)
Setting the system stack area
(3)
ICR setting in interrupt
controller
(4)
Setting for start of
peripheral function
Setting the interrupt
enable bit to "enable"
(5)
Interrupt handling program
Initial setting of
peripheral function
Branching to stack handling (8)
Interrupt vector
(7)
Processing by
hardware
Setting ILM and I in PS
(9)
Handling of interrupt to peripheral function (executing
interrupt handling routine)
Clearing the interrupt source
(10) Interrupt return instruction (RETI)
Main program
(6)
Interrupt request generated
Main program
(1) Specify the system stack area.
(2) Initialize the peripheral function for generating interrupt requests.
(3) Specify the interrupt control register (ICR) in the interrupt controller.
(4) Set the peripheral function to operation start state and the interrupt enable bit to "enable".
(5) Set the interrupt level mask register (ILM) and interrupt enable flag (I) to allow interrupts
to be accepted.
(6) A hardware interrupt request is generated when the peripheral function generates an
interrupt.
(7) The hardware interrupt handling saves register contents for branching to the interrupt
handling program.
(8) Process the interrupt generation for the peripheral function using the interrupt handling
program.
(9) Clear the interrupt request from the peripheral function.
(10)Execute the interrupt return instruction to return to the program that was executed before
branching.
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3.4.4
Multiple Interrupts
CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
For hardware interrupts, multiple interrupts are enabled by setting different
interrupt levels to a interrupt level setting bit (IL0, IL1, IL2) in the interrupt
control register (ICR) for multiple interrupt requests from the peripheral
function. However, multi-startup is not allowed for the extended intelligent I/O
service.
■ Multiple Interrupts Operation
If, when an interrupt handling routine is being executed, an interrupt request with a higher priority
level is issued, the interrupt request with the higher priority level is accepted by interrupting the
current interrupt handling. After processing the interrupt with the higher level has been completed,
the processing of the original interrupt is restarted. The interrupt level can be set to a value from 0 to
7. When set to level 7, the CPU will not accept the interrupt request.
If, when interrupt handling is being executed, another interrupt is issued which has the same
priority or lower as the current one, the new interrupt request will be retained until processing
of the current interrupt is completed unless the I flag or ILM is changed. By setting the I flag in
the condition code register (CCR) to "interrupt disabled" (I in CCR set to "0") or the interrupt
level mask register (ILM) to "interrupt disabled" (ILM set to "000") during the interrupt
handling routine, starting multiple interrupts can be temporarily prohibited.
Note:
Starting multiple instanc es of the extended intelligent I/O s ervice (EI 2OS) is pr ohibited. If
an extended intelligent I/O service (EI2OS) is being processed, all other interrupt requests
and extended intelligent I/O service requests are retained.
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
■ Example of Multiple Interrupts
In the following example for processing multiple interrupts, the timer interrupt has priority
over A/D converter interrupts: the interrupt level of the A/D converter is set to 2, and the timer
interrupt level is set to 1. When a timer interrupt is generated while an A/D converter interrupt is
being processed with this setting, the processing shown in Figure 3.4-5 is performed.
Figure 3.4-5 Example of Multiple Interrupts
Main program
Peripheral
initialized
A/D interrupt handling
Interrupt level 2
(ILM=010)
(1)
A/D interrupt (2)
generated
Timer interrupt handling
Interrupt level 1
(ILM=001)
(3) Timer interrupt generated
Interrupt
(4) Timer interrupt handling
Restart
Main process (8)
restart
(6) A/D interrupt handling
(5) Timer interrupt return
(7) A/D interrupt return
● A/D interrupt generation
When A/D converter interrupt handling starts, the interrupt level mask register (ILM) is
automatically set to the same interrupt level (IL2 to IL0 in ICR) as that for the A/D converter
(in this example, (2). If a new interrupt request of level 1 or 0 is generated in this case, the new
interrupt is processed with priority.
● End of interrupt handling
If, after an interrupt handling is completed, a return instruction (RETI) is executed, the contents
of dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) that were saved to the stack are
returned, and the interrupt level mask register (ILM) is set to the value immediately before the
interrupt.
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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
MB90930 Series
3.4.5
Hardware Interrupt Processing Time
The duration between the generation of a hardware interrupt request and the
execution of the interrupt handling routine must include the time until the
instruction currently being executed is completed plus the interrupt handling
time.
■ Hardware Interrupt Processing Time
The interrupt request sample wait time and interrupt handling time (time required for preparing
for interrupt handling) are required while an interrupt request is generated and accepted, then
the interrupt handling routine is executed. Figure 3.4-6 shows the interrupt handling time.
Figure 3.4-6 Interrupt Handling Time
CPU operation
Interrupt wait time
Execution of normal instruction
Interrupt request
sample wait time
Interrupt handling
Interrupt handling routine
Interrupt handling time
(θ machine cycles)*
Interrupt request generated
: Final instruction cycle during interrupt request sampling
* : One machine cycle corresponds to one clock interval of the machine clock (φ).
● Interrupt request sample wait time
It means the time from when an interrupt request is generated until the instruction currently
being executed is completed. Whether an interrupt request is generated is determined by
sampling the interrupt requests in the final cycle of each instruction. Therefore, the CPU cannot
detect an interrupt request while an instruction is still being executed, which results in wait
time.
The interrupt request sample wait time reaches the maximum value if an interrupt request
occurs immediately after the start of a sequence of the type "POPW RW0, ... RW7 instruction"
(45 machine cycles), because these sequences have the longest execution cycle.
● Interrupt handling time (θ machine cycles)
After an interrupt request is accepted, the CPU performs such operations as saving the contents
of the dedicated registers to the system stack, acquiring the interrupt vector, and so on. This
requires an interrupt handling time of θ machine cycles. The interrupt handling time can be
obtained from the following formulas:
At the start of interrupt processing: θ = 24 + 6 × Z machine cycles
At the return from an interrupt: θ = 11 + 6 × Z machine cycles (RETI instruction)
The interrupt handling time depends on the address indicated by the stack pointer. Table 3.4-3
shows the required correction value (Z) for the interrupt handling time.
One machine cycle corresponds to one clock cycle of the machine clock (φ).
Table 3.4-3 Correction Value (Z) for Interrupt Handling Time
Address indicated by the stack pointer
External, 8-bit
CM44-10150-1E
Correction value (Z)
+4
External, even-numbered address
+1
External, odd-numbered address
+4
Internal, even-numbered address
0
Internal, odd-numbered address
+2
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CHAPTER 3 INTERRUPT
3.5 Software Interrupt
3.5
MB90930 Series
Software Interrupt
Software interrupts have the function to transfer control from the program
currently executed by the CPU to the interrupt handling program defined by the
user when a software interrupt instruction (INT instruction) is executed.
Hardware interrupts are disabled while a software interrupt is being executed.
■ Starting Software Interrupt
● Starting Software Interrupt
To issue a software interrupt, use the INT instruction. Software interrupt requests have no
interrupt request flag or enable flag, but always generate an interrupt request if the INT
instruction is executed.
● Disabling hardware interrupts
The INT instruction has no interrupt level, so the interrupt level mask register (ILM) is not
updated. During the execution of the INT instruction, the I flag in the condition code register
(CCR) is set to "0" to mask the hardware interrupt. To enable hardware interrupts during
software interrupt handling, set the I flag to "1" in the software interrupt handling routine.
● Software Interrupt Operation
When the CPU receives and executes an INT instruction, it starts execution of the microcode
for software interrupt handling. Use this microcode for saving the contents of the CPU internal
registers to the system stack, masking hardware interrupts (I flag in CCR set to "0") and
branching to the corresponding interrupt vector.
For the allocation of interrupt numbers and interrupt vectors, see Section "3.2
Sources and Interrupt Vectors".
Interrupt
■ Return from Software Interrupt
When an interrupt return instruction (RETI instruction) is executed in the interrupt handling
program, the 12-byte data saved to the system stack is restored to the dedicated registers.
Moreover, the control returns to the processing that was being executed immediately before the
interrupt branch.
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CHAPTER 3 INTERRUPT
3.5 Software Interrupt
MB90930 Series
■ Software Interrupt Operation
Figure 3.5-1 shows the operation performed from software interrupt generation to completion
of interrupt handling.
Figure 3.5-1 Software Interrupt Operation
Internal data bus
PS,PC…
(2) Microcode
(1)
PS
I
S
IR
F2MC-16LX
Queue
Fetch
RAM
PS
I
S
IR
: Processor status register
: Interrupt enable flag
: Stack flag
: Instruction register
(1) Execute the software interrupt instruction.
(2) Based on the microcode for the software interrupt instruction, perform the necessary
processing, such as saving the contents of the dedicated registers, and perform branch
processing.
(3) Execute the RETI instruction in the user's interrupt handling routine to end interrupt
handling.
■ Precaution for Software Interrupt
If the program bank register (PCB) is set to "FFH", the CALLV instruction's vector area
overlaps the table for INT #vct8 instruction. When making the software, be sure that the
addresses for the CALLV instruction and INT #vct8 instruction do not overlap.
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6
MB90930 Series
Interrupt by Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) is a function to automatically
transfer data between the peripheral function (I/O) and memory, and generates
a hardware interrupt when the data transfer is completed.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service is processed as a type of hardware interrupt. It provides a
function to automatically transfer data between the peripheral function (I/O) and memory. The
data transfer that was previously performed by the interrupt-handling program is provided in
the same way as via DMA (direct memory access). After completion, the end condition is set,
and then an automatic branch to the interrupt handling routine occurs. The user only has to
make a program for starting and ending EI2OS. It is not necessary to provide a program for
data transfer while the service is being processed.
● Advantages of using the extended intelligent I/O service (EI2OS)
Compared with data transfer as provided by the interrupt handling routine, using EI2OS
provides the advantages listed below:
• No transfer program is required, which reduces overall program size.
• Transfer may be suspended based on the state of the peripheral function (I/O), which
eliminates the need to transfer unnecessary data.
• Either incrementing or not updating the buffer address may be selected.
• Either incrementing or not updating the I/O register address may be selected.
● Completion interrupt for the extended intelligent I/O service (EI2OS)
When data transfer by EI2OS is completed, the end condition is stored in the S1 and S0 bits of
the interrupt control register (ICR). After this, the system automatically branches to the
interrupt handling routine.
The completion source for EI2OS can be determined by using the interrupt handling program to
check the EI2OS status (S1 and S0 bits in ICR).
The interrupt number and interrupt vector for each peripheral are fixed. For detailed
information, see Section "3.2 Interrupt Sources and Interrupt Vectors".
● Interrupt control register (ICR)
This register is located in the interrupt controller and used to start the EI2OS, specify EI2OS
channels, and indicate the state when EI2OS ends.
● Extended intelligent I/O service (EI2OS) descriptor (ISD)
This is a data item of 8 byte, which is located in the RAM at the addresses "000100H" to
"00017FH", provided for 16 channels. It retains the transfer mode, I/O address and transfer
counts, and buffer addresses. The corresponding channel is specified by the interrupt control
register (ICR).
Note:
During the operation of the extended intelligent I/O service (EI2OS), program execution of
the CPU is stopped.
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
■ Operation of Extended Intelligent I/O Service (EI2OS)
Figure 3.6-1 shows the EI2OS operation.
Figure 3.6-1 Operation of Extended Intelligent I/O Service (EI2OS)
Memory space
by IOA
I/O
register
I/O register
CPU
Peripheral
function (I/O)
(5)
Interrupt request
(3)
ISD
by ICS
(2)
(3)
(1)
Interrupt control register (ICR)
Interrupt controller
by BAP
(4)
ISD :
IOA
BAP
ICS :
DCT
Buffer
by DCT
EI2OS descriptor
: I/O address pointer
: Buffer address pointer
EI2OS channel selection bit in the interrupt control register (ICR)
: Data counter
(1) I/O requests the transfer.
(2) Interrupt controller selects the descriptor.
(3) Transfer source/destination are read from the descriptor.
(4) Data transfer is performed between I/O and memory.
(5) Interrupt source is automatically cleared.
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6.1
MB90930 Series
Extended Intelligent I/O Service (EI2OS) Descriptor
(ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) is located in the
internal RAM at the addresses "000100H" to "00017FH" and consists of
8 bytes ✕ 16 channels.
■ Configuration of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The EI2OS Descriptor (ISD) consists of 8 bytes × 16 channels. Each ISD has the structure
shown in Figure 3.6-2. The relationship between the channel number and ISD address is
indicated in Table 3.6-1.
Figure 3.6-2 Configuration of EI2OS Descriptor (ISD)
MSB
LSB
Data counter: upper 8 bits (DCTH)
H
Data counter: lower 8 bits (DCTL)
I/O register address pointer: upper 8 bits (IOAH)
I/O register address pointer: lower 8 bits (IOAL)
EI2OS status register (ISCS)
Buffer address pointer: upper 8 bits (BAPH)
Buffer address pointer: middle 8 bits (BAPM)
ISD heading address
(000100H + 8 ✕ ICS)
Buffer address pointer: lower 8 bits (BAPL)
L
Table 3.6-1 Relationship between Channel Number and Descriptor Address
86
Channel No.
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
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MB90930 Series
3.6.2
CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
Extended Intelligent I/O Service (EI2OS) Descriptor
(ISD) Registers
The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the
registers listed below.
• Data counter (DCT)
• I/O register address pointer (IOA)
• Extended intelligent I/O service (EI2OS) status register (ISCS)
• Buffer address pointer (BAP)
Note that the initial value of each register is undefined at reset.
■ Data Counter (DCT)
The data counter (DCT) is a register with a length of 16 bits for storing the transfer data count.
Whenever an item of data is transferred, the counter is decremented by one. When this counter
reaches zero, EI2OS operation ends. The maximum transfer count that can be specified by the
data counter (DCT) is 65,536
(64 Kbytes). Figure 3.6-3 shows the configuration of the DCT.
Figure 3.6-3 Configuration of Data Counter (DCT)
DCTH
DCTL
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 XXXXXXXXXXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W:Readable/Writable
X: Undefined value
■ I/O Register Address Pointer (IOA)
The I/O register address pointer (IOA) is a register with a length of 16 bits to indicate the lower
address (A15 to A00) of the I/O register for data transfer with the buffer. The upper address
(A23 to A16) is set to all 0's, allowing I/O addresses from "000000H" to "00FFFFH" to be
specified. Figure 3.6-4 shows the configuration of the IOA.
Figure 3.6-4 Configuration of I/O Register Address Pointer (IOA)
IOAH
IOAL
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 XXXXXXXXXXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W:Readable/Writable
X: Undefined value
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS)
The extended intelligent I/O service (EI2OS) status register (ISCS) consists of 8 bits indicating
whether buffer address pointer and I/O register address pointer can be updated or are fixed.
They also indicate the type of data transfer (in bytes or in words) as well as the direction of
transfer. Figure 3.6-5 shows the configuration of the ISCS.
Figure 3.6-5 Configuration of EI2OS Status Register (ISCS)
bit7
bit6
bit5
bit4
RESV RESV RESV IF
bit3
bit2
bit1
bit0
Initial value
BW
BF
DIR
SE
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
EI2OS completion control bit
SE
0
Not completed by request from a peripheral function
1
Completed by request from a peripheral function
Data transfer direction bit
DIR
0
I/O register address pointer → Buffer address pointer
1
Buffer address pointer → I/O register address pointer
BAP update/fix selection bit
BF
0
Buffer address pointer is updated after data transfer *1
1
Buffer address pointer is not updated after data transfer
BW
Transfer data length specification bit
0
Byte
1
Word
IF
IOA update/fix selection bit
0
I/O register address pointer is updated after data transfer *2
1
I/O register address pointer is not updated after data transfer
RESV
Reserved bits
Always write "0" to these bits.
R/W : Readable/Writable
X : Undefined value
*1 : Buffer address pointer varies only in the lower 16 bits and can only be incremented.
*2 : Address pointer allows only incrementing.
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a register consisting of 24 bits. It is used to store the
address for the next EI2OS data transfer. A BAP is separately assigned for the respective
EI2OS channel; each EI2OS channel can be used to transfer data between any 16 Mbyte
address and the I/O. If the BF bit of the EI2OS status register (ISCS) (bit in the EI2OS status
register indicating whether BAP can be updated or is fixed) is set to "updated", the BAP varies
only in the lower 16 bits (BAPM, BAPL), while the upper 8 bits (BAPH) will not be changed.
The buffer address pointer (BAP) can specify the area "000000H" to "FFFFFFH".
Figure 3.6-6 shows the configuration of the buffer address pointer (BAP).
Figure 3.6-6 Configuration of Buffer Address Pointer (BAP)
BAP
bit23 to bit16
BAPH
(R/W)
bit15 to bit8
BAPM
(R/W)
bit7 to bit0
BAPL
(R/W)
Initial value
XXXXXXH
R/W:Readable/Writable
X: Undefined value
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6.3
MB90930 Series
Operation of the Extended intelligent I/O Service
(EI2OS)
If a peripheral function issues an interrupt request and the corresponding
interrupt control register (ICR) is set to start EI2OS, the CPU allows EI2OS data
transfer. After the data transfer is completed for the count specified, the system
will automatically perform the hardware interrupt.
■ Processing Procedure for Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 shows the operational flow of EI2OS processing using the CPU-internal
microcode.
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3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
Figure 3.6-7 Operation Flow of Extended Intelligent I/O Service (EI2OS)
Interrupt request generated
from peripheral function
ISE = 1
NO
YES
Interrupt sequence
Read ISD/ISCS
Completion
request from peripheral
function
YES
DIR = 1
YES
NO
Data indicated by IOA
(Data transfer)
Memory area indicated by BAP
IF = 0
Data indicated by BAP
(Data transfer)
Memory area indicated by IOA
YES
NO
BF = 0
DCT = 00
NO
Update value
depends on BW
Update IOA
Update value
depends on BW
Update BAP
YES
NO
Decrement DCT
(-1)
YES
Set S1/S0 to "00B"
Peripheral function
interrupt request cleared
CPU operation resumes
2
ISD : EI OS descriptor
ISCS: EI2OS status register
IF
: IOA update/fix selection bit in EI2OS
status register (ISCS)
BW : Transfer data length setting bit in
EI2OS status register (ISCS)
BF : BAP update/fix selection bit in EI2OS
status register (ISCS)
DIR : Data transfer direction setting bit in EI2OS
status register (ISCS)
SE : EI2OS completion control bit in EI2OS
status register (ISCS)
CM44-10150-1E
YES
SE = 1
NO
NO
EI2OS completion processing
Set S1/S0 to "01B"
Set S1/S0 to "11B"
Clear ISE to "0"
Interrupt sequence
DCT : Data counter
IOA : I/O register address pointer
BAP : Buffer address pointer
ISE : EI2OS enable bit in interrupt control register (ICR)
S1,S0: EI2OS status bit in interrupt control register (ICR)
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
Extended Intelligent I/O Service (EI2OS) Procedure
3.6.4
The extended intelligent I/O service (EI2OS) needs to set the system stack area,
extended intelligent I/O service (EI2OS) descriptor, peripheral function, interrupt
control register (ICR) and others.
■ Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-8 shows the procedure for the extended intelligent I/O service (EI2OS).
Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Processing by software
Processing by hardware
Start
Specifying the system stack area
Setting the EI2OS descriptor
Initial
setting
Initial setting of peripheral function
Setting of interrupt
control register (ICR)
Specify the operation start
interrupt enable bit for
the built-in resource
Set ILM and I in PS
Run the user program
S1,S0 = 00B
(Interrupt request) and (ISE=1)
Data transfer
Determining whether interrupt
NO
branching was performed because
of count-out or because of a completion request from the resource
(Branch to interrupt vector)
Resetting the extended
intelligent I/O service
(such as channel switching)
YES
S1,S0 = 01B or
S1,S0 = 11B
Processing buffer data
RETI
ISE : EI2OS enable bit in interrupt control register (ICR)
S1,S0: EI2OS status bits in interrupt control register (ICR)
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
3.6.5
Extended Intelligent I/O Service (EI2OS)
Processing Time
The time required for processing the extended intelligent I/O service (EI2OS)
varies depending on the following factors:
• Setting of EI2OS status register (ISCS)
• Address (area) indicated by I/O register address pointer (IOA)
• Address (area) indicated by buffer address pointer (BAP)
• Bus width of external data bus for external access
• Data length of data to be transferred
At the end of data transfer by EI2OS, the interrupt handling time is added to the
total time for processing, because a hardware interrupt occurs.
■ Processing Time for Extended Intelligent I/O Service (EI2OS) (Time
Consumed per Transfer)
● When data transfer continues
The EI2OS process time required for data transfer is shown in Table 3.6-2 based on the setting
of the EI2OS status register (ISCS).
Table 3.6-2 Execution Time for Extended Intelligent I/O Service
Setting of EI2OS completion control bit (SE)
Completion by completion request
from peripherals
Setting of the IF bit indicating
whether IOA can be updated or is fixed
Setting of the BF bit indicating
whether BAP address can be updated
or is fixed
Ignoring completion requests
from peripherals
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Unit: Machine cycle (1 machine cycle corresponds to one clock interval of the machine clock (φ))
As shown in Table 3.6-3, settings must be corrected depending on the conditions under which
EI2OS is executed.
Table 3.6-3 Correction Values for Data Transfer during EI2OS Execution
Internal access
I/O register address pointer
Internal access
Buffer address pointer
External access
External access
B/Even
Odd
B/Even
8/Odd
B/Even
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/Even
+1
+3
+2
+5
8/Odd
+4
+6
+5
+8
B:
Byte data transfer
8:
External bus width for 8-bit, word transfer
Even: Even address, word transfer
Odd: Odd address, word transfer
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CHAPTER 3 INTERRUPT
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
MB90930 Series
● When the data counter (DCT) stops counting (after the final data transfer is completed)
When data transfer by EI2OS is completed, the interrupt handling time is added to the total
processing time, since a hardware interrupt is generated. The EI2OS processing time required
when counting ends can be obtained from the following formula.
EI2OS processing time when counting ends =
EI2OS processing time by the end of data transfer + (21+6×Z) machine cycles
↑
Interrupt handling time
One machine cycle corresponds to one clock cycle of the machine clock (φ).
The interrupt handling time varies depending on the address indicated by the stack pointer.
Table 3.6-4 shows the applicable correction values (Z) for the interrupt handling time.
Table 3.6-4 Correction Values (Z) for Interrupt Handling Time
Address indicated by the stack pointer
External, 8-bit
Correction value (Z)
+4
External, even-numbered address
+1
External, odd-numbered address
+4
Internal, even-numbered address
0
Internal, odd-numbered address
+2
● When data transfer is ended by completion request from the peripheral function (I/O)
If EI2OS data transfer is not fully completed (ICR: S1, S0 = 11B) due to the completion request
received from the peripheral function (I/O), data transfer is not executed and a hardware
interrupt is generated.
The EI2OS processing time can in this case be obtained from the formula shown below. The
parameter Z in the formula represents a correction value for the interrupt handling time (see
Table 3.6-4).
EI2OS processing time until the transfer ended : 36 + 6 × Z machine cycles
One machine cycle corresponds to one clock cycle of the machine clock (φ).
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CHAPTER 3 INTERRUPT
3.7 Exception Handling Interrupt by Execution of Undefined
Instruction
MB90930 Series
3.7
Exception Handling Interrupt by Execution of
Undefined Instruction
F2MC-16LX handles exception handling by undefined instructions. Exception
handling is basically performed in the same way as interrupt handling, i.e., the
normal flow of processing is interrupted for starting exception handling if an
exception event is detected at the instruction boundary.
In general, exception handling is performed when an unexpected operation is
executed. Therefore, it should only be used for debugging or by recovery
software for emergency use.
■ Exception Handling Interrupt by Execution of Undefined Instruction
● Exception handling operation
F2MC-16LX counts any code that is not defined in the instruction map as an undefined
instruction. If undefined instructions are executed, the same processing as for a software
interrupt instruction such as "INT # 10" is performed.
For except handling, the following processing is performed before branching to the interrupt
routine.
• The contents of the A, DPR, ADB, DTB, PCB, PC, and PS registers are saved to the system
stack.
• The I flag of the condition code register (CCR) is cleared to "0", masking hardware
interrupts.
• The S flag of the condition code register (CCR) is set to "1", enabling the use of the system
stack.
The program counter (PC) value saved to the stack represents the address under which the
undefined instruction is stored. In other words, the address at which an instruction code of 2
bytes or more is stored which has been identified as "undefined". If the type of the exception
cause needs to be identified in the exception handling routine, use this PC value.
● Return from exception handling
After returning from exception handling with the RETI instruction, exception handling will
start again, since the PC points to an undefined instruction. Take appropriate action, for
example, reset a software.
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CHAPTER 3 INTERRUPT
3.8 Stack Operations of Interrupt Handling
MB90930 Series
Stack Operations of Interrupt Handling
3.8
If an interrupt is accepted, the content of the dedicated register is automatically
saved to the system stack before processing branches to interrupt handling.
Return from the stack is also automatically performed after interrupt handling
is completed.
■ Stack Operation when Interrupt Handling Starts
When an interrupt is accepted, the CPU automatically saves the current contents of the
dedicated registers to the system stack, in the following order:
1) Accumulator (A)
2) Direct page register (DPR)
3) Additional data bank register (ADB)
4) Data bank register (DTB)
5) Program counter bank register (PCB)
6) Program counter (PC)
7) Processor status register (PS)
Figure 3.8-1 shows stack operation at the beginning of interrupt handling.
Figure 3.8-1 Stack Operation when Interrupt Processing Starts
Immediately
before interrupt
SSB
Address
00H
08FEH
A
0000H
08FEH
AH
AL
DPR 01H
ADB 00H
DTB
PCB FFH
PC
803FH
PS
20E0H
SSB
08FFH
08FEH
SSP
00H
Immediately
after interrupt
Memory
08F2H
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
H
L
SP
Address
00H
08FFH
08FEH
SSP
08F2H
A
0000H
08FEH
AH
AL
DPR 01H
ADB 00H
DTB
PCB FFH
00H
PC
803FH
PS
20E0H
Memory
Byte
08F2H
00H
00H
08H
FEH
01H
00H
00H
FFH
80H
3FH
20H
E0H
Byte
SP
AH
AL
DPR
ADB
DTB
PCB
PC
PS
SP after
updated
■ Stack Operation after Return from Interrupt Handling
When the interrupt return instruction (RETI) is executed at the end of interrupt handling, the
values of PS, PC, PCB, DTB, ADB, DPR, and A are returned from the stack in the reverse
order at the start of interrupt handling. This will restore the dedicated registers to their states
immediately before the interrupt started.
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CHAPTER 3 INTERRUPT
3.8 Stack Operations of Interrupt Handling
MB90930 Series
■ Stack Area
● Allocation of the stack area
The stack area is used for saving/returning the program counter (PC) as required for executing
subroutine call instructions (CALL) and vector call instructions (CALLV) in addition to
interrupt handling. Moreover, it is used for temporarily saving/ returning the contents of
registers by PUSHW and POPW instructions. The stack area is allocated in RAM in addition to
the data area.
Figure 3.8-2 shows the allocation of the stack area.
Figure 3.8-2 Stack Area
Vector table
(Reset/interrupt
vector call instructions)
FFFFFFH
FFFC00H
ROM area
FF0000 H*1
~
~
~
~
000D00H *2
Built-in RAM area
Stack area
000380 H
000180 H
General-purpose
register
bank area
000100 H
0000C0H
000000 H
Built-in I/O area
*1: Built-in ROM capacity depends on product type.
*2: Built-in RAM capacity depends on product type.
Notes:
• In o rdinary cases, u se even addresses f or setting t he addresses of st ack p ointers
(SSP, USP).
• Avoid overlapped allocation of the system stack area, user stack area, and data area.
● System stack and user stack
For interrupt handling, the system stack area is used. Even if the user stack area is being used
when an interrupt occurs, processing forcibly switches to the system stack. Thus, the system
stack area must also be correctly prepared in a system where mainly the user stack area is used.
Unless it is necessary to separate the available free stack space, use only the system stack.
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CHAPTER 3 INTERRUPT
3.9 Example Program for Interrupt Handling
3.9
MB90930 Series
Example Program for Interrupt Handling
An example program for interrupt handling is shown below.
■ Example Program for Interrupt Handling
This is an example of an interrupt handling program that uses the external interrupt 0 (INT0)
instruction.
A coding example of the program is as follows.
[Coding example]
DDR5
ENIR
EIRR
ELVRL
ICR02
STACK
EQU
000015H
; Port 5 direction register
EQU
000030H
; DTP/interrupt enable register
EQU
000031H
; DTP/interrupt source register
EQU
000032H
; Request level setting resister
EQU
0000B2H
; Interrupt control register 02
SSEG
; Stack
RW
100
STACK_TRW
1
STACK ENDS
;----------Main program---------------------------------------CODE
CSEG
START:
MOV
RP, #0
; General-purpose register uses
; heading
; bank
MOV
ILM, #07H
; Set ILM in PS to level 7
MOV
A, #!STACK_T
; System stack setting
MOV
SSB, A
MOVW A, #STACK_T
; Stack pointer setting.
; Because the SMOVW
SP, A
; flag is 1, the stack pointer is
; set to SSP
MOV
DDR5, #00000000B
; Set P50/INT0 pin to input
AND
CCR, #0E0H
; Clear bit0 to bit4 of CCR in PS
OR
CCR, #40H
; Set I-flag in CCR in PS to
; enable
; interrupts
MOV
I:ICR02, #00H
; Set interrupt level to 0
; (highest)
MOV
I:ELVR, #00000001B ; Specify INT0 to be "H"-level
; request
MOV
I:EIRR, #00H
; Clear INT0 interrupt source
MOV
I:ENIR, #01H
; Enable INT0 input
:
LOOP: NOP
; Dummy loop
NOP
NOP
NOP
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CM44-10150-1E
MB90930 Series
CHAPTER 3 INTERRUPT
3.9 Example Program for Interrupt Handling
BRA
LOOP
; Unconditional jump
;----------Interrupt program----------------------------------ED_INT1:
MOV
I:EIRR, #00H
; Prohibit acceptance of new
; INT0
NOP
NOP
NOP
NOP
NOP
NOP
RETI
; Return from interrupt
CODE
ENDS
;----------Vector setting-------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFBCH
; Specify a vector for interrupt
; #16(10H)
DSL
ED_INT1
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
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CHAPTER 3 INTERRUPT
3.9 Example Program for Interrupt Handling
MB90930 Series
■ Specification of Processing for Sample Program of Extended Intelligent I/O
Service (EI2OS)
1) If "H" level is detected for the signal input to the INT0 pin, the extended intelligent I/O
service (EI2OS) will start.
2) If the INT0 pin enters "H" level, EI2OS starts and transfers the data in port 0 to the memory
at address "3000H".
3) After the transfer of 100-byte data is completed, an interrupt is generated due to the end of
EI2OS transfer.
A coding example of the program is as follows.
[Coding example]
BAPL
.SECTION
.ORG
.RES.B
.ORG
.RES.B
.RES.B
.RES.B
.ORG
.RES.B
.ORG
.RES.B
BAPM
.RES.B
BAPH
.RES.B
ISCS
IOAL
.RES.B
.RES.B
01H
01H
IOAH
.RES.B
01H
DCTL
DCTH
.RES.B
.RES.B
01H
01H
DDR5
ENIR
EIRR
ELVR
ICR02
.SECTION
.RES.B
STACKT .RES.B
;----------Main
.SECTION
START:
AND
MOV
MOV
MOV
MOVW
100
IO,IO, LOCATE=0x000000
0015H
01H
; Port 5 direction register
0030H
01H
; DTP/Interrupt enable register
01H
; DTP/Interrupt source register
01H
; Request level setting register
00B2H
01H
; Interrupt control register 02
0100H
01H
; Lower byte of buffer address
; pointer
01H
; Middle byte of buffer address
; pointer
01H
; Upper byte of buffer address
; pointer
;
;
;
;
;
;
;
EI2OS status
Lower byte of
pointer
Upper byte of
pointer
Lower byte of
Upper byte of
I/O address
I/O address
data counter
data counter
STACK,STACK ; Stack
0FEH
01H
program---------------------------------------PROG,CODE
CCR, #0BFH
; Clear the I-flag in CCR in PS to
; disable interrupts
RP, #00
; Set the register bank pointer
A, #bnksym STACKT
; Specify the system stack
SSB, A
A, #STACKT
; Set the stack pointer.
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CHAPTER 3 INTERRUPT
3.9 Example Program for Interrupt Handling
MB90930 Series
MOVW
MOV
MOV
MOV
MOV
MOV
SP, A
; In this case, SSP is set,
; because the
; S-flag is set to "1".
I:DDR5, #00000000B
; Set the P50/INT0 pin to "input"
BAPL, #00H
; Set the buffer address to 003000H
BAPM, #30H
BAPH, #00H
ISCS, #00010001B
; I/O addresses not updated, but
; byte
; transfer and buffer address
; updated
; Transferred from I/O to buffer,
; completed by peripheral function
; (resource)
IOAL, #00H
; Set the transfer source address
; (Port0:000000H)
MOV
MOV
MOV
IOAH, #00H
DCTL, #064H
MOV
MOV
DCTH,
#00H
I:ICR02, #00001000B
; Set the transfer byte count
; (100 bytes)
; EI2OS channel 0, EI2OS enabled
; Interrupt level 0 (highest level)
I:ELVR, #00000001B
; Specify INT0 to be "H"-level
; request.
I:EIRR, #00H ; Clear INT0 interrupt source
I:ENIR, #01H ; INT0 interrupt enabled
ILM, #07H
; Set ILM in PS to level 7.
CCR, #0E0H
; Clear bit0 to bit4 of CCR in PS.
CCR,
#040H ; Set the I-flag in CCR in PS to
; enable interrupts
MOV
MOV
MOV
MOV
AND
OR
:
LOOP: BRA
LOOP ; Infinite loop
;----------Interrupt program----------------------------------WARI
CLRB
EIRR:0
; DTP/interrupt request flag
; cleared
:
User processing
:
; Checking EI2OS completion source,
; processing of data in the
; buffer, EI2OS
; reset, etc.
RETI
;----------Vector setting-------------------------------------.SECTION VECT,CODE, LOCATE=0xFFFF54
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CHAPTER 3 INTERRUPT
3.9 Example Program for Interrupt Handling
102
MB90930 Series
.ORG
0FFFFBCH
; Set vector to interrupt #16(10H)
.DATA.E
.ORG
.DATA.E
.DATA.B
WARI
0FFFFDCH
START
00H
; Reset vector setting
;
; Mode data setting
END
START
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 4
RESET
This chapter describes the reset operation.
4.1 Outline of Reset
4.2 Reset Sources and Oscillation Stabilization Wait Time
4.3 External Reset Pin
4.4 Reset Operation
4.5 Reset Source Bit
4.6 State of Each Pin by Reset
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CHAPTER 4 RESET
4.1 Outline of Reset
4.1
MB90930 Series
Outline of Reset
If a reset source occurs, the CPU immediately suspends the processing
currently being executed and enters the reset clear wait state. After the reset is
cleared, processing starts at the address indicated by the reset vector.
There are six reset sources:
• Power-on reset
• External reset request from RST pin
• Software reset request
• Watchdog timer overflow
• Lower power voltage detected
• Counter overflow of CPU operation detection function
■ Reset Sources
The reset sources are shown in Table 4.1-1.
Table 4.1-1 Reset Sources
Reset
Source
Machine clock
Status of
Watchdog
timer
CPU
Oscillation
operation stabilization
detection
wait
Power-on
System powered on
Main clock
(MCLK)
Stopped
Stopped
Yes
External pin
"L" level input to RST pin
Main Clock
(MCLK)
Stopped
Stopped
No
Software
Set the internal reset signal
generation bit (RST) in the lowpower consumption mode control
register (LPMCR) to "0".
Main clock
(MCLK)
Stopped
Stopped
No
Watchdog
timer
Watchdog timer overflow
Main clock
(MCLK)
Stopped
Stopped
No
Low-voltage
Low-voltage of power supply
detection reset detected (4.0 ± 0.3V)
Main clock
(MCLK)
Stopped
Stopped
No
CPU operation
Counter overflow of CPU operation
detection
detection function
function
Main clock
(MCLK)
Stopped
Stopped
No
MCLK: Main clock (divide-by-2 clock of oscillation clock)
● Power-on reset
Power-on reset is a reset that occurs when the power is turned on. The oscillation stabilization
wait time is fixed to 216 oscillation clock cycles (216/HCLK). When the oscillation stabilization
wait time has elapsed, the reset is executed.
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CHAPTER 4 RESET
4.1 Outline of Reset
MB90930 Series
● External reset
External reset is a reset that occurs when "L" level is input to the external reset pin (RST pin).
The required time period for "L" level input to RST pin is 16 machine cycles (16/φ) or more.
For an external reset, no oscillation stabilization wait time applies.
Note:
Only if the RST pin generates a reset request, when a reset source occurs during a write
operation (while a transfer type instruction such as MOV is e xecuted), the system enters
reset clear wait state after the end of the instruction. This ensures that the write operation
completes normally when a reset occurs during the write operation.
However, st ring t ype in struction (such as M OVS) accepts r esets b efore t he t ransfer f or
the specified counter is c ompleted. For this reason, it cannot be assured that all data will
be transferred in this case.
● Software resets
In a software reset, an internal reset is performed if the internal reset signal generation bit
(RST) in the low-power consumption mode control register (LPMCR) is cleared to "0". The
oscillation stabilization wait time does not apply for software resets.
● Watchdog resets
In a watchdog reset, a reset is performed when the watchdog timer overflows, if the watchdog
control bit (WTE) in the watchdog timer control register (WDTC) is not cleared to "0" within
the specified time after starting the watchdog timer. The oscillation stabilization wait time does
not apply for watchdog resets.
● Low-voltage detection resets
In a low-voltage detection reset, a reset occurs if the voltage of the power supply is lower than
specified.
For 4.0V detection voltage, no oscillation stabilization wait time applies.
This function is always available once the power is turned on.
● CPU operation detection resets
In CPU operation detection resets, a reset is performed when the CPU operation detection
function counter overflows, if the CPU operation detection circuit clear bit (CL) in the lowvoltage/CPU operation detection reset control register (LVRC) is not cleared to "0" within the
specified time after power-on. This function always works after the power turned on.
Definitions of the clock:
HCLK
MCLK
φ
1/φ
: Oscillation clock frequency
: Main clock frequency
: Machine clock frequency (CPU operation clock)
: Machine cycle (CPU operation clock cycle)
Refer to Section "5.1 Clock" for details.
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CHAPTER 4 RESET
4.1 Outline of Reset
MB90930 Series
Note:
If a re set is ge nerated in s top m ode, ( 216/HCLK (about 16.39 ms when using
HCLK=4MHz) is used as the oscillation stabilization wait time.
an os cillator of
Refer to Section "5.1 Clock" for details.
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CHAPTER 4 RESET
4.2 Reset Sources and Oscillation Stabilization Wait Time
MB90930 Series
4.2
Reset Sources and Oscillation Stabilization Wait Time
The MB90930 series has 6 types of reset sources. The oscillation stabilization wait time
at reset depends on the reset source.
■ Reset Sources and Oscillation Stabilization Wait Time
Table 4.2-1 shows the reset sources and oscillation stabilization wait time.
Table 4.2-1 Reset Sources and Oscillation Stabilization Wait Time
Reset
Oscillation stabilization wait time
( ): for an oscillation clock frequency of 4 MHz
Reset source
Power-on
System powered on
213/HCLK (approx. 2.05ms) + 216/HCLK (approx. 16.39ms) =
approx. 18.44ms
Note:
213/HCLK (approx. 2.05ms) is the stabilization time of the stepdown circuit.
Watchdog
Watchdog timer overflow
Not used; WS1 and WS0 bit are initialized to "11B".
External
"L" input from RST pin
Not used; WS1 and WS0 bits are initialized to "11B" however.
Low-voltage
detection reset
Low-voltage of power supply
detected (4.0±0.3V)
Not used: WS1 and WS0 bits initialized to "11B"
CPU operation
detection
CPU operation detection timer
overflow
Not used; WS1 and WS0 bits are initialized to "11B" however.
Software
RST bit in the low-power
consumption mode control register
(LPMCR) set to "0"
Not used; WS1 and WS0 bits are initialized to "11B" however.
HCLK
: Oscillation clock frequency
WS1, WS0 : Oscillation stabilization wait time selection bit in the clock selection register (CKSCR)
Figure 4.2-1 shows the oscillation stabilization wait time when a power-on reset occurs.
Figure 4.2-1 Oscillation Stabilization Wait Time for Power-on Reset
VCC
213/HCLK
216/HCLK
CLK
CPU operation
Stabilization
wait time of
step-down circuit
Oscillation
stabilization
wait time
HCLK: Oscillation clock frequency
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CHAPTER 4 RESET
4.2 Reset Sources and Oscillation Stabilization Wait Time
MB90930 Series
Table 4.2-2 Oscillation Stabilization Wait Time Depending on Clock Selection Register (CKSCR)
Settings
WS1
WS0
0
0
215/HCLK (approx. 8.19ms)
0
1
213/HCLK (approx. 2.05ms)
1
0
214/HCLK (approx. 4.10ms)
1
216/HCLK (approx. 16.39ms) (other than power-on reset)
213/HCLK (approx. 2.05ms) + 216/HCLK (approx. 16.39ms)= approx. 18.44ms
(at power-on reset)
1
Oscillation stabilization wait time ( ): for an oscillation clock frequency of 4MHz
HCLK: Oscillation clock frequency
Note:
Ceramic and crystal res onators generally need the o scillation stabilization wait time of
several ms to a dozen ms or so from the starting of the o scillation until the stabilization to
the natural frequency. Therefore, set an appropriate value for the resonator used. Refer
to Section "5.1 Clock" for details.
■ Oscillation Stabilization Wait Reset State
The reset operation for the power-on reset and the reset in stop mode will be performed after
the oscillation stabilization wait time set by the time-base timer has elapsed. If, in this case, the
external reset input is not cleared, the reset operation will be performed after the external reset
is released.
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4.3 External Reset Pin
MB90930 Series
4.3
External Reset Pin
The external reset pin (RST pin) is a reset-input dedicated pin which generates
an internal reset if "L" level is input. The MB90930 series starts reset
operations in synchronization with CPU operation clock, however, only resets
through external pins are performed asynchronously.
■ Block Diagram of External Reset Pin
Figure 4.3-1 Block Diagram for Internal Reset
RST
CPU operation clock
(PLL multiplication circuit,
divide-by-2 of HCLK)
P-ch
Pin
N-ch
Input buffer
Synchronization circuit
Clock synchronization
Internal reset signal
HCLK: Oscillation clock
Note:
Inputs to the RST pin are accepted during cycles in which memory is not affected in order
to prevent memory from being destroyed by a reset during a write operation.
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CHAPTER 4 RESET
4.4 Reset Operation
4.4
MB90930 Series
Reset Operation
If a reset is released, the target for reading mode data and the reset vector is
selected based on the setting of the mode pins, and a mode fetch is performed.
With this mode fetch operation, the CPU operation mode and the execution
start address after the reset operation is completed are determined. At poweron, as well as at return from stop mode by reset, mode fetch is performed after
the oscillation stabilization wait time has elapsed.
■ Outline of Reset Operation
Figure 4.4-1 shows the operation flow for reset.
Figure 4.4-1 Operation Flow for Reset
Power-on reset
Stop mode
Low-voltage detection reset
External reset
Software reset
Watchdog timer reset
CPU operation detection reset
Reset mode
Mode fetch
(Reset operation)
Oscillation stabilization
wait reset state
Fetch the mode data
Fetch the reset vector
Normal operation
(RUN state)
Obtain instruction code from
address indicated by reset
vector and execute instruction
■ Mode Pins
The mode pins (MD2 to MD0) specify how to fetch the reset vector and mode data. Reset
vector and mode data are read during the reset sequence. For further information about mode
pins, see Section "7.2 Mode Pins (MD2 to MD0)".
■ Mode Fetch
If a reset is released, the CPU performs a hardware-based transfer of the reset vector and mode
data to the relevant register inside the CPU core. Reset vector and mode data are allocated in a
4-byte area at the addresses "FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to
the bus immediately after the reset is released to fetch the reset vector and mode data. With this
mode fetch operation, the CPU starts processing from the address indicated by the reset vector.
Figure 4.4-2 shows the transfer of reset vector and mode data.
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4.4 Reset Operation
MB90930 Series
Figure 4.4-2 Transfer of Reset Vector and Mode Data
Memory space
FFFFDFH
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDDH
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
F2MC-16LX CPU core
Mode
register
Micro ROM
Reset sequence
PCB
PC
● Mode data (Address: FFFFDFH)
The mode register setting can be changed only by a reset operation, and the setting becomes
effective after the reset operation. For further information about mode data, see Section "7.3
Mode Data".
● Reset vector (Address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation is written to this area. Execution will start
from the address in this vector.
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CHAPTER 4 RESET
4.5 Reset Source Bit
4.5
MB90930 Series
Reset Source Bit
The source for reset generation can be identified by reading the watchdog
timer control register (WDTC) and the low-voltage/CPU operation detection
reset control register (LVRC).
■ Reset Source Bit
Each reset source has the corresponding flip flop as shown in Figure 4.5-1. These contents can
be obtained by reading the watchdog timer control register (WDTC). If, after the reset is
released, the reset source must be identified, process the read value of the watchdog timer
control register (WDTC) with software and branch to the appropriate program.
Figure 4.5-1 Block Diagram of Reset Source Bit
Not cleared
regularly
Power supply
voltage lowered
CPU operation
detection
reset request
detection circuit
RST pin
Power-on
Low-voltage
detection
circuit
Not cleared
regularly
RST=L
LPMCR : RST
bit write
detection
circuit
Watchdog
timer reset
detection
circuit
External reset
request
detection
circuit
Power-on
detection
circuit
RST bit set
Clear
Watchdog timer
control register
(WDTC)
S
R
S
R
Q
S
F/F
F/F
Q
R
S
F/F
Q
R
F/F
Q
Delay
circuit
Read the watchdog
timer control
register (WDTC)
Internal data bus
S
R
Q
F/F
112
:
:
:
:
Set
R eset
O ut put
Flip Flop
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4.5 Reset Source Bit
MB90930 Series
■ Correspondence between Reset Source Bit and Reset Source
The configuration of reset source bits in the watchdog timer control register (WDTC) is shown
in Figure 4.5-2, and the correspondence between the contents of reset source bits and reset
sources is shown in Table 4.5-1. For further information, see Section "9.3.1 Watchdog Timer
Control Register (WDTC)".
Figure 4.5-2 Configuration of Reset Source Bits (Watchdog Timer Control Register)
Watchdog Timer Control Register (WDTC)
Address
bit15 .....................bit8 bit7
0000A8H
(TBTC)
bit6
PONR
-
R
-
bit5
bit4
bit3
bit2
WRST ERST SRST WTE
R
R
R
bit1
bit0
Initial value
WT1
WT0
X-XXX111B
W
W
W
R : Read only
W : Write only
X : Undefined value
Table 4.5-1 Correspondence between the Contents of Reset Source Bits and Reset Source
Reset source
PONR
WRST
ERST
SRST
Power-on reset request generated
1
X
X
X
Reset request generated due to watchdog timer overflow
Y
1
Y
Y
External reset requested by RST pin
Low-voltage detection (4.0V) reset request generated (*1)
CPU operation detection reset request generated (*2)
Y
Y
1
Y
Software reset request generated
Y
Y
Y
1
Y: Retains the previous state
X: unspecified
*1: If a low-voltage detection reset request is generated, the LVRF bit in the low-voltage/CPU operation
detection reset control register (LVRC) is set to "1".
*2: If a CPU operation detection reset request is generated, the CPUF bit in the low-voltage/CPU operation
detection reset control register (LVRC) is set to "1".
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CHAPTER 4 RESET
4.5 Reset Source Bit
MB90930 Series
■ State of Reset Source Bits
Figure 4.5-3 State of Reset Source Bits
(1)
State of flag
at power-on
(2)
Bit clearing
(3)
State of flag at low-voltage
detection (4.0V)
(4)
Bit clearing
(5)
State of flag at low-voltage
detection (1.4V)
(1)
(2)
(3)
(4)
(5)
1
0
0
0
1
ERST bit
(External reset input,
CPU operation detection, or
LVRF=1)
1 or 0
0
1
0
1
LVRF bit *
(Low voltage detection,
4V ± 0.3V)
1 or 0
0
1
0
1
VCC=4.0V
VCC=1.4V
VCC
PONR bit
(Power-on=1 or RAMF=1)
* : The LVRF bit is in the low voltage and CPU operation detection reset control register (LVRC 6EH).
(1) At power-on:
When power is turned on, the power-on reset bit (PONR), ERST, and LVRF bits are set to "1".
However, if power is turned on without an ordinary startup, ERST, and LVRF bits may be set to "0".
(2) Bit clearing (Clearing bits by reading the WDTC register and writing "0" to LVRF)
(3) At low-voltage detection (4V ± 0.3V) :
If low-voltage (VCC = 4V ± 0.3V) is detected, the LVRF and ERST bits are set to "1".
(4) Bit clearing (Clearing bits by reading the WDTC register and writing "0" to LVRF)
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4.5 Reset Source Bit
MB90930 Series
■ Notes on the Reset Source Bit
● When multiple reset sources occur
When multiple reset sources occur, the corresponding reset source bits in the watchdog timer
control register (WDTC) are set to "1". For example, if an external reset request from the RST
pin and overflow of the watchdog timer occur at the same time, the ERST and WRST bits are
both set to "1".
● Clearing the reset source bit
The reset source bit is cleared only if the watchdog timer control register (WDTC) is read out.
A flag that is set to the corresponding reset source bit will not be cleared and will remain set to
"1" even if other reset sources cause a reset thereafter.
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CHAPTER 4 RESET
4.6 State of Each Pin by Reset
4.6
MB90930 Series
State of Each Pin by Reset
This section describes the state of each pin by reset.
■ State of Pins During Reset
The state of a pin during reset is determined by the setting of the mode pins (MD2 to
MD0=011B).
For the state of each pin during reset, see Section "6.7 Pin State in the Standby Mode and at
the Time of Reset".
● Setting internal vector mode
I/O pins (peripheral function pins) are all set to high impedance and internal ROM becomes the
target for reading the mode data.
■ State of Pin After Reading the Mode Data
The state of a pin after the mode data is read out is determined by the mode data (M1,
M0=00B).
● If single-chip mode is selected (M1, M0=00B)
I/O pins (peripheral function pins) are all set to high impedance and internal ROM becomes the
target for reading the mode data.
Note:
Make sure that, if a pin is set to high impedance because a reset source is occurred, this
does not cause incorrect operation of devices connected to the pin.
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CHAPTER 5
CLOCK
This chapter describes the clock.
5.1 Clock
5.2 Block Diagram of the Clock Generation Block
5.3 Clock Selection Register (CKSCR)
5.4 PLL/Sub clock Control Register (PSCCR)
5.5 Clock Mode
5.6 Oscillation Stabilization Wait Time
5.7 Connection of Oscillator and External Clock
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CHAPTER 5 CLOCK
5.1 Clock
5.1
MB90930 Series
Clock
The clock generation block controls the operation of the internal clock that
controls operation of the CPU and peripheral functions. The clock generated by
the clock generation block is called the machine clock. One cycle of machine
clock is called one machine cycle. The 2-frequency division of the oscillation
clock is called a main clock. The 4- or 2-frequency division of the clock
supplied from a low-speed oscillator is called a sub clock, and the clock by the
PLL oscillation is called PLL clock.
■ Clock
The clock generation block contains the oscillation circuit that generates the oscillation clock
with connecting the oscillator to the oscillation pin. The oscillation clock can also be supplied
with inputting an external clock to the oscillation pin. The clock generation block also contains
the PLL clock multiplier circuit, which can generate six clocks whose frequencies are
multiplication of the oscillation clock frequency. The clock generation block controls the
oscillation stabilization wait time and PLL clock multiplication, and performs switching
operation of the internal clock with the clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either with connecting the oscillator to high-speed oscillation
pins (X0 and X1).
● Main clock (MCLK)
The clock has the divided-by-two frequency of the oscillation clock. It supplies the input clock
to the time-base timer and clock selector.
● Sub clock (SCLK))
The sub clock is generated with dividing the clock, which was generated with connecting an
oscillator to the low-speed oscillation pins (X0A and X1A) or with inputting an external clock,
by 4 or 2. The division ratio of the sub clock is set with SCDS bit in the PLL/sub clock control
register (PSCCR). This clock can be used as the operating clock in the watch timer or the lowspeed machine clock.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock with the PLL clock multiplier
circuit (PLL oscillation circuit). Depending on the multiplication rate selection bits (CKSCR:
CS1 and CS0, PSCCR: CS2), one of 6 types of clocks can be selected.
● Machine clock
This is the operating clock for the CPU and peripheral functions. One cycle of the machine
clock is defined as a machine cycle (1/φ). The machine clock can be selected among any of the
main clock, sub clock 6 types of PLL clocks.
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5.1 Clock
MB90930 Series
Note:
When the oper ating voltage is 5V , an oscillation cloc k of 3 MH z to 16 MHz can be
generated. The maximum operating frequency for the CPU and peripheral functions is 32
MHz. Th erefore, if the multiplier r ate t hat e xceeds t he ma ximum o perating f requency is
set, devices will not operate correctly. Although the P LL oscillation operates at the r ange
of 4 MHz to 32 MH z, the PLL oscillation range depends on the operating v oltage and
multiplication rate. Refer to "Data sheet" for details.
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CHAPTER 5 CLOCK
5.1 Clock
MB90930 Series
■ Clock Supply Map
Machine clock generated in the clock generation block is supplied as the operating clock for
the CPU and peripheral functions. The operation of CPU and peripheral functions are affected
by switching (clock mode) between a main clock and sub clock/ PLL clock and by a change in
the PLL clock multiplication rate. Since some peripheral functions receive divided output from
a time-base timer, a peripheral can select a operating clock.
Figure 5.1-1 shows the clock supply map.
Figure 5.1-1 Clock Supply Map
Peripheral function
4
Watch timer
4
Watchdog
timer
8/16-bit
PPG timer 0 to 5
Clock generation block
1
X1A*2
Pin
X0
Pin
X1
Pin
3
4
6
8
8/16-bit
reload timer 0 to 3
PLL multiplier circuit
PCLK (PLL clock)
X0A*1
Pin
2
Clock
generation
circuit
Clock selector
4/2-divided
CAN1
φc
Clock modulator
A/D converter (24ch)
(Sub clock)
Clock
generation
HCLK
circuit
SCLK
2-divided
(Oscillation clock)
Pin TIN0 to TIN3
Pin TOT0 to TOT3
Pin RX1
Pin TX1
Pin AN0 to AN23
Real-time watch timer
Clock selector
MCLK
(Main clock)
Pin PPG0 to PPG5
Pin SCK0 to SCK3
φ
UART0 to UART3
(Machine clock)
Pin SIN0 to SIN3
Pin SOT0 to SOT3
I/O timer
Free-run timer
CPU
Input capture
0 to 7
Pin IN0 to IN7
Pin IN2R to IN7R
Pin PWM1P0 to PWM1P3
SMC0 to SMC3
Pin PWM1M0 to PWM1M3
Pin PWM2P0 to PWM2P3
Pin PWM2M0 to PWM2M3
HCLK : Oscillation clock
MCLK : Main clock
PCLK : PLL clock
φ
: Machine clock
φc
: CAN1 clock
*1
: X0A pin is optional (dual clock products only).
*2
: X1A pin is optional (dual clock products only).
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4
Oscillation stabilization
Wait Control
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CHAPTER 5 CLOCK
5.2 Block Diagram of the Clock Generation Block
MB90930 Series
5.2
Block Diagram of the Clock Generation Block
The clock generation block consists of the following blocks:
• Oscillation clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• PLL/Sub clock control register (PSCCR)
• Oscillation stabilization wait time selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block. The standby control circuit
and time-base timer circuit are included also.
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
RST Pin
CPU intermittent
operation cycle
selector
Reset (release)
Pin Hi-Z control
Internal reset
generation
circuit
Internal reset
Intermitted cycle selected
CPU clock
control circuit
CPU operating
clock
Watch, sleep, and stop signals
Standby
control circuit
2
Watch and stop signals
Interrupt (release)
Peripheral
clock
control circuit
Peripheral functions
operating clock
Sub clock oscillation stabilization wait release
Main clock oscillation stabilization wait release
Clock generation
block
Operating clock
selector
Machine
clock
2
CS2
PLL/sub clock
control register
(PSCCR): bit8
Oscillation
stabilization
wait time selector
2
PLL multiplier
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
2divided
Oscillation clock
(HCLK)
X0 Pin
X1 Pin
Oscillation clock
oscillation circuit
X0A*1 Pin
X1A*2 Pin
Pin high
impedance
control circuit
Sub clock
(SCLK)
4-divided/
2-divided
Main
clock
4divided
512divided
2divided
2divided
Time-base timer
1024divided
2divided
2divided
2divided
4divided
To watchdog timer
8divided
2divided
2divided
Watch timer
Sub clock
oscillation
circuit
SCDS
PLL/sub clock
control register
(PSCCR): bit10
*1: X0A pin is optional (dual clock products only).
*2: X1A pin is optional (dual clock products only).
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CHAPTER 5 CLOCK
5.2 Block Diagram of the Clock Generation Block
MB90930 Series
● Oscillation clock generation circuit
The oscillation clock (HCLK) is generated with connecting the oscillator to high speed
oscillation pins (X0 and X1).
● Sub clock generation circuit
The sub clock (SCLK) is generated either with connecting the low speed oscillator to
oscillation pins (X0A and X1A) or with inputting an external clock.
X0A pin and X1A pin are optional pins (dual clock products only).
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock with the PLL oscillation and
supplies the clock as a PLL clock (PCLK) to the clock selector.
● Clock selector
It selects a clock to be supplied to the CPU and peripheral functions among the main clock, the
sub clock and 6 types of PLL clocks.
● Clock selection register (CKSCR)
The clock selection register switches an oscillation clock/PLL clock and main clock/sub clock,
and selects an oscillation stabilization wait time and PLL clock multiplication rate.
● PLL/sub clock control register (PSCCR)
This register selects the PLL clock multiplication rate (selects with the setting of CS0 and CS1
bits in the clock selection register and CS2 bit in this register), and sets the sub clock division
ratio (divide-by-two/divide-by-four).
● Oscillation stabilization wait time selector
This selector selects an oscillation stabilization wait time for the oscillation clock. Selection is
made from among 4 types of time-base timer outputs.
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5.2 Block Diagram of the Clock Generation Block
MB90930 Series
5.2.1
Register in the Clock Generation Block
This section explains the register in the clock generation block.
■ List of the Registers in the Clock Generation Block and Its Initial Values
Figure 5.2-2 lists the clock selection register and its initial values.
Figure 5.2-2 List of Clock Selection Register and Its Initial Values
bit
15
14
13
12
11
10
9
8
Clock selection register (CKSCR)
1
1
1
1
1
1
0
0
PLL clock control register (PSCCR)
-
-
-
-
0
0
0
0
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CHAPTER 5 CLOCK
5.3 Clock Selection Register (CKSCR)
5.3
MB90930 Series
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) switches the main clock, sub clock, and
PLL clock, and selects an oscillation stabilization wait time and PLL clock
multiplication rate.
■ Clock Selection Register (CKSCR)
Figure 5.3-1 Clock Selection Register (CKSCR)
Address
bit 15
0000A1H
14
13
12
11
10
9
8
Initial value
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
11111100B
R
R
R/W R/W R/W R/W R/W R/W
CS2 (PSCCR register: bit8)
bit9
bit8
CS2
CS1
CS0
0
0
0
1 × HCLK
0
0
1
2 × HCLK
0
1
0
3 × HCLK
0
1
1
4 × HCLK
1
1
0
6 × HCLK
1
1
1
8 × HCLK
Multiplication rate selection bits
bit10
MCS
PLL clock selection bit
0
Selects PLL clock.
1
Selects main clock.
bit11
SCS
Sub clock selection bit
0
Selects sub clock.
1
Selects main clock.
bit13 bit12
WS1 WS0
Oscillation stabilization wait time selection bits
The values within ( ) are examples calculated at an
oscillation clock (HCLK) frequency of 4 MHz.
0
0
215/HCLK (approx. 8.19ms)
0
1
213/HCLK (approx. 2.05ms)
1
0
214/HCLK (approx. 4.10ms)
1
1
216/HCLK
(approx. 16.38ms, other than power-on reset)
216/HCLK + 213/HCLK
(approx. 18.44ms, power-on reset only)
bit14
MCM
HCLK
R/W
R
: Oscillation clock
: Readable/Writable
: Read only
PLL clock operation bit
0
Operating with PLL clock
1
Operating with main clock or sub clock
bit15
SCM
Sub clock operation bit
0
Operating with sub clock
1
Operating with main clock or PLL clock
: Initial value
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5.3 Clock Selection Register (CKSCR)
MB90930 Series
Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1 / 3)
Bit name
Function
Indicates whether the main clock or sub clock is selected as the machine
clock.
bit15
SCM:
Sub clock operation flag
bit
•
•
bit14
MCM:
PLL clock operation flag
bit
When the sub clock operation flag bit (CKSCR: SCM) is "0" and the sub clock
selection bit (CKSCR: SCS) is "1", it indicates that the clock is in the transition
from the sub clock to the main clock. When the sub clock operation flag bit
(CKSCR: SCM) is "1" and the sub clock selection bit (CKSCR: SCS) is "0", it
indicates that the clock is in the transition from the main clock to the sub clock.
Writing has no effect on operation.
Indicates whether the main clock or PLL clock has been selected as the machine
clock.
• When the PLL clock operation flag bit (CKSCR: MCM) is "1" and the PLL clock
selection bit (CKSCR: MCS) is "0", it indicates that it is during the PLL clock
oscillation stabilization wait time.
• Writing has no effect on operation.
Selects the oscillation stabilization wait time of the oscillation clock when the stop
mode is canceled, when the transition from sub clock mode to main clock mode
occurs, and when the transition from sub clock mode to PLL clock mode occurs.
Selects one of four time-base timer outputs.
bit13,
bit12
WS1 and WS0:
Oscillation stabilization
wait time selection bits
CM44-10150-1E
Returned to the initial value with any reset.
Note:
Set the oscillation stabilization wait time to an appropriate value depending on the
oscillator used. Refer to "4.2 Reset Sources and Oscillation Stabilization Wait
Time" for details.
When the switching from the main clock mode to PLL clock mode is executed,
the oscillation stabilization wait time is fixed at 214/HCLK (during operation at an
oscillation clock frequency of 4 MHz: approx. 4.1 ms). When the CPU switches
from sub clock mode to PLL clock mode or when it returns from PLL stop mode
to PLL clock mode, the oscillation stabilization wait time follows the values
specified in these bits.
Since the PLL clock oscillation stabilization wait time requires 214/HCLK or
more, for switching from sub clock mode to PLL clock mode and transiting to
PLL stop mode, set these bits to "10B" or "11B".
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CHAPTER 5 CLOCK
5.3 Clock Selection Register (CKSCR)
MB90930 Series
Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2 / 3)
Bit name
Function
Specifies whether to select the main clock or sub clock as the machine clock.
•
•
bit11
bit10
SCS:
Sub clock selection bit
MCS:
PLL clock selection bit
When the machine clock is switched from the main clock to the sub clock
(CKSCR: SCS=1→0), it is synchronized with the sub clock and changed to
1/SCLK sub clock mode (approx. 122μs during operation at an oscillation clock
frequency of 32.768 kHz; divided by 4).
When the machine clock is switched from the sub clock to the main clock, it
changes to main clock mode after the oscillation stabilization wait time occurs to
the main clock. The time-base timer is automatically cleared.
Returns to the initial value by any reset.
Notes:
• When both MCS and SCS bits are "0", the SCS bit is preferred, and it is
set to the sub clock mode.
• When the sub clock selection bit (CKSCR: MCS) and the PLL clock
selection bit (CKSCR: SCS) are both "0", the sub clock is preferred.
• When switching from the main clock to the sub clock (CKSCR:
SCS=1→0), write after disabling time-base timer interrupt with the
time-base timer interrupt enable bit (TBTC: TBIE), or interrupt level
mask register (ILM: ILM2 to ILM0).
• When the power is turned on or stop mode is cancelled, an oscillation
stabilization wait time of 214/SCLK occurs to the sub clock (approx.
2 seconds during operation at an oscillation clock frequency of
32.768 kHz; divided by 4). Therefore, the oscillation stabilization wait
time occurs, if the clock mode is changed from the main clock mode to
the sub clock mode during that period.
Specifies whether the main clock or PLL clock to be selected as the machine clock.
When the machine clock is switched from the main clock to the PLL clock (CKSCR:
MCS=1 to 0), the clock mode changes to the PLL clock mode after the PLL clock
oscillation stabilization wait time is generated. The time-base timer is cleared
automatically. When the switching from the main clock mode to PLL clock mode is
executed, the oscillation stabilization wait time is fixed at
214/HCLK (during operation at an oscillation clock frequency of 4 MHz: approx.
4.1ms).
Returns to the initial value by any reset.
Notes:
• When both MCS and SCS bits are "0", the SCS bit is preferred, and it is
set to the sub clock mode.
• When switching from the main clock to the PLL clock (CKSCR:
MCS=1 to 0), write after disabling time-base timer interrupt with the
time-base timer interrupt enable bit (TBTC: TBIE), or interrupt level
mask register (ILM: ILM2 to 0).
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5.3 Clock Selection Register (CKSCR)
MB90930 Series
Table 5.3-1 Functions of Clock Selection Register (CKSCR) (3 / 3)
Bit name
Function
•
•
•
bit9,
bit8
CS1 and CS0:
Multiplication rate
selection bits
These bits and CS2 bit in the PLL/sub clock control register (PSCCR) select a
multiplication rate for the PLL clock.
One of six types of PLL clock multiplication rate can be selected.
Any reset causes the bits to return to the initial value.
Setting of CS0, CS1, and CS2.
CS2
CS1
CS0
PLL clock multiplication
rate
0
0
0
×1
0
0
1
×2
0
1
0
×3
0
1
1
×4
1
1
0
×6
1
1
1
×8
Note:
When the PLL clock is selected (CKSCR: MCS=0), writing is inhibited. To
rewrite the multiplier, write "1" to the PLL clock selection bit (CKSCR: MCS),
rewrite the multiplication rate selection bits (CKSCR: CS1 and CS0), then set the
PLL clock selection bit (CKSCR: MCS) back to "0".
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CHAPTER 5 CLOCK
5.4 PLL/Sub clock Control Register (PSCCR)
MB90930 Series
PLL/Sub clock Control Register (PSCCR)
5.4
The PLL/sub clock control register selects the PLL multiplication rate and the
division ratio of the sub clock. This register is write-only. The value read from
all bits is"1".
■ PLL/Sub Clock Control Register (PSCCR)
Figure 5.4-1 shows the configuration of the PLL/sub clock control register (PSCCR). Table
5.4-1 describes the function of each bit in the PLL/sub clock control register (PSCCR).
Figure 5.4-1 Configuration of PLL/Sub Clock Control Register (PSCCR)
Address
bit
0000CFH
15
14
13
12
11
10
9
8
Initial value
−
−
−
−
Resv
SCDS
Resv
CS2
XXXX0000B
−
−
−
−
W
W
W
W
bit8
CS2
0
1
Multiplication rate selection bit
See the clock selection registers
(CKSCR).
bit9
Reserved
0
Reserved bit
Always write "0".
Read value is always "1".
bit10
W
SCDS
: Write only
X
: Undefined value
−
: Undefined
: Initial value
Sub clock division selection bit
0
4-divided.
1
2-divided.
bit11
Reserved
0
128
Reserved bit
Always write "0".
Read value is always "1".
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CHAPTER 5 CLOCK
5.4 PLL/Sub clock Control Register (PSCCR)
MB90930 Series
Table 5.4-1 Function Description of Each Bit in the PLL/Sub Clock Control Register (PSCCR)
Bit name
Function
bit15
to
bit12
Undefined
These bits are not used.
• Writing to these bits has no effect.
• Read value is always "1".
bit11
Reserved bit
•
•
bit10
SCDS:
Sub clock division
selection bit
bit9
Reserved bit
Always write "0".
Read value is always "1".
Selects a division ratio for the sub clock.
bit8
CS2:
Multiplication rate
selection bit
•
•
•
•
When "0" is written, 4 division is selected.
When "1" is written, 2 division is selected.
Read value is always "1".
This bit is initialized to "0" with all reset sources.
•
•
Always write "0".
Read value is always "1".
•
This bit, and CS1 and CS0 bits in the clock selection register (CKSCR) determine
the PLL multiplication rate.
CS2
CS1
CS0
PLL clock multiplication
rate
0
0
0
×1
0
0
1
×2
0
1
0
×3
0
1
1
×4
1
1
0
×6
1
1
1
×8
• Read value is always "1".
• This bit is initialized to "0" with all reset sources.
Note:
When MCS or MCM bit is "0", it is prohibited to change the value of this bit.
Change the value in the main clock mode.
Note: The PSCCR register is write-only register. The read value is different from the write value.
Do not use read-modify-write (RMW) instructions (such as SETB/CLRB).
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CHAPTER 5 CLOCK
5.5 Clock Mode
5.5
MB90930 Series
Clock Mode
There are main clock mode and PLL clock mode.
■ Clock Mode
● Main clock mode
The main clock mode uses the divided-by-two clock (oscillation clock), generated either by
connecting the oscillator to oscillation pins (X0 and X1), as the operating clock for the CPU
and peripheral functions.
● Sub clock mode
The sub clock mode uses the divided-by-four or divided-by-two clock, generated either by
connecting the oscillator to the low-speed oscillation pins (X0A and X1A) or by inputting an
external clock, as the operating clock for the CPU and peripheral functions. The division ratio
for the sub clock can be selected with SCDS bit in the PLL/sub clock control register
(PSCCR).
X0A pin and X1A pin are optional pins (dual clock products only).
● PLL clock mode
The PLL clock mode uses the clock multiplied by the PLL clock multiplier circuit (PLL
oscillation circuit) as operating clock for the CPU and peripheral functions. The multiplication
rate for PLL clock can be set with the clock selection register (CKSCR: CS1 and CS0) and
PLL clock control register (PSCCR: CS2).
■ Transition of Clock Mode
The clock mode can make the transition to the main clock mode, sub clock mode or PLL clock
mode with setting the PLL clock selection bit (CKSCR: MCS) and the sub clock selection bit
(CKSCR: SCS).
● Transition from main clock mode to PLL clock mode
When the PLL clock selection bit (CKSCR: MCS) is rewritten from "1" to "0", after the PLL
oscillation stabilization wait time (214/HCLK) is elapsed, the transition from main clock to
PLL clock mode is made.
● Transition from PLL clock mode to main clock mode
When the PLL clock selection bit (CKSCR: MCS) is rewritten from "0" to "1", with the timing
the PLL clock and main clock edges match (after 1 to 12 PLL clocks), the transition from PLL
clock to main clock mode is made.
● Transition from main clock mode to sub clock mode
When the sub clock selection bit (CKSCR: SCS) is rewritten from "1" to "0", with the timing
of sub clock edge detected, the transition from main clock mode to sub clock mode is made.
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5.5 Clock Mode
MB90930 Series
● Transition from sub clock mode to main clock mode
When the sub clock selection bit (CKSCR: SCS) is rewritten from "0" to "1", after the main
clock oscillation stabilization wait time is elapsed, the transition from sub clock mode to main
clock mode is made.
● Transition from PLL clock mode to sub clock mode
When the sub clock selection bit (CKSCR: SCS) is rewritten from "1" to "0", the transition
from PLL clock mode to sub clock mode is made.
● Transition from sub clock mode to PLL clock mode
When the sub clock selection bit (CKSCR: SCS) is rewritten from "0" to "1", after the main
clock oscillation stabilization wait time is elapsed, the transition from sub clock mode to main
clock mode is made.
■ Selection of PLL Clock Multiplication Rate
6 types of PLL clock multiplication rates (1 to 4, 6, and 8 multiplications) can be set with
writing "000B" to "011B", "110B", and "111B" to the multiplication rate selection bits (CKSCR:
CS1 and CS0, PSCCR: CS2).
■ Machine Clock
The PLL clock, or main clock, sub clock output from the PLL multiplication circuit is used as
the machine clock. This machine clock is supplied to the CPU and peripheral functions. One of
the main clock, PLL clock and sub clock can be selected with writing to PLL clock selection
bit (CKSCR: MCS) and sub clock selection bit (CKSCR: SCS).
Notes:
• Even if the PLL c lock selection bit (C KSCR: MCS) are rewritten, the machine clock is
not s witched immediately. I f a machine clock-dependent pe ripheral f unction is
operated, con firm t hat t he machine clock is switched surely with referring to th e PLL
clock operation flag bit (CKSCR: MCM) before the operation.
• When the PLL clock selection bit (CKSCR: MCS) is "0" (PLL clock mode) and the sub
clock selection bit (CKSCR: SCS) is "0" (sub clock mode), the SCS bit is preferred, and
the transition to the sub clock mode occurs.
• When switching the clock mode, do not switch to the other clock m ode or low-power
consumption mode until the switching is completed. T he completion of switching can
be ch ecked w ith re ferring to th e M CM bit in the c lock se lection r egister (C KSCR).
Before the switching is completed, if a s witching to th e other clock mode or low-power
consumption mode is performed, the switching may have no effect.
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CHAPTER 5 CLOCK
5.5 Clock Mode
MB90930 Series
Figure 5.5-1 shows a diagram of the state transition with machine clock switching.
Figure 5.5-1 Diagram for State Transition with Machine Clock Selection
Main
MCS = 1
MCM = 1
SCS = 1
SCM = 1
CS1, CS0 = xxB
CS2=x
(10)
(12)
(1)
(13)
(8)
Main --> PLLx
MCS = 0
MCM = 1
SCS = 1
SCM = 1
CS1, CS0 = xxB
CS2 = x
(9)
(9)
(9)
(9)
(9)
(9)
132
(2)
(3)
(4)
(5)
(6)
(7)
Main --> Sub
MCS = 1
MCM = 1
SCS = 0
SCM = 1
CS1, CS0 = xxB
CS2 = x
Sub --> Main
MCS = 1
MCM = 1
SCS = 1
SCM = 0
CS1, CS0 = xxB
CS2 = x
(11)
(20)
(12)
(11)
Sub
MCS = X
MCM = 1
SCS = 0
SCM = 0
CS1, CS0 = xxB
CS2 = x
(10)
(14)
(15)
(16)
(17)
(18)
(19)
Sub --> PLL
MCS = 0
MCM = 1
SCS = 1
SCM = 0
CS1, CS0 = xxB
CS2 = 0
PLL1 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 00B
CS2 = 0
PLL1: Multiplied
MCS = 0
MCM = 0
SCS = 1
SCM = 1
(8) CS1, CS0 = 00B (10)
CS2 = 0
PLL1 --> Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS = 00B
CS2 = 0
PLL2 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 01B
CS2 = 0
PLL2: Multiplied
MCS = 0
MCM = 0
SCS = 1
(10)
(8) SCM = 1
CS1, CS0 = 01B
CS2 = 0
PLL2 --> Sub (21)
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 = 01B
CS2 = 0
PLL3 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 10B
CS2 = 0
PLL3: Multiplied
MCS = 0
MCM = 0
SCS = 1
(10)
(8) SCM = 1
CS1, CS0 = 10B
CS2 = 0
PLL3 --> Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 =10B
CS2 = 0
PLL4 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 11B
CS2 = 0
PLL4: Multiplied
MCS = 0
MCM = 0
SCS = 1
(10)
(8) SCM = 1
CS1, CS0 = 11B
CS2 = 0
PLL4 --> Sub (21)
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 = 11B
CS2 = 0
PLL6 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 10B
CS2 = 1
PLL6: Multiplied
MCS = 0
MCM = 0
SCS = 1
(10)
(8) SCM = 1
CS1, CS0 = 10B
CS2 = 1
PLL6 --> Sub (21)
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 =10B
CS2 = 1
PLL6 --> Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 11B
CS2 = 1
PLL8: Multiplied
MCS = 0
MCM = 0
SCS = 1
(10)
(8) SCM = 1
CS1, CS0 = 11B
CS2 = 1
PLL8 --> Sub
(21)
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 =11B
CS2 = 1
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(21)
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CHAPTER 5 CLOCK
5.5 Clock Mode
MB90930 Series
(1)
(2)
Write "0" to MCS bit
End of PLL clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0
(3)
End of PLL clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0
(4)
End of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0
(5)
End of PLL clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0
(6)
End of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1
(7)
End of PLL clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 1
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Write "1" to MCS bit (the resets included)
Synchronous timing of PLL clock and main clock
Write "0" to SCS bit
Synchronous timing of main clock and sub clock
Write "1" to SCS bit (MCS=1)
End of main clock oscillation stabilization wait time
End of main clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0
(15)
End of main clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0
(16)
End of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0
(17)
End of main clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0
(18)
End of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1
(19)
End of main clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 1
(20)
(21)
Write "1" to SCS bit (MCS=0)
Synchronous timing of PLL clock and sub clock
MCS
MCM
SCS
SCM
CS1, CS0
CS2
: PLL clock selection bit in the clock selection register (CKSCR)
: PLL clock operation flag bit in the clock selection register (CKSCR)
: Sub clock selection bit in the clock selection register (CKSCR)
: Sub clock operation flag bit in the clock selection register (CKSCR)
: Multiplication rate selection bit in the clock selection register (CKSCR)
: Multiplication rate selection bit in the PLL/sub clock control register (PSCCR)
Notes:
• The initial value of the machine clock is the main clock (CKSCR: MCS=1, SCS=1).
• When both SCS and MCS are "0", SCS is preferred, and the sub clock is selected.
• When switching from the sub clock mode to PLL clock mode, set CKSCR: WS1, WS0
to "10B" or "11B".
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CHAPTER 5 CLOCK
5.6 Oscillation Stabilization Wait Time
5.6
MB90930 Series
Oscillation Stabilization Wait Time
When the power is turned on or when the stop mode is released where the
oscillation clock is stopped, the oscillation clock requires some time to be
stabilized (oscillation stabilization wait time) after the oscillation is started. Also,
when the clock mode is switched from main to PLL, main to sub, sub to main, or
sub to PLL, the oscillation stabilization wait time is required.
■ Operation during Oscillation Stabilization Wait Time
Ceramic and crystal oscillators require the time period of several to several dozens of
milliseconds after the oscillation is started until it is stabilized at the natural frequency
(oscillation frequency). Accordingly, CPU operation should be disabled immediately after the
oscillation starts and the machine clock is supplied to the CPU when the oscillation is
stabilized after the oscillation stabilization wait time has elapsed.
However, the oscillation stabilization wait time depends on the type of oscillator (such as
ceramic and crystal). The proper oscillation stabilization wait time for the oscillator used must
be selected. The oscillation stabilization wait time can be set with the clock selection register
(CKSCR).
When the clock mode is switched from main to PLL, main to sub, sub to main, or sub to PLL,
the CPU runs in the clock mode set before the switching during the oscillation stabilization
wait time. When the oscillation stabilization wait time has elapsed, the CPU starts to run in the
clock mode switched. Figure 5.6-1 shows the oscillation operation right after the oscillation
starts.
Figure 5.6-1 Oscillation Operation Immediately after Oscillation Stabilization Wait Time
Oscillation time of
oscillator
Oscillation stabilization wait time
Starting normal operation or
switching to PLL clock
X1
Oscillation starts
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CHAPTER 5 CLOCK
5.7 Connection of Oscillator and External Clock
MB90930 Series
5.7
Connection of Oscillator and External Clock
The MB90930 series contains a system clock generation circuit. An internal
clock is generated with connecting the oscillator to the oscillation pin. A clock
externally input to the low-speed oscillation pin can be used as the oscillation
clock.
■ Connection of Oscillator and External Clock
● Example of connection of crystal oscillator or ceramic resonator
Figure 5.7-1 Example of Connection of Crystal Oscillator or Ceramic Resonator
X0
X1
C1
C2
MB90930 series
X0A*1
X1A*2
C3
C4
*1 : X0A pin is optional (dual clock products only).
*2 : X1A pin is optional (dual clock products only).
Figure 5.7-2 Example of Connection of External Clock
X0A*1
X1A*2
MB90930 series
*1 : X0A pin is optional (dual clock products only).
*2 : X1A pin is optional (dual clock products only).
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CHAPTER 5 CLOCK
5.7 Connection of Oscillator and External Clock
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CHAPTER 6
LOW-POWER
CONSUMPTION MODE
This chapter explains the low-power
consumption mode.
6.1 Overview of the Low-power Consumption Mode
6.2 Block Diagram of Low-power Consumption Circuit
6.3 Low-power Consumption Mode Control Register
(LPMCR)
6.4 CPU Intermittent Operation Mode
6.5 Standby Mode
6.6 State Transition Diagram
6.7 Pin State in the Standby Mode and at the Time of Reset
6.8 Notes on Using the Low-power Consumption Mode
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1 Overview of the Low-power Consumption Mode
6.1
MB90930 Series
Overview of the Low-power Consumption Mode
This series has the following CPU operating modes based on the operating
clock selection and clock operation control.
• Clock modes (PLL clock mode, main clock mode, sub clock mode)
• CPU intermittent operation modes (PLL clock intermittent operation mode, main
clock intermittent operation mode, sub clock intermittent operation mode)
• Standby modes (sleep mode, time-base timer mode, watch mode and stop
mode)
■ CPU Operation Modes and Current Consumption
Figure 6.1-1 shows the relationship between the CPU operation modes and their current
consumption.
Figure 6.1-1 CPU Operation Modes and Current Consumption
Current dissipation
Several
dozens of mA
CPU
operation
mode
8 multiplier clock
PLL clock mode
6 multiplier clock
4 multiplier clock
3 multiplier clock
2 multiplier clock
1 multiplier clock
PLL clock intermittent
operation mode
8 multiplier clock
6 multiplier clock
4 multiplier clock
3 multiplier clock
2 multiplier clock
1 multiplier clock
Main clock mode(1/2 clock mode)
Main clock intermittent operation mode
Sub clock mode
Several
mA
Sub clock intermittent operation mode
Standby mode
Sleep mode
Time-base timer mode
Watch mode
Several
μA
Low-power consumption mode
Stop mode
Note: This figure shows the image of operation modes and the actual current dissipation is partially different
from this figure.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1 Overview of the Low-power Consumption Mode
MB90930 Series
■ Clock Mode
● PLL clock mode
In this mode the PLL multiplier clock of the oscillation clock (HCLK) is to operate the CPU
and peripheral functions.
● Main clock mode
In this mode the divide-by-two clock of the oscillation clock (HCLK) is to operate the CPU
and peripheral functions. During the main clock mode, the PLL multiplier circuit stops.
● Sub clock mode
In this mode the divide-by-four clock of the sub clock (SCLK) is to operate the CPU and
peripheral functions. During the sub clock mode, the main clock and the PLL multiplier circuit
stops.
Reference:
See Section "5.5 Clock Mode" for the clock mode.
■ CPU Intermittent Operation Mode
In this mode, the power dissipation is reduced with operating the CPU intermittently while
providing high-speed clock to peripheral functions. During the CPU intermittent operation
mode, intermittent clock is input only to the CPU when a register, built-in memory, peripheral
function, or external unit is accessed.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1 Overview of the Low-power Consumption Mode
MB90930 Series
■ Standby Mode
In this mode, the power dissipation is reduced with stopping to provide the clock to the CPU
(sleep mode), stopping to provide the clock to the CPU and peripheral functions (time-base
timer mode) using a low-power consumption control circuit, or stopping the oscillation clock
(stop mode).
● PLL sleep mode
In this mode, during the PLL clock mode, providing operation clock to the CPU is stopped.
Others than the CPU are operated with PLL clock.
● Main sleep mode
In this mode, providing the operation clock to the CPU is stopped during the main clock mode.
Others than the CPU are operated with the main clock.
● Sub sleep mode
In this mode, providing the operation clock to the CPU is stopped during the sub clock mode.
Others than the CPU are operated with the main clock.
● Time-base timer mode
In this mode, operations other than the oscillation clock and time-base timer are stopped.
Functions other than the time-base timer are stopped.
● Watch mode
In this mode, only watch timer is operated. Only the sub clock is operated, and main clock and
PLL multiplier circuit are stopped.
● Stop mode
In this mode, the source oscillation is stopped, and all functions are stopped.
Note:
Since the os cillation clock is stopped in the stop mode, data can be held with the lowest
power dissipation. When switching the clock mode, do not switch to other clock modes or
the low-power consumption mode until the switching is completed. Check the switching is
completed by ref erring t o t he MCM bit and th e SCM bit in t he clock se lection r egister
(CKSCR). Before the switching is completed, if a swit ching to the other clock mode and
low-power consumption mode is performed, the switching may have no effect.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2 Block Diagram of Low-power Consumption Circuit
MB90930 Series
6.2
Block Diagram of Low-power Consumption Circuit
The low-power consumption control circuit consists of the following seven
blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of Low-power Consumption Control Circuit
Figure 6.2-1 shows the block diagram of the low-power consumption control circuit.
Figure 6.2-1 Block Diagram of Low-power Consumption Control Circuit
Low-power consumption mode control register (LPMCR)
Re-
STP SLP SPL RST TMD CG1 CG0 served
RST
Pin high
impedance
control circuit
Internal reset
Internal reset
generation
circuit
Intermittent cycle
selected
Pin
CPU intermittent
operation selector
CPU clock
control circuit
2
Interrupt cancel
Pin Hi-Z control
CPU clock
Stop and sleep signals
Standby control
circuit
Stop signal
Machine clock
Clock generation
block
Peripheral clock
control circuit
Peripheral clock
Cancellation of oscillation stabilization wait
Clock selector
Oscillation
stabilization
wait time selector
2
2
PLL multiplier
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
X0 Pin
X1 Pin
221024divided
HCLK divided MCLK divided
System clock
Time-base timer
generation
circuit
4divided
X0A* Pin
X1A* Pin
CM44-10150-1E
Sub clock
generation
circuit
4divided
4divided
4divided
2divided
To watchdog timer
SCLK
HCLK: Oscillation clock
MCLK: Main clock
SCLK: Sub clock
*:
X0A pin and X1A pin are optional pins (dual clock products only) .
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2 Block Diagram of Low-power Consumption Circuit
MB90930 Series
● CPU intermittent operation selector
Selects the number of clocks for pauses in the CPU intermittent operation mode.
● Standby control circuit
Controls the CPU clock control circuit and peripheral clock control circuit, and makes
transition to and cancellation of the low-power consumption mode.
● CPU clock control circuit
Controls clocks supplied to the CPU and peripheral clock control circuit peripheral functions.
● Peripheral clock control circuit
Controls clocks supplied to peripheral functions.
● Pin high impedance control circuit
Makes external pins high-impedance in the time-base timer mode and stop mode. The pull-up
resistor is disconnected from the pin with the pull-up option selected in the stop mode.
● Internal reset generation circuit
Generates internal reset signals.
● Low-power consumption mode control register (LPMCR)
Makes the transition to and cancellation of the standby mode and configures the CPU
intermittent operation function.
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6.3 Low-power Consumption Mode Control Register (LPMCR)
MB90930 Series
6.3
Low-power Consumption Mode Control Register
(LPMCR)
The low-power consumption mode control register (LPMCR) makes the
transition to and cancellation of the low-power consumption mode and
configures the pause cycle count of the CPU clocks in the CPU intermittent
operation mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low-power consumption mode control register, and
Table 6.3-1 lists the functions of each bit.
Figure 6.3-1 Configuration of Low-power Consumption Mode Control Register (LPMCR)
Address bit15
0000A0 H
bit8 bit7
(CKSCR)
bit6
bit5
bit4
bit3
bit2
bit1
R/W R/W R/W R/ W
Reserved
Initial value
Reser ved 00011000 B
STP SLP SPL RST TMD CG0
CG1
R/W R/W R/ W
bit0
R/W
Reser ved bit
Writing/reading has no effect to operation.
CG1 CG0 CPU clock pause cycle count selection bits
0
0
0 clock (CPU clock = peripheral clock)
0
1
8 clocks (CPU clock:peripheral clock = 1:approx. 3, 4)
1
0
16 clocks (CPU clock:peripheral clock = 1:approx. 5, 6)
1
1
32 clocks (CPU clock:peripheral clock = 1:approx. 9, 10)
TMD
Watch and time-base timer mode bit
0
Transition to time-base timer mode
1
No change, no effect to others
Internal reset signal generation bit
RST
0
Generates internal reset signals at 3 machine cycles
1
No change, no effect to others
SPL
0
Hold
1
High impedance
SLP
R/W
: Readable/writable
: Initial value
CM44-10150-1E
Pin state specification bit
(In watch, time-base timer, and stop modes)
Sleep mode bit
0
No change, no effect to others
1
Transition to sleep mode
STP
Stop mode bit
0
No change, no effect to others
Transition to stop mode
1
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3 Low-power Consumption Mode Control Register (LPMCR)
MB90930 Series
Table 6.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR)
Bit name
bit7
bit6
STP:
Stop mode bit
SLP:
Sleep mode bit
bit5
SPL:
Pin state specification bit
(in watch, time-base
timer, and stop modes)
bit4
RST:
Internal reset signal
generation bit
Function
•
•
•
•
•
Directs the transition to the stop mode.
When this bit is set to "1", the transition to the stop mode is made.
Writing "0" to this bit has no effect.
Reset, time-base timer cancellation, or stop cancellation clears the bit to "0".
Reading this bit always returns "0".
•
•
•
•
•
Directs the transition to the sleep mode.
When this bit is set to "1", the transition to the sleep mode is made.
Writing "0" to this bit has no effect.
Reset, sleep cancellation, or stop cancellation clears the bit to "0". When the STP
bit and SLP bit are set to "1" at the same time, the transition to the stop mode is
made.
Reading this bit always returns "0".
•
•
•
•
This bit is valid only in the time-base timer mode or stop mode.
When this bit is set to "0", the level of external pins is held.
When this bit is set to "1", the external pins are made to high impedance.
Reset initializes the bit to "0".
•
When this bit is set to "0", the internal reset signals are generated at 3 machine
cycles.
Writing "1" to this bit has no effect.
Reading this bit always returns "1".
•
•
•
•
bit3
TMD:
Watch and time-base
timer mode bit
•
•
Directs the transition to the watch mode and the time-base timer mode.
In the main clock mode or PLL clock mode, when this bit is set to "0", the transition
to the time-base timer mode is made.
In the sub clock mode, when this bit is set to "0", the transition to the watch mode is
made.
Reset or interrupt request generation initializes the bit to "1".
Reading this bit always returns "1".
Set the pause cycle count for CPU clock in the CPU intermittent operation function.
Specified cycle count CPU clock supply is stopped at each instruction.
One of four clock counts can be selected.
Any reset initializes the bits to "00B".
•
bit2,
bit1
CG1, CG0:
CPU clock pause cycle
count selection bits
•
•
•
•
bit0
Reserved:
Reserved bit
Writing/reading has no effect.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port
in the stop mode, watch mode or time-base timer mode, disable the output of peripheral
functions, and then set the STP bit to "1" or TMD bit to "0" in the low-power consumption
mode control register (LPMCR). Listed below are applicable pins.
Applicable pins: P00/SEG24 to P07/SEG31,P10/PPG2/IN5,P11/TOT0/WOT/PPG3/
IN4,P12/TIN0/PPG4,P13/PPG5,P22/SEG00 to P27/SEG05,P30/SEG06
to P37/SEG13,P40/SEG14 to P47/SEG21,P90/SEG22,P91/
SEG23,PD1/SOT2,PD2/SCK2,PD4/SOT3,PD5/SCK3,PD6/TOT2,PE0/
TOT3,P52/TX1/TX3,P54/TX0/TX2/SGA1,PE2/SGO1,P70/
PWM1P0,P71/PWM1M0,P72/PWM2P0,P73/PWM2M0,P74/
PWM1P1,P75/PWM1M1,P76/PWM2P1,P77/PWM2M1,P80/
PWM1P2,P81/PWM1M2,P82/PWM2P2,P83/PWM2M2,P84/
PWM1P3,P85/PWM1M3,P86/PWM2P3,P87/PWM2M3,P56/SGO0/
FRCK,P57/SGA0,PC7/PPG1/TIN1/IN6,PC6/PPG0/TOT1/IN7,PC5/
SCK1/TRG,PC4/SOT1,PC2/SCK0/INT6/IN2,PC1/SOT0/INT5/IN3
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3 Low-power Consumption Mode Control Register (LPMCR)
■ Access to the Low-power Consumption Mode Control Register
The transition to the low-power consumption mode (stop mode, sleep mode time-base timer
mode or watch mode) is executed with writing to the low-power consumption mode control
register. The instructions listed in Table 6.3-2 should be used for the transition to the low-power
consumption mode.
The following
command string must be allocated immediately after using the low-
power consumption mode transition instructions in Table 6.3-2.
MOV LPMCR, #H'xx; Low-power consumption mode transition instruction in Table 6.3-2
NOP
NOP
JMP $+3
; Jump to next instruction
MOV A, #H'10 ; Any instruction
If instruction lines other than shown in
are added, operations after canceling the
standby mode will not be assured.
If the C language is used to access the low-power consumption mode control register, see
Section "6.8 Notes on Using the Low-power Consumption Mode" and "■ Notes on Accessing
to the Low-power Consumption Mode Control Register (LPMCR) for the Transition to the
Standby Mode".
Use even addresses to write in the low-power consumption mode control register (LPMCR) in
units of words. Writing to an odd address may cause malfunction.
When functions other than the functions listed in Table 6.3-1 are controlled, any instructions
can be used.
● Priorities of STP, SLP, and TMD Bits
If a stop mode request, sleep mode request, and time-base timer mode request are executed at
the same time, those requests are processed with the following order of priorities:
Stop mode request > Time-base timer mode request > Sleep mode request
Table 6.3-2 List of Instructions Used for Transition to Low-power Consumption Mode
MOV io,#imm8
MOV io,A
MOV @RLi+disp8,A
MOVW io,#imm16
MOVW io,A
MOVW @RLi+disp8,A
SETB io:bp
CLRB io:bp
CM44-10150-1E
MOV dir,#imm8
MOV dir,A
MOV eam,#imm8
MOV addr16,A
MOV eam,Ri
MOV eam,A
MOVW dir,#imm16
MOVW dir,A
MOVW eam,#imm16
MOVW addr16,A
MOVW eam,RWi
MOVW eam,A
SETB dir:bp
CLRB dir:bp
SETB addr16:bp
CLRB addr16:bp
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4 CPU Intermittent Operation Mode
6.4
MB90930 Series
CPU Intermittent Operation Mode
The CPU intermittent operation mode is used to reduce power dissipation with
intermittent operation of the CPU while external buses or peripheral functions
are operated with high-speed.
■ CPU Intermittent Operation Mode
When the register, internal memory (ROM and RAM), I/O, peripheral functions, and external
buses are accessed, the CPU intermittent operation mode holds the clock provided to the CPU
every time an instruction is executed to delay the activation of an internal bus cycle. While
high-speed peripheral clocks are supplied to peripheral functions, the execution speed of the
CPU is reduced, the processing can be performed with low-power consumption.
The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select
the number of cycles which halts the clock supplied to the CPU.
The operation of external buses itself uses the same clock as the one which is used in
peripheral functions.
The instruction execution time in the CPU intermittent operation mode can be calculated by
adding the normal execution time to the adjusted value that is the number of instruction
executions for accesses to the register, internal memory, peripheral functions and external
buses multiplied by the number of pause cycle count. Figure 6.4-1 shows the clock in the CPU
intermittent operation mode.
Figure 6.4-1 Clock in the CPU Intermittent Operation Mode
Peripheral
clock
CPU clock
Pause cycle
One instruction execution cycle
Internal bus activated
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MB90930 Series
6.5
Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
The standby mode includes the sleep mode (PLL sleep mode, main sleep
mode, sub sleep mode) and watch mode, stop mode.
■ Operation States in the Standby Mode
Table 6.5-1 shows the operation states in the standby mode.
Table 6.5-1 Operation States in the Standby Mode
Standby Mode
PLL
sleep mode
Sleep mode Main
sleep mode
Transition
conditions
SCS=1
MCS=0
SLP=1
SCS=1
MCS=1
SLP=1
SCS=0
SLP=1
Main
clock
Sub clock
Machine
clock
CPU
Peripheral
Release
method
Operating
Operating
Operating Operating
Sub
Stopped
sleep mode
Time-base
Operating
SCS=1
timer mode
TMD=0
Time-base (SPL=0)
Operating
Stopped Stopped*1
timer mode Time-base
SCS=1
timer mode
TMD=0
(SPL=1)
Watch mode
SCS=0
Stopped
(SPL=0)
TMD=0
Watch
Stopped*2
mode
Watch mode
SCS=0
(SPL=1)
TMD=0
Stopped
Stop mode
STP=1
(SPL=0)
Stopped
Stopped
Stop mode
Stop mode
STP=1
(SPL=1)
*1
: The time-base timer and the watch timer operate.
*2
: The watch timer operate.
SPL : Pin state specification bit in the low-power consumption mode control register (LPMCR)
SLP : Sleep bit in the low-power consumption mode control register (LPMCR)
STP : Watch watch stop bit in the low-power consumption mode control register (LPMCR)
TMD : Watch/time-base timer mode bit in the low-power consumption mode control register (LPMCR)
MCS : PLL clock selection bit in the clock selection register (CKSCR)
SCS : Sub clock selection bit in the clock selection register (CKSCR)
Hi-Z : High impedance
CM44-10150-1E
Pin
FUJITSU MICROELECTRONICS LIMITED
Hold
Reset
Interrupt
Hi-Z
Hold
Hi-Z
Hold
Hi-Z
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
MB90930 Series
Note:
To set a pin to high impedance when the pin shares a port with peripheral functions in the
stop mod e, watch mod e or t ime-base timer mode, disab le th e output of peripheral
functions, and then set the STP bit to "1" or TMD bit to "0" in the low-power consumption
mode control register (LPMCR). Listed below are applicable pins.
Applicable pins: P00/SEG24 to P07/SEG31,P10/PPG2/IN5,P11/TOT0/WOT/PPG3/
IN4,P12/TIN0/PPG4,P13/PPG5,P22/SEG00 to P27/SEG05,P30/SEG06
to P37/SEG13,P40/SEG14 to P47/SEG21,P90/SEG22,P91/
SEG23,PD1/SOT2,PD2/SCK2,PD4/SOT3,PD5/SCK3,PD6/TOT2,PE0/
TOT3,P52/TX1/TX3,P54/TX0/TX2/SGA1,PE2/SGO1,P70/
PWM1P0,P71/PWM1M0,P72/PWM2P0,P73/PWM2M0,P74/
PWM1P1,P75/PWM1M1,P76/PWM2P1,P77/PWM2M1,P80/
PWM1P2,P81/PWM1M2,P82/PWM2P2,P83/PWM2M2,P84/
PWM1P3,P85/PWM1M3,P86/PWM2P3,P87/PWM2M3,P56/SGO0/
FRCK,P57/SGA0,PC7/PPG1/TIN1/IN6,PC6/PPG0/TOT1/IN7,PC5/
SCK1/TRG,PC4/SOT1,PC2/SCK0/INT6/IN2,PC1/SOT0/INT5/IN3
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CM44-10150-1E
MB90930 Series
6.5.1
Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
When the transition to the sleep mode is directed in the lowpower consumption
mode control register (LPMCR), if the PLL clock mode is set, the transition to
the PLL sleep mode is made, if the main clock mode is set, the transition to the
main sleep mode is made, and if the sub clock mode is set, the transition to the
sub sleep mode is made.
■ Transition to Sleep Mode
When the low-power consumption mode control register is set (LPMCR: SLP=1, TMD=1, and
STP=0), the transition to the sleep mode is made. When the transition to the sleep mode is
made, if MCS bit is "0" and SCS bit is "1" in the clock selection register (CKSCR), the
transition to the PLL sleep mode is made. If MCS bit is "1" and SCS bit is "1", the transition to
the main sleep mode is made, and if SCS bit is "0", the transition to the sub sleep mode is
made.
Note:
When the SLP b it and STP bit are set to "1" a t the same time, the STP bit is pr eferred,
and the transition to the stop mode is made. When the SLP bit is set to "1" and TMD bit is
set to "0" at the same time, the TMD bit is preferred, and the transition to the time-base
timer mode or the watch mode is made.
● Data retaining function
In the sleep mode, the contents of dedicated registers, such as accumulators, and the internal
RAM are retained.
● Operations while an interrupt request exists
When "1" is set to the SLP bit in the low-power consumption mode control register (LPMCR),
if an interrupt request exists, the transition to the sleep mode is not made. Therefore, if the CPU
does not accept the interrupt request, the CPU executes the next instruction, and if the CPU
accepts the interrupt request, the CPU operation immediately branches to the interrupt
processing routine.
● Pin state
During the sleep mode, pins keep the state before switching to the sleep mode.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
MB90930 Series
■ Releasing Sleep Mode
The low-power consumption control circuit cancels the sleep mode with a reset input or
generation of an interrupt.
● Return by reset
The mode is initialized to the main clock mode by reset.
● Return by interrupt
During the sleep mode, if an interrupt request with interrupt level higher than "7" is generated
by a peripheral circuit or others, the sleep mode will be canceled. After the sleep mode is
canceled, the interrupt request will be treated the same as the normal interrupt processing. If
the interrupt is accepted based on the setting of the I flag in the condition code register (CCR),
interrupt level mask register (ILM), and interrupt control register (ICR), the CPU will execute
an interrupt processing. If the interrupt is not accepted, the processing will be continued with
the next instruction after the one which was specified to the sleep mode.
Figure 6.5-1 shows the cancellation of the sleep mode with the generation of the interrupt
requests.
Figure 6.5-1 Cancellation of Sleep Mode with Interrupt Request Generation
Interrupt of peripheral functions
Enable flag settings
INT occurs (IL < 7)
NO
Does not cancel sleep
Does not cancel sleep
YES
I=0
YES
Executes the next instruction
Cancels sleep
NO
ILM < IL
YES
Executes the next instruction
NO
Executes interrupt processing
Note:
When a n interrupt processing is executed, it is no rmal t hat an interrupt pr ocessing is
executed aft er ex ecuting the ne xt instruction co ming af ter th e o ne wh ich is s pecified to
the sleep mode.
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CM44-10150-1E
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
MB90930 Series
Figure 6.5-2 shows the cancellation of the sleep mode (external reset).
Figure 6.5-2 Cancellation of Sleep Mode (External Reset)
RST pin
Sleep mode
Main clock
Oscillating
PLL clock
Oscillating
CPU clock
CPU operation
PLL clock
Stopped
Cancellation of sleep mode
CM44-10150-1E
Reset sequence
Processing
Cancellation of reset
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
6.5.2
MB90930 Series
Time-base Timer Mode
In the time-base timer mode, the other functions than the source oscillation,
time-base timer and watch timer are stopped. Therefore, all the functions
except the time-base timer and the watch timer are stopped.
■ Transition to Time-base Timer Mode
In the PLL clock mode or main clock mode, when "0" is written to the TMD bit of the lowpower consumption mode control register (LPMCR), the transition to the time-base timer mode
is made.
● Data retaining function
In the time-base timer mode, the contents of dedicated registers such as accumulators and the
internal RAM are retained.
● Operations while an interrupt request occurs
When "0" is written to the TMD bit in the low-power consumption mode control register
(LPMCR), if an interrupt request exists, the transition to the time-base timer mode is not made.
● Pin state
It can be controlled with the SPL bit in the low-power consumption mode control register
(LPMCR) whether the external pins in the time-base timer mode are retained in the state they
were right before the transition or go to the high-impedance state.
Note:
In the time-base timer mode, when the pin which shares a port with peripheral functions is
set t o h igh-impedance, disab le t he ou tput of t he per ipheral f unctions, t hen set "0" t he
TMD bit in the low-power consumption mode control register (LPMCR). Listed below are
applicable pins.
Applicable pins: P00/SEG24 to P07/SEG31,P10/PPG2/IN5,P11/TOT0/WOT/PPG3/IN4,P12/
TIN0/PPG4,P13/PPG5,P22/SEG00 to P27/SEG05,P30/SEG06 to P37/
SEG13,P40/SEG14 to P47/SEG21,P90/SEG22,P91/SEG23,PD1/
SOT2,PD2/SCK2,PD4/SOT3,PD5/SCK3,PD6/TOT2,PE0/TOT3,P52/
TX1/TX3,P54/TX0/TX2/SGA1,PE2/SGO1,P70/PWM1P0,P71/
PWM1M0,P72/PWM2P0,P73/PWM2M0,P74/PWM1P1,P75/
PWM1M1,P76/PWM2P1,P77/PWM2M1,P80/PWM1P2,P81/
PWM1M2,P82/PWM2P2,P83/PWM2M2,P84/PWM1P3,P85/
PWM1M3,P86/PWM2P3,P87/PWM2M3,P56/SGO0/FRCK,P57/
SGA0,PC7/PPG1/TIN1/IN6,PC6/PPG0/TOT1/IN7,PC5/SCK1/TRG,PC4/
SOT1,PC2/SCK0/INT6/IN2,PC1/SOT0/INT5/IN3
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
MB90930 Series
■ Releasing Time-base Timer Mode
The low-power consumption control circuit releases the time-base timer mode with reset input
or interrupt generation.
● Return by reset
The mode is initialized to the main clock mode by reset.
● Return by interrupt
During the time-base timer mode, if an interrupt request with interrupt level higher than "7" is
generated by peripheral circuits or others (the interrupt control register ICR: IL2, IL1, and IL0
are other than "111B"), the low-power consumption control circuit releases the time-base timer
mode. After the time-base timer mode is canceled, the interrupt request will be treated the same
as the normal interrupt processing. If an interrupt is accepted based on the settings of the I flag
in the condition code register (CCR), interrupt level mask register (ILM), and interrupt control
register (ICR), the interrupt processing is executed. If the interrupt is not accepted, the
processing will be continued with the next instruction before the transition to the time-base
timer mode is made.
Note:
It is normal that an
interrupt proc essing w ill be execut ed after executing the next
instruction coming after the one which is specified to the time-base timer mode. However,
if t he t ransition to th e t ime-base t imer mo de a nd acceptance of an exte rnal bu s hold
request occur simult aneously, t he t ransition t o the in terrupt processing m ight b e m ade
before the next instruction is executed.
Figure 6.5-3 shows the operation for return from the time-base timer mode.
Figure 6.5-3 Cancellation of Time-base Timer Mode (External Reset)
RST pin
Time-base
timer mode
Main clock
Oscillating
PLL clock
Oscillation stabilization wait
CPU clock
CPU operation
Main clock
Stopped
Reset sequence
Oscillating
PLL clock
Processing
Cancellation of reset
Cancellation of time-base timer mode
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
6.5.3
MB90930 Series
Watch Mode
In the watch mode, operations other than the sub clock and watch timer are
stopped. Almost all the functions of the chip are stopped.
This mode can be used with the dual clock product.
■ Transition to Watch Mode
In the sub clock mode (CKSCR: SCS=0), when "0" is written to the TMD bit of the low-power
consumption mode control register (LPMCR), the transition to the watch mode is made.
● Data retaining function
In the watch mode, the contents of dedicated registers such as accumulators and the internal
RAM are retained.
● Operations while an interrupt request occurs
When "1" is set to the TMD bit in the low-power consumption mode control register
(LPMCR), if an interrupt request exists, the transition to the watch mode is not made.
● Setting the pin state
It can be controlled with the SPL bit in the low-power consumption mode control register
(LPMCR) whether the external pins in the watch mode are retained in the state they were right
before the transition or go to the high-impedance state.
Note:
In the watch mode, when the pin which shares a port with peripheral functions is set to
high-impedance, disable the output of the peripheral functions, then set "1" the TMD bit in
the low-power consumption mode control register (LPMCR). Listed below are applicable
pins.
Applicable pins: P00/SEG24 to P07/SEG31, P10/PPG2/IN5, P11/TOT0/PPG3/IN4, P12/
TIN0/PPG4, P13/PPG5, P22/SEG00 to P27/SEG05, P30/
SEG06 to P37/SEG13, P40/SEG14 to P47/SEG21, P90/SEG22, P91/
SEG23, PD1/SOT2, PD2/ SCK2, PD4/SOT3, PD5/SCK3, PD6/
TOT2, PE0/TOT3, P52/TX1/TX3, P54/TX0/ TX2/SGA1, PE2/SGO1,
P70/PWM1P0, P71/PWM1M0, P72/PWM2P0, P73/ PWM2M0, P74/
PWM1P1, P75/PWM1M1, P76/PWM2P1, P77/PWM2M1, P80/
PWM1P2, P81/PWM1M2, P82/PWM2P2, P83/PWM2M2, P84/
PWM1P3, P85/ PWM1M3, P86/PWM2P3, P87/PWM2M3, P56/SGO0/
FRCK, P57/SGA0, PC7/ PPG1/TIN1/IN6, PC6/PPG0/TOT1/IN7, PC5/
SCK1/TRG, PC4/SOT1, PC2/ SCK0/INT6/IN2, PC1/SOT0/INT5/IN3
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
MB90930 Series
■ Releasing Watch Mode
The low-power consumption control circuit cancels the watch mode with a reset input or
generation of an interrupt.
● Return by reset
When the watch mode is released by a reset source, after the watch mode is released, the
system enters oscillation stabilization wait reset state. The reset sequence is executed after the
oscillation stabilization wait time has elapsed.
● Return by interrupt
During the watch mode, if an interrupt request with interrupt level higher than "7" is generated
by peripheral circuits or others (the interrupt control register ICR: IL2, IL1 and IL0 are other
than "111B"), the low-power consumption control circuit releases the watch mode, and then
immediately the transition to the sub clock mode is made. After the transition to the sub clock
mode is made, the interrupt request will be treated the same as the normal interrupt processing.
If the interrupt request is accepted with setting of the I flag in the condition code register
(CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU will
execute an interrupt processing. If the interrupt request is not accepted, the processing will be
continued with the next instruction before the transition to the watch mode is made.
Note:
When a n interrupt processing is executed, it is no rmal t hat an interrupt p rocessing is
executed a fter e xecuting the next in struction coming a fter the one w hich is s pecified t o
the sleep mode.
Figure 6.5-4 shows the cancellation of the watch mode (external reset).
Figure 6.5-4 Cancellation of Watch Mode (External Reset)
RST pin
Watch mode
Main clock
PLL clock
Stopped
Sub clock
Oscillating
Main clock
CPU clock
CPU operation
Oscillating
Oscillation stabilization wait
Stopped
Reset sequence
Processing
Cancellation of reset
Cancellation of watch mode
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6.5 Standby Mode
6.5.4
MB90930 Series
Stop Mode
In this mode, the source oscillation is stopped to stop all the functions.
Therefore, data can be retained with the lowest-power dissipation.
■ Transition to Stop Mode
When the STP bit in the low-power consumption mode control register (LPMCR) is set to "1",
the transition to the stop mode is made.
● Data retaining function
In the stop mode, the contents of dedicated registers such as accumulators and the internal
RAM are retained.
● Operations while an interrupt request occurs
When "1" is set to the STP bit in the low-power consumption mode control register (LPMCR),
if an interrupt request exists, the transition to the stop mode is not made.
● Setting the pin state
It can be controlled with the SPL bit in the low-power consumption mode control register
(LPMCR) whether the external pins in the stop mode are retained in the state they were right
before the transition or go to the high-impedance state.
Note:
In t he st op mo de, when th e pin which sha res a p ort with peripheral fu nctions is set to
high-impedance, disable the output of the peripheral functions, then set "1" the STP bit in
the low-power consumption mode control register (LPMCR). Listed below are applicable
pins.
Applicable pins: P00/SEG24 to P07/SEG31,P10/PPG2/IN5,P11/TOT0/WOT/PPG3/
IN4,P12/TIN0/PPG4,P13/PPG5,P22/SEG00 to P27/SEG05,P30/SEG06
to P37/SEG13,P40/SEG14 to P47/SEG21,P90/SEG22,P91/
SEG23,PD1/SOT2,PD2/SCK2,PD4/SOT3,PD5/SCK3,PD6/TOT2,PE0/
TOT3,P52/TX1/TX3,P54/TX0/TX2/SGA1,PE2/SGO1,P70/
PWM1P0,P71/PWM1M0,P72/PWM2P0,P73/PWM2M0,P74/
PWM1P1,P75/PWM1M1,P76/PWM2P1,P77/PWM2M1,P80/
PWM1P2,P81/PWM1M2,P82/PWM2P2,P83/PWM2M2,P84/
PWM1P3,P85/PWM1M3,P86/PWM2P3,P87/PWM2M3,P56/SGO0/
FRCK,P57/SGA0,PC7/PPG1/TIN1/IN6,PC6/PPG0/TOT1/IN7,PC5/
SCK1/TRG,PC4/SOT1,PC2/SCK0/INT6/IN2,PC1/SOT0/INT5/IN3
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6.5 Standby Mode
MB90930 Series
■ Releasing Stop Mode
The low-power consumption control circuit cancels the stop mode with a reset input or
generation of an interrupt. When the CPU returns from the stop mode and the oscillation clock
(HCLK) and the sub clock (SCLK) are stopped. Therefore, after the main clock oscillation
stabilization wait time or the sub clock oscillation stabilization wait time passes, the stop mode
is released.
● Return by reset
When the stop mode is released by a reset source, after the stop mode is released, the system
enters oscillation stabilization wait reset state. The reset sequence is executed after the
oscillation stabilization wait time has elapsed.
● Return by interrupt
During the stop mode, if an interrupt request with interrupt level higher than "7" is generated
by peripheral circuits or others (the interrupt control register ICR: IL2, IL1, and IL0 are other
than "111B"), the low-power consumption control circuit releases the stop mode. When the
stop mode is released, after the main clock oscillation stabilization wait time which was
specified with the WS1 and WS0 bits in the clock selection register (CKSCR) passes, the
interrupt is treated the same as the normal interrupt processing. If the interrupt request is
accepted with setting of the I flag in the condition code register (CCR), interrupt level mask
register (ILM), and interrupt control register (ICR), the CPU will execute an interrupt
processing. If the interrupt is not accepted, the processing will be continued with the next
instruction before the transition to the stop mode is made.
Notes:
• When an interrupt processing is execu ted, it is n ormal that an int errupt processing is
executed after executing the next instruction coming after the one which is specified to
the slee p mode. However , if t he transition t o the st op mo de and a cceptance of an
external b us ho ld request o ccur simu ltaneously, before the n ext inst ruction is
executed, the transition to the interrupt processing might be made.
• In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the
CPU returns from PLL stop mode, therefore, it is ne cessary to secure the main clock
oscillation stabilization w ait time and PLL clock os cillation stabiliz ation wait time. The
oscillation stabiliz ation wait ti me in this case bases up
on the values set in the
oscillation stabilization wait time selec tion bit in the
clock selection register
(CKSCR:WS1, WS 0), and the main clock o scillation stabilization wait time and PLL
clock oscillation stabilization wait time will be counted together. Th erefore, set a value
to the "CKSC R:WS1, W S0" bit in li ne with the longest one of the oscillation
stabilization w ait times. H owever, becaus e 214/HCLK or mo re is ne eded for t he PLL
clock oscillation stabilization wait time, set "10 B" or "11B" to the "CKSCR: WS1, WS0"
bit.
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6.5 Standby Mode
MB90930 Series
Figure 6.5-5 shows the cancellation of the stop mode (external reset).
Figure 6.5-5 Cancellation of Stop Mode (External Reset)
RST pin
Stop mode
Main clock
PLL clock
Stopped
CPU clock
CPU operation
Oscillating
Oscillation stabilization wait
Main clock
Stopped
Reset sequence
Processing
Cancellation of reset
Cancellation of stop mode
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6.6 State Transition Diagram
MB90930 Series
6.6
State Transition Diagram
Figure 6.6-1 shows the transition diagram and conditions of the operation
status.
■ State Transition Diagram
Figure 6.6-1 State Transition Diagram
Power applied
CPU operation detetion reset
Software reset
External reset
Watchdog timer reset
Power voltage lowered
Power-on reset
End of oscillation
stabilization wait
Low-voltage
detection reset
*
Reset
End of
oscillation
stabilization
wait
SCS=1
SCS=0
MCS=0
Main clock
mode
SCS=0
SCS=1
MCS=1
SLP=1
Interrupt
Main sleep mode
TMD=0
Sub clock mode
PLL clock mode
Interrupt
Timebase timer
mode
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
PLL Timebase
timer mode
STP=1
STP=1
Main stop mode
Interrupt
End of oscillation
stabilization wait
Main clock oscillation
stabilization wait
Interrupt
Sub sleep mode
TMD=0
Interrupt
Timebase timer
mode
STP=1
PLL stop mode
Interrupt
SLP=1
End of oscillation
stabilization wait
PLL clock oscillation
stabilization wait
Sub stop mode
Interrupt
End of oscillation
stabilization wait
Sub clock oscillation
stabilization wait
*: This mode can be used with the dual clock product.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.6 State Transition Diagram
MB90930 Series
■ Operation States in the Low-power Consumption Mode
Table 6.6-1 shows the operation states in the low-power consumption mode.
Table 6.6-1 Operation States in the Low-power Consumption Mode
Operation state
Main
clock
Sub
clock
PLL
clock
PLL
PLL sleep
PLL time-base
timer*1
PLL stop
PLL oscillation
stabilization wait
Operating
Operating
Operating
Stopped
Stopped
Stopped
Stopped
Operating
Operating
Operating
Main time-base
timer*2
Main stop
Main oscillation
stabilization wait
Operating
Operating
Stopped
Stopped
Operating
Operating
Sub
Watch
Operating
Operating
Stopped
Sub stop
Power-on reset
Stopped
Stopped
Sub oscillation
stabilization wait
Reset
Stopped
Stopped
Operating
Timebase timer
Operating
Operating
Clock
source
PLL
clock
Stopped
Stopped
Stopped
Operating
Operating
Operating
Operating
Operating
Main
clock
Stopped
Operating
Stopped
Operating
Operating
Watch
Operating
Operating
Stopped
Sub sleep
Peripheral
Operating
Main
Main sleep
CPU
Stopped
Stopped
Operating
Operating
Operating
Stopped
Sub
clock
Operating
Main
clock
Stopped
Operating
Stopped
Operating
Stopped
Stopped
Operating
*1: In PLL clock mode
*2: In main clock mode
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6.7 Pin State in the Standby Mode and at the Time of Reset
MB90930 Series
6.7
Pin State in the Standby Mode and at the Time of
Reset
This section describes pin states in the standby mode and at the time of reset,
for each memory access mode.
■ Pin States in Single Chip Mode
Table 6.7-1 shows each pin state in the single chip mode.
Table 6.7-1 Each Pin State in Single Chip Mode
In standby mode
Product name
Pin name
In sleep mode
During stop/watch/time-base timer
SPL=0
SPL=1
The previous state
is kept.*2
Input cut-off*3/
Output Hi-Z
At reset
P00 to P07
P10 to P15
P36, P37
P40 to P47
P52, P54, P56, P57
P60 to P67
Evaluation
product,
mask ROM
product, and
Flash memory
product
P22 to P27
P30 to P35
P70 to P77
P80 to P87
The previous state
is kept.*2
Input unavailable*4/
Output Hi-Z
P90 to P92
P94 to P96
PC4 to PC7
PD0 to PD6
PE0 to PE2
P50, P51, P53, P55
PC0 to PC3
Input available*1 (External interrupt enabled)
COM0 to COM3
*1:
*2:
*3:
*4:
Output "L"
Output "L"
Output "L"
Output "L"
"Input available" means that input functions can be used. Therefore, pull-up/pull-down processing or external input is needed. If the
pin is used as an output port, its state is the same as other ports.
"The previous state is kept" means that the output state right before the mode is kept as it is. However, note that if it was input state,
input will be unavailable.
"Output state is kept as it is" means that if an internal peripheral with output is operated, its value is kept, and if the pin is outputting
as a port, its value is kept.
"Input cut-off" indicates the state in which an operation of an input gate near the pin is disabled, and "Output Hi-Z" means that the
pin-driving transistor is prohibited from driving, and the pin is switched to high impedance state.
"Input unavailable" means that the input value to the pin cannot be accepted internally because the internal circuit is stopped while the
operation of input gate near the pin is allowed.
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6.7 Pin State in the Standby Mode and at the Time of Reset
MB90930 Series
Note:
To set a pin to high impedance when the pin shares a port with peripheral functions in the
stop mod e, watch mod e or t ime-base timer mode, disab le th e output of peripheral
functions, and then set the STP bit to "1" or TMD bit to "0" in the low-power consumption
mode control register (LPMCR). Listed below are applicable pins.
Applicable pins: P00/SEG24 to P07/SEG31,P10/PPG2/IN5,P11/TOT0/WOT/PPG3/
IN4,P12/TIN0/PPG4,P13/PPG5,P22/SEG00 to P27/SEG05,P30/SEG06
to P37/SEG13,P40/SEG14 to P47/SEG21,P90/SEG22,P91/
SEG23,PD1/SOT2,PD2/SCK2,PD4/SOT3,PD5/SCK3,PD6/TOT2,PE0/
TOT3,P52/TX1/TX3,P54/TX0/TX2/SGA1,PE2/SGO1,P70/
PWM1P0,P71/PWM1M0,P72/PWM2P0,P73/PWM2M0,P74/
PWM1P1,P75/PWM1M1,P76/PWM2P1,P77/PWM2M1,P80/
PWM1P2,P81/PWM1M2,P82/PWM2P2,P83/PWM2M2,P84/
PWM1P3,P85/PWM1M3,P86/PWM2P3,P87/PWM2M3,P56/SGO0/
FRCK,P57/SGA0,PC7/PPG1/TIN1/IN6,PC6/PPG0/TOT1/IN7,PC5/
SCK1/TRG,PC4/SOT1,PC2/SCK0/INT6/IN2,PC1/SOT0/INT5/IN3
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6.8 Notes on Using the Low-power Consumption Mode
MB90930 Series
6.8
Notes on Using the Low-power Consumption Mode
Take notice of the following points when using the low-power consumption
mode.
• Transition to the standby mode and interrupts
• Notes on the transition to the standby mode
• Releasing the standby mode by an interrupt
• At releasing the stop mode
• Oscillation stabilization wait time
• Switching the clock mode
• Notes on accessing to the low-power consumption mode control register
(LPMCR) for the transition to the standby mode.
■ Transition to Standby Mode and Interrupts
Once an interrupt request is generated from a peripheral function to the CPU, the transition to
any standby mode is not made because the setting to the low-power consumption mode control
register, (LPMCR:STP=1, SLP=1) or (LPMCR:TMD=0), is ignored (and also even after
interrupt processing, the transition to the standby mode is not made.). In this case, if the
interrupt level is higher than "7", it is not a matter whether the interrupt request is accepted by
the CPU.
Additionally, even when the CPU is processing an interrupt, if the interrupt request flag bit is
cleared and there is no other interrupt request, the transition to the standby mode can be made.
■ Notes on Transition to Standby Mode
During the stop mode, watch mode or time-base timer mode, if the pin which shares a port with
a peripheral function is set to high-impedance, follow the procedure below.:
1)
Disable the output of peripheral functions.
2)
Set "1" to SPL/STP bits or "1" to TMD bit in the low-power consumption mode control
register (LPMCR).
■ Releasing the Standby Mode by Interrupt
During the sleep, time-base timer, or stop mode, if the interrupt request with interrupt level
higher than "7" is generated, the standby mode will be released. The releasing will be
performed without regard to whether the CPU accepts the interrupt or not.
After the standby mode is released, if the priority of the interrupt level setting bit (ICR: IL2,
IL1, and IL0) for the interrupt request is higher than the interrupt level mask register (ILM) and
the interrupt enable flag in the condition code register is enabled (CCR: I=1), the CPU will
branch to the interrupt processing routine, as normal interrupt operation.
If the interrupt is not accepted, the operation will be restarted from the next instruction after the
one which specified to the standby mode.
When an interrupt processing is executed, it is normal that an interrupt processing is executed
after executing the next instruction coming after the one which is specified to the standby
mode.
However, before the next instruction is executed, the interrupt processing might be performed
depending on the conditions at the transition to the standby mode,
If the branch to the interrupt processing routine right after the return is prevented, measures
such as disabling interrupts before setting the standby mode are necessary.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.8 Notes on Using the Low-power Consumption Mode
MB90930 Series
■ At Releasing the Stop Mode
Before the transition to the stop mode is made, the mode can be released with input according
to the setting of the interrupt input sources of external interrupts "H" level, "L" level, and rising
edge, and falling edge.
■ Oscillation Stabilization Wait Time
● Oscillation clock oscillation stabilization wait time
Since the oscillator for source oscillation is stopped during the stop mode, the oscillation
stabilization wait time has to be secured. For the oscillation stabilization wait time, the time
selected with the WS1 and WS0 bits in the clock selection register (CKSCR) is taken. Set
"00B" to the WS1 and WS0 bits only in the main clock mode.
● PLL clock oscillation stabilization wait time
Since the PLL multiplier circuit is stopped during the main clock mode, if the transition to the
PLL clock mode is made, a PLL clock oscillation stabilization wait time has to be secured.
During the PLL clock oscillation stabilization wait time, the main clock operates.
At the time the mode is switched from the main clock mode to PLL clock mode, the PLL clock
oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock).
Since the main clock and the PLL multiplier circuit are stopped during the sub clock mode, if
the transition to the PLL clock mode is made, the main clock oscillation stabilization wait time
and PLL clock oscillation stabilization wait time has to be secured. The oscillation stabilization
wait time in this case bases upon the values set in the oscillation stabilization wait time
selection bit in the clock selection register (CKSCR:WS1, WS0), and the main clock
oscillation stabilization wait time and PLL clock oscillation stabilization wait time will be
counted together. However, because 214/HCLK or more is needed for the PLL clock oscillation
stabilization wait time, set "10B" or "11B" to the "CKSCR: WS1, WS0" bit.
When the CPU returns from PLL stop mode, therefore, it is necessary to secure the main clock
oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The
oscillation stabilization wait time in this case bases upon the values set in the oscillation
stabilization wait time selection bit in the clock selection register (CKSCR:WS1, WS0), and
the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait
time will be counted together. Therefore, set a value to the "CKSCR:WS1, WS0" bit in line
with the longest one of the oscillation stabilization wait times. However, because 214/HCLK or
more is needed for the PLL clock oscillation stabilization wait time, set "10B" or "11B" to the
"CKSCR: WS1, WS0" bit.
■ Switching the Clock Mode
When switching the clock mode, do not switch to the other clock mode or low-power
consumption mode until the switching is completed. The completion of switching can be
checked by referring to the MCM bit and the SCM bit in the clock selection register (CKSCR).
Before the switching is completed, if a switching to the other clock mode or low-power
consumption mode is performed, the switching may have no effect.
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6.8 Notes on Using the Low-power Consumption Mode
MB90930 Series
■ Notes on Accessing to the Low-power Consumption Mode Control Register
(LPMCR) for the Transition to the Standby Mode
● When the low-power consumption mode control register (LPMCR) is accessed with the
assembler language:
• When the setting for the transition to the standby mode is made in the low-power
consumption mode control register (LPMCR), use the instructions in Table 6.3-2.
• The following
command string must be allocated immediately after using the lowpower consumption mode transition instructions in Table 6.3-2.
MOV LPMCR, #H'xx; Low-power Consumption Mode Transition Instruction in Table 6.3-2
NOP
NOP
JMP $+3
; Jump to next instruction
MOV A, #H'10; Any instruction
If a
command string other than shown in is allocated, operations after the standby
mode is canceled will not be assured.
● When the low-power consumption mode control register (LPMCR) is accessed with the C
language.
When the setting for the transition to the standby mode is performed in the low-power
consumption mode control register (LPMCR), access with one of the following method of (1)
to (3):
(1) Making the instruction for the transition to the standby mode to a function, insert two of
the built-in function of __wait_nop(). If there is a possibility that an interrupt other than the
interrupt of the return to the standby is generated within the function, execute an
optimization at compile time to prevent the generation of LINK/UNLINK instruction.
Example: watch mode or time-base timer mode transition function
void enter_watch(){
IO_LPMCR.byte = 0x10; /* Set "0" to the TMD bit in LPMCR */
__wait_nop();
__wait_nop();
}
(2) Write the instruction for the transition to the standby mode with __asm statement, and
insert two NOP instructions and a JMP instruction after the instruction for the transition to
the standby mode.
Example: The transition to the sleep mode
__asm("MOV I:_IO_LPMCR, #H'58);
/* Set "1" to the SLP bit in LPMCR */
__asm("NOP");
__asm("NOP");
__asm("JMP $+3");
/* Jump to next instruction */
(3) Write the instruction for the transition to the standby mode between #pragma asm and
#pragma endasm, and insert two NOP instructions and a JMP instruction after the
instruction for the transition to the standby mode.
Example: The transition to the stop mode
#pragma asm
MOV I:_IO_LPMCR, #H'98
NOP
NOP
JMP $+3
#pragma endasm
CM44-10150-1E
/* Set "1" to the STP bit in LPMCR */
/* Jump to next instruction */
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6.8 Notes on Using the Low-power Consumption Mode
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CM44-10150-1E
CHAPTER 7
MODE SETTING
This chapter explains the operation mode and
memory access mode.
7.1 Mode Setting
7.2 Mode Pins (MD2 to MD0)
7.3 Mode Data
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CHAPTER 7 MODE SETTING
7.1 Mode Setting
7.1
MB90930 Series
Mode Setting
F2MC-16LX has various modes for access methods and access areas.Each
mode is set according to the setting of mode pins at reset and the modefetched mode data.
■ Mode Setting
In the F2MC-16LX, various modes are provided for access methods and access area, and in this
module, those modes are classified as shown in Figure 7.1-1.
Figure 7.1-1 Classification of Modes
Operation mode
RUN mode
Bus mode
Single chip mode
Flash programming mode
■ Operation Mode
The operation mode refers to a mode that controls the operation states of devices. It is specified
with the contents of the mode pins (MD2 to MD0) and Mx bit in the mode data. A normal
operation can be started with selecting an operation mode.
■ Bus Mode
The bus mode refers to a mode that controls the operations of internal ROM and external
access function. It is specified with the contents of the mode pins (MD2 to MD0) and Mx bit in
the mode data. The mode pins (MD2 to MD0) specifies the bus mode for reading the reset
vector and mode data, and the Mx bit in mode data specifies the bus mode in normal
operations.
■ RUN Mode
The RUN mode means the CPU operation mode. The RUN mode has the main clock mode,
PLL clock mode, and various low-power consumption mode. See Section "CHAPTER 6 LOWPOWER CONSUMPTION MODE" for details.
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7.2 Mode Pins (MD2 to MD0)
MB90930 Series
7.2
Mode Pins (MD2 to MD0)
Mode pins are three external pins of MD2 to MD0, and they specify load
methods for reset vectors and mode data.
■ Mode Pins (MD2 to MD0)
The mode pins allow to select the external data bus or internal data bus for reading reset vectors
and select the bus width upon the external data bus. For the internal Flash memory products,
the mode pins specify the Flash memory write mode to write the internal Flash memory
program and others. Table 7.2-1 shows the mode pin setting.
Table 7.2-1 Mode Pin Setting
MD2
MD1
MD0
Mode name
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Flash serial write mode
1
1
1
Flash writer write mode
Reset vectors
access area
External data
bus width
Remarks
Setting prohibited
Internal vector mode
Internal
Mode
data
Operation after reset sequence is
controlled with mode data.
Setting prohibited
-
-
-
Set MD2 to MD0: 0=Vss, 1=Vcc.
Note:
In the MB90930 series, the mode pins are used in the single chip mode only. Therefore,
set the MD2 to MD0 to "011B".
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CHAPTER 7 MODE SETTING
7.3 Mode Data
7.3
MB90930 Series
Mode Data
Mode data is stored at "FFFFDFH" of memory and specifies the operation after
a reset sequence.The data is fetched to a CPU automatically.
■ Mode Data
While a reset sequence is executed, mode data in "FFFFDFH" address is fetched and stored in the
mode register in the CPU core. The CPU set the memory access mode with this mode data. The
mode register value can be changed by a reset sequence only. The setting of the mode data is
valid after the reset sequence. Figure 7.3-1 shows the configuration of mode data.
Figure 7.3-1 Mode Data Configuration
bit
Mode data
7
6
5
4
3
2
1
0
M1 M0 0
0
0
0
0
0
Bits for extending functions (reserved area)
Bits for setting bus mode
■ Bus Mode Setting Bits
These bits specify the operation mode after the reset sequence is completed. Table 7.3-1 shows
the relationship between each bit and the functions.
Table 7.3-1 Bus Mode Setting Bits and Functions
M1
M0
0
0
0
1
1
0
1
1
Function
Single chip mode
(Setting prohibited)
Note:
In the MB90930 series, the mode data is used in th e single chip mode only. Therefore,
set the M1 and MD0 to "00B".
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7.3 Mode Data
MB90930 Series
Figure 7.3-2 shows the correspondence between the access areas and physical addresses in the
single chip mode.
Figure 7.3-2 Correspondence between Access Areas and Physical Addresses in Single Chip
Mode
000000H
000000H
Peripheral area
0000F0H
000100H
Peripheral area
Register
0000F0H
000100H
RAM area
RAM area
Address #2
003700H
003700H
Peripheral area
004000H
008000H
010000H
Register
Peripheral area
004000H
RAM area
(16 Kbytes)
ROM area
(FF bank image)
Address #1
008000H
010000H
ROM area
(FF bank image)
Address #1
ROM area*
ROM area*
FFFFFFH
: Internal access memory
: access prohibited
FFFFFFH
MB90V930-102/MB90V930-101
(Evaluation product)
MB90F931/MB90F931S (Flash memory product)
MB90931/MB90931S (Mask ROM product)
Product type
Address #1
Address #2
MB90F931/MB90F931S
(Flash memory product 128KB)
FE0000H
002100H
MB90931/MB90931S (MASK ROM product 128 KB)
FE0000H
-
002100H
003700H
MB90V930-102/MB90V930-101
* : The evaluation product does not have built-in ROM. It should be regarded as a ROM decode
area at the tool side.
■ Relationship between Mode Pins and Mode Data
Table 7.3-2 shows the relationship between mode pins and mode data.
Table 7.3-2 Relationship between Mode Pins and Mode Data
Mode
MD2
MD1
MD0
M1
M0
Single chip mode
0
1
1
0
0
Note:
In the MB90930 series, mode pins are used in the single chip mode only.
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CHAPTER 7 MODE SETTING
7.3 Mode Data
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MB90930 Series
CM44-10150-1E
CHAPTER 8
I/O PORTS
This chapter describes the functions and
operations of the I/O ports.
8.1 I/O Ports
8.2 Assignment of Registers and Pins Shared with External
Pins
8.3 Port 0
8.4 Port 1
8.5 Port 2
8.6 Port 3
8.7 Port 4
8.8 Port 5
8.9 Port 6
8.10 Port 7
8.11 Port 8
8.12 Port 9
8.13 Port C
8.14 Port D
8.15 Port E
8.16 Input Level Select Registers (PIL0 to PIL2)
8.17 Sample Program for I/O Ports
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CHAPTER 8 I/O PORTS
8.1 I/O Ports
8.1
MB90930 Series
I/O Ports
The I/O ports can be used as general-purpose I/O ports (parallel I/O ports). The
number of ports for the MB90930 series is 13 ports (93 pins). Each port is used
both for peripheral functions and for providing input/output pins.
■ I/O Port Functions
The I/O ports use the port data register (PDR) to receive data from the CPU and then output it
to the I/O pins or to obtain the input signals from the I/O pins and then write it to the CPU. The
port also uses the port direction register (DDR) to set the I/O pin's input/output direction in
units of individual bits. The functions of each port/peripheral function are listed below
• Port 0:
Used as a general-purpose I/O port or for peripheral functions (LCD)
• Port 1:
Used as a general-purpose I/O port or for peripheral functions (PPG/Reload timer/ICU/
Real-time watch timer)
• Port 2:
Used as a general-purpose I/O port or for peripheral functions (LCD)
• Port 3:
Used as a general-purpose I/O port or for peripheral functions (LCD)
• Port 4:
Used as a general-purpose I/O port or for peripheral functions (LCD)
• Port 5:
Used as a general-purpose I/O port or for peripheral functions (External interrupt input pin/
CAN/Sound generator/ADC trigger input pin/Free-run timer clock input)
• Port 6:
Used as a general-purpose I/O port or for peripheral functions (Analog input pin)
• Port 7:
Used as a general-purpose I/O port or for peripheral functions (Stepping motor controller/
Analog input pin)
• Port 8:
Used as a general-purpose I/O port or for peripheral functions (Stepping motor controller/
Analog input pin)
• Port 9:
Used as a general-purpose I/O port or for peripheral functions (LCD)
• Port C:
Used as a general-purpose I/O port or for peripheral functions (External interrupt input pin/
LIN-UART/PPG)
• Port D:
Used as a general-purpose I/O port or for peripheral functions (LIN-UART)
• Port E:
Used as a general-purpose I/O port or for peripheral functions (Reload timer/Sound
generator/ICU)
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CHAPTER 8 I/O PORTS
8.1 I/O Ports
MB90930 Series
Table 8.1-1 shows the list of functions of each port.
Table 8.1-1 List of Functions of Each Port (1 / 2)
Port
name
Port 0
Pin name
Output
format
Input format
P00/SEG24 to
P07/SEG31
Function
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Generalpurpose I/O
port
P07
P06
P05
P04
P03
P02
P01
P00
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
-
-
-
-
-
-
-
-
-
-
P15
P14
P13
P12
P11
P10
-
-
IN0
IN1
PPG5
PPG4
PPG3
PPG2
-
-
-
TIN2
-
TIN0
IN4
IN5
-
-
-
-
-
-
TOT0
-
Generalpurpose I/O
port
P27
P26
P25
P24
P23
p22
-
-
Peripheral
function
SEG05
SEG04
SEG03
SEG02
SEG01
SEG0
-
-
Generalpurpose I/O
port
P37
P36
P35
P34
P33
P32
P31
P30
Peripheral
function
SEG13
SEG12
SEG11
SEG10
SEG09
SEG08
SEG07
SEG06
Generalpurpose I/O
port
P47
P46
P45
P44
P43
P42
P41
P40
Peripheral
function
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
Generalpurpose I/O
port
P57
P56
P55
P54
P53
P52
P51
P50
SGA0
SGO0
INT2
SGA1
INT3
TX1
INT1
INT0
IN4R
FRCK
-
IN2R
-
-
RX1
ADTG
-
IN5R
-
-
-
-
-
-
Generalpurpose I/O
port
P67
P66
P65
P64
P63
P62
P61
P60
Peripheral
function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Peripheral
function
Generalpurpose I/O
port
Port 1
P10/PPG2 to
P15/IN0
Peripheral
function
Port 2
P22/SEG00 to
P27/SEG05
CMOS
(Hysteresis)
(Automotive level*)
Port 3
Port 4
Port 5
CMOS
P30/SEG06 to
P37/SEG13
P40/SEG14 to
P47/SEG21
P50/INT0 to
P57/SGA0
Peripheral
function
Port 6
P60/AN0 to
P67/AN7
CM44-10150-1E
Analog CMOS
(Hysteresis)
(Automotive level*)
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CHAPTER 8 I/O PORTS
8.1 I/O Ports
MB90930 Series
Table 8.1-1 List of Functions of Each Port (2 / 2)
Port
name
Port 7
Port 8
Port 9
Pin name
Output
format
Input format
P70/PWM1P0
to P77/
PWM2M1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Generalpurpose
output port
P77
P76
P75
P74
P73
P72
P71
P70
Peripheral
function
Generalpurpose
output port
P80/PWM1P2
to P87/
PWM2M3
Peripheral
function
P90/SEG22 to
P96/SEG23
CMOS
(Hysteresis)
(Automotive level*)
Port C
Function
CMOS
Port E
AN13
AN12
AN11
AN10
AN9
AN8
P87
P86
P85
P84
P83
P82
P81
P80
PWM2M PWM2P PWM1M PWM1P PWM2M PWM2P PWM1M PWM1P
3
3
3
3
2
2
2
2
AN21
AN20
AN19
AN18
AN17
AN16
Generalpurpose I/O
port
-
P96
P95
P94
P93
P92
P91
P90
Peripheral
function
-
V2
V1
V0
-
-
SEG23
SEG22
Generalpurpose I/O
port
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PPG1
PPG0
SCK1
SOT1
SIN1
SCK0
SOT0
SIN0
TIN1
TOT1
TRG
-
INT7
INT6
INT5
INT4
IN6
IN7
-
-
-
IN2
IN3
-
-
PD6
PD5
PD4
PD3
PD2
PD1
PD0
-
TOT2
SCK3
SOT3
SIN3
SCK2
SOT2
SIN2
-
-
-
-
-
-
-
-
-
-
-
-
-
PE2
PE1
PE0
-
-
-
-
-
SGO1
TIN3
TOT3
-
-
-
-
-
IN3R
IN6R
IN7R
Generalpurpose I/O
port
Peripheral
function
PE0/TOT3 to
PE2/SGO1
AN14
AN22
Peripheral
function
Port D
AN15
AN23
PC0/SIN0 to
PC7/PPG1
PD0/SIN2 to
PD6/TOT2
PWM2M PWM2P PWM1M PWM1P PWM2M PWM2P PWM1M PWM1P
1
1
1
1
0
0
0
0
Generalpurpose I/O
port
Peripheral
function
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
Note:
Port 6/7/8 is also u sed as an analog in put pin. If using th e por t a s a gen eral-purpose port,
always set the corresponding analog input enable register (ADER6/7/8) bit to "0". At a reset,
the ADER6/7/8 bit is initialized to "1".
P94 t o P96 of po rt 9 h as LCD co ntroller/driver r eference p ower supp ly pins V0 t o V2
enabled in the initial state.
To use t hese por ts a s g eneral-purpose p orts, se t th e cor responding b its in th e LCD
output control register (LOCR3) to "0".
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CHAPTER 8 I/O PORTS
8.2 Assignment of Registers and Pins Shared with External Pins
MB90930 Series
8.2
Assignment of Registers and Pins Shared with
External Pins
The registers related to I/O port setting are listed
■ List of I/O Port Registers
Table 8.2-1 shows the list of registers of each port.
Table 8.2-1 List of Registers of Each Port (1 / 2)
Register name
Read/write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
--XXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXX--B
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
XXXXXXXXB
Port 9 data register (PDR9)
R/W
000009H
-XXXXXXXB
Port C data register (PDRC)
R/W
00000CH
XXXXXXXXB
Port D data register (PDRD)
R/W
00000DH
-XXXXXXXB
Port E data register (PDRE)
R/W
00000EH
-----XXXB
Port 0 direction register (DDR0)
R/W
000010H
00000000B
Port 1 direction register (DDR1)
R/W
000011H
--000000B
Port 2 direction register (DDR2)
R/W
000012H
000000--B
Port 3 direction register (DDR3)
R/W
000013H
00000000B
Port 4 direction register (DDR4)
R/W
000014H
00000000B
Port 5 direction register (DDR5)
R/W
000015H
00000000B
Port 6 direction register (DDR6)
R/W
000016H
00000000B
Port 7 direction register (DDR7)
R/W
000017H
00000000B
Port 8 direction register (DDR8)
R/W
000018H
00000000B
Port 9 direction register (DDR9)
R/W
000019H
-0000000B
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CHAPTER 8 I/O PORTS
8.2 Assignment of Registers and Pins Shared with External Pins
MB90930 Series
Table 8.2-1 List of Registers of Each Port (2 / 2)
Register name
Read/write
Address
Initial value
Port C direction register (DDRC)
R/W
00001CH
00000000B
Port D direction register (DDRD)
R/W
00001DH
-0000000B
Port E direction register (DDRE)
R/W
00001EH
-----000B
Analog input enabling register (ADER6)
R/W
00001AH
11111111B
Analog input enabling register (ADER7)
R/W
00001BH
11111111B
Analog input enabling register (ADER8)
R/W
00001FH
11111111B
R/W:Readable/Writable
X: Undefined value
-:
Undefined
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CHAPTER 8 I/O PORTS
8.3 Port 0
MB90930 Series
8.3
Port 0
Port 0 is a general-purpose I/O port that is also used for peripheral function I/O
port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 0.
■ Port 0 Configuration
Port 0 consists of the following three elements:
• General-purpose I/O pins and peripheral function input/output pins (P00/SEG24 to P07/
SEG31)
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
■ Port 0 Pins
The I/O pins of Port 0 are also used for peripheral function I/O pins. If used as peripheral
function I/O pins, they must not be used as general purpose I/O ports. Table 8.3-1 shows the
pins of Port 0.
Table 8.3-1 Port 0 Pins
Port name
Port 0
Pin name
Port function
Peripheral
function
P00/SEG24 P00
SEG24
P01/SEG25 P01
SEG25
P02/SEG26 P02
SEG26
Type of input/output
Input
Output
P03/SEG27 P03 GeneralSEG27
CMOS Hysteresis/
CMOS
LCDC
purpose
I/O
Automotive level*
P04/SEG28 P04
SEG28
P05/SEG29 P05
SEG29
P06/SEG30 P06
SEG30
P07/SEG31 P07
SEG31
Circuit
type
F
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.3 Port 0
MB90930 Series
■ Pin Block Diagram for Port 0
Figure 8.3-1 shows the pin block diagram for Port 0.
Figure 8.3-1 Pin Block Diagram for Port 0
Peripheral function output
Peripheral function
output enabled
PDR (Port data register)
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
Note:
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is
forced to work as a peripheral function output irrespective of the DDR0 register value.
■ Registers for Port 0
The Port 0 registers are PDR0 and DDR0. The register bits have a one-to-one correspondence
with the Port 0 pins. Table 8.3-2 shows the correspondence between registers and pins for Port
0.
Table 8.3-2 Correspondence between Registers and Pins for Port 0
Port name
Bit of related register and its corresponding pin
PDR0, DDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
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CHAPTER 8 I/O PORTS
8.3 Port 0
MB90930 Series
8.3.1
Port 0 Registers (PDR0, DDR0)
This section describes the registers for Port 0.
■ Functions of Port 0 Registers
● Port 0 data register (PDR0)
The PDR0 register indicates the pin states.
● Port 0 direction register (DDR0)
The DDR0 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0"
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDR0 register's setting.
Table 8.3-3 Functions of Port 0 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is Sets the output buffer to
"0"
"OFF" to be an input port
1
Direction latch is Sets the output buffer to
"1"
"ON" to be an output port
0
Port 0 data register
(PDR0)
Port 0 direction
register (DDR0)
R/W
Address
Initial value
R/W 000000H XXXXXXXXB
R/W 000010H 00000000B
R/W: Readable/Writable
X: Undefined value
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CHAPTER 8 I/O PORTS
8.3 Port 0
8.3.2
MB90930 Series
Description of Port 0 Operation
This section describes the operation of Port 0.
■ Operation of Port 0
● Operation as an output port
With the corresponding DDR0 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR0 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR0 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR0 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR0 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR0 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR0 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the value of the DDR0 register is cleared. Thus, all the output buffers are set to
"OFF" (input port) and the pins are set to high impedance.
In a reset operation, the PDR0 register is not initialized. Therefore, if used as an output port,
write the output data into the PDR0 register and then set the corresponding DDR0 register to
"1".
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CHAPTER 8 I/O PORTS
8.3 Port 0
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR0 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.3-4 shows the pin states of Port 0.
Table 8.3-4 Pin States of Port 0
Pin name
Normal
operation
Sleep mode
P00/SEG24 to
P07/SEG31
General-purpose
I/O port
General-purpose
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High-impedance
Table 8.3-5 Priority of Pin Output of Port 0
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P00/SEG24
SEG24
P00
-
-
P01/SEG25
SEG25
P01
-
-
P02/SEG26
SEG26
P02
-
-
P03/SEG27
SEG27
P03
-
-
P04/SEG28
SEG28
P04
-
-
P05/SEG29
SEG29
P05
-
-
P06/SEG30
SEG30
P06
-
-
P07/SEG31
SEG31
P07
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.4 Port 1
8.4
MB90930 Series
Port 1
Port 1 is a general-purpose I/O port that is also used for a peripheral function
input port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams
of pins, and registers for Port 1.
■ Port 1 Configuration
Port 1 consists of the following three elements:
• General-purpose I/O pins and external interrupt input pins (P10/PPG2/IN5 to P15/IN0)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
■ Port 1 Pins
The pins of Port 1 are also used for peripheral function I/O pins. If used as peripheral function
I/O pins, they must not be used as general purpose I/O ports. Table 8.4-1 shows the pins of Port
1.
Table 8.4-1 Port1 Pins
Port name
Pin name
P10/PPG2/IN5
Port function
P10
P11/TOT0/PPG3/IN4 P11
Peripheral function
PPG2 PPG
IN5
ICU
TOT0
IN4
ICU
PPG3 PPG
RLT
P12/TIN0/PPG4
P12
P13/PPG5
P13
P14/TIN2/IN1
P14
P15/IN0
P15
Port 1
Generalpurpose I/O
TIN0
PPG4 PPG
PPG5 PPG
TIN2
RLT
Type of input/output
Circuit
type
CMOS
Hysteresis/
CMOS
Automotive
*
level
I
RTC
IN1
ICU
IN0
: Function enabled in the initial state
* : Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet
("3. DC Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.4 Port 1
MB90930 Series
■ Pin Block Diagram for Port 1
Figure 8.4-1 shows the pin block diagram for Port 1.
Figure 8.4-1 Pin Block Diagram for Port 1
Peripheral
function input
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port 1
The Port 1 registers are PDR1 and DDR1. The register bits have a one-to-one correspondence
with the Port 1 pins. Table 8.4-2 shows the correspondence between registers and pins for Port
1.
Table 8.4-2 Correspondence between Registers and Pins for Port 1
Port name
Bit of related register and its corresponding pin
PDR1, DDR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
-
-
P15
P14
P13
P12
P11
P10
Port 1
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CHAPTER 8 I/O PORTS
8.4 Port 1
8.4.1
MB90930 Series
Port 1 Registers (PDR1, DDR1)
This section describes the registers for Port 1.
■ Functions of Port 1 Registers
● Port 1 data register (PDR1)
The PDR1 register indicates the pin states.
● Port 1 direction register (DDR1)
The DDR1 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Notes:
• When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction c orresponding t o t he p in i s s et t o " enabled", t he p in w orks a s a
peripheral function output pin irrespective of the DDR1 register's setting.
• If a peripheral fu nction wit h an input pin is us ed, se t th e DD R1 register bit
corresponding to each peripheral function's input pin to "0" to make it work as an inp ut
port.
Table 8.4-3 Functions of Port 1 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is Sets the output buffer to
"0"
"OFF" to be an input port
1
Direction latch is Sets the output buffer to
"1"
"ON" to be an output port
0
Port 1 data register
(PDR1)
Port 1 direction
register (DDR1)
R/W
Address
Initial value
R/W
000001H
--XXXXXXB
R/W
000011H
--000000B
R/W: Readable/Writable
X: Undefined value
- : Undefined
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8.4.2
Description of Port 1 Operation
CHAPTER 8 I/O PORTS
8.4 Port 1
This section describes the operation of Port 1.
■ Operation of Port 1
● Operation as an output port
With the corresponding DDR1 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR1 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR1 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR1 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR1 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR1 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR1 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Operation as a peripheral function input
For a port that is also used for peripheral function input, the pin value is always used as input to
the peripheral function. To use an external signal as input for the peripheral function, set the
DDR1 register for the input port to "0".
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CHAPTER 8 I/O PORTS
8.4 Port 1
MB90930 Series
● Reset operation
At CPU reset, the DDR1 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and also as the pull-up resistor is cut, the pins are set to "high-impedance".
In a reset operation, the PDR1 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR1 register and then set the corresponding DDR1 register to "1".
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set
to high impedance. This is because, irrespective of the DDR1 register value, the output buffer
is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.4-4 shows the pin states of Port 1.
Table 8.4-4 Pin States of Port 1
Normal
operation
Pin name
Sleep mode
P10/PPG2 /IN5 General-purpose General-purpose
to P15/IN0
I/O port
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port
in st op mod e o r t ime-base t imer mo de, di sable t he ou tput of pe ripheral functions, and
then set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
Table 8.4-5 Priority of Pin Output of Port 1
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P10/PPG2/IN5
PPG2
P10
-
-
P11/TOT0/PPG3/IN4
PPG3
TOT0
P11
-
P12/TIN0/PPG4
PPG4
P12
-
-
P13/PPG5
PPG5
P13
-
-
P14/TIN2/IN1
P14
-
-
-
P15/IN0
P15
-
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.5 Port 2
MB90930 Series
8.5
Port 2
Port 2 is a general-purpose I/O port that is also used for peripheral function I/O
port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as a
general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 2.
■ Port 2 Configuration
Port 2 consists of the following three elements:
• General-purpose I/O pins and peripheral function input/output pins (P22/SEG00 to P27/
SEG05)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
■ Port 2 Pins
The I/O pins of Port 2 are also used for peripheral function I/O pins. If used as peripheral
function I/O pins, they must not be used as general purpose I/O ports. Table 8.5-1 shows the
pins of Port 2.
Table 8.5-1 Port 2 Pins
Port name
Pin name
Peripheral
function
Port function
P22/SEG00
P22
SEG00
P23/SEG01
P23
SEG01
P24/SEG02
P24
P25/SEG03
General SEG02
P25 Purpose I/O SEG03
P26/SEG04
P26
SEG04
P27/SEG05
P27
SEG05
Port 2
LCDC
Type of input/output
Input
Output
CMOS Hysteresis/
CMOS
Automotive level*
Circuit
type
F
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.5 Port 2
MB90930 Series
■ Pin Block Diagram for Port 2
Figure 8.5-1 shows the pin block diagram for Port 2.
Figure 8.5-1 Pin Block Diagram for Port 2
Peripheral
function output
PDR (Port data register)
LCD output
Peripheral function
output enabled
P-ch
PDR read
Internal data bus
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
Note:
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is
forced to work as a peripheral function output irrespective of the DDR2 register value.
■ Registers for Port 2
The Port 2 registers are PDR2 and DDR2. The register bits have a one-to-one correspondence
with the Port 2 pins. Table 8.5-2 shows the correspondence between registers and pins for Port
2.
Table 8.5-2 Correspondence between Registers and Pins for Port 2
Port name
Bit of related register and its corresponding pin
PDR2, DDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
-
-
Port 2
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8.5.1
Port 2 Data Register (PDR2, DDR2)
CHAPTER 8 I/O PORTS
8.5 Port 2
This section describes the registers for Port 2.
■ Functions of Port 2 Registers
● Port 2 data register (PDR2)
The PDR2 register indicates the pin states.
● Port 2 direction register (DDR2)
The DDR2 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDR2 register's setting.
Table 8.5-3 Functions of Port 2 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is
"0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch is
"1"
Sets the output buffer to
"ON" to be an output port
0
Port 2 data register
(PDR2)
Port 2 direction
register (DDR2)
R/W
Address
Initial value
R/W
000002H
XXXXXX--B
R/W
000012H
000000--B
R/W: Readable/Writable
X: Undefined value
- : Undefined
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CHAPTER 8 I/O PORTS
8.5 Port 2
8.5.2
MB90930 Series
Description of Port 2 Operation
This section describes the operation of Port 2.
■ Operations of Port 2
● Operation as an output port
With the corresponding DDR2 register bit set to "1", the port works as an output port.
When used as an output port, if data is written to the PDR2 register, it is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR2 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR2 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR2 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR2 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR2 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDR2 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDR2 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR2 register and then set the corresponding DDR2 register to "1".
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CHAPTER 8 I/O PORTS
8.5 Port 2
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR2 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.5-4 shows the pin states of Port 2.
Table 8.5-4 Pin States of Port 2
Normal
operation
Pin name
P22/SEG00 to
P27/SEG05
Sleep mode
General-purpose General-purpose
I/O port
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.5-5 Priority of Pin Output of Port 2
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P22/SEG00
SEG00
P22
-
-
P23/SEG01
SEG01
P23
-
-
P24/SEG02
SEG02
P24
-
-
P25/SEG03
SEG03
P25
-
-
P26/SEG04
SEG04
P26
-
-
P27/SEG05
SEG05
P27
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.6 Port 3
8.6
MB90930 Series
Port 3
Port 3 is a general-purpose I/O port that is also used for peripheral function I/O
port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 3.
■ Port 3 Configuration
Port 3 consists of the following three elements:
• General-purpose I/O pins and peripheral function input/output pins (P30/SEG06 to P37/
SEG13)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
■ Port 3 Pins
The I/O pins of Port 3 are also used for peripheral function I/O pins. If used as peripheral
function I/O pins, they must not be used as general purpose I/O ports. Table 8.6-1 shows the
pins of Port 3.
Table 8.6-1 Port 3 Pins
Port name
Pin name
Peripheral
function
Port function
P30/SEG06
P30
SEG06
P31/SEG07
P31
SEG07
P32/SEG08
P32
SEG08
P33/SEG09
P33
P34/SEG10
P34
P35/SEG11
P35
SEG11
P36/SEG12
P36
SEG12
P37/SEG13
P37
SEG13
Port 3
Type of input/output
Input
Output
SEG09
General
CMOS Hysteresis/
CMOS
LCDC
Purpose I/O SEG10
Automotive level*
Circuit
type
F
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.6 Port 3
MB90930 Series
■ Pin Block Diagram for Port 3
Figure 8.6-1 shows the pin block diagram for Port 3.
Figure 8.6-1 Pin Block Diagram for Port 3
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
PDR read
Internal data bus
LCD output
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
Note:
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is
forced to work as a peripheral function output irrespective of the DDR3 register value.
■ Registers for Port 3
The Port 3 registers are PDR3 and DDR3. The register bits have a one-to-one correspondence
with the Port 3 pins. Table 8.6-2 shows the correspondence between registers and pins for Port
3.
Table 8.6-2 Correspondence between Registers and Pins for Port 3
Port name
Bit of related register and its corresponding pin
PDR3, DDR3
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P37
P36
P35
P34
P33
P32
P31
P30
Port 3
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CHAPTER 8 I/O PORTS
8.6 Port 3
8.6.1
MB90930 Series
Port 3 Registers (PDR3, DDR3)
This section describes the registers for Port 3.
■ Functions of Port 3 Registers
● Port 3 data register (PDR3)
The PDR3 register indicates the pin states.
● Port 3 direction register (DDR3)
The DDR3 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDR3 register's setting.
Table 8.6-3 Functions of Port 3 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is
"0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch is
"1"
Sets the output buffer to
"ON" to be an output port
0
Port 3 data register
(PDR3)
Port 3 direction
register (DDR3)
R/W
Address
Initial value
R/W
000003H
XXXXXXXXB
R/W
000013H
00000000B
R/W: Readable/Writable
X: Undefined value
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8.6.2
Description of Port 3 Operation
CHAPTER 8 I/O PORTS
8.6 Port 3
This section describes the operation of Port 3.
■ Operation of Port 3
● Operation as an output port
With the corresponding DDR3 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR3 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR3 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR3 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR3 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR3 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR3 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDR3 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDR3 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR3 register and then set the corresponding DDR3 register to "1".
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CHAPTER 8 I/O PORTS
8.6 Port 3
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR3 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.6-4 shows the pin states of Port 3.
Table 8.6-4 Pin States of Port 3
Pin name
Normal
operation
Sleep mode
P30/SEG06 to General-purpose General-purpose
P37/SEG13
I/O port
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.6-5 Priority of Pin Output of Port 3
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P30/SEG06
SEG06
P30
-
-
P31/SEG07
SEG07
P31
-
-
P32/SEG08
SEG08
P32
-
-
P33/SEG09
SEG09
P33
-
-
P34/SEG10
SEG10
P34
-
-
P35/SEG11
SEG11
P35
-
-
P36/SEG12
SEG12
P36
-
-
P37/SEG13
SEG13
P37
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.7 Port 4
MB90930 Series
8.7
Port 4
Port 4 is a general-purpose I/O port that is also used for a peripheral function
I/O port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 4.
■ Port 4 Configuration
Port 4 consists of the following three elements:
• General-purpose I/O pins and peripheral function input/output pins (P40/SEG14 to P47/
SEG21)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Port 4 Pins
The I/O pins of Port 4 are also used for peripheral function I/O pins. If used as peripheral
function I/O pins, they must not be used as general purpose I/O ports. Table 8.7-1 shows the
pins of Port 4.
Table 8.7-1 Port 4 Pins
Port name
Pin name
Port function
Peripheral
function
P40/SEG14 P40
SEG14
P41/SEG15 P41
SEG15
P42/SEG16 P42
SEG16
P43/SEG17 P43
Port 4
P44/SEG18 P44
Generalpurpose I/O
SEG17
LCDC
SEG18
P45/SEG19 P45
SEG19
P46/SEG20 P46
SEG20
P47/SEG21 P47
SEG21
Type of input/output
Input
Output
CMOS Hysteresis/
CMOS
Automotive level*
Circuit
type
F
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.7 Port 4
MB90930 Series
■ Pin Block Diagram for Port 4
Figure 8.7-1 shows the pin block diagram for Port 4.
Figure 8.7-1 Pin Block Diagram for Port 4
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
PDR read
Internal data bus
LCD output
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
Note:
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is
forced to work as a peripheral function output irrespective of the DDR4 register value.
■ Registers for Port 4
The Port 4 registers are PDR4 and DDR4. The register bits have a one-to-one correspondence
with the Port 4 pins. Table 8.7-2 shows the correspondence between registers and pins for Port
4.
Table 8.7-2 Correspondence between Registers and Pins for Port 4
Port name
Bit of related register and its corresponding pin
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
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8.7 Port 4
MB90930 Series
8.7.1
Port 4 Registers (PDR4, DDR4)
This section describes the registers for Port 4.
■ Functions of Port 4 Registers
● Port 4 data register (PDR4)
The PDR4 register indicates the pin states.
● Port 4 direction register (DDR4)
The DDR4 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDR4 register's setting.
Table 8.7-3 Functions of Port 4 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is Sets the output buffer to
"0"
"OFF" to be an input port
1
Direction latch is Sets the output buffer to
"1"
"ON" to be an output port
0
Port 4 data register
(PDR4)
Port 4 direction
register (DDR4)
R/W
Address
Initial value
R/W
000004H
XXXXXXXXB
R/W
000014H
00000000B
R/W: Readable/Writable
X : Undefined value
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8.7 Port 4
8.7.2
MB90930 Series
Description of Port 4 Operation
This section describes the operation of Port 4.
■ Operation of Port 4
● Operation as an output port
With the corresponding DDR4 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR4 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR4 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR4 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR4 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR4 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR4 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDR4 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDR4 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR4 register and then set the corresponding DDR4 register to "1".
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8.7 Port 4
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR4 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.7-4 shows the pin states of Port 4.
Table 8.7-4 Pin States of Port 4
Normal
operation
Pin name
P40/SEG14 to
P47/SEG21
Sleep mode
General-purpose General-purpose
I/O port
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.7-5 Priority of Pin Output of Port 4
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P40/SEG14
SEG14
P40
-
-
P41/SEG15
SEG15
P41
-
-
P42/SEG16
SEG16
P42
-
-
P43/SEG17
SEG17
P43
-
-
P44/SEG18
SEG18
P44
-
-
P45/SEG19
SEG19
P45
-
-
P46/SEG20
SEG20
P46
-
-
P47/SEG21
SEG21
P47
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.8 Port 5
8.8
MB90930 Series
Port 5
Port 5 is a general-purpose I/O port that is also used for a peripheral function
I/O port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 5.
■ Port 5 Configuration
Port 5 consists of the following three elements:
• General-purpose I/O pins and peripheral function input pins (P50/INT0/ADTG to P57/
SGA0/IN4R)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
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8.8 Port 5
MB90930 Series
■ Port 5 Pins
The I/O pins of Port 5 are also used for peripheral function input pins. Therefore, if used as
peripheral function input/output pins, they must not be used as general-purpose I/O ports.
Table 8.8-1 shows the pins of Port 5.
Table 8.8-1 Port 5 Pins
Port
name
Pin
name
Port function
Type of input/
output
Peripheral function
Input
P50/
INT0/
ADTG
P50
INT0
P51/
INT1/
RX1
P51
INT1 External RX1
interrupt
P52/TX1 P52
Port 5
Circuit
type
Output
ADTG A/D
-
CAN1
TX1
P53/
INT3
P53
P54/
SGA1/
IN2R
GeneralSGA
P54 purpose
SG
1
I/O
P55/
INT2
P55
INT2
P56/
SGO0/
FRCK/
IN5R
P56
SGO
0
P57/
SGA0/
IN4R
P57
INT3
-
CMOS
Hysteresis/
CMOS
Automotive
level*
IN2R ICU
I
External
interrupt
FRCK FRT
IN5
ICU
R
SG
SGA
0
IN4R ICU
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.8 Port 5
MB90930 Series
■ Pin Block Diagram for Port 5
Figure 8.8-1 shows the pin block diagram for Port 5.
Figure 8.8-1 Pin Block Diagram for Port 5
Peripheral
function input
Peripheral
function output
Peripheral function
output enabled
PDR (Port data register)
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port 5
The Port 5 registers are PDR5 and DDR5. The register bits have a one-to-one correspondence
with the Port 5 pins. Table 8.8-2 shows the correspondence between registers and pins for Port
5.
Table 8.8-2 Correspondence between Registers and Pins for Port 5
Port name
Bit of related register and its corresponding pin
PDR5, DDR5
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P57
P56
P55
P54
P53
P52
P51
P50
Port 5
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8.8 Port 5
MB90930 Series
8.8.1
Port 5 Registers (PDR5, DDR5)
This section describes the registers for Port 5.
■ Functions of Port 5 Registers
● Port 5 data register (PDR5)
The PDR5 register indicates the pin states.
● Port 5 direction register (DDR5)
The DDR5 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Notes:
• When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction c orresponding t o t he p in i s s et t o " enabled", t he p in w orks a s a
peripheral function output pin irrespective of the DDR5 register's setting.
• If a peripheral fu nction wit h an input pin is us ed, se t th e DD R5 register bit
corresponding to each peripheral function's input pin to "0" to make it work as an inp ut
port.
Table 8.8-3 Functions of Port 5 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is Sets the output buffer to
"0"
"OFF" to be an input port
1
Direction latch is Sets the output buffer to
"1"
"ON" to be an output port
0
Port 5 data register
(PDR5)
Port 5 direction
register (DDR5)
R/W
Address
Initial value
R/W 000005H
XXXXXXXXB
R/W 000015H
00000000B
R/W: Readable/Writable
X: Undefined value
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8.8 Port 5
8.8.2
MB90930 Series
Description of Port 5 Operation
This section describes the operation of Port 5.
■ Operation of Port 5
● Operation as an output port
With the corresponding DDR5 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR5 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR5 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDR5 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR5 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR5 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR5 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Operation as a peripheral function input
For a port that is also used for a peripheral function input, the pin value is always set. To use an
external signal as input for the peripheral function, set the DDR5 register for the input port to
"0".
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8.8 Port 5
MB90930 Series
● Reset operation
At CPU reset, the DDR5 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDR5 register is not initialized. Therefore, if used as an output port,
set the output data in the PDR5 register and then set the corresponding DDR5 register to "1".
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR5 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.8-4 shows the pin states of Port 5.
Table 8.8-4 Pin States of Port 5
Stop mode,
time-base timer
mode
(SPL=0)
Stop mode,
time-base timer
mode
(SPL=1)
General-purpose General-purpose
I/O port
I/O port
General-purpose I/O
port
Input cut-off/output
Hi-Z
P50/INT0, P51/INT1,
General-purpose General-purpose
P53/INT3, P55/INT2
(External interrupt being
I/O port
I/O port
set)
General-purpose I/O
port
Input enabled/output
Hi-Z
Pin name
P50/INT0/ADTG to
P57/SGA0
Normal
operation
Sleep mode
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.8-5 Priority of Pin Output of Port 5
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P50/INT0/ADTG
P50
-
-
-
P51/INT1
P51
-
-
-
P52/TX1
TX1
P52
-
-
P53/INT3
P53
-
-
-
SGA1
P54
-
-
P55
-
-
-
P56/SGO0/FRCK/IN5R
SGO0
P56
-
-
P57/SGA0/IN4R
SGA0
P57
-
-
P54/SGA1/IN2R
P55/INT2
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.9 Port 6
8.9
MB90930 Series
Port 6
Port 6 is a general-purpose I/O port that is also used as an analog input of A/D
converter. The use of each pin can be switched per bit between the analog
input and the port. This section mainly describes the function of this port as a
general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 6.
■ Port 6 Configuration
Port 6 consists of the following four elements:
• General-purpose I/O pins and analog input pins (P60/AN0 to P67/AN7)
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Analog input enabling register (ADER6)
■ Port 6 Pins
The Port 6 input/output pins are also used as analog input pins and peripheral function I/O pins
If a pin is used for an analog input, it cannot be used as a general-purpose I/O port. In addition,
if a pin is used for a general-purpose port, do not use it as an analog input pin. Table 8.9-1
shows the Port 6 pins.
Table 8.9-1 Port 6 Pins
Port name Pin name
Port 6
Port function
Peripheral function
P60/AN0/
P60
OUT0
AN0
Analog
input 0
P61/AN1/
P61
OUT1
AN1
Analog
input 1
P62/AN2/
P62
OUT2
AN2
Analog
input 2
AN3
Analog
input 3
AN4
Analog
input 4
P65/AN5/
P65
OUT1R
AN5
Analog
input 5
P66/AN6/
P66
OUT2R
AN6
Analog
input 6
P67/AN7/
P67
OUT3R
AN7
Analog
input 7
P63/AN3/
P63
OUT3
P64/AN4/
P64
OUT0R
Generalpurpose
I/O
Type of input/output
Input
CMOS
Hysteresis/
Automotive
level*/
Analog input
Output
CMOS
Circuit
type
H
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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8.9 Port 6
MB90930 Series
■ Pin Block Diagram for Port 6
Figure 8.9-1 shows the pin block diagram of Port 6.
Figure 8.9-1 Pin Block Diagram for Port 6
ADER6
Analog input
PDR (Port data register)
Internal data bus
PDR read
P-ch
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
Note:
For pins t hat are t o be used as input ports, set the corresponding DDR6 regist er bit to "0",
and the corresponding ADER6 register bit to "0".
For pins to be used as a nalog input pins, set the corresponding DDR6 register bit to "0"
and the corresponding ADER6 r egister bit to "1". In this case, reading the PDR6 r egister
returns "0".
■ Registers for Port 6
The Port 6 registers are PDR6, DDR6, and ADER6. The register bits have a one-to-one
correspondence with the Port 6 pins. Table 8.9-2 shows the correspondence between registers
and pins for Port 6.
Table 8.9-2 Correspondence between Registers and Pins for Port 6
Port name
Bit of related register and its corresponding pin
PDR6, DDR6, ADER6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P67
P66
P65
P64
P63
P62
P61
P60
Port 6
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8.9 Port 6
MB90930 Series
Port 6 Registers (PDR6, DDR6, ADER6)
8.9.1
This section describes the registers for Port 6.
■ Functions of Port 6 Registers
● Port 6 data register (PDR6)
The PDR6 register indicates the pin states.
● Port 6 direction register (DDR6)
The DDR6 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
● ADER6 register (ADER6)
The ADER6 register specifies whether a pin is to be used as a port or as an analog input in
units of individual bits. The pin works as an analog input if the bit corresponding to the pin is
set to "1" or as an input/output port if the bit is set to "0".
Notes:
• When used as port input/output, if a medium level signal is input, an input leak current
flows. Therefore, pins used for analog input must have their corresponding ADER6 bits
set to "1".
• At a re set, the DDR6 register is clea red and the ADER6 re gister is se t to become an
analog input.
Table 8.9-3 Functions of Port 6 Registers
Register name
Data
When reading
Pin state is "L"
level
With DDR6=0, the state
is high impedance.
With DDR6=1, "L" level
is output.
1
Pin state is "H"
level
With DDR6=0, the state
is high impedance.
With DDR=1, "H" level is
output.
0
Direction latch is Sets the output buffer to
"0"
"OFF" to be an input port
1
Direction latch is Sets the output buffer to
"1"
"ON" to be an output port
0
Port input/output mode
1
Analog input mode
0
Port 6 data register
(PDR6)
Port 6 direction
register (DDR6)
Analog input
enable register
(ADER6)
When writing
R/W
Address
Initial value
R/W
000006H
XXXXXXXXB
R/W
000016H
00000000B
R/W
00001AH
11111111B
R/W: Readable/Writable
X: Undefined value
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8.9.2
Description of Port 6 Operation
CHAPTER 8 I/O PORTS
8.9 Port 6
This section describes the operation of Port 6.
■ Operation of Port 6
● Operation as an output port
With the corresponding DDR6 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR6 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR6 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR re gister and then
write "1" to the DDR register.
● Operation as an input port
With the corresponding DDR6 register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR6 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR6 register.
● Operation as an analog input
If the port is to be used for analog input, set the ADER6 register bit corresponding to the
analog input pin to "1". Then, general-purpose port operation is prohibited and the pin will
work as analog input pin. In this state, "0" is read from the PDR6.
● Reset operation
At CPU reset, the DDR6 register value is cleared and ADER6 register value is set to operate
the port in analog input mode. For use as a general-purpose port, set the ADER6 register to "0"
in advance to operate the port in input/output mode.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Reading the PDR6 register allows the pin values (peripheral function's output values)
to be read. For use as a general-purpose port, set the ADER6 register to "0" in advance to
operate the port in input/output mode.
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CHAPTER 8 I/O PORTS
8.9 Port 6
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because the output buffer is forcibly set to "OFF". To prevent
leakage due to the input open, the input is fixed.
Table 8.9-4 shows the pin states of Port 6.
Table 8.9-4 Pin States of Port 6
Pin name
P60/AN0 to
P67/AN7
Normal
operation
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
Sleep mode
General-purpose General-purpose
I/O port
I/O port
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Table 8.9-5 Priority of Pin Output of Port 6
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P60/AN0
P60
-
-
-
P61/AN1
P61
-
-
-
P62/AN2
P62
-
-
-
P63/AN3
P63
-
-
-
P64/AN4
P64
-
-
-
P65/AN5
P65
-
-
-
P66/AN6
P66
-
-
-
P67/AN7
P67
-
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.10 Port 7
MB90930 Series
8.10
Port 7
Port 7 is a general-purpose output-only port that is also used for a peripheral
function port. The use of each pin can be switched per bit between the
peripheral function and the port. This section mainly describes the functions of
this port as a general-purpose output-only port. It indicates the configuration,
pins, block diagrams of pins, and registers for Port 7.
■ Port 7 Configuration
Port 7 consists of the following four elements:
• General-purpose output pins and peripheral function pins (P70/PWM1P0/AN8 to P77/
PWM2M1/AN15)
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Analog input enabling register (ADER7)
■ Port 7 Pins
The pins of Port 7 are also used for peripheral function pins. If used as peripheral function pins,
they must not be used as general purpose output ports. Table 8.10-1 shows the pins of Port 7.
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8.10 Port 7
MB90930 Series
Table 8.10-1 Port 7 Pins
Port
name
Pin name
P70/
PWM1P0/
AN8
Port function
Type o f
input/output
Peripheral function
PWM1P0
AN8
Analog
input 8
P71/
PWM1M0/ P71
AN9
PWM1M0
AN9
Analog
input 9
P72/
PWM2P0/
AN10
PWM2P0
AN10
Analog
input 10
PWM2M0
AN11
Analog
input 11
P70
P72
P73/
PWM2M0/ P73
GeneralAN11
Port 7
purpose
P74/
output
PWM1P1/ P74
AN12
Stepping
motor
controller
PWM1P1
AN12
Analog
input 12
P75/
PWM1M1/ P75
AN13
PWM1M1
AN13
Analog
input 13
P76/
PWM2P1/
AN14
PWM2P1
AN14
Analog
input 14
PWM2M1
AN15
Analog
input 15
P76
P77/
PWM2M1/ P77
AN15
Input
Output
(Analog
input)
-
Circuit
type
L
: Function enabled in the initial state
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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8.10 Port 7
MB90930 Series
■ Pin Block Diagram for Port 7
Figure 8.10-1 shows the pin block diagram for Port 7.
Figure 8.10-1 Pin Block Diagram for Port 7
Peripheral
function output
PDR (Port data register)
Analog input
Peripheral function
output enabled
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is forced
to work as a peripheral function output irrespective of the DDR7 register value.
■ Registers for Port 7
The Port 7 registers are PDR7 and DDR7. The register bits have a one-to-one correspondence
with the Port 7 pins. Table 8.10-2 shows the correspondence between registers and pins for
Port 7.
Table 8.10-2 Correspondence between Registers and Pins for Port 7
Port name
Bit of related register and its corresponding pin
PDR7, DDR7
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
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CHAPTER 8 I/O PORTS
8.10 Port 7
8.10.1
MB90930 Series
Port 7 Registers (PDR7, DDR7, ADER7)
This section describes the registers for Port 7.
■ Functions of Port 7 Registers
● Port 7 data register (PDR7)
The PDR7 register indicates the pin states.
● Port 7 direction register (DDR7)
The DDR7 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or becomes the high
impedance state if the bit is set to "0".
● ADER7 register (ADER7)
The ADER7 register specifies whether a pin is to be used as a port or as an analog input in
units of individual bits. The pin works as an analog input if the bit corresponding to the pin is
set to "1" or as an input/output port if the bit is set to "0".
Note:
When t he ou tput en able b it o f the p eripheral f unction (st epping mot or con troller)
corresponding to the pin is set to "enabled", the pin works as a peripheral function output
pin irrespective of the DDR7 register's setting.
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8.10 Port 7
MB90930 Series
Table 8.10-3 Functions of Port 7 Registers
Register
Data
name
Analog
input
enable
register
(ADER7)
When writing
0
When PWM output enabled:
Output value of peripheral
function is "L"
When PWM output disabled:
PDR value is "0"
1
When PWM output enabled:
Output value of peripheral
function is "H"
When PWM output disabled:
PDR value is "1"
Sets the output latch
to "1", and outputs
"H" level when used
as an output port
0
Direction latch is "0"
Sets the output buffer
to "OFF".
Direction latch is "1"
Sets the output buffer
to "ON" to be an
output port.
Port 7 data
register
(PDR7)
Port 7
direction
register
(DDR7)
When reading
1
R/W Address
Initial value
Sets the output latch
to "0", and outputs "L"
level when used as an
output port
0
Port input/output mode
1
Analog input mode
R/W
000007H
XXXXXXXXB
R/W
000017H
00000000B
R/W 00001BH
11111111B
R/W: Readable/Writable
X: Undefined value
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CHAPTER 8 I/O PORTS
8.10 Port 7
8.10.2
MB90930 Series
Description of Port 7 Operation
This section describes the operation of Port 7.
■ Operation of Port 7
● Operation as an output port
Any data written to the PDR7 register is retained in the PDR output latch and then output to the
pins as it is.
Reading the PDR7 register allows the pin values (same values as in the PDR output latch) to be
read.
● Operation as an analog input
If the port is to be used for analog input, set the ADER7 register bit corresponding to the
analog input pin to "1". Then, general-purpose port operation is prohibited and the pin will
work as analog input pin. In this state, "0" is read from the PDR7.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. For use as a general-purpose port, set the ADER7 register to "0" in advance to
operate the port in input/output mode.
● Reset operation
At CPU reset, the DDR7 register value is cleared and ADER7 register value is set to operate
the port in analog input mode. For use as a general-purpose port, set the ADER7 register to "0"
in advance to operate the port in input/output mode.
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because the output buffer is forcibly set to "OFF".
Table 8.10-4 shows the pin states of Port 7.
Table 8.10-4 Pin States of Port 7
Pin name
Normal
operation
Sleep mode
P70/ PWM1P0 to General-purpose General-purpose
P77/PWM2M1
output port
output port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose output
port
Output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
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8.10 Port 7
MB90930 Series
Table 8.10-5 Priority of Pin Output of Port 7
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P70/ PWM1P0/AN8
PWM1P0
P70
-
-
P71/ PWM1M0/AN9
PWM1M0
P71
-
-
P72/ PWM2P0/AN10
PWM2P0
P72
-
-
P73/ PWM2M0/AN11
PWM2M0
P73
-
-
P74/ PWM1P1/AN12
PWM1P1
P74
-
-
P75/ PWM1M1/AN13
PWM1M1
P75
-
-
P76/PWM2P1/AN14
PWM2P1
P76
-
-
P77/PWM2M1/AN15
PWM2M1
P77
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
■ Output Driver Driving Power Supply for Port 7
The output driver driving power supply for port 7 is the power supply (DVcc/DVss) for highcurrent output buffer pin.
● Flash memory/Mask ROM products
As the Flash memory product and Mask ROM product have DVcc and Vcc isolated from each
other, DVcc can be set to a potential higher than Vcc.
● Evaluation product
As the evaluation product does not have DVcc and Vcc isolated from each other, DVcc must
be set to a potential equal to or lower than Vcc.
Note:
If DVcc is tu rned o n with Vcc inact ive on a Flash mem ory/Mask ROM pr oducts, por t 7
may momentarily output an "H" or "L" level signal at the rise of DVcc. To prevent this, it is
advisable to turn on Vcc and DVcc at the same time or to turn on Vcc prior to DVcc.
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CHAPTER 8 I/O PORTS
8.11 Port 8
8.11
MB90930 Series
Port 8
Port 8 is a general-purpose output-only port that is also used for a peripheral
function port. The use of each pin can be switched per bit between the
peripheral function and the port. This section mainly describes the functions of
this port as a general-purpose output-only port. It indicates the configuration,
pins, block diagrams of pins, and registers for Port 8.
■ Port 8 Configuration
Port 8 consists of the following four elements:
• General-purpose output pins and peripheral function pins
(P80/PWM1P2/AN16 to P87/PWM2M3/AN23)
• Port 8 data register (PDR8)
• Port 8 direction register (DDR8)
• Analog input enabling register (ADER8)
■ Port 8 Pins
The pins of Port 8 are also used for peripheral function output pins. If used as peripheral
function pins, they must not be used as general purpose output ports. Table 8.11-1 shows the
pins of Port 8.
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8.11 Port 8
MB90930 Series
Table 8.11-1 Port 8 Pins
Port
name
Port 8
Pin name
Port function
Type of input/
output
Peripheral function
P80/
PWM1P2/ P80
AN16
PWM1P2
AN16
Analog
input 16
P81/
PWM1M2/ P81
AN17
PWM1M2
AN17
Analog
input 17
P82/
PWM2P2/ P82
AN18
PWM2P2
AN18
Analog
input 18
PWM2M2
AN19
Analog
input 19
P83/
PWM2M2/ P83
GeneralAN19
purpose
P84/
output
PWM1P3/ P84
AN20
Stepping
motor
controller
PWM1P3
AN20
Analog
input 20
P85/
PWM1M3/ P85
AN21
PWM1M3
AN21
Analog
input 21
P86/
PWM2P3/ P86
AN22
PWM2P3
AN22
Analog
input 22
P87/
PWM2M3/ P87
AN23
PWM2M3
AN23
Analog
input 23
Input
Output
Analog
input
-
Circuit
type
L
: Function enabled in the initial state
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.11 Port 8
MB90930 Series
■ Pin Block Diagram for Port 8
Figure 8.11-1 shows the pin block diagram for Port 8.
Figure 8.11-1 Pin Block Diagram for Port 8
Peripheral
function output
PDR (Port data register)
Analog input
Peripheral function
output enabled
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is forced
to work as a peripheral function output irrespective of the DDR8 register value.
■ Registers for Port 8
The Port 8 registers are PDR8 and DDR8. The register bits have a one-to-one correspondence
with the Port 8 pins. Table 8.11-2 shows the correspondence between registers and pins for
Port 8.
Table 8.11-2 Correspondence between Registers and Pins for Port 8
Port name
Bit of related register and its corresponding pin
PDR8, DDR8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P87
P86
P85
P84
P83
P82
P81
P80
Port 8
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8.11 Port 8
MB90930 Series
8.11.1
Port 8 Registers (PDR8, DDR8, ADER8)
This section describes the registers for Port 8.
■ Functions of Port 8 Registers
● Port 8 data register (PDR8)
The PDR8 register indicates the pin states.
● Port 8 direction register (DDR8)
The DDR8 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or becomes the high
impedance state if the bit is set to "0".
● ADER8 register (ADER8)
The ADER8 register specifies whether a pin is to be used as a port or as an analog input in
units of individual bits. The pin works as an analog input if the bit corresponding to the pin is
set to "1" or as an input/output port if the bit is set to "0".
Note:
When t he ou tput en able b it o f the p eripheral f unction (st epping mot or con troller)
corresponding to the pin is set to "enabled", the pin works as a peripheral function output
pin irrespective of the DDR8 register's setting.
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8.11 Port 8
MB90930 Series
Table 8.11-3 Functions of Port 8 Registers
Register
name
Data
When reading
When writing
0
When PWM output enabled:
Output value of peripheral
function is "L"
When PWM output disabled:
PDR value is "0"
Sets the output latch
to "0", and outputs
"L" level when used
as an output port
1
When PWM output enabled:
Output value of peripheral
function is "H"
When PWM output disabled:
PDR value is "1"
Sets the output latch
to "1", and outputs
"H" level when used
as an output port
0
Port 8 data
register
(PDR8)
Port 8
direction
register
(DDR8)
Analog
input
enable
register
(ADER8)
1
R/W
Address
R/W
000008H
XXXXXXXXB
Direction latch is "0"
Sets the output buffer
to "OFF".
000018H
00000000B
Direction latch is "1"
Sets the output buffer R/W
to "ON" to be an
output port.
0
Port input/output mode
1
Analog input mode
R/W
Initial value
00001FH 11111111B
R/W: Readable/Writable
X: Undefined value
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8.11.2
Description of Port 8 Operation
CHAPTER 8 I/O PORTS
8.11 Port 8
This section describes the operation of Port 8.
■ Operation of Port 8
● Operation as an output port
With the corresponding DDR8 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR8 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR8 register allows the pin values (same values as in the PDR output latch) to be
read.
● Operation as an analog input
If the port is to be used for analog input, set the ADER8 register bit corresponding to the
analog input pin to "1". Then, general-purpose port operation is prohibited and the pin will
work as analog input pin. In this state, "0" is read from the PDR8.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function.
For use as a general-purpose port, set the ADER8 register to "0" in advance to operate the port
in input/output mode.
● Reset operation
At CPU reset, the DDR8 register value is cleared and ADER8 register value is set to operate
the port in analog input mode. For use as a general-purpose port, set the ADER8 register to "0"
in advance to operate the port in input/output mode.
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because the output buffer is forcibly set to "OFF".
Table 8.11-4 shows the pin states of Port 8.
Table 8.11-4 Pin States of Port 8
Pin name
Normal
operation
Sleep mode
P80/PWM1P2 to General-purpose General-purpose
P87/PWM2M3
output port
output port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose output
port
Output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
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8.11 Port 8
MB90930 Series
Table 8.11-5 Priority of Pin Output of Port 8
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P80/PWM1P2/AN16
PWM1P2
P80
-
-
P81/PWM1M2/AN17
PWM1M2
P81
-
-
P82/PWM2P2/AN18
PWM2P2
P82
-
-
P83/PWM2M2/AN19
PWM2M2
P83
-
-
P84/PWM1P3/AN20
PWM1P3
P84
-
-
P85/PWM1M3/AN21
PWM1M3
P85
-
-
P86/PWM2P3/AN22
PWM2P3
P86
-
-
P87/PWM2M3/AN23
PWM2M3
P87
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
■ Output Driver Driving Power Supply for Port 8
The output driver driving power supply for port 8 is the power supply (DVcc/DVss) for highcurrent output buffer pin.
● Flash memory/Mask ROM products
As the Flash memory product and Mask ROM product have DVcc and Vcc isolated from each
other, DVcc can be set to a potential higher than Vcc.
● Evaluation product
As the evaluation product does not have DVcc and Vcc isolated from each other, DVcc must
be set to a potential equal to or lower than Vcc.
Note:
If DVcc is tu rned o n with Vcc inact ive on a Flash mem ory/Mask ROM pr oducts, por t 8
may momentarily output an "H" or "L" level signal at the rise of DVcc. To prevent this, it is
advisable to turn on Vcc and DVcc at the same time or to turn on Vcc prior to DVcc.
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CHAPTER 8 I/O PORTS
8.12 Port 9
MB90930 Series
8.12
Port 9
Port 9 is a general-purpose I/O port that is also used for a peripheral function
I/O port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port 9.
■ Port 9 Configuration
Port 9 consists of the following five elements:
• General-purpose I/O pins and peripheral function input/output pins
(P90/SEG22, P91/SEG23)
• General-purpose I/O pins and low-speed oscillation pins (P92/X0A*, P93/X1A*)
• General-purpose I/O pins and peripheral function input/output pins (P94/V0 to P96/V2)
• Port 9 data register (PDR9)
• Port 9 direction register (DDR9)
*: X0A pin and X1A pin are optional pins (dual clock products only).
■ Port 9 Pins
The pins of Port 9 are also used for peripheral function I/O pins. If used as peripheral function
I/O pins, they must not be used as general purpose I/O ports. Table 8.12-1 shows the pins of
Port 9.
Table 8.12-1 Port 9 Pins
Type of input/output
Port name
Pin name
Port function
Peripheral function
Input
P90/SEG22
P90
P91/SEG23
P91
P92*1
P92
P93*1
P93
P94/V0
P94
Output
Circuit
type
SEG22
F
LCD Controller
Port 9
P95/V1
P95
P96/V2
P96
Generalpurpose
I/O
SEG23
CMOS Hysteresis/
Automotive level*2
I
CMOS
V0
Generalpurpose
I/O
V1
External divide
G
V2
: Function enabled in the initial state
*1 : Single clock products only
*2 : Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet
("3. DC Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.12 Port 9
MB90930 Series
■ Pin Block Diagram for Port 9
Figure 8.12-1 shows the pin block diagram for Port 9.
Figure 8.12-1 Pin Block Diagram for Port 9
Peripheral
function output
PDR (Port data register)
P-ch
PDR read
Internal data bus
LCD Vn
Peripheral function
output enabled
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is forced
to work as a peripheral function's output irrespective of the DDR9 register value.
■ Registers for Port 9
The Port 9 registers are PDR9 and DDR9. The register bits have a one-to-one correspondence
with Port 9 pins. Table 8.12-2 shows the correspondence between registers and pins for Port 9.
Table 8.12-2 Correspondence between Registers and Pins for Port 9
Port name
Bit of related register and its corresponding pin
PDR9, DDR9
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
-
P96
P95
P94
P93
P92
P91
P90
Port 9
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8.12.1
Registers for Port 9 (PDR9, DDR9)
CHAPTER 8 I/O PORTS
8.12 Port 9
This section describes the registers for Port 9.
■ Functions of Port 9 Registers
● Port 9 data register (PDR9)
The PDR9 register indicates the pin states.
● Port 9 direction register (DDR9)
The DDR9 register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDR9 register's setting.
Table 8.12-3 shows functions of Port 9 registers.
Table 8.12-3 Functions of Port 9 Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch
is "0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch
is "1"
Sets the output buffer to
"ON" to be an output port
0
Port 9 data register
(PDR9)
Port 9 direction
register (DDR9)
R/W
Address
Initial value
R/W
000009H
-XXXXXXXB
R/W
000019H
-0000000B
R/W:Readable/Writable
X: Undefined value
- : Undefined
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8.12 Port 9
8.12.2
MB90930 Series
Description of Port 9 Operation
This section describes the operation of Port 9.
■ Operation of Port 9
● Operation as an output port
With the corresponding DDR9 register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDR9 register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDR9 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR re gister and then
write "1" to the DDR register.
● Operation as an input port
With the corresponding DDR9 register bit set to "0", the port works as an input port.
In working as an input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDR9 register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDR9 register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDR9 register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDR9 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDR9 register is not initialized. Therefore, if used as an output port,
set the output data in the PDR9 register and then set the corresponding DDR9 register to "1".
Port 9 has its feature as the LCD controller/driver reference power supply (V0 to V2) enabled
in the initial state. To use it as a general-purpose port, set the corresponding bit in the LCD
output control register (LOCR3) to "0".
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8.12 Port 9
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDR9 register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.12-4 shows the pin states of Port 9.
Table 8.12-4 Pin States of Port 9
Normal
operation
Pin name
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
Sleep mode
P90/SEG22 to General-purpose General-purpose
P96/V2
I/O port
I/O port
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.12-5 Priority of Pin Output of Port 9
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
P90/SEG22
SEG22
P90
-
-
P91/SEG23
SEG23
P91
-
-
P92
P92
-
-
-
P93
P93
-
-
-
P94/V0
V0
P94
-
-
P95/V1
V1
P95
-
-
P96/V2
V2
P96
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.13 Port C
8.13
MB90930 Series
Port C
Port C is a general-purpose I/O port that is also used for a peripheral function
input port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port C.
■ Port C Configuration
Port C consists of the following three elements.
• General-purpose I/O pins and external interrupt input pins (PC0/SIN0/INT4 to PC7/PPG1/
TIN1/IN6)
• Port C data register (PDRC)
• Port C direction register (DDRC)
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CHAPTER 8 I/O PORTS
8.13 Port C
MB90930 Series
■ Port C Pins
The pins of Port C pins are also used for peripheral function input/output pins. If used as
peripheral function I/O pins, they must not be used as general purpose I/O ports. Table 8.13-1
shows the pins of Port C.
Table 8.13-1 Port C Pins
Port
Pin
name name
Type of input/output
Port function
Peripheral function
Input
PC0/
SIN0/
INT4
PC0
SIN0
PC1/
SOT0/
INT5/
IN3
PC1
SOT0
INT4
IN3
PC3/
SIN1/
Port C INT7
PC4/
SOT1
SCK0
PC5/
SCK1/ PC5
TRG
SCK1
PC6/
PPG0/
TOT1/
IN7
PPG0
IN2
External
interrupt
PC7
CMOS Hysteresis/
Automotive level*
I
INT6
CMOS/
CMOS Hysteresis/
Automotive level*
INT7
J
CMOS
TRG
IN7
PPG
PC7/
PPG1/
TIN1/
IN6
J
UART
PC3 General- SIN1
purpose
I/O
PC4
SOT1
PC6
CMOS/
CMOS Hysteresis/
Automotive level*
INT5
ICU
PC2/
SCK0/
PC2
INT6/
IN2
Output
Circuit
type
PPG1
TOT1
RLT
CMOS Hysteresis/
Automotive level*
I
ICU
IN6
TIN1
: Function enabled in the initial state
* : Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet
("3. DC Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For SIN0 and SIN1 pins, CMOS 0.7Vcc/0.3Vcc can also be selected.
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.13 Port C
MB90930 Series
■ Pin Block Diagram for Port C
Figure 8.13-1 shows the pin block diagram for Port C.
Figure 8.13-1 Pin Block Diagram for Port C
Peripheral
function input
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port C
The Port C registers are PDRC and DDRC. The register bits have a one-to-one correspondence
with the Port C pins. Table 8.13-2 shows the correspondence between the registers and pins for
Port C.
Table 8.13-2 Correspondence between Registers and Pins for Port C
Port name
Bit of related register and its corresponding pin
PDRC, DDRC
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Port C
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8.13.1
Registers for Port C (PDRC, DDRC)
CHAPTER 8 I/O PORTS
8.13 Port C
This section describes the registers for Port C.
■ Functions of Port C Registers
● Port C data register (PDRC)
The PDRC register indicates the pin states.
● Port C direction register (DDRC)
The DDRC register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Notes:
• When a peripheral fu nction with an o utput pin is used , a nd t he output en able bit of
each peripheral function corresponding to the pin is set to "enabled", the pin works as
a peripheral function output pin irrespective of the DDRC register's setting.
• If a peripheral fu nction wit h an inpu t pin is used, se t the DDRC re gister bit
corresponding to each peripheral function's input pin to "0" to make it work as an inp ut
port.
Table 8.13-3 Functions of Port C Registers
Register name
Data
When reading
When writing
0
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch
is "0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch
is "1"
Sets the output buffer to
"ON" to be an output port
Port C data register
(PDRC)
Port C direction
register (DDRC)
R/W
Address
Initial value
R/W 00000CH
XXXXXXXXB
R/W 00001CH
00000000B
R/W: Readable/Writable
X : Undefined value
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CHAPTER 8 I/O PORTS
8.13 Port C
8.13.2
MB90930 Series
Description of Port C Operation
This section describes the operation of Port C.
■ Operation of Port C
● Operation as an output port
With the corresponding DDRC register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDRC register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDRC register allows the pin values (same values as in the PDR output latch) to
be read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDRC register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDRC register, it is retained in the PDR output latch, but not output to
the pins.
The pin levels ("L" or "H") are read from the PDRC register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDRC register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Operation as a peripheral function input
For a port that is also used for a peripheral function input, the pin value is always set. To use an
external signal as input for the peripheral function, set the DDRC register for the input port to
"0".
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CHAPTER 8 I/O PORTS
8.13 Port C
MB90930 Series
● Reset operation
At CPU reset, the DDRC register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and, the pins are set to high impedance.
In a reset operation, the PDRC register is not initialized. Therefore, if used as an output port,
set the output data in the PDRC register and then set the corresponding DDRC register to "1".
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDRC register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.13-4 shows the pin states of Port C.
Table 8.13-4 Pin States of Port C
Pin name
Normal
operation
Sleep mode
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
PC0/SIN0/INT4 to General-purpose General-purpose
General-purpose I/O port Input cut-off/output Hi-Z
PC7/PPG1/TIN1/IN6
I/O port
I/O port
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port
in stop mode or time-base timer mode, disable the output of peripheral functions, and set
the STP bit to "1" or TMD bit to "0" in t he low-power consumption mode control register
(LPMCR).
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CHAPTER 8 I/O PORTS
8.13 Port C
MB90930 Series
Table 8.13-5 Priority of Pin Output of Port C
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
PC0/SIN0/INT4
PC0
-
-
-
PC1/SOT0/INT5/IN3
SOT0
PC1
-
-
PC2/SCK0/INT6/IN2
SCK0
PC2
-
-
PC3/SIN1/INT7
PC3
-
-
-
PC4/SOT1
SOT1
PC4
-
-
PC5/SCK1/TRG
SCK1
PC5
-
-
PC6/PPG0/TOT1/IN7
PPG0
TOT1
PC6
-
PC7/PPG1/TIN1/IN6
PPG1
PC7
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.14 Port D
MB90930 Series
8.14
Port D
Port D is a general-purpose I/O port that is also used for a peripheral function I/
O port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as
a general-purpose I/O port. It indicates the configuration, pins, block diagrams
of pins, and registers for Port D.
■ Port D Configuration
Port D consists of the following three elements.
• General-purpose I/O pins and peripheral function input/output pins (PD0/SIN2 to PD6/
TOT2)
• Port D data register (PDRD)
• Port D direction register (DDRD)
■ Pins of Port D
The I/O pins of Port D are also used for peripheral function input/output pins. If used as
peripheral function I/O pins, they must not be used as general purpose I/O ports. Table 8.14-1
shows the Port D pins.
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8.14 Port D
MB90930 Series
Table 8.14-1 Port D Pins
Port name Pin name
Port function
PD0/SIN2 PD0
Port D
PD1/
SOT2
PD1
PD2/
SCK2
PD2
PD3/SIN3 PD3
Peripheral
function
Type of Input/Output
Input
Output
CMOS/
CMOS Hysteresis/
Automotive level*
SIN2
J
SOT2
I
CMOS Hysteresis/
Automotive level*
SCK2
Generalpurpose
I/O
SIN3
PD4/
SOT3
PD4
SOT3
PD5/
SCK3
PD5
SCK3
PD6/
TOT2
PD6
TOT2
Circuit
type
UART
CMOS/
CMOS Hysteresis/
Automotive level*
F
CMOS
J
I
CMOS Hysteresis/
Automotive level*
F
I
: Function enabled in the initial state
*: Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
SIN2 and SIN3 pins also select CMOS 0.7Vcc/0.3Vcc.
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.14 Port D
MB90930 Series
■ Pin Block Diagram for Port D
Figure 8.14-1 shows the pin block diagram for Port D.
Figure 8.14-1 Pin Block Diagram for Port D
Peripheral
function input
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
PDR read
Internal data bus
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port D
The Port D registers are PDRD and DDRD. The register bits have a one-to-one correspondence
with the Port D pins. Table 8.14-2 shows the correspondence between the registers and pins for
Port D.
Table 8.14-2 Correspondence between Registers and Pins for Port D
Port name
Bit of related register and its corresponding pin
PDRD, DDRD
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
-
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Port D
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8.14 Port D
MB90930 Series
Registers for Port D (PDRD, DDRD)
8.14.1
This section describes the registers for Port D.
■ Functions of Port D Registers
● Port D data register (PDRD)
The PDRD register indicates the pin states.
● Port D direction register (DDRD)
The DDRD register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a p eripheral f unction with an o utput p in is used, if the o utput enable bit o f ea ch
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDRD register's setting.
Table 8.14-3 Functions of Port D Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is
"0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch is
"1"
Sets the output buffer to
"ON" to be an output port
0
Port D data
register (PDRD)
Port D direction
register (DDRD)
R/W
Address
Initial value
R/W
00000DH
-XXXXXXXB
R/W
00001DH
-0000000B
R/W: Readable/Writable
X: Undefined value
- : Undefined
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8.14.2
Description of Port D Operation
CHAPTER 8 I/O PORTS
8.14 Port D
This section describes the operation of Port D.
■ Operation of Port D
● Operation as an output port
With the corresponding DDRD register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDRD register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDRD register allows the pin values (same values as in the PDR output latch) to
be read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDRD register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDRD register, it is retained in the PDR output latch, but not output to
the pins.
The pin levels ("L" or "H") are read from the PDRD register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDRD register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDRD register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDRD register is not initialized. Therefore, if used as an output port,
set the output data in the PDRD register and then set the corresponding DDRD register to "1".
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CHAPTER 8 I/O PORTS
8.14 Port D
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDRD register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.14-4 shows the pin states of Port D.
Table 8.14-4 Pin States of Port D
Pin name
Normal
operation
Sleep mode
PD0/SIN2 to General-purpose General-purpose
PD6/TOT2
I/O port
I/O port
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
General-purpose I/O port
Input cut-off/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in LPMCR)
Hi-Z: High impedance
Table 8.14-5 Priority of Pin Output of Port D
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
PD0/SIN2
PD0
-
-
-
PD1/SOT2
SOT2
PD1
-
-
PD2/SCK2
SCK2
PD2
-
-
PD3/SIN3
PD3
-
-
-
PD4/SOT3
SOT3
PD4
-
-
PD5/SCK3
SCK3
PD5
-
-
PD6/TOT2
TOT2
PD6
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.15 Port E
MB90930 Series
8.15
Port E
Port E is a general-purpose I/O port that is also used for a peripheral function
I/O port. The use of each pin can be switched per bit between the peripheral
function and the port. This section mainly describes the function of this port as a
general-purpose I/O port. It indicates the configuration, pins, block diagrams of
pins, and registers for Port E.
■ Port E Configuration
Port E consists of the following three elements.
• General-purpose I/O pins and peripheral function input/output pins (PE0/TOT3 to PE2/
SGO1)
• Port E data register (PDRE)
• Port E direction register (DDRE)
■ Port E Pins
The I/O pins of Port E are also used for peripheral function input/output pins. If used as
peripheral function I/O pins, they must not be used as general purpose I/O ports. Table 8.15-1
shows the pins of Port E.
Table 8.15-1 Port E Pins
Port
name
Pin
name
Type of Input/Output
Port function
Peripheral function
Input
PE0/
TOT3/ PE0
IN7R
TOT3
IN7R
RLT
Port E
PE1/
TIN3/
IN6R
GeneralPE1
purpose I/O
PE2/
SGO1/ PE2
IN3R
TIN3
SGO1
Output
Circuit
type
IN6R
SG
ICU
CMOS
Hysteresis/
Automotive
level*
CMOS
I
IN3R
: Function enabled in the initial state
*:Automotive level is a standard for input voltage. For the standard values, please refer to the data sheet ("3. DC
Characteristics" in "■ ELECTRICAL CHARACTERISTICS").
For the circuit type, refer to Section "1.7 I/O Circuit Types".
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CHAPTER 8 I/O PORTS
8.15 Port E
MB90930 Series
■ Pin Block Diagram for Port E
Figure 8.15-1 shows the pin block diagram for Port E.
Figure 8.15-1 Pin Block Diagram for Port E
Peripheral
function input
Peripheral
function output
PDR (Port data register)
Peripheral function
output enabled
P-ch
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
Note:
If the peripheral function's output enable bit is set to "enabled", the corresponding pin is
forced to work as a peripheral function output irrespective of the DDRE register value.
■ Registers for Port E
The Port E registers are PDRE and DDRE. The register bits have a one-to-one correspondence
with the Port E pins. Table 8.15-2 shows the correspondence between the registers and pins for
Port E.
Table 8.15-2 Correspondence between Registers and Pins for Port E
Port name
Bit of related register and its corresponding pin
PDRE, DDRE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
-
-
-
-
-
PE2
PE1
PE0
Port E
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8.15.1
Registers for Port E (PDRE, DDRE)
CHAPTER 8 I/O PORTS
8.15 Port E
This section describes the registers for Port E.
■ Functions of Port E Registers
● Port E data register (PDRE)
The PDRE register indicates the pin states.
● Port E direction register (DDRE)
The DDRE register is used to set the pin input/output direction for each bit. The pin works as
an output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit
is set to "0".
Note:
When a p eripheral f unction with an o utput p in is used, if the o utput enable bit o f ea ch
peripheral f unction co rresponding t o t he pin is s et to "en abled", th e p in wo rks as a
peripheral function output pin irrespective of the DDRE register's setting.
Table 8.15-3 Functions of Port E Registers
Register name
Data
When reading
When writing
Pin state is "L"
level
Sets the output latch to
"0", and outputs "L" level
when used as an output
port
1
Pin state is "H"
level
Sets the output latch to
"1", and outputs "H" level
when used as an output
port
0
Direction latch is
"0"
Sets the output buffer to
"OFF" to be an input port
1
Direction latch is
"1"
Sets the output buffer to
"ON" to be an output port
0
Port E data
register (PDRE)
Port E direction
register (DDRE)
R/W
Address
Initial value
R/W
00000EH
-----XXXB
R/W
00001EH
-----000B
R/W: Readable/Writable
X: Undefined value
- : Undefined
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CHAPTER 8 I/O PORTS
8.15 Port E
8.15.2
MB90930 Series
Description of Port E Operation
This section describes the operation of Port E
■ Operation of Port E
● Operation as an output port
With the corresponding DDRE register bit set to "1", the port works as an output port.
When used as an output port, any data written to the PDRE register is retained in the PDR
output latch and then output to the pins as it is.
Reading the PDRE register allows the pin values (same values as in the PDR output latch) to
be read.
Note:
If the po rt da ta reg ister use s a read-modify-write (RMW) instr uction ( e.g., a bit set
instruction), the target bit is se t to th e value specified and the output bit specified by t he
DDR register is not affected. However, the input bit specified by the DDR re gister writes
the in put va lue from t he pin t o the output la tch, a nd t he valu e is output. The refore, to
switch the input bit to the output bit, write the output data to the PDR register and then set
the DDR register as the output.
● Operation as an input port
With the corresponding DDRE register bit set to "0", the port works as an input port.
In working as input port, the output buffer is set to "OFF", and the pins to high impedance.
If data is written to the PDRE register, it is retained in the PDR output latch, but not output to the
pins.
The pin levels ("L" or "H") are read from the PDRE register.
● Operation as a peripheral function output
To use the port as a peripheral function output, set it with the output enable bit of the peripheral
function. Switching the input/output has priority over the peripheral function's output enable
bit. Therefore, even if the DDRE register bit is set to "0", the port is used as a peripheral
function output as long as the corresponding peripheral function is output enabled. Even if a
peripheral function is output enabled, the pin value can be read, allowing the peripheral
function's output value to be detected.
● Reset operation
At CPU reset, the DDRE register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to high impedance.
In a reset operation, the PDRE register is not initialized. Therefore, if used as an output port,
set the output data in the PDRE register and then set the corresponding DDRE register to "1".
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CHAPTER 8 I/O PORTS
8.15 Port E
MB90930 Series
● Operation for the stop and time-base timer modes
If the pin state specification bit of the low-power consumption mode control register (SPL in
LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are
set to high impedance. This is because, irrespective of the DDRE register value, the output
buffer is forcibly set to "OFF". To prevent leakage due to the input open, the input is fixed.
Table 8.15-4 shows the pin states of Port E.
Table 8.15-4 Pin States of Port E
Stop mode,
time-base timer mode
(SPL=0)
Stop mode,
time-base timer mode
(SPL=1)
PE0/TOT3/IN7R
General-purpose General-purpose
to
General-purpose I/O port
I/O port
I/O port
PE2/SGO1/IN3R
Input cut-off/output Hi-Z
Normal
operation
Pin name
Sleep mode
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Table 8.15-5 Priority of Pin Output of Port E
Pin name
Priority 1
Priority 2
Priority 3
Priority 4
PE0/TOT3/IN7R
TOT3
PE0
-
-
PE1/TIN3/IN6R
PE1
-
-
-
PE2/SGO1/IN3R
SGO1
PE2
-
-
Note: Priority 1 has the highest priority and Priority 4 has the lowest priority.
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CHAPTER 8 I/O PORTS
8.16 Input Level Select Registers (PIL0 to PIL2)
MB90930 Series
Input Level Select Registers (PIL0 to PIL2)
8.16
The input level select registers allow to switch from Automotive input levels (VIH/
VIL=0.8VCC/0.5VCC) to CMOS Hysteresis input levels (VIH/VIL=0.8VCC/0.2VCC). In
addition, the serial input pin (SIN) can select CMOS input levels (VIH/VIL=0.7VCC/
0.3VCC).
■ Input Level Select Register 0 (PIL0)
PIL0
ddress
A bit
7
6
5
4
3
2
1
0
00008CH
Reserved
ILP6
ILP5
ILP4
ILP3
ILP2
ILP1
ILP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Initial alue v 0
R/W: Readable/Writable
● bit7: Reserved bit
This is a reserved bit. Always write "0" to this bit.
● bit6 to bit0:ILP6 to ILP0
These bits set the input level of corresponding ports.
ILP6 to ILP0 correspond to Port 6 to Port 0 respectively.
"When set to "0": Sets to Automotive input level.
"When set to 1": Sets to CMOS hysteresis input level (VIH/VIL=0.8VCC/0.2VCC).
■ Input Level Selection Register 1 (PIL1)
PIL1
Address bit
15
14
13
12
11
10
9
8
00008DH
-
-
-
Reserved
ILSIN1
ILSIN0
ILP9
Reserved
-
-
-
R/W
R/W
R/W
R/W
R/W
X
X
X
0
0
0
0
0
Initial value
R/W: Readable/Writable
-:
Undefined
X:
Undefined value
● bit15 to bit13: Undefined bits
These are undefined bits. Writing has no effect on operation. Read value is undefined.
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8.16 Input Level Select Registers (PIL0 to PIL2)
MB90930 Series
● bit12: Reserved bit
This is a reserved bit. Always write "0" to this bit.
● bit11:ILSIN1
Selects the input level of serial input pin of UART1(SIN1).
When set to "0": Sets to the level specified in PIL0 register.
When set to "1": Sets to CMOS input level (0.7VCC/0.3VCC).
● bit10: ILSIN0
Selects the input level of serial input pin of UART0(SIN0).
When set to "0": Sets to the level specified in PIL0 register.
When set to "1": Sets to CMOS input level (0.7VCC/0.3VCC).
● bit9: ILP9
Selects the input level of Port 9.
"When set to "0": Sets to Automotive input level.
"When set to 1": Sets to CMOS hysteresis input level (VIH/VIL=0.8VCC/0.2VCC).
● bit8: Reserved bit
This is a reserved bit. Always write "0" to this bit.
■ Input Level Selection Register 2 (PIL2)
Address bit
7
6
5
00008EH
-
-
-
-
-
-
R/W
Initial alue v X
X
X
0
PIL2
4
3
2
1
0
ILPE
ILPD
ILPC
R/W
R/W
R/W
R/W
0
0
0
0
ILSIN3 ILSIN2
R/W: Readable/Writable
-:
Undefined
X:
Undefined value
● bit7 to bit5: Undefined bits
These are undefined bits. Writing has no effect on operation. Read value is undefined.
● bit4: ILSIN3
These bits are used to select the input level for the serial input pin (SIN3) of UART3.
When set to "0": Sets to the level specified in PIL2 register.
When set to "1": Sets to CMOS input level (0.7VCC/0.3VCC).
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CHAPTER 8 I/O PORTS
8.16 Input Level Select Registers (PIL0 to PIL2)
MB90930 Series
● bit3: ILSIN2
These bits are used to select the input level for the serial input pin (SIN2) of UART2.
When set to "0": Sets to the level specified in PIL2 register.
When set to "1": Sets to CMOS input level (0.7VCC/0.3VCC).
● bit2 to bit0:ILPE to ILPC
These bits set the input levels of corresponding ports.
ILPE to ILPC correspond to Port E to Port C respectively.
"When set to "0": Sets to Automotive input level.
"When set to 1": Sets to CMOS input level (VIH/VIL=0.8VCC/0.2VCC).
Note:
The t hreshold of the co rresponding inp ut pin var ies immed iately af ter t he setting of the
input level select register is cha nged. Therefore, do not use the read value from the pin
until 2 machine cycles are elapsed after the setting is changed.
When the setting is changed, be sure to disable the corresponding resource.
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8.17
Sample Program for I/O Ports
CHAPTER 8 I/O PORTS
8.17 Sample Program for I/O Ports
A sample program that uses the I/O port is shown below.
■ Sample Program for I/O Ports
● Specification of processing
On ports 0 and 1, all 7-segment LEDs (8-segment if Dp is included) are on.
The P10 pin corresponds to the LED's common anode pin, and the P00 to P07 pins correspond
to the segment pins.
Figure 8.17-1 shows an example of 8-segment LED connection.
Figure 8.17-1 Example of 8-segment LED Connection
MB90930 series
[Coding example]
PDR0
EQU
000000H
PDR1
EQU
000001H
DDR0
EQU
000010H
DDR1
EQU
000011H
;---------Main program--------------------------------------------------------CODE
CSEG
START:
;Initial setting completed
MOV
I:PDR1, #00000000B
;P10 set to "L" level,
MOV
I:DDR1, #11111111B
;All bits in Port 1 set as outputs
MOV
I:PDR0, #11111111B
;All bits in Port 0 set to "1"
MOV
I:DDR0, #11111111B
;All bits in Port 0 set as outputs
CODE
ENDS
;-----------------------------------------------------------------------------END
START
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CHAPTER 8 I/O PORTS
8.17 Sample Program for I/O Ports
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CM44-10150-1E
CHAPTER 9
WATCHDOG TIMER/
TIME-BASE TIMER/
WATCH TIMER
(Sub clock)
This chapter describes the functions and
operations of the watchdog timer / time-base
timer / watch timer (sub clock).
9.1 Outline of Watchdog Timer/Time-base Timer/Watch
Timer
9.2 Block Diagrams of Watchdog Timer/Time-base Timer/
Watch Timer
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
9.4 Operation of Watchdog Timer/Time-base Timer/Watch
Timer
9.5 Notes on Using the Watchdog Timer/Time-base Timer
9.6 Program Example for Watchdog Timer/Time-base Timer
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.1 Outline of Watchdog Timer/Time-base Timer/Watch Timer
9.1
MB90930Series
Outline of Watchdog Timer/Time-base Timer/Watch
Timer
The circuit configurations of the watchdog timer, time-base timer and watch
timer are shown below respectively.
• Watchdog timer: watchdog counter, control register, and watchdog reset
circuit
• Time-base timer: 18-bit timer, circuit to control interval interrupts
• Watch timer:
15-bit timer, circuit to control interval interrupts
■ Functions of the Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter that has a clock source using the
carry-over signal from a 18-bit time-base timer or 15-bit watch timer, control register, and
watchdog reset control section. If the timer is not cleared within a certain time after the startup,
the CPU will be reset.
■ Functions of Time-base Timer
The time-base timer is an 18-bit free-run counter (time-base counter) that counts up
synchronously with the main clock (in divide-by-2 of oscillation clock). It has an interval timer
function to select one of four interval times. It also has a function to supply operation clocks of
the oscillation stabilization wait time timer output, and the watchdog timer, etc. The time-base
timer uses the main clock irrespective of the MCS bit in CKSCR and SCS bit.
■ Functions of Watch Timer
The watch timer, which is a timer for the watchdog timer's clock source and sub clock
oscillation stabilization time waiting, has a function of an interval timer by regularly generating
an interrupt. The watch timer uses the sub clock irrespective of the MCS bit in CKSCR and
SCS bit.
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.2 Block Diagrams of Watchdog Timer/Time-base Timer/Watch
Timer
MB90930Series
9.2
Block Diagrams of Watchdog Timer/Time-base
Timer/Watch Timer
The block diagrams of the watchdog timer/time-base timer/watch timer are
shown below.
■ Block Diagram of Watchdog Timer/Time-base Timer/Watch Timer
Figure 9.2-1 Block Diagram of watchdog timer/time-base timer/watch timer
main clock
TBTC
TBC1
Selector
TBC0
TBR
TBIE
AND
Q
211
213
215
218
TBTRES
Clock input
Time-base timer
211
213
215
218
S
R
TBOF
Time-base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
CLR
OF
Watchdog reset
generation circuit
CLR
F2MC-16LX bus
WTE
To WDGRST
internal reset
generation
circuit
WTC
WDCS
SCE
AND
Q
SCM
Power-on reset,
Stopping the sub clock
S
R
WTC2
to
WTC0
Selector
WTR
WTIE
WTOF
AND
Q
S
R
28
29
210
211
212
213
214
215
WTRES
210
213
214
215
Watch timer
Clock input
sub clock
Clock
interrupt
WDTC
From power-on
generation
PONR
−
WRST
ERST
RST pin
SRST
From LPMCR
register's RST bit
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
9.3
MB90930Series
List of Registers for Watchdog Timer/Time-base
Timer/Watch Timer
This section describes the list of registers for the watchdog timer/time-base
timer/watch timer.
■ List of Registers of Watchdog Timer/Time-base Timer/Watch Timer
Figure 9.3-1 lists the registers used for the watchdog timer/time-base timer/watch timer.
Figure 9.3-1 List of Registers for Watchdog Timer/Time-base Timer/Watch Timer
Watchdog Control Register
Address: 0000A8H
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PONR
−
R
(X)
−
(-)
R
(X)
R
(X)
SRST
WTE
WT1
WT0
R
(X)
W
(1)
W
(1)
W
(1)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
−
−
TBIE
TBOE
TBR
TBC1
TBC0
−
(-)
−
(-)
R/W
(0)
R/W
(0)
W
(1)
R/W
(0)
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WDCS
SCE
WTIE
WTOF
WTR
R/W
(1)
R
(0)
R/W
(0)
R/W
(0)
W
(1)
WRST ERST
WDTC
Time-base timer control register
Address: 0000A9H
−
Initial value →
(1)
Watch timer control register
Address: 0000AAH
Initial value →
R:
W:
R/W :
-:
260
WTC2 WTC1 WTC0
R/W
(0)
R/W
(0)
TBTC
WTC
R/W
(0)
Read only
Write only
Readable/Writable
Undefined
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
MB90930Series
9.3.1
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) indicates the watchdog timer start,
clear, and reset sources.
■ Bit Configuration of the Watchdog Timer Control Register (WDTC)
Figure 9.3-2 shows the bit configuration of the watchdog timer control register (WDTC).
Figure 9.3-2 Bit Configuration of the Watchdog Timer Control Register (WDTC)
Address: 0000A8H
bit7
bit6
PONR
−
R
(X)
−
(-)
Initial value →
R:
W:
-:
bit5
bit4
WRST ERST
R
(X)
R
(X)
bit3
bit2
bit1
bit0
SRST
WTE
WT1
WT0
R
(X)
W
(1)
W
(1)
W
(1)
WDTC
Read only
Write only
Undefined
Note:
Do n ot acce ss usin g re ad-modify-write ( RMW) inst ructions, since t hey m ay ca use an
error in operation.
[bit7, bit5 to bit3] PONR, WRST, ERST, SRST
PONR, WRST, ERST, and SRST are flags indicating reset sources. They are set as
shown in Table 9.3-1 by reset. All bits are cleared after reading the WDTC register.
These bits are read-only register.
Table 9.3-1 PONR, WRST, ERST, and SRST (reset Source Bits)
Reset source
Power-on
PONR
WRST
ERST
SRST
1
-
-
-
Watchdog Timer
1
External pin (RST input)
CPU operation detection reset
Low-voltage detection reset
1
1
RST bit (software reset)
1
1
: Previous value is retained.
-: Undefined
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
[bit2] WTE
MB90930Series
While the watchdog timer is in the stop state, if WTE is written with "0", the watchdog
timer starts operating. By writing "0" twice or more, the watchdog timer counter is
cleared. Writing "1" has no effect.
The watchdog timer stops if any reset source is generated. "1" is output in read
operations.
[bit1, bit0] WT1, WT0
WT1 and WT0 are bits used to select the watchdog timer's interval time. Data is valid
only when it is written during the startup of the watchdog timer. Data written during
other than the startup of the watchdog timer is ignored. These bits can only be written.
The clock input to the watchdog timer is selected with the 3 bits: the WDCS bit of the
watch timer control register WTC, the result of a logical AND of the SCM bit in the lowpower consumption control circuit clock selection register LPMCR, and the WT1 and
WT0 bits. This is, with WDCS set to "1", if the main clock and PLL clock are selected as
the machine clock, the output of the time-base timer can be selected as the input clock of
the watchdog timer.
Table 9.3-2 shows setting the interval time with the WT1/WT0 bits.
Table 9.3-2 WT1, WT0 (Interval Time Selection Bits)
Interval time (4MHz oscillation)
logical
multiplication
WT1
1
0
0
Approx. 3.58 ms
Approx. 4.61 ms
1
0
1
Approx. 14.33 ms
Approx. 18.43 ms
1
1
0
Approx. 57.23 ms
Approx. 73.73 ms
1
1
1
Approx. 458.75 ms
Approx. 589.82 ms
0
0
0
Approx. 436 ms
Approx. 563 ms
0
0
1
Approx. 3.50 s
Approx. 4.50s
0
1
0
Approx. 7.0 s
Approx. 9.0 s
0
1
1
Approx. 14.0 s
Approx. 18.0 s
WT0
Maximum*
Minimum
* : The maximum interval time is the value available when the watchdog timer is operating and the time-base
timer or watch timer is not reset.
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
MB90930Series
9.3.2
Time-base Timer Control Register (TBTC)
The time-base timer control register (TBTC) is used to control interrupts by the
time-base timer and clear the time-base counter.
■ Bit Configuration of the Time-base Timer Control Register (TBTC)
Figure 9.3-3 shows the bit configuration of the time-base timer control register (TBTC).
Figure 9.3-3 Bit Configuration of the Time-base Timer Control Register (TBTC)
Time-base timer control register
Address: 0000A9H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
−
−
TBIE
TBOF
TBR
TBC1
TBC0
−
(1)
−
(-)
−
(-)
R/W
(0)
R/W
(0)
W
(1)
R/W
(0)
R/W
(0)
Initial value →
W:
R/W :
-:
TBTC
Write only
Readable/Writable
Undefined
[bit15] Reserved
bit15 is a reserved bit. Always set it to "1".
[bit12] TBIE
The TBIE bit is used to enable interval interrupts by the time-base timer. If set to "1",
interrupts are enabled, if set to "0", interrupts are disabled. This bit is cleared by reset.
This bit can be read and written.
[bit11] TBOF
TBOF is an interrupt request flag of the time-base timer. With the TBIE bit set to "1", if
the TBOF bit is set to "1", an interrupt request is generated. It is set to "1" in intervals
specified by the bits TBC1 and TBC0.
The TBOF bit is cleared by the conditions listed below.
• Writing "0"
• Transition to main stop mode
• Transition to PLL stop mode
• Transition from sub clock mode to main clock mode
• Transition from sub clock mode to PLL clock mode
• Transition from main clock mode to PLL clock mode
• Writing "0" to the TBR bit
• Reset
Writing "1" has no effect.
Reading by read-modify-write (RMW) instructions always reads "1".
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
MB90930Series
Note:
Clear the TBOF bit, after the time-base timer interrupts are disabled by the TBIE bit or the
interrupt level mask register (ILM) in the processor status (PS).
[bit10] TBR
The TBR bit is used to clear all bits in the time-base timer's counter to "0". Writing "0"
will clear the time-base counter. Writing "1" has no effect. "1" is always in read.
[bit9, bit8] TBC1, TBC0
TBC1 and TBC0 are bits used to set the time-base timer's interval.
At a reset, they will be initialized to "00B". These bits can be read and written.
Table 9.3-3 Interval Time and Cycle Count of TBC1 and TBC0
TBC1
TBC0
Interval time
for source oscillation: 4 MHz
Oscillation clock (source oscillation)
cycle count
0
0
1.024 ms
212cycles
0
1
4.096 ms
214cycles
1
0
16.384 ms
216cycles
1
1
131.072 ms
219cycles
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
MB90930Series
9.3.3
Watch Timer Control Register (WTC)
The watch timer control register (WTC) is used to select the clock signal,
control interrupts and intervals, and clear the counter.
■ Watch Timer Control Register (WTC)
Figure 9.3-4 shows the bit configuration of the watch timer Control Register (WTC).
Figure 9.3-4 Bit Configuration of the Watch Timer Control Register (WTC)
Address: 0000AAH
bit7
bit6
bit5
bit4
bit3
WDCS
SCE
WTIE
WTOF
WTR
R/W
(1)
R
(0)
R/W
(0)
R/W
(0)
W
(1)
Initial value →
R:
W:
R/W :
bit2
bit1
bit0
WTC2 WTC1 WTC0
R/W
(0)
R/W
(0)
WTC
R/W
(0)
Read only
Write only
Readable/Writable
[bit7] WDCS
The WDCS bit is used to select the watchdog timer's clock source. If set to "0", the
watch timer's clock output is selected as the watchdog timer's clock source. If set to "1",
the time-base timer's clock output is selected as the watchdog timer's clock source. This
bit is initialized to "1" by reset.
Note:
If WD CS is mo dified, a s th e tim e-base tim er an d wa tch th e wa tchdog cou nt ma y b e
shorter b y 1 cou nt. Therefore, t o modify WDCS, cle ar the wat chdog timer im mediately
before the clock mode is modified.
[bit6] SCE
This bit indicates that the sub clock's oscillation stabilization wait time has elapsed. This
bit is set to "0" while the oscillation stabilization wait time is in progress. The oscillation
stabilization wait time is fixed to 214 cycles (sub clock). This bit is initialized to "1" by
reset.
[bit5] WTIE
The WTIE bit enables interval interrupts by the watch wait timer. This bit is set to "1" to
enable interrupts or set to "0" to disable them. This bit is initialized to "0" by reset. This
bit can be read and written.
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9.3 List of Registers for Watchdog Timer/Time-base Timer/
Watch Timer
[bit4] WTOF
MB90930Series
The WTOF bit is the watch timer's interrupt request flag. With the WTIE bit set to "1", if
the WTOF bit is set to "1", an interrupt request is generated. The WTOF bit is set to "1"
at intervals set by bits WTC2 to WTC0.
The WTOF bit is cleared by the conditions listed below.
• Writing "0"
• Transition to stop mode
• Reset
Writing "1" has no effect.
Reading by read-modify-write (RMW) instructions always reads "1".
[bit3] WTR
The WTR bit is used to clear all bits in the watch timer's counter to "0". If the WTR bit is
set to "0", the clock counter is cleared. Writing "1" has no effect. "1" is always read.
[bit2 to bit0] WTC2, WTC1, WTC0
The WTC2, WTC1, and WTC0 bits are used to set the watch timer's interval. Table 9.3-4
shows the settings for the interval. Reset initializes bits WTC2 to WTC0 to "000B". This
bit can be read and written.
Setting bits WTC2 to WTC0 requires setting the WTOF bit to "0".
Table 9.3-4 Selection of the Watch Timer Interval
WTC2
WTC1
WTC0
Interval Time *
0
0
0
31.25ms
0
0
1
62.5ms
0
1
0
125ms
0
1
1
250ms
1
0
0
500ms
1
0
1
1.00s
1
1
0
2.00s
1
1
1
4.00s
* : The value of the interval time applies to a sub clock oscillation of 32.768 kHz.
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
9.4
Operation of Watchdog Timer/Time-base Timer/
Watch Timer
This section describes the operation of the watchdog timer/time-base timer/
watch timer.
■ Operation of Watchdog Timer/Time-base Timer/Watch Timer
● Watchdog Timer
The watchdog timer issues a reset request if, for example, due to the program running out of
control, the WTE bit in the WDTC register is not set to "0" within the specified time.
● Time-base Timer
The time-base timer provides such timer functions as acting the watchdog timer's clock source,
and providing the oscillation stabilization wait time for main clock and the PLL clock. It also
provides an interval interrupt function by generating interrupts at regular intervals.
● Watch Timer
The watch timer provides such timer functions as acting the watchdog timer's clock source, and
providing the oscillation stabilization wait time for sub clock. It also provides an interval
interrupt function by generating interrupts at regular intervals.
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
9.4.1
Watchdog Timer Operation
The watchdog timer issues a reset request if, for example due to a program
running out of control, the WTE bit in the WDTC register is not set to "0" within
the specified time.
■ Method of Starting the Watchdog Timer
The watchdog timer can be started by setting the WTE bit in the WDTC register to "0" when it
is stopped. At the same time, the reset generation interval of the watchdog timer is specified in
the bits WT1 and WT0. Only the data at the time of the startup of the watchdog timer is valid
to set the interval.
■ Prohibiting Watchdog Timer Reset
After the startup of the watchdog timer, the 2-bit watchdog counter must be regularly cleared
by the program. Concretely, the WTE bit in the WDTC register must be regularly set to "0".
The watchdog counter is a 2-bit counter that uses the time-base timer's carry-over signal as the
clock source. Therefore, if the time-base timer is cleared, the time before generation of a
watchdog reset may become longer than according to the original settings.
Figure 9.4-1 Watchdog Timer Operation
Time-base Timer
Watchdog
00
01
10
00
01
10
11
00
WTE write
Watchdog start
Watchdog clear
Watchdog reset
generated
■ Watchdog Stop
The watchdog timer can be stopped by various reset sources.
■ Clearing the Watchdog Timer
The watchdog timer is cleared by writing the WTE bit as well as by reset, transition to sleep
mode, stop mode, watch mode.
In watch mode, the watchdog timer's counter is cleared and then the counting stops.
■ Checking Reset Sources
After a reset, the reset source can be determined by checking the PONR, WRST, ERST, and
SRST bits in the watchdog timer control register (WDTC).
■ Interval Time of the Watchdog Timer
Figure 9.4-2 shows the relationship between the timing when the watchdog timer is cleared and
its interval time. The interval time varies depending on the timing for clearing the watchdog
timer, which requires 3.5 to 4.5 times the count clock interval.
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
Figure 9.4-2 Clear Timing and Interval Time of the Watchdog Timer
[WDG timer block diagram]
2-bit counter
Clock
selector
a
WTE bit
Divide-by2 circuit
Count enable
output circuit
b
Divide-by2 circuit
c
Reset circuit
Reset
signal
Count enable and clearing
[Minimum interval time] If the WTE bit is cleared immediately before the rise of count clock
Count start
Counter clear
Count clock a
Divide-by-2 value b
Divide-by-2 value c
Count enabled
Reset signal d
WTE bit clear
7 x (count clock interval/2)
Watchdog reset occurs
[Maximum interval time] If WTE bit is cleared immediately after the rise of count clock
Count start
Counter clear
Count clock a
Divide-by-2 value b
Divide-by-2 value c
Count enabled
Reset signal
WTE bit clear
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9 x (count clock interval/2)
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Watchdog reset occurs
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
9.4.2
Operation of Time-base Timer
The time-base timer provides such timer functions as acting the watchdog
timer's clock source, and providing the oscillation stabilization wait time for
main clock and the PLL clock. It also provides an interval interrupt function by
generating interrupts at regular intervals.
■ Operation of Time-base Timer
The time-base timer consists of an 18-bit counter and uses a main clock as the count clock.
While a main clock is input, count operation continues.
Time-base counter is cleared by the following conditions:
• Power-on reset
• Transition to main stop mode
• Transition to PLL stop mode
• Transition from main clock mode to PLL clock mode
• Transition from sub clock mode to main clock mode
• Transition from sub clock mode to PLL clock mode
• Setting the TBR bit in the TBTC register to "0".
The watchdog timer and interval interrupt functions, which use the output of the time-base
timer, are affected by clearing the time-base timer.
■ Interval Interrupt Function
This function is used to generate interrupts at regular intervals using the time-base counter's
carry-over signal. It sets the TBOF flag each time the interval set by the bits TBC1 and TBC0
in the TBTC register elapses. This flag is set based on the time when the time-base timer is
finally cleared.
If a transition from main clock mode to PLL clock mode occurs, the time-base timer is cleared,
since the time-base timer is used as a timer for waiting for a stabilization of the PLL clock's
oscillation.
If a transition to stop mode occurs, the time-base timer is used as a timer for waiting for
oscillation stabilization when operation resumes. Therefore, the TBOF flag is cleared at the
same time as the mode transition.
■ Interrupts of the Time-base Timer
If the time-base timer counter counts up with the internal count clock and the bit of the selected
interval timer overflows, the interrupt request flag bit (TBOF bit of the TBTC register) is set to
"1". Then, if the interrupt request enable bit is set to enabled (TBIE in the TBTC register =1),
an interrupt request (#34) is sent to the CPU. In the interrupt handling routine, set the TBOF bit
to "0" to clear the interrupt request. In addition, the TBOF bit is set if the specified bit
overflows, irrespective of the TBIE bit value.
When the TBOF bit is set to "1" and the TBIE bit is switched from "disabled" to "enabled" ("0"
to "1"), an interrupt request is generated immediately.
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
Note:
Clear the interrupt request flag bit (TBTC:TBOF) after the time-base timer interrupts are
disabled by the TBIE bit or the Interrupt level mask register (ILM) in the processor status
(PS).
■ Interrupts and EI2OS of Time-base Timer
Table 9.4-1 shows the time-base timer's interrupts and EI2OS.
Table 9.4-1 Time-base Timer Interrupts and EI2OS
Interrupt level setting register
Interrupt
No.
Vector table address
Register name
Address
Lower
Upper
Bank
ICR11
0000BCH
FFFF70H
FFFF71H
FFFF72H
#34 (22H)
EI2OS
×
×: Not available
Notes:
• ICR11 is com monly u sed b y t ime-base t imer int errupts and wat ch tim er (sub clo ck)
interrupts.
The interrupt is therefore used for 2 purposes, but the interrupt level is the same.
• The time-base timer cannot use the extended intelligent I/O service (EI2OS).
■ Timer Function for the Oscillation Stabilization Wait Time
The time-base timer is used as a timer for the oscillation stabilization wait time of the main
clock and the PLL clock. Oscillation stabilization wait time is counted starting from a counter
set to "0" (count clear) and ends when the oscillation stabilization wait time bit overflows. If,
however, a return from the time-base timer mode to the PLL clock mode occurs, the time-base
timer counter is not cleared and indicates a time on the way of counting. Table 9.4-2 shows the
clearing of the time-base counter and the oscillation stabilization wait time.
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
Table 9.4-2 Clearing the Time-base Timer Counter and Oscillation Stabilization Wait Time
Counter clear
TBOF clear
Oscillation stabilization
wait time
Writing "0" to TBR bit in TBTC
Y
Y
-
Power-on reset
Y
Y
Main clock oscillation
stabilization wait time
Y
Y
Main clock oscillation
stabilization wait time
Releasing sub stop mode
N
N
Sub clock oscillation
stabilization wait time
Transition from main clock mode to
PLL clock mode (MCS=1 → 0)
Y
Y
PLL clock oscillation
stabilization wait time
Transition from sub clock mode to
main clock mode (SCS=0 → 1)
Y
Y
Main clock oscillation
stabilization wait time
Transition from sub clock mode to
PLL clock mode (MCS=0, SCS=0 → 1)
Y
Y
Main clock oscillation
stabilization wait time
Releasing time-base timer mode
N
N
None
Releasing sleep mode
N
N
None
Operation
Releasing main stop mode
Releasing PLL stop mode
Y: Used
N: Not used
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9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
9.4.3
Operation of Watch Timer
The watch timer provides such timer functions as acting the watchdog timer's
clock source, and providing the oscillation stabilization wait time for sub clock.
It also provides an interval interrupt function by generating interrupts at regular
intervals.
■ Operation of Watch Timer
The watch timer consists of a 15-bit counter that uses a sub clock as the count clock. While a
sub oscillation clock is input, count operation continues. The watch timer is cleared by poweron reset, by a transition to stop mode, and by the writing WTR bit in the WTC register to "0".
Note:
The wat chdog t imer an d in terval in terrupt, which u se th e wat ch t imer's ou tput, a re
affected by clearing the watch timer.
When setting the watch timer clear bit (WTR) of the watch timer control register (WTC) to
"0" to clear the watch timer, perform such an operation while the interrupts of the watch
timer a re disab led wi th t he WTC overflow interrupt en able bit ( WTIE) set t o "0". In
addition, prior to enabling the interrupts, clear the interrupt requests by setting "0" to the
overflow bit (WTOF) of WTC to "0".
■ Interval Interrupt Function of Watch Timer
The interval interrupt function generates interrupts at regular intervals based on carry-over
signals of the watch timer. It sets the WTOF flag at regular intervals that are specified by the
WTC2 to WTC0 bits of the WTC register. The timing when the flag is set is based on the time
when the watch timer is finally cleared.
In a transition to stop mode, the watch timer is used to provide a timer for the oscillation
stabilization wait time before operation resumes. Therefore, the WTOF flag is also cleared at a
mode transition.
■ Interrupts and EI2OS of Watch Timer
Table 9.4-3 shows the watch timer's interrupts and EI2OS.
Table 9.4-3 Watch Timer Interrupts and EI2OS
Interrupt
No.
Interrupt level setting register
Vector table address
Register name
Address
Lower
Upper
Bank
ICR09
0000B9H
FFFF84H
FFFF85H
FFFF86H
#30 (1EH)
EI2OS
×
×: Not available
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer
MB90930Series
Notes:
• The watch t imer an d t he r eal-time wat ch t imer sh are t he sam e int errupt ve ctor. In
addition, ICR09 is commonly used by real-time watch timer interrupts and PPG timer 2
to PPG timer 5 interrupts, and the interrupt level is the same.
• The watch timer cannot use the extended intelligent I/O service (EI2OS).
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.5 Notes on Using the Watchdog Timer/Time-base Timer
MB90930Series
9.5
Notes on Using the Watchdog Timer/Time-base
Timer
This section provides the notes on using the watchdog timer and the effects on
peripheral functions of clearing an interrupt request when using the time-base
timer and clearing the time-base timer.
■ Notes on Using the Watchdog Timer
● Stopping the watchdog timer
The watchdog timer is stopped by any of the reset sources.
● Interval time
The interval time is determined by a count clock that uses a carry-over signal of the time-base
timer or watch timer. For this reason, the watchdog timer's interval time may be longer than
according to the original setting when the counter as the clock source is cleared respectively.
As the time-base timer can be cleared by the transition from the main clock mode to the PLL
clock mode, the transition from the sub clock mode to the main clock mode, the transition from
the sub clock mode to the PLL clock mode, as well as writing "0" to the time-base timer clear
bit (TBR) of the time-base timer control register (TBTC), special attention is needed.
● Selection of interval time
The interval time can be set at the startup of the watchdog timer. Data written during other than
the startup is ignored.
● Notes on programming
To make a program that repeatedly clears the watchdog timer in the main loop, the processing
time of the main loop, including interrupt handling, cannot exceed the minimum interval time
of the watchdog timer.
● Watchdog timer operation in time-base timer mode
In time-base timer mode, the watchdog timer stops while the time-base timer operates.
■ Notes on Using the Time-base Timer
● Clearing an interrupt request
Clearing the TBOF bit of the time-base timer control register must be performed via the TBIE
bit or the interrupt level mask register (ILM) of the processor status register (PS) while timebase timer interrupts are masked.
● Effects of clearing the time-base timer
The following operations are affected by clearing the time-base timer's counter.
• When an interval timer function (interval interrupt) by the time-base timer is used
• When the watchdog timer is used.
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.5 Notes on Using the Watchdog Timer/Time-base Timer
MB90930Series
● Using the oscillation stabilization wait time timer
In main stop mode, the main clock oscillation stops at power-on. Therefore, the main clock,
which uses the operation clock provided from the time-base timer, requires an oscillation
stabilization wait time after the oscillator has started operation. Select an appropriate
oscillation stabilization wait time for the type of resonator connected to the main clock's
oscillator (clock generation block). For details, see Section "5.6 Oscillation Stabilization Wait
Time".
● Notes on peripheral functions whose clock is provided by the time-base timer
In the mode in which main clock oscillation stops, the counter is cleared and the time-base timer
stops. In addition, the clock is provided from the time-base timer in the state after initialization if
the time-base timer's counter is cleared. Therefore, the "H" level may be shortened or the "L"
level may be prolonged by 1/2 an interval at maximum. Although the watchdog timer's clock is
also provided in the state after initialization, the watchdog timer's counter is cleared as well,
causing the watchdog timer to operate with the standard interval.
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9.5 Notes on Using the Watchdog Timer/Time-base Timer
MB90930Series
■ Operation of Time-base Timer
Figure 9.5-1 shows the operation in the following states:
• When a power-on reset occurs
• When transition to sleep mode occurs during operation of the interval timer function.
• When transition to stop mode occurs.
• When a counter clear request occurs.
Transition to stop mode clears the time-base timer, and operation stops. At the return from the stop
mode, the time-base timer counts the oscillation stabilization wait time.
Figure 9.5-1 Operation of Time-base Timer
Counter value
3FFFFH
Clearing by transition
to stop mode
Oscillation
stabilization
wait overflow
00000H
CPU operation
started
Power-on reset
(option)
Interval
Counter cleared
(TBTC:TBR=0)
(TBTC:TBC1, TBC0=11B)
Cleared by interrupt handling routine
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
Sleep
Interval interrupt sleep released
Stop
STP bit
(LPMCR register)
Stop cleared by external interrupt
If the interval time selection bits (TBTC: TBC1, TBC0) in the time-base timer control register
is set to "11B" (219/HCLK).
: Oscillation stabilization wait time
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.6 Program Example for Watchdog Timer/Time-base Timer
9.6
MB90930Series
Program Example for Watchdog Timer/Time-base
Timer
A program example for the watchdog timer/time-base timer is shown below.
■ Program Example for Watchdog Timer
● Specification of processing
The watchdog timer is cleared with every loop in the main program.
The main program has to go around once within the minimum interval time of the watchdog
timer.
[Coding example]
WDTC
EQU
0000A8H
;Watchdog timer control register
WTE
EQU
WDTC:2
;Watchdog control bit
;---------Main program-------------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) should be initialized
WDG_START:
MOV
;Watchdog timer started
;Interval time of 221±218 cycles selected
;---------Main loop----------------------------------------------------------MAIN:
CLRB
I:WTE
;Watchdog timer cleared
;
:
2 bits regularly cleared
;
User process
;
:
JMP
MAIN
;Loop by the period shorter than the
;interval time of the watchdog timer
CODE
ENDS
;---------Vector setting-----------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Set to single-chip mode
VECT
ENDS
ENDS
START
278
WDTC,
#00000011B
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.6 Program Example for Watchdog Timer/Time-base Timer
MB90930Series
■ Program Example for Time-base Timer
● Specification of processing
This program repeatedly generates interval interrupt at 212/HCLK (HCLK: oscillation clock).
The interval time at this point of time is approx. 1.0 ms (at 4 MHz operation).
[Coding example]
ICR12
EQU
;Interrupt control register for the
;time-base timer
TBTC
EQU
0000A9H
;Time base-timer control register
TBOF
EQU
TBTC:3
;Interrupt request flag bit
;---------Main program-------------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) should be initialized
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR12, #00H
;Interrupt level 0 (highest)
MOV
I:TBTC, #10010000B ;Upper 3 bits are fixed
;Interrupts enabled, TBOF clear
;Counter clear
;Selection of 212/HCLK interval time
MOV
ILM, #07H
;ILM in PS is set to level 7
OR
CCR, #40H
;Interrupt enabled
LOOP:
MOV
A, #00H
;Infinite loop
MOV
A, #01H
BRA
LOOP
;---------Interrupt program--------------------------------------------------WARI:
CLRB
I:TBOF
;Clear interrupt request flag
;
:
;
User process
;
:
RETI
;Return from interrupt
CODE
ENDS
;---------Vector setting-----------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF70H
;Setting vector to interrupt #35(23H)
DSL
WARI
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single-chip mode
VECT
ENDS
ENDS
START
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CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock)
9.6 Program Example for Watchdog Timer/Time-base Timer
MB90930Series
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CHAPTER 10
INPUT CAPTURE
This chapter describes the input capture
operation.
10.1 Outline of Input Capture
10.2 List of Input Capture Registers
10.3 Description of Operations
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CHAPTER 10 INPUT CAPTURE
10.1 Outline of Input Capture
10.1
MB90930 Series
Outline of Input Capture
The input capture unit consists of 1 16-bit free-run timer and 8 16-bit input
captures.
■ Configuration of Input Capture
● Input capture (× 8)
The input capture consists of 8 independent external input pins, their corresponding capture
registers and control registers. Based on detection of any edges of signals input from external
input pins, the 16-bit free-run timer value can be stored in the capture register and an interrupt
can be generated at the same time.
Valid edges (rising edge, falling edge and both edges) of the external input signal can be
selected.
8 input captures can operate independently.
Interrupts can be generated at any valid edge of the external input signal.
● 16-bit free-run timer (× 1)
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, a 16-bit compare
clear register, and a prescaler. The output value of this counter is used to provide the basic time
(base timer) for the input capture.
The counter operation clock can be selected from among eight types.
There are eight internal clocks: φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128 (φ : Machine clock).
An interrupt can be generated by overflows of the counter value and compare matching with
the compare clear register (compare matching requires a mode setting).
The counter value is initialized to "0000H" by reset, program clear, and compare matching with
the compare clear register.
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10.1 Outline of Input Capture
MB90930 Series
10.1.1
Block Diagram of Input Capture
Input capture consists of the following blocks.
■ Block Diagram of Input Capture
Figure 10.1-1 Block Diagram of Input Capture Unit 0
16-bit free-run timer
Edge detection circuit
IN3/IN3R
Input capture data register 3 (IPCP3)
Pin
IN2/IN2R
input capture data register 2 (IPCP2)
Pin
Input capture edge register
IEI3
IEI2
2
Input capture control
status register (ICS23)
ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20
Input capture
interrupt request
Input capture control
status register (ICS01)
Internal data bus
2
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
2
2
ICUS1
IN1
ICUS0 IEI1 IEI0
Input capture edge register (ICE01)
Pin
Input capture data register 1 (IPCP1)
LIN-UART1
IN0
Pin
Input capture data register 0 (IPCP0)
LIN-UART0
Edge detection circuit
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CHAPTER 10 INPUT CAPTURE
10.1 Outline of Input Capture
MB90930 Series
Figure 10.1-2 Block Diagram of Input Capture Unit 1
16-Bit free-run timer
Edge detection circuit
IN7/IN7R
Pin
Input capture data register 7 (IPCP7)
LIN-UART3
IN6/IN6R
Pin
Input capture data register 6 (IPCP6)
LIN-UART2
2
ICUS7
2
ICUS6 IEI7
IEI6
Input capture edge register (ICE67)
2
ICP7 ICP6 ICE7 ICE6 EG71 EG70 EG61 EG60
Input capture interrupt
request
Input capture control
status register (ICS45)
Internal data bus
Input capture control
status register (ICS67)
ICP5 ICP4 ICE5 ICE4 EG51 EG50 EG41 EG40
2
2 Input capture edge register (ICE45)
IEI5
IEI4
IN5/IN5R
Pin
Input capture data register 5 (IPCP5)
IN4/IN4R
Pin
Input capture data register 4 (IPCP4)
Edge detection circuit
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10.2
List of Input Capture Registers
CHAPTER 10 INPUT CAPTURE
10.2 List of Input Capture Registers
This section lists the input capture registers.
■ List of Registers for 16-bit Free-run Timer Section
Figure 10.2-1 lists registers for the 16-bit free-run timer section.
Figure 10.2-1 List of Registers for 16-bit Free-run Timer Section
Compare clear register (Upper)
Address: 000025H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
R/W
(X)
CL14
R/W
(X)
CL13
R/W
(X)
CL12
R/W
(X)
CL11
R/W
(X)
CL10
R/W
(X)
CL09
R/W
(X)
CL08
R/W
(X)
CPCLR
Compare clear register (Lower)
Address: 000024H
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
R/W
(X)
CL06
R/W
(X)
CL05
R/W
(X)
CL04
R/W
(X)
CL03
R/W
(X)
CL02
R/W
(X)
CL01
R/W
(X)
CL00
R/W
(X)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T15
R/W
(0)
T14
R/W
(0)
T13
R/W
(0)
T12
R/W
(0)
T11
R/W
(0)
T10
R/W
(0)
T09
R/W
(0)
T08
R/W
(0)
CPCLR
Timer data register (Upper)
Address: 000027H
Initial value →
TCDT
Timer data register (Lower)
Address: 000026H
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
R/W
(0)
T06
R/W
(0)
T05
R/W
(0)
T04
R/W
(0)
T03
R/W
(0)
T02
R/W
(0)
T01
R/W
(0)
T00
R/W
(0)
TCDT
Timer control status register (Upper)
Address: 000029H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
R/W
(0)
Reserved
(-)
MSI2
R/W
(0)
MSI1
R/W
(0)
MSI0
R/W
(0)
ICLR
R/W
(0)
ICRE
R/W
(0)
(-)
TCCSH
Timer control status register (Lower)
Address: 000028H
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IVF
R/W
(0)
IVFE
R/W
(0)
STOP
R/W
(0)
MODE
R/W
(0)
SCLR
R/W
(0)
CLK2
R/W
(0)
CLK1
R/W
(0)
CLK0
R/W
(0)
TCCSL
R/W: Readable/writable
X:
Undefined value
-:
Undefined
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MB90930 Series
■ List of Registers for Input Capture Section
Figure 10.2-2 lists of registers for the input capture section.
Figure 10.2-2 List of Registers for Capture Section
Input capture data register (Upper)
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
bit15
ch.0 000061H
ch.1 000063H
ch.2 000065H
ch.3 000067H
ch.4 003941H
ch.5 003943H
ch.6 003945H
ch.7 003947H
bit13
bit12
bit11
bit10
bit9
bit8
IPCP0 to
IPCP7
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
Input capture data register (Lower)
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
bit14
R
(X)
bit7
ch.0 000060H
ch.1 000062H
ch.2 000064H
ch.3 000066H
ch.4 003940H
ch.5 003942H
ch.6 003944H
ch.7 003946H
R
(X)
R
(X)
bit6
bit5
R
(X)
bit4
R
(X)
bit3
R
(X)
bit2
R
(X)
bit1
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
← Initial value
bit0
IPCP0 to
IPCP7
← Initial value
Input capture control status register (Upper)
Address: 00006AH
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
R/W
(0)
ICP2
R/W
(0)
ICE3
R/W
(0)
ICE2
R/W
(0)
EG31
R/W
(0)
EG30
R/W
(0)
EG21
R/W
(0)
EG20
R/W
(0)
ICS23
Input capture control status register (Lower)
bit7
bit6
bit5
Address: 000068H
ICP1 ICP0
ICE1
R/W
R/W
R/W
Initial value →
(0)
(0)
(0)
Input capture control status register (Upper)
Address: 0000D2H
Initial value →
bit4
bit3
bit2
bit1
bit0
ICE0
R/W
(0)
EG11
R/W
(0)
EG10
R/W
(0)
EG01
R/W
(0)
EG00
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP7
R/W
(0)
ICP6
R/W
(0)
ICE7
R/W
(0)
ICE6
R/W
(0)
EG71
R/W
(0)
EG70
R/W
(0)
EG61
R/W
(0)
EG60
R/W
(0)
ICS01
ICS67
Input capture control status register (Lower)
Address: 0000D0H
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP5
R/W
(0)
ICP4
R/W
(0)
ICE5
R/W
(0)
ICE4
R/W
(0)
EG51
R/W
(0)
EG50
R/W
(0)
EG41
R/W
(0)
EG40
R/W
(0)
ICS45
(Continued)
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(Continued)
Input capture edge register (Upper)
Address: 00006BH
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(-)
(-)
(-)
(-)
(-)
(-)
IEI3
R
(X)
IEI2
R
(X)
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(-)
ICUS1
R/W
(0)
(-)
ICUS0
R/W
(0)
IEI1
R
(X)
IEI0
R
(X)
ICE23
Input capture edge register (Lower)
bit15
Address: 000069H
Initial value →
(-)
(-)
Input capture edge register (Upper)
Address: 0000D3H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(-)
(-)
(-)
ICUS7
R/W
(0)
(-)
ICUS6
R/W
(0)
IEI7
R
(X)
IEI6
R
(X)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(-)
(-)
(-)
(-)
(-)
(-)
IEI5
R
(X)
IEI4
R
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IN7R
R/W
(0)
IN6R
R/W
(0)
IN5R
R/W
(0)
IN4R
R/W
(0)
IN3R
R/W
(0)
IN2R
R/W
(0)
(-)
(-)
ICE01
ICE67
Input capture edge register (Lower)
Address: 0000D1H
Initial value →
ICE45
Input capture Input Select Register
Address: 000048H
Initial value →
R/W:
R:
W:
X:
-:
ICISR
Readable/writable
Read only
Write only
Undefined value
Undefined
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10.2.1
MB90930 Series
Detailed Description of the Input Capture
Registers
There are three types of input capture registers:
• Input capture register (IPCP0 to IPCP7)
• Input capture control registers (ICS01/ICS23/ICS45/ICS67)
• Input capture input select register (ICISR)
■ Input Capture Register (IPCP0 to IPCP7)
The IPCP register is used to store the value of the 16-bit free-run timer at detection of a valid
edge of the corresponding external pin input waveform (word access is required. Writing is
unavailable).
Figure 10.2-3 Configuration of Input Capture Data Register (IPCP0 to IPCP7)
Input capture data register (Upper)
Address: ch.0 000061H
Address: ch.1 000063H
Address: ch.2 000065H
Address: ch.3 000067H
Address: ch.4 003941H
Address: ch.5 003943H
Address: ch.6 003945H
Address: ch.7 003947H
bit15
ch.0 000060H
ch.1 000062H
ch.2 000064H
ch.3 000066H
ch.4 003940H
ch.5 003942H
ch.6 003944H
ch.7 003946H
bit13
bit12
bit11
bit10
bit9
bit8
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
R
(X)
bit7
Input capture data register (Lower)
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
bit14
R
(X)
R
(X)
R
(X)
bit6
bit5
bit4
R
(X)
bit3
R
(X)
bit2
R
(X)
bit1
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
IPCP0 to
IPCP7
← Initial value
bit0
IPCP0 to
IPCP7
← Initial value
R: Read only
X: Undefined value
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MB90930 Series
■ Input Capture Control Status Register (ICS01/ICS23/ICS45/ICS67)
Figure 10.2-4 Configuration of Input Capture Control Status Register
(ICS01/ICS23/ICS45/ICS67)
Input capture control status register (Upper)
Address: 00006AH
Initial value →
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
R/W
(0)
ICP2
R/W
(0)
ICE3
R/W
(0)
ICE2
R/W
(0)
EG31
R/W
(0)
EG30
R/W
(0)
EG21
R/W
(0)
EG20
R/W
(0)
ICS23
Input capture control status register (Lower)
bit7
bit6
bit5
Address: 000068H
ICP1 ICP0
ICE1
R/W
R/W
R/W
Initial value →
(0)
(0)
(0)
Input capture control status register (Upper)
bit7
bit6
bit5
Address: 0000D2H
ICP7 ICP6
ICE7
R/W
R/W
R/W
Initial value →
(0)
(0)
(0)
Input capture control status register (Lower)
Address: 0000D0H
Initial value →
R/W :
bit4
bit3
bit2
bit1
bit0
ICE0
R/W
(0)
EG11
R/W
(0)
EG10
R/W
(0)
EG01
R/W
(0)
EG00
R/W
(0)
bit4
bit3
bit2
bit1
bit0
ICE6
R/W
(0)
EG71
R/W
(0)
EG70
R/W
(0)
EG61
R/W
(0)
EG60
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP5
R/W
(0)
ICP4
R/W
(0)
ICE5
R/W
(0)
ICE4
R/W
(0)
EG51
R/W
(0)
EG50
R/W
(0)
EG41
R/W
(0)
EG40
R/W
(0)
ICS01
ICS67
ICS45
Readable/Writable
[bit7, bit6]: ICP7 to ICP0
These are input capture interrupt flags. When any valid edge of external input pins is
detected, these bits are set to "1". With the interrupt enable bits (ICE7 to ICE0) set, an
interrupt can be generated at detection of a valid edge. The corresponding bits are
cleared by writing "0". Writing "1" has no effect. In read-modify-write (RMW)
instructions, "1" is read.
0
No valid edge detected (initial value)
1
Valid edge detected
ICPn: n corresponds to the channel number of the input capture.
[bit5, bit4]: ICE7 to ICE0
These bits are input capture interrupt enable bits. With the ICE bits set to "1", an input
capture interrupt is generated if the corresponding interrupt flags (ICP7 to ICP0) are set
to "1".
0
Interrupt disabled (Initial value)
1
Interrupt enabled
ICEn: n corresponds to the channel number of the input capture.
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MB90930 Series
[bit3 to bit0]: EGn1, EGn0 (n=7 to 0)
These bits are used to select the polarity of a valid edge from the external input. They are
also used for enabling input capture operation.
EGn1
EGn0
0
0
Edge detection polarity
No edge detected (stop state) (initial value)
0
1
Rising edge detected ↑
1
0
Falling edge detected ↓
1
1
Both edges detected ↑ & ↓
EGn1/EGn0: n corresponds to the channel number of the input capture.
■ Input Capture Input Select Register (ICISR)
Figure 10.2-5 Configuration of Input Capture Input Select Register (ICISR)
Input capture Input Select Register
Address: 000048H
Initial value →
R/W :
-:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IN7R
R/W
(0)
IN6R
R/W
(0)
IN5R
R/W
(0)
IN4R
R/W
(0)
IN3R
R/W
(0)
IN2R
R/W
(0)
(-)
(-)
ICISR
Readable/Writable
Undefined
[bit7 to bit2] IN7R to IN2R
Each bit selects the input capture input port of each channel in ch.7 to ch.2.
[bit1, bit0] Undefined bits
Read value is undefined. Writing has no effect on operation.
INnR
Input Capture input
Set pin IN7 to IN2 as input capture input (initial value)
0
ICISR
Input Port
IN2R (bit 2)
IN2 : PC2
IN3R (bit 3)
IN3 : PC1
IN4R (bit 4)
IN4 : P11
IN5R (bit 5)
IN5 : P10
IN6R (bit 6)
IN6 : PC7
IN7R (bit 7)
IN7 : PC6
Set pin IN7R to IN2R as input capture input
1
ICISR
Input Port
IN2R (bit 2)
IN2 : P54
IN3R (bit 3)
IN3 : PE2
IN4R (bit 4)
IN4 : P57
IN5R (bit 5)
IN5 : P56
IN6R (bit 6)
IN6 : PE1
IN7R (bit 7)
IN7 : PE0
INnR: n corresponds to the channel number of input capture
There is only one input capture input for ch.1 and ch.0.
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10.2 List of Input Capture Registers
MB90930 Series
10.2.2
Input Capture Edge Register (ICE)
The input capture edge register has a function to indicate the selected edge
direction and to select whether the input signal is input from either external pin
or LIN-UART. By cooperating with the LIN-UART, the baud rate measurement at
the LIN slave operation can be performed.
The correspondence between ICE01 to ICE67 / channel name and input pin
(UART) name is shown as follows.
ICE01: input capture ch.0, ch.1 IN0 (/UART0)
IN1 (/UART1)
ICE23: input capture ch.2, ch.3 IN2
IN3
ICE45: input capture ch.4, ch.5 IN4
IN5
ICE67: input capture ch.6, ch.7 IN6 (/UART2)
IN7 (/UART3)
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MB90930 Series
■ Input Capture Edge Register (ICE)
Figure 10.2-6 Input Capture Edge Register (ICE)
ICE01
Address: 000069H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
ICUS1
ICUS0 IEI1
IEI0
R/W
R/W
R
R
Initial value
XXX0X0XX B
bit10
ICUS0
Input signal selection bit0
0
Input signal of external pin IN0
1
Signal from UART0
bit12
ICUS1
Input signal selection bit 1
0
Input signal of external pin IN1
1
Signal from UART1
ICE23
Address: 00006BH
ICE45
Address: 0000D1H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
IEI3
IEI2
R
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
IEI5
IEI4
R
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
ICE67
Address: 0000D3H
bit8
ICUS7
ICUS6
IEI7
IEI6
R/W
R/W
R
R
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Initial value
bit8
XXX0X0XX B
IEIn
0
1
Detected edge
indication bit n
Detects falling edge
Detects rising edge
bit9
IEIm
0
1
bit10
ICUS6
R/W : Readable/writable
: Read only
R
X
: Undefined
: Undefined value
: Initial value
n = 0, 2, 4, 6 m = n+1
292
0
1
Detected edge
indication bit m
Detects falling edge
Detects rising edge
Input signal selection bit 6
Input signal of external pin IN6
Signal from UART2
bit12
ICUS7
0
1
Input signal selection bit7
Input signal of external pin IN7
Signal from UART3
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10.2 List of Input Capture Registers
MB90930 Series
Table 10.2-1 Functions of Input Capture Edge Register 01(ICE01)
Bit name
Function
bit15
Undefined bits
When reading: The value is undefined.
When writing: No effect.
bit12
ICUS1:
Input signal selection
bit 1
This bit selects the input signal used as the trigger of input capture 1.
When set to "0": Select the external pin IN1.
When set to "1": Select the LIN-UART1
bit11
Undefined bit
When reading: The value is undefined.
When writing: No effect.
bit10
ICUS0:
Input signal selection
bit 0
This bit selects the input signal used as the trigger of input capture 0.
When set to "0": Select the external pin IN0.
When set to "1": Select the LIN-UART0.
IEI1:
Detected edge indication
bit 1
This bit indicates the type of edges detected (rising/falling) by input capture 1.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
The value of this bit is disabled when the capture operation is stopped
(ICS01: EG11, EG10=00B).
IEI0:
Detected edge indication
bit0
This bit indicates the type of edge (rising/falling) detected by input capture 0.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
The value of this bit is disabled when the capture operation is stopped
(ICS01: EG01, EG00=00B).
to
bit13
bit9
bit8
Table 10.2-2 Functions of Input Capture Edge Register 23, 45(ICE23, ICE45)
Bit name
Function
bit15
to
Undefined bits
When reading: The value is undefined.
When writing: No effect.
IEI3, IEI5:
Detected edge indication
bit 3, bit 5
This bit indicates the type of edge (rising/falling) detected by input capture 3, 5.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
This bit value is disabled when the capture operation is stopped
(ICSnm:EGm1, EGm0=00B). (n = 2, 4 m = n+1)
IEI2, IEI4:
Detected edge indication
bit 2, bit 4
This bit indicates the type of edge (rising/falling) detected by input capture 2, 4.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
This bit is disabled when the capture operation is stopped.
(ICSnm:EGn1, EGn0=00B). (n = 2, 4 m = n+1)
bit10
bit9
bit8
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Table 10.2-3 Functions of Input Capture Edge Register 67(ICE67)
Bit name
Function
bit15
Undefined bits
When reading: The value is undefined.
When writing: No effect.
bit12
ICUS7:
Input signal selection bit 7
This bit selects the input signal used as the trigger of the input capture 7.
When set to "0": Select the external pin IN7.
When set to "1": Select the LIN-UART3
bit11
Undefined bit
When reading: The value is undefined.
When writing: No effect.
bit10
ICUS6:
Input signal selection bit 6
This bit selects the input signal used as the trigger of input capture 6.
When set to "0": Select the external pin IN6
When set to "1": Select the LIN-UART2
IEI7:
Detected edge indication bit
7
This bit indicates the type of edge (rising/falling) detected by input capture 7.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
The value of this bit is disabled when the capture operation is stopped
(ICS67: EG71, EG70=00B)
IEI6:
Detected edge indication bit
6
This bit indicates the type of edge (rising/falling) detected by input capture 6.
• This bit is read-only.
"0": Indicates that falling edge has been detected.
"1": Indicates that rising edge has been detected.
Note:
The value of this bit is disabled when the capture operation is stopped
(ICS67: EG61, EG60=00B)
to
bit13
bit9
bit8
Note:
For in put cap tures 0 ,1,6, a nd 7 , if t he inpu t sign al is select ed t o the LI N-UART
(ICEnm:ICUS), the input capture is u sed to calculate the baud rate when the LIN-UART
operates the LIN slave. In this case, it must be set to the input capture interrupt enable
(ICSnm:ICEn=1 or ICEm=1) and to the detection of both edges (ICSnm:EGn1, EGn0=11B
or EGm1, EGm0=11 B). See Sect ion "17 .7.3 Operation wit h LIN Fun ction (O peration
Mode 3)" for details of the baud rate calculation.
n = 0, 2, 4, 6
m = n+1
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10.2 List of Input Capture Registers
MB90930 Series
10.2.3
Detailed Description of 16-Bit Free-run Timer
Register
There are three types of 16-bit free-run timer registers:
• Timer data register (TCDT)
• Compare clear register (CPCLR)
• Timer control status register (TCCSH, TCCSL)
■ Timer Data Register (TCDT)
Figure 10.2-7 Configuration of the Timer Data Register (TCDT)
Timer data register (Upper)
Address: 000027H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T15
R/W
(0)
T14
R/W
(0)
T13
R/W
(0)
T12
R/W
(0)
T11
R/W
(0)
T10
R/W
(0)
T09
R/W
(0)
T08
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
R/W
(0)
T06
R/W
(0)
T05
R/W
(0)
T04
R/W
(0)
T03
R/W
(0)
T02
R/W
(0)
T01
R/W
(0)
T00
R/W
(0)
TCDT
Timer data register (Lower)
Address: 000026H
Initial value →
R/W :
TCDT
Readable/Writable
This is a register that can read the count value for the 16-bit free-run timer. The counter value
is cleared to "0000H" at a reset. Be sure the write operation is always performed in stop
(STOP=1) state. The timer value can be set when writing to this register only in the stop
(STOP=1) state. This register requires word access. The 16-bit free-run timer is initialized by
the following:
• Reset
• Clearing (CLR) the timer control/status registers
• Matching the compare clear register value and timer counter value (this requires to set a
mode)
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10.2 List of Input Capture Registers
MB90930 Series
■ Compare Clear Register (CPCLR)
Figure 10.2-8 Configuration of the Compare Clear Register (CPCLR)
Compare clear register (Upper)
Address: 000025H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
R/W
(X)
CL14
R/W
(X)
CL13
R/W
(X)
CL12
R/W
(X)
CL11
R/W
(X)
CL10
R/W
(X)
CL09
R/W
(X)
CL08
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
R/W
(X)
CL06
R/W
(X)
CL05
R/W
(X)
CL04
R/W
(X)
CL03
R/W
(X)
CL02
R/W
(X)
CL01
R/W
(X)
CL00
R/W
(X)
CPCLR
Compare clear register (Lower)
Address: 000024H
Initial value →
R/W :
X:
CPCLR
Readable/Writable
Undefined value
This compare clear register is a 16-bit compare register used for comparison with a 16-bit freerun timer. As the register value at initialization is not specified, enable its operation after a
value has been set. This register requires word access. When "1" has been set to the MODE bit
of timer control status register (TCCSH, TCCSL), if the register value matches the value of the
16-bit free-run timer value, the 16-bit free-run timer value is cleared to "0000H". In addition,
when the register value matches the value of the 16-bit free run timer, the compare clear
interrupt flag is set. When the compare clear interrupt flag is "1", if interrupts are enabled, an
interrupt request is issued to the CPU.
■ Timer Control Status Register (TCCSH, TCCSL)
Figure 10.2-9 Configuration of the Timer Control Status Register (TCCSH, TCCSL)
Timer control status register (Upper)
Address: 000029H
Initial value →
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
R/W
(0)
Reserved
(-)
(-)
MSI2
R/W
(0)
MSI1
R/W
(0)
MSI0
R/W
(0)
ICLR
R/W
(0)
ICRE
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IVF
R/W
(0)
IVFE
R/W
(0)
STOP
R/W
(0)
MODE
R/W
(0)
SCLR
R/W
(0)
CLK2
R/W
(0)
CLK1
R/W
(0)
CLK0
R/W
(0)
TCCS
Timer control status register (Lower)
Address: 000028H
Initial value →
R/W :
-:
TCCS
Readable/Writable
Undefined
[bit15]: ECKE
This bit is used to select whether to use an internal or external source for the count clock
of the 16-bit free-run timer. As the clock is updated immediately after writing the ECKE
bit, be sure to change this bit only while input capture is stopped.
296
0
Internal clock source is selected (initial value)
1
Clock is input from the external pin (FRCK)
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CHAPTER 10 INPUT CAPTURE
10.2 List of Input Capture Registers
MB90930 Series
Note:
With th e in ternal clo ck select ed, specify the cou nt clock in bit2 t o bit 0 (CLK2 to CLK0 ).
This count clock works as a base clock. If the clock is input from FRCK, set bit6 of DDR5
to "0".
[bit14]: Reserved bit
"1" is always set at writing. "1" is always read.
[bit13]: Undefined bit
Read value is undefined. Writing has no effect on operation.
[bit12 to bit10]: MSI2 to MSI0
These bits are used to set the count for masking compare clear interrupts. They are set with
the 3-bit reload counter: Every time the counter value is set to "000B", the count value is
reloaded. In addition, the counter value is loaded when writing to this register. The
masking count = the set count (For example, for masking twice and throwing an interrupt
the third time, set these bits to "010B"). However, note that setting these bits to "000B"
does not mask interrupt sources.
[bit9]: ICLR
This bit is an interrupt request flag for compare clear. The ICLR bit is set to "1" if the
compare clear register value and the value of the 16-bit free-run timer value match. An
interrupt occurs if the interrupt request enable bit (bit8: ICRE) is set. The ICLR bit is
cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modifywrite (RMW) instruction.
0
No interrupt request (initial value)
1
Interrupt requested
[bit8]: ICRE
This bit is an interrupt enable bit for compare clear. If, with the ICRE bit set to "1", the
interrupt flag (bit9: ICLR) is set to "1", an interrupt is generated.
0
Interrupt disabled (initial value)
1
Interrupt enabled
[bit7]: IVF
This bit is an interrupt request flag for the 16-bit free-run timer. If the 16-bit free-run
overflows, the IVF bit is set to "1". If the interrupt request enable bit (bit6: IVFE) is set,
an interrupt is generated. The IVF bit is cleared by writing "1". Writing "1" has no effect.
"1" is always read by a read-modify-write (RMW) instruction.
CM44-10150-1E
0
No interrupt request (initial value)
1
Interrupt requested
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CHAPTER 10 INPUT CAPTURE
10.2 List of Input Capture Registers
MB90930 Series
[bit6]: IVFE
This bit is an interrupt enable bit for the 16-bit free-run timer. If, with the IVFE bit set to
"1", the interrupt flag (bit7: IVF) is set to "1", an interrupt is generated.
0
Interrupt disabled (initial value)
1
Interrupt enabled
[bit5]: STOP
This bit is used to stop counting the 16-bit free-run timer. Writing "1" will stop counting
the timer. Writing "0" starts counting the timer.
0
Count enabled (operation) (initial value)
1
Count disabled (stopped)
[bit4]: MODE
This bit is used to set the initialization condition of the 16-bit free-run timer. If this bit is
set to "0", the counter is initialized by reset and the clear bit (bit3:SCLR). If this bit is set
to "1", the counter can be initialized by matching with the compare clear register
(CPCLR) value in addition to reset and the clear bit (bit3:SCLR).
The counter value is initialized when the count value changes.
0
Initialized by reset or the clear bit (initial value)
1
Initialized by reset, the clear bit, or the compare clear register
[bit3]: SCLR
This bit is used to initialize the 16-bit free-run timer to "0000H" during operation.
Writing "1" initializes the counter to "0000H". Writing "0" has no effect. The read value
is always "0". The counter value is initialized when the count value changes.
To initialize in timer stop mode, write "0000H" to the data register.
SCLR
Meaning of flag
0
No meaning (initial value)
1
Counter initialized to "0000H"
Note:
Writing "0" t o t his bit be fore th e ne xt cou nt clo ck cycle af ter wr iting "1" p revents t he
counter value from being initialized.
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CHAPTER 10 INPUT CAPTURE
10.2 List of Input Capture Registers
MB90930 Series
[bit2 to bit0]: CLK2 to CLK0
These bits are used to select a count clock for the 16-bit free-run timer. Because the
clock changes immediately after setting the CLK bit, change the bit only when input
capture is stopped.
CLK2
CLK1
CLK0
Count clock
φ=32MHz
φ= 8MHz
φ= 4MHz
φ= 1MHz
0
0
0
φ
31.25 ns
125 ns
0.25 μs
1 μs
0
0
1
φ/2
62.5 ns
0.25 μs
0.5 μs
2 μs
0
1
0
φ/4
0.125 μs
0.5 μs
1 μs
4 μs
0
1
1
φ/8
0.25 μs
1 μs
2 μs
8 μs
1
0
0
φ/16
0.5 μs
2 μs
4 μs
16 μs
1
0
1
φ/32
1 μs
4 μs
8 μs
32 μs
1
1
0
φ/64
2 μs
8 μs
16 μs
64 μs
1
1
1
φ/128
4 μs
16 μs
32 μs
128 μs
φ=Machine clock
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CHAPTER 10 INPUT CAPTURE
10.3 Description of Operations
10.3
MB90930 Series
Description of Operations
This section describes the operations of the input capture.
■ Description of Operations
● 16-Bit Free-run Timer
The 16-bit free-run timer starts counting the counter value from "0000H" when a reset has been
released. This counter value is used as a reference time for the 16-bit input capture.
● 16-bit input capture
The 16-bit input capture can generate an interrupt after fetching a 16-bit free-run timer value
into the capture register upon detection of the specified valid edge.
■ Input Capture Interrupts and EI2OS
Table 10.3-1 shows input capture interrupts and EI2OS
Table 10.3-1 Input Capture Interrupts and EI2OS
Channel
Interrupt No.
Interrupt level setting register
Vector table address
Register Name
Address
Lower
Upper
Bank
EI2OS
Input capture 0
#15 (0FH)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
*
Input capture 1
#19 (13H)
ICR04
0000B4H
FFFFB0H
FFFFB1H
FFFFB2H
*
Input capture 2
#21 (15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
*
Input Capture 3 to 7
#23 (17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
*
Free-run timer Overflow
Free-run timer clear
#31 (1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
×
× : Not available
* : Available when not using interrupt sources sharing ICR02, ICR04, ICR05, ICR06, and the interrupt vector.
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CHAPTER 10 INPUT CAPTURE
10.3 Description of Operations
MB90930 Series
10.3.1
16-bit Input Capture
The 16-bit input capture can generate an interrupt after fetching a 16-bit freerun timer value into the capture register upon detection of the specified valid
edge.
■ Operation of 16-bit Input Capture
Figure 10.3-1 Example of Timing for Fetching Input Captures
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IN0
IN1
IN example
Data register 0
Undefined
3FFFH
Undefined
Data register 1
Data register
example
Capture 0 interrupt
Undefined
BFFFH
BFFFH
7FFFH
Capture 1 interrupt
Capture example interrupt
Capture 0= rising edge
Capture 1= falling edge
Capture example = both edges (example)
Interrupt by another valid edge
Interrupt by software
■ Input Timing for a 16-bit Input Capture
Figure 10.3-2 Capture Timing for an Input Signal
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
value
N+1
Interrupt
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CHAPTER 10 INPUT CAPTURE
10.3 Description of Operations
10.3.2
MB90930 Series
16-bit Free-run Timer
The 16-bit free-run timer starts counting the counter value from "0000H" when a
reset has been released. This counter value is used as a reference time for the
16-bit input capture.
■ Operations of 16-bit Free-run Timer
The counter value is cleared in the following conditions:
• Overflow occurs
• Compare-match with compare clear register value successful (this requires to set a mode)
• Setting the SCLR bit of the TCCSH, TCCSL registers to "1" during operation
• Writing "0000H" to TCDT in timer stop mode
An interrupt may occur if an overflow is generated or if the compare clear register value is
compared and matched with the free-run timer (for a compare match interrupt, a mode setting
is required).
Figure 10.3-3 Clearing the Counter at an Overflow
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Interrupt
Figure 10.3-4 Clearing the Counter by Compare Matching with the Compare Clear Register
Value
Counter value
FFFFH
Matched
BFFFH
Matched
7FFFH
3FFFH
Time
0000H
Reset
Compare
register value
BFFFH
Interrupt
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CHAPTER 10 INPUT CAPTURE
10.3 Description of Operations
MB90930 Series
■ Clear Timing for 16-bit Free-run Timer
The counter is cleared by reset, by software, and by matching with the compare clear register.
Counter clearing by reset is performed as soon as the clear source occurs, while counter
clearing by matching with the compare clear register or by software is performed after
synchronizing with the count timing.
Figure 10.3-5 Clear Timing for the 16-bit Free-run Timer
Compare clear
register value
Compare latch
N
Counter value
N
0000H
■ Count Timing of 16-bit Free-run Timer
The 16-bit free-run timer counts up using the clock (internal or external clock) input. If an
external clock is selected, counting occurs at the rising edge.
Figure 10.3-6 Count Timing of 16-Bit Free-run Timer
External clock input
Count clock
Counter value
CM44-10150-1E
N
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N+1
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10.3 Description of Operations
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CM44-10150-1E
CHAPTER 11
16-BIT RELOAD TIMER
This chapter describes the functions and
operations of the 16-bit reload timer.
11.1 Overview of 16-bit Reload Timer
11.2 Configuration of 16-bit Reload Timer
11.3 Pins of 16-bit Reload Timer
11.4 Registers of 16-bit Reload Timer
11.5 Interrupts of 16-bit Reload Timer
11.6 Operation of 16-bit Reload Timer
11.7 Notes on Using 16-bit Reload Timer
11.8 Sample Program for 16-bit Reload Timer
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CHAPTER 11 16-BIT RELOAD TIMER
11.1 Overview of 16-bit Reload Timer
11.1
MB90930 Series
Overview of 16-bit Reload Timer
The 16-bit reload timer has two modes: Internal clock mode (with countdown
performed in synchronization with three types of internal clock), and event
count mode (with countdown performed by detecting any pulse edge input to
the external pin. Either mode may be selected. This timer defines an underflow
when the counter value is in the range from 0000H to FFFFH. Therefore, an
underflow occurs at a count of [reload register's setting value + 1].
Counter operation can be selected either reload mode in which an underflow
causes the count set value to be reloaded for repeated counting, or one shot
mode in which counting is stopped when an underflow occurs. Counter
underflow may generate an interrupt and supports the extended intelligent I/O
service (EI2OS).
■ Operation Mode of 16-bit Reload Timer
Table 11.1-1 lists the operation modes of the 16-bit reload timer.
Table 11.1-1 Operation Mode of 16-bit Reload Timer
Clock mode
Counter operation
16-bit reload timer operation
Reload mode
Software trigger operation
External trigger operation
External gate input operation
Internal clock mode
One shot mode
Reload mode
Event count mode
(External clock mode)
One shot mode
Software trigger operation
■ Internal Clock Mode
One type of count clock can be selected among three types of internal clock to operate as
follows.
● Software trigger operation
Writing "1" to TRG bit of the timer control status register (TMCSR0 to TMCSR3) starts count
operation. Trigger input by the TRG bit is also enabled for external trigger input and external
gate input.
● External trigger operation
Starts count operation when the selected edge (rising, falling, or both) is input to the TIN0/
TIN1/TIN2/TIN3 pin.
● External gate input operation
Continues counting while the signal level selected ("L" or "H") is being input to the TIN0/
TIN1/TIN2/TIN3 pin.
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CHAPTER 11 16-BIT RELOAD TIMER
11.1 Overview of 16-bit Reload Timer
MB90930 Series
■ Event Count Mode (External Clock Mode)
Event count mode is a function to start countdown at the selected valid edge (rising, falling, or
both) when the edge is input to the TIN0/TIN1/TIN2/TIN3 pin. It is also used as an interval
timer when using an external clock with a constant interval.
■ Count Operation
● Reload mode
If the countdown causes an underflow (0000H −> FFFFH), the setting value for counting is
reloaded and count operation is continued. Since an underflow can generate an interrupt
request, it can be used as an interval timer. Also, a toggled waveform, which reverses itself at
every underflow, is output from the TOT0/TOT1/TOT2/TOT3 pins. Table 11.1-2 lists the
interval time for the 16-bit reload timer.
Table 11.1-2 Interval Time of 16-bit Reload Timer
Count clock
Count clock cycle
21/φ (0.0625 μs)
Internal clock
External clock
Interval time
0.0625 μs to 4.096 ms
3/φ
(0.25 μs)
0.25 μs to 16.384 ms
25/φ
(1.0 μs)
10.0 μs to 65.54 ms
23/φ
or more (0.5 μs)
0.25 μs or more
2
φ: Machine clock () indicates the value for 32MHz machine clock operation.
● One shot mode
If countdown leads to an underflow (0000H −> FFFFH), the count operation will be stopped. An
underflow can generate an interrupt. During counter operation, the square wave that indicates
counting can be output from the TOT0, TOT1, TOT2, and TOT3 pins.
References:
• The 16-bit reload timer can be used for creating the UART baud rate.
• The 16-bit reload timer can be used as an activation trigger for A/D converter.
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CHAPTER 11 16-BIT RELOAD TIMER
11.1 Overview of 16-bit Reload Timer
MB90930 Series
■ Interrupts and EI2OS of 16-bit Reload Timer
Table 11.1-3 lists the interrupts and EI2OS from the 16-bit reload timer.
Table 11.1-3 Interrupts and EI2OS of 16-bit Reload Timer
Channel
Interrupt No.
16-bit reload timer 0
Interrupt control register
Vector table address
Register name
Address
Lower
Upper
Bank
#17 (11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
16-bit reload timer 1
#28 (1CH)
ICR08
0000B8H
FFFF8CH
FFFF8DH
FFFF8EH
16-bit reload timer 2
#18 (12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
16-bit reload timer 3
#22 (16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
EI2OS
: Available when not using interrupt source sharing ICR03, ICR08, ICR05, and interrupt vector.
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CHAPTER 11 16-BIT RELOAD TIMER
11.2 Configuration of 16-bit Reload Timer
MB90930 Series
11.2
Configuration of 16-bit Reload Timer
The 16-bit reload timer consists of the following 7 blocks:
• Count clock generator circuit
• Reload control circuit
• Output control circuit
• Operation control circuit
• 16-bit timer registers (TMR0 to TMR3)
• 16-bit reload registers (TMRLR0 to TMRLR3)
• Timer control status registers (TMCSR0L to TMCSR3L, TMCSR0H to
TMCSR3H)
■ Block Diagram of 16-bit Reload Timer
Figure 11.2-1 shows a block diagram of the 16-bit reload timer.
Figure 11.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRLR0 *1
<TMRLR1 to TMRLR3>
16-bit reload registers
Reload signal
TMR0 *1
<TMR1 to TMR3>
Reload
control
circuit
16-bit timer registers (down counter) UF
Count clock generation circuit
Machine
clock
φ
Prescaler 3
CLK
Gate
input
Valid clock
judgement
circuit
Clear
Input
control
circuit
P12/TIN0 *1
<P07/TIN1>
<P14/TIN2>
<PE1/TIN3>
to UART0, UART1*1
<to A/D converter>
CLK
Internal
clock
Pin
Wait signal
Output control circuit
Clock
selector
External clock
3
2
Output signal
Re- generation circuit
versed
Select
signal
Function select
⎯
⎯
⎯
Reserved
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Timer control status register
Pin
Operation
control circuit
UF CNTE TRG
(TMCSR0) *1
<TMCSR1 to TMCSR3>
*1: Has ch.0 to ch.3. < > indicates ch.1 to ch.3.
*2: Interrupt number
CM44-10150-1E
P11/TOT0*1
<P06/TOT1>
<PD6/TOT2>
<PE0/TOT3>
EN
FUJITSU MICROELECTRONICS LIMITED
Interrupt request signal
#17 (11H)*2
<#28(1CH)/#18(12H)/#22(16H)>
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CHAPTER 11 16-BIT RELOAD TIMER
11.2 Configuration of 16-bit Reload Timer
MB90930 Series
● Count clock generator circuit
The count clock generator circuit generates the count clock for the 16-bit reload timer from the
machine clock or external input clock.
● Reload control circuit
Controls reload operation when the timer starts and when underflow occurs.
● Output control circuit
Controls the reversal of TOT pin output due to 16-bit timer register underflow and the enable/
disable state of TOT pin output.
● Operation control circuit
Controls starting/stopping of the 16-bit reload timer.
● 16-bit timer registers (TMR0 to TMR3)
These are the 16-bit down counter. The current counter value is read from these registers.
● 16-bit reload registers (TMRLR0 to TMRLR3)
These registers are used to set the interval time of the 16-bit reload timer. The set value in these
registers is loaded into the 16-bit timer registers for countdown.
● Timer control status registers (TMCSR0L to TMCSR3L/TMCSR0H to TMCSR3H)
These registers are used to select the count clock and operation mode, set operating conditions,
activate a trigger by software, enable/disable count operation, select reload/one shot mode,
select the pin output level, enable/disable timer output, control interrupts, and check the state of
operation of the 16-bit reload timer.
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11.3
Pins of 16-bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER
11.3 Pins of 16-bit Reload Timer
This section shows the pins of the 16-bit reload timer and their block diagram.
■ Pins of 16-bit Reload Timer
The pins of 16-bit reload timer can also be used for general-purpose ports. Table 11.3-1 shows
the pin functions, I/O type, and settings for using the 16-bit reload timer.
Table 11.3-1 Pins of 16-bit Reload Timer
Pin name
Pin function
P12/TIN0/PPG4
I/O of Port 1/Timer input
P11/TOT0/PPG3/IN4
I/O of Port 1/Timer output
PC7/PPG1/TIN1/IN6
I/O of Port C/Timer input
PC6/PPG0/TOT1/IN7
I/O of Port C/Timer
output
P14/TIN2/IN1
CMOS output/
CMOS hysteresis
input
Pull-up
selection
No
I/O of Port 1/Timer input
PD6/TOT2
I/O of Port D/Timer
output
PE1/TIN3
I/O of Port E/Timer input
PE0/TOT3
I/O of Port E/Timer
output
CM44-10150-1E
I/O type
FUJITSU MICROELECTRONICS LIMITED
Standby
control
Setting
to use pin
Yes
Sets to input port
(DDR1:bit2=0)
PPG4 output disabled
Sets to timer output
enabled
(TMCSR0L:OUTE=1)
PPG3 output disabled
Sets to input port
(DDRC:bit7=0)
PPG1 output disabled
Sets to timer output
enabled
(TMCSR1L:OUTE=1)
PPG0 output disabled
Sets to input port
(DDR1:bit4=0)
Sets to timer output
enabled
(TMCSR2L:OUTE=1)
Sets to input port
(DDRE:bit1=0)
Sets to timer output
enabled
(TMCSR3L:OUTE=1)
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CHAPTER 11 16-BIT RELOAD TIMER
11.3 Pins of 16-bit Reload Timer
MB90930 Series
■ Block Diagram of Pins for 16-bit Reload Timer
Figure 11.3-1 shows a block diagram of the pins for the 16-bit reload timer.
Figure 11.3-1 Block Diagram of Pins for 16-bit Reload Timer
Peripheral function input*
Internal data bus
PDR
(Port data register)
Peripheral function output*
Peripheral function
output enabled*
PDR read
P-ch
Output latch
PDR write
Pin
DDR (Port direction register)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control: stop, watch mode and SPL=1
*: Peripheral function I/O is only applicable to pins with a peripheral function.
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
MB90930 Series
11.4
Registers of 16-bit Reload Timer
This section lists the registers of the 16-bit reload timer.
■ Register List of 16-bit Reload Timer
Figure 11.4-1 lists the registers of the 16-bit reload timer.
Figure 11.4-1 Register List of 16-Bit Reload Timer
Address
bit15
bit8
bit7
16-bit reload
timer 0
000051H,000050H TMCSR0L, TMCSR0H (Timer control status register)
16-bit reload
timer 1
000055H,000054H TMCSR1L, TMCSR1H (Timer control status register)
bit0
000053H,000052H TMR0/TMRLR0 (16-bit timer register/16-bit reload register)*
000057H,000056H TMR1/TMRLR1 (16-bit timer register/16-bit reload register)*
Address
bit15
bit8
bit7
16-bit reload
timer 2
0000D5H,0000D4H TMCSR2L, TMCSR2H (Timer control status register)
16-bit reload
timer 3
0000D7H,0000D6H TMCSR3L, TMCSR3H (Timer control status register)
003951H,003950H
003953H,003952H
bit0
TMR2/TMRLR2 (16-bit timer register/16-bit reload register)*
TMR3/TMRLR3 (16-bit timer register/16-bit reload register)*
*: Functions as a 16-bit timer register (TMR) for reading, and as a 16-bit reload register (TMRLR) for writing.
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
11.4.1
MB90930 Series
Timer Control Status Registers, Upper
(TMCSR0H to TMCSR3H)
Upper bit11 to bit8 and lower bit7 in the timer control status registers (TMCSR0
to TMCSR3) have functions to select the operation mode and set the operating
condition of the 16-bit reload timer. The lower bit7 (MOD0 bit) is described here.
■ Timer Control Status Registers, Upper (TMCSR0H to TMCSR3H)
Figure 11.4-2 Timer Control Status Registers, Upper (TMCSR0H to TMCSR3H)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9
TMCSR0H
000051H
TMCSR1H
000055H
−
−
−
-
-
-
bit8
bit7 bit6
Reserved
CSL1 CSL0 MOD2 MOD1 MOD0
-
R/W R/W R/W R/W R/W
............ bit0
(TMCSR:L)
Initial value
----0000B
TMCSR2H
0000D5H
TMCSR3H
0000D7H
MOD2 MOD1 MOD0
Operation mode selection bits
(in internal clock mode)
Input pin function
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
MOD2 MOD1 MOD0
0
0
X
0
1
X
1
0
X
1
1
CSL1 CSL0
0
0
0
1
1
0
1
1
Reserved
−
Rising edge
Trigger input
Falling edge
Both edges
"L" level
Gate input
"H" level
Operation mode selection bits
(in event count mode)
Input pin function
X
Valid edge/level
Trigger prohibition
Valid edge
−
−
Rising edge
Trigger input
Falling edge
Both edges
Count clock selection bits
Function
Count clock
21/φ (0.0625μs)
Internal clock mode
23/φ (0.25μs)
25/φ (1.0μs)
Event count mode
External event input
Count clock selection bit
Always write "1" to this bit. When reading, "1” is
1
always read from this bit.
R/W : Readable/Writable
: Undefined
−
: Undefined value
X
: Initial value
: Machine clock, () indicates the value for 32-MHz machine clock operation.
φ
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
MB90930 Series
Table 11.4-1 Functions of Upper Bits of Timer Control Status Registers
(TMCSR0H to TMCSR3H)
Bit name
bit15
to Undefined bits
bit13
bit12 Reserved bit
CSL1, CSL0:
bit11,
Count clock selection
bit10
bits
bit9
to
bit7
Function
•
•
Value at reading is not defined.
Writing does not affect operation.
When writing, "1" is always set to this bit. When reading, "1" is always read from this
bit.
• Select the count clock.
• When these bits are values other than "11B", internal clock mode is set to count the
internal clock.
• When these bits are "11B", event count mode is set to count the external clock edge.
Internal clock mode:
• The MOD2 bit is used to select the function of the input pin.
• When the MOD2 bit is "0", the input pin is used as trigger input pin. When a valid
edge is input, the value of the reload register is loaded into the counter to continue
with count operation. The MOD1 and MOD0 bits are used to select the type of the
valid edge.
MOD2, MOD1, MOD0:
• When the MOD2 bit is "1", the input pin is set as a gate input and counts only while a
Operation mode selection
valid level is being input.
bits
• Since the value of the MOD1 bit has no effect, any value ("0" or "1") can be set.
• The MOD0 is used to select the valid level.
Event count mode:
• Since the value of the MOD2 bit has no effect, any value ("0" or "1") can be set.
• The input pin is used as a trigger input pin for event input. The MOD1 and MOD0 bits
are used to select a valid edge.
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
11.4.2
MB90930 Series
Timer Control Status Registers, Lower
(TMCSR0L to TMCSR3L)
Lower 7 bits of the timer control status registers (TMCSR0 to TMCSR3) have
functions to set the operating condition, enable/disable the operation, control
interrupts, and check the status of the 16-bit reload timer.
■ Timer Control Status Registers, Lower (TMCSR0L to TMCSR3L)
Figure 11.4-3 Timer Control Status Registers, Lower (TMCSR0L to TMCSR3L)
Address
TMCSR0L
000050H
TMCSR1L
000054H
bit15
bit8 bit7
(TMCSR:H)
*
bit6
bit5
bit4
bit3
MOD0 OUTE OUTL RELD INTE
bit2
bit1
bit0
UF CNTE TRG
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
TMCSR2L
0000D4H
TMCSR3L
0000D6H
TRG
Software trigger bit
0
No change, and no effect on others
1
Starts counting after reload
Count enable bit
CNTE
0
Stops counting
1
Enables counting (waiting for activation trigger)
UF
Underflow interrupt request flag bit
When writing
When reading
0
No counter underflow
Clears this bit
1
Counter underflow generated
No change, and no effect on others
Interrupt request enable bit
INTE
0
Disables interrupt request output
1
Enables interrupt request output
Reload selection bit
RELD
0
One shot mode
1
Reload mode
Pin output level selection bit
One shot mode
(RELD = 0)
Reload mode
(RELD = 1)
0
Rectangular wave of "H" during counting
Toggle output of "L" when count starts
1
Rectangular wave of "L" during counting
Toggle output of "H" when count starts
OUTL
OUTE
0
Pin function
Timer output enable bit
Register and pin corresponding to each channel
General-purpose ports
TMCSR0
P11
TMCSR1
PC6
R/W : Readable/Writable
TOT0
TOT1
1 Timer output
: Initial value
*
: For details about the MOD0 (Bit7), see Section 11.4.1 "Timer Control Status Registers, Upper (TMCSR0H to TMCSR3H)"
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
MB90930 Series
Table 11.4-2 Functions of Lower Bits of Timer Control Status Registers (TMCSR0L to TMCSR3L)
Bit name
bit6
OUTE:
Timer output enable bit
Function
•
•
•
•
OUTL:
Pin output level selection bit •
•
•
RELD:
bit4
Reload selection bit
•
bit5
bit3
INTE:
Interrupt request enable bit
•
•
•
•
UF:
bit2 Underflow interrupt request •
flag bit
•
•
CNTE:
bit1
•
Count enable bit
•
•
bit0
TRG:
Software trigger bit
CM44-10150-1E
•
•
Enables/disables outputs from the timer output pin.
When this bit is "0", the pin is used as general-purpose port; When this bit is "1", the
pin is set as a timer output pin.
The output waveform from the timer output pin becomes toggle output in reload mode
and square wave output in one shot mode, which indicates that counting is in progress.
A register used to select the output level of the timer output pin.
Toggle this bit to "0" or "1" to reverse the pin level.
Enables reload operation.
Setting this bit "1" selects the reload mode, loads the value of the reload register into
the counter when underflow occurs, and continues the count operation.
Setting this bit to "0" selects the one shot mode, and stops the count operation when
underflow occurs.
Enables/disables output of interrupt requests to the CPU.
When this bit and the interrupt request flag bit (UF) are set to "1", an interrupt request
is output.
This bit is set to "1" when a counter underflow occurs.
Writing "0" clears this bit. Writing "1" has no change and no effect on others.
"1" is always read from this bit when reading by the read-modify-write (RMW)
instruction.
This bit is also cleared when EI2OS occurs.
Enables/disables count operation.
When this bit is set to "1", activation trigger wait state is entered. When activation
trigger occurs, the actual counting starts.
Used to activate the interval timer function or counter function by software.
Writing this bit to "1" activates the software trigger, loads the value of the reload
register into the counter, and starts the count operation. Writing "0" has no effect.
When reading, "0" is always read from this bit.
When CNTE=1, the trigger input by this bit is always valid regardless of the operation
mode.
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
11.4.3
MB90930 Series
16-bit Timer Registers (TMR0 to TMR3)
The 16-bit timer registers (TMR0 to TMR3) can always read the count value of
the 16-bit down counter.
■ 16-bit Timer Registers (TMR0 to TMR3)
Figure 11.4-4 shows the bit configuration of the 16-bit timer registers (TMR0 to TMR3).
Figure 11.4-4 Bit Configuration of 16-bit Timer Registers (TMR0 to TMR3)
TMR0: 000053H
TMR1: 000057H
TMR0: 000052H
TMR1: 000056H
TMR2: 003951H
TMR3: 003953H
TMR2: 003950H
TMR3: 003952H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
R
D14
R
D13
R
D12
R
D11
R
D10
R
D9
R
D8
R
Initial value
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
R
D7
R
D7
R
D7
R
D7
R
D2
R
D1
R
D0
R
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
R
D14
R
D13
R
D12
R
D11
R
D10
R
D9
R
D8
R
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R
D7
R
D7
R
D7
R
D7
R
D2
R
D1
R
D0
R
XXXXXXXXB
Initial value
XXXXXXXXB
R : Read-only
X : Undefined
These registers can read the counter value of the 16-bit down counter. When the counter
operation is enabled (TMCSR0 to TMCSR3:CNTE=1) and the count is started, the value
written to the 16-bit reload register is loaded into these registers and countdown is started. In
counter stop state (TMCSR0 to TMCSR3:CNTE=0), the values of these register are retained.
Notes:
• Although these registers can be rea d during the counter op eration, a word
instruction (e.g. MOVW A, 003AH) must be used.
transfer
• Be sure to use word access.
• The 16-bit timer registers (TMR0 to TMR3) are read-only registers, and assigned the
same address as th e writ e-only 16 -bit re load registers (TMRLR0 to TMRLR3).
Therefore, wr iting doe s no t af fect TMR value, but is performed to TMRLR0 to
TMRLR3.
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CHAPTER 11 16-BIT RELOAD TIMER
11.4 Registers of 16-bit Reload Timer
MB90930 Series
11.4.4
16-bit Reload Registers (TMRLR0 to TMRLR3)
The 16-bit reload registers (TMRLR0 to TMRLR3) are used to set a reload value
to the 16-bit down counter. The value written to these registers are loaded to
the down counter and counted down.
■ 16-bit Reload Registers (TMRLR0 to TMRLR3)
Figure 11.4-5 shows the bit configuration of the 16-bit reload registers (TMRLR0 to TMRLR3).
Figure 11.4-5 Bit Configuration of 16-bit Reload Register (TMRLR0 to TMRLR3)
TMRLR0H: 000053H
TMRLR1H: 000057H
TMRLR0L: 000052H
TMRLR1L: 000056H
TMRLR2H: 003951H
TMRLR3H: 003953H
TMRLR2L: 003950H
TMRLR3L: 003952H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
W
D14
W
D13
W
D12
W
D11
W
D10
W
D9
W
D8
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
W
D7
W
D7
W
D7
W
D7
W
D2
W
D1
W
D0
W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
W
D14
W
D13
W
D12
W
D11
W
D10
W
D9
W
D8
W
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D0
W
XXXXXXXXB
D7
W
D7
W
D7
W
D7
W
D7
W
D2
W
D1
W
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
R : Read only
X : Undefined value
Regardless of the operation mode of the 16-bit reload timer, these registers are set the initial
value of the counter in the state the counter operation is disabled (TMCSR0 to
TMCSR3:CNTE=0). When the counter operation is enabled (TMCSR0 to TMCSR3:CNTE=1)
and the counter is started, the countdown is started from the value written to these registers.
In reload mode, the value set in the 16-bit reload registers (TMRLR0 to TMRLR3) is reloaded
into the counter and the countdown continues when underflow occurs. In one shot mode, the
counter stops at "FFFFH" when underflow occurs.
Notes:
• Writing to th ese r egisters mu st b e pe rformed wit h t he co unter st opped (T MCSR0 to
TMCSR3: CNTE=0). And, a word t ransfer instruction (e. g. MOVW 003AH, A) must be
used to write to these registers.
• Be sure to use word access.
• The 16-bit reload registers (TMRLR0 to TMRLR3) are functionally write-only registers,
and a ssigned the same address as t he r ead-only 1 6-bit t imer r egisters ( TMR0 to
TMR3). Therefore, since the read value is the value of TMR0 to T MR3, instructions to
perform the read-modify-write (RMW) operations, such as INC/DEC, cannot be used.
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CHAPTER 11 16-BIT RELOAD TIMER
11.5 Interrupts of 16-bit Reload Timer
11.5
MB90930 Series
Interrupts of 16-bit Reload Timer
The 16-bit reload timer can generate an interrupt request due to counter
underflow. The timer also supports the extended intelligent I/O service (EI2OS).
■ Interrupts of 16-bit Reload Timer
Table 11.5-1 lists the interrupt control bits and interrupt sources of the 16-bit reload timer.
Table 11.5-1 Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer
16-bit Reload Timer
Interrupt request flag bit
TMCSR0 to TMCSR3:UF
Interrupt request enable bit
TMCSR0 to TMCSR3:INTE
Interrupt source
Underflow of 16-bit down counter (TMR0 to TMR3)
In the 16-bit reload timer, when the underflow of the down counter (0000H −> FFFFH) occurs,
UF bit in the timer control status registers (TMCSR0L to TMCSR3L,TMCSR0H to TMCSR3H)
is set to "1". When interrupt requests are enabled (TMCSR0 to TMCSR3:INTE=1), the interrupt
request is output to the interrupt controller.
■ Interrupts and EI2OS of 16-bit Reload Timer
Table 11.5-2 lists the interrupts and EI2OS of the 16-bit reload timer.
Table 11.5-2 Interrupts and EI2OS of 16-bit Reload Timer
Channel
Interrupt No.
16-bit reload timer 0
Interrupt control register
Vector table address
Register name
Address
Lower
Upper
Bank
#17 (11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
16-bit reload timer 1
#28 (1CH)
ICR08
0000B8H
FFFF8CH
FFFF8DH
FFFF8EH
16-bit reload timer 2
#18 (12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
16-bit reload timer 3
#22 (16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
EI2OS
: Available when not using interrupt sources sharing ICR03, ICR05, ICR08 or the interrupt vector.
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer has a circuit supporting EI2OS. Therefore, a counter underflow can
start EI2OS. However, EI2OS is available only when no other peripheral function that shares
the interrupt control register (ICR) does not use the interrupt. To use the EI2OS on the 16-bit
reload timer 0, DTP/external interrupt 1 must be disabled. To use EI2OS on the 16-bit reload
timer 1, PPG timer 1 interrupt must be disabled.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
11.6
Operation of 16-bit Reload Timer
This section describes the 16-bit reload timer settings and counter operation
states.
■ 16-bit Reload Timer Settings
● Settings of internal clock mode
To operate as an interval timer, the settings shown in Figure 11.6-1 are required.
Figure 11.6-1 Settings of Internal Clock Mode
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMCSR
- CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
Other than "11B"
TMRLR
Setting of the initial counter value (reload value)
: Bit used
1 : Set to "1"
● Settings of event count mode
To operate as an event counter, the settings shown in Figure 11.6-2 are required.
Figure 11.6-2 Settings of Event Count Mode
TMCSR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
- CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
1
1
TMRLR
Setting of the initial counter value (reload value)
DDRE
DDRC
DDR1
: Bit used
1 : Set to "1"
: Set the bit corresponding to the pin used to "0".
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
■ Counter Operation States
The state of the counter is determined by the CNTE bit of the timer control status register
(TMCSR0L to TMCSR3L, TMCSR0H to TMCSR3H) and the internal WAIT signal. States
that can be set include the stop state (STOP state), activation trigger wait state (WAIT state),
and operation state (RUN state). Figure 11.6-3 shows a counter state transition diagram.
Figure 11.6-3 Counter State Transition Diagram
STOP state CNTE=0, WAIT=1
TIN pin: Input disabled
TOT pin : General-purpose port
Reset
Counter: Retains the value at stop.
Not
specified immediately after reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
CNTE=1, WAIT=1
WAIT state
TIN pin: Valid for trigger input only
TOT pin : Initial value output
Counter: Retains the value at stop. Not specified
until loading immediately after reset
TRG=1
(Software trigger)
External trigger from TIN
CNTE=1
TRG=1
UF=1 &
RELD=0
(One shot mode)
LOAD
RUN state
CNTE=1, WAIT=0
TIN pin: Functions as TIN pin
TOT pin : Functions as TOT pin
Counter: Operating
UF=1 &
RELD=1
(Reload mode)
TRG=1
(Software trigger)
CNTE=1, WAIT=0
Loads reload register's value into the counter.
Load end
: State transition by hardware
WAIT
TRG
CNTE
UF
RELD
322
: State transition by register access
: WAIT signal (internal signal)
: Software trigger bit of timer control status register (TMCSR)
: Count enable bit of timer control status register (TMCSR)
: Underflow interrupt request flag bit of timer control status register (TMCSR)
: Reload selection bit of timer control status register (TMCSR)
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
11.6.1
Internal Clock Mode (Reload Mode)
The counter operates in sync with the internal count clock to count down the
16-bit counter and generates the interrupt request to CPU with the counter
underflow. The counter also can output a toggle waveform from the timer
output pin.
■ Operation in Internal Clock Mode (Reload Mode)
When the count operation is enabled (TMCSR0 to TMCSR3:CNTE=1) and the timer is
activated by the software trigger bit (TMCSR:TRG) or the external trigger, the value of the 16bit reload registers (TMRLR0 to TMRLR3) is loaded into the counter and the count operation
is started. When both the count enable bit and the software trigger bit are set to "1", the count is
enabled and starts.
If the counter value causes underflow (0000H −> FFFFH), the value of the 16-bit reload register
(TMRLR0 to TMRLR3) is loaded to the counter, and the count operation is continued. At this
moment, the underflow interrupt request flag bit (UF) is set to "1", and the interrupt request
occurs if the interrupt request enable bit (INTE) is set to "1".
And, the TOT pin outputs a toggle waveform that is reversed at every underflow.
● Software trigger operation
Writing "1" to the TRG bit of the timer control status registers (TMCSR0L to TMCSR3L,
TMCSR0H to TMCSR3H) starts the counter.
Figure 11.6-4 shows the software trigger operation in reload mode.
Figure 11.6-4 Software Trigger Operation in Reload Mode
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T
*
TOT pin
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
● External trigger operation
When the valid edge (rising, falling, or both can be selectable) is input to the TIN pin, the
counter is activated. Figure 11.6-5 shows the external trigger operation in reload mode.
Figure 11.6-5 External Trigger Operation in Reload Mode
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN pin
TOT pin
*
2T to 2.5T
T: Machine cycle
*: It takes 2T to 2.5T from external trigger input to loading reload data.
Note:
The p ulse widt h o f t he t rigger inp ut to t he T IN pin s (TI N0 t o TI N3) must conf orm t o t he
rating in the data sheet.
● Gate input operation
While the valid level ("H" level or "L" level can be selected) is being input to the TIN pin, the
count operation is performed. Figure 11.6-6 shows the gate input operation in reload mode.
Figure 11.6-6 Gate Input Operation in Reload Mode
Count clock
Counter
Reload data
-1
-1
-1
0000H
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
TIN pin
T
*
TOT pin
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
Note:
The pu lse width of the ga te input to th e T IN p ins (TIN0 to T IN3) m ust co nform to th e
rating in the data sheet.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
11.6.2
Internal Clock Mode (One Shot Mode)
The counter operates in sync with the internal count clock to count down the
16-bit counter and generates the interrupt request to CPU with the counter
underflow. The counter also output a square wave from TOT0 to TOT3 pins,
which indicates that counting is in progress.
■ Operation of Internal Clock Mode (One Shot Mode)
When the count operation is enabled (TMCSR0 to TMCSR3:CNTE=1) and the timer is
activated by the software trigger bit (TMCSR0 to TMCSR3:TRG) or the external trigger, the
count operation is started. When both the count enable bit and the software trigger bit are set to
"1", the count is enabled and starts. If the counter value causes underflow (0000H −> FFFFH),
the counter stops at FFFFH. At this moment, the underflow interrupt request flag bit (UF) is set
to "1", and the interrupt request occurs if the interrupt request enable bit (INTE) is set to "1".
The counter can also output a square wave from TOT pin, which indicates that counting is in
progress.
● Software trigger operation
Writing "1" to the TRG bit of the timer control status registers (TMCSR0L to TMCSR3L,
TMCSR0H to TMCSR3H) starts the counter. Figure 11.6-7 shows the software trigger
operation in on shot mode.
Figure 11.6-7 Software Trigger Operation in One Shot Mode
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T
*
TOT pin
Waiting for activation trigger
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
● External trigger operation
When the valid edge (rising, falling, or both can be selectable) is input to the TIN0 to TIN3 pins, the
counter is activated. Figure 11.6-8 shows the external trigger operation in one shot mode.
Figure 11.6-8 External Trigger Operation in One Shot Mode
Count clock
Reload
data
Counter
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN pin
*
2T to 2.5T
TOT pin
Waiting for activation trigger
T: Machine cycle
*: It takes 2T to 2.5T from external trigger input to loading reload data.
Note:
The p ulse widt h o f t he t rigger inp ut to t he T IN pin s (TI N0 t o TI N3) must conf orm t o t he
rating in the data sheet.
● Gate input operation
While the valid level ("H" level or "L" level can be selected) is being input to the TIN0 to TIN3
pins, the count operation is performed. Figure 11.6-9 shows the gate input operation in one shot
mode.
Figure 11.6-9 Gate Input Operation in One Shot Mode
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T
*
TOT pin
Waiting for activation trigger
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
Note:
The pu lse width of the ga te input to th e T IN p ins (TIN0 to T IN3) m ust co nform to th e
rating in the data sheet.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
11.6.3
Event Count Mode
The counter counts input edges from the TIN pin to count down the 16-bit
counter and generates the interrupt request to CPU with the counter underflow.
The TOT0 to TOT3 pins can also output either a toggle waveform or square
wave.
■ Event Count Mode
When the count operation is enabled (TMCSR0 to TMCSR3:CNTE=1) and the counter is activated
(TMCSR0 to TMCSR3:TRG=1), the value of the 16-bit reload register (TMRLR0 to TMRLR3)
is loaded into the counter and counted down whenever the valid edge (rising, falling, or both
can be selected) of pulses (external count clock) input to the TIN0 to TIN3 pins is detected.
When both the count enable bit and the software trigger bit are set to "1", the count is enabled
and starts.
● Operation in reload mode
If the counter value causes underflow (0000H −> FFFFH), the value of the 16-bit reload register
(TMRLR0 to TMRLR3) is loaded to the counter, and the count operation is continued. At this
moment, the underflow interrupt request flag bit (UF) is set to "1", and the interrupt request
occurs if the interrupt request enable bit (TMCSR0 to TMCSR3:INTE) is set to "1". And, the
TOT0 to TOT3 pins output a toggle waveform that is reversed at every underflow. Figure 11.610 shows the count operation in reload mode.
Figure 11.6-10 Count Operation in Reload Mode
TIN pin
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T
*
TOT pin
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
Note:
The "H" and "L" widths of the clock input to the TIN pins (TIN0 to TIN3) must conform to
the rating in the data sheet.
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CHAPTER 11 16-BIT RELOAD TIMER
11.6 Operation of 16-bit Reload Timer
MB90930 Series
● Operation in one shot mode
If the counter value causes underflow (0000H −> FFFFH), the counter stops at FFFFH. At this
moment, the underflow request flag bit (UF) is set to "1", and the interrupt request occurs if the
interrupt request output enable bit (INTE) is set to "1". The counter can also output a square
wave from TOT0 to TOT3 pins, which indicates that counting is in progress. Figure 11.6-11
shows the count operation in one shot mode.
Figure 11.6-11 Count Operation in One Shot Mode
TIN pin
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
*
T
TOT pin
Waiting for activation trigger
T: Machine cycle
*: It takes 1T from trigger input to loading reload data.
Note:
The "H" and "L" widths of the clock input to the TIN pins (TIN0 to TIN3) must conform to
the rating in the data sheet.
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CHAPTER 11 16-BIT RELOAD TIMER
11.7 Notes on Using 16-bit Reload Timer
MB90930 Series
11.7
Notes on Using 16-bit Reload Timer
This section provides notes on using the 16-bit reload timer.
■ Notes on Using 16-bit Reload Timer
● Notes on setup by program
Writing to the 16-bit reload registers (TMRLR0 to TMRLR3) must be performed with the
counter stopped (TMCSR0 to TMCSR3:CNTE=0). Although the 16-bit timer registers (TMR0
to TMR3) can be read during the counter operation, a word transfer instruction (e.g. MOVW
A, dir) must be used.
Changing the CSL1 and CSL0 bits of the timer control status registers (TMCSR0L to
TMCSR3L, TMCSR0H to TMCSR3H) must be performed with the counter stopped (TMCSR0
to TMCSR3:CNTE=0).
● Notes on interrupts
If the UF bit of the timer control status registers (TMCSR0L to TMCSR3L, TMCSR0H to
TMCSR3H) is set to "1" and the interrupt request is enabled (TMCSR:INTE=1), return from
interrupt processing cannot be performed. Be sure to clear the UF bit.
Interrupt control register is shared between the 16-bit reload timers 0 and 2, the 16-bit reload
timer 1 and the PPG timer 1, and the 16-bit reload timer 3 and the input capture 2. When the
16-bit reload timer uses EI2OS, interrupts by the resource sharing the interrupt control register
must be disabled.
● Notes in standby mode
When an evaluation product transfers to the standby mode or returns from it, the external
interrupt request flag bit in external interrupt source register is set (EIRR:ER) no matter
whether the external interrupt is set enable or disable (ENIR:EN=1/0).
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CHAPTER 11 16-BIT RELOAD TIMER
11.8 Sample Program for 16-bit Reload Timer
11.8
MB90930 Series
Sample Program for 16-bit Reload Timer
This section provides sample programs for internal clock mode and event
count mode of the 16-bit reload timer.
■ Sample Program for Internal Clock Mode
● Processing specifications
Use the 16-bit reload timer to generate a 12.5ms interval timer interrupt.
Use reload mode to generate interrupts repeatedly.
Use no external trigger, but use a software trigger to start the timer.
Does not use EI2OS.
Use 32-MHz machine clock and 1 μs count clock.
[Coding example]
ICR03 EQU 0000B3H
;Interrupt control register 03
TMCSR EQU 000050H
;Timer control status register
TMR
EQU 000052H
;16-bit timer register
TMRLR EQU 000052H
;16-bit reload register
UF
EQU TMCSR:2
;Interrupt request flag bit
CNTE EQU TMCSR:1
;Counter operation enable bit
TRG
EQU TMCSR:0
;Software trigger bit
;----------Main program---------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) already initialized
AND CCR, #0BFH
;Interrupt disabled
MOV I:ICR03, #00H
;Interrupt level 0 (highest)
CLRB I:CNTE
;Counter paused
MOVW I:TMRLR, #30D3H ;Sets the data for the 12.5ms timer
MOVW I:TMCSR, #0001000000011011B
;Interval timer operation, clock 2 μs
;Disables external trigger, disables
;external output
;Selects reload mode, enables interrupt
;Clears the interrupt flag, and starts
;counter
MOV ILM, #07H
;Sets ILM in PS to level 7.
OR
CCR, #40H
;Interrupt enabled
LOOP: MOV A, #00H
;Infinite loop
MOV A, #01H
;
BRA LOOP
;
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CHAPTER 11 16-BIT RELOAD TIMER
11.8 Sample Program for 16-bit Reload Timer
MB90930 Series
;----------Interrupt program----------------------------------WARI:
CLRB I:UF
;Clears the interrupt request flag
;
:
;
User processing;
:
RETI
; Return from interrupt.
CODE ENDS
;----------Vector setting-------------------------------------VECT CSEG ABS=0FFH
ORG 0FFB8H
;Set the vector to interrupt #17(11H)
DSL
ORG
VECT
WARI
0FFDCH
DSL START
DB
00H
ENDS
END START
;Reset vector setting
;Set to single-chip mode.
■ Sample Program for Event Count Mode
● Processing specifications
When the rising edge in the pulses input to the external event input pin is counted the 10,000th
time by the 16-bit reload timer/counter, an interrupt occurs.
The device operates in one shot mode.
The rising edge is selected for external trigger input.
Does not use EI2OS.
[Coding example]
ICR03 EQU
;Interrupt control register for 16-bit
;reload timer
TMCSR EQU 000050H
;Timer control status register
TMR
EQU 000052H
;16-bit timer register
TMRLR EQU 000052H
;16-bit reload register
DDR1 EQU 000011H
;Port data register
UF
EQU TMCSR:2
;Interrupt request flag bit
CNTE EQU TMCSR:1
;Counter operation enable bit
TRG
EQU TMCSR:0
;Software trigger bit
;----------Main program --------------------------------------CSEG
START:
;
:
;Stack pointer (SP) already initialized
AND CCR, #0BFH
;Interrupt disabled
MOV I:ICR03, #00H
;Interrupt level 0 (highest)
MOV I:DDR1, #00H
;Sets P12/TIN0 pin to input
CLRB I:CNTE
;Counter paused
MOVW I:TMRLR, #2710H ;Sets reload value to 10000
MOVW I:TMCSR, #0000110010001011B
;Counter operation, external trigger, rising
CM44-10150-1E
0000B3H
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CHAPTER 11 16-BIT RELOAD TIMER
11.8 Sample Program for 16-bit Reload Timer
MB90930 Series
;edge, external output disabled
;Selects one shot mode, enables interrupt
;Clears the interrupt flag, and starts
;counter
MOV ILM, #07H
;Set ILM in PS to level 7
OR
CCR, #40H
;Interrupt enabled
LOOP: MOV A, #00H
;Infinite loop
MOV A, #01H
;
BRA LOOP
;
;----------Interrupt program----------------------------------WARI:
CLRB I:UF
;Clears the interrupt request flag
;
:
;
User processing
;
:
RETI
; Return from interrupt
CODE ENDS
;----------Vector setting-------------------------------------VECT CSEG ABS=0FFH
ORG 0FF84H
;Set the vector to interrupt #30(1EH)
DSL
ORG
DSL
DB
VECT
END
332
WARI
0FFDCH
START
00H
ENDS
START
; Reset vector setting
; Set to single-chip mode
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 12
PPG TIMER
This chapter describes the operations of PPG
timer.
12.1 Overview of PPG Timer
12.2 Block Diagram of PPG Timer
12.3 Registers of PPG Timer
12.4 Interrupt of PPG Timer
12.5 PPG Timer Operation
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CHAPTER 12 PPG TIMER
12.1 Overview of PPG Timer
12.1
MB90930 Series
Overview of PPG Timer
The PPG timer consists of the prescaler, 16-bit down counter (x1), 16-bit data
register with a buffer for setting cycle, 16-bit compare register with a buffer
for setting a duty, and a pin control section.
The PPG timer can output pulses synchronized to the external or software
trigger. The cycle and duty of the output pulse can be changed freely by
updating two 16-bit register values.
■ Overview of PPG Timer
● PWM function
The PPG timer can output pulses programmably by updating the values of the registers above
in synchronization to the trigger.
It can also be used as a D/A converter by an external circuit.
● One shot function
This function can detect an edge of the trigger input, and output a single pulse.
● Pin control
• Set to "1" after duty is matched (priority).
• Reset to "0" by counter borrow.
• Has output value fixed mode to simply output all "L" (or all "H").
• Polarity can be specified.
● 16-bit down counter
The counter operation clock can be selected among 10 types. 10 types of internal clock
(φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, φ/512)
φ: Machine Clock
● Interrupt request
• Timer activation
• Counter borrow (cycle match)
• Duty match
• Counter borrow (cycle match) or duty match
• Multiple channels can be set to activate simultaneously and restart during operation by an
external trigger.
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CHAPTER 12 PPG TIMER
12.2 Block Diagram of PPG Timer
MB90930 Series
12.2
Block Diagram of PPG Timer
This section shows a block diagram of PPG timer.
■ Block Diagram
Figure 12.2-1 Block Diagram
PCNTH0 to PCNTH5 CNTE STGR MDSE RTRG CKS1
CKS0 PGMS FSEL
Initial value: 1
PCSR
PDUT
Prescaler
1/1
1/4
1/16
1/64
Machine
clock
CK
Load
CMP
PCNT
16-bit down counter
1 bit
down
counter
1
0
Borrow
Selector
Start
S
Q
PPG output
R
OSEL
Trigger input
PC5/SCK1/TRG
Interrupt
selection
PGMS
Enable
Edge detect
Interrupt
IRQ #25, #27, #29
Software trigger
Figure 12.2-2 Block Diagram of PPG Ch.0 Output
PCNTL0
EGS1 EGS0 IREN
PPG ch.0
Output
Divided by 2
IRQF
Divided by 2
IRS1
IRS0 POEN OSEL
PC6/PPG0
Divided by 2
10
01
00
PPGDIV
CM44-10150-1E
DIV1
Selector
11
DIV0
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CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
12.3
MB90930 Series
Registers of PPG Timer
This section describes the registers of the PPG timer.
■ Registers of PPG Timer
Registers of PPG timer are described in detail next.
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12.3.1
List of PPG Timer Registers
CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
This section describes the list of the PPG timer registers.
■ List of PPG Timer Registers
PPG Control Status Register (upper) (PCNTH0 to PCNTH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
00002BH
00002DH
00002FH
0000DBH
0000DDH
0000DFH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
CNTE STGR MDSE RTRG CKS1 CKS0 PGMS FSEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
← Initial value
PPG Control Status Register (lower) (PCNTL0 to PCNTL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
00002AH
00002CH
00002EH
0000DAH
0000DCH
0000DEH
R/W :
bit7
bit6
bit5
bit4
bit3
EGS1 EGS0 IREN IREQF IRS1
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
bit2
bit1
bit0
IRS0 POEN OSEL
R/W
R/W
R/W
0
0
0
← Initial value
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
← Initial value
Readable/Writable
PPG Down Counter Register (upper) (PDCRH0 to PDCRH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
003921H
003929H
003931H
0039E1H
0039E9H
0039F1H
PPG Down Counter Register (lower) (PDCRL0 to PDCRL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
R:
003920H
003928H
003930H
0039E0H
0039E8H
0000F0H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
← Initial value
Read only
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CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
MB90930 Series
PPG Cycle Setting Register (upper) (PCSRH0 to PCSRH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
003923H
00392BH
003933H
0039E3H
0039EBH
0039F3H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
W
W
W
W
W
W
W
W
1
1
1
1
1
1
1
1
← Initial value
PPG Cycle Setting Register (lower) (PCSRL0 to PCSRL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
W:
003922H
00392AH
003932H
0039E2H
0039EAH
0000F2H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
W
W
W
W
W
W
W
1
1
1
1
1
1
1
1
← Initial value
Write only
PPG Duty Setting Register (upper) (PDURH0 to PDURH5)
Address:
bit15
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
003925H
003920H
003935H
0039E5H
0039E0H
0039F5H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
← Initial value
PPG Duty Setting Register (lower) (PDURL0 to PDURL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
W:
003924H
00392CH
003934H
0039E4H
0039ECH
0000F4H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
← Initial value
Write only
PPG0 Output Division Setting Register (PPGDIV0 to PPGDIV5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
R:
R/W :
338
003926H
00392EH
003936H
0039E6H
0039EEH
0000F6H
bit7
R
1
bit6
R
1
bit5
R
1
bit4
R
1
bit3
R
1
bit2
R
1
bit1
DIV1
R/W
0
bit0
DIV0
R/W
0
← Initial value
Read only
Readable/Writable
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
MB90930 Series
12.3.2
Detailed Description of PPG Timer
CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
The PPG timer has the following 5 registers.
• PPG control status register (PCNT0 to PCNT5)
• PPG down counter register (PDCR0 to PDCR5)
• PPG cycle setting register (PCSR0 to PCSR5)
• PPG duty setting register (PDUT0 to PDUT5)
• PPG output division setting register (PPGDIV0 to PPGDIV5)
■ PPG Control Status Register (PCNT)
Upper bits of PPG control status register (PCNTH0 to PCNTH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
00002BH
00002DH
00002FH
0000DBH
0000DDH
0000DFH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
CNTE STGR MDSE RTRG CKS1 CKS0 PGMS FSEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
← Initial value
Lower bits of PPG control status register (PCNTL0 to PCNTL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
R/W :
00002AH
00002CH
00002EH
0000DAH
0000DCH
0000DEH
bit7
bit6
bit5
EGS1 EGS0 IREN
R/W
R/W
R/W
0
0
0
bit4
IRQF
R/W
0
bit3
IRS1
R/W
0
bit2
bit1
bit0
IRS0 POEN OSEL
R/W
R/W
R/W
0
0
0
← Initial value
Readable/Writable
[bit15] CNTE: Timer enable bit
This bit enables the operation of the 16-bit down counter.
0
Stop (initial value)
1
Enabled
[bit14] STGR: Software trigger bit
Writing "1" to the STGR bit issues a software trigger.
The read value of the STGR bit is always "0".
[bit13] MDSE: Mode selection bit
This bit selects either the PWM operation to output pulses continuously or the one shot operation
to output a single pulse. This bit cannot be rewritten during operation.
CM44-10150-1E
0
PWM operation (initial value)
1
One shot operation
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CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
MB90930 Series
[bit12] RTRG: Restart enable bit
This bit enables to restart based on a trigger (software/external). This bit cannot be
rewritten during operation.
0
Restart disabled (initial value)
1
Restart enable
[bit11, bit10] CKS1,CKS0: Count clock selection bits
These bits are used to select a counter clock for the 16-bit count down. These bits cannot
be rewritten during operation.
CKS1
CKS0
Cycle
0
0
φ (initial value)
0
1
φ/4
1
0
φ/16
1
1
φ/64
φ: Machine clock
[bit9] PGMS: PPG output mask selection bit
By writing "1" into PGMS bit, PPG output can be masked to either "0" or "1",
regardless of mode setting, cycle setting value, and duty setting value.
0
No output mask (initial value)
1
Output mask
PPG output when writing "1" to PGMS
Polarity
PPG output
Normal polarity
"L"
Reverse polarity
"H"
To output all "H" at normal polarity or all "L" at reverse polarity, write the same value
into the cycle setting register and duty setting register. This enables the reverse of the
above mask values to be output.
[bit8] FSEL: Count clock division control bit
0
Divided by 2
1
Divided by 1 (initial value)
FSEL bit sets the division ratio of the count clock.
If "0" is written to FSEL, the cycle set by the counter clock selection bits (CKS1 and
CKS0) is further divided by 2.
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12.3 Registers of PPG Timer
MB90930 Series
[bit7, bit6] EGS1,EGS0: Trigger input edge selection bits
These bits select a valid edge polarity of the external trigger. Writing "1" to the software
trigger bit enables the software triggers in any mode selected.
EGS1
EGS0
Edge selection
0
0
Invalid (initial value)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
[bit5] IREN: Interrupt request enable bit
This bit enables to interrupt the PPG timer. When the IREN bit is "1", setting the
interrupt flag (bit4:IRQF) to "1" generates an interrupt.
0
Interrupt disabled (initial value)
1
Interrupt enabled
[bit4] IRQF: Interrupt request flag
When the interrupt source selected by the interrupt source selection bit ((bit3,
bit2:IRS1, IRS0) occurs, IRQF is set to "1". If the interrupt request enable bit
(bit5:IREN) is enabled the interrupt request is issued to the CPU.
The IRQF bit is readable and writable. It can be cleared by writing "0"; writing "1" will
not change the bit value. The read value is "1" regardless of the bit value when using a
read-modify-write (RMW) instruction.
If setting "1" and writing "0" occur simultaneously, writing "0" is preferred.
0
No interrupt request (initial value)
1
Interrupt requested
[bit3, bit2] IRS1,IRS0: Interrupt source selection bits
These bits select the source to set the bit4:IRQF. These bits cannot be rewritten during
operation.
IRS1
IRS0
0
0
Software trigger or valid trigger input (initial value)
0
1
Counter borrow (cycle match)
1
0
Normal polarity PPG↑, or reverse polarity PPG↓ (duty match)
1
1
Counter borrow or normal polarity PPG↑, or reverse polarity PPG↓
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Edge selection
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12.3 Registers of PPG Timer
MB90930 Series
[bit1] POEN: PPG output enable bit
Setting this bit to "1" enables PPG to output from the pin.
0
General-purpose port (initial value)
1
PPG output pin
[bit0] OSEL: PPG output polarity specification bit
This bit sets the polarity of the PPG output.
0
Normal polarity (initial value)
1
Reverse polarity
The following operation can be performed in combination with the bit9: PGMS.
PGMS
OSEL
PPG output
0
0
Normal polarity (initial value)
0
1
Reverse polarity
1
0
Output fixed to "L"
1
1
Output fixed to "H"
Polarity
Stop state
Normal polarity
"L" output
Reverse polarity
"H" output
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Duty matched
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Counter matched
CM44-10150-1E
CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
MB90930 Series
■ PPG Down Counter Register (PDCR)
PDCR register can read the value of the 16-bit down counter.
Access the PDCR register in words.
PPG down counter register (upper) (PDCRH0 to PDCRH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
003921H
003929H
003931H
0039E1H
0039E9H
0039F1H
← Initial value
PPG down counter register (lower) (PDCRL0 to PDCRL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
003920H
003928H
003930H
0039E0H
0039E8H
0000F0H
← Initial value
Read only
■ PPG Cycle Setting Register (PCSR)
The PCSR register sets the cycle with a buffer. Transfer from the buffer is executed by a
counter borrow or activation.
Write to the cycle setting register, then to the duty setting register at the time of initializing the
cycle setting register or for changing the setting.
Access the PCSR register in words. Only writing is available, and reading results in an
undefined value.
PPG cycle setting register (upper) (PCSRH0 to PCSRH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
003923H
00392BH
003933H
0039E3H
0039EBH
0039F3H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
W
W
W
W
W
W
W
W
1
1
1
1
1
1
1
1
← Initial value
PPG cycle setting register (lower) (PCSRL0 to PCSRL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
W:
003922H
00392AH
003932H
0039E2H
0039EAH
0000F2H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
W
W
W
W
W
W
W
1
1
1
1
1
1
1
1
← Initial value
Write only
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CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
MB90930 Series
■ PPG Duty Set Register (PDUT)
The PDUT register sets the duty with a buffer. The transfer from the buffer is executed by a
counter borrow or activation.
If both values are the same in the cycle setting register and the duty setting register, all "H" for
normal polarity or all "L" for reverse polarity is output.
Do not set the value which causes PCSR<PDUT. PPG output will be undefined.
Access the PDUT register in words. Only writing is available, and reading results in an
undefined value.
PPG duty setting register (upper) (PDURH0 to PDURH5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
003925H
003920H
003935H
0039E5H
0039E0H
0039F5H
← Initial value
PPG duty setting register (lower) (PDURL0 to PDURL5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
W:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
003924H
00392CH
003934H
0039E4H
0039ECH
0000F4H
← Initial value
Write only
■ PPG0 Output Division Set Register (PPGDIV)
PPG0 Output Division Setting Register (PPGDIV0 to PPGDIV5)
Address:
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
R:
bit7
R
1
003926H
00392EH
003936H
0039E6H
0039EEH
0000F6H
bit6
R
1
bit5
R
1
bit4
R
1
bit3
R
1
bit2
R
1
bit1
DIV1
R/W
0
bit0
DIV0
R/W
0
← Initial value
Read only
[bit7 to bit2] Undefined bits
These are undefined bits.
Writing has no effect on operation.
Read value is always "1".
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CHAPTER 12 PPG TIMER
12.3 Registers of PPG Timer
MB90930 Series
[bit1, bit0] DIV1, DIV0: Division setting bits
These bits set the division ratio of PPG ch.0.
DIV1
DIV0
Division ratio
0
0
1/1 (initial value)
0
1
1/2
1
0
1/4
1
1
1/8
Note:
There are following limitations when the 1/2, 1/4, and 1/8 division setting is used.
• The output waveform is fixed to 50% of the duty.
• The one shot operation (PCNT:MDSE=1) is prohibited.
• The PPG output reverse function (PCNT:OSEL=1) is prohibited.
• The state of the PPG output fixed (PCNT:PGMS, OSEL=01B, 10B, 11B) is prohibited.
• When PCSR=PDUT, the setting is prohibited.
Figure 12.3-1 Rising Timing of PPG Division
PPG
CNTE
Activation trigger
PPG 1/2 division
Depended on the rising timing of PPG.
The PPG division is depended on the rising timing of PPG.
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CHAPTER 12 PPG TIMER
12.4 Interrupt of PPG Timer
12.4
MB90930 Series
Interrupt of PPG Timer
The PPG timer can generate an interrupt request by timer activation, counter
borrow (cycle match), and duty match. The timer also supports the extended
intelligent I/O service (EI2OS).
■ Interrupt of PPG Timer
Table 12.4-1 shows the interrupt control bits and interrupt source of the PPG timer.
Table 12.4-1 Interrupt Control Bits and Interrupt Source of PPG Timer
Lower bits of PPG control status register (PCNTL5 to PCNTL0)
Interrupt source
Interrupt flag bit
Interrupt
enabled bit
IRQF
IREN
• Timer activation
• Counter borrow (cycle match)
• Duty match
Clear interrupt flag
• Write "0" to IRQF bit
• Clear by EI2OS
• Reset
The interrupt flag bit of the PPG timer is set to "1" by the interrupt source listed in Table 12.41. If the interrupt enable bit is set to "1" at this time, an interrupt request is output to an
interrupt controller.
■ Interrupt of PPG Timer and EI2OS
Table 12.4-2 shows the interrupt of PPG and EI2OS.
Table 12.4-2 Interrupt of PPG Timer and EI2OS
Channel
Interrupt
No.
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
PPG timer 0
#25(19H)
ICR07
0000B7H
FFFF98H
FFFF99H
FFFF9AH
PPG timer 1
#27(1BH)
ICR08
0000B8H
FFFF90H
FFFF91H
FFFF92H
#29(1DH)
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8AH
PPG timer 2
PPG timer 3
PPG timer 4
PPG timer 5
: Available when ICR07, ICR08, ICR09, or interrupt sources sharing an interrupt vector are not used
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CHAPTER 12 PPG TIMER
12.4 Interrupt of PPG Timer
MB90930 Series
■ EI2OS Functions of PPG Timer
The PPG timer has a circuit supporting EI2OS. Thus, the PPG timer can activate EI2OS by
timer activation, counter borrow (cycle match), and duty match. However, EI2OS for ICR07,
ICR08, ICR09 is available only when no other peripheral function that shares the interrupt
control register (ICR) or the interrupt vector is used. For example, when the EI2OS is activated
with the PPG timer 0, external interrupts of the channel 6/7 and the interrupt of UART3
transmission must be prohibited.
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CHAPTER 12 PPG TIMER
12.5 PPG Timer Operation
12.5
MB90930 Series
PPG Timer Operation
This section describes the PPG Timer Operation.
■ PPG Timer Operation
PWM operation, one shot operation, interrupt source and timing are described next.
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CHAPTER 12 PPG TIMER
12.5 PPG Timer Operation
MB90930 Series
12.5.1
PWM Operation
In PWM operation, pulses can be output continuously after an activation trigger
was detected. The cycle of the output pulse can be controlled by changing the
PCSR value, the duty ratio can be controlled by changing the PDUT value.
■ When Disabling Restart
Figure 12.5-1 Timing of PWM Operation When Restart is Disabled
Rising edge detected
Trigger is ignored.
Activation trigger
m
n
0
PPG
(1)
(2)
(1) = T (n+1) μs
T : Counter clock cycle
(2) = T (m+1) μs
m : PCSR value
n : PDUT value
■ When Enabling Restart
Figure 12.5-2 Timing of PWM Operation When Restart is Enabled
Rising edge detected
Restart by trigger.
Activation trigger
m
n
0
PPG
(1)
(1) = T (n+1) μs
(2)
(2) = T (m+1) μs
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CHAPTER 12 PPG TIMER
12.5 PPG Timer Operation
MB90930 Series
Note:
After writing data into PCSR, be sure to write to PDUT.
Refer to the data sheet for the minimum pulse width of the external TRG input.
However, even if a pulse with a smaller pulse width than quoted above is input, it may be
recognized as valid. Also, since there is no filter functions for the external TRG input, add
an external filter as required.
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CHAPTER 12 PPG TIMER
12.5 PPG Timer Operation
MB90930 Series
12.5.2
One Shot Operation
In one shot operation, a single pulse with an arbitrary width can be output by
a trigger. When restart is enabled, the counter value is reloaded if an
activation trigger is detected during operation.
■ When Disabling Restart
Figure 12.5-3 Timing of One Shot Operation When Restart is Disabled
Rising edge detected
Trigger is ignored.
Activation trigger
m
n
0
PPG
(1)
(2)
(1) = T (n+1) μs
(2) = T (m+1) μs
■ When Enabling Restart
Figure 12.5-4 Timing of One Shot Operation When Restart is Enabled
Rising edge detected
Restart by trigger.
Activation trigger
m
n
0
PPG
(1)
(2)
(1) = T (n+1) μs
(2) = T (m+1) μs
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CHAPTER 12 PPG TIMER
12.5 PPG Timer Operation
12.5.3
MB90930 Series
Interrupt Source and Timing
2.5T (T: count clock cycle) is required at most for loading the count value after
an activation trigger.
Figure 12.5-5 Interrupt Output Sources and Timing
Activation trigger
→ Up to 2.5T ←
Load
Clock
Count value
XXXXH
0003H
0002H
0001H
0000H
0003H
0002H
0001H
0000H
PPG
PPG 1/2 division
Interrupt
Software trigger
Compare match
Borrow
Compare match
Borrow
Note:
An interrupt is generated in the timing of 1/1 division when the 1/2, 1/4, and 1/8 division is
used.
■ Example of PWM Output for All "L" or All "H"
PPG
Decrease duty
ratio gradually
Write "1" to PGMS (mask bit) by an
interrupt from a borrow.
When "0" is written to PGMS (mask bit)
using an interrupt by a borrow, PPG waveform
can be output without outputting glitches.
PPG
Decrease duty
ratio gradually
352
Using an interrupt by compare match,
write the same value as that in the cycle
setting register to the duty setting register.
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CM44-10150-1E
CHAPTER 13
REAL-TIME WATCH
TIMER
This chapter describes the functions and
operations of the real-time watch timer.
13.1 Overview of Real-Time Watch Timer
13.2 Registers of Real-Time Watch Timer
13.3 Interrupts of Real-Time Watch Timer
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CHAPTER 13 REAL-TIME WATCH TIMER
13.1 Overview of Real-Time Watch Timer
13.1
MB90930 Series
Overview of Real-Time Watch Timer
The real-time watch timer consists of the real-time watch timer control register,
sub-second data register, second/minute/hour/day data registers, 1/2 clock
divider, 22-bit prescaler, and second/minute/hour/day counters. An MCU
oscillation frequency of 4 MHz is used to operate the real-time watch timer
specified. The real-time watch timer operates as a real-world timer, providing
information on real-world time.
■ Block Diagram of Real-Time Watch Timer
Figure 13.1-1 shows a block diagram of the real-time watch timer.
Figure 13.1-1 Block Diagram of Real-Time Watch Timer
16LX bus
/
16
pin P11/TOT0/PPG3/IN4
Upper bits of subsecond register
Lower bits of subsecond register
22
UPDT
1/2 clock divider
Oscillation clock
Middle bits of subsecond register
1/2 clock divider
Sub-second counter (22-bit down counter)
Second interrupt
ST (start)
16LX bus
/ 16
Second register
6 bits
Minute counter
Second counter
H
H
Day register
Hour register
Minute register
6 bits
5 bits
5 bits
Hour counter
Day counter
H
H
Month interrupt
Minute interrupt
Hour interrupt
Day interrupt
16LX bus
/
16
Upper bits of
control register
Middle bits of
control register
Lower bits of
control register
ST
0E
Second interrupt
Minute interrupt
IRQ#30
Hour interrupt
Day interrupt
Month interrupt
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
13.2
Registers of Real-Time Watch Timer
The six types of registers of the real-time watch timer are as follows:
• Real-time watch timer control register (WTCR)
• Sub-second data register (WTBR)
• Second data register (WTSR)
• Minute data register (WTMR)
• Time data register (WTHR)
• Day data register (WTDR)
■ List of Registers of Real-Time Watch Timer
Figure 13.2-1 lists the registers of the real-time watch timer.
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
Figure 13.2-1 Registers of Real-Time Watch Timer
Real-time watch timer
Upper bits of control register bit 7
Address : 0000CEH
6
5
4
Initial value
Real-time watch timer
Middle bits of control register bit 15
Address : 0000CDH
INTE3
14
13
INT3
(R/W)
(0)
(R/W)
(0)
Initial value
Initial value
Sub-second data register
bit 7
Sub-second data register
Address : 003959H
Initial value
Sub-second data register
Address : 003958H
Initial value
Second data register
INT2
INTE1
INT1
INTE0
INT0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
4
3
2
1
Reserved Reserved Reserved
4
0
WTCRL
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
1
0
D21
D20
D19
D18
D17
D16
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
WTBRH
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D9
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
S0
(R/W)
(0)
bit 7
bit 15
bit 7
6
bit 15
14
S5
S4
S3
S2
S1
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
WTBRM
WTBRL
WTSR
5
4
3
2
1
0
M5
M4
M3
M2
M1
M0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
13
Initial value
WTMR
12
11
10
9
8
H4
H3
H2
H1
H0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
WTHR
12
11
10
9
8
MS1
MS0
N4
N3
N2
N1
N0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
bit 15
14
13
WTCRH
WTCRM
D15
Initial value
Initial value
8
bit 15
Address : 00395CH
Day data register
Address : 00395EH
9
(R/W)
(0)
5
Initial value
Hour data register
Address : 00395DH
10
(R/W)
(0)
6
Address : 00395BH
Minute data register
0
INT4
(R/W)
(0)
INTE2
(R/W)
(0)
Initial value
1
11
(R/W)
(0)
Address : 00395AH
2
12
Real-time watch timer
5
6
Lower bits of control register bit 7
Address : 0000CCH
Reserved Reserved Reserved
(R/W)
(0)
3
Reserved Reserved INTE4
(R/W)
(R/W) (R/W)
(0)
(0)
(0)
WTDR
R/W : Readable/Writable
-:
Undefined
X:
Undefined value
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
13.2.1
Real-Time Watch Timer Control Register
The real-time watch timer control register is used to start and stop the real-time
watch timer, control interrupts, and set external output pins.
■ Bit Configuration of Timer Control Register
Figure 13.2-2 shows the bit configuration of the timer control register.
Figure 13.2-2 Bit Configuration of Timer Control Register
Real-time watch timer
Upper bits of control register bit 7
Address : 0000CEH
6
5
4
3
2
1
Reserved Reserved INTE4
(R/W)
(R/W) (R/W)
(0)
(0)
(0)
Initial value
0
INT4
(R/W)
(0)
Real-time watch timer
Middle bits of control register bit 15
Address : 0000CDH
INTE3
14
13
12
11
10
9
8
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
1
Initial value
Real-time watch timer
5
6
Lower bits of control register bit 7
Address : 0000CCH
Reserved Reserved Reserved
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
4
Reserved Reserved Reserved
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
WTCRH
WTCRM
0
ST
WTCRL
(R/W)
(0)
R/W : Readable/Writable
-:
Undefined
X:
Undefined value
WTCRH [bit7 to bit4] Undefined bits
• If these bits are read, "1" is read.
• Writing to these bits does not affect the operation.
WTCRH [bit3, bit3] Reserved bits
These bits must be set to "00".
WTCRH [bit1, bit0], WTCRM [bit15 to bit8]: INT4 to INT0, INTE4 to INTE0: Interrupt
flag, and interrupt enable flag
INT4 to INT0 are interrupt flags, which are set in case of overflow in the sub-second
counter, second counter, minute counter, hour counter, or day counter. When the
corresponding INTE bit is "1" at the time the INT bit is set to "1", the real-time watch timer
generates an interrupt signal. These flags are designed to generate an interrupt signal at
every one second, one minute, one hour, one day, and one month, respectively.
By setting the INT bit set to "0", the corresponding flag is cleared. Setting the bit to "1" has
no effect. In read-modify-write instructions executed for the INT bit, "1" is read out.
WTCRL [bit7 to bit5] Reserved
These bits must be set to "000".
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
WTCRL [bit4] Undefined bits
• If this bit is read, "1" is read.
• Writing to this bit does not affect the operation.
WTCRL [bit3, bit2, bit1] Reserved
This bit must be set to "000".
WTCRL [bit 0] ST: Start bit
When the ST bit is set to "1", the real-time watch timer loads the second/minute/hour/day
values from each register to start the corresponding operation. Note that resetting the ST bit
to "0" also resets all counters and prescalers to "0" and stops operation.
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
13.2.2 Sub-Second Data Register
The sub-second data register stores the reload values of the 22-bit prescaler
used for dividing the frequency of the oscillation clock. Reload values are
specified in such a way that 22-bit prescaler output takes an interval of
precisely half seconds.
■ Bit Configuration of Sub-second Data Register
Figure 13.2-3 shows the bit configuration of the sub-second data register.
Figure 13.2-3 Bit Configuration of Sub-second Data Register
Sub-second data register
Address : 00395A H
bit
Initial value =>
Sub-second data register
Address : 003959 H
bit
Initial value =>
Sub-second data register
Address : 003958
H
Initial value =>
bit
7
-
6
-
5
D21
4
D20
3
D19
2
D18
1
D17
0
D16
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
WTBRH
WTBRM
WTBRL
R/W : Readable/Writable
-:
Undefined
X:
Undefined value
WTBRH [bit5 to bit0], WTBRM [bit15 to bit8], WTBRL [bit7 to bit0]: D21 to D0
The sub-second data register is used to store a reload value for the 22-bit prescaler. This
value is reloaded after the reload counter reaches "0". Confirm that reload operation is not
executed between write instructions after changing all 3 bytes. Otherwise, the 22-bit
prescaler may load an incorrect value that combines bytes from new and old data. We
recommend rewriting the contents of the sub-second register in ordinary cases (with the
start bit set to "0"). If the sub-second register is set to "0", the 21-bit prescaler does not
operate.
The oscillation clock is used as the input clock, and its frequency is designed to be 4 MHz.
Setting hexadecimal 0F423F as the reload value of the 22-bit prescaler results in the clock
signal output at accurate intervals of 0.5 second.
WTBRH [bit7, bit6] Undefined bit
• If these bits are read, "1" is read.
• Writing to these bits does not affect the operation.
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
13.2.3
MB90930 Series
Second/Minute/Hour/Day Data Registers
The second/minute/hour/day data registers are used to store time information.
The data of second, minute, hour, and day is indicated in binary notation. When
these registers are read, the unit simply returns the counter values. However,
the MS1 and MS0 bits of the WTDR register retain the values that were set in
the register, and the set values are read.
■ Bit Configuration of Second/minute/hour/day Data Registers
bit 15
Initial value =>
Second data register
Address: 00395BH
14
-
bit 7 6 5 4
Initial value =>
-
Minute data register
Address: 00395C H
Hour data register
Address:
bit 15
Initial value =>
-
00395DH
14
-
bit 7 6 5 4
MS1
MS0
R/W
R/W
Initial value =>
(0)
(0)
Day data register
Address: 00395EH
13
S5
R/W
(0)
12
S4
R/W
(0)
11
S3
R/W
(0)
10
S2
R/W
(0)
9
S1
R/W
(0)
8
S0
R/W
(0)
M5
R/W
(0)
M4
R/W
(0)
3210
M3
M2
R/W
R/W
(0)
(0)
M1
R/W
(0)
M0
R/W
(0)
13
-
12
H4
R/W
(0)
11
H3
R/W
(0)
10
H2
R/W
(0)
9
H1
R/W
(0)
8
H0
R/W
(0)
-
N4
R/W
(0)
3210
N3
N2
R/W
R/W
(0)
(0)
N1
R/W
(0)
N0
R/W
(1)
WTSR
WTMR
WTHR
WTDR
R/W : Readable/Writable
-:
Undefined
WTSR [bit13 to bit8] S5 to S0 bits: Second data bits
WTMR [bit5 to bit0] M5 to M0 bits: Minute data bits
WTHR [bit12 to bit8] H4 to H0 bits: Hour data bits
WTDR [bit4 to bit0] N4 to N0 bits: Day data bits
Since the second/minute/hour/day data registers have 4 byte registers, please check that the
value obtained from the registers is consistent. For example, if the value of "1 day, 1 hour, 59
minutes, 59 seconds" is obtained, that value may represent "1 day, 0 hour, 59 minutes, 59
seconds", "1 day, 1 hour, 0 minutes, 0 seconds", or "1 day, 2 hours, 0 minutes, 0 seconds".
Similarly, the operation clock of the MCU is one half of the oscillation clock (when the PLL
stops), the read value from these registers may be incorrect. This is caused by synchronization
between the read operation and the count operation. Therefore, it is recommended that the read
instruction is triggered by using the second interrupt.
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CHAPTER 13 REAL-TIME WATCH TIMER
13.2 Registers of Real-Time Watch Timer
MB90930 Series
Note:
Do not set impossible data (e.g., 60 seconds) in the WTSR, WTMR, WTHR, or WTDR
register. Do not set the N4 to N1 bits to a value that conflicts with the value set in the MS1 and
MS0 bits.
WTDR [bit7, bit6] MS1 and MS0 bits: Day count data setting bits
These bits are used to specify the maximum count value of the day counter.
MS1
MS0
0
0
Counts up to 31 days (initial value).
0
1
Counts up to 30 days.
1
0
Counts up to 29 days.
1
1
Counts up to 28 days.
WTSR [bit15, bit14] Undefined bits
WTMR [bit7, bit6] Undefined bits
WTHR [bit15 to bit13] Undefined bits
WTDR [bit5] Undefined bit
• If this bit is read, "1" is read.
• Writing to this bit does not affect the operation.
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CHAPTER 13 REAL-TIME WATCH TIMER
13.3 Interrupts of Real-Time Watch Timer
13.3
MB90930 Series
Interrupts of Real-Time Watch Timer
The real-time watch timer can be generated an interrupt request when the subsecond counter, second counter, minute counter, hour counter, or day counter
overflows.
■ Interrupts of Real-Time Watch Timer
Table 13.3-1 lists the interrupt control bits and interrupt sources of the real-time watch timer.
Table 13.3-1 Interrupt Control Bits and Interrupt Sources of Real-Time Watch Timer
Real-time watch timer control register (WTCR)
Interrupt source
Interrupt flag bit
Interrupt enable bit
Second interrupt
(sub-second counter overflow)
INT0
INTE0
Minute interrupt
(second counter overflow)
INT1
INTE1
Hour interrupt
(minute counter overflow)
INT2
INTE2
Day interrupt
(hour counter overflow)
INT3
INTE3
Month interrupt
(day counter overflow)
INT4
INTE4
Clearance of interrupt flag
• Writing "0" to the INT0 to
INT4 bit
• Resetting
If the interrupt source listed in Table 13.3-2 is generated, the interrupt flag bit of the real-time
watch timer is set to "1". If the interrupt enable bit of the real-time watch timer is "1" when the
interrupt flag bit is set to "1", the real-time watch timer outputs an interrupt request to the
interrupt controller.
■ Interrupts of Real-Time Watch Timer and EI2OS
Table 13.3-2 shows the real-time watch timer interrupt and EI2OS.
Table 13.3-2 Interrupts of Real-Time Watch Timer and EI2OS
Channel
Real-time
watch timer
Interrupt
number
#30 (1EH)
Interrupt level setting
register
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
ICR09
0000B9H
FFFF84H
FFFF85H
FFFF86H
*
*: Cannot be used
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CHAPTER 14
DELAY INTERRUPT
GENERATION MODULE
This chapter describes the functions and
operations of the delay interrupt generation
module.
14.1 Overview of Delay Interrupt Generation Module
14.2 Operation of Delay Interrupt Generation Module
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CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
14.1 Overview of Delay Interrupt Generation Module
MB90930 Series
Overview of Delay Interrupt Generation Module
14.1
The delay interrupt generation module is used to generate an interrupt for task
switching. Using this module enables software to issue/cancel an interrupt
request to F2MC-16LX CPU.
■ Block Diagram of Delay Interrupt Generation Module
Figure 14.1-1 shows a block diagram of the delay interrupt generation module.
Figure 14.1-1 Block Diagram of Delay Interrupt Generation Module
Internal data bus
Delay interrupt source generation/clear
Source latch
■ List of Registers of Delay Interrupt Generation Module
The following figure shows the register configuration of the delay generation module [delay
interrupt source generation/clear register (DIRR: Delayed Interrupt Request Register)].
Figure 14.1-2 Register Configuration of Delay Interrupt Generation Module
DIRR Address:
bit15
bit14
bit13
bit12
bit11
bit10
bit9
00009FH
bit8
D8
R/W
Initial value
XXXXXXX0B
This register becomes a source clear state when reset.
DIRR is used to generate/cancel a delay interrupt request. Writing "1" to this register generates
a delay interrupt request; writing "0" cancels the request. This register becomes a source clear
state when reset. Although the undefined bit area can be written to either "0" or "1", in
consideration of future extensions, it is recommended that the set bit and clear bit instructions
are used to access this register.
■ Interrupts of Delay Interrupt Generation Module and EI2OS
Table 14.1-1 lists the interrupts of the delay interrupt generation module and EI2OS.
Table 14.1-1 Interrupts of Delay Interrupt Generation Module and EI2OS
Interrupt level setting register
Vector table address
Interrupt No.
#42(2AH)
Register name
Address
Lower
Upper
Bank
ICR15
0000BFH
FFFF54H
FFFF55H
FFFF56H
EI2OS
X
X: Not available
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CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
14.2 Operation of Delay Interrupt Generation Module
MB90930 Series
14.2
Operation of Delay Interrupt Generation Module
When the CPU writes "1" to the relevant bit in DIRR by software, the request
latch in the delay interrupt generation module is set to generate an interrupt
request to the interrupt controller.
■ Operation of Delay Interrupt Generation Module
When the CPU writes "1" to the relevant bit in DIRR by software, the request latch in the delay
interrupt generation module is set to generate an interrupt request to the interrupt controller. If
any other interrupt request has a priority lower than that of the interrupt from the delay
interrupt generation module, or if there are no other interrupt requests, the interrupt controller
issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM
bit in its internal request. If the request level is higher than that of the ILM bit, the CPU starts a
hardware interrupt handling microprogram immediately after the instruction in current
execution is completed. As a result, the interrupt handling routine is executed in response to the
interrupt generated by the delay interrupt generation module. Writing "0" to the relevant bit of
DIRR within the interrupt handling routine clears the interrupt source of the delay interrupt
generation module, and also switches the task. Figure 14.2-1 shows the operation of the delay
interrupt generation module.
Figure 14.2-1 Operation of Delay Interrupt Generation Module
Delay interrupt generation module
Delay interrupt controller
WRITE
Other
request
F2MC-16LX
ICR yy
ICR yy
CMP
DIRR
CMP
ICR xx
ICR xx
INTA
■ Notes on Using Delay Interrupt Generation Module
● Delay interrupt request latch
This latch is set by writing "1" to the relevant bit of DIRR, and cleared by writing "0" to that
bit. Therefore, note that the interrupt handling starts again immediately after the return from the
interrupt handling unless the software has been designed to clear the source within the interrupt
handling routine.
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CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
14.2 Operation of Delay Interrupt Generation Module
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CM44-10150-1E
CHAPTER 15
DTP/EXTERNAL
INTERRUPT CIRCUIT
This chapter describes the functions and
operations of the DTP/external interrupt circuit.
15.1 Overview of DTP/External Interrupt Circuit
15.2 Configuration of DTP/External Interrupt Circuit
15.3 Pins of DTP/External Interrupt Circuit
15.4 Registers of DTP/External Interrupt Circuit
15.5 Operations of DTP/External Interrupt Circuit
15.6 Notes on Using the DTP/External Interrupt Circuit
15.7 Sample Programs of DTP/External Interrupt Circuit
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.1 Overview of DTP/External Interrupt Circuit
15.1
MB90930 Series
Overview of DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral)/external interrupt circuit is located between
externally connected peripheral units and the F2MC-16LX CPU. This circuit is
used to transfer an interrupt request or a data transfer request generated by
the peripheral unit to the CPU, generate an external interrupt request, or start
the extended intelligent I/O service (EI2OS).
■ DTP/External Interrupt Function
The DTP/external interrupt function uses a signal input to the DTP/external interrupt pin as a
start source, which is received by the CPU according to the same procedure as for normal
hardware interrupt. This function is used to generate an external interrupt and to start the
extended intelligent I/O service (EI2OS).
When an interrupt request is received by the CPU, and the corresponding extended intelligent
I/O service (EI2OS) is disabled, the DTP/external interrupt function operates as an external
input function and branches to an interrupt routine. When the EI2OS is enabled, the function
operates as the DTP function, transfers data automatically via the EI2OS, and branches to an
interrupt routine when the specified numbers of data transfer is completed. Table 15.1-1 shows
an overview of the DTP/external interrupt.
Table 15.1-1 Overview of DTP/External Interrupt
External interrupt
Input pin
Interrupt source
Interrupt No.
DTP function
× 8 (P50/INT0, P51/INT1, P53/INT3, P55/INT2, PC0/INT4 to PC3/INT7)
Selects the detection level or edge for each pin with the request level register
(ELVRH/ELVRL)
Inputs either "H" level/"L" level/rising edge/
falling edge
Inputs "H" level/"L" level
#16 (10H), #20 (14H), #24 (18H), #26 (1AH)
Interrupt control
Enables or disables an interrupt request output by external interrupt enable register (ENIR)
Interrupt flag
Retains the interrupt source in the external interrupt source register (EIRR)
2
Selection of processing Sets EI OS to "disabled"
(ICR:ISE=0)
Processing
Branches to the external interrupt processing
routine
Sets the EI2OS to "enabled"
(ICR:ISE=1)
Branches to the interrupt routine after the specified
number of automatic data transfers via the EI2OS is
completed
ICR: Interrupt control register
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.1 Overview of DTP/External Interrupt Circuit
MB90930 Series
■ Interrupts of DTP/External Interrupt Circuit and EI2OS
Table 15.1-2 lists interrupts of the DTP/external interrupt circuit and the EI2OS.
Table 15.1-2 Interrupts of DTP/External Interrupt Circuit and EI2OS
Interrupt control register
Channel
Vector table address
Interrupt No.
Register
name
Address
Lower
Upper
Bank
#16 (10H)
ICR02
0000B2H
FFFFBCH
FFFFBDH
FFFFBEH
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
#24 (18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
#26(1AH)
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
EI2OS
: Available if the interrupt requests shared with the registers ICR02 to ICR07 are not used.
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.2 Configuration of DTP/External Interrupt Circuit
MB90930 Series
Configuration of DTP/External Interrupt Circuit
15.2
The DTP/external interrupt circuit consists of the following four blocks.
• DTP/Interrupt input detection circuit
• External interrupt level setting register (ELVRL/ELVRH)
• External interrupt source register
• External interrupt enable register (ENIR)
■ Block Diagram of DTP/External Interrupt Circuit
Figure 15.2-1 shows a block diagram of the DTP/external interrupt circuit.
Figure 15.2-1 Block Diagram of DTP/External Interrupt Circuit
External interrupt level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Pin
Selector
Selector
PC3/INT7
Pin
Selector
Selector
PC2/INT6
Internal data bus
Pin
P50/INT0
Pin
P51/INT1
Pin
Selector
Selector
PC1/INT5
Pin
P55/INT2
Pin
Selector
Pin
Selector
P53/INT3
PC0/INT4
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#16(10H)
#20(14H)
#24(18H)
#26(1AH)
EN7
370
EN6
EN5
EN4
EN3
EN2
EN1
EN0
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MB90930 Series
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.2 Configuration of DTP/External Interrupt Circuit
● DTP/external interrupt input detection circuit
When the level or edge selected for each pin by the external interrupt level setting register
(ELVRH/ELVRL) is detected from a pin input signal and then the valid signal is detected. The
IR bit of the external interrupt source register (EIRR) corresponding to the pin is set to "1".
● External Interrupt Level Setting Register (ELVRH/ELVRL)
Selects a valid level or edge for each pin.
● External Interrupt Source Register (EIRR)
Retains the DTP/external interrupt source. When there is an external interrupt request flag bit
corresponding to each pin and the pin has the valid signal, this register is set to "1".
● External Interrupt Enable Register (ENIR)
Enables/disables an external interrupt for each pin.
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.3 Pins of DTP/External Interrupt Circuit
15.3
MB90930 Series
Pins of DTP/External Interrupt Circuit
This section describes the pins of the DTP/external interrupt circuit and their
block diagram.
■ Pins of DTP/External Interrupt Circuit
The pins of the DTP/external interrupt circuit are used as both general-purpose ports and other
peripheral functions. Table 15.3-1 shows the pin functions, I/O type, and settings for using the
DTP/external interrupt circuit.
Table 15.3-1 Pins of DTP/External Interrupt Circuit
Pin name
P50/INT0/
ADTG
P51/INT1/
RX1/RX3
P53/INT3
Pin function
I/O type
Pull-up
resistor
Standby
control
Setting required to use pins
None
Sets to input port
(DDR5: bit0=0)
Sets to input port
(DDR5: bit1=0)
Sets to input port
(DDR5: bit3=0)
Sets to input port
(DDR5: bit5=0)
Sets to input port
(DDRC: bit0=0)
Sets to input port
(DDRC: bit1=0)
UART0 data output disabled
Sets to input port
(DDRC: bit2=0)
UART0 clock output disabled
Sets to input port
(DDRC: bit3=0)
I/O of Port 5/
External interrupt input
P55/INT2/
RX0/RX2
CMOS output/
CMOS hysteresis
PC0/INT4/SIN0
PC1/INT5/IN3/
SOT0
PC2/INT6/IN2/
SCK0
None
I/O of Port C/
External interrupt input
PC3/INT7/SIN1
■ Block Diagram of DTP/External Interrupt Circuit Pins
Figure 15.3-1 shows a block diagram of the pins of the DTP/external interrupt circuit.
Figure 15.3-1 Block Diagram of DTP/External Interrupt Circuit Pins
Internal data bus
PDR (Port data register)
PDR read
Output latch
Resource input (INT)
P-ch
PDR write
DDR( Port direction register)
Pin
N-ch
Direction
latch
DDR write
DDR read
372
Standby control (SPL=1)
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4 Registers of DTP/External Interrupt Circuit
MB90930 Series
15.4
Registers of DTP/External Interrupt Circuit
This section lists the registers of the DTP/external interrupt circuit.
■ Registers of DTP/External Interrupt Circuit
The DTP/external interrupt circuit consists of the following three types.
• External interrupt source register (EIRR)
• External interrupt enable register (ENIR)
• External interrupt level setting register (ELVRH/ELVRL)
Figure 15.4-1 lists the registers of the DTP/external interrupt circuit.
Figure 15.4-1 List of Registers of DTP/External Interrupt Circuit
Address
bit15
bit8
bit7
bit0
000031H, 000030H External interrupt source register (EIRR) External interrupt enable register (ENIR)
000033H, 000032H
CM44-10150-1E
External interrupt level setting register (ELVR)
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4 Registers of DTP/External Interrupt Circuit
15.4.1
MB90930 Series
External Interrupt Source Register (EIRR)
The external interrupt source register (EIRR) is used to retain and clear
interrupt sources.
■ External Interrupt Source Register (EIRR)
Figure 15.4-2 shows the configuration of the external interrupt source register. Table 15.4-1
lists the functions of each bit.
Figure 15.4-2 External Interrupt Source Register (EIRR)
Address
000031H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ER7 to
ER0
R/W : Readable/Writable
: Initial value
0
1
bit7
bit0
ENIR
Initial value
00000000B
External interrupt request flag bit
When reading
When writing
No DTP/external interrupt input
Clears this bit
DTP/External interrupt input No change, and no effect on others
Table 15.4-1 Functions of Each Bit of External Interrupt Source Register (EIRR)
Bit name
Function
•
•
bit15 ER7 to ER0:
to External interrupt
•
bit8 request flag bit
•
Sets to "1" when the edge or level signal selected by the bits (LB7, LA7 to LB0, LA0) of the
external interrupt level setting register (ELVRH/ELVRL) is input to the DTP/external
interrupt pin (retaining the interrupt source).
Outputs an interrupt request to the CPU when this bit and the corresponding bits (EN7 to
EN0) of the external interrupt enable register (ENIR) are set to "1".
This bit is cleared by writing "0". Writing "1" has no effect on this bit, and the bit remains
unchanged.
If the extended intelligent I/O service (EI2OS) is activated, the corresponding external
interrupt request flag bit is automatically cleared when one data transfer is completed.
Notes: • When a read-modify-write (RMW) instruction is used, "1" is read.
• When multiple external interrupt request outputs are enabled (ENIR:EN7 to EN0=1), clear only the bits which the
CPU accepts an interrupt (the bits set to "1" among ER7 to ER0). No other bits must be cleared unconditionally.
The initial value is "00H". However, the value after reset cancellation depends on the state of the DTP/external
interrupt pin.
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CM44-10150-1E
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4 Registers of DTP/External Interrupt Circuit
MB90930 Series
15.4.2
External Interrupt Enable Register (ENIR)
The external interrupt enable register (ENIR) is used to enable/disable interrupt
request output to the CPU.
■ External Interrupt Enable Register (ENIR)
Figure 15.4-3 shows the configuration of the external interrupt enable register (ENIR). Table
15.4-2 lists the functions of each bit.
Also, Table 15.4-3 shows the correspondence among the external interrupt source register
(EIRR), the external interrupt enable register (ENIR), and each channel.
Figure 15.4-3 External Interrupt Enable Register (ENIR)
Address bit15
000030H
bit 8
EI RR
bit 7
bit 6
bit 6
bit 4 bit 3
bit 2
bit 1
bit 0 Initial value
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B
R/W
R/W : Readable/Writable
: Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EN7 to
EN0
External interrupt request enable bit
0
1
External interrupt requests disabled
External interrupt requests enabled
Table 15.4-2 Functions of Each Bit of External Interrupt Enable Register (ENIR)
Bit name
bit7
to
bit0
EN7 to EN0:
External interrupt
request enable bits
Function
Bits to enable/disable interrupt request output to the CPU. When these bits and the
corresponding bits (ER7 to ER0) of the external interrupt source register (EIRR) are "1", an
interrupt request is output to the CPU.
• The state of the DTP/external interrupt pin can be read from the port data register, regardless
of the state of the external interrupt request enable bits.
• The bits (ER7 to ER0) of the external interrupt source register (EIRR) is set to "1" when an
interrupt source is detected, regardless of the value of the external interrupt request enable
bits.
Note: To use the DTP/external interrupt pin, write "0" to the corresponding port direction register bit and set the pin as "input".
Table 15.4-3 Correspondence between Channels and DTP/Interrupt Control Register (EIRR,
ENIR)
DTP/External interrupt pin
Interrupt No.
External interrupt request
flag bit
External interrupt request
enable bit
PC3/INT7
#26 (1AH)
ER7
EN7
PC2/INT6
#26 (1AH)
ER6
EN6
PC1/INT5
#24 (18H)
ER5
EN5
PC0/INT4
#24 (18H)
ER4
EN4
P53/INT3
#20 (14H)
ER3
EN3
P55/INT2
#20 (14H)
ER2
EN2
P51/INT1
#16 (10H)
ER1
EN1
P50/INT0
#16 (10H)
ER0
EN0
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4 Registers of DTP/External Interrupt Circuit
15.4.3
MB90930 Series
External Interrupt Level Setting Register
(ELVRH/ELVRL)
The external interrupt level setting register (ELVRH/ELVRL) is used to select a
signal level or edge type for each pin for detecting that an signal input to the
DTP/external interrupt pin is a DTP/external interrupt source.
■ External Interrupt Level Setting Register (ELVRH/ELVRL)
Figure 15.4-4 shows the configuration of the external interrupt level setting register (ELVRH/
ELVRL). Table 15.4-4 lists the functions of each bit.
Also, Table 15.4-5 shows the correspondence between each bit of the external interrupt level
setting register (ELVRH/ELVRL) and each channel.
Figure 15.4-4 Configuration of External Interrupt Level Setting Register (ELVRH/ELVRL)
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B
000032H
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B
R/W : Readable/Writable
: Initial value
LB7 to
LB0
LA7 to
LA0
0
0
0
1
0
1
1
External interrupt request detection selection bits
1
"L" level detection
"H" level detection
Rising edge detection
Falling edge detection
Table 15.4-4 Functions of Each Bit of External Interrupt Level Setting Register (ELVRH/ELVRL)
Bit name
bit15
to
bit0
Function
LB7 to LB0, LA7 to LA0:
External interrupt request
detection selection bits
•
•
Bits to select the signal level or edge type which is input to the DTP/external
interrupt pin and used as DTP/external interrupt source.
Two bits are assigned to one pin.
Note: When a selected detection signal is input to the DTP/external interrupt pin, the external interrupt request flag bit is set
to "1", regardless of the setting of the external interrupt enable register (ENIR).
Table 15.4-5 Correspondence between Channels and Bits of External Interrupt Level Setting
Register (ELVRH/ELVRL)
376
DTP/external interrupt pin
Interrupt No.
Bit name
PC3/INT7
#26(1AH)
LB7, LA7
PC2/INT6
#26(1AH)
LB6, LA6
PC1/INT5
#24 (18H)
LB5, LA5
PC0/INT4
#24 (18H)
LB4, LA4
P53/INT3
#20 (14H)
LB3, LA3
P55/INT2
#20 (14H)
LB2, LA2
P51/INT1
#16 (10H)
LB1, LA1
P50/INT0
#16 (10H)
LB0, LA0
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CM44-10150-1E
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operations of DTP/External Interrupt Circuit
MB90930 Series
15.5
Operations of DTP/External Interrupt Circuit
The DTP/external interrupt circuit has an external interrupt function and a DTP
function. This section describes the settings and operations of each function.
■ Settings of the DTP/External Interrupt Circuit
To operate the DTP/external interrupt circuit, the settings shown in Figure 15.5-1 are required.
Figure 15.5-1 DTP/External Interrupt Circuit
ICR07/ bit15 bit14 bit13 bit12 bit11 bit10 bit9
ICR06/ ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1
ICR04/
0
◆
◆
ICR02
◆
◆
◆
◆
1
◆
◆
bit8
bit3
bit2
bit1
bit0
IL0 ICS3 ICS2 ICS1 ICS0 ISE
◆
0
◆
◆
◆
◆
◆
1
bit7
bit6
bit5
bit4
IL2
◆
◆
IL1
◆
◆
IL0
◆
◆
For external interrupts
For DTP
EIRR/ ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN EN2 EN1 EN0
ENIR
◆
◆
◆
◆
◆
◆
◆
◆
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
DDR5/
DDRC
P55
P53
P51 P50
PC3 PC2 PC1 PC0
◆ : Used bit
: Set "1" to the bit corresponding to the used pin
: Set "0" to the bit corresponding to the used pin
0 : Set to "0"
1 : Set to "1
Set the registers of the DTP/external interrupt circuit as follows:
1) Set the input port to the general-purpose I/O port, which is shared with the pin to be used
as external interrupt input.
2) Disable the target bit for the external interrupt enable register (ENIR).
3) Set the target bit for the external interrupt level setting register (ELVRH/ELVRL).
4) Clear the target bit for the external interrupt source register (EIRR).
5) Enable the target bit for the external interrupt enable register (ENIR).
Before setting the registers of the DTP/external interrupt circuit, disable the external interrupt
request output (ENIR: EN7 to EN0=0) first. To enable the external interrupt request output
(ENIR: EN7 to EN0=1), the corresponding interrupt request flag bit must be cleared (EIRR:
ER7 to ER0=0) in advance.
This is to avoid accidentally generating an interrupt request when setting the register.
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operations of DTP/External Interrupt Circuit
MB90930 Series
● Switching between external interrupt function and DTP function
To switch between the external interrupt function and the DTP function, set the ISE bit of the
corresponding interrupt control register (ICR). When the ISE bit is "1", the extended intelligent
service (EI2OS) is enabled and the DTP function operates. When the ISE bit is "0", the EI2OS
is disabled and only the external interrupt function can operate.
Note:
When multiple interr upts are assigned to o ne ICR r egister, all of th ese interrupt request has
the same interrupt level (IL2 to IL0). Using EI2OS with one interrupt request will generally
disable the use of other interrupt requests.
■ DTP/External Interrupt Operation
Table 15.5-1 lists the control bits and interrupt sources of the DTP/external interrupt circuit.
Table 15.5-1 Control Bits and Interrupt Sources of DTP/External Interrupt Circuit
DTP/external interrupt circuit
Interrupt request flag bit
EIRR: ER7 to ER0
Interrupt request enable bit
ENIR: EN7 to EN0
Interrupt source
Valid edge/level input to pins (INT7 to INT0)
If a source specified by the external interrupt level setting register (ELVRH/ELVRL) is input
to the corresponding pin after a DTP/external interrupt request is set, this resource generates an
interrupt request signal to the interrupt controller. When the ISE bit is "0", an interrupt
handling microprogram is executed. When the ISE bit is "1", an extended intelligent I/O service
(EI2OS) processing (DTP processing) microprogram is executed. Figure 15.5-2 shows a
flowchart of the DTP/external interrupt circuit operation.
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CM44-10150-1E
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operations of DTP/External Interrupt Circuit
MB90930 Series
Figure 15.5-2 Flowchart of DTP/External Internal Circuit Operation
DTP/External interrupt circuit
Other request
Interrupt controller
ELVRH/
CPU
ELVRL
EIRR
ICR YY
ENIR
ICR XX
IL
CMP
CMP
ILM
Interrupt
handling
microprogram
Source
DTP processing routine
(EI2OS starts)
Generation of DTP/external
interrupt request
Date transfer between
memory and peripheral
Judging interrupt
controller acceptance
Update descriptor
Descriptor
data counter
Judging CPU
interrupt acceptance
0
≠0
Return from DTP processing
Starting interrupt
handling microprogram
Interrupt handling routine
Resetting or stopping
CPU process return
1
ICR : ISE
0
Starting external interrupt routine
Processing and clearing interrupt flag
Return from external interrupt
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operations of DTP/External Interrupt Circuit
15.5.1
MB90930 Series
External Interrupt Function
The DTP/external interrupt circuit has an external interrupt function that issues
an interrupt request by an input to the DTP external interrupt pin with a signal
level selected.
■ External Interrupt Function
When a signal (edge or level) selected by the external interrupt level setting register (ELVRH/
ELVRL) is detected at the DTP/external interrupt pin, the bits (ER7 to ER0) of the external
interrupt source register (EIRR) are set to "1". In such case, when the interrupt request enable
bits of the external interrupt enable register (ENIR) is set to "enable" (ENIR: EN7 to EN0=1),
generation of an interrupt source is reported to the interrupt controller. The interrupt controller
determines the priority of the interrupt level (ICR: IL2 to IL0) for interrupt requests from other
peripheral functions and the interrupt priority when multiple interrupt is issued at the same
time. The CPU determines the interrupt level mask register (PS: ILM2 to ILM0), the priority of
the interrupt level, and the interrupt enable bit (PS: CCR=1). When the interrupt request is
accepted by the CPU, an interrupt handling (microprogram) by an internal CPU operation is
executed to branch to an interrupt handling routine. Clear the interrupt request by writing "0" to
the interrupt request flag bit processed in the interrupt handling routine.
Notes:
• The ER bit is set to "1" when the DTP/external interrupt start source, regardless of the
state of the corresponding EN bit.
• When the interrupt routine starts, clear the ER bit that is the start source. While the ER
bit is set to "1", the process cannot return from the interrupt. In such case, be sure not
to clear any flag bit other than that for the interrupt source unconditionally.
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CM44-10150-1E
MB90930 Series
15.5.2
DTP Function
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operations of DTP/External Interrupt Circuit
The DTP/external interrupt circuit has a DTP function that detects a signal from
the external peripheral unit at the DTP/external interrupt pin to start an
extended intelligent I/O service (EI2OS).
■ Operation of DTP Function
The DTP function detects a data transfer request signal from an external peripheral unit, then
automatically transfers data between memory and the peripheral unit. An external interrupt
function for level detection will start the extended intelligent I/O service (EI2OS). This
function operates in the same way as an external interrupt function before the CPU accepts an
interrupt request. When EI2OS operation is enabled (ICR: ISE=1) and the interrupt request is
accepted, EI2OS is activated, and data transfer is started. When one data transfer is completed,
the function updates the descriptor clears the interrupt request, and prepares for the next
request from the pin. When all transfer by EI2OS is completed, the process is branched to the
interrupt handling routine.
Figure 15.5-3 shows an example of the interface between memory and an external peripheral
unit.
Figure 15.5-3 Example of Interface with External Peripheral Unit
"H" level request (ELVR: LB0, LA0=01B)
Input to INT0 pin
(DTP source)
CPU internal operation
(microprogram)
Descriptor
selection/reading
Descriptor
update
Read address
Address bus pin
Write address
Write data
Read data
Data bus pin
Read signal
Write signal
*1
Externally
connected
peripheral unit
Internal data bus
Write operation*2
Register
Data transfer
request
Read
DTP source*1
operation*1
Interrupt
INT DTP/External request
interrupt
circuit
CPU
(EI2OS)
Internal
memory
*1: Canceled within three machine clocks after transfer starts
*2: When the extended intelligent I/0 service (EI2OS) is "peripheral → memory transfer"
Note:
The external peripheral unit must cancel only the level of the data transfer request signal
(DTP source) within three machine clocks after initial transfer starts.
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.6 Notes on Using the DTP/External Interrupt Circuit
15.6
MB90930 Series
Notes on Using the DTP/External Interrupt Circuit
This section provides notes on the signals input to the DTP/external interrupt
circuit, and explains how to clear standby mode and interrupts.
■ Notes on Using the DTP/External Interrupt Circuit
● Conditions for peripheral units externally connected when using the DTP function
The externally connected peripheral units where the DTP function can be support must be able
to automatically clear a data transfer request when the transfer starts. Unless a transfer request
is canceled within three machine clock cycles after transfer operation starts, the DTP/external
interrupt circuit assumes that a new transfer request has been generated.
● Input polarity of external interrupts
When the external interrupt level setting register (ELVRH/ELVRL) is set to "edge detection",
the pulse width must be at least 3 machine clocks in order to detect that the edge has been
input.
When the request input level is set to "level setting", the pulse width must be at least 3 machine
clock cycles. Even if the external interrupt source register (EIRR) is cleared, the request to the
interrupt controller is continuously generated as long as the interrupt input pin remains active
level.
When the "level detection" is set and a level to be an interrupt source is input, the source F/F in
the external interrupt source register (EIRR) is set to "1", and the source is retained as shown in
Figure 15.6-1. Therefore, even if the source is canceled, the request to the interrupt controller
remains active as long as the interrupt request output is enabled. To cancel the request to the
interrupt controller, clear the external interrupt request flag bit to clear the source F/F as shown
in Figure 15.6-2.
Figure 15.6-1 Clearing the Source Hold Circuit When a Level is Set
DTP/External
interrupt source
DTP/Interrupt input
detection circuit
Source F/F
(EIRR register)
Enable gate
To interrupt
controller
(interrupt request)
Retains the source unless cleared
Figure 15.6-2 Relationship between DTP/External Interrupt Source and Interrupt Request
when Interrupt Request Output is Enabled
DTP/External interrupt source
(at "H" level detection)
Interrupt source canceled
Interrupt request issued
to interrupt controller
Inactive by clearing source F/F
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.6 Notes on Using the DTP/External Interrupt Circuit
MB90930 Series
● Notes on interrupts
When the external interrupt function is active and the interrupt request output is enabled with
the request flag bit "1", the process cannot return from the interrupt handling. Be sure to clear the
external interrupt request flag bit in the interrupt handing routine. When the DTP function is active,
EI2OS automatically clears this flag. When a level detection is active, the external interrupt request
flag bit is immediately set again, even if the bit was cleared, as long as the level to be an interrupt
source is retained. Disable the interrupt request output or cancel the interrupt source as required.
● Notes in standby mode
When an evaluation product transfers to the standby mode or returns from it, the DTP/ external
interrupt request flag bit in external interrupt source register is set (EIRR: ER) no matter
whether the external interrupt is set enable or disable (ENIR: EN=1/0).
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.7 Sample Programs of DTP/External Interrupt Circuit
15.7
MB90930 Series
Sample Programs of DTP/External Interrupt Circuit
This section provides sample programs of the external interrupt function and
the DTP function.
■ Sample Program of External Interrupt Function
● Processing specifications
The program detects the rising edge of pulses input to the INT0 pin, and generates an external
interrupt.
[Coding example]
ICR02 EQU
0000B2H
; Interrupt control register for
; External external interrupt circuit
DDR5 EQU
000015H
; Port 5 direction register
ENIR EQU
000030H
; External interrupt enable register
EIRR EQU
000031H
; External interrupt source register
ELVRL EQU
000032H
; External interrupt level setting
; register
ELVRH EQU
000033H
; External interrupt level setting
; register
ER0
EQU
EIRR:0
; INT0 interrupt flag bit
EN0
EQU
ENIR:0
; INT0 interrupt enable bit
;----------Main program---------------------------------------CODE CSEG
START:
;
:
; Stack pointer (SP) already
initialized
MOV
I:DDR5, #00000000B ; Set DDR5 to "input"
AND
CCR, #0BFH
; Interrupt disabled
; Interrupt level 0 (highest), EI2OS
; disabled
CLRB EN0
; Disable INT0 with ENIR
MOV
I:ELVR, #00000010B ; Select rising edge for INT0
CLRB I:ER0
; Clear the source of INT0 with EIRR
SETB I:EN0
; Enable INT0 with ENIR
MOV
ILM, #07H
; Set ILM in PS to level 7
OR
CCR, #40H
; Interrupt enabled
LOOP: MOV
A, #00H
; Infinite loop
MOV
A, #01H
BRA
LOOP
;----------Interrupt program----------------------------------WARI:
CLRB ER0
; Clear the interrupt request flag
;
:
;
User processing
;
:
MOV
384
I:ICR02, #00H
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CM44-10150-1E
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.7 Sample Programs of DTP/External Interrupt Circuit
MB90930 Series
RETI
; Return from interrupt.
CODE ENDS
;----------Vector setting-------------------------------------VECT CSEG ABS=0FFH
ORG
0FFBCH
; Set a vector for the interrupt
; #16 (10H)
VECT
DSL
ORG
DSL
DB
ENDS
END
WARI
0FFDCH
START
00H
; Reset vector setting
; Set to single-chip mode
START
■ Sample Program of DTP Function
● Processing specifications
The program detects the "H" level of signal input to the INT0 pin and activate ch.0 of the
extended intelligent I/O service (EI2OS).
The DTP processing (EI2OS) outputs the data in RAM to port 0.
[Coding example]
ICR02 EQU
0000B2H
DDR0
DDR5
ENIR
EIRR
ELVRL
EQU
EQU
EQU
EQU
EQU
000010H
000015H
000030H
000031H
000032H
ELVRH EQU
000033H
ER0
EN0
BAPL
BAPM
EQU
EQU
EQU
EQU
EIRR:0
ENIR:0
000100H
000101H
BAPH
EQU
000102H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Interrupt control register for
DTP/external interrupt circuit
Port 0 direction register
Port 5 direction register
External interrupt enable register
External interrupt source register
External interrupt level setting
register
External interrupt level setting
register
INT0 interrupt flag bit
INT0 interrupt enable bit
Lower bits of buffer address pointer
Middle bits of buffer address
pointer
Upper bits of buffer address pointer
ISCS EQU
000103H
; EI2OS status register
IOAL EQU
000104H
; Lower bits of I/O address register
IOAH EQU
000105H
; Upper bits of I/O address register
DCTL EQU
000106H
; Lower bits of data counter
DCTH EQU
000107H
; Upper bits of data counter
;----------Main program---------------------------------------CODE CSEG
START:
;
:
; Stack pointer (SP) already
; initialized
MOV
I:DDR0, #11111111B ; Set DDR0 to "output"
MOV
I:DDR5, #00000000B ; Set DDR5 to "input"
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CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.7 Sample Programs of DTP/External Interrupt Circuit
AND
MOV
MOV
CCR, #0BFH
I:ICR02, #08H
MB90930 Series
;Interrupt disabled
; Interrupt level 0 (highest)
;
MOV
BAPL, #00H
;
MOV
BAPM, #06H
;
MOV
BAPH, #00H
;
ISCS, #12H
;
;
;
MOV
IOAL, #00H
;
MOV
IOAH, #00H
;
MOV
DCTL, #0AH
;
MOV
DCTH, #00H
;
CLRB I:EN0
;
MOV
I:ELVR, #00000001B ;
CLRB I:ER0
;
EI2OS enable, ch.0
Set output data address
Byte transfer, I/O address
fixed,
buffer address + 1, memory → I/O
As transfer destination address
pointer, specify port 0 (PDR0)
Transfer count: 10 times
Disable INT0 with ENIR
Select "H" level for INT 0
Clear the source of INT0 with
EIRR
SETB I:EN0
; Enable INT0 with ENIR
MOV
ILM, #07H
; Set ILM in PS to level 7
OR
CCR, #40H
; Interrupt enabled
LOOP: MOV
A, #00H
; Infinite loop
MOV
A, #01H
;
BRA
LOOP
;
;----------Interrupt program----------------------------------WARI:
CLRB I:ER0
; Clear the interrupt request flag
;
:
; Switch the channel, change the
; transfer
; address as required
;
User processing
; Set the processing again, such
;
;
;
;
;
as the termination of EI2OS
To terminate the processing,
interrupt must be disabled
Return from interrupt
:
RETI
CODE ENDS
;----------Vector setting-------------------------------------VECT CSEG ABS=0FFH
ORG
0FFBCH
; Set a vector for the interrupt
; #16 (10H)
VECT
386
DSL
ORG
DSL
DB
ENDS
END
WARI
0FFDCH
START
00H
; Reset vector setting
; Set to single-chip mode
START
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CM44-10150-1E
CHAPTER 16
8-/10-BIT A/D
CONVERTER
This chapter describes the functions and
operations of the 8-/10-bit A/D converter.
16.1 Overview of 8-/10-bit A/D Converter
16.2 Block Diagram of 8-/10-bit A/D Converter
16.3 Configuration of 8-/10-bit A/D Converter
16.4 Interrupts of 8-/10-bit A/D Converter
16.5 Explanation of 8-/10-bit A/D Converter Operations
16.6 Precautions when Using 8-/10-bit A/D Converter
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.1 Overview of 8-/10-bit A/D Converter
16.1
MB90930 Series
Overview of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts analog input voltages to 8-bit or 10-bit
digital values in the RC successive approximation conversion method.
• Up to 24 channels of analog input pins can be selected for input signals.
• The software trigger, internal timer output or external trigger can be selected
as a start trigger.
■ Functions of 8-/10-bit A/D Converter
This converter converts an analog voltage (input voltage) which is input to the analog input pin
to an 8-bit or 10-bit digital value (A/D conversion).
The 8-/10-bit A/D converter has the following functions:
• The minimum A/D conversion time is 1.4 μs * per channel, including the sampling time.
• The minimum sampling time is 0.5 μs * per channel.
• The RC successive approximation conversion method with a sample and hold circuit is used
as the conversion method.
• 8-bit or 10-bit resolution can be specified.
• Up to 24 channels can be used as analog input pins.
• Interrupt requests can be generated by storing A/D conversion results in the A/D data
register.
• When an interrupt request is generated, EI2OS can be started.
• The software, internal timer output or external trigger (falling edge) can be selected as a
start trigger.
*: When the frequency of the machine clock is 32MHz, and AVCC ≥ 4.5 V.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.1 Overview of 8-/10-bit A/D Converter
■ Conversion Modes of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has the following conversion modes:
Table 16.1-1 Conversion Modes of 8-/10-bit A/D Converter
Conversion mode
Description
Single conversion mode
A/D conversion is performed sequentially from the start channel to the end
channel. Once the A/D conversion is completed for the end channel, the A/D
conversion function is stopped.
Continuous conversion
mode
A/D conversion is performed sequentially from the start channel to the end
channel. When the A/D conversion for the end channel is completed, the
conversion sequence returns to the start channel to continue the A/D conversion
operation.
Stop conversion mode
A/D conversion is performed while stopping after each channel is processed.
Once the A/D conversion is completed for the end channel, the conversion
sequence returns to the start channel to repeat the A/D conversion and stop
operation.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.2 Block Diagram of 8-/10-bit A/D Converter
16.2
MB90930 Series
Block Diagram of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter consists of the following blocks.
■ Block Diagram of 8-/10-bit A/D Converter
Figure 16.2-1 Block Diagram of 8-/10-bit A/D Converter
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.2 Block Diagram of 8-/10-bit A/D Converter
MB90930 Series
● Detailed descriptions of pins and other items in the block diagram
Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/10-bit A/D
converter.
Table 16.2-1 Pins and Interrupt Request Numbers in Block Diagram
Pin name/Interrupt request number in block diagram
Actual pin name/interrupt request number
ADTG
Trigger input pin
P50/ADTG
TO
Internal timer output
Output of 16-bit reload timer 1
AN0 to AN7
AN8 to AN15
AN16 to AN23
Analog input pins ch.0 to ch.7
Analog input pins ch.8 to ch.15
Analog input pins ch.16 to ch.23
P60/AN0 to P67/AN7
P70/AN8 to P77/AN15
P80/AN16 to P87/AN23
AVRH
Vref+ Input pin
AVRH
AVCC
VCC Input pin
AVCC
AVSS
VSS Input pin
AVSS
Interrupt request output
Interrupt request output
#32 (20H)
● A/D control status register (ADCS0, ADCS1)
This register starts A/D conversion by software, selects the start trigger for the A/D conversion,
selects the conversion mode, enables or disables interrupt requests, checks and clears the
interrupt request flag, pauses A/D conversion operation, checks the state during the conversion,
and selects the resolution type.
● Successive approximation circuit (SAR)
Successive approximation is performed for each bit and the conversion results are stored.
When the next
A/D conversion starts, the results of the current A/D conversion stored in the circuit are
destroyed.
● A/D data register (ADCR0, ADCR1)
The A/D conversion results are stored in the successive approximation circuit for each bit
separately during the conversion and then stored in this register when the A/D conversion is
completed, and the results are confirmed. This register can be used to read the A/D conversion
results.
● A/D setting register (ADSR0, ADSR1)
This register sets up the start channel and end channel for A/D conversion as well as sets the
compare time and sampling time for A/D conversion.
● Start selector
This selects the type of triggers used to start A/D conversion. The internal timer output or
external pin input can be specified as the start trigger.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.2 Block Diagram of 8-/10-bit A/D Converter
MB90930 Series
● Decoder
The decoder selects an analog input pin to be used for A/D conversion from the setting of the
A/D conversion start channel select bits (ADSR: ANS4 to ANS0) and A/D conversion end
channel select bits (ADSR: ANE4 to ANE0) in the A/D setting register.
● Analog channel selector
This selector selects a pin to be used for A/D conversion from the 24 channels of analog input
pins after receiving a signal from the decoder.
● Sample and hold circuit
This circuit holds the input voltage selected by the analog channel selector. As the circuit
maintains the input voltage generated immediately after start of A/D conversion, the
conversion can be performed without being affected by input voltage changes during the A/D
conversion process.
● D/A converter
This converter generates a reference voltage which is compared with the input voltage held in
the sample and hold circuit.
● Comparator
The comparator compares the input voltage held in the sample and hold circuit with the output
voltage of the D/A converter to determine which is higher/lower.
● Control circuit
This circuit determines an A/D conversion value after receiving the higher/lower signal from
the comparator. Once the conversion results are confirmed, the data from these conversion
results is stored in the A/D data register. When the output of interrupt requests is enabled, an
interrupt is generated.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
16.3
Configuration of 8-/10-bit A/D Converter
The pins, registers and interrupt sources of the A/D converter are shown below.
■ Pins of 8-/10-bit A/D Converter
The pins of the 8-/10-bit A/D converter are also used as general-purpose I/O ports. Table 16.31 lists the functions of each pin and settings for when using the 8-/10-bit A/D converter.
Table 16.3-1 Pins of 8-/10-bit A/D Converter (1 / 2)
Function
name
Pin name
Trigger input
P50/ADTG/INT0
ch.0
P60/AN0
ch.1
P61/AN1
ch.2
P62/AN2
ch.3
P63/AN3
ch.4
P64/AN4
ch.5
P65/AN5
ch.6
P66/AN6
ch.7
P67/AN7
CM44-10150-1E
Pin function
Setting for when using 8-/10-bit
A/D converter
General-purpose I/O port/
External trigger input/
External interrupt 0 input
Set as input port by port direction register
(DDR5)
General-purpose I/O port/
Analog inputs/
PPG output
Enable analog signal input
(ADER6: Corresponding bits of ADE7 to
ADE0 set to "1")
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16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-1 Pins of 8-/10-bit A/D Converter (2 / 2)
Function
name
Pin name
ch.8
P70/PWM1P0/
AN8
ch.9
P71/PWM1M0/
AN9
ch.10
P72/PWM2P0/
AN10
ch.11
P73/PWM2M0/
AN11
ch.12
P74/PWM1P1/
AN12
ch.13
P75/PWM1M1/
AN13
ch.14
P76/PWM2P1/
AN14
ch.15
P77/PWM2M1/
AN15
ch.16
P80/PWM1P2/
AN16
ch.17
P81/PWM1M2/
AN16
ch.18
P82/PWM2P2/
AN18
ch.19
P83/PWM2M2/
AN19
ch.20
P84/PWM1P3/
AN20
ch.21
P85/PWM1M3/
AN21
ch.22
P86/PWM2P3/
AN22
ch.23
P87/PWM2M3/
AN23
394
Pin function
General-purpose I/O port/
PWM outputs/
Analog inputs
Setting for when using 8-/10-bit
A/D converter
Enable analog signal input (ADER8,7:
Corresponding bits of ADE23 to ADE8
set to "1")
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MB90930 Series
CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
■ List of Registers and Initial Values of 8-/10-bit A/D Converter
Figure 16.3-1 List of Registers and Initial Values of 8-/10-bit A/D Converter
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
16.3.1
MB90930 Series
Upper bits in the A/D control status register
(ADCS1)
The upper bits in the A/D control status register (ADCS1) enable the following
settings:
• Starting A/D conversion by software
• Selecting the start trigger for A/D conversion
• Enabling or disabling the interrupt requests by storing A/D conversion results
into the A/D data register
• Checking and clearing the interrupt request flag by storing A/D conversion
results into the A/D data register
• Pausing A/D conversion operation and checking the state during the
conversion
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16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
■ Upper Bits in the A/D Control Status Register (ADCS1)
Figure 16.3-2 Upper Bits in the A/D Control Status Register (ADCS1)
Address
bit 15
000021H
14
13
12
11
10
9
BUSY INT INTE PAUS STS1 STS0 STRT
R/W R/W R/W R/W R/W R/W
W
8
Initial value
−
−
0000000X B
bit8
−
Undefined bit
The read value is always "1"
bit9
STRT
A/D conversion software start bit
0
Does not start A/D conversion
1
Starts A/D conversion
bit11 bit10
A/D conversion start trigger select bits
STS1 STS0
0
0 Starts by software
0
1 Starts by software or external trigger
1
0 Starts by software or internal timer
1
1 Starts by software, external trigger, or internal timer
bit12
PAUS
Pause flag bit
(Valid only when EI2OS or DMA is used)
When reading
0
1
When writing
A/D conversion not paused
Cleared to "0"
A/D conversion paused
Setup disabled
bit13
Interrupt request enable bit
INTE
Disables interrupt request
0
Enables interrupt request
1
bit14
INT
0
1
Interrupt request flag bit
When reading
When writing
A/D conversion uncompleted
Cleared to "0"
A/D conversion completed
Not affected
bit15
BUSY
R/W
W
−
X
: Readable/writable
: Write only
: Undefined
: Undefined value
: Initial value
CM44-10150-1E
0
1
A/D conversion operation flag bit
When reading
When writing
A/D conversion completed A/D conversion forcibly
(inactivated state)
terminated
A/D conversion being performed Not affected
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16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (1 / 3)
Bit name
bit15
BUSY:
A/D conversion
operation flag bit
Function
This bit forcibly terminates the 8-/10-bit A/D converter. When read, it indicates
whether the 8-/10-bit A/D converter is running or stopped.
When set to "0": Forcibly terminates the 8-/10-bit A/D converter.
When set to "1": Does not affect the operation.
When read: "1" is read if the 8-/10-bit A/D converter is running, while "0" is
read if the converter is stopped. "1" is also read when in "halt
state" in the stop conversion mode.
Notes:
•
•
•
•
"1" is read by the read-modify-write (RMW) instruction.
In the single conversion mode, this bit is cleared upon the completion of A/D
conversion.
In the continuous conversion and the stop conversion modes, this bit is not
cleared until stopped by writing "0".
Do not forcibly terminate A/D converter operation (BUSY=0) and start it (by
software (STRT = 1)/ external trigger/ timer) at the same time.
This bit indicates the generation of an interrupt request.
•
•
bit14
INT:
Interrupt request
flag bit
•
When A/D conversion is completed and the A/D conversion results are stored in the
A/D data register (ADCR), the INT bit is set to "1".
When interrupt requests are enabled (INTE = 1) and the interrupt request flag bit is set (INT
= 1), an interrupt request is generated.
This bit is cleared when "0" is written to it. Alternatively, it is automatically cleared
when the data transfer of the A/D conversion results is completed by EI2OS.
When set to "0": Cleared
When set to "1": Not affected
Note:
"1" is read by the read-modify-write (RMW) instruction.
This bit enables or disables the output of interrupt requests.
bit13
398
INTE:
Interrupt request
enable bit
When interrupt requests are enabled (INTE = 1) and the interrupt request flag
bit is set (INT = 1), an interrupt request is generated.
Note:
When transferring the A/D conversion results by EI2OS, always set the bit to
"1".
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (2 / 3)
Bit name
Function
The PAUS bit indicates that the A/D conversion data protection function has
been activated. The PAUS bit is valid only when the output of interrupt requests
is enabled (ADCS: INTE = 1).
When the A/D conversion data protection function is activated:
Set to "1"
When set to "0": Cleared to"0"
When set to "1": Set to"1"
•
bit12
PAUS:
Pause flag bit
•
•
When the output of interrupt requests is enabled (ADCS: INTE = 1) and A/D
conversion is performed, an interrupt request is generated upon setup of the interrupt
request flag bit (ADCS: INT) every time the A/D conversion session is completed. If
the next A/D conversion session is completed without clearing the interrupt request
flag bit (ADCS: INT) beforehand, the A/D conversion operation is paused to prevent
the previous data from being overwritten (A/D conversion data protection function).
When A/D conversion operation is paused, the PAUS bit is set to "1".
When the interrupt request flag bit (ADCS: INT) is cleared, the 8-/10-bit A/D
converter releases the pause status and restarts the A/D conversion operation.
The interrupt request flag bit (ADCS: INT) is cleared by writing "0". Alternatively,
when the A/D data register is set to transfer the A/D conversion results by EI2OS, the
interrupt request flag bit (ADCS: INT) is cleared by EI2OS upon the completion of
transfer of the A/D conversion results.
Notes:
•
•
CM44-10150-1E
For the A/D conversion data protection function, see Section "16.5.5 A/D
Conversion Data Protection Function".
Even when the pause status is released, the PAUS bit is not cleared automatically.
To clear the PAUS bit, write "0".
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (3 / 3)
Bit name
Function
These bits select the type of triggers used to start the 8-/10-bit A/D converter
(start trigger).
bit11,
bit10
STS1, STS0:
A/D conversion
start trigger select
bits
•
•
•
•
"00B": Starting by software
"01B": Starting by external pin trigger/software
"10B": Starting by 16-bit reload timer/software
"11B": Starting by external pin trigger/16-bit reload timer/software
Notes:
•
•
•
•
bit9
STRT:
A/D conversion
software start bit
This bit starts the 8-/10-bit A/D converter by software.
When set to "1": 8-/10-bit A/D converter starts.
• When A/D conversion operation is paused in the stop conversion mode, the
A/D conversion operation is restarted by writing "1" to the STRT bit.
When set to "0": Invalid. No changes
Notes:
•
•
•
bit8
400
Undefined bit
When external pin trigger is selected ("01B", "11B"):
A/D conversion starts when the falling edge is detected at the ADTG pin.
When 16-bit reload timer is selected (10B, 11B):
A/D conversion starts when the output of the 16-bit reload timer 1 becomes "1".
When more than one start triggers are selected (Other than STS1, STS0 = 00B):
the 8-/10-bit A/D converter is started by the first start trigger generated.
Change start trigger settings, when the operations of the peripheral functions
used to generate a start trigger are stopped (inactive trigger state).
•
•
"0" is read by the read-modify-write (RMW) instruction.
When read by an instructions other than read-modify-write (RMW) instructions,
"1" is read rather than the written value.
Do not forcibly terminate the 8-/10-bit A/D converter (BUSY = 0) and start it by
software (STRT = 1) at the same time.
When read: "1" is always read.
When write: Not affected.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
16.3.2
Lower Bits in the A/D Control Status Register
(ADCS0)
The lower bits in the A/D control status register enable the following settings:
• Selecting the A/D conversion mode
• Selecting the start and end channels of the A/D conversion
■ Lower Bits in the A/D Control Status Register (ADCS0)
Figure 16.3-3 Lower Bits in the A/D Control Status Register (ADCS0)
Address
bit 7
6
5
4
3
2
1
0
Reserved
000020H MD1 MD0 S10
−
−
−
−
R/W R/W R/W
−
−
−
− R/W
Initial value
000XXXX0B
bit0
Reserved bit
Always write "0"
Reserved
bit5
S10
0
1
R/W : Readable/writable
−
: Undefined
X : Undefined value
: Initial value
CM44-10150-1E
Resolution select bit
Sets the resolution of A/D conversion to 10 bits
Sets the resolution of A/D conversion to 8 bits
bit7 bit6
MD1 MD0
0
0
0
1
1
0
1
1
A/D conversion mode select bits
Single conversion mode 1
Single conversion mode 2
Continuous conversion mode
Stop conversion mode
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-3 Functions of Lower Bits in the A/D Control Status Register (ADCS0)
Bit name
Function
These bits set the A/D conversion mode.
For detailed information about how to use each mode, see Section "16.5
Explanation of 8-/10-bit A/D Converter Operations".
In single conversion modes 1 and 2:
•
•
•
A/D conversion is performed on the analog input from the start channel (ADSR:
ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) in succession.
The A/D conversion operation will stop when the A/D conversion for the end
channel is completed.
For the difference between single conversion modes 1 and 2, see Section "16.5
Explanation of 8-/10-bit A/D Converter Operations".
In continuous conversion mode:
•
bit7,
bit6
MD1, MD0:
A/D conversion mode
select bits
•
A/D conversion is performed on the analog input from the start channel (ADSR:
ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) in succession.
When the A/D conversion is completed for the end channel, the conversion
sequence returns to the analog input of the start channel to continue the A/D
conversion.
In stop conversion mode:
•
•
A/D conversion starts from the start channel (ADSR: ANS4 to ANS0). The A/D
conversion operation will stop every time the
A/D conversion for a channel is completed. If a start trigger is entered while the
A/D conversion operation is still stopped, A/D
conversion for the next channel will be performed.
The A/D conversion operation will stop when the A/D conversion for the end
channel is completed. If a start trigger is entered while the conversion operation
is still stopped, the conversion sequence will return to the analog input of the
start channel to continue the A/D conversion.
Note:
When changing the conversion mode, make sure that A/D conversion
has not already started (stop state).
bit5
402
S10:
Resolution select bit
This bit sets the resolution of A/D conversion.
When set to "0": Resolution of A/D conversion is set to A/D conversion
data bits D9 to D0 (10 bits)
When set to "1": Resolution of A/D conversion is set to A/D conversion
data bits D7 to D0 (8 bits)
Note:
When changing bit S10, make sure that A/D conversion has not already
started (stop state). If bit S10 is changed after the A/D conversion has
already started, the conversion results stored in the A/D conversion data
bits (D9 to D0) will become invalid.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
16.3.3
A/D Data Registers (ADCR0/ADCR1)
A/D data registers (ADCR0/ADCR1) are used to record the digital values
generated from the conversion results. While ADCR0 records the lower 8 bits of
the conversion results, ADCR1 records the highest 2 bits. Every time
conversion is completed, these registers are rewritten, and in general, store the
last conversion values.
■ A/D Data Registers (ADCR0/ADCR1)
Figure 16.3-4 A/D Data Registers (ADCR0/ADCR1)
Data register - upper bits
bit 15
Address
ADCR1 000023 H
−
−
14
13
12
11
10
9
8
Initial value
−
−
−
−
−
−
−
−
−
−
D9
D8
XXXXXX00B
R
R
Data register - lower bits
Address
ADCR0 000022H
bit 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
00000000B
R : Read only
X : Undefined value
− : Undefined
Table 16.3-4 Functions of A/D Data Registers (ADCR0/ADCR1)
Bit name
bit15
to
bit10
bit9
to
bit0
Undefined bits
D9 to D0:
A/D conversion data
bits
Function
When reading, "1" is always read.
These bits store A/D conversion results.
When resolution is set to 10 bits (S10 = 0):
Conversion data is stored in D9 to D0 (10 bits).
When resolution is set to 8 bits (S10 = 1):
Conversion data is stored in D7 to D0 (8 bits). Then, the read value of
D9, D8 becomes "1".
Notes:
•
•
CM44-10150-1E
Writing to these registers is prohibited.
To read the conversion results stored in the A/D conversion data bits (D9 to
D0), a word instruction (MOVW) must be used.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
A/D Setting Registers (ADSR0/ADSR1)
16.3.4
The A/D setting registers (ADSR0/ADSR1) enable the following settings:
• Setting A/D conversion times (sampling time and compare time)
• Setting sampling channels (start channel and end channel)
• Displaying the current sampling channels
■ A/D Setting Registers (ADSR0/ADSR1)
Figure 16.3-5 A/D Setting Registers (ADSR0/ADSR1)
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
404
φ
φ
φ
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CM44-10150-1E
CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-5 Functions of A/D Setting Registers (ADSR0/ADSR1) (1 / 2)
Bit name
bit15
to
bit13
ST2, ST1, ST0:
Sampling time
select bits
bit12
to
bit10
CT2, CT1, CT0:
Compare time
select bits
bit9
to
bit5
ANS4 to ANS0:
A/D conversion
start channel
select bits
CM44-10150-1E
Function
These bits set the sampling time for A/D conversion.
•
•
They set the time spent from start of A/D conversion to when the input analog voltage
is sampled and then held in the sample and hold circuit.
For information about the settings of these bits, see Table 16.3-6.
These bits set the compare time for A/D conversion.
•
•
They set the time spent from when A/D conversion is performed on the analog input
to when the results are stored in the data bits (D9 to D0).
For information about the settings of these bits, see Table 16.3-7.
These bits set the channel with which A/D conversion is started. When reading,
you can identify the channel number currently being converted when the A/D
conversion is in progress, and you can identify the last channel number on which
the A/D conversion was performed when the A/D conversion is completed or
stopped.
In addition, even when a particular value is set to these bits, the channel number
of the channel on which the A/D conversion was performed previously is read
rather than that set value until the A/D conversion starts. At a reset, the value is
initialized to "00000B".
Start channel < End channel:
A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS4 to ANS0) and ends at the channel set by the A/D
conversion end channel select bits (ANE4 to ANE0).
Start channel = End channel:
A/D conversion is performed for the only one channel that is set by the A/D
conversion start (= end) channel select bits (ANS4 to ANS0 = ANE4 to
ANE0).
Start channel > End channel:
A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS4 to ANS0) to AN23, and then another A/D
conversion starts up to the channel set by the A/D conversion end channel
select bits (ANE4 to ANE0).
In continuous conversion mode, stop conversion mode:
Once A/D conversion is completed at the channel set by the A/D conversion
end channel select bits (ANE4 to ANE0), the conversion sequence returns to
the channel set by A/D conversion start channel select bits (ANS4 to ANS0).
Read (in mode other than stop conversion mode):
The channel number of the channel (23 to 0) for which A/D conversion is
currently being performed is read.
Read (in stop conversion mode):
When a read is performed in the stop mode, the channel number of the last
channel for which A/D conversion was performed immediately before it was
stopped is read.
Note:
Do not set the A/D conversion start channel bits (ANS4 to ANS0) during
A/D conversion.
Use the word access method when writing to these bits. If a byte-access or bit
operation is performed, A/D conversion may start from an unintended
channel.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
Table 16.3-5 Functions of A/D Setting Registers (ADSR0/ADSR1) (2 / 2)
Bit name
bit3
to
bit0
ANE4 to ANE0:
A/D conversion
end channel
select bits
Function
These bits set the channel at which A/D conversion ends.
Start channel < End channel:
A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS4 to ANS0) and ends at the channel set by the A/D
conversion end channel select bits (ANE4 to ANE0).
Start channel = End channel:
A/D conversion is performed for the only one channel that is set by the A/D
conversion start (= end) channel select bits (ANS4 to ANS0 =
ANE4 to ANE0).
Start channel > End channel:
A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS4 to ANS0) to AN23, and then another A/D
conversion starts up to the channel set by the A/D conversion end channel
select bits (ANE4 to ANE0).
In continuous conversion mode, stop conversion mode:
Once A/D conversion is completed at the channel set by the A/D conversion
end channel select bits (ANE4 to ANE0), the conversion sequence returns to
the channel set by A/D conversion start channel select bits (ANS4 to ANS0).
Notes:
•
•
406
Do not set the A/D conversion end channel bits (ANE4 to ANE0) during A/D
conversion.
Do not use a read-modify-write (RMW) instruction to set the sampling time select
bits (ST2, ST1 and ST0), the compare time select bits (CT2, CT1 and CT0), or the
A/D conversion end channel select bits (ANE4, ANE3, ANE2, ANE1 and ANE0)
after setting the A/D conversion start channel select bits (ANS4, ANS3, ANS2,
ANS1 and ANS0). As the previously converted channel is read by bits ANS4,
ANS3, ANS2, ANS1 and ANS0 until A/D conversion operation starts, the bit
values of ANS4, ANS3, ANS2, ANS1 and ANS0 may be rewritten when a readmodify-write (RMW) instruction is used to set bits ST2, ST1, ST0, bits CT2, CT1,
CT0, and bits ANE4, ANE3, ANE2, ANE1, ANE0 after bits ANS4, ANS3,
ANS2, ANS1 and ANS0 are set.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
MB90930 Series
■ Setup for Sampling Time (Bits ST2 to ST0)
Table 16.3-6 Correlation between Bit ST2 to ST0 and Sampling Times
ST2
ST1
ST0
Sampling time setting
Example setting
(φ: Internal operating frequency)
0
0
0
4 machine cycles
φ = 8MHz: 0.5μs
0
0
1
6 machine cycles
φ = 8MHz: 0.75μs
0
1
0
8 machine cycles
φ = 16MHz: 0.5μs
0
1
1
12 machine cycles
φ = 24MHz: 0.5μs
1
0
0
24 machine cycles
φ = 8MHz: 3 μs
1
0
1
36 machine cycles
φ = 16MHz: 2.25μs
1
1
0
48 machine cycles
φ = 16MHz: 3.0 μs
1
1
1
128 machine cycles
φ = 32MHz: 4.0μs
The sampling time must be set in accordance with the drive impedance (Rext), which is
connected to the analog input. The conversion accuracy is not guaranteed unless the following
conditions are satisfied:
• Rext ≤ 1.5kΩ:
• 4.5V ≤ AVCC < 5.5V: Set the sampling time to 0.5μs or higher.
• 4.0V ≤ AVCC < 4.5V: Set the sampling time to 1.2μs or higher.
• Rext > 1.5kΩ: Set the sampling time to Tsamp shown in the following expression, or higher.
• 4.5V ≤ AVCC < 5.5V: Tsamp = (2.52kΩ + Rext) × 10.7pF × 7
• 4.0V ≤ AVCC < 4.5V: Tsamp = (13.6kΩ + Rext) × 10.7pF × 7
■ Setup for Compare Time (Bits CT2 to CT0)
Table 16.3-7 Correlation between Bits CT2 to CT0 and Compare Times
Compare time setting
Example setting
(φ: Internal operating frequency)
0
22 machine cycles
φ = 20MHz: 1.1μs
0
1
33 machine cycles
φ = 32MHz: 1.03μs
0
1
0
44 machine cycles
φ = 32MHz: 1.375μs
0
1
1
66 machine cycles
φ = 32MHz: 2.063μs
1
0
0
88 machine cycles
φ = 8MHz: 11.0 μs
1
0
1
132 machine cycles
φ = 16MHz: 8.25μs
1
1
0
176 machine cycles
φ = 20MHz: 8.8μs
1
1
1
264 machine cycles
φ = 32MHz: 8.25μs
CT2
CT1
CT0
0
0
0
The compare time must be set in accordance with the analog power supply voltage (AVCC).
The conversion accuracy is not guaranteed unless the following conditions are satisfied:
• 4.5V ≤ AVCC < 5.5 V: Set the compare time to 1.00μs or higher.
• 4.0V ≤ AVCC < 4.5 V: Set the compare time to 2.00μs or higher.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
16.3.5
MB90930 Series
Analog Input Enable Registers (ADER6,7,8)
These registers enable or disable the analog input pins used for the 8-/10-bit A/D
converter.
■ Analog Input Enable Registers (ADER6,7,8)
Figure 16.3-6 Analog Input Enable Registers (ADER6,7,8)
Table 16.3-8 Function of Port 6 Analog Input Enable Registers (ADER6, 7, 8)
Bit name
Function
bit15
to
bit8
ADE23 to ADE16:
Analog input enable
bits
These bits enable or disable analog input from A/D conversion analog input
pins (AN23 to AN16), located on port 8.
When set to "0": Analog input disabled
When set to "1": Analog input enabled
bit15
to
bit8
ADE15 to ADE8:
Analog input enable
bits
These bits enable or disable analog input from A/D conversion analog input
pins (AN15 to AN8), located on port 7.
When set to "0": Analog input disabled
When set to "1": Analog input enabled
bit7
to
bit0
ADE7 to ADE0:
Analog input enable
bits
These bits enable or disable analog input from A/D conversion analog input
pins (AN7 to AN0), located on port 6.
When set to "0": Analog input disabled
When set to "1": Analog input enabled
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.3 Configuration of 8-/10-bit A/D Converter
Notes:
• To use t he r egister as an analog inp ut pin, wr ite "1" t o th e bit s in the analog inp ut
enable register (ADER6, 7, 8) corresponding to the pin to be used in order to set it as
analog input.
• Setting the analog input pin as ADEx = 0 is prohibited. The pin must always be set as
ADEx = 1.
• Each analog input pin is also used as a general-purpose I/O port and input/output of a
peripheral function. When set as ADEx = 1, the pin is forced to become an analog input
pin regardless of the settings of the port direct ion register (DDR6, 7, 8) and I/O settings
of peripheral functions, therefore it cannot be used otherwise.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.4 Interrupts of 8-/10-bit A/D Converter
16.4
MB90930 Series
Interrupts of 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, an interrupt request is generated when the
conversion results are stored in the A/D data register (ADCR) upon the
completion of A/D conversion. The extended intelligent I/O service (EI2OS) can
be used.
■ Interrupts of A/D Converter
When the A/D conversion results are stored in the A/D data register (ADCR) upon the
completion of A/D conversion of analog input voltage, the interrupt request flag bit in the A/D
control status register (ADCS: INT) is set to "1". An interrupt request is generated when the
output of interrupt requests is enabled
(ADCS: INTE = 1) and the interrupt request flag bit is set (ADCS: INT = 1).
■ Interrupts and EI2OS of 8-/10-bit A/D Converter
Reference:
For information about the interrupt number, interrupt control register, and interrupt vector
address, see "CHAPTER 3 INTERRUPTS".
■ EI2OS of 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, EI2OS can be used to transfer the A/D conversion results from
the A/D data register (ADCR) to memory. For information about how to use the EI2OS
functions, see Section "16.5.4 Conversion Operation by EI2OS Function" as well as Section
"16.5.5 A/D Conversion Data Protection Function".
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
16.5
Explanation of 8-/10-bit A/D Converter Operations
The 8-/10-bit A/D converter performs A/D conversion operation in the following
conversion modes. Each mode is specified by setting the A/D conversion mode
select bits in the A/D control status register (ADCS: MD1, MD0):
• Single conversion mode
• Continuous conversion mode
• Stop conversion mode
■ Single Conversion Mode (ADCS: MD1, MD0 = 00B or 01B)
• When a start trigger is entered, A/D conversion is performed on the analog input from the
start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) in
succession.
• The A/D conversion operation will stop when the A/D conversion for the end channel is
completed.
Notes:
• In single conversion mode1 (ADCS: MD1, MD0 = 00B), the 8-/10-bit A/D converter may
be restarted when a start trigger is entered while A/D conversion is being performed or
paused*. T herefore, do n ot e nter th e st art tr igger wh ile A/D co nversion is being
performed or paused.
In single conversion mode2 (ADCS: MD1, MD0 = 0 1B), the 8-/10-bit A/D converter is
not r estarted even whe n a st art t rigger is e ntered while A/D conversion is b eing
performed or paused*.
• When restarting the converter in single conversion mode 1 or 2, follow the procedure
shown Section "16.5.1 Single Conversion Mode".
*: In pause state, the A/D conversion protection function operates, and the conversion is
temporarily stopped. For more information, see Section "16.5.5 A/D Conversion Data
Protection Function".
■ Continuous Conversion Mode (ADCS: MD1, MD0 = 10B)
• When a start trigger is entered, A/D conversion is performed on the analog input from the
start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) in
succession.
• When the A/D conversion is completed for the end channel, the conversion sequence
returns to the analog input of the start channel to continue the A/D conversion.
■ Stop Conversion Mode (ADCS: MD1, MD0 = 11B)
• When a start trigger is entered, A/D conversion starts at the start channel (ADSR: ANS4 to
ANS0). The A/D conversion operation will stop every time the A/D conversion for a
channel is completed. This state is called "pause state". If a start trigger is entered while the
A/D conversion operation is still stopped,
A/D conversion for the next channel will be performed.
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16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
• The A/D conversion operation will stop when the A/D conversion for the end channel is
completed. If a start trigger is entered while the conversion operation is still stopped, the
conversion sequence will return to the analog input of the start channel to continue the A/D
conversion.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
16.5.1
Single Conversion Mode
In single conversion mode, A/D conversion is performed sequentially from the
start channel to the end channel. The A/D conversion operation will stop when
the A/D conversion for the end channel is completed.
■ Setup for Single Conversion Mode
To operate the 8-/10-bit A/D converter in the single conversion mode, the settings described in
Figure 16.5-1 are required.
Figure 16.5-1 Setup for Single Conversion Mode
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
■ Operations and Applications of Single Conversion Mode
• When a start trigger is entered, an A/D conversion starts from the channel set by the A/D
conversion start channel select bits (ANS4 to ANS0), and continues through to the channel
set by the A/D conversion end channel select bits (ANE4 to ANE0).
• When the A/D conversion is completed for the channel set by the A/D conversion end
channel select bits (ANE4 to ANE0), the A/D conversion operation is stopped.
•
To force the termination of an A/D conversion, write "0" to the A/D conversion operation
flag bit in the A/D control status register (ADCS: BUSY).
[When the start channel and end channel are the same]
When the channel number of the start and end channels are set to the same number (ADSR: ANS4
to ANS0 = ADSR: ANE4 to ANE0), A/D conversion is terminated after performing
conversion for only one channel once, which is specified as the start channel (= end
channel).
[Conversion sequence in single conversion mode]
Table 16.5-1 shows examples of the conversion sequence in single conversion mode.
Table 16.5-1 Conversion Sequence in Single Conversion Mode
Start channel
End channel
Conversion sequence in single
conversion mode
Pin AN3
Pin AN0
AN0 −> AN1 −> AN2 −> AN3 −>
(ADSR: ANS4 to ANS0 = 00000B) (ADSR: ANE4 to ANE0 = 00011B) Terminated
AN5 −> AN6 −> AN7 −> AN8 −> …
Pin AN2
Pin AN5
AN30 −> AN31 −> AN0 −> AN1 −>
(ADSR: ANS4 to ANS0 = 00101B) (ADSR: ANE4 to ANE0 = 00010B)
AN2 −> Terminated
Pin AN3
Pin AN3
AN3 −> Terminated
(ADSR: ANS4 to ANS0 = 00011B) (ADSR: ANE4 to ANE0 = 00011B)
Note: Start channel > End channel:
Starts sampling on the channels that do not have any analog input pin (AN24 to AN31), therefore, we
do not recommend this setting.
[Restart]
If you want to restart the A/D conversion while the A/D conversion is in execution or pause
state, the conversion is required to forcibly terminate before restarting. Follow the procedure
below:
1) Clear the A/D conversion operation flag bit (ADCS: BUSY)
2) Clear the interrupt request flag bit (ADCS: INT)
3) Set the A/D conversion software start bit (ADCS: STRT)
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
16.5.2
Continuous Conversion Mode
In continuous conversion mode, A/D conversion is performed sequentially from
the start channel to the end channel. When the A/D conversion for the end
channel is completed, the conversion sequence returns to the start channel to
continue the A/D conversion operation.
■ Setup for Continuous Conversion Mode
To operate the 8-/10-bit A/D converter in the continuous conversion mode, the settings
described in Figure 16.5-2 are required.
Figure 16.5-2 Setup for Continuous Conversion Mode
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16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
■ Operations and Applications of Continuous Conversion Mode
• When a start trigger is entered, an A/D conversion starts from the channel set by the A/D
conversion start channel select bits (ANS4 to ANS0), and continues through to the channel
set by the A/D conversion end channel select bits (ANE4 to ANE0).
• When the A/D conversion is completed for the channel set by the A/D conversion end
channel select bits (ANE4 to ANE0), the conversion sequence returns to the channel set by
the A/D conversion start channel select bits (ANS4 to ANS0) to continue the A/D
conversion.
•
To force the termination of an A/D conversion, write "0" to the A/D conversion operation
flag bit in the A/D control status register (ADCS: BUSY).
[When the start channel and end channel are the same]
When the start channel is set to the same channel as the end channel (ADSR: ANS4 to
ANS0 = ADSR: ANE4 to ANE0), A/D conversion is performed at the one channel set as the
start channel (= end channel) repeatedly.
[Conversion sequence in continuous conversion mode]
Table 16.5-2 shows examples of the conversion sequence in continuous conversion mode.
Table 16.5-2 Conversion Sequence in Continuous Conversion Mode
Start channel
End channel
Conversion sequence in
continuous conversion mode
Pin AN3
Pin AN0
AN0 −> AN1 −> AN2 −> AN3 −>
(ADSR: ANS4 to ANS0 = 00000B) (ADSR: ANE4 to ANE0 = 00011B) AN0 −> Repeat
AN5 −> AN6 −> AN7 −> AN8 −> …
Pin AN2
Pin AN5
AN30 −> AN31 −> AN0 −> AN1 −>
(ADSR: ANS4 to ANS0 = 00101B) (ADSR: ANE4 to ANE0 = 00010B)
AN2 −> AN5 −> Repeat
Pin AN3
Pin AN3
AN3 −> AN3 −> Repeat
(ADSR: ANS4 to ANS0 = 00011B) (ADSR: ANE4 to ANE0 = 00011B)
Note: Start channel > End channel:
Starts sampling on the channels that do not have any analog input pin (AN24 to AN31), therefore, we do
not recommend this setting.
[Restart]
If you want to restart the A/D conversion while the A/D conversion is in execution or pause
state, the conversion is required to forcibly terminate before restarting. Follow the procedure
below:
1) Clear the A/D conversion operation flag bit (ADCS: BUSY)
2) Clear the interrupt request flag bit (ADCS: INT)
3) Set the A/D conversion software start bit (ADCS: STRT)
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16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
16.5.3
Stop Conversion Mode
In the stop conversion mode, A/D conversion is performed by repeatedly
stopping and starting at each channel. The A/D conversion sequence returns to
the start channel to continue the A/D conversion, when a start trigger is
entered after the A/D conversion is completed for the end channel and the A/D
conversion operation is stopped.
■ Setup for Stop Conversion Mode
To operate the 8-/10-bit A/D converter in the stop conversion mode, the settings described in
Figure 16.5-3 are required.
Figure 16.5-3 Setup for Stop Conversion Mode
■ Operations and Applications of Stop Conversion Mode
• When a start trigger is entered, A/D conversion starts from the channel set by the A/D
conversion start channel select bits (ANS4 to ANS0). The A/D conversion operation will
stop every time the A/D conversion for a channel is completed. When the start trigger is
entered while the A/D conversion operation is stopped, A/D conversion is performed for the
next channel.
• When the A/D conversion is completed for the channel set by the A/D conversion end
channel select bits (ANE4 to ANE0), the A/D conversion operation is stopped. When the
start trigger is entered while the A/D conversion operation is stopped, the conversion
sequence returns to the channel set by the A/D conversion start channel select bits (ANS4 to
ANS0) to continue the A/D conversion.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
• To force the termination of an A/D conversion, write "0" to the A/D conversion operation
flag bit in the A/D control status register (ADCS: BUSY).
[When the start channel and end channel are the same]
When the start channel is set to the same channel as the end channel (ADSR: ANS4 to
ANS0 = ADSR: ANE4 to ANE0), A/D conversion is performed and then stopped repeatedly
at the only one channel specified as the start channel (= end channel).
[Conversion sequence in stop conversion mode]
Table 16.5-3 shows example conversion sequences for the stop conversion mode.
Table 16.5-3 Conversion Sequence in Stop Conversion Mode
Start channel
End channel
Conversion sequence in stop conversion
mode
Pin AN0
(ADSR: ANS4 to ANS0 =
00000B)
Pin AN3
(ADSR:ANE4 to ANE0 =
00011B)
AN0 −> Stop/Start −> AN1 −> Stop/Start −> AN2 −>
Stop/Start −> AN3 −> Stop/Start −> AN0 −> Repeat
Pin AN5
(ADSR: ANS4 to ANS0 =
00101B)
Pin AN2
(ADSR: ANE4 to ANE0 =
00010B)
AN5 −> Stop/Start −> AN6 −> Stop/Start −> AN7 −>
Stop/Start −> AN8 −> Stop/Start −>…
AN30 −> Stop/Start −> AN31 −> Stop/Start −>
AN0 −> Stop/Start −> AN1 −> Stop/Start −> AN2 −>
Stop/Start −> AN5 −> Repeat*
Pin AN3
(ADSR: ANS4 to ANS0 =
00011B)
Pin AN3
(ADSR: ANE4 to ANE0 =
00011B)
AN3 −> Stop/Start −> AN3 −> Stop/Start −> Repeat
Note: Start channel > End channel:
Starts sampling on the channels that do not have any analog input pin (AN24 to AN31), therefore, we
do not recommend this setting.
[Restart]
If you want to restart the A/D conversion while the A/D conversion is in execution or pause
state, the conversion is required to forcibly terminate before restarting. Follow the procedure
below:
1) Clear the A/D conversion operation flag bit (ADCS: BUSY)
2) Clear the interrupt request flag bit (ADCS: INT)
3) Set the A/D conversion software start bit (ADCS: STRT)
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16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
16.5.4
Conversion Operation by EI2OS Function
In the 8-/10-bit A/D converter, the EI2OS function can be used to transfer the
A/D conversion results to the memory.
■ Conversion Operation by EI2OS Function
Figure 16.5-4 shows the flow of the conversion operation when the EI2OS function is used.
Figure 16.5-4 Conversion Operation Flow When EI2OS Function is Used
A/D converter starts
Sample & hold
A/D conversion starts
A/D conversion ends
Interrupt occurs
EI2OS starts
Conversion results transferred
Specified
number of sessions
completed?*
NO
Interrupt cleared
YES
Interrupt processed
*: Determined by EI2OS settings
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
16.5.5
MB90930 Series
A/D Conversion Data Protection Function
The data protection function is activated when A/D conversion is performed
while the output of interrupt requests is enabled.
■ Explanation of A/D Conversion Data Protection Function in 8-/10-bit A/D
Converter
The A/D conversion data protection function prevents A/D conversion data from being
unretrieved.
The 8-/10-bit A/D converter has one A/D data register (ADCR1/ADCR0) for storing conversion
data and one successive approximation circuit for storing the data on which A/D conversion is
currently being performed. During the A/D conversion, the 8-/10-bit A/D converter stores the
conversion data for each bit separately in the successive approximation circuit. Once the A/D
conversion is completed, the A/D conversion results are stored in the A/D data register.
Depending on whether or not to use the A/D conversion data protection function, the 8-/10-bit
A/D converter operates differently, as described below.
• If you set the interrupt request enable bit (ADCS: INTE) to "0", the data protection function
is disabled. In this case, when A/D conversions are performed successively, the conversion
results are stored in the A/D data register every time the 8-/10-bit A/D converter completes
each conversion (Consequently, the latest conversion data is always stored).
• If you set the interrupt request enable bit (ADCS: INTE) to "1", the data protection function
is enabled. When A/D conversions are performed successively in this state, the interrupt
request flag bit becomes "1" (ADCS: INT = 1) upon the completion of the first conversion
session. If the next A/D conversion is performed and completed while INT = 1, the 8-/10-bit
A/D converter enters to the "pause state" just before the conversion results are transferred
from the successive approximation circuit to the A/D data register, preventing the
conversion data from being overwritten. At this point, "1" is set to the pause flag bit in the
A/D control status register (ADCS: PAUS). If you clear the interrupt request flag bit
(ADCS: INT) to "0" in the pause state, the data stored in the successive approximation
circuit is transferred to the A/D data register (see Figure 16.5-5).
Figure 16.5-5 Operation of A/D Conversion Data Protection Function
A/D (1) conversion time
Sampling time
Compare time
A/D (2) conversion time
Sampling time
A/D conversion data
protection function
in operation
A/D (3)
conversion time
Compare time
A/D conversion data register: ADCR
A/D conversion interrupt
(INT bit)
INT=0 INT=1
A/D conversion data protection
function (PAUS bit)
420
INT cleared
PAUS=0 PAUS=1
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
● A/D conversion data protection function when reading the A/D conversion results by CPU
• When the A/D conversion results are stored in the A/D data register (ADCR) after A/D
conversion is performed on analog input, "1" is set to the interrupt request flag bit in the A/D
control status register (ADCS: INT).
• When the next A/D conversion session is completed, if the interrupt request flag bit (ADCS:
INT), which was set upon the completion of the previous A/D conversion session, is still
set, and interrupt requests are enabled (ADCS: INTE = 1), the A/D conversion operation
will be paused just before the new data overwrites the current data in the A/D data register
in order to protect the data.
• As the output of interrupt requests is enabled by the A/D control status register (ADCS:
INTE = 1), an interrupt request is generated when the INT bit is set. When the INT bit is cleared,
the A/D conversion operation is released from the pause.
• When performing A/D conversion sessions successively, the 8-/10-bit A/D converter starts
the next conversion session. At this point, the pause flag bit (ADCS: PAUS) is not cleared
to "0" automatically. To clear, you must write "0" to this bit.
Notes:
• If the output of interrupt requests is disabled during the pause state (ADCS: INTE =
0), A/D conversion may start, causing the data in the A/D data register to be rewritten.
• When performing multiple A/D conversion sessions successively, always read the data
stored in the A/ D da ta r egister b efore clea ring the interrupt r equest f lag bit ( ADCS:
INT). If the interrupt request flag bit (ADCS: INT) is cleared before the data stored in
the A/D data register is re ad while t he A/D conversion is paused, t he fi rstly-stored
conversion data will be o
verwritten b y th e ne xt c onversion data and therefore
destroyed.
● A/D conversion data protection function when transferring the A/D conversion results by
EI2OS
If the next A/D conversion session is completed while the EI2OS function is used to transfer
the A/D conversion result from the A/D data register to the memory, the A/D conversion
operation is paused just before the new data overwrites the current data in the A/D data register
for data protection purposes. When the A/D conversion operation stops, the pause flag bit of
the A/D control status register (ADCS: PAUS) is set to "1".
Once the transfer of the A/D conversion results to the memory is completed using the EI2OS
function, the A/D conversion is released from the pause state. When performing A/D
conversion sessions successively, the A/D conversion operation is resumed. At this point, the
pause flag bit (ADCS: PAUS) is not cleared to "0" automatically. To clear, you must write "0"
to the PAUS bit.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
Notes:
• Do not clear the interrupt request flag bit from CPU (ADCS: INT = 0), when the EI2OS
function is used to transfer the A/D conversion results to the memory, or the data in the
A/D data register, which is being transferred, may be rewritten.
• Do not disab le the out put of interr upt requests, when the EI 2OS funct ion is used to
transfer the A/D conversion results to the memory. If th e output of interrupt requests is
disabled during the pause state (ADCS: INTE = 0) , A/D conversion may start, causing
the data in the A/D data register, which is currently being transferred, to be rewritten.
• Do not restart while the EI2OS function is used to transfer the A/D conversion results to
the memo ry. I f re started while the A/D conversion is pa used, th e co nversion results
may be destroyed.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.5 Explanation of 8-/10-bit A/D Converter Operations
MB90930 Series
● Processing flow of A/D conversion data protection function when EI2OS is used
Figure 16.5-6 shows the processing flow of the A/D conversion data protection function when
EI2OS is used.
Figure 16.5-6 Processing Flow of A/D Conversion Data Protection Function When EI2OS is
Used
EI2OS setup
Continuous A/D
conversion starts
1st conversion completed
Store to A/D data register
EI2OS starts
2nd conversion completed
EI2OS terminated
NO
A/D paused
YES
Store to A/D data register
3rd conversion
EI2OS starts
Continues
All conversions completed
EI2OS terminated
NO
A/D paused
YES
EI2OS starts
Interrupt processing
A/D conversion stopped
Completed
Note: The flow for when the A/D converter operation is stopped is omitted.
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CHAPTER 16 8-/10-BIT A/D CONVERTER
16.6 Precautions when Using 8-/10-bit A/D Converter
16.6
MB90930 Series
Precautions when Using 8-/10-bit A/D Converter
Precautions must be taken for the following points when using the 8-/10-bit A/D
converter.
■ Precautions When Using 8-/10-bit A/D Converter
● Analog input pins
• The analog input pins are also used as general-purpose I/O ports for port 6, 7 and 8. When
using them as analog input pins, set up the analog input enable register (ADER6, ADER7
and ADER8) to switch them to analog input pins.
• When using the pin as analog input pin, write "1" to the bit in the analog input enable
register (ADER6, ADER7 and ADER8) which corresponds to the pin to be used in order to
enable the analog input.
• If a medium-level signal is input while the pin remains set as a general-purpose I/O port,
input leakage current is flowed to the gate. When using it as an analog input pin, always
enable the analog input before use.
● Precaution when using the internal timer or external trigger to start the converter
When setting the A/D start trigger select bits of the A/D control status register (ADCS: STS1 and
STS0) to start the 8-/10-bit A/D converter by internal timer output or external trigger, set the
level of the timer output and the external trigger to the inactive side ("H" side for the external
trigger). If the input value of the start trigger is set to the active side, the operation may start as
soon as the A/D start trigger select bits of the A/D control status register (ADCS: STS1 and
STS0) are set.
● Power application and analog input sequence of the 8-/10-bit A/D converter
• Always apply power to the 8-/10-bit A/D converter and analog inputs after the digital power
supply (VCC) is turned on.
• When power-off, turn off the 8-/10-bit A/D converter and the analog inputs before turning
off the digital power supply.
• Do not allow AVRH to exceed AVCC when turning on and off the power.
● Power supply voltage of the 8-/10-bit A/D converter
Care must be taken to ensure that the power supply of the 8-/10-bit A/D converter (AVCC) does
not exceed the digital power supply (VCC) voltage to prevent latch-up.
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CHAPTER 17
LIN-UART
This chapter explains the functions and
operations of the LIN-UART.
17.1 Overview of LIN-UART
17.2 Configuration of LIN-UART
17.3 Pins of LIN-UART
17.4 LIN-UART Registers
17.5 Interrupts of LIN-UART
17.6 LIN-UART Baud Rates
17.7 Operation of LIN-UART
17.8 Notes on Using LIN-UART
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CHAPTER 17 LIN-UART
17.1 Overview of LIN-UART
17.1
MB90930 Series
Overview of LIN-UART
The LIN (Local Interconnect Network)-UART is a general-purpose serial data
communication interface for performing synchronous or asynchronous
communication (start-stop synchronization) with external devices. LIN-UART
provides bidirectional communication function (normal mode), master-slave
communication function (multiprocessor mode in master/slave systems), and
special features for LIN bus systems.
■ Functions of LIN-UART
● Functions of LIN-UART
LIN-UART is a general-purpose serial data communication interface for transmitting serial
data to and receiving data from another CPU and peripheral devices. It has the functions listed
in Table 17.1-1.
Table 17.1-1 Functions of LIN-UART (1 / 2)
Function
Data buffer
Full-duplicate double-buffer
Serial input
Perform oversampling 5 times and determine the received value by majority
decision of sampling value (asynchronous mode only)
Transfer mode
• Clock synchronous (selecting start/stop synchronous or start/stop bit)
• Clock asynchronous (start/stop bits can be used.)
Baud rate
• Dedicated baud rate generator (The baud rate is consisted of 15-bit reload
counter.)
• An external clock can be inputted and also be adjusted by reload counter.
Data length
• 7 bits (other than synchronous or LIN mode)
• 8 bits
Signaling
NRZ (non return to zero)
Start bit timing
Synchronization to the falling edge of the start bit in the asynchronous mode
Detection of receive error
• Framing error
• Overrun error
• Parity error (not supported for operation mode 1)
Interrupt request
• Receive interrupt (receive termination, detection of receive error, LIN synch
break detection)
• Transmit interrupt (transmit data empty)
• Interrupt request to ICU (LIN synch field detection: LSYN)
• Both the transmission and reception support the extended intelligent I/O
service (EI2OS) (except UART3)
Master/Slave type
communication function
(multiprocessor mode)
This function enables communication between 1 (only use master) and n (slave)
(This function supports both of master and slave system.)
Synchronous mode
Master or slave function
Pin access
Capable of reading the state of serial I/O pin directly
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CHAPTER 17 LIN-UART
17.1 Overview of LIN-UART
MB90930 Series
Table 17.1-1 Functions of LIN-UART (2 / 2)
Function
•
•
•
•
•
LIN bus option
Master device operation
Slave device operation
LIN synch break detection
LIN synch break generation
Detection of start/stop edges in LIN synch field connected to input capture 0,
1, 6, and 7
Synchronous serial clock
Synchronous serial clock can be continuously outputted to SCK pin for
synchronous communication with start/stop bits.
Clock delay option
Special synchronous clock mode for delaying clock (enabled to SPI)
The LIN-UART operates in four different modes, which are determined by the MD0 and the
MD1 bits of the LIN-UART serial mode register (SMR). Mode 0 and 2 are used for
bidirectional serial communication, mode 1 for master/slave communication and mode 3 for
LIN master/slave communication.
Table 17.1-2 LIN-UART Operation Modes
Data length
Operation mode
Without Parity
0
Normal mode
1
Multi processor
mode
2
Normal mode
3
LIN mode
With Parity
7 bits or 8 bits
7 bits or 8 bits+1
*
Stop bit
length
Data bit format
Asynchronous
-
8 bits
8 bits
Synchronous
method
-
1 bit or
2 bits
Asynchronous
Synchronous
None,
1 bit, 2 bits
Asynchronous
1 bit
LSB first
MSB first
LSB first
- : Setting disabled
* : +1 is the address/data select bit (AD) used for controlling communication in multiprocessor mode.
The MD1 and MD0 bits of the LIN-UART serial mode register (SMR) determine the operation
mode of LIN-UART as shown in the following table:
Table 17.1-3 LIN-UART Operation Modes
MD1
MD0
Mode
Type
0
0
1
1
0
1
0
1
0
1
2
3
Asynchronous (normal mode)
Asynchronous (multiprocessor mode)
Synchronous (normal mode)
Asynchronous (LIN mode)
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CHAPTER 17 LIN-UART
17.1 Overview of LIN-UART
MB90930 Series
Notes:
• Mode 1 o peration is sup ported both for master and slave operation of LIN-UART in a
master/slave connection system.
• In Mo de 3, t he L IN-UART f unction is fixed t o the communication format 8N1-Format,
LSB first.
• If the mode is changed, LIN-UART cuts off all possible transmission or reception and
awaits then new action.
■ LIN-UART Interrupt and EI2OS
Interrupt control register
Channel
Vector table address
EI2OS
Interrupt No.
Register name
Address
Lower
Upper
Bank
LIN-UART0 reception
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
LIN-UART0 transmission
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
LIN-UART1 reception
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
*1
LIN-UART1 transmission
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
*2
LIN-UART2 reception
#35(23H)
ICR12
0000BCH
FFFF70H
FFFF71H
FFFF72H
*1
LIN-UART2 transmission
#36(24H)
ICR12
0000BCH
FFFF6CH
FFFF6DH
FFFF6EH
*2
LIN-UART3 reception
#24(18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
*3
LIN-UART3 transmission
#26(1AH)
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
*2
*1: EI2OS can only be used when the interrupt source that shares ICR12 to ICR14, and the interrupt vector is not used.
Reception error can be detected. EI2OS stop function is available.
*2: EI2OS can only be used when the interrupt source that shares ICR07, ICR13, ICR14, and the interrupt vector is not used.
*3: EI2OS can only be used when the interrupt source that shares ICR06 and the interrupt vector is not used. Reception error
can be detected. EI2OS stop function is available.
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17.2
Configuration of LIN-UART
CHAPTER 17 LIN-UART
17.2 Configuration of LIN-UART
This section briefly outlines the blocks of the LIN-UART.
■ LIN-UART Consists of the Following Blocks
• Reload counter
• Reception control circuit
• Reception shift register
• Reception data register (RDR)
• Transmission control circuit
• Transmission shift register
• Transmission data register (TDR)
• Error detection circuit
• Oversampling circuit
• Interrupt generation circuit
• LIN synch Break/synch field detection circuit
• Bus idle detection circuit
• LIN-UART serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Extended communication control register (ECCR)
• Extended status control register (ESCR)
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CHAPTER 17 LIN-UART
17.2 Configuration of LIN-UART
MB90930 Series
■ Block Diagram of LIN-UART
Figure 17.2-1 Block Diagram of LIN-UART
OTO,
EXT,
REST
CLK
PE
Transmission clock
Reload
counter
SCKn
Reception clock
Start bit
Restart reception
reload counter
Oversampling
circuit
Received
bit counter
Transmission
bit counter
Received
parity counter
Transmission
parity counter
Reception
IRQ
Transmission
IRQ
TDRE
SOTn
Pin
RDRF
Internal
signal to
capture
SOTn
SINn
LIN break/
Synch field
detection
circuit
To E I2OS
SINn
Transmission
shift register
Reception
shift register
Error
detection
PE
ORE
FRE
TIE
RIE
LBIE
LBD
RBI
TBI
Transmission
start circuit
detection
circuit
Pin
Programming
generation
circuit
Transmission
control circuit
Reception
control circuit
Pin
SINn
ORE FRE
Transmission start
LIN break
generation
circuit
Bus idle detec- LBR
LBL1
tion circuit
LBL0
RDRn
TDRn
RBI
LBD
TBI
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSRn
Register
MD1
MD0
OTO
EXT
REST
UPCL
USCKE
USOE
SMRn
Register
PEN
P
SBL
CL
AD
CRE
RXE
TXE
SCRn
Register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
LBR
MS
ESCRn SCDE
Register SSM
ECCRn
Register
RBI
TBI
n = 0, 1, 2, 3
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CHAPTER 17 LIN-UART
17.2 Configuration of LIN-UART
MB90930 Series
■ Explanation of the Blocks
● Reload counter
15-bit reload counter that functions as the dedicated baud rate generator. The reload counter
consists of a
15-bit register for the reload value. It generates the transmitting and receiving clocks with the
external clock or the internal clock. The count value of the transmission reload counter can be
read via the BGRn1/BGRn0.
● Reception control circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and
received parity counter. The received bit counter counts reception data bits. When reception of
one data item for the specified data length is completed, the received bit counter sets the flag in
the LIN-UART reception data register. In this case, if the reception interrupt is enabled, the
reception interrupt request is generated. The start bit detection circuit detects start bits from the
serial input signal and sends a signal to the reload counter to synchronize it to the falling edge
of these start bits. The received parity counter calculates the parity of the reception data.
● Reception shift register
The reception shift register fetches reception data input from the SINn pin, shifting the data bit
by bit. When reception is completed, the reception shift register transfers receive data to the
RDR register.
● Reception data register (RDR)
This register retains reception data. Serial input data is converted and stored in this register.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start
circuit, and transmission parity counter. The transmission bit counter counts transmission data
bits. When the transmission of one data item of the specified data length is completed, the
transmission bit counter sets the flag in the transmission data register. In this case, if the
transmission interrupt is enabled, the transmission interrupt request is generated. The
transmission start circuit starts transmission when data is written to TDR register. The
transmission parity counter generates a parity bit for data to be transmitted if parity is enabled.
● Transmission shift register
The transmission shift register transfers data written to the TDR register to itself and outputs
the data to the SOTn pin, shifting the data bit by bit.
● Transmission data register (TDR)
This register sets transmission data. Data written to this register is converted to serial data and
outputted.
● Error detection circuit
The error detection circuit checks if there was any error at the end of reception. If an error has
occurred, it sets the corresponding error flags.
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CHAPTER 17 LIN-UART
17.2 Configuration of LIN-UART
MB90930 Series
● Oversampling circuit
The oversampling circuit oversamples for five times in the asynchronous mode. The received
value is determined by majority decision of sampling value. It is switched off in synchronous
operation mode.
● Interrupt generation circuit
The interrupt generation circuit controls all interrupt sources. If a corresponding interrupt
enable bit is set, the interrupt will be generated immediately.
● LIN synch break/synch field detection circuit
The LIN synch break/synch field detection circuit detects a LIN synch break when the LIN
master node transmits a message header. The LBD flag is set when the LIN synch break is
detected. An internal signal is output to the capture in order to detect the 1st and 5th falling
edges of the LIN synch field and to measure the actual serial clock synchronization transmitted
by the master node.
● LIN synch break generation circuit
The LIN synch break generation circuit generates a LIN synch break of a determined length.
● Bus idle detection circuit
The bus idle detection circuit detects if neither reception nor transmission is going on. In this
case, the circuit generates the flag bits TBI and RBI.
● LIN-UART serial mode register (SMR)
Operating functions are as follows:
• Selecting the LIN-UART operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting dedicated reload timer
• Resetting the LIN-UART software (preserving the settings of the registers)
• Specifying whether to enable/disable serial data output to the corresponding pin
• Specifying whether to enable/disable clock output to the corresponding pin
● Serial control register (SCR)
Operating functions are as follows:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable/disable transmission
• Specifying whether to enable/disable reception
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CHAPTER 17 LIN-UART
17.2 Configuration of LIN-UART
MB90930 Series
● Serial status register (SSR)
Operating functions are as follows:
• Indicating status of receive/transmit operations and errors
• Specifying LSB first or MSB first as transfer direction
• Receive interrupt enable/disable
• Transmit interrupt enable/disable
● Extended status control register (ESCR)
• LIN synch break interrupt enable/disable
• Indicating LIN synch break detection
• Specifying LIN synch break length
• Directly accessing SINn and SOTn pins
• Specifying continuous clock output operation in LIN-UART synchronous clock mode
• Specifying sampling clock edge
● Extended communication control register (ECCR)
• Bus idle detection
• Setting synchronous clock
• LIN synch break generation
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CHAPTER 17 LIN-UART
17.3 Pins of LIN-UART
17.3
MB90930 Series
Pins of LIN-UART
This section lists and details the pins, interrupt sources, and registers of the
LIN-UART.
■ Pins of LIN-UART
The LIN-UART pins also serve as general-purpose ports. Table 17.3-1 lists the pin functions, I/
O formats, and settings required to use LIN-UART.
Table 17.3-1 Pins of LIN-UART
Pin name
Pin function
I/O type
PC0/SIN0
PC3/SIN1
PD0/SIN2
PD3/SIN3
Port I/O,
serial data input
CMOS output,
CMOS/CMOS hysteresis/
Automotive input
PC1/SOT0
PC4/SOT1
PD1/SOT2
PD4/SOT3
Port I/O,
serial data output
PC2/SCK0
PC5/SCK1
PD2/SCK2
PD5/SCK3
Pull-up select
Setting to use pin
Sets to input port
(DDR: corresponding bit = 0)
Set to output enable mode
(SMRn: SOE = 1)
None
Port I/O,
Serial clock
input/output
Standby
control
Yes
CMOS output,
CMOS hysteresis/
Automotive input
Set as an input port
when a clock is inputted
(DDR: corresponding bit = 0)
Set to output enable mode
when a clock is outputted
(SMRn: SCKE = 1)
See "3. DC Characteristics in ■ ELECTRICAL CHARACTERISTICS" in the data sheet for
the standard value.
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CHAPTER 17 LIN-UART
17.3 Pins of LIN-UART
MB90930 Series
■ Block Diagram of LIN-UART Pins
Figure 17.3-1 Block Diagram of LIN-UART Pins
Resource input
Resource output
Resource
output enable
Port data register (RDR)
Internal data bus
PDR read
P-ch
Output write
PDR write
Pin
Port direction register (RDR)
N-ch
Direction latch
DDR write
General-purpose
I/O pin/SIN
General-purpose
I/O pin/SCK
General-purpose
I/O pin/SOT
Standby control (SPL = 1)
DDR read
Standby control: stop mode (SPL =1), time-base timer mode (SPL = 1)
Note: Resource I/O signals are inputted or outputted from pins including resource functions.
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
17.4
MB90930 Series
LIN-UART Registers
This section lists LIN-UART registers.
■ List of LIN-UART Registers
Figure 17.4-1 List of LIN-UART Registers
• LIN-UART0
Address:
bit15
bit8
bit7
bit0
000035H,
000034H
SCR0 (serial control register)
SMR0 (serial mode register)
000037H,
000036H
SSR0 (serial status register)
RDR0/TDR0 (reception data register/transmission data register)
000039H,
000038H
ESCR0 (extended status control register)
ECCR0 (extended communication control register)
00003BH,
00003AH
BGR01 (baud rate generator register)
BGR00 (baud rate generator register)
• LIN-UART1
Address:
bit15
bit8
bit7
bit0
0000C5H,
0000C4H
SCR1 (serial control register)
SMR1 (serial mode register)
0000C7H,
0000C6H
SSR1 (serial status register)
RDR1/TDR1 (reception data register/transmission data register)
0000C9H,
0000C8H
ESCR1 (extended status control register)
ECCR1 (extended communication control register)
0000CBH,
0000CAH
BGR11 (baud rate generator register)
BGR10 (baud rate generator register)
• LIN-UART2
Address:
bit15
bit8
bit7
bit0
0000E1H,
0000E0H
SCR2 (serial control register)
SMR2 (serial mode register)
0000E3H,
0000E2H
SSR2 (serial status register)
RDR2/TDR2 (reception data register/transmission data register)
0000E5H,
0000E4H
ESCR2 (extended status control register)
ECCR2 (extended communication control register)
0000E7H,
0000E6H
BGR21 (baud rate generator register)
BGR20 (baud rate generator register)
• LIN-UART3
Address:
bit15
bit8
bit7
bit0
0000E9H,
0000E8H
SCR3 (serial control register)
SMR3 (serial mode register)
0000EBH,
0000EAH
SSR3 (serial status register)
RDR3/TDR3 (reception data register/transmission data register)
0000EDH,
0000ECH
ESCR3 (extended status control register)
ECCR3 (extended communication control register)
0000EFH,
0000EEH
BGR31 (baud rate generator register)
BGR30 (baud rate generator register)
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.1
Serial Control Register (SCR)
The serial control register (SCR) specifies parity, selects the stop bit and data
lengths, selects a frame data format in mode 1, clears the reception error flag,
and specifies whether to enable/disable transmission and reception.
■ Serial Control Register (SCR)
Figure 17.4-2 Serial Control Register (SCR)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7
SCR0 : 000035H
PEN
P SBL CL AD CRE RXE TXE
SCR1 : 0000C5H
SCR2 : 0000E1H R/W R/W R/W R/W R/W W R/W R/W
SCR3 : 0000E9H
bit8
bit0
Initial value
00000000B
TXE
Transmission enable bit
0
Disables transmission
1
Enables transmission
bit9
RXE
Reception enable bit
0
Disables reception
1
Enables reception
bit10
Reception error flag clear bit
CRE
Write
Read
0
Has no effect on operation
1
Clear all reception error
flags (PE, FRE, ORE)
Always read "0"
bit11
AD
Address/data format select bit
0
Data frame
1
Address frame
bit12
CL
Data length select bit
0
7 bits
1
8 bits
bit13
SBL
Stop bit length select bit
0
1 it
1
2 bits
b
bit14
P
R/W
: Readable/Writable
W
: Write-only
: Initial value
CM44-10150-1E
Parity select bit
0
Even parity
1
Odd parity
bit15
PEN
Parity enabled bit
0
Without parity
1
With parity
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
Table 17.4-1 Functions of Each Bit in Serial Control Register (SCR)
Bit name
Function
This bit selects whether to add a parity bit (during transmission) and whether to
detect parity (during reception).
Note:
Parity bit is only provided in operation mode 0 and in operation mode 2 with
start/stop bit (ECCR: SSM=1).
This bit is fixed to "0" in mode 3 (LIN).
bit15
PEN:
Parity enable bit
bit14
P:
When parity is provided (SCR: PEN=1), this bit selects even (0) or odd (1) parity.
Parity selection bit
SBL:
bit13 Stop bit length
selection bit
CL:
bit12 Data length
selection bit
This bit selects the length of the stop bit (frame end mark of transmission data) in
operation modes 0 and 1 (asynchronous) or in operation mode 2 (synchronous) with
start/stop bit (ECCR: SSM=1).
This bit is fixed to "0" in mode 3 (LIN).
Note:
At reception, always first stop bit is detected.
This bit specifies the length of transmission or reception data. This bit is fixed to
"1" in modes 2 and 3.
AD:
Address/data
bit11
format selection
bit
This bit specifies the frame data format to be transmitted and received in
multiprocessor mode (mode 1). Writing to this bit is provided for a master CPU,
reading from this bit for slave CPU.
• When set to 0: data frame
• When set to 1: address data frame
The reading value is a value of last received data format.
Note:
For using this bit, see Section "17.8 Notes on Using LIN-UART".
CRE:
bit10 Reception error
flag clear bit
This bit clears the FRE, ORE, and PE flags of the serial status register (SSR).
• Writing "1" to this bit clears the error flag.
• Writing "0" has no effect.
"0" is always read.
Note:
Clear reception error flags after the receive operation.
bit9
RXE:
Reception
operation enable
bit
This bit enables/disables LIN-UART reception.
• If this bit is set to "0", LIN-UART disables the reception of data frames.
• If this bit is set to "1", LIN-UART enables the reception of data frames.
The LIN synch break detection in mode 3 remains unaffected.
Note:
If reception is disabled (RXE=0) during receiving, it is stopped immediately. In
this case, the data is not guaranteed.
bit8
TXE:
Transmission
operation enable
bit
This bit enables/disables LIN-UART transmission.
• If the bit is set to "0", LIN-UART disables the transmission of data frames.
• If the bit is set to "1", LIN-UART enables the transmission of data frames.
Note:
If transmission is disabled (TXE=0) during transmitting, it is stopped
immediately. In this case, the data is not guaranteed.
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.2
LIN-UART Serial Mode Register (SMR)
LIN-UART serial mode register (SMR) selects an operation mode and baud rate
clock and specifies whether to enable/disable output of serial data and clocks
to the corresponding pin.
■ LIN-UART Serial Mode Register (SMR)
Figure 17.4-3 Serial Mode Register (SMR)
Address
bit15
SMR0:000034H
SMR1:0000C4H
SMR2:0000E0H
SMR3:0000E8H
bit8 bit7
bit6 bit5
bit4
bit2
bit3
bit1
bit0 Initial value
MD1 MD0 OTO EXT REST UPCL SCKE SOE 00000000B
R/W R/W R/W R/W W
W
R/W R/W
bit0
SOE
LIN-UART serial data output enable bit
0
General-purpose I/O port
1
LIN-UART serial data output pin
bit1
SCKE
LIN-UART serial clock output enable bit
0
General-purpose I/O port or LIN-UART clock
input pin
1
LIN-UART serial clock output pin
bit2
LIN-UART programmable clear bit
UPCL
Write
0
Has no effect on operation
1
Reset LIN-UART
Read
Always
read "0"
bit3
Reload counter restart bit
REST
Write
0
Has no effect on operation
1
Restart reload counter
Read
Always
read "0"
bit4
EXT
External serial clock source select bit
0
Baud rate generator (Reload counter) used
1
External serial clock source used
bit5
OTO
R/W
: Readable/Writable
W
: Write-only
: Initial value
CM44-10150-1E
One-to-one external clock input enable bit
0
Baud rate generator (Reload counter) used
1
External clock used as it is
bit7
bit6
MD1
MD0
0
0
Mode 0: Asynchronous normal
0
1
Mode 1: Asynchronous multiprocessor
1
0
Mode 2: Synchronous
1
1
Mode 3: Asynchronous LIN
Operation mode setting bits
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17.4 LIN-UART Registers
MB90930 Series
Table 17.4-2 Functions of Each Bit in Serial Mode Register (SMR)
Bit name
Function
bit7,
bit6
MD1, MD0:
Operation mode
setting bits
These two bits set the LIN-UART operation mode.
bit5
OTO:
One-to-one external
clock input enable
bit
This bit sets an external clock directly to the LIN-UART serial clock by
writing "1".
This function is used for operation mode 2 (synchronous) slave operation
(ECCR: MS=1).
When EXT=0, this bit is fixed to "0".
bit4
EXT:
External serial
clock source select
This bit selects the clock input.
When "0" is set to this bit, it selects the clock of internal baud rate generator
(reload counter). When "1" is set to it, it selects the external serial clock
source.
bit3
REST:
Reload counter
restart bit
If "1" is written to this bit, the reload counter is restarted.
Writing "0" to this bit has no effect.
"0" is always read.
UPCL:
LIN-UART
programmable clear
bit (LIN-UART
software reset)
Writing "1" to this bit resets LIN-UART immediately (LIN-UART software
reset). The register settings are preserved. Possible reception or transmission
will cut off.
All of transmission/reception interrupt sources (TDRE, RDRF, LBD, PE,
ORE, FRE) are cleared. Reset the LIN-UART after disabling the interrupt and
transmission. Also, when the reception data register is cleared (RDR = 00H),
the reload counter restarts.
Writing "0" to this bit has no effect.
"0" is always read.
bit1
SCKE:
LIN-UART serial
clock output enable
bit
This bit controls the serial clock I/O ports.
When this bit is "0", SCKn pin operates as general-purpose I/O port or serial
clock input pin. When this bit is "1", the pin operates as serial clock output pin
and outputs clock in operation mode 2 (synchronous).
Note:
When using SCKn pin as serial clock input (SCKE=0) pin, set the
corresponding DDR bit of general-purpose I/O port as input port. Also,
select external clock (EXT = 1) using the clock selection bit.
Reference:
When the SCKn pin is assigned to serial clock output (SCKE=1), it
functions as the serial clock output pin regardless of the status of the
general-purpose I/O ports.
bit0
SOE:
LIN-UART serial
data output enable
bit
This bit enables or disables the output of serial data.
When this bit is "0", SOTn pin operates as general-purpose I/O port. When this
bit is "1", SOTn pin operates as serial data output pins (SOTn).
Reference:
When the output of serial data is enabled (SOE=1), SOTn pin functions as
SOTn regardless of the status of general-purpose I/O ports.
bit2
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.3
Serial Status Register (SSR)
The serial status register (SSR) checks the transmission and reception status
and error status, and enables or disables the interrupts.
■ Serial Status Register (SSR)
Figure 17.4-4 Serial Status Register (SSR)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7
SSR0:000037H
SSR1:0000C7H PE ORE FRE RDRF TDRE BDS RIE TIE
SSR2:0000E3H R
R
R
R
R R/W R/W R/W
SSR3:0000EBH
bit0
Initial value
00001000B
bit8
TIE
Transmission interrupt request enable bit
0
Disables transmission interrupts
1
Enables transmission interrupts
bit9
RIE
Reception interrupt request enable bit
0
Disables reception interrupt
1
Enables reception interrupt
bit10
BDS
Transfer direction selection bit
0
LSB first (transfer from lowest bit)
1
MSB first (transfer from highest bit)
bit11
TDRE
Transmission data empty flag bit
0
Data exists in transmission data register
TDR.
1
Transmission data register TDR is empty.
bit12
RDRF
Reception data full flag bit
0
Reception data register RDR is empty.
1
Data exists in reception data register RDR.
bit13
FRE
Framing error flag bit
0
No framing error occurred
1
A framing error occurred
bit14
ORE
Overrun error flag bit
0
No overrun error occurred
1
An overrun error occurred
bit15
PE
R/W
: Readable/Writable
R
: Read-only
Parity error flag bit
0
No parity error occurred
1
A parity error occurred
: Initial value
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
Table 17.4-3 Functions of Each Bit in Serial Status Register (SSR)
Bit name
Function
bit15
PE:
Parity error flag bit
• This bit is set to "1" when a parity error occurs during reception at PE=1 and is
cleared when "1" is written to the CRE bit of the serial control register (SCR).
• A reception interrupt request is outputted when this bit and the RIE bit are "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
bit14
ORE:
Overrun error flag bit
• This bit is set to "1" when an overrun error occurs during reception and is cleared
when "1" is written to the CRE bit of the serial control register (SCR).
• A reception interrupt request is outputted when this bit and the RIE bit are "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
bit13
FRE:
Framing error flag bit
• This bit is set to "1" when a framing error occurs during reception and is cleared
when "1" is written to the CRE bit of the serial control register (SCR).
• A reception interrupt request is outputted when this bit and the RIE bit are "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
bit12
RDRF:
Receive data full flag bit
• This flag indicates the status of the reception data register (RDR).
• This bit is set to "1" when reception data is loaded into RDR and cleared to "0"
when the reception data register (RDR) is read.
• A reception interrupt request is outputted when this bit and the RIE bit are "1".
TDRE:
Transmission data empty
flag bit
• This flag indicates the status of the transmission data register (TDR).
• This bit is cleared to "0" when transmission data is written to TDR and indicates
that valid data exists in TDR. This bit is set to "1" when data is loaded into the
transmission shift register and transmission starts and indicates that no valid data
exists in TDR.
• A transmission interrupt request is generated if both this bit and the TIE bit are
"1".
• If the LBR bit in the extended communication control register (ECCR) register is
set to "1" while the TDRE bit is "1", then this bit once changes to "0". After the
completion of LIN synch break generation, the TDRE bit changes back to "1".
Note:
This bit is set to "1" as its initial value.
bit11
This bit selects whether to transfer serial data from the least significant bit (LSB
first, BDS=0) or the most significant bit (MSB first, BDS=1).
bit10
BDS:
Transfer direction
selection bit
bit9
RIE:
Reception interrupt
request enable bit
• This bit enables or disables the reception interrupt request output to the CPU.
• When both this bit and the receive data flag bit (RDRF) are "1", or when one or
more error flag bits (PE, ORE, FRE) is "1", then a reception interrupt request is
outputted.
bit8
TIE:
Transmission interrupt
request enable bit
• This bit enables or disables the transmission interrupt request output to the CPU.
• A transmission interrupt request is outputted when this bit and the TDRE bit are
"1".
442
Note:
The high-order and low-order sides of serial data are interchanged with each
other during reading from or writing to the serial data register. If this bit is set to
another value after the data is written to the RDR register, the data becomes
invalid. This bit is fixed to "0" in mode 3 (LIN).
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.4
Reception Data Register and Transmission Data
Register (RDR/TDR)
Both RDR and TDR registers are located at the same address. At reading, it
functions as the reception data register. At writing, it functions as the
transmission data register.
■ Reception Data Register and Transmission Data Register (RDR/TDR)
Figure 17.4-5 shows the bit configuration of reception data register and transmission data
register (RDR/TDR).
Figure 17.4-5 Reception Data Register and Transmission Data Register (RDR/TDR)
Address
bit
RDR0/TDR0: 000036H
RDR1/TDR1: 0000C6H
RDR2/TDR2: 0000E2H
RDR3/TDR3: 0000EAH
7
6
5
4
3
2
1
0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 to bit0
R/W
R/W: Readable/Writable
Data resister
Read
Read from reception data
register
Write
Write to transmission data
register
Reception data register (RDR) is the data buffer register for serial data reception.
The serial data signal transmitted to the serial input pin (SINn pin) is converted in the shift
register and stored in the reception data register (RDR).
When the data length is 7 bits, the upper bit (RDR: D7) contains "0".
When the reception data is stored in this register (RDR), the reception data full flag bit (SSR:
RDRF) is set to "1". If a reception interrupt is enabled (SSR: RIE=1) at this point, generates a
reception interrupt request.
Read the reception data register (RDR) when the reception data full flag bit (SSR:RDRF) is
"1". The RDRF bit is cleared automatically to "0" when RDR is read.
Also the reception interrupt is cleared if it is enabled and no error has occurred.
Data in RDR is invalid when a reception error occurs (SSR: PE, ORE, or FRE = 1).
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CHAPTER 17 LIN-UART
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MB90930 Series
■ Transmission Data Register (TDR)
Transmission data register (TDR) is the data buffer register for serial data transmission.
When data to be transmitted is written to the transmission data register (TDR) in transmission
enable state (SCR: TXE=1), it is transferred to the transmission shift register, then converted to
serial data, and transmitted from the serial data output pin (SOTn pin).
If the data length is 7 bits, the upper bit (TDR: D7) is invalid data.
When transmission data is written to this register (TDR), the transmission data empty flag bit
(SSR: TDRE) is cleared to "0".
When transfer to the transmission shift register is completed and transmission starts, the
transmission data empty flag bit (SSR: TDRE) is set to "1".
When the transmission data empty flag bit (SSR: TDRE) is "1", the next part of transmission
data can be written. If transmission interrupt has been enabled, a transmission interrupt is
generated. Write the next part of transmission data when a transmission interrupt is generated
or the transmission data empty flag bit (SSR: TDRE) is "1".
Note:
The transmission data register is a write-only register and the reception data register is a
read-only register. These registers are located in th e same address, so th e read value is
different f rom th e wr ite value. Therefore, in structions t hat pe rform a re ad-modify-write
(RMW) operation, such as the INC/DEC instruction, cannot be used.
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.5
Extended Status Control Register (ESCR)
Extended status control register (ESCR) provides several LIN functions
(enabling/disabling LIN synch break interrupt, selecting LIN synch break
length, and detecting LIN synch break), direct access to the SINn and SOTn
pins and setting of continuous clock output in LIN-UART synchronous clock
mode and sampling clock edge.
■ Bit Configuration of Extended Status Control Register (ESCR)
Figure 17.4-6 shows the bit configuration of the extended status control register (ESCR), and
Table 17.4-4 shows the function of each bit.
Figure 17.4-6 Bit Configuration of Extended Status Control Register (ESCR)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7
ESCR0 : 000039H
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
ESCR1 : 0000C9H
ESCR2 : 0000E5H R/W R/W R/W R/W R/W R/W R/W R/W
ESCR3 : 0000EDH
bit 0 Initial value
00000100B
bit8
SCES
0
1
Sampling clock edge selection bit (mode 2)
Sampling on rising clock edge (normal)
Sampling on falling clock edge (inverted clock)
bit9
CCO
0
1
Continuous clock output enable bit (mode 2)
Continuous clock output disabled
Continuous clock output enabled
bit10
SIOP
0
1
Serial input/output pin direct access setting bit
Write (SOPE = 1)
Read
Fixes SOTn pin to "0"
Reading the value of SINn
pin
Fixes SOTn pin to "1"
bit11
SOPE
0
1
Serial output pin direct access enable bit
Serial output pin direct access disabled
Serial output pin direct access enabled
bit12
LBL0
0
1
0
1
bit13
LBL1
0
0
1
1
LIN synch break length select bits
13-bit length
14-bit length
15-bit length
16-bit length
bit14
LBD
0
1
R/W
x
: Readable/Writable
: Undefined value
bit15
LBIE
0
1
LIN synch break detected flag bit
Write
Read
LIN synch break detected flag No LIN synch break
cleared
detected
Has no effect on operation
LIN synch break detected
LIN synch break detection interrupt enable bit
LIN synch break detection interrupt disabled
LIN synch break detection interrupt enabled
: Initial value
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CHAPTER 17 LIN-UART
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MB90930 Series
Table 17.4-4 Functions in Each Bit of the Extended Status Control Register (ESCR)
Bit name
Function
LBIE:
LIN synch break
detection interrupt
enable bit
This bit enables/disables LIN synch break detection interrupt.
An interrupt is generated when the LIN synch break detected flag (LBD) is "1"
and the interrupt is enabled (LBIE = 1).
This bit is fixed to "0" in operation modes 1 and 2.
bit14
LBD:
LIN synch break
detected flag bit
This bit is set to "1" if a LIN synch break was detected in operation mode 3 (the
serial input is "0" when bit width is 11 bits or more). Writing "0" to it clears this
bit and the corresponding interrupt, if it is enabled. Read-modify-write (RMW)
instructions always read "1". Note that this dose not indicate a LIN synch break
detection.
Note:
When LIN synch break detection is performed, disable reception
(SCR:RXE=0) after enabling LIN synch break detection interrupt (LBIE=1).
bit13,
bit12
LBL1/0:
LIN synch break
length selection
bits
These bits specify the bit length for the LIN synch break generation time.
Receiving a LIN synch break is always fixed to 11 bit times.
bit11
SOPE:
Serial output pin
direct access
enable bit*
Setting this bit to "1" when serial data output is enabled (SMR:SOE = 1) enables
direct writing to the SOTn pin.*
Note:
Setting value of this bit is valid only when the TXE bit of the serial control
register (SCR) is "0".
bit10
SIOP:
Serial input/
output pin direct
access bit*
Normal read instructions always return the value of the SINn pin.
If writing this bit when direct access to the serial output pin is enabled
(SOPE=1), the written value is reflected to the SOTn pin.
Note:
Setting value of this bit is valid only when the TXE bit of the serial control
register (SCR) is "0".
For the bit operation instruction, the bit value of the SOTn in the read cycle is
returned.*
bit9
CCO:
Continuous clock
output enable bit
This bit enables a continuous serial clock output at the SCKn pin if LIN-UART
operates in operation mode 2 (synchronous) and master setting and the SCKn
pin is configured as a clock output.
Note:
When CCO bit is "1", use SSM bit of ECCR as setting to "1".
SCES:
Sampling clock
edge selection bit
Setting this bit to "1" inverts the sampling edge from the rising edge to the
falling edge in operation mode 2 (synchronous) with the slave setting.
If the SCKn pin is clock output in operation mode 2 with the master setting
(ECCR: MS=0), the internal serial clock and the output clock signal are
inverted.
During operation modes 0, 1, 3, set this bit to "0".
bit15
bit8
* : Table 17.4-5 Interaction of SOPE and SIOP
446
SOPE
SIOP
Writing to SIOP
Reading from SIOP
0
R/W
Has no effect (However, the written value is held)
Return the SINn value
1
R/W
Write "0" or "1" to SOTn
Return the SINn value
1
RMW
Reads current value of SOTn and write "0" or "1" to SIOP
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CM44-10150-1E
CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.6
Extended Communication Control Register
(ECCR)
The extended communication control register (ECCR) provides bus idle
detection, synchronous clock settings, and the LIN synch break generation.
■ Bit Configuration of Extended Communication Control Register (ECCR)
Figure 17.4-7 shows the bit configuration of the extended communication control register
(ECCR), and Table 17.4-6 shows the function of each bit.
Figure 17.4-7 Bit Configuration of Extended Communication Control Register (ECCR)
Address
ECCR0:000038H
ECCR1:0000C8H
ECCR2:0000E4H
ECCR3:0000ECH
bit 15
bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
LBR
MS SCDE SSM
RBI
TBI
W
R/W R/W R/W
R
R
000000XXB
bit0
TBI*
0
1
Transmission bus idle detection flag bit
Transmitting
No transmission operation
bit1
RBI*
0
1
Reception bus idle detection flag bit
Receiving
No reception operation
bit2
Unused bit
Read value is undefined.
Always write "0".
bit3
SSM
0
1
bit4
SCDE
0
1
bit5
MS
0
1
Start/stop bit mode enable bit (mode 2)
No start/stop bit
Enable start/stop bit
Serial clock delay enable bit (mode 2)
Disable clock delay
Enable clock delay
Master/Slave function selection bit (mode 2)
Master mode (generating serial clock)
Slave mode (receiving external serial clock)
bit6
LBR
R/W
R
W
X
−
0
1
: Readable/Writable
: Read only
: Write-only
: Undefined value
: Undefined
LIN synch break generating bit
Write
Read
Has no effect on operation
Always read "0"
Generate LIN synch break
bit7
Unused bit
Read value is undefined. Always write "0"
: Initial value
*: Not used in operation mode 2 when SSM = 0
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
Table 17.4-6 Functions of Each Bit in the Extended Communication Control Register (ECCR)
Bit name
Function
bit7
Unused bit
This bit is unused. Read value is undefined. Always write "0"
bit6
LBR: LIN synch
break generating bit
Writing "1" to this bit generates a LIN synch break of the length selected by the
LBL0/LBL1 bits of the ESCR, if operation mode 3 is selected. Setting "0" to it
in operation mode 0.
bit5
MS:
Master/Slave mode
selection bit
This bit selects master or slave mode in mode 2.
If master mode ("0") is selected, LIN-UART generates the synchronous clock.
If slave mode ("1") is selected, LIN-UART receives external serial clock. This
bit is fixed to "0" in modes 0, 1 and 3.
Change this bit, when the SCR: TXE bit is "0".
Note:
If slave mode is selected, the clock source must be external and enabled the
external clock input (SMR: SCKE = 0, EXT = 1, OTO = 1).
bit4
SCDE:
Serial clock delay
enable bit
Setting the SCDE bit to "1" in the master mode operation during mode 2
outputs a delayed serial clock as shown in Figure 17.7-5. This bit is enabled to
SPI.
This bit is fixed to "0" in modes 0, 1 and 3.
bit3
SSM:
Start/Stop bit mode
enable bit
This bit adds start and stop bits to the synchronous data format when set to "1"
mode 2.
This bit is fixed to "0" in modes 0, 1 and 3.
bit2
Unused bit
This bit is unused.
Read value is undefined.
Always write to "0".
bit1
RBI:
Reception bus idle
detection flag bit
This bit is "1" if there is no reception operation on the SIN pin and it is kept at
"H". Do not use this bit in mode 2 when SSM=0.
bit0
TBI:
Transmission bus
idle detection flag
bit
This bit is "1" if there is no transmission operation on the SOTn pin. Do not use
this bit in mode 2 when SSM=0.
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CHAPTER 17 LIN-UART
17.4 LIN-UART Registers
MB90930 Series
17.4.7
Baud Rate Generator Registers 0 and 1 (BGRn0/
BGRn1)
The baud rate generator registers 0 and 1 (BGRn0/BGRn1) set the division ratio
for the clock value. Also, the count value of the transmission reload counter
can be read.
■ Bit Configuration of Baud Rate Generator Registers (BGRn0/BGRn1)
Figure 17.4-8 shows the bit configuration of the baud rate generator registers (BGRn0/
BGRn1).
Figure 17.4-8 Bit Configuration of Baud Rate Generator Registers (BGRn0/BGRn1)
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
Address
00000000 B
BGR00: 00003AH
00000000 B
BGR01: 00003BH
BGR10: 0000CAH R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BGR11: 0000CBH
BGR20: 0000E6H
BGR21: 0000E7H
BGR30: 0000EEH
BGR31: 0000EFH
bit7 - bit0
BGRn0
Write
Read
Baud rate generator register n0
Writes to the reload counter 0 to 7.
Reads the transmission reload counter bits 0 to 7.
bit14 - bit8
BGRn1
Baud rate generator register n1
Write
Writes to the reload counter 8 to 14.
Read
Reads the transmission reload counter bits 8 to 14.
bit15
R/W : Readable/Writable
R
: Read only
−
: Undefined
n = 0, 1, 2, 3
Read
Undefined bit
"0" can be read
The baud rate generator registers determine the division ratio for the serial clock.
The BGRn1 corresponds to the upper bit and BGRn0 to lower bit, writing of the reload value to
counter and reading of the transmission reload counter value are allowed. Also, byte and word
access are enabled.
When writing the reload value to the baud rate generator registers, the reload counter starts
counting.
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
17.5
MB90930 Series
Interrupts of LIN-UART
LIN-UART uses both reception and transmission interrupts. An interrupt
request can be generated for either of the following causes:
• Receive data is set in the reception data register (RDR), or a reception error
occurs.
• Transmission data is transferred from the transmission data register (TDR) to
the transmission shift register and transmission is started.
• LIN synch break is detected.
The extended intelligent I/O service (EI2OS) is available for these interrupts.
■ Interrupts of LIN-UART
Table 17.5-1 shows the interrupt control bits and interrupt cause of the LIN-UART.
Table 17.5-1 Interrupt Control Bits and Interrupt Cause of LIN-UART
Reception and Interrupt
transmission/ request
capture
flag bit
Reception
Transmission
Input capture
Operation mode
Flag
register
0
1
2
3
RDRF
SSR
❍
❍
❍
❍
Receive data is
written to RDR
ORE
SSR
❍
❍
❍
❍
Overrun error
FRE
SSR
❍
❍
❍
Framing error
PE
SSR
❍
×
×
Parity error
"1" is written to
reception error flag
clear bit (SCR: CRE)
LBD
ESCR
×
×
×
❍
LIN synch break
ESCR:LBIE
detection
"0" is written to
ESCR: LBD.
TDRE
SSR
❍
❍
❍
❍
Transmission
SSR:TIE
register is empty.
Writing transmission
data
ICP0/
ICP1/
ICP6/
ICP7
ICS01/
ICS67
×
×
×
❍
1st falling edge
of LIN synch
field
ICP0/
ICP1/
ICP6/
ICP7
ICS01/
ICS67
×
×
×
❍
Interrupt cause
5th falling edge
of LIN synch
field
Interrupt cause
enable bit
Clearing interrupt
request flag
Receive data is read
SSR:RIE
ICS01:ICE0/
ICE1,
ICS67:ICE6/
ICE7
Disable ICP0/ICP1/
ICP6/ICP7
❍ : Bit used
× : Unused bit
: Availabe only when ECCR: SSM=1
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
● Reception interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the serial
status register (SSR) is set to "1":
Data reception is completed
The received data was transferred from the serial input shift register to the
reception data register (RDR) and data can be read (RDRF=1).
Overrun error
RDRF = 1 and RDR was not read by the CPU and next serial data is received
(ORE=1).
Framing error
Stop bit reception error (FRE=1)
Parity error
Parity detection error (PE=1)
If at least one of these flag bits above is "1" and the reception interrupt is enabled (SSR: RIE =
1), a reception interrupt request is generated.
If the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". The
error flags are cleared to "0", if "1" is written to the reception error flag clear bit (CRE) of the
serial control register (SCR).
Note:
The CRE flag is write only and held "1" for one clock cycle when "1" is written to it.
● Transmission interrupt
If transmission data is transferred from the transmission data register (TDR) to the transfer shift
register and transfer is started, the transmission data register empty flag bit (TDRE) of the
serial status register (SSR) is set to "1". In this case, a transmission interrupt request is
generated, if the transmission interrupt is enabled (SSR: TIE=1).
Note:
The initial value of TDRE (after hardware or software reset) is "1". Therefore, an interrupt
is generated immediately then, if the TIE bit is set to "1". Also note, that the only way to
clear the TDRE flag is writing data to the transmission data register (TDR).
● LIN synch break interrupt
This works for LIN slave operation in operation mode 3.
If the bus (serial input) is "0" for more than 11 bit times, the LIN synch break detected flag bit
(LBD) of the extended status control register (ESCR) is set to "1". The LIN synch break
interrupt and the LBD flag are cleared after writing "0" to the LBD flag. The LBD flag has to
be cleared before input capture interrupt for LIN synch field.
When LIN synch break detection is performed, it is necessary to disable the reception (SCR:
RXE=0).
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
● LIN synch field edge detection interrupts
This works for LIN slave operation in operation mode 3.
After LIN synch break detection, the internal signal is set to "1" at first falling edge of the LIN
synch field and to the "0" after fifth falling edge. When the internal signal is set in the capture
side to be inputted to capture (ICU0/1/6/7) and to be detected both edges, the interrupt occurs if
the capture interrupt is enabled.
The difference of the count values detected in the capture is serial clock 8 bits for master, and
new baud rate can be calculated.
When the falling edge of the start bit is detected, the reload counter restarts automatically.
■ LIN-UART Interrupts and EI2OS
Table 17.5-2 LIN-UART Interrupts and EI2OS
Interrupt control register
Channel
Interrupt No.
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
LIN-UART0 reception
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
LIN-UART0 transmission
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
LIN-UART1 reception
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
*1
LIN-UART1 transmission
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
*2
LIN-UART2 reception
#35(23H)
ICR12
0000BCH
FFFF70H
FFFF71H
FFFF72H
*1
LIN-UART2 transmission
#36(24H)
ICR12
0000BCH
FFFF6CH
FFFF6DH
FFFF6EH
*2
LIN-UART3 reception
#24(18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
*3
LIN-UART3 transmission
#26(1AH)
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
*2
*1: EI2OS can only be used when the ICR12 to ICR14 and interrupt source that shares the interrupt vector are not used.
Reception error can be detected. EI2OS stop function is available.
*2: EI2OS can only be used when the ICR07, ICR13, ICR14, and interrupt source that shares the interrupt vector are not
used.
*3: EI2OS can only be used when the ICR06 and the interrupt source that shares the interrupt vector are not used. Reception
error can be detected. EI2OS stop function is available.
■ LIN-UART EI2OS Functions
LIN-UART has a circuit for operating EI2OS, which can be started up for either reception or
transmission interrupts.
● For reception
EI2OS can be used if other interrupt is not enabled because the UART shares the interrupt
control registers with transmission interrupt and other UART.
● For transmission
The interrupt control register shares with the transmission interrupt or other UART. Therefore,
EI2OS can be used if other interrupt is not enabled.
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
17.5.1
Timing of Reception Interrupt Generation and Flag
Set
The following are the reception interrupt causes: completion of reception (SSR:
RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE).
■ Timing of Reception Interrupt Generation and Flag Set
The received data is stored in the RDR register if the first stop bit is detected in mode 0, 1, 2 (if
SSM = 1), 3, or the last data bit was detected in mode 2 (if SSM = 0). Each flag is set if the
reception is completed (SSR:RDRF = 1) and the reception error occurs (SSR: PE, ORE, or
FRE=1). In this case, if the reception interrupt is enabled (SSR:RIE=1), reception interrupt
occurs.
Note:
If a r eception error has occurred in each
contains invalid data.
mode, th e re ception da ta register (RDR)
Figure 17.5-2 shows the reception operation and flag set timing.
Figure 17.5-1 Reception Operation and Flag Set Timing
Reception data
(mode 0/3)
ST
D0
D1
D2
...
D5
D6
D7/P
SP
ST
Reception data
(Mode 1)
ST
D0
D1
D2
...
D6
D7
AD
SP
ST
D0
D1
D2
...
D4
D5
D6
D7
D0
Reception data
(Mode 2)
PE*1, FRE
RDRF
ORE*2
(RDRF = 1)
Reception interrupt occurs
*1: The PE flag will always remain "0" in mode 1 or 3.
*2: An overrun error occurs, if next data is transferred before the reception data is read (RDRF=1).
ST: Start Bit SP: Stop Bit AD: Mode 1 (multiprocessor) address/data selection bit
Note:
Figure 17.5-2 does not show all possible reception options for mode 0. This is an example
for "7P1" and "8N1" (P = "even parity" or "odd parity").
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
Figure 17.5-2 ORE Flag Set Timing
Reception data
RDRF
ORE
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
17.5.2
Timing of Transmission Interrupt Generation and
Flag Set
A transmission interrupt is generated when the transmission data is
transferred from transmission data register (TDR) to transmission shift register
and transmission is started.
■ Timing of Transmission Interrupt Generation and Flag Set
When the data written to the TDR register is transferred to the transmission shift register and
the transmission is started, next data to be written is enabled (SSR: TDRE=1). Then, if
transmission interrupt is enabled (SSR: TIE=1), the transmission interrupt occurs. Because the
TDRE bit is "read only", it only can be cleared to "0" by writing data into TDR.
Figure 17.5-3 shows the transmission operation and flag set timing for the each modes of LINUART.
Figure 17.5-3 Transmission Operation and Flag Set Timing
Transmission interrupt generated
Transmission interrupt generated
Mode 0, 1 or 3:
Write to TDR
TDRE
Serial output
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
AD
AD
Transmission interrupt generated
Transmission interrupt generated
Mode 2 (SSM = 0):
Write to TDR
TDRE
Serial output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
ST: Start bit D0 to D7: data bits P: Parity SP: Stop bit
AD: Address/data selection bit (mode1)
Note:
Figure 17. 5-3 d oes not sh ow all possible transmission op tions fo r mo de 0. This is an
example for only "8p1" (p = "even parity or "odd parity").
Parity bit is not provided in mode 3 or mode 2, if SSM = 0.
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CHAPTER 17 LIN-UART
17.5 Interrupts of LIN-UART
MB90930 Series
■ Transmission Interrupt Request Generation Timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1),
transmission interrupt is generated.
Note:
A tr ansmission int errupt is g enerated im mediately after the tr ansmission int errupt is
enabled (SSR:TIE=1) because the TDRE bit is set to "1" as its initial value. TDRE can be
cleared only by writing new data to the transmission data register (TDR). Carefully specify
the transmission interrupt enable timing.
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17.6
LIN-UART Baud Rates
CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
One of the following can be selected for the LIN-UART transmission/reception
clock source:
• Dedicated baud rate generator (Reload Counter)
• Input external clock to baud rate generator (Reload Counter)
• External clock (directly use SCKn pin input clock)
■ UART Baud Rate Selection
One of the following three types of baud rates can be selected. The baud rate selection circuit is
designed as shown in Figure 17.6-1.
● Baud rates determined using the dedicated baud rate generator (reload counter) with
internal clock divided
LIN-UART has two independent internal reload counters for transmission and reception serial
clock. The baud rate can be selected via the 15-bit reload value determined by the baud rate
generator registers 1, 0 (BGRn1, BGRn0).
The reload counter divides the internal clock by set value.
It is used in asynchronous or synchronous (master) mode.
Internal clock and baud rate generator clock is selected for the setting of clock source (SMR:
EXT=0, OTO=0).
● Baud rates determined using the dedicated baud rate generator (reload counter) with
external clock divided
An external clock is used for the clock source of the reload counter.
The baud rate can be selected via the 15-bit reload value determined by the baud rate generator
registers 1, 0 (BGRn1, BGRn0).
The reload counter divides the external clock by set value.
It is used in asynchronous mode.
Select external clock and baud rate generator clock for the setting of the clock source (SMR:
EXT=1, OTO=0).
This was designed to use the oscillators with special frequencies and having the possibility to
divide them.
● Baud rates using external clock (one-to-one mode)
The clock input from LIN-UART clock pulse input pins (SCKn) is used as it is (synchronous
mode 2 slave operation (ECCR: MS=1)).
It is used in synchronous mode (slave).
Select external clock and direct use of external clock for the setting of clock source (SMR:
EXT=1, OTO=1).
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CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
MB90930 Series
Figure 17.6-1 Baud Rate Selection Circuit of LIN-UART
REST
Start bit falling
edge detection
Reload value: v
Reception
15-bit reload counter
Set
Rxc = 0?
Reload
Rxc = v/2?
FF
Reception clock
0
Reset
1
Reload value: v
CLK
0
SCKn
(external clock
input)
1
Transmission
15-bit reload counter
Counter value: TXC
EXT
Txc = 0?
Set
FF
Reload
OTO
0
Reset
Txc = v/2?
1
Transmission
clock
Internal data bus
EXT
REST
OTO
SMRn
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR9
BGR8
BGRn1
register
BGR7
BGR6
BGR5
BGR4
BGR3
BGR2
BGR1
BGR0
BGRn0
register
n=0,1,2,3
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17.6.1
Setting the Baud Rate
CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
This section describes how the baud rates are set and the resulting serial clock
frequency is calculated.
■ Calculating the Baud Rate
The both 15-bit reload counters are programmed by the baud rate generator registers 1, 0
(BGRn1/BGRn0).
The calculation formula for the baud rate is as follows.
Reload value:
v=
(
φ
b
) -1
v: reload value b: baud rate φ: machine clock, external clock frequency
Example of calculation
If the machine clock is 32 MHz, the internal clock is used, and the desired baud rate is
19200 bps, then the reload value v is calculated as shown below.
Reload value:
v=
(
32 × 106
19200
) -1 = 1665
The exact baud rate can then be calculated:
b=
φ
(v + 1)
=
32 × 106
= 19207.6831
1666
Note:
Setting th e re load value to "0" st ops th e re load counter. For th is re ason, th e m inimum
division ratio is 2.
For transmission/reception in asynchronous mode, the reload value must be greater than
or eq ual to 4 be cause 5 t imes o ver-sampling is per formed t o d etermine th e re ception
value.
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CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
MB90930 Series
■ Reload Value and Baud Rate for Each Clock Speed
Reload value and baud rate for each clock speed is shown in Table 17.6-1.
Table 17.6-1 Reload Value and Baud Rate
8 MHz
Baud rate
10 MHz
16 MHz
20 MHz
32 MHz
Reload
value
dev.
Reload
value
dev.
Reload
value
dev.
Reload
value
dev.
Reload
value
dev.
4M
-
-
-
-
-
-
4
0
7
0
2M
-
-
4
0
7
0
9
0
15
0
1M
7
0
9
0
15
0
19
0
31
0
500000
15
0
19
0
31
0
39
0
63
0
460800
-
-
-
-
-
-
-
-
68
-0.16
250000
31
0
39
0
63
0
79
0
127
0
230400
-
-
-
-
-
-
-
-
138
0.08
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
207
-0.16
125000
63
0
79
0
127
0
159
0
255
0
115200
68
-0.64
86
0.22
138
0.08
173
0.22
277
0.08
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
416
0.08
57600
138
0.08
173
0.22
277
0.08
346
-0.06
554
-0.01
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
832
-0.030
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
1110
<0.01
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1665
0.02
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
3070
<0.01
9600
832
0.04
1041
0.03
1666
0.02
2083
0.03
3332
<0.01
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
4443
<0.01
4800
1666
0.02
2082
-0.02
3332
<0.01
4166
<0.01
6666
<0.01
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
13332
<0.01
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
26666
<0.01
600
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
300
26666
<0.01
-
-
-
-
-
-
-
-
The unit of frequency deviation (dev.) is %.
Note:
The maximum baud rate for synchronous mode is 1/5 of the machine clock.
■ External Clock
If the EXT bit of the SMR is set to "1", an external clock is selected. In the baud rate generator,
the external clock can be used in the same way as the internal clock.
When slave operation is used in synchronous mode 2, select the one-to-one external clock
input mode (SMR:OTO=1). In this mode, the external clock input to SCKn is input directly to
the UART serial clock.
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CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
MB90930 Series
Note:
The e xternal cloc k signal is synchronized to the int ernal clock in th e LIN -UART. Th is
means that indivisible external clock rates will result in phase unstable signals.
■ Operation of the Reload Counter
Figure 17.6-2 shows the operation of the 2 reload counters when the reload value is 832.
Figure 17.6-2 Operation of the Reload Counter
Transmission/Reception clock
Reload
counter
001
000
832
831
830
829
828
827
413
412
411
410
Reload counter value
Transmission/Reception clock
Reload
counter
417
416
415
414
Note:
The falling edge of the s erial clock signal is generated after the reload value divided by 2
((v+1)/2) is counted.
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CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
17.6.2
MB90930 Series
Reload counter
The reload counter is a 15-bit reload counter that functions as dedicated baud
rate generator. The transmission/reception clock is generated by the external
or internal clock.
The count value in the transmission reload counter can be read from the baud
rate generator registers (BGR1, BGR0).
■ Function of Reload Counter
The reload counter has the transmission and reception reload counters and functions as
dedicated baud rate generator. It consists of a 15-bit register for the reload value and generates
the transmission/reception clocks by the external or internal clock. The count value in the
transmission reload counter can be read from the baud rate generator registers (BGR1, BGR0).
● Count start
When the reload value is written to the baud rate generator registers (BGR1, BGR0), the reload
counter starts counting.
● Restart
The reload counter restarts under the following conditions.
Common for transmission/reception reload counter
• UART programmable reset (SMR:UPCL bit)
• Programmable restart (SMR:REST bit)
Reception reload counter
• Falling edge of start bit is detected in asynchronous mode
If the REST bit of the serial mode register (SMR) is set to "1", both reload counters are
restarted at the next clock cycle.
This feature is intended to use the transmission reload counter as a simple timer.
Figure 17.6-3 shows a possible usage of this feature (assume that the reload value is 100).
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CHAPTER 17 LIN-UART
17.6 LIN-UART Baud Rates
MB90930 Series
Figure 17.6-3 Example of a Simple Timer through Restarting the Reload Timer
MCU
Clock
Reload
Counter
Clock
Outputs
RESET
Reload
Value
37
36
35 100 99
98
97
96
95
94
93
92
91
90
89
88
87
Read
BGR0/BGR1
Dat a
Bus
90
: don’t care
In this case, machine cycle after restart cyc is calculated as follows:
cyc = v - c + 1 = 100 - 90 + 1 = 11
v: reload value, c: reload counter value
Note:
The reload counter restarts also when UART is reset by writing "1" to SMR:UPCL bit.
• Automatic restart (reception reload counter only)
In asynchronous mode, if a falling edge of a start bit is detected, the reception reload
counter is restarted. This is intended to synchronize the reception shift register to the
reception data.
● Clearing counters
The reload value of the baud rate generator registers (BGR1, BGR0) and the reload counters
are cleared to "00H" by the reset and the counters stop.
Although the counter value is temporarily cleared to "00H" by the LIN-UART reset (writing
"1" to SMR:UPCL), the reload counter restarts since the reload value is retained. The counter
value is not cleared to "00H" by the restart setting (writing "1" to SMR:REST), and the reload
counter restarts.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
17.7
MB90930 Series
Operation of LIN-UART
LIN-UART operates in operation mode 0 for bidirectional serial communication,
in mode 1 as master or slave in multiprocessor communication, and in mode 2
and 3 in bidirectional communication as master or slave.
■ Operation of LIN-UART
● Operation mode
There are four LIN-UART operation modes: modes 0 to 3. As listed in Table 17.7-1, an
operation mode can be selected according to the inter-CPU communication method and data
transfer method.
Table 17.7-1 LIN-UART Operation Modes
Data length
Operation mode
Without parity
0
Normal mode
1
Multiprocessor
mode
7 bits or 8 bits + 1*
2
Normal mode
8 bits
3
LIN mode
With parity
7 bits or 8 bits
8 bits
Synchronous
method
Stop bit length
Data bit format
1 bit or 2 bits
LSB-first
MSB-first
Asynchronous
-
-
Asynchronous
Synchronous
None, 1 bit, 2 bits
Asynchronous
1 bit
LSB-first
-: Setting disabled
*: "+1" means the address/data selection bit (AD) used for controlling communication in the multiprocessor mode
Note:
Mode 1 op eration is sup ported bot h for ma ster or slave o peration of LI N-UART in a
master/slave c onnection system. In Mode 3, the communication f ormat is fixed to 8N1,
LSB first.
If the m ode is c hanged, LI N-UART c uts of f all poss ible tr ansmission or re ception and
awaits then new action.
■ Inter-CPU Connection Method
External clock one-to-one connection (normal mode) or master/slave connection
(multiprocessor mode) can be selected. For either connection method, the data length, whether
to enable parity, and the synchronization method must be common to all CPUs. Select an
operation mode as follows:
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs.
Select operation mode 0 for asynchronous mode and operation mode 2 for synchronous
mode. Note, that one CPU has to set to the master and the other to the slave in mode 2.
• Select operation mode 1 for the master/slave connection method and use it either for the
master or slave system.
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MB90930 Series
■ Synchronous Method
In asynchronous operation, LIN-UART reception clock is automatically synchronized to the
falling edge of a received start bit. In synchronous mode, the synchronization is performed
either by the clock signal of the master device or by the clock signal if operating as master.
■ Signaling
NRZ (Non Return to Zero)
■ Enabling Transmission/Reception
LIN-UART controls both transmission and reception using SCR: TXE bit and SCR: RXE bit
respectively.
To disable the transmission or reception, follow the procedure described below.
• If reception operation is disabled during reception, finish reception and read the reception
data register (RDR). Then stop the reception operation.
• If the transmission operation is disabled during transmission, wait until transmission
finishes and then stop the transmission operation.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
17.7.1
MB90930 Series
Operation in Asynchronous Mode (Operation
Modes 0 and 1)
When LIN-UART is used in operation mode 0 (normal mode) or operation mode
1 (multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
● Transmission/Reception data format
Transmit/reception data always begins with a start bit ("L" level) followed by transmission/
reception for a specified data bit length, and ends with at least one stop bit ("H" level).
The bit transfer direction (LSB first or MSB first) is determined by the BDS bit of the serial
status register (SSR). The parity bit (if enabled) is always placed between the last data bit and
the first stop bit.
In operation mode 0, the length of the data frame can be 7 bits or 8 bits, with or without parity,
and the stop bit length (1 or 2).
In operation mode 1, the length of the data frame can be 7 bits or 8 bits with a following
address-/data-bit instead of a parity bit. The stop bit length (1 or 2) can be selected.
The calculation formula for the bit length of a transmission/reception frame is:
Length = 1 + d + p + s
(d = number of data bits [7 or 8], p = parity [0 or 1],
s = number of stop bits [1 or 2])
Figure 17.7-1 shows the data format in the asynchronous mode.
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17.7 Operation of LIN-UART
MB90930 Series
Figure 17.7-1 Transmission/Reception Data Format (Operation Modes 0 and 1)
[Operation mode 0]
ST D0
D1 D2 D3 D4 D5 D6 D7 SP SP
ST D0
D1 D2 D3 D4 D5 D6 D7 SP
Without
P
Data 8-bit
ST D0
D1 D2 D3 D4 D5 D6 D7
P
SP SP
With P
ST D0
D1 D2 D3 D4 D5 D6 D7
P
ST D0
D1 D2 D3 D4 D5 D6 SP SP
ST D0
D1 D2 D3 D4 D5 D6 SP
ST D0
D1 D2 D3 D4 D5 D6
SP
Without
P
Data 7-bit
P
SP SP
With P
ST D0
D1 D2 D3 D4 D5 D6
P
SP
ST D0
D1 D2 D3 D4 D5 D6 D7 AD SP SP
ST D0
D1 D2 D3 D4 D5 D6 D7 AD SP
ST D0
D1 D2 D3 D4 D5 D6 AD SP SP
ST D0
D1 D2 D3 D4 D5 D6 AD SP
[Operation mode 1]
Data 8-bit
Data 7-bit
ST
SP
P
AD
: Start bit
: Stop mode
: arity
P it b
: Address/data bit
Note:
If BDS bit of th e se rial s tatus r egister (SSR) is se t t o "1" (MSB fir st), t he bit s tream
processes in the following order: D7, D6, ..., D1, D0 (P).
● Transmission operation
If the transmission data register empty flag bit (TDRE) of the serial status register (SSR) is "1",
transmission data is allowed to be written to the transmission data register (TDR). When data is
written, the TDRE flag goes "0". If the transmission operation is enabled (TXE of the serial
control register (SCR)=1), the data is written to the transmission shift register and the
transmission starts at the next clock cycle of the serial clock, beginning with the start bit.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag.
Note, that the initial value of the TDRE flag is "1", an interrupt will occur immediately after
"1" is written to TIE in this case.
When data length is set to 7 bits (CL=0), MSB bit of TDR becomes unused bit regardless of
setting for transfer direction selection bit (BDS) (LSB first or MSB first).
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Note:
As t he in itial v alue of transmission da ta empty flag bit (SS R: TD RE) is "1"
transmission interrupt is enabled (SSR: TIE=1), the interrupt occurs immediately.
if th e
● Reception operation
Reception operation is performed when it is enabled (SCR: RXE=1). If a start bit is detected, a
data frame is received according to the data format specified by the SCR. In case of errors, the
corresponding error flags are set (SSR: PE, ORE, FRE). After the reception of the data frame,
the data is transferred from the reception shift register to the reception data register (RDR) and
the receive data register full flag bit (SSR: RDRF) is set to "1". In this case, if the reception
interrupt request is enabled (SSR: RIE=1), the reception interrupt request is occurred.
When reading data after reception of one frame data, check the error flag state and read
reception data from the RDR register if the reception is performed normally. If the reception
error occurs, perform error processing.
When the reception data is read, the receive data register full flag bit (SSR: RDRF) is cleared
to "0".
When data length is set to 7 bits (CL=0), MSB bit of TDR becomes unused bit regardless of
setting for transfer direction selection bit (BDS) (LSB first or MSB first).
Note:
Only when the receive data register full flag bit (SSR: RDRF) is set to "1" an d no errors
have occurred (SSR: PE, ORE, FRE=0), the reception data register (RDR) contains valid
data.
● Used clock
Use the internal clock or external clock. Select the baud rate generator (SMR: EXT = 0 or 1,
OTO = 0) for desired baud rate.
● Stop bit
1- or 2-stop bit can be selected at the transmission. When 2-stop bit is selected, both stop bits
are detected at the reception.
When first stop bit is detected, the receive data register full flag bit (SSR: RDRF) is "1". Then,
when the start bit is not detected, the reception bus idle flag (ECCR:RBI) is set to "1",
indicating no reception operation.
● Error detection
In mode 0, the parity, overrun, and framing errors can be detected.
In mode 1, the overrun and framing errors can be detected, and the parity error cannot be
detected.
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17.7 Operation of LIN-UART
MB90930 Series
● Parity
Parity can set to add (transmission) or detect (reception) the parity bit.
The parity enable bit (SCR: PEN) specifies whether parity is enabled or disabled, and parity
selection bit (SCR: P) selects the even/odd parity.
In operation mode 1, the parity cannot be used.
Figure 17.7-2 Transmission Data when Parity Enabled
SIN
ST
SP
1 0 1 1 0 0 0 0 0
SOT
ST
Parity error generating at
received even parity
(SCR: P = 0)
SP
Even parity transmitting
(SCR: P = 0)
SP
Odd parity transmitting
(SCR: P = 1)
1 0 1 1 0 0 0 0 1
SOT
ST
1 0 1 1 0 0 0 0 0
Data
Parity
ST: Start bit, SP: Stop bit at parity ON (PEN=1)
Note: Parity cannot be used at operation mode 1.
● Data signal type
The data signal type is NRZ data format.
● Data transition method
The direction of the bit stream (LSB first or MSB first) is determined by BDS bit of the Serial
Status Register (SSR).
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
17.7.2
MB90930 Series
Operation in Synchronous Mode
(Operating Mode 2)
The clock synchronous transfer method is used for LIN-UART operation mode
2 (normal mode).
■ Operation in Synchronous Mode (Operation Mode 2)
● Transmission/Reception data format
In the synchronous mode, 8-bit data is transmitted/received with or without start/stop bits
depending the selection (ECCR: SSM). Also, when the start/stop bit is provided
(ECCR: SSM = 1), presence or absence of the parity bit can be selected (SCR: PEN).
Figure 17.7-3 illustrates the data format in the synchronous operation mode.
Figure 17.7-3 Transmission/Reception Data Format (Operation Mode 2)
Transmission/Reception data
(ECCR:SSM=0,SCR:PEN=0)
D0 D1 D2 D3 D4 D5 D6 D7
*
Transmission/Reception data
(ECCR:SSM=1,SCR:PEN=0)
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
Transmission/Reception data
(ECCR:SSM=1,SCR:PEN=1)
ST D0
P
SP
*
D1 D2 D3 D4 D5 D6 D7
SP
SP
*: Set to 2-stop bits (SCR: SBL = 1)
ST: Start bit
SP: Stop bit
P: Parity bit
● Clock inversion function
If the SCES bit of the extended status control register (ESCR) is set to "1", the serial clock is
inverted. Therefore, in slave mode LIN-UART samples the data at the falling edge of the
received serial clock. Note, that in master mode if SCES is set to "1", the mark level is "0".
Figure 17.7-4 Transfer Data Format with Clock Inversion
Mark level
Reception or transmission clock
(SCES = 0, CCO = 0):
Reception or transmission clock
(SCES = 1, CCO = 0):
Data stream (SSM = 1)
(No parity, 1 stop bit)
Mark level
ST
SP
Data frame
● Start/stop bits
If the SSM bit of the extended communication control register (ECCR) is set to "1", the start
and stop bits are added as in the asynchronous mode.
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MB90930 Series
● Clock supply
In clock synchronous mode (normal), the number of the transmit/reception bits must be equal
to the number of the clock cycles. When the start/stop bit is enabled, the number of the added
start/stop bits must be equal, as well.
When the serial clock output is enabled (SMR:SCKE=1) in master mode (ECCR:MS=0), a
synchronous clock is output automatically at transmission/reception. When the serial clock
output is disabled (SMR:SCKE=0) or the slave mode is selected (ECCR:MS=1), the clock for
each bit of transmit/reception data must be supplied from the outside.
While there is no transmission/reception, the clock signal must be kept at "H" as the mark
level.
If the SCDE bit of the ECCR register is "1", a delayed transmit clock is output as shown in
Figure 17.7-5. This function is required when the receiving device samples data at the rising or
falling edge of the clock.
Figure 17.7-5 Delayed Transmitting Clock Signal (SCDE=1)
Writing transmission
data
Reception data sample edge (SCES = 0)
Transmitting or
receiving clock
(normal)
Mark level
Mark level
Transmitting
clock (SCDE = 1)
Mark level
Transmission and
reception data
0
1
1
0
LSB
1
0
0
Data
1
MSB
If the SCES bit of the ESCR register is "1", the UART clock signal is inverted. Receiving data
is sampled at the falling edge of the clock. In this case, the serial data must be valid value at the
falling edge of the clock.
If the CCO bit of ESCR register is "1", the serial clock output of the SCKn pin is continuously
supplied in the master mode. In this mode, be sure to add the start/stop bits (SSM = 1) to
identify the start and end of data frame. Figure 17.7-6 shows the operation of this function.
Figure 17.7-6 Continuous Clock Supply (Mode 2)
Reception or transmission clock
(SCES = 0, CCO = 1):
Reception or transmission clock
(SCES = 1, CCO = 1):
Data stream (SSM = 1)
(No parity, 1 stop bit)
ST
SP
Data frame
● Error detection
If no start/stop bits are selected (ECCR: SSM = 0), only overrun errors are detected.
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MB90930 Series
● Communication settings for synchronous mode
For communication in the synchronous mode, following settings have to be done:
• Baud rate generator registers (BGR0/BGR1)
Set the desired value for the dedicated baud rate reload counter.
• Serial mode register (SMR)
MD1, MD0 : "10B" (Mode 2)
SCKE
: "1" . . . . . . for the dedicated baud rate reload counter
"0" . . . . . . for external clock input
SOE
: "1" . . . . . . for transmission and reception
"0" . . . . . . for reception only
• Serial control register (SCR)
RXE, TXE : set one of these bits to "1"
AD
: no address/data selection - don't care
CL
: automatically fixed to 8-bit data - don't care
CRE
: "1" to clear receive error flags. Suspend transmission and reception.
-- when SSM=0:
PEN, P, SBL: don't care
-- when SSM=1:
PEN : "1". . . . . . . if parity bit is added/detected, "0" . . . . . . . .if not
P
: "0". . . . . . . for even parity,
SBL : "1". . . . . . . for 2 stop bits,
"1" . . . . . . . .odd parity
"0" . . . . . . . .for 1 stop bit.
• Serial status register (SSR)
BDS : "0" . . . . . . for LSB first,
"1" . . . . . . . .for MSB first
RIE : "1" . . . . . . if reception interrupts are used;
"0" . . . . . . . .reception interrupts are
disabled.
TIE : "1" . . . . . . if transmission interrupts are used;"0" . . . . . . . .transmission interrupts
are disabled.
• Extended communication control register (ECCR)
SSM : "0" . . . . . . if no start/stop bits are desired (normal) "
"1" . . . . . . for adding start/stop bits (extended function)
MS : "0" . . . . . . for master mode (LIN-UART generates the serial clock)
"1" . . . . . . for slave mode (LIN-UART receives serial clock from the master
device)
Note:
To start the communication, write data to TDR register.
Only wh en receiving the da ta, disa ble th e serial ou tput (SMR: SOE = 0) an d writ e th e
dummy data to TDR.
By enabling the continuous clock and start/stop bits, the bi-directional communication the
same as the asynchronous mode is allowed.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
17.7.3
Operation with LIN Function (Operation Mode 3)
LIN-UART can be used either as LIN-Master or LIN-Slave in operation mode 3.
For this LIN function, setting the LIN-UART to mode 3 configures the data
format to 8N1-LSB-first format.
■ Operation in Asynchronous LIN Mode
● Operation as LIN master
In LIN mode, the master determines the baud rate of the whole bus, therefore slaves devices
have to synchronize to the master. Therefore, the desired baud rate remains fixed in master
operation after initialization.
Writing "1" into the LBR bit of the extended communication control register (ECCR) generates
a 13 bits to 16 bits time "L" level on the SOTn pin, which is the LIN synch break and the start
of a LIN message.
Thereby the TDRE flag of the serial status register (SSR) goes "0" and is reset to "1" (initial
value) after the break, and generates a transmission interrupt for the CPU (if TIE of SSR is
"1").
The length of the LIN break to be sent can be determined by the LBL1/LBL0 bits of the ESCR
as follows:
Table 17.7-2 LIN Break Length
LBL0
LBL1
Break length
0
0
13 bits
1
0
14 bits
0
1
15 bits
1
1
16 bits
The synch field is sent as byte data of 55H after the LIN break. To prevent a transmission
interrupt, the 55H can be written to the TDR just after writing the "1" to the LBR bit, although
the TDRE flag is "0".
● Operation as LIN slave
In LIN slave mode, LIN-UART has to synchronize to the master's baud rate. If reception is
disabled (RXE = 0), however, LIN break interrupt is enabled (LBIE = 1) LIN-UART will
generate a reception interrupt. In this case, the LBD bit of ESCR is set to "1".
Writing "0" to this bit clears the reception interrupt request flag.
For the calculation of the baud rate, the UART0 operation is explained as an example. When
UART0 detects first falling edge of synch field, set the internal signal inputted to the input
capture (ICU0) to "H" and start ICU0. This internal signal is set to "L" at fifth falling edge,
ICU0 must be set to the LIN mode (ICE01). Also, the ICU0 interrupt must be set to enable and
to detect both edges (ICS01). The time which the ICU0 input signal is "1" is the value
multiplied the baud rate by 8.
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MB90930 Series
Therefore, baud rate setting value is summarized as follows:
without free-run timer overflow : BGR value = {(b-a) × Fe/(8 × φ)} -1
with free-run timer overflow
: BGR value = {(max + b-a) × Fe/(8 × φ)}-1
max : the free-run timer maximum value
a : ICU data register value after the 1st interrupt
b : ICU data register value after the 2nd interrupt
φ is the machine clock frequency (MHz).
Fe is the external clock frequency (MHz).
When the internal baud rate generator is used(EXT=0),
it calculates as Fe=φ.
Note:
As shown in the LIN slave mode, when the BGR value newly calculated by sync field
generates ±15% or more baud rate error, do not set the baud rate.
For the correspondence between other LIN-UARTs and ICUs, see Section "10.3.1 16-bit Input
Capture" and "10.3.2 16-bit Free-run Timer".
● LIN Synch Break detection interrupt and flag
If a LIN synch break is detected in the slave mode, the LIN break detected flag (LBD) of the
ESCR is set to "1". This causes an interrupt, if the LIN break interrupt is enabled (LBIE=1).
Figure 17.7-7 LIN Synch Break Detection and Flag Set Timing
Serial clock cycle#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial
Clock
Serial input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs when RXE = 1
Reception interrupt occurs when RXE = 0
The figure above demonstrates the LIN synch break detection and flag set timing.
Note that the data framing error (FRE) flag bit of the SSR will cause a reception interrupt 2 bits
times earlier than the LIN break interrupt ("8N1"), so that it is recommended to set RXE to "0"
if a LIN break is expected.
LIN synch break detection is only supported in operation mode 3.
Figure 17.7-8 shows a typical start of a LIN message and the operation of the LIN-UART.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
Figure 17.7-8 UART Operation in LIN Slave Mode
Serial Clock
Serial input
(LIN bus)
LBR cleared by CPU
LBD
ICU input
(LSYN)
Synch break (at 14-bit setting)
Synch field
● LIN bus timing
Figure 17.7-9 LIN Bus Timing and LIN-UART Signals
No clock used
(calibration frame)
Prior serial clock
New calibrated serial clock
ICU count
LIN
bus
(SIN)
RXE
LBD
(IRQ0)
LBIE
ICU input
(LSYN)
IRQ(ICU)
RDRF
(IRQ0)
RIE
RDR read
by CPU
Enables reception interrupt
LIN break begins
LIN break detected and interrupt
IRQ clear by CPU (LBD → 0)
IRQ (ICU)
IRQ clear: Start ICU
IRQ(ICU)
IRQ clear: Calculate & set new baud rate
LBIE disable
Reception enable
Falling edge of start bit
Store one byte of received data to RDR
RDR read by CPU
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
17.7.4
MB90930 Series
Serial Pin Direct Access
LIN-UART allows the user to directly access to the transmission pin (SOTn) or
the reception pin (SINn).
■ LIN-UART Pin Direct Access
The LIN-UART provides the ability for the software to access directly to serial input or output
pin.
The status of the serial input pin (SINn) can be read by the serial input/output pin direct access
bit (ESCR:SIOP).
If direct write to the serial output pin (SOTn) is allowed (ESCR: SOPE = 1) when the serial
output is enabled (SMR: SOE = 1) after "0" or "1" is written to the SIOP bit of the ESCR
register, the SOTn value can be set arbitrarily.
In LIN mode, this function can be used for reading the transmitted data or for error handling
when the LIN bus line signal is physically incorrect.
Notes:
• Direct access is en abled only when the transmission is not ongoing (transmission shift
register is empty).
• Write a value to the se rial out put pin dir ect access bit (ESCR:SIOP) before enabling
the tr ansmission ( SMR: S OE = 1) . T his p revents th e signal of th e unexpected le vel
from being outputted because the SIOP bit retains the previous value.
• During a Read-Modify-Write (RMW) instruction, the SIOP bit returns the actual value of
the SOTn pin in the read cycle ins tead of the value of SINn during a normal read
instruction.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
17.7.5
Bidirectional Communication Function (Normal
Mode)
In operation mode 0 or 2, normal serial bidirectional communication is
available. Select operation mode 0 for asynchronous communication and
operation mode 2 for synchronous communication.
■ Bidirectional Communication Function
Figure 17.7-10 shows the settings to operate LIN-UART in normal mode (operation mode 0 or
2).
Figure 17.7-10 Settings for LIN-UART Operation Modes 0 and 2
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCRn, SMRn
PEN
P
SBL CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
Mode 0
Mode 2
SSRn, TDRn/RDRn
Mode 0
Mode 2
ESCRn, ECCRn
Set conversion data (during writing)
Retain reception data (during reading)
PE ORE FRE RDRF TDRE BDS RIE TIE
LBIE
LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 0
Mode 2
−
LBR MS SCDE SSM
−
: Used bit
: Unused bit
: Set "1"
: Set "0"
: Bit used if SSM = 1 (Synchronous start-/stop-bit mode)
: Bit automatically set correctly
RBI TBI
n = 0, 1, 2, 3
● Inter-CPU connection
Two CPUs are interconnected as shown in Figure 17.7-11.
Figure 17.7-11 Connection Example of LIN-UART Mode 2 Bidirectional Communication
SOT
SIN
SCK
SOT
Output
Input
CPU-1 (Master)
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SIN
SCK
CPU-2 (Slave)
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MB90930 Series
● Communication procedure
Communication starts at arbitrary timing from the transmission side when the transmission data
is provided. When the transmission data is received at the reception side, ANS (per one byte in
example) is returned periodically. Figure 17.7-12 shows an example of the bidirectional
communication flowchart.
Figure 17.7-12 Example of Bidirectional Communication Flowchart
(Transmission side)
(Reception side)
Start
Start
Operation mode setting
(0 or 2)
Operation mode setting (match
with the transmission side)
Set 1 byte data to TDR
and communicate
Data
transmission
NO
NO
Read and process the
reception data
478
YES
Reception
data exists
YES
Reception
data exists
Read and process the
reception data
Data
transmission
(ANS)
1 byte data transmission
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
17.7.6
Master/Slave Type Communication Function
(Multiprocessor Mode)
LIN-UART communication with multiple CPUs connected in master/slave mode
is available for both master or slave systems in the operation mode 1.
■ Master/Slave Type Communication Function
Figure 17.7-13 shows the settings to operate LIN-UART in multiprocessor mode (operation
mode 1).
Figure 17.7-13 Settings for LIN-UART Operation Mode 1
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCRn, SMRn
PEN
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
Mode 1
SSRn, TDRn/RDRn
PE ORE FRE RDRF TDRE BDS RIE
Set conversion data (during writing)
Retain reception data (during reading)
TIE
Mode 1
ESCRn, ECCRn
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
−
LBR MS SCDE SSM
−
RBI
TBI
Mode 1
: Used bit
: Unused bit
: Set to "1"
: Set to "0"
: Bit automatically set correctly
n = 0, 1, 2, 3
● Inter-CPU connection
As shown in Figure 17.7-14, a communication system consists of one master CPU and multiple
slave CPUs connected to two communication lines. LIN-UART can be used for the master or
slave CPU.
Figure 17.7-14 Connection Example of LIN-UART Master/Slave Communication
SOT
SIN
Master CPU
SOT
SIN
Slave CPU# 0
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SOT
SIN
Slave CPU# 1
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CHAPTER 17 LIN-UART
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MB90930 Series
● Function selection
Select the operation mode and data transfer mode for master-slave communication as shown in
Table 17.7-3.
Table 17.7-3 Selection of the Master/Slave Communication Function
Operation mode
Address transmission/
reception
Data transmission/
reception
Master
CPU
Slave
CPU
Mode 1
(AD bit
Transmission/
Reception)
Mode 1
(AD bit
Transmission/
Reception)
Data
Parity
Synchronous
method
Stop Bit
Bit direction
None
Asynchronous
1 bit or
2 bits
LSB first or
MSB-first
AD=1
+
7 or 8-bit address
AD=0
+
7 or 8-bit data
● Communication procedure
When the master CPU transmits address data, communication starts. The AD bit in the address
data is set to "1", and the communication destination slave CPU is selected. Each slave CPU
checks the address data using a program. When the address data indicates the address assigned
to a slave CPU, the slave CPU communicates with the master CPU.
Figure 17.7-15 shows a flowchart of master-slave communication (multiprocessor mode)
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
Figure 17.7-15 Master/Slave Communication Flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set to operation mode 1
Set to operation mode 1
Set the SINn pin as the serial
data input
Set the SOTn pin as the
serial data output
Set the SINn pin as the serial
data input
Set the SOTn pin as the
serial data output
Set 7 or 8 data bits
Set 1 or 2 stop bits
Set 7 or 8 data bits
Set 1 or 2 stop bits
Set "1" in AD bit
Enable transmission/
reception
Enable transmission/
reception
Receive byte
Send address to slave
AD bit = 1
NO
YES
Slave address
match?
Set "0" in AD bit
YES
Communicate with
master CPU
Communicate with slave
CPU
Terminate
communication?
NO
Terminate
communication?
NO
NO
YES
YES
Communicate
with another slave
CPU
NO
YES
Disable transfer/reception
End
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
17.7.7
MB90930 Series
LIN Communication Function
LIN-UART communication with LIN devices is available for both LIN master or
LIN slave systems.
■ LIN Master/Slave Type Communication Function
The settings shown in Figure 17.7-16 are required to operate LIN-UART in LIN
communication mode (operation mode 3).
Figure 17.7-16 Settings for LIN-UART in Operation Mode 3 (LIN)
PEN
P
SBL CL
AD CRE RXE TXE MD1 MD0 OTO EXT
REST UPCL SCKE
SOE
Mode 3
PE ORE FRE
RDRF TDRE
Set conversion data (during writing)
Retain reception data (during reading)
BDS RIE TIE
Mode 3
LBIE LBD LBL1 LBL0 SOPE
SIOP
CCO SCES
−
LBR MS
SCDE SSM
−
RBI TBI
Mode 3
: Used bit
: Unused bit
: Set to "1"
: Set to "0"
: Bit automatically set correctly
n = 0, 1, 2, 3
● LIN device connection
Figure 17.7-17 shows a communication system of one LIN-master device and a LIN-slave
device.
LIN-UART can operate both as LIN-master or LIN-slave.
Figure 17.7-17 Connection Example of LIN-bus System
SOT
SOT
LIN bus
SIN
LIN master
482
SIN
Transceiver
Transceiver
FUJITSU MICROELECTRONICS LIMITED
LIN slave
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
17.7.8
Sample Flowcharts for LIN-UART in LIN
Communication
(Operation Mode 3)
This section shows sample flowcharts for LIN-UART in LIN communication.
■ LIN Master Device
Figure 17.7-18 LIN Master Flowchart
Start
Initial setting:
Set to operation mode 3
Serial data output enabled, Baud rate setting
Synch break length setting
TXE = 1, TIE = 0, RXE = 1, RIE = 1
NO
Message?
(Reception)
YES
Wake up?
(0x80 reception)
NO
YES
Data field
reception?
RDRF = 1
Reception interrupt
RXE = 0
Synch break interrupt enabled
Synch break transmission:
ECCR: LBR = 1
Synch field transmission:
TDR = 0x55
(Transmission)
RDRF = 1
Reception interrupt
Data 1 reception*1
YES
NO
Data N reception
Set transmission data 1
TDR = Data 1
Enables transmission
interrupts
TDRE = 1
Transmission
interrupt
*1
Set transmission data N
TDR = Data N
Disables transmission
interrupts
LBD = 1
Synch break interrupt
RDRF = 1
Reception interrupt
Enables reception
LBD = 0
Disable synch break
interrupts
Data 1 reception*1
Read data 1
RDRF = 1
Reception interrupt
RDRF = 1
Reception interrupt
Synch field reception *1
Identify field set: TDR = lD
Data N reception*1
Read data N
RDRF = 1
Reception interrupt
ID field reception*1
No error?
NO
Error processing*2
YES
*1: If an error occurs, process the error.
*2: • When FRE and ORE are "1", write "1" to SCR: CRE bit to clear the error flag.
• If the ESCR: LBD bit is set to "1", execute the UART reset.
Note: Detect an error in each process and handle it appropriately.
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CHAPTER 17 LIN-UART
17.7 Operation of LIN-UART
MB90930 Series
■ LIN Slave Device
Figure 17.7-19 LIN Slave Flowchart
Start
Initial setting:
Set to operation mode 3
Serial data output enabled
TXE = 1, TIE = 0, RXE = 0, RIE = 1
Connection with LIN-UART and ICU
Disables reception
ICU interrupt enabled
Synch break interrupt
enabled
LBD = 1
Synch break interrupt
Synch break detection clear
ESCR: LBD = 0
Disable synch break interrupts
(Reception)
YES
Data field
reception?
RDRF = 1
Reception interrupt
Data N reception*1
Read ICU data
Clear ICU interrupt flag
ICU interrupt
(Transmission)
RDRF = 1
Reception interrupt
Data 1 reception*1
ICU interrupt
NO
Disables reception
Set transmission data 1
TDR = Data 1
Enables transmission
interrupts
TDRE = 1
Transmission
interrupt
Set transmission data N
TDR = Data N
Disables transmission
interrupts
RDRF = 1
Reception interrupt
Read ICU data
Baud rate adjustment
Enables reception
Clear ICU interrupt flag
ICU interrupt disabled
Data 1 reception*1
Read data 1
RDRF = 1
Reception interrupt
RDRF = 1
Reception interrupt
Data N reception*1
Read data N
Disables reception
Identify field reception*1
Sleep
mode?
NO
YES
Wake up
reception?
YES
No error?
NO
Error processing*2
YES
NO
Wake up
transmission?
YES
NO
Wake up code transmission
*1: If an error occurs, process the error.
*2: • When FRE and ORE are "1", write "1" to SCR: CRE bit to clear the error flag.
• If the ESCR: LBD bit is set to "1", execute the UART reset.
Note: Detect an error in each process and handle it appropriately.
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17.8
Notes on Using LIN-UART
CHAPTER 17 LIN-UART
17.8 Notes on Using LIN-UART
Notes on using LIN-UART are given below.
■ Notes on Using LIN-UART
● Enabling operations
The LIN-UART has the TXE (transmission) and RXE (reception) enable bit in the serial
control register (SCR) for transmission and reception, respectively. Both, transmission and
reception operations, must be enabled before the transfer starts because they have been
disabled as the default value (initial value). Also, you can disable these operations to stop
transfer as required.
● Communication mode setting
Set the communication mode while the LIN-UART is not operating. If the mode is set during
transmission/reception, the transmitted/received data is not guaranteed.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR: TDRE) is "1" (no
transmission data and transmission data write enable state). A transmission interrupt request is
generated as soon as the transmission interrupt request is enabled (SSR: TIE=1). Be sure to set
the TIE flag to "1" after setting the transmission data to avoid an immediate interrupt.
● Changing operation settings
It is recommended to reset LIN-UART after changing operation settings, particularly if (for
example) start-/stop-bits added to or removed from the data format.
The correct operation settings are not guaranteed even if you reset the LIN-UART
(SMR:UPCL=1) at the same time as setting the LIN-UART serial mode register (SMR).
Therefore, it is recommended to reset the LIN-UART (SMR:UPCL=1) once again, after setting
the bit in LIN-UART serial mode register (SMR).
● Using LIN functions
The LIN features are available in mode 3, but using mode 3 sets the UART data format
automatically to LIN format (8-bit length, no parity, one stop bit, and LSB first).
While the length of LIN break transmit bit is variable, the detection bit length is fixed to 11
bits.
● LIN slave settings
When starting LIN slave mode, be sure to set the baud rate before receiving the LIN synch
break in order to ensure that at least 13 bits of the LIN synch break is detected.
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CHAPTER 17 LIN-UART
17.8 Notes on Using LIN-UART
MB90930 Series
● Software compatibility
Although this LIN-UART is similar to the old FJ-UART, it is not software compatible to them.
The programming models may be the same, but the structure of the registers differ.
Furthermore, the setting of the baud rate is now determined by a reload value instead of
selecting a predefined value.
● Bus idle function
The bus idle function cannot be used in synchronous mode 2.
● AD bit (serial control register (SCR): address/data type select bit)
Special care has to be taken when using the AD bit.
The AD bit is used to select the address/data for transmission in write operation, and to read the
AD bit received last in read operation. Internally, the received and the transmitted value are
stored in different registers.
With Read-Modify-Write (RMW) instructions, the transmitted value is read. This can lead to a
wrong value in the AD bit, when one of the other bits in the same register is accessed by an
instruction of this kind.
Therefore, this bit should be written by the last register access before transmission.
Alternatively, using byte wise access and writing the correct values for all bits at once avoids
this problem.
● Software reset of LIN-UART
When TXE bit of serial control register (SCR) is "0", execute LIN-UART software reset (SMR:
UPCL = 1).
● Synch break detection
In mode 3 (LIN operation), the LBR bit in the ESCR register is set to "1" if the serial input is
kept at "0" for more than 11-bit time (synch break detection). Then the LIN-UART waits for
the following synch field to be received. If the LIN-UART is set into this state for other
reasons than the synch break, it recognizes that synch break is inputted (LBD = 1) and waits for
synch field.
In this case, execute the LIN-UART reset (SMR: UPCL = 1).
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CHAPTER 18
CAN CONTROLLER
This chapter describes an overview of the CAN
controller and its functions.
18.1 Features of CAN Controller
18.2 Block Diagram of CAN Controller
18.3 Classification of CAN Controller Registers
18.4 CAN Controller Transmission
18.5 CAN Controller Reception
18.6 Using CAN Controller
18.7 Procedure of Transmission via Message Buffer (x)
18.8 Procedure of Reception Via Message Buffer (x)
18.9 Specifying the Multi-level Message Buffer Configuration
18.10 CAN WAKE UP Function
18.11 Precautions When Using CAN Controller
18.12 Sample Program of CAN
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CHAPTER 18 CAN CONTROLLER
18.1 Features of CAN Controller
18.1
MB90930 Series
Features of CAN Controller
The CAN controller is a module that is integrated into a 16-bit microcomputer
(F2MC-16LX). CAN (Controller Area Network) is the standard protocol used for
serial communication between controllers in automobiles, and is widely
applied in the industrial fields.
■ Features of CAN Controller
The CAN controller has the following features:
• Conforms to CAN specifications version 2.0, Part A and B.
Supports send/receive operations in the standard and extended frame formats.
• Supports data frame transmission based on remote frame reception.
• 16 send/receive message buffers
29-bit ID and 8-byte data
Multi-level message buffer structure
• Supports full-bit compare, full-bit mask, and partial-bit mask filtering.
Provides two acceptance mask registers in either the standard or extended frame format.
• Bit speed is programmable between 10 kbps to 1 Mbps (Using 1 Mbps requires a minimum
8 MHz machine clock).
• CAN WAKE UP function
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CHAPTER 18 CAN CONTROLLER
18.2 Block Diagram of CAN Controller
MB90930 Series
18.2
Block Diagram of CAN Controller
Figure 18.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 18.2-1 Block Diagram of CAN Controller
F2MC-16LX bus
Clock
PSC
PR
PH
RSJ
TOE
TS
RS
CSR HALT
NIE
NT
NS1.0
TQ (operation clock)
Prescaler 1 to 64
frequency division
Bit timing generation
SYNC, TSEG1, TSEG2
BTR
Error
control
RTEC
Send/receive
sequencer
BVALR
TREQR
IDLE, SUSPND,
send, receive,
ERR, OVRLD
Bus
state
machine
Node status
change
interrupt
Node status change
interrupt generation
TBFX clear
Send buffer
X judgment
TBFX
Error
frame
generation
AcceptData
ance filter
counter
control
Overload
frame
generation
TDLC RDLC IDSEL
TBFX
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
TIER
RCR
RIER
RPTRR
ROVRR
TBFx, set, clear
Receive
complete
interrupt
Transmission
complete interrupt
generation
RBFx, set
Transmission
complete
interrupt
RBFx, TBFx, set, clear
RBFx, set
CRCER
RDLC
Receive complete
interrupt generation
AMR1
IDR0 to 15,
DLCR0 to 15,
DTR0 to 15,
RAM
ACK
CRC
generation generation
TDLC
CRC generation/
error check
Receive shift
register
Destuffing/
stuffing
error check
ARBLOST
0
1
STFER
IDSEL
AMSR
AMR0
Stuffing
Send shift
register
RFWTR
Acceptance
filter
RAM address
generation
BITER
Receive buffer
x judgment
ACKER
RBFx,
FRMER
Arbitration
check
Bit error
check
Verify error
check
Format error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3
MB90930 Series
Classification of CAN Controller Registers
The CAN controller registers can be classified into the following 4 types:
• General control register
• Message buffer control register
• Message buffer
• CAN WAKE UP control register
■ General Control Registers
The following 4 types of general control registers are provided:
• Control status register (CSR)
• Last event indication register (LEIR)
• Receive and transmit error counters (RTEC)
• Bit timing register (BTR)
Table 18.3-1 lists the general control registers.
Table 18.3-1 List of General Control Registers
Address
Abbreviation
Access
Initial Value
Control status register
CSR
(R/W, R)
00---000B
0----0-1B
Last event indication register
LEIR
(R/W)
-------- B
000-0000B
Receive and transmit error counters
RTEC
(R)
00000000B
00000000B
Bit timing register
BTR
(R/W)
-1111111B
11111111B
Register
CAN1
003D00H
003D01H
003D02H
003D03H
003D04H
003D05H
003D06H
003D07H
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
■ Message Buffer Control Registers
The following 14 types of message buffer control registers are provided:
• Message buffer valid register (BVALR)
• IDE register (IDER)
• Transmission request register (TREQR)
• Transmission RTR register (TRTRR)
• Remote frame receive wait register (RFWTR)
• Transmission cancel register (TCANR)
• Transmission complete register (TCR)
• Transmission interrupt enable register (TIER)
• Receive complete register (RCR)
• Remote request receive register (RRTRR)
• Receive overrun register (ROVRR)
• Receive interrupt enable register (RIER)
• Acceptance mask selection register (AMSR)
• Acceptance mask registers 0 and 1 (AMR0, AMR1)
Table 18.3-2 lists message buffer control registers.
Table 18.3-2 List of Message Buffer Control Registers (1 / 2)
Address
CAN1
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
(R/W)
00000000B
00000000B
Transmission request register
TREQR
(R/W)
00000000B
00000000B
Transmission cancel register
TCANR
(W)
00000000B
00000000B
Transmission complete register
TCR
(R/W)
00000000B
00000000B
Receive complete register
RCR
(R/W)
00000000B
00000000B
Remote request receive register
RRTRR
(R/W)
00000000B
00000000B
Receive overrun register
ROVRR
(R/W)
00000000B
00000000B
RIER
(R/W)
00000000B
00000000B
Register
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
Receive interrupt enable register
00007FH
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-2 List of Message Buffer Control Registers (2 / 2)
Address
CAN1
Abbreviation
Access
Initial Value
IDER
(R/W)
XXXXXXXXB
XXXXXXXXB
Transmission RTR register
TRTRR
(R/W)
00000000B
00000000B
Remote frame receive wait
register
RFWTR
(R/W)
XXXXXXXXB
XXXXXXXXB
TIER
(R/W)
00000000B
00000000B
Register
003D08H
IDE register
003D09H
003D0AH
003D0BH
003D0CH
003D0DH
003D0EH
003D0FH
Transmission interrupt enable
register
003D10H
003D11H
003D12H
Acceptance mask selection
register
XXXXXXXXB
XXXXXXXXB
AMSR
(R/W)
XXXXXXXXB
XXXXXXXXB
003D13H
003D14H
XXXXXXXXB
XXXXXXXXB
003D15H
Acceptance mask register 0
AMR0
(R/W)
003D16H
XXXXX---B
XXXXXXXXB
003D17H
003D18H
XXXXXXXXB
XXXXXXXXB
003D19H
Acceptance mask register 1
AMR1
(R/W)
003D1AH
XXXXX---B
XXXXXXXXB
003D1BH
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
■ Message Buffers
The following 3 types of message buffers are provided:
• ID register x (x = 0 to 15) (IDRx)
• DLC register x (x = 0 to 15) (DLCRx)
• Data register x (x = 0 to 15) (DTRx)
Table 18.3-3, Table 18.3-4, and Table 18.3-5 list message buffers: ID register, DLC register,
and data register respectively.
Table 18.3-3 List of Message Buffers (ID Register) (1 / 3)
Address
CAN1
003B00H to
003B1FH
Register
Abbreviation
Access
Initial Value
General-purpose RAM
--
(R/W)
XXXXXXXXB to
XXXXXXXXB
003B20H
XXXXXXXXB
XXXXXXXXB
003B21H
ID register 0
IDR0
(R/W)
003B22H
XXXXX---B
XXXXXXXXB
003B23H
003B24H
XXXXXXXXB
XXXXXXXXB
003B25H
ID register 1
IDR1
(R/W)
003B26H
XXXXX---B
XXXXXXXXB
003B27H
003B28H
XXXXXXXXB
XXXXXXXXB
003B29H
ID register 2
IDR2
(R/W)
003B2AH
XXXXX---B
XXXXXXXXB
003B2BH
003B2CH
XXXXXXXXB
XXXXXXXXB
003B2DH
ID register 3
IDR3
(R/W)
003B2EH
XXXXX---B
XXXXXXXXB
003B2FH
003B30H
XXXXXXXXB
XXXXXXXXB
003B31H
ID register 4
IDR4
(R/W)
003B32H
XXXXX---B
XXXXXXXXB
003B33H
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-3 List of Message Buffers (ID Register) (2 / 3)
Address
CAN1
Register
Abbreviation
Access
003B34H
XXXXXXXXB
XXXXXXXXB
003B35H
ID register 5
IDR5
(R/W)
003B36H
XXXXX---B
XXXXXXXXB
003B37H
003B38H
XXXXXXXXB
XXXXXXXXB
003B39H
ID register 6
IDR6
(R/W)
003B3AH
XXXXX---B
XXXXXXXXB
003B3BH
003B3CH
XXXXXXXXB
XXXXXXXXB
003B3DH
ID register 7
IDR7
(R/W)
003B3EH
XXXXX---B
XXXXXXXXB
003B3FH
003B40H
XXXXXXXXB
XXXXXXXXB
003B41H
ID register 8
IDR8
(R/W)
003B42H
XXXXX---B
XXXXXXXXB
003B43H
003B44H
XXXXXXXXB
XXXXXXXXB
003B45H
ID register 9
IDR9
(R/W)
003B46H
XXXXX---B
XXXXXXXXB
003B47H
003B48H
XXXXXXXXB
XXXXXXXXB
003B49H
ID register 10
IDR10
(R/W)
003B4AH
XXXXX---B
XXXXXXXXB
003B4BH
003B4CH
XXXXXXXXB
XXXXXXXXB
003B4DH
ID register 11
IDR11
(R/W)
003B4EH
XXXXX---B
XXXXXXXXB
003B4FH
494
Initial Value
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-3 List of Message Buffers (ID Register) (3 / 3)
Address
CAN1
Register
Abbreviation
Access
003B50H
XXXXXXXXB
XXXXXXXXB
003B51H
ID register 12
IDR12
(R/W)
003B52H
XXXXX---B
XXXXXXXXB
003B53H
003B54H
XXXXXXXXB
XXXXXXXXB
003B55H
ID register 13
IDR13
(R/W)
003B56H
XXXXX---B
XXXXXXXXB
003B57H
003B58H
XXXXXXXXB
XXXXXXXXB
003B59H
ID register 14
IDR14
(R/W)
003B5AH
XXXXX---B
XXXXXXXXB
003B5BH
003B5CH
XXXXXXXXB
XXXXXXXXB
003B5DH
ID register 15
IDR15
(R/W)
003B5EH
XXXXX---B
XXXXXXXXB
003B5FH
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Initial Value
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-4 List of Message Buffers (DLC Register) (1 / 2)
Address
CAN1
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
(R/W)
---- XXXXB
DLC register 1
DLCR1
(R/W)
---- XXXXB
DLC register 2
DLCR2
(R/W)
---- XXXXB
DLC register 3
DLCR3
(R/W)
---- XXXXB
DLC register 4
DLCR4
(R/W)
---- XXXXB
DLC register 5
DLCR5
(R/W)
---- XXXXB
DLC register 6
DLCR6
(R/W)
---- XXXXB
DLC register 7
DLCR7
(R/W)
---- XXXXB
DLC register 8
DLCR8
(R/W)
---- XXXXB
DLC register 9
DLCR9
(R/W)
---- XXXXB
DLC register 10
DLCR10
(R/W)
---- XXXXB
DLC register 11
DLCR11
(R/W)
---- XXXXB
DLC register 12
DLCR12
(R/W)
---- XXXXB
003B60H
003B61H
003B62H
003B63H
003B64H
003B65H
003B66H
003B67H
003B68H
003B69H
003B6AH
003B6BH
003B6CH
003B6DH
003B6EH
003B6FH
003B70H
003B71H
003B72H
003B73H
003B74H
003B75H
003B76H
003B77H
003B78H
003B79H
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-4 List of Message Buffers (DLC Register) (2 / 2)
Address
CAN1
Register
Abbreviation
Access
Initial Value
DLC register 13
DLCR13
(R/W)
---- XXXXB
DLC register 14
DLCR14
(R/W)
---- XXXXB
DLC register 15
DLCR15
(R/W)
---- XXXXB
003B7AH
003B7BH
003B7CH
003B7DH
003B7EH
003B7FH
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-5 List of Message Buffers (Data Register)
Address
Register
Abbreviation
Access
Initial Value
003B80H to
003B87H
Data register 0 (8 bytes)
DTR0
(R/W)
XXXXXXXXB to
XXXXXXXXB
003B88H to
003B8FH
Data register 1 (8 bytes)
DTR1
(R/W)
XXXXXXXXB to
XXXXXXXXB
003B90H to
003B97H
Data register 2 (8 bytes)
DTR2
(R/W)
XXXXXXXXB to
XXXXXXXXB
003B98H to
003B9FH
Data register 3 (8 bytes)
DTR3
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BA0H to
003BA7H
Data register 4 (8 bytes)
DTR4
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BA8H to
003BAFH
Data register 5 (8 bytes)
DTR5
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BB0H to
003BB7H
Data register 6 (8 bytes)
DTR6
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BB8H to
003BBFH
Data register 7 (8 bytes)
DTR7
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BC0H to
003BC7H
Data register 8 (8 bytes)
DTR8
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BC8H to
003BCFH
Data register 9 (8 bytes)
DTR9
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BD0H to
Data register 10 (8 bytes)
003BD7H
DTR10
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BD8H to
Data register 11 (8 bytes)
003BDFH
DTR11
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BE0H to
Data register 12 (8 bytes)
003BE7H
DTR12
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BE8H to
Data register 13 (8 bytes)
003BEFH
DTR13
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BF0H to
Data register 14 (8 bytes)
003BF7H
DTR14
(R/W)
XXXXXXXXB to
XXXXXXXXB
003BF8H to
Data register 15 (8 bytes)
003BFFH
DTR15
(R/W)
XXXXXXXXB to
XXXXXXXXB
CAN1
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.1
Control Status Register (CSR)
Bit operation instructions (read-modify-write instructions) cannot be used for
the control status register (CSR).
■ Bit Configuration of Control Status Register (CSR)
Figure 18.3-1 shows the bit configuration of the control status register (CSR).
Figure 18.3-1 Bit Configuration of Control Status Register (CSR)
Address:
003D01H (CAN1)
Address:
003D00H (CAN1)
R:
R/W :
-:
bit15
TS
R
0
bit14
RS
R
0
bit13
−
−
−
bit12
−
−
−
bit11
−
−
−
bit10
NT
R/W
0
bit9
NS1
R
0
bit8
NS0
R
1
<- Initial value
bit7
TOE
R/W
0
bit6
−
−
−
bit5
−
−
−
bit4
−
−
−
bit3
−
−
−
bit2
NIE
R/W
0
bit1
−
−
−
bit0
HALT
R/W
1
<- Initial value
Read only
Readable/Writable
Undefined
[bit15] TS: Transmission status bit
This bit indicates whether a message is being sent.
• 0: No message being sent.
• 1: Message being sent.
This bit is also "0" when an error frame and an overload frame are being sent.
[bit14] RS: Receive status bit
This bit indicates whether a message is being received.
• 0: No message being received.
• 1: Message being received.
This bit is "1" while a message exists on the bus. Therefore, this bit is also "1" when a
message is being sent. This bit does not necessarily indicate whether a receive message
passed through an acceptance filter. Consequently, when this bit is "0", it indicates that the
bus operation is stopped (HALT = 0), the bus is in intermission/bus idle state, or an error/
overload frame exists on the bus.
[bit10] NT: Node status transition flag
This bit becomes "1" when the node status changes incrementally, and also when it changes
from bus-off to error active.
In other words, the NT bit is set to "1" when the node status changes as follows. The values
in parentheses show the values of the NS1 and NS0 bits.
• From error active ("00B") to warning ("01B")
• From warning ("01B") to error passive ("10B")
• From error passive ("10B") to bus-off ("11B")
• From bus-off ("11B") to error active ("00B")
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When the node status transition interrupt enable bit (NIE) is "1", an interrupt is generated.
Writing "0" to the NT bit sets the bit to "0". Writing "1" to this bit is ignored. "1" is read
from this bit when a read-modify-write (RMW) instruction is executed.
[bit9, bit8] NS1, NS0: Bit1 and bit0 of node status
The NS1 and NS0 bits indicate the current node status.
Table 18.3-6 shows this relationship.
Table 18.3-6 Relationship Between NS1/NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (Error active)
1
0
Error passive
1
1
Bus-off
Note:
Warning ( error a ctive) is con sidered as pa rt o f error a ctive b y th e explanation of n ode
status in CAN Specifications 2.0B, b ut it indicat es t hat th e re ceive or t ransmit error
counter exceeded 96. Figure 18.3-2 shows a diagram of node status transition.
Figure 18.3-2 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Transmit error counter
REC≥96
or
TEC≥96
REC≥128
or
TEC≥128
Error
passive
500
Warning
Error
active
After "0" is written to the HALT bit in
the register (SCR), 11 consecutive bits
of high level (recessive bits) are input
to the receive input pin (RX) 128 times.
REC<96
and
TEC<96
REC<128
or
TEC<128
TEC≥256
Bus-off
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18.3 Classification of CAN Controller Registers
MB90930 Series
[bit7] TOE: Transmission output enable bit
Writing "1" to the TOE bit switches the general-purpose port pin to the CAN controller send
pin.
• 0: General-purpose port pin
• 1: CAN controller send pin
[bit2] NIE: Node status transition interrupt enable bit
The NIE bit enables or disables node status transition interrupts (when NT = 1).
• 0: Disables node status transition interrupts.
• 1: Enables node status transition interrupts.
[bit0] HALT: Bus operation stop bit
The HALT bit sets or releases bus operation stop, or indicates the state of the bus operation.
When reading
• 0: Indicates that the bus is in operation.
• 1: Indicates that bus operation is stopped.
When writing
• 0: Releases bus operation stop.
• 1: Sets bus operation stop.
Note:
Make sure that the HALT bit is "1" before you write "0" to this bit during bus-off.
Reference program example:
switch(IO_CANCT0.CSR.bit.NS)
{
case0:/*error active*/
break;
case1:/*warning*/
break;
case2:/*error passive*/
break;
default:/*bus off*/
for(i=0;(i<=500)&&(IO_CANCT0.CSR.bit.HALT==0);i++);
IO_CANCT0.CSR.word=0x0084;/*HALT=0*/
break;
}
Note: Variable i is used as a fail-safe measure.
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18.3 Classification of CAN Controller Registers
MB90930 Series
■ Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or releases bus operation stop, or indicates the state of the bus
operation.
● Condition to set bus operation stop (HALT = 1)
Bus operation stop (HALT = 1) is set under the following three conditions:
• After hardware reset
• When the node status changes to bus-off
• When "1" is written to HALT
Notes:
• Bus operation must be stopped by writing "1" t o HALT before F 2MC-16LX enters the
low-power consumption m ode ( stop m ode, clock m ode, o r hardware standby mode). If
"1" is written to HA
LT during transmission, bus operation will stop after the
transmission is completed (H ALT = 1) . If "1" is writ ten to HAL T d uring re ception, bu s
operation st ops imm ediately (HALT = 1 ). I f a r eceive m essage is being st ored in
message buffer (x), bus operation will stop after the message is stored (HALT = 1).
• Always read HALT bit to check whether bus operation has stopped.
● Condition to release bus operation stop (HALT = 0)
Writing "0" to the HALT bit releases bus operation stop.
Notes:
• The release of bus operation stop which was set after hardware reset or by writing "1"
to HALT will be performed after "0" is written to HALT and then 11 cons ecutive bits of
high level (recessive bits) are input to the receive input pin (RX).
• The release of bus operation stop which was set by the change in the node status to
bus-off will be performed after "0" is written to HALT and then 11 c onsecutive bits of
high level (recessive bits) are input to the receive input pin (RX) 128 times.
Then, the values of bot h t he t ransmit an d rece ive error coun ters rea ch "0", and the
node status changes to error active.
• Make sure that the HALT bit is "1" before you write "0" to this bit during bus-off.
■ State between Bus Operation Stops (HALT = 1)
While bus operation is stopped:
• All bus operation is disabled including sending and receiving.
• The transmission output pin (TX) outputs high level (recessive bit).
• The values of other registers and error counters do not change.
Note:
The bit timing register (BTR) must be set while bus operation is stopped (HALT = 1).
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.2
Last Event Indication Register (LEIR)
The last event indication register (LEIR) indicates the last event.
NTE, TCE and RCE are exclusive. When one of the last event bits is set to "1",
other bits are set to "0".
■ Bit Configuration of Last Event Indication Register (LEIR)
Figure 18.3-3 shows the bit configuration of the last event indication register (LEIR).
Figure 18.3-3 Bit Configuration of Last Event Indication Register (LEIR)
Address:
003D02H (CAN1)
R/W :
-:
bit7
NTE
R/W
0
bit6
TCE
R/W
0
bit5
RCE
R/W
0
bit4
−
−
−
bit3
bit2
bit1
bit0
MBP3 MBP2 MBP1 MBP0
R/W
R/W
R/W
R/W
0
0
0
0
<- Initial value
Readable/Writable
Undefined
[bit7] NTE: Node status transition event bit
When the NTE bit is "1", it indicates that node status transition was the last event.
The NTE bit is set to "1" simultaneously with the NT bit in the control status register (CSR).
The NTE bit is set to "1" independently of the setting of the node status transition interrupt
enable (NIE) bit in CSR.
Writing "0" to the NTE bit sets the bit to "0". Writing "1" to the NTE bit is ignored.
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
[bit6] TCE: Transmission complete event bit
When the TCE bit is "1", it indicates that transmission completion was the last event.
The TCE bit is set to "1" simultaneously with any 1 bit in the transmission complete register
(TCR).The TCE bit is set to "1" independently of the bit setting of the transmission interrupt
enable register (TIER).
Writing "0" to the TCE bit sets the bit to "0". Writing "1" to the TCE bit is ignored.
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the number of the
message buffer for which a send operation was completed.
[bit5] RCE: Receive complete event bit
When the RCE bit is "1", it indicates that reception completion was the last event.
The RCE bit is set to "1" simultaneously with any 1 bit in the receive complete register
(RCR).The RCE bit is set to "1" independently of the bit setting of the receive interrupt
enable register (RIER).
Writing "0" to the RCE bit sets the bit to "0". Writing "1" to the RCE bit is ignored.
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
When the RCE bit is set to "1", the MBP3 to MBP0 bits are used to indicate the number of
the message buffer for which a receive operation was completed.
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MB90930 Series
[bit3 to bit0] MBP3 to MBP0: Message buffer pointer bits
When the TCE or RCE bit is set to "1", the MBP3 to MBP0 bits indicate the number of the
relevant message buffer (0 to 15).
When the NTE bit is set to "1", the MBP3 to MBP0 bits have no meaning.
Writing "0" to the MBP3 to MBP0 bits sets these bits to "0". Writing "1" to the MBP3 to
MBP0 bits is ignored.
"1" is read from these bits when a read-modify-write (RMW) instruction is executed.
When LEIR is accessed within the CAN interrupt handler, the event that caused an interrupt
is not necessarily the same as that indicated by LEIR. At the time when an interrupt to LEIR
access is requested within the interrupt handler, another CAN event may occur.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.3
Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters (RTEC) indicate the transmit error
count and receive error count defined by the CAN specifications.This register
is read-only.
■ Bit Configuration of Receive and Transmit Error Counters (RTEC)
Figure 18.3-4 shows the bit configuration of the receive and transmit error counters (RTEC).
Figure 18.3-4 Bit Configuration of Receive and Transmit Error Counters (RTEC)
Address:
003D05H (CAN1)
Address:
bit7
003D04H (CAN1)
R:
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
bit6
bit5
bit4
bit3
bit2
bit1
<- nitial value
I
bit0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
<- nitial value
I
Read only
[bit15 to bit8] TEC7 to TEC0: Transmit error counter
TEC7 to TEC0 are a transmit error counter.
TEC7 to TEC0 indicate 0 to 7 for a counter value greater than 256. The subsequent
increments are not counted as a counter value. In such a case, the node status is shown as
bus-off (NS1 and NS0 in the control status register (CSR) = 11B).
[bit7 to bit0] REC7 to REC0: Receive error counter
REC7 to REC0 are a receive error counter.
REC7 to REC0 indicate 0 to 7 for a counter value greater than 256. The subsequent
increments are not counted as a counter value. In such a case, the node status is shown as
error passive (NS1 and NS0 in the control status register (CSR) = 10B).
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3.4
MB90930 Series
Bit Timing Register (BTR)
The bit timing register (BTR) sets the prescaler and bit timing.
■ Bit Configuration of Bit Timing Register (BTR)
Figure 18.3-5 shows the bit configuration of the bit timing register (BTR).
Figure 18.3-5 Bit Configuration of Bit Timing Register (BTR)
Address:
003D07H (CAN1)
Address:
003D06H (CAN1)
R/W :
-:
bit15
−
−
−
bit14 bit13 bit12 bit11 bit10
bit9
bit8
TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
<- nitial value
I
bit7
RSJ1
R/W
1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RSJ0 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
<- nitial value
I
Readable/Writable
Undefined
Note:
BTR must be set while the bus operation is stopped (HALT = 1).
[bit14 to bit12] TS2.2 to TS2.0: Time segment 2 setting bits 2 to 0
The TS2.2 to TS2.0 bits determine time segment 2 (TSEG2) by dividing the unit time (TQ)
by [(TS2.2 to TS2.0)+1]. Time segment 2 is equivalent to phase buffer segment 2
(PHASE_SEG2) in the CAN specifications.
[bit11 to bit8] TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0
The TS1.3 to TS1.0 bits determine time segment 1 (TSEG1) by dividing the unit time (TQ)
by [(TS1.3 to TS1.0)+1]. Time segment 1 is equivalent to the propagation segment
(PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specifications.
[bit7, bit6] RSJ1, RSJ0: Re-synchronous jump width setting bits 1, 0
The RSJ1 and RSJ0 bits determine the re-synchronous jump width by dividing the unit time
(TQ) by [(RSJ1, RSJ0)+1].
[bit5 to bit0] PSC5 to PSC0: Prescaler setting bits 5 to 0
The PSC5 to PSC0 bits determine the unit time (TQ) of the CAN controller by dividing the
input clock by [(PSC5 to PSC0)+1].
Figure 18.3-6 and Figure 18.3-7 show the bit time segments in the CAN specifications and in
the CAN controller respectively.
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18.3 Classification of CAN Controller Registers
MB90930 Series
Figure 18.3-6 Bit Time Segments in CAN Specifications
Nominal bit time
SYNC_SEG
PROP_SEG
PIUSL_SEG1 PIUSL_SEG2
Sample point
Figure 18.3-7 Bit Time Segments in CAN Controller
Nominal bit time
SYNC_SEG
TSEG2
TSEG1
Sample point
The following shows the relationship among PSC = PSC5 to PSC0, TS1 = TS1.3 to TS1.0, TS2 =
TS2.2 to TS2.0, RSJ = RSJ1, and RSJ0 when the input clock (CLK), unit time (TQ), bit time
(BT), synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1, TSEG2), and resynchronous jump width [(RSJ1+RSJ0)+1] are frequency-divided.
TQ
= (PSC+1) × CLK
BT
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1+1) + (TS2+1)) × TQ
= (3 + TS1+TS2) × TQ
RSJW
= (RSJ + 1) × TQ
To ensure proper operation, the following conditions must be satisfied:
BT
≥ 8TQ
TSEG2
≥ RSJW
TSEG2
≥ 2TQ
When PSC = 0
TSEG1 ≥ 5TQ
When PSC ≥ 1
TSEG1 ≥ 2TQ
TSEG1 ≥ RSJW
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
■ Sample Setting of the Bit Timing Register
The following is the sample setting of the bit timing register.
● Operating conditions
• Communication speed (BT): 100 kbps (10μs)
• 1TQ: 0.5μs (1/20 of 1BT)
• Re-synchronous jump width (RSJW): 4TQ
• Delay time: 50 ns
• Internal operation frequency: 16 MHz (0.0625μs)
● Sample setting
The following procedure is used to specify the setting value of each bit.
1. TQ = (PSC+1) × CLK
0.5 = (PSC+1) × 0.0625
PSC = 0.5/0.0625-1 = 7
Therefore, the setting value for PSC5 to PSC0 is as follows:
PSC5 to PSC0 = 000111B
2. RSJW = (RSJ+1) × TQ
4TQ = (RSJ+1) × TQ
RSJ = 4-1 = 3
Therefore, the setting value for RSJ1 to RSJ0 is as follows:
RSJ1 to RSJ0 = 11B
3. TSEG2 ≥ RSJW
(TS2+1) × TQ ≥ 4TQ
TS2 ≥ 4-1 ≥ 3
Therefore, the setting value for TS2.2 to TS2.0 is as follows:
TS2.2 to TS2.0 ≥ 011B
4. TSEG1 ≥ RSJW
(TS1+1) × TQ ≥ 4TQ
TS1 ≥ 3
Therefore, the setting value for TS1.3 to TS1.0 is as follows:
TS1.3 to TS1.0 ≥ 0100B
Since the condition for the communication speed is 100 kbps, the following combinations are
available for 3. and 4.
- TS1.3 to TS1.0 = 1010B TS2.2 to TS2.0 = 111B
- TS1.3 to TS1.0 = 1011B TS2.2 to TS2.0 = 110B
- TS1.3 to TS1.0 = 1100B TS2.2 to TS2.0 = 101B
- TS1.3 to TS1.0 = 1101B TS2.2 to TS2.0 = 100B
- TS1.3 to TS1.0 = 1110B TS2.2 to TS2.0 = 011B
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.5
Message Buffer Valid Register (BVALR)
The message buffer valid register (BVALR) sets the validity of message buffer
(x) and indicates the state of the message buffer.
■ Bit Configuration of Message Buffer Valid Register (BVALR)
Figure 18.3-8 shows the bit configuration of the message buffer valid register (BVALR).
Figure 18.3-8 Bit Configuration of Message Buffer Valid Register (BVALR)
Address:
000071H (CAN1)
Address:
000070H (CAN1)
R/W :
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
Readable/Writable
The message buffer valid register (BVALR) consists of 16 bits, and each bit sets whether to
validate or invalidate each of 16 message buffers.
• 0: Message buffer (x) invalid
• 1: Message buffer (x) valid
When message buffer (x) is set to invalid ("0"), no message is sent or received.
When the buffer is set to invalid ("0") during a send operation, it becomes invalid (BVALx =
0) after the transmission is completed or is ended by an error.
When the buffer is set to invalid ("0") during a receive operation, it immediately becomes invalid
(BVALx = 0). If, however, the receive message is being stored in the message buffer (x), the
message buffer (x) becomes invalid after the message is stored.
Notes:
• "x" indicates the message buffer number (x = 0 to 15).
• When message buffer (x) is invalidated by writing "0" to the corresponding bit (BVALx),
the execution of bit operation instructions is disabled until the bit is set to "0".
• To invalidate the me ssage buffer (BVAL in BVALR=0) while the CAN controller is
participating in a CAN co mmunication ( the r ead valu e of t he HALT bit in CSR is "0",
and the CAN controller is ready to receive or transmit messages by participating i n a
CAN bus co mmunication), fo llow th e ca utions in Sect ion "18.11 Pre cautions When
Using CAN Controller".
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3.6
MB90930 Series
IDE Register (IDER)
The IDE register sets the frame format used by message buffer (x) during send/
receive operations.
■ Bit Configuration of IDE Register (IDER)
Figure 18.3-9 shows the bit configuration of the IDE register (IDER).
Figure 18.3-9 Bit Configuration of IDE Register (IDER)
Address:
003D09H (CAN1)
Address:
003D08H (CAN1)
R/W :
bit15
bit14
IDE15 IDE14
R/W
R/W
X
X
bit13
IDE13
R/W
X
bit12
IDE12
R/W
X
bit11
IDE11
R/W
X
bit10
IDE10
R/W
X
bit9
IDE9
R/W
X
bit8
IDE8
R/W
X
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IDE7
R/W
X
IDE6
R/W
X
IDE5
R/W
X
IDE4
R/W
X
IDE3
R/W
X
IDE2
R/W
X
IDE1
R/W
X
IDE0
R/W
X
<- nitial value
I
<- nitial value
I
Readable/Writable
The IDE register (IDER) consists of 16 bits, and each bit specifies a frame format used for each
of 16 message buffers.
• 0: Standard frame format (ID11 bits) is used for message buffer (x)
• 1: Extended frame format (ID29 bits) is used for message buffer (x)
Notes:
• This register must be set while message buffer (x) is invalid (BVALx in the message
buffer valid register (BVALR) = 0). If this is set while the buffer is valid (BVALx = 1),
unnecessary receive messages may be stored.
• To invalidate the message buffer (BVAL in BVALR = 0) whi le the CAN controller is
participating in a CAN co mmunication ( the r ead valu e of t he HALT bit in CSR is "0",
and the CAN controller is ready to receive or transmit messages by participating in a
CAN bus co mmunication), fo llow th e ca utions in Sect ion "18.11 Pre cautions When
Using CAN Controller".
510
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.7
Transmission Request Register (TREQR)
The transmission request register (TREQR) sets a transmission request for
message buffer (x) and indicate the state of the buffer.
■ Bit Configuration of Transmission Request Register (TREQR)
Figure 18.3-10 shows the bit configuration of the transmission request register (TREQR).
Figure 18.3-10 Bit Configuration of Transmission Request Register (TREQR)
Address:
000073H (CAN1)
Address:
000072H (CAN1)
R/W :
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TREQ15TREQ14TREQ13TREQ12TREQ11TREQ10 TREQ9 TREQ8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
Readable/Writable
When "1" is written to TREQx, transmission for message buffer (x) will start. If RFWTx in the remote
frame receive wait register (RFWTR)*1 is "0", transmission starts immediately. If RFWTx =1,
transmission is delayed until a remote frame is received (the remote request receive register
(RRTRR)*1 becomes "1"), and then starts. If "1" is written to TREQx when RRTRx is already "1",
transmission starts immediately even when RFWTx = 1.*2
*1: For details about TRTRR and RFWTR, see Sections "18.3.8 Transmission RTR register
(TRTRR)" and "18.3.9 Remote Frame Receive Wait Register (RFWTR)".
*2: For details of clearing transmission, see Sections "18.3.10 Transmission Cancel Register
(TCANR)" and "18.3.11 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read from this bit when a read-modify-write (RMW) instruction is executed.
If the attempts to clear this bit (to "0") when a send operation is completed and to set the bit by
writing "1" occur at the same time, clearing the bit has priority.
When "1" is written to more than one bit, transmission starts from the message buffer (x) with
the lowest number.
TREQx remains "1" in transmission wait state, and becomes "0" when transmission is
completed or cleared.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Transmission RTR register (TRTRR)
18.3.8
The transmission RTR register (TRTRR) sets the transmission RTR (remote
transmission request) bit via message buffer (x).
■ Bit Configuration of Transmission RTR Register (TRTRR)
Figure 18.3-11 shows the bit configuration of the transmission RTR register (TRTRR).
Figure 18.3-11 Bit Configuration of Transmission RTR Register (TRTRR)
Address:
003D0BH (CAN1)
Address:
003D0AH (CAN1)
R/W :
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TRTR15TRTR14TRTR13TRTR12TRTR11TRTR10 TRTR9 TRTR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
Readable/Writable
The transmission RTR register (TRTRR) consists of 16 bits, and each bit sets the remote
transmission request for each of 16 message buffers.
• 0: Sends a data frame.
• 1: Sends a remote frame.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.9
Remote Frame Receive Wait Register (RFWTR)
The remote frame receive wait register (RFWTR) sets the condition for starting
transmission when a request for data frame transmission is set (TREQx in the
transmission request register (TREQR) is "1" and TRTRx in the transmission
RTR register (TRTRR) is "0").
■ Bit Configuration of Remote Frame Receive Wait Register (RFWTR)
Figure 18.3-12 shows the bit configuration of the remote frame receive wait register (RFWTR).
Figure 18.3-12 Bit Configuration of Remote Frame Receive Wait Register (RFWTR)
Address:
bit15
003D0DH (CAN1)
Address:
R/W :
bit9
bit8
RFWT15RFWT14RFWT13RFWT12RFWT11RFWT10 RFWT9 RFWT8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
bit7
003D0CH (CAN1)
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit1
<- nitial value
I
bit0
RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
<- nitial value
I
Readable/Writable
The remote frame receive wait register (RFWTR) consists of 16 bits, and each bit sets the
transmission start condition when the corresponding message buffer is set for data frame
transmission.
• 0: Starts transmission immediately.
• 1: Waits until a remote frame is received (the remote request receive register (RRTRR)
becomes "1"), and then starts transmission.
Notes:
• Transmission starts immediately if a r equest for transmission is set when RRTRx is
already "1".
• Do not set RFWTx to "1" for remote frame transmission.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3.10
MB90930 Series
Transmission Cancel Register (TCANR)
The transmission cancel register (TCANR) cancels requests in wait state for
transmission to message buffer (x) when "1" is written to TCANx.
When canceling is completed, TREQx in the transmission request register
(TREQR) becomes "0". Writing "0" to TCANx is ignored.
The transmission cancel register (TCANR) is a write-only register, and its read
value is always "0".
■ Bit Configuration of Transmission Cancel Register (TCANR)
Figure 18.3-13 shows the bit configuration of the transmission cancel register (TCANR).
Figure 18.3-13 Bit Configuration of Transmission Cancel Register (TCANR)
Address:
000075H (CAN1)
Address:
000074H (CAN1)
W:
514
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
<- nitial value
I
<- nitial value
I
Write only
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.11 Transmission Complete Register (TCR)
When transmission via message buffer (x) is completed, the corresponding
TCx becomes "1".
When TIEx in the transmission interrupt enable register (TIER) is "1", an
interrupt is generated.
■ Bit Configuration of Transmission Complete Register (TCR)
Figure 18.3-14 shows the bit configuration of the transmission complete register (TCR).
Figure 18.3-14 Bit Configuration of Transmission Complete Register (TCR)
Address:
000077H (CAN1)
bit15
TC15
R/W
0
bit14
TC14
R/W
0
bit13
TC13
R/W
0
bit12
TC12
R/W
0
bit11
TC11
R/W
0
bit10
TC10
R/W
0
bit9
TC9
R/W
0
bit8
TC8
R/W
0
Address:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000076H (CAN1)
TC7
R/W
0
TC6
R/W
0
TC5
R/W
0
TC4
R/W
0
TC3
R/W
0
TC2
R/W
0
TC1
R/W
0
TC0
R/W
0
R/W :
<- nitial value
I
<- nitial value
I
Readable/Writable
TCx = 0 is made under the following conditions:
• "0" is written to TCx.
• "1" is written to TREQx in the transmission request register (TREQR).
When "0" is written to TCx after transmission is completed, TCx is set to "0". Writing "1"
to TCx is ignored. "1" is read from this bit when a read-modify-write (RMW) instruction is
executed.
Note:
If the att empts to set this bit to "1" when transmission is completed and to clear t he bit by
writing "0" occur at the same time, setting the bit to "1" has priority.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Transmission Interrupt Enable Register (TIER)
18.3.12
The transmission interrupt enable register (TIER) enables or disables
transmission interrupts via message buffer (x). A transmission interrupt is
generated when transmission is completed (when TCx in the transmission
complete register (TCR) becomes "1").
■ Bit Configuration of Transmission Interrupt Enable Register (TIER)
Figure 18.3-15 shows the bit configuration of the transmission interrupt enable register (TIER).
Figure 18.3-15 Bit Configuration of Transmission Interrupt Enable Register (TIER)
Address:
003D0FH (CAN1)
bit15 bit14 bit13 bit12 bit11 bit10
TIE15 TIE14 TIE13 TIE12 TIE11 TIE10
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
bit9
TIE9
R/W
0
bit8
TIE8
R/W
0
Address:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
003D0EH (CAN1)
TIE7
R/W
0
TIE6
R/W
0
TIE5
R/W
0
TIE4
R/W
0
TIE3
R/W
0
TIE2
R/W
0
TIE1
R/W
0
TIE0
R/W
0
R/W :
<- nitial value
I
<- nitial value
I
Readable/Writable
The transmission interrupt enable register (TIER) consists of 16 bits, and each bit sets whether
to enable or disable transmission interrupts to each of 16 message buffers.
• 0: Disables transmission interrupts.
• 1: Enables transmission interrupts.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.13 Receive Complete Register (RCR)
When storing a receive message in message buffer (x) is completed, RCx
becomes "1".
When RIEx in the receive complete interrupt enable register is "1", an interrupt
is generated.
■ Bit Configuration of Receive Complete Register (RCR)
Figure 18.3-16 shows the bit configuration of the receive complete register (RCR).
Figure 18.3-16 Bit Configuration of Receive Complete Register (RCR)
Address:
000079H (CAN1)
bit15 bit14 bit13 bit12 bit11 bit10
RC15 RC14 RC13 RC12 RC11 RC10
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
bit9
RC9
R/W
0
bit8
RC8
R/W
0
Address:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000078H (CAN1)
RC7
R/W
0
RC6
R/W
0
RC5
R/W
0
RC4
R/W
0
RC3
R/W
0
RC2
R/W
0
RC1
R/W
0
RC0
R/W
0
R/W :
<- nitial value
I
<- nitial value
I
Readable/Writable
RCx = 0 is made under the following conditions:
• "0" is written to RCx.
• After the receive message is processed, write "1" to RCx. Otherwise, writing "1" to RCx is
ignored.
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
Note:
If the at tempts to set this bit to "1" when a receive operation is completed and to clear t he
bit by writing "0" occur at the same time, setting the bit to "1" has priority.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3.14
MB90930 Series
Remote Request Receive Register (RRTRR)
When a received remote frame is stored in message buffer (x), RRTRx becomes
"1" (at the same time when the RCx setting becomes "1").
■ Bit Configuration of Remote Request Receive Register (RRTRR)
Figure 18.3-17 shows the bit configuration of the remote request receive register (RRTRR).
Figure 18.3-17 Bit Configuration of Remote Request Receive Register (RRTRR)
Address:
bit15
00007BH (CAN1)
Address:
00007AH (CAN1)
R/W :
bit14
bit13
bit12
bit11
bit10
bit9
bit8
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
Readable/Writable
RRTRx = 0 is made under the following conditions:
• "0" is written to RRTRx.
• After a received data frame is stored in message buffer (x) (at the same time when the RCx
setting becomes "1").
• After transmission via message buffer (x) is completed (when TCx in the transmission
complete register (TCR) is "1").
Writing "1" to RRTRx is ignored.
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
Note:
If the attempts to se t this b it to "1" a nd t o clear th e bit b y w riting "0 " o ccur at th e sa me
time, setting the bit to "1" has priority.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.15 Receive Overrun Register (ROVRR)
If the receive complete register (RCR) is already "1" when storing a receive
message into message buffer (x) is completed, ROVRx becomes "1" to indicate
that reception caused an overrun.
■ Bit Configuration of Receive Overrun Register (ROVRR)
Figure 18.3-18 shows the bit configuration of the receive overrun register (ROVRR).
Figure 18.3-18 Bit Configuration of Receive Overrun Register (ROVRR)
Address:
bit15
00007DH (CAN1)
Address:
00007CH (CAN1)
R/W :
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ROVR15ROVR14ROVR13ROVR12ROVR11ROVR10 ROVR9 ROVR8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<- nitial value
I
<- nitial value
I
Readable/Writable
Writing "0" to ROVRx makes ROVRx = 0. Writing "1" to ROVRx is ignored. When "0" is
written to ROVRx after a reception overrun is confirmed, ROVRx is set to "0".
"1" is read from this bit when a read-modify-write (RMW) instruction is executed.
Note:
If the attempts to se t this b it to "1" a nd t o clear th e bit b y w riting "0 " o ccur at th e sa me
time, setting the bit to "1" has priority.
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Receive Interrupt Enable Register (RIER)
18.3.16
The receive interrupt enable register (RIER) enables or disables receive
interrupts via message buffer (x).
A receive interrupt is generated when reception is completed (when RCx in the
receive complete register (RCR) is "1").
■ Bit Configuration of Receive Interrupt Enable Register (RIER)
Figure 18.3-19 shows the bit configuration of the receive interrupt enable register (RIER).
Figure 18.3-19 Bit Configuration of Receive Interrupt Enable Register (RIER)
Address:
00007FH (CAN1)
Address:
00007EH (CAN1)
R/W :
bit15 bit14 bit13 bit12 bit11 bit10
bit9
RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
bit8
RIE8
R/W
0
<- nitial value
I
bit7
RIE7
R/W
0
bit0
RIE0
R/W
0
<- nitial value
I
bit6
RIE6
R/W
0
bit5
RIE5
R/W
0
bit4
RIE4
R/W
0
bit3
RIE3
R/W
0
bit2
RIE2
R/W
0
bit1
RIE1
R/W
0
Readable/Writable
The receive interrupt enable register (RIER) consists of 16 bits, and each bit sets whether to
enable or disable receive interrupts to each of 16 message buffers.
• 0: Disables receive interrupts.
• 1: Enables receive interrupts.
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FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.17 Acceptance Mask Selection Register (AMSR)
The acceptance mask selection register (AMSR) selects a mask (acceptance
mask) for the comparison between the receive message ID and message buffer
(x) ID.
■ Bit Configuration of Acceptance Mask Selection Register (AMSR)
Figure 18.3-20 shows the bit configuration of the acceptance mask selection register (AMSR).
As listed in Table 18.3-7, the acceptance mask for the corresponding message buffer is selected
based on a combination of 2 bits.
Figure 18.3-20 Bit Configuration of Acceptance Mask Selection Register (AMSR)
Address:
003D10H (CAN1)
Address:
003D11H (CAN1)
Address:
003D12H (CAN1)
Address:
003D13H (CAN1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
<- nitial value
I
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AMS7.1 AMS7.0 AMS6.1 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
<- nitial value
I
bit7
bit5
bit4
bit3
bit2
bit1
bit0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
<- nitial value
I
AMS15.1 AMS15.0 AMS14.1 AMS14.0 AMS13.1 AMS13.0 AMS12.1 AMS12.0
R/W
X
R/W :
bit6
AMS11.1 AMS11.0 AMS10.1 AMS10.0 AMS9.1 AMS9.0 AMS8.1 AMS8.0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
<- nitial value
I
Readable/Writable
Table 18.3-7 Selection of the Acceptance Mask
AMSx.1
AMSx.0
0
0
Full-bit compare
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
CM44-10150-1E
Acceptance Mask
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Notes:
• AMSx.1 and AMSx.0 must be set while message buffer (x) is invalid (when BVALx in
the message buffer valid register (BVALR) is "0"). If these bits are set while the buffer
is valid (BVALx = 1), unnecessary receive messages may be stored.
• To invalidate the message buffer (BVAL in BVALR = 0) whi le the CAN controller is
participating in a CAN co mmunication ( the r ead valu e of t he HALT bit in CSR is "0",
and the CAN controller is ready to receive or transmit messages by participating in a
CAN bus co mmunication), fo llow th e ca utions in Sect ion "18.11 Pre cautions When
Using CAN Controller".
522
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.18 Acceptance Mask Registers 0 and 1 (AMR0/AMR1)
There are 2 types of acceptance mask register: AMR0 and AMR1, and both can
be used in either the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for an acceptance mask in the standard frame
format; AM28 to AM0 (29 bits) are used for an acceptance mask in the extended
frame format.
■ Bit Configuration of Acceptance Mask Registers 0 and 1 (AMR0/AMR1)
Figure 18.3-21 shows the bit configuration of the acceptance mask registers 0 and 1 (AMR0/
AMR1).
Figure 18.3-21 Bit Configuration of Acceptance Mask Registers 0 and 1 (AMR0/AMR1)
AMR0 BYTE0
Address:
003D14H (CAN1)
bit7
AM28
R/W
X
bit6
AM27
R/W
X
bit5
AM26
R/W
X
bit4
AM25
R/W
X
bit3
AM24
R/W
X
bit2
AM23
R/W
X
bit1
AM22
R/W
X
bit0
AM21
R/W
X
<- nitial value
I
bit15
AM20
R/W
X
bit14
AM19
R/W
X
bit13
AM18
R/W
X
bit12
AM17
R/W
X
bit11
AM16
R/W
X
bit10
AM15
R/W
X
bit9
AM14
R/W
X
bit8
AM13
R/W
X
<- nitial value
I
bit7
AM12
R/W
X
bit6
AM11
R/W
X
bit5
AM10
R/W
X
bit4
AM9
R/W
X
bit3
AM8
R/W
X
bit2
AM7
R/W
X
bit1
AM6
R/W
X
bit0
AM5
R/W
X
<- nitial value
I
bit15
AM4
R/W
X
bit14
AM3
R/W
X
bit13
AM2
R/W
X
bit12
AM1
R/W
X
bit11
AM0
R/W
X
bit10
−
−
−
bit9
−
−
−
bit8
−
−
−
<- Initial value
bit7
AM28
R/W
X
bit6
AM27
R/W
X
bit5
AM26
R/W
X
bit4
AM25
R/W
X
bit3
AM24
R/W
X
bit2
AM23
R/W
X
bit1
AM22
R/W
X
bit0
AM21
R/W
X
<- nitial value
I
bit15
AM20
R/W
X
bit14
AM19
R/W
X
bit13
AM18
R/W
X
bit12
AM17
R/W
X
bit11
AM16
R/W
X
bit10
AM15
R/W
X
bit9
AM14
R/W
X
bit8
AM13
R/W
X
<- nitial value
I
AMR0 BYTE1
Address:
003D15H (CAN1)
AMR0 BYTE2
Address:
003D16H (CAN1)
AMR0 BYTE3
Address:
003D17H (CAN1)
AMR1 BYTE0
Address:
003D18H (CAN1)
AMR1 BYTE1
Address:
003D19H (CAN1)
(Continued)
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
(Continued)
AMR1 BYTE2
Address:
003D1AH (CAN1)
bit7
AM12
R/W
X
bit6
AM11
R/W
X
bit5
AM10
R/W
X
bit4
AM9
R/W
X
bit3
AM8
R/W
X
bit2
AM7
R/W
X
bit1
AM6
R/W
X
bit0
AM5
R/W
X
<- nitial value
I
bit15
AM4
R/W
X
bit14
AM3
R/W
X
bit13
AM2
R/W
X
bit12
AM1
R/W
X
bit11
AM0
R/W
X
bit10
−
−
−
bit9
−
−
−
bit8
−
−
−
<- Initial value
AMR1 BYTE3
Address:
003D1BH (CAN1)
R/W :
-:
Readable/Writable
Undefined
● 0: Compare
Compares the acceptance code corresponding to this bit (IDRx in the ID register to be
compared with the receive message ID) with the bit of the receive message ID. If these bits do
not match, the message is not received.
● 1: Mask
Masks the acceptance code ID register (IDRx) corresponding to this bit. The comparison with
the bit of the receive message ID is not performed.
Notes:
• AMR0 and AMR1 must be set while all
message buf fers ( x) select ing AM R0 and
AMR1 are invalid (BVALx in the message buffer valid register (BVALR) is "0"). If these
bits are set while the mess age buffers are valid (BVALx = 1), unnecess ary receive
messages may be stored.
• To invalidate the message buffer (BVAL in BVALR = 0) whi le the CAN controller is
participating in a CAN co mmunication ( the r ead valu e of t he HALT bit in CSR is "0",
and the CAN controller is ready to receive or transmit messages by participating in a
CAN bus co mmunication), fo llow th e ca utions in Sect ion "18.11 Pre cautions When
Using CAN Controller".
524
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
MB90930 Series
18.3.19 Message Buffers
CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
There are 16 message buffers being provided, and 1 message buffer x (x = 0 to
15) consists of an ID register (IDRx), a DLC register (DLCRx), and a data
register (DTRx).
■ Message Buffers
Message buffer (x) is used for both send and receive operations.
Lower-numbered message buffers have higher priority.
When a transmission request is issued to more than one message buffer during transmission,
transmission starts from the message buffer having the lowest number (See Section "18.4
CAN Controller Transmission".).
When a receive message ID passes through the acceptance filters (the mechanism to compare
the acceptance mask ID of a receive message with the message buffer) of more than one
message buffers during reception, the receive message is stored in the message buffer having
the lowest number (See Section "18.5 CAN Controller Reception".).
If the same acceptance filter is specified in more than one message buffers, these message
buffers can be used as a multi-level message buffer. This makes some time reserve for
reception (See Section "18.8 Procedure of Reception Via Message Buffer (x)".).
Notes:
• Write ope ration t o a messag e bu ffer and to t he general-purpose RAM ar ea must be
performed in units of wor ds b y using e ven-numbered a ddresses. Not e that t he wr ite
operation in units of bytes may result in undefined data being written to the upper byte
during writing to the lower byte.
• When the BVALx bit in the me ssage buffer valid register (BVALR) is "0" (invalid),
message buffer (x) (IDRx, DLCRx, and DTRx) can b e used as ge neral-purpose RAM.
If, however, the CAN controller is se nding or receiving data, it u ses a m essage buffer,
resulting in the poss ibility of the delay in the C PU access for up to 64 machine cy cles.
The same processing may occur in the general-purpose RAM area (CAN0: Addresses
003A00H to 003A1FH and addresses 003B00H to 003B1FH).
CM44-10150-1E
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
18.3.20
MB90930 Series
ID Register x (x = 0 to 15) (IDRx)
ID register x (x = 0 to 15) (IDRx) is an ID register for message buffer (x).
■ Bit Configuration of ID Register x (x = 0 to 15) (IDRx)
Figure 18.3-22 shows the bit configuration of ID register x (x = 0 to 15) (IDRx).
Figure 18.3-22 Bit Configuration of ID Register x (x = 0 to 15) (IDRx)
BYTE0
Address:
003B20H +4x (CAN1)
bit7
ID28
R/W
X
bit6
ID27
R/W
X
bit5
ID26
R/W
X
bit4
ID25
R/W
X
bit3
ID24
R/W
X
bit2
ID23
R/W
X
bit1
ID22
R/W
X
bit0
ID21
R/W
X
<- nitial alue
I
v
bit15
ID20
R/W
X
bit14
ID19
R/W
X
bit13
ID18
R/W
X
bit12
ID17
R/W
X
bit11
ID16
R/W
X
bit10
ID15
R/W
X
bit9
ID14
R/W
X
bit8
ID13
R/W
X
<- nitial alue
I
v
bit7
ID12
R/W
X
bit6
ID11
R/W
X
bit5
ID10
R/W
X
bit4
ID9
R/W
X
bit3
ID8
R/W
X
bit2
ID7
R/W
X
bit1
ID6
R/W
X
bit0
ID5
R/W
X
<- nitial alue
I
v
bit15
ID4
R/W
X
bit14
ID3
R/W
X
bit13
ID2
R/W
X
bit12
ID1
R/W
X
bit11
ID0
R/W
X
bit10
−
−
−
bit9
−
−
−
bit8
−
−
−
BYTE1
Address:
003B21H +4x (CAN1)
BYTE2
Address:
003B22H +4x (CAN1)
BYTE3
Address:
003B23H +4x (CAN1)
R/W :
-:
<- Initial value
Readable/Writable
Undefined
When message buffer (x) is used in the standard frame format (IDEx in the IDE register
(IDER) = 0), use 11 bits of ID28 to ID18. When the buffer is used in the extended frame
format (IDEx = 1), use 29 bits of ID28 to ID0.
ID28 to ID0 have the following functions:
• Setting an acceptance code (ID to be compared with a receive message ID)
• Setting a send message ID
In the standard frame format, it is prohibited to set all bits of ID28 to ID22 to "1".
• Storing a receive message ID
A receive message ID is stored also in the bits masked by an acceptance mask. In the
standard frame format, undefined values (part of a message received previously) are stored
in ID17 to ID0.
526
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Notes:
• Write operation to the ID register must be performed in units of words. Note that the
write operation in units of bytes may result in undefined data being written to the upper
byte during writing to the lower byte. Writing to the upper byte is ignored.
• The ID register must be set while message buffer (x) is invalid (BVALx in the message
buffer va lid re gister (B VALR) is "0") . If th is register is s et w hile the buffer is valid
(BVALx = 1), unnecessary receive messages may be stored.
• To invalidate the message buffer (BVAL in BVALR = 0) whi le the CAN controller is
participating in a CAN co mmunication ( the r ead valu e of t he HALT bit in CSR is "0",
and the CAN controller is ready to receive or transmit messages by participating i n a
CAN bus co mmunication), fo llow th e ca utions in Sect ion "18.11 Pre cautions When
Using CAN Controller".
■ Sample Setting of the ID Register
Table 18.3-8 and Table 18.3-9 show the sample setting of the ID register in the standard and
extended frame formats.
Table 18.3-8 Sample Setting of ID Register in Standard Frame Format (1 / 2)
ID (Decimal)
ID (Hexadecimal)
BYTE0
BYTE1
1
1
00
20
2
2
00
40
3
3
00
60
4
4
00
80
5
5
00
A0
6
6
00
C0
7
7
00
E0
8
8
01
00
9
9
01
20
10
A
01
40
•
•
•
•
30
1E
03
C0
31
1F
03
C1
32
20
03
C2
•
•
•
•
100
064
0C
80
101
065
0C
A0
•
•
CM44-10150-1E
•
•
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-8 Sample Setting of ID Register in Standard Frame Format (2 / 2)
ID (Decimal)
ID (Hexadecimal)
BYTE0
BYTE1
200
0C8
19
00
•
•
•
•
2043
7FB
FF
06
2044
7FC
FF
80
2045
7FD
FF
A0
2046
7FE
FF
C0
2047
7FF
FF
E0
Table 18.3-9 Sample Setting of ID Register in Extended Frame Format (1 / 2)
ID (Decimal)
ID (Hexadecimal)
BYTE0
BYTE1
BYTE0
BYTE1
1
1
00
00
00
08
2
2
00
00
00
10
3
3
00
00
00
18
4
4
00
00
00
20
5
5
00
00
00
28
6
6
00
00
00
30
7
7
00
00
00
38
8
8
00
00
00
40
9
9
00
00
00
48
10
A
00
00
00
50
•
•
•
•
30
1E
00
00
00
F0
31
1F
00
00
00
F8
32
20
00
00
01
00
•
•
•
•
100
064
00
00
03
20
101
065
00
00
03
28
06
40
•
•
200
528
•
•
0C8
00
00
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
Table 18.3-9 Sample Setting of ID Register in Extended Frame Format (2 / 2)
ID (Decimal)
ID (Hexadecimal)
BYTE0
BYTE1
•
•
BYTE0
BYTE1
•
•
2043
7FB
00
00
3F
D8
2044
7FC
00
00
3F
E0
2045
7FD
00
00
3F
E8
2046
7FE
00
00
3F
F0
2047
7FF
00
00
3F
F8
•
•
•
•
8190
1FFE
00
00
FF
F0
8191
1FFF
00
00
FF
F8
8192
2000
00
01
00
00
•
•
•
•
536870905
1FFFFFF9
FF
FF
FC
80
536870906
1FFFFFFA
FF
FF
FD
00
536870907
1FFFFFFB
FF
FF
FD
80
536870908
1FFFFFFC
FF
FF
FE
00
536870909
1FFFFFFD
FF
FF
FE
80
536870910
1FFFFFFE
FF
FF
FF
00
536870911
1FFFFFFF
FF
FF
FF
80
CM44-10150-1E
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CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
DLC Register x (x = 0 to 15) (DLCRx)
18.3.21
DLC register x (x = 0 to 15) (DLCRx) stores DLC corresponding to message
buffer x.
■ Bit Configuration of DLC Register x (x = 0 to 15) (DLCRx)
Figure 18.3-23 shows the bit configuration of DLC register x (x = 0 to 15) (DLCRx).
Figure 18.3-23 Bit Configuration of DLC Register x (x = 0 to 15) (DLCRx)
Address:
003B60H +2x (CAN1)
R/W :
-:
bit7
−
−
−
bit6
−
−
−
bit5
−
−
−
bit4
−
−
−
bit3
DLC3
R/W
X
bit2
DLC2
R/W
X
bit1
DLC1
R/W
X
bit0
DLC0
R/W
X
<- nitial alue
I
v
Readable/Writable
Undefined
● Transmission
• When a data frame is sent (TRTRx in the transmission RTR register (TRTRR) is "0"), the
data length of the send message is specified (in units of bytes).
• When a remote frame is sent (TRTRx = 1), the data length of the request message is
specified (in units of bytes).
Note:
Setting values other than 0000B to 1000B (0 to 8 bytes) is disabled.
● Reception
• When a data frame is received (RRTRx in the remote frame request receive register
(RRTRR) is "0"), the data length of the receive message is stored (in units of bytes).
• When a remote frame is received (RRTRx = 1), the data length of the request message is
stored (in units of bytes).
Note:
Write operation to the DLC register must be performed in un its of words. Note that write
operation in units of bytes m ay result in un defined da ta be ing wr itten to th e up per byte
during writing to the lower byte. Writing to the upper byte is ignored.
530
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
18.3.22 Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is a data register for message buffer (x).
Data register x (x = 0 to 15) (DTRx) is used only to send or receive data frames;
it is not used to send or receive remote frames.
■ Bit Configuration of Data Register x (x = 0 to 15) (DTRx)
Figure 18.3-24 shows the bit configuration of data register x (x = 0 to 15) (DTRx).
Figure 18.3-24 Bit Configuration of Data Register x (x = 0 to 15) (DTRx)
BYTE0
Address:
003B80H +8x (CAN1)
bit7
D7
R/W
X
bit6
D6
R/W
X
bit5
D5
R/W
X
bit4
D4
R/W
X
bit3
D3
R/W
X
bit2
D2
R/W
X
bit1
D1
R/W
X
bit0
D0
R/W
X
<- nitial alue
I
v
bit15
D7
R/W
X
bit14
D6
R/W
X
bit13
D5
R/W
X
bit12
D4
R/W
X
bit11
D3
R/W
X
bit10
D2
R/W
X
bit9
D1
R/W
X
bit8
D0
R/W
X
<- nitial alue
I
v
bit7
D7
R/W
X
bit6
D6
R/W
X
bit5
D5
R/W
X
bit4
D4
R/W
X
bit3
D3
R/W
X
bit2
D2
R/W
X
bit1
D1
R/W
X
bit0
D0
R/W
X
<- nitial alue
I
v
bit15
D7
R/W
X
bit14
D6
R/W
X
bit13
D5
R/W
X
bit12
D4
R/W
X
bit11
D3
R/W
X
bit10
D2
R/W
X
bit9
D1
R/W
X
bit8
D0
R/W
X
<- nitial alue
I
v
bit7
D7
R/W
X
bit6
D6
R/W
X
bit5
D5
R/W
X
bit4
D4
R/W
X
bit3
D3
R/W
X
bit2
D2
R/W
X
bit1
D1
R/W
X
bit0
D0
R/W
X
<- nitial alue
I
v
bit15
D7
R/W
X
bit14
D6
R/W
X
bit13
D5
R/W
X
bit12
D4
R/W
X
bit11
D3
R/W
X
bit10
D2
R/W
X
bit9
D1
R/W
X
bit8
D0
R/W
X
<- nitial alue
I
v
BYTE1
Address:
003B81H +8x (CAN1)
BYTE2
Address:
003B82H +8x (CAN1)
BYTE3
Address:
003B83H +8x (CAN1)
BYTE4
Address:
003B84H +8x (CAN1)
BYTE5
Address:
003B85H +8x (CAN1)
(Continued)
CM44-10150-1E
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531
CHAPTER 18 CAN CONTROLLER
18.3 Classification of CAN Controller Registers
MB90930 Series
(Continued)
BYTE6
Address:
003B86H +8x (CAN1)
bit7
D7
R/W
X
bit6
D6
R/W
X
bit5
D5
R/W
X
bit4
D4
R/W
X
bit3
D3
R/W
X
bit2
D2
R/W
X
bit1
D1
R/W
X
bit0
D0
R/W
X
<- nitial alue
I
v
bit15
D7
R/W
X
bit14
D6
R/W
X
bit13
D5
R/W
X
bit12
D4
R/W
X
bit11
D3
R/W
X
bit10
D2
R/W
X
bit9
D1
R/W
X
bit8
D0
R/W
X
<- nitial alue
I
v
BYTE7
Address:
003B87H +8x (CAN1)
R/W :
Readable/Writable
● Setting send message data (any length between 0 and 8 bytes)
Sending data begins with MSB, followed by BYTE0, BYTE1, to BYTE7 in this order.
● Receive message data
Storing data begins with MSB, followed by BYTE0, BYTE1, to BYTE7 in this order.
If receive message data is less than 8 bytes, the remaining bytes in the data register (DTRx) to
which data is stored are undefined.
Note:
Write operation to the data register must be performed in units of words. Note that write
operation in units of bytes m ay result in un defined da ta be ing wr itten to th e up per byte
during writing to the lower byte. Writing to the upper byte is ignored.
532
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
MB90930 Series
18.4
CAN Controller Transmission
CHAPTER 18 CAN CONTROLLER
18.4 CAN Controller Transmission
The CAN controller starts the transmission via message buffer (x) when "1" is
written to TREQx in the transmission request register (TREQR). At this
moment, TREQx becomes "1" and TCx in the transmission complete register
(TCR) becomes "0".
■ Starting CAN Controller Transmission
When RFWTx in the remote frame receive wait register (RFWTR) becomes "0", transmission
starts immediately. When RFWTx is "1", transmission is delayed until a remote frame is
received (RRTRx in the remote request receive register (RRTRR) becomes "1") and then
started.
When a request for transmission is issued to more than one message buffer (more than one
TREQx is "1"), transmission starts from the message buffer with the lowest number.
Message transmission to the CAN bus (via transmission output pin TX) starts when the bus is
idle.
When TRTRx in the transmission RTR register (TRTRR) is "0", a data frame is sent. When
TRTRx is "1", a remote frame is sent.
If arbitration for transmission fails due to the conflict of the message buffer with another CAN
controller on the CAN bus, or if an error occurs during transmission, the message buffer waits
until the bus becomes idle and then repeats retransmission until the transmission is completed
successfully.
■ Clearing a CAN Controller Transmission Request
● Clearing via the transmission cancel register (TCANR)
A transmission request issued to message buffer (x) for which transmission was not executed
during send wait state can be cleared by writing "1" to TCANx in the transmission cancel
register (TCANR). When the clearing is completed, TREQx becomes "0".
● Clearing by storing a receive message
Reception is performed even for the message buffer (x) for which a transmission request was
issued but transmission was not executed.
If a request for data frame transmission was issued but transmission was not executed for
message buffer (x) (TRTRx = 0 or TREQx = 1), the transmission request is cleared (TREQx =
0) after a receive data frame that passed the acceptance filter is stored. This transmission
request is not cleared by storing a remote frame (TREQx = 1 remains unchanged).
If a request for remote frame transmission is issued but transmission was not executed for
message buffer (x) (TRTRx = 1 or TREQx = 1), the transmission request is cleared (TREQx =
0) after a receive remote frame that passed the acceptance filter is stored. This transmission
request is cleared by storing either of a data frame or a remote frame.
■ Completing CAN Controller Transmission
When transmission is successful, RRTRx and TREQx become "0" and TCx in the transmission
complete register (TCR) becomes "1". When transmission complete interrupts are enabled
(when TIEx in the transmission interrupt enable register (TIER) is "1"), an interrupt is
generated.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
533
CHAPTER 18 CAN CONTROLLER
18.4 CAN Controller Transmission
MB90930 Series
■ Flowchart of CAN Transmission Setting
Figure 18.4-1 shows a flowchart of the CAN transmission setting.
Figure 18.4-1 Flowchart of CAN Transmission Setting
START
Set bit timing:
Set frame format: IDE
Set ID:
Set acceptance filter:
Accept
Bit timing register (BTR)
register (IDER)
ID register (IDR)
Acceptance mask selection register (AMSR)
ance mask registers (AMR0,1)
Select message buffer to be used:
Message buffer valid register (BVALR)
Set transmission complete interrupt:
Transmission interrupt enable register (TIER)
Data frame
Remote frame
Select frame type
Set frame type:
Transmission RTR register
(TRTRR = 1)
Set frame type:
Transmission RTR register
(TRTRR = 0)
Set send data length:
DLC register (DLCR)
Set request data length:
DLC register (DLCR)
Store send data in data register
Data register (DTR)
YES
Wait to receive
remote frame?
NO
Wait to receive remote frame
RFWTR = 0
Wait to receive remote frame
RFWTR = 1
Clear bus operation stop HALT = 1
Message signal Set transmission request for data frame:
Data frame transmission TREQR
Wait to receive remote frame
Communication error
NO:0
Transmission successful?
TCR
YES:1
Cancel
transmission?
NO
YES
Cancel transmission request:
Transmission TCANR register
TREQR
1
0
1
Transmission completed
TCR
0
Cancel transmission
END
534
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 18 CAN CONTROLLER
18.4 CAN Controller Transmission
MB90930 Series
■ Flowchart of CAN Controller Transmission
Figure 18.4-2 shows a flowchart of the CAN controller transmission.
Figure 18.4-2 Flowchart of CAN Controller Transmission
Transmission request
(TREQx = 1)
TCx = 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are other message buffers that satisfy
the above conditions, the buffer with the
lowest number is selected.
NO
Is the bus idle?
YES
0
1
TRTRx?
Remote frame is sent.
Data frame is sent.
NO
Is transmission
successful?
YES
TCANx?
RRTEx = 0
TREQx = 0
TC = 1
1
TREQx = 0
1
TIEx?
0
0
Transmission complete
interrupt is generated.
End of transmission
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CHAPTER 18 CAN CONTROLLER
18.5 CAN Controller Reception
18.5
MB90930 Series
CAN Controller Reception
Reception starts when the start of a data frame or a remote frame (SOF) is
detected on the CAN bus.
■ Acceptance Filtering
Receive messages in the standard frame format are compared with message buffer (x) set in the
standard frame format (IDEx in the IDE register (IDER) is "0"). Receive messages in the
extended frame format are compared with message buffer (x) set in the extended frame format
(IDEx is "1").
When all bit sets to be compared with the acceptance mask match after the comparison of the
receive message ID and acceptance code (ID register (IDRx) to be compared with the receive
message ID), the receive message passes the acceptance filter for message buffer (x).
■ Storing the Receive Message
When a receive operation is successful, the receive message including the ID that passed the
acceptance filter is stored in message buffer (x).
When a data frame is received, the receive message is stored in the ID register (IDRx), DLC
register (DLCRx), and data register (DTRx).
Even if the data of the receive message is less than 8 bytes, a certain data is stored in the
remaining bytes in DTRx with undefined values.
When a remote frame is received, the receive message is stored only in IDRx and DLCRx, and
DTRx remains unchanged.
If more than one message buffer includes IDs that passed the acceptance filter, message buffer
x which should store the receive message is determined by the following rule:
Message buffer x (x = 0 to 15) which has the lower number has higher priority. In other words,
message buffer 0 has the highest priority, and message buffer 15 has the lowest priority.
For storing a receive message, the message buffer for which RCx bit in the receive complete
register (RCR) is set to "0" basically has priority.
If the bits in the acceptance mask selection register (AMSR) are set for a message buffer for
which all-bit compare (AMSx.1 and AMSx.0 bits) are set to "00", the receive message is stored
regardless of the value of the RCx bit in RCR.
When there are several buffers for which the RCx bit in RCR is set to "0" and the bits in
AMSR are set to all-bit compare, the receive message is stored in message buffer x having the
lowest number (highest priority). If no such message buffers exist, the receive message is
stored in message buffer x having a lower number.
Figure 18.5-1 shows a flowchart of determining message buffer x which should store the
receive message. It is recommended to set message buffers in order of buffers for which the
bits in AMSR are set to all-bit compare, buffers that use AMR0 or AMR1, and buffers for
which the bits in AMSR are set to all-bit mask; sequentially in order of buffer numbers within
each group.
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CHAPTER 18 CAN CONTROLLER
18.5 CAN Controller Reception
MB90930 Series
Figure 18.5-1 Flowchart for Determining Message Buffer (x) which Stores Receive Messages
Start
Are message buffers with RCx set to "0"
or with AMSx.1 and AMSx.0 set to "00B"
found?
NO
YES
Select the lowestnumbered message buffer
Select the lowernumbered message buffer
End
■ Receive Overrun
When the RCx bit in the receive complete register (RCR) corresponding to message buffer x in
which a receive message is to be stored has already been set to "1" and storing a receive
message in message buffer x is completed, the ROVRx bit in the receive overrun register
(ROVRR) is set to "1" to indicate a receive overrun.
■ Processing for Receiving Data Frame and Remote Frame
● Processing for receiving a data frame
When a data frame is received, RRTRx in the remote request receive register (RRTRR)
becomes "0".
TREQx in the transmission request register (TREQR) becomes "0" immediately before a
receive message is stored. Transmission requests to message buffer (x) for which transmission
was not executed are cleared. The requests are cleared for both data and remote frame
transmission.
● Processing for receiving a remote frame
When a remote frame is received, RRTRx becomes "1".
When TRTRx in the transmission RTR register (TRTRR) is "1", TREQx becomes "0". As a
result, requests for remote frame transmission to the message buffer for which transmission
was not executed are cleared.
Notes:
• Requests for data frame transmission are not cleared.
• For de tails of clearing a tr ansmission request, se e Sec tion "1 8.4
Transmission".
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CHAPTER 18 CAN CONTROLLER
18.5 CAN Controller Reception
MB90930 Series
■ Receive Complete
RCx in the receive complete register (RCR) becomes "1" after a receive message is stored.
When receive interrupts are enabled (RIEx in the receive interrupt enable register (RIER) is
"1"), an interrupt is generated.
Note:
This CAN controller does not receive messages which were sent by itself.
■ Flowchart of CAN Reception Setting
Figure 18.5-2 shows the flowchart of the CAN reception setting.
Figure 18.5-2 Flowchart of CAN Reception Setting
START
Set bit timing:
Set frame format: IDE
Set ID:
Set acceptance filter:
Accept
Bit timing register (BTR)
register (IDER)
ID register (IDR)
Acceptance mask selection register (AMSR)
ance mask registers (AMR0,1)
Select message buffer to be used:
Message buffer valid register (BVALR)
Set receive complete interrupt:
Receive complete interrupt enable register (RIER)
Clear bus operation stop HALT = 1
NO
Is message received?
RCR=1?
YES
Message store processing
Processed by receive complete
interrupt, etc.
Read received byte count
Clear receive overrun flag
ROVRR=0
Read receive message
Receive overrun?
ROVRR=0?
NO
YES
Clear receive complete interrupt flag
RCR=0
END
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CHAPTER 18 CAN CONTROLLER
18.5 CAN Controller Reception
MB90930 Series
■ Flowchart of CAN Controller Reception
Figure 18.5-3 shows a flowchart of the CAN controller reception.
Figure 18.5-3 Flowchart of CAN Controller Reception
Detect start of data frame
or remote frame (SDF)
Is there a message
buffer (x) for message that passes
acceptance filter?
NO
YES
NO
Was reception
successful?
YES
Determine message buffer (x)
to store receive message
Store receive message
in message buffer (x)
1
RCx?
0
Data frame
ROVRx = 1
Remote frame
Which type
of message was
received?
RRTRx = 0
RRTRx = 1
1
TRTRx?
0
TREQx = 0
RCx = 1
RIEx?
0
1
Receive interrupt
generated
End of reception
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CHAPTER 18 CAN CONTROLLER
18.6 Using CAN Controller
18.6
MB90930 Series
Using CAN Controller
Using the CAN controller requires the following settings:
• Bit timing setting
• Frame format setting
• ID setting
• Acceptance filter setting
• Low-power consumption mode setting
■ Setting Bit Timing
The bit timing register (BTR) must be set while bus operation is stopped (the bus operation
stop bit (HALT) in the control status register (CSR) is "1").
After the setting is completed, release the bus operation stop by writing "0" to HALT.
■ Setting Frame Format
Set a frame format used for message buffer (x). To use the standard frame format, set IDEx in
the IDE register (IDER) to "0". To use the extended frame format, set IDEx to "1".
This must be set while the message buffer (x) is invalid (BVALx in the message buffer valid
register (BVALR) is "0"). If this is set while the buffer is valid (BVALx = 1), unnecessary
receive messages may be stored.
■ Setting ID
Set the ID of message buffer (x) in ID28 to ID0 of the ID register (IDRx). When the standard
frame format is used, it is unnecessary to set the ID of message buffer (x) in ID17 to ID0. The
ID of message buffer (x) is used as a send message during transmission, and used as an
acceptance code during reception.
This must be set while the message buffer (x) is invalid (BVALx in the message buffer valid
register (BVALR) is "0"). If this is set while the buffer is valid (BVALx = 1), unnecessary
receive messages may be stored.
■ Setting Acceptance Filter
The acceptance filter of message buffer (x) is specified via the acceptance code and acceptance
mask setting. This must be set while the accepting message buffer (x) is invalid (BVALx in the
message buffer valid register (BVALR) is "0"). If this is set while the buffer is valid (BVALx =
1), unnecessary receive messages may be stored.
Set the acceptance mask which was used for each message buffer (x) in the acceptance mask
selection register (AMSR). The acceptance mask registers (AMR0 and AMR1) must also be
specified if they are used (For details of the setting, see Sections "18.3.17 Acceptance Mask
Selection Register (AMSR)" and "18.3.18 Acceptance Mask Registers 0 and 1 (AMR0/
AMR1)").
The acceptance mask must be set so that transmission request will not be cleared even when an
unnecessary receive message is stored. To send only messages with the same ID, for example,
the acceptance mask must be set to "full-bit compare".
■ Setting Low-power Consumption Mode
To set the F2MC-16LX to low-power consumption mode (stop, watch, etc.), write "1" to the
bus operation stop bit (HALT) in the control status register (CSR) and then check that the bus
operation is stopped (HALT = 1).
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CHAPTER 18 CAN CONTROLLER
18.7 Procedure of Transmission via Message Buffer (x)
MB90930 Series
18.7
Procedure of Transmission via Message Buffer (x)
After completing the settings of the bit timing, frame format, ID, and
acceptance filter, set BVALx to "1" to validate message buffer (x).
■ Procedure of Transmission Via Message Buffer (x)
● Setting the send data length code
Set the send data length code (in units of bytes) in DLC3 to DLC0 of the DLC register
(DLCRx).
For data frame transmission (when TRTRx in the transmission RTR register (TRTRR) is "0"),
specify the data length of the send message.
For remote frame transmission (when TRTRx = 1), specify the data length of the request
message (in units of bytes).
Setting values other than 0000B to 1000B (0 to 8 bytes) is disabled.
● Setting the send data (for data frame transmission only)
For data frame transmission (when TRTRx in the transmission RTR register (TRTRR) is "0"),
set the data in the data register (DTRx) as much as the number of send bytes.
The send data must be rewritten by setting the TREQx bit in the transmission request register
(TREQR) to "0".
It is unnecessary to set the BVALx bit in the message buffer valid register (BVALR) to "0".
Note that setting the BVALx bit to "0" may result in a loss of received remote frames.
● Setting the transmission RTR register
For data frame transmission, set TRTRx in the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
● Setting the send start conditions (for data frame transmission only)
To start transmission immediately after a request for data frame transmission is specified, set
RFWTx in the remote frame receive wait register (RFWTR) to "0" (TREQx in the transmission
request register (TREQR) is "1" and TRTRx in the transmission RTR register (TRTRR) is "0").
To delay the start of transmission until a remote frame is received (RRTRx in the remote
request receive register (RRTRR) becomes "1") after a request for data frame transmission is
specified (TREQx = 1 and TRTRx = 0), set RFWTx to "1".
When RFWTx is set to "1", remote frame transmission is disabled.
● Setting a transmission complete interrupt
To generate a transmission complete interrupt, set TIEx in the transmission interrupt enable
register (TIER) to "1".
Otherwise, set TIEx to "0".
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CHAPTER 18 CAN CONTROLLER
18.7 Procedure of Transmission via Message Buffer (x)
MB90930 Series
● Setting a transmission request
To make a transmission request, set TREQx in the transmission request register (TREQR) to
"1".
● Clearing a transmission request
To clear a transmission request to message buffer (x), write "1" to TCANx in the transmission
cancel register (TCANR).
Check TREQx. When TREQx = 0, transmission has been cleared or completed. Check TCx in
the transmission complete register (TCR). When TCx = 0, transmission has been cleared.
When TCx = 1, transmission has been completed.
● Processing for transmission completion
When transmission is successful, TCx in the transmission complete register (TCR) becomes
"1".
If transmission complete interrupts are enabled (TIEx in the transmission complete interrupt
enable register (TIER) is "1"), an interrupt is generated.
Check that transmission is completed, and then write "0" to TCx to set it to "0". This releases
the transmission complete interrupt.
The following transmission requests in wait state are cleared when a message is received or
stored:
• A request for data frame transmission based on data frame reception
• A request for remote frame transmission based on data frame reception
• A request for remote frame transmission based on remote frame reception
A request for data frame transmission is not cleared when a remote frame is received or stored.
However, the ID and DLC are changed with the ID and DLC of the received remote frame.
Note that the ID and DLC of the data frame to be sent will be the values of the received remote
frame.
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CHAPTER 18 CAN CONTROLLER
18.8 Procedure of Reception Via Message Buffer (x)
MB90930 Series
18.8
Procedure of Reception Via Message Buffer (x)
After completing the settings of the bit timing, frame format, ID, and
acceptance filter, make the following settings.
■ Procedure of Reception Via Message Buffer (x)
● Setting a receive interrupt
To enable receive interrupts, set RIEx in the receive interrupt enable register (RIER) to "1".
To disable receive interrupts, set RIEx to "0".
● Starting reception
To start reception after the setting, set BVALx in the message buffer valid register (BVALR) to
"1" to validate message buffer (x).
● Processing for receive completion
When a message is received successfully after passing through the acceptance filter, the receive
message is stored in message buffer (x), and RCx in the receive complete register (RCR)
becomes "1". For data frame reception, RRTRx in the remote request receive register (RRTRR)
becomes "0". For remote frame reception, RRTRx becomes "1".
When receive interrupts are enabled (RIEx in the receive interrupt enable register (RIER) is
"1"), an interrupt is generated.
Check the completion of reception (RCx = 1), and then process the receive message.
After completing the processing of the receive message, check ROVRx in the receive overrun
register (ROVRR).
When ROVRx = 0, the processed receive message is valid. Write "0" to RCx to set it to "0"
(the receive complete interrupt is also cleared), and finish reception.
When ROVRx = 1, a receive overrun may have occurred, which means that the processed
receive message may have been overwritten with another receive message. In such a case,
write "0" to the ROVRx bit to set it to "0", and then process the receive message again.
Figure 18.8-1 shows an example of receive interrupt handling.
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CHAPTER 18 CAN CONTROLLER
18.8 Procedure of Reception Via Message Buffer (x)
MB90930 Series
Figure 18.8-1 Example of Receive Interrupt Handling
Interrupt when RCx = 1
Read receive message
A := ROVRx
ROVRx := 0
A = 0?
NO
YES
RCx := 0
End
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CHAPTER 18 CAN CONTROLLER
18.9 Specifying the Multi-level Message Buffer Configuration
MB90930 Series
18.9
Specifying the Multi-level Message Buffer
Configuration
When the time to process messages is insufficient, such as when reception is
performed frequently or an unspecified number of messages are received,
combine more than one message buffer into a multi-level message buffer to
provide the CPU with some time reserve for processing receive messages.
■ Specifying the Multi-level Message Buffer Configuration
To prepare a multi-level message buffer, the same acceptance filter must be set to all of the
message buffers being combined.
If the bits in the acceptance mask selection register (AMSR) are set to all-bit compare [(AMSx.1,
AMSx.0) = (0, 0)], the message buffers cannot be configured to be a multi-level message
buffer. This is because all-bit compare stores receive messages regardless of the value of the
RCx bit in the receive complete register (RCR). This means that, even if all-bit compare and
the same acceptance code (ID register (IDRx)) are specified for more than one message buffer,
a receive message is always stored in the message buffer having the lower number (lower
priority). Therefore, you cannot specify all-bit compare and the same acceptance code to more
than one message buffer.
Figure 18.9-1 shows an example of multi-level message buffer operation.
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CHAPTER 18 CAN CONTROLLER
18.9 Specifying the Multi-level Message Buffer Configuration
MB90930 Series
Figure 18.9-1 Example of Multi-level Message Buffer Operation
: Initialized
AMS15, AMS14, AMS13
AMSR 10 10 10
AM28 to AM18
AMR0 is selected
AMS0
0000 1111 111
IDE
ID28 to ID18
RC15, RC14, RC13
Message buffer 13
0101 0000 000
0
RCR
0
0
0
Message buffer 14
0101 0000 000
0
ROVRR
0
0
0
Message buffer 15
0101 0000 000
ROVR15, ROVR14, ROVR13
Mask
Message is being received: Receive message is stored in message buffer 13.
IDE
ID28 to ID18
Message is being
received
0101 1111 000
0
Message buffer 13
0101 1111 000
0
Message buffer 14
0101 0000 000
Message buffer 15
0101 0000 000
RCR
0
0
1
ROVRR
0
0
0
0
Message is being received: Receive message is stored in message buffer 14.
Message is being
received
0101 1111 001
0
Message buffer 13
0101 1111 000
0
Message buffer 14
0101 1111 001
Message buffer 15
0101 0000 000
RCR
0
1
1
ROVRR
0
0
0
0
Message is being received: Receive message is stored in message buffer 15.
Message is being
received
0101 1111 010
0
Message buffer 13
0101 1111 000
0
Message buffer 14
0101 1111 001
Message buffer 15
0101 0000 010
RCR
1
1
1
ROVRR
0
0
0
0
Message is being received: When overrun occurs (ROVR = 13), receive message is stored in message
buffer 13.
Message is being
received
0101 1111 011
0
Message buffer 13
0101 1111 011
0
Message buffer 14
0101 1111 001
Message buffer 15
0101 0000 010
RCR
1
1
1
ROVRR
0
0
1
0
Note:
Four messages ar e re ceived by message buffers 13, 14, and 15 using t he same
acceptance filter setting.
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18.10 CAN WAKE UP Function
CHAPTER 18 CAN CONTROLLER
18.10 CAN WAKE UP Function
The RX1 pin is shared with INT1 pin respectively. Enabling an interrupt by INT1
allows WAKE UP by a CAN receive operation.
■ Pins Used for CAN WAKE UP Function
Since the RX1 pin is shared with the INT1 pin, enabling an interrupt by INT2 allows the use of
the WAKE UP function.
Table 18.10-1 shows the relationship among the CAN WAKE UP function, RX pin, and INT
pin.
Table 18.10-1 Relationship Among CAN WAKE UP Function, RX Pins, and INT Pins
CAN1
RX pin
Interrupt Function
RX1
INT1
■ CAN WAKE UP Function
By receiving CAN data, operation can be returned from sleep mode, time-base timer mode, or
stop mode.
Note:
To use the CAN WAKE UP function, it is nece ssary to set external interrupts before the
shift to sleep mode, time-base timer mode or stop mode.
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CHAPTER 18 CAN CONTROLLER
18.11 Precautions When Using CAN Controller
18.11
MB90930 Series
Precautions When Using CAN Controller
Using the CAN controller requires the following cautions.
■ Caution for Disabling Message Buffer by BVAL Bits
When the BVAL bits are used to disable message buffers in order to read/write contents of the
message buffer, the CAN controller may not perform send/receive operation properly. This
section describes the workaround of this phenomenon.
● Condition
When the following two conditions are satisfied at the same time, the CAN controller may not
perform send operation properly.
• The CAN controller is participating in a CAN communication. In other words, the read
value of the HALT bit is "0" and the CAN controller is ready for send/receive operation by
participating in a CAN bus communication.
• The BVAL bits are set to disable message buffers to read or write the contents of the
message buffers.
● Workaround
Operation for suppressing transmission request
To suppress or cancel a transmission request, use the TCAN bit instead of the BVAL bit.
Operation for composing send messages
To set the ID or IDE register to compose a send message, use the BVAL bit to disable
message buffers. To do this, read the transmission request bit to confirm that the bit is "0"
(TREQ = 0) or check the transmission complete bit to confirm the completion of
transmission (TC = 1) before setting the BVAL bit to disable the message buffer (BVAL =
0).
If transmit request was made in advance, be sure to verify that there is no pending transmit
request before invaliding the message buffer.
Never write "0" to BVALx bit until you check that transmit operation is not performed.
a) Cancel the transmission request (TCANx=1;), if necessary
b) and wait for the transmission completion (while (TREQx=1;)) by polling bit or transmission
complete interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note:
For case a), if transmission of that buffer has already started, canceling the transmission
is ignored and disabling the buffer is delayed until the end of the transmission.
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CHAPTER 18 CAN CONTROLLER
18.12 Sample Program of CAN
MB90930 Series
18.12 Sample Program of CAN
This section shows a sample program of CAN.
■ Sample Program for CAN Transmission/Reception
● Processing specifications
Set buffer 5 in CAN0 for data frame transmission, and buffer 0 for the reception.
• Set the frame format to the standard frame format.
• ID setting: Buffer 0: ID = 0, Buffer 5: ID = 5
• Bit rate is 100 kbps (internal operation frequency: f = 16 MHz)
• Acceptance mask (full-bit compare)
• After the entry to the bus (HALT = 0), send data A0A0H.
• Issue a transmission request (TREQx = 1) in the transmission complete interrupt routine and
send the same data (Setting TREQx to transmission start clears the transmission complete
interrupt flag.)
• In the receive interrupt routine, clear the receive interrupt flag.
[Coding example]
:
:
:
//data format set (CAN initialize)
MOVW IDER0, #0000H
; Frame format setting (0: set, 1:
; extended)
MOVW BTR0, #05CC7H
; Bit rate setting to 100 kbps
; (internal operation frequency:
; f = 16 MHz)
MOVW BVALR0, #21H
; Message buffer 5, 0 valid
MOVW IDR51, #0A000H
; Data frame 5ID setting (ID = 0005)
MOVW IDR01, #2000H
; Data frame 0ID setting (ID = 0001)
MOVW ANSR00, #0000H
; Acceptance mask selection register
; (full-bit compare)
//send setting
MOVW DLCR5, #020H
MOVW
MOVW
RFTR0, #0000H
TRTR0, #0000H
MOVW
TIRER0, #0020H
;
;
;
;
;
;
;
Transfer data length setting
(00H:0-byte length,08H:8-byte length)
Remote frame receive wait register
Remote transmission request
(0: data transfer, 1: remote frame
send)
Transmission interrupt enable register
//send setting
MOVW RIER5, #0001H
; Receive interrupt enable register
//bus operation start
MOVW CSR00, #80H
shift BBS
CSR00:0, shift
; Control status register (HALT = 0)
; HALT = 0 waiting
//send data setting
MOVW DTR50, #0A0A0H
CM44-10150-1E
; Write A0A0H to data register in message
; buffer 5
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CHAPTER 18 CAN CONTROLLER
18.12 Sample Program of CAN
MOVW
TREQR0, #0020H
MB90930 Series
; Transmission request register
; (1: transmission start, 0:
; transmission stop)
:
:
//receive complete interrupt
CAN0RX MOVW, #0000H
; Receive complete register
RETI
//transmission complete interrupt
CAN0TX MOVW TREQR0, #0020H
; Transmission request register
; (1:transmission complete, 0:
; transmission stop)
RETI
:
:
:
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CHAPTER 19
LCD CONTROLLER/
DRIVER
This chapter describes the functions and
operations of the LCD controller/driver.
19.1 Overview of LCD Controller/Driver
19.2 Configuration of LCD Controller/Driver
19.3 LCD Controller/Driver Pins
19.4 Registers of LCD Controller/Driver
19.5 LCD Controller/Driver Display RAM
19.6 Operation of LCD Controller/Driver
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.1 Overview of LCD Controller/Driver
19.1
MB90930 Series
Overview of LCD Controller/Driver
The LCD controller/driver has a built-in display data memory of 16 × 8 bits and
controls the LCD display with 4 common outputs and 32 segment outputs.
Three types of duty output can be selected to directly drive the LCD (Liquid
Crystal Display) panel.
■ Functions of LCD Controller/Driver
The LCD controller/driver has the function that directly displays the contents of the display
data memory (Display RAM) using the common and segment outputs.
• It has a built-in LCD drive voltage divide resistor. It also allows connection with an external
divide resistor.
• Available up to four common outputs (COM0 to COM3) and 32 segment outputs (SEG00 to
SEG31).
• It has a built-in 16-byte display data memory (display RAM).
• Selects a duty cycle of 1/2, 1/3, or 1/4 (limited by bias setting).
• Directly drives the LCD.
Table 19.1-1 shows the available combinations of bias duty.
Table 19.1-1 Combinations of Bias Duties
Bias
1/2 duty
1/3 duty
1/4 duty
1/2 bias
Y
N
N
1/3 bias
N
Y
Y
Y : Recommended mode
N : Use prohibited
Note:
Each SEG pin cannot b e u sed as t he seg ment output if t he ge neral-purpose port is
selected in the LCRH, LOCR1, and LOCR2 setting.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
19.2
Configuration of LCD Controller/Driver
The LCD controller/driver contains the following 8 blocks. It functionally
consists of two sections: the controller section where a segment and common
signals are generated according to the contents of the display RAM, and the
driver section, which drives the LCD.
• LCD control register (LCRL/LCRH)
• Display RAM
• Prescaler
• Timing controller
• AC circuit
• Common driver
• Segment driver
• Divide resistor
■ Block Diagram of LCD Controller/Driver
Figure 19.2-1 shows the block diagram of the LCD controller/driver.
Figure 19.2-1 Block Diagram of LCD Controller/Driver
V0 V1 V2 V3
Lower bits in LCD
control register
(LCRL)
Divide resistor
4
Time-base
timer output
Sub Clock
Circuit AC circuit
Internal data bus
Prescaler
Timing
controller
Common
driver
32
Display RAM
16 × 8 bits
Segment
driver
COM0
COM1
COM2
COM3
SEG00
SEG01
SEG02
SEG03
SEG04
to
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
Upper bits in LCD
control register
(LCRH)
Controller
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Driver
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
● Lower bits in the LCD control register (LCRL)
Performs LCD drive power control, and selects display/display blanking, display mode
selection, and LCD clock interval selection.
● Upper bits in the LCD control register (LCRH)
Switches between segment outputs (SEG12 to SEG23) and the general-purpose port.
● LCD output control register 1/2 (LOCR1/LOCR2)
Switches between segment outputs (SEG00 to SEG11, SEG24 to SEG31) and the generalpurpose port.
● LCD output control register 3 (LOCR3)
Switches between reference power supply pins (V0 to V2) and the general-purpose port.
● Display RAM
16 × 8-bit RAM to generate a segment output signal. The RAM data is automatically read in
synchronization with the selected timing of the common signal and output from the segment
output pin.
● Prescaler
Generates one of four frame frequencies depending on its setting.
● Timing controller
Controls the common signal and segment signal based on the setting of the frame frequency
and LCRL register.
● AC circuit
Generates the AC waveform used for driving the LCD from the timing controller signal.
● Common driver
A driver for the LCD common pin.
● Segment driver
A driver for the LCD segment pin.
● Divide resistor
Divides the LCD drive current to generate. The divide resistor can be used as external.
■ Power Supply Voltage of LCD Controller/Driver
The LCD driver's power supply voltage is determined using a built-in divide resistor or by
connecting a divide resistor to pins V0 to V3.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
19.2.1
Internal Divided Resistor of LCD Controller/Driver
The LCD driver's power supply voltage is generated via an external divide
resistor connected to pins V0 to V3 or an internal divide resistor.
■ Internal Divided Resistor of LCD Controller/Driver
The LCD controller/driver has a built-in internal divide resistor. Alternatively, the LCD drive
power supply pins (V0 to V3) can be connected to connect the external divide resistors.
The internal divide resistor and external divide resistor are selected by the LCD control
register's drive power supply control bit (LCRL: VSEL). Setting the VSEL bit to "1" allows the
internal divide resistor to enter the current-carrying state. Therefore, set it to "1" if the internal
divide resistor is to be used instead of the external divide register.
The LCD controller enable is inactive at LCD operation stop (LCRL: MS1, MS0 = 00B).
Figure 19.2-2 shows an equivalent circuit of the internal divide resistor.
Figure 19.2-2 Equivalent Circuit of Internal Divide Resistor
VCC
V3
V3
P-ch
N-ch
V2
P-ch
V2
R
N-ch
V1
P-ch
V0
R
V1
R
N-ch
LCD Controller
enable
V0
N-ch
VSEL
V0 to V3: Voltage between V0 to V3
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
■ Using the Internal Divided Resistor
Even if the internal divide resistor is used, connect an external resistor between VCC and V3.
Figure 19.2-3 shows a state when using the internal divide resistor.
When specifying the 1/2 bias setting, short the V2 and V1 pins.
Figure 19.2-3 A State When Using the Internal Divide Resistor
VCC
VCC
VR
VR
V3
V3
V3
V2
R
V2
R
R
V0
V0
N-ch
LCD Controller
enable
R
V1
V1
V0
R
V2
Short
R
V1
V3
V1
V0
N-ch
LCD Controller
enable
1/2 bias
V2
1/3 bias
V0 to V3: Voltage between V0 to V3
■ Brightness Adjustment When Using the Internal Divided Resistor
Unless the brightness is increased by using the internal divide resistor, connect an external
variable resistor (VR) between VCC and V3 as shown in Figure 19.2-4 to adjust the V3 voltage.
Figure 19.2-4 Brightness Adjustment When Using the Internal Divide Resistor
VCC
VR
V3
V2
V1
V0
LCD Controller
enable
V3
R
R
R
V2
V1
V0
N-ch
To control the brightness
V0 to V3: Voltage between V0 to V3
556
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
19.2.2
External Divided Resistor of LCD Controller/Driver
An external divide resistor or internal divide resistor is used to generate the
LCD drive voltage.
The brightness can be controlled by connecting a variable resistor between the
VCC and V3 pins.
■ External Divided Resistor of LCD Controller/Driver
An external divide resistor can be connected between the LCD drive power supply pins (V0 to
V3). Figure 19.2-5 and Table 19.2-1 show the connection of the external divide resistor and
LCD drive voltage based on the bias method.
Figure 19.2-5 Example Connection of the External Divide Resistor
VCC
V3
V2
VCC
VR
VR
V3
R
R
V2
VLCD
R
V1
V0
VLCD
V1
R
R
V0
V0=VSS
V0=VSS
1/2 bias
1/3 bias
Table 19.2-1 Setting the LCD Drive Voltage
V3
V2
V1
V0
1/2 bias
VLCD
1/2VLCD
1/2VLCD
VSS
1/3 bias
VLCD
2/3VLCD
1/3VLCD
VSS
V0 to V3 : Voltage between V0 to V3 pins
: LCD operating voltage
VLCD
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.2 Configuration of LCD Controller/Driver
MB90930 Series
■ Using the External Divide Resistor
If an external divide resistor is used, the current that flows into the resistor when the LCD
controller is stopped can be blocked by connecting the VSS side of the divide resistor to the V0
pin only, because the V0 pin is connected to VSS (GND) via an internal transistor.
Figure 19.2-6 shows the state when using an external divide resistor.
Figure 19.2-6 A State When Using an External Divide Resistor
VCC
V3
V3
V2
V1
V0
LCD controller enable
R
V2
R
V1
R
V0
VR
RX
RX
RX
V0=VSS
N-ch
• To connect an external resistor to inhibit the influence from the internal divide resistor,
write "0" to the LCD control register's drive voltage control bit (LCRL: VSEL) to
disconnect the entire internal divide resistor.
• Writing a value except "00B" to the display mode selection bits (LCRL: MS1, MS0) in the
LCD control register while the internal divide resistor is disconnected, the LCDC enable
transistor (N-ch) is set to "ON", and the current will pass through the external divide
resistor.
• On the other hand, writing "00B" to the display mode selection bits (MS1, MS0) turns the
LCDC enable transistor "OFF", and the current stops passing through the external divide
resistor.
Note:
The RX value for the external resistor depends on t he LCD used. Select an appropriate
value.
558
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.3 LCD Controller/Driver Pins
MB90930 Series
19.3
LCD Controller/Driver Pins
The pins of the LCD controller/driver and their block diagram are shown in this
section.
■ Pins of the LCD Controller/Driver
The pins of the LCD controller/driver include 4 common output pins (COM0 to COM3), 32
segment output pins (SEG00 to SEG31), and 4 LCD drive power supply pins (V0 to V3).
● COM0 to COM3 pins
COM0 to COM3 pins are used as the LCD common output pins.
● P22/SEG00 to P35/SEG11, P36/SEG12 to P43/SEG17, P44/SEG18 to P47/SEG21, P90/
SEG22, P91/SEG23 and P00/SEG24 to P07/SEG31
All of pins above can function both as the general-purpose I/O port and as the LCD segment
output pin. These functions are switched by setting LCRH, LOCR1 or LOCR2 register.
● V0 to V3 pins
The V0 to V3 pins are used as the LCD drive power supply pins (V0 to V3).
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.3 LCD Controller/Driver Pins
MB90930 Series
■ Block Diagram of LCD Controller/Driver Pins
Figure 19.3-1 shows a block diagram of multiplexed pins with segment output.
Figure 19.3-1 Block Diagram of LCD Controller/Driver Pins
Multi-use pins with segment output
Common segment control signal
P-ch
LCD drive voltage (V3 or V2)
N-ch
Reset operation stop signal
LCRH setting
N-ch
P-ch
LCD drive voltage (V1 or V0)
N-ch
Common segment control signal
Internal data bus
PDR (Port direction register)
Stop mode (SPL=1)
or LCD enable
PDR read
PDR read (bit operation instruction)
Output latch
P-ch
PDR write
Pin
DDR
DDR write
(Port data register)
N-ch
P00/SEG24 to P07/SEG31
P22/SEG00 to P27/SEG05
P30/SEG06 to P37/SEG13
P40/SEG14 to P47/SEG21
P90/SEG22, P91/SEG23
Stop mode (SPL=1) or LCD enable
SPL: The pin state specification in the low-power consumption mode control register (LPMCR)
V0 to V3 : Voltages of V0 to V3 pins
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
MB90930 Series
19.4
Registers of LCD Controller/Driver
This section describes the registers of the LCD controller/driver.
■ Bit Configuration of LCD Controller/Driver Register
Figure 19.4-1 shows the bit configuration of the registers of the LCD controller/driver.
Figure 19.4-1 Bit Configuration of LCD Controller/Driver Related Register
LCRL (lower bits in the LCDC control register)
Address
00006CH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CSS
R/W
LCEN
R/W
VSEL
R/W
BK
R/W
MS1
R/W
MS0
R/W
FP1
R/W
FP0
R/W
00010000B
bit11
bit10
bit9
bit8
Initial value
SEG0
R/W
00000000B
LCRH (upper bits in the LCDC control register)
Address
00006DH
bit15
Reserved
R/W
bit14
SEG5
R/W
bit13
SEG4
R/W
bit12
DTCH
R/W
SEG3
R/W
SEG2
R/W
SEG1
R/W
R/W: Readable/Writable
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
19.4.1
MB90930 Series
Lower Bits in the LCD Control Register (LCRL)
The lower bits in the LCD control register (LCRL) are used to control the drive
power, select display blanking, and select the display mode.
■ Bit Configuration of the Lower Bits in the LCD Control Register (LCRL)
shows the bit configuration of the lower bits in the LCD control register (LCRL).Bit
Configuration of the Lower Bits in the LCD Control Register (LCRL)
Address
00006CH
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CSS LCEN VSEL
bit7
BK
MS1
MS0
FP1
FP0
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
bit6
R/W
R/W
Frame interval selection bit
FP1 FP0 Select time-base timer
Select sub clock
output(CSS=0)
(CSS=1)
0
0
1
1
0
1
Fc/(211 × N )
SCLK/(25 × N )
Fc/(212
× N )
SCLK/(26 × N )
0
Fc/(213
× N )
SCLK/(27 × N )
1
14
× N )
SCLK/(28 × N )
Fc/(2
N: Time-division count
Fc: Original oscillation
SCLK: Sub clock
MS1 MS0
0
0
1
LCD operation stop
1/2 duty output mode (time division)
1
0
1/3 duty output mode (time division)
1
1
1/4 duty output mode (time division)
BK
0
1
VSEL
562
Display blanking selection bit
Display
Display blanking
LCD drive power control bit
0
External divide resistor used
1
Internal divide resistor used
LCEN
R/W : Reading/writing permitted
: Initial value
Display mode selection bit
0
Watch mode operation enable bit
0
Stops watch mode operation
1
Does not stop watch mode operation
CSS
Clock selection bit
0
Select time-base timer output
1
Select a sub clock
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MB90930 Series
CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
Table 19.4-1 Functions of Each Lower Bit in the LCD Control Register (LCRL)
Bit name
Function
bit7
CSS:
Clock selection
bit
The selection bit for the frame interval generation clock.
If this bit is set to "0", the time-base timer clock output is selected. If this bit is set
to "1", the sub clock is selected.
bit6
LCEN:
time-base timer
mode operation
enable bit
The operation enable bit during the time-base timer mode.
In time-base timer mode, if this bit is set to "0", the operation stops. If this bit is set
to "1", operation starts.
bit5
VSEL:
LCD drive
power control bit
Selects whether the electricity is turned on to the internal divide resistor.
If this bit is set to "0", the internal divide resistor is cut-off. If this bit is set to "1",
the electricity is turned on to the internal divide resistor. To connect an external
divide resistor, this bit must be set to "0".
bit4
BK:
Display blanking
selection bit
Selects LCD display/nondisplay.
When in the display section blanking mode (nondisplay, BK = 1), the segment
output takes a non-select waveform (that doesn't meet the display conditions).
bit3,
bit2
MS1, MS0:
Display mode
selection bit
Select one of 3 duties for the output waveform.
The common pin is specified according to the selected duty output mode.
If these bits are set to "0", the LCD controller/driver will stop the display
operation.
Note:
If the selected frame interval generation clock stops due to a transition to the stop
mode, the display operation should be stopped in advance.
bit1,
bit0
FP1, FP0:
Frame interval
selection bit
CM44-10150-1E
Select one of 4 frame intervals for the LCD display.
Note:
When setting the register, calculate the optimal frame frequency for the LCD module to
be used.
The frame frequency is affected by the original oscillator frequency.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
19.4.2
MB90930 Series
Upper Bits in the LCD Control Register (LCRH)
This register is used to select bias mode, switch between segment output
(SEG12 to SEG23) and general-purpose port (P36, P37, P40 to P47, P90, P91).
■ Bit Configuration of the Upper Bits in the LCD Control Register (LCRH)
Figure 19.4-2 shows the bit configuration of the upper bits in the LCD control register
(LCRH).
Figure 19.4-2 Bit Configuration of the Upper Bits in the LCD Control Register (LCRH)
Address
bit15 bit14 bit13 bit12 bit11 bit10
bit9
Initial value
bit8
Re00006DH served
SEG5 SEG4 DTCH SEG3 SEG2 SEG1 SEG0
R/W
R/W
R/W
R/W
R/W R/W
00000000 B
R/W R/W
Bias selection bit
DTCH
0
1/3 bias
1
1/2 bias
SEG SEG SEG SEG SEG SEG
5
4
3
2
1
0
Segment output
none
General-purpose port
0
0
0
0
0
0
0
0
0
0
0
1
SEG12 to SEG15 P42 to P47,P90,P91
0
0
0
0
1
1
SEG12 to SEG19 P46,P47,P90,P91
0
0
0
1
1
1
SEG12 to SEG20 P47,P90,P91
0
0
1
1
1
1
SEG12 to SEG21 P90,P91
0
1
1
1
1
1
SEG12 to SEG22 P91
1
1
1
1
1
1
SEG12 to SEG23 None
Reserved
R/W :Readable/Writable
Segment output
P36,P37,P40 to P47,P90,P91
Reserved bit
Always set this bit to "0".
: Initial value
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
MB90930 Series
Table 19.4-2 Functions of Each Upper Bit in the LCD Control Register (LCRH)
Bit name
Function
bit15
Reserved:
Reserved bit
Be sure to set this bit to "0".
bit14
SEG5:
Segment pin
switch bit
Switches whether to use the P91/SEG23 pin as the segment output or general-purpose
port.
bit13
SEG4:
Segment pin
switch bit
Switches whether to use the P90/SEG22 pin as the segment output or general-purpose
port.
bit12
DTCH:
Bias selection
bit
Selects 1/2 or 1/3 bias mode is used for internal divide resistor.
If this bit is set to "0", the 1/2 bias mode is used. If this bit is set to "1", 1/3 bias mode
is used. To use 1/2 bias mode, please short terminal V1 and V2 for using external
resistor (LCRL: VSEL=0), or set this bit to "1" for using internal resister (LCRL:
VSEL=1) to short inside the device.
bit11
SEG3:
Segment pin
switch bit
Switches whether to use the P47/SEG21 pin as the segment output or general-purpose
port.
bit10
SEG2:
Segment pin
switch bit
Switches whether to use the P46/SEG20 pin as the segment output or general-purpose
port.
bit9
SEG1:
Segment pin
switch bit
Switches whether to use the P42/SEG16 to P45/SEG19 pins as the segment output or
general-purpose port.
bit8
SEG0:
Segment pin
switch bit
Switches whether to use the P36/SEG12 to P37/SEG13 and P40/SEG14 to P41/
SEG15 pins as the segment output or general-purpose port.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
19.4.3
MB90930 Series
LCD Output Control Register 2/1 (LOCR2/LOCR1)
These registers are used to switch between segment output (SEG00 to SEG11,
SEG24 to SEG31) and general-purpose port (P22 to P27, P30 to P35, P00 to
P07).
■ Bit Configuration of the LCD Output Control Register 2/1 (LOCR2/LOCR1)
Figure 19.4-3 shows the bit configuration of the LCD output control register 2/1 (LOCR2/
LOCR1).
Figure 19.4-3 Bit Configuration of the LCD Output Control Register 2/1 (LOCR2/LOCR1)
LOCR1
bit7
bit6
bit5
bit4
Address 000058H SEG10_11 SEG08_09 SEG06_07 SEG04_05
R/W
Initial alue
LOCR2
Address 000059H
Initial alue
bit3
bit2
bit1
bit0
SEG03
SEG02
SEG01
SEG00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
v 0
v 0
R/W :Readable/Writable
Table 19.4-3 Setting and Pin Functions of LCD Output Control Register 2/1
(LOCR2/LOCR1) (1 / 2)
Segment output
SEG31 to SEG24
SEG10_11 to SEG00
Segment output
General-purpose port
Initial value 00000000B
Initial value 11111111B SEG00 to SEG11 P00 to P07
Initial value 00000000B
Initial value 11111110B SEG01 to SEG11 P00 to P07, P22
Initial value 00000000B
Initial value 11111100B SEG02 to SEG11 P00 to P07, P22 to P23
Initial value 00000000B
Initial value 11111000B SEG03 to SEG11 P00 to P07, P22 to P24
Initial value 00000000B
Initial value 11110000B SEG04 to SEG11 P00 to P07, P22 to P25
Initial value 00000000B
Initial value 11100000B SEG06 to SEG11 P00 to P07, P22 to P27
Initial value 00000000B
Initial value 11000000B SEG08 to SEG11 P00 to P07, P22 to P27, P30 to P31
Initial value 00000000B
Initial value 10000000B SEG10, SEG11
P00 to P07, P22 to P27, P30 to P33
Initial value 00000000B
Initial value 00000000B None
P00 to P07, P22 to P27, P30 to P35
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
MB90930 Series
Table 19.4-3 Setting and Pin Functions of LCD Output Control Register 2/1
(LOCR2/LOCR1) (2 / 2)
Segment output
SEG31 to SEG24
SEG10_11 to SEG00
Segment output
General-purpose port
Initial value 00000001B
Initial value 00000000B SEG24
P01 to P07, P22 to P27, P30 to P35
Initial value 00000011B
Initial value 00000000B SEG24, SEG25
P02 to P07, P22 to P27, P30 to P35
Initial value 00000111B
Initial value 00000000B SEG24 to SEG26 P03 to P07, P22 to P27, P30 to P35
Initial value 00001111B
Initial value 00000000B SEG24 to SEG27 P04 to P07, P22 to P27, P30 to P35
Initial value 00011111B
Initial value 00000000B SEG24 to SEG28 P05 to P07, P22 to P27, P30 to P35
Initial value 00111111B
Initial value 00000000B SEG24 to SEG29 P06, P07, P22 to P27, P30 to P35
Initial value 01111111B
Initial value 00000000B SEG24 to SEG30 P07, P22 to P27, P30 to P35
Initial value 11111111B
Initial value 00000000B SEG24 to SEG31 P22 to P27, P30 to P35
Table 19.4-4 Functions of Each Bit in the LCD Output Control Register 1 (LOCR1)
Bit name
Function
bit7
SEG10_11:
Segment pin switch bit
Switches whether to use the P34/SEG10 and P35/SEG11 pins as the segment
output or general-purpose port.
bit6
SEG08_09:
Segment pin switch bit
Switches whether to use the P32/SEG08 and P33/SEG09 pins as the segment
output or general-purpose port.
bit5
SEG06_07:
Segment pin switch bit
Switches whether to use the P30/SEG06 and P31/SEG07 pins as the segment
output or general-purpose port.
bit4
SEG04_05:
Segment pin switch bit
Switches whether to use the P26/SEG04 and P27/SEG05 pins as the segment
output or general-purpose port.
bit3
SEG03:
Segment pin switch bit
Switches whether to use the P25/SEG03 pin as the segment output or
general-purpose port.
bit2
SEG02:
Segment pin switch bit
Switches whether to use the P24/SEG02 pin as the segment output or
general-purpose port.
bit1
SEG01:
Segment pin switch bit
Switches whether to use the P23/SEG01 pin as the segment output or
general-purpose port.
bit0
SEG00:
Segment pin switch bit
Switches whether to use the P22/SEG00 pin as the segment output or
general-purpose port.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
MB90930 Series
Table 19.4-5 Functions of Each Bit in the LCD Output Control Register 2 (LOCR2)
Bit name
Function
bit15
SEG31:
Switches whether to use the P07/SEG31 pin as the segment output or generalSegment pin switch bit purpose port.
bit14
SEG30:
Switches whether to use the P06/SEG30 pin as the segment output or generalSegment pin switch bit purpose port.
bit13
SEG29:
Switches whether to use the P05/SEG29 pin as the segment output or generalSegment pin switch bit purpose port.
bit12
SEG28:
Switches whether to use the P04/SEG28 pin as the segment output or generalSegment pin switch bit purpose port.
bit11
SEG27:
Switches whether to use the P03/SEG27 pin as the segment output or generalSegment pin switch bit purpose port.
bit10
SEG26:
Switches whether to use the P02/SEG26 pin as the segment output or generalSegment pin switch bit purpose port.
bit9
SEG25:
Switches whether to use the P01/SEG25 pin as the segment output or generalSegment pin switch bit purpose port.
bit8
SEG24:
Switches whether to use the P00/SEG24 pin as the segment output or generalSegment pin switch bit purpose port.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.4 Registers of LCD Controller/Driver
MB90930 Series
19.4.4
LCD Output Control Register 3 (LOCR3)
This register is used to switch between reference power supply pins (V0 to V2)
and general-purpose port (P94 to P96) of the LCD controller/driver.
■ Bit Configuration of the LCD Output Control Register 3 (LOCR3)
Figure 19.4-4 shows the bit configuration of the LCD output control register 3 (LOCR3).
Figure 19.4-4 Bit Configuration of the LCD Output Control Register 3 (LOCR3)
LOCR3
Address 000088H
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
−
−
Reserved
Reserved
−
V2
V1
V0
−
−
R/W
R/W
−
R/W
R/W
R/W
×
×
0
0
×
1
1
1
R/W :Readable/Writable
- : Undefined
Table 19.4-6 Functions of Each Bit in the LCD Output Control Register 3 (LOCR3)
Bit name
Function
bit7
Unused bit
Writing has no effect on operation.
bit6
Unused bit
Writing has no effect on operation.
bit5
Reserved bit
Always write "0" to this bit.
bit4
Reserved bit
Always write "0" to this bit.
bit3
Unused bit
Writing has no effect on operation.
bit2
V2:
LCDC pin
power supply
switch bit
This bit switches whether to use the P96/V2 pin as the LCDC power supply pin or
general-purpose port.
0: P96
1: V2
bit1
V1:
LCDC pin
power supply
switch bit
This bit switches whether to use the P95/V1 pin as the LCDC power supply pin or
general-purpose port.
0: P95
1: V1
bit0
V0:
LCDC power
supply pin
switch bit
This bit switches whether to use the P94/V0 pin as the LCDC power supply pin or
general-purpose port.
0: P94
1: V0
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.5 LCD Controller/Driver Display RAM
19.5
MB90930 Series
LCD Controller/Driver Display RAM
The display RAM is a 16 × 8 bits display data memory to generate a segment
output signal.
■ Display RAM and Output Pins
The RAM data is automatically read out in synchronization with the selected timing of the
common signal and output from the segment output pin.
The contents of the VRAM are output from the segment output pin at the same time of writing
to the display RAM.
If the content of each bit is "1", the segment output signal is converted to the selected voltage
(LCD displayed). If the content of each bit is "0", the segment output signal is converted to the
nonselect voltage (LCD not displayed) and then output.
The LCD display operates independently of the CPU, therefore reading and writing of the
display RAM can be performed with any timing.
Pins among Pin SEG00 to SEG31 that are not specified by the LCRH, LOCR1 and LOCR2
registers as the segment output can be used as general-purpose ports, and the corresponding
RAM area can be used as normal RAM (Table 19.5-1).
Table 19.5-1 shows the relationship between the duty value, common output, and display
RAM.
Figure 19.5-1 shows the relationship between display RAM, common output pins, and segment
output pins.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.5 LCD Controller/Driver Display RAM
MB90930 Series
Figure 19.5-1 Display RAM and Correspondence between Common Output Pins
and Segment Output Pins
Address
3960H
3961H
3962H
3963H
3964H
3965H
3966H
3967H
3968H
3969H
396AH
396BH
396CH
396DH
396EH
396FH
CM44-10150-1E
COM3
COM2
COM1
COM0
bit3
bit2
bit1
bit0
SEG00
bit7
bit6
bit5
bit4
SEG01
bit11
bit10
bit9
bit8
SEG02
bit15
bit14
bit13
bit12
SEG03
bit3
bit2
bit1
bit0
SEG04
bit7
bit6
bit5
bit4
SEG05
bit11
bit10
bit9
bit8
SEG06
bit15
bit14
bit13
bit12
SEG07
bit3
bit2
bit1
bit0
SEG08
bit7
bit6
bit5
bit4
SEG09
bit11
bit10
bit9
bit8
SEG10
bit15
bit14
bit13
bit12
SEG11
bit3
bit2
bit1
bit0
SEG12
bit7
bit6
bit5
bit4
SEG13
bit11
bit10
bit9
bit8
SEG14
bit15
bit14
bit13
bit12
SEG15
bit3
bit2
bit1
bit0
SEG16
bit7
bit6
bit5
bit4
SEG17
bit11
bit10
bit9
bit8
SEG18
bit15
bit14
bit13
bit12
SEG19
bit3
bit2
bit1
bit0
SEG20
bit7
bit6
bit5
bit4
SEG21
bit11
bit10
bit9
bit8
SEG22
bit15
bit14
bit13
bit12
SEG23
bit3
bit2
bit1
bit0
SEG24
bit7
bit6
bit5
bit4
SEG25
bit11
bit10
bit9
bit8
SEG26
bit15
bit14
bit13
bit12
SEG27
bit3
bit2
bit1
bit0
SEG28
bit7
bit6
bit5
bit4
SEG29
bit11
bit10
bit9
bit8
SEG30
bit15
bit14
bit13
bit12
SEG31
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.5 LCD Controller/Driver Display RAM
MB90930 Series
Table 19.5-1 Relationship between Display RAM and Segment Output Pins, and Multiplexed Pins
Value of SEG5 to SEG0
bits in the LCRH register
Segment to output
Display RAM area
00_0000B
None
-
P36 to P47, P90, P91
00_0001B
SEG12 to SEG15
3966H, 3967H
P42 to P47, P90, P91
00_0011B
SEG12 to SEG19
3966H to 3969H
P46, P47, P90, P91
00_0111B
SEG12 to SEG20
3966H to 396AH
P47, P90, P91
00_1111B
SEG12 to SEG21
3966H to 396AH
P90, P91
01_1111B
SEG12 to EG22
3966H to 396BH
P91
11_1111B
SEG12 to SEG23
3966H to 396BH
None
Pins used as
general-purpose port
Table 19.5-2 Relation of pin that corresponds to LCD output control register 2/1
(LOCR2/LOCR1)
LOCR2 register
SEG31 to
SEG24
LOCR1 register
SEG10_11 to
SEG00
Segment to output
Display RAM area
00000000B
11111111B
SEG00 to SEG11
3960H to 3965H
P00 to P07
00000000B
11111110B
SEG01 to SEG11
3960H to 3965H
P00 to P07, P22
00000000B
11111100B
SEG02 to SEG11
3961H to 3965H
P00 to P07, P22, P23
00000000B
11111000B
SEG03 to SEG11
3961H to 3965H
P00 to P07, P22 to P24
00000000B
11110000B
SEG04 to SEG11
3962H to 3965H
P00 to P07, P22 to P25
00000000B
11100000B
SEG06 to SEG11
396H to 3965H
P00 to P07, P22 to P27
00000000B
11000000B
SEG08 to SEG11
3964H to 3965H
P00 to P07, P22 to P27, P30, P31
00000000B
10000000B
SEG10, SEG11
3965H
P00 to P07, P22 to P27, P30 to
P33
00000000B
00000000B
None
-
P00 to P07, P22 to P27, P30 to
P35
00000001B
00000000B
SEG24
396CH
P01 to P07, P22 to P27, P30 to
P35
00000011B
00000000B
SEG24, SEG25
396CH
P02 to P07, P22 to P27, P30 to
P35
00000111B
00000000B
SEG24 to SEG26
396CH, 396DH
P03 to P07, P22 to P27, P30 to
P35
00001111B
00000000B
SEG24 to SEG27
396CH, 396DH
P04 to P07, P22 to P27, P30 to
P35
00011111B
00000000B
SEG24 to SEG28
396CH to 396EH
P05 to P07, P22 to P27, P30 to
P35
00111111B
00000000B
SEG24 to SEG29
396CH to 396EH
P06, P07, P22 to P27, P30 to P35
01111111B
00000000B
SEG24 to SEG30
396CH to 396FH
P07, P22 to P27, P30 to P35
11111111B
00000000B
SEG24 to SEG31
396CH to 396FH
P22 to P27, P30 to P35
Pin used as generalpurpose port
Note: RAM area which is not used as display allows to be used as the normal RAM. The byte access is only available.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.5 LCD Controller/Driver Display RAM
MB90930 Series
Table 19.5-3 Relationship between Duty, Common Output, and Bits Used as Display RAM
Bits used for each display data
Duty setting
value
Common output
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1/2
COM0, COM1 (2)
N
N
Y
Y
N
N
Y
Y
1/3
COM0 to COM2 (3)
N
Y
Y
Y
N
Y
Y
Y
1/4
COM0 to COM3 (4)
Y
Y
Y
Y
Y
Y
Y
Y
Y: Used
N: Not used
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
19.6
MB90930 Series
Operation of LCD Controller/Driver
The LCD controller/driver controls and drives the LCD display.
■ Operation of LCD Controller/Driver
The settings shown in Figure 19.6-1 are required for the LCD display.
Figure 19.6-1 Settings of LCD Controller/Driver
bit15 bit14 bit13 bit12 bit11 bit10 bit9
LCRH/LCRL
bit8
bit7
bit6
bit5
Reserved SEG5 SEG4 DTCH SEG3 SEG2 SEG1 SEG0 CSS LCEN VSEL
bit4
bit3
bit1
bit0
BK
MS1 MS0 FP1
FP0
0
Other than 00B
bit15 bit14 bit13 bit12 bit11 bit10 bit9
LOCR2/LOCR1
bit2
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG10_11 SEG08_09 SEG06_07 SEG04_05 SEG03 SEG02 SEG01 SEG00
bit7
bit6
bit5
bit4
ReReserved served
LOCR3
0
Display RAM
3960H to 396FH
bit3
bit2
bit1
bit0
V2
V1
V0
0
Display data
: Used bit
0 : Set to "0"
When you setup the LCD controller/driver as above, and the selected frame interval generation
clock is oscillating, the LCD panel's drive waveform is output to the common/segment output
pins (COM0 to COM3, SEG00 to SEG31) according to the display RAM.
The frame interval generation clock can be switched even during LCD display operation.
However, the display may flicker in the event of switching, therefore, stop the display
temporarily with blanking (LCRL: BK = 1) before switching the clock.
The display drive output is a two-frame AC waveform selected by the bias and duty settings.
COM2/COM3 pin output in case of a duty setting of 1/2 takes a non-select level waveform.
Similarly, the COM3 pin output in case of a duty setting of 1/3 takes a nonselect level
waveform.
If the LCD display operation stops (LCRL: MS1, MS0 = 00B) or is being reset, both common/
segment output pins enter "L" level.
Note:
If th e f rame in terval gen eration clo ck st ops du ring t he LCD displa y o peration, th e AC
circuit will stop, and then the curr ent is directly applied to th e LCD element. In this case,
the LCD display operation must be sto pped in ad vance. The conditions under which the
original oscillator clock stops depends on the standby mode selection.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
■ Drive Waveform of the LCD
If the LCD is driven with the DC, the LCD element, by its nature, undergoes a chemical
change causing a deterioration of the element. Therefore, the LCD controller/driver has a builtin AC circuit to drive the LCD with a two-frame AC waveform. There are three types of output
waveform:
• 1/2 bias, 1/2 duty output waveform
• 1/3 bias, 1/3 duty output waveform
• 1/3 bias, 1/4 duty output waveform
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
19.6.1
MB90930 Series
Output Waveform during the LCD Controller/Driver
Operation (1/2 Duty)
The display drive output is a 2-frame AC waveform of the multiplex drive
method.
Only COM0 and COM1 are used for display while 1/2 duty. COM2 and COM3 are
not used.
■ 1/2 Bias, 1/2 Duty Output Waveform
The LCD element is turned ON for which the potential difference between the common output
and segment output is greatest.
The output waveform when the contents of the display RAM is as shown in Table 19.6-1 is
shown in Figure 19.6-2.
Table 19.6-1 Example of the Display RAM Contents
Display RAM contents
Segment
COM3
COM2
COM1
COM0
SEGn
-
-
0
0
SEG (n+1)
-
-
0
1
-: Not used
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
Figure 19.6-2 Example of 1/2 Bias, 1/2 Duty Output Waveform
COM0
V3
V2 = V1
V0 = VSS
COM1
V3
V2 = V1
V0 = VSS
COM2
V3
V2 = V1
V0 = VSS
COM3
V3
V2 = V1
V0 = VSS
SEGn
V3
V2 = V1
V0 = VSS
SEG (n + 1)
V3
V2 = V1
V0 = VSS
V3 (ON)
V2
VSS
-V2
-V3 (ON)
V3 (ON)
V2
VSS
-V2
-V3 (ON)
V3 (ON)
V2
VSS
-V2
-V3 (ON)
V3 (ON)
V2
VSS
-V2
-V3 (ON)
1 frame
1 interval
V0 to V3: Voltages of V0 to V3 pins
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
■ Example of LCD Panel Connection and Display Data (1/2 Duty Drive Method)
Figure 19.6-3 Example of LCD Panel Display Data
*6
*0
SEGn
SEG(n + 3)
COM1
*1
SEG(n + 1)
*5
*2
*3
*4
SEG(n + 2)
COM0
COM2
COM1
COM0
bit3
bit2
bit1* 1
bit0* 0 SEGn
bit7
bit6
bit5*
bit4*
bit3
bit2
bit1* 5
bit0* 4 SEG(n + 2)
bit7
bit6
bit5* 7
bit4* 6 SEG(n + 3)
Address COM3
mH
(m + 1)H
e.g.) Whendisplaying 5
*7
3
Address COM3
1
1
SEGn
1
0
SEG1
1
0
SEG2
0
1
SEG3
3960H
3961H
0: OFF
1: ON
0
1
0
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
SEG11
1
0
SEG10
1
0
1
1
SEG09
SEG08
0
1
1
1
SEG07
SEG06
0
0
0
0
SEG05
SEG04
1
1
1
SEG03
1
1
1
SEG02
SEG01
1
[LCD panel]
SEG00
0
COM1
3965H
1
0
3964H
1
0
3963H
1
0
3962H
1
3961H
1
3960H
0
COM0
1
COM2
Example data ocrresponding to number 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
COM3
[Address]
COM0
1
[Segment No.]
[Display RAM]
COM1
SEG(n + 1)
2
*0 to *7: Indicates the correspondence with the display RAM.
Bit2, bit3, bit6, and bit7 ar
e not used.
578
COM2
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
19.6.2
Output Waveform during the LCD Controller/Driver
Operation (1/3 Duty)
COM0, COM1, and COM2 are used for display while 1/3 duty. COM3 is not used.
■ 1/3 Bias, 1/3 Duty Output Waveform
The LCD element is turned ON for which the potential difference between the common output
and segment output is greatest.
The output waveform corresponding to the display RAM contents shown in Table 19.6-2 is
illustrated in Figure 19.6-4.
Table 19.6-2 Example of the Display RAM Contents
Display RAM contents
Segment
COM3
COM2
COM1
COM0
SEGn
-
1
0
0
SEG (n+1)
-
1
0
1
-: Not used
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
Figure 19.6-4 Example of 1/3 Bias, 1/3 Duty Output Waveform
V3
V2
V1
V0 = VSS
V3
V2
V1
V0 = VSS
V3
V2
V1
V0 = VSS
COM0
COM1
COM2
V3
V2
V1
V0 = V SS
V3
V2
V1
V0 = VSS
COM3
SEGn
V3
V2
V1
V0 = VSS
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
SEG (n + 1)
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
V3 (ON)
V2
V1
V0 = VSS
-V1
-V2
-V3 (ON)
1 frame
V0 to V3: Voltages of V0 to V3 pins
580
1 interval
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
■ Example of LCD Panel Connection and Display Data (1/3 Duty Drive Method)
Figure 19.6-5 Example of LCD Panel Display Data
e.g.) When displaying 5
*3
*0
*6
COM0
*4
SEGn
COM1
*8
Address COM3
3960H
COM2
COM1
COM0
bit3
bit2* 2
bit1* 1
bit0* 0
SEGn
bit7
bit6* 5
bit5* 4
bit4* 3
SEG(n + 1)
bit3
bit2* 8
bit1* 7
bit0* 6
SEG(n + 2)
Address COM3
(m + 1)H
*5
SEG(n + 2)
SEG(n + 1)
COM2
mH
*7
*1
3961H
3964H
0
1
SEG08
1
3963H
1
1
SEG07
1
1
0
SEG06
0
3962H
1
1
SEG05
1
0
0
SEG04
0
3961H
0
0
SEG03
0
1
1
SEG02
1
3960H
0
1
SEG01
1
1
0
SEG00
1
COM1
COM2
[Segment No.]
[LCD panel]
COM0
0
0
1
SEGn
1
1
1
SEG1
0
1
0
SEG2
0
0
1
SEG3
1
1
1
SEG4
0
1
0
SEG5
When
starting
with bit0
When
starting
with bit4
0: OFF
1: ON
Example data ocrresponding to number 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
COM3
[Display RAM]
COM0
[Address]
*0 to *8: Indicates the correspondence with the display RAM.
Bit3, bit7, and *2 ar
e not used.
3962H
COM2 COM1
1
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
0
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
: Data when star
ting with bit4
: Data when star
ting with bit0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
As the 1/3 duty uses 3 b
ytes to display 2 digits,
2 types of data arra
y are provided: starting with
the first byte of bit0 and starting with the second
byte of bit4.
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
19.6.3
MB90930 Series
Output Waveform during the LCD Controller/Driver
Operation (1/4 Duty)
COM0, COM1, COM2, and COM3 are all used for display while 1/4 duty.
■ 1/3 Bias, 1/4 Duty Output Waveform
The LCD element is turned ON for which the potential difference between the common output
and segment output is greatest.
The output waveform corresponding to the display RAM contents shown in Table 19.6-3 is
illustrated in Figure 19.6-6.
Table 19.6-3 Example of the Display RAM Contents
Display RAM contents
Segment
582
COM3
COM2
COM1
COM0
SEGn
0
1
0
0
SEG (n+1)
0
1
0
1
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
Figure 19.6-6 Example of 1/3 Bias, 1/4 Duty Output Waveform
COM0
V3
V2
V1
V 0 = V SS
COM1
V3
V2
V1
V 0 = V SS
COM2
V3
V2
V1
V 0 = V SS
COM3
V3
V2
V1
V 0 = V SS
SEGn
V3
V2
V1
V 0 = V SS
V3
V2
V1
V 0 = V SS
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
SEG (n + 1)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
V 3 (ON)
V2
V1
V SS
-V 1
-V 2
-V 3 (ON)
1 frame
1 interval
V0 to V3: Voltages of V0 to V3 pins
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CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 Operation of LCD Controller/Driver
MB90930 Series
■ Example of LCD Panel Connection and Display Data (1/4 Duty Drive Method)
Figure 19.6-7 Example of LCD Panel Display Data
e.g.) When displaying 5
*4
*0
COM3
COM0
*7
SEGn
*5
COM1
*1
*3
*2
*6
SEG(n + 1)
COM2
Address COM3
mH
bit3*
3
bit7* 7
COM2
COM1
COM0
bit2*
bit1*
bit0*
2
bit6* 6
1
bit5* 5
Address COM3
3960H
1
SEGn
0
bit4* 4
0
1
SEGn
0
1
1
SEG1
0: OFF
1: ON
3963H
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
SEG07
0
0
1
1
SEG06
3962H
1
1
1
1
SEG05
0
1
1
0
SEG04
3961H
0
0
1
1
SEG03
0
0
0
1
SEG02
SEG01
1
1
0
1
3960H
1
1
1
SEG00
COM0
COM1
COM2
1
[Address]
COM0
1
Example data ocrresponding to number 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
COM3
[Segment No.]
[Display RAM]
[LCD panel]
584
0
SEG(n + 1)
*0 to *7: Indicates the correspondence with the display RAM.
COM2 COM1
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 20
LOW-VOLTAGE/CPU
OPERATION DETECTION
RESET CIRCUIT
This chapter describes the functions and
operations of the low-voltage/CPU operation
detection reset circuit.
20.1 Overview of the Low-voltage/CPU Operation Detection
Reset
20.2 Configuration of the Low-Voltage/CPU Operation
Detection
20.3 Register of the Low-voltage/CPU Operation Detection
Reset Circuit
20.4 Operation of the Low-voltage/CPU Operation Detection
Reset Circuit
20.5 Notes on Using the Low-voltage/CPU Operation
Detection Reset Circuit
20.6 Sample Program for the Low-voltage/CPU Operation
Detection Reset Circuit
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.1 Overview of the Low-voltage/CPU Operation Detection
Reset
20.1
MB90930 Series
Overview of the Low-voltage/CPU Operation
Detection Reset
The low-voltage detection reset circuit has the function to monitor the supply
voltage and detect the voltage drop. If it detects a low voltage, an internal reset
is generated.
On the other hand, the CPU operation detection reset circuit is a 20-bit counter
that uses the original oscillator as a count clock. If it is not cleared within a
specified time after it has started, an internal reset is generated.
■ Low-voltage Detection Reset Circuit
Table 20.1-1 shows the detection voltage of the low-voltage/CPU operation detection reset
circuit.
Table 20.1-1 Detection Voltage of the Low-voltage/CPU Operation Detection Reset Circuit
Detection voltage
Flash products
4.0V ± 0.3V
If a low-voltage is detected, the low-voltage detection flag (LVRC: LVRF) is set to "1", and an
internal reset is output.
As the operation continues even in STOP mode, a low-voltage detection causes to generate an
internal reset and to clear the STOP mode.
In an internal RAM write operation, a low-voltage reset is generated only after the write
operation has been completed.
*: For evaluation product, the internal reset is not generated even when a low-voltage is
detected.
In this case, low-voltage detection flag bit (LVRF) in the low-voltage/CPU operation
detection reset control register (LVRC) is set, however, reset source bit in the watchdog
timer control register (WDTC) is not set.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.1 Overview of the Low-voltage/CPU Operation Detection
Reset
MB90930 Series
■ CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit is a counter to prevent the program from running out
of control. This circuit starts automatically after the power is turned on. Once started, the
counter of the circuit must be cleared regularly within a specified time. If the program fails to
clear the counter within the specified time due to a problem, such as an infinite loop, an
internal reset is performed. The CPU operation detection circuit generates an internal reset with
a length of 5 machine cycles.
Table 20.1-2 Interval Time of the CPU Operation Detection Reset Circuit
Interval time
220/Fc (about 262 ms)
Note: The interval time is indicated in the parentheses when the oscillator clock operates at 4
MHz.
In any mode in which the CPU stops, this circuit also stops.
The counter clearing conditions of this circuit are listed below:
• Writing "0" the CL bit in the LVRC register
• Internal reset
• Stop of oscillator clock
• Transition to sleep mode
• Transition to time-base timer mode
• Power-on reset
Note:
For evaluation product, the internal reset is not generated unless the counter of the CPU
operation detection reset circuit is cleared for a given length of time.
In this ca se, th e CPU op eration detection flag bit (C PUF) in the low -voltage/CPU
operation detection reset control register (LVRC) is set, however, reset source bit in t he
watchdog timer control register (WDTC) is not set.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.2 Configuration of the Low-Voltage/CPU Operation Detection
20.2
MB90930 Series
Configuration of the Low-Voltage/CPU Operation
Detection
The low-voltage/CPU operation detection reset circuit consists of 3 blocks:
• CPU operation detection circuit
• Voltage compare circuit
• Low-voltage/CPU operation detection reset control register (LVRC)
■ Block Diagram of the Low-voltage/CPU Operation Detection Reset Circuit
Figure 20.2-1 shows the block diagram of the low-voltage/CPU operation detection reset
circuit.
Figure 20.2-1 Block Diagram of the Low-voltage/CPU Operation Detection Reset Circuit
Voltage compare
circuit
+
Constant
voltage source
VSS
CPU operation detection circuit
Oscillator
clock
VCC
F/F
Counter
Internal
reset
Overflow
Noise canceller
Clear
ReReserved served
ReReserved served
CL
LVRF
Reserved
CPUF
Low-voltage/CPU operation detection reset
control register (LVRC)
Internal data bus
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.2 Configuration of the Low-Voltage/CPU Operation Detection
MB90930 Series
● CPU operation detection circuit
A counter used to prevent the program from running out of control. Once started, the counter of
the circuit must be cleared regularly within a specified time.
● Voltage compare circuit
Compares the detection voltage with the power supply voltage, and if it detects a low-voltage,
outputs the "H" level.
After power-up, it operates continuously.
● Low-voltage/CPU operation detection reset control register (LVRC)
Contains flags for low-voltage/CPU operation detection reset and is used to clear the counter
for the CPU operation detection function.
● Reset sources for the low-voltage/CPU operation detection reset circuit
If the power supply voltage falls below the detection voltage, an internal reset occurs.
If the counter of the CPU operation detection circuit is not cleared within a specified time, an
internal reset occurs.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.3 Register of the Low-voltage/CPU Operation Detection
Reset Circuit
20.3
MB90930 Series
Register of the Low-voltage/CPU Operation
Detection Reset Circuit
The low-voltage/CPU operation detection reset control register (LVRC) clears
the counters of the low-voltage/CPU operation detection reset flag and the CPU
operation detection circuit. This register accepts only byte access. Do not
access the register in words (whether to read from or write to it).
■ Bit Configuration of the Low-voltage/CPU Operation Detection Reset Control
Register (LVRC)
Figure 20.3-1 shows the bit configuration of the low-voltage/CPU operation detection reset
control register (LVRC).
Figure 20.3-1 Bit Configuration of the Low-voltage/CPU Operation Detection Reset
Control Register (LVRC)
Address
00006EH
bit7
bit6
ReReserved served
bit5
bit4
bit3
ReReserved served
W
CPUF
0
1
LVRF
Initial value
CPUF
00111000B
R/W R/W
R/W
CPU operation detection flag bit
Write
Read
Clears this bit
No overflow
Does not change, and has no effect
Overflow
Low-voltage detection flag bit
Write
Read
Clears this bit
No low-voltage detected
Low-voltage detected
Does not change, and has no effect
CPU operation detection flag bit
CL
0
1
bit0
Reserved
CL LVRF
R/W R/W R/W R/W
0
1
bit1
bit2
Clears the counter
Does not change, and has no effect
Reserved
Reserved bit
Always set this bit to "1"
Reserved
Reserved bit
Always set this bit to "0"
R/W: Readable/Writable
W:
Write only
:
Initial value
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.3 Register of the Low-voltage/CPU Operation Detection
Reset Circuit
MB90930 Series
Table 20.3-1 Functions of Each Bit in the Low-voltage/CPU Operation Detection Reset Control
Register
Bit name
Function
bit7, Reserved:
bit6 Reserved bits
Be sure to write "0" to this bit.
bit5, Reserved:
bit4 Reserved bits
Be sure to write "1" to this bit.
CL:
bit3 CPU operation
detection clear bit
Used to clear the counter of the CPU operation detection circuit.
Writing "0" to this bit allows the counter of the CPU operation detection circuit to be cleared.
LVRF:
bit2 Low-voltage
detection flag bit
If a voltage drop is detected, this bit is set to "1".
This bit is cleared by writing "0". Writing "1" has no effect on this bit, and the bit remains
unchanged.
This bit isn't initialized by the internal reset but it is initialized by the external reset input.
bit1
Reserved:
Reserved bit
CPUF:
bit0 CPU operation
detection flag bit
CM44-10150-1E
Be sure to write "0" to this bit.
If CPU operation detection function's counter causes an overflow, this bit is set to "1".
This bit is cleared by writing "0". Writing "1" has no effect on this bit, and the bit remains
unchanged.
This bit is not initialized by the internal reset but it is initialized by the external reset input.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.4 Operation of the Low-voltage/CPU Operation Detection
Reset Circuit
20.4
MB90930 Series
Operation of the Low-voltage/CPU Operation
Detection Reset Circuit
This circuit is used to monitor the power supply voltage. If the power supply
voltage is lower than the setting value, this circuit generates an internal reset.
The CPU operation detection function generates an internal reset if the counter
is not cleared within a certain period. If an internal reset occurs by detecting a
low-voltage or CPU runaway, the register content cannot be assured. When a
low-voltage reset is cleared and the operation stabilization wait time has
elapsed, a reset sequence is executed and then the program will restart from
the address specified by the reset vector.
■ Operation of the Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit starts the low-voltage detection operation after a reset is
cleared without requiring the operation stabilization wait time.
■ Operation of the CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit starts the CPU operation detection after a reset is
cleared without requiring the operation stabilization wait time.
Note:
As the low-voltage reset circuit is always operating, current is co nsumed even in sleep a nd
stop mode.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.5 Notes on Using the Low-voltage/CPU Operation Detection
Reset Circuit
MB90930 Series
20.5
Notes on Using the Low-voltage/CPU Operation
Detection Reset Circuit
This section provides notes on using the low-voltage/CPU operation detection
reset circuit.
■ Notes on Using the Low-voltage Detection Reset Circuit
● Operation stop disabled in the program
The low-voltage detection reset circuit continuously operates when the operation stabilization
wait time has elapsed after power-up. Software does not allow the operation to stop.
● Operation in STOP mode
The low-voltage detection reset function operates even in STOP mode. If a low-voltage
condition is detected in STOP mode, a reset occurs and the STOP mode is released.
● Operation of evaluation product
For the evaluation device, the internal reset is not generated even when a low-voltage is
detected.
In this case, low-voltage detection flag bit (LVRF) in the low-voltage/CPU operation detection
reset control resister (LVRC) is set, however, reset source bit in the watchdog timer control
resister (WDTC) is not set.
■ Notes on Using the CPU Operation Detection Reset Circuit
● Operation stop disabled in the program
The CPU operation detection reset circuit continuously operates after the power-up. Software
does not allow the operation to stop.
● Resets by CPU operation detection function suppressed
The CPU operation detection function must clear the counter in constant intervals. Writing "0"
to the CL bit in the LVRC register clears the counter, and suppresses a reset generation.
● Stopping and clearing the counter
In the modes where the CPU stops, the CPU operation detection function will clear the counter,
causing a stop of operation.
● Operation of evaluation product
For the evaluation product, the internal reset is not generated even when the counter of the
CPU operation detection reset circuit is not cleared for a specified time.
In this case, the CPU operation detection flag bit (CPUF) in the low-voltage/CPU operation
detection reset control register (LVRC) is set, however, reset source bit in the watchdog timer
control register (WDTC) is not set.
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CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.6 Sample Program for the Low-voltage/CPU Operation
Detection Reset Circuit
20.6
MB90930 Series
Sample Program for the Low-voltage/CPU Operation
Detection Reset Circuit
This section provides a sample program for the low-voltage/CPU operation
detection reset circuit.
■ Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit
● Specification of processing
Clear the counter of the CPU operation detection function.
[Coding example]
LVRC
; Address of the low-voltage/CPU
; operation
; detection reset control register
;----------Main program---------------------------------------------CSEG
; [CODE SEGMENT]
:
MOV
LVRC, #00110101B ; Clears the counter of the CPU
; operation
; detection function
:
END
594
EQU
006EH
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 21
STEPPING MOTOR
CONTROLLER
This chapter explains the function and
operation of a stepping motor controller.
21.1 Overview of Stepping Motor Controller
21.2 Registers for Stepping Motor Controller
21.3 Operation of Stepping Motor Controller
21.4 Cautions when Using Stepping Motor
Controller
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.1 Overview of Stepping Motor Controller
MB90930 Series
Overview of Stepping Motor Controller
21.1
The stepping motor controller consists of these; Two PWM pulse generators,
four motor drivers and selector logic.
The four motor drivers have a high-output driving capability, and two motor
coils can be connected directly to four pins. The motor rotation is designed to
be controlled by a combination of the PWM pulse generators and selector logic
circuits. The synchronization mechanism enables synchronous operation of
two PWM pulse generators to operate surely.
■ Block Diagram of Stepping Motor Controller
Figure 21.1-1 Block Diagram of Stepping Motor Controller
Machine clock
OE1
Prescaler
CK
PWM1Pn
PWM1 pulse generator
EN
P1
Output
enable
Selector
PWM
PWM1Mn
P0
PWM1 selection
register
PWM1 compare register
OE2
CK
SC
CE
PWM2Pn
PWM2 pulse generator
EN
Output
enable
Selector
PWM2Mn
PWM
road
PWM2 compare register
596
BS
PWM2 selection
register
FUJITSU MICROELECTRONICS LIMITED
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CM44-10150-1E
CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
MB90930 Series
21.2
Registers for Stepping Motor Controller
There are five types of registers for the stepping motor controller:
• PWM Control register
• PWM1 Compare register
• PWM2 Compare register
• PWM1 Selection register
• PWM2 Selection register
■ Registers for Stepping Motor Controller
PWM Control register (PWC0,PWC1,PWC2,PWC3)
Address
0080H,0082H,
7
6
5
4
3
2
1
0
0084H,0086H
OE2
OE1
P1
P0
CE
SC
RESV
RESV
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PWM1 Compare register (PWC10,PWC11,PWC12,PWC13)
Address
3980H,3988H,
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
3990H,3998H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Address
3981H,3989H,
15
-
14
-
13
-
12
-
11
-
10
-
9
D9
8
D8
3991H,3999H
-
-
-
-
-
-
R/W
R/W
-
-
-
-
-
-
X
X
PWM2 Compare register (PWC20,PWC21,PWC22,PWC23)
Address
3982H,398AH,
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
3992H,399AH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Address
3983H,398BH,
15
-
14
-
13
-
12
-
11
-
10
-
9
D9
8
D8
3993H,399BH
-
-
-
-
-
-
R/W
R/W
-
-
-
-
-
-
X
X
PWM1 Selection register (PWS10,PWS11,PWS12,PWS13)
Address
3984H,398CH,
7
-
6
-
5
P2
4
P1
3
P0
2
M2
1
M1
0
M0
3994H,399CH
-
-
R/W
R/W
R/W
R/W
R/W
R/W
-
-
0
0
0
0
0
0
PWM2 Selection register (PWS20,PWS21,PWS22,PWS23)
Address
3985H,398DH,
15
RESV
14
BS
13
P2
12
P1
11
P0
10
M2
9
M1
8
M0
3995H,399DH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
21.2.1
MB90930 Series
PWM Control Register
The PWM control register starts/stops the stepping motor controller, and
performs interrupt control, and performs setting of external output pins, etc.,
for the stepping motor controller.
■ PWM Control Register
PWM Control register (PWC0, PWC1, PWC2, PWC3)
0080H,0082H
0084H,0086H
7
6
OE2 OE1
R/W
R/W
0
0
5
P1
R/W
0
4
3
P0
CE
R/W R/W
0
0
2
1
SC
RESV
R/W R/W
0
0
0
RESV
R/W
0
[bit7] 0E2: Output enable bit
If the OE2 bit is set to "1", external pins are used for PWM2P0, PWM2P1, PWM2P2,
PWM2P3, and PWM2M0, PWM2M1, PWM2M2, PWM2M3. If the bit is "0", these pins
can be used as general-purpose I/O ports.
Note:
In both cases, the ADER7/8 register bit corresponding must be set to "0".
[bit6] 0E1: Output enable bit
If the OE1 bit is set to "1", external pins are used for PWM1P0, PWM1P1, PWM1P2,
PWM1P3 and PWM1M0, PWM1M1, PWM1M2, PWM1M3. If the bit is "0", these pins
can be used as general-purpose I/O ports.
Note:
In both cases, the ADER7/8 register bit corresponding must be set to "0".
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
MB90930 Series
[bit5, bit4] P1, P0: Operating clock select bits (bits to select operating clock)
The P1 and P0 bits specify the clock input signal for the PWM pulse generator.
PI
P0
Clock input
PWM cycle (at Fcp = 32 MHz)
PWM cycle (at Fcp = 16 MHz)
SC=0
SC=1
SC=0
SC=1
0
0
FCP
8.0μs
32.0μs
16.0μs
64.0μs
0
1
1/2*FCP
16.0μs
64.0μs
32.0μs
128.0μs
1
0
1/4*FCP
32.0μs
128.0μs
64.0μs
256.0μs
1
1
1/8*FCP
64.0μs
256.0μs
128.0μs
512.0μs
FCP: Machine clock
Note:
After operation clock selection, set "1" in CE.
[bit3] CE: Count enable bit
The CE bit enables operation of the PWM pulse generator. When "1" is set to the CE bit,
the PWM pulse generator starts its operating. The PWM2 pulse generator starts after one
machine clock from PWM1 pulse generator starts in order to reduce the switching noise
generated by the output driver.
When the CE bit is cleared to "0" during operation of the PWM pulse generator, the
generator is initialized to stop operating.
[bit2] SC: 8/10 bits switching bit
When "1" is set to the SC bit, the PWM pulse generator operates at 10 bit. When "0" is set
to the SC bit, the PWM pulse generator operates at 8 bit.
[bit1, bit 0] Reserved bits
Always set the reserved bits to "0".
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
21.2.2
MB90930 Series
PWM1&2 Compare Registers
The value of the two 8(10) bits compare register of PWM1&2 determine the
width of the PWM pulse. The stored "00H (000H)" value indicates that the PWM
duty is 0%, and the stored "FFH" ("3FFH") value indicates that the PWM duty is
99.6% (99.9%).
■ PWM1&2 Compare Registers
The PWM1&2 compare registers can be accessed at any time, but the changed value is
reflected in the pulse width at the end of the current PWM cycle after "1" is set to the BS bit of
the PWM2 selection register.
When "0" is set to SC bit of the PWM control register, and PWM performs 8 bit operation, the
D9 and D8 bits are undefined value.
Be sure to perform word-access to the PWM1&2 compare registers
PWM1 Compare register (PWC10, PWC11, PWC12, PWC13)
7
6
54
3980H, 3988H
D7
D6
D5 D4
3990H, 3998H
R/W
R/W
R/W R/W
X
X
XX
3981H, 3989H
3991H, 3999H
15
- -
14
-
13 12
-
-
- -
32
D3 D2
R/W R/W
XX
11 10
- -
10
D1 D0
R/W R/W
XX
-
9
D9
R/W
XX
8
D8
R/W
PWM2 Compare register (PWC20, PWC21, PWC22, PWC23)
3982H, 398AH
3992H, 399AH
3983H, 398BH
3993H, 399BH
7
D7
R/W
X
6
D6
R/W
X
54
D5 D4
R/W R/W
XX
15
14
-
13 12
-
- -
32
D3 D2
R/W R/W
XX
-
- -
11 10
- -
10
D1 D0
R/W R/W
XX
-
9
D9
R/W
XX
8
D8
R/W
[bit9 to bit0] D9 to D0: Compare data
These bits are used to set the PWM pulse width.
[bit15 to bit10] Undefined bits
• When these bits are read, "1" is read.
• Writing to these bits does not affect operation.
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
MB90930 Series
Figure 21.2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width
Register value
One PWM cycle
256 (1024) input cycles
000H
80H (200H)
FFH (3FFH)
CM44-10150-1E
128 (512) input cycle
255 (1023) input cycle
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21.2 Registers for Stepping Motor Controller
21.2.3
MB90930 Series
PWM1&2 Selection Registers
The PWM1&2 selection registers determine whether to set the output of the
external pin of the stepping motor controller to "0", "1", PWM pulse, or high
impedance.
■ PWM1&2 Selection Registers
PWM1 Selection register (PWS10, PWS11, PWS12, PWS13)
7
6
54
3984H, 398CH
P2
P1
3994H, 399CH
R/W R/W
0 0
32
P0
M2
R/W R/W
0 0
10
M1
M0
R/W R/W
0 0
PWM2 Selection register (PWS20, PWS21, PWS22, PWS23)
15
14
13 12
3985H, 398DH
BS P2
P1
RESV
3995H, 399DH
R/W
R/W
R/W R/W
0
0
00
11 10
P0
M2
R/W R/W
00
9
8
M1
M0
R/W R/W
00
[bit15] Reserved bit
Always set the reserved bit to "0".
[bit14] BS: Rewrite bit
The BS bit makes the setting for the PWM output match another setting. Until the BS bit is
set, changes made to the two compare registers and two selection registers are not reflected
in the output signal.
When "1" is set to the BS bit, the PWM pulse generator and the selector load the values of
the registers at the end of the current PWM cycle. The BS bit is cleared to "0"
automatically at the beginning of the next PWM cycle.
When "1" is set to the BS bit with automatically clear by software simultaneously, the BS
bit is set the BS bit is set to "1" (no change is made to the BS bit) and automatic clearing is
cancelled.
When "0" is set to the BS bit with automatically clear by software simultaneously, the BS
bit is clear to "0", however the PWM pulse generator and the selector not load the values of
the registers at the end of the current PWM cycle.
Note:
When BS=1, BS bit is "1" read and write "1" into again BS bit, if execute in read-modifywrite type instruction of except BS bit.
When a BS bit was automatically cleared by opening of PWM cycle in between read and
write, "1" is set after BS bit clear again.
Therefore, values of the registers are loaded in PWM pulse generator and selector when a
BS bit is not set in "1" by an end of the next PWM cycle.
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2 Registers for Stepping Motor Controller
MB90930 Series
Figure 21.2-2 load timing of PWM compare register value
[Automatic clear of BS bit]
Load the values of the registers and
reflected in the output signal.
PWM 1 cycle
PWM pulse
PWM pulse generator
counter value
……
3FFH
PWM compare
register value
3FFH
PWM pulse generator
compare register value
XXXH
000H
……
Load
……
……
3FFH
200H
000H
……
200H
……
3FFH
000H
Load
3FFH
200H
BS
[When set a BS bit in "1" with automatic clear simultaneously]
Load the values of the registers and
reflected in the output signal.
PWM 1 cycle
PWM pulse
PWM pulse generator
counter value
……
3FFH
PWM compare
register value
3FFH
PWM pulse generator
compare register value
XXXH
000H
……
Load
……
……
3FFH
200H
000H
……
200H
……
3FFH
000H
Load
3FFH
200H
BS
Automatic clear and "1" simultaneously
write of a BS bit.
[When set a BS bit in "0" with automatic clear simultaneously]
Load the values of the registers
and reflected in the output signal.
PWM 1 cycle
PWM pulse
PWM pulse generator
counter value
……
3FFH
PWM compare
register value
3FFH
PWM pulse generator
compare register value
XXXH
000H
……
Load
……
……
3FFH
200H
000H
……
200H
……
3FFH
000H
Load
3FFH
200H
Automatic clear and "0" simultaneously
write of a BS bit.
BS
[When set a BS bit in "0" before the PWM cycle end]
Not load the values of the registers and
not reflected in the output signal.
PWM 1 cycle
PWM pulse
PWM pulse generator
counter value
……
3FFH
PWM compare
register value
3FFH
PWM pulse generator
compare register value
XXXH
BS
CM44-10150-1E
000H
……
Load
……
200H
……
3FFH
000H
……
……
……
3FFH
000H
Not load
3FFH
"0" write of a BS bit before the 1 cycle end.
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21.2 Registers for Stepping Motor Controller
MB90930 Series
[bit13 to bit11] P2 to P0: Output select bits
These bits are used to select the output signal for PWM2Px.
[bit10 to bit8] M2 to M0: Output select bits
These bits are used to select the output signal for PWM2Mx.
[bit5 to bit3] P2 to P0: Output select bits
These bits are used to select the output signal for PWM1Px.
[bit2 to bit0] M2 to M0: Output select bits
These bits are used to select the output signal for PWM1Mx.
The table below shows the relationship between the output levels and the select bits.
P2
P1
P0
PWMnPx
M2
M1
M0
PWMnMx
0
0
0
L
0
0
0
L
0
0
1
H
0
0
1
H
0
1
X
PWM Pulse
0
1
X
PWM Pulse
1
X
X
High impedance
1
X
X
High impedance
[bit7, bit6] Undefined bits
• When these bits are read, "1" is read.
• Writing to these bits does not affect operation.
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.3 Operation of Stepping Motor Controller
MB90930 Series
21.3
Operation of Stepping Motor Controller
The operation of the stepping motor controller is explained.
■ Setting Operation of Stepping Motor Controller
Figure 21.3-1 Setting of Stepping Motor Controller
PWM1 H width (compare value) is set.
PWM2 H width (compare value) is set.
Used bit
Not used bit
1 is set.
0 is set.
Channel No.
● Operation of PWM-pulse generator
When the counter is started (PWCn: CE = 1), the counter starts incrementing from 00H on the
selected count clock rising. The PWM output pulse wave remains "H" until the value of the
counter matches the value set to PWM compare register, and then changes to and remains "L"
until the value of the counter overflows (FFH --> 00H).
Figure 21.3-2 shows the PWM waveform generated by the PWM generator
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21.3 Operation of Stepping Motor Controller
MB90930 Series
Figure 21.3-2 Examples of PWM1&2 Waveform Output
When the value of compare register is "00H"/"000H"(duty ratio is 0%):
Value of counter:
PWM waveform:
When the value of compare register is "80H"/"200H"(duty ratio is 50%):
Value of counter:
PWM waveform:
When the value of compare register is "FFH"/"3FFH"(duty ratio is 99.6%/99.9%):
Value of counter:
PWM waveform:
One count
● Selection of motor drive signals
Motor drive signals that are output to each pin related to the stepping motor controller can be
selected among four types of signals for each pin by setting the PWM selection register.
Table 21.3-1 lists the selection of the motor drive signals and the settings of PWM selection
registers 1&2.
When these registers are set and "1" is written to the BS bit of the PWM selection register 2,
the setting of these registers is enabled at the end of the current PWM cycle. The BS bit is to
be cleared automatically to 0 at the beginning of the next PWM cycle. When "1" is written to
the BS bit, and the BS bit is cleared to 0 simultaneously at the beginning of the next PWM
cycle, "1" is written to the BS bit and clearing of the BS bit is cancelled.
Table 21.3-1 Selection of Motor Drive Signals and Setting of PWM Selection Registers 1&2
P2, P1, P0 Bits
PWM2P Output
PWM1P Output
M2, M1, M0 Bits
PWM1M Output
PWM2M Output
000B
L
000B
L
001B
H
001B
H
01XB
PWM Pulse
01XB
PWM Pulse
1XXB
High impedance
1XXB
High impedance
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CHAPTER 21 STEPPING MOTOR CONTROLLER
21.4 Cautions when Using Stepping Motor Controller
MB90930 Series
21.4
Cautions when Using Stepping Motor Controller
The cautions when using the stepping motor controller are described below.
■ Cautions when Changing PWM Setting
The PWM compare registers 1&2 (PWC1n, PWC2n) and the PWM selection registers 1&2
(PWS1n, PWS2n) can be accessed at any time. However, to change setting of the "H" width of
PWM or to change the PWM output, "1" must be written to the BS bit of the PWM2 selection
register after (or and at the same time) a setting is written to those registers (the PWM compare
register 1&2 and the PWM selection register 1&2).
When "1" is set to the BS bit, the new setting is enabled at the end of the current PWM cycle
and the BS bit is cleared automatically.
Also, when "1" is written to the BS bit and the BS bit is reset at the end of the PWM cycle
simultaneously, "1" is written to the BS and resetting of the BS bit is cancelled.
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21.4 Cautions when Using Stepping Motor Controller
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CM44-10150-1E
CHAPTER 22
SOUND GENERATOR
This chapter describes the functions and
operations of the sound generator.
22.1 Outline of the Sound Generator
22.2 Registers of the Sound Generator
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22.1 Outline of the Sound Generator
22.1
MB90930 Series
Outline of the Sound Generator
The sound generator contains the sound control register, frequency data
register, amplitude data register, decrement grade register, tone count register,
PWM pulse generator, frequency counter, decrement counter, and tone pulse
counter.
■ Block Diagram of the Sound Generator
Figure 22.1-1 shows a block diagram of the sound generator.
Figure 22.1-1 Block Diagram of the Sound Generator
Clock input
Prescaler
S1
S0
8-bit PWM
Pulse
generator
CO
EN
PWM
CI
Frequency
counter
Toggle
flip-flop
CO
EN
Reload
1/d
Reload
Frequency
data register
Amplitude
data register
DEC
DEC
Decrement
counter
DQ
EN
CI
CO
EN
SGA0/SGA1
OE1
Decrement
grade register
Tone p ulse
counter
Tone count
register
Mixed
TONE OE2
OE1
SGO0/SGO1
OE2
CI
CO
EN
INTE
INT
ST
IRQ #33
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
MB90930 Series
22.2
Registers of the Sound Generator
The sound generator has the following 5 types of registers.
• Sound control registers (SGCRH0/SGCRH1, SGCRL0/SGCRL1)
• Frequency data registers (SGFR0/SGFR1)
• Amplitude data registers (SGAR0/SGAR1)
• Decrement grade registers (SGDR0/SGDR1)
• Tone count registers (SGTR0/SGTR1)
■ Registers of the Sound Generator
Figure 22.2-1 illustrates the registers of the sound generator.
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22.2 Registers of the Sound Generator
MB90930 Series
Figure 22.2-1 Registers of the Sound Generator
Upper bits in the sound control register (GCRH0, SGCRH1)
Bit
Address: 00005BH
Address: 0000D9H
Initial value →
15
14
13
12
11
TST
-
-
-
-
(R/W)
(0)
-
-
-
-
10
9
ReBUSY
served
(R/W)
(R)
(1)
(0)
8
DEC
(R/W)
(0)
Lower bits in the sound control register (SGCRL0, SGCRL1)
Bit
Address: 00005AH
Address: 0000D8H
Initial value →
7
6
5
4
3
2
1
0
S1
S0
TONE
OE2
OE1
INTE
INT
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Amplitude Data Register (SGAR0, SGAR1)
Bit
Address: 00005DH
Address: 003975H
Initial value →
15
14
13
12
11
10
9
8
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Frequency Data Register (SGFR0, SGFR1)
Bit
Address: 00005CH
Address: 003974H
Initial value →
7
6
5
4
3
2
1
0
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Tone Count Register (SGTR0, SGTR1)
Bit
Address: 00005FH
Address: 003977H
Initial value →
15
14
13
12
11
10
9
8
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Decrement Grade Register (SGDR0, SGDR1)
Bit
Address: 00005EH
Address: 003976H
Initial value →
R/W :
X:
-:
612
7
6
5
4
3
2
1
0
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Readable/Writable
Undefined value
Undefined
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
MB90930 Series
22.2.1
Sound Control Register
(SGCRH0/SGCRH1, SGCRL0/SGCRL1)
The sound control register controls the operating status by controlling the
interrupt of the sound generator and setting its external output pins.
■ Bit Configuration of Sound Control Register (SGCRH0/SGCRH1, SGCRL0/
SGCRL1)
Figure 22.2-2 shows the bit configuration of the sound control register.
Figure 22.2-2 Bit Configuration of Sound Control Register
Upper bits in the sound control register (SGCRH0, SGCRH1)
Bit
Address: 00005BH
Address: 0000D9H
Initial value →
15
14
13
12
11
TST
-
-
-
-
(R/W)
(0)
-
-
-
-
10
9
Re
BUSY
served
(R/W)
(R)
(1)
(0)
8
DEC
(R/W)
(0)
Lower bits in the sound control register (SGCRL0, SGCRL1)
Bit
Address: 00005AH
Address: 0000D8H
Initial value →
R/W :
R:
-:
7
6
5
4
3
2
1
0
S1
S0
TONE
OE2
OE1
INTE
INT
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Readable/Writable
Read only
Undefined
[bit15] TST: Test bit
This bit is to test the device. User applications must clear the bit to "0".
[bit10] Reserved bit
Always write "1" to this bit.
Reading the bit returns "1".
[bit9] BUSY: Busy bit
This bit indicates whether the sound generator is operating. The bit is set to "1" as the ST bit
is set to "1". It is reset to "0" when the operation is completed at the end of one tone cycle
with the ST bit reset to "0". Any write instruction performed on this bit has no effect.
[bit8] DEC: Automatic decrement enable bit
The DEC bit is for automatic degradation of sound in combination with the decrement grade
register.
If this bit is set to "1", the value held in the amplitude data register is decremented by one
every time the decrement counter counts the number of tone pulses from the toggle flip-flop
specified by the decrement grade register.
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
MB90930 Series
[bit7, bit6] S1, S0: Operation clock select bits
This bit group specifies the clock input signal for the sound generator.
S1
S0
Clock input
0
0
Machine Clock
0
1
1/2 machine clock
1
0
1/4 machine clock
1
1
1/8 machine clock
[bit5] TONE: Tone output bit
After this bit is set to "1", the SGO signal will be a simple rectangular waveform (tone
pulses) from the toggle flip-flop. Otherwise, it will be a combination (AND logic) of the tone
and PWM pulses.
[bit4] OE2: Sound output enable bit
If this bit is set to "1", the external pin is assigned to be used for SGO output. In other cases,
it can be used as a general-purpose pin.
[bit3] OE1: Amplitude output enable bit
If this bit is set to "1", the external pin is assigned to be used for SGA output. In other cases,
it can be used as a general-purpose pin.
The SGA signal is a PWM pulse from the PWM pulse generator, indicating the sound
amplitude.
[bit2] INTE: Interrupt enable bit
This bit is used to enable interrupt signals of the sound generator. If the INT bit is set to "1"
with this bit "1", the sound generator outputs an interrupt with a signal.
[bit1] INT: Interrupt bit
This bit is set to "1" if the tone pulse count specified by the tone count register and
decrement grade register is counted by the tone pulse counter.
Writing "0" to this bit resets it to "0". Writing "1" has no effect, and read-modify-write
instructions always return "1".
[bit0] ST: Start bit
This bit is used to start sound generator operation. As long as this bit is "1", the sound
generator is operating.
If this bit is reset to "0", the sound generator stops the operation at the end of the current tone
cycle. The BUSY bit indicates whether the sound generator has completely stopped the
operation.
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
MB90930 Series
22.2.2
Frequency Data Register(SGFR0/SGFR1)
The frequency data register stores the reload value for the frequency counter.
The value stored indicates the frequency of sound (or tone signal from the
toggle flip-flop). The register value is reloaded into the counter by each toggle
signal transition.
■ Frequency Data Registers (SGFR0/SGFR1)
Figure 22.2-3 shows the bit configuration of the frequency data register; Figure 22.2-4 shows
the relationship between tone signals and register values.
Figure 22.2-3 Bit Configuration of Frequency Data Register
Frequency Data Register (SGFR0, SGFR1)
Bit
Address: 00005CH
Address: 003974H
Initial value →
R/W :
X:
7
6
5
4
3
2
1
0
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Readable/Writable
Undefined value
Figure 22.2-4 Relationship between Register Value and Tone Signal
One tone cycle
Tone signal
(Register value + 1) x
1 PMW cycle
(Register value + 1) x
1 PMW cycle
Note:
Changing t he re gister valu e d uring o peration may cau se a de viation o f a 50 % of dut y
cycle depending on the change timing.
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
22.2.3
MB90930 Series
Amplitude Data Register(SGAR0/SGAR1)
The amplitude data register stores the reload value for the PWM pulse
generator. The register value indicates the sound amplitude. It is reloaded to
the PWM pulse generator each time a tone cycle ends.
■ Amplitude Data Registers (SGAR0/SGAR1)
Figure 22.2-5 shows the bit configuration of the amplitude data register.
Figure 22.2-5 Bit Configuration of Amplitude Data Register
Amplitude Data Register (SGAR0, SGAR1)
Bit
Address: 00005DH
Address: 003975H
Initial value →
R/W :
15
14
13
12
11
10
9
8
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Readable/Writable
If the decrement counter reaches the reload value while the DEC bit is "1", the register value is
decremented by 1. If the register value reaches "00H", no more decrement is made to the
register value. However, the sound generator continues its operation until the ST bit is cleared.
Figure 22.2-6 shows the relationship between register values and PWM pulses.
Figure 22.2-6 Relationship between Register Value and PWM Pulse
Register value
One PMW cycle 256
input clock cycles
00H
One input clock cycle
80H
129 input clock cycles
FEH
256 input clock cycles
FFH
256 input clock cycles
When the register value is set to "FFH", the PWM signal is always set to "1".
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
MB90930 Series
22.2.4
Decrement Grade Register(SGDR0/SGDR1)
The decrement grade register stores the reload value for the decrement
counter. The register is to automatically decrement the value held in the
amplitude data register.
■ Decrement Grade Registers (SGDR0/SGDR1)
Figure 22.2-7 shows the bit configuration of the decrement grade register.
Figure 22.2-7 Bit Configuration of Decrement Grade Register
Decrement Grade Register (SGDR0, SGDR1)
Bit
Address: 00005EH
Address: 003976H
Initial value →
R/W :
X:
7
6
5
4
3
2
1
0
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Readable/Writable
Undefined value
If the decrement counter counts tone pulses up to the reload value with the DEC bit "1", the
amplitude data register is decremented by 1 at the end of the tone cycle.
This operation enables automatic sound degradation while reducing the number of CPU
interventions.
Note that the tone pulse count specified by the register is "register value +1". With the
decrement grade register set to "00H", the decrement operation is performed by every tone
cycle.
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CHAPTER 22 SOUND GENERATOR
22.2 Registers of the Sound Generator
22.2.5
MB90930 Series
Tone Count Register(SGTR0/SGTR1)
The tone count register stores the reload value for the tone pulse counter. The
tone pulse counter counts the number of tone pulses (or the number of
decrement operations), and sets the INT bit when it reaches to the reload value.
The register aims to decrease the interrupts.
■ Tone Count Registers (SGTR0/SGTR1)
Figure 22.2-8 shows the bit configuration of the tone count register.
Figure 22.2-8 Bit Configuration of Tone Count Register
Tone Count Register (SGTR0, SGTR1)
Bit
Address: 00005FH
Address: 003977H
Initial value →
R/W :
X:
15
14
13
12
11
10
9
8
D7
D7
D7
D7
D7
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Readable/Writable
Undefined value
The count input of the tone pulse counter is connected to the carry-out signal from the
decrement counter. If the tone count register is set to "00H", the tone pulse counter sets the INT
bit every time a carry-out occurs at the decrement counter. The tone pulse count stored is
therefore expressed as follows:
((decrement grade register) + 1) × ((tone count register) + 1)
In other words, if both registers are set to "00H", the INT bit is set by every tone cycle.
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CM44-10150-1E
CHAPTER 23
ROM MIRROR FUNCTION
SELECT MODULE
This chapter describes the ROM mirror function
select module.
23.1 Outline of the ROM Mirror Function Select Module
23.2 ROM Mirror Function Select Register (ROMM)
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CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE
23.1 Outline of the ROM Mirror Function Select Module
MB90930 Series
Outline of the ROM Mirror Function Select Module
23.1
The ROM mirror function select module can be used to select the viewing of
bank FF via bank 00 by setting its register.
■ Register of the ROM Mirror Function Select Module
Figure 23.1-1 shows the bit configuration of register of the ROM mirror function select
module.
Figure 23.1-1 Bit Configuration of Register of ROM Mirror Function Select Module
Bit
Address: 00006FH
Initial value →
W:
-:
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MI
(W)
(1)
ROMM
Write only
Undefined
■ Block Diagram of the ROM Mirror Function Select Module
Figure 23.1-2 is a block diagram of the ROM mirror function select module.
Figure 23.1-2 Block Diagram of ROM Mirror Select Function
Internal data bus
ROM mirror function select register
Address area
Bank FF
Bank 00
ROM
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CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE
23.2 ROM Mirror Function Select Register (ROMM)
MB90930 Series
23.2
ROM Mirror Function Select Register (ROMM)
Do not access the ROM mirror function select register (ROMM) with address
008000H to 00FFFFH being used.
This register accepts only byte access. Do not access the register in words
(whether to read from or write to it).
■ ROM Mirror Function Select Register (ROMM)
Figure 23.2-1 shows the bit configuration of the ROM mirror function select register (ROMM).
Figure 23.2-1 Bit Configuration of ROM Mirror Function Select Register (ROMM)
Bit
Address: 00006FH
Initial value →
W:
-:
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MI
(W)
(1)
ROMM
Write only
Undefined
[bit8] MI
Writing "1" to this bit allows ROM data in bank FF to be read from bank 00. Writing "0" to the
bit disables this function via bank 00.
This bit is a write-only bit.
Note:
When the ROM mirror function is e nabled, addresses "008000H to 0 0FFFFH" in bank 00
mirror addresses "FF8000H to FFFFFFH". ROM addresses of "FF7FFFH" and below are
not mirrored in bank 00 even if the ROM mirror function is enabled.
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CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE
23.2 ROM Mirror Function Select Register (ROMM)
MB90930 Series
■ Memory Space
Figure 23.2-2 shows memory space.
Figure 23.2-2 Memory Space
FFFFFFH
ROM area
ROM area
010000H
ROM mirror area
008000H
RAM area
(evaluation product only)
Peripheral area
000000H
RAM area
RAM area
I/O area
I/O area
ROM mirror function in use
622
RAM area
(evaluation product only)
Peripheral area
ROM mirror function not in use
FUJITSU MICROELECTRONICS LIMITED
Internal area
Access barred area
CM44-10150-1E
CHAPTER 24
1M-BIT FLASH MEMORY
This chapter describes the functions and
operations of the 1M-bit flash memory.
The following methods are available for writing/
erasing data to/from the flash memory:
• Executing programs to write/erase data
• Writing via the serial programmer
• Writing via the flash memory programmer
This chapter explains "Executing programs to
write/erase data".
24.1 Overview of 1M-bit Flash Memory
24.2 Sector Configuration of 1M-bit Flash Memory
24.3 Flash Memory Control Status Register (FMCS)
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
24.5 Starting the Flash Memory Automatic Algorithm
24.6 Confirming the Automatic Algorithm Execution State
24.7 Writing/Erasing Flash Memory
24.8 Flash Security Function
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CHAPTER 24 1M-BIT FLASH MEMORY
24.1 Overview of 1M-bit Flash Memory
24.1
MB90930 Series
Overview of 1M-bit Flash Memory
The 1M-bit flash memory is mapped into the FE to FF banks on the CPU
memory map. The flash memory interface circuit allows the CPU to readaccess and program-access the flash memory in the same way as for masked
ROM. Instructions from the CPU allows to write/erase data in the flash memory
via the flash memory interface circuit. Internal CPU control therefore enables
rewriting of the flash memory while it is mounted. As a result, the programming
and data can be improved efficiently.
The selector operation, such as "enable sector protection", cannot be used.
■ Features of 1M-Bit Flash Memory
The 1M-bit flash memory has the following features:
• 1M: Sector configuration of 128K words × 8 /64K words × 16 bits
• Automatic programming algorithm (similar to the Embedded Algorithm: MBM29F400TA)
• Suspend/restart to erase function provided
• Detect writing/erasing completion with the data polling and toggle bit
• Detect writing/erasing completion with the CPU interrupts
• Compatible with JEDEC standard commands
• Able to erase on a sector basis (any combination of sectors)
• Minimum of 10,000 write/erase operations
■ How to Write/Erase Flash Memory
You cannot write or read the flash memory at the same time. If you perform a data writing/
erasing operation on the flash memory, copy the program on the flash memory to RAM and
then perform the operation on the RAM. This makes it possible to perform a write operation
without reading the flash memory.
■ Flash Memory Control Status Register (FMCS)
The figure below shows the bit configuration of the flash memory control status resister
(FMCS) used for flash memory.
Address: 0000AEH
Initial value →
bit7
bit6
bit5
INTE RDYINT WE
R/W
R/W
R/W
0
0
0
bit4
RDY
W
X
bit3
bit2
bit1
bit0
Reserved Reserved Reserved Reserved
R
0
R/W
0
W
0
R/W
0
R/W:Readable/Writable
W: Write only
R: Read only
X: Undefined value
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CHAPTER 24 1M-BIT FLASH MEMORY
24.2 Sector Configuration of 1M-bit Flash Memory
MB90930 Series
24.2
Sector Configuration of 1M-bit Flash Memory
This section shows the sector configuration of the 1M-bit flash memory.
■ Sector Configuration
Figure 24.2-1 illustrates the sector configuration of the 1M-bit flash memory. The addresses in
the figure indicate the upper and lower addresses of each sector.
Figure 24.2-1 Sector Configuration of 1M-bit Flash Memory
1M-bit flash memory
Programmer
address
SA5 (8K Byte)
SA4 (8K Byte)
CPU
address
7FFFFH
FFFFFFH
7E000H
7DFFFH
FFE000H
FFDFFFH
7C000H
7BFFFH
FFC000H
FFBFFFH
70000H
6FFFFH
FF0000H
FEFFFFH
64000H
63FFFH
FE4000H
FE3FFFH
62000H
61FFFH
FE2000H
FE1FFFH
60000H
FE0000H
SA3 (48K Byte)
SA2 (48K Byte)
SA1 (8K Byte)
SA0 (8K Byte)
● Programmer address
The programmer address in the Figure 24.2-1 corresponds to the CPU address when writing
data to the flash memory with the parallel programmer. Use this programmer address for
writing/erasing with a general-purpose programmer.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.3 Flash Memory Control Status Register (FMCS)
24.3
MB90930 Series
Flash Memory Control Status Register (FMCS)
The flash memory control status resister (FMCS), located in the flash memory
interface circuit, is used for the writing/erasing operation on the flash memory.
■ Flash Memory Control Status Register (FMCS)
The figure below shows the bit configuration of the flash memory control status resister
(FMCS).
Address: 0000AEH
Initial value →
bit7
bit6
bit5
INTE RDYINT WE
R/W
R/W
R/W
0
0
0
bit4
RDY
R
X
bit3
bit2
bit1
bit0
Reserved Reserved Reserved Reserved
W
0
R/W
0
W
0
R/W
0
R/W:Readable/Writable
W: Write only
R: Read only
X: Undefined value
The following explains the function of each bit in the flash memory control status resister
(FMCS).
[bit7] INTE: INTerrupt Enable
This bit enables or disables an interrupt request generation upon completion of the flash
memory write/erase operation.
An interrupt to the CPU occurs when the INTE and RDYINT bits are both "1". The interrupt
will not occur if the INTE bit is "0".
0
Disable interrupt at write/erase completion
1
Enable interrupt at write/erase completion
[bit6] RDYINT: ReaDY INTerrupt
This bit shows the flash memory operation status.
Upon completion of the flash memory write/erase operation, it is set to "1". After writing/
erasing the flash memory, writing/erasing the flash memory is disabled upon the bit "0".
After writing/erasing is completed and the bit is set to "1", writing/erasing the flash memory
is enabled.
Writing "0" clears to set this bit to "0". When "1" is set, operation is ignored. Upon
completion of flash memory automatic algorithm (see Section "24.6 Confirming the
Automatic Algorithm Execution State"), the bit is set to "1". The bit returns to "1" when read
by the read-modify-write (RMW) instruction.
626
0
Write/erase operation executing
1
Write/erase operation completed (interrupt request is generated)
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CM44-10150-1E
CHAPTER 24 1M-BIT FLASH MEMORY
24.3 Flash Memory Control Status Register (FMCS)
MB90930 Series
[bit5] WE: Write Enable
This bit is a write enable bit to flash memory area.
When this bit is "1", the write after a command sequence (see Section "24.5 Starting the
Flash Memory Automatic Algorithm") issued to the FC to FF bank is to flash memory.
Write/erase signal is not generated with this bit "0". This bit activates a flash memory write/
erase command.
If no write-in and/or erasing of data is intended, always set this to "0" to prevent accidental
loss of flash memory data.
0
Flash memory write/erase disabled
1
Flash memory write/erase enabled
[bit4] RDY: ReadDY
This bit enables to write/erase to the flash memory.
Writing/erasing to flash memory is disabled upon the bit "0". Even in this state, a read/reset
command and a sector erase suspend command are acceptable.
0
Write/erase operation executing
1
Write/erase operation completed (next data write/erase enabled)
[bit3 to bit0] Reserved bits
These bits are reserved bits. Be sure to set these bits to "0" normally.
■ Automatic Algorithm Termination Timing
Figure 24.3-1 shows the relationships between the automatic algorithm termination timing and
RDYINT/RDY bits.
The RDYINT and RDY bits cannot be changed at the same time. Make a program so that
decisions to terminate the automatic algorithm are made using either of these bits.
Figure 24.3-1 Relationships between the Automatic Algorithm Termination Timing and RDYINT/RDY
Bits
Automatic algorithm
termination timing
RDYINT bit
RDY bit
1 Machine cycle
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CHAPTER 24 1M-BIT FLASH MEMORY
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
24.4
MB90930 Series
Flash Memory Write Control Registers (FWR0/
FWR1)
The flash memory write control registers (FWR0/FWR1) exist in the flash
memory interface to be used to set the flash memory write-protect feature.
■ Flash Memory Write Control Registers (FWR0/FWR1)
The flash memory write control registers (FWR0/FWR1) contain the bits to enable/disable the
programming of data into individual sectors (SA0 to SA5). The initial value of each bit is "0"
to disable programming. Writing "1" to one of the bits enables programming into the
corresponding sector. Writing "0" to the bit prevents an accidental write from being executed to
the sector. Once you have written "0" to the bit, therefore, you cannot write to the sector even
though you write "1" to the bit. You have to reset the bit before you write to the sector again.
Figure 24.4-1 1-Mbit Flash Memory Write Control Registers (FWR0/FWR1)
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CHAPTER 24 1M-BIT FLASH MEMORY
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
MB90930 Series
Table 24.4-1 Functions of Flash Memory Write Control Registers (FWR0/FWR1)
Bit name
bit15
Reserved bits
to bit6
Function
For programming, be sure to write "0" to these bits. The values read from the bits are indefinite.
These bits are used to set the accidental write preventive function for the individual sectors of
flash memory. Writing "1" to one of the bits permits programming into the corresponding sector.
Writing "0" to the bit write-protects that sector (prevents an accidental write to the sector). A
reset initializes the bit to "0" (programming prohibited).
Write-protection setup bits and corresponding flash sectors
(2-Mbit dual operation flash memory)
bit5
to
bit0
SA5E to SA0E:
Write-protection
setup bits
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SA5E
SA4E
SA3E
SA2E
SA1E
SA0E
Corresponding flash memory sector
SA5
SA4
SA3
SA2
SA1
SA0
Write-disable : State of "0". The bit corresponding to each sector can (be set to "1" to) permit
programming into that sector, with no "0" written in the flash memory write
control register (FWR0/FWR1). (State existing immediately after a reset).
Write-enable : State of "1". Data can be programmed into the corresponding sector.
Write-protect : State of "0". The bit corresponding to each sector cannot (be set to "1" to)
permit programming into that sector even by writing "1" to it with "0" written
in the flash memory write control register (FWR0/FWR1).
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CHAPTER 24 1M-BIT FLASH MEMORY
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
MB90930 Series
Figure 24.4-2 Flash Memory Write-disable/enable/protect States in Flash Memory Write Control
Register (FWR0/FWR1)
Initialize
Register
write
Register
write
Initialize
RST
Writedisable
Write-enable Write-protect
Write-disable
SA0E
Writedisable
Write-enable
Write-disable
Writedisable
Write-protect
Write-disable
Writedisable
Write-enable
Write-disable
SA1E
SA2E
SA3E
Write-disable:
State of "0". The bit corresponding to each sector can (be set to "1" to) permit programming
into that sector, with no "0" written in the flash memory write control register (FWR0/
FWR1). (State existing immediately after a reset).
Write-enable:
State of "1". Data can be programmed into the corresponding sector.
Write-protect:
State of "0". The bit corresponding to each sector cannot (be set to "1" to) permit
programming into that sector even by writing "1" to it with "0" written in the flash memory
write control register (FWR0/FWR1).
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CHAPTER 24 1M-BIT FLASH MEMORY
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
MB90930 Series
■ Setup Flowchart for Flash Memory Write Control Registers (FWR0/FWR1)
Set the FMCS:WE bit and write-permit or write-protect each sector by setting the
corresponding bit in the flash memory write control register (FWR0/FWR1) to "1" or "0",
respectively. To these registers, be sure to write data in words. No bit manipulation instruction
can be used for setting their bits.
Figure 24.4-3 Sample Procedure for Write-protecting/Write-permitting Flash Memory
Start of writing
FMCS: WE (bit5)
Permit flash memory programming.
FWR0/FWR1
Write-protect flash memory
setting
(Write "0" to write-protect and "1" to
write-permit sectors.)
Write program command
sequence
(1) YYYAAAH ← XXAAH
(2) YYY554H ← XX55H
(3) YYYAAAH ← XX80H
(4) Write address ← Write data
Next address
Read internal address.
Data polling
(DQ7)
DATA
DATA
0
Timing limit
(DQ5)
1
Read internal address.
DATA
Data polling
(DQ7)
DATA
Write error
Last address?
NO
YES
FMCS: WE (bit5)
Disable flash memory programming.
End of writing
CM44-10150-1E
YYY : Upper 12 bits of an arbitrary address not set to "0"
(neither write-inhibited nor write-protected) in flash
memory write control register FWR0/FWR1 in the
flash memory area.
X:
Arbitrary value
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CHAPTER 24 1M-BIT FLASH MEMORY
24.4 Flash Memory Write Control Registers (FWR0/FWR1)
MB90930 Series
■ Note on Setting the FMCS:WE Bit
To program into flash memory, set FMCS:WE to "1" to write-permit it and set the flash
memory write control register (FWR0/FWR1). When FMCS:WE inhibits writing (contains
"0"), the write to flash memory is not operated even though it is permitted by the flash memory
write control register (FWR0/FWR1).
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CHAPTER 24 1M-BIT FLASH MEMORY
24.5 Starting the Flash Memory Automatic Algorithm
MB90930 Series
24.5
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, Chip Erase, and Sector Erase. Control of
suspend and restart is enabled for Sector erase.
■ Command Sequence Table
Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to
the command register is in bytes, but use word access to write. The data in the upper bytes at
this time is ignored.
Table 24.5-1 Command Sequence Table
Bus
Command
programming
sequence
cycle
Read/
1st bus write
cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus write
cycle
5th bus write
cycle
Address Data Address Data Address Data Address Data Address Data
1
yyyXXX XXF0
-
-
-
-
-
4
yyyAAA XXAA yyy554 XX55 yyyAAA XXF0
RA
RD
-
-
-
-
program*2
4
yyyAAA XXAA yyy554 XX55 yyyAAA XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip erase
6
yyyAAA XXAA yyy554 XX55 yyyAAA XX80 yyyAAA XXAA yyy554
XX55 yyyAAA XX10
Sector erase*2
6
yyyAAA XXAA yyy554 XX55 yyyAAA XX80 yyyAAA XXAA yyy554
XX55
Read/
reset*1, *2
Programming
RD
-
-
Address Data
-
reset*1
RA
6th bus write
cycle
SA
(even)
Sector erase suspend
Entering address "yyyXXXX" data (xxB0H) suspends erasing during sector erasure.
Sector erase restart
Entering address "yyyXXXX" data (xx30H) restarts erasing after sector erasing is suspended.
XX30
RA: Read address
PA: Write address. Only even number addresses can be specified.
SA: Sector address (see Section "24.2 Sector Configuration of 1M-bit Flash Memory".)
RD: Read data
PD: Write data. Only word data can be specified.
yyy: Upper 12 bits of the arbitrary address which is not set "0" (write prohibited/write-protect prohibited) in the flash memory writing control
register (FWR0/FWR1)
*1: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
*2: For RA, PA, and SA, specify the address which is not set to "0" by the flash memory writing control register (FWR0/FWR1).
Notes: • The addresses in the table above are based on the memory map. Addresses and data are described with the hexadecimal number.
However, "X" indicates an arbitrary number.
• If the chip erase command is issued by accessing to the sector enabled to write where the sector is enabled/disabled to write, the
contents in all sectors will be erased including the sectors where the writing is disabled.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
24.6
MB90930 Series
Confirming the Automatic Algorithm Execution
State
Because the write/erase flow of the flash memory is controlled using the
automatic algorithm, the flash memory has hardware sequence flags for
informing its internal operating state and completion of operation.
■ Hardware Sequence Flags
The hardware sequence flags have the four-bit output of the data polling flag (DQ7), toggle bit
flag (DQ6), timing limit exceeded flag (DQ5), and sector erase timer flag (DQ3). With the state
of each bit, completion of writing/chip sector erase, or validity of erase code write is
confirmed.
Table 24.6-1 lists the bit assignments of the hardware sequence flags.
Table 24.6-1 Bit Assignments of Hardware Sequence Flags
Bit
o.
N
Hardware Sequence Flags
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
-
-
-
The hardware sequence flags can be referenced by read-accessing the addresses of the target sectors
in the flash memory after setting of the command sequence (see Table 24.5-1).
The automatic algorithm execution state can be confirmed with the following methods.
• Confirmation with referring to the hardware sequence flags
• Confirmation with referring to the RDY bit of flash memory control register (FMCS)
When programming, the next instruction should be executed after the completion of automatic
algorithm execution is confirmed with one of these methods. The following sections describe
each hardware sequence flag separately.
Table 24.6-2 lists the functions of the hardware sequence flags.
Table 24.6-2 Hardware Sequence Flag Functions List
Status
DQ7
Write → Write completed
(write address specified)
Chip/sector erase → Erase completed
Sector erase wait → Erase started
Status change
Erase → Sector erase suspended
for normal
(Sector being erased)
operation
Sector erase suspend → Erase restarted
(Sector being erased)
Sector erase suspended
(Sector not being erased)
Abnormal
operation
634
Write
Chip sector erase
DQ6
DQ5
DQ3
DQ7 → DATA:7 Toggle → DATA:6 0 → DATA:5
0 → DATA:3
0→ 1
Toggle → Stop
0→1
1
0
Toggle
0
0→ 1
0→ 1
Toggle → 1
0
1→ 0
1→ 0
1 → Toggle
0
0→ 1
DATA:7
DATA:6
DATA:5
DATA:3
DQ7
Toggle
1
0
0
Toggle
1
1
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CM44-10150-1E
CHAPTER 24 1M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
MB90930 Series
24.6.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) is to indicate that the automatic algorithm is being
executed or has terminated by the data polling function.
■ Data Polling Flag (DQ7) State Transition
● State Change for Normal Operation
Operating
Status
Write →
Completed
DQ7
DQ7 → DATA:7
Sector erase→
Sector erase
Sector erase
Chip/sector erase → Sector erase wait → Erase suspended
suspend →
suspended Sector
Completed
Started
Sector being
Restarted Sector
not being erased
erased
being erased
0→
1
0
0→
1
1→ 0
DATA:7
● State Change for Abnormal Operation
Operating
Status
Write
Chip/sector
Erase
DQ7
DQ7
0
■ Write
Read-access during execution of the automatic write algorithm causes the flash memory to
output the opposite data of bit7 last written, regardless of the value at the address specified by
the address signal. When the flash memory is read-accessed upon completion of the automatic
write algorithm, it outputs bit7 of the value read from the address located by the address signal.
■ Chip/Sector Erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes
the flash memory to output "0" from the sector currently being erased. For a chip erase, readaccess causes the flash memory to output "0" regardless of the value at the address specified by
the address signal. Read-access at the end of the algorithm causes the flash memory to output
"1" in the same way.
■ Sector Erase Suspended
Read-access for an access from sector erase suspended causes the flash memory to output "1" if
the address specified by the address signal belongs to the sector being erased. The flash memory
outputs bit7 (DATA: 7) of the read value at the address specified by the address signal if the
address specified by the address signal does not belong to the sector being erased. Referencing
this flag together with the toggle bit flag (DQ6) enables to see whether the flash memory is in
the sector erase suspended state and which sector is being erased.
Note:
When the automatic algorithm is be ing started, read-access to the specified addr ess is
ignored. After the termination of data polling flag (DQ7) is confirmed, data can be read. A
data read after completion of t he automatic a lgorithm s hould t herefore follow t he r ead
access which confirms the completion of data polling.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
24.6.2
MB90930 Series
Toggle Bit Flag (DQ6)
In the same manner of the data polling flag (DQ7), the toggle bit flag (DQ6) is to
indicate that the automatic algorithm is being executed or has terminated by
the toggle bit function.
■ Toggle Bit Flag (DQ6) State Transition
● State Change for Normal Operation
Operating
status
Write →
Completed
DQ6
Toggle → DATA:6
Sector erase →
Chip/sector erase → Sector erase wait → Erase suspended
Completed
Started
Sector being
erased
Toggle → Stop
Toggle
Toggle → 1
Sector erase
suspend →
Restarted
Sector being
erased
Sector erase
suspended
Sector not being
erased
1 → Toggle
DATA:6
● State Change for Abnormal Operation
Operating
Status
Write
Chip/sector
Erase
DQ6
Toggle
Toggle
■ Write and Chip/Sector Erase
Continuous read-access during execution of the automatic write algorithm and chip/sector
erase algorithm causes the flash memory to toggle the "1" or "0" state alternately for every read
cycle, regardless of the value at the address specified by the address signal. When the flash
memory is continuously read-accessed upon completion of the automatic write or chip/sector
erase algorithm, it stops toggling bit6 and outputs bit6 (DATA: 6) of the value read from the
address located by the address signal.
■ Sector Erase Suspended
When the flash memory is read-accessed during sector erase suspended, it outputs "1" if the
address located by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, the flash memory outputs bit6 (DATA:6) of the value read
from the address located by the address signal.
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24.6 Confirming the Automatic Algorithm Execution State
MB90930 Series
24.6.3
Timing Limit Exceeded Flag (DQ5)
The timing limit excess flag (DQ5) indicates that the automatic algorithm has
exceeded the time (internal pulse count) specified inside the flash memory.
■ Transition of State of Timing Limit Exceeded Flag (DQ5)
● State Change for Normal Operation
Sector erase →
Operating
Chip/sector erase → Sector erase wait → Erase suspended
Write → Completed
status
Completed
Started
Sector being
erased
0 → DATA:5
DQ5
0→ 1
0
0
Sector erase
suspend →
Restarted
Sector being
erased
Sector erase
suspended
Sector not
being erased
0
DATA:5
● State Change for Abnormal Operation
Operating
status
Write
Chip/sector
Erase
DQ5
1
1
■ Write and Chip/Sector Erase
When the flash memory is read-accessed after the write or chip/sector erase automatic
algorithm is started, this flag outputs "0" if the specified time (time required for write/erase
operation) has not been exceeded, or "1" if the time has been exceeded. Because this is done
regardless of whether the automatic algorithm is being executed or has terminated, this flag can
be indicated whether writing/erasing is successfully executed or not. Therefore, if the
automatic algorithm is still executed by the data polling
function or toggle bit function with this flag "1", that indicates the writing is failed.
For example, writing "1" to a flash memory address where "0" has been written will cause the
fail state to occur. In this case, the flash memory will be locked and the automatic algorithm
will not terminate to execute. In rare cases, it may terminate normally with writing "1". As a
result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit
flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing
limit exceeded flag (DQ5) will output "1". Note that this state indicates that the flash memory
is not malfunctioned, but has not been operated correctly. When this state occurs, execute the
Reset command.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
24.6.4
MB90930 Series
Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is to indicate whether the automatic
algorithm is being executed during the sector erase wait period after the Sector
Erase command has been started.
■ Transition of State of Sector Erase Timer Flag (DQ3)
● State Change for Normal Operation
Operating
status
Write →
Completed
DQ3
0 → DATA:3
Sector erase →
Sector erase
Sector erase
Chip/sector erase → Sector erase wait → Erase suspend
suspend →
suspended Sector
Completed
Started
Sector being
Restarted Sector
not being erased
erased
being erased
0→ 1
1
1→
0
0→ 1
DATA:3
● State Change for Abnormal Operation
Operating
status
Write
Chip/sector
Erase
DQ3
0
1
■ Sector Erase
Read-access after the Sector Erase command has been started causes the flash memory to
output "0" if the automatic algorithm is being executed during the sector erase wait period,
regardless of the value at the address specified by the address signal of the sector that issued
the command. The flash memory outputs "1" if the sector erase wait period has been exceeded.
When the data polling function or toggle bit function indicates that the erase algorithm is being
executed, internally controlled erase has already started if this flag is "1". Continuous write of
the sector erase codes or issues of commands other than the Sector Erase Suspend command
will be ignored until erase is terminated.
If this flag is "0", the flash memory accepts an additional sector erase code to be written. To
confirm this, it is advisable to check the state of this flag before continuing to write sector
erase codes. If the flag is "1" at the second status check, the additional sector erase code may
not have been accepted.
■ Sector Erase Suspended
When the flash memory is read-accessed during sector erase suspended, it outputs "1" if the
address located by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, the flash memory outputs bit3 (DATA:3) of the value read
from the address located by the address signal.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.7 Writing/Erasing Flash Memory
MB90930 Series
24.7
Writing/Erasing Flash Memory
This section describes each operation of flash memory Write/Erase with
activation of the automatic algorithm.
■ Writing/Erasing Flash Memory
The automatic algorithm can be activated by writing either command sequence of the Read/
Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Erase Restart (see Table 24.51) from the CPU to flash memory. Writing from CPU to the flash memory must be performed
continuously. In addition, the termination of the automatic algorithm can be confirmed with the
data polling function. After the normal termination, the flash memory is returned to the read/
reset state.
The following items related to writing/erasing of the flash memory are described respectively:
• Setting the read/reset state
• Writing data
• Erasing all data (erasing all chips)
• Erasing optional data (erasing sectors)
• Suspending sector erase
• Restarting sector erase
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CHAPTER 24 1M-BIT FLASH MEMORY
24.7 Writing/Erasing Flash Memory
24.7.1
MB90930 Series
Setting Flash Memory to the Read/Reset State
This section describes the procedure for issuing the Read/Reset command to
set the flash memory to the read/reset state.
■ Setting Flash Memory to the Read/Reset State
To set the flash memory to the read/reset state, issue the Read/Reset command in the command
sequence table (see Table 24.5-1) continuously to the target sector in flash memory.
The Read/Reset command has two types of command sequences to execute the first and third
bus operations. However, there are no essential differences between these command sequences.
The read/reset state is the initial state of the flash memory. When power is on and when a
command terminates normally, the flash memory is set to the read/reset state. In the read/reset
state, other commands wait for input.
In the read/reset state, data is readable by regular read-access. In the same manner to the mask
ROM, program access from the CPU is enabled. The Read/Reset command is not required to
read data for a regular read. Use the command mainly to initialize an automatic algorithm, for
example, when the command has failed to terminate normally for some reason.
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24.7 Writing/Erasing Flash Memory
MB90930 Series
24.7.2
Writing Data to Flash Memory
This section describes the procedure for issuing the Write command to write
data to the flash memory.
■ Writing Data to the Flash Memory
To start the automatic algorithm for writing data into flash memory, issue the write command
in the command sequence table (see Table 24.5-1) continuously to the target sector in flash
memory. Upon completion of a data write to the target address in the fourth cycle, the
automatic algorithm is activated to start automatic writing.
● Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle. Odd
addresses cannot be written correctly. That is, writing to even addresses must be done in units
of word data.
Although writing can be performed in any order of addresses and beyond a sector boundary,
each write command can write only one word of data.
● Notes on writing data
When the flash memory data "0" is written to "1", the data polling flag (DQ7) or toggle bit flag
(DQ6) does not indicate the termination. Therefore, the flash memory elements are determined
to be malfunctioned and become the following statuses. Do not set the data on the flash
memory "0" back to "1" by writing data.
• The time prescribed for writing is exceeded, and the timing limit exceeded flag (DQ5)
indicates an error.
• The data is viewed as if dummy data "1" had been written on the flash memory (When data
is read in the read/reset state, the data remains "0". When "0" is returned to "1", erase
operation should be performed).
All commands are ignored during the execution of the automatic write algorithm. If a hardware
reset is activated during writing at an address, the data at that address is not guaranteed.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.7 Writing/Erasing Flash Memory
MB90930 Series
■ Writing Procedure to the Flash Memory
Figure 24.7-1 shows an example of the procedure for writing to the flash memory. The
hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution
State") can be used to determine the state of the automatic algorithm in the flash memory. In
this procedure, the data polling flag (DQ7) is used to confirm that writing has terminated.
The data read to check the flag is read from the address written to the last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag
(DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is "1", the data
polling flag bit (DQ7) must be rechecked.
In the same manner of the toggle bit flag (DQ6), the toggle operation stops at the same time
that the timing limit exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must
therefore be rechecked.
Figure 24.7-1 Example of writing Procedure to the Flash Memory
Write start
FMCS:WE (bit 5)
Flash memory
write enabled
Write command sequence
(1) yyyAAAH ← XXAAH
(2) yyy554H ← XX55H
(3) yyyAAAH ← XXA0H
(4) Write address ← Write data
Internal address read
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Internal address read
Data
Data polling (DQ7)
Data
Write error
Last address
NO
YES
FMCS:WE (bit 5)
Flash memory
write disabled
Write completed
642
Check with hardware
sequence flags
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24.7 Writing/Erasing Flash Memory
MB90930 Series
24.7.3
Erasing All Data of Flash Memory (Chip Erase)
This section describes the procedure for issuing the Chip Erase command to
erase all data in the flash memory.
■ Erasing All Data of Flash Memory (Chip Erase)
To erase all data from flash memory, issue the Chip Erase command in the command sequence
table (see Table 24.5-1) continuously to the target sectors in flash memory. The Chip Erase
command is executed in six bus operations. The chip erase operation starts upon completion of
the write in the sixth cycle.
For chip erase, the user need not write to the flash memory before erasing. During the
execution of the automatic erase algorithm, the flash memory writes "0" for verification before
all of the cells are erased automatically.
■ Notes on Chip Erase
If the chip erase command is issued by accessing to the sector enabled to write where the sector
is enabled/disabled to write, the contents in all sectors will be erased including the sectors
where the writing is disabled.
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24.7 Writing/Erasing Flash Memory
24.7.4
MB90930 Series
Erasing Arbitrary Data of Flash Memory
(Sector Erase)
This section describes the procedure for issuing the Sector Erase command to
erase one or more optional sectors in flash memory. The data by individual
sector can be erased. Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in Flash Memory
To erase optional data in the flash memory, issue the Sector Erase command in the command
sequence table (see Table 24.5-1) continuously to the target sectors in flash memory.
● Specifying Sectors
The Sector Erase command is executed in six bus operations. The sector erase code (30H) is
written to an accessible even-numbered address in the target sector in the sixth cycle. Then,
sector erase wait of 80 μs is started. To erase multiple sectors, write the erase code (30H) to the
addresses in the target sectors after the above processing operation.
● Notes on specifying multiple sectors
Erasing sectors starts at the end of the sector erase wait period of 80 μs after writing the last
sector erase code. Therefore, to erase multiple sectors at one time, the address in each sector to
be erased and the sector erase code (in the sixth cycle of the command sequence) must be input
within 80 μs. The sector erase timer (hardware sequence flag: DQ3) can be used to check
whether writing of the subsequent sector erase code is valid. At this time, specify so that the
address used for reading the sector erase timer indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm
Execution State") can be used to determine the state of the automatic algorithm in the flash
memory. Figure 24.7-2 shows an example of the procedure for erasing sectors in the flash
memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated.
Note that the data to read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops toggling its output concurrently with the change of the timing
limit exceeded flag (DQ5) to "1". The toggle bit flag (DQ6) must therefore be rechecked even
when the timing limit exceeded flag (DQ5) is "1" (processing in Figure 24.7-2
).
Since the data polling flag (DQ7) also changes at the same time as the timing limit exceeded
flag (DQ5) changes, the data polling flag (DQ7) must be rechecked.
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24.7 Writing/Erasing Flash Memory
MB90930 Series
Figure 24.7-2 Example of Procedure for Erasing Sectors in the Flash Memory
Erase start
FMCS:WE (bit5)
Flash memory erase enabled
Erase command sequence
(1) yyyAAAH XXAA
H
(2) yyy554H XX55
H
80H
(3) yyyAAAH XX
(4) yyyAAAH XXAA
H
(5) yyy554H XX55
H
(6) Enter code to sector to erase. (30H)
YES
Any other sector
to erase?
NO
Internal address read 1
Internal address read 2
NO
YES
Toggle bit (DQ6)
data 1 (DQ6) = data 2 (DQ6)
Sector erase
completed
Next sector
YES
NO
0
Timing limit (DQ5)
1
Internal address read 1
Internal address read 2
NO
Toggle bit (DQ6)
data 1 (DQ6) = data 2 (DQ6)
YES
Erase error
Last sector
NO
YES
FMCS:WE (bit5)
Flash memory
erase disabled
Check with hardware
sequence flag
Erase completed
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CHAPTER 24 1M-BIT FLASH MEMORY
24.7 Writing/Erasing Flash Memory
24.7.5
MB90930 Series
Suspending Sector Erase of Flash Memory
This section describes the procedure for issuing the Sector Erase Suspend
command to suspend erasing of flash memory sectors. During the suspension,
data can be read from sectors that are not being erased.
■ Suspending Sector Erase of Flash Memory
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspended
command in the command sequence table (see Table 24.5-1) from CPU to the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and
enables data to be read from sectors that are not being erased. In the sector erase suspended
state, only reading is enabled; data cannot be written.
The Sector Erase Suspend command is valid only during sector erase operations which include
an erase wait time. The command will be ignored during chip erase or write operations.
The Sector Erase Suspend command is implemented by writing the erase suspend code (B0H).
At this time, specify an optional address in the flash memory for the address. An Erase
Suspend command reissued during sector erase suspended will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will
immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state.
Entering the Erase Suspend command during the erase operation after the sector erase wait
period has terminated will set the erase suspend state after a maximum period of 20 μs has
elapsed. The Sector Erase Suspend command should be entered after 20 μs or more is elapsed
after the Sector Erase command or Sector Erase Restart command is issued.
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24.7 Writing/Erasing Flash Memory
MB90930 Series
24.7.6
Restarting Sector Erase of Flash Memory
This section describes the procedure for issuing the Sector Erase Restart
command to restart suspended erasing of flash memory sectors.
■ Restarting Sector Erase of Flash Memory
To restart a suspended sector erase operation, issue the Sector Erase Restart command in the
command sequence table (see Table 24.5-1) to flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase
suspended state set using the Sector Erase Suspend command. The Sector Erase Restart
command is implemented by writing the erase restart code (30H). At this time, specify an
optional address in the flash memory area for the address.
If a Sector Erase Restart command is issued during sector erasure, the command will be
ignored.
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CHAPTER 24 1M-BIT FLASH MEMORY
24.8 Flash Security Function
24.8
MB90930 Series
Flash Security Function
The flash security function enables to protect the contents in the flash memory.
■ Overview of Flash Security Function
If protection code "01H" is written in the security bit, the flash memory is in the protected state
by security. Once the access to the flash memory is protected, the protected state cannot be
released until the chip erase is performed. Data in the flash memory cannot be read/written
from the external pins unless the protected state is released.
This function is compatible for the applications necessary for the security of self-contained
programs and data stored in the flash memory.
The addresses of the security bit depend on the flash memory size. Table 24.8-1 shows the
address of security bit.
Table 24.8-1 Address of Security Bit
MB90F931/MB90F931S
Flash memory size
Address of security bit
Embedded 1M-bit flash memory
FC0001H
■ How to Apply Security
Write the protection code "01H" to the security bit. The security is applied after the external
reset or power-on.
■ How to Release the Security
Execute the memory data erase function.
■ Operation with the Security Enabled
Read:
invalid data is read
Write:
cannot be written
■ Others
• To set the general-purpose parallel writer, follow the specification of parallel writer.
• It is recommended to write the protection code after programming the flash memory is
completed. It enables to prevent the contents of the memory to be accidentally protected
during programming.
Notes:
• Security bits are allocated in the flash memory area. Writing the protection code "01 H"
to the security bit applies the security. Therefore, Do not write "01H" to the securit y bit
unless the security is to be functioned.
• See Table 24.8-1 above for the address of the security bit.
• Security can not b e a pplied for e ach sector b y specifying t he secto r of t he flash
memory. The security function works for the entire area of the flash memory.
• Note that the flash memory fault cannot be analyzed with the security applied.
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CHAPTER 25
EXAMPLES OF SERIAL
PROGRAMMING
CONNECTION
This chapter gives the examples of connection
for serial programming using the AF220/AF210/
AF120/AF110 Flash Microcontroller Programmer
manufactured by Yokogawa Digital Computer
Corporation.
25.1 Basic Configuration for Serial Programming Connection
25.2 Example of Connection in Single-Chip Mode (Using
Power from User System)
25.3 Example of Connection with Flash Microcontroller
Programmer (Using Power from the User System)
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration for Serial Programming Connection
25.1
MB90930 Series
Basic Configuration for Serial Programming
Connection
The flash memory product supports serial onboard programming (Fujitsu
standard) of flash ROM. This section provides the relevant specifications.
■ Basic Configuration of Serial Programming Connection
Fujitsu-standard serial onboard programming uses the AF220/AF210/AF120/AF110 flash
microcontroller programmer manufactured by Yokogawa Digital Computer Corporation. It is
possible to write it by selecting either of the program that operates by the single chip mode or
the internal ROM external ROM bus mode.
Figure 25.1-1 shows the basic configuration of the connection for MB90F931/MB90F931S
serial programming.
Figure 25.1-1 Flash Products Basic Configuration for Serial Programming Connection
MB90F931/
MB90F931S
Note:
Contact Yokogawa Digit al Comp uter Corporation for inf ormation on th e fu nctions and
operating procedures o f t he AF2 20/AF210/AF120/AF110 flash microcontroller
programmers and on their gen eral-purpose commo n co nnection cable (AZ210) and
connector.
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration for Serial Programming Connection
■ Pins Used for Fujitsu Standard Serial On-board Writing
Table 25.1-1 shows the functions of the related pins used for Fujitsu Standard serial on-board
writing.
Table 25.1-1 Pins Used for Fujitsu-standard Serial Onboard Programming
Pin
MD2,
MD1, MD0
X0, X1
P00, P01
Function
Description
Mode Pins
The serial programming mode is set according to the setting of MD2=1, MD1=1,
and MD0=0.
Oscillation pins
As, in the serial programming mode, CPU internal operation clock is the
PLL clock multiplied-by-1, the internal operation clock frequency is
equal to the oscillation clock frequency. Consequently, the frequencies
that can be input to the high-speed oscillation input pin for serial writing
are from 4 MHz to 32 MHz.
Programming
program start pins
Input "L" level to P00, and "H" level to P01.
RST
Reset pin
-
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
VCC
Source voltage supply
pin
If the programming voltage (VCC=5.0V±10%) is supplied from the user system,
connection with the flash microcontroller programmer is not required.
VSS
GND pin
Must be shared with GND of the flash microcontroller programmer.
Use UART1 in CLK synchronous mode.
To use the P00, SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit
shown in the Figure 25.1-2 is required.
Using the flash microcontroller programmer’s /TICS signal, the user circuit can be
disconnected in serial programming mode. See the connection example.
Figure 25.1-2 Pin Control Circuit
MB90F931/MB90F931S
4.7kΩ
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration for Serial Programming Connection
MB90930 Series
■ Oscillator Clock Frequency and Serial Clock Input Frequency
The serial clock frequency of the flash memory product that can be input can be derived by the
formula shown below. Based on the oscillator clock frequency used, modify the serial clock
input frequency in accordance with the oscillator clock frequency as required.
Calculate the serial clock frequency that can be input as follows:
Table 25.1-2 shows a calculation example.
Serial clock frequency = 0.125 × oscillator clock frequency
Table 25.1-2 Example of Serial Clock Frequency Calculation
Oscillator
clock
frequency
Maximum serial clock
frequency that can be
input to microcontroller
Maximum serial clock
frequency that can be set for
AF220/AF210/AF120/AF110
Maximum serial clock
frequency that can be
set for AF200
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration for Serial Programming Connection
■ System Configuration of Flash Microcontroller Programmer
Table 25.1-3 shows the system configuration of the flash microcontroller programmer.
Table 25.1-3 System Configuration of the Flash Microcontroller Programmer
Type
Main
body
Function
AF220/AC4P
Model with built-in Ethernet interface
/100V to 220V power adapter
AF210/AC4P
Standard model
/100V to 220V power adapter
AF120/AC4P
Model with built-in single key Ethernet interface /100V to 220V power adapter
AF110/AC4P
Single key model
/100V to 220V power adapter
AZ221
Programmer dedicated RS232C cable for PC/AT
AZ210
Standard target probe (a) length: 1m
FF201
Fujitsu F2MC-16LX flash microcontroller control module
AZ290
Remote controller
/P2
2MB PC Card (Option) FLASH memory capacity up to 128 K bytes supported
/P4
4MB PC Card (Option) FLASH memory capacity of up to 512 K bytes supported
Inquiries:
Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
■ Examples of Serial Programming Connections
Examples for the following four types of connections are shown below.
•
Example of connection in single-chip mode (using power from the user system)
•
Example minimum connection with flash microcontroller programmer (using power from
the user system)
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.2 Example of Connection in Single-Chip Mode (Using Power
from User System)
25.2
MB90930 Series
Example of Connection in Single-Chip Mode (Using
Power from User System)
In the user system, mode pins MD2 and MD0, which are set to single-chip
mode, are supplied with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of
AF220/AF210/AF120/AF110, and the system is set to serial programming mode
(serial programming mode: MD2, MD1, MD0= 110).
Figure 25.2-1 Example of Serial Programming Connection in Single Chip Mode for
flash memory product (Power Supplied from the User System)
MB90F931/MB90F931S
4.7kΩ
4.7kΩ
4.7kΩ
10kΩ
4.7kΩ
4.7kΩ
4.7kΩ
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.2 Example of Connection in Single-Chip Mode (Using Power
from User System)
Using the P00, SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as
shown in Figure 25.2-2 (the user circuit is disconnected in serial programming mode by
outputting "L" in the flash microcontroller programmer’s "/TICS" signal).
MB90930 Series
Figure 25.2-2 Pin Control Circuit
MB90F931/MB90F931S
4.7kΩ
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
CM44-10150-1E
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CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.3 Example of Connection with Flash Microcontroller
Programmer (Using Power from the User System)
25.3
MB90930 Series
Example of Connection with Flash Microcontroller
Programmer (Using Power from the User System)
If, in serial programming mode, pins (MD2, MD0 and P00) are set as shown
below, MD2, MD0, and P00 do not need to be connected with the flash
microcontroller programmer.
Figure 25.3-1 Example of Minimum Connection with Flash Microcontroller Programmer for
MB90F035
(Using Power from the User System)
4.7kΩ
MB90F931/MB90F931S
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
3, 4, 9, 10, 11, 12, 16, 17,
18, 19, 20, 23, 24, 25, and 26
pins are OPEN.
656
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.3 Example of Connection with Flash Microcontroller
Programmer (Using Power from the User System)
Using the P00, SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as
shown in Figure 25.3-2 (the user circuit is disconnected in serial programming mode by
outputting "L" in the flash microcontroller programmer’s "/TICS" signal).
MB90930 Series
Figure 25.3-2 Pin Control Circuit
MB90F931/MB90F931S
4.7kΩ
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
657
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
25.3 Example of Connection with Flash Microcontroller
Programmer (Using Power from the User System)
658
FUJITSU MICROELECTRONICS LIMITED
MB90930 Series
CM44-10150-1E
CHAPTER 26
ROM SECURITY
FUNCTION
This chapter explains the ROM security
function.
26.1 Overview of ROM Security Function
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
659
CHAPTER 26 ROM SECURITY FUNCTION
26.1 Overview of ROM Security Function
26.1
MB90930 Series
Overview of ROM Security Function
The ROM security function protects the content of ROM.
■ Overview of ROM Security Function
The ROM security function is to avoid disclosing the ROM data to third parties by restricting
the access to ROM.
Please contact Fujitsu Microelectronics for details of this function.
660
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 27
ADDRESS MATCH
DETECTION FUNCTION
This chapter describes the functions and
operations of the address match detection
function.
27.1 Outline of the Address Match Detection Function
27.2 Sample Application of the Address Match Detection
Function
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CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.1 Outline of the Address Match Detection Function
27.1
MB90930 Series
Outline of the Address Match Detection Function
Once the address matches the setting value in the address detection register,
the INT9 instruction is executed. Once the INT9 interrupt service routine is
processed, the address match can be detected.
There are two address detection registers, each of which has a compare enable
bit. If the address detection register matches the program counter with the
compare enable bit "1", the CPU forces the execution of an INT9 instruction.
■ Block Diagram of the Address Match Detection Function
Figure 27.1-1 shows a block diagram of the address match detection function.
Figure 27.1-1 Block Diagram of the Address Match Detection Function
Compare
Address latch
Address detection register
F2MC-16LX
Enable bit
CPU core
F2MC-16LX bus
■ Register Configuration of the Address Match Detection Function
Figure 27.1-2 shows the register configuration of the address match detection function.
Figure 27.1-2 Register Configuration of the Address Match Detection Function
byte
byte
Access
byte
PADR0 address: 1FF2H/1FF1H/1FF0H
PADR1 address: 1FF5H/1FF4H/1FF3H
bit
PACSR address: 00009EH
662
7
6
-
-
-
-
5
4
3
2
1
R/W
XXXXXXH
R/W
XXXXXXH
0
ReReReReserved served AD1E served AD0E served
R/W
R/W
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
Initial value
Initial value
--000000B
R/W
CM44-10150-1E
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.1 Outline of the Address Match Detection Function
MB90930 Series
■ Program Address Detection Registers (PADR0/PADR1)
The program address detection register holds the address to be compared with the program
counter value. When the address of the instruction executed by the program matches the set
value, with the PACSR interrupt enable bit "1", this module requests the CPU to execute the
INT9 instruction.
If the corresponding interrupt enable bit is "0", no actions are taken.
Figure 27.1-3 shows the register configuration of the program address detection register.
Figure 27.1-3 Configuration of Program Address Detection Register
byte
byte
byte
PADR0 address: 1FF2H/1FF1H/1FF0H
PADR1 address: 1FF5H/1FF4H/1FF3H
Access
Initial value
R/W
XXXXXXH
R/W
XXXXXXH
PADR0 and PADR1 correspond to the PACSR's interrupt enable bits as follows:
Program address detection register
Interrupt enable bit
PADR0
PACSR: AD0E
PADR1
PACSR: AD1E
■ Program Address Detection Control Register (PACSR)
The program address detection control register (PACSR) controls the address detection
function and indicates its state.
Figure 27.1-4 shows the bit configuration of the program address detection control register
(PACSR).
Figure 27.1-4 Bit Configuration of Program Address Detection Control Register (PACSR)
bit
PACSR address: 00009EH
Initial value
7
−
6
−
−
−
−
−
5
4
3
Reserved Reserved AD1E
R/W
0
R/W
0
R/W
0
2
1
Reserved AD0E
R/W
0
R/W
0
0
Reserved
R/W
0
R/W : Readable/Writable
Undefined
−:
[bit7, bit6] Undefined bits
Reading the bit returns an indeterminate value; writing it has no effect on the operation.
[bit5, bit4] Reserved bits
Always write "0".
[bit3] AD1E (Compare Enable 1)
This bit enables the operation of PADR1.
If the PADR1 register value matches the address with this bit "1", the INT9 instruction is
issued to the CPU.
[bit2] Reserved bit
Always write "0".
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CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.1 Outline of the Address Match Detection Function
MB90930 Series
[bit1] AD0E (Compare Enable 0)
This bit enables the operation of PADR0.
If the PADR0 register value matches the address with this bit "1", the INT9 instruction is
issued to the CPU.
[bit0] Reserved bit
Always write "0".
■ Operation of the Address Match Detection Function
If the program counter has the same address as the program address detection register, the
INT9 instruction is executed. If the INT9 interrupt service routine is processed, the address
match detection function can be achieved.
There are two address detection registers, each of which has a compare enable bit. If the
address detection register matches the program counter, with the compare enable bit "1", the
CPU forces the execution of the INT9 instruction.
Note:
If the address detection register and program counter values match, the contents of the
internal da ta bus ar e re placed to "01 H" and th e I NT9 inst ruction is execu ted. Before
updating the content of the address detection register, set the compare enable bit to "0".
Updating it with the compare enable bit "1" may cause an error.
The a ddress ma tch detection fu nction is e ffective only for address es in built-in R OM.
Even if an address in the exte rnal memory area is spec ified. The INT9 instruction will not
be executed.
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FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
MB90930 Series
27.2
Sample Application of the Address Match Detection
Function
The address match detection can be functioned by providing the E2PROM and
storing correction-related information and patch programs in it. The CPU
specifies the address necessary to be corrected based on the information
stored in the E2PROM and transmits to the patch program to RAM. Address
match detection allows the execution of the INT9 instruction to pass control to
the patch program.
■ System Configuration
Figure 27.2-1 shows a sample system configuration.
Figure 27.2-1 Sample System Configuration
E2PROM
MCU
F MC-16LX
2
SIN
Pull-up resistor
Connector (UART)
■ E2PROM Memory Map
Table 27.2-1 shows the E2PROM memory map.
Table 27.2-1 E2PROM Memory Map
Address
Explanation
0000H
Corrected program No. 0 byte count (0 indicates no ROM correction.)
0001H
Program address No. 0 bit7 to bit0
0002H
Program address No. 0 bit15 to bit8
0003H
Program address No. 0 bit24 to bit16
0004H
Corrected program No. 1 byte count (0 indicates no ROM correction.)
0005H
Program address No. 1 bit7 to bit0
0006H
Program address No. 1 bit15 to bit8
0007H
Program address No. 1 bit24 to bit16
0010H or greater
Corrected program No. 0/1 main body
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CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
MB90930 Series
Note:
E2PROM in the initial state must be all "0".
666
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
MB90930 Series
27.2.1
Example of Program Error Correction
The main part of the patch program and its program address are transferred to
the MCU via the connector (UART). The MCU writes the information to E2PROM.
■ If a Program Error Occurs
Figure 27.2-2 shows an example of address match detection function processing in which a
program error occurs.
Figure 27.2-2 Example of Address Match Detection Function Processing
MB90930 series
FFFFFFH
(3)
ROM
(1)
RAM
PC = Interrupt generating address
Abnormal program
External E2PROM
Register setting for
address match
detection function
· Program byte count
· Interrupt generating address
· Corrected program
Data transfer via UART
Corrected program
(2)
000000H
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
667
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
27.2.2
MB90930 Series
Example of Correction Processing
The MCU reads the E2PROM value after a reset. If the byte count of the patch
program is not "0", the MCU reads the main part of the patch program and
writes it to RAM. It then sets PADR0 or PADR1 to the program address to
enable the operation. The start address of the program written to RAM is stored
in RAM at the address specified in each address detection register.
In this case, the INT9 service routine searches for the user defined address to
jump to the corrected program.
■ Flowchart of the Address Match Detection Function Processing
Figure 27.2-3 shows a flowchart of address match detection function processing.
Figure 27.2-3 Flowchart of Address Match Detection Function Processing
Reset
INT9
Read 00H in E2PROM
YES
0000H (E2PROM)=0
NO
Go to corrected program
JMP 000400H
Read address
0001H to 0003H (E2PROM)
↓ MOV
PADR0 (MCU)
Execute corrected program
000400H to 000480H
Read address
0010H to 0090H (E2PROM)
↓ MOV
000400H to 000480H (MCU)
End corrected program
JMP FF0050H
Enable comparison
MOV PACSR, #02H
Execute program normally
PC=PADR0
NO
YES
INT9
668
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
Figure 27.2-4 Diagram of Address Match Detection Function Processing
MB90930 Series
FFFFFFH
ROM
E2PROM
FFFFH
0090H
0010H
0003H
0002H
0001H
0000H
FF0050H
FF0000H
MB90930 series
Abnormal program
FE0000H
Corrected program
001100H
Lower byte of program address: 00H
Middle byte of program address: 00H
Upper byte of program address: 00H
Corrected program byte count: 80H
RAM
000480H
000400H
000100H
000000H
Stack area
RAM area
Patch program
RAM/register area
I/O area
■ INT9 Interrupt
The interrupt routine checks the PC value saved to the stack to identify the address detected as
having caused an interrupt and branches control to the corresponding program. Information
stacked upon the occurrence of the interrupt is discarded.
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
669
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION
27.2 Sample Application of the Address Match Detection
Function
670
FUJITSU MICROELECTRONICS LIMITED
MB90930 Series
CM44-10150-1E
APPENDIX
The appendix provides the I/O map and
describes the available instructions.
APPENDIX A I/O Maps
APPENDIX B Instructions
CM44-10150-1E
FUJITSU MICROELECTRONICS LIMITED
671
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
APPENDIX A I/O Maps
The registers of individual peripheral resources are assigned the following
addresses.
Table A-1 and Table A-2 list the addresses assigned for the registers of
individual peripheral resources.
Table A-1 I/O Map (1 / 12)
Address
Register Name
Abbreviation
Access
Peripheral
Functions
Initial Value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
0AH,
0BH
(Not available)
0CH
Port C data register
PDRC
R/W
Port C
XXXXXXXXB
0DH
Port D data register
PDRD
R/W
Port D
XXXXXXXXB
0EH
Port E data register
PDRE
R/W
Port E
XXXXXXXXB
Port 0
00000000B
0FH
10H
672
(Not available)
Port 0 direction register
DDR0
R/W
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (2 / 12)
Address
Register Name
Abbreviation
Access
Peripheral
Functions
Initial Value
11H
Port 1 direction register
DDR1
R/W
Port 1
XX000000B
12H
Port 2 direction register
DDR2
R/W
Port 2
000000XXB
13H
Port 3 direction register
DDR3
R/W
Port 3
00000000B
14H
Port 4 direction register
DDR4
R/W
Port 4
00000000B
15H
Port 5 direction register
DDR5
R/W
Port 5
00000000B
16H
Port 6 direction register
DDR6
R/W
Port 6
00000000B
17H
Port 7 direction register
DDR7
R/W
Port 7
00000000B
18H
Port 8 direction register
DDR8
R/W
Port 8
00000000B
19H
Port 9 direction register
DDR9
R/W
Port 9
X0000000B
1AH
Analog input enable 6
ADER6
R/W
Port 6, A/D
11111111B
1BH
Analog input enable 7
ADER7
R/W
Port 7, A/D
11111111B
1CH
Port C direction register
DDRC
R/W
Port C
00000000B
1DH
Port D direction register
DDRD
R/W
Port D
X0000000B
1EH
Port E direction register
DDRE
R/W
Port E
XXXXX000B
1FH
Analog input enable 8
ADER8
R/W
Port 8, A/D
11111111B
20H
A/D control status register
lower
ADCS0
R/W
21H
A/D control status register
upper
ADCS1
R/W
22H
A/D data register lower
ADCR0
R
00000000B
23H
A/D data register upper
ADCR1
R
XXXXXX00B
CM44-10150-1E
000XXXX0B
A/D converter
FUJITSU MICROELECTRONICS LIMITED
0000000XB
673
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (3 / 12)
Address
Register Name
Abbreviation
24H
Compare clear register
Peripheral
Functions
Initial Value
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
00000000B
CPCLR
25H
26H
Timer data register
Access
TCDT
27H
R/W
16bit free-run timer
00000000B
28H
Timer control status
register lower
TCCSL
R/W
00000000B
29H
Timer control status
register upper
TCCSH
R/W
01-00000B
2AH
PPG0 control status
register lower
PCNTL0
R/W
00000000B
2BH
PPG0 control status
register upper
PCNTH0
R/W
00000001B
2CH
PPG1 control status
register lower
PCNTL1
R/W
00000000B
2DH
PPG1 control status
register upper
PCNTH1
R/W
00000001B
2EH
PPG2 control status
register lower
PCNTL2
R/W
00000000B
2FH
PPG2 control status
register upper
30H
16bit PPG0
16bit PPG1
16bit PPG2
PCNTH2
R/W
00000001B
External interrupt enable
ENIR
R/W
00000000B
31H
External interrupt request
EIRR
R/W
00000000B
32H
External interrupt level
lower
ELVRL
R/W
33H
External interrupt level
upper
ELVRH
R/W
674
External interrupt
FUJITSU MICROELECTRONICS LIMITED
00000000B
00000000B
CM44-10150-1E
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (4 / 12)
Address
Register Name
Abbreviation
Access
Peripheral
Functions
Initial Value
34H
Serial mode register 0
SMR0
R/W, W
00000000B
35H
Serial control register 0
SCR0
R/W, W
00000000B
36H
Reception/Transmission
data register 1
RDR0/
TDR0
R/W
00000000B
37H
Serial status register 0
SSR0
R/W, R
00001000B
38H
Extended Communication
Control
register 0
ECCR0
R/W, R, W
39H
Extended status Control
Register 0
ESCR0
R/W
00000100B
3AH
Baud Rate Generator
Register 00
BGR00
R/W
00000000B
3BH
Baud Rate Generator
Register 01
BGR01
R/W, R
00000000B
3CH
to
47H
48H
Input capture Input Select
Register
ICISR
R/W
Timer control status
register 0 lower
TMCSR0L
R/W
51H
Timer control status
register 0 upper
TMCSR0H
R/W
Timer register 0/Reload
register 0
TMR0/
TMRLR0
R/W
54H
Timer control status
register 1 lower
TMCSR1L
R/W
55H
Timer control status
register 1 upper
TMCSR1H
R/W
TMR1/
TMRLR1
R/W
56H
57H
Input capture
0/1/2/3/4/5/6/7
00000000B
(Not available)
50H
53H
000000XXB
(Not available)
49H
to
4FH
52H
UART
(LIN/SCI) 0
Timer register 1/Reload
register 1
CM44-10150-1E
00000000B
16bit reload timer 0
XXX10000B
XXXXXXXXB
XXXXXXXXB
00000000B
16bit reload timer 0
XXX10000B
XXXXXXXXB
FUJITSU MICROELECTRONICS LIMITED
XXXXXXXXB
675
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (5 / 12)
Address
Register Name
Abbreviation
Access
LOCR1
R/W
Peripheral
Functions
Initial Value
58H
LCD output control
register 1
59H
LCD output control
register 2
LOCR2
R/W
00000000B
5AH
Sound control register 0
lower
SGCRL0
R/W
00000000B
5BH
Sound control register 0
upper
SGCRH0
R/W
5CH
Frequency data register 0
SGFR0
R/W
XXXXXXXXB
5DH
Amplitude data register 0
SGAR0
R/W
00000000B
5EH
Decrement grade register
0
SGDR0
R/W
Tone count register 0
SGTR0
R/W
Input capture register 0
IPCP0
R
00000000B
LCDC
5FH
Sound generator 0
0XXXX100B
XXXXXXXXB
Sound generator 0
XXXXXXXXB
XXXXXXXXB
60H
61H
XXXXXXXXB
Input capture 0/1
XXXXXXXXB
62H
Input capture register 1
IPCP1
R
63H
XXXXXXXXB
XXXXXXXXB
64H
Input capture register 2
IPCP2
R
65H
XXXXXXXXB
Input capture 2/3
XXXXXXXXB
66H
Input capture register 3
IPCP3
R
67H
XXXXXXXXB
68H
Input capture control
status register 0/1
69H
Input capture edge register
0/1
ICE01
R/W
XXX0X0XXB
6AH
Input capture control
status register 2/3
ICS23
R/W
00000000B
6BH
Input capture edge register
2/3
ICE23
R/W
6CH
LCD control register
lower
LCRL
R/W
6DH
LCD control register
upper
LCRH
ICS01
00000000B
R/W
Input capture 0/1
Input capture 2/3
676
XXXXXXXXB
LCD controller/
Driver
R/W
FUJITSU MICROELECTRONICS LIMITED
00010000B
00000000B
CM44-10150-1E
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (6 / 12)
Abbreviation
Access
Peripheral
Functions
Initial Value
6EH
Low voltage/CPU
operation
detection reset control
register
LVRC
R/W
Low voltage/CPU
operation detection
reset
00111000B
6FH
ROM mirror register
ROMM
W
ROM mirror
XXXXXXX1B
Message buffer valid area
BVALR
(R/W)
00000000B
00000000B
Transmission request
register
TREQR
(R/W)
00000000B
00000000B
Transmission cancel
register
TCANR
(W)
00000000B
00000000B
TCR
(R/W)
00000000B
00000000B
Address
Register Name
70H
71H
72H
73H
74H
75H
76H
77H
Transmission completed
register
CAN1
78H
79H
7AH
7BH
RCR
(R/W)
00000000B
00000000B
Remote request receiving
register
RRTRR
(R/W)
00000000B
00000000B
Receiving overrun register
ROVRR
(R/W)
00000000B
00000000B
Receiving interrupt enable
register
RIER
(R/W)
00000000B
00000000B
PWM control register 0
PWC0
R/W
Receiving completed
register
7CH
7DH
7EH
7FH
80H
81H
82H
PWM control register 1
PWC1
R/W
Stepping motor
controller 1
000000X0B
Stepping motor
controller 2
000000X0B
Stepping motor
controller 3
000000X0B
(Not available)
PWM control register 2
PWC2
85H
86H
000000X0B
(Not available)
83H
84H
Stepping motor
controller 0
R/W
(Not available)
PWM control register 3
CM44-10150-1E
PWC3
R/W
FUJITSU MICROELECTRONICS LIMITED
677
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (7 / 12)
Address
Register Name
Abbreviation
87H
88H
Peripheral
Functions
Initial Value
LCDC
XXXXX111B
(Not available)
LCD output control
register 1
LOCR3
89H
8AH
Access
R/W
(Not available)
A/D setting register 0
ADSR0
00000000B
R/W
A/D
8BH
A/D setting register 1
8CH
ADSR1
R/W
00000000B
Port input Level Select 0
PIL0
R/W
00000000B
8DH
Port input Level Select 1
PIL1
R/W
8EH
Port input Level Select 2
PIL2
R/W
8FH
to
9DH
Port Input Level
Select
XXXX0000B
XXXX0000B
(Not available)
9EH
Program address detection
control register
9FH
Delay interrupt/release
register
A0H
A1H
PACSR
R/W
Address match
detection function
XXXX0X0XB
DIRR
R/W
Delayed interrupt
XXXXXXX0B
Low-power mode control
register
LPMCR
R/W
00011000B
Clock select register
CKSCR
R/W, R
Low-power
consumption control
circuit
A2H
to
A7H
11111100B
(Not available)
A8H
Watchdog timer control
register
WDTC
R, W
Watchdog timer
XXXXX111B
A9H
Time base timer control
register
TBTC
R/W, W
Time base timer
1XX00100B
WTC
R/W, W, R
Watch timer
(sub clock)
10001000B
Flash interface
000X0000B
AAH
Watch timer control
register
ABH
to
ADH
AEH
AFH
678
(Not available)
FLASH control register
FMCS
R/W
(Not available)
FUJITSU MICROELECTRONICS LIMITED
CM44-10150-1E
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (8 / 12)
Address
Register Name
Abbreviation
Access
Peripheral
Functions
Initial Value
B0H
Interrupt control register
00
ICR00
R/W
00000111B
B1H
Interrupt control register
01
ICR01
R/W
00000111B
B2H
Interrupt control register
02
ICR02
R/W
00000111B
B3H
Interrupt control register
03
ICR03
R/W
00000111B
B4H
Interrupt control register
04
ICR04
R/W
00000111B
B5H
Interrupt control register
05
ICR05
R/W
00000111B
B6H
Interrupt control register
06
ICR06
R/W
00000111B
B7H
Interrupt control register
07
ICR07
R/W
00000111B
B8H
Interrupt control register
08
ICR08
R/W
00000111B
B9H
Interrupt control register
09
ICR09
R/W
00000111B
BAH
Interrupt control register
10
ICR10
R/W
00000111B
BBH
Interrupt control register
11
ICR11
R/W
00000111B
BCH
Interrupt control register
12
ICR12
R/W
00000111B
BDH
Interrupt control register
13
ICR13
R/W
00000111B
BEH
Interrupt control register
14
ICR14
R/W
00000111B
BFH
Interrupt control register
15
ICR15
R/W
00000111B
Interrupt controller
C0H
to
C3H
CM44-10150-1E
(Not available)
FUJITSU MICROELECTRONICS LIMITED
679
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (9 / 12)
Address
Register Name
Abbreviation
Access
Peripheral
Functions
Initial Value
C4H
Serial mode register 1
SMR1
R/W, W
00000000B
C5H
Serial control register 1
SCR1
R/W, W
00000000B
C6H
Reception/Transmission
data register 1
RDR1/TDR1
R/W
00000000B
C7H
Serial status register 1
SSR1
R/W, R
00001000B
C8H
Extended Communication
Control Register 1
ECCR1
R/W, R
C9H
Extended Status Control
Register 1
ESCR1
R/W
00000100B
CAH
Baud Rate Generator
Register 10
BGR10
R/W
00000000B
CBH
Baud Rate Generator
Register 10
BGR11
R/W, R
00000000B
CCH
Watch timer control
register lower
WTCRL
R/W
000XXXX0B
CDH
Watch timer control
register middle
WTCRM
R/W
CEH
Watch timer control
register upper
WTCRH
R/W
CFH
PLL/Sub Clock Control
Register
PSCCR
W
D0H
Input capture control
status register 4/5
ICS45
R/W
D1H
Input capture edge register
4/5
UART
(LIN/SCI) 1
Real-time watch
Timer
000000XXB
00000000B
XXXXXX00B
PLL/Sub Clock
XXXXXX00B
00000000B
Input capture 4/5
680
ICE45
R/W, R
FUJITSU MICROELECTRONICS LIMITED
XXXXXXXXB
CM44-10150-1E
APPENDIX
APPENDIX A I/O Maps
MB90930 Series
Table A-1 I/O Map (10 / 12)
Address
Register Name
Abbreviation
Access
ICS67
R/W
Peripheral
Functions
Initial Value
D2H
Input capture control
status register 6/7
D3H
Input capture edge register
6/7
D4H
Timer control status
register 2 lower
D5H
Timer control status
register 2 upper
TMCSR2H
R/W
XXX10000B
D6H
Timer control status
register 3 lower
TMCSR3L
R/W
00000000B
D7H
Timer control status
register 3 upper
D8H
Sound control register 1
lower
D9H
Sound control register 1
upper