The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM25-10151-2E F2MC-8L 8-BIT MICROCONTROLLER MB89480/480L Series HARDWARE MANUAL F2MC-8L 8-BIT MICROCONTROLLER MB89480/480L Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED PREFACE ■ Objective and Intended Readership of This Manual Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB89480/480L series has been developed as a general-purpose version of the F2MC-8L family consisting of proprietary 8-bit, single-chip microcontrollers applicable as application-specific integrated circuits (ASICs). The MB89480/480L series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. This manual describes the functions and operation of the MB89480/480L series and is aimed at engineers using the MB89480/480L series of microcontrollers to develop actual products. See "F2MC-8L MB89600 Series Programming Manual" for details on the MB89480/480L instruction set. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ Trademark Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ Configuration of This Manual This manual consists of the following 17 chapters and an appendix: CHAPTER 1 OVERVIEW Provides an overview of the features and functions of the MB89480/480L series. CHAPTER 2 HANDLING DEVICES Describes points to note when using the MB89480/480L series. CHAPTER 3 CPU Describes the functions of the MB89480/480L series CPU. CHAPTER 4 I/O PORTS Describes the function and operation of the MB89480/480L series I/O ports. CHAPTER 5 TIME-BASE TIMER Describes the function and operation of the MB89480/480L series time-base timer. CHAPTER 6 WATCHDOG TIMER Describes the functions and operation of the MB89480/480L series watchdog timer. CHAPTER 7 WATCH PRESCALER Describes the functions and operation of the MB89480/480L series watch prescaler. CHAPTER 8 8-BIT PWM TIMER Describes the functions and operation of the MB89480/480L series PWM timer. CHAPTER 9 PWC TIMER Describes the functions and operation of the MB90370 series PWC timer. CHAPTER 10 6-BIT PPG TIMER Describes the functions and operation of the MB89480/480L series 6-bit PPG. i CHAPTER 11 8/16-BIT TIMER/COUNTER Describes the functions and operation of the MB89480/480L series 8/16-bit Timer/Counter. CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) Describes the function and operation of the MB89480/480L series external interrupt (edge). CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) Describes the function and operation of the MB89480/480L series external interrupt (level). CHAPTER 14 A/D CONVERTER Describes the functions and operation of the MB89480/480L series A/D converter. CHAPTER 15 UART/SIO Describes the function and operation of the MB89480/480L series UART/SIO. CHAPTER 16 BUZZER OUTPUT Describes the function and operation of the MB89480/480L series audible alarm output. CHAPTER 17 LCD CONTROLLER/DRIVER Describes the function and operation of the MB89480/480L series liquid crystal display (LCD) controller-driver circuit. APPENDIX The appendixes provide I/O maps, mask options, instruction summary, instruction list, instruction map and other information. ii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright© 2004-2007 FUJITSU LIMITED All rights reserved iii READING THIS MANUAL ■ Page Layout In this manual, an entire section is presented on a single page or spread whenever possible. The reader can thus view a section without having to flip pages. The content of each section is summarized immediately below the title. You can obtain a rough overview of this product by reading through these summaries. Also, higher level section headings are given in lower sections so that you can know to which section the text you are currently reading belongs. ■ Finding Information In addition to the standard table of contents and index, the following methods are available to find information in a particular section when required. ● Register index Information can be looked up in the register index by register name, by bit name, and by their respective abbreviations. ● Subheading index The sub-headings in each section (lines that start with ■) are collected together in the subheading index. The subheading index provides a means of looking up information at a finer level of detail than the table of contents. ■ Naming Conventions for Register Name and Pin Name ● Example for description of register name and bit name By writing “1” to the sleep bit (STBC: SLP) in the standby control register. Bit name Bit name abbreviation Register name Register name abbreviation Disable the interrupt request output (TBTC: TBIE = 0) from the time-base timer. Setup data Bit name abbreviation Register name abbreviation Interrupt is accepted if the interrupt is enabled (CCR: I = 1). Register name abbreviation Bit name abbreviation Current status ● Notations for shared pins Pin P14/SEG27/AN0 Many of the pins in the devices of this series are multi-function pins. (They can be switched between two or more functions under program control.) The multiple names of these pins (indicating their multiple functions) are separated by slant bars (/). iv ■ Facing Pages Organization and Notation Conventions Subheading Section summary Section title Higher level section Table title Figure title Chapter title Reference Indicates an item or manual that should be referenced. Series title Note Provides useful information for reference. Check Points requiring check and prohibited items. Always read checks. v ■ Development Tools and Other Resources Required for Development The following items are required for developing the MB89480/480L series. Contact FUJITSU sales representative for the required development tools and other resources. ● Manuals required for development Checklist ❑• F2MC-8L MB89480/480L Series Data Sheet (Provides electrical characteristics and various characteristic examples for the device.) ❑• F2MC-8L MB89600 Series Programming Manual (Describes the F2MC-8L family instruction set.) *• F2MC-8L MB89600 Series C Compiler Manual (Only required when developing in C.) (Describes program development in C and how to run the compiler.) *• F2MC-8L MB89600 Series Assembler Manual (Describes program development in assembly language.) *• F2MC-8L MB89600 Series Support System Manual (Describes how to run the macro assembler, linker, and library manager.) *• F2MC-8L MB89600 Series Software Simulator Manual (Only required when performing evaluation using the simulator.) (Describes how to operate the software simulator.) Manuals marked with * are provided with the products. In addition, manuals for products such as development tools are provided with the product. ● Software required for development Checklist ❑• C compiler (Only required when developing in C.) ❑• Assembler, linker, librarian ❑• Software simulator (Only required when performing evaluation using the simulator.) ❑• Emulator/debugger (Only required when performing evaluation using the MB2140A series.) The part number for each software package differs depending on the operating system. See the F2MC development tools catalog or product guide for details. ● Items required for evaluation using one-time PROM microcontrollers (when performing your own PROM programming) Checklist ❑• MB89P485 ❑• ROM programmer (a programmer able to program an MBM27C256A) See the data sheet for details of recommended programmers. vi ● Development tool Checklist ❑• MB89PV480 (Piggyback/evaluation device) ❑• Evaluation tools (Main unit) MB2141A (Pod) + (Probe) MB2144-505 + MB2144-202 Check with the supplier when using a third party development environment. ● Reference material • F2MC development tools catalog • Microcomputer product guide vii viii CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 HANDLING DEVICES ................................................................................ 23 Notes on Handling Devices .............................................................................................................. 24 CHAPTER 3 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 3.7.1 3.7.2 3.7.3 3.7.4 OVERVIEW ................................................................................................... 1 Features of MB89480/480L Series ..................................................................................................... 2 MB89480/480L Series Product Range ............................................................................................... 4 Differences between Products ............................................................................................................ 7 Block Diagram of MB89480/480L Series ............................................................................................ 8 Pin Assignment ................................................................................................................................... 9 Package Dimensions ........................................................................................................................ 12 Pin Functions .................................................................................................................................... 16 CPU ............................................................................................................ 25 Memory Space .................................................................................................................................. Special Purpose Areas ................................................................................................................ Storing 16-bit Data in Memory ..................................................................................................... Dedicated Registers ......................................................................................................................... Condition Code Register (CCR) .................................................................................................. Register Bank Pointer (RP) ......................................................................................................... General-purpose Registers ............................................................................................................... Interrupts ........................................................................................................................................... Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) ......................................................... Interrupt Processing .................................................................................................................... Multiple Interrupts ........................................................................................................................ Interrupt Processing Time ........................................................................................................... Stack Operation during Interrupt Processing ............................................................................... Stack Area for Interrupt Processing ............................................................................................. Resets ............................................................................................................................................... Reset Flag Register (RSFR) ........................................................................................................ External Reset Pin ....................................................................................................................... Reset Operation .......................................................................................................................... Pin States during Reset ............................................................................................................... Clocks ............................................................................................................................................... Clock Generator .......................................................................................................................... Clock Controller ........................................................................................................................... System Clock Control Register (SYCC) ...................................................................................... Clock Modes ................................................................................................................................ Oscillation Stabilization Wait Time .............................................................................................. Standby Modes (Low-Power Consumption) ..................................................................................... Operating States in Standby Modes ............................................................................................ Sleep Mode ................................................................................................................................. Stop Mode ................................................................................................................................... Watch Mode ................................................................................................................................ ix 26 28 30 31 33 36 37 39 40 42 45 46 47 48 49 51 53 54 57 58 60 61 63 65 68 71 73 74 75 76 3.7.5 Standby Control Register (STBC) ............................................................................................... 3.7.6 State Transition Diagram ............................................................................................................. 3.7.7 Notes on Using Standby Modes .................................................................................................. 3.8 Memory Access Mode ...................................................................................................................... CHAPTER 4 4.1 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.7 4.7.1 4.7.2 4.8 122 124 126 128 129 131 133 WATCHDOG TIMER ................................................................................ 135 Overview of Watchdog Timer ......................................................................................................... Block Diagram of Watchdog Timer ................................................................................................. Watchdog Timer Control Register (WDTC) .................................................................................... Operation of Watchdog Timer ......................................................................................................... Notes on Using Watchdog Timer .................................................................................................... Program Example for Watchdog Timer .......................................................................................... CHAPTER 7 7.1 7.2 TIME-BASE TIMER .................................................................................. 121 Overview of Time-base Timer ......................................................................................................... Block Diagram of Time-base Timer ................................................................................................ Time-base Timer Control Register (TBTC) ..................................................................................... Time-base Timer Interrupt .............................................................................................................. Operation of Time-base Timer ........................................................................................................ Notes on Using Time-base Timer ................................................................................................... Program Example for Time-base Timer .......................................................................................... CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.6 I/O PORTS .................................................................................................. 85 Overview of I/O Ports ........................................................................................................................ 86 Port 0 ................................................................................................................................................ 88 Port 0 Registers (PDR0, DDR0, RDR0) ...................................................................................... 90 Operation of Port 0 ...................................................................................................................... 92 Port 1 ................................................................................................................................................ 94 Port 1 Registers (PDR1, DDR1) .................................................................................................. 96 Operation of Port 1 ...................................................................................................................... 98 Port 2 .............................................................................................................................................. 100 Port 2 Registers (PDR2, DDR2, PURC2) .................................................................................. 104 Operation of Port 2 .................................................................................................................... 106 Port 3 .............................................................................................................................................. 108 Port 3 Register (PDR3) .............................................................................................................. 110 Operation of Port 3 .................................................................................................................... 111 Port 4 .............................................................................................................................................. 112 Port 4 Registers (PDR4) ............................................................................................................ 114 Operation of Port 4 .................................................................................................................... 115 Port 5 .............................................................................................................................................. 116 Port 5 Register (PDR5) .............................................................................................................. 118 Operation of Port 5 .................................................................................................................... 119 Program Example for I/O Ports ....................................................................................................... 120 CHAPTER 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 77 79 81 83 136 137 139 140 142 143 WATCH PRESCALER ............................................................................. 145 Overview of Watch Prescaler ......................................................................................................... 146 Block Diagram of Watch Prescaler ................................................................................................. 148 x 7.3 7.4 7.5 7.6 7.7 Watch Prescaler Control Register (WPCR) .................................................................................... Watch Prescaler Interrupt ............................................................................................................... Operation of Watch Prescaler ......................................................................................................... Notes on Using Watch Prescaler .................................................................................................... Program Example for Watch Prescaler .......................................................................................... CHAPTER 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.5 8.6 8.7 8.8 8.9 8.10 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.7 9.8 9.9 9.10 9.11 8-BIT PWM TIMER ................................................................................... 157 Overview of 8-bit PWM Timer ......................................................................................................... Block Diagram of 8-bit PWM Timer ................................................................................................ Structure of 8-bit PWM Timer ......................................................................................................... Registers of 8-bit PWM Timer ......................................................................................................... PWM Control Register (CNTR) ................................................................................................. PWM Compare Register (COMR) ............................................................................................. 8-bit PWM Timer Interrupts ............................................................................................................. Operation of Interval Timer Function .............................................................................................. Operation of PWM Timer Function ................................................................................................. States in Each Mode during 8-bit PWM Timer Operation ............................................................... Notes on Using 8-bit PWM Timer ................................................................................................... Program Example for 8-bit PWM Timer .......................................................................................... CHAPTER 9 149 151 152 154 156 158 160 162 163 164 166 168 169 170 171 173 174 PWC TIMER ............................................................................................. 177 Overview of Pulse Width Count Timer ............................................................................................ Block Diagram of Pulse Width Count Timer ................................................................................... Structure of Pulse Width Count Timer ............................................................................................ Registers of Pulse Width Count Timer ............................................................................................ PWC Pulse Width Control Register 1 (PCR1) ........................................................................... PWC Pulse Width Control Register 2 (PCR2) ........................................................................... PWC Reload Buffer Register (PLBR) ........................................................................................ Pulse Width Count Timer Interrupts ................................................................................................ Operation of Interval Timer Function .............................................................................................. Operation of Pulse Width Measurement Function .......................................................................... States in Each Mode during Pulse Width Count Timer Operation .................................................. Notes on Using Pulse Width Count Timer ...................................................................................... Program Example for Timer Function of Pulse Width Count Timer ................................................ Program Example for Pulse Width Measurement Function of Pulse Width Count Timer ............... 178 180 182 183 184 187 189 191 192 195 198 199 200 203 CHAPTER 10 6-BIT PPG TIMER .................................................................................... 205 10.1 Overview of 6-bit PPG Timer .......................................................................................................... 10.2 Block Diagram of 6-bit PPG Timer .................................................................................................. 10.3 Pin of 6-bit PPG Timer .................................................................................................................... 10.4 Registers of 6-bit PPG Timer .......................................................................................................... 10.4.1 6-bit PPG Control Register 1 (PPGC1) .................................................................................... 10.4.2 6-bit PPG Control Register 2 (PPGC2) ..................................................................................... 10.5 Operation of 6-bit PPG Timer ......................................................................................................... 10.6 Notes on Using 6-bit PPG Timer .................................................................................................... 10.7 Program Example for 6-bit PPG Timer ........................................................................................... xi 206 209 211 212 213 214 215 217 219 CHAPTER 11 8/16-BIT TIMER/COUNTER ..................................................................... 221 11.1 Overview of 8/16-bit Timer/Counter ................................................................................................ 11.2 Block Diagram of 8/16-bit Timer/Counter ....................................................................................... 11.3 Pins of 8/16-bit Timer/Counter ........................................................................................................ 11.4 Registers of 8/16-bit Timer/Counter ................................................................................................ 11.4.1 Timer 11/21 Control Register (T11CR/T21CR) ......................................................................... 11.4.2 Timer 12/22 Control Register (T12CR/T22CR) ......................................................................... 11.4.3 Timer 11/21 Data Register (T11DR/T21DR) ............................................................................. 11.4.4 Timer 12/22 Data Register (T12DR/T22DR) ............................................................................. 11.5 8/16-bit Timer/Counter Interrupt ..................................................................................................... 11.6 Operation of Interval Timer Function .............................................................................................. 11.7 Operation of Counter Function ....................................................................................................... 11.8 Operation of the Square Wave Output Initial Setting Function ....................................................... 11.9 Operation of 8/16-bit Timer/Counter Stop and Restart ................................................................... 11.10 States in Each Mode during 8/16-bit Timer/Counter Operation ...................................................... 11.11 Notes on Using 8/16-bit Timer/Counter .......................................................................................... 11.12 Program Examples for 8/16-bit Timer/Counter ............................................................................... 222 224 226 228 229 231 233 235 237 239 241 243 245 246 247 249 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) ......................................... 253 12.1 Overview of the External Interrupt 1 Circuit .................................................................................... 12.2 Block Diagram of the External Interrupt 1 Circuit ............................................................................ 12.3 Pins of the External Interrupt 1 Circuit ............................................................................................ 12.4 Registers of External Interrupt 1 Circuit .......................................................................................... 12.4.1 External Interrupt Control Register 1 (EIC1) .............................................................................. 12.4.2 External Interrupt Control Register 2 (EIC2) .............................................................................. 12.5 External Interrupt 1 Circuit Interrupts .............................................................................................. 12.6 Operation of the External Interrupt 1 Circuit ................................................................................... 12.7 Program Example for the External Interrupt 1 Circuit ..................................................................... 254 255 256 257 258 260 262 263 264 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) ....................................... 265 13.1 Overview of External Interrupt 2 Circuit (Level) .............................................................................. 13.2 Block Diagram of External Interrupt 2 Circuit .................................................................................. 13.3 Pins of External Interrupt 2 Circuit .................................................................................................. 13.4 Registers of External Interrupt 2 Circuit .......................................................................................... 13.4.1 External Interrupt 2 Control Register (EIE2) .............................................................................. 13.4.2 External Interrupt 2 Flag Register (EIF2) ................................................................................... 13.5 External Interrupt 2 Circuit Interrupt ................................................................................................ 13.6 Operation of External Interrupt 2 Circuit ......................................................................................... 13.7 Program Example for External Interrupt 2 Circuit ........................................................................... 266 267 268 270 271 273 274 275 276 CHAPTER 14 A/D CONVERTER .................................................................................... 277 14.1 Overview of A/D Converter ............................................................................................................. 14.2 Block Diagram of A/D Converter ..................................................................................................... 14.3 Pins of A/D Converter ..................................................................................................................... 14.4 Registers of A/D Converter ............................................................................................................. 14.4.1 A/D Control Register 1 (ADC1) .................................................................................................. 14.4.2 A/D Control Register 2 (ADC2) .................................................................................................. xii 278 279 281 282 283 285 14.4.3 A/D Data Registers (ADDL and ADDH) ..................................................................................... 14.5 A/D Converter Interrupt ................................................................................................................... 14.6 Operation of A/D Converter ............................................................................................................ 14.7 Notes on Using A/D Converter ....................................................................................................... 14.8 Program Example for A/D Converter .............................................................................................. 287 288 289 291 293 CHAPTER 15 UART/SIO ................................................................................................. 295 15.1 Overview of UART/SIO ................................................................................................................... 15.2 Block Diagram of UART/SIO .......................................................................................................... 15.3 Pins of UART/SIO ........................................................................................................................... 15.4 Registers of UART/SIO ................................................................................................................... 15.4.1 Serial Mode Control Register 1 (SMC1) .................................................................................... 15.4.2 Serial Mode Control Register 2 (SMC2) .................................................................................... 15.4.3 Serial Status and Data Register (SSD) ..................................................................................... 15.4.4 Serial Input Data Register (SIDR) ............................................................................................. 15.4.5 Serial Output Data Register (SODR) ......................................................................................... 15.4.6 Serial Rate Control Register (SRC) ........................................................................................... 15.5 UART/SIO Interrupts ....................................................................................................................... 15.6 Operation of UART/SIO .................................................................................................................. 15.7 Operation of mode 0 ....................................................................................................................... 15.8 Operation of mode 1 ....................................................................................................................... 296 297 299 301 302 304 306 308 309 310 311 312 313 317 CHAPTER 16 BUZZER OUTPUT .................................................................................... 323 16.1 Overview of Buzzer Output ............................................................................................................. 16.2 Block Diagram of Buzzer Output .................................................................................................... 16.3 Structure of Buzzer Output ............................................................................................................. 16.3.1 Buzzer Register (BUZR) ............................................................................................................ 16.4 Program Example for Buzzer Output .............................................................................................. 324 326 327 328 329 CHAPTER 17 LCD CONTROLLER/DRIVER .................................................................. 331 17.1 Overview of LCD Controller/Driver ................................................................................................. 17.2 Block Diagram of LCD Controller/Driver ......................................................................................... 17.2.1 LCD Controller/Driver Internal Dividing Resistors (Device without Voltage Booster) ................ 17.2.2 LCD Controller/Driver External Dividing Resistors (Device without Booster) ............................ 17.2.3 LCD Controller/Driver Power Supply Voltage (Devices with Internal Voltage Booster) ............. 17.3 Structure of LCD Controller/Driver .................................................................................................. 17.3.1 LCD Controller Register (LCR1) ................................................................................................ 17.3.2 LCD Controller Register 2 (LCR2) ............................................................................................. 17.3.3 Display RAM .............................................................................................................................. 17.4 Operation of LCD Controller/Driver ................................................................................................. 17.4.1 Output Waveforms during LCD controller/Driver Operation (1/2 Duty Ratio) ............................ 17.4.2 Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) ........................... 17.4.3 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) ........................... 17.5 Program Example for LCD Controller/Driver .................................................................................. xiii 332 333 335 338 339 341 347 349 351 353 355 358 361 364 APPENDIX ......................................................................................................................... 367 APPENDIX A I/O MAP ............................................................................................................................. APPENDIX B Instructions ........................................................................................................................ B.1 Addressing ..................................................................................................................................... B.2 Special Instructions ........................................................................................................................ B.3 F2MC-8L Instructions ..................................................................................................................... B.4 Instruction Map ............................................................................................................................... B.5 Bit Manipulation Instructions (SETB, CLRB) .................................................................................. APPENDIX C Mask Options ..................................................................................................................... APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers .............. D.1 Programming One-time PROM Microcontroller with serial programmer ........................................ D.2 Programming One-time PROM Microcontroller parallel programmer ............................................ D.3 Programming EPROM for Piggyback/Evaluation Device ............................................................... APPENDIX E MB89480/480L Series Pin States ...................................................................................... 368 371 373 377 381 386 387 388 389 390 391 392 393 INDEX................................................................................................................................... 395 xiv Main changes in this edition Page Changes (For details, refer to main body.) - Changed the terms (Port data direction register →Port direction register) 8 Figure 1.4-1 Block Diagram of MB89480/480L Series is changed. (Changed the arrow directions of X1, X1A) 49 Note is added. 60 Note is deleted. 87 Table 4.1-1 Port Functions is changed. (The line of Port5 is added.) 187 Figure 9.4-3 PWC Pulse Width Control Register 2 (PCR2) Measured pulses are changed for the W2, W1, W0=110. (High level and rising to rising →Both edges) 334 ● Display RAM is changed. (Its contents are automatically read out to the segment outputs in sync with the timing of the selected common signal. → Its contents are automatically read in sync with the timing of the selected common signal, and output from the segment outputs at the same time as writing the display RAM.) 385 Table B.3-4 Other Instructions is changed. (The instructions are added in operation.) 388 Note is added. The vertical lines marked in the left side of the page show the changes. xv xvi CHAPTER 1 OVERVIEW This chapter describes the features and basic specifications of the MB89480/480L series. 1.1 Features of MB89480/480L Series 1.2 MB89480/480L Series Product Range 1.3 Differences between Products 1.4 Block Diagram of MB89480/480L Series 1.5 Pin Assignment 1.6 Package Dimensions 1.7 Pin Functions 1 CHAPTER 1 OVERVIEW 1.1 Features of MB89480/480L Series The MB89480/480L series has been developed as a general-purpose version of the F2MC-8L family consisting of 8-bit proprietary, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as 21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD controller/driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89480/480L series is designed suitable for LCD remote controller as well as in a wide range of applications for consumer product. ■ Features of MB89480/480L Series • Supports high speed operation Minimum instruction execution time: 0.32µs (source oscillation at 12.5MHz) • Package used QFP package and SH-DIP package for MB89P485/L, MB89485/L MDIP package and MQFP package for MB89PV480 • F2MC-8L CPU core Instructions set optimized for controller applications - Multiplication and division instructions - 16-bit operations - Bit-test branch instructions - Bit manipulation instructions, etc. • Six timers sub-systems - PWC timer (also usable as an interval timer) - PWM timer - 8/16-bit timer/counter 2 ch - 21-bit time-base timer - Watch prescaler • Programmable Pulse Generator (PPG) - 6-bit PPG with program -selectable pulse width and period • External interrupts - Edge detection (Selectable edge) : 4 channels - "L" level interrupt (Wake-up function): 8 channels • A/D converter (4 channels) - 10-bit successive approximation type • UART / SIO - Synchronous/asynchronous data transfer capable 2 • LCD controller/driver - max. 31 segments output × 4 commons - Booster for LCD driving (selected by mask option) • Buzzer - 7 frequency types are selectable by software • Low-power consumption modes - Stop mode (Oscillation stops to minimize the current dissipation.) - Sleep mode (The CPU stops to reduce the current dissipation to approx. 1/3 of normal.) - Watch mode (Operation except the watch prescaler stops to reduce the power dissipation to an extremely low level.) - Sub clock mode • Watchdog timer reset • I/O ports - Max 42 channels 3 CHAPTER 1 OVERVIEW 1.2 MB89480/480L Series Product Range The MB89480/480L series contains 3 different models. Table 1.2-1 lists the product range and Table 1.2-2 lists the common specifications. ■ MB89480/480L Series Product Range Table 1.2-1 MB89480/480L Series Product Range Model MB89485L MB89485 MB89P485L MB89P485 MB89PV480 Parameter Class ROM capacity Mass Production Products (mask ROM product) OTP 16K × 8 bits (internal ROM) 16K × 8 bits (internal PROM) Low-power consumption (standby modes) 1K × 8 bits Sleep mode, stop mode, watch mode, sub clock mode Process CMOS 2.2V to 3.6V 2.2V to 5.5V *: Use MBM27C256A as the external ROM. 4 32K × 8 bits (external ROM)* 512 × 8 bits RAM capacity Operating voltage Piggy-back 2.7V to 3.6V 3.5V to 5.5V 2.7V to 5.5V Table 1.2-2 Common Specifications for the MB89480/480L Series (1 / 2) Parameter Number of instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Minimum interrupt processing time : 136 instructions : 8-bit : 1 to 3 bytes : 1, 8, or 16-bit : 0.32µs/12.5 MHz : 2.88µs/12.5 MHz Ports I/O ports (CMOS) N-channel open drain I/O ports Output ports (N-channel open drain) Input port Total : 11 pins : 28 pins : 2 pins : 1 pins : 42 pins Time-base timer 21-bit Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Watchdog timer Reset period (167.8 ms to 335.5 ms) at 12.5 MHz Pulse width count timer 1 channel 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst, external) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) PWM timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64 tinst) 8-bit resolution PWM operation 6-bit programmable pulse generator Can generate square wave with programmable period. 8/16-bit timer/ counter 11, 12 Can be operated either as a 2-channel 8-bit timer/counter (Timer 11 and Timer 12, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8/16-bit timer/ counter 21, 22 Can be operated either as a 2-channel 8-bit timer/counter (Timer 21 and Timer 22, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable External Interrupt 4 independent channels (selectable edge, interrupt vector, request flag) 8 channels ("L" level interrupt) CPU functions Peripheral functions Specification 5 CHAPTER 1 OVERVIEW Table 1.2-2 Common Specifications for the MB89480/480L Series (2 / 2) Peripheral functions Parameter Specification A/D converter 10-bit resolution × 4 channels A/D conversion function (conversion time: 60 tinst) Supports repeated activation by internal clock. LCD controller/ driver Common output Segment output Bias power supply pins LCD display RAM size Internal dividing resistor ladder/ booster UART/SIO Synchronous/asynchronous data transfer capable (7 and 8 bits with parity bit; 8 and 9 bits without parity bit) Buzzer output 7 frequency types are selectable by software : 4 (max.) : 31 (max.) (Select resistor ladder) /26 (max.) (Select booster) :4 : 31 x 4 bits : selected by mask option Low-power consumption modes Sleep mode, stop mode, watch mode, sub clock mode Process CMOS *: tinst is instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. See "3.6.3 System Clock Control Register (SYCC)". 6 1.3 Differences between Products This section describes the differences between the 5 products in the MB89480/480L series and lists points to note in products selection. ■ Differences between Products and Points to Note for Product Selection Table 1.3-1 Package and corresponding products Classification MB89485/485L MB89P485/485L MB89PV480 DIP-64P-M01 O O X FPT-64P-M09 O O X MDP-64C-P02 X X O MQP-64P-P01 X X O Package O : Available X : Not Available For more information about each package, see section "1.6 Package Dimensions". • Memory space Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: - The stack area, etc., is set at the upper limit of the RAM. • Current dissipation - For the MB89PV480, add the current consumed by the EPROM mounted in the piggyback socket. - When operating at low speed, the current consumed by the one-time PROM products is greater than that for the mask ROM product. However, the current dissipation are roughly the same in sleep or stop mode. Reference: See "■ Electrical characteristics" in the data sheet for details. 7 CHAPTER 1 OVERVIEW 1.4 Block Diagram of MB89480/480L Series The block diagram of MB89480/480L series is shown in Figure 1.4-1. ■ Block Diagram of MB89480/480L Series Figure 1.4-1 Block Diagram of MB89480/480L Series CMOS I/O port Main clock oscillator X0 X1 Buzzer output P07/INT27/BUZ Clock control Sub-clock oscillator RST Reset circuit (Watchdog timer) 6-bit PPG P06/INT26/PPG 8-bit PWC timer External interrupt 2 (level) Port 0 X0A X1A P05/INT25/PWC 1 P04/INT24 * 8 1 P03/INT23 * 21-bit time-base timer P02/INT22 to P00/INT20 AVcc AVss 8-bit PWM timer P20/PWM 1 P24/C1/TO2 * P25/C0/EC2 *1 P26/V1/TO1 P27/V2/EC1 UART/SIO Port 2 *4 P21/SCK P22/SO P23/SI 8/16-bit timer/counter 21,22 10-bit A/D converter N-ch open-drain I/O port External interrupt 1 (edge) 8/16-bit timer/counter 11,12 2 4 4 Port 1 CMOS I/O port *4 Internal data bus Watch prescaler 4 4 1 P14/SEG27/AN0 * to 1 P17/SEG30/AN3 * P10/SEG23/INT10 to P13/SEG26/INT13 8 Booster 7 SEG1 to SEG7 2 2 P31/COM3 2 LCD controller/driver N-ch open-drain output port RAM (512 bytes/1 Kbyte) F2MC-8L CPU ROM (16 Kbytes/32 Kbyte) Other pins Vcc, Vss, MODE, C *2 32 × 4-bit display RAM (16 bytes) 16 N-ch open-drain I/O port P57 3 P56/SEG22 to P54/SEG20 4 P53/SEG19 to P50/SEG16 4 P47/SEG15 to P44/SEG12 P43/SEG11 to P40/SEG8 4 *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled. *2: For product other than MB89P485, C pin is N.C. pin. *3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0. *4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port. 8 to V3 V0/SEG0 *3 Port 4 and Port 5 *4 P30/COM2 Port 3 COM0 COM1 1.5 Pin Assignment Figure 1.5-1 to Figure 1.5-3 show the pin assignment for the MB89480/480L series. ■ DIP-64P-M01 Pin Assignment Figure 1.5-1 DIP-64P-M01 Pin Assignment (TOP VIEW) COM0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 92 91 90 89 88 87 86 85 84 83 82 81 80 79 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC A14 A13 A8 A9 A11 OE/Vpp A10 CE O8 O7 O6 O5 O4 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 *1 P16/SEG29/AN2 *1 P15/SEG28/AN1 *1 P14/SEG27/AN0 *1 RST MODE X1 X0 (DIP-64P-M01) (MDP-64C-P02) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 31 is N.C. pin. *3: Pin assignment on package top. Pin no. Pin symbol Pin no. Pin symbol Pin no. Pin symbol Pin no. 65 A15 73 A1 81 O6 89 Pin symbol A8 66 A12 74 A0 82 O7 90 A13 67 A7 75 O1 83 O8 91 A14 68 A6 76 O2 84 CE 92 Vcc 69 A5 77 O3 85 A10 70 A4 78 VSS 86 OE 71 A3 79 O4 87 A11 72 A2 80 O5 88 A9 N.C. : As connected internally, do not use. 9 CHAPTER 1 OVERVIEW ■ FPT-64P-M09 Pin Assignment Figure 1.5-2 FPT-64P-M09 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C Vss X0 X1 MODE RST *1 P14/SEG27/AN0 1 * P15/SEG28/AN1 *1 P16/SEG29/AN2 *1 P17/SEG30/AN3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 (FPT-64P-M09) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 23 is N.C. pin. 10 ■ MQP-64C-P01 Pin Assignment SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 Figure 1.5-3 MQP-64C-P01 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 (TOP VIEW) 77 76 75 74 73 72 71 70 69 85 86 87 88 89 90 91 92 93 P26/V1/TO1 V0/SEG0 1 P25/C0/EC2 * 1 P24/C1/TO2 * P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 1 P03/INT23 * 1 P04/INT24 * P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc 1 P17/SEG30/AN3 * *1 P14/SEG27/AN0 P15/SEG28/AN1 *1 P16/SEG29/AN2 (MQP-64C-P01) *1 C Vss X0 X1 MODE RST *2 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A 20 21 22 23 24 25 26 27 28 29 30 31 32 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 84 83 82 81 80 79 78 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 94 95 96 65 66 67 68 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: Pin 24 is N.C. pin. Pin assignment on package top Pin No. Pin Symbol Pin No. Pin Pin Pin No. Symbol Symbol Pin No. Pin Symbol 65 N.C. 73 A2 81 N.C. 89 OE 66 Vpp 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.: As connected internally, do not use. 11 CHAPTER 1 OVERVIEW 1.6 Package Dimensions Three different packages are available for the MB89480/480L series. Figure 1.6-1 to Figure 1.6-4 show the package dimensions. ■ DIP-64P-M01 Package Dimensions Figure 1.6-1 DIP-64P-M01 Package Dimensions 64-pin plastic SH-DIP Lead pitch 1.778mm(70mil) Package width × package length 17 × 58 mm Sealing method Plastic mold Mounting height 5.65 mm MAX (DIP-64P-M01) 64-pin plastic SH-DIP (DIP-64P-M01) Note: Pins width and pins thickness include plating thickness. +0.22 +.009 58.00 –0.55 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 +0.70 4.95 –0.20 +.028 .195 –.008 +0.50 0.70 –0.19 +.020 .028 –.007 0.27±0.10 (.011±.004) +0.20 3.30 –0.30 .130 +.008 –.012 +0.40 1.378 –0.20 .0543 C 12 +.016 –.008 2001 FUJITSU LIMITED D64001S-c-4-5 1.778(.0700) 0.47±0.10 (.019±.004) 19.05(.750) +0.50 0.25(.010) M 1.00 –0 .039 +.020 –.0 0~15° Dimensions in mm (inches). Note: The values in parentheses are reference values. ■ FPT-64P-M09 Package Dimensions Figure 1.6-2 FPT-64P-M09 Package Dimensions 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12 × 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LQFP64-12 × 12-0.65 (FPT-64P-M09) 64-pin plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8˚ 64 17 1 16 0.65(.026) C "A" 2003 FUJITSU LIMITED F64018S-c-3-5 0.32±0.05 (.013±.002) 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 13 CHAPTER 1 OVERVIEW ■ MDP-64C-P02 Package Dimensions Figure 1.6-3 MDP-64C-P02 Package Dimensions 64-pin ceramic MDIP Lead pitch 1.778mm (70mil) Row spacing 15.24mm (750mm) Motherboard material Ceramic Mounted packing material Plastic mold (MDP-64C-P02) 64-pin ceramic MDIP (MDP-64C-P02) 0°~9° 56.90±0.64 (2.240±.025) 15.24(.600) TYP INDEX AREA 2.54±0.25 (.100±.010) 33.02(1.300)REF 0.25±0.05 (.010±.002) 1.27±0.25 (.050±.010) 10.16(.400)MAX 1.778±0.25 (.070±.010) C 14 19.05±0.30 (.750±.012) 18.75±0.30 (.738±.012) 1994 FUJITSU LIMITED M64002SC-1-4 +0.13 0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) Dimensions in mm (inches). Note: The values in parentheses are reference values. ■ MQP-64C-P01 Package Dimensions Figure 1.6-4 MQP-64C-P01 Package Dimensions 64-pin ceramic MQFP Lead pitch 1.00 mm Lead shape Straight Motherboard material Ceramic Mounted package material Plastic (MQP-64C-P01) 64-pin ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP INDEX AREA 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) +0.40 1.20 –0.20 .047 1.00±0.25 (.039±.010) +.016 –.008 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 1.27±0.13 (.050±.005) 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 0.30(.012)TYP 7.62(.300)TYP 18.00(.709) TYP 0.40±0.10 (.016±.004) 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 9.48(.373)TYP 11.68(.460)TYP 0.50(.020)TYP C 1994 FUJITSU LIMITED M64004SC-1-3 10.82(.426) 0.15±0.05 MAX (.006±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 15 CHAPTER 1 OVERVIEW 1.7 Pin Functions Table 1.7-1 and Table 1.7-2 list the MB89480/480L series I/O pins and their functions. Table 1.7-3 lists the I/O circuit types. The letter in the I/O Circuit Type column of Table 1.7-1 refers to the letter in the Circuit Class column of Table 1.7-3. ■ Pin Functions Table 1.7-1 Pin Functions (1 / 3) Pin Number SHMQFP* DIP*1 QFP*3 2 MDIP*4 33 26 25 X0 34 27 26 X1 29 22 21 X0A I/O Circuit Type Function A Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. A Connection pins for a crystal or other oscillator of sub clock. An external clock can be connected to X0A (for low-speed: 32.768kHz). In this case, leave X1A open. 30 23 22 X1A 35 28 27 MODE B Input pins for setting the memory access mode. Connect directly to VSS. 36 29 28 RST C Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor and a hysteresis input. The pin outputs a "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. P00/INT20 to P02/INT22 D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input. D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/ counter 21, 22 input when booster is selected. 50 to 48 43 to 41 42 to 40 47 16 Pin Name 40 39 P03/INT23 46 39 38 P04/INT24 D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 output when booster is selected. 45 38 37 P05/INT25/ PWC D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and PWC input. 44 37 36 P06/INT26/ PPG D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and 6-bit PPG output. 43 36 35 P07/INT27/ BUZ D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input and buzzer output. Table 1.7-1 Pin Functions (2 / 3) Pin Number SHMQFP* DIP*1 QFP*3 2 MDIP*4 Pin Name P10/SEG23/ INT10 25 to 28 18 to 21 17 to 20 to P13/SEG26/ INT13 P14/SEG27/ AN0 37 to 40 30 to 33 29 to 32 to P17/SEG30/ AN3 I/O Circuit Type Function F/K General-purpose N-ch open-drain output port. A hysteresis input. The pin is shared with external interrupt 1 input and LCD segment output. G/K General-purpose N-ch open-drain output port. An analog input. The pin is shared with A/D converter input and LCD segment output. LCD segment output will be disabled when booster is selected. 51 44 43 P20/PWM E General-purpose CMOS I/O port. The pin is shared with PWM output. 52 45 44 P21/SCK E General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. 53 46 45 P22/SO E General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. 54 47 46 P23/SI D General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. H General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 21,22 output (It is redirected to P04/INT24 when booster is selected), and operates as a capacitor connecting pin when booster is selected. 55 48 47 P24/C1/TO2 56 49 48 P25/C0/EC2 F General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer/counter 21,22 input (It is redirected to P03/ INT23 when booster is selected), and operates as a capacitor connecting pin when booster is selected. 58 51 50 P26/V1/TO1 H General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 11,12 output, and LCD power driving pin. 59 52 51 P27/V2/EC1 F General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 11,12 input, and LCD power driving pin. 62 55 54 P30/COM2 I/K General-purpose N-ch open-drain output port. The pin is shared with the LCD common output 61 54 53 P31/COM3 I/K General-purpose N-ch open-drain output port. The pin is shared with the LCD common output 9 to 16 2 to 9 1 to 8 P40/SEG8 to P47/SEG15 H/K General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output. 9 to 15 P50/SEG16 to P56/ SEG22 H/K General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output. 16 P57 J General-purpose CMOS input port SEG1 to SEG7 K LCD segment output only pins COM0, COM1 K LCD common output only pins 17 to 23 10 to 16 24 2 to 8 1, 63 17 59 to 64, 58 to 64 1 58, 56 57, 55 17 CHAPTER 1 OVERVIEW Table 1.7-1 Pin Functions (3 / 3) Pin Number SHMQFP* DIP*1 QFP*3 2 MDIP*4 I/O Circuit Type 60 53 52 V3 — 57 50 49 V0/SEG0 —/K Function LCD driving power supply pin LCD driving power supply pin when booster is selected. LCD segment output only pin when booster is not selected. When MB89P485 is used, connect this pin to an external 0.1µF capacitor to ground. 31 24 23 C — 64 57 56 VCC — Power supply pin (+3V or +5V) 32 25 24 VSS — Power supply pin (GND) 41 34 33 AVCC — A/D converter power supply pin 42 35 34 AVSS — A/D converter power supply pin. Use at the same voltage level as VSS. *1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 *4: MDP-64C-P02 18 Pin Name When MB89485/L, MB89P485L or MB89PV480 is used, this pin will become a N.C. pin. Table 1.7-2 Pin Functions for the External EPROM Socket (MB89PV480 only) Pin Number Pin Name I/O 95 94 67 91 88 92 93 68 69 70 71 72 73 74 75 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 83 82 81 80 79 77 76 75 86 85 84 83 82 79 78 77 O8 O7 O6 O5 O4 O3 O2 O1 I Data input pins 65 76 81 90 65 76 81 90 N.C. — Internally connected pins. Always leave open. 65 66 Vpp O "H" level output pin 78 80 VSS O Power supply pin (GND) 84 87 CE O Chip enable pin for the EPROM. Outputs "H" in standby mode. 86 89 OE O Output enable pin for the EPROM. Always outputs "L". 92 96 VCC O Power supply pin for the EPROM MDIP*1 MQFP*2 91 90 66 87 85 88 89 67 68 69 70 71 72 73 74 Function *1: MDP-64C-P02 *2: MQP-64C-P01 19 CHAPTER 1 OVERVIEW Table 1.7-3 I/O Circuit Types (1 / 2) Circuit Class Circuit Remarks X1 (X1A) N-ch P-ch X0 (X0A) P-ch • N-ch • • A Main and sub clock circuit oscillation feedback resistor High-speed side = approx. 500kΩ Low-speed side = approx. 5MΩ Stop mode control signal • • Hysteresis input Pull-down resistor Approx. 50kΩ. (Available in MB89485/485L/ PV480 only) • • Pull-up resistor (P-ch) Approx. 50 kΩ. Hysteresis input • • • • CMOS output CMOS input Hysteresis input Selectable pull-up resistor Approx. 50 kΩ. • • • CMOS output CMOS input Selectable pull-up resistor Approx. 50 kΩ. B R P-ch C N-ch Pull-up resistor register R P-ch D N-ch Port Resources Pull-up Resistor register R P-ch E N-ch Port 20 Table 1.7-3 I/O Circuit Types (2 / 2) Circuit Class Circuit Remarks N-ch F Port • • • N-ch open-drain output CMOS input Hysteresis input • • • N-ch open-drain output CMOS input Analog input • • N-ch open-drain output CMOS input Resources G N-ch Port Analog input H N-ch Port I N-ch N-ch open-drain output J Port CMOS input P-ch N-ch K LCD segment output P-ch N-ch 21 CHAPTER 1 OVERVIEW 22 CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. 2.1 Notes on Handling Devices 23 CHAPTER 2 HANDLING DEVICES 2.1 Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. ■ Notes on Handling Devices • Take great care not to exceed the maximum rated voltage (prevent latch-up). Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-withstand voltage pins, or if voltage higher than the ratings is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the maximum ratings. Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. • Stabilizing supply voltage is important. A rapid fluctuation of VCC power supply voltage could cause malfunctions, even if it occurs within the operation assurance range of the voltage. The voltage must therefore be stabilized. As stabilization guidelines, it is recommended to stabilize the voltage so that VCC ripple fluctuations (peak to peak value) will be less than 10% of the standard VCC value at the commercial frequency (50Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. • Treatment of unused input pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. • Treatment of N.C. pins Be sure to leave (internally connected) N.C. pins open. • Treatment of power supply pins on microcontroller with A/D converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. • Precautions when using an external clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset and wake-up from stop mode. • MB89480/480L series C pin handling Table 2.1-1 lists the connection of C pin: Table 2.1-1 Connection of C pin C pin connection 24 MB89485/485L/P485L/PV480 N.C. pin MB89P485 This pin must be connected to an external 0.1µF capacitor to ground. CHAPTER 3 CPU This chapter describes the functions and operation of the CPU in MB89480/480L series. 3.1 Memory Space 3.2 Dedicated Registers 3.3 General-purpose Registers 3.4 Interrupts 3.5 Resets 3.6 Clocks 3.7 Standby Modes (Low-Power Consumption) 3.8 Memory Access Mode 25 CHAPTER 3 CPU 3.1 Memory Space The microcontrollers of the MB89480/480L series offer a memory space of 64 Kbytes. The memory space contains the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general-purpose registers and vector table. ■ Structure of Memory Space • I/O area (addresses: 0000H to 007FH) - Control registers and data registers for the internal peripheral functions are allocated in this area. - As the I/O area is allocated within the memory space, I/O can be accessed in the same way as memory. High-speed access using direct addressing is available. • RAM area - Internal static RAM is provided as an internal data area. - The internal RAM size differs between products. - Addresses between 80H and FFH support high-speed access using direct addressing. - Addresses between 100H and 1FFH can be used as the general-purpose register area. - The contents of RAM becomes undefined after a reset. • ROM area - Internal ROM is provided as an internal program area. - The internal ROM size differs between products. Set the memory access mode to internal ROM mode. - Addresses between FFC0H and FFFFH are used for the vector table, etc. 26 ■ Memory Map Figure 3.1-1 Memory Map MB89485/485L 0000H MB89P485/P485L 0080H RAM 0080H 0280H RAM RAM 0100H 0100H Generalpurpose registers I/O I/O 0080H 0100H 0200H 0000H 0000H I/O MB89PV480 0200H Generalpurpose registers 0200H Generalpurpose registers 0280H 0480H Vacant Vacant Vacant 8000H C000H FFC0H FFFFH C000H ROM FFC0H FFFFH ROM FFC0H FFFFH External ROM (32K) Vector table (reset, interrupt, vector call instruction) 27 CHAPTER 3 CPU 3.1.1 Special Purpose Areas In addition to the I/O area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. ■ General-purpose Register Area (Addresses: 0100H to 01FFH) • Provides auxiliary registers for 8-bit arithmetic operation and transfer. • Allocated to a part of the RAM area. Can also be used as normal RAM. • Using the area as general-purpose registers enables high-speed access by general-purpose register addressing using short instructions. Reference: See "3.2.2 Register Bank Pointer (RP)" and "3.3 General-purpose Registers" for details. ■ Vector Table Area (Addresses: FFC0H to FFFFH) • Used as the vector table for the vector call instruction, interrupts, and resets. • The vector table is allocated at the top of the ROM area. The start address of the corresponding processing routine is set as data at each vector table address. Table 3.1-1 lists the vector table addresses referenced by the vector call instruction, interrupts, and resets. Reference: See "3.4 Interrupts", "3.5 Resets", and "(6) CALLV #vct" in "B.2 Special Instructions" for details. 28 Table 3.1-1 Vector Table Vector call instruction Vector table address Upper Lower CALLV #0 FFC0H FFC1H CALLV #1 FFC2H CALLV #2 Vector call instruction Vector table address Upper Lower IRQF FFDCH FFDDH FFC3H IRQE FFDEH FFDFH FFC4H FFC5H IRQD FFE0H FFE1H CALLV #3 FFC6H FFC7H IRQC FFE2H FFE3H CALLV #4 FFC8H FFC9H IRQB FFE4H FFE5H CALLV #5 FFCAH FFCBH IRQA FFE6H FFE7H CALLV #6 FFCCH FFCDH IRQ9 FFE8H FFE9H CALLV #7 FFCEH FFCFH IRQ8 FFEAH FFEBH IRQ7 FFECH FFEDH IRQ6 FFEEH FFEFH IRQ5 FFF0H FFF1H IRQ4 FFF2H FFF3H IRQ3 FFF4H FFF5H IRQ2 FFF6H FFF7H IRQ1 FFF8H FFF9H IRQ0 FFFAH FFFBH Mode data — FFFDH Reset vector FFFEH FFFFH 29 CHAPTER 3 CPU 3.1.2 Storing 16-bit Data in Memory For 16-bit data and the stack, store the upper data in the lower memory address value. ■ Storing 16-bit Data in RAM When writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address. Handle reading of 16-bit data in the same way. Figure 3.1-2 shows how 16-bit data is stored in memory Figure 3.1-2 Storing 16-bit Data in Memory Before execution Memory After execution Memory MOVW 0081H,A 0080H 0080H 0081H A 1234H A 0082H 1234H 12H 0081H 34H 0082H 0083H 0083H ■ Storing 16-bit Operands The byte order applies when specifying a 16-bit operand in an instruction. Store the upper byte at the address following the operation code (instruction) and the lower byte at the next address. The byte ordering applies to both 16-bit immediate data and operands that specify a memory address. Figure 3.1-3 shows how 16-bit data is stored in an instruction. Figure 3.1-3 Storing of 16-bit Data in an Instruction [Example] MOV A,5678H MOVW A,#1234H ; Extended address ; 16-bit immediate data After assembly . . . XXX0H XXX2H XXX5H XXX8H XX XX 60 56 78 E4 12 34 XX ; Extended address ; 16-bit immediate data . . . ■ Storing 16-bit Data on Stack The same byte order applies when saving data of 16-bit register on the stack during an interrupt or similar. The upper byte is stored in the lower address. 30 3.2 Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. ■ Configuration of Dedicated Register The dedicated registers in the CPU consist of seven 16-bit registers. Some of these registers are also able to be used as 8-bit registers, using the lower 8 bits only. Figure 3.2-1 shows the configuration of the dedicated registers. Figure 3.2-1 Configuration of Dedicated Register Initial value 16 bits FFFDH PC XXXXH A XXXXH T XXXXH IX XXXXH EP XXXXH SP I-flag = 0, IL0, IL1 = 11B Other bits are undefined. RP CCR PS : Program counter A register for indicating the current instruction storage positions : Accumulator A temporary register for storing arithmetic operations or transfer : Temporary accumulator A register which performs arithmetic operations with the accumulator : Index register A register for indicating an index address : Extra pointer A pointer for indicating a memory address : Stack pointer A register for indicating the current stack location : Program status A register for storing a register bank pointer and condition code ■ Functions of Dedicated Register • Program counter (PC) The program counter is a 16-bit counter that indicates the memory address of the instruction currently being executed by the CPU. Instruction execution, interrupts, resets, and similar update the contents of the program counter. The initial value during a reset is the read address of the mode data (FFFDH). • Accumulator (A) The accumulator is a 16-bit arithmetic operation register. The accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator (T). The content of the accumulator can be treated as either word (16-bit) or byte (8-bit) data. Only the lower 8 bits (AL) of the accumulator are used for byte arithmetic operations or transfers. In this case, the upper 8 bits (AH) remain unchanged. The initial value after a reset is undefined. 31 CHAPTER 3 CPU • Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations. For byte-length arithmetic operations, only the lower 8 bits of the temporary accumulator (TL) are used and the upper 8 bits (TH) are not used. Transferring data to the accumulator (A) automatically transfers the previous content of the accumulator to the temporary accumulator. In this case also, a byte transfer leaves the upper 8 bits of the temporary accumulator (TH) unchanged. The initial value after a reset is undefined. • Index register (IX) The index register is a 16-bit register used to hold the index address. The index register is used in conjunction with a single byte offset value (-128 to +127). Adding the sign-extended offset value to the index address generates the memory address for data access. The initial value after a reset is undefined. • Extra pointer (EP) The extra pointer is a 16-bit register used to hold a memory address for data access. The initial value after a reset is undefined. • Stack pointer (SP) The stack pointer is a 16-bit register used to hold the address referenced during operations such as interrupts, subroutine calls, and the stack save and restore instructions. The value of the stack pointer during program execution is the address of the most recently saved data on the stack. The initial value after a reset is undefined. • Program status (PS) The program status is a 16-bit control register. The upper 8 bits contain the register bank pointer (RP) which points to the address of the current general-purpose register bank. The lower 8 bits contain the condition code register (CCR) which contains flags indicating the current CPU status. The two 8-bit registers which form the program status cannot be accessed independently (the program status can only be accessed by the MOVW A,PS and MOVW PS,A instructions). Refer to the F2MC-8L MB89600 series Programming Manual for details on using the dedicated registers. 32 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests. ■ Structure of Condition Code Register (CCR) Figure 3.2-2 Structure of Condition Code Register (CCR) RP PS CCR bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR initial value R4 R3 R2 R1 R0 — — — H I IL1 IL0 N Z V C X011XXXXB X: Undefined value Half-carry flag Interrupt enable flag Interrupt level bits Negative flag Zero flag Overflow flag Carry flag • Half-carry flag (H) This flag is set to "1" when a carry from bit3 to bit4 or a borrow from bit4 to bit3 occurs as a result of an arithmetic operation. It is cleared to "0" otherwise. As this flag is for the decimal adjustment instructions, do not use this flag in cases other than addition or subtraction. • Negative flag (N) This flag is set to "1" if the most significant bit (MSB) is set to "1" as a result of an arithmetic operation. It is cleared to "0" when the bit is set to "0". • Zero flag (Z) This flag is set to "1" when an arithmetic operation results is "0". It is cleared to "0" otherwise. • Overflow flag (V) This flag is set to "1" if the complement on 2 overflows as a result of an arithmetic operation. It is cleared to "0" if the overflow does not occur. • Carry flag (C) This flag is set to "1" when a carry from bit7 or borrow to bit7 occurs as a result of an arithmetic operation. It is cleared to "0" otherwise. Set to the shift-out value in case of a shift instruction. Figure 3.2-3 shows the change of the carry flag by a shift instruction. 33 CHAPTER 3 CPU Figure 3.2-3 Change of Carry Flag by Shift Instruction • Left shift (ROLC) • Right shift (RORC) bit7 bit0 bit7 bit0 C C Reference: The condition code register is a part of the program status (PS) and cannot be accessed independently. Note: In practice, the flag bits are rarely fetched and used directly. Instead, the bits are used indirectly by instructions such as branch instructions (such as BNZ) or the decimal adjustment instructions (DAA, DAS). The initial value of the flags after a reset is undefined. ■ Interrupt Acceptance Control Bit • Interrupt enable flag (I) Interrupt is enabled when this flag is set to "1" and the CPU accepts interrupt. Interrupt is prohibited when this flag is set to "0" and the CPU does not accept interrupt. The initial value after a reset is "0". Normal practice is to set the flag to "1" by the SETI instruction and clear to "0" by the CLRI instruction. • Interrupt level bits (IL1, IL0) These bits indicate the level of the interrupt currently being accepted by the CPU. The value is compared with the interrupt level setting registers (ILR1 to ILR4) which have a setting for each peripheral function interrupt request (IRQ0 to IRQF). Given that the interrupt enable flag is enabled (I = 1), the CPU only performs interrupt processing for interrupt requests with an interrupt level value that is less than the value of these bits. Table 3.2-1 lists the interrupt level priorities. The initial value after a reset is "11B". See "3.4 Interrupts" for details on interrupts. Table 3.2-1 Interrupt Level IL1 IL0 0 0 Interrupt level High to low High 1 34 0 1 1 0 2 1 1 3 Low (no interrupt) Note: The interrupt level bits (IL1, IL0) are normally "11B" when the CPU is not processing an interrupt (during main program execution). 35 CHAPTER 3 CPU 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. ■ Configuration of Register Bank Pointer (RP) Figure 3.2-4 shows the configuration of the register bank pointer (RP). Figure 3.2-4 Configuration of Register Bank Pointer (RP) RP bit15 14 13 R4 R3 R2 PS 12 R1 CCR 11 10 9 8 7 6 5 4 3 2 1 0 RP initial value R0 — — — H I IL1 IL0 N Z V C XXXXXXXXB X: Undefined value The register bank pointer indicates the address of the register bank currently in use. Figure 3.2-5 shows the relationship between the pointer contents and the actual address is based on the conversion rule. Figure 3.2-5 Rule for Conversion of Actual Addresses of General-purpose Register Area Upper bits of RP "0" "0" "0" "0" "0" "0" Lower operation codes "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 Generated addresses A15 A14 A13 A12 A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 • The register bank pointer points to the memory block (register bank) in the RAM area that is used for general-purpose registers. A total of 32 register banks are available. A register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer. Each register bank contains 8-bit general-purpose registers. Registers are specified by the lower 3 bits of the operation codes. • Using the register bank pointer, the addresses 0100H to 01FFH can be used as the general-purpose register area. However, the available area is limited on some products if internal RAM only is used. The initial value after a reset is undefined. Notes: • The register bank pointer is a part of the program status (PS) and cannot be accessed independently. • The register bank pointer must be set before using the general purpose register. 36 3.3 General-purpose Registers The general-purpose registers are a memory block made up of banks, with 8 × 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. The function permits the use of up to 32 banks, but the number of banks that can actually be used depends on how much RAM the device has. Register banks are valid for interrupt processing, vector call processing, and subroutine calls. ■ Configuration of General-purpose Registers • The general-purpose registers are 8 bits and located in the register banks of the general-purpose register area (in RAM). • One bank contains eight registers (R0 to R7) and up to a total of 32 banks. • The register bank currently in use is specified by the register bank pointer (RP). The lower three bits of the operation code specify general-purpose register 0 (R0) to general-purpose register 7 (R7). Figure 3.3-1 shows the configuration of general-purpose registers. Figure 3.3-1 Configuration of General-purpose Registers Lower 3 bits of the operation code 100H* 108H* 1F8H* 1FFH R0 000 R1 001 R2 010 R3 011 R4 100 R5 101 R6 110 R7 111 R0 000 : : R7 111 : : : : : : R0 000 : : R7 111 ⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ Bank 0 (RP=00000---B) Bank 1 (RP=00001---B) Bank 2 to Bank 30 ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ Bank 31 (RP=11111---B) ⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ 32 banks (RAM area) The number of banks is limited on available RAM size. *: The top address of a register bank = 0100H + 8 × (upper 5 bits of RP) 37 CHAPTER 3 CPU Reference: See "3.1.1 Special Purpose Areas" for the general-purpose register area available for each product. ■ Features of General-purpose Registers General-purpose registers have the following features: • RAM can be accessed at high-speed using short instructions (general-purpose register addressing). • Registers are grouped in blocks in the form of register banks. This simplifies the process of saving register contents and dividing registers by function. Dedicated register banks can be fixedly assigned for each interrupt processing or vector call (CALLV #0 to #7) processing routine by general-purpose register. For example, register bank 4 is used for interrupt 2. For example, a particular interrupt processing routine only uses a particular register bank which cannot be written to unintentionally by other routines. The interrupt processing routine only needs to specify its dedicated register bank at the start of the routine to effectively save the general-purpose registers in use prior to the interrupt. Therefore, saving the general-purpose registers to the stack or other memory location is not necessary. This allows high-speed interrupt handling while maintaining simplicity. Also, as an alternative to saving general-purpose registers in subroutine calls, register banks can be used to create reentrant programs (programs that do not use fixed addresses and can be entered more than once) usually made by the index register (IX). Note: If an interrupt processing routine changes the register bank pointer (RP), ensure that the program does not also change the interrupt level bits in the condition code register (CCR: IL1, IL0) when specifying the register bank. 38 3.4 Interrupts The MB89480/480L series has 15 interrupt request input corresponding to peripheral functions. An interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller. The CPU performs interrupt operation according to how the interrupt is accepted. The interrupt request wakes up from standby modes, and returns to the interrupt or normal operation. ■ Interrupt Requests from Peripheral Functions Table 3.4-1 lists the interrupt requests corresponding to the peripheral functions. On acceptance of an interrupt, execution branches to the interrupt processing routine. The contents of interrupt vector table address corresponding to the interrupt request specifies the branch destination address for the interrupt processing routine. An interrupt processing level can be set for each interrupt request in the interrupt level setting registers (ILR1, ILR2, ILR3, ILR4). Three levels are available. If an interrupt request with the same or lower level occurs during execution of an interrupt processing routine, the latter interrupt is not normally processed until the current interrupt processing routine completes. If interrupt request set the same level occur simultaneously, the highest priority is IRQ0. Table 3.4-1 Interrupt Request and Interrupt Vector Vector table address Upper Lower Bit names of the interrupt level setting register IRQ0 (External interrupt 1-1) FFFAH FFFBH L01, L00 IRQ1 (External interrupt 1-2) FFF8H FFF9H L11, L10 IRQ2 (External interrupt 1-3) FFF6H FFF7H L21, L20 IRQ3 (External interrupt 1-4) FFF4H FFF5H L31, L30 IRQ4 (External interrupt 2) FFF2H FFF3H L41, L40 IRQ5 (UART/SIO) FFF0H FFF1H L51, L50 IRQ6 (8/16-bit Timer ch.1) FFEEH FFEFH L61, L60 IRQ7 (8/16-bit Timer ch.2) FFECH FFEDH L71, L70 IRQ8 (A/D Converter) FFEAH FFEBH L81, L80 IRQ9 (PWM) FFE8H FFE9H L91, L90 IRQA (PWC) FFE6H FFE7H LA1, LA0 IRQB (Time-base timer) FFE4H FFE5H LB1, LB0 IRQC (Watch prescaler) FFE2H FFE3H LC1, LC0 IRQD (Vacancy) FFE0H FFE1H LD1, LD0 IRQE (Vacancy) FFDEH FFDFH LE1, LE0 IRQF (reserved for FLASH testing) FFDCH FFDDH LF1, LF0 Interrupt request Simultaneouslygenerated samelevel IRQ priority High Low 39 CHAPTER 3 CPU 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) The interrupt level setting registers (ILR1, ILR2, ILR3, ILR4) together contain 16 blocks of 2-bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interrupt’s corresponding 2bit data (interrupt level setting bits). ■ Configuration of Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) Figure 3.4-1 shows the configuration of the interrupt level setting registers. Figure 3.4-1 Configuration of Interrupt Level Setting Registers Register Address ILR1 007BH ILR2 007CH ILR3 007DH ILR4 007EH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value L31 L30 L21 L20 L11 L10 L01 L00 11111111B W W W W W W W W L71 L70 L61 L60 L51 L50 L41 L40 W W W W W W W W LB1 LB0 LA1 LA0 L91 L90 L81 L80 W W W W W W W W LF1 LF0 LE1 LE0 LD1 LD0 LC1 LC0 W W W W W W W W 11111111B 11111111B 11111111B W: Write only Two bits of the interrupt level setting registers are allocated to each interrupt request. The value of the interrupt level setting bits in these registers sets the interrupt priority (interrupt levels 1 to 3). The interrupt level setting bits are compared with the interrupt level bits in the condition code register (CCR: IL1, IL0). The CPU does not accept interrupt requests set to interrupt level 3. Table 3.4-2 shows the relationship between the interrupt level setting bits and the interrupt levels. Table 3.4-2 Relationship between Interrupt Level Setting Bits and Interrupt Levels 40 L01 to LF1 L00 to LF0 Request interrupt level 0 0 1 0 1 0 2 1 1 3 1 High to low High Low (no interrupt) Notes: • The interrupt level bits in the condition code register (CCR: IL1, IL0) are normally "11B" during main program execution. • As the IRL1, ILR2, ILR3 and ILR4 registers are write only, the bit manipulation instructions cannot be used. 41 CHAPTER 3 CPU 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine. ■ Interrupt Processing The procedure for interrupt operation is performed in the following order: interrupt source generated at peripheral function, set the interrupt request flag bit (request FF), discriminate the interrupt request enable bit (enable FF), the interrupt level (ILR1, ILR2, ILR3, ILR4 and CCR: IL1, IL0), simultaneously generated interrupt requests with the same level, then check the interrupt enable flag (CCR: I). Figure 3.4-2 shows the interrupt processing. 42 Figure 3.4-2 Interrupt Processing Internal bus Condition code register (CCR) Register file PS I IR IPLA Check 2 F MC-8L·CPU Comparator (5) Wake-up from stop mode Wake-up from sleep mode (6) RAM (1) Initialize peripheral · · · Enable FF AND YES Is an interrupt request present at the peripheral? Request FF (3) Is interrupt request output enabled for the peripheral? NO (4) Peripherals Level comparator (7) START NO IL (4) Interrupt controller (3) YES Check the interrupt priority level and transfer the level to the CPU (5) Compare the level with the IL bits in PS Is the level higher than IL? (2) Main program execution YES I-flag = 1? YES NO NO Interrupt processing routine Clear interrupt request (7) Restore PC and PS Execute interrupt processing RETI Save PC and PS to the stack (6) PC ← interrupt vector Update IL in PS 43 CHAPTER 3 CPU (1) After a reset, all interrupt requests are disabled. Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1, ILR2, ILR3, ILR4), and start peripheral function. The interrupt level can be set to 1, 2 or 3. Level 1 is the highest priority, followed by level 2. Setting level 3 disables the interrupt for that peripheral function. (2) Execute the main program (for multiple interrupts, execute the interrupt processing routine). (3) The interrupt request flag bit (request FF) for a peripheral function is set to "0" when the peripheral function generates an interrupt source. If the interrupt request enable bit for the peripheral function is set to "enable" (enable FF = 1), the peripheral function outputs the interrupt request to the interrupt controller. (4) The interrupt controller continuously monitors for interrupt requests from the peripheral functions and passes the interrupt level of the current interrupt request with the highest interrupt level to the CPU. The interrupt controller also evaluates the priority order if requests with the same level are present simultaneously. (5) If the interrupt level received by the CPU has a higher priority (a lower level value) than the level set in the interrupt level bits in the condition code register (CCR: IL1, IL0), the CPU checks the interrupt enable flag (CCR: I) and receives the interrupt if interrupts are enabled (CCR: I = 1). (6) The CPU saves the contents of the program counter (PC) and program status (PS) on the stack, reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt, updates the interrupt level bits in the condition code register (CCR: IL1, IL0) with the received interrupt level, and starts execution of the interrupt processing routine. (7) Finally, on execution of the RETI instruction, the CPU restores the program counter (PC) and program status (PS) values saved on the stack and resumes execution from the instruction following the last instruction executed before the interrupt. Notes: • As the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt request is received, the bit must be cleared by the program (normally, by writing "0" to the interrupt request flag bit) at interrupt processing routine. • If the interrupt request flag bit is cleared at the top of the interrupt processing routine, the peripheral function that has generated the interrupt becomes able to generate another interrupt during execution of the interrupt processing routine (resetting the interrupt request flag bit). However, the interrupts are not normally accepted until the current processing routine completes. Reference: An interrupt wakes up the CPU from standby mode (low-power consumption). See "3.7 Standby Modes (Low-Power Consumption)" for details. 44 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting registers for two or more interrupt requests from peripheral functions. ■ Multiple Interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority. Interrupt levels can be set in the range 1 to 3. However, the CPU does not accept interrupt requests set to interrupt level 3. • Example of multiple interrupts As an example of multiple interrupt processing, assume that an external interrupt has a higher priority than the timer interrupt. The timer interrupt is set to level 2 and the external interrupt is set to level 1. Figure 3.4-3 shows the processing when the external interrupt occurs during execution of timer interrupt processing. Figure 3.4-3 Example of Multiple Interrupts Main program Timer interrupt processing Interrupt level 2 (CCR:IL1, IL0 = 10B) External interrupt processing Interrupt level 1 (CCR:IL1, IL0 = 01B) Initialize peripheral (1) (3) External interrupt occurs Timer interrupt occurs (2) (4) External interrupt processing Halt Restart Restart main program (8) interrupt (6) Timer processing (7) Timer interrupt returns (5) External interrupt returns • During execution of timer interrupt processing, the interrupt level bits in the condition code register (CCR:IL1, IL0) are automatically set to the same value as the interrupt level setting registers (ILR1, ILR2, ILR3, ILR4) corresponding to the timer interrupt (level 2 in this example). If the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time, the interrupt processing has priority. • To temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag in the condition code register is set to "interrupts disabled" (CCR: I = 0) or the interrupt level bits (IL1, IL0) set to "00B". • On execution of the interrupt return instruction (RETI) at the completion of interrupt processing, the CPU restores the program counter (PC) and program status (PS) values saved on the stack and resumes execution of the interrupted program. Restoring the program status (PS) returns the condition code register (CCR) to the value prior to the interrupt. 45 CHAPTER 3 CPU 3.4.4 Interrupt Processing Time The time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing). The maximum time for this process is 30 instruction cycles. ■ Interrupt Processing Time When an interrupt request occurs, the time until the interrupt is accepted and the interrupt processing routine is executed includes the interrupt request sampling wait time and the interrupt handling time. • Interrupt request sampling wait time Whether or not an interrupt request has occurred is determined by sampling and testing for interrupt requests during the final cycle of each instruction. Therefore, the CPU is unable to identify interrupt requests during execution of an instruction. The longest wait time occurs when an interrupt request is generated immediately after starting execution of a DIVU instruction, which has the longest instruction cycles (21 instruction cycles). • Interrupt handling time Nine instruction cycles are required to perform the following preparation for interrupt processing after the CPU accepts an interrupt request: -Save the program counter (PC) and program status (PS). -Set the top address of the interrupt processing routine (the interrupt vector) in the PC. -Update the interrupt level bits (PS:CCR: IL1, IL0) in the program status (PS). Figure 3.4-4 shows the interrupt processing time. Figure 3.4-4 Interrupt Processing Time CPU operation Interrupt waiting time Execution of a normal instruction Interrupt handling Interrupt request sampling wait time Interrupt handling time (9 instruction cycles) Interrupt processing routine Interrupt request occurs : Final cycle of instruction. Interrupt requests are sampled at this timing. The total interrupt processing time of 21 + 9 = 30 instruction cycles is required if an interrupt request occurs immediately after starting execution of a DIVU instruction, which has the longest instruction cycles (21 instruction cycles). If, on the other hand, the program does not use the DIVU or MULU instructions, the maximum interrupt processing time is 6 + 9 = 15 instruction cycles. Note: The time of one instruction cycle changes with the clock mode and the main clock frequency as selected by the "speed-shift" (gear) function. See "3.6 Clocks" for detail 46 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. ■ Stack Operation during Interrupt Processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted. Figure 3.4-5 shows the stack operation at the start of interrupt processing. Figure 3.4-5 Stack Operation during Interrupt Processing Immediately before interrupt Immediately after interrupt Address Memory PS 0870H 027CH 027DH PC E000H 027EH 027FH SP 0280H 0280H 0281H ××H ××H ××H ××H ××H ××H Address Memory SP PS PC 027CH 0870H E000H 027CH 08H 027DH 70H 027EH E0H 027FH 00H 0280H ××H ××H 0281H ⎫ ⎬ PS ⎭ ⎫ ⎬ PC ⎭ ■ Stack Operation at Interrupt Return On execution of the interrupt return instruction (RETI) at the completion of interrupt processing, the CPU performs the opposite processing to interrupt initiation, restoring first the program status (PS) and then the program counter (PC) from the stack. This returns the PS and PC to their states immediately prior to the start of the interrupt. Note: The CPU does not automatically save the contents of the accumulator (A) or temporary accumulator (T) contents to the stack. Use the PUSHW and POPW instructions to save and restore A and T contents to and from the stack. 47 CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. ■ Stack Area for Interrupt Processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC). The stack area is also used by the PUSHW and POPW instructions to temporarily save and restore registers. • The stack area is located in RAM along with the data area. • Initializing the stack pointer (SP) to the top address of RAM and allocating data areas upwards from the bottom RAM address is recommended. Figure 3.4-6 shows the example of stack area setting. Figure 3.4-6 Stack Area for Interrupt Processing 0000H I/O 0080H Data area RAM 0100H Stack area 0200H Generalpurpose registers 0480H Recommended set value for SP (When the top address of RAM is 0480H.) Access prohibited ROM FFFFH Note: The stack area is used in the downward direction starting from a high address by functions such as interrupts, subroutine calls, and the PUSHW instruction. Instructions such as return instructions (RETI, RET) and the POPW instruction release stack area in the upward direction. Take care when the stack address is decreased by multiple interrupts or subroutine calls that the stack does not overlap the general-purpose register area or data areas containing other data. 48 3.5 Resets The MB89480/480L series supports the following four types of reset source: • External reset • Software reset • Watchdog reset • Power-on reset ■ Reset Source Table 3.5-1 Reset Source Reset source Reset conditions External reset Set the external reset pin to the "L" level. Software reset Write "0" to the software reset bit in the standby control register (STBC: RST). Watchdog reset Watchdog timer overflow Power-on reset Power is turned on. • External reset Inputting an "L" level to the external reset pin (RST) generates an external reset. Returning the reset pin to the "H" level disables the external reset. When power is turned on or for external resets in stop mode, the reset operation is performed after the oscillation stabilization wait time has passed and the external reset is released. The external reset pin can also function as a reset output pin. • Software reset Writing "0" to the software reset bit in the standby control register (STBC: RST) generates a fourinstruction cycle reset. The software reset does not wait for the oscillation stabilization wait time. • Watchdog reset The watchdog reset generates a four-instruction cycle reset if data is not written to the watchdog timer control register (WDTC) within a fixed time after the watchdog timer starts. The watchdog reset does not wait for the oscillation stabilization wait time. • Power-on reset Turning on the power generates a reset. The reset operation is performed after the oscillation stabilization wait time has passed. Note: Please select "There is power-on reset" and "Reset output and exist" by the mask option when you use the device without inputting external reset when the power supply is turned on. 49 CHAPTER 3 CPU ■ Main Clock Oscillation Stabilization Wait Time and the Reset Source Whether there will be an oscillation stabilization wait time depends on the operating mode when reset occurs. Following reset, operation always starts out in the normal main clock operating mode, regardless of the kind of reset it was, or the operating mode (standby mode) prior to reset. Therefore, if reset occurs while the main clock oscillator is stopped or in a stabilization wait time, the system will be in a "main clock oscillation stabilization wait reset" state, and a clock stabilization period will be provided. In software or watchdog reset, if the reset occurs while the device is in main clock mode, no stabilization time is provided. Table 3.5-2 shows the relationships between the reset sources and the main clock oscillation stabilization wait time, and reset (mode fetch) operations. Table 3.5-2 Reset Source and Oscillation Stabilization Wait Time Reset operation and main clock oscillation stabilization wait time Reset source Operating state Reset External reset * At power on, during stop mode After the main clock oscillation stabilization wait time, if the external reset is waked up, reset is operated. "L" level is output at RST pin during the main clock oscillation stabilization wait time. Main clock mode After 4-instruction-cycle reset occurs, reset is operated. "L" level is output at RST pin during 4-instruction-cycle. Sub clock mode Reset is operated after the main clock oscillation stabilization wait time. "L" level is output at RST pin during the main clock oscillation stabilization wait time. Software and watchdog reset Power-on reset Device enters main clock oscillation stabilization wait time at power on. Reset is operated after wait time ends. "L" level is output at RST pin during the main clock oscillation stabilization wait time. *: No oscillation stabilization wait time is required for external reset while main clock mode is operating. Reset is operated after external reset is waked up. 50 3.5.1 Reset Flag Register (RSFR) The reset flag register (RSFR) can be used to identify the reset generation sources when a reset occurs. ■ Reset Flag Register (RSFR) Figure 3.5-1 Reset Flag Register (RSFR) Address bit7 bit6 bit5 bit4 000EH PONR ERST WDOG SFTR R R R R bit3 — bit2 — SFTR 0 1 WDOG 0 1 ERST 0 1 PONR R — X : Readable/Writable : Undefined : Undefined value 0 1 bit1 — bit0 — Initial value XXXX----B Software reset flag Read — The reset source is a software reset. Write Operation is not affected Watchdog reset flag Read Write — The reset source is a watchdog reset. Operation is not affected External reset flag Read Write — Operation is The reset source is an external reset. not affected Power-on reset flat Read Write — Operation is The reset source is a power-on reset. not affected 51 CHAPTER 3 CPU Table 3.5-3 Explanation of the Functions of Each Bit of the Reset Flag Register (RSFR) Bit name Function • "1" is set when a power-on reset occurs. bit7 PONR: Power-on reset flag • "1" is set after power-on. This register is cleared to "0" by reading it. Writing to this bit has no effect. • "1" is set when an external reset occurs. bit6 ERST: External reset flag • "1" is set to the external reset flag while retaining each reset flag if each reset flag is set before the external reset flag is set. This register is cleared to "0" by reading it. Writing to this bit has no effect. • "1" is set when a watchdog reset occurs. bit5 WDOG: Watchdog reset flag • "1" is set to the watchdog reset flag while retaining each reset flag if each reset flag is set before the watchdog reset flag is set. This register is cleared to "0" by reading it. Writing to this bit has no effect. • "1" is set when a software reset occurs. bit4 SFTR: Software reset flag • "1" is set to the software reset flag while retaining each reset flag if each reset flag is set before the software reset flag is set. This register is cleared to "0" by reading it. Writing to this bit has no effect. bit3 to bit0 Undefined bits Values during a read operation are undefined. Writing to these bits has no effect. Note: Each reset source flag is set when each reset source occurs. When each reset source flag register is read, each bit of the reset source flag register is cleared. Thus, determine the reset source by reading this register using the initialization routine after the reset. 52 3.5.2 External Reset Pin Inputting an "L" level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an "L" level depending on internal reset sources. ■ Block Diagram of External Reset Pin The external reset pin (RST) is a hysteresis input type and N-ch open-drain output type with a pull-up resistor. Figure 3.5-2 shows the block diagram of the external reset pin. Figure 3.5-2 Block Diagram of External Reset Pin Pull-up resistor Approx. 50 kΩ/5.0V RST P-ch Internal reset source Pin N-ch Internal reset signal Input buffer ■ Functions of External Reset Pin Inputting an "L" level to the external reset pin (RST) generates an internal reset signal. The pin outputs an "L" level depending on internal reset sources or during the oscillation stabilization wait time due to an external reset. Software reset, watchdog reset, and power-on reset are classed as internal reset sources. Note: The external reset input accepts asynchronous with the internal clock. Therefore, initialization of the internal circuit requires a clock. Especially when an external clock is used, a clock is needed to be input at the reset. 53 CHAPTER 3 CPU 3.5.3 Reset Operation When the CPU wakes up from a reset, it reads the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization wait time has passed when power is turned on, or when the CPU wakes up from stop mode by a reset. If reset occurs during a write to RAM, the contents of the RAM address cannot be assured. ■ Overview of Reset Operation Figure 3.5-3 Reset Operation Flow Diagram External reset input Software reset Watchdog reset NO Reset active Power-on reset Initialize pin states based on the mode pin values Stop mode or during power on ? YES Regulator recovery time*1 Regulator recovery time*1 Power-on stabilization wait time*2 Oscillation stabilization wait in the reset state Oscillation stabilization wait in the reset state External reset disabled? NO YES Fetch mode data Mode fetch (reset operation) Fetch reset vector Normal operation (RUN state) Fetch the instruction code from the address indicated by the reset vector and execute the instruction. *1: The regulator recovery time is required for MB89P485 only. *2: The power-on stabilization wait time is required for MB89P485 and selectable for MB89485. 54 ■ Mode Pins The MB89480/480L series devices are single-chip mode devices. The mode pins (MODE) must be tied to VSS. Do not change the mode pin settings, even after the reset has been completed. ■ Mode Fetch When the CPU wakes up from a reset, it reads the mode data and reset vector from internal ROM. • Mode data (address: FFFDH) Always set the mode data to "00H" (single-chip mode). • Reset vector (address: FFFEH (upper), FFFFH (lower)) Contains the address where execution is to start after completion of the reset. The CPU starts executing instructions from the address contained in the reset vector. ■ Oscillation Stabilization Wait in Reset State The reset operation for a power-on reset or external reset in stop mode starts after the main clock oscillation stabilization wait time determined by the time-based timer. If the external reset input has not been released when the wait time completes, the reset operation does not start until the external reset is released. As the oscillation stabilization wait time is also required when an external clock is used, a reset requires that the external clock is input. The main clock oscillation stabilization wait time is made by the time-base timer. ■ Effect of Reset on RAM Contents The contents of RAM are unchanged before and after a reset other than power-on reset. If an external reset is input close to a write timing, however, the contents of the write address cannot be assured. For this reason, all RAM locations being used should be initialized following reset. ■ Regulator Recovery Time MB89P485 contains an on-chip voltage regulator for the internal 3V circuits. In low-power consumption mode or in the stop mode, the internal voltage regulator is turned off to minimize power dissipation. The regulator recovery time is the time for the internal voltage regulator to resume normal operation. The regulator recovery time is 20µs long, and it is required only in MB89P485. ■ Power-on Stabilization Time When power-on, the on-chip voltage regulator requires a stabilization time in additional to the recovery time. This additional wait time is called Power-on Stabilization Time. The external power supply voltage must reach the minimum operation voltage within the Power-on stabilization time. The Power-on Stabilization Time is required in MB89P485 and selectable by mask option in MB89485. It depends on the oscillating clock, and it is 217/FCH long (FCH is the main clock operating frequency). 55 CHAPTER 3 CPU Table 3.5-4 Regulator Recovery Time and Power-on Stabilization Time Regulator Recovery Time Power-on Stabilization Time MB89PV480 No No MB89P485 Yes Yes MB89485 No Selectable * MB89P485L No No MB89485L No No *: specify by mask option. 56 3.5.4 Pin States during Reset Reset initializes the pin states. ■ Pin States during Reset When a reset source occurs, with a few exceptions, all I/O pins (peripheral pins) go to the high-impedance state and the mode data is read from internal ROM. ■ Pin States after Reading Mode Data With a few exceptions, the I/O pins remain in the high-impedance state immediately after reading the mode data. Note: For devices connected to pins that change to high-impedance state when a reset source occurs, take care that malfunction does not occur due to the change in the pin states. Reference: See "APPENDIX E MB89480/480L Series Pin States" for pin states at times other than a reset. 57 CHAPTER 3 CPU 3.6 Clocks The clock generator is provided with an oscillator. By connecting with external resonator, circuits generate the high speed main clock source oscillation. Alternatively, externally generated clock inputs can be used. Clock controller controls the speed and supply of the clock signals according to the clock and standby modes. ■ Clock Supply Map Oscillation of a clock and its supply to the CPU and peripheral circuit (peripheral functions) are controlled by the clock controller. As shown in the map, operating clocks fed to the CPU and peripheral circuits are affected by main clock/sub clock switching (clock mode), main clock speed switching (speed-shift function), and standby modes (sleep/stop/watch). Divided output derived from the free-run counter clocked by the peripheral circuit clock is supplied to the peripheral functions. Divided output from the time-base timer and watch prescaler are also supplied to the peripheral functions. These clocks, however, are not affected by the speed-shift function, etc. The time-base timer is clocked by the output of the main clock source oscillator after it is fed through a divide-by-n circuit, and the watch prescaler is clocked directly by the sub clock oscillator. Figure 3.6-1 shows the clock supply map. 58 Figure 3.6-1 Clock Supply Map Peripheral functions X0 Pin X1 Pin Main clock FCH oscillator Time-base timer *1 *1, 3 Watchdog timer Baud Rate Generator 3 *2 UART/SIO Clock controller SCK Pin Oscillation control Clock mode Stop mode *1,3 Speed-shift Function Divide-by-2 LCD Divide-by-4 Divide-by-8 Divide-by-32 4 *2 8-bit PWM timer Sleep/stop/watch Oscillation stabilization wait 6 *2 8/16-bit timer/counter ch.1 Supply to the CPU Clock mode EC1 Pin Divide-by-2 Stop / watch Supply to peripheral circuit *2 6 8/16-bit timer/counter ch.2 EC2 Pin *4 Continuous activation *2 3 Pin Pin 4 *1 Free-run counter X0A X1A 10-bit A/D converter BUZZER Sub clock FCL oscillator *1, 3 8-bit PWC Timer Watch prescaler *2 PWC Pin 4 *2 6-bit PPG *1 Oscillation stabilization wait control *1: Not affected by clock mode, speed-shift function, etc. *2: Operating speed, etc., affected by clock mode or speed-shift function. *3: Stops operating if its clock source (main or sub clock oscillator) stops. *4: Time-base timer output can be selected in continuous A/D conversion operating mode. In other modes, clock speed is affected by clock mode and speed-shift function. 59 CHAPTER 3 CPU 3.6.1 Clock Generator Enable and stop of the main clock oscillations is controlled by normal mode and stop mode. ■ Clock Generator • Crystal or ceramic resonator Connect as shown in Figure 3.6-2 Figure 3.6-2 Connection Example for a Crystal or Ceramic Resonator When single clock is used When dual clock is used MB89480 series X0A X1 X0 Sub clock oscillator Main clock oscillator Sub clock oscillator Main clock oscillator X1A MB89480 series X0A X1 X0 X1A Open R 32.768 kHz C C C C C C • External clock Connect the external clock to the X0/X0A pin and leave X1/X1A pin open, as shown in Figure 3.6-3 Figure 3.6-3 Connection Example for External Clock When dual clock is used MB89480 series X0A X1 Open MB89480 series X1A Open 32.768 kHz 60 Sub clock oscillator Main clock oscillator Sub clock oscillator Main clock oscillator X0 When single clock is used X0 X1 Open X0A X1A Open 3.6.2 Clock Controller The clock controller contains the following seven blocks: • Main clock oscillator • Sub clock oscillator • System clock selector • Clock controller • Oscillation stabilization wait time selector • System clock control register (SYCC) • Standby control register (STBC) ■ Block Diagram of Clock Controller Figure 3.6-4 shows the block diagram of the clock controller. Figure 3.6-4 Block Diagram of Clock Controller STBC STBC STP SLP SPL RST TMD — — — Pin state Stop mode Sleep mode Watch mode Clock for watch prescaler Sub clock control Enable Sub clock oscillator Divide-by-4 Divide-by-8 Divide-by-32 From watch prescaler 214/FCH 217/FCH 218/FCH 215/FCL Clock controller Main clock oscillator Selector Prescaler Divide-by-2 Divide-by-2 Enable Selector Main clock control From time-base timer Clock for time-base timer System clock selector CPU operation clock Clock supply to peripheral circuits Stop of clock supply to the CPU Oscillation stabilization wait time selector 2 Clock select SYCC SYCC SCM — WT2 WT1 WT0 SCS CS1 CS0 FCH : Main clock oscillation FCL : Sub clock oscillation tinst : Instruction cycle 61 CHAPTER 3 CPU ● Main clock oscillator The main clock oscillator is stopped in main-stop mode. ● Sub clock oscillator The sub clock oscillator is normally running except in sub-stop mode. ● System clock selector The system clock selector selects one of four clocks: one of four divided clocks derived from the main clock master clock oscillator. ● Clock controller This circuit controls the supply of operating clocks to the CPU and peripheral circuits, selecting the clock based on the active mode: normal (RUN), or standby (sleep/stop/watch) mode. Supply of the clock to the CPU is stopped until the clock supply stop signal in the oscillation stabilization wait time selector is released. ● Oscillation stabilization wait time selector This register selector selects a wait time from among three main clock oscillation stabilization wait times timed by the time-base timer oscillation stabilization time as the clock supply stop signal to the CPU based on the normal mode, standby mode and reset. ● System clock control register (SYCC) The SYCC register is used to select the speed of the main clock, and the main clock oscillation stabilization wait time, and to check the status of these selections. ● Standby control register (STBC) This register controls from normal operation (RUN) to the standby modes, sets the pin states in the stop mode, and initiates software reset. 62 3.6.3 System Clock Control Register (SYCC) The system clock control register (SYCC) controls main clock speed selection, and oscillation stabilization wait time selection. ■ Configuration of System Clock Control Register (SYCC) Figure 3.6-5 Configuration of System Clock Control Register (SYCC) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0007H SCM — WT2 WT1 WT0 SCS CS1 CS0 X-1MM100B R/W R/W R/W R/W R/W R/W R Initial value Main clock speed select bits CS1 CS0 0 0 64/FCH (5.12µs) 0 1 16/FCH (1.28 µs) 1 0 8/FCH (0.64µs) 1 1 4/FCH (0.32µs) SCS 0 1 Instruction cycle (FCH = 12.5 MHz) System clock select bit Selects sub clock (32 kHz) mode Selects main clock mode Oscillation stabilization wait time select bit WT1 WT0 R/W R — X M FCH : Readable/Writable : Read only : Undefined : Undefined value : Per option selection : Initial value Main clock oscillation stabilization wait time per selected time-base timer output (FCH = 12.5MHz) 0 0 Reserved 0 1 Approx. 214/FCH (Approx. 1.3 ms) 1 0 Approx. 217/FCH (Approx. 10.5 ms) 1 1 Approx. 218/FCH (Approx. 21.0 ms) WT2 1 SCM 0 1 Reserved bit Always write "1" System clock monitor bit Sub clock (main clock stopped or in oscillation stabilization wait time) Main clock : Main clock oscillation (12.5MHz) 63 CHAPTER 3 CPU Table 3.6-1 Functions of Bits in System Clock Control Register (SYCC) Bit name Function bit7 SCM: System clock monitor bit • Indicates the current clock mode (operating clock). • "0" indicates sub clock mode (main clock is stopped or in the oscillation stabilization wait time to go to main clock mode). • "1" indicates main clock mode. This is a read only bit. Writing to it has no effect on operation. bit6 Undefined bit • The read value is undefined. • Writing to this bit has no effect on operation. bit5 WT2: Reserved bit This bit must always write to "1". bit4, bit3 WT1, WT0: Oscillation stabilization wait time select bits • Select main clock oscillation stabilization wait time. • Selected wait time applies if external interrupt causes "wake up" from main-stop mode (transition to normal (run) mode). Initial value of these bits is an option selection. Accordingly, when an oscillation stabilization wait time is provided at reset, the wait time will be as selected by the option. Note: These bits should not be changed at the same time switching from sub clock to main clock (SCS = 1 -> 0). Before changing the bits, first check the SCM bit to verify that the device is not currently in the main clock oscillation stabilization wait time. bit2 SCS: System clock select bit • Specifies the clock mode. • Writing "0" to this bit sets the CPU changing from main clock to sub clock mode. • Writing "1" to this bit causes the device to go from sub clock to main clock mode after the oscillation stabilization wait time set by WT1 and WT0 bits. bit1, bit0 CS1, CS0: Main clock speed select bits • These bits select the clock speed for the main clock mode. • Four different speeds can be set for CPU and peripheral function operating clocks (speed-shift function). However, the clock for the time-base timer is not affected by these bits. ■ Instruction Cycle (tinst) Instruction cycle (minimum execution time) can be selected as 1/4, 1/8, 1/16, or 1/64 of the main clock. The selection is made by main clock speed select bits (CS1 and CS0) of the SYCC register. With main clock mode, and the highest clock speed selected (SYCC: SCS = 1, CS1 = 1, CS0 = 1), and with a main clock source oscillation (FCH) of 12.5 MHz, the instruction cycle is 4/FCH = approximately 0.32 µs. 64 3.6.4 Clock Modes The clock modes consist of main clock mode and sub clock mode. In the main clock mode, the primary operating clock is provided by the main clock. The speed of the main clock is selected by switching between one of four clocks obtained by dividing the output of the main clock source oscillation (speed-shift function). In the sub clock mode, the main clock source oscillation is stopped, and operating clocks are provided solely by the sub clock. ■ Clock Mode Operating States Table 3.6-2 Clock Mode Operating States Clock Oscillator Main clock speed SYCC register (SYCC: CS1, CS0) Clock mode Fast (1.1) (1.0) Main clock mode (0.1) (0.0) Slow Standby mode RUN Sleep Oscillate Stop Stop RUN Sleep Oscillate Stop Stop RUN Sleep Oscillate Stop Stop RUN Sleep Oscillate Stop Stop RUN Sleep Sub clock mode – Main Stop FCH/8 Oscillate Stop FCH/16 Oscillate Stop FCH/64 Oscillate Oscillate Stop Stop Stop CPU FCH/4 Oscillate Stop Watch Mode Sub Operating clocks for various sections Oscillate Stop Non-reset event triggering Time-base Watch except Peripherals timer prescaler standby mode FCH/2 Stop IRQ FCL Stop Stop FCH/2 FCH/8 Stop Stop FCH/2 FCH/16 Stop FCH/2 FCH/64 Stop FCL/2 FCL Stop Stop Stop FCL Stop* Stop* External interrupt IRQ FCL Stop External interrupt IRQ FCL Stop External interrupt IRQ FCL FCL/2 Stop FCH/4 External interrupt IRQ External interrupt External or watch interrupt FCH: Main clock source oscillation (12.5MHz) FCL: Sub clock source oscillation * : Since the time-base timer runs on the main clock, it stops in sub clock mode. Reference: See "3.7 Standby Modes (Low-Power Consumption)" for a description of the standby modes. 65 CHAPTER 3 CPU ■ Speed-Shift (Main Clock Speed-switching) Function One of four main clock frequencies can be selected by writing the appropriate values between "00B" and "11B" to main clock speed select bits of the system clock control register (SYCC: CS1, CS0). The switch-selected clock signal provides the operating clock for the CPU and peripheral circuits. The time-base timer and watch prescaler, however, is not affected by the speed-shift (gear) function. A slower main clock speed reduces power dissipation. ■ Operation of Main Clock Mode The main clock and the sub clock oscillators both run in "main-run" mode (the normal main clock operating mode). The watch prescaler runs on the sub clock, but the CPU, time-base timer, and other peripheral circuits all use the main clock. When operating in main clock mode, the speed-shift function can be used to select a main clock speed. This selection affects all circuits that are clocked by the main clock except for the time-base timer. By specifying a standby mode, you can also go to "main-sleep", or "main-stop" mode. When the device is reset, the system always starts out in "main-run" mode regardless of how the reset was initiated (Each operating mode exited by reset). ● Changing from main clock mode to sub clock mode Writing "0" to the system clock select bit in the system clock control register (SYCC:SCS) changes the CPU from the main clock to sub clock mode. You can confirm which clock is currently being used by reading the system clock monitor bit of the same register (SYCC: SCM). Note: If you go to sub clock mode immediately after power on, write the software so as to provide a longer sub clock oscillation stabilization wait time than that defined by the watch prescaler. ■ Operation of Sub clock Mode In the normal sub clock operating mode ("sub-run" mode), the system runs on the sub clock only. The main clock oscillator is stopped. Using the low speed sub clock reduces power dissipation. Other than the time-base timer, all functions operate the same in sub clock mode as they do in main clock mode. If standby mode is specified while operating in sub clock mode, the device goes to "sub-sleep", "sub-stop", or "watch" mode. ● Returning to main clock mode from sub clock mode Writing "1" to the system clock select bit in the system clock control register (SYCC:SCS) returns to main clock mode from sub clock mode. Operation from the main clock, however, will not start after the main clock oscillation stabilization wait time has passed. One of four wait times can be selected by setting the oscillation stabilization wait time select bits of the system clock control register (SYCC: WT1, WT0). 66 Note: Do not change the oscillation stabilization wait time select bits (SYCC: WT1, WT0) at the same time you switch from sub clock to main clock mode (SYCC: SCS = 1), or during the oscillation stabilization wait time. Always check the system clock monitor bit to verify that the main clock is the active operating clock (SYCC: SCM = 1) before changing these bits. The device always enters the main clock oscillation stabilization wait time when the system is returned from sub clock mode to main clock mode. 67 CHAPTER 3 CPU 3.6.5 Oscillation Stabilization Wait Time When the system transitions to main-run mode from a state in which the main clock is stopped (such as at power-on, in main-stop and sub clock modes, etc.), a main clock oscillation stabilization time is required before operation starts. Similarly, a sub clock oscillation stabilization wait time is required when exiting the substop mode, because the sub clock oscillation is stopped in that mode. ■ Oscillation Stabilization Wait Time After starting, ceramic, crystal, and other resonators typically require the time between several milliseconds and several tens of milliseconds to stabilize at their fixed oscillation frequency. Therefore, operation of the CPU and other functions is disabled when oscillation first starts and no clock signal is supplied to the CPU until the oscillation stabilization wait time has passed and the oscillation has sufficiently stabilized. The time required for oscillation to stabilize depends on the resonator type (crystal, ceramic, etc.) connected to the clock generator. Consequently, it is necessary to select an oscillation stabilization wait time that matches the type of oscillator being used. Figure 3.6-6 shows the operation of an oscillator immediately after starting oscillation. Figure 3.6-6 Operation of Oscillator immediately after Starting Oscillation Resonator oscillation time Oscillation starts Oscillation stabilization wait time Normal operation (wake-up from stop mode or reset operation) Oscillation stabilizes ■ Regulator Recovery Time MB89P485 contains an on-chip voltage regulator for the internal 3V circuits. In power-down mode or in the stop mode, the internal voltage regulator stops the operation to minimize power dissipation. The regulator recovery time is the time for the internal voltage regulator to resume normal operation. The regulator recovery time is 20µs. ■ Power-on Stabilization Wait Time When power-on, the on-chip voltage regulator requires a stabilization time in addition to the oscillation stabilization time. This additional wait time is called power-on stabilization time. The external power supply voltage must reach the minimum operation voltage within the power-on stabilization time. The power-on stabilization time is required for MB89P485 and selectable by mask option in MB89485. 217/FCH of the power-on stabilization wait time is required (FCH is the main clock operating frequency). ■ Stabilization Wait Time for Different Operation for Different Product Table 3.6-3 shows the operating states while waiting for the oscillation stabilization and the wait time in each operation time. 68 Table 3.6-3 Operating States while Waiting Oscillation Stabilization Time Operating Mode Oscillation Oscillation stabilization wait time Started Power-on stabilization wait time Started Regulator recovery time CPU Time-based Watchdog Other Timer timer Peripherals Operating Operating Operating Halted Halted Halted Halted Pin Cancel Method Hold* - Halted *: During an oscillation stabilization wait time initiated by an external interrupt, pins go to their states immediately before stop mode. Pins go to their reset states during an oscillation stabilization wait time initiated by a reset. (See "3.5.3 Reset Operation".) Table 3.6-4 Wait Time for Each Action Operation Power-on reset MB89485 MB89P485 MB89PV480/P485L/485L Regulator recovery wait Power-on stabilization wait time + Power-on stab. wait Oscillation stabilization wait time (Selectable) + Oscillation time + Oscillation time stabilization wait time stabilization wait time External reset in stop/sub/clock Oscillation stabilization wait mode or external interrupt trigger time recovery from main stop mode Regulator recovery wait time + Oscillation stabilization wait time Oscillation stabilization wait time ■ Main Clock Oscillation Stabilization Wait Time When first starting operation in main clock mode after a state in which the main clock oscillation is stopped, an oscillation wait time for main clock is required. This wait time starts when the counter of the time-base timer starts counting up from its cleared state, and ends when the count overflows at the specified bit. ● Oscillation stabilization wait time during operation A time must be selected for the oscillation stabilization wait time when an external interrupt takes the system from main-stop mode back to main-run mode, or when going from sub clock to main clock mode. One of four possible wait times can be selected, using the oscillation stabilization wait time select bits of the system clock control register (SYCC: WT1, WT0). ● Oscillation stabilization wait time at reset The oscillation stabilization wait time at reset (the initial values of WT1 and WT0) is selected as an option setting. Table 3.6-5 shows the relationship between the conditions in which main clock mode operation is started and oscillation stabilization wait time. 69 CHAPTER 3 CPU Table 3.6-5 Main Clock Mode Startup Conditions vs. Oscillation Stabilization Wait Time During sub clock mode Main clock mode startup conditions Oscillation stabilization wait time selection At power-on Exit from main-stop mode Software reset External reset and watchdog External reset reset Option setting External interrupt Transition from sub clock to main clock mode (SYCC: SCS*1=1) SYCC: WT1, WT0*2 *1: System clock select bit of system clock control register *2: Oscillation stabilization wait time select bits of system clock control register ■ Sub clock Oscillation Stabilization Wait Time When an external interrupt returns the system from sub-stop (sub clock oscillation stopped) to sub-run mode (thus starting the sub clock oscillation), a set sub clock oscillation stabilization wait time is provided. (This set wait time is equal to 215/FCL, where FCL is the sub clock oscillator frequency.) The sub clock oscillation stabilization wait time is also entered at power-on. Therefore, if you go to sub clock mode after power on, you should insert a software wait, to provide a longer wait time before starting this transition than the sub clock oscillation stabilization wait time. The sub clock oscillation stabilization wait time starts when the watch prescaler starts counting up from the cleared state, and ends when it overflows. 70 3.7 Standby Modes (Low-Power Consumption) The standby modes consist of sleep mode, stop mode, and watch mode. From both main clock and sub clock modes, standby modes are changed to sleep mode, stop mode, or watch mode by setting the standby control register (STBC). From main clock mode, you can go only to sleep or stop mode, but from sub clock mode you can go any of the three standby modes. Standby mode reduces the power dissipation by stopping the operation of the CPU and peripheral functions. This section describes the relationship between standby mode and clock mode, and the operation of various sections during standby mode. ■ Standby Modes Watch mode reduce the power dissipation by lowering the frequencies of the clocks that run the CPU and peripheral circuits. You can do this by switching from main clock to sub clock mode, or by using the speedshift function to select a lower main clock frequency. Standby modes reduce the power dissipation, however, by stopping the clock signal supply to the CPU via clock controller (sleep mode), by stopping the clock signal supply to the CPU and peripheral circuits (watch mode), or by stopping the source oscillation itself (stop mode). ● Main-sleep Mode Main-sleep mode stops the operation of CPU and watchdog timer, but operate the peripheral functions except watch prescaler by the main clock. (Certain functions can still run on the sub clock.) ● Sub-sleep Mode Sub-sleep mode stops the operation of main clock oscillator, CPU, watchdog timer, and time-base timer, but operate the peripheral functions on the sub clock. ● Main-stop Mode Main-stop mode stops the operation of CPU and peripheral functions. The main clock oscillation is stopped, but the sub clock oscillation keeps running. Everything is shut down except external interrupt servicing, watch prescaler count operation, and some functions that operate from the sub clock. ● Sub-stop Mode Sub-stop mode stops all chip functions except the external interrupt, and stops the main clock and sub clock oscillations. ● Watch Mode You can only go to watch mode from the sub clock mode. All functions are shut down except the watch prescaler (watch interrupt), external interrupts, and some functions that operate from the sub clock. 71 CHAPTER 3 CPU Note: Even when the main clock is stopped, as it is in the main-stop and watch modes, as long as the sub clock oscillation is still operating, some buzzer outputs and LCD controller/drivers will still operate. See "CHAPTER 16 BUZZER OUTPUT", "CHAPTER 17 LCD CONTROLLER/DRIVER", and the clock supply map provided in "3.6 Clocks" for details. 72 3.7.1 Operating States in Standby Modes This section describes the operating states of the CPU and peripheral functions in standby modes. ■ Operating States in Standby Modes Table 3.7-1 Operating States of the CPU and Peripheral Functions in Standby Modes Main clock mode Sub clock mode Function RUN Sleep Stop RUN Sleep Stop Watch Main clock Operating Operating Stop Stop Stop Stop Stop Sub clock Operating Operating Operating Operating Operating Stop Operating Operating Stop Stop Operating Stop Stop Stop Operating Hold Hold Operating Hold Hold Hold I/O ports Operating Hold Hold Operating Hold Hold Hold Instructions Peripheral functions CPU ROM RAM Watch prescaler Operating Operating Operating Operating Operating Stop Operating Time-base timer Operating Operating Stop Stop Stop Stop Stop 8/16-bit timer/counter 11, 12, 21, 22 Operating Operating Stop Operating Operating Stop Stop UART/SIO Operating Operating Stop Operating Operating Stop Stop *1 8-bit PWM timers Operating Operating Stop Operating Operating Stop Stop A/D converter Operating Operating Stop Operating Operating Stop Stop External Interrupts 1 and 2 Operating Operating Operating Operating Operating Operating Operating 6-bit PPG Operating Operating Stop Operating Operating Stop Stop Watchdog timer Operating Stop Stop Operating*2 Stop Stop Stop PWC timer Operating Operating Stop Operating Operating Stop Stop 6-bit PPG Operating Operating Stop Operating Operating Stop Stop A/D convertor Operating Operating Stop Operating Operating Stop Stop BUZZER Operating Operating Operating*2 Operating*2 Operating*2 Stop LCD controller/driver Operating Operating Operating Operating Operating *3 *3 *3 Operating*2 *4 Stop Operating*3 *1: Watch prescaler counts but does not generate watch interrupts. *2: Can be operated if watch prescaler output is selected as its operating clock. *3: If the sub clock is selected as the operating clock, in watch mode, LCD controller/driver operation must be enabled. *4: In devices with on-chip voltage boosters (MB89480 series), the voltage booster stops operating. ● Pin States in Standby Mode Almost all I/O pins will either keep the state they were placed in by the pin state control bit of the standby control register (STBC: SPL) just prior to going to the stop or watch mode, or will go to the high impedance state. This is true regardless of the clock mode. Reference: See "APPENDIX E MB89480/480L Series Pin States" for pin states in a standby mode. 73 CHAPTER 3 CPU 3.7.2 Sleep Mode This section describes the operations of sleep mode. ■ Operation of Sleep Mode ● Changing to sleep mode Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents and RAM contents, at their values immediately prior to entering sleep mode. However, peripheral functions except the watchdog timer continue to operate. Writing "1" to the sleep bit in the standby control register (STBC: SLP) changes the CPU to sleep mode. If an interrupt request is generated when "1" is written to the SLP bit, the write to the bit is ignored, and the CPU continues the instruction execution without change to sleep mode. (The CPU does not change to sleep mode even after completion of the interrupt processing.) ● Wake-up from sleep mode A reset or an interrupt from a peripheral function wakes up the CPU from sleep mode. The reset operation also initializes the pin states. If an interrupt request with an interrupt level higher than "11B" occurs from a peripheral function or an external interrupt circuit during sleep mode, the CPU wakes up from sleep mode, regardless of the interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1 and IL0) in the CPU. The normal interrupt operation is performed after wake-up from sleep mode. If the interrupt request is accepted, the CPU executes interrupt processing. If the interrupt request is not accepted, the CPU continues execution from the subsequent instruction following the instruction executed immediately before changing to sleep mode. 74 3.7.3 Stop Mode This section describes the operations of stop mode. ■ Operation of Stop Mode ● Changing to stop mode Stop mode stops the source oscillation. Most functions stop while maintaining all register and RAM contents at their value immediately before changing to stop mode. If the system is in main clock mode, the main clock oscillation stops. Except the external interrupt circuit, however, the CPU and other peripheral functions stop operating. Writing "1" to the stop bit in the standby control register (STBC: STP) changes the CPU to stop mode. At this time, external pin states are held if the pin state specification bit (STBC: SPL) is "0". If SPL is "1", external pins go to the high-impedance state. (Pins with the pull-up resistor go to the "H" level.) If an interrupt request is generated when "1" is written to the STP bit, the write to the bit is ignored, and the CPU continues the instruction execution without change to stop mode. (The CPU does not change to stop mode even after completion of the interrupt processing.) Prohibit interrupt request output from the time-base timer (TBTC: TBIE = 0) before changing to stop mode in main clock mode as necessary. ● Wake-up from stop mode A reset or an external interrupt wakes up the CPU from stop mode. If reset occurs during stop mode on a product, the reset operation starts after the main clock oscillation stabilization wait time. The reset initializes pin states. If an interrupt request with an interrupt level higher than "11B" occurs from an external interrupt circuit during stop mode, the CPU wakes up from stop mode, regardless of the interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1, IL0) in the CPU. Only external interrupt requests can occur during stop mode because peripheral functions are stopped. After wake-up from stop mode, the normal interrupt operation is performed after the oscillation stabilization wait time has passed. If the interrupt request is accepted, the CPU executes interrupt processing. If the interrupt request is not accepted, the CPU continues execution from the subsequent instruction following the instruction executed immediately before entering stop mode. Some peripheral functions restart from mid-operation when the CPU wakes up from stop mode by an external interrupt. The first interval time from the interval timer function, for example, is undefined. Therefore, initialize all peripheral functions after wake-up from stop mode. Note: Only interrupt requests from external interrupt circuits can be used to wake up from stop mode by an interrupt. 75 CHAPTER 3 CPU 3.7.4 Watch Mode This section describes the operations of watch mode. ■ Operation of watch Mode ● Changing to watch mode Watch mode stops the clocks that clock the CPU and the main peripheral circuit. You can go to watch mode only from sub clock mode (in which the main clock oscillation is stopped). Prior to going to watch mode, registers are saved and the contents of RAM are held. All chip functions other than watch prescaler (watch interrupt), external interrupt circuit, and certain functions that run off of the sub clock stop. Accordingly, data can be held with extremely small power dissipation. Writing "1" to the watch bit in the standby control register (STBC: TMD) changes the CPU to watch mode. This can be done, however, only when the system clock select bit of the system clock control register (SYCC: SCS) is "0" (sub clock mode active). When you go to watch mode, external pin states are held if the pin state specification bit in the standby control register (STBC: SPL) is "0". If SPL is "1", external pins go the high-impedance state. (Pins with a pull-up resistor (optional) go to the "H" level) If an interrupt request is generated when "1" is written to the TMD bit, the write to the bit is ignored, and the CPU continues the instruction execution without change to watch mode. (The CPU does not change to watch mode even after completion of the interrupt processing.) ● Wake-up from watch mode A reset, a watch interrupt or an external interrupt wakes up CPU from watch mode. If a reset occurs during watch mode on a product with power-on reset, the reset operation starts after the main clock oscillation stabilization wait time. Products without power-on reset, do not require for the oscillation stabilization wait time after a reset in watch mode. The reset initializes pin states. If an interrupt request with an interrupt level higher than "11B" occurs from a watch prescaler or an external interrupt circuit during watch mode, the CPU wakes up from watch mode, regardless of the interrupt enable flag (CCR:I) and interrupt level bits (CCR: IL1, IL0) in the CPU. Only watch interrupt or external interrupt requests can occur during watch mode because most of the peripheral functions except watch prescaler are stopped. After wake-up from stop mode, the normal interrupt operation is performed. If the interrupt request is accepted, the CPU executes interrupt processing. If the interrupt request is not accepted, the CPU continues execution from the subsequent instruction following the instruction executed immediately before entering watch mode. Some peripheral functions restart from mid-operation when the CPU wakes up from watch mode. The first interval time from the interval timer function, for example, is undefined. Therefore, initialize all peripheral functions after wake-up from watch mode. 76 3.7.5 Standby Control Register (STBC) The standby control register (STBC) controls the changing to sleep mode or stop mode, sets the pin states in stop mode, and initiates software resets. ■ Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC) Address 0008H bit7 STP R/W bit6 SLP R/W bit5 SPL R/W bit4 RST W bit3 TMD R/W bit2 — bit1 — bit0 — Initial value 00010---B Watch bit TMD 0 1 RST 0 1 SPL 0 1 SLP 0 1 STP 0 R/W W — : Readable/Writable : Write only : Undefined : Initial value 1 Valid only in sub clock mode (SYCC: SCS = 0) Read Reading always returns "0". — Write No effect on operation Changing to watch mode Software reset bit Read Write Generates a reset signal for four instruction cycles. — Reading always returns "1". No effect on operation Pin state specification bit Read Write External pins hold their states prior to entering stop mode or watch mode. External pins go to high-impedance state on entering stop mode or watch mode. Sleep bit Read Reading always returns "0". — Write No effect on operation Change to sleep mode. Stop bit Read Reading always returns "0". — Write No effect on operation Change to stop mode. 77 CHAPTER 3 CPU Table 3.7-2 Functions of Bits in Standby Control Register (STBC) Bit name Function bit7 STP: Stop bit Sets the CPU changing to stop mode. Writing "1" to this bit sets the CPU changing to stop mode. Writing "0" to this bit has no effect on operation. Reading this bit always returns "0". bit6 SLP: Sleep bit Sets the CPU changing to sleep mode. Writing "1" to this bit sets the CPU changing to sleep mode. Writing "0" to this bit has no effect on operation. Reading this bit always returns "0". bit5 SPL: Pin state specification bit Specifies the states of the external pins during stop mode and watch mode. Writing "1" to this bit specifies that external pins to go to high impedance state on entering stop mode or watch mode. (Pin with a pull-up resistor go to "H" level.) Writing "0" to this bit specifies that external pin hold their states (levels) on changing to stop mode or watch mode. Reading this bit always returns "0". bit4 RST: Software reset bit Specifies a software reset. Writing "1" to this bit has no effect on operation. Writing "0" to this bit generates an internal reset source for four instruction cycles. Reading this bit always returns "1". bit3 TMD: Watch bit Sets the CPU changing to watch mode. A write to this bit is valid only in sub clock mode (SYCC:SCS=0). Writing "1" to this bit sets the CPU changing to watch mode. Writing "0" to this bit has no effect on operation. Reading this bit always returns "0". bit2 to bit0 Undefined bits 78 The read value is undefined. Writing to these bits has no effect on operation. 3.7.6 State Transition Diagram This section shows the state transition diagram. ■ State Transition Diagram Figure 3.7-2 State Transition Diagram Power on Power-on reset [1] Oscillation stabilization wait reset state Reset state [2] [7] [3] [3] Main clock mode [1] [4] Main-stop mode Main-RUN state Main-sleep mode [2] [5] [8] [6] Main clock oscillation stabilization wait [4] [6] [7] Sub clock mode <8> <6> <5> <7> Sub-RUN main clock oscillation stabilization wait Sub clock oscillation stabilization wait Sub-stop mode <4> [5] <1> Sub-RUN state Sub-sleep mode <2> [8] <3> <9> <11> <10> Watch state 79 CHAPTER 3 CPU ● Changing to/wake-up from clock modes (non-standby modes) Table 3.7-3 Changing to/wake-up from Clock Modes State transition Conditions/events required to transition Changing to normal main clock mode state (main-RUN) after power-on reset [1] Main clock oscillation stabilization wait time complete. (Timebase timer output) [2] Wake up from reset input. Reset in main-RUN state [3] Have external, software, or watchdog reset. Changing from main-RUN state to sub-RUN state [4] SYCC: SCS=0* Changing from sub-RUN state back to main-RUN state [5] SYCC: SCS=1 [6] Main clock oscillation stabilization wait time complete. (Can be checked by looking at SYCC: SCM) [7] Have external, software, or watchdog reset. Reset in sub-RUN state [8] Have external, software, or watchdog reset. SYCC: System clock control register *: Changing to sub-RUN state at power-on occurs after the sub clock oscillation stabilization wait time complete. ● Changing to/wake-up from standby modes Table 3.7-4 Changing to/wake-up from Standby Modes Conditions/events required to transition State transition Main clock mode Sub clock mode Changing to sleep mode [1] STBC: SLP = 1 <1> STBC: SLP = 1 Wake-up from sleep mode [2] Interrupt (any) [3] External reset <2> Interrupt (any) <3> External reset Changing to stop mode [4] STBC: STP = 1 <4> STBC: STP = 1 Wake-up from stop mode [5] External interrupt [6] Main clock oscillation stabilization wait time completes. (Have time-base timer output.) [7] External reset [8] External reset (during oscillation stabilization wait time) <5> External interrupt <6> Sub clock oscillation stabilization wait time ends.(Have watch prescaler output.) <7> External reset <8> External reset (during oscillation stabilization wait time) Changing to watch mode _ <9> STBC: TMD = 1* Wake-up from watch mode _ <10> External or watch interrupt <11> External reset STBC: Standby control register *: Changing to watch mode is possible only from sub-RUN state (SYCC: SCS = 0). Neither software nor watchdog resets can occur during standby mode because the CPU and watchdog timer are both stopped. 80 3.7.7 Notes on Using Standby Modes The CPU does not change to a standby mode if an interrupt request occurs from a peripheral function when a standby mode is set in the standby control register (STBC). Also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted. ■ Changing to a Standby Mode and Interrupts If an interrupt request with an interrupt level higher than "11B" occurs from a peripheral function to the CPU, writing "1" to the stop bit (STP), or sleep bit (SLP) in the standby control register (STBC) is ignored. Therefore, the CPU does not change to a standby mode. (The CPU also does not change to the standby mode after completing interrupt processing.) This does not depend on whether or not the CPU accepts the interrupt. Even if the CPU is currently performing interrupt processing, the interrupt request flag bit is cleared and, if no other interrupt request is present, the device can change to the standby mode. ■ Wake-up from Standby Mode by Interrupt If an interrupt request with an interrupt level higher than "11B" occurs from a peripheral function or others during sleep or stop mode, the CPU wakes up from a standby mode. This does not depend on whether or not the CPU accepts the interrupt. After wake-up from a standby mode, the CPU performs the normal interrupt operations. If the level set in the interrupt level setting register (ILR1 to ILR4) corresponding to the interrupt request is higher than the interrupt level bits in the condition code register (CCR: IL1, IL0), and if the interrupt enable flag is enabled (CCR: I = 1), the CPU branches to the interrupt processing routine. If the interrupt is not accepted, operation restarts from the instruction following the instruction that activated a standby mode. To prevent control from branching to an interrupt processing routine after wake-up, take measures such as disabling interrupts before setting a standby mode. ■ Notes on Setting Standby Mode When setting the standby control register (STBC) to go to a standby mode, make the settings in accordance with Table 3.7-5. The order of precedence as to which mode will be activated if more than one bit is set to "1" is "stop" mode, and "sleep" mode. Other factors being equal, it is best to set "1" for just one bit. Table 3.7-5 Low-Power Consumption Mode Settings Using Standby Control Register STBC register Mode STP (bit7) SLP (bit6) 0 0 Normal 0 1 Sleep 1 0 Stop 81 CHAPTER 3 CPU ■ Oscillation Stabilization Wait Time As the oscillator that provides the source oscillation is stopped during stop mode in both main clock mode, a wait time is required for oscillation to stabilize after the oscillator restarts operation. In main clock mode, the main clock oscillation stabilization wait time is selected from one of three possible wait times defined by the time-base timer. In main clock mode, if the interval time set for the time-base timer is less than the oscillation stabilization wait time, the time-base timer generates an interval timer interrupt request before the end of the oscillation stabilization wait time. To prevent this, disable the interrupt request output for the time-base timer (TBTC: TBIE = 0) before changing to stop mode in main clock mode as necessary. 82 3.8 Memory Access Mode In the MB89480/480L series, the memory access mode is the only single-chip mode. ■ Single-chip Mode In single-chip mode, the device uses internal RAM and ROM only. Therefore, the CPU can access no areas other than the internal I/O area, RAM area, and ROM area (internal access). ■ Mode Pins (MODE) Always set the mode pins, MODE, to VSS. At reset, reads the mode data and reset vector from internal ROM. Do not change the mode pin settings, even after completion of the reset (i.e. during normal operation). Table 3.8-1 lists the mode pin settings. Table 3.8-1 Mode Pin Setting Pin state Description MODE VSS Reads the mode data and reset vector from internal ROM. VCC Settings prohibited ■ Mode Data Always set the mode data in internal ROM to "00H" to select single-chip mode. Figure 3.8-1 Configuration of Mode Data Address bit7 FFFDH bit6 bit5 bit4 bit3 bit2 bit1 bit0 Data 00H Operation Selects single-chip mode. Other than 00H Reserved. Do not set this value. 83 CHAPTER 3 CPU ■ Operation for Selecting the Memory Access Mode Selecting mode other than single-chip mode is not possible. Table 3.8-2 shows the mode pin and mode data. Table 3.8-2 Mode pin and Mode Data Memory Access Mode Mode Pin (MODE) Mode Data Single-chip Mode Vss 00H Other modes Setting prohibited Setting prohibited Figure 3.8-2 shows the operation for selecting the memory access mode. Figure 3.8-2 Operation for selecting the Memory Access Mode Reset Generated Check mode pin Setting Prohibited Mode pin (MODE) Other Vss Single-chip mode The mode data is read from internal ROM I/O pin at high impedance Wait for reset to be released (external reset or oscillation stabilization wait time) Reset in progress ? Fetch mode data and reset vector from internal ROM Mode fetch Check mode data Setting Prohibited Other Mode data ? Single-chip mode (00H) Set I/O pin functions for program execution (RUN) state Set I/O state of each pin in the port data direction registers (DDR), etc. I/O pins can be used as ports 84 CHAPTER 4 I/O PORTS This chapter describes the functions and operation of the I/O ports. 4.1 Overview of I/O Ports 4.2 Port 0 4.3 Port 1 4.4 Port 2 4.5 Port 3 4.6 Port 4 4.7 Port 5 4.8 Program Example for I/O Ports 85 CHAPTER 4 I/O PORTS 4.1 Overview of I/O Ports The I/O ports consist of 42 pins general-purpose I/O ports. The ports also serve as peripherals (I/O pins of peripheral functions). ■ Functions of I/O Port The functions of the I/O ports are to output data from the CPU via the I/O pins and to fetch signals input to the I/O pins into the CPU. Input and output are performed via the port data registers (PDR). Also, for certain ports the direction of each I/O pin can be individually set to either input or output for each bit by the port direction register (DDR). The following lists the functions of each port and the peripheral with which the ports also serve as. • Port 0: General-purpose I/O port. Also serves as peripherals (INT20 to INT27, PWC, PPG, BUZ, EC2*1, TO2*1) • Port 1: General-purpose I/O port. Also serves as peripherals (AN0 to AN3, INT10 to INT13, SEG23 to SEG26, SEG27 to SEG30*2) • Port 2: General-purpose I/O port. Also serves as peripherals (C0, C1, V1, V2, PWM, SCK, SO, SI, EC1, TO1, EC2*2, TO2*2) • Port 3: General-purpose N-channel open-drain output port. Also serves as peripherals (COM2, COM3) • Port 4: General-purpose I/O port. Also serves as peripherals (SEG8 to SEG15) • Port 5: General-purpose I/O port. Also serves as peripherals (except for P57, which is general-purpose input port only) (SEG16 to SEG22) *1: When built-in booster is selected. *2: When built-in booster is not selected. 86 Table 4.1-1 lists the functions of each port and Table 4.1-2 lists the registers for each port. Table 4.1-1 Port Functions Port Pin name Input type Port0 P00/INT20 to P07/INT27/ BUZ CMOS (resource hysteresis) P10/SEG23/ INT10 Port1 to P17/SEG30/ AN3 N-ch open-drain (resource hysteresis/ analog) Output type Function General purpose I/O CMOS port push-pull External Interrupts 2 N-ch opendrain bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P07 P06 P05 P04 P03 P02 P01 P00 INT27 INT26 INT25 INT24 INT23 INT22 INT21 INT20 Peripherals BUZ PPG PWC TO2*1 EC2*1 — — — General purpose I/O port P17 P16 P15 P14 P13 P12 P11 P10 LCD segment output SEG30*2 SEG29*2 SEG28*2 SEG27*2 SEG26 SEG25 SEG24 SEG23 Analog input/ External interrupts 1 AN3 AN2 AN1 AN0 P27 P26 P25 P24 P23 P22 P21 P20 LCD driver V2 V1 C0*1 C1*1 — — — — Peripherals EC1 TO1 EC2*2 TO2*2 SI SO SCK PWM P31 P30 P20/PWM to P23/SI CMOS (resource hysteresis) P24/C1/TO2 to P27/V2/EC1 N-ch open-drain (resource hysteresis) N-ch opendrain P30/COM2 to P31/COM3 — — — — — — — N-ch opendrain Output only port Port3 LCD common output — — — — — — Port4 P40/SEG8 to P47/SEG15 CMOS N-ch opendrain General purpose I/O port P47 P46 P45 P44 P43 P42 LCD segment output SEG15 SEG14 SEG13 Port5 P50/SEG22 to P57 CMOS N-ch opendrain General purpose I/O port P57*3 P56 P55 — SEG22 SEG21 Port2 CMOS General purpose push-pull I/O port INT13 INT12 INT11 INT10 LCD segment output COM3 COM2 P41 P40 SEG12 SEG11 SEG10 SEG9 SEG8 P54 P53 P52 P51 P50 SEG20 SEG19 SEG18 SEG17 SEG16 *1: When built-in booster is selected. *2: When built-in booster is not selected. *3: Input only Table 4.1-2 Port Registers Register Read/Write Port 0 data register (PDR0) R/W Port 0 data direction register (DDR0) W* Port 0 pull-up resistor control register (PURC0) R/W Port 1 data register (PDR1) R/W Port 1 data direction register (DDR1) W* A/D input enable register (ADER) R/W Port 2 data register (PDR2) R/W Port 2 data direction register (DDR2) R/W Port 2 pull-up resistor control register (PURC2) R/W Port 3 data register (PDR3) R/W Port 4 data register (PDR4) R/W Port 5 data register (PDR5) R/W * : Bit manipulation instructions cannot be used on DDR0, DDR1. R/W: Readable/Writable R: Read only W: Write only X: Undefined value -: Unused pin Address 0000H 0001H 0070H 0002H 0003H 0030H 0004H 0006H 0072H 000CH 0010H 0012H Initial value XXXXXXXXB 00000000B 11111111B XXXXXXXXB 00000000B 1111----B 00000000B 00000000B ----1111B ------11B 11111111B X1111111B 87 CHAPTER 4 I/O PORTS 4.2 Port 0 Port 0 is general-purpose I/O port that also serves as resource signal I/O pins. This section principally describes the port functions when operating as general-purpose I/O ports. The section describes the structure, pins, the pin block diagram, and the registers for port 0. ■ Structure of Port 0 Port 0 consists of four components respectively. • General-purpose I/O pins (P00/INT20 to P07/INT27/BUZ) • Port 0 data register (PDR0) • Port 0 data direction register (DDR0) • Port 0 pull-up resistor control register (PURC0) ■ Pins of Port 0 Port 0 consists of eight I/O pins of a CMOS input and CMOS output type. As the I/O pins are shared with resource I/O, the pins cannot be used as general-purpose I/O ports when the corresponding resource is used. Table 4.2-1 lists the port 0 pins. Table 4.2-1 Pins of Port 0 Shared peripheral Port Pin name Circuit type Input Output P00/ INT20 INT20 - P01/INT21 INT21 - P02/INT22 INT22 - INT23 - INT24 - P05/INT25/PWC INT25 , PWC - P06/INT26/PPG INT26 PPG P07/INT27/BUZ INT27 BUZ P03/INT23* Port0 P04/INT24* I/O type Function P00 to P07 Generalpurpose I/O Input Output CMOS hysteresis CMOS * : If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 88 D ■ Block Diagram of Pins of Port 0 Figure 4.2-1 Block Diagram of Pins of Port 0 To external interrupt circuit External interrupt input enable INT20 to ITN27 To peripheral input PDR (Port data register) Pull-up resistor Approx. 50 kΩ Stop, watch mode Internal data bus PDR read Pull-up resistor Peripheral control register output Peripheral output enable P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin DDR N-ch DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: When a port is used as a normal input port, peripheral circuit operation that uses the same pins must be disabled. ■ Port 0 Registers • The port 0 registers consist of PDR0, DDR0 and PURC0. • Each bit in these registers has a one-to-one relationship with port 0 pin respectively. Table 4.2-2 shows the correspondence between pins and registers for port 0. Table 4.2-2 Correspondence between Pins and Registers for Port 0 Port Correspondence between register bits and pins PDR0, DDR0, PURC0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00 Port0 89 CHAPTER 4 I/O PORTS 4.2.1 Port 0 Registers (PDR0, DDR0, RDR0) This section describes the port 0 registers. ■ Functions of Port 0 Register ● Port 0 data register (PDR0) The PDR0 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state. Reference: For bit manipulation instructions (SETB and CLRB), since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. ● Port 0 direction register (DDR0) The DDR0 register sets the direction (input or output) for each pin (bit). Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets the pin as an input port. Note: As the DDR0 register is write only, the bit manipulation instructions (SETB and CLRB) cannot be used. ● Settings as peripheral output To use a peripheral that has an output pin, set the peripheral output enable bit for that pin to the "enable" state. As can be seen in the block diagram, the peripheral has precedence over the general-purpose port for use of the output pin. Once the peripheral output is enabled, the states set in the PDR0 and DDR0 registers are no longer valid, and do not affect the data output by the peripheral, or the enabling of the output. ● Settings as a peripheral input To use a peripheral that has a port 0 pin as an input pin, set that pin as an input port. The output latch data for that pin will no longer be valid. 90 Table 4.2-3 lists the functions of the port 0 registers. Table 4.2-3 Functions of Port 0 Registers Register Data Read Write 0 Pin state is the "L" level. Sets "0" to the output latch. Outputs an "L" level to the pin if the pin functions as an output port. Pin state is the "H" level. Sets "1" to the output latch. Outputs an "H" level to the pin if the pin functions as an output port. Port 0 data register (PDR0) 1 Port 0 data direction register (DDR0) Read/ Write Address Initial value R/W 0000H XXXXXXXXB W 0001H 00000000B Disables output transistor and sets the pin as an input pin. 0 Reading is not permitted (write only). Enables output transistor and sets the pin as output pin. 1 R/W: Readable/Writable W : Write only X : Undefined value ● Port 0 pull-up resistor control register (PURC0) By using pull-up resistor control register (PURC0), it is possible to turn on/off pull-up resistor. When pull-up resistor is selected in pull-up resistor control register, the states of these pins in stop mode (SPL=1) are in "H" level (pull-up state) rather than high impedance. However, during reset, pull-up is unavailable and will be in high impedance state. Figure 4.2-2 lists the setting of Port 0 pull-up resistor control register. Figure 4.2-2 Pull-up resistor control register setting (PURC0) Address 0070H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PUR07 PUR06 PUR05 PUR04 PUR03 PUR02 PUR01 PUR00 R/W R/W R/W R/W R/W R/W R/W Initial value 11111111B R/W PUR03 PUR02 PUR01 PUR00 0 P03 pull-up ON P02 pull-up ON P01 pull-up ON P00 pull-up ON 1 P03 pull-up OFF P02 pull-up OFF P01 pull-up OFF P00 pull-up OFF PUR07 PUR06 PUR05 PUR04 0 P07 pull-up ON P06 pull-up ON P05 pull-up ON P04 pull-up ON 1 P07 pull-up OFF P06 pull-up OFF P05 pull-up OFF P04 pull-up OFF R/W : Readable/Writable : Initial value 91 CHAPTER 4 I/O PORTS 4.2.2 Operation of Port 0 This section describes the operations of the port 0. ■ Operation of Port 0 ● Operation as an output port • Setting the corresponding DDR0 register bit to "1" sets a pin as an output port. • When a pin is set as an output port, its output transistor is enabled and the pin outputs the data stored in the output latch. • Writing data to the PDR0 register stores the data in the output latch and outputs the data directly to the pin. • Reading the PDR0 register returns the pin value. ● Operation as an input port • Setting the corresponding DDR0 register bit to "0" sets a pin as an input port. • When a pin is set as an input port, the output transistor is "OFF" and the pin goes to the high-impedance state. • Writing data to the PDR0 register stores the data in the output latch of the PDR but does not output the data to the pin. • Reading the PDR0 register returns the pin value. ● Operation as a peripheral output • If a peripheral output enable bit is set to "enable", the corresponding pin becomes a peripheral output. • Reading the PDR0 register returns the pin value, regardless of whether peripheral output is enabled/ disabled. ● Operation as a peripheral input • A port pin is set as a peripheral input by setting the corresponding DDR0 register bit to "0". • Reading the PDR0 register returns the pin value, regardless of whether or not the peripheral is using the input pin. ● Operation at reset • Resetting the CPU initializes the DDR0 register values to "0". This sets the output transistors "OFF" (all pins become input ports) and sets the pins to the high-impedance state. • The PDR0 register is not initialized by a reset. Therefore, to use as output ports, the output data must be set in the PDR0 registers before setting the corresponding DDR0 register bits to output mode. ● Operation in stop mode The pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device changes to stop mode. This is achieved by forcibly setting the output transistor "OFF" regardless of the DDR0 register values. 92 Table 4.2-4 lists the state of pins of port 0. Table 4.2-4 The State of Pins of Port 0 Pin name Normal operation main-sleep mode main-stop mode (SPL=0) sub-sleep mode sub-stop mode (SPL=0) watch mode (SPL=0) Main-stop mode (SPL = 1) sub-stop mode (SPL = 1) watch mode (SPL = 1) Reset P00 to P07 General-purpose I/O ports Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance Reference: Pins with a pull-up resistor go to the "H" level (pull-up state) rather than to the high-impedance state when the output transistors are all "OFF". 93 CHAPTER 4 I/O PORTS 4.3 Port 1 Port 1 is general-purpose I/O port that also serves as external interrupt, analog input pins and LCD segment outputs. This section principally describes the port functions when operating as general-purpose I/O ports. The section describes the structure, pins, the pin block diagram, and the registers for port 1. ■ Structure of Port 1 Port 1 consists of four components respectively. • General-purpose I/O pins (P10/SEG23/INT10 to P17/SEG30/AN3) • Port 1 data register (PDR1) • Port 1 data direction register (DDR1) • A/D input enable register (ADER) ■ Pins of Port 1 • Port 1 consists of eight I/O pins of a CMOS input and N-ch open-drain output type. • As the I/O pins are shared with resource I/O, the pins cannot be used as general-purpose I/O ports when the corresponding resource is used. Table 4.3-1 lists the port 1 pins. Table 4.3-1 Pins of Port 1 Shared peripheral Port Pin name Input Output P10/SEG23/INT10 INT10 SEG23 P11/SEG24/INT11 INT11 SEG24 P12/SEG25/INT12 INT12 SEG25 INT13 SEG26 AN0 SEG27 P15/SEG28/AN1 AN1 SEG28* P16/SEG29/AN2 AN2 SEG29* P17/SEG30/AN3 AN3 SEG30* P13/SEG26/INT13 Port1 P14/SEG27/AN0 I/O type Function General purpose I/O Input CMOS hysteresis F/K N-ch open-drain CMOS analog *: If booster is selected, SEG27 to SEG30 will be disabled by mask option. See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 94 Output Circuit type G/K ■ Block Diagram of Pins of Port 1 Figure 4.3-1 Block Diagram of Pins of Port 1 A/D converter channel selector A/D converter analog input To external interrupt input External interrupt input enable A/D Input enable PDR (Port data register) Stop, watch mode Internal data bus PDR read LCD output enable PDR read (for bit manipulation instructions) LCD segment output Mask Option Output latch PDR write Pin N-ch DDR DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Port 1 Registers • The port 1 registers consist of PDR1, DDR1 and ADER. • Each bit in these registers has a one-to-one relationship with port 1 pin respectively. Table 4.3-2 shows the correspondence between pins and registers for port 1. Table 4.3-2 Correspondence between Pins and Registers for Port 1 Port Port1 Correspondence between register bits and pins PDR1, DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADER bit7 bit6 bit5 bit4 - - - - Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 95 CHAPTER 4 I/O PORTS 4.3.1 Port 1 Registers (PDR1, DDR1) This section describes the port 1 registers. ■ Functions of Port 1 Register ● Port 1 data register (PDR1) The PDR1 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state. Note: For bit manipulation instructions (SETB and CLRB), since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. ● Port 1 data direction register (DDR1) • The DDR1 register sets the direction (input or output) for each pin (bit). • Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets the pin as an input port. Note: As the DDR1 register is write-only, the bit manipulation instructions (SETB and CLRB) cannot be used. ● Settings when pins are used as external interrupt inputs When port pins are used as external interrupt input pins, in addition to enabling the external interrupt circuit (external interrupt 1), the corresponding pins must also be set as inputs. The corresponding output latch data has no significance in this case. ● Settings as an analog input When port 1 pins are used as analog signal input pins, write "0" to the corresponding bits of DDR1 to set the pin as input pin and write "1" to the corresponding bits of ADER to set the pin as analog input pin. ● Settings as an LCD segment output To use pins as LCD segment outputs, DDR1 corresponding bits for pins used for this purpose should be set to turn the output transistor "OFF", to prevent it from interfering with the LCD segment output. Also set the corresponding LCD output enable bit to the "enable" state. 96 Table 4.3-3 lists the functions of the port 1 registers. Table 4.3-3 Functions of Port 1 Registers Register Data Read Write 0 Pin state is the "L" level. Sets "0" to the output latch. Outputs an "L" level to the pin if the pin functions as an output port. 1 Pin state is the "H" level. Sets "1" to the output latch. The pin is set to high impedance. Port 1 data register (PDR1) 0 Port 1 data direction register (DDR1) 1 Reading is not permitted (writeonly) Read/ Write Address Initial value R/W 0002H XXXXXXXXB W 0003H 00000000B Disables output transistor and sets the pin as an input pin. Enables output transistor and sets the pin as output pin. R/W: Readable/Writable W : Write only X : Undefined value ● A/D input enable register (ADER) The ADER register sets the function for each pin. Setting "1" to the bit corresponding to a port (pin) sets the pin as an analog input port. Setting "0" sets the pin as a general purpose I/O port. Reference: To set the pin as analog input port, the corresponding bit in DDR1 also should be set to "0". Figure 4.3-2 A/D input enable register (ADER) Address 0030H bit7 bit6 bit5 bit4 ADER7 ADER6 ADER5 ADER4 R/W R/W R/W bit3 bit2 bit1 bit0 Initial value — — — — 1111----B R/W ADER7 0 1 ADER6 ADER5 ADER4 Port input mode Port input mode Port input mode Port input mode Analog input mode Analog input mode Analog input mode Analog input mode R/W : Readable/Writable : Initial value — : Undefined 97 CHAPTER 4 I/O PORTS 4.3.2 Operation of Port 1 This section describes the operations of the port 1. ■ Operation of Port 1 ● Operation as an output port • Setting the corresponding DDR1 register bit to "1" sets a pin as an output port. • When a pin is set as an output port, its output transistor is enabled and the pin outputs the data stored in the output latch. • Writing data to the PDR1 register stores the data in the output latch and outputs the data directly to the pin. When the output latch value is "0", the output transistor turns "OFF" and an "L" level is output from the pin. When the output latch value is "1", the output transistor turns "OFF" and the pin goes to high impedance state. • Reading the PDR1 register returns the pin value. ● Operation as an input port • Setting the corresponding DDR1 and ADER register bit to "0" sets a pin as an input port. • When a pin is set as an input port, the output transistor is "OFF" and the pin goes to the high-impedance state. • Writing data to the PDR1 register store the data in the output latch of the PDR but does not output the data to the pin. • Reading the PDR1 register returns the pin value. ● Operation as an external interrupt input • When a port is an external interrupt input, the port is made an input by setting the corresponding DDR1 register bits to "0". • Reading the PDR1 register returns the pin value, regardless of whether external interrupt inputs or interrupt request outputs are enabled/disabled. ● Operation as an analog input • Set the DDR1 bit that corresponds to the analog input pin to "0" to turn the port to input port. • Set the ADER corresponding bit to "1" to set the port as analog input port. ● Operation as an LCD segment output When the LCD output is selected, set the DDR1 register bits corresponding to the LCD segment output pins to "0" to turn the output transistor "OFF". 98 ● Operation at reset • Resetting the CPU initializes the DDR1 register values to "0". This sets the output transistors "OFF" (all pins become input ports) and sets the pins to the high-impedance state. • The PDR1 register is not initialized by a reset. Therefore, to use as output ports, the output data must be set in the PDR1 registers before setting the corresponding DDR1 register bits to output mode. ● Operation in stop mode The pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device changes to stop mode. This is achieved by forcibly setting the output transistor "OFF" regardless of the DDR1 register values. Table 4.3-4 lists the state of pins of port 1. Table 4.3-4 The State of Pins of Port 0 Pin name Normal operation main-sleep mode main-stop mode (SPL=0) sub-sleep mode sub-stop mode (SPL=0) watch mode (SPL=0) Main-stop mode (SPL = 1) sub-stop mode (SPL = 1) watch mode (SPL = 1) Reset P10 to P17 General-purpose I/O ports Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance 99 CHAPTER 4 I/O PORTS 4.4 Port 2 Port 2 is general-purpose I/O port that also serves as resource signal I/O pins. This section principally describes the port functions when operating as generalpurpose I/O port. The section describes the structure, pins, the pin block diagram, and the registers for port 2. ■ Structure of Port 2 Port 2 consists of four components. • General-purpose I/O port (P20/PWM to P27/V2/EC1) • Port 2 data register (PDR2) • Port 2 data direction register (DDR2) • Port 2 pull-up resistor control register (PURC2) ■ Pins of Port 2 • Port 2 consists of four CMOS I/O ports and four N-ch open drain I/O ports. • As the I/O pins are shared with resource I/O, the pins cannot be used as general-purpose I/O ports when the corresponding resource is used. Table 4.4-1 Pins of Port 2 Shared peripheral Port Pin name I/O type Function P20/PWM Circuit type Input Output - PWM P21/SCK Input Output SCK E CMOS P22/SO - SO P23/SI SI - CMOS D C1 P24/C1/TO2* H P20 to P27 General-purpose I/O Port 2 - TO2 C0 P25/C0/EC2* EC2 - CMOS hysteresis V1 P26/V1/TO1 - CMOS H CMOS hysteresis F TO1 V2 P27/V2/EC1 EC1 F N-ch open drain - * : If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. P24 and P25 are also fixed as capacitor connecting pins C1 and C0 by mask option. See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 100 ■ Block Diagram of Pins of Port 2 Figure 4.4-1 Block Diagram of Pins of Port 2 (P20 to P23) To peripheral input PDR (Port data register) Internal data bus PDR read Stop, watch mode Peripheral output Pull-up resistor Approx. 50kΩ Pull-up resistor control register Peripheral output enable P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin DDR DDR write DDR read N-ch (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: When a port is used as a normal input port, peripheral circuit operation that uses the same pins must be disabled. 101 CHAPTER 4 I/O PORTS Figure 4.4-2 Block Diagram of Pins of Port 2 (P24, P25) To peripheral input PDR (Port data register) Stop, watch mode Peripheral output Internal data bus PDR read Peripheral output enable Mask option * Booster Mask option * PDR read (for bit manipulation instructions) Output latch Pin PDR write N-ch DDR DDR write DDR read (Port direction register) Stop, watch mode (SPL = 1) * : If booster is selected by mask option, C0, C1 will connect to pin by mask option and input buffer will be disabled to avoid current leakage. SPL: Pin state specification bit in the standby control register (STBC) Note: When a port is used as a normal input port, peripheral circuit operation that uses the same pins must be disabled. 102 Figure 4.4-3 Block Diagram of Pins of Port 2 (P26, P27) To peripheral input Stop, watch mode LCD pin select PDR (Port data register) LCD driver/booster Peripheral output Internal data bus PDR read Peripheral output enable N-ch PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch DDR DDR write DDR read (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: When a port is used as a normal input port, peripheral circuit operation that uses the same pins must be disabled. ■ Port 2 Registers • The port 2 registers consist of PDR2, DDR2 and PURC2. • Each bit in these registers has a one-to-one relationship with port 2 pin. Table 4.4-2 shows the correspondence between pins and registers for port 2. Table 4.4-2 Correspondence between Pins and Registers for Port 2 Port Port2 Correspondence between register bits and pins PDR2, DDR2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20 PURC2 - - - - bit3 bit2 bit1 bit0 103 CHAPTER 4 I/O PORTS 4.4.1 Port 2 Registers (PDR2, DDR2, PURC2) This section describes the port 2 registers. ■ Functions of Port 2 Register ● Port 2 data register (PDR2) The PDR2 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state. Note: For bit manipulation instructions (SETB and CLRB), since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. ● Port 2 data direction register (DDR2) • The DDR2 register sets the direction (input or output) for each pin (bit). • Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets the pin as an input port. ● Settings as peripheral output To use a peripheral that has an output pin, set the peripheral output enable bit for that pin to the "enable" state. As can be seen in the block diagram, the peripheral has precedence over the general-purpose port for use of the output pin. Once the peripheral output is enabled, the states set in the PDR2 and DDR2 registers are no longer valid, and do not affect the data output by the peripheral, or the enabling of the output. ● Settings as a peripheral input To use a peripheral that has a port 2 pin as an input pin, set that pin as an input port. The output latch data for that pin will no longer be valid. ● Setting as LCD driver / booster pin To use pins as LCD driver/booster pin, DDR2 corresponding bits for pins used for this purpose should be set to turn the output transistor "OFF", to prevent it from interfering with the LCD driver/booster operation. Also set the corresponding LCD pin select bit to the "enable" state. Note: As the peripheral has precedence over the DDR2 setting, do not enable the peripheral when the pin is used for LCD driver/booster. 104 Table 4.4-3 shows the function of the register of port 2. Table 4.4-3 Functions of Port 2 Register Register Data Read Write Read/Write Address Initial value R/W 0004H 00000000B R/W 0006H 00000000B Sets "0" to the output latch. Pin state is the "L" Outputs an "L" level to the pin if the level. pin functions as an output port. 0 Port 2 data register (PDR2) 1 Pin state is the "H" level. Sets "1" to the output latch. Outputs an "H" level to the pin if the pin functions as an output port for P20 to P23. The pin is set to high impedance for P24 to P27. 0 Input port Disables output transistor and sets the pin as an input pin. output port Enables output transistor and sets the pin as output pin. Port 2 data direction register (DDR2) 1 R/W: Readable/Writable ● Port 2 pull-up resistor control register (PURC2) By using pull-up resistor control register (PURC2), it is possible to turn on/off pull-up resistor. When pull-up resistor is selected in pull-up resistor control register, the states of these pins in stop mode (SPL=1) are in "H" level (pull-up state) rather than high impedance. However, during reset, pull-up is unavailable and will be in high impedance state. Figure 4.4-4 shows the setting of port 2 pull-up resistor control register. Figure 4.4-4 Pull-up resistor control register setting (PURC2) PURC2 Address bit7 bit6 bit5 bit4 0072H — — — — bit3 bit2 bit1 bit0 Initial value PUR23 PUR22 PUR21 PUR20 R/W R/W R/W ----1111B R/W PUR23 PUR22 PUR21 PUR20 0 P23 pull up ON P22 pull up ON P21 pull up ON P20 pull up ON 1 P23 pull up OFF P22 pull up OFF P21 pull up OFF P20 pull up OFF R/W : Readable/Writable : Initial value — : Undefined 105 CHAPTER 4 I/O PORTS 4.4.2 Operation of Port 2 This section describes the operations of the port 2. ■ Operation of Port 2 ● Operation as an output port • Setting the corresponding DDR2 register bit to "1" sets a pin as an output port. • When a pin is set as an output port, its output transistor is enabled and the pin outputs the data stored in the output latch. • Writing data to the PDR2 register stores the data in the output latch of the PDR and outputs the data directly to the pin. • Reading the PDR2 register returns the pin value. P26, P27 are default to function as LCD power pins. When P26, P27 are set to function as general purpose I/O ports (by setting LCR2:PSEL to "1") reading PDR2:bit6 and PDR2:bit7 return the corresponding pin values. ● Operation as an input port • Setting the corresponding DDR2 register bit to "0" set P20 to P25 as an input port. • Setting the corresponding DDR2 register bit to "0" and LCR2 :PSEL to "1" set P26, P27 as an input port. • When a pin is set as an input port, the output transistor is "OFF" and the pin goes to the high-impedance state. • Writing data to the PDR2 registers stores the data in the output latch but does not output the data to the pin. • Reading the PDR2 register returns the pin values. Reference: If booster is selected by mask option, bit 4 and bit 5 of PDR2 are always read as "0" for pin P24 and P25. ● Operation as a peripheral output • If a peripheral output enable bit is set to "enable", the corresponding pin becomes a peripheral output. • Reading the PDR2 register returns the pin value, regardless of whether peripheral output is enabled/ disabled. ● Operation as a peripheral input • A port pin is set as a peripheral input by setting the corresponding DDR2 register bit to "0". • Reading the PDR2 register returns the pin value, regardless of whether or not the peripheral input is used. 106 ● Operation as LCD driver/booster pin • When the LCD driver/booster is selected, set the DDR2 register bits corresponding to the LCD driver/ booster pins to "0" to turn the output transistor "OFF". • Setting LCR2 :PSEL to "0" will set the P26 and P27 as LCD power supply pin V1 and V2. If booster is selected by mask option, C0 and C1 will connect to P25 and P24, EC2 and TO2 will be redirected to P03 and P04 respectively. ● Operation at reset Resetting the CPU initializes both the PDR2 and DDR2 register values to "0". This sets the output transistor "OFF" (all pins become input ports) and sets the pins to the high-impedance state. ● Operation in stop mode The pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC:SPL) is "1" when the device changes to stop mode. This is achieved by forcibly setting the output transistor "OFF" regardless of the DDR2 register values. Table 4.4.4 lists the port 2 pin states. Table 4.4-4 Port 2 Pin state Pin name Normal operation main-sleep mode main-stop mode (SPL=0) sub-stop mode sub-stop mode (SPL=0) watch mode (SPL=0) Main-stop mode (SPL=1) sub-stop mode (SPL=1) watch mode (SPL=1) Reset P20/PWM, P21/SCK, P22/SO, P23/SI Hi-Z P24/C1/TO2 Hi-Z/C1 * P25/C0/EC2 General-purpose I/O ports/peripheral I/O Hi-Z Hi-Z/C0 * P26/V1/TO1 V1 P27/V2/EC1 V2 * : When booster is selected SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance Reference: Pins with a pull-up resistor go to the "H" level (pull-up state) rather than the high-impedance state when the output transistors are all "OFF". 107 CHAPTER 4 I/O PORTS 4.5 Port 3 Port 3 is a general-purpose output only port that also serves as the LCD common outputs. This section principally describes the port functions when operating as a general-purpose output port. The section describes the structure, pins, the pin block diagram, and the port registers for port 3. ■ Structure of Port 3 Port 3 consists of the following two components: • General-purpose output port/LCD common output pins (P30/COM2, P31/COM3) • Port 3 data register (PDR3) ■ Pins of Port 3 Port 3 consists of two N-channel open-drain pins output. P30 and P31 are also used as LCD common output pins COM2 and COM3. While it is being used by LCD, this pin cannot be used as the generalpurpose output port. Table 4.5-1 lists the port 3 pins. Table 4.5-1 Pins of Port 3 Shared peripheral Port Pin name Circuit type Output P30/COM2 Port 3 Input Output — N-ch open-drain COM2 General-purpose I/O P31/COM3 I/O type Function COM3 See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 108 I/K ■ Block Diagram of Pins of Port 3 Figure 4.5-1 Block Diagram of Pins of Port 3 LCD output enable Internal data bus PDR (Port data register) LCD common output PDR read N-ch Output latch PDR write Pin N-ch Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Port 3 Register • The port 3 register consists of PDR3. • Each bit in the register has a one-to-one relationship with port 3 pin. Table 4.5-2 shows the correspondence between pins and register for port 3. Table 4.5-2 Correspondence between Pins and Registers for Port 3 Port Correspondence between register bits and pins PDR3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin - - - - - - P31 P30 Port3 109 CHAPTER 4 I/O PORTS 4.5.1 Port 3 Register (PDR3) This section describes the port 3 register. ■ Functions of Port 3 Register ● Port 3 data register (PDR3) The PDR3 register holds the output latch states. Therefore, it does not read out as the pin. ● Settings as an LCD common output To use pins as LCD common outputs, PDR3 corresponding bits for pins used for this purpose should be set to turn the output transistor "OFF", to prevent it from interfering with the LCD common output. Also set the corresponding LCD output enable bit to the "enable" state. Table 4.5-3 lists the functions of the port 3 registers. Table 4.5-3 Functions of Port 3 Register Register Data Write 0 Output latch value Sets "0" to the output latch. is "0" Outputs an "L" level to the pin. 1 Output latch value Sets "1" to the output latch. is "1" The pin is set to high impedance. Port 3 data register (PDR3) R/W: Readable/Writable 110 Read Read/Write Address Initial value R/W 000CH ------11B 4.5.2 Operation of Port 3 This section describes the operations of the port 3. ■ Operation of Port 3 ● Operation as an output port • Writing data to the PDR3 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance state. • Reading the PDR3 register returns output latch value. ● Operation as an LCD common output • When the LCD output is selected, set the PDR3 register bits corresponding to the LCD common output pins to "1" to turn the output transistor "OFF". • You cannot read the LCD output data by reading PDR3 register. (If you read the PDR registers, you will get the output latch data, not the LCD output data.) ● Operation at reset Resetting the CPU initializes the PDR3 register value to "1". This sets output transistors "OFF" and sets the pins to the high-impedance state. ● Operation in stop mode The pins go to the high-impedance state, if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device changes to stop mode. This is achieved by forcibly setting the output transistor "OFF" regardless of the PDR3 register value. Table 4.5-4 lists the port 3 pin states. Table 4.5-4 Port 3 Pin State Pin name P30/COM2, P31/COM3 Normal operation main-sleep mode main-stop mode (SPL=0) sub-sleep mode sub-stop mode (SPL=0) watch mode (SPL=0) General-purpose output port/LCD common output Main-stop mode (SPL = 1) sub-stop mode (SPL = 1) watch mode (SPL = 1) Reset Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance 111 CHAPTER 4 I/O PORTS 4.6 Port 4 Port 4 is general-purpose I/O port that also serves as LCD segment output. This section principally describes the port functions when operating as general-purpose output ports. The section describes the structure, pins, the pin block diagram, and the registers for port 4. ■ Structure of Port 4 Port 4 consists of two components. • General-purpose I/O pins/LCD segment output pins (P40/SEG8 to P47/SEG15) • Port 4 data register (PDR4) ■ Pins of Port 4 Port 4 consists of eight N-channel open-drain I/O ports. When P40 to P47 are used as LCD segment output pins, they cannot be used as general purpose I/O pins. Table 4.6-1 lists the port 4 pins. Table 4.6-1 Pins of Port 4 Shared peripheral Port Pin name Circuit type Output P40/SEG8 SEG8 P41/SEG9 SEG9 P42/SEG10 SEG10 P43/SEG11 Port 4 P44/SEG12 P40 to P47 General purpose I/O Input Output CMOS N-ch open drain SEG11 SEG12 P45/SEG13 SEG13 P46/SEG14 SEG14 P47/SEG15 SEG15 See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 112 I/O type Function H/K ■ Block Diagram of Pins of Port 4 Figure 4.6-1 Block Diagram of Pins of Port 4 LCD output enable Stop, watch mode PDR (Port data register) LCD segment output Internal data bus PDR read PDR read (for bit manipulation instructions) Output latch N-ch PDR write Pin N-ch Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: Do not use the pins as output ports if using as an LCD segment output. ■ Port 4 Register • The port 4 register consists of PDR4. • Each bit in the register has a one-to-one relationship with port 4. Table 4.6-2 shows the correspondence between pins and register for port 4. Table 4.6-2 Correspondence between Pins and Registers for Port 4 Port Correspondence between register bits and pins PDR4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P47 P46 P45 P44 P43 P42 P41 P40 Port4 113 CHAPTER 4 I/O PORTS 4.6.1 Port 4 Registers (PDR4) This section describes the port 4 register. ■ Functions of Port 4 Register ● Port 4 data register (PDR4) The PDR4 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state. Note: For bit manipulation instructions (SETB and CLRB), since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. ● Settings as an LCD segment output To use pins as LCD segment outputs, PDR4 corresponding bits for pins used for this purpose should be set to turn the output transistor "OFF", to prevent it from interfering with the LCD segment output. Also set the corresponding LCD output enable bit to the "enable" state. Table 4.6-3 lists the functions of the port 4 register. Table 4.6-3 Functions of Port 4 Register Register Data Read 0 Output latch pin state is the "L" level. Sets "0" to the output latch. Outputs an "L" level to the pin. 1 Output latch pin state is the "H" level. Sets "1" to the output latch. The pin is set to high impedance. Port 4 data register (PDR4) R/W: Readable/Writable 114 Write Read/Write Address Initial value R/W 0010H 11111111B 4.6.2 Operation of Port 4 This section describes the operations of the port 4. ■ Operation of Port 4 ● Operation as an output port • Writing data to the PDR4 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance state. • Reading the PDR4 register returns output latch value. ● Operation as an input port • To set the pin as an input port, write "1" to the bits in the PDR4 register. The output transistor is "OFF". • Reading the PDR4 register returns the pin value. ● Operation as LCD segment output • When the LCD output is selected, set the PDR4 register bits corresponding to the LCD segment output pins to "1" to turn the output transistor "OFF". • You cannot read the LCD output data by reading PDR4 register. ● Operation at reset Resetting the CPU initializes the PDR4 register values to "1". This turns all the output transistors "OFF" and sets the pins to the high-impedance state. ● Operation in stop mode The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC:SPL) is "1" when the device changes to stop mode. Table 4.6-4 lists the port 4 pin states. Table 4.6-4 Port 4 Pin State Pin name P40/SEG8 to P47/SEG15 Normal operation main-sleep mode main-stop mode (SPL=0) sub-sleep mode sub-stop mode (SPL=0) watch mode (SPL=0) General-purpose output port/LCD segment output Main-stop mode (SPL = 1) sub-stop mode (SPL = 1) watch mode (SPL = 1) Reset Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance 115 CHAPTER 4 I/O PORTS 4.7 Port 5 Port 5 is general-purpose I/O port that also serves as LCD segment output. This section principally describes the port functions when operating as general-purpose output ports. The section describes the structure, pins, the pin block diagram, and the registers for port 5. ■ Structure of Port 5 Port 5 consists of two components. • General-purpose I/O pins/LCD segment output pins (P50/SEG16 to P56/SEG22), general-purpose input only pin P57 • Port 5 data register (PDR5) ■ Pins of Port 5 Port 5 consists of seven I/O pins of N-ch open-drain type and one input only port. lists the port 5 pins. Table 4.7-1 Pins of Port 5 Port Pin name Function Shared peripheral Output P50/SEG16 SEG16 P51/SEG17 SEG17 P52/SEG18 SEG18 P53/SEG19 Port 5 P50 to P56 General-purpose I/O SEG19 P54/SEG20 SEG20 P55/SEG21 SEG21 P56/SEG22 SEG22 P57 P57 General-purpose input — I/O type Circuit type Input Output CMOS Nch opendrain H/K CMOS — J See Table 1.7-3 in "1.7 Pin Functions" for a description of the circuit type. 116 ■ Block Diagram of Pins of Port 5 Figure 4.7-1 Block Diagram of Pins of Port 5 (P50 to P56) LCD output enable Stop, watch mode PDR (Port data register) LCD segment output Internal data bus PDR read PDR read (for bit manipulation instructions) Output latch N-ch PDR write Pin N-ch Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Internal data bus Figure 4.7-2 Block Diagram of Pins of Port 5 (P57) PDR (Port data register) Pin PDR read P57 ■ Port 5 Register • The port 5 register consists of PDR5. • Each bit in the register has a one-to-one relationship with port 5. Table 4.7-1 lists the correspondence between pins and register for port 5. Table 4.7-2 Correspondence between Pins and Registers for Port 5 Port Correspondence between register bits and pins PDR5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50 Port5 117 CHAPTER 4 I/O PORTS 4.7.1 Port 5 Register (PDR5) This section describes the port 5 register. ■ Functions of Port 5 Register ● Port 5 data register (PDR5) The PDR5 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state. Note: For bit manipulation instructions (SETB and CLRB), since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. ● Settings as an LCD segment output To use pins as LCD segment outputs, PDR5 corresponding bits for pins used for this purpose should be set to turn the output transistor "OFF", to prevent it from interfering with the LCD segment output. Also set the corresponding LCD output enable bit to the "enable" state. Table 4.7-3 lists the functions of the port 5 register. Table 4.7-3 Functions of Port 5 Register Register Data Read 0 Pin state is the "L" level. Port 5 data register (PDR5) 1 R/W: Readable/Writable X: Undefined value 118 Pin state is the "H" level. Write Sets "0" to the output latch. Outputs "L" level to the pin if the pin functions as an output port. (no effect for P57) Sets "1" to the output latch. The pin is set to high impedance. (no effect for P57) Read/ Write Address Initial value R/W 0012H X1111111B 4.7.2 Operation of Port 5 This section describes the operations of the port 5. ■ Operation of Port 5 ● Operation as an output port • Writing data to the PDR5 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance state. (P57 is an input only port, writing "0" to PDR5:bit7 has no effect for P57) • Reading the PDR5 register returns output latch value. ● Operation as an input port • To set the pin as an input port, write "1" to the bits in the PDR5 register. The output transistor is "OFF". (P57 is an input only port, writing "1" to PDR5:bit7 has no effect for P57) • Reading the PDR5 register returns the pin value. ● Operation as LCD segment output • When the LCD output is selected, set the PDR5 register bits corresponding to the LCD segment output pins to "1" to turn the output transistor "OFF". • You cannot read the LCD output data by reading PDR5 register. ● Operation at reset Resetting the CPU initializes the PDR5 register values to "1". This turns all the output transistors "OFF" and sets the pins to the high-impedance state. ● Operation in stop mode The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC:SPL) is "1" when the device changes to stop mode. Table 4.7-4 lists the port 5 pin states. Table 4.7-4 Port 5 Pin State Pin name Normal operation main-sleep mode main-stop mode (SPL=0) sub-sleep mode sub-stop mode (SPL=0) watch mode (SPL=0) P50 to P56 General-purpose I/O ports P57 General-purpose input ports Main-stop mode (SPL = 1) sub-stop mode (SPL = 1) watch mode (SPL = 1) Reset Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance 119 CHAPTER 4 I/O PORTS 4.8 Program Example for I/O Ports This section gives a program example using the I/O ports. ■ Program Example for I/O Ports ● Processing description • Port 0 and port 1 are used to illuminate all elements of seven segment LED (eight segments if the decimal point is included). • The P10 pin is used for the anode common pin of the LED and the P00 to P07 pins operate as the segment pins. Figure 4.8-1 shows the connection example for an eight segment LED of port in MB89480. Figure 4.8-1 Connection Example for an Eight Segment LED MB89480 P10 P07 P06 .... .... P00 ● Coding example PDR0 EQU 0000H ; Address of the Port 0 data register DDR0 EQU 0001H ; Address of the Port 0 data direction register PDR1 EQU 0002H ; Address of the Port 1 data register DDR1 EQU 0003H ; Address of the Port 1 data direction register ;--------- Main program ------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB PDR1:0 ; Set P10 to the "L" level. MOV PDR0, #11111111B ; Set all port 0 pins to the "H" level. MOV DDR1, #11111111B ; Set P10 as an output (#xxxxxxx1B). MOV DDR0, #11111111B ; Set all port 0 pins as outputs. : ENDS ;-------------------------------------------------------------------------------------------------------------------------END 120 CHAPTER 5 TIME-BASE TIMER This chapter describes the functions and operation of the time-base timer. 5.1 Overview of Time-base Timer 5.2 Block Diagram of Time-base Timer 5.3 Time-base Timer Control Register (TBTC) 5.4 Time-base Timer Interrupt 5.5 Operation of Time-base Timer 5.6 Notes on Using Time-base Timer 5.7 Program Example for Time-base Timer 121 CHAPTER 5 TIME-BASE TIMER 5.1 Overview of Time-base Timer The time-base timer provides interval timer functions. Four different interval times can be selected. The time-base timer uses a 21-bit free-run counter which counts-up in sync with the internal count clock (divide-by-two the main clock source oscillation). The timebase timer also provides the timer output for the main clock oscillation stabilization wait time and the operating clock for the peripheral functions such as the watchdog timer and buzzer, continuous activation clock for the A/D converter. The time-base timer stops operating in modes in which the main clock source oscillation is stopped. ■ Interval Timer Function The interval timer function generates repeated interrupt requests at fixed time intervals. • The timer generates an interrupt request each time the interval timer bit overflows on the time-base timer counter. • The interval time can be selected from four different settings. Table 5.1-1 lists the available interval time for the time-base timer. Table 5.1-1 Time-base timer Interval time Internal count clock cycle Interval time 213/FCH (approx. 0.66 ms) 2/FCH (0.16 µs) 215/FCH (approx. 2.62 ms) 218/FCH (approx. 21.0 ms) 222/FCH (approx. 335.5 ms) FCH: Main clock source oscillation The values enclosed in parentheses are for a 12.5 MHz main clock source oscillation. 122 ■ Clock Supply Function The clock supply function provides the timer output used for the main clock oscillation stabilization wait time (three values), and operation clock for some peripheral functions. Table 5.1-2 lists the cycles of the clocks that the time-base timer supplies to various peripheral functions. Table 5.1-2 Cycles of Clocks Supplied by Time-base Timer Clock destination Clock cycle 214/FCH (approx. 1.31 ms) Main clock oscillation stabilization wait time 217/FCH (approx. 10.5 ms) 218/FCH (approx. 21.0 ms) Remarks Selected by the oscillation stabilization wait time select bits of the system clock control register (SYCC: WT1, WT0), which is in the clock control section. Watchdog timer 221/FCH (approx. 167.8 ms) Count-up clock for the watchdog timer Buzzer output 29/FCH to 212/FCH (approx. 41.0 to 327.7 µs) See "CHAPTER 16 BUZZER OUTPUT". A/D converter 28/FCH (approx. 20.5 µs) Clock for continuous activation LCD controller/driver 27/FCH (approx. 10.2 µs) Frame cycle clock FCH: Main clock source oscillation The values enclosed in parentheses are for a 12.5 MHz main clock source oscillation. Note: The oscillation stabilization wait time should be used as a guide line since the oscillation cycle is unstable immediately after oscillation starts. 123 CHAPTER 5 TIME-BASE TIMER 5.2 Block Diagram of Time-base Timer The time-base timer consists of the following four blocks: • Time-base timer counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of Time-base Timer Figure 5.2-1 Block Diagram of Time-base Timer To LCD controller/driver To A/D converter ⎞ ⎟ To buzzer output ⎠ Time-base timer counter Divide-by -two FCH × 21 × 22 To watchdog timer × 23 . . . × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 . . . × 220 × 221 OF OF OF Counter clear Watchdog timer clear Power-on reset Sub clock mode start Stop mode start OF Counter clear circuit clock ⎞ To controller for the ⎟ oscillation ⎠ stabilization wait time selector Interval timer selector IRQB time-base timer interrupt OF: Overflow FCH: Main clock source oscillation TBTC TBOF TBIE — — — TBC1 TBC0 TBR ● Time-base timer counter A 21-bit up-counter that uses the divide-by-two main clock source oscillation as a count clock. The counter stops when the main clock oscillator is stopped. ● Counter clear circuit In addition to being cleared by setting the TBTC register (TBR=0), the counter is cleared when device changes to main stop (STBC: STP =1) and by power-on reset. ● Interval timer selector Selects one of four operating time-base timer counter. An overflow on the selected bit triggers an interrupt. 124 ● Time-base Timer Control Register (TBTC) The TBTC register is used to select the interval time, clear the counter, control interrupt requests, and check the state of the time-base timer. 125 CHAPTER 5 TIME-BASE TIMER 5.3 Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) is used to select the interval times bit, clear the counter, control interrupts, and check the state of the time-base timer. ■ Time-base Timer Control Register (TBTC) Figure 5.3-1 Time-base Timer Control Register (TBTC) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000AH TBOF TBIE — — — TBC1 TBC0 TBR 00---000B R/W R/W R/W R/W W Time-base timer initialization bit TBR Read Write 0 — Clears time-base timer counter 1 Reading always returns "1". No effect. The bit does not change. TBC1 TBC0 Interval time selection bits 0 0 213/FCH 0 1 215/FCH 1 0 218/FCH 1 1 222/FCH FCH: Main clock source oscillation TBIE Interrupt request enable bit 0 Disables interrupt request output. 1 Enables interrupt request output. TBOF R/W :Readable/Writable W : Write only — : Undefined : Initial value 126 Overflow interrupt request flag bit Read Write 0 No overflow on specified bit Clears this bit. 1 Overflow on specified bit No effect. The bit does not change. Table 5.3-1 Functions of Time-base Timer Control Register (TBTC) Bit name Function bit7 TBOF: Overflow interrupt request flag bit This bit is set to "1" when counter overflow occurs on the specified bit of the timebase timer counter. An interrupt request is output when both this bit and the interrupt request enable bit (TBIE) are "1". Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. bit6 TBIE: interrupt request enable bit This bit enables or disables an interrupt request output to the CPU. An interrupt request is output when both this bit and the overflow interrupt request flag bit (TBOF) are "1". bit5 to bit3 Undefined bits The read value is undefined. Writing to these bits has no effect on the operation. bit2, bit1 TBC1, TBC0: Interval time selection bits These bits select the cycle of the interval time of the time-base timer. These bits select which bit of the time-base timer counter to use as the interval timer bit. Four different interval times can be selected. bit0 TBR: Time-base timer initialization bit This bit clears the time-base timer counter to "0". Writing "0" to this bit clears the counter to "000000H". Writing "1" has no effect and does not change the bit value. The read value is always "1". 127 CHAPTER 5 TIME-BASE TIMER 5.4 Time-base Timer Interrupt The time-base timer can generate an interrupt request when an overflow occurs on the specified bit of the time-base counter (for the interval timer function). ■ Interrupts for Time-base Timer • The counter counts-up on the internal count clock. When an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1". At this time, an interrupt request (IRQB) to the CPU is generated if the interrupt request enable bit is enabled (TBTC: TBIE =1). • Write "0" to the TBOF bit in the interrupt processing routine to clear the interrupt request. The TBOF bit is set when at the specified counter bit overflows, regardless of the TBIE bit value. Note: When enabling an interrupt request output (TBIE = 1) after wake-up from a reset, always clear the TBOF bit (TBOF = 0) at the same time. References: • An interrupt request is generated immediately if the TBOF bit is "1" when the TBIE bit is changed from disabled to enabled ("0" -> "1"). • The TBOF bit is not set if the counter is cleared (TBTC: TBR = 0) at the same time as an overflow on the specified bit occurs. ■ Oscillation Stabilization Wait Time and Time-base Timer Interrupt If the interval time is set shorter than the main clock oscillation stabilization wait time, an interval interrupt request from the time-base timer (TBTC: TBOF = 1) is generated at the time when the main clock mode starts operation. In this case, disable the time-base timer interrupt when changing to a mode in which the main clock oscillation is stopped (main stop mode). ■ Register and Vector Table for Time-base Timer Interrupts Table 5.4-1 Register and Vector Table for Time-base Timer Interrupt Interrupt level setting register Vector table address Interrupt Register IRQB ILR3(007DH) Set bit LB1 (bit7) LB0 (bit6) See "3.4.2 Interrupt Processing" for details on the operation of interrupt. 128 Upper Lower FFE4H FFE5H 5.5 Operation of Time-base Timer The time-base timer has the interval timer function and the clock supply function for some peripherals. ■ Operation of Interval Timer Function (Time-base Timer) Figure 5.5-1 shows the settings required to operate the time-base timer as the interval timer function. Figure 5.5-1 Interval Timer Function Settings Time-base timer control register (TBTC) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TBOF TBIE — — — TBC1 TBC0 TBR 0 1 0 : Used bit 0 : Set "0". 1: Set "1". Provided the main clock is oscillating, the time-base timer counter continues to count-up in sync with the internal count clock (divide-by-two main clock source oscillation). After being cleared (TBR = 0), the counter restarts counting-up from zero. The time-base timer sets the overflow interrupt request flag bit (TBOF) to "1" when an overflow occurs on the interval timer bit. Consequently, the time-base timer generates interrupt requests at fixed intervals (the selected interval time), based on the time that the counter is cleared. ■ Operation of Clock Supply Function The time-base timer is also used as a timer to generate the main clock oscillation stabilization wait time. The time from when the time-base timer counter is cleared and starts counting-up until an overflow occurs on the oscillation stabilization wait time bit is the oscillation stabilization wait time. One of three possible wait times is selected by the oscillation stabilization wait time select bits of the system clock control register (SYCC: WT1, WT0). The time-base timer also provides the clock for the watchdog timer, buzzer output, A/D converter and LCD controller/driver. Clearing the time-base timer counter affects the operation of the continuous activation cycle of the A/D converter and the buzzer output. If the time-base timer output is selected by the watchdog timer count clock (WDTC: CS=0), at the same time the time-base timer counter is cleared due to changing to main stop (STBC: STP=1). ■ Operation of Time-base Timer The state of following operations are shown in Figure 5.5-2. • A power-on reset occurs. • Changes to sleep mode during operation of the interval timer function in the main clock mode. • Changes to main stop mode. • A counter clear request occurs. The time-base timer is cleared by changing to sub clock and main stop modes, and stops operation. The time-base timer counts the oscillation stabilization wait time after wake-up from sub clock and main stop modes. 129 CHAPTER 5 TIME-BASE TIMER Figure 5.5-2 Operation of Time-base Timer Counter value 1FFFFFH Cleared by changing to main stop mode. Oscillation stabilization wait overflow 00000H CPU operation starts Counter clear (TBTC: TBR = 0) Interval cycle (TBTC: TBC1, TBC0 = 11B) Power-on reset Cleared by the interrupt processing routine. TBOF bit TBIE bit Sleep mode SLP bit (STBC register) Stop mode Wake-up from Sleep mode by IRQB STP bit (STBC register) Wake-up from Stop mode by an external interrupt For the case when the interval time selection bits in the time-base timer control register (TBTC: TBC1, TBC0) are set to "11B" (222/FCH). : Indicates the oscillation stabilization wait time. 130 5.6 Notes on Using Time-base Timer This section lists points to note when using the time-base timer. ■ Notes on Using Time-base Timer ● Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit is enabled (TBTC: TBIE = 1). Always clear the TBOF bit. ● Clearing time-base timer In addition to being cleared by the time-base timer initialization bit (TBTC: TBR = 0), the timer is cleared whenever the main clock oscillation stabilization wait time is required. When the time-base timer is selected as a count clock of the watchdog timer, clearing the time-base timer also clears the watchdog timer. ● Using as timer for oscillation stabilization wait time As the main clock source oscillation is stopped when the power is turned on during main-stop mode, the time-base timer provides the main clock oscillation stabilization wait time after the oscillator starts. An appropriate oscillation stabilization wait time must be selected for the type of resonator connected to the main clock oscillator (clock generator). See "3.6.5 Oscillation Stabilization Wait Time". ● Notes on peripheral functions that provided a clock supply from time-base timer In modes in which the main clock source oscillation is stopped, the time-base timer also stops, and the counter is cleared. As the clock derived from the time-base timer restarts output from its initial state when the time-base timer counter is cleared, the "H" level may be shorter or the "L" level longer by a maximum of half cycle. The clock of the watchdog timer also restarts output from its initial state. Figure 5.6-1 shows the effect on the buzzer output of clearing the time-base timer. 131 CHAPTER 5 TIME-BASE TIMER Figure 5.6-1 Effect on Buzzer Output of Clearing Time-base Timer Counter value (bit11:0) 00FFFH 00800H 00000H Clearing the counter by the program (TBTC: TBR = 0) Clock supplied to the buzzer output For the case when the buzzer selection bits in the buzzer register (BUZR: BZ2, BZ1, BZ0) are set to "001B". (Divide-by-4096 main source oscillation, approximately 3.051 kHz output at 12.5 MHz operation) 132 5.7 Program Example for Time-base Timer This section gives a program example for the time-base timer. ■ Program Example for Time-base Timer ● Processing description Generates repeated interval timer interrupts at 218/FCH (FCH: the main clock source oscillation) intervals. At this time, the interval time is set to approximately 26.2 ms (FCH: at 10 MHz operation). ● Coding example TBTC EQU 0000AH ; Address of the time-base timer control register TBOF EQU TBTC:7 ; Define the interrupt request flag bit. ILR3 EQU 007DH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFE4H IRQB DW WARI ; Set interrupt vector. INT_V ENDS ;-----Main program--------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : CLRI ; Disable interrupts. MOV ILR3,#01111111B ; Set interrupt level (level 1). MOV TBTC,#01000100B ; Clear interrupt request flag enable interrupt request output, select 218/FCH, and clear time-base timer. SETI ; Enable interrupts. : ;-----Interrupt program---------------------------------------------------------------------------------------------------------------------------------WARI CLRB TBOF ; Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;-------------------------------------------------------------------------------------------------------------------------------------------------------------END 133 CHAPTER 5 TIME-BASE TIMER 134 CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 6.1 Overview of Watchdog Timer 6.2 Block Diagram of Watchdog Timer 6.3 Watchdog Timer Control Register (WDTC) 6.4 Operation of Watchdog Timer 6.5 Notes on Using Watchdog Timer 6.6 Program Example for Watchdog Timer 135 CHAPTER 6 WATCHDOG TIMER 6.1 Overview of Watchdog Timer The watchdog timer is a 1-bit counter that uses, as its count clock source, either the time-base timer derived from the main clock, or the watch prescaler derived from the sub clock. The watchdog timer resets the CPU if not cleared within a fixed time after activation. ■ Watchdog Timer Function • The watchdog timer is a counter provided to guard against program runaway. Once activated, the counter must be repeatedly cleared within a fixed time interval. If the program becomes trapped in an endless loop or similar and does not clear the counter within the fixed time, the watchdog timer generates a four-instruction cycle watchdog reset to the CPU. • Either the time-base timer output or the watch prescaler output can be selected as the watchdog timer count clock. • Table 6.1-1 lists the watchdog timer interval times. If not cleared, the watchdog timer generates a watchdog reset at a time between the minimum and maximum times listed. Clear the counter within the minimum time given in the table below. Table 6.1-1 Watchdog Timer Interval Time Count clock Time-base timer output (main clock oscillator frequency at 12.5 MHz) Watch prescaler output (sub clock oscillator frequency at 32.768 kHz) Minimum time Approx. 335.5 ms*1 500 ms*2 Maximum time Approx. 671 ms *1: Divide-by-two the main clock source oscillation (FCH) × time-base timer count value 1000 ms (221). *2: The time of a clock cycle at the sub clock oscillator frequency (FCL) × watch prescaler count (214). See "6.4 Operation of Watchdog Timer" for the details on the minimum and maximum time of the watchdog timer interval times". Reference: The watchdog timer counter is cleared whenever the device changes to sleep, stop or watch mode. Operation halts until the device returns to normal operation (RUN state). 136 6.2 Block Diagram of Watchdog Timer The watchdog timer consists of the following six blocks: • Count clock selector • Watchdog timer counter • Reset controller • Watchdog timer clear selector • Counter clear controller • Watchdog timer control register (WDTC) ■ Block Diagram of Watchdog Timer Figure 6.2-1 Block Diagram of Watchdog Timer WDTC register CS — — — WTE3 WTE2 WTE1 WTE0 Watchdog timer 222/FCH (time-base timer output) Count clock selector 214/FCL (watch prescaler output) Clear signal from time-base timer Clear signal from watch prescaler Clear 1-bit counter Start Overflow Reset controller RST Watchdog timer clear selector Sleep mode start Stop mode start Watch mode start Counter clear controller FCH: main clock source oscillation FCL: sub clock source oscillation ● Count clock selector The count clock selector selects the count clock for the watchdog timer counter. Either the time-base timer output or the watch prescaler output can be selected as the count clock. ● Watchdog timer counter (1-bit counter) A 1-bit counter that uses the time-base timer output or the watch prescaler output as a count clock. 137 CHAPTER 6 WATCHDOG TIMER ● Reset controller Generates a reset signal to the CPU when an overflow occurs on the watchdog timer counter. ● Watchdog timer clear selector The watchdog timer clear selector selects a watchdog timer clear signal from either the time-base timer or watch prescaler at the same time as the count clock selector selects a clock. (It selects the clear signal from the selected clock source.) ● Counter clear controller Controls clearing, activating, and halting the operation of watchdog timer counter. ● Watchdog timer control register (WDTC) The WDTC register is used to select the count clock, and to activate or clear the watchdog timer counter. As the register is write-only, the bit manipulation instructions cannot be used. 138 6.3 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to activate or clear the watchdog timer. ■ Watchdog Timer Control Register (WDTC) Figure 6.3-1 Watchdog timer Control Register (WDTC) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0009H CS — — — WTE3 WTE2 WTE1 WTE0 0---XXXXB W W W W R/W WTE3 0 WTE2 1 WTE1 0 Other than the above R/W : Readable/Writable W : Write only — : Undefined X CS Watchdog timer control bits WTE0 1 • Activate the watchdog timer (when writing for the first time after a reset). • Clear the watchdog timer (when writing for the second and subsequent times after a reset). No operation Count clock switch 0 Cycle time of time-base timer output (222/FCH*1) 1 Cycle time of watch prescaler output (214/FCL*2) : Undefined value : Initial value Note: As the bit3 to bit0 are write-only, the bit manipulation instructions cannot be used. *1: FCH: main clock source oscillation *2: FCL: sub clock source oscillation Table 6.3-1 Functions Watchdog Timer Control Register (WDTC) Bit name bit7 CS: Count clock select bit bit6 to bit4 Undefined bits bit3 to bit0 WTE3 to WTE0: Watchdog timer control bits Function At watchdog timer startup, selects the watchdog timer count clock. Selects either the time-base timer output or the watch prescaler output as the count clock. Note: When using the sub clock mode, always select the watch prescaler output. Make the count clock selection when the watchdog timer is started. Once the timer is started, do not change the count clock. Bit manipulation instructions cannot be used. • The read value is undefined. • Writing to these bits has no effect on operation. These bits set the interval time of the watchdog timer. Writing "0101B" to these bits activates (when writing for the first time after a reset) or clears (when writing for the second and subsequent times after a reset) the watchdog timer. Writing a value other than "0101B" has no effect on the operation. Note: The read value is "1111B". The bit manipulation instructions cannot be used. 139 CHAPTER 6 WATCHDOG TIMER 6.4 Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. ■ Operation of Watchdog Timer ● Activating watchdog timer • The watchdog timer is activated by writing "0101B" to the watchdog control bits in the watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset. • The count clock switch bit (WDTC: CS) is written to the desired state in the same write operation. • Once activated, the watchdog timer cannot be stopped other than by a reset. ● Clearing watchdog timer • The watchdog timer counter is cleared by writing "0101B" to the watchdog control bits in the watchdog control register (WDTC: WTE3 to WTE0) for the second or subsequent times after a reset. • If the counter is not cleared within the interval time of the watchdog timer, the counter overflows and the watchdog timer generates an internal reset signal for four-instruction cycles. ● Interval time of watchdog timer The interval time changes depending on the watchdog timer clear timing. Figure 6.4-1 shows the relationship between the watchdog timer clear timing and the interval time. The indicated times apply if the time-base timer output is selected as the count clock, and the main clock source oscillation is 12.5 MHz. 140 Figure 6.4-1 Watchdog Timer Clear and Interval Time Minimum time 335.5ms Count clock output of the time-base timer Watchdog clear Overflow 1-bit watchdog counter Watchdog reset Maximum time 671 ms Count clock output of the time-base timer Watchdog clear Overflow 1-bit watchdog counter Watchdog reset 141 CHAPTER 6 WATCHDOG TIMER 6.5 Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer. ■ Notes on Using Watchdog Timer ● Stopping watchdog timer Once activated, the watchdog timer cannot stop until a reset generates. ● Count clock selection The count clock select bit (WDTC: CS) can only be changed writing "0101B" to the watchdog control bits (WDTC: WTE3 to WTE0) to activate the watchdog timer. Therefore, the CS bit cannot be changed by a bit operation instruction. Do not change the CS bit after activating the timer. In the sub clock mode, the main clock source oscillation is stopped, which means that the time-base timer also stops. For the watchdog timer to operate in sub clock mode, then, the watch prescaler must have been selected in advance as the count clock (WDTC: CS = 1). ● Clearing watchdog timer • Clearing the counter being used as a count clock of the watchdog timer (time-base timer or watch prescaler) also simultaneously clears the watchdog timer counter. • The watchdog timer counter is cleared on changing to sleep, stop or watch mode. ● Notes on programming When writing a program in which the watchdog timer is repeatedly cleared in the main loop, the processing time for the main loop including interrupt processing must be less than the minimum watchdog timer interval time. ● Operation in sub clock mode If the watchdog reset signal is generated in sub clock mode, operation will start in main clock mode after an oscillation stabilization wait time. Therefore, a reset signal will be output during the oscillation stabilization wait time. 142 6.6 Program Example for Watchdog Timer This section gives a program example for the watchdog timer. ■ Program Example for Watchdog Timer ● Processing description • Selects the watch prescaler as the count clock and activates the watchdog timer immediately after the program. • Clears the watchdog timer in each loop of the main program. • The processing time for the main loop, including interrupt processing, must be less than the minimum interval time of the watchdog timer (approximately 500 ms at 32.768 KHz operation). ● Coding example WDTC WDT_CLR EQU EQU 00009H 10000101B ; Address of the watchdog timer control register VECT DSEG ABS ; [DATA SEGMENT] ORG 0FFFEH RST_V DW PROG ; Set reset vector. VECT ENDS ;-----Main program--------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] PROG ; Initialization routine after a reset MOVW SP,#0280H ; Set initial value of (for interrupt processing). : Initialization of peripheral functions (interrupts), etc. : INIT MOV WDTC,#WDT_CLR ; Activate the watchdog timer. : ; Select the watch prescaler as the count clock. MOV WDTC,#WDT_CLR ; Clear the watchdog timer. : User processing (interrupt processing may occur during this cycle) : ; The loop must be executed in less than the minimum interval JMP MAIN time of the watchdog timer. ENDS ;-------------------------------------------------------------------------------------------------------------------------------------------------------------END MAIN 143 CHAPTER 6 WATCHDOG TIMER 144 CHAPTER 7 WATCH PRESCALER This chapter describes the functions and operation of the watch prescaler. 7.1 Overview of Watch Prescaler 7.2 Block Diagram of Watch Prescaler 7.3 Watch Prescaler Control Register (WPCR) 7.4 Watch Prescaler Interrupt 7.5 Operation of Watch Prescaler 7.6 Notes on Using Watch Prescaler 7.7 Program Example for Watch Prescaler 145 CHAPTER 7 WATCH PRESCALER 7.1 Overview of Watch Prescaler The watch prescaler provides interval timer functions. Six different interval times can be selected. The watch prescaler uses a 17-bit free-run counter which counts-up in sync with a sub clock generated by the clock generator. The watch prescaler also provides the timer output for the sub clock oscillation stabilization wait time and the operating clock for watchdog timer and buzzer output. ■ Interval Timer Function (Watch Interrupt) • The interval timer function generates repeated interrupts at fixed intervals with the sub clock used as the count clock. • Interrupts are generated by watch prescaler interval timer divided clock outputs. • The interval timer divided clock output (interval time) can be selected from different settings. • The watch prescaler counter can be cleared. Table 7.1-1 lists the available interval times for the watch prescaler. Table 7.1-1 Watch Prescaler Interval Time Sub clock Cycle Time Interval time 210/FCL (31.25 ms) 213/FCL (0.25 s) 1/FCL (approx. 30.5 µs) 214/FCL (0.50 s) 215/FCL (1.00 s) 216/FCL (2.00 s) 217/FCL (4.00 s) FCL: Sub clock source oscillation The values enclosed in parentheses are for a 32.768 kHz sub clock source oscillation. Note: The watch prescaler cannot be used in devices in which a single clock option has been selected. 146 ■ Clock Supply Function The watch prescaler has the following clock supply functions: • The timer output used for the sub clock oscillation stabilization wait time (one value) • The clock used for the watchdog timer (one value) • The clock used for the buzzer output (three values) Table 7.1-2 lists the cycles of the clocks that the watch prescaler supplies to various peripherals. Table 7.1-2 Clocks Supplied by Watch Prescaler Sub clock destination Sub clock cycle Remarks Sub clock oscillation stabilization wait time 215/FCL (1.00 s) Do not switch to the sub clock mode during the oscillation stabilization wait time. Watchdog timer 214/FCL (0.50 s) Count-up clock for the watchdog timer Buzzer output 23/FCL to 25/FCL (approx. 0.24 to 0.98 ms) See "CHAPTER 16 BUZZER OUTPUT". FCL: Sub clock source oscillation The values enclosed in parentheses are for a 32.768 kHz sub clock source oscillation. Note: The oscillation stabilization wait time should be used as a guideline since the oscillation cycle is unstable immediately after oscillation starts. 147 CHAPTER 7 WATCH PRESCALER 7.2 Block Diagram of Watch Prescaler The watch prescaler consists of the following four blocks: • Watch prescaler counter • Counter clear circuit • Interval timer selector • Watch prescaler control register (WPCR) ■ Block Diagram of Watch Prescaler Figure 7.2-1 Block Diagram of Watch Prescaler Watch prescaler counter 0 To watchdog timer To buzzer output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 × 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 FCL (31.25ms) (0.25s) Watchdog timer clear (0.5s) (1.0s) Interval timer selector To clock controller for the oscillation stabilization wait time selector (2.0s) (4.0s) Counter clear circuit IRQC WPCR WIF WIE — — WS2 WS1 Power-on reset Stop mode start (in sub clock mode) WS0 WCLR FCL: Sub clock source oscillation The cycle enclosed in parentheses is for a 32.768kHz sub clock oscillation ● Watch prescaler counter A 17-bit up-counter that uses the sub clock source oscillation clock as its count clock. ● Counter clear circuit In addition to being cleared by setting the WPCR register (WCLR = 0), the counter is cleared when the device changes to sub-stop mode (STBC: STP = 1) and by power-on reset. ● Interval timer selector This circuit selects one of six divided clock outputs of the watch prescaler counter as the interval timer output. The falling edge of the selected output is the event that triggers the watch interrupt. ● Watch Prescaler Control Register (WPCR) The WPCR register is used to select the interval time, clear the counter, control interrupts, and check the state of the watch prescaler. 148 7.3 Watch Prescaler Control Register (WPCR) The watch prescaler control register (WPCR) is used to select the interval time, clear the counter, control interrupts, and check state of the watch prescaler. ■ Watch Prescaler Control Register (WPCR) Figure 7.3-1 Watch Prescaler Control Register (WPCR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000BH WIF WIE — — WS2 WS1 WS0 WCLR 00--0000B R/W R/W R/W R/W R/W R/W Watch prescaler clear bit WCLR Read Write 0 — Clears the watch prescaler 1 Reading always return "1". WS2 0 0 0 0 1 1 WIE 0 1 WIF R/W : Readable/Writable — : Undefined : Initial value WS1 0 0 1 1 0 0 WS0 0 1 0 1 0 1 No effect. The bit does not change. Interrupt Cycle 31.25ms 210/FCL 0.25s 213/FCL 0.5s 214/FCL 1.0s 215/FCL 2.0s 216/FCL 4.0s 217/FCL Interrupt Request Enable Bit Disables interrupt request output Enables interrupt request output Watch interrupt request flag bit 0 Read Have no interval interrupt 1 Have interval interrupt Write Clears this bit. No effect. The bit does not change. 149 CHAPTER 7 WATCH PRESCALER Table 7.3-1 Functions of Watch Prescaler Control Register (WPCR) Bit name Function bit7 WIF: Watch interrupt request flag bit Set to "1" by the falling edge of the selected interval timer divided output. An interrupt request is output when both this bit and the interrupt request enable bit (WIE) are "1". Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. bit6 WIE: Interrupt request enable bit This bit enables or disables an interrupt request output to the CPU. An interrupt request is output when both this bit and the watch interrupt request flag bit (WIF) are "1". bit5, Undefined bits bit4 The read value is undefined. Writing to these bits has no effect on the operation. bit3 WS2, WS1, WS0: to Watch interrupt interval time bit1 selection bits Select interval timer cycle. Specify which bit of the watch prescaler counter (or which divided output) will be used for the interval timer. One of six interval times may be selected. WCLR: bit0 Watch prescaler clear bit Bit used to clear the watch prescaler counter. Writing "0" to this bit clears the counter to 00000H. Writing "1" has no effect and does not change the bit value. The read value is always "1". 150 7.4 Watch Prescaler Interrupt The watch prescaler generates an interrupt request at the falling edge of the specific divided output (interval timer function). ■ Interrupts for Interval Timer Function (Watch Interrupt) The watch prescaler counter counts up, clocked by the sub clock source oscillation. Unless the system is in main-stop mode, the watch interrupt request flag is set to "1" (WPCR: WIF = 1) at the end of the selected time interval. At this time, an interrupt request (IRQC) to the CPU is generated if the interrupt request enable bit is enabled (WPCR: WIE = 1). Write "0" to the WIF bit in the interrupt processing routine to clear the interrupt request. The WIF bit is set when the specified divided output falls, regardless of the WIE bit value. Note: When enabling an interrupt request output (WIE = 1) after wake-up from a reset, always clear the WIF bit (WIF = 0) at the same time. References: • An interrupt request is generated immediately if the WIF bit is "1" when the WIE bit is changed from disabled to enabled ("0" -> "1"). • The WIF bit is not set if the counter cleared (WPCR: WCLR = 0) at the same time as an overflow on the specified bit occurs. ■ Oscillation Stabilization Wait Time and Watch Interrupt If the interval time is set shorter than the sub clock oscillation stabilization wait time, a watch interrupt request from the watch prescaler (WPCR: WIF = 1) is generated at the time when CPU wakes up from substop mode by an external interrupt. In this case, disable the watch prescaler interrupt (WPCR: WIE = 0) when changing to sub-stop mode. ■ Register and Vector Table for Watch Prescaler Interrupt Table 7.4-1 lists the register and vector table for watch prescaler interrupt. Table 7.4-1 Register and Vector Table for Watch Prescaler Interrupt Interrupt level setting register Vector table address Interrupt Register IRQC ILR4 (007EH) Setting bits LC1 (bit1) LC0 (bit0) Upper Lower FFE2H FFE3H See "3.4.2 Interrupt Processing" for details on the interrupt operations. 151 CHAPTER 7 WATCH PRESCALER 7.5 Operation of Watch Prescaler The watch prescaler has the interval timer function and the clock supply function. ■ Operation of Interval Timer Function (Watch Prescaler) Figure 7.5-1 shows the settings required to operate as the interval timer function. Figure 7.5-1 Interval Timer Function Settings WPCR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WIF WIE — — WS2 WS1 WS0 WCLR 0 1 0 : Used bit 1: Set "1" 0: Set "0" Provided the sub clock is oscillating, the watch prescaler 17-bit counter continues to count-up using the sub clock as its count clock. After being cleared (WCLR = 0), the counter restarts counting-up from "00000H". When the counter reaches a full count of "1FFFFH", the next count takes it "00000H", and it continues to count-up. As the count proceeds, a falling edge will eventually occur at the selected divided clock output. At this time, unless the system is in main stop mode, the watch prescaler sets the watch interrupt request flag bit (WIF) to "1". Consequently, the watch prescaler generates watch interrupt requests at fixed intervals (the selected interval time), based on the time that the counter is cleared. ■ Operation of Clock supply Function The watch prescaler is also used as a timer to generate the sub clock oscillation stabilization wait time. The time between the counter cleared state and the falling edge of the MSB output is used the sub clock oscillation stabilization wait time (215/FCL, where FCL is sub clock source oscillation). The watch prescaler also provides the clock for the watchdog timer and buzzer output. Clearing the watchdog timer counter affects the operation of the buzzer output. When the watch prescaler is selected as the clock source for the watchdog timer (WDTC: CS = 1) both counters are cleared simultaneously. 152 ■ Operation of Watch Prescaler Figure 7.5-2 shows counter states when the interval timer is operating in sub clock mode and the system goes into the sleep and stop modes, and when there is a counter clear request. Figure 7.5-2 Operation of Watch Prescaler Power-on reset Counter value 1FFFFH 17FFFH Cleared by changing to sub-stop mode. 0FFFFH 07FFFH 00000H Sub clock oscillation stabilization wait time Interval cycle Sub clock oscillation stabilization wait time Cleared by the interrupt processing routine. Counter clear (WPCR: WCLR = 0) WIF bit WIE bit SLP bit (STBC register) Sub clock sleep mode Sub-stop mode Wake-up from sleep by IRQC STP bit (STBC register) Wake-up from stop mode by an external interrupt For the case when the interrupt interval time selection bits in the watch prescaler control register (WPCR: WS2, WS1, WS0) are set to "011B" (215/FCL). 153 CHAPTER 7 WATCH PRESCALER 7.6 Notes on Using Watch Prescaler This section lists points to note when using the watch prescaler. The watch prescaler cannot be used in devices in which the single-clock option has been selected. ■ Notes on Using Watch Prescaler ● Notes on setting bits by program The system cannot recover from interrupt processing if the interrupt request flag bit (WPCR: WIF) is "1" and the interrupt request enable bit is enabled (WPCR: WIE = 1). Always clear the WIF bit. ● Clearing Watch prescaler In addition to being cleared by the watch prescaler clear bit (WPCR: WCLR = 0), the watch prescaler is cleared wherever the sub clock oscillation stabilization wait time is required. When the watch prescaler is selected as a count clock of the watchdog timer (WDTC: CS = 1), clearing the watch prescaler also clears the watchdog timer. ● Using as timer for oscillation stabilization wait time As the sub clock source oscillation is stopped when the power is turned on and during sub-stop mode, the watch prescaler provides the oscillation stabilization wait time after the oscillator starts. Do not switch clock modes from main clock to sub clock during this wait time (immediately after power on, etc.) The sub clock oscillation stabilization wait time is fixed. See "3.6.5 Oscillation Stabilization Wait Time" for details. ● Notes on watch interrupt In main-stop mode, the watch prescaler counter operates, but no watch interrupt is generated. ● Notes on peripheral functions that provides a clock supply from watch prescaler As the clock derived from the watch prescaler restarts output from the its initial state when the watch prescaler counter is cleared, the "H" level may be shorter or the "L" level longer by a maximum of half cycle. The clock of the watchdog timer also restarts output from its initial state. However, as the watchdog timer counter is cleared at the same time, the watchdog timer operates in normal cycle. Figure 7.6-1 shows the effect on the buzzer output of clearing the watch prescaler. 154 Figure 7.6-1 Effect on Buzzer Output Due to Clearing of Watch Prescaler Counter value (bit4:0) 001FH 0010H 0000H Clearing the counter by the program (WPCR: WCLR = 0) Clock supplied to the buzzer output For the case when the buzzer selection bits in the buzzer register (BUZR: BZ2, BZ1, BZ0) are set to "101B". (Divide-by-32 sub clock source oscillation, 1024 Hz output at 32.768 kHz operation). 155 CHAPTER 7 WATCH PRESCALER 7.7 Program Example for Watch Prescaler This section gives program example for the watch prescaler. ■ Program Example for the Watch Prescaler ● Processing description Generates repeated watch interrupts at 215/FCL (FCL = sub clock source oscillation) intervals. At this time, the interval time is 1 second (at 32.768 kHz operation). ● Coding example WPCR WIF ILR4 INT_V EQU 000BH ; Address of watch prescaler control register EQU WPCR:7 ; Define the watch interrupt request flag bit. EQU 007EH ; Address of the interrupt level setting register 2 DSEG ABS ; [DATA SEGMENT] ORG 0FFE2H IRQC DW WARI ; Set interrupt vector. INT_V ENDS ;------------ Main program -----------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : CLRI ; Disable interrupts. MOV ILR4, #11111110B ; Set interrupt priority (level 2). MOV WPCR, #01000110B ; Clear interrupt request flag, enable interrupt request output, select 215/FCL, and clear watch prescaler. SETI ; Enable interrupts. : ;------------ Interrupt program -----------------------------------------------------------------------------------------WARI CLRB WIF ; Clear interrupt request flag. PUSHWA XCHW A,T PUSHWA : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------------------------------------------------------------------END 156 CHAPTER 8 8-BIT PWM TIMER This chapter describes the functions and operation of the 8-bit PWM timer. 8.1 Overview of 8-bit PWM Timer 8.2 Block Diagram of 8-bit PWM Timer 8.3 Structure of 8-bit PWM Timer 8.4 Registers of 8-bit PWM Timer 8.5 8-bit PWM Timer Interrupts 8.6 Operation of Interval Timer Function 8.7 Operation of PWM Timer Function 8.8 States in Each Mode during 8-bit PWM Timer Operation 8.9 Notes on Using 8-bit PWM Timer 8.10 Program Example for 8-bit PWM Timer 157 CHAPTER 8 8-BIT PWM TIMER 8.1 Overview of 8-bit PWM Timer The 8-bit PWM timer can be selected to function as either an interval timer or PWM timer with 8-bit resolution. The interval timer function counts-up in sync with one of four internal count clocks. Therefore, an 8-bit interval timer time can be set and the output can be used to generate variable frequency square waves. Also, the 8-bit PWM timer can be used as a D/A converter by connecting the PWM output to low pass filter. ■ Interval Timer Function (Square Wave Output Function) The interval timer function generates repeated interrupts at variable time intervals. Also, as the 8-bit PWM timer can invert the output level of the pin (PWM) each time an interrupt is generated, the 8-bit PWM timer can output a variable frequency square waves. • The interval timer can operate with a cycle among 1 and 28 times the count clock cycle. • The count clock can be selected from four different clocks. Table 8.1-1 lists the range for the interval time and square wave output. Table 8.1-1 Interval Time and Square Wave Output Range Count clock cycle Interval time Square wave output (Hz) 1 1 tinst 1 tinst to 28 tinst 1/(2 tinst) to 1/(29 tinst) 2 8 tinst 23 tinst to 211 tinst 1/(24 tinst) to 1/(212 tinst) 3 16tinst 24 tinst to 212 tinst 1/(25 tinst) to 1/(213 tinst) 4 64 tinst 26 tinst to 214 tinst 1/(27 tinst) to 1/(215 tinst) Internal count clock tinst: Instruction cycle (affected by clock mode, etc.) [Calculation example for the interval time and square wave frequency] In this example, the main clock source oscillation (FCH) is 12.5 MHz, the PWM compare register (COMR) value is set to "DDH (221)", and the count clock cycle is set to 1 tinst. In this case, the interval time and the frequency of the square wave output from the PWM pin (where the PWM timer operates continuously and the value of the COMR register is constant) are calculated as follows. Assume that the main clock mode and its highest clock speed has been selected via the system clock control register (SYCC: SCS = 1, CS1 = 1, CS0 = 1, 1 instruction cycle = 4/FCH). Interval time = (1 × 4/FCH) × (COMR register value + 1) = (4/12.5 MHz) × (221 + 1) = 71.04 µs Output frequency = FCH/(1 × 8 × (COMR register value +1)) = 12.5 MHz/(8 × (221 + 1)) = approx. 7.04 kHz 158 ■ PWM Timer Function The PWM timer function has 8-bit resolution and can control the "H" and "L" widths of one cycle. • As the resolution is 1/256, pulses can be output with duty ratios between 0 and 99.6%. • The cycle of the PWM wave can be selected from four types. • The PWM timer can be used as a D/A converter by connecting the output to a low pass filter. Table 8.1-2 lists the available PWM wave cycles for the PWM timer function. Figure 8.1-1 shows a configuration example of D/A converter. Table 8.1-2 Available PWM Wave Cycle for PWM Timer Function 1 2 3 4 Internal count clock Count clock cycle 1 tinst 8 tinst 16 tinst 64 tinst PWM wave cycle 28 tinst 211 tinst 212 tinst 214 tinst Figure 8.1-1 Configuration Example of D/A Converter Using PWM Output and Low Pass Filter tinst: Instruction cycle (affected by clock mode, etc.) PWM output Analog output (Va) PWM R C Analog output waveform Va Va Tr Vcc The analog output voltage and the PWM output waveform are related as follows:Va/Vcc = TH/T Tr is the time it takes the output to rise to a constant voltage level. t PWM output waveform Vcc 0 TL TH T Note: Interrupt requests are not generated during operation of the PWM function. 159 CHAPTER 8 8-BIT PWM TIMER 8.2 Block Diagram of 8-bit PWM Timer The 8-bit PWM timer consists of the following six blocks: • Count clock selector • 8-bit counter • Comparator circuit • PWM generator and output controller • PWM compare register (COMR) • PWM control register (CNTR) ■ Block Diagram of 8-bit PWM Timer Figure 8.2-1 Block Diagram of 8-bit PWM Timer Internal data bus CNTR P/TX COMR — P1 P0 TPE TIR OE TIE PWM compare register Start 8-bit counter CLK Clear IRQ9 Overflow 8 Latch 8 Count clock selector Comparator circuit Timer/PWM X1 X8 PWM generator and output controller X 16 Output X 64 P20/PWM tinst: Instruction cycle 160 Pin Output pin control bit 1 tinst ● Count clock selector Selects a count-up clock for the 8-bit counter from the four internal count clocks. ● 8-bit counter The 8-bit counter counts-up on the count clock selected by the count clock selector. ● Comparator circuit The comparator circuit has a latch to hold the COMR register value. The circuit latches the COMR register value when the 8-bit counter value is "00H". The comparator circuit compares the 8-bit counter value with the latched COMR register value, and detects when a match occurs. ● PWM generator and output controller When a match is detected during interval timer operation, an interrupt request is generated and, if the output pin control bit (CNTR: OE) is "1", the output controller inverts the output level of the PWM pin. in this case, the 8-bit counter is cleared. When a match is detected during PWM timer operation, the PWM generator changes the output level of the PWM pin from "H" to "L". The pin is set back to the "H" level when the next overflow occurs on the 8-bit counter. ● PWM compare register (COMR) The COMR register is used to set the value that is compared with the value of the 8-bit counter. ● PWM control register (CNTR) The CNTR register is used to select the operating mode, enable or disable operation, set the count clock, control interrupts, and check the PWM status. Setting the operation to PWM timer mode (P/TX = 0) disables clearing of the 8-bit counter and generation of interrupt requests IRQ9 when the comparator circuit detects a match. 161 CHAPTER 8 8-BIT PWM TIMER 8.3 Structure of 8-bit PWM Timer This section describes the pin, pin block diagram, register source, and interrupts of the 8-bit PWM timer. ■ Pin of 8-bit PWM Timer The 8-bit PWM timer uses the P20/PWM pin. This pin can function either as a general-purpose I/O port (P20) and as the interval timer or PWM timer output. When the PWM timer function is selected, the pin outputs the PWM wave. Setting the output pin control bit (CNTR: OE) to "1" makes Pin P20/PWM the output-only pin for 8-bit PWM timer. Once this has been done, the pin performs its PWM function regardless of the state of the port data register output latch data (PDR2: bit0). ■ Block Diagram of 8-bit PWM Timer Pin Figure 8.3-1 Block Diagram of 8-bit PWM Timer Pin From PWM timer output From output control bit (CNTR: OE) PDR (Port data register) Stop, watch mode Pull-up resistor Approx. 50 kΩ Internal data bus PDR read Pull-up resistor control register P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin (Port direction register) N-ch DDR DDR write DDR read Stop, watch mode (SPL = 1) Watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 162 P20/PWM 8.4 Registers of 8-bit PWM Timer This section describes the registers of the 8-bit PWM timer. Figure 8.4-1 Registers of 8-bit PWM Timer CNTR (PWM control register) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0034H P/TX — P1 P0 TPE TIR OE TIE 0-000000B R/W R/W R/W R/W R/W R/W bit5 bit4 bit3 bit2 bit1 bit0 R/W COMR (PWM compare register) Address bit7 bit6 Initial value XXXXXXXXB 0035H W W W W W W W W R/W: Readable/Writable W : Write only — : Undefined X : Undefined value Note: As the PWM compare register (COMR) is write only, the bit manipulation instructions cannot be used. ■ 8-bit PWM Timer Interrupt Source IRQ9:For the interval timer function, the 8-bit PWM timer generates an interrupt request if interrupt request output is enabled (CNTR: TIE = 1) when the counter value matches the value set in the COMR register. (No interrupt requests are generated when the PWM function is operating.) 163 CHAPTER 8 8-BIT PWM TIMER 8.4.1 PWM Control Register (CNTR) The PWM control register (CNTR) is used to select the operating mode of the 8-bit PWM timer (interval timer operation or PWM timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit PWM timer. ■ PWM Control Register (CNTR) Figure 8.4-2 PWM Control Register (CNTR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0034H P/TX — P1 P0 TPE TIR OE TIE 0-000000B R/W R/W R/W R/W R/W R/W R/W TIE Interrupt request enable bit 0 Disables interrupt request output. 1 Enables interrupt request output. OE Output pin control bit 0 Functions as a general-purpose port (P20). 1 Functions as the interval timer/PWM timer output pin (PWM). Interrupt request flag bit Read TIR Interval timer function 0 Counter value and set value do not match. 1 Counter value and set value match. TPE No change Clears this bit. No effect. The bit does not change. Counter operation enable bit 0 Stops count operation. 1 Starts count operation. P1 P0 0 0 0 1 1 0 1 1 P/TX Clock selection bits 1 tinst * Internal count clock 8 tinst * 16 tinst * 64 tinst * Operating mode selection bit 0 Operates as an interval timer. 1 Operates as a PWM timer. R/W : Readable/Writable — : Undefined X : Undefined value : Initial value 164 Write PWM timer function * : tinst : Instruction cycle Table 8.4-1 Functions of Bits in PWM Control Register (CNTR) Bit name Function bit7 This bit switches between the interval timer function (P/TX = 0) and PWM timer function (P/TX =1). P/TX: Note: Operating mode selection bit Write to this bit when the counter operation is stopped (TPE = 0), interrupts are disabled (TIE = 0), and the interrupt request flag bit is cleared (TIR = 0). bit6 Undefined bit bit5, P1, P0: bit4 Clock selection bits bit3 The read value is undefined. Writing to this bit has no effect on the operation. These bits select the count clock for the interval timer function and PWM timer function. These bits can select the count clock from four internal count clocks. Note: Do not change P1 and P0 when the counter is operating (TPE = 1). This bit activates or stops operation of the PWM timer function and interval timer function. TPE: Writing "1" to this bit starts the count operation. Writing "0" to this bit stops the count and clears the Counter operation enable bit counter to "00H". bit2 TIR: Interrupt request flag bit For the interval timer function: This bit is set to "1" when the counter and PWM compare register (COMR) values match. An interrupt request is output to the CPU when both this bit and the interrupt request enable bit (TIE) are "1". For the PWM timer function: Interrupt requests are not generated. Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. bit1 OE: Output pin control bit The P20/PWM pin functions as a general-purpose port (P20) when this bit is set to "0", and a dedicated pin (PWM) when this bit is set to "1". The PWM pin outputs a square wave when the interval timer function is selected and a PWM waveform when the PWM timer function is selected. bit0 TIE: Interrupt request enable bit This bit enables or disables interrupt request output to the CPU. An interrupt request is output when both this bit and the interrupt request flag bit (TIR) are "1". 165 CHAPTER 8 8-BIT PWM TIMER 8.4.2 PWM Compare Register (COMR) The PWM compare register (COMR) sets the interval time for the interval timer function. The register value sets the "H" width of the pulse for the PWM timer function. ■ PWM Compare Register (COMR) Figure 8.4-3 shows the bit structure of the PWM compare register. As the register is write-only, bit manipulation instructions cannot be used. Figure 8.4-3 PWM Compare Register (COMR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB 0035H W W W W W W W W W: Write only X: Undefined value ● Interval timer operation This register is used to set the value to be compared with the counter value. The register specifies the interval time. The counter is cleared when the counter value matches the value set in this register, and the interrupt request flag bit is set to "1" (CNTR: TIR = 1). If data is written to the COMR register during counter operation, the new value applies from the next cycle (after the next match is detected). Reference: The COMR setting for interval timer operation can be calculated using the following formula. The instruction cycle time is affected by the clock mode, and the speed-shift selection. COMR register value = interval time/(count clock cycle × instruction speed-shifting cycle) - 1 ● PWM timer operation This register is used to set the value to be compared with the counter value. The register therefore sets the "H" width of the pulse. The PWM pin outputs an "H" level until the counter value matches the value set in this register. From the match until the counter value overflows, the PWM pin outputs an "L" level. If data is written to the COMR register during counter operation, the new value applies from the next cycle (after the next overflow). 166 Note: In PWM timer operation, the COMR setting and the PWM cycle time can be calculated using the following formulas. The instruction cycle time is affected by the clock mode, and the speed-shift selection. COMR register value = duty ratio (%) × 256 PWM wave cycle = count clock cycle × instruction cycle × 256 167 CHAPTER 8 8-BIT PWM TIMER 8.5 8-bit PWM Timer Interrupts The 8-bit PWM timer can generate an interrupt request when a match is detected between the counter value and PWM compare register value for the interval timer function. Interrupt requests are not generated for the PWM timer function. 8-bit PWM timer generates the IRQ9 as an interrupt request. ■ Interrupts for Interval Timer Function The counter value is counted-up from "00H" on the selected count clock. When the counter value matches the PWM compare register (COMR) value, the interrupt request flag bit (CNTR: TIR) is set to "1". At this time, an interrupt request to the CPU is generated if the interrupt request enable bit is enabled (CNTR: TIE = 1). Write "0" to the TIR bit in the interrupt processing routine to clear the interrupt request. The TIR bit is set to "1" when the counter value matches the set value, regardless of the value of the TIE bit. Note: The TIR bit is not set if the counter is stopped (CNTR: TPE = 0) at the same time as the counter value matches the COMR register value. An interrupt request is generated immediately if the TIR bit is "1" when the TIE bit is changed from disabled to enabled ("0" -> "1"). ■ Registers and Vector Tables for 8-bit PWM Timer Interrupts Table 8.5-1 Registers and Vector Tables for 8-bit PWM Timer Interrupts Interrupt level setting register Vector table address Interrupt Register 8-bit PWM Timer IRQ9 ILR3 (007DH) Setting bits L91 (bit3) L90 (bit2) See "3.4.2 Interrupt Processing" for details on the interrupt operation. 168 Upper Lower FFE8H FFE9H 8.6 Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8-bit PWM timer. ■ Operation of Interval Timer Function Figure 8.6-1 shows the settings required to operate as an interval timer function. Figure 8.6-1 Interval Timer Function Settings CNTR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P/TX — P1 P0 TPE TIR OE TIE 0 COMR : Used bit 1 : Set "1". 0 : Set "0". 1 Sets interval time (compare value). On activation, the counter starts counting-up from "00H" on the rising edge of the selected count clock. When the counter value matches the value set in the COMR register (compare value), the PWM timer inverts the level of the PWM pin (PWM) on the next rising edge of the count clock, clears the counter, sets the interrupt request flag bit (CNTR: TIR = 1), and restarts counting from "00H". Figure 8.6-2 shows the operation of the 8-bit PWM timer. Figure 8.6-2 Operation of 8-bit PWM Timer Counter value Compare value (FFH) Compare value (80H) FFH 80H 00H Time Timer cycle COMR value (FFH) COMR value modified (FFH →80H)* Cleared by the program TIR bit TPE bit OE bit PWM pin When the output pin control bit (OE) is "0", the pin operates as a general-purpose I/O port (P20). *: If the PWM compare register (COMR) value is modified during counter operation, the new value is used from the next cycle. Do not change the count clock cycle (CNTR: P1, P0) during operation of the interval timer function (CNTR: TPE = 1). Setting the COMR register value to "00H" causes the PWM pin output to be inverted with the cycle of the selected count clock. When the counter is stopped (CNTR: TPE = 0) while the interval timer function is selected, the PWM pin outputs an "L" level. 169 CHAPTER 8 8-BIT PWM TIMER 8.7 Operation of PWM Timer Function This section describes the operation of the PWM timer function of the 8-bit PWM timer. ■ Operation of PWM Timer Function Figure 8.7-1 shows the settings required to operate as the PWM timer function in the 8-bit PWM mode. Figure 8.7-1 PWM Timer Function Settings CNTR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P/TX — P1 P0 TPE TIR OE TIE 1 × 1 × 1 COMR Sets “H” width of pulse (compare value). : Used bit × : Unused bit 1 : Set "1". On activation, the counter starts counting-up from "00H" on the rising edge of the selected count clock. The PWM pin (PWM waveform) outputs an "H" level until the counter value matches the value set in the COMR register. From the match until the counter value overflows (FFH -> 00H), the PWM pin outputs an "L" level. Figure 8.7-2 shows the PWM waveforms output from the PWM pin. Figure 8.7-2 Example of PWM Waveform Output (PWM Pin) For COMR register value of "00H" (duty ratio = 0%) Counter value 00H PWM waveform FFH00H H L For COMR register value of "80H" (duty ratio = 50%) Counter value 00H PWM waveform 80H FFH00H H L For COMR register value of "FFH" (duty ratio = 99.6%) Counter value 00H FFH00H H PWM waveform L One count width Notes: • Do not change the count clock cycle (CNTR: P1, P0) during operation of the PWM timer function (CNTR: TPE = 1). • When the PWM timer function is selected, the PWM pin maintains its existing level when the counter is stopped (CNTR: TPE = 0). 170 8.8 States in Each Mode during 8-bit PWM Timer Operation This section describes the operation of the 8-bit PWM timer when the device changes to sleep or stop mode or an operation halt request occurs during operation. ■ Operation during Standby Mode or Operation Halt Figure 8.8-1 and Figure 8.8-2 show the counter value states when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or PWM timer function. The counter halts and maintains its current value when the device changes to stop mode. Operation starts again from the stored counter value after wake-up from stop mode by an external interrupt. Therefore, the first interval time or PWM wave cycle does not match the set value. Always initialize the 8-bit PWM timer after wake-up from stop mode. ● For interval timer function Figure 8.8-1 Counter Operation during Standby Modes or Operation Halt (For Interval Timer Function) Counter value Cleared by the operation halt. COMR value (FFH) FFH 00H Timer cycle Stop request Oscillation stabilization wait time Time Cleared by the program Operation halts Operation restarts TIR bit TPE bit PWM pin (OE = 1) * "L" level while counter is stopped. Sleep mode SLP bit Stop mode (STBC register) Wake-up from sleep mode by IRQ9. STP bit (STBC register) Wake-up from stop mode by an external interrupt. * : The PWM pin goes to the high-impedance state during stop mode if the pin state specification bit in the standby control register (STBC: SPL) is "1" and the PWM pin is not set to with a pull-up resistor. When the SPL bit is "0", the pin maintains its value prior to changing to stop mode. 171 CHAPTER 8 8-BIT PWM TIMER ● For PWM timer function Figure 8.8-2 Operation during Standby Modes or Operation Halt (For PWM Timer Function) 00H 00H 00H 00H 00H PWM pin (PWM waveform) * Maintains the level prior to halting. TPE bit Operation halts Operation restarts Sleep mode SLP bit (STBC register) Wake-up from sleep mode by an interrupt other than IRQ9 (IRQ9 is not generated). Stop mode STP bit (STBC register) Oscillation stabilization wait time Wake-up from stop mode by an external interrupt. * : The PWM pin (PWM) goes to the high-impedance state during stop mode if the pin state specification bit in the standby control register (STBC: SPL) is "1" and the PWM pin is not set to with a pull-up resistor. When the SPL bit is "0", the pin maintains its value prior to changing to stop mode. 172 8.9 Notes on Using 8-bit PWM Timer This section lists points to note when using the 8-bit PWM Timer. ■ Notes on Using 8-bit PWM Timer ● Error Activating the counter by program is not synchronized with the start of counting-up using the selected count clock. Therefore, the time from activating the counter until a match with the PWM compare register (COMR) is detected may be shorter than the theoretical time by a maximum of one cycle of the count clock. Figure 8.9-1 shows the error that occurs on starting counter operation. Figure 8.9-1 Error on Starting Counter Operation Counter value 00H 01H 02H 03H 04H Count clock One cycle Error Cycle for 00H Counter activate ● Notes on setting by program • Do not change the count clock cycle (CNTR: P1, P0) when the interval timer function or PWM timer function is operating (CNTR: TPE = 1). • Stop the counter (CNTR: TPE = 0), disable interrupts (TIE = 0), and clear the interrupt request flag (TIR = 0) before switching between the interval timer function and PWM timer function (CNTR: P/TX). • Interrupt processing cannot return if the interrupt request flag bit (CNTR: TIR) is "1" and the interrupt request enable bit is enabled (CNTR: TIE = 1). Always clear the TIR bit. • The TIR bit is not set if the counter is disabled (CNTR: TPE = 0) at the same time as the counter and COMR register values match. 173 CHAPTER 8 8-BIT PWM TIMER 8.10 Program Example for 8-bit PWM Timer This section gives program examples for the 8-bit PWM Timer. ■ Program Example for Interval Timer Function ● Processing description • Generates repeated interval timer interrupts at 5 ms intervals. • Outputs a square wave to the PWM pin that inverts after each interval time. • With a main clock master oscillation FCH of 12.5 MHz, and the highest speed clock selected by the speed-shift function (1 instruction cycle time = 4/FCH), the COMR register is set for an interval time of approximately 5 ms. (An internal clock period of 64 tinst is selected as the count clock.) The COMR register setting is calculated as follows: COMR register value = 5 ms/(64 × 4/12.5 MHz) - 1 = 243.0 (0F3H) 174 ● Coding example CNTR COMR EQU EQU 0034H 0035H ; Address of the PWM control register ; Address of the PWM compare register TPE TIR EQU EQU CNTR:3 CNTR:2 ; Define the counter operation enable bit. ; Define the interrupt request flag bit. ILR3 EQU 007DH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFE8H IRQ9 DW WARI ; Set interrupt vector. INT_V ENDS ;-----Main program--------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : CLRI ; Disable interrupts. CLRB TPE ; Stop counter operation. MOV ILR3,#11110111B ; Set interrupt level (level 1). MOV COMR,#0F3H ; Value compared with the counter value (interval time) MOV CNTR,#00111011B ; Operate interval timer, select 64 tinst, start counter operation, clear interrupt request flag, enable PWM pin output, enable interrupt request output. SETI ; Enable interrupts. : ;-----Interrupt program---------------------------------------------------------------------------------------------------------------------------------WARI CLRB TIR ; Clear interrupt request flag. PUSHW A XCHW A,T ; Save A and T. PUSHW A : User processing : POPW A XCHW A,T ; Restore A and T. POPW A RETI ENDS ;-------------------------------------------------------------------------------------------------------------------------------------------------------------END ■ Program Example for PWM Timer Function ● Processing description • Generates a PWM wave with a duty ratio of 50%. Then, changes the duty ratio to 25%. • Does not generate interrupts. • For a 12.5 MHz source oscillation, (FCH), and the highest speed clock selected by the speed-shift function (1 instruction cycle time = 4/FCH), selecting the interval 16 tinst count clock gives a PWM wave cycle of 16 × 4/12.5 MHz × 256 = 1.31 ms. • The following shows the COMR register value required for a duty ratio of 50%: COMR register value = 50/100 × 256 = 128 (080H) 175 CHAPTER 8 8-BIT PWM TIMER ● Coding example CNTR COMR EQU EQU 0034H 0035H ; Address of the PWM control register ; Address of the PWM compare register TPE EQU CNTR:3 ; Define the counter operation enable bit. ;-----Main program--------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB TPE ; Stop counter operation. MOV COMR,#80H ; Set "H" width of pulse. Duty ratio = 50% MOV CNTR,#10101010B ; Operate PWM timer, select 16 tinst, start counter operation, clear interrupt request flag, enable PWM pin output, and disable interrupt request output. : : ; Change the duty ratio to 25% (effective from the next PWM MOV COMR,#40H wave cycle). : ENDS ;-------------------------------------------------------------------------------------------------------------------------------------------------------------END 176 CHAPTER 9 PWC TIMER This chapter describes the functions and operation of the PWC Timer (pulse width count timer). 9.1 Overview of Pulse Width Count Timer 9.2 Block Diagram of Pulse Width Count Timer 9.3 Structure of Pulse Width Count Timer 9.4 Registers of Pulse Width Count Timer 9.5 Pulse Width Count Timer Interrupts 9.6 Operation of Interval Timer Function 9.7 Operation of Pulse Width Measurement Function 9.8 States in Each Mode during Pulse Width Count Timer Operation 9.9 Notes on Using Pulse Width Count Timer 9.9 Notes on Using Pulse Width Count Timer 9.10 Program Example for Timer Function of Pulse Width Count Timer 9.11 Program Example for Pulse Width Measurement Function of Pulse Width Count Timer 177 CHAPTER 9 PWC TIMER 9.1 Overview of Pulse Width Count Timer The pulse width count timer (PWC) can be selected to function as either an interval timer or the pulse width measurement. The interval timer function counts down in sync with one of three internal count clocks. The pulse width measurement function measures the width of pulses input to an external pin. ■ Interval Timer Function The interval timer function generates repeated interrupts at variable time intervals. • The interval timer can operate with a cycle among 1 and 28 times the internal count clock cycle. • The internal count clock can be selected from three different clocks. • Two operating modes are available: reload timer mode (continuous operation) and one-shot mode (onetime operation). Table 9.1-1 lists the available interval time and square wave output ranges. Table 9.1-1 Interval Time and Square Wave Output Range Internal count clock cycle Interval time 1 tinst 1 tinst to 28 tinst 4 tinst 22 tinst to 210 tinst 32 tinst 25 tinst to 213 tinst tinst: Instruction cycle (affected by clock mode, etc.) Note: The following shows an example of the interval time and square wave output frequency. For an 12.5 MHz main clock source oscillation (FCH), a PWC reload buffer register (PLBR) value of "DDH (221)", and a count clock cycle of one instruction cycle, the interval time and square wave output frequency are calculated as follows: Interval time = (1 × 4/FCH) × (PLBR register value) = (4/12.5 MHz) × 221 = approx. 70.7 µs Output frequency = FCH/(1 x 8 × (PLBR register value) = 12.5 MHz/ (8 × 221) = approx. 7.1 kHz PLBR register value of "00H" is assumed as 256. 178 ■ Pulse Width Measurement Function The pulse width measurement function can measure the "H" width, "L" width, and one-cycle width of pulses input to an external pin (PWC pin). • The PWC can perform continuous pulse width measurement. • The measurement speed (internal count clock) can be selected from three different speeds. • The width of long input pulses can be measured using an interrupt processing routine. Table 9.1-2 lists the available pulse widths measured by the pulse width measurement function. Table 9.1-2 Pulse Width Measured by Pulse Width Measurement Function Internal count clock cycle Interval time 1 tinst 1 tinst to 28 tinst 4 tinst 22 tinst to 210 tinst 32 tinst 25 tinst to 213 tinst tinst: Instruction cycle (affected by clock mode, etc.) 179 CHAPTER 9 PWC TIMER 9.2 Block Diagram of Pulse Width Count Timer The pulse width count timer consists of the following six blocks: • Count clock selector • 8-bit down-counter • Input pulse edge detector • PWC reload buffer register (PLBR) • PWC pulse width control register 1 (PCR1) • PWC pulse width control register 2 (PCR2) ■ Block Diagram of Pulse Width Count Timer Figure 9.2-1 Block Diagram of Pulse Width Count Timer IRQA PCR1 Internal data bus EN — IE — — UF IR BF RM TO C1 C0 W2 W1 W0 PCR2 FC P05/INT25/PWC Input pulse edge 8-bit down-counter detector Count clock selector PLBR tinst: Instruction cycle 180 X1 X4 X32 Pin 1 tinst ● Count clock selector Selects a count-down clock for the 8-bit down-counter from the three available internal count clocks. ● 8-bit down-counter The 8-bit down-counter starts counting from the value set in the PWC reload buffer register (PLBR) when operating as an interval timer, and from FFH when performing pulse width measurement. When an underflow (00H -> FFH) occurs, the counter inverts the timer output bit (PCR2: TO). ● Input pulse edge detector Operates when the pulse width measurement function is selected, and starts or stops the 8-bit down-counter when an edge input from the PWC pin matches the edge specified by the PWC pulse width control register 2 (PCR2). ● PWC reload buffer register (PLBR) When operating in reload timer mode of the interval timer function, the PLBR register value is re-loaded to the counter and the count continues whenever a counter value underflow (00H -> FFH) occurs. When performing pulse width measurement, the value of the 8-bit down-counter is transferred to the PLBR register when measurement completes. ● PWC pulse width control register1, 2 (PCR1, PCR2) These registers are used to select the function, set operating conditions, enable or disable operation, control interrupts, and to check the PWC status. 181 CHAPTER 9 PWC TIMER 9.3 Structure of Pulse Width Count Timer This section describes the pins, pin block diagram, registers, and interrupt source of the pulse width count timer. ■ Pins of Pulse Width Count Timer The pulse width count timer uses the P05/INT25/PWC pin, which can function either as general-purpose I/O port (P05), or as the measured pulse input (PWC), and external interrupt input (INT25). PWC:The pulse width measurement function measures the pulse widths input to this pin. Set the pin as an input port in the port direction register (DDR0: bit5 = 0) when using as the PWC pin for the pulse width measurement function. ■ Block Diagram of Pulse Width Count Timer Pins Figure 9.3-1 Block Diagram of Pulse Width Count Timer Pins To PWC Timer input Pull-up resistor Approx. 50 kΩ PDR (Port data register) Stop, watch mode Pull-up resistor control register Internal data bus PDR read P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin DDR N-ch P05/INT25/PWC DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Reference: When pull-up resistor is selected in pull-up resistor control register, the states of these pins in stop mode (SPL=1) are in "H" level (pull-up state) rather than high impedance. However, during reset, pull-up is unavailable and will be in high impedance state. 182 9.4 Registers of Pulse Width Count Timer This section describes the registers of the pulse width count timer. Figure 9.4-1 Registers of Pulse Width Count Timer PCR1 (PWC pulse width control register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0031H EN — IE — — UF IR BF 0-0--000B R/W R/W R R/W R/W PCR2 (PWC pulse width control register 2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0032H FC RM TO C1 C0 W2 W1 W0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit4 bit3 bit2 bit1 bit0 PLBR (PWC reload buffer register) Address bit7 bit6 bit5 Initial value XXXXXXXXB 0033H R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R ……For the interval timer function ……For the pulse width measurement function R/W: Readable/Writable R : Read only — : Undefined X : Undefined value ■ Pulse Width Count Timer Interrupt Source IRQA: For both the interval timer and pulse width measurement functions, the PWC generates an interrupt request if interrupt request output is enabled (PCR1: IE = 1) when the counter value underflows (00H -> FFH). Also, for the pulse width measurement function, the PWC also generates an interrupt request for the pulse width measurement function if interrupt request output is enabled (PCR1: IE = 1) when pulse width measurement completes or a pulse width measurement value remains in the PLBR register. 183 CHAPTER 9 PWC TIMER 9.4.1 PWC Pulse Width Control Register 1 (PCR1) The PWC pulse width control register 1 (PCR1) is used to enable or disable functions, control interrupts and check the state of the pulse width count timer. ■ PWC Pulse Width Control Register 1 (PCR1) Figure 9.4-2 PWC Pulse Width Control Register 1 (PCR1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0031H EN — IE — — UF IR BF 0-0--000B R/W R/W R R/W R/W BF Buffer full flag bit 0 No pulse width measurement value 1 Pulse width measurement value IR Measurement completion interrupt request flag bit Read Write 0 Pulse width measurement not complete. Clears this bit. 1 Pulse width measurement complete. UF No effect. The bit does not change. Underflow (00H →FFH) interrupt request flag bit Read 0 No underflow (00H 1 Underflow (00H → FFH) on counter →FFH) on counter Write Clears this bit. No effect. The bit does not change. The UF, IR, and BF bits are interrupt request flag bits. IE 0 Disables interrupt request output. 1 Enables interrupt request output. EN R/W: Readable/Writable R : Read only — : Undefined : Initial value 184 Interrupt request enable bit Counter operation enable bit 0 Disables/stops operation. 1 Enables/starts operation. Table 9.4-1 Functions of Bits in PWC Pulse Width Control Register 1 (PCR1) (1 / 2) Bit name Function bit7 EN: Counter operation enable bit For the interval timer function: Writing "1" to this bit starts the counter counting-down from the PWC reload buffer register (PLBR) value. Writing "0" to this bit stops the counter operation. For the pulse width measurement function: Writing "1" to this bit enables measurement. The counter starts counting-down from "FFH" on detection of the specified edge on the measurement pulse. Writing "0" to this bit stops the counter operation. Note: If operation is disabled (EN = 0) during measurement in pulse width measurement mode, the counter stops but the value is not transferred to the PLBR1 register. Restarting operation (EN = 1) sets the counter value to "FFH" then enables operation. bit6 Undefined bit The read value is undefined. Writing to these bits has no effect on the operation. bit5 IE: Interrupt request enable bit This bit enables or disables an interrupt request output to the CPU. An interrupt request is output to the CPU when both this bit and one or more of the interrupt request flag bits (UF, IR, and BF) are "1". bit4, bit3 Undefined bits The read value is undefined. Writing to these bits has no effect on the operation. UF: Underflow (00H →FFH) interrupt request flag bit This bit is set to "1" when the counter underflow (00H →FFH) occurs. An interrupt request is output when both this bit and the interrupt request enable bit (IE) are "1". Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. Reference: • When the interval timer function is active and the counter underflow (00H → FFH) occurs, in reload timer mode, counting-down continues from the PLBR register value. In one-shot timer mode, the counter operation automatically stops (EN = 0). • If the counter underflow (00H →FFH) occurs while measuring a long input pulse in the pulse width measurement function, this bit is set to "1" and counter operation continues. IR: Measurement completion interrupt request flag bit For the pulse width measurement function: This bit is set to "1" when the pulse width measurement is completed. An interrupt request is output when both this bit and the interrupt request enable bit (IE) are "1". Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. For the interval timer function: The bit has no meaning. bit2 bit1 185 CHAPTER 9 PWC TIMER Table 9.4-1 Functions of Bits in PWC Pulse Width Control Register 1 (PCR1) (2 / 2) bit0 186 Bit name Function BF: Buffer full flag bit For the pulse width measurement function: This bit is an interrupt request flag and is set to "1" when a measurement value is present in the PLBR register. An interrupt request is output when both this bit and the interrupt request enable bit (IE) are "1". This bit is set to "1" when pulse width measurement completes and cleared to "0" when the measurement value is read from the PLBR register. This bit is read only. The write value has no meaning and has no effect on the operation. For the interval timer function: This bit has no meaning. 9.4.2 PWC Pulse Width Control Register 2 (PCR2) The PWC pulse width control register 2 (PCR2) is used to select the operating mode (pulse width measurement or interval timer operation, etc.), select the count clock, set the measured pulse (measurement edges), and check the timer output state of the pulse width count timer. ■ PWC Pulse Width Control Register 2 (PCR2) Figure 9.4-3 PWC Pulse Width Control Register 2 (PCR2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0032H FC RM TO C1 C0 W2 W1 W0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W W2 W1 Measured pulse selection bits W0 Only applies to the pulse width measurement function (FC = 1) 0 0 0 "H" pulse (rising edge to falling edge) 0 0 1 "L" pulse (falling edge to rising edge) 0 1 0 Rising edge to rising edge (one cycle) 0 1 1 Falling edge to falling edge (one cycle) 1 1 0 Both edges C1 C0 0 0 1 tinst 0 1 4 tinst 1 0 32 tinst 1 1 Do not use this setting Count clock selection bits tinst: Instruction cycle TO 0 1 RM Write Can be used to set the Reads the current output output value when the value. counter is stopped. Reload mode selection bit Only applies to the interval timer function (FC = 0). 0 Reload timer mode 1 One-shot timer mode FC R/W: Readable/Writable : Initial value Timer output bit Read Operating mode selection bit 0 Operates as an interval timer function. 1 Operates as a pulse width measurement function. 187 CHAPTER 9 PWC TIMER Table 9.4-2 Functions of Bits in PWC Pulse Width Control Register 2 (PCR2) Bit name Function bit7 FC: Operating mode selection bit This bit switches between the interval timer function (FC = 0) and pulse width measurement function (FC = 1). Note: When using the pulse width measurement function (FC = 1), set the P05/INT25/PWC pin as an input port. bit6 RM: Reload mode selection bit For the interval timer function: This bit selects reload timer mode (RM = 0) or one-shot timer mode (RM = 1). For the pulse width measurement function: This bit has no meaning. bit5 TO: Timer output bit The value of this bit is inverted each time a counter value underflow (00H →FFH) occurs. By counting the number of times this bit is inverted (number of underflow (00H →FFH) occurs), pulse widths longer than 28 × the cycle of the selected count clock can be measured. bit4, bit3 C1, C0: Count clock selection bits These bits select the count clock for the interval timer function and pulse width measurement function. Three internal count clocks can be selected. bit2 to bit0 W2, W1, W0: Measured pulse selection bits For the pulse width measurement function: These bits select which pulse edges to use as the start and end conditions for pulse measurement. Five types of pulse width or cycle can be selected. For the interval timer function: These bits have no meaning. Note: Do not modify the PCR2 register while the counter is operating (PCR1: EN = 1). 188 9.4.3 PWC Reload Buffer Register (PLBR) The PWC reload buffer register (PLBR) functions as a reload register for the interval timer function and as a measurement value storage register for the pulse width measurement function. ■ PWC Reload Buffer Register (PLBR) Figure 9.4-4 shows the bit configuration of the PWC reload buffer register. Figure 9.4-4 PWC Reload Buffer Register (PLBR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB 0033H R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W ……For the interval timer function R ……For the pulse width measurement function R/W: Readable/Writable R : Read only X : Undefined value ● For interval timer function The register functions as a reload register, specifying the interval time. The counter starts counting-down from the set value written in this register when counter operation is enabled (PCR1: EN = 1). In reload timer mode, the PLBR register value is reloaded to the counter and the counter continues counting-down when a counter value underflows (00H -> FFH). If a value is written to the PLBR register during counter operation, the new value applies from the next time the counter is reloaded due to an underflow (00H -> FFH). Note: The setting value of the PLBR register for the interval timer function is calculated as follows: PLBR register value = interval time/(count clock cycle × instruction cycle) ● For pulse width measurement function The register is used to store the pulse width measurement value. The counter value is transferred to this register when pulse width measurement completes on detection of the edge specified for measurement completion. At this time, the buffer full flag bit (PCR1: BF) and the measurement completion interrupt request flag bit (PCR1: IR) are set to "1". Reading this register clears the BF bit to "0". The register is read-only for the pulse width measurement function. 189 CHAPTER 9 PWC TIMER Reference: The pulse width for the pulse width measurement function is calculated based on the PLBR register value as follows: Pulse width = (256 - PLBR register value) × count clock cycle × instruction cycle 190 9.5 Pulse Width Count Timer Interrupts The pulse width count timer has the following two interrupts: • Counter value underflow (00H -> FFH) for the interval timer function • Measurement completion and buffer full for the pulse width measurement function ■ Interrupt for the Interval Timer Function The counter value is counted-down from the set value on the selected count clock. When an underflow occurs, the underflow (00H -> FFH) interrupt request flag bit (PCR1: UF) is set to "1". At this time, an interrupt request (IRQA) to the CPU is generated if the interrupt request enable bit is enabled (PCR1: IE = 1). Write "0" to the UF bit in the interrupt processing routine to clear the interrupt request. Reference: The UF bit is not set if the counter is stopped (PCR1: EN = 0) at the same time as the counter value underflows (00H -> FFH). An interrupt request is generated immediately if the UF bit is "1" when the IE bit is changed from disabled to enabled ("0" -> "1"). ■ Interrupt for Pulse Width Measurement Function When the specified measurement completion edge is detected, the measurement completion interrupt request flag bit (PCR1: IR) and the buffer full flag bit (PCR1: BF) are set to "1". Also, when a counter underflow (00H -> FFH) occurs due to measurement of a long pulse, the UF bit is set to "1". At this time, an interrupt request (IRQA) to the CPU is generated if the interrupt request enable bit is enabled (PCR1: IE = 1). Write "0" to the IR and UF bits in the interrupt processing routine to clear the interrupt request. Also read the PWC reload buffer register (PLBR) to clear the BF bit to "0". Note: The IR and BF bits are not set if the counter is stopped (PCR1: EN = 0) at the same time as the specified measurement completion edge is detected. An interrupt request is generated immediately if the IR, BF, or UF bit is "1" when the IE bit is changed from disabled to enabled ("0" -> "1"). ■ Register and Vector Table for Pulse Width Count Timer Interrupt Table 9.5-1 Register and Vector Table for Pulse Width Count Timer Interrupt Interrupt level setting register Vector table address Interrupt Register IRQA ILR3 (007DH) Setting bits LA1 (bit5) LA0 (bit4) Upper Lower FFE6H FFE7H See "3.4.2 Interrupt Processing" for details on the operation of interrupt. 191 CHAPTER 9 PWC TIMER 9.6 Operation of Interval Timer Function This section describes the operation of the interval timer function of the pulse width count timer. ■ Operation of Interval Timer Function The interval timer function can operate as a continuous timer (reload timer mode), or as a timer that operates for one cycle and then stops (one-shot mode). ● Reload timer mode Figure 9.6-1 shows the settings required to operate in reload timer mode. Figure 9.6-1 Interval Timer Function (Reload Timer Mode) Settings PCR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EN — IE — — UF IR BF x x W2 W1 W0 x x x 1 PCR2 PLBR FC RM 0 0 TO C1 C0 : Used bit x : Unused bit 1 : Set "1". 0 : Set "0". Sets interval time (counter initial value). On activation, a value decremented by 1 from the PLBR register value is loaded to the counter and the counter starts counting-down on the rising edge of the selected count clock. When the counter value underflows (00H -> FFH), the PWC inverts the timer output bit (PCR2: TO) value, reloads the PLBR register value to the counter, and sets the underflow (00H -> FFH) interrupt request flag bit (PCR1: UF = 1) on the next rising edge of the count clock. Figure 9.6-2 shows the operation in reload timer mode. 192 Figure 9.6-2 Operation in Reload Timer Mode Counter value FFH Reload 80H 00H Time Timer cycle PLBR value (FFH) Cleared by the program PLBR value modified* (FFH →80H) UF bit EN bit For an initial value of "0" TO bit *: If the PWC reload buffer register (PLBR) value is modified during operation, the new value is valid from the next cycle. Reference: Setting the PLBR register value to "01H" causes the TO bit to be inverted after each count clock cycle. ● One-shot timer mode Figure 9.6-3 shows the settings required to operate in one-shot timer mode. Figure 9.6-3 Interval Timer Function (One-shot Timer Mode) Settings PCR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EN — IE — — UF IR BF × × W2 W1 W0 × × × 1 PCR2 PLBR FC RM 0 1 TO C1 C0 Sets interval time (counter initial value). : Used bit × : Unused bit 1 : Set "1". 0 : Set "0". On activation, a value decremented by 1 from the PLBR register value is loaded to the counter and the counter starts counting-down on the rising edge of the selected count clock. When the counter value underflows (00H -> FFH), the counter inverts the timer output bit (PCR2: TO) value, automatically clears the counter operation enable bit (PCR1: EN = 0) to stop counter operation, and sets the underflow (00H -> FFH) interrupt request flag bit (PCR1: UF = 1) on the next rising edge of the count clock. Figure 9.6-4 shows the operation in one-shot timer mode. 193 CHAPTER 9 PWC TIMER Figure 9.6-4 Operation in One-shot Timer Mode Counter value FFH 80H 00H Time Timer cycle PLBR value (FFH) PLBR value modified (FFH →80H)* Cleared by the program UF bit EN bit Automatic clear Reactivate Invert Automatic clear Reactivate Automatic clear Reactivates with the initial value unchanged ("0") TO bit For an initial value of "1" on activation *: If the PWC reload buffer register (PLBR) value is modified during operation, the new value is used from the next cycle. Reference: Do not modify PCR2 when the counter is operating (PCR1: EN = 1). The UF bit is set to "1" if a counter value underflows (00H -> FFH), regardless of the value of the interrupt request enable bit (PCR1: IE). When the counter is stopped (PCR1: EN = 0) while the interval timer function is selected, the TO bit maintains the value it had immediately before the counter stopped. 194 9.7 Operation of Pulse Width Measurement Function This section describes the operations of the pulse width measurement function of the pulse width count timer. ■ Operation of Pulse Width Measurement Function Figure 9.7-1 shows the settings required to operate as the pulse width measurement function. Figure 9.7-1 Pulse Width Measurement Function Settings bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 × × 0 × × × × × EN — IE — — UF IR BF FC RM TO C1 C0 W2 W1 W0 1 × × DDR0 PCR1 1 PCR2 PLBR Holds the pulse width measurement value. : Used bit : Used to measure long pulse widths × : Unused bit 1 : Set "1". 0 : Set "0". When counter operation is enabled, the counter starts counting-down from "FFH" when a measurement start edge is detected on the pulse input to the PWC pin. (For "H" width measurement, the counter starts measurement from the next rising edge if the input has been already "H".) On detection of the measurement completion edge, the current down-counter value is transferred to the PWC reload buffer register (PLBR), the measurement completion interrupt request flag bit (PCR1: IR) and buffer-full flag bit (PCR1: BF) are both set to "1", and counter operation is re-enabled. (The function supports continuous pulse width measurement and so can be used like an input capture.) Figure 9.7-2 shows the operation when the measured pulse selection bits (PCR2: W2, W1, W0) are set to "000B" ("H" width measurement). Figure 9.7-2 Example of "H" Width Measurement Using Pulse Width Measurement Function "H" width Input pulse (input waveform to the PWC pin) Counter value FFH Time EN bit Counter operation Cleared by the program IR bit BF bit Data transferred from downcounter to PLBR PLBR read 195 CHAPTER 9 PWC TIMER Notes: • If the previous PLBR register value has not been read during continuous pulse width measurement, the PWC leaves the BF bit set to "1" and maintains the previous measurement value. In this case, the new measurement value is lost. • Do not modify the PCR1/PCR2 register during pulse width measurement (PCR1: EN = 1). ■ Measuring Long Pulse Widths To measure pulse widths longer than 28 times the cycle of the selected count clock, it is necessary to count the number of counter underflows (00H -> FFH) by software in the interrupt processing routine. Counting by software requires a buffer in RAM (a software counter) to hold the number of counter underflows (00H -> FFH). After initializing the software counter and enabling counter operation, the counter starts counting-down from "FFH" when a measurement start edge is detected on the pulse input to the PWC pin. An interrupt request is generated on detection of the measurement completion edge or when the counter underflows (00H -> FFH). Check the measurement completion interrupt request flag bit (PCR1: IR) and underflow (00H -> FFH) interrupt request flag bit (PCR1: UF) in the interrupt processing routine. If the UF bit is "1", write "0" to the UF bit to clear the interrupt request and increment the software counter (the PWC counter continues to operate). When the IR bit is "1", calculate the pulse width including underflows (00H -> FFH) from the values of the software counter and PWC reload buffer register (PLBR). When the PLBR register value is "00H", calculate as 256. ● Calculating the width of long pulses Pulse width = [(256 - PLBR register value) + (number of counter underflows (00H × FFH) × 256)] × onecycle width of count clock Calculate the pulse width before the next underflow (00H x FFH) occurs. The correct measurement value may not be able to be calculated after the next underflow (00H x FFH) occurs. Figure 9.7-3 shows the operation when the measured pulse selection bits (PCR2: W2, W1, W0) are set to "011B" (falling edge to falling edge). 196 Figure 9.7-3 Measuring Long Pulse Widths One cycle Input pulse (input waveform to the PWC pin) EN bit Counter value FFH Software counter value 0 1 2 3 Set "0" UF bit Cleared by the program Cleared by the program IR bit BF bit Data transferred from down-counter to PLBR PLBR read 197 CHAPTER 9 PWC TIMER 9.8 States in Each Mode during Pulse Width Count Timer Operation This section describes the operation of the pulse width count timer when the device changes to sleep or stop mode or an operation halt request occurs during operation. ■ Operation during Standby Mode or Operation Halt Figure 9.8-1 shows the counter value state when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or pulse width measurement function. The counter halts and maintains its current value when the device changes to stop mode. Operation starts again from the stored counter value after wake-up from stop mode by an external interrupt. Therefore, the first interval time or pulse width measurement is not correct value. Always initialize the pulse width count timer after wake-up from stop mode. Figure 9.8-1 Counter Operation during Standby Modes or Operation Halt PLBR value (FFH) Counter value FFH 80H 00H Time Timer cycle Stop request Oscillation stabilization wait time Interval time after wake-up from stop mode (undefined) UF bit Operation halts Operation halts Cleared by the program EN bit Operation restarts IE bit Sleep mode SLP bit Wake-up from stop mode by an external interrupt (STBC register) Wake-up from sleep mode by IRQA STP bit (STBC register) 198 Stop mode 9.9 Notes on Using Pulse Width Count Timer This section lists points to note when using the pulse width count timer. ■ Notes on Using Pulse Width Count Timer ● Error When using the interval timer function, activating the counter by program is not synchronized with the start of counting-down using the selected internal count clock. Therefore, the time from activating the counter until an underflow (00H -> FFH) occurs may be shorter than the theoretical time by a maximum of one cycle of the count clock. Figure 9.9-1 shows the error that occurs on starting counter operation. Figure 9.9-1 Error on Starting Counter Operation Counter value Set value: n n-1 n-2 n-3 n-4 Count clock One cycle Error Cycle of set value n Counter activate ● Notes on setting by program • Do not modify the contents of the PWC pulse width control register 2 (PCR2) when the interval timer function or pulse width measurement function is operating (PCR1: EN = 1). • Stop the counter (EN = 0), disable interrupts (IE = 0), and clear the interrupt request flag bits (UF, IR, BF = 0) in the PCR1 register before switching between the interval timer function and pulse width measurement function (PCR2: FC). • Interrupt processing cannot return if the interrupt request flag bit (PCR1: UF, IR, or BF) is "1" and the interrupt request enable bit is enabled (PCR1: IE = 1). Always clear the interrupt request flag bit. • If a previous measurement value has not been read when performing continuous pulse width measurement for pulse width measurement function, new measurement values are not transferred to the PWC reload buffer register (PLBR). The PLBR maintains the previous value. Always read the measurement value before the next underflow (00H -> FFH) when measuring long pulse widths. • The interrupt request flag bit (PCR1: UF, IR, or BF) is not set if the counter is stopped (PCR1: EN = 0) at the same time as an interrupt source is generated. 199 CHAPTER 9 PWC TIMER 9.10 Program Example for Timer Function of Pulse Width Count Timer This section gives two program examples for the timer function of the pulse width count timer. ■ Program Example 1 for Interval Timer Function (Reload Timer Mode) ● Processing description • Generates repeated interval timer interrupts at 3 ms intervals (reload timer mode). • Outputs a square wave to the TO pin that inverts after each interval time cycle. The initial value of TO pin is "L" level. • The following shows the PLBR register value that results in an interval time of approximately 3 ms for a 12.5 MHz source oscillation. The count clock is 32 tinst (tinst: divide-by-four main clock source oscillation when the highest main clock speed is selected). PLBR register value = 3 ms/(32 × 4/12.5 MHz) = 293.0 (125H) 200 ● Coding example PCR1 PCR2 PLBR EQU EQU EQU 0031H 0032H 0033H ; Address of the PWC pulse width control register 1 ; Address of the PWC pulse width control register 2 ; Address of the PWC reload buffer register EN IE UF EQU EQU EQU PCR1:7 PCR1:5 PCR1:2 ; Define the counter operation enable bit. ; Define the interrupt request enable bit. ; Define the underflow (00H →FFH) interrupt request flag bit. ILR3 EQU 007DH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFE6H IRQA DW WARI ; Set interrupt vector. INT_V ENDS ;-----Main program-------------------------------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : CLRI ; Disable interrupts. CLRB EN ; Stop counter operation. CLRB IE ; Disable interrupt request output. MOV ILR3,#11011111B ; Set interrupt level (level 1). MOV PLBR,#125H ; Counter reload value (interval time) MOV PCR2,#00010000B ; Select interval timer function, reload timer mode, initial output value of the TO bit, and 32 tinst. MOV PCR1,#11100000B ; Start counter operation, enable interrupt request output, clear underflow (00H →FFH) interrupt request flag, clear measurement completion interrupt request flag (bit 1). SETI ; Enable interrupts. : ;-----Interrupt processing routine-------------------------------------------------------------------------------------------------------------------------------------------WARI CLRB UF ; Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------END ■ Program Example 2 for Interval Timer Function (One-shot Timer Mode) ● Processing description • Generates a single 3 ms interval timer interrupt (one-shot timer mode). • Outputs a pulse wave to the TO pin that inverts after each interval time cycle. The initial value of TO pin is "H" level. • The following shows the PLBR register value that results in an interval time of approximately 3 ms for a 12.5 MHz source oscillation. The count clock is 32 tinst (tinst: divide-by-four main clock source oscillation when the highest main clock speed is selected). PLBR register value = 3 ms/(32 × 4/12.5 MHz) = 293.0 (125H) 201 CHAPTER 9 PWC TIMER ● Coding example PCR1 PCR2 PLBR EQU EQU EQU 0031H 0032H 0033H ; Address of the PWC pulse width control register 1 ; Address of the PWC pulse width control register 2 ; Address of the PWC reload buffer register EN IE UF EQU EQU EQU PCR1:7 PCR1:5 PCR1:2 ; Define the counter operation enable bit. ; Define the interrupt request enable bit. ; Define the underflow (00H →FFH) interrupt request flag bit. ILR3 EQU 007DH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFE6H IRQA DW WARI ; Set interrupt vector. INT_V ENDS ;-----Main program---------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : CLRI ; Disable interrupts. CLRB EN ; Stop counter operation. CLRB IE ; Disable interrupt request output. MOV ILR3,#11011111B ; Set interrupt level (level 1). MOV PLBR,#125H ; Counter reload value (interval time) ; Select interval timer function, one-shot timer mode, initial output MOV PCR0,#01110000B value of the TO bit, and 32 tinst. ; Start counter operation, enable interrupt request output, clear underflow (00H →FFH) interrupt request flag, clear measurement MOV PCR1,#11100000B complete interrupt request flag (bit 1). SETI ; Enable interrupts. : ;-----Interrupt processing routine---------------------------------------------------------------------------------------------------------------------WARI CLRB UF ; Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;--------------------------------------------------------------------------------------------------------------------------------------------------------------END 202 9.11 Program Example for Pulse Width Measurement Function of Pulse Width Count Timer This section gives a program example for the pulse width measurement function of the pulse width count timer. ■ Program Example for Pulse Width Measurement Function ● Processing description • Measures the "H" width of a pulse input to the PWC pin (pulse width measurement function). • Generates an interrupt when pulse width measurement completes and continues measurement. • The following shows the relationship between the PLBR register value and the measured pulse width when the main clock source oscillation is 12.5 MHz and the 4 tinst (tinst: divide-by-four main clock source oscillation when the highest main clock speed is selected) count clock is selected. Pulse width = (256 - PLBR register value) × 4 × 4/12.5 MHz (measurement range: 1.28 µs to 327.7 µs) ● Coding example DDR0 PCR1 PCR2 PLBR EQU EQU EQU EQU 0001H 0031H 0032H 0033H ; Address of the PORT2 data direction register ; Address of the PWC pulse width control register 1 ; Address of the PWC pulse width control register 2 ; Address of the PWC reload buffer register EN IE IR BF EQU EQU EQU EQU PCR1:7 PCR1:5 PCR1:1 PCR1:0 ; Define the counter operation enable bit. ; Define the interrupt request enable bit. ; Measurement completion interrupt request flag bit ; Buffer full flag bit ILR3 EQU 007DH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFE6H IRQA DW WARI ; Set interrupt vector. INT_V ENDS ;-----Main program--------------------------------------------------------------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. : MOV DDR0,#00000000B ; Set P05/INT25/PWC pin as an input. CLRI ; Disable interrupts. CLRB EN ; Stop counter operation. CLRB IE ; Disable interrupt request output. CLRB BF ; Clear buffer full flag (PCR1: BF). MOV ILR3,#11011111B ; Set interrupt level (level 1). MOV PCR0,#10001000B ; Select the pulse width measurement function, 4 tinst, and "H" pulse, ; Enable counter operation, enable interrupt request output, clear underflow (00H →FFH) MOV PCR1,#10100000B interrupt request flag (bit 2), clear measurement completion interrupt request flag (IR). SETI ; Enable interrupts. ;-----Interrupt processing routine--------------------------------------------------------------------------------------------------------------------------------------------WARI CLRB IR ; Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A MOV A,PLBR ; Read pulse width measurement value and clear BF flag. : User processing : POPW A XCHW A,T POPW A RETI 203 CHAPTER 9 PWC TIMER ENDS ;-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------END 204 CHAPTER 10 6-BIT PPG TIMER This chapter describes the functions and operation of the 6-bit PPG timer (remote control transmit output generator). 10.1 Overview of 6-bit PPG Timer 10.2 Block Diagram of 6-bit PPG Timer 10.3 Pin of 6-bit PPG Timer 10.4 Registers of 6-bit PPG Timer 10.5 Operation of 6-bit PPG Timer 10.6 Notes on Using 6-bit PPG Timer 10.7 Program Example for 6-bit PPG Timer 205 CHAPTER 10 6-BIT PPG TIMER 10.1 Overview of 6-bit PPG Timer The 6-bit PPG timer is a 6-bit binary counter that can select one of four clocks as its count clock to function as remote control transmit generator. Both the cycle of the output waveform and its "H" state pulse width can be set, which allows the circuit to be used as a 6-bit PPG timer. ■ 6-bit PPG Timer Function • Generates frequencies for use by 6-bit PPG timer function, and outputs the signal at the PPG pin. • The cycle and "H" state pulse width of the output waveform can be set separately. • The count clock can be selected from four different internal clocks. • The frequencies can generate with a cycle among 2 and 26 - 1 times the count clock cycle. Table 10.1-1 lists the available range of output cycle and "H" state pulse widths Table 10.1-1 Output Cycles and "H" Pulse Width Ranges Internal count clock cycle Output cycle Output "H" pulse width* 0.5 tinst 1 tinst to 31.5 tinst 0.5 tinst to 31.5 tinst 1 tinst 2 tinst to 63 tinst 1 tinst to 62 tinst 8 tinst 16 tinst to 504 tinst 8 tinst to 496 tinst 32 tinst 64 tinst to 2016 tinst 32 tinst to 1984 tinst tinst: instruction cycle (affected by clock mode, etc.) *: Can also output a steady "H" level state (100% duty cycle). 206 ● Calculation example for the 6-bit PPG function cycle and "H" state pulse width (when a 1 tinst clock is selected for count clock cycle). Assume a main clock source oscillation (FCH) of 12.5 MHz, and a 1 tinst clock selected for count clock cycle. Also assume the highest clock speed of the main clock mode selected from the system clock control register (SYCC: SCS = CS1 = CS0 = 1). (This makes the instruction cycle time 4/FCH.) Then, for the indicated comparison values, the output waveform cycle and "H" state pulse width can be calculated as follows: Cycle comparison value = 011110B (30 clock cycles) Pulse width comparison value = 001010B (10 clock cycles) Cycle=cycle comparison value × count clock cycle = 011110B (30 clock cycles) × 1 × 4/FCH = 30 × 0.32 µs = 9.6 µs "H" state pulse width = "H" pulse width comparison value × count clock cycle = 001010B (10 clock cycles) × 1 × 4/FCH = 10 × 0.32 µs = 3.2 µs If the "H" pulse width setting is equal to or greater than the cycle setting, the output will be a steady "H" level. ■ 6-bit PPG Function 6-bit PPG can set the cycle and "H" pulse width of its output waveform separately. The valid range of "H" pulse width comparison settings, however, is from "1" (1.6% duty ratio) to the cycle comparison setting (100% duty ratio). This means that the lower the cycle comparison setting (the shorter the cycle of the output waveform), the lower the resolution (the larger the minimum duty ratio step size). For a cycle comparison setting of "2", for example, the possible "H" pulse width comparison settings would be "1", and "2", which would result in a resolution of 1/2. The duty ratios for these settings would be 50%, and 100%, or a minimum duty ratio step of 50%. The output cycle and duty ratio are calculated as follows: Output cycle = cycle comparison value × selected count clock cycle. Duty ratio = "H" pulse width compare value/cycle compare value × 100 (%) 207 CHAPTER 10 6-BIT PPG TIMER Table 10.1-2 shows the available output cycle, resolution and the minimum steps for duty ratio. Table 10.1-2 6-bit PPG Resolution and Output Cycles Output cycle Count clock = 1 tinst Count clock = 32 tinst "H" pulse width comparison value setting range 0 — — 1 always "H" 1 — — 1 always "H" 2 2 tinst 64 tinst 1 to 2 1/2 50.0% 3 3 tinst 96 tinst 1 to 3 1/3 33.3% 4 4 tinst 128 tinst 1 to 4 1/4 25.0% 5 5 tinst 160 tinst 1 to 5 1/5 20.0% 6 6 tinst 192 tinst 1 to 6 1/6 16.7% 7 7 tinst 224 tinst 1 to 7 1/7 14.3% 8 8 tinst 256 tinst 1 to 8 1/8 12.5% 9 9 tinst 288 tinst 1 to 9 1/9 11.1% 10 10 tinst 320 tinst 1 to 10 1/10 10.0% : : 15 tinst 480 tinst 1 to 15 1/15 6.7% : : 20 tinst 640 tinst 1 to 20 1/20 5.0% : : 25 tinst 800 tinst 1 to 25 1/25 4.0% : : 30 tinst 960 tinst 1 to 30 1/30 3.3% : : 40 tinst 1280 tinst 1 to 40 1/40 2.5% : : 50 tinst 1600 tinst 1 to 50 1/50 2.0% : : 60 tinst 1920 tinst 1 to 60 1/60 1.7% : : 63 tinst 2016 tinst 1 to 63 1/63 1.6% Period comparison value 15 20 25 30 40 50 60 63 tinst: instruction cycle 208 Resolution Duty ratio Minimum step 10.2 Block Diagram of 6-bit PPG Timer The 6-bit PPG timer consists of the following five blocks: • Count clock selector • 6-bit counter • Comparator circuit • 6-bit PPG control register 1 (PPGC1) • 6-bit PPG control register 2 (PPGC2) ■ Block Diagram of 6-bit PPG timer Figure 10.2-1 Block Diagram of 6-bit PPG timer Internal data bus PPGC1 RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 "H" pulse width comparison value 6 1 tinst Count clock selector × 1/2 × 1 × 8 × 32 6-bit PPG output 6-bit counter CLK CLEAR P06/INT26/PPG Comparator circuit Pin 6-bit PPG output enable signal 6 Period comparison value PPGC2 RCEN — SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 Internal data bus tinst: Instruction cycle 209 CHAPTER 10 6-BIT PPG TIMER ● Count clock selector Selects a count-up clock for the 6-bit counter from the four available internal count clock. ● 6-bit counter The 6-bit counter counts-up, on the count clock selected by the count clock selector. The counter can be cleared by the output enable bit of the PPGC2 register (PPGC2: RCEN = 0). ● Comparison circuit The comparison circuit holds a "H" state until the count in the 6-bit counter matches the setting in the "H" pulse width compare register. Then it holds the "L" state until the counter count matches the setting in the cycle compare register, at which time the counter is cleared to all zeros and continues counting. ● 6-bit PPG control register 1 (PPGC1) PPGC1 is used to select the counter clock for the 6-bit PPG timer, and set the output "H" pulse width comparison value. ● 6-bit PPG control register 2 (PPGC2) PPGC2 is used to enable/disable outputs for the 6-bit PPG timer, and set the output cycle comparison value. 210 10.3 Pin of 6-bit PPG Timer The section describes the pin, pin block diagram and register of the 6-bit PPG timer. ■ Pin of 6-bit PPG Timer The 6-bit PPG uses the P06/INT26/PPG pin. The pin can function as general purpose I/O port (P06), as the remote control output (PPG), or as a external interrupt input (INT26). PPG: When the output enable bit in the 6-bit PPG control register is set to "1" (PPGC2: RCEN = 1), this pin functions as the 6-bit PPG timer pin, outputting a waveform having a "H" state pulse width and cycle as set. ■ Block Diagram of 6-bit PPG Timer Pin Figure 10.3-1 Block Diagram of 6-bit PPG Timer Pin From 6-Bit PPG output PDR (Port data register) From output control bit PPGC2: RCEN Stop, watch mode Pull-up resistor control register PDR read Internal data bus Pull-up resistor Approx. 50 kΩ P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin DDR N-ch P06/INT26/PPG DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: When pull-up resistor is selected in pull-up register, the states of these pins in stop and watch mode (SPL=1) are in "H" level (pull-up state) rather than high impedance. However, during reset, pull-up is unavailable and will be in high impedance state. 211 CHAPTER 10 6-BIT PPG TIMER 10.4 Registers of 6-bit PPG Timer This section describes the registers of the 6-bit PPG timer. ■ Registers of 6-bit PPG Timer Figure 10.4-1 Registers of 6-bit PPG Timer PPGC1 (PPG control register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 003EH RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W PPGC2 (PPG control register 2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 003FH RCEN — SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0-000000B R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable — : Undefined 212 10.4.1 6-bit PPG Control Register 1 (PPGC1) 6-bit PPG control register 1 is used to select the counter clock of the 6-bit PPG timer, and set the "H" pulse width. ■ 6-bit PPG Control Register 1 (PPGC1) Figure 10.4-2 6-bit PPG Control Register 1 (PPGC1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 003EH RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable tinst : Instruction cycle : Initial value HSC5 to HSC0 "H" pulse width setting bits XXXXXX "H" pulse width comparison value RCK1 RCK0 Count clock selection bits 0 0 0.5 tinst 0 1 1 tinst 1 0 8 tinst 1 1 32 tinst Table 10.4-1 Functions of Bits in PPG Control Register 1 (PPGC1) Bit name bit7, bit6 bit5 to bit0 RCK2, RCK1: Count clock selection bits HSC5 to HSC0: "H" pulse width setting bits Function Select one of four internal clocks as the 6-bit PPG timer count clock. These bits set the number of counts for which the 6-bit PPG timer output is to remain "H". (The "H" pulse width comparison value to be compared by the count in the counter.) Note: When the count clock is 0.5 tinst: The setting value between "000000" and "111110" (00H to 3EH) is always set a value less than the cycle comparison setting. If they are set equal to or greater than the setting, a steady "H" level is output. When the count clock is 1/8/32 tinst The setting value between "000001" and "111110" (01H to 3EH) is always set a value less than the cycle comparison value. If the value is set to "000000", a 0.5 tinst long "H" pulse will be outputted. If they are set equal to or greater than the setting, a steady "H" level is output. 213 CHAPTER 10 6-BIT PPG TIMER 10.4.2 6-bit PPG Control Register 2 (PPGC2) 6-bit PPG control register 2 is used to enable/disable output of the 6-bit PPG waveform, and set the output cycle setting. ■ 6-bit PPG Control Register 2 (PPGC2) Figure 10.4-3 6-bit PPG Control Register 2 (PPGC2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 003FH RCEN — SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0-000000B R/W R/W R/W R/W R/W R/W R/W XXXXXX Cycle setting bits Cycle compare value of 6-bit PPG output RCEN 0 1 Output enable bit Disable output; clear counter. Enable output; start counter. SCL5 to SCL0 R/W — : Readable/Writable : Undefined : Initial value Table 10.4-2 Functions of Bits in PPG Control Register 2 (PPGC2) Bit name Function bit7 RCEN: Output enable bit When this bit is "0", the P06/INT26/PPG pin functions as a general-purpose port pin (P06/ INT26), and when it is "1", the pin functions as the PPG output pin (PPG). Setting this bit to "0" clears and stops the counter; setting it to "1" starts the counter. bit6 Undefined bit The read value is undefined. Writing to this bit has no effect on the operation. bit5 to bit0 SCL5 to SCL0: Cycle setting bits These bits set the length of the output cycle in terms of counter counts. (The cycle period comparison value to be compared by the count in the counter.) Note: When the count clock is 0.5 tinst The setting value is between "000001" and "111111" (01H to 3FH). The PPG output will remain the previous state until the cycle comparison value is matched by the count value in the counter. Then the 6-Bit PPG output will output "H" level. When the count clock is 1/8/32 tinst The setting value is between "000010" and "111111" (02H to 3FH). The PPG output will remain the previous state until the cycle comparison value is matched by the count value in the counter. Then the 6-Bit PPG output will output "H" level. If this setting value is set to "01H" and the "H" pulse width comparison value is "00H", PPG will output a 0.5 tinst long "H" pulse. 214 10.5 Operation of 6-bit PPG Timer The 6-bit PPG timer generates a pulse in which the cycle and "H" state pulse width of the output can be set separately. ■ Operation of 6-bit PPG Timer Figure 10.5-1 shows the settings required to operate the 6-bit PPG timer. Figure 10.5-1 6-bit PPG Timer Settings bit7 bit6 bit5 bit4 bit3 PPGC1 RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSCD1 HSC0 bit2 bit1 PPGC2 RCEN — SCL5 SCL4 SCL3 SCL2 SCL1 bit0 SCL0 1 : Used bit 1: Set "1". 0: Set "0". ● Interval time When the 6-bit PPG output is enabled, its 6-bit counter starts counting up from "0" in synchronization with the selected count clock. During the first cycle, the PPG pin output will remain in "H" level until the count in the counter matches the "H" state pulse width comparison value. When this happens, the PPG pin goes "L" level and stays there until the count matches the cycle period comparison value, at which time the 6-bit counter is cleared to "0" and continues to count. The fact that the pulse width and period can be set separately enables the circuit to be used as a 6-bit PPG. Figure 10.5-2 shows the operation of the 6-bit PPG timer. 215 CHAPTER 10 6-BIT PPG TIMER Figure 10.5-2 Operation of 6-bit PPG Timer Counter value Cycle setting value (PPGC2: SCL0 to SCL5) "H" pulse width setting value (PPGC1: HSC0 to HSC5) 00H Period*1 "H" Pulse Width*2 PPG output waveform *1 : When count clock is 0.5 tinst Period = 0.5 tinst x (Period comparison value + 1) When count clock is 1/8/32 tinst Period = Count clock period x Period comparison value *2: When count clock is 0.5 tinst Pulse width = 0.5 tinst x ("H" pulse width comparison value + 1) When count clock is 1/8/32 tinst Pulse width = Count clock period x "H" pulse width comparison value 216 10.6 Notes on Using 6-bit PPG Timer This section lists points to note when using the 6-bit PPG timer. ■ Notes on Using 6-bit PPG Timer ● "H" pulse width restrictions Generally, the "H" pulse width setting bits of 6-bit PPG control register 1 (PPGC1: HSC5 to HSC0) must always be set less than the cycle setting bits of PPG control register 2 (PPGC2: SCL5 to SCL0). For any count clock, when SCL5 to SCL0 is "00H", HSC5 to HSC0 is equal to SCL5 to SCL0, or HSC5 to HSC0 is larger than SCL5 to SCL0, the PPG pin will remain at steady "H" level. For any count clock, when HSC5 to HSC0 is "00H" and SCL5 to SCL0 is not equal to "00H", the PPG pin will start to output "L" level and then output a 0.5 tinst long "H" pulse after every cycle match is detected. ● Resolution When count clock is 0.5 tinst, the maximum "H" pulse width resolution is 1/64 of the cycle (the resolution when the cycle setting is "111111" (3FH). Reducing the time of the cycle reduces the resolution, with the minimum resolution of 1/2 occurring with a cycle setting of "000001" (01H).When count clock is 1/8/32 tinst, the maximum "H" pulse width resolution is 1/63 of the cycle (the resolution when the cycle setting is "111111" (3FH). Reducing the time of the cycle reduces the resolution, with the minimum resolution of 1/2 occurring with a cycle setting of "000010" (02H). ● Changing settings during operation Direct comparisons are performed between the 6-bit counter of the 6-bit PPG waveform frequency and the "H" pulse width setting bits (PPGC1: HSC5 to HSC0), and between the counter and the cycle setting bits (PPGC2: SCL5 to SCL0). Therefore, if a setting is reduced in mid-count, the cycle time(t1) may be long until the counter overflows in the worst case and takes effect in next cycle. Similarly, the "H" state pulse width(t2) may be long in the worst case until the next end-of-cycle match is detected. Figure 10.6-1 illustrates what happens when settings are changed during 6-bit PPG timer operation. 217 CHAPTER 10 6-BIT PPG TIMER Figure 10.6-1 Changing Settings during 6-bit PPG Timer Operation Counter value Overflow 3FH Cycle setting value (PPGC2: SCL) *1 *2 *1 *3 "H" pulse width setting value (PPGC1: HSC) 00H PPG output waveform One cycle t2*4 t1*4 *1: Since the current count in the counter is less than the new setting, the new setting takes effect for the current cycle. *2: Since cycle is changed to a value less than the current count, the counter counts all the way to counter overflow and takes effect in the next cycle (in the worst case). *3: Since the new "H" pulse width setting is less that the current count, the pulse width match is not detected until the next cycle (in the worst case). *4: The length of the t1 and t2 is depended on when the new cycle setting value and "H" pulse width setting value. It wll vary from case to case. ● Errors Activating the counter by program is not synchronized with the start of counting-up using the selected count clock. Therefore, the time from activating the counter until a match with the "H" pulse comparison value and cycle comparison value are detected may be shorter than the theoretical time by a maximum of one cycle of the count clock. Figure 10.6-2 shows the error that occurs on starting counter operation. Figure 10.6-2 Error during activating Operation Counter value 00H Count clock One cycle Error Cycle for 0 count Counter activate 218 01H 02H 03H 04H 10.7 Program Example for 6-bit PPG Timer This section gives a program example for the 6-bit PPG timer. ■ Programming Example for 6-bit PPG Timer ● Processing description • Generate the 6-bit PPG at a cycle of approximately 12 µs and a 33% duty ratio. • With a main clock source oscillation (FCH) of 12.5 MHz, the highest clock speed (speed shift function), and the 1 tinst clock selected (1 instruction cycle time = 4/FCH), the comparison value for a cycle of approximately 12 µs is as found as follows: Cycle comparison value (PPGC2: SCL5 to SCL0) = 12 µs/(1 × 4/12.5 MHz) = 37.5 • The comparison value for a "H" state pulse width to provide a 33% duty ratio is found as follows: "H" pulse width comparison value (PPGC1: HSC5 to HSC0) = 33/100 × cycle comparison value = 0.33 × 37.5 = 12 ● Coding example PPGC1 EQU 003EH ; PPG control register 1 PPGC2 EQU 003FH ; PPG control register 2 ;----- Main program ------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : MOV PPGC1,#01001100B; Select 1 tinst count clock, set "H" pulse width comparison ; value. MOV PPGC2,#10100101B; Enable output and start counter, set cycle period, ; comparison value. : ENDS ;-------------------------------------------------------------------------------------------------------------------------------END 219 CHAPTER 10 6-BIT PPG TIMER 220 CHAPTER 11 8/16-BIT TIMER/COUNTER This chapter describes the functions and operation of the 8/16-bit timer/counter. 11.1 Overview of 8/16-bit Timer/Counter 11.2 Block Diagram of 8/16-bit Timer/Counter 11.3 Pins of 8/16-bit Timer/Counter 11.4 Registers of 8/16-bit Timer/Counter 11.5 8/16-bit Timer/Counter Interrupt 11.6 Operation of Interval Timer Function 11.7 Operation of Counter Function 11.8 Operation of the Square Wave Output Initial Setting Function 11.9 Operation of 8/16-bit Timer/Counter Stop and Restart 11.10 States in Each Mode during 8/16-bit Timer/Counter Operation 11.11 Notes on Using 8/16-bit Timer/Counter 11.12 Program Examples for 8/16-bit Timer/Counter 221 CHAPTER 11 8/16-BIT TIMER/COUNTER 11.1 Overview of 8/16-bit Timer/Counter The 8/16-bit timer/counter is made up of two 8-bit timers (Timer 11/21 and Timer 12/22) that can be used separately (8-bit mode) or connected in cascade to form one counter (16-bit mode). Timer 11/21 can be selected to function as either an interval timer or a counter. The interval timer function counts up in sync with one of three internal count clocks. The counter function counts up by a clock input to the external pin. Timer 12/22 functions as an interval timer clocked by one of three internal count clocks. In the 16-bit mode, it is connected in series with Timer 11/21. The output can be used to generate variable frequency square wave output. ■ Interval Timer Function The interval timer function generates repeated interrupt requests at variable intervals. Also, as the 8/16-bit timer/counter can invert the output level of the pin (TO1/TO2 pin) each time an interval time is generated, the 8/16-bit timer/counter can output variable frequency square waves (Timer 11/21 in 8-bit mode, or 16bit mode). • In 8-bit mode, Timer 11/21 and Timer 12/22 operate as two independent interval timers, each of which can count time intervals ranging from the clock period (the time of one clock cycle) to 28 times the clock period. • In 16-bit mode, the two counters form a single 16-bit timer, with Timer 11/21 containing the LSBs and Timer 12/22 the MSBs. The interval timer can operate with a cycle among 1 and 216 times the internal count clock cycle. • The count clock can be selected from three different internal clocks. (An external clock can be selected for Timer 11/21, but it will then function as a counter). Table 11.1-1 to Table 11.1-3 list the interval time and square wave output ranges for the various modes. Table 11.1-1 Timer 11/21 Interval Times and Square Wave Output Ranges in 8-bit Mode Count clock cycle Internal count clock External clock Interval time Square wave output range (Hz) 2 tinst 2 tinst to 29 tinst 1/(22 tinst) to 1/(210 tinst) 32 tinst 25 tinst to 213 tinst 1/(26 tinst) to 1/(214 tinst) 512 tinst 29 tinst to 217 tinst 1/(210 tinst) to 1/(218 tinst) 1 text 1 text to 28 text 1/(2 text) to 1/(29 text) Table 11.1-2 Timer 12/22 Interval Times and Square Wave Output Ranges In 8-bit Mode Count clock cycle Internal count clock 222 Interval time 2 tinst 2 tinst to 29 tinst 32 tinst 25 tinst to 213 tinst 512 tinst 29 tinst to 217 tinst Table 11.1-3 Interval Times and Square Wave Output Ranges in 16-bit mode Count clock cycle Internal count clock External clock Interval Time Square wave output range (Hz) 2 tinst 2 tinst to 217 tinst 1/(22 tinst) to 1/(218 tinst) 32 tinst 25 tinst to 221 tinst 1/(26 tinst) to 1/(222 tinst) 512 tinst 29 tinst to 225 tinst 1/(210 tinst) to 1/(226 tinst) 1 text 1 text to 216 text 1/(2 text) to 1/(217 text) tinst: Instruction cycle (affected by clock mode, etc.) text: External clock period ● Calculation example for the interval time and square wave frequency In this example, the main clock source oscillation (FCH) is 12.5 MHz, the Timer 11/21 data register (T11DR/T21DR) value is set to "DDH (221)", and the count clock cycle is set to the 8-bit mode operation at 2 tinst. In this case, the Timer 11/21 interval time and frequency of square wave output from the TO1/TO2 pin are calculated as follows. Assume that the highest clock speed has been selected via the system clock control register (SYCC: CS1 = 1, CS0 = 1) (1 instruction cycle = 4/FCH). Interval time = (2 × 4/FCH) × (T11DR/T21DR register value + 1) = (8/12.5 MHz) × (221 + 1) = approx. 142.08µs Output frequency = FCH/(2 × 8 × (T11DR/T21DR register value + 1)) = 12.5 MHz/ (16 × (221 + 1)) = approx. 3.52 kHz ■ Counter Function The counter function counts falling edges of an external count clock applied to the external pin (EC1, EC2 pin). Since the external clock can be selected only for Timer 11/21, the counter function operates in either timer 11/21 in the 8-bit mode or 16-bit mode. • The counter counts up, clocked by external clocks. When the count equals the set value, it generates an interrupt request in both 8-bit and 16-bit mode and inverts the level being output at the TO1/TO2 pin. • In the 8-bit mode, Timer 11/21 can count as high as 28. • In the 16-bit mode, the function counts as high as 216. • By injecting an external clock having a set period, the counter function can be used the same way as the interval timer function. 223 CHAPTER 11 8/16-BIT TIMER/COUNTER 11.2 Block Diagram of 8/16-bit Timer/Counter The 8/16-bit timer/counter consists of the following five blocks: • Count clock selectors 1 and 2 • Counter circuits 1 and 2 • Square wave output controller • Timer data registers (T11DR, T12DR, T21DR, T22DR) • Timer control registers (T11CR, T12CR, T21CR, T22CR) ■ Block Diagram of 8/16-bit Timer/Counter Figure 11.2-1 Block Diagram 8/16-bit Timer/Counter T11CR T1STR T1STP T1CS0 T1CS1 T1OS0 T1OS1 T1IE T21CR / Square wave 2 output controller Initialize pin control/output T1IF Output enable signal / 2 R,S CK Pin Q T.FF ×2 × 32 × 512 P26/V1/TO1 P24/C1/TO2* Counter circuit 1 CK CLR Pin 8-bit counter Count clock P27/V2/EC1 selector 1 P25/C0/EC2* CO T11DR/T21DR read Comparator EQ Comparison data latch LOAD Data register Internal data bus 1tinst Interrupt request IRQ6 IRQ7 T11DR/T21DR and T12DR/T22DR Write Data register LOAD Comparison data latch Comparator EQ T12DR/T22DR read Count clock selector 2 1tinst CK CLR ×2 × 32 × 512 8-bit counter Counter circuit 2 2 / T12CR T2STR T2STP T2CS0 T2CS1 T2OS0 T2OS1 T2IE T22CR T2IF tinst : Instructin cycle * : If booster is selected, EC2 and TO2 will be redireted to P03/INT23 and P04/INT24 respectively. 224 ● Count clock selectors 1, 2 This circuit selects an input clock. In timer 11/21 in the 8-bit and 16 bit modes, count clock selector 1 selects one of four clocks: three internal clocks, and an external clock. In the 8-bit mode, count Clock Selector 2 selects one of three internal clocks only. ● Counter circuits 1, 2 • Counter circuit 1 and counter circuit 2 are each made up of an 8-bit counter, a comparator, a comparison data latch, and a data register (T11DR/T21DR or T12DR/T22DR). • In each counter circuit, the 8-bit counter counts up clocked by the selected count clock. The comparator compares the count in the counter with the value in the comparison data latch. When it detects a match, it clears the counter, and loads the contents of the data register into the comparison data latch. • In the 8 bit-mode, the two counter circuits operate independently as Timer 11/21 and timer 12/22. In the 16-bit mode, the two circuits are connected in series to form a single 16-bit counter with counter circuit 1 forming the lower (8 LSBs) end of the counter, and counter circuit 2 at the upper (8 MSBs) end. ● Square wave output control circuit • An interrupt request is generated when the comparator detects a match in the 8-bit mode or the 16-bit mode. At this time, if the square wave output is enabled, the output control circuit inverts the level output at the TO1/TO2 pin. (only for 8-bit timer 11/21 in 8-bit mode or 16-bit mode) • The circuit can also initialize the output level to have the output square wave start out in a specific state ("H" or "L") (only for 8-bit timer 11/21 in 8-bit mode or 16-bit mode). ● Timer data registers (T11DR/T21DR and T12DR/T22DR) The value to be compared with the count in the 8-bit counter is set by writing the desired value into these registers. They can be read to determine the current counter values. ● Timer control registers(T11CR/T21CR and T12CR/T22CR) These registers are used to select the function, to enable or disable operation, control interrupts, and check the timer/counter status. 225 CHAPTER 11 8/16-BIT TIMER/COUNTER 11.3 Pins of 8/16-bit Timer/Counter This section describes the pins, pin block diagram, registers, and interrupt source of the 8/16-bit timer/counter. ■ Pins of 8/16-bit Timer/Counter The 8/16-bit timer/counter 11,12 uses the P27/V2/EC1 pin and P26/V1/TO1 pin. The 8/16-bit timer/counter 21,22 uses the P25/C0/EC2 and P24/C1/TO2 pins. The P27/V2/EC1, P25/C0/EC2 pins can function as a general-purpose I/O port (P25, P27) or external clock input pin of timer(EC1, EC2). The P26/V1/TO1, P24/ C1/TO2 pins can function as a general-purpose I/O port (P24, P26) or the square wave output pin of timer (TO1, TO2). EC1 and EC2: In timer 11/21 in the 8-bit mode or 16-bit mode, if external clock input (counter function) is selected (T11CR/T21CR: T1CS1 = 1, T1CS0 = 1), the counter counts the external clocks applied to this pin. The P27/V2/EC1, P25/C0/EC2 pins set the pin as an input port in the port direction register (DDR2: bit5, bit7 = 0) when using as the EC1 and EC2 pins. TO1 and TO2: In timer 11/21 in the 8-bit mode or 16-bit mode, a square wave is output at this pin. Enabling square wave output (T11CR/T21CR: T1OS1, T1OS0 = 11B) automatically sets the P26/V1/TO1, P24/C1/TO2 pins as an output pin, regardless of the port direction register (DDR2: bit5, bit7) value, and sets the pin to function as the TO1, TO2 pins. 226 ■ Block Diagram of 8/16-bit Timer Counter Pins Figure 11.3-1 Block Diagram of 8/16-bit Timer Counter Pins (P24, P25) External clock input (EC2) PDR (Port data register) Stop, watch mode Mask option * Timer output (TO2) Internal data bus PDR read Timer output enable Booster Mask option * PDR read (for bit manipulation instructions) Output latch Pin PDR write N-ch DDR P24/C1/TO2* P25/C0/EC2* (Port direction register) DDR write Stop, watch mode (SPL = 1) DDR read * : If booster is selected by mask option, EC2 and TO2 will be redirected to P03 and P04 respectively. SPL: Pin state specification bit in the standby control register (STBC) Figure 11.3-2 Block Diagram of 8/16-bit Timer/Counter Pins (P26, P27) External clock input (EC1) Stop, watch mode LCD pin select PDR (Port data register) LCD driver/booster Timer output (TO1) Internal data bus PDR read Timer output enable N-ch PDR read (for bit manipulation instructions) Output latch PDR write Pin DDR N-ch P26/V1/TO1 P27/V2/EC1 (Port direction register) DDR write DDR read Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 227 CHAPTER 11 8/16-BIT TIMER/COUNTER 11.4 Registers of 8/16-bit Timer/Counter This section describes the registers of the 8/16-bit timer/counter. ■ Registers of 8/16-bit Timer/Counter Figure 11.4-1 Registers of 8/16-bit Timer/Counter T11CR/T21CR (Timer 11/21 control register) Address 003BH 0037H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000000X0B T1IF T1IE T1OS1 T1OS0 T1CS1 TS1CS0 T1STP T1STR R/W R/W R/W R/W R/W R/W R/W R/W bit3 bit2 bit1 bit0 Initial value 000000X0B T12CR/T22CR (Timer 12/22 control register) Address 003AH 0036H bit7 bit6 bit5 bit4 T2IF T2IE T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR R/W R/W R/W R/W R/W R/W R/W R/W bit3 bit2 bit1 bit0 T11DR/T21DR (Timer 11/21 data register) Address 003DH 0039H bit7 bit6 bit5 bit4 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit3 bit2 bit1 bit0 T12DR/T22DR (Timer 12/22 data register) Address 003CH 0038H bit7 bit6 bit5 bit4 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined value ■ Interrupt Source of 8/16-bit Timer/Counter IRQ6: In the interval timer and counter functions for timer 11 in 8-bit mode or 16-bit mode, timer 12 in 8-bit mode, if the interrupt request output is enabled, an IRQ6 interrupt request will be generated when the count in the counter equals the value set in the data register. Interrupt request outputs are enabled by setting the proper timer control register bit (T11CR: T1IE = 1 in Timer 11 in 8-bit mode or 16-bit mode, T12CR: T2IE = 1 in Timer 12 in 8-bit mode). IRQ7: In the interval timer and counter functions for timer 21 in 8-bit mode or 16-bit mode, timer 22 in 16-bit modes, if the interrupt request output is enabled, an IRQ7 interrupt request will be generated when the count in the counter equals the value set in the data register. Interrupt request outputs are enabled by setting the proper timer control register bit (T21CR: T1IE = 1 in Timer 21 in 8-bit mode or 16-bit mode, T22CR: T2IE = 1 in Timer 22 in 8-bit mode). 228 11.4.1 Timer 11/21 Control Register (T11CR/T21CR) In Timer 11/21 in the 8-bit mode and in the 16-bit mode, the timer 11/21 control register (T11CR/T21CR) is used to select functions, to enable/disable operation, to control interrupts, and to check status. In the 8-bit mode, the timer 12/22 control register (T12CR/T22CR) must still be initialized, even only Timer 11/21 is used. ■ Timer 11/21 Control Register (T11CR/T21CR) Figure 11.4-2 Timer 11/21 Control Register (T11CR/T21CR) Address bit7 bit6 003BH 0037H T1IF T1IE R/W R/W bit5 bit4 bit3 bit2 bit1 bit0 Initial value T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR R/W R/W R/W R/W R/W R/W Timer activation bit T1STR 0 Stops counter 1 Clears counter, then starts it Timer stop bit T1STP 0 Causes counter to resume counting without clearing 1 Temporarily stops counter T1CS1 T1CS0 Count clock selection bits (tinst: instruction cycle) 0 0 2 tinst 0 1 32 tinst 1 0 512 tinst 1 1 External clock Square wave output control bits T1OS1 T1OS0 0 0 Use pin for general-purpose port 0 1 Set data to output square wave "L" state 1 0 Set data to output square wave "H" state 1 1 Output set level at square wave output pin (TO1/ TO2) T1IE Interrupt request enable bit 0 Disable interrupt request output 1 Enable interrupt request output T1IF R/W X : Readable/Writable : Undefined value : Initial value 000000X0B Interrupt request Flag Bit Read Write 0 No counter match Clears this bit 1 Have counter match No effect: The bit does not change. *: The square wave output pin will go to the level corresponding to data set when T1STR is "0". 229 CHAPTER 11 8/16-BIT TIMER/COUNTER Table 11.4-1 Timer 11/21 Control Register (T11CR/T21CR) Bits Bit name Function bit7 T1IF: Interrupt request flag bit • 8 bit-mode: Set to "1" when the count in the timer 11/21 counter matches the value set in the T11DR/T21DR, the timer 11/21 data register (comparison data latch). • 16-bit mode: Set to "1" when the counts in the timer 11/21 and timer 12/22 counters match the values set in the T11DR/T21DR and T12DR/T22DR registers, respectively. • An interrupt request is output when both this bit and the interrupt request enable bit (T1IE) are "1". • Writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit6 T1IE: Interrupt request enable bit • This bit enables or disables an interrupt request output to the CPU. • An interrupt request is output when both this bit and the interrupt request flag bit (T1IF) are "1". T1OS1 and T1OS0: square wave output control bits • P26/V1/TO1 or P24/C1/TO2 is a general-purpose I/O port pin (P24, P26) if both of these bits are "00B". If the bits are not "00B", it is the square wave output pin (TO1 or TO2). • If written to "01B", or "10B", the initialize data will be set in the square wave output controller, but the corresponding level will not be output to the TO1 or TO2 pin. • If both bits are "11B", and the function is in the stop timer state (T2STR= 0), the TO1 or TO2 pin is set to a level corresponding to the initialize data. bit3, bit2 T1CS1 and T1CS0: Clock source selection bits • Selects the count clock to be supplied to the counter. • Selects one of three internal clocks, or an external clock. • When both bits are "11B", Timer 11/21 operates as a counter with the external clock is selected as the count clock. Note: If external clock input is selected (T1CS1, T1CS0 = 11B), set the P27/V2/EC1, P25/C0/EC2 pin as an input port pin. bit1 T1STP: Timer stop bit • This bit is used to temporarily stop the counter. • Writing this bit to "1" temporarily stops the counter. Writing it to "0" when the timer in startup state (T1STR = 1), restarts the counter where it left off. T1STR: Timer activation bit • Starts and stops timer. • Changing this bit from "0" to "1" clears the counter. At this time, if the timer is in the continuous operation mode (T1STP = 0), the counter starts (counts up, clocked by the selected count clock). Writing this bit to "0" stops the counter. • In the 16-bit mode, both Timer 11/21 and Timer 12/22 are cleared at timer start (T1STP = 0 -> 1). bit5, bit4 bit0 Note: Before using 8/16-bit timer/counter Timer 11/21 only in 8-bit mode, first set the timer count clock selection bits of the Timer 12/22 control register (T12CR/T22CR: T2CS1, T2CS0) to some state other than "11B". Operating in this mode without making this register setting could result in faulty operation. 230 11.4.2 Timer 12/22 Control Register (T12CR/T22CR) In timer 12/22 in the 8-bit mode, the timer 12/22 control register (T12CR/T22CR) is used to select functions, to enable/disable operation, to control interrupts, and to check states. In the 16-bit mode, although the function is controlled by the timer 11/21 control register (T11CR/T21CR), the timer 12/22 control register (T12CR/T22CR) must still be set. ■ Timer 12/22 Control Register (T12CR/T22CR) Figure 11.4-3 Timer 12/22 Control Register (T12CR/T22CR) Address bit7 bit6 003AH 0036H T2IF T2IE R/W R/W bit5 bit4 bit3 bit2 bit1 bit0 Initial value T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR R/W R/W R/W R/W R/W 000000X0B R/W Timer activation bit T2STR 0 Stops counter 1 Clears counter, then starts it T2STP Timer stop bit 0 Causes counter to resume counting without clearing 1 Temporarily stops counter T2CS1 Count clock selection bits T2CS0 0 0 2 tinst 0 1 32 tinst 1 0 512 tinst 1 1 16-bit mode T2OS1 T2OS0 Unused bits 0 0 0 1 These two bits must set to "00B". 1 0 Do not set to other value. 1 1 T2IE interrupt request enable bit 0 Disables interrupt request output 1 Enables interrupt request output interrupt request flag bit T2IF R/W : Readable/Writable X : Undefined value : Initial value Read Write 0 No counter match Clears this bit 1 Have counter match No effect: The bit does not change. 231 CHAPTER 11 8/16-BIT TIMER/COUNTER Table 11.4-2 Timer 12/22 Control Register (T12CR/T22CR) Bits Bit name Function T2IF: Interrupt request flag bit • Set to "1" when the count in the timer 12/22 counter matches the value set in the T12DR/T22DR, the timer 12/22 data register (comparison data latch). • An interrupt request is output when both this bit and the interrupt request enable bit (T2IE) are "1". • Writing "0" clears this bit. writing "1" has no effect and does not change the bit value. Note : In the 16-bit mode, the T1IF bit is the valid interrupt request flag, and the T2IF bit has no effect. bit6 T2IE: Interrupt request enable bit • This bit enables or disables an interrupt request output to the CPU. • An interrupt request is output when both this bit and the interrupt request flag bit (T2IF) are "1". Note : In the 16 bit mode, the T1IE bit is the valid interrupt request enable bit, and the T2IE bit has no effect. bit5, bit4 T2OS1 and T2OS0: Unused bits • These two bits must set to "00B". • Do not set to other value. T2CS1 and T2CS0: Clock source selection bits • Selects the count clock to be supplied to the counter. • Selects one of three internal clocks. • Setting to "11B" selects the 16-bit mode. Note : In 16-bit mode, T1CS1 and T1CS0 select the clock. T2CS1 and T2CS0 serve only to select the 16 bit-mode. T2STP: Timer stop Bit • This bit is used to temporarily stop the counter. • Writing this bit to "1" temporarily stops the counter. Writing it to "0" when the timer startup state (T2STR) is "1", restarts the counter where it left off. Note : In 16-bit mode, T1STP is the stop bit, and T2STP has no effect. T2STR: Timer activation bit • Starts and stops timer. • Changing this bit from “0” to "1" clears the counter. At this time, if the timer is in the continuous operation mode (T2STP = 0), the counter starts (counts up, clocked by selected count clock). Writing this bit to "0" stops the counter. Note : In 16-bit mode, T1STR is the start bit, and T2STR has no effect. bit7 bit3, bit2 bit1 bit0 Note: When using timer 12/22 in the 16-bit mode, set T2CS1 and T2CS0 to "11B"; then use the T11CR/ T21CR register to control the circuit. 232 11.4.3 Timer 11/21 Data Register (T11DR/T21DR) The timer 11/21 data register (T11DR/T21DR) is used to set all or part of the interval time or counter value, and to read out all or part of the counter value, depending on the mode and function being used. In 8-bit mode, it sets the timer 11/21 interval timer (interval timer function) or counter value (counter function), and reads out the counter value. In 16-bit mode, it sets the 8 LSBs of the 16-bit timer interval (interval timer function) or counter value (counter function), and reads out the counter value. ■ Timer 11/21 Data Register (T11DR/T21DR) The value set into this register is compared with the counter value (count). If you read the register, you get the current counter value. The register setting cannot be read out. Figure 11.4-4 shows the bit structure of the timer 11/21 data register. Figure 11.4-4 Timer 11/21 Data Register (T11DR/T21DR) Address 003DH 0039H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable ● 8-bit mode (Timer 11/21) • The value in this register is compared with the count in the timer 11/21 counter. For the interval timer function, it sets the interval time, and for the counter function, it sets the count to be detected. When count operation enabled (T11CR/T21CR: T1STR = 0 -> 1, T1STP = 0), the value in the T11DR/T21DR register is loaded into the comparison data latch, and the counter starts counting up. • When the counter counts up to where it matches the value in the comparison data latch, the value in the T11DR/T21DR register is re-loaded into the comparison data latch, and the counter is cleared and continues to count. • Since the comparison data latch is reloaded when a match is detected, if a new value is loaded into the T11DR/T21DR register while the counter is counting, the new value will not take effect until the next count cycle (after a match is detected in the current cycle). Reference : The T11DR/T21DR register setting for interval timer operation can be calculated using the following formula. (The instruction cycle time is affected by the clock mode, and the speed-shift selection.) T11DR/T21DR register value = interval time/(count clock cycle × instruction cycle) -1 233 CHAPTER 11 8/16-BIT TIMER/COUNTER ● 16-bit mode The value in this register is compared with the counter value for the lower 8 bits (LSBs) of the 16-bit timer. In the interval timer function, this sets the lower 8 bits of the interval time setting, and in the counter function, the lower 8 bits of the count to be detected. The contents of the T11DR/T21DR register are loaded into the lower 8 bits of the comparison data latch when the counter first starts operating and when a match is detected in the 16-bit count. Therefore, if a new value is loaded into the T11DR/T21DR register while the 16-bit counter is counting, the new value will not take effect until after the next match is detected. For information on T11DR/T21DR register settings in the interval timer mode, refer to "11.4.4 Timer 12/ 22 Data Register (T12DR/T22DR)". 234 11.4.4 Timer 12/22 Data Register (T12DR/T22DR) The timer 12/22 data register (T12DR/T22DR) is used to set all or part of the interval time or counter value, and to read out all or part of the counter value, depending on the mode and function being used. In 8-bit mode, it sets the Timer 12/22 interval timer (interval timer function) or counter value (counter function), and reads out the counter value. In 16-bit mode, it sets the 8 LSBs of the 16-bit timer interval (interval timer function) or counter value (counter function), and reads out the counter value. ■ Timer 12/22 Data Register (T12DR/T22DR) The value set into this register is compared with the counter value (count). If you read the register, you get the current counter value. The register setting cannot be read out. Figure 11.4-5 shows the bit structure of the timer 12/22 data register. Figure 11.4-5 Timer 12/22 Data Register (T12DR/T22DR) Address 003CH 0038H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable ● 8-bit mode (Timer 12/22) The value in this register is compared with the count in the timer 12/22 counter. For the interval timer function, it sets the interval time, and for the counter function, it sets the count to be detected. The value in the T12DR/T22DR register is reloaded into the comparison data latch when counter operation starts, and when a match is detected. If a new value is loaded into the T12DR/T22DR register while the counter is counting, the new value will not take effect until the next count cycle (after a match is detected in the current cycle). Reference : The T12DR/T22DR register setting for interval timer operation can be calculated using the following formula. (The instruction cycle time is affected by the clock mode, and speed-shift selection.) T12DR/T22DR register value = interval time/(count clock cycle × instruction cycle time) -1 235 CHAPTER 11 8/16-BIT TIMER/COUNTER ● 16-bit mode The value in this register is compared with the counter value for the upper 8 bits (MSBs) of the 16-bit timer. In the interval timer function, this sets the upper 8 bits of the interval time setting, and in the counter function, the upper 8 bits of the count to be detected. The contents of the T12DR/T22DR register are loaded into the upper 8 bits of the comparison data latch when the counter first starts operating and when a match is detected in the 16-bit count. Therefore, if a new value is loaded into the T12DR/T22DR register while the 16-bit counter is counting, the new value will not take effect until after the next match is detected. In the 16-bit mode, the operation of the counter is controlled by the Timer 11/21 control register (T11CR/ T21CR). Reference : In the interval timer function, the T11DR/T21DR and T12DR/T22DR register settings can be calculated from the following formula. (The instruction cycle time is affected by the clock mode, and the speed-shift selection.) 16-bit data value = interval time/(count clock cycle × instruction cycle) -1 The 8 MSBs of the 16-bit data value are the T12DR/T22DR register setting, and the 8 LSBs are the T11DR/T21DR register setting. 236 11.5 8/16-bit Timer/Counter Interrupt In the 8/16-bit timer/counter, interrupt conditions are satisfied (if interrupts are enabled) when the counter matches the data register. This is true for both the interval timer and counter functions. ■ 8/16-bit Timer/Counter Interrupt Table 11.5-1 lists the interrupt request flag bit, interrupt request output enable bit, and interrupt source of the 8/16-bit timer/counter. Table 11.5-1 8/16-bit Timer/Counter Interrupt Control Bits and Interrupts 8-bit mode 16-bit mode Timer 11/21 and Timer 12/22 Timer 11/21 Timer 12/22 Timer 11/12 + Timer 12/22 Interrupt request flag bit T11CR/T21CR:T1IF T12CR/T22CR:T2IF T11CR/T21CR:T1IF interrupt request enable bit T11CR/T21CR:T1IE T12CR/T22CR:T2IE T11CR/T21CR:T1IE Interrupt source 8-bit counter matches T11DR/T21DR 8-bit counter matches T12DR/T22DR 16-bit counter matches T11DR/T21DR and T12DR/T22DR In 8-bit mode, 8/16-bit timer/counter interrupt requests are generated independently for Timer 11/21 and Timer 12/22. In 16-bit mode, the interrupt request is generated only for Timer 11/21, but basic operation is the same. Interrupt operation will therefore be described only for Timer 11/21 in 8-bit mode. ■ 8-bit Mode Timer 11/21 Interrupt Operation The counter counts up from "00H", clocked by the selected count clock. When the count in the counter matches the value in the comparison data latch (corresponding to the value in timer data register T11DR/ T21DR), the interrupt request flag bit is set to "1" (T11CR/T21CR: T1IF). At this time, an interrupt request (IRQ6, IRQ7) to the CPU is generated if the interrupt request enable bit is enabled (T11CR/T21CR: T1IE=1). Write "0" to the T1IF bit in the interrupt processing routine to clear the interrupt request. The T1IF bit is set to "1" when the counter value matches the set value, regardless of the value of the T1IE bit. Notes : • The T1IF bit is not set if the counter is stopped (T11CR/T21CR: T1STR = 0) at the same time as the counter value matches the T11DR/T21DR1 register. • An interrupt request is generated immediately if the T1IF bit is "1" when the T1IE bit is changed from disabled to enabled ("0" -> "1"). 237 CHAPTER 11 8/16-BIT TIMER/COUNTER ■ Registers and Vector Table for 8/16-bit Timer/Counter (11, 12, 21, 22) Interrupt Table 11.5-2 Registers and Vector Table for 8/16-bit Timer/Counter Interrupt Interrupt level settings register Vector table address Interrupt Register Setting bits Upper Lower IRQ6 (Timer ch.1) ILR2 (007CH) L61 (bit5) L60 (bit4) FFEEH FFEFH IRQ7 (Timer ch.2) ILR2 (007CH) L71 (bit7) L70 (bit6) FFECH FFEDH See "3.4.2 Interrupt Processing" for details on the interrupt operation. 238 11.6 Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8/16-bit timer/ counter (11, 12, 21, 22). ■ Operation of Interval Timer Function ● 8-bit mode Figure 11.6-1 shows the settings required to operate Timer 11/21 as the interval timer function in the 8-bit mode. Figure 11.6-1 Interval Timer Function (Timer 11/21) Settings T11CR/T21CR bit7 bit6 T1IF T1IE bit5 bit4 bit3 bit2 bit1 bit0 T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR other than “11” T11DR/T21DR T12CR/T22CR Sets the interval time (compare value). T2IF T2IE x x : Used bit T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR 0 0 other than “11” x x x : Unused bit 0: Set "0". Figure 11.6-2 shows the settings required to operate Timer 12/22 as the interval timer function in the 8-bit mode. Figure 11.6-2 Interval Timer Function (Timer 12/22) Settings T12CR/T22CR bit7 bit6 T2IF T2IE bit5 bit3 bit2 bit1 bit0 T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR 0 T12DR/T22DR bit4 0 other than “11” Sets the interval time (compare value). : Used bit 0: Set "0". On activation in 8-bit mode, the counter starts counting-up from "00H", on the rising edge of the selected count clock. Eventually, the count in the counter will match the value set in the data register (comparison data latch). When this occurs, interrupt request flag bit in the timer control register (T11CR/T21CR: T1IF) is set to "1", and the counter starts counting-up again from "00H". If using timer 11/21, the output of the square wave output control circuit is inverted when a match is detected; and if square wave output is enabled (T11CR/T21CR: T1OS1, T1OS0 = values other than "00B"), a square wave is output at the TO1 or TO2 pin. Figure 11.6-3 shows, operation of the interval timer function in the 8-bit mode. 239 CHAPTER 11 8/16-BIT TIMER/COUNTER Figure 11.6-3 Operation of Interval Timer Function in 8-bit Mode (Timer 12/22) Counter value Compare value (E0H) Compare value (FFH) FFH E0H 80H 00H Time T11DR/T21DR value modified (E0H T11DR/T21DR value (E0H) T1IF bit Activate FFH)*1 Cleared by the program Match Match Match Counter Clear *2 T1STR Bit (T1STP = 0) TO1 Pin TO2 Pin *1 If a new value is written to the data register during counter operation, the new value is used from the next cycle. *2 At activation, and each time a match is detected, the counter is cleared and the data register setting is loaded into the comparison data latch. ● 16-bit mode Figure 11.6-4 shows the settings required to operate as the interval timer function in the 16-bit mode. Figure 11.6-4 Interval Timer Function Settings (16-bit Mode) T11CR/T21CR bit7 bit6 T1IF T1IE bit5 bit4 bit3 bit2 bit1 bit0 T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR Other than "11" T12CR/T22CR T11DR/T21DR T12DR/T22DR T2IF T2IE x x T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR 0 0 1 1 x x Sets the interval time (lower8 bits). Sets the interval time (upper8 bits). : Used bit x : Unused bit 1: Set “1”. 0: Set “0”. In 16-bit mode, the timer 11/21 control register (T11CR/T21CR) controls the timer. The timer 12/22 control register (T12CR/T22CR) must, however, still be initialized. The data to be compared with the 16bit counter is set in both data registers: the upper 8 bits in T12DR/T22DR and the lower 8 bits in T11DR/ T21DR. All 16 bits of the counter are cleared simultaneously. All other operation in the 16-bit mode is the same as Timer 11/21 operation in 8-bit mode. 240 11.7 Operation of Counter Function This section describes the operations of the counter function of the 8/16-bit timer/ counter. ■ Operation of Counter Function ● 8-bit mode Figure 11.7-1 shows the settings required to operate the timer 11/21 as the counter function in the 8-bit mode. Figure 11.7-1 Counter Function Settings (8-Bit Mode) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 × 0 × 0 × × × x T1IF T1IE DDR2 T11CR/T21CR T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR 1 1 Sets value to be compared with counter. T12CR/T22CR T2IF T2IE × × T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR 0 0 Other than “11” × : Used bit × : Unused bit 1: Set "1" 0: Set "0" × Counter operation in the 8-bit mode is the same as interval timer operation of timer 11/21 in 8-bit mode, except that an external clock is used in lieu of the internal clock. ● 16-bit mode Figure 11.7-2 shows the settings required to operate as the counter function in the 16-bit mode. Figure 11.7-2 Counter Function Settings (16-bit Mode) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 × 0 × 0 × × × x T1IF T1IE DDR2 T11CR/T21CR T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR 1 T12CR/T22CR T2IF T2IE × × 1 T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR 0 0 1 1 T11DR/T21DR Sets the interval time (lower 8 bits). T12DR/T22DR Sets the interval time (upper 8 bits). × x : Used bit × : Unused bit 1: Set "1". 0: Set "0". 241 CHAPTER 11 8/16-BIT TIMER/COUNTER Counter operation in the 16-bit mode is the same as interval timer operation in 16-bit mode, except that an external clock is used in lieu of the internal clock. Figure 11.7-3 shows the operation of the counter function in the 16-bit mode. Figure 11.7-3 Operation of Counter Function in 16-bit Mode External clock Counter clear T1STR bit (T1STP = 0) Counter value 0000H 0001H 0002H 0003H 1388H 0000H 0001H Comparison data latch 1 (compared with lower 8 bits) 88H 34H Comparison data latch 2 (compared with upper 8 bits) 13H 12H T11DR/T21DR register* (lower 8 bits setting) T12DR/T22DR register* (upper 8 bits setting) T11CR/T21CR: T1IF/T3IF Load Load 88H 34H 13H 12H Data set (to 1234H) Cleared by the program. * The desired timing and desired settings can be used. At activation, and each time a match is detected, the data register settings are loaded into the comparison data latches, and the counter is cleared. Note : When the counter value during operation is read out in 16-bit mode, always read it twice, and verify that a proper value is got before using it. 242 11.8 Operation of the Square Wave Output Initial Setting Function The square wave output can be set to the desired initial value using the timer 11/21 control register (T11CR/T21CR). ■ Operation of Square Wave Output Initial Setting Function The square wave output can be set to the desired initial value by the program, but this can be done only when the timer operation is stopped (T11CR/T21CR: T1STR = 0). Figure 11.8-1 shows an equivalent circuit for the square wave output control circuit initial setting. To perform the initial setting, follow the procedure in Table 11.8-1. The operation of the square wave output when this is done is as shown in Figure 11.8-2. Figure 11.8-1 Square Wave Output Initial Setting Equivalent Circuit Output enable signal T1STR T1OS1 Level latch D Q > Q D Q > Q Level latch T1OS0 D Q D Q > Q > Q Sets output pin "H" (to SET pin of T.FF) Sets output pin "L" (to RST pin of T.FF) Write strobe signal Table 11.8-1 Square Wave Output Initial Setting Procedure (T11CR/T21CR Register) Step Settings and Operation (1) To set the square wave output pin (TO1, TO2) "L" level, set the square wave output control bits (T11CR/T21CR: T1OS1, T1OS0) first to "01B", then to "11B". To set the TO1 pin "H" level, set the bits to "10B", then "11B". Note : Until the bits are written to "11B", the circuit simply holds the latched value, and the square wave output, TO1 or TO2 pin level remains in its current or previous state. (2) If the square wave output control bits (T1OS1, T1OS0) are written to "11B" and the timer operation stopped (T1STR = 0), the TO1 pin will output the level corresponding to the level latch value (initial value). This can also be accomplished by setting T1OS1, T1OS0, and T1STR simultaneously. If the timer activation bit is set (T1STR= 1), the counter will start. (3) The square wave output is inverted each time the counter value matches the data register settings. 243 CHAPTER 11 8/16-BIT TIMER/COUNTER Figure 11.8-2 Square Wave Output Initial Setting Operation P26/V1/TO1 P24/C1/TO2 Pin state Port *1 Timer *2 Previous square wave output value Square wave output (1) Setting value (2) (3) *1: When both T1OS1 bit and T1OS0 bit of the T11CR/T21CR register is "0", the P26/V1/TO1 or P24/C1/TO2 pin is a general-purpose port (P26 or P24). *2: If both T1OS1 and T1OS2 bit is "1", the P26/V1/TO1 pin is a square wave output pin (TO1), the P24/C1/TO2 pin is a square wave output pin (TO2). 244 11.9 Operation of 8/16-bit Timer/Counter Stop and Restart This section describes the stop and restart operation functions of the 8/16-bit timer/ counter. ■ Timer Stop and Restart Operation is described for timer 11/21 only. Timer 12/22, however, operates the same way. Timer 11/21 is stopped and restarted using the timer stop bit and timer activation bit in the timer 11/21 control register (T11CR/T21CR: T1STP and T1STR). • To start the counter after clearing it Set T1STP, T1STR bit to "01B". On the T1STR bit rising edge, the counter will be cleared and start counting. • To temporarily stop the timer and then resume counting (without clearing the counter) First stop the counter by setting T1STP, T1STR to "11B", then set T1STP, T1STR to "01B" to resume counting where you left off. Table 11.9-1 lists the timer states for each T1STP, T1STR bit, and operation when the timer is activated from that state (T1STP, T1STR = 01B). Table 11.9-1 Timer Stop and Restart Timer operation when counter is activated (T1STP, T1STR=01B) from the state shown at the left T1STP (T2STP) T1STR (T2STR) 0 0 Counter stopped Counter cleared and starts counting 0 1 Counter operating Counter keeps on operating as it is. 1 0 Counter stopped Counter cleared and starts counting 1 1 Counter temporarily stopped Counter resumes counting without being cleared Timer State 245 CHAPTER 11 8/16-BIT TIMER/COUNTER 11.10 States in Each Mode during 8/16-bit Timer/Counter Operation This section describes the operation of the 8/16-bit timer/counter when the device changes to sleep or stop mode or an operation halt request occurs during operation. ■ Operation during Standby Mode or Operation Halt • Figure 11.10-1 shows the counter value state when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or counter function (for timer 11/21). • The counter halts and maintains its current value when the device changes to stop mode. Operation starts again from the stored counter value after wake-up from stop mode by an external interrupt. therefore, the first interval time or external clock count is not correct value. Always initialize the 8/16bit timer/counter after wake-up from stop mode. • Operation when entering or exiting watch mode (STBC: TMD = 1) is the same as when entering or exiting stop mode. The watch mode is waked up by the watch interrupt and external interrupt. When the counter is stopped temporarily (T1STP = 1), it holds the count it had when it was stopped. • When it is restarted (T1STP= 0), it resumes counting from the count at which it was stopped. Figure 11.10-1 Counter Operation during Standby Mode or Operation Halt Counter value Data register setting 0000H Activate Match Match Match Match Counter clear T1STR bit Cleared by the program. T1IF bit * TO1 pin TO2 pin SLP bit (STBC register) STP bit (STBC register) Sleep mode Wake-up from sleep mode by IRQ6/IRQ7 Stop mode External interrupt Temporary stop T1STP bit *: The TO1 or TO2 pin goes to the high-impedance state during stop mode if the pin state specification bit in the standby control regisater (STBC: SPL) is "1" and the TO1 or TO2 pin is not set to with a pull-up resistor. When the SPL bit is "0", the pin maintains its value prior to changing to stop mode. 246 Match Match Time 11.11 Notes on Using 8/16-bit Timer/Counter This section lists points to note when using the 8/16-bit timer/counter. Those points can apply on Timer 11/21 and 12/22. ■ Notes on Using 8/16-bit Timer/Counter ● Notes when counter is stopped This information is described for timer 11/21, but the same information applies to timer 12/22. As shown in Figure 11.11-1, if the clock is "L" when T1STP temporarily stops the timer, the count will be incremented by 1. This may also occur if the input clock is "L" after a temporary stop, and the T1STP and T1STR bits are both written to "00B" simultaneously. When using the T1STP bit to temporarily stop the counter, first read out the counter value; then write T1STP bit to “0”. Figure 11.11-1 shows the operation when the timer stop bit is used. Figure 11.11-1 Operation when Timer Stop Bit is Used When input clock is "L" When input clock is "H" Clock input to the timer (EC1/EC2, internal clock) Counter value T1STP, T1STR bits (T11CR/T21CR register) 01H 02H 01 Temporary stop 01H 11 00 Stop 02H 01 Temporary stop 03H 04H 11 00 Stop ● Error Activating of 8/16-bit timer/counter by program is not synchronized with the start of counting-up using the selected count clock. Therefore, the time from activating the counter to match the register setting may be shorter than the theoretical time by a maximum of one cycle of the count clock. Figure 11.11-2 shows the error that occurs on starting counter operation. 247 CHAPTER 11 8/16-BIT TIMER/COUNTER Figure 11.11-2 Error on Starting Counter Operation Counter value 0 1 2 3 4 Count clock One cycle Error Cycle for 0 count Counter activates ● Using one 8-bit channel When 8/16-bit timer/counter timer 11/21 only is used in the 8-bit mode, before doing so, first set the timer count clock select bits of the timer 12/22 control register (T12CR/T22CR: T2CS1, T2CS0) to some state other than "11B". No setting to do so may result in faulty operation. ● Notes on setting by program • When the 8/16-bit timer/counter timer only is used in the 16-bit mode, count clock select bits of the timer 12/22 control register (T12CR/T22CR: T2CS1, T2CS0) should always be set to "11B", and bits 5 and 4, the unused bits (T12CR/T22CR: T2OS1, T2OS0) to "00B". • In 16-bit mode, when the counter value is read out during operation, always read it twice and verify that a proper value is got before using it. • While the timer is operating (T11CR/T21CR: T1STR = 1), performing the initial state setting will not immediately cause the square wave output level to change. The output state will be initialized when the timer stops. • Interrupt processing cannot return if the interrupt request flag bit (T11CR/T21CR: T1IF, T12CR/ T22CR: T2IF) is "1" and the interrupt request enable bit is enabled (T11CR/T21CR: T1IE = 1, T12CR/ T22CR: T2IE = 1). Always clear the interrupt request flag bit. • The interrupt request flag bit (T11CR/T21CR: T1IF or T12CR/T22CR: T2IF) is not set if the counter is disabled by the timer start bit (T11CR/T21CR: T1STR = 0 or T12CR/T22CR: T2STR = 0) at the same time as an interrupt source is generated. 248 11.12 Program Examples for 8/16-bit Timer/Counter This section gives a program examples for 8/16-bit timer/counter. ■ Program Example for Interval Timer Function ● Processing description • Using Timer ch.1 only, in 8-bit mode, generates interval timer interrupts at 20 ms intervals. • Outputs a square wave to the TO1 pin that inverts after each interval time. • With a main clock master oscillation FCH of 12.5 MHz, and the highest speed main clock selected by the speed-shift function (1 instruction cycle time = 4/FCH), and with an internal clock period of 512 tinst selected as the count clock, the T11DR setting for an interval of approximately 20 ms is calculated as follows: T11DR register value = 20 ms/(512 × 4/12.5 MHz) - 1 = 122.07 (7AH) ● Coding example T12CR EQU 003AH ; Address of the Timer 12 control register T11CR EQU 003BH ; Address of the Timer 11 control register T12DR EQU 003CH ; Address of the Timer 12 data register T11DR EQU 003DH ; Address of the Timer 11 data register T1IF EQU T11CR:7 ; Define the timer Ch1 interrupt request flag bit. ILR2 EQU 007CH ;Address of the interrupt level setting register 2 INT_V DSEGABS ORG0 IRQ6 FFEEH DW WARI ;Set interrupt vector. ENDS ;----------Main program----------------------------------------------------------------------------------------------------CSEG ;[CODE SEGMENT] ;Stack pointer (SP) etc. are already initialized. : CLRI ;Disable interrupts. MOV MOV ILR2,#11101111B T12CR,#00000010B MOV T11CR,#00011000B ;Set interrupt priority to level 2. ;Clear timer 12 interrupt request flag, disable interrupt request output, set other than 16-bit mode, stop operation. ; Clear timer 11 interrupt request flag, initialize square wave output 249 CHAPTER 11 8/16-BIT TIMER/COUNTER ; "L", select 512 tinst, and stop operation. MOV T11DR,#7AH ; Set value compared with the counter value (interval time). MOV T11CR,#11111001B ; timer 11 interrupt request, clear counter, and start timer. SETI ; Enable CPU interrupts. : : ;----------Interrupt Program------------------------------------------------------------------------------------------------WARI CLRB T1IF PUSHW A XCHW A,T PUSHW A ; Clear interrupt request flag. : User processing : POPW A XCHW A,T POPW A RETI ENDS ;-------------------------------------------------------------------------------------------------------------------------------END 250 ■ Program Example for Pulse Counter Function ● Processing description • Using Timer ch.1 in 16-bit mode, count external clocks input to the EC1 pin, and generate an interrupt once for each 5000 clocks (1388H). • Shows a sample program (READ16) for reading out the count in the 16-bit counter, while the counter is counting. ● Coding example DDR2 EQU 0006H ; Address of the Port 2 direction register T12CR EQU 003AH ; Address of the Timer 12 control register T11CR EQU 003BH ; Address of the Timer 11 control register T12DR EQU 003CH ; Address of the Timer 12 data register T11DR EQU 003DH ; Address of the Timer 11 data register T1IF EQU T11CR:7 ; Define the timer Ch1 interrupt request flag bit. ILR2 EQU 007CH ; Address of the interrupt level setting register 3 NT_V DSEG ABS ORG 0FFEEH IRQ6 DW WARI ; Set interrupt vector. ENDS ;----------Main program----------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) etc. are already initialized. MOV DDR2,#00000000B CLRI ; Set EC pin as an input. ; Disable interrupts. MOV ILR2,#11101111B ; Set interrupt level 2. MOV T11DR,#088H ; Set lower 8 bits of counter comparison value. MOV T12DR,#013H ; Set upper 8 bits of counter comparison value. MOV T12CR,#00001100B ; Set timer 12 to 16-bit mode. MOV T11CR,#01001101B SETI ; Clear timer 11 interrupt request flag, enable interrupt request output, set P26/V1/TO1 as general-purpose port (P26), select external clock, clear counter, and start operation. ; Enable CPU interrupts. ;----------Data read subroutine-------------------------------------------------------------------------------------READ16 MOVW A,T12DR ; 16-bit read, T11DR + T12DR. MOVW A,T12DR ; 16-bit read, T11DR + T12DR, save old value in T register. CMPW A ; Check first and second reads, compare A and T registers. BEQ RET16 ; If match, return. 251 CHAPTER 11 8/16-BIT TIMER/COUNTER XCHW A,T INCW A CMPW A BNE READ16 ; Old value + 1 ; If mismatch, read again. RET16 RET : ;----------Interrupt program-----------------------------------------------------------------------------------------WARI CLRB T1IF PUSHW A XCHW A,T PUSHW A ; Clear interrupt request flag. : User process : POPW A XCHW A,T POPW A RETI ENDS ;-------------------------------------------------------------------------------------------------------------------------------END 252 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) This chapter describes the functions and operation of the external interrupt 1 circuit (edge). 12.1 Overview of the External Interrupt 1 Circuit 12.2 Block Diagram of the External Interrupt 1 Circuit 12.3 Pins of the External Interrupt 1 Circuit 12.4 Registers of External Interrupt 1 Circuit 12.5 External Interrupt 1 Circuit Interrupts 12.6 Operation of the External Interrupt 1 Circuit 12.7 Program Example for the External Interrupt 1 Circuit 253 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.1 Overview of the External Interrupt 1 Circuit The external interrupt 1 circuit detects edges on the signals input to the four external interrupt pins and generates the corresponding interrupt requests to the CPU. ■ Functions of the External Interrupt Circuit 1 The function of the external interrupt 1 circuit is to detect specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU. These interrupts can cancel standby mode and return the device to the normal operating state (main RUN state). External interrupt pins: 4 pins (P10/SEG23/INT10 to P13/SEG26/INT13) External interrupt sources: Input of a specified edge (rising edge or falling edge) on the signal input to an external interrupt pin. 254 Interrupt control: Output of external interrupt requests is enabled or disabled by the interrupt request enable bits in external interrupt control registers 1 and 2 (EIC1, EIC2). Interrupt flags: Detection of specified edges sets the external interrupt request flag bits in external interrupt control registers 1 and 2 (EIC1, EIC2). Interrupt request: Separate interrupt requests are generated for each external interrupt source (IRQ0, IRQ1, IRQ2, IRQ3). 12.2 Block Diagram of the External Interrupt 1 Circuit The external interrupt 1 circuit consists of four blocks with the same functions. Each block contains the following two elements: • Edge detect circuits (10 to 13) • External interrupt control registers 1, 2 (EIC1, EIC2) ■ Block Diagram of the External Interrupt 1 Circuit Figure 12.2-1 Block Diagram of the External Interrupt 1 Circuit Pin P11/SEG24/INT11 Edge detect circuit 10 1 2 3 Selector Selector Edge detect circuit 11 1 2 3 Pin P10/SEG23/INT10 EIR1 SEL3 SEL2 EIE1 EIC1 EIR0 SEL1 SEL0 EIE0 IRQ0 IRQ1 P13/SEG26/INT13 Edge detect circuit 12 1 2 3 Selector Edge detect circuit 13 1 2 3 Selector Pin EIC1 Pin P12/SEG25/INT12 EIR3 SEL7 SEL6 EIE3 EIC2 IRQ3 EIR2 SEL5 SEL4 EIE2 EIC2 IRQ2 ● Edge detect circuit If the polarity of an edge on the input signal to one of the external interrupt 1 circuit pins (INT10 to INT13) matches the edge polarity specified for the pin in the EIC1 or EIC2 register (SEL0 to SEL7), the edge detect circuit sets the corresponding external interrupt request flag bit (EIR0 to EIR3) to "1". ● External interrupt control registers (EIC1, EIC2) The EIC1 and EIC2 registers are used for operations such as edge selection, enabling or disabling interrupt requests, and checking interrupt requests. 255 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.3 Pins of the External Interrupt 1 Circuit This section describes the pins, pin block diagram, registers, and external interrupt sources of the external interrupt 1 circuit. ■ Pins of External Interrupt 1 Circuit The external interrupt 1 circuit has four external interrupt pins. The external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or general-purpose I/O ports. Although the P10/SEG23/INT10 to P13/SEG26/INT13 pins continuously function as external interrupt input, the external interrupt 1 circuit does not output interrupt requests if output of interrupt requests is disabled for the pin. The pin states can be read directly from the port data register (PDR1) at any time. Table 12.3-1 Pins of External Interrupt 1 Circuit External Interrupt Pin When Used as an Input-Only Port When Used as an External Interrupt Input (Output of Interrupt (Output of Interrupt Requests Requests Enabled) Disabled) P10/SEG23/INT10 INT10 (EIC1: EIE0=1) P10 (EIC1: EIE0=0) P11/SEG24/INT11 INT11 (EIC1: EIE1=1) P11 (EIC1: EIE1=0) P12/SEG25/INT12 INT12 (EIC2: EIE2=1) P12 (EIC2: EIE2=0) P13/SEG26/INT13 INT13 (EIC2: EIE3=1) P13 (EIC2: EIE3=0) INT10 to INT13: The external interrupt 1 circuit generates the interrupt request for the pin when an edge of the specified polarity is input. ■ Block Diagram of the External Interrupt 1 Circuit Pins Figure 12.3-1 Block Diagram of the External Interrupt 1 Circuit Pins To external interrupt input External interrupt input enable PDR (Port data register) PDR read Internal data bus Stop, watch mode PDR read (for bit manipulation instructions) Output latch PDR write Pin DDR DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 256 LCD output enable N-ch P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 12.4 Registers of External Interrupt 1 Circuit This section describes the registers of the external interrupt 1 circuit. Figure 12.4-1 Registers of External Interrupt 1 Circuit EIC1 (External interrupt control register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0025H EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W IRQ1 INT11 IRQ0 INT10 EIC2 (External interrupt control register 2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0026H EIR3 SEL7 SEL6 EIE3 EIR2 SEL5 SEL4 EIE2 00000000B R/W R/W R/W R/W R/W R/W R/W R/W IRQ3 INT13 IRQ2 INT12 R/W : Readable /Writable ■ External Interrupt 1 Circuit Interrupt Sources IRQ0: This interrupt request is generated if an edge of the selected polarity is input to the external interrupt 1 circuit pin INT10 when output of interrupt requests is enabled. IRQ1: This interrupt request is generated if an edge of the selected polarity is input to the external interrupt 1 circuit pin INT11 when output of interrupt requests is enabled. IRQ2: This interrupt request is generated if an edge of the selected polarity is input to the external interrupt 1 circuit pin INT12 when output of interrupt requests is enabled. IRQ3: This interrupt request is generated if an edge of the selected polarity is input to the external interrupt 1 circuit pin INT13 when output of interrupt requests is enabled. 257 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.4.1 External Interrupt Control Register 1 (EIC1) External interrupt control register 1 (EIC1) is used to select the edge polarity and to control interrupts for external interrupt pins INT10, INT11. ■ External Interrupt Control Register 1 (EIC1) Figure 12.4-2 External Interrupt Control Register 1 (EIC1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0025H EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W EIE0 0 1 INT10 Interrupt request enable bit Disable output of interrupt requests. Enable output of interrupt requests. SEL1 SEL0 0 0 0 1 1 0 1 1 INT10 External interrupt request flag bit EIR0 0 1 Read Write The specified edge has not been input. Clear this bit. The specified edge has been input. No effect. The bit does not change. EIE1 0 1 INT11 Interrupt request enable bit Disable output of interrupt requests. Enable output of interrupt requests. SEL3 SEL2 0 0 0 1 1 0 1 1 EIR1 0 1 R/W : Readable/Writable : Initial value 258 INT10 Edge polarity selection bits No edge detection Rising edge Falling edge Both edges INT11 Edge polarity selection bits No edge detection Rising edge Falling edge Both edges INT11 External interrupt request flag bit Read The specified edge has not been input. The specified edge has been input. Write Clear this bit. No effect. The bit does not change. Table 12.4-1 External Interrupt Control Register 1 (EIC1) Bits Bit name Function bit7 EIR1: INT11 External interrupt request flag bit • This bit is set to "1" when the edge selected by INT11 edge polarity selection bits (SEL3, SEL2) is input to external interrupt pin INT11. • An interrupt request is output when both this bit and INT11 interrupt request enable bit (EIE1) are "1". • Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value. bit6, bit5 SEL3, SEL2: INT11 Edge polarity selection bits • Control the mode of the input edge polarity of INT11 pin • Writing "00" uses no edge detection, "01" uses rising-edge mode, "10" uses fallingedge mode or "11" uses both-edge mode. • Always write "0" into EIR1 when changing this bit. bit4 EIE1: INT11 Interrupt request enable bit Enables or disables output of interrupt requests to the CPU. An interrupt request is output when both this bit and INT11 external interrupt request flag bit (EIR1) are "1". bit3 EIR0: INT10 External interrupt request flag bit • This bit is set to "1" when the edge selected by INT10 edge polarity selection bits (SEL1, SEL0) is input to external interrupt pin INT10. • An interrupt request is output when both this bit and INT10 interrupt request enable bit (EIE0) are "1". • Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value. bit2, bit1 SEL1, SEL0: INT10 Edge polarity selection bits • Control the mode of the input edge polarity of INT10 pin • Writing "00" uses no edge detection, "01" uses rising-edge mode, "10" uses fallingedge mode or "11" uses both-edge mode. • Always write "0" into EIR0 when changing this bit. bit0 EIE0: INT10 Interrupt request enable bit Enables or disables output of interrupt requests to the CPU. An interrupt request is output when both this bit and INT10 external interrupt request flag bit EIR0) are "1". 259 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.4.2 External Interrupt Control Register 2 (EIC2) External interrupt control register 2 (EIC2) is used to select the edge polarity and to control interrupts for external interrupt pins INT12, INT13. ■ External Interrupt Control Register 2 (EIC2) Figure 12.4-3 External Interrupt Control Register 2 (EIC2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0026H EIR3 SEL7 SEL6 EIE3 EIR2 SEL5 SEL4 EIE2 00000000B R/W R/W R/W R/W R/W R/W R/W R/W EIE2 0 INT12 Interrupt request enable bit 1 Enable output of interrupt requests. Disable output of interrupt requests. SEL5 SEL4 0 0 1 Rising edge 1 0 Falling edge 1 1 Both edges INT12 External interrupt request flag bit Read Write 0 The specified edge has not been input. Clear this bit. 1 The specified edge has been input. No effect. The bit does not change. EIE3 0 INT13 Interrupt request enable bit 1 Enable output of interrupt requests. Disable output of interrupt requests. SEL7 SEL6 INT 13 Edge polarity selection bits 0 0 0 1 No edge detection 1 0 Falling edge 1 1 Both edges EIR3 260 No edge detection 0 EIR2 R/W : Readable/Writable : Initial value INT12 Edge polarity selection bits Rising edge INT13 External interrupt request flag bit Read Write 0 The specified edge has not been input. Clear this bit. 1 The specified edge has been input. No effect. The bit does not change. Table 12.4-2 External Interrupt Control Register 2 (EIC2) Bits Bit name Function bit7 EIR3: INT13 External interrupt request flag bit • This bit is set to "1" when the edge selected by INT13 edge polarity selection bits (SEL7, SEL6) is input to external interrupt pin INT13. • An interrupt request is output when both this bit and INT13 interrupt request enable bit (EIE3) are "1". • Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value. bit6, bit5 SEL7, SEL6: INT13 Edge polarity selection bits • Control the mode of the input edge polarity of INT13 pin • Writing "00" uses no edge detection, "01" uses rising-edge mode, "10" uses fallingedge mode or "11" uses both-edge mode. • Always write "0" into EIR3 when changing this bit. bit4 EIE3: INT13 Interrupt request enable bit Enables or disables output of interrupt requests to the CPU. An interrupt request is output when both this bit and INT13 external interrupt request flag bit (EIR3) are "1". bit3 EIR2: INT12 External interrupt request flag bit • This bit is set to "1" when the edge selected by INT12 edge polarity selection bits (SEL5, SEL4) is input to external interrupt pin INT12. • An interrupt request is output when both this bit and INT12 interrupt request enable bit (EIE2) are "1". • Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value. bit2, bit1 SEL5, SEL4: INT12 Edge polarity selection bits • Control the mode of the input edge polarity of INT12 pin • Writing "00" use no edge detection, "01" uses rising-edge mode, "10" uses fallingedge mode or "11" uses both-edge mode. • Always write "0" into EIR2 when changing this bit. bit0 EIE2: INT12 Interrupt request enable bit Enables or disables output of interrupt requests to the CPU. An interrupt request is output when both this bit and INT12 external interrupt request flag bit (EIR2) are "1". 261 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.5 External Interrupt 1 Circuit Interrupts The external interrupt 1 circuit can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. ■ Interrupts When the External Interrupt Circuit 1 is Operating On detecting a specified edge on an external interrupt input, the external interrupt circuit sets the corresponding external interrupt request flag bit (EIC1, EIC2 : EIR0 to EIR3) to "1". An interrupt request to the CPU (IRQ0 to IRQ3) is generated at this time if the corresponding interrupt request enable bit is enabled (EIC1, EIC2,: EIE0 to EIE3 = 1). Always write "0" to the corresponding external interrupt request flag bit in the interrupt processing routine to clear the interrupt request. Notes: • When enabling interrupts (EIE0 to EIE3 = 1) after exit of a reset, always clear the corresponding external interrupt request flag bit (EIR0 to EIR3 = 0) at the same time. Interrupt processing cannot return if the external interrupt request flag bit is "1" and the interrupt request enable bit is enabled. Always clear the external interrupt request flag bit in the interrupt processing routine. • Cancelling stop mode using an interrupt is only possible using the external interrupt circuit. An interrupt request is generated immediately if the external interrupt request flag bit is "1" when the interrupt request enable bit is changed from disabled to enabled ("0" -> "1"). ■ Register and Vector Table for the External Interrupt 1 Circuit Interrupts Table 12.5-1 Register and Vector Table for External Interrupt 1 Circuit Interrupts Interrupt Level Setting Register Vector Table Address Interrupt Register Setting Bits Upper Lower IRQ0 ILR1 (007BH) L01 (bit1) L00 (bit0) FFFAH FFFBH IRQ1 ILR1 (007BH) L11 (bit3) L10 (bit2) FFF8H FFF9H IRQ2 ILR1 (007BH) L21 (bit5) L20 (bit4) FFF6H FFF7H IRQ3 ILR1 (007BH) L31 (bit7) L30 (bit6) FFF4H FFF5H Reference: See "3.4.2 Interrupt Processing" for details on the operation of interrupts. ■ Notes when changing edge polarity selection When changing the edge polarity for INT10 to INT13, always write "0" into the corresponding EIR bits. This will prevent accidentally creating an interrupt. 262 12.6 Operation of the External Interrupt 1 Circuit The external interrupt 1 circuit can detect a specified edge on a signal input to an external interrupt pin. ■ Operation of the External Interrupt 1 Circuit Figure 12.6-1 shows the settings required to operate the external interrupt 1 circuit. Figure 12.6-1 External Interrupt 1 Circuit Settings EIC1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 EIC2 EIR3 SEL7 SEL6 EIE3 EIR2 SEL5 SEL4 EIE2 : Used bit • If the polarity of an edge on the input signal to one of the external interrupt pins (INT10 to INT13) matches the edge polarity specified for the pin in the external interrupt control register (EIC1, EIC2: SEL0 to SEL7), the external interrupt 1 circuit sets the external interrupt request flag bit (EIC1, EIC2: EIR0 to EIR3) to "1". • The external interrupt request flag bit is set when the edge polarity match occurs, regardless of the value of the interrupt request enable bit (EIC1, EIC2 : EIE0 to EIE3). Figure 12.6-2 shows the operation when an external interrupt is input to the INT11 pin. Figure 12.6-2 External interrupt 1 circuit operation (INT11) Input wave form to INT 11 Cleared at the same time as the EIE1 bit is set. Interrupt request flag bit cleared by the program. EIR1 bit EIE1 bit SEL3 bit SEL2 bit IRQ1 Rising edge set Falling edge set Note: The pin state can be read directly from the port data register (PDR1), even when used as an external interrupt input. 263 CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) 12.7 Program Example for the External Interrupt 1 Circuit This section gives a program example for the external interrupt 1 circuit. ■ Program Example for the External Interrupt 1 Circuit ● Processing description Generates interrupts on detecting a rising edge on pulses input to the INT11 pin. ● Coding example EIC1 EQU 0025H ;External interrupt control register 1 EIR1 SEL2 EIE1 EQU EQU EQU EIC1:7 EIC1:5 EIC1:4 ;Defines the external interrupt request flag bit. ;Defines the edge polarity selection bit. ;Defines the interrupt request enable bit. ILR0 EQU 007BH ;Set interrupt level setting register 1. INT_V DSEG ABS ;[DATA SEGMENT] ORG 0FFF8H IRQ1 DW WARI ;Set INT11 interrupt vector. INT_V ENDS ;-----Main program---------------------------------------------------------------------------------------------------------------------------CSEG ;[CODE SEGMENT] ;Stack pointer (SP) etc. are already initialized. : CLRI ;Disable interrupts. CLRB EIR1 ;Clear interrupt request flag. MOV ILR0,#11110111B ;Set interrupt level (level 1). SETB SEL2 ;Select rising edge. SETB EIE1 ;Enable output of interrupt requests. SETI ;Enable interrupts. : ;-----Interrupt processing routine-----------------------------------------------------------------------------------------------------------WARI CLRB EIR1 ;Clear INT11 interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;--------------------------------------------------------------------------------------------------------------------------------------------------END 264 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) This chapter describes the functions and operation of the external interrupt 2 circuit (level). 13.1 Overview of External Interrupt 2 Circuit (Level) 13.2 Block Diagram of External Interrupt 2 Circuit 13.3 Pins of External Interrupt 2 Circuit 13.4 Registers of External Interrupt 2 Circuit 13.5 External Interrupt 2 Circuit Interrupt 13.6 Operation of External Interrupt 2 Circuit 13.7 Program Example for External Interrupt 2 Circuit 265 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) 13.1 Overview of External Interrupt 2 Circuit (Level) The external interrupt circuit 2 detects the level of the signals input to the eight external interrupt pins and generates the interrupt requests to the CPU. ■ External Interrupt 2 Circuit Function (Level Detection) The external interrupt 2 circuit function detects the signals of the "L" levels input to the external interrupt pins and to generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode and change the device to the normal operating state (main-run or sub-run mode). 266 External interrupt pins: 8 pins (P00/INT20 to P07/INT27/BUZ) External interrupt sources: "L" level signal input to an external interrupt pin. Interrupt control: Enables or disables to input external interrupt controlled by external interrupt 2 control register (EIE2) Interrupt flag: IRQ flag bit of external interrupt 2 flag register (EIF2). Flag set when there is an IRQ. Interrupt request: IRQ4 is generated if any enabled external interrupt pin is "L". 13.2 Block Diagram of External Interrupt 2 Circuit The external interrupt circuit 2 consists of the following three blocks: • Interrupt request generator • External interrupt 2 control register (EIE2) • External interrupt 2 flag register (EIF2) ■ Block Diagram of External Interrupt Circuit 2 Figure 13.2-1 Block Diagram of External Interrupt 2 Circuit EIE2 EIF2 IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 IF20 Interrupt request generator P00/INT20 Pin P01/INT21 Pin P02/INT22 Pin P03/INT23 Pin P04/INT24 Pin P05/INT25 Pin P06/INT26 Pin P07/INT27 Pin External interrupt request IRQ4 ● Interrupt request generator The interrupt request generator generates CPU interrupt request signals based on signals input at external interrupt pins (INT20 to INT27) and the external interrupt input enable bits. ● External interrupt 2 control register (EIE2) External interrupt input enable bits (IE20 to IE27) enable or disable "L" level signals input at the corresponding external interrupt pins. ● External interrupt 2 flag register (EIF2) The external interrupt request flag bit of this register (IF20) is used to hold (and clear) interrupt request signals. 267 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) 13.3 Pins of External Interrupt 2 Circuit This section describes the pins, pin block diagram, registers, and external interrupt sources of the external interrupt 2 circuit. ■ Pins of External Interrupt 2 Circuit The external interrupt 2 circuit uses eight external interrupt pins. The external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or as generalpurpose or peripheral I/O pin. When P00/INT20 to P07/INT27/BUZ pins are set as inputs in the port 0 direction register (DDR0), and the corresponding external interrupt inputs are enabled in the external interrupt 2 control register (EIE2), they operate as external interrupt input pins (INT20 to INT27). When they are being used as the input port, the pin states can be read from the port data register (PDR0) at any time. Table 13.3-1 lists the pins of external interrupt 2 circuit. Table 13.3-1 Pins of External Interrupt 2 Circuit 268 External interrupt pin When used as an external interrupt input (Interrupt Input Enabled) When used as General-purpose I/O port or other pheripheral I/O (Interrupt Input Disabled) P00/INT20 INT20 (EIE2:IE20=1) P00 (EIE2:IE20=0) P01/INT21 INT21 (EIE2:IE21=1) P01 (EIE2:IE21=0) P02/INT22 INT22 (EIE2:IE22=1) P02 (EIE2:IE22=0) P03/INT23 INT23 (EIE2:IE23=1) P03 (EIE2:IE23=0) P04/INT24 INT24 (EIE2:IE24=1) P04 (EIE2:IE24=0) P05/INT25/PWC INT25 (EIE2:IE25=1) P05/PWC (EIE2:IE25=0) P06/INT26/PPG INT26 (EIE2:IE26=1) P06/PPG (EIE2:IE26=0) P07/INT27/BUZ INT27 (EIE2:IE27=1) P07/BUZ (EIE2:IE27=0) ■ Block Diagram of External Interrupt 2 Circuit Pins Figure 13.3-1 Block Diagram of External Interrupt 2 Circuit Pins To external interrupt circuit External interrupt input enable Pull-up resistor Approx. 50 kΩ PDR (Port data register) Internal data bus Stop, watch mode PDR read Pull-up resistor control register P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pins DDR DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) N-ch P00/INT20 P01/INT21 P02/ITN22 P03/INT23 P04/INT24 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ Note: Pins with a pull-up resistor go to the "H" level (pull-up state) rather than the high-impedance state when the output transistor is turned "OFF". However, during reset, pull-up is unavailable and will be Hi-Z. 269 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) 13.4 Registers of External Interrupt 2 Circuit This section describes the registers of the external interrupt 2 circuit. Figure 13.4-1 Registers of External Interrupt 2 Circuit EIE2 (External interrupt 2 control register) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0027H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B R/W R/W R/W R/W R/W R/W R/W R/W EIF2 (External interrupt 2 flag register) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0028H — — — — — — — IF20 -------0B R/W R/W : Readable/Writable — : Undefined ■ External Interrupt 2 Circuit Interrupt Sources IRQ4: IRQ4 is generated if any one of external interrupt pins INT20 to INT27 are input "L" level signal with "1" in the external interrupt input enable bit for that pin. 270 13.4.1 External Interrupt 2 Control Register (EIE2) The external interrupt 2 control register (EIE2) is used to enable/disable input of external interrupt pins (INT20 to INT27). ■ External Interrupt 2 Control Register (EIE2) Figure 13.4-2 External Interrupt 2 Control Register (EIE2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0027H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B R/W R/W R/W R/W R/W R/W R/W R/W IE20 to IE27 R/W : Readable/Writable — : Undefined : Initial value External interrupt input enable bits 0 Enables external interrupt input 1 Disables external interrupt input Table 13.4-1 External Interrupt 2 Control Register (EIE2) Bits vs. Pins Bit Pin bit 7 IE27 INT27 bit 6 IE26 INT26 bit 5 IE25 INT25 bit 4 IE24 INT24 bit 3 IE23 INT23 bit 2 IE22 INT22 bit 1 IE21 INT21 bit 0 IE20 INT20 271 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) Table 13.4-2 Functions of Bits in External Interrupt 2 Control Register (EIE2) Bit name bit7 to bit0 272 IE27 to IE20: External interrupt enable bits Function • These bits enable/disable input of external interrupts at external interrupt pins INT20 to INT27. • Setting these bits to "1" puts the corresponding pin into its external interrupt input mode, and enables input of external interrupts at the pin. • Conversely, "0" in the bit allows the pin to function in its general-purpose port mode and inhibits input of interrupts at the pin. Notes: • When using a pin for external interrupts, set it as an input by writing its bit in the port 0 data direction register (DDR0) to "0". • The state of the pin can always be read directly out of the port 0 data register (PDR0) regardless of the sate of this external interrupt input enable bit. 13.4.2 External Interrupt 2 Flag Register (EIF2) External Interrupt 2 flag register (EIF2) is used to hold the IRQ state when a level interrupt has been detected, and clear the interrupt request flag. ■ External Interrupt 2 Flag Register (EIF2) Figure 13.4-3 External Interrupt 2 Flag Register (EIF2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0028H — — — — — — — IF20 --------0B R/W IF20 0 R/W — : Readable/Writable : Undefined : Initial value 1 External interrupt request flag bit Read Write No external IRQ ("L" level not detected). Clears this bit. Have external IRQ ("L" level detected). No effect. This bit does not change. Table 13.4-3 Functions of Bits in External Interrupt 2 Flag Register (EIF2) Bit name bit7 to bit1 bit0 Function Undefined bits • The read value is undefined. • Writing to these bits has no effect on the operation. IF20: External interrupt request flag bit • This bit is set to "1" when a "L" is detected at an enabled external interrupt pin (INT20 to INT27). • Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. Note: Writing "0" to the external interrupt input enable bits of the external interrupt 2 control register (EIE2: IE20 to IE27) simply disables the corresponding external interrupt input; it does not clear the interrupt request. IRQ4 will continue to be sent to the CPU until it is cleared by writing "0" to the IF20 bit. 273 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) 13.5 External Interrupt 2 Circuit Interrupt The external interrupt 2 circuit interrupt trigger event is the detection of a "L" level at the external interrupt pin. ■ Interrupts for External Interrupt 2 Circuit Operation • If a "L" level is detected at an enabled external interrupt pin, the external interrupt request flag bit (EIF2: IF20) is set to "1", and an interrupt request (IRQ4) to the CPU is generated. Write "0" to the IF20 bit in the interrupt processing routine to clear the interrupt request. • Once the external interrupt request flag bit (IF20) is set to "1", IRQ4 continues to be asserted as long as the flag set. Disabling the interrupt input by writing the IE bit (IE20 to IE27) of the EIE2 register to "0" will not clear the interrupt request. Always clear the IF20 bit. • Also, if the external interrupt pin stays "L" level, writing "0" to the IF20 bit without disabling the external interrupt input will not clear the interrupt either, because IF20 will immediately be set again by the "L" pin. After an interrupt request is generated, then, either the input must be disabled, or the external IRQ signal de-asserted. Notes: • When enabling interrupts of CPU after wake-up from a reset, clear the IF20 bit in advance. • Wake-up from stop mode by an interrupt is possible using only the external interrupt circuit 1 and 2. ■ Register and Vector Table for External Interrupt 2 Circuit Interrupts Table 13.5-1 Registers and Vector Table for External Interrupt 2 Circuit Interrupts Interrupt level setting register Vector table address Interrupt Register IRQ4 ILR2 (007CH) Setting bits L41 (bit1) L40 (bit0) Reference: See "3.4.2 Interrupt Processing" for details on the interrupts operation. 274 Upper Lower FFF2H FFF3H 13.6 Operation of External Interrupt 2 Circuit The external interrupt 2 circuit issues an interrupt request to the CPU when it detects a "L" level at one of its external interrupt pins. ■ Operation of External Interrupt 2 Circuit Figure 13.6-1 shows the settings required to operate the external interrupt 2 circuit. Figure 13.6-1 External Interrupt 2 Circuit Settings bit6 bit5 bit4 bit3 bit2 bit1 bit0 EIE2 IE27 bit7 IE26 IE25 IE24 IE23 IE22 IE21 IE20 EIF2 — — — — — — — IF20 DDR0 — — — — — — — — * * * * * * * * ∗ : Used bit : Set bits for pins used for external interrupts to "0" If a "L" level signal is applied to one of the INT20 to INT27 pins with the corresponding external interrupt input enable bit (IE20 to IE27) in the "enable" state, the circuit sends an IRQ4 interrupt request to the CPU. Figure 13.6-2 shows external interrupt 2 circuit operation (for a signal received at INT20). Figure 13.6-2 Operation of External Interrupt 2 (INT20) Input waveform to the INT20 pin ("L" level detected) External interrupt input enabled EIE2: IE20 Cleared by the interrupt processing routine. EIF2: IF20 (Same as IRQ4) Interrupt processing IRQ4 interrupt processing routine operation RETI Can be read at any time. Interrupt processing RETI PDR0: bit0 Note: The pin state can be read directly from the port data register (PDR0) even when the pin is being used as an external interrupt input. 275 CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) 13.7 Program Example for External Interrupt 2 Circuit This section gives a program example for the external interrupt 2 circuit. ■ Program Example for External Interrupt 2 Circuit ● Processing description Generates interrupts on detecting a "L" level input the INT20 pin. ● Coding example DDR0 EIE2 EIF2 EQU EQU EQU 0001H 0027H 0028H ; Address of port 0 data direction register ; Address of external interrupt 2 control register ; Address of external interrupt 2 flag register IF20 EQU EIF2:0 ; Define the external interrupt request flag bit. ILR2 EQU 007CH ; Address of the set interrupt level setting register 2 INT_V ORG IRQ4 INT_V DSEG 0FFF2H DW ENDS ABS ; [DATA SEGMENT] WARI CSEG ; Set interrupt vector. ; ;------------------------------------------------------------------------------------------------------------------------------------Main program CSEG : CLRI CLRB MOV MOV MOV SETI IF20 ILR2,#11111110B DDR0,#00000000B EIE2,#00000001B ; [CODE SEGMENT] ;Stack pointer (SP) etc. are already initialized. ; Disable interrupts. ; Clear external interrupt request flag. ; Set interrupt priority (level 2). ; Set P00/INT20 pin as input. ; Enable external interrupt input at INT20 pin. ; Enable interrupts. ;-----------------------------------------------------------------------------------------------------------------------------------Interrupt processing routine WARI MOV EIE2,#00000000B CLRB IF20 PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ; Disable external interrupt input at INT20 pin. ; Clear external interrupt request flag. ;-----------------------------------------------------------------------------------------------------------------------------------END 276 CHAPTER 14 A/D CONVERTER This chapter describes the functions and operation of the A/D converter. 14.1 Overview of A/D Converter 14.2 Block Diagram of A/D Converter 14.3 Pins of A/D Converter 14.4 Registers of A/D Converter 14.5 A/D Converter Interrupt 14.6 Operation of A/D Converter 14.7 Notes on Using A/D Converter 14.8 Program Example for A/D Converter 277 CHAPTER 14 A/D CONVERTER 14.1 Overview of A/D Converter The A/D converter can function as an 10-bit successive approximation type A/D converter. The function selects one input signal from the four channels of analog input pin and can be activated either by software, by an internal clock, or by 8/16-bit timer 21 output. ■ A/D Conversion Function The A/D conversion function converts the analog voltage (input voltage) input to an analog input pin to an 10-bit digital value. • Selects one input from four analog input pins. • Conversion speed is 60 instruction cycles (19.2 µs for a 12.5 MHz main clock source oscillation). • Generates an interrupt when A/D conversion completes. • Conversion completion can also be determined by software. The following methods are available to activate A/D conversion: • Activation by software • Continuous activation by a time-base timer output (divide-by-28 main clock source oscillation) • Continuous activation by 8/16-bit timer 21 output. 278 14.2 Block Diagram of A/D Converter The A/D converter consists of the following nine blocks: • Clock selector (input clock selector for A/D converter activation) • Analog channel selector • Sample hold circuit • D/A converter • Comparator • Controller • A/D data register (ADDL and ADDH) • A/D control register 1 (ADC1) • A/D control register 2 (ADC2) ■ Block Diagram of A/D Converter Figure 14.2-1 Block Diagram of A/D Converter ADC2 — 28/FCH (Time-base timer output) P17/SEG30/AN3 P16/SEG29/AN2 P15/SEG28/AN1 P14/SEG27/AN0 RESV RESV ADCK ADIE ADMD EXT RESV Clock selector Analog channel selector Internal data bus 8/16-bit timer 21 output Comparator Sample hold circuit Controller ADDL and ADDH AVCC AVSS D/A converter — ANS2 ANS1 ANS0 ADI ADMV — AD ADC1 IRQ8 FCH: Main clock source oscillation ● Clock selector Selects the clock used to activate the A/D conversion when continuous activation is enabled (ADC2: EXT = 1). 279 CHAPTER 14 A/D CONVERTER ● Analog channel selector Selects one of the four analog input pins. ● Sample hold circuit Holds the input voltage selected by the analog channel selector. The circuit samples and holds the input voltage immediately after the A/D conversion is activated. This allows A/D conversion to proceed without being affected by input voltage fluctuation. ● D/A converter Generates the voltage corresponding to the value set in the ADDL and ADDH register. ● Comparator Compares the sampled and held input voltage with the output voltage of the D/A converter, and determines which voltage is higher or lower. ● Controller For the A/D conversion function, the controller successively determines the value of each bit of the ADDL and ADDH register, starting from the most significant bit and proceeding to the least significant bit, based on the greater-than/less-than signal from the comparator. When conversion is complete, the circuit sets the interrupt request flag bit (ADC1: ADI). ● A/D data register (ADDL and ADDH) Stores the A/D conversion result for the A/D conversion function. ● A/D control register 1 (ADC1) The ADC1 register is used to enable or disable each function, select the analog input pin, check status, and control interrupts. ● A/D control register 2 (ADC2) The ADC2 register is used to select the input clock, enable or disable interrupts, and select functions. ■ A/D Converter Power Supply Voltage ● AVCC The A/D converter power supply pin. Use at the same voltage as VCC. When high A/D conversion resolution is required, take measures to ensure that the noise on VCC is not present on AVCC, or use a separate power supply. Connect this pin to the power supply, even if the A/D converter is not used. ● AVSS The A/D converter ground pin. Use at the same voltage as VSS. When high A/D conversion accuracy is required, take measures to ensure that the noise on VSS is not present on AVSS. Connect this pin to ground (GND), even if the A/D converter is not used. 280 14.3 Pins of A/D Converter This section describes the pins, pin block diagrams, registers, and an interrupt source for the A/D converter. ■ Pins of A/D Converter The A/D converter function uses the P14/AN0 to P17/AN3 pins. These pins can function as generalpurpose I/O port (P14 to P17), or the analog input pins (AN0 to AN3). ● AN0 to AN3: • The analog voltages to be converted (A/D conversion function) are applied to these pins. • To select the analog input function for one of these pins, you set the corresponding bit of the port direction register (DDR1) to "1", to turn off the output transistor, then set the corresponding bit of the A/D input enable register (ADER) to "1", and set the analog input channel select bits (ADC1: ANS0 to ANS2) to select the pin as the analog input channel. Pins that are not needed for analog inputs can still be used as general-purpose I/O port pins, even while the A/D converter is being used. ■ Block Diagram of A/D Converter Pin Figure 14.3-1 Block Diagram of P40/AN0 to P47/AN7 Pins A/D converter channel selector A/D converter analog input PDR (Port data register) Internal data bus PDR read N-ch A/D input enable Stop, watch mode LCD output enable PDR read (for bit manipulation instructions) Output latch PDR write Pins DDR DDR write (Port direction register) N-ch P14/SEG27/AN0 P15/SEG28/AN1 P16/SEG29/AN2 P17/SEG30/AN3 Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 281 CHAPTER 14 A/D CONVERTER 14.4 Registers of A/D Converter This section describes the registers of the A/D converter. Figure 14.4-1 Registers of A/D Converter ADC1 (A/D control register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002CH — ANS2 ANS1 ANS0 ADI ADMV RESV AD -0000000B R/W R/W R/W R/W R R/W R/W ADC2 (A/D control register 2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002DH — RESV RESV ADCK ADIE ADMD EXT RESV -0000001B R/W R/W R/W R/W R/W R/W R/W ADDH (A/D data register H) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002EH — — — — — — D9 D8 ------XXB R R ADDL (A/D data register L) R/W R — X Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002FH D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R R R R R R R R : Readable/Writable : Read only : Undefined : Undefined value ■ A/D Converter Interrupt Source IRQ8: The A/D converter generates an interrupt request if an interrupt request output is enabled (ADC2: ADIE = 1) when A/D conversion completes. 282 14.4.1 A/D Control Register 1 (ADC1) A/D control register 1 (ADC1) is used to enable or disable the functions, select the analog input pin, and check the status of the A/D converter. ■ A/D Control Register 1 (ADC1) Figure 14.4-2 A/D Control Register 1 (ADC1) Address bit7 002CH bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ANS2 ANS1 ANS0 ADI ADMV RESV AD -0000000B R/W R/W R/W R/W R R/W R/W A/D converter activation bit AD Only applies when software activation is specified (ADC2: EXT = 0). 0 Does not activate the A/D conversion 1 Activates the A/D conversion Reserved bit RESV Always write "0" to this bit ADMV Conversion-in-progress flag bit 0 Conversion not currently in progress 1 Conversion currently in progress Interrupt request flag bit ADI Read Write 0 Conversion not complete. Clears this bit. 1 Conversion completes. No effect. The bit does not change. ANS2 ANS1 ANS0 Analog input channel selection bits 0 0 0 P14/AN0 pin 0 0 1 P15/AN1 pin 0 1 0 P16/AN2 pin 0 1 1 P17/AN3 pin 1 0 0 Prohibited 1 0 1 Prohibited 1 1 0 Prohibited 1 1 1 Prohibited R/W : Readable/Writable R : Read only — : Undefined : Undefined value 283 CHAPTER 14 A/D CONVERTER Table 14.4-1 Functions of Bits in A/D Control Register 1 (ADC1) Bit name bit7 bit6 to bit4 Undefined bit ANS2, AN1, ANS0: Analog input channel selection bits Function • The read value is undefined. • Writing to this bit has no effect on the operation. • These bits select which of the AN0 to AN3 pins to use as the analog input pin. • When using software activation (ADC2: EXT = 0), these bits can be modified at the same time as activating the A/D conversion (AD = 1). Notes: • Disable general-purpose port output corresponding to the analog input pin, and set it as analog input pin by ADER. Do not modify these bits when the ADMV bit is set to "1". • Pins not used as analog inputs can be used as general-purpose ports. bit3 ADI: Interrupt request flag bit • This bit is set to "1" when the A/D conversion is completed. • An interrupt request is output when both this bit and the interrupt request enable bit (ADC2: ADIE) are "1". • Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value. bit2 ADMV: Conversion-inprogress flag bit • This bit indicates whether or not the A/D converter is currently performing a conversion. • The bit is set to "1" when a conversion is in progress. Note: This bit is read-only. The write value has no meaning and has no effect on the operation. bit1 RESV: Reserved bit Note: Always write "0" to this bit. AD: A/D converter activation bit • This bit activates the A/D conversion by software. • Writing "1" to this bit activates the A/D conversion when continuous activation is not specified (ADC2: EXT = 0). Notes: • Writing "0" to this bit does not stop the A/D conversion. The read value is always "0". • This bit has no meaning when continuous activation is specified. bit0 284 14.4.2 A/D Control Register 2 (ADC2) A/D control register 2 (ADC2) is used to select the A/D converter functions, select the input clock, enable or disable interrupts and continuous activation, and check the status of the A/D converter. ■ A/D Control Register 2 (ADC2) Figure 14.4-3 A/D Control Register 2 (ADC2) Address bit7 bit6 Bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002DH — RESV RESV ADCK ADIE ADMD EXT RESV -0000001B R/W R/W R/W R/W R/W R/W R/W RESV Reserved bit Always write "1" to this bit. EXT Continuous activation enable bit 0 Activates by the AD bit in the ADC1 register. 1 Activates continuously by the clock selected in the ADCK bit. ADMD Function selection bit 0 A/D conversion function 1 Prohibited ADIE Interrupt request enable bit 0 Disables interrupt request output. 1 Enables interrupt request output. Input clock selection bit ADCK Only applies when continuous activation is enabled (EXT = 1). 0 Time-base timer output (divide-by-28 main clock source oscillation) 1 8/16-bit timer 21 output RESV R/W : Readable/Writable — : Undefined : Initial value Reserved bits Always write "0" to these bits. 285 CHAPTER 14 A/D CONVERTER Table 14.4-2 Functions of Bits in A/D Control Register 2 (ADC2) Bit name Function bit7 Undefined bit • The read value is undefined. • Writing to this bit has no effect on the operation. bit6, bit5 Reserved bits Note: Always write "0" to these bits. bit4 ADCK: Input clock selection bit This bit selects the input clock used to activate the A/D conversion when continuous activation is specified (EXT = 1). Setting this bit to "0" selects the time-base timer output (divide-by-28 main clock source oscillation). Setting this bit to "1" selects output of 8/16-bit timer 21. bit3 ADIE: Interrupt request enable bit • This bit enables or disables an interrupt request output to the CPU. • An interrupt request is output when both this bit and the interrupt request flag bit (ADC1: ADI) are "1". bit2 ADMD: Function selection bit Note: Always write "0" to this bit. bit1 EXT: Continuous activation enable bit This bit selects whether to activate the A/D conversion by software or to operate continuously synchronized with an input clock. Setting this bit to "0": enables software activation by the A/D converter activation bit (ADC1: AD). Setting this bit to "1": enables continuous activation on the rising edge of the clock selected in the input clock selection bit (ADC2: ADCK). bit0 RESV: Reserved bit Notes: • Always write "1" to this bit. • The read value is always "1". 286 14.4.3 A/D Data Registers (ADDL and ADDH) These registers stores in the 10 bits A/D conversion result for the A/D conversion function. (lower 8-bits in ADDL and upper 2-bits in ADDH) ■ A/D Data Registers (ADDL and ADDH) Figure 14.4-4 shows the bit structure of the A/D data registers (ADDL and ADDH). Figure 14.4-4 A/D Data Registers (ADDL and ADDH) ADDH Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002EH — — — — — — D9 D8 ------XXB R R ADDL Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 002FH D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R R R R R R R R R : Read only — : Undefined X : Undefined value ● For A/D conversion function The conversion result is decided approximately 60 instruction cycles after A/D conversion is activated. The data of conversion is stored in these registers. The values of these registers are undefined while A/D conversion is in progress. These registers are read-only for the A/D conversion function. 287 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Interrupt The A/D converter has the following interrupt: Conversion completion for the A/D conversion function ■ Interrupt for A/D Conversion Function • When A/D conversion completes, the interrupt request flag bit (ADC1: ADI) is set to "1". At this time, an interrupt request (IRQ8) to the CPU is generated if the interrupt request enable bit is enabled (ADC2: ADIE = 1). Write "0" to the ADI bit in the interrupt processing routine to clear the interrupt request. • The ADI bit is set after completion of A/D conversion, regardless of the ADIE bit value. Note: An interrupt request is generated immediately if the ADI bit is "1" when the ADIE bit is changed from disabled to enabled ("0" -> "1"). ■ Register and Vector Table for A/D Converter Interrupt Table 14.5-1 Register and Vector Table for A/D Converter Interrupt Interrupt level settings register Vector table address Interrupt Register IRQ8 ILR3 (007DH) Setting bits L81 (bit1) L80 (bit0) Upper Lower FFEAH FFEBH Reference: See "3.4.2 Interrupt Processing" for details on the operation of interrupt. 288 14.6 Operation of A/D Converter The A/D conversion functions of the A/D converter can be activated by software or can be activated continuously. ■ Activating A/D Conversion Function ● Software activation Figure 14.6-1 shows the settings required for software activation of the A/D conversion function. Figure 14.6-1 A/D Conversion Function (Software Activation) Settings ADC1 ADC2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — ANS2 ANS1 ANS0 ADI ADMV RESV AD 0 1 ADMD EXT RESV 0 0 1 — RESV RESV ADCK 0 0 × ADIE ADDL Stores the A/D conversion result. ADDH Stores the A/D conversion result. : Used bit × : Unused bit 1 : Set "1". 0 : Set "0". On activation, the A/D converter starts the operation of the A/D conversion function. The A/D conversion function can be reactivated while conversion is in progress. ● Continuous activation Figure 14.6-2 shows the settings required for continuous activation of the A/D conversion function. Figure 14.6-2 A/D Conversion Function (Continuous Activation) Settings ADC1 ADC2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — ANS2 ANS1 ANS0 ADI ADMV RESV AD 0 × ADMD EXT RESV 0 1 1 — RESV RESV 0 0 ADCK ADIE ADDL Stores the A/D conversion value. ADCH Stores the A/D conversion value. : Used bit × : Unused bit 1 : Set "1". 0 : Set "0". When continuous activation is enabled, the rising edge of the selected input clock activates the A/D conversion, starting operation of the A/D conversion function. When continuous activation is disabled (ADC2: EXT = 0), continuous activation halts but software activation is available. 289 CHAPTER 14 A/D CONVERTER ■ Operation of A/D Conversion Function The following describes the operation of the A/D converter. The A/D conversion requires approximately 60 instruction cycles from activation to completion. (1) On activation, A/D conversion sets the conversion-in-progress flag bit (ADC1: ADMV = 1) and connects the sample hold circuit to the specified analog input pin. (2) The internal sample hold capacitor captures the voltage at the analog input pin for approximately 16 instruction cycles. The capacitor holds the voltage until the A/D conversion completes. (3) The comparator compares the voltage captured by the sample hold capacitor with the A/D converter reference voltage starting from the most significant bit (MSB) and ending with the least significant bit (LSB), and transfers each bit sequentially to the ADDL and ADDH register. (4) When the complete result has been transferred to the ADDL and ADDH register, the conversion-inprogress flag bit is cleared (ADC1: ADMV = 0) and the interrupt request flag bit is set (ADC1: ADI = 1). 290 14.7 Notes on Using A/D Converter This section lists points to note when using the A/D converter. ■ Notes on Using A/D Converter ● Input impedance of analog input pins The A/D converter contains a sample hold circuit as shown in Figure 14.7-1 to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1µF for the analog input pin. Figure 14.7-1 Analog Input Equivalent Circuit Sample hold circuit Analog input pin If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. Comparator R C Close for 16 instruction cycles after activating A/D conversion. Analog channel selector ● Notes on setting by program • For the A/D conversion function, the ADDL and ADDH registers maintain previous values until the next A/D conversion is activated. However, the content of the ADDL and ADDH registers becomes indeterminate immediately after activating A/D conversion. • Do not re-select the analog input channel (ADC1: ANS2 to ANS0) while the A/D conversion is operating. Particularly, when continuous activation is enabled, only perform such operations after disabling continuous activation (ADC2: EXT = 0) and waiting for the conversion-in-progress flag bit (ADC1: ADMV) to go to "0". • A reset or activation of stop mode stops the A/D converter and initializes all registers. • Interrupt processing cannot return if the interrupt request flag bit (ADC1: ADI) is "1" and the interrupt request enable bit is enabled (ADC2: ADIE = 1). Always clear the ADI bit. ● Note on interrupt requests The interrupt request flag bit (ADC1: ADI) is not set if A/D conversion is reactivated (ADC1: AD = 1) at the same time as the previous A/D conversion completes. 291 CHAPTER 14 A/D CONVERTER ● Turn-on sequence for A/D converter power supply and analog inputs • Always apply the A/D converter power supply (AVCC, AVSS) and analog inputs (AN0 to AN3) at the same time or after turning on the digital power supply (VCC). • Similarly, when power supply is turned off, always turn off the A/D converter power supply (AVCC, AVSS) and analog inputs (AN0 to AN3) at the same time or before turning off the digital power supply (VCC). • Take care that AVCC, AVSS, and the analog inputs do not exceed the digital power supply voltage when turning the A/D converter power supply on or off. ● Conversion time A/D conversion function conversion time is affected by oscillator frequency, and main clock speed switching (speed shift function). ● Continuous activation input clock The time-base timer output, which can be selected as input clock, is not affected by the speed shift function. Note also that the cycle time is affected (for one cycle) when the time-base timer is cleared. 292 14.8 Program Example for A/D Converter This section gives program examples for the A/D conversion function of the10-bit A/D converter. ■ Program Example for A/D Conversion Function ● Processing description Performs software-activated A/D conversion of the analog voltage input to the AN0 pin. The example does not use interrupts and detects conversion completion within the program loop. ● Coding example DDR1 ADC1 ADC2 ADDL ADDH ADER AN0 ADI ADMV AD EXT EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0003H 002CH 002DH 002FH 002EH 0030H DDR1:4 ADC1:3 ADC1:2 ADC1:0 ADC2:1 ; Port 1 direction ; A/D control register 1 ; A/D control register 2 ; A/D data register L ; A/D data register H : A/D input enable register ; Define the AN0 analog input pin. ; Define the interrupt request flag bit. ; Define the conversion-in-progress flag bit. ; Define A/D converter activation bit (software activation) ; Define the continuous activation enable bit. ;-----Main program-------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB AN0 ; Set P14/AN0 pin as an analog input pin (AN0). SETB ADER:0 CLRI ; Disable interrupts. CLRB EXT ; Disable continuous activation. AD_WAIT BBS ADMV,AD_WAIT ; Loop to check that the A/D converter is stopped. MOV ADC1,#00000000B ; Select analog input channel 0 (AN0), clear interrupt request flag, and do not activate software. MOV ADC2,#00000001B ; Disable interrupt request output, select the A/D conversion function, and select software activation by the AD bit SETI ; Enable interrupts. : SETB AD ; Activate by software AD_CONV BBS ADMV,AD_CONV ; Loop to delay until A/D conversion completes (approx. 30 µs at 12.5 MHz). CLRB ADI ; Clear interrupt request flag. MOV A,ADDL ; Read A/D conversion data.(Lower 8 bits) 293 CHAPTER 14 A/D CONVERTER MOV A,ADDH ; Read A/D conversion data (upper 2 bits) : : ENDS ;------------------------------------------------------------------------------------------------------------------------------END 294 CHAPTER 15 UART/SIO This chapter describes the functions and operation of the UART/SIO. 15.1 Overview of UART/SIO 15.2 Block Diagram of UART/SIO 15.3 Pins of UART/SIO 15.4 Registers of UART/SIO 15.5 UART/SIO Interrupts 15.6 Operation of UART/SIO 15.7 Operation of mode 0 15.8 Operation of mode 1 295 CHAPTER 15 UART/SIO 15.1 Overview of UART/SIO The UART/SIO is a general-purpose serial data communication interface. The UART/SIO supports both synchronous and asynchronous mode operation and transmits variablelength serial data. The transfer format is the "NRZ" system and the transfer data rate is configured by setting the dedicated baud rate generator, external clocks, or internal timers. ■ Function of UART/SIO The UART/SIO communicates with other CPUs and peripheral devices by sending/receiving serial data (serial input/output). • The full-duplex double buffer embedded in the device enables full-duplex bi-directional communication. • Users can configure the UART/SIO to the synchronous transfer mode or asynchronous transfer mode. • Internal baud rate generator allows users to select a baud rate from 14 different speeds. The baud rate is also configured by setting external clock inputs. • The variable data length system allows users to set the data length at 7 to 8-bit non-parity or 8 to 9-bit parity mode (See Table 15.1-1). • The data transfer format is based on the NRZ (Non Return to Zero) system. Table 15.1-1 UART/SIO Operating Mode Data Length Operating Mode Non-parity Parity 7 bits 8 bits 8 bits 9 bits 0 1 296 8 bits Transfer Mode Stop Bit Length Asynchronous 1 bit or 2 bits Synchronous — 15.2 Block Diagram of UART/SIO The UART/SIO consists of the following six blocks: • Serial mode control register 1 (SMC1) • Serial mode control register 2 (SMC2) • Serial status and data register (SSD) • Serial rate control register (SRC) • Serial input data register (SIDR) • Serial output data register (SODR) ■ Block Diagram of UART/SIO Figure 15.2-1 Block Diagram of UART/SIO Internal data bus Baud rate generator Registers: Serial Rate Control Register (SRC) Reload SMC1 MD PEN TDP SBL CL CLK2 CLK1 CLK0 SMC2 RERC RXE TXE BRGE TXOE SCKE RIE TIE PER OVE FER RDRF TDRE — — — SSD SODR CLK2 to CLK0 SIDR 8-bit counter 1/2 MD=0 Divide by 8 0.8µs 0.5µs (at 12.5 MHz) 3.2µs BRGE MD Selector 12.8µs PER P21/SCK MD=1 Receiving status decision circuit Start bit detect Receiving counter FER RDRF RIE Parity generator Receiving data register TDRE TIE PEN RXE P23/SI Shift Register CL SBL MD Send start circuit OVF Send counter IRQ5 SCKE P21/SCK TXOE P22/SO Shift Register Parity generator TXE TDRE Transmission data register TDP, PEN 297 CHAPTER 15 UART/SIO ● Serial Mode Control Registers (SMC1 and SMC2) These registers control operating modes in the UART/SIO. The register sets transfer mode (synchronous/ asynchronous), parity/non-parity, stop bit length, operating mode (data length), transmission data rate, enable/disable of UART/SIO operation, enable/disable of serial clock output, enable/disable of serial output and enable/disable of interrupt request to CPU. ● Serial Rate Control Register (SRC) This register controls the data transmission rate (baud rate). The register selects transfer rate generated by baud rate generator. ● Serial Status and Data Register (SSD) This register shows UART/SIO sending/receiving, error status, as well as receives parity. ● Serial Input Data Register (SIDR) This register holds received data. Serial data received is converted and stored in the register. When the data length is set to 7 bits, bit7 does not have meaning. ● Serial Output Data Register (SODR) This register sets sending data. The data written in this register is converted to the serial data and output. When the data length is set to 7 bits, bit7 does not have meaning. 298 15.3 Pins of UART/SIO This section describes the pins and pin block diagram of UART/SIO. ■ Pin of UART/SIO The pins for the UART/SIO function are shift clock input/output pin (P21/SCK), serial data output pin (P22/SO) and serial data input pin (P23/SI). ● P21/SCK : • This pin function either as a general purpose input/output port (P21) or a clock input/output pin (hysteresis input) for the UART/SIO(SCK). When clock output is enabled (SMC2: SCKE=1), this pin function as clock output pin (SCK) irrespective of settings on corresponding port direction register. In this case, do not select an external clock (SMC1: CLK2, CLK1, CLK0 do not select 100B). • To use the port as a UART/SIO clock input pin, disable the clock output (SMC2: SCKE = 0) and configure the port as an input port by setting a corresponding port direction register bit (DDR2: bit1 = 0). In this case, be sure to select an external clock (SMC1: CLK2, CLK1, CLK0 = 100B). ● P22/SO : This pin function either as general-purpose input/output port (P22) or serial data output pin of the UART/SIO (SO). When serial data output is enabled (SMC2: TXOE=1), this pin function as serial data output pin of the UART/SIO irrespective of settings on corresponding port direction register. ● P23/SI : This pin function either as general-purpose input/output port (P23) or serial data input pin (hysteresis input) of the UART/SIO (SI). To use the port as a UART/SIO serial data input pin, configure the port as input port by setting a corresponding bit of the port direction register (DDR2: bit3 = 0). 299 CHAPTER 15 UART/SIO ■ Block Diagram of UART/SIO Pin Figure 15.3-1 Block Diagram of UART/SIO Pin SCK, SI To UART/SIO PDR (Port data register) Internal data bus PDR read Stop, watch mode UART/SIO output Pull-up resistor Approx. 50kΩ Pull-up resistor control register Output enable P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pins DDR (Port data DDR write direction register) DDR read N-ch P21/SCK P22/SO P23/SI Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Note: When pull-up resistor is selected in pull-up resistor control register, the states of these pins in stop and watch mode (SPL=1) are in "H" level (pull-up state) rather than high impedance. However, during reset, pull-up is unavailable and will be in high impedance state. 300 15.4 Registers of UART/SIO This section describes the registers of the UART/SIO. ■ Registers of UART/SIO Figure 15.4-1 Registers of UART/SIO SMC1 (Serial mode control register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0020H MD PEN TDP SBL CL CLK2 CLK1 CLK0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W SMC2 (Serial mode control register 2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0021H RERC RXE TXE BRGE TXOE SCKE RIE TIE 00000000B W R/W R/W W R/W R/W R/W R/W bit4 bit3 bit2 bit1 bit0 SRC (Serial rate control register) Address bit7 bit6 bit5 Initial value XXXXXXXXB 0022H R/W R/W R/W R/W R/W R/W R/W R/W SSD (Serial status and data register) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0023H PER OVE FER RDRF TDRE — — — 00001---B R R R R R bit5 bit4 bit3 bit2 bit1 bit0 SIDR (Serial input data register) Address bit7 bit6 0024H Initial value XXXXXXXXB R R R R R R R R bit4 bit3 bit2 bit1 bit0 SODR (Serial output data register) Address bit7 bit6 bit5 0024H XXXXXXXXB W R/W R W — X Initial value W W W W W W W : Readable/Writable : Read only : Write only : Undefined : Undefined value 301 CHAPTER 15 UART/SIO 15.4.1 Serial Mode Control Register 1 (SMC1) Serial mode control register 1 (SMC1) sets transfer mode (synchronous/asynchronous), stop bit length, data length, parity/non-parity and selects the serial clock. ■ Serial Mode Control Register 1 (SMC1) Figure 15.4-2 Serial Mode Control Register 1 (SMC1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0020H MD PEN TDP SBL CL CLK2 CLK1 CLK0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W CLK2 0 0 0 0 1 R/W : Readable/Writable : Initial value 302 CLK1 0 0 1 1 0 CLK0 0 1 0 1 0 Clock selection bits 2 instruction cycles 8 instruction cycles 32 instruction cycles Dedicated baud rate generator External clock CL 0 1 Character bit length control bit 7-bit data length 8-bit data length SBL 0 1 Stop bit length control bit 1-bit length 2-bit length TDP 0 1 Parity polarity bit Even parity Odd parity PEN 0 1 Parity control bit Non-parity Parity (odd/even selected by TDP bit) MD 0 1 Mode control bit Asynchronous mode (UART) Synchronous mode (SIO) Table 15.4-1 Functions of Bits in Serial Mode Control Register 1 (SMC1) Bit name Function bit7 MD: Mode control bit This bit selects the UART/SIO operating mode. In asynchronous mode, the UART/SIO operates on the serial clock divided by 8. In synchronous mode, it operates on the selected serial clock. bit6 PEN: Parity control bit In asynchronous mode operation, this bit sets whether there is parity data or not. bit5 TDP: Parity polarity bit In asynchronous mode operation, this bit decides which sort of parity data during serial transmission. During serial receiving, it checks parity data. bit4 SBL: Stop bit length control bit This bit determines the stop bit length in clock asynchronous mode operation. • In serial transmissions, a stop bit of the bit length specified is appended. • In serial receiving, a stop bit is recognized as in a 1-bit length regardless of the value set here. bit3 CL: Character bit length control bit This bit sets the character bit length in asynchronous mode operation. bit2 to bit0 CLK2, CLK1, CLK0: Clock selection bits These bits select the serial clock. 303 CHAPTER 15 UART/SIO 15.4.2 Serial Mode Control Register 2 (SMC2) Serial mode control register 2 (SMC2) sets the serial data output enable to pins, clock output enable to pins, transmission/receiving interrupt enable and baud rate generator start bit. ■ Serial Mode Control Register 2 (SMC2) Figure 15.4-3 Serial Mode Control Register 2 (SMC2) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0021H RERC RXE TXE BRGE TXOE SCKE RIE TIE 00000000B W R/W R/W W R/W R/W R/W R/W TIE 0 1 Transmission interrupt enable bit Disable transmission interrupt Enable transmission interrupt RIE 0 1 Receiving interrupt enable bit Disable receiving interrupt Enable receiving interrupt SCKE 1 Serial Clock output enable bit P21/SCK functions as a general purpose I/O port or shift clock input P21/SCK functions as shift clock output TXOE 0 1 Serial data output enable bit P22/SO functions as a general purpose I/O port P22/SO functions as serial data output BRGE 0 1 Baud rate generator start bit Stops the baud rate generator Starts the baud rate generator TXE 0 1 Transmission operation enable bit Disables transmission operations Enables transmission operations RXE 0 1 Receiving operation enable bit Disables receiving operations Enables receiving operations RERC 0 1 Receiving every flag clear bit Clears all error flags No change to this bit, no effect on the other bits 0 R/W : Readable/Writable W : Write only : Initial value 304 Table 15.4-2 Functions of Bits in Serial Mode Control Register 2 (SMC2) Bit name Function bit7 RERC: Receiving error flag clear bit Writing "0" to this bit clears all error flags (PER, OVE and FER) in the SSD register. This bit is always "1" when read. bit6 RXE: Receiving operation enable bit This bit enables reception of serial data. The receiving operation is stopped by writing "0" to this bit after receiving the current serial data, and disabled thereafter. bit5 TXE : Transmission operation enable bit This bit enables transmission of serial data. The transmission operation is stopped by writing "0" to this bit after transmitting the current serial data, then disabled thereafter. bit4 BRGE: Baud rate generator start bit This bit starts the baud rate generator bit3 TXOE: Serial data output enable bit The P22/SO pin functions as a general-purpose port (P22) when this bit is set to "0" and as the serial data output pin (SO) when set to "1". The pin functions as the (SO) pin when serial data output is enabled (TXOE = 1), regardless of the state of the general-purpose port P22. bit2 SCKE: Serial clock output enable bit • This bit controls shift clock input and output. • The P21/SCK pin function as the shift clock input pin when this bit is set to “0” and as the shift clock output pin when set to “1”. • Set the P21/SCK pin as an input port when using this pin as the shift clock input. Also, selects external shift clock operation in the shift clock selection bits (SMC1: CLK2, CLK1, CLK0 = 100B) • When using this pin as internal shift clock output (SCKE = 1), select internal shift clock operation (SMC1: CLK2, CLK1, CLK0 = other than "100B") Notes: • The pin functions as the SCK output pin when shift clock is enabled (SCKE = 1) regardless of the state of the general-purpose port (P21). • Set to shift clock input operation (SCKE = 0) when using this pin as a general-purpose port (P21). bit1 RIE: Receiving interrupt enable bit This bit enables receiving interrupts. If the RDRF bit is "1" or if any error flag is "1", a receiving interrupt is immediately generated once receiving interrupts are enabled. bit0 TIE: Transmission interrupt enable bit This bit enables transmission interrupts. If the TDRE bit is "1", a transmission interrupt is immediately generated once transmission interrupts are enabled. 305 CHAPTER 15 UART/SIO 15.4.3 Serial Status and Data Register (SSD) The serial status and data register (SSD) is used to set and monitor transmit/receive operations, error status. ■ Serial Status and Data Register (SSD) Figure 15.4-4 Serial Status and Data Register (SSD) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0023H PER OVE FER RDRF TDRE — — — 00001---B R R R R R R — 306 : Read only : Undefined : Initial value TDRE 0 1 Transmission data register empty Full of transmission data Empty RDRF 0 1 Receive data register full Empty Full of receiving data FER 0 1 Framing error flag No frame error Framing error OVE 0 1 Overrun error flag No overrun error Overrun error PER 0 1 Parity error flag No parity error Parity error Table 15.4-3 Functions of Bits in Serial Status and Data Register (SSD) Bit name Function bit7 PER: Parity error flag This bit is set when a parity error is generated during receiving. This bit can be cleared by writing "0" to the RERC bit of the SMC2 register. When this flag is set, SIDR data becomes invalid. If the PER bit is set when the RIE bit of the SMC2 register is "1", a receiving interrupt request is generated. bit6 OVE: overrun error bit This bit is set when an overrun error is generated during receiving. This bit can be cleared by writing "0" to the RERC bit of the SMC1/SMC2 register. When this flag is set, SIDR data becomes invalid. If the OVE bit is set when the RIE bit of the SMC2 register is "1", a receiving interrupt request is generated. bit5 FER: Framing error flag This bit is set when a framing error is generated during receiving. This bit can be cleared by writing "0" to the RERC bit of the SMC2 register. When this flag is set, SIDR data becomes invalid. If the FER bit is set when the RIE bit of the SMC2 register is "1", a receiving interrupt request is generated. bit4 RDRF: Receive data register full This flag represents the status of the receiving data register SIDR. This flag is set when receiving data is loaded into the SIDR register. It is cleared when the SIDR register is read. If the RDRF bit is set when the RIE bit of the SMC2 register is "1", a receiving interrupt request is generated. bit3 TDRE: Transmission data register empty This flag represents the status of the transmission data register SODR. This flag is cleared when transmission data is written into the SODR register. It is set when the data is loaded into the transmission shift register and transmission begins. If the TDRE bit is set when the TIE bit of SMC2 register is "1", a transmission interrupt request is generated. bit2 to bit0 Undefined bits • The read value is undefined. • Writing to these bits has no effect on the operation. 307 CHAPTER 15 UART/SIO 15.4.4 Serial Input Data Register (SIDR) The serial input data register (SIDR) is used to input (receive) serial data. ■ Serial Input Data Register (SIDR) Figure 15.4-5 shows the bit configuration of the serial input data register. Figure 15.4-5 Serial Input Data Register (SIDR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R X Initial value XXXXXXXXB 0024H R R R R R R R : Read only : Undefined value • This register stores received data. Serial data signal sent to the serial data input pin (SI pin) is converted in the shift register and stored in this register. • If received data is normally set in this register, the receive data flag bit (RDRF) is set to "1", and a receive interrupt request occurs if it is enabled. When the interrupt request is detected, check the RDRF bit in an interrupt processing or in a program. If a receive data is stored on this register, read this register, and then the RDRF flag is cleared automatically. 308 15.4.5 Serial Output Data Register (SODR) The serial output data register (SODR) is used to output (transmit) serial data. ■ Serial Output Data Register (SODR) Figure 15.4-6 shows the bit configuration of the serial output data register. Figure 15.4-6 Serial Output Data Register (SODR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 XXXXXXXXB 0024H W W X Initial value W W W W W W W : Write only : Undefined value • When transmission is enabled, writing transmit data to this register will transfer the transmit data to the transmit register. The transmit data is converted on the transmit shift register and sent to the serial data output pin (SO). • Setting transmit data in the SODR register sets the transmit data flag to "0". After the transmit data is transferred to the transmit shift register, the transmit data flag is set to "1" and the SODR is ready for the next data. If transmit interrupt request is enabled, interrupt occurs. Write next transmission data when transmit data flag bit is set to "1". • When the data rate length is set to 7 bits, bit7 does not have meaning. 309 CHAPTER 15 UART/SIO 15.4.6 Serial Rate Control Register (SRC) The serial rate control register (SRC) is to set the UART/SIO transmission speed (baud rate). ■ Serial rate control register (SRC) Figure 15.4-7 shows the bit configuration of the serial rate control register. Figure 15.4-7 Serial rate control register (SRC) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB 0022H R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined value When the clock selection bits, CLK2 to CLK0 of SMC1, are set to "011B", the dedicated baud rate generator is selected as the serial clock. Also, be sure to write to this register only when the UART/SIO operations are stopped. 310 15.5 UART/SIO Interrupts The UART/SIO has five flags related to interrupts - three error flag bits (PER, OVE, FER), a receive data flag bit (RDRF) and a transmit data flag bit (TDRE). Except the TDRE flag which is related to data transmission, all other four flags are related to data reception. ■ Transmit Interrupt • When transmission is enabled, writing transmit data to this SODR register transfers the transmit data to the transmit register. The transmit data is converted on the transmit shift register and sent from the serial data transmit pin (SO). • When the UART/SIO is ready to accept next data, the TDRE is set to “1”, and an interrupt request (IRQ5) is output to the CPU if transmit interrupt request is enabled (SMC2: TIE=1). ■ Receive Interrupt • When the data is input normally to the stop bit(s), the RDRF is set to "1". When an over run error or a framing error or parity error occurs, each corresponding error flag bit is set to "1". • These bits are set when the stop bit(s) are detected, and an interrupt request (IRQ5) to the CPU is generated if receive interrupt is enabled (SMC2: RIE=1). ■ Register and Vector Table for UART/SIO Interrupts Table 15.5-1 Registers and Vector Tables for UART/SIO Interrupts Interrupt level setting register Vector table address Interrupt Register IRQ5 ILR2 (007CH) Setting bits L51 (bit3) L50 (bit2) Upper Lower FFF0H FFF1H Reference: See "3.4.2 Interrupt Processing" for details on the interrupt operation. 311 CHAPTER 15 UART/SIO 15.6 Operation of UART/SIO This section describes the operation of the UART/SIO. The UART/SIO has a serial communication function (operation mode 0 and 1). ■ Operation of UART/SIO ● Operation mode The UART/SIO has 2 operation modes. The modes 0 and 1 are standard serial transmission modes in which a data type from 7 bit data length/parity or 8 bit data length/non-parity is selected (See Table 15.5-1). 312 15.7 Operation of mode 0 The operating mode 0 provides an asynchronous mode operation. ■ Operation of Operating Mode 0 • The serial clock is selected by the bits CLK2 to CLK0 of the SMC1 register. Selection can be made from five sources: three internal clock outputs, one external clock output, and one baud rate generator output. Always be sure to input a clock when the external clock has been selected. • In clock asynchronous mode, the shift clock selected by the bits CLK2 to CLK0 is divided by eight for use as the baud rate generator. Data transfer in the range -2% to +2% of the selected baud rate is possible. Figure 15.7-1 Transmit Operation in Mode 0 (CLK2, CLK1, CLK0 not equal to 011B) 1 (bps) Baud rate = Clock selection from CLK2 to CLK0 8× Figure 15.7-2 Transmit Operation in Mode 0 (CLK2, CLK1, CLK0 = 011B) 1 (bps) Baud rate = 8× 2× n× 4/FCH 8/FCH 16/FCH 64/FCH FCH : Main clock source oscillation frequency n : Value of serial rate control register SRC speed-shift selection Table 15.7-1 Baud Rate Setting Frequency FCH 12.5MHz 8MHz 7.3728MHz 4.9152MHz Instruction cycle 4/FCH(0.32µs) 4/FCH(0.5µs) 4/FCH(0.54µs) 4/FCH(0.81µs) 97656(n=2) 62500(n=2) — 76800(n=1) 48828(n=4) 31250(n=4) 38400(n=3) 38400(n=2) 13020(n=15) 10417(n=12) 19200(n=6) 19200(n=4) 12207 (n=16) 9615 (n=13) 9600 (n=12) 9600 (n=8) 6104 (n=32) 4807 (n=26) 4800 (n=24) 4800 (n=16) 3004 (n=65) 2403 (n=52) 2400 (n=48) 2400 (n=32) 1502 (n=130) 1201 (n=104) 1200 (n=96) 1200 (n=64) — 600 (n=208) 600 (n=192) 600 (n=128) — — — 300 (n=0) Baud rate 313 CHAPTER 15 UART/SIO ■ Transmission Data Format The UART/SIO uses only data of the NRZ (Non-Return to Zero) format. The diagram below shows this data format. In the diagram a stop bit length of two bits is used. As shown in the diagram below, transfer data must begin from a start bit ("L" level), and the data bit length specified by the LSB first is transferred and then ends on a stop bit ("H" level). Transfer data is assumed as "H" level when idle. Figure 15.7-3 Transfer Data format 7-bit length 1 St D0 D1 D2 D3 D4 D5 D6 Sp Sp Parity off Stop bit 2 bits 7-bit length 2 Parity on St D0 D1 D2 D3 D4 D5 D6 P Sp Sp Stop bit 2 bits 8-bit length 3 Parity off St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp Stop bit 2 bits 8-bit length 4 St D0 D1 D2 D3 D4 D5 D6 D7 P Parity on Sp Sp St: Start bit D0 to D7: Data bits P: Parity bit Stop bit 2 bits ■ Receiving Operation in Clock Asynchronous Mode • Bits CLK2 to CLK0 of the SMC1 register select the baud rate clock. For information on the baud rate clock, see Figure 15.7-4 and Table 15.7-1. Receiving is enabled when the RXE bit of the SMC1 register is set to "1". Receiving operation starts at the first falling edge (detection of a start bit) of input data. Once receiving operation has ended, the RDRF bit of the SSD register is set to "1", and receiving data is loaded into the SIDR register. Also, if the RDRF bit is set to "1" when the RIE bit is "1", a receiving interrupt is sent to the CPU. If any one of three errors (PER, OVE, or FER) is present when receiving ends, the RDRF bit will not be set to "1", and receiving data will not be loaded into SIDR. Therefore, the value in the SIDR register will be the former data received. Also, as long as the RXE bit is not set to "0" receiving operation will continue when a start bit is detected even if an error flag is present. • Writing a "0" to the RXE bit of the SMC2 register during receiving operation will disable any further receiving operation once current data receiving has ended. Figure 15.7-4 Receiving Operation in CLK Asynchronous Mode. RXE SI SIDR is read RDRF 314 St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2 ■ Receiving Errors in Asynchronous Mode • Three types of error detection are performed in asynchronous mode. The three errors are: parity error, overrun error, and framing error. When an error is detected, a "1" is set in the corresponding PER, OVE, or FER bit of the SSD register. • These errors are detected as described below when receiving ends. When any of these errors is detected, the RDRF bit will not be set, and receiving data will not be loaded into the SIDR register. Therefore the value in the SIDR register will be last data received. Also, these error flags can all be cleared by writing "0" into the RERC bit of the SMC2 register. Figure 15.7-5 Set Timing for receive errors SI D5 D6 D7/P Sp Sp PER OVE FER Error interrupt ■ Detecting the Start Bit during Receiving Operation The start bit is recognized when a "L" level is present for four clock pulses of the selected serial clock (clock generator output, and so on.) after the first falling edge of input data. After the start bit is detected, data is sampled at the rising edge of the fifth clock pulse of the serial clock Figure 15.7-6 Start Bit Detection Serial clock 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 D0 SI1 4 clock pulses Start bit detected Data sampled St: Start bit D0 to D7: Data bits 315 CHAPTER 15 UART/SIO ■ Transmission Operation in Clock Asynchronous Mode • When the TXE bit of the SMC2 register is set to "1", the TDRE bit of the SSD register is cleared, and transmission operation begins once transmission data is written into the SODR register. The TDRE bit of the SSD register is set once transmission data output begins after the data in the SODR register is loaded into the shifter. Writing data to the SODR register during transmission operation (when the TDRE bit is "1") causes the TDRE bit to be cleared, and transmission operation to continue after current transmission operation for the specified bit length has been terminated. • Also, writing "0" to the TXE bit of the SMC2 register during transmission operation disables transmission operation once current transmission for the specified bit length ends on condition that the SODR register is empty (the TDRE bit is "1".) If there is data in the SODR register (TDRE bit is "0"), transmission operation will be disabled once data in the SODR register has been transmitted. Figure 15.7-7 Transmission Operation in CLK Asynchronous Mode TXE Data is written to SODR TDRE An interrupt is sent to the CPU SO An interrupt is sent to the CPU St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2 St: Start bit D0 to D7: Data bits Sp: Stop bit 316 15.8 Operation of mode 1 The operating mode 1 provides a clock synchronous mode operation. ■ Operation of Operating Mode 1 • In synchronous mode, the CLK2 to CLK0 bits of the SMC1 register select the clock from one of five source: three internal clocks, an external clock, or the baud rate generator. Shift operation are then performed using the selected clock as a shift clock. Be sure to set the SCKE bit of SMC2 to "0" when an external clock is input. • Also, be sure to set the SCKE bit to "1" if outputting an internal clock or baud rate generator as the shift clock. The following equation is show the calculating the baud rate in synchronous mode Figure 15.8-1 Transmit Operation in Mode 1 (CLK2, CLK1, CLK0 = 011B) 1 (bps) Baud rate = 2× n× 4/FCH 8/FCH 16/FCH 64/FCH speed-shift selection FCH : Main clock oscillation frequency n : Value of serial rate control register SRC Figure 15.8-2 Transmit Operation in Mode 1 (CLK2, CLK1, CLK0 are not 011B) 1 (bps) Baud rate = Clock selection from CLK2 to CLK0 317 CHAPTER 15 UART/SIO ■ 8-bit Receiving Operation Figure 15.8-3 Setting of 8-bit Receiving Operation in CLK Synchronous Mode bit7 SMC1 MD 1 SMC2 bit6 bit5 bit4 bit3 PEN TDP SBL CL 0 0 0 bit2 bit1 bit0 CLK2 CLK1 CLK0 1 RERC RXE TXE BRGE TXOE SCKE RIE TIE 0 SSD PER OVE FER RDRF TDRE X X X — — X 1 0 — X : Used bit : Unused bit : Set "1" : Set "0" Receiving operation can be enabled by setting the TXE, RXE bits to "11B". Operation starts when data is written to the SODR register. Receiving operation is performed in synchronization with the rising edge of the shift clock. Once receiving the 8-bit data has ended, shifter data is loaded into the SIDR register, the RDRF flag is set to "1", and, if the RIE bit is "1", an interrupt request is sent to the CPU. If an overrun error has occurred when receiving has ended, data will not be loaded into the SIDR register. Writing "0" to the TXE bit during receiving operations will stop the reception operations once the current 8-bit data reception has ended. Be sure that serial clock input is always "H" level when serial operation is stopped (regardless of the value of the RXE bit). Figure 15.8-4 8-bit Receiving Operation in CLK Synchronous Mode Data is written to SODR SCK SI 0 1 2 3 4 5 6 7 Data is loaded into SIDR RDRF An interrupt is sent to the CPU 318 ■ Continuous Receiving Operations In synchronous mode, it is possible to perform continuous receiving operations in addition to the 8-bit data receiving. In addition to the bits used during the 8-bit receiving, the TIE bit of the SMC2 register and the TDRE bit of the SSD register are also used for this type of operation. Receiving operation is enabled by setting the TXE,RXE bits to "11B". This operation starts when data is written to the SODR register. Receiving operation is performed in synchronization with the rising edge of the shift clock. Once shift operation begins, the TDRE bit is set to "1", and an interrupt is sent to the CPU if the TIE bit is "1". The next shift operation can be enabled by writing data to the SODR register before the current 8-bit shift operation ends, and this allows receiving operation to continue even after receiving the 8-bit data. After receiving 8-bit data, the data in the shifter is loaded into the SIDR register and the RDRF flag is set to "1", and then if the RIE bit is "1", an interrupt request is sent to the CPU. If an overrun error occurs after receiving the data, the data will not be loaded into the SIDR register, therefore the contents of the SIDR register will be last data received. Also, reading the SIDR register clears the receiving interrupt (RDRF). Subsequent receive operations can be stopped by writing "0" to the TXE bit. Writing "0" to the TXE bit during receiving operation stops receiving operation after receiving the current 8-bit data. Figure 15.8-5 Continuous Receiving Operations in Synchronous Mode SCK SI 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Data is written to SODR TDRE Data is loaded to SIDR RDRF An interrupt is sent to the CPU SIDR is read An interrupt is sent to the CPU 319 CHAPTER 15 UART/SIO ■ 8-bit Transmission Operation Figure 15.8-6 Setting of 8-bit Transmission Operation bit7 SMC1 MD 1 SMC2 bit6 bit5 bit4 bit3 PEN TDP SBL CL 0 0 0 bit2 bit1 bit0 CLK2 CLK1 CLK0 1 RERC RXE TXE BRGE TXOE SCKE RIE TIE 1 SSD PER OVE FER RDRF TDRE X X — — X 1 0 — X : Used bit : Unused bit : Set "1" : Set "0" The transmission operation can be activated by writing the SODR register after setting the TXE,RXE bits to "11B". When transmission operation starts, the data written in the SODR register is loaded into the shifter and shift operation begins. Once SODR register data is loaded into the shifter, the TDRE flag is set to "1" and, if the TIE bit is "1", an interrupt request is sent to the CPU. Serial data output can be enabled by setting TXOE to "1", then output is made in synchronization with the falling edge of the shift clock. Writing "0" to the TXE bit during transmission operation stops transmission operation once current 8-bit data is transmitted. Also, after transmitting the 8-bit data, the RDRF bit is automatically set to "1", and an interrupt is sent to the CPU if the RIE bit is "1". Data transmission begins from bit0 and ends at bit7. Be sure to set the serial clock input to "H" level when serial operation is stopped (regardless of the value of the TXE bit). Figure 15.8-7 8-bit Transmission Operation Data is written to SODR SCK SO 0 1 2 3 4 5 6 7 TDRE RDRF An interrupt is sent to the CPU 320 An interrupt is sent to the CPU ■ Continuous Transmission Operations In clock synchronous mode, it is possible to perform continuous transmission operations in addition to transmitting the 8-bit data. The transmission operation is enabled by setting the TXE,RXE bits to "11B" and then, start when data is written to the SODR register. Once transmission operation starts, data written in the SODR register is loaded into the shifter and shift operation begins. When data in the SODR register is loaded into the shifter, the TDRE flag is set to "1" and, if the TIE bit is "1", an interrupt is sent to the CPU. The continuous operations are performed by writing the next data to be transmitted into the SODR register (SODR register is empty) during current transmission operation while the TDRE bit is "1". The TDRE bit is cleared by writing to SODR, and then the data written in the SODR register is loaded into the shifter and transmission operation continues after transmitting the current 8-bit data. Subsequent transmission operation can be stopped by writing "0" to the TXE bit. Writing "0" to the TXE bit during transmission operation when the SODR register is empty (TDRE bit is "1") will stop transmission operation after transmitting the current 8-bit. Also, when there is data in the SODR register (TDRE bit is "0"), transmission operation will stop after data in the SODR register has been transmitted. Finally, when the 8-bit data transmission ends, the RDRF bit is set to "1", and, if the RIE bit is "1", an interrupt is sent to the CPU. Figure 15.8-8 Continuous Transmission Operation in Synchronous Mode Data is written to SODR SCK SO 0 1 2 3 4 5 6 7 0 1 2 3 TDRE RDRF An interrupt is sent to the CPU An interrupt is sent to the CPU 321 CHAPTER 15 UART/SIO 322 CHAPTER 16 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output. 16.1 Overview of Buzzer Output 16.2 Block Diagram of Buzzer Output 16.3 Structure of Buzzer Output 16.4 Program Example for Buzzer Output 323 CHAPTER 16 BUZZER OUTPUT 16.1 Overview of Buzzer Output The buzzer output can select from seven different output frequencies (square waves) and can be used for applications such as sounding a buzzer to confirm key input. The function uses the same output pin as the remote control transmit output. ■ Buzzer Output Function The buzzer output function outputs a signal (square wave) suitable for applications such as sounding a buzzer to confirm an operation. • For buzzer output, one of seven output frequencies can be selected, or the output disabled. • Four divide-by-n outputs are supplied from the time-base timer and three from the watch prescaler, for selection as the buzzer output signal. Reference: Since divided outputs of the time-base timer and watch prescaler are fed as the buzzer output signal, the buzzer output will be affected when the signal source selected for it (time-base timer or watch prescaler) is cleared. Note: Since the time-base timer stops when the main clock oscillator stops (during sub clock mode), do not select the divided output of the time-base timer as the buzzer output when sub clock mode is used. Similarly, do not select the watch prescaler as the buzzer source in a chip in which the single clock system is selected. 324 Table 16.1-1 lists the seven output frequencies (square waves) that can be selected for the buzzer output function. Table 16.1-1 Output Frequency Clock supply source Buzzer output cycle Square wave output (Hz) 212/FCH FCH/212 (3.052 kHz) 211/FCH FCH/211 (6.104 kHz) 210/FCH FCH/210 (12.207 kHz) 29/FCH FCH/29 (24.414 kHz) 25/FCL FCL/25 (1.024 kHz) 24/FCL FCL/24 (2.048 kHz) 23/FCL FCL/23 (4.096 kHz) Time-base Timer Watch Prescaler FCH: Main clock oscillation frequency FCL: Sub clock oscillation frequency The frequencies enclosed in parentheses ( ) are for FCH = 12.5 MHz, and FCL = 32.768 kHz. Note: Calculation example for output frequency. For a 12.5 MHz main clock source oscillation and if the buzzer register (BUZR) selects a time-base timer divided output of FCH/210 (BZ2, BZ1, BZ0 = 011B), the output frequency of the BUZ pin is calculated as follows: Output frequency = FCH/210 = 12.5 MHz/1024 = approx. 12.207 kHz 325 CHAPTER 16 BUZZER OUTPUT 16.2 Block Diagram of Buzzer Output The buzzer output consists of the following two blocks: • Buzzer output selector • Buzzer output register (BUZR) ■ Block Diagram of Buzzer Output Figure 16.2-1 Block Diagram of Buzzer Output Internal data bus BUZR BZ2 BZ1 BZ0 Select From time-base timer From watch prescaler 212/FCH 211/FCH 210/FCH 29/FCH 25/F Buzzer output selector Buzzer output enable signal Buzzer output Pin CL 24/FCL 23/FCL P07/INT27/BUZ FCH: Main clock oscillation frequency FCL: Sub clock oscillation frequency ● Buzzer output selector Selects one of the four frequencies output from the time-base timer or three frequencies output from the watch prescaler. ● BUZR register The BUZR register to set the buzzer output frequency and enable buzzer output. Buzzer output is enabled if an output frequency is specified (BUZR: BZ2, BZ1, BZ0 = other than "000B") in the BUZR register. 326 16.3 Structure of Buzzer Output This section describes the pin, pin block diagram, and register of the buzzer output. ■ Buzzer Output Pin The buzzer output uses the P07/INT27/BUZ pin. This pin can function either as an general purpose I/O port (P07), external interrupt input (INT27) or the buzzer output pin (BUZ). BUZ:This pin outputs a buzzer square wave with the specified frequency. Setting a buzzer output frequency in the buzzer output register (BZCR: BZ2, BZ1, BZ0 = other than "000B") automatically sets the P07/BUZ pin as the BUZ pin. ■ Block Diagram of Buzzer Output Pin Figure 16.3-1 Block Diagram of Buzzer Output Pin (P07/BUZ) Buzzer output Buzzer output enable PDR (Port data register) Stop, watch mode Pull up resistor control register PDR read Internal data bus Pull-up resistor Approx. 50 kΩ P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write Pin N-ch DDR P07/INT27/BUZ DDR write (Port direction register) Stop mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Buzzer Output Register Figure 16.3-2 Buzzer Output Register BUZR (Buzzer Register) Address bit7 0040H — bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value — — — — BZ2 BZ1 BZ0 -----000B R/W R/W R/W R/W : Readable/Writable — : Undefined 327 CHAPTER 16 BUZZER OUTPUT 16.3.1 Buzzer Register (BUZR) The buzzer register (BUZR) is used to select the buzzer output frequency and also enables buzzer output. ■ Buzzer Register (BUZR) Figure 16.3-3 Buzzer Register (BUZR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0040H — — — — — BZ2 BZ1 BZ0 -----000B R/W R/W R/W BZ2 BZ1 BZ0 R/W : Readable/Writable — : Undefined X : Undefined value : Initial value FCH : Main clock oscillation frequency FCL : Sub clock oscillation frequency 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Buzzer selection bits Disables buzzer output. Makes pin available for use as a general-purpose port (P07). FCH/212 Functions as a buzzer output pin (BUZ). Time-base timer outputs FCH/211 FCH/210 FCH/29 Watch prescaler outputs FCL/25 FCL/24 FCL/23 Table 16.3-1 Buzzer Register (BUZR) Bits Bit name Function bit7 to bit3 Unused bits bit2 to bit0 These bits selects buzzer output and enable output. Setting "000B" disables the buzzer output and sets the pin as a general-purpose output port (P07). Setting other than "000B" sets the pin as the buzzer output (BUZ) pin and outputs a square wave of the selected frequency. Selects one of four divided outputs from the time-base timer or three from the timeclock BZ2, BZ1, BZ0: prescaler. Buzzer selection bits Do not select a time-base timer division output in sub clock mode. The sub clock oscillator operates in the main-stop mode. Therefore, if the pin state specification bit (STBC: SPL) is "0", the buzzer output can be used even in main-stop mode by selecting one of the watch prescaler divided-by-n outputs (BZ2, BZ1, BZ0 = 101B to 111B). 328 The read value is undefined. Writing to these bits has no effect on the operation. 16.4 Program Example for Buzzer Output This section gives a program example for the buzzer output. ■ Program Example for Buzzer Output ● Processing description • Output a buzzer output of approximately 3.051 kHz to the BUZ pin, then turn the buzzer output "OFF". • For a 12.5 MHz main clock source oscillation and selecting 212/FCH (FCH: main clock oscillation), the buzzer output frequency is as follows: Buzzer output frequency = 12.5 MHz/212 = 12.5 MHz/4096 = 3.052 kHz ● Coding example BUZR EQU 0040H ; Buzzer register ;-----Main program---------------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : BUZON MOV BUZR,#00000001B ; Buzzer output "ON". : : : BUZOFF MOV BUZR,#00000000B ; Buzzer output "OFF". : ENDS ;-------------------------------------------------------------------------------------------------------------------------------END 329 CHAPTER 16 BUZZER OUTPUT 330 CHAPTER 17 LCD CONTROLLER/DRIVER This chapter describes the functions and operation of the LCD controller/driver. 17.1 Overview of LCD Controller/Driver 17.2 Block Diagram of LCD Controller/Driver 17.3 Structure of LCD Controller/Driver 17.4 Operation of LCD Controller/Driver 17.5 Program Example for LCD Controller/Driver 331 CHAPTER 17 LCD CONTROLLER/DRIVER 17.1 Overview of LCD Controller/Driver The LCD controller/driver includes 16 bytes of built-in display RAM, the contents of which control an LCD display via 31 segment and 4 common outputs. The LCD controller/driver can drive an LCD display panel directly, using one of three selectable duty ratios. ■ LCD Controller/Driver Function The LCD controller/driver function displays the contents of a display data memory directly to the LCD panel (liquid crystal display) by segment and common outputs. • Built-in dividing resistor for LCD driving voltage. (selected by mask option) • Can be connected to the external divider resistor. • Built-in booster. (selected by mask option) • Up to 31 segment outputs (SEG0 to SEG30, select resistor ladder) Up to 26 segment outputs (SEG1 to SEG26, select booster) and four common outputs (COM0 to COM3) may be used. • Built-in display RAM: 16 bytes (32 × 4 bits) • Three selectable duty ratios (1/2, 1/3 and 1/4). Not all duty ratios are available with all bias settings, however. • Either the main or sub clock can be selected as the drive clock. • LCD can be driven directly. Table 17.1-1 shows the duty ratios available with each bias setting Table 17.1-1 Bias and Duty Ratio Combinations Bias 1/2 duty ratio Without internal voltage booster 1/2 bias 1/3 bias × With internal voltage booster 1/2 bias × 1/3 bias × 1/3 duty ratio 1/4 duty ratio × × × × :Recommended mode × : Do not use Notes: • Built-in booster cannot be used to generate LCD driver supply voltage if single clock option is selected. • The 1/2 bias mode cannot be used if LCD driver supply voltage is generated by booster. 332 17.2 Block Diagram of LCD Controller/Driver The LCD controller/driver is made up of the nine blocks listed below. Functionally, the circuit can be broken into two major sections: the controller section, which generates LCD segment and common signals based on the current contents of display RAM, and the driver section, which develops sufficient drive to operate the display. • LCD control register 1 (LCR1) • LCD control register 2 (LCR2) • Display RAM • Prescaler • Timing controller • V/I converter • Common output driver • Segment output driver • Dividing resistor/Booster ■ Block Diagram of LCD Controller/Driver Figure 17.2-1 Block Diagram of LCD Controller/Driver Dividing resistor / Booster Prescaler Sub clock (32 kHz) Timing controller V/I converter Internal bus 4 31 Display RAM 32 × 4 bit (16 bytes) Controller Common output driver FCH/27 (Time-base timer output) COM0 COM1 COM2 COM3 Segment output driver LCDC LCD control controlregister register1/2 1/2 (LCR1/LCR2) V3 V2 V1 V0 C1 C0 SEG0 SEG1 SEG2 SEG3 SEG4 : : SEG26 SEG27 SEG28 SEG29 SEG30 Driver 333 CHAPTER 17 LCD CONTROLLER/DRIVER ● LCD control register 1/2 (LCR1/LCR2) These registers are used to select the frame clock (the clock used to generate the frame cycle), enable/ disable operation in watch mode, control the LCD driver supply voltage, select display blanking/nonblanking, select the display mode, and select the LCD clock cycle. ● Display RAM This 32 × 4-bit block of RAM controls the segment output signals. Its contents are automatically read in sync with the timing of the selected common signal, and output from the segment outputs at the same time as writing the display RAM. ● Prescaler The prescaler selects settings from 2 clocks and 4 frequencies to generate the frame frequency. ● Timing controller This block controls the segment and common signals based on the frame frequency and LCR1/LCR2 register settings. ● V/I converter This circuit generates alternating current waveforms from the voltage signals it receives from the timing controller to drive the LCD. ● Common output driver Contains the drivers for the LCD common pins. ● Segment output driver Contains the drivers for the LCD segment pins. ● Dividing resistor / Booster Generate LCD driver supply voltage. ■ LCD Controller/Driver Supply Voltage The LCD driver supply voltage can be generated from booster or voltage divider. The voltage divider can be made up of internal dividing resistors or external dividing resistors connected to the V1 to V3 pins. 334 17.2.1 LCD Controller/Driver Internal Dividing Resistors (Device without Voltage Booster) In devices that have internal dividing resistors, the LCD driver supply voltage can be generated from an internal voltage divider. (External dividing resistors may also be used.) ■ Internal Dividing Resistors • The selection of internal or external diving resistors is made by the drive supply voltage control bit of LCD control register 1 (LCR1: VSEL). VSEL = 1 connects the internal resistors. Set VSEL to "1" when you want to use the internal resistors only (when no external resistors are connected). • The LCD enable is inactive when LCD operation is stopped (LCR1: MS1 = MS0 = 00B), and when operation is stopped (LCR1: LCEN = 0) in watch mode (STBC: TMD = 1). Pin V2 and V1 should be shorted together when using the 1/2 bias setting. Figure 17.2-2 shows an equivalent circuit of the internal voltage divider Figure 17.2-2 Internal Voltage Divider Equivalent Circuit Vcc 2R P-ch N-ch V3 V3 R P-ch N-ch V2 V2 R P-ch Short together when using 1/2 bias. N-ch V1 V1 R P-ch N-ch LCDC enable VSEL N-ch MB89480 Series V1 to V3: Voltages at V1 to V3 pins. 335 CHAPTER 17 LCD CONTROLLER/DRIVER ■ Use of Internal Voltage Divider Resistors Figure 17.2-3 shows the voltage divider circuits for 1/2 and 1/3 bias. As shown in this figure, in the 1/2 bias mode (with LCDC enabled) V2 and V1 will be 1/2 of V3 (V3 is the LCD operating voltage, which is VCC/ 2 in this configuration). In the 1/3 bias mode, V1 is 1/3 of V3, and V2 is 2/3 of V3. Figure 17.2-3 Use of Internal Voltage Divider Resistors Vcc Vcc 2R 2R V3 V3 V3 V2 V1 R V2 R V1 V3 R V2 R V1 V1 R LCDC enable V2 R LCDC enable N-ch MB89480 series MB89480 series 1/2 Bias 1/3 Bias N-ch V1 to V3: Voltages at V1 to V3 pins. ■ Display Brightness Adjustment when Internal Divider Resistors are Used When internal divider resistors do not provide sufficient LCD display brightness, connect an external brightness adjust variable resistor (VR) between VCC and V3 as shown in Figure 17.2-4. Figure 17.2-4 Use of Internal Voltage Divider Resistors with Brightness Adjustment Vcc 2R V3 V3 V2 V1 R VR V2 R V1 R LCDC enable N-ch MB89480 Series When display brightness adjustment is desired V1 to V3: Voltages at V1 to V3 pins. 336 Reference: During LCD operation, the 2R internal resistance will be in the divider circuit, and VR will be in parallel with this resistor. 337 CHAPTER 17 LCD CONTROLLER/DRIVER 17.2.2 LCD Controller/Driver External Dividing Resistors (Device without Booster) External voltage dividing resistors can also be used with devices that have internal dividing resistors. Display brightness can be adjusted by a variable resistor connected between the Vcc and V3 pins. ■ External Dividing Resistors If you do not wish to use the internal divider resistors, external voltage divider resistors can be connected at the LCD drive voltage supply pins (V1 to V3). Figure 17.2-5 shows connections for external divider resistors for the two biasing modes, and Table 17.2-1 lists the corresponding LCD drive voltages Figure 17.2-5 External Voltage Divider Resistor Connections Vcc Vcc V3 VR V3 VR R R V2 V2 R VLCD VLCD V1 V1 R R MB89480 series MB89480 series 1/3 bias 1/2 bias Table 17.2-1 LCD Drive Voltages and Biasing Modes V3 V2 V1 1/2 bias VLCD 1/2VLCD 1/2VLCD 1/3 bias VLCD 2/3VLCD 1/3VLCD V1 to V3: Voltages at pins V1 to V3. VLCD: LCD operating voltage 338 17.2.3 LCD Controller/Driver Power Supply Voltage (Devices with Internal Voltage Booster) In devices that have an internal voltage booster, the supply voltage for the LCD driver is developed by the reference voltage generator and voltage booster. V0 to V3, C0, and C1 pins are used to connect external capacitors. V1 can also be used to connect an external reference voltage. ■ Devices with Internal Voltage Boosters ● Reference voltage generator An external circuit can be used to supply the reference voltage to the voltage booster. The external reference voltage is connected to the V1 pin. ● Voltage booster From a 32.768 kHz input clock (sub clock) and the reference voltage, the internal voltage booster configured as shown in Figure 17.2-6 generates a voltage equal to twice or three times the reference voltage (depending on the switch position). Since the circuit uses the sub clock, it does not work in modes in which the sub clock is stopped (during sub-stop mode, etc.). Similarly, it cannot be used in devices for which the single-clock option is selected. When the voltage booster is used, capacitors as shown in Figure 17.2-6 should be connected to pins V0 to V3, C0, and C1. Since the voltage booster cannot generate 1/2 bias voltage, do not select 1/2 duty ratio output mode (LCR1: MS1, MS0 = 01B) 339 CHAPTER 17 LCD CONTROLLER/DRIVER Figure 17.2-6 Reference Voltage Generator/Voltage Booster External Connections Voltage booster X0A X1A Sub clock generator C1 C0 C2 C3 V0 V3 V2 V1 C4 C5 Reference Voltage Check: When applying an external reference voltage at the V1 pin, check the applicable data sheet for information on the maximum voltage, etc. to be used. 340 17.3 Structure of LCD Controller/Driver The section describes the pins, pin block diagrams, register, and display RAM of the LCD controller/driver. ■ LCD Controller/Driver Pins The LCD controller/driver uses 4 common output pins (COM0 to COM3), 31 segment output pins (SEG0 to SEG30), 2 external capacitor pins (C0 and C1), 3 LCD driving power supply pins (V1 to V3). ● COM0, COM1, P31/COM2, and P32/COM3 Pins • P30/COM2 and P31/COM3 pins can function either as output-only ports (P30 and P31) or LCD common output pins (COM2 and COM3). The selection is selected by the operation of the LCDC (LCR1: MS1,MS0=10B or 11B). • When LCD display operation stop (LCR1: MS1, MS0=00B) or 1/2 duty ratio is selected (LCR1: MS1 MS0=01B), P30/COM2 and P31/COM3 function as output only ports (P30 and P31). • When 1/3 duty ratio is selected (LCR1: MS1, MS0=10B), P30/COM2 function as LCD common output pin (COM2) and P31/COM3 function as output only port. • When 1/4 duty ratio is selected (LCR1: MS1, MS0=11B), P30/COM2 function as LCD common output pin (COM2) and P31/COM3 function as LCD common output pin (COM3). Note: When the pins are used as LCD common outputs, the corresponding port data register bits (PDR3: bit0 and bit1) should be set to "1" to turn the output transistor "off". (COM0 and COM1 are dedicated LCD common output pins.) ● SEG0/V0 to SEG7, P40/SEG8 to P47/SEG15, P50/SEG16 to P56/SEG22, and P10/SEG23 to P17/ SEG30 In device with Booster, SEG0 is used as V0. It can be used as segment output in device without booster only. Also, when booster is selected, segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled. P40/SEG8 to P47/SEG15, P50/SEG16 to P56/SEG22 and P10/SEG23 to P17/SEG30 pins can function either as general-purpose I/O ports (P40 to P47, P50 to P56 and P10 to P17) or LCD segment output pins (SEG8 to SEG15, SEG16 to SEG23, SEG24 to SEG30). The selection, is made by LCD control register 2 (LCR2: bit5 to bit0) Note: When these pins are used as LCD segment outputs, the corresponding port data registers (PDR1, PDR4 and PDR5) should be set to all "1s" to turn the output transistors off. (SEG0 to SEG7 are dedicated LCD segment output pins.) 341 CHAPTER 17 LCD CONTROLLER/DRIVER ● V1 to V3 They are the LCD driving power supply pins. ■ Block Diagrams of LCD Controller/Driver Pin Figure 17.3-1 Block Diagram of LCD Controller/Driver Pin (Dedicated Common/Segment Output Pins) Dedicated common/segment output pins Common/segment control signal P-ch LCD drive voltage (V3 or Vss) N-ch Pins COM0, COM1 SEG0*, SEG1 to SEG7 P-ch LCD drive voltage (V1 or V2) N-ch Common/segment control signal *: In device without booster V0 to V3: V1 to V3 pin voltages Figure 17.3-2 Block Diagram of LCD Controller-Driver Pin (Dual Function Common Output Pins, P30/COM2 and P31/COM3) Common control signal LCD driving voltage (V3 or Vss) P-ch LCD driving voltage (V1 or V2) P-ch N-ch N-ch Common control signal Internal data bus PDR (Port data register) LCD output enable N-ch PDR read Output latch PDR write Pins Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 342 N-ch P30/COM2 P31/COM3 Figure 17.3-3 Block Diagram of LCD Controller-Driver Pin (Dual Function Segment Output Pins, P40/SEG8 to P47/SEG15 and P50/SEG16 to P56/SEG22) Segment control signal LCD driving voltage (V3 or Vss) P-ch LCD driving voltage (V1 or V2) P-ch N-ch N-ch Segment control signal PDR (Port data register) Stop, watch mode LCD output enable Internal data bus PDR read N-ch PDR read (for bit manipulation instructions) Output latch PDR write Pins Stop, watch mode (SPL = 1) N-ch P40/SEG8 to P47/SEG15 P50/SEG16 to P50/ P56/SEG22 SPL: Pin state specification bit in the standby control register (STBC) 343 CHAPTER 17 LCD CONTROLLER/DRIVER Figure 17.3-4 Block Diagram of LCD Controller-Driver Pin (Dual Function Segment Output Pins, P10/SEG23/INT10 to P13/SEG26/INT13) Segment Control Signal LCD driving voltage V3 or Vss P-ch N-ch Segment Control Signal LCD driving voltage V1 or V2 P-ch N-ch PDR (Port data register) Stop, watch mode LCD output enable Internal data bus PDR read PDR read (for bit manipulation instructions) N-ch Output latch PDR write Pins DDR N-ch DDR write (Port direction register) Stop, watch mode (SPL = 1) P10/SEG23/INT10 to P13/SEG26/INT13 SPL: Pin state specification bit in the standby control register (STBC) Figure 17.3-5 Block Diagram of LCD Controller-Driver Pin (Dual Function Segment Output Pins, P14/SEG27/AN0 to P17/SEG30/AN3) Segment Control Signal LCD driving voltage V3 or Vss P-ch N-ch Segment Control Signal LCD driving voltage V1 or V2 PDR (Port data register) P-ch N-ch Stop, watch mode AD input enable LCD output enable Internal data bus PDR read N-ch PDR read (for bit manipulation instructions) Mask Option Output latch PDR write Pins DDR DDR write (Port direction register) Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 344 N-ch P14/SEG27/AN0 to P17/SEG30/AN3 Figure 17.3-6 Block Diagram of LCD Controller-Driver Pin (P24/C1/TO2, P25/C0/EC2) PDR (Port data register) Mask option * Stop, watch mode Booster Internal data bus PDR read Mask option * PDR read (for bit manipulation instructions) Output latch Pins PDR write DDR N-ch P24/C1/TO2 P25/C0/EC2 (Port direction register) DDR write DDR read Stop, watch mode (SPL = 1) * : If booster is selected by mask option, C0, C1 will connect to pin by mask option and input buffer will be disabled to avoid current leakage. SPL: Pin state specification bit in the standby control register (STBC) Figure 17.3-7 Block Diagram of LCD Controller-Driver Pin (P26/V1/TO1, P27/V2/EC1) LCD pin select PDR (Port data register) Stop, watch mode LCD driver/booster Internal data bus PDR read N-ch PDR read (for bit manipulation instructions) Output latch PDR write Pins DDR N-ch P26/V1/TO1 P27/V2/EC1 (Port direction register) DDR write DDR read Stop, watch mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) 345 CHAPTER 17 LCD CONTROLLER/DRIVER ■ LCD Controller/Driver Register Figure 17.3-8 LCD Controller/Driver Register LCR1 (LCD Control Register 1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 005EH CSS LCEN VSEL BK MS1 MS0 FP1 FP0 00010000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined value ■ LCD Controller/Driver RAM LCD controller/driver has 32 × 4-bit of internal display RAM in which the data used to generate the segment output signals is stored. 346 17.3.1 LCD Controller Register (LCR1) LCD Control Register 1 (LCR1) is used to select the frame cycle, enable/disable operation in watch mode, control the LCD drive supply voltage, select display blanking/ non-blanking, and select the display mode. ■ LCD Control Register 1 (LCR1) Figure 17.3-9 LCD Control Register 1 (LCR1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 005EH CSS LCEN VSEL BK MS1 MS0 FP1 FP0 00010000B R/W R/W R/W R/W R/W R/W R/W R/W Frame cycle Selection bits FP1 FP0 0 Main clock (CSS=0) Sub clock (CSS=1) 0 FCH/(2 × N) (763 Hz) FCL/(25 × N) (256 Hz) 0 1 FCH/(213 × N) (381 Hz) FCL/(26 × N) (128 Hz) 1 0 FCH/(2 × N) (190 Hz) FCL/(27 × N) (64 Hz) 1 1 FCH/(215 × N) (95 Hz) FCL/(28 × N) (32 Hz) () N FCH FCL : : : : 12 14 Values for FCH=12.5 MHz, FCL=32.768 kHz, and N=4 Number of time divisions Main clock source oscillation Sub clock source oscillation Display mode selection bits MS1 MS0 0 0 Stop LCD operation 0 1 1/2 duty ratio output mode (time division N = 2) 1 0 1/3 duty ratio output mode (time division N = 3) 1 1 1/4 duty ratio output mode (time division N = 4) Display blanking selection bit BK 0 Display unblanked 1 Display blanked Drive supply voltage control bit VSEL Internal divider resistor 0 External divider resistors used (internal divider resistors isolated) 1 Internal divider resistors used. Watch mode operation enable bit LCEN 0 Stop in watch mode 1 Run in watch mode CSS R/W : Readable/Writable : Initial value Frame cycle generate clock selection bit 0 Main clock 1 Sub clock 347 CHAPTER 17 LCD CONTROLLER/DRIVER Table 17.3-1 LCD Control Register (LCR1) Bit Functions Bit name Function bit7 CSS: Frame cycle generation clock selection bit Selects the frame clock, which generates the frame cycle for LCD display. "0" selects the output of the time-base timer derived from the main clock divided by 27; "1" selects the sub clock as the frame clock. Note: The time-base timer output may not be selected as the frame clock in the main-stop and sub clock modes because the main clock oscillator is stopped in those modes. Reference: When the time-base timer output is selected, the frame clock is not affected when clock speed is changed via the speed shift function. (The time-base timer’s count clock is not supplied through the speed shift function.) bit6 LCEN: Watch mode operation enable bit Determines whether the LCD controller/driver will operate in watch mode. If this bit is "1", the LCD display will continues to operate after the system goes to watch mode; if it is "0", the LCD will cease operation. To use the display in watch mode, the sub clock must be selected as the frame clock (CSS = 1). bit5 VSEL: LCD drive supply voltage control bit In devices that have an internal dividing resistor, the VSEL bit controls the divider current path continuity. A "1" in this bit completes the divider current path; a "0" opens it. This bit must be "0" when external dividing resistors are used. bit4 BK: Display blanking selection bit Blanks/unblanks the LCD. Setting this bit to "1" (blank) outputs a "deselect" waveform to the LCD segments (which blanks the display). MS1, MS0: bit3, Display mode bit2 selection bits Select one of three output waveform duty ratio modes. The mode selected affects the common pins used. Setting both bits to "0" turns "off" the display (stops LCD controller/driver display operation), P30/COM2 and P31/COM3 function as output only ports (P30 and P31) Setting to "01", 1/2 duty ratio is selected, P30/COM2 and P31/COM3 function as output only ports (P30 and P31). Setting to "10" P30/COM2 function as LCD common output pin (COM1) and P31/COM3 function as output only port. Setting to "11" P30/COM2 function as output only port and P31/COM3 function as LCD common output pin (COM3) Before going to a mode in which the selected frame cycle generate clock oscillator is stopped (stop mode, etc.), these bits should be written to "00B" to turn off the display. These bits select one of four LCD display frame cycles. FP1, FP0: bit1, To determine this register setting, calculate the optimum frame frequency for the LCD module Frame cycle selection bit0 you are using. Note that the frame cycle is a function of main clock frequency or sub clock bits frequency. 348 17.3.2 LCD Controller Register 2 (LCR2) LCD Control Register 2 (LCR2) is used to switch between segment and port. Select a function from general-purpose I/O port or segment output. ■ LCD Control Register 2 (LCR2) Figure 17.3-10 LCD Control Register 1 (LCR2) Address bit7 bit6 005FH RESV PSEL R/W bit5 bit4 bit3 bit2 bit1 bit0 SEG14 SEG13 SEG12 SEG11 SEG10 SEG00 R/W R/W R/W R/W R/W 00000000B R/W SEG00 Segment Output Selection bit 0 Select as ports (P54 to P56) 1 Select as segment output (SEG20 to SEG22) SEG10 Segment Output Selection bit 0 Select as ports (P50 to P53) 1 Select as segment output (SEG16 to SEG19) SEG11 Segment Output Selection bit 0 Select as ports (P44 to P47) 1 Select as segment output (SEG12 to SEG15) SEG12 Segment Output Selection bit 0 Select as ports (P40 to P43) 1 Select as segment output (SEG8 to SEG11) SEG13 Segment Output Selection bit 0 Select as ports (P14 to P17) 1 Select as segment output (SEG27 to SEG30) SEG14 Segment Output Selection bit 0 Select as ports (P10 to P13) 1 Select as segment output (SEG23 to SEG26) PSEL LCD Voltage Supply Selection bit 0 Select as LCD power supply pins (V1 and V2) 1 Select as port pins (P26, P27) RESV R/W : Readable/Writable — : Undefined value : Initial value Initial value Reserved bit Always write "0" to this bit 349 CHAPTER 17 LCD CONTROLLER/DRIVER Table 17.3-2 LCD Control Register (LCR2) Bit Functions Bit name Function bit7 RESV: Reserved bit bit6 PSEL Selecting P26/V1/TO1 to P27/V2/EC1 to function either as general purpose LCD Voltage Supply selection bit I/O ports (P26, P27) or as LCD power supply pin (V1 and V2). bit5 bit4 bit3 bit2 bit1 bit0 350 Always write "0" to this bit. SEG14: Segment Output Selection bit Selecting P10/SEG23/INT10 to P13/SEG26/INT13 to function either as general purpose I/O ports (P10 to P13) or as LCD segment output (SEG30 to SEG26). Note: When segment output is selected, the corresponding port data register bit (PDR1 bit 3 to 0) should be set to "1" to turn the output transistor off. SEG13: Segment Output Selection bit Selecting P14/SEG27/AN0 to P17/SEG30/AN3 to function either as generalpurpose I/O ports (P14 to P17) or as LCD segment output (SEG27 to SEG30). Note: When segment output is selected, the corresponding port data register bit (PDR1 bit 7 to 4) should be set to "1" to turn the output transistor off. Reference: If booster is selected, SEG13 no functions, P14 to P17 always become ports. SEG12: Segment Output Selection bit Selecting P40/SEG8 to P43/SEG11 to function either as general purpose I/O ports (P40 to P43) or as LCD segment output (SEG8 to SEG11). Note: When segment output is selected, the corresponding port data register bit (PDR3 bit 4 to 0) should be set to "1" to turn the output transistor off. SEG11: Segment Output Selection bit Selecting P44/SEG12 to P47/SEG15 to function either as general purpose I/O ports (P44 to P47) or as LCD segment output (SEG12 to SEG15). Note: When segment output is selected, the corresponding port data register bit (PDR7 bit 7 to 4) should be set to "1" to turn the output transistor off. SEG10: Segment Output Selection bit Selecting P50/SEG16 to P53/SEG19 to function either as general purpose I/O ports (P50 to P53) or as LCD segment output (SEG16 to SEG19). Note: When segment output is selected, the corresponding port data register bit (PDR1 bit3 to 0) should be set to "1" to turn the output transistor off. SEG00: Segment Output Selection bit Selecting P54/SEG20 to P56/SEG22 to function either a general purpose I/O ports (P54 to P56) or as LCD segment output (SEG20 to SEG22). Note: When segment output is selected, the corresponding port data register bit (PDR5 bit 6 to 4) should be set to "1" to turn the output transistor off. 17.3.3 Display RAM Display RAM consists of 32 × 4-bit (16 bytes) of display data memory used to generate the segment output signals. ■ Display RAM and Output Pins The contents of display RAM are automatically read out and output via the segment outputs in sync with the selected common signal timing. A "1" bit is converted to a "select" (display on) voltage and a "0" to a "deselect" (display off) voltage. Since the operation of the LCD is not directly related to the operation of the CPU, display RAM read/write timing can be set by the user. The SEG8 to SEG30 pins that are not dedicated segment outputs may be used as general-purpose I/O port pins, and the RAM that goes with those pins may be used as regular RAM. (See Table 17.3-3.) Table 17.3-4 shows the relationship between duty ratio mode, common outputs, and display RAM. Figure 17.3-11 shows which display RAM bits are associated with each segment and common output pin. Figure 17.3-11 Segment/Common Output Pins and Corresponding Display RAM Address bit3 bit2 bit1 bit0 SEG0 bit7 bit6 bit5 bit4 SEG1 bit3 bit2 bit1 bit0 SEG2 bit7 bit6 bit5 bit4 SEG3 bit3 bit2 bit1 bit0 SEG4 bit7 bit6 bit5 bit4 SEG5 bit3 bit2 bit1 bit0 SEG6 bit7 bit6 bit5 bit4 SEG7 bit3 bit2 bit1 bit0 SEG8 bit7 bit6 bit5 bit4 SEG9 bit3 bit2 bit1 bit0 SEG10 bit7 bit6 bit5 bit4 SEG11 bit3 bit2 bit1 bit0 SEG12 bit7 bit6 bit5 bit4 SEG13 bit3 bit2 bit1 bit0 SEG14 bit7 bit6 bit5 bit4 SEG15 bit3 bit2 bit1 bit0 SEG16 bit7 bit6 bit5 bit4 SEG17 bit3 bit2 bit1 bit0 SEG18 bit7 bit6 bit5 bit4 SEG19 bit3 bit2 bit1 bit0 SEG20 bit7 bit6 bit5 bit4 SEG21 bit3 bit2 bit1 bit0 SEG22 bit7 bit6 bit5 bit4 SEG23 bit3 bit2 bit1 bit0 SEG24 bit7 bit6 bit5 bit4 SEG25 bit3 bit2 bit1 bit0 SEG26 bit7 bit6 bit5 bit4 SEG27 bit3 bit2 bit1 bit0 SEG28 bit7 bit6 bit5 bit4 SEG29 bit3 bit2 bit1 bit0 SEG30 - - - - COM3 COM2 COM1 COM0 0060H 0061H 0062H 0063H 0064H 0065H Pins SEG8 to SEG15 share pins with Port 4 (P40 to P47). 0066H 0067H 0068H 0069H Pins SEG16 to SEG22 share pins with Port 5 (P50 to P56). 006AH 006BH 006CH 006DH Pins SEG23 to SEG30 share pins with Port 1 (P10 to P17). 006EH 006FH RAM area and common pins used in 1/2 duty ratio mode RAM area and common pins used in 1/3 duty ratio mode RAM area and common pins used in 1/4 duty ratio mode 351 CHAPTER 17 LCD CONTROLLER/DRIVER Table 17.3-3 Segment Outputs, Display RAM Area, and Sharing Port Pins Segment Output Pins Used Corresponding Display RAM Area General-Purpose Ports Sharing Same Pins SEG0 to SEG7 (8 pins) 60H to 63H None SEG0 to SEG11 (12 pins) 60H to 65H P40 to P43(4 pins) SEG0 to SEG15 (16 pins) 60H to 67H P40 to P47 (8 pins) SEG0 to SEG19 (20 pins) 60H to 69H P40 to P47, P50 to P53 (12 pins) SEG0 to SEG22 (23 pins) 60H to 6BH P40 to P47, P50 to P56 (15 pins) SEG0 to SEG26 (27 pins) 60H to 6DH P40 to P47, P50 to P56, P10 to P13 (19 pins) SEG0 to SEG30 (31 pins) 60H to 6FH P40 to P47, P50 to P56, P10 to P17 (23 pins) Reference: The area in the display RAM area that are not required for display data can be used as regular RAM. Table 17.3-4 Relationship Duty Ratio and Common Outputs and Display RAM Used Bits Display Data Bit Used Duty Ratio Setting Value Common Outputs Used 1/2 bit7 bit6 COM0, COM1 (2 pins) - - 1/3 COM0 to COM2 (3 pins) - 1/4 COM0 to COM3 (4 pins) bit5 bit4 bit3 bit2 - - bit1 - : Used - : Not used Notes: • COM3, COM2 pins, mask option, are selected by the operation of LCDC. • When 1/3 duty ratio is used, P30/COM2 will be set as common output pin. • When 1/4 duty ratio is used, P30/COM2 and P31/COM3 will be set as common output pins. 352 bit0 17.4 Operation of LCD Controller/Driver The LCD controller/driver provides the necessary control and drive for an LCD display. ■ Operation of LCD Controller/Driver Figure 17.4-1 shows the settings required to operate the LCD display Figure 17.4-1 LCD Controller/Driver Settings LCR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CSS LCEN VSEL BK MS1 MS0 FP1 FP0 0 Display RAM 060H to 06FH Other than “00H” Display data : Used bit 1 : Set "1". 0 : Set "0". • Once the above settings have been made, if the selected clock for frame cycle generation is running, LCD panel driving waveforms reflecting the contents of display RAM will be output at the segment and common output pins (COM0 to COM3 and SEG0 to SEG30). • Although the clock for frame period generation can be switched even while the LCD is displaying data, the display may flicker when the switching occurs. This can be avoided by temporarily blanking the display (LCR1: BK = 1), etc. while switching. • The display driving output is a two-frame a.c. waveform for which the bias level and display duty cycle is selected by settings. • When LCD display operation is stopped (LCR1: MS1 = MS0 = 00B), and during reset, only COM1, COM0 and SEG0 to SEG7 output pins will go to "L" level COM2/P30, COM3/P31 and SEG8/P40 to SEG30/P17 will be high impedance. Note: If the selected frame cycle generate clock were to stop while the LCD display is operating, the circuit that converts the waveform from d.c. to a.c. would also stop, causing a d.c. voltage to be applied to the liquid crystal cells. The LCD display must be therefore be stopped before the clock is stopped. The conditions under which the main clock (time-base timer) and sub clock are stopped are a function of the clock mode and standby mode. Also note that when the time-base timer is selected as the frame clock source (LCR1: CSS = 0), clearing the time-base timer will affect the frame cycle. Reference: See "APPENDIX E MB89480/480L Series Pin States". 353 CHAPTER 17 LCD CONTROLLER/DRIVER ■ LCD Driving Waveforms It is characteristic of LCDs that applying d.c. drive to the panel can cause electrochemical degradation of the material used in the LCD cells. For this reason, the LCD controller/driver includes a circuit to convert the original driving waveform to a two-frame a.c. output waveform (zero d.c. bias) to drive the LCD. There are three types of output waveform: • 1/2 bias, 1/2 duty ratio output waveform • 1/3 bias, 1/3 duty ratio output waveform • 1/3 bias, 1/4 duty ratio output waveform 354 17.4.1 Output Waveforms during LCD controller/Driver Operation (1/2 Duty Ratio) The display drive output is a multiplex drive-type two-frame a.c. waveform. In the 1/2 duty ratio mode, the only common outputs are COM0 and COM1. (P30/COM2 and P31/ COM3 function as output only ports) ■ 1/2 Bias, 1/2 Duty Output Waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is "turned on". Figure 17.4-2 shows the output waveforms for the display RAM contents listed in Table 17.4-1. Table 17.4-1 Display RAM Contents Example Display RAM contents Segment COM3 COM2 COM1 COM0 SEGn — — 0 0 SEG (n+1) — — 0 1 -: Not used 355 CHAPTER 17 LCD CONTROLLER/DRIVER Figure 17.4-2 Output Waveforms, 1/2 Bias and 1/2 Duty Ratio Example COM0 V3 V2=V1 VSS COM1 V3 V2=V1 VSS SEGn V3 V2=V1 VSs SEG (n+1) V3 V2=V1 VSS Difference in potential between COM0 and SEGn V3(ON) V2 VSS -V2 -V3(ON) V3(ON) V2 VSS -V2 -V3(ON) Difference in potential between COM1 and SEGn Difference in potential between COM0 and SEG (n+1) V3(ON) V2 VSS -V2 -V3(ON) Difference in potential between COM1 and SEG (n+1) V3(ON) V2 VSS -V2 -V3(ON) 1 frame 1 cycle V1 to V3: V1 to V3 pin voltages 356 ● LCD panel connections and display data example (1/2 duty ratio drive mode) Figure 17.4-3 Segment/Common Connections, Data States and Corresponding Display Example) Using segments to represent “5”. *0 SEGn COM1 *6 *7 SEGn+3 *1 *5 SEGn+1 *2 *3 *4 SEGn+2 COM0 Address COM3 COM2 COM1 COM0 nH (n+1)H bit3 bit7 bit3 bit7 bit2 bit6 bit2 bit6 bit1*1 bit5*3 bit1*5 bit5*7 bit0*0 bit4*2 bit0*4 bit4*6 *0 to *7: Indicate corresponding display RAM bits. (Bits 2, 3, 6, and Segment No. COM3 COM2 COM1 COM0 Address 1 0 –– –– SEG0 060H 1 1 –– –– SEG1 1 1 –– –– SEG2 061H 1 1 –– –– SEG3 0 0 –– –– SEG4 062H 0 0 –– –– SEG5 1 1 –– –– SEG6 063H 0 1 –– –– SEG7 0 1 –– –– SEG8 064H 1 1 –– –– SEG9 1 0 –– –– SEG10 065H 1 1 –– –– SEG11 Display RAM 7 are not used.) LCD Panel COM3 COM2 COM1 COM0 Address SEGn SEGn+1 SEGn+2 SEGn+3 060H 061H — — — — — — — — 1 1 1 0 1 0 0 1 SEG0 SEG1 SEG2 SEG3 0: OFF 1: ON LCD Display Bit States for Numerals “0” through “9” bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — — 1 1 — — 0 1 — — 1 1 — — 1 1 — — 0 0 — — 0 0 — — 1 0 — — 1 1 — — 1 1 — — 1 0 — — 1 1 — — 0 1 — — 1 0 — — 1 0 — — 1 1 — — 1 1 — — 0 0 — — 1 1 — — 1 0 — — 1 1 — — 1 0 — — 1 1 — — 0 1 — — 1 1 — — 1 1 — — 1 1 — — 0 1 — — 1 1 — — 0 0 — — 0 1 — — 1 1 — — 1 1 — — 1 1 — — 1 1 — — 1 1 — — 1 1 — — 1 0 — — 1 1 — — 1 1 — — 1 1 357 CHAPTER 17 LCD CONTROLLER/DRIVER 17.4.2 Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) In the 1/3 duty ratio mode, the COM0, COM1 and COM2 outputs are used by the display. (P31/COM3 function as output only port) ■ Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) ● 1/3 bias, 1/3 duty output waveform Table 17.4-2 Display RAM Contents Example Display RAM contents Segment COM3 COM2 COM1 COM0 SEGn — 1 0 0 SEG (n+1) — 1 0 1 -: Not used 358 Figure 17.4-4 Output Waveforms, 1/3 Bias and 1/3 Duty Ratio Example V3 V2 V1 VSS COM0 V3 V2 V1 VSS V3 V2 V1 VSS COM1 COM2 V3 V2 V1 V0=VSS V3 V2 V1 VSS V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) SEGn SEG (n+1) Difference in potential between COM0 and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in potential between COM0 and SEG (n+1) Difference in potential between COM1 and SEG (n+1) Difference in potential between COM2 and SEG (n+1) 1 frame V0 to V3: V0 to V3 pin voltages 1 cycle 359 CHAPTER 17 LCD CONTROLLER/DRIVER ● LCD panel connections and display data example (1/3 duty ratio drive mode) Figure 17.4-5 Segment/Common Connections, Data States and Corresponding Display Example) Using segments to represent “5”. COM0 *6 *3 *0 *4 *7 SEGn COM1 *1 COM2 *5 *8 SEGn+2 SEGn+1 Address 060H Address COM3 COM2 COM1 COM0 nH (n+1)H bit3 bit7 bit3 bit2*2 bit6*5 bit2*8 bit1*1 bit5*4 bit1*7 bit0*0 bit4*3 bit0*6 SEGn SEGn+1 SEGn+2 *0 to *8: Indicate corresponding display RAM bits. (Bits 3 and 7 and bit2 *2 are not used.) 061H 062H COM3 COM2 COM1 COM0 — — — — — — 0 1 0 0 1 0 064H SEG8 ÐÐ 1 0 1 063H 1 1 1 ÐÐ SEG7 SEG6 ÐÐ 0 1 0 062H 1 1 1 ÐÐ SEG5 SEG4 ÐÐ 0 0 0 061H 0 0 0 ÐÐ SEG3 1 1 1 ÐÐ SEG2 SEG1 ÐÐ 1 0 1 060H Address 1 1 0 ÐÐ SEG0 Segment No. COM3 COM2 COM1 COM0 Display RAM 1 1 0 1 1 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 0: OFF 1: ON LCD Display LCD Panel 0 1 1 0 1 1 Bit States for Numerals "0" through "9" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — 1 0 1 — 0 1 — 0 1 1 — 1 1 1 1 — 1 1 1 — 1 0 1 0 — 0 0 0 — 0 0 — 0 0 0 — 1 1 1 — 1 1 1 — 0 0 0 0 — 1 1 1 — 0 1 — 0 1 0 — 1 0 1 — 1 0 1 — 1 1 1 0 — 1 1 1 — 0 0 — 0 0 0 — 1 1 1 — 1 1 1 — 1 1 1 1 — 0 1 0 — 0 0 — 0 0 1 — 1 1 1 — 1 1 1 — 0 1 0 1 — 1 1 1 — 0 0 — 0 0 1 — 1 1 0 — 1 1 0 — 1 1 1 1 — 1 1 1 — 0 1 — 0 1 1 — 1 1 0 — 1 1 0 — 1 1 1 1 — 0 0 1 — 0 0 — 0 0 1 — 1 1 1 — 1 1 1 — 0 0 1 1 — 1 1 1 — 0 1 — 0 1 1 — 1 1 1 — 1 1 1 — 1 1 1 1 — 1 1 1 — 0 0 — 0 0 1 — 1 1 1 — 1 1 1 — 1 1 1 :Data in unit starting at bit 4 :Data in unit starting at bit 0 In 1/3 duty ratio operation, to be able to define two digits in three bytes, the data stored in two bytes, with the first byte starting at bit 0, and second byte starting at bit 4. 360 17.4.3 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) In the 1/4 duty ratio mode, all four common outputs, COM0, COM1, COM2, and COM3 are used. ■ Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) ● 1/3 bias, 1/4 duty output waveforms The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is "turned on". Figure 17.4-6 shows the output waveforms for the display RAM contents listed in Table 17.4-3. Table 17.4-3 Display RAM Contents Example Display RAM contents Segment COM3 COM2 COM1 COM0 SEGn 0 1 0 0 SEG (n+1) 0 1 0 1 361 CHAPTER 17 LCD CONTROLLER/DRIVER Figure 17.4-6 Output Waveforms, 1/3 Bias and 1/4 Duty Ratio V3 V2 V1 VSS V3 V2 V1 VSS V3 V2 V1 VSS V3 V3 V3 VSS V3 V2 V1 VSS V3 V2 V1 VSS V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) V3(ON) V2 V1 VSS -V1 -V2 -V3(ON) COM0 COM1 COM2 COM3 SEGn SEG (n+1) Difference in potential between COM0 and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in potential between COM3 and SEGn Difference in potential between COM0 and SEG (n+1) Difference in potential between COM1 and SEG (n+1) Difference in potential between COM2 and SEG (n+1) Difference in potential between COM3 and SEG (n+1) 1 frame 1 cycle V1 to V3: V1 to V3 pin voltages 362 ● 8-segment LCD panel connections and Display data (1/4 duty ratio drive mode) Figure 17.4-7 Segment/Common Connections, Data States and Corresponding Display Example) Using segments to represent “5”. COM0 COM3 *4 *0 SEGn COM1 *5 *1 *2 Address COM3 COM2 COM1 COM0 bit3*3 bit7*7 bit2*2 bit6*6 bit1*1 bit5*5 bit0*0 bit4*4 SEGn SEGn+1 Address COM3 COM2 COM1 COM0 060H 1 1 0 1 SEG0 0 0 1 1 SEG1 063H LCD Display Bit States for Numerals "0" through "9" 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 1 1 1 1 0 0 SEG7 SEG6 1 1 0 0 062H 1 1 1 1 SEG5 SEG4 0 1 1 0 061H 0 0 1 1 SEG3 0 0 0 1 SEG2 SEG1 1 1 0 1 060H Address 1 1 1 1 SEG0 Segment No. COM3 COM2 COM1 COM0 Display RAM *6 0: OFF 1: ON *0 to *7: Indicate corresponding display RAM bits. LCD Panel *3 SEGn+1 COM2 nH *7 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 363 CHAPTER 17 LCD CONTROLLER/DRIVER 17.5 Program Example for LCD Controller/Driver The section gives a program example for LCD controller/driver. ■ Program example for LCD Controller/Driver ● Processing description The process writes LCD display data to display RAM. The data is that required to display the numbers "0" through "9" in an LCD panel connected as shown in Figure 17.4-7. The settings are as follows: • Internal voltage divider resistors are selected in a device with no voltage booster • (LCR1: VSEL = 1) • 1/3 bias and 1/4 duty ratio are used. • The sub clock (LCR1: CSS = 1) is selected as the clock for frame cycle generation. • The frame frequency is set at 32 Hz (LCR1: FP1, FP0 = 11B) • Operation is stopped in watch mode. ● Coding example LCRAM EQU 0060H ;Starting address of LCD display RAM LCR1 EQU 005EH ; Address of LCD control register 1 (LCR1) LCDSEG CSEG ; 8-segment LCD display data LCDDATA DB 11011111B ;"0" DB 11001000B ;"1" DB 11110110B ;"2" DB 11111100B ;"3" DB 11101001B ;"4" DB 01111101B ;"5" DB 01111111B ;"6" DB 11011001B ;"7" DB 11111111B ;"8" DB 11111101B ;"9" DB 00000000B ;END LCDSEG ENDS ;----------Main program---------------------------------------------------------------------------------------------------CSEG ; [CODE SEGMENT] : LCDSET 364 MOVW EP,#LCRAM ; Set LCD display RAM address. MOVW IX,#LCDDATA ; Set LCD display data table address. MOV A,@IX+00H MOV @EP,A INCW EP INCW IX BNZ LCDSET MOV LCR1,#10101111B ; Set LCR1 and turn LCD display on. ; Continue until data end (00H) is detected. : ENDS ;-------------------------------------------------------------------------------------------------------------------------------END 365 CHAPTER 17 LCD CONTROLLER/DRIVER 366 APPENDIX The appendices provide I/O map, instruction list and other information. APPENDIX A I/O MAP APPENDIX B Instructions B.1 Addressing B.2 Special Instructions B.3 F2MC-8L Instructions B.4 Instruction Map B.5 Bit Manipulation Instructions (SETB, CLRB) APPENDIX C Mask Options APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers D.1 Programming One-time PROM Microcontroller with serial programmer D.2 Programming One-time PROM Microcontroller parallel programmer D.3 Programming EPROM for Piggyback/Evaluation Device APPENDIX E MB89480/480L Series Pin States 367 APPENDIX A I/O MAP APPENDIX A I/O MAP Table A-1 lists the addresses of the registers used by the internal peripheral functions of the MB89480/480L series. ■ I/O map Table A-1 I/O Map (1 / 3) Address Register name Register Description Read/Write Initial value 00H PDR0 Port 0 data register R/W XXXXXXXXB 01H DDR0 Port 0 data direction register W* 00000000B 02H PDR1 Port 1 data register R/W XXXXXXXXB 03H DDR1 Port 1 data direction register W* 00000000B 04H PDR2 Port 2 data register R/W 00000000B 05H (Reserved) 06H DDR2 Port 2 data direction register R/W 00000000B 07H SYCC System clock control register R/W X-1MM100B 08H STBC Standby control register R/W 00010XXXB 09H WDTC Watchdog timer control register W* 0---XXXXB 0AH TBTC Time-base timer control register R/W 00---000B 0BH WPCR Watch prescaler control register R/W 00--0000B 0CH PDR3 Port 3 data register R/W ------11B R XXXX----B R/W 11111111B R/W X1111111B 0DH 0EH (Reserved) RSFR Reset flag register 0FH 10H (Reserved) PDR4 Port 4 data register 11H 12H (Reserved) PDR5 Port 5 data register 13H (Reserved) 14H to 1FH (Reserved) 20H SMC1 UART/SIO mode control register 1 R/W 00000000B 21H SMC2 UART/SIO mode control register 2 R/W 00000000B 22H SRC UART/SIO rate control register R/W XXXXXXXXB 368 Table A-1 I/O Map (2 / 3) Address Register name Register Description Read/Write Initial value 23H SSD UART/SIO status/data register R 00001---B 24H SIDR/SODR UART/SIO data register R/W XXXXXXXXB 25H EIC1 External interrupt control register 1 R/W 00000000B 26H EIC2 External interrupt control register 2 R/W 00000000B 27H EIE2 External interrupt 2 enable register R/W 00000000B 28H EIF2 External interrupt 2 flag register R/W -------0B 29H to 2BH (Reserved) 2CH ADC1 A/D control register 1 R/W -0000000B 2DH ADC2 A/D control register 2 R/W -0000001B 2EH ADDH A/D data register (Upper byte) R ------XXB 2FH ADDL A/D data register (Lower byte) R XXXXXXXXB 30H ADEN A/D input enable register R/W 1111----B 31H PCR1 PWC control register 1 R/W 0-0--000B 32H PCR2 PWC control register 2 R/W 00000000B 33H PLBR PWC reload buffer register R/W XXXXXXXXB 34H CNTR PWM timer control register R/W 0-000000B 35H COMR PWM timer compare register W* XXXXXXXXB 36H T22CR Timer 22 control register R/W 000000X0B 37H T21CR Timer 21 control register R/W 000000X0B 38H T22DR Timer 22 data register R/W XXXXXXXXB 39H T21DR Timer 21 data register R/W XXXXXXXXB 3AH T12CR Timer 12 control register R/W 000000X0B 3BH T11CR Timer 11 control register R/W 000000X0B 3CH T12DR Timer 12 data register R/W XXXXXXXXB 3DH T11DR Timer 11 data register R/W XXXXXXXXB 3EH PPGC1 PPG control register 1 R/W 00000000B 3FH PPGC2 PPG control register 2 R/W 0-000000B 40H BUZR Buzzer control register R/W -----000B 41H to 5DH (Reserved) 5EH LCR1 LCD control register 1 R/W 00010000B 5FH LCR2 LCD control register 2 R/W -0000000B 369 APPENDIX A I/O MAP Table A-1 I/O Map (3 / 3) Address Register name Register Description Read/Write Initial value 60H to 6FH VRAM LCD data RAM R/W XXXXXXXXB 70H PURC0 Port 0 pull up resistor control register R/W 11111111B R/W ----1111B 71H (Reserved) PURC2 72H Port 2 pull up resistor control register 73H to 76H (Reserved) 77H (Reserved) 78H (Reserved) 79H (Reserved) 7AH (Reserved) 7BH ILR1 Interrupt level setting register 1 W* 11111111B 7CH ILR2 Interrupt level setting register 2 W* 11111111B 7DH ILR3 Interrupt level setting register 3 W* 11111111B 7EH ILR4 Interrupt level setting register 4 W* 11111111B 7FH (Reserved) * : Bit manipulation instruction cannot be used. ● Read/write access symbols R/W: Readable/writable R: Read only W: Write only ● Initial value symbols 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. -: Undefined bit. M: The initial value of this bit is determined by mask option. Note: Do not use vacancies. 370 APPENDIX B Instructions This appendix describes the F2MC-8L instruction set. ■ Instruction List Symbols Table B-1 lists the meaning of the symbols and Table B-2 lists the meanings of the columns used in "B.3 F2MC-8L Instructions". Table B-1 Instruction List Symbols (1 / 2) Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of the accumulator A (8 bits) AL Lower 8 bits of the accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of the temporary accumulator T (8 bits) TL Lower 8 bits of the temporary accumulator T (8 bits) IX Index register IX (16 bits) EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) 371 APPENDIX B Instructions Table B-1 Instruction List Symbols (2 / 2) Symbol Meaning Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (× ) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ((× )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) ■ Instruction List Columns Table B-2 Instruction List Columns Column Description Mnemonic Assembler notation of an instruction ~ Number of instructions # Number of bytes Operation Operation of an instruction TL, TH, AH A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • "—" indicate no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP Code Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ←This indicates 48, 49 ... 4F. 372 B.1 Addressing The F2MC-8L supports the following ten addressing modes; • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing • Relative addressing • Inherent addressing ■ Addressing Modes ● Direct addressing Indicated by "dir" in the instruction list. Used to access the area between "0000H" and "00FFH". For direct addressing, the upper one byte of the address is "00H" and the operand specifies the lower one byte. Figure B.1-1 shows an example Figure B.1-1 Direct Addressing MOV 1 2H, A 0 0 1 2H 4 5H A 4 5H ● Extended addressing Indicated by "ext" in the instruction list. Used to access the entire 64-Kbyte area. For extended addressing, the first operand specifies the upper one byte of the address and the second operand specifies the lower one byte. Figure B.1-2 shows an example. Figure B.1-2 Extended Addressing MOVW A, 1 2 3 4H 1 2 3 4H 5 6H 1 2 3 5H 7 8H A 5 6 7 8H 373 APPENDIX B Instructions ● Bit direct addressing Indicated by "dir: b" in the instruction list. Used to access the area between "0000H" and "00FFH" in bit units. For bit direct addressing, the upper one byte of the address is "00H", the operand specifies the lower one byte of the address, and the lower three bits of the operation code specify the bit position. Figure B.1-3 shows an example. Figure B.1-3 Bit Direct Addressing SETB 3 4H : 2 76543210 0034H XXXXX1XXB ● Index addressing Indicated by "@IX+off" in the instruction list. Used to access the entire 64-Kbyte area. Index addressing generates the address is obtained by adding the sign-extended contents of the first operand to the index register (IX). Figure B.1-4 shows an example. Figure B.1-4 Index Addressing MOVW A, @IX+5 AH IX 2 7 A 5H + 2 7 F FH 2 8 0 0H 1 2H 3 4H A 1 2 3 4H ● Pointer addressing Indicated by "@EP" in the instruction list. Used to access the entire 64-Kbyte area. Pointer addressing uses the extra pointer (EP) the address. Figure B.1-5 shows an example. Figure B.1-5 Pointer Addressing MOVW A, @EP EP 2 7 A 5H 2 7 A 5H 1 2H 2 7 A 6H 3 4H A 1 2 3 4H ● General-purpose register addressing Indicated by "Ri" in the instruction list. Used to access the general-purpose register area register bank. For general-purpose register addressing, the upper one byte of the address is fixed at "01" and the lower byte is generated from the register bank pointer (RP) and the lower three bits of the operation code. The CPU accesses the resulting address. Figure B.1-6 shows an example. Figure B.1-6 General-purpose Register Addressing MOV A, R6 RP 0 1 0 1 0B 374 + 0 1 5 6H A BH A A BH ● Immediate addressing Indicated by "#d8" in the instruction list. Used when immediate data is required. In immediate addressing, the operand is used directly as immediate data. The operation code determines whether the data is byte or word. Figure B.1-7 shows an example. Figure B.1-7 Immediate Addressing MOV A, #5 6H A 5 6H ● Vector addressing Indicated by "vct" in the instruction list. Used to branch to a subroutine address stored in the vector table. For vector addressing, the "vct" data is contained in the operation code. Table B.1-1 lists the correspondence between "vct" and the resulting address. Table B.1-1 Vector Table Address Corresponding to "vct" #vct Vector table address (branch destination upper address: lower address) 0 FFC0H : FFC1H 1 FFC2H : FFC3H 2 FFC4H : FFC5H 3 FFC6H : FFC7H 4 FFC8H : FFC9H 5 FFCAH : FFCBH 6 FFCCH : FFCDH 7 FFCEH : FFCFH Figure B.1-8 shows an example. Figure B.1-8 Vector Addressing CALLV #5 (Conversion) F F C AH F EH F F C B H D CH PC F E D CH 375 APPENDIX B Instructions ● Relative addressing Indicated by "rel" in the instruction list. Used to branch to a destination in the area 128 bytes above or below the program counter (PC). Relative addressing adds the sign-extended contents of the first operand to the PC and stores the result in the PC. Figure B.1-9 shows an example. Figure B.1-9 Relative Addressing BNE F EH Old PC 9 A B CH + 9ABCH + FFFEH New PC 9 A B AH This example branches to the address containing the BNE operation code and therefore results in an endless loop. ● Inherent addressing Inherent addressing is used for instructions in the instruction list that do not have operands and for which the operation code determines the operation. The operation of inherent addressing depends on the instruction. Figure B.1-10 shows an example. Figure B.1-10 Inherent Addressing NOP Old PC 9 A B CH 376 New PC 9 A B DH B.2 Special Instructions This section describes special instructions, other than addressing. ■ Special Instructions ● JMP @A This instruction moves the address contained in the accumulator (A) to the program counter (PC) and branches to the new address. This instruction can be used to perform an N option branch by placing N branch destination addresses in a table and moving the desired address to the accumulator. Figure B.2-1 shows an outline of the instruction operation Figure B.2-1 JMP @A (Before execution) A (After execution) 1 2 3 4H Old PC X X X XH A 1 2 3 4H New PC 1 2 3 4H ● MOVW A,PC This instruction stores the PC contents in the accumulator A. This performs the opposite operation to "JMP @A". By executing this instruction in the main routine and calling a particular subroutine, the subroutine can determine whether the contents of A match a predetermined value. The subroutine can check whether program runaway has occurred by checking whether or not execution has branched from an expected location. Figure B.2-2 shows an outline of the instruction operation Figure B.2-2 MOVW A,PC (Before execution) A Old PC X X X XH 1 2 3 3H (After execution) A 1 2 3 4H New PC 1 2 3 4H The content of A after executing this instruction is the address of the next instruction (not the address containing the operation code of this instruction. Accordingly, the value "1234H" stored in A in the example shown in Figure B.2-2 is the address of the next operation code after "MOVW A, PC". 377 APPENDIX B Instructions ● MULU A This instruction performs an unsigned multiplication of AL (lower 8 bits of the accumulator) and TL (lower 8 bits of the temporary accumulator) and stores the 16-bit result in A. The contents of T (temporary accumulator) does not change. The arithmetic operation does not use the pre-execution contents of AH (upper 8 bits of the accumulator) and TH (upper 8 bits of the temporary accumulator). Since the flags remain unchanged, use care when branching is required based on the result of multiplication. Figure B.2-3 shows an outline of the instruction operation. Figure B.2-3 MULU A (Before execution) (After execution) A 5 6 7 8H A 1 8 6 0H T 1 2 3 4H T 1 2 3 4H ● DIVU A This instruction divides the 16 bits of T by the 8 bits of AL, treating the data as unsigned. The instruction stores the result in AL and the remainder in TL, both as 8 bit data. AH and TH are both set to "zero". The arithmetic operation does not use the value of AH prior to instruction execution. The result is not assured for data that produces a result that exceeds 8 bits. As there is no indication that the result exceeded 8 bits, check the data before performing. Since the flags remain unchanged, use care when branching is required based on the result of the division. Figure B.2-4 shows an outline of the instruction operation Figure B.2-4 DIVU A (Before execution) 378 (After execution) A 5 6 7 8H A 0 0 3 4H T 1 8 6 2H T 0 0 0 2H ● XCHW A,PC This instruction exchanges the contents of A and PC, and as a result branches to the address corresponding to contents of A before execution. The contents of A after execution assume the address next to the address where the operation code of the “XCHW A,PC” is stored. The instruction can be used to specify a table in the main routine which is used in a subroutine. Figure B.2e shows an outline of the instruction operation. Figure B.2-5 XCHW A,PC (Before execution) (After execution) A 5 6 7 8H A 1 2 3 5H PC 1 2 3 4H PC 5 6 7 8H The content of A after executing this instruction is the address of the next instruction (not the address containing the operation code of this instruction). Accordingly, the value "1235H" stored in A in the example shown in Figure B.2-6 is the address of the next operation code after "XCHW A,PC". Therefore, the value of A is "1235H", not "1234H". Figure B.2-6 shows an assembly language example. Figure B.2-6 Example Using XCHW A, PC (Main routine) • • • MOVW A, #PUTSUB XCHW A, PC DB ‘PUT OUT DATA’,EOL MOVW A, 1234H • • • (Subroutine) PUTSUB PTS1 XCHW A, EP PUSHW A MOV A, @EP INCW EP MOV IO, A CMP A, #EOL BNE PTS1 POPW A XCHW A, EP Table data output here. 379 APPENDIX B Instructions ● CALLV #vct This instruction is used to branch to a subroutine address in the vector table. The instruction saves the return address (contents of the PC) to the address corresponding to the SP (stack pointer) branches to the address stored in the vector table using vector addressing. As "CALLV #vct" is a single-byte instruction, using this instruction for commonly used subroutines reduces the overall program size. Figure B.2-7 shows an outline of the instruction operation. Figure B.2-7 Execution example of CALLV VCT (Before execution) (After execution) PC 5 6 7 8H PC F E D CH SP 1 2 3 4H SP 1 2 3 2H (-2) 1 2 3 2H X XH 1 2 3 2H 5 6H 1 2 3 3H X XH 1 2 3 3H 7 9H F F C 6 H F EH F F C 6H F EH F F C 7H D C H F F C 7H D CH The content of PC saved to stack area after executing this instruction is the address of next instruction (not the address containing the operation code of this instruction). Accordingly, the value "5679H" saved to stack (1232H, 1233H) in the example shown in Figure B.2-7 is the address (return address) of the next operation code after "MOVW A,PC". 380 B.3 F2MC-8L Instructions Table B.3-1 to Table B.3-4 list the F2MC-8L instructions. ■ Transfer Instructions Table B.3-1 Transfer Instructions (1 / 2) No. Mnemonic ~ # Operation TL TH AH 1 2 3 4 5 MOV MOV MOV MOV MOV dir, A @IX+off, A ext, A @EP, A Ri, A 3 4 4 3 3 2 2 3 1 1 (dir) ← (A) ((IX)+off)← (A) (ext) ← (A) ((EP)) ← (A) (Ri) ← (A) — — — — — — — — — — — — — — — 6 7 8 9 10 MOV MOV MOV MOV MOV A, #d8 A, dir A, @IX+off A, ext A, @A 2 3 4 4 3 2 2 2 3 1 (A) ← d8 (A) ← (dir) (A) ← ((IX)+off) (A) ← (ext) (A) ← ((A)) AL AL AL AL AL — — — — — 11 12 13 14 15 MOV MOV MOV MOV MOV A, @EP A, Ri dir, #d8 @IX+off,#d8 @EP, #d8 3 3 4 5 4 1 1 3 3 2 (A) ← ((EP)) (A) ← (Ri) (dir) ← d8 ((IX)+off) ← d8 ((EP)) ← d8 AL AL — — — 16 17 18 19 20 MOV Ri, #d8 MOVW dir, A MOVW @IX+off, A MOVW ext, A MOVW @EP, A 4 4 5 5 4 2 2 2 3 1 (Ri) ← d8 (dir) ← (AH), (dir+1) ← (AL) ((IX)+off) ← (AH), ((IX)+off+1) ← (AL) (ext) ← (AH), (ext+1) ← (AL) ((EP)) ← (AH), ((EP)+1) ← (AL) 21 22 23 24 25 MOVW MOVW MOVW MOVW MOVW EP, A A, #d16 A, dir A, @IX+off A, ext 2 3 4 5 5 1 3 2 2 3 26 27 28 29 30 MOVW MOVW MOVW MOVW MOVW A, @A A, @EP A, EP EP, #d16 IX, A 4 4 2 3 2 1 1 1 3 1 NZVC OP code — — — — 45 46 61 47 48 to 4F — — — — — ++—— ++—— ++—— ++—— ++—— 04 05 06 60 92 — — — — — — — — — — ++—— ++—— 07 08 to 0F 85 86 87 — — — — — — — — — — — — — — — (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir+1) (AH) ← ((IX)+off), (AL) ← ((IX)+off+1) (AH) ← (ext), (AL) ← (ext+1) — AL AL AL AL — AH AH AH AH — dH dH dH dH (AH) ← ((A)),(AL) ← ((A)+1) AL AL — — — AH AH — — — dH dH dH — — (AH) ← ((EP)), (AL) ← ((EP)+1) (A) ← (EP) (EP) ← d16 (IX )← (A) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —— — — ++—— ++—— ++—— ++—— ++—— ++—— — — — — — — — — — — — — 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 381 APPENDIX B Instructions Table B.3-1 Transfer Instructions (2 / 2) No. Mnemonic ~ # Operation TL TH AH 31 32 33 34 35 MOVW A, IX MOVW SP, A MOVW A, SP MOV @A, T MOVW @A, T 2 2 2 3 4 1 1 1 1 1 (A) ← (IX) (SP) ← (A) (A) ← (SP) ((A)) ← (T) ((A)) ← (TH), ((A)+1) ← (TL) — — — — — — — — — — dH — dH — — 36 37 38 39 40 MOVW MOVW MOVW MOVW SWAP 3 2 2 3 2 3 1 1 3 1 (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ←→(AL) — — — — — — — — — — — dH — — AL 41 42 43 44 45 SETB dir:b CLRB dir:b XCH A, T XCHW A, T XCHW A, EP 4 4 2 3 3 2 2 1 1 1 (dir):b ← 1 (dir):b ← 0 (AL) ←→(TL) (A) ←→(T) (A) ←→(EP) — — AL AL — — — — AH — — — — dH dH 46 47 48 XCHW A, IX XCHW A, SP MOVW A, PC 3 3 2 1 1 1 (A) ←→(IX) (A )←→(SP) (A) ← (PC) — — — — — — dH dH dH IX, #d16 A, PS PS, A SP, #d16 NZVC — — — — — — — — — — — — — — — — — — — — — — — — — — — — ++++ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — OP code F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • The automatic transfer to the T register is TL←AL for instructions that perform a byte transfer to A. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. 382 ■ Arithmetic Operation Instructions Table B.3-2 Arithmetic Operation Instructions (1 / 2) No. Mnemonic ~ # 3 2 3 4 3 1 2 2 2 1 Operation TL TH AH NZVC OP code (A) ← (A)+(Ri)+C (A) ← (A)+d8+C (A) ← (A)+(dir)+C (A) ← (A)+((IX)+off)+C (A) ← (A)+((EP))+C — — — — — — — — — — — — — — — ++++ ++++ ++++ ++++ ++++ 28 to 2F 24 25 26 27 1 2 3 4 5 ADDC ADDC ADDC ADDC ADDC 6 7 8 9 10 ADDCW A ADDC A SUBC A, Ri SUBC A, #d8 SUBC A, dir 3 2 3 2 3 1 1 1 2 2 (A) ← (A)+(T)+C (AL) ← (AL)+(TL)+C (A) ← (A)-(Ri)-C (A) ← (A)-d8-C (A) ← (A)-(dir)-C — — — — — — — — — — dH — — — — ++++ ++++ ++++ ++++ ++++ 23 22 38 to 3F 34 35 11 12 13 14 15 SUBC A, @IX+off SUBC A, @EP SUBCW A SUBC A INC Ri 4 3 3 2 4 2 1 1 1 1 (A) ← (A)-((IX)+off)-C (A) ← (A)-((EP))-C (A) ← (T)-(A)-C (AL) ← (TL)-(AL)-C (Ri) ← (Ri)+1 — — — — — — — — — — — — dH — — ++++ ++++ ++++ ++++ +++— 36 37 33 32 C8 to CF 16 17 18 19 20 INCW EP INCW IX INCW A DEC Ri DECW EP 3 3 3 4 3 1 1 1 1 1 (EP) ← (EP)+1 (IX) ← (IX)+1 (A) ← (A)+1 (Ri) ← (Ri)-1 (EP) ← (EP)-1 — — — — — — — — — — — — dH — — 21 22 23 24 25 DECW IX DECW A MULU A DIVU A ANDW A 3 3 1 9 2 1 3 1 1 1 1 1 (IX) ← (IX)-1 (A) ← (A)-1 (A) ← (AL)*(TL) (A) ← (T)/(AL), MOD →(T) (A) ← (A) ∧ (T) — — — dL — — — — 00 — — dH dH 00 dH 26 27 28 29 30 ORW A XORW A CMP A CMPW A RORC A 3 3 2 3 2 1 1 1 1 1 (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL)-(AL)(T)-(A) — — — — — — — — — — 31 ROLC A 2 1 — 32 33 34 35 CMP CMP CMP CMP 2 3 3 4 2 2 1 2 (A)-d8 (A)-(dir) (A)-((EP)) (A)-((IX)+off) 36 37 38 39 40 CMP A, Ri DAA DAS XOR A XOR A, #d8 3 2 2 2 2 1 1 1 1 2 (A)-(Ri) decimal adjust for addition decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 A, Ri A, #d8 A, dir A, @IX+off A, @EP A, #d8 A, dir A, @EP A, @IX+off →C →A C ←A← — — — — — — — — ++—— +++— — — — — C3 C2 C0 D8 to DF D3 ++R— D2 D0 01 11 63 dH dH — — — ++R— ++R— ++++ ++++ ++—+ 73 53 12 13 03 — — ++ + 02 — — — — — — — — — — — — ++++ ++++ ++++ ++++ 14 15 17 16 — — — — — — — — — — — — — — — ++++ ++++ ++++ ++R— ++R— 18 to 1F 84 94 52 54 —— — — ++—— ——— — ——— — — 383 APPENDIX B Instructions Table B.3-2 Arithmetic Operation Instructions (2 / 2) No. Mnemonic ~ # Operation TL TH AH NZVC OP code 41 42 43 44 45 XOR XOR XOR XOR AND A, dir A, @EP A, @IX+off A, Ri A 3 3 4 3 2 2 1 2 1 1 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ((EP)) (A) ← (AL) ∀ ((IX)+off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) — — — — — — — — — — — — — — — ++R— ++R— ++R— ++R— ++R— 55 57 56 58 to 5F 62 46 47 48 49 50 AND AND AND AND AND A, #d8 A, dir A, @EP A, @IX+off A, Ri 2 3 3 4 3 2 2 1 2 1 (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (A) ← (AL) ∧ ((EP)) (A) ← (AL) ∧ ((IX)+off) (A) ← (AL) ∧ (Ri) — — — — — — — — — — — — — — — ++R— ++R— ++R— ++R— ++R— 64 65 67 66 68 to 6F 51 52 53 54 55 OR OR OR OR OR A A, #d8 A, dir A, @EP A, @IX+off 2 2 3 3 4 1 2 2 1 2 (A) ← (AL) ∨ (A) ← (AL) ∨ (A) ← (AL) ∨ (A) ← (AL) ∨ (A) ← (AL) ∨ — — — — — — — — — — — — — — — ++R— ++R— ++R— ++R— ++R— 72 74 75 77 76 56 57 58 59 60 OR A, Ri CMP dir, #d8 CMP @EP, #d8 CMP @IX+off, #d8 CMP Ri, #d8 3 5 4 5 4 1 3 2 3 2 (A )← (AL) ∨ (Ri) (dir)-d8 ((EP))-d8 ((IX)+off)-d8 (Ri)-d8 — — — — — — — — — — — — — — — ++R— ++++ ++++ ++++ ++++ 78 to 7F 95 97 96 98 to 9F 61 62 INCW SP DECW SP 3 3 1 1 (SP) ← (SP)+1 (SP) ← (SP)-1 — — — — — — 384 (TL) d8 (dir) ((EP)) ((IX)+off) — — — — — — — — C1 D1 ■ Branch Instructions Table B.3-3 Branch Instructions No . Mnemonic ~ # Operation TL TH AH 1 2 3 4 5 BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel 3 3 3 3 3 2 2 2 2 2 if Z=1 then PC ← PC+rel if Z=0 then PC ← PC+rel if C=1 then PC ← PC+rel if C=0 then PC ← PC+rel if N=1 then PC ← PC+rel — — — — — — — — — — — — — — — 6 7 8 9 10 BP rel BLT rel BGE rel BBC dir:b, rel BBS dir:b, rel 3 3 3 5 5 2 2 2 3 3 if N=0 then PC ← PC+rel if V ∀ N=1 then PC ← PC+rel if V ∀ N=0 then PC ← PC+rel if (dir:b)=0 then PC ← PC+rel if (dir:b)=1 then PC ← PC+rel — — — — — — — — — — — — — — — 11 12 13 14 15 JMP @A JMP ext CALLV #vct CALL ext XCHW A, PC 2 3 6 6 3 1 3 1 3 1 (PC) ← (A) (PC) ← ext vector call subroutine call (PC) ← (A), (A) ← (PC)+1 — — — — — — — — — — — — — — dH 16 17 RET RETI 4 6 1 1 return from subroutine return form interrupt – — — — — — TL TH AH NZVC — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — +—— +—— — — — — — — — — — — — — — — — — — — — — — — — — restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 ■ Other Instructions Table B.3-4 Other Instructions No . Mnemonic ~ # Operation 1 2 3 4 5 PUSHW A POPW A PUSHW IX POPW IX NOP 4 4 4 4 1 1 1 1 1 1 ((SP))<-(A),(SP)<-(SP)-2 (A)<-((SP)),(SP)<-(SP)+2 ((SP))<-(IX),(SP)<-(SP)-2 (IX)<-((SP)),(SP)<-(SP)+2 No operation — — — — – — — — — — — dH — — — 6 7 8 9 CLRC SETC CLRI SETI 1 1 1 1 1 1 1 1 (C)<-0 (C)<-1 (I)<-0 (I)<-1 — — — — — — — — — — — — NZVC — — — — — — — — — — — — — — — — — — — — — — — — — — R S — — — — — — — — OP code 40 50 41 51 00 81 91 80 90 385 L 386 F E D C B A 9 8 7 6 5 4 3 2 A A A A A A A A @A, T @A, T A, @A A, @A MOV MOV MOV MOV MOV MOV MOV A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP MOV CMP CMP CMP CMP CMP CMP CMP A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP CMP A, @EP A, R7 ADDC A, R6 ADDC A, R5 ADDC A, R4 ADDC A, R3 ADDC A, R2 ADDC A, R1 ADDC A, R0 ADDC SUBC SUBC SUBC SUBC SUBC SUBC SUBC A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP SUBC MOV MOV MOV MOV MOV MOV MOV R7, A R6, A R5, A R4, A R3, A R2, A R1, A R0, A @EP, A MOV XOR XOR XOR XOR XOR XOR XOR A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP XOR AND AND AND AND AND AND AND A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP AND OR OR OR OR OR OR OR OR CMP A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 R7, #d8 MOV R6, #d8 MOV R5, #d8 MOV R4, #d8 MOV R3, #d8 MOV R2, #d8 MOV R1, #d8 MOV R0, #d8 MOV R7, #d8 CMP R6, #d8 CMP R5, #d8 CMP R4, #d8 CMP R3, #d8 CMP R2, #d8 CMP R1, #d8 CMP R0, #d8 CMP A, @EP @EP#, d8 @EP#, d8 MOV A, @IX+d @IX+d,#d8 @IX+d,#d8 OR A, @IX+d AND A, @IX+d XOR @IX+d, A MOV A, @IX+d SUBC CMP dir, #d8 CMP DAS MOVW A, @IX+d MOV dir, #d8 MOV DAA MOVW ADDC A, dir A, #d8 A A MOV A, @IX+d OR OR ORW MOV CMP A, dir A, #d8 A A PS, A A, @IX+d AND AND ANDW OR MOV A, dir A, #d8 A A ext, A OR XOR XOR XORW AND AND dir, A A, T A, T IX SETC SETI XOR MOV XCHW XOR MOVW CLRC CLRI A, PS MOVW MOV A, dir SUBC A, #d8 SUBC SUBCW IX A, ext SUBC A, dir ADDC A, #d8 ADDC ADDCW XCH MOV MOV 9 ADDC A, dir A, #d8 A A addr16 SUBC A 8 7 CMP A, dir CMP CMP CMPW addr16 ADDC POPW POPW 6 MOV MOV A, #d8 MOV RORC CMP PUSHW CALL JMP DIVU MULU A 5 SETB SETB SETB SETB SETB SETB SETB SETB CLRB CLRB CLRB CLRB CLRB CLRB CLRB CLRB dir : 7 dir : 6 dir : 5 dir : 4 dir : 3 dir : 2 dir : 1 dir : 0 dir : 7 dir : 6 dir : 5 dir : 4 dir : 3 dir : 2 dir : 1 dir : 0 A dir : 7, rel BBS dir : 6, rel BBS dir : 5, rel BBS dir : 4, rel BBS dir : 3, rel BBS dir : 2, rel BBS dir : 1, rel BBS dir : 0, rel BBS dir : 7, rel BBC dir : 6, rel BBC dir : 5, rel BBC dir : 4, rel BBC dir : 3, rel BBC dir : 2, rel BBC dir : 1, rel BBC dir : 0, rel BBC B EP IX SP A INC INC INC INC INC INC INC INC R7 R6 R5 R4 R3 R2 R1 R0 A, @EP MOVW A, @IX+d MOVW A, dir MOVW A, ext MOVW INCW INCW INCW INCW C EP IX SP A DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 @EP, A MOVW @IX+d, A MOVW dir, A MOVW ext, A MOVW DECW DECW DECW DECW D @A CALLV CALLV CALLV CALLV CALLV CALLV CALLV CALLV #7 #6 #5 #4 #3 #2 #1 #0 EP, #d16 MOVW IX, #d16 MOVW SP, #d16 MOVW A, #d16 MOVW EP, A MOVW IX, A MOVW SP, A MOVW JMP E BLT BGE BZ BNZ BN BP BC BNC rel rel rel rel rel rel rel rel A, EP XCHW A, IX XCHW A, SP XCHW A, PC XCHW A, EP MOVW A, IX MOVW A, SP MOVW A, PC MOVW F Table B.4-1 ROLC PUSHW 4 RETI 3 RET 2 SWAP 1 NOP 0 B.4 1 0 H APPENDIX B Instructions Instruction Map Table B.4-1 lists the F2MC-8L instruction map. ■ Instruction Map F2MC-8L instruction map B.5 Bit Manipulation Instructions (SETB, CLRB) The bit manipulation instructions use a different read operation to the normal operation for some bits of peripheral function registers. ■ Read-modify-write Operation Bit manipulation instructions set to "1" (SETB) or clear to "0" (CLRB) the specified bit only of a register or RAM location. However, as the CPU handles data in 8-bit units, the actual operation consists of reading the 8-bit data, modifying the specified bit, then writing the result back to the same address. This is called a read-modify-write operation. Table B.5-1 shows the bus operation for bit manipulation instructions Table B.5-1 Bus Operation for Bit Manipulation Instructions Code A0 to A7 A8 to AF Mnemonic CLRB dir:b ~ Cycle 4 1 2 3 4 SETB dir:b Address bus N+1 dir address dir address N+2 Data bus RD WR RMW dir Data Data Next instruction 0 0 1 0 1 1 0 1 0 1 0 0 ■ Read Source when Executing Bit Manipulation Instructions The read source for a read-modify-write of some I/O ports and interrupt request flag bits is different than for a standard read. ● I/O ports (Bit manipulation instructions) For some I/O ports, a standard read reads the I/O pin values whereas a bit manipulation instruction reads, the output latch value. This is to prevent unintentionally modifying other output latch bit values and is independent of the pin input/output direction or pin state. ● Interrupt request flag bits (Bit manipulation instructions) For interrupt request flag bits, a standard read reads the flag bit to determine whether an interrupt has occurred. Bit manipulation instructions, however, always read interrupt request flag bits as "1". This is to prevent unintentionally clearing the flag by writing "0" to the interrupt request flag bit when performing bit manipulation of a different bit. 387 APPENDIX C Mask Options APPENDIX C Mask Options This appendix lists the mask options for the MB89480/480L series. ■ Mask Options Table C-1 Mask Options Part number MB89485 No. MB89485L Specify when ordering masking Specifying procedure MB89P485 MB89P485L Setting not possible MB89PV480 Setting not possible Booster selection (KSV) Internal resistor ladder Booster Selectable 1 101/103: Internal resistor ladder 102/104: Booster 101: Internal resistor ladder 102: Booster -- 101/102: No protection 103/104: with protection -- 2 Selection of OTPROM content protection feature No protection feature With protection feature Selection of oscillation stabilization time (OSC) 214/FCH(approx.1.3ms) Selectable OSC 218/FCH(approx.21.0ms) 218/ FCH(approx.21.0ms) 3 217/FCH(approx.10.5ms) 218/FCH(approx.21.0ms) 4 Selection of power-on stabilization time Nil 217/FCH Selectable Fixed to nil 217/FCH Fixed to nil Fixed to nil FCH: Main clock source oscillation frequency Note: When using the device without inputting the external reset in the timing of power-on, select "with power-on reset" and "with output reset" from the mask options. 388 APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers In MB89P485/L, there is a built-in PROM which can be programmed with Serial programmer by using dedicated adapter. Optionally, it can also be programmed with a parallel programmer and dedicated adapter. ■ One-time PROM product There are two one-time PROM products, MB89P485/L in this series. There is a built-in PROM in MB89P485/L. The built-in PROM can be programmed with serial programmer and parallel programmer with dedicated adaptor. Please refer section "D.1 Programming One-time PROM Microcontroller with serial programmer" and "D.2 Programming One-time PROM Microcontroller parallel programmer" for detail. The following show the one-time PROM product with different option. Table D-1 One-Time PROM programming option Package Programmable with Serial Programmer Programmable with parallel Programmer MB89P485/P485L-101 Yes Yes MB89P485/P485L-102 Yes Yes MB89P485/P485L-103* Yes No MB89P485/P485L-104* Yes No * : OTPROM content protection feature is available. ■ Piggyback/Evaluation Device There is a piggyback/evaluation product MB89PV480 in this series. There is no built-in PROM in MB89PV480. The EPROM used by MB89PV480 can be programmed with an general-purpose EPROM programmer with dedicated adaptor. Please refer "D.3 Programming EPROM for Piggyback/Evaluation Device" for detail. 389 APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers D.1 Programming One-time PROM Microcontroller with serial programmer This section describes programming One-time PROM microcontroller with FUJITSU FLASH programmer. ■ Programming the OTPROM To program the OTPROM use FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-6628-1-0770 FAX (65)-6628-1-0220 ■ Programming Adaptor for OTPROM To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter listed below. Package Compatible socker adaptor DIP-64P-M01 MB91919-812 FPT-64P-M09 MB91919-813 Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-6628-1-0770 FAX (65)-6628-1-0220 ■ OTPROM Content Protection For product with OTPROM content protection feature (MB89P485-103, MB89P485-104), OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by any serial programmer. Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H" in FFFCH). It is advised to write the OTPROM protection code at last. ■ Programming Yield All bits cannot be programmed at Fujitsu Shipping test to a blanked OTPROM microcontroller, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 390 D.2 Programming One-time PROM Microcontroller parallel programmer This section describes programming One-time PROM microcontroller with parallel programmer. ■ OTP Programming Adaptor and Recommended ROM Write Applicable adapter model Package name Fujitsu Microelectronics Asia Pte Ltd. Recommended writer maker and writer Minato electronics Co., Ltd. Fujitsu MCU Programmer MODEL 1890A MB91919 - 001 DIP-64P-M01 MB91919-604 Under evaluation Available FPT-64P-M09 MB91919-605 Under evaluation Available Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-6628-1-0770 Minato electronics Co., Ltd. : TEL (81)-45-59-1-5611 ■ Writing Data to the OTPROM Using Writer from Minato Electronics Co., Ltd. 1. Set the OTPROM writer for the CU50-OTP (device code: T.B.D.). 2. Load the program data to the OTPROM writer. 3. Write data using the OTPROM writer. ■ Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. ■ OTPROM Content Protection This feature is available in MB89P485/P485L-103 and MB89P485/P485L-104 only. It is not available in product which can be programmed by parallel programmer, i.e. MB89P485/P485L-101 and MB89P485/ P485L-102 391 APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers D.3 Programming EPROM for Piggyback/Evaluation Device This section describes programming EPROM for piggyback/evaluation device. ■ EPROM for Use MBM27C256A-20TVM ■ Programming Socket Adaptor To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below. Table D.3-1 Programming Socket Adaptor Package Adaptor socket part number LCC-32 (Rectangle) ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403 ■ Memory Space Figure D.3-1 Memory Map of Piggyback/Evaluation Device Address 0000H Normal operating mode Corresponding addresses on the EPROM programmer I/O 0080H RAM 0480H 8000H Not available 0000H PROM 32 Kbytes FFFFH EPROM 32 Kbytes 7FFFH ■ Programming to EPROM 1. Set the EPROM programmer to the MBM27C256A. 2. Load program data into the EPROM programmer at 0000H to 7FFFH. 3. Program to 0000H to 7FFFH with the EPROM programmer. 392 APPENDIX E MB89480/480L Series Pin States This section describes the pin states of the MB89480/480L series in each mode. ■ Pin States in Each Mode Table E-1 Pin States in Each Mode Pin name Normal operation Sleep mode Stop mode SPL=0 Stop mode SPL=1 During reset X0 Oscillator input Oscillator input Hi-Z Hi-Z Oscillator input X1 Oscillator output Oscillator output output "H" Output "H" Oscillator output X0A Oscillator input Oscillator input Hi-Z Hi-Z Oscillator input X1A Oscillator output Oscillator output output "H" Output "H" Oscillator output MODE Mode input Mode input Mode input Mode input Mode input RST Reset I/O Reset input Reset input Reset input Reset I/O Port / external interrupt 2 input Hold / external interrupt 2 input Hold / external interrupt 2 input "H" (if pull up) Hi-Z ( if not pull up) / external interrupt 2 input Hi-Z Port / external interrupt 2 input or peripheral I/O Hold / external interrupt 2 input or peripheral I/O Hold / external interrupt 2 input "H" (if pull up) Hi-Z ( if not pull up) / external interrupt 2 input Hi-Z P10/SEG23/ INT10 to P13/SEG26/ INT13 Port / peripheral I/O or external interrupt 1 input Hold / peripheral I/O or external interrupt 1 input Hold / external interrupt 1 input Hi-Z / external interrupt 1 input Hi-Z P14/SEG27/ AN0 to P17/SEG30/ AN3 Port / peripheral I/O or AD input Hold / peripheral I/O or AD input Hold Hi-Z Hi-Z Port / peripheral I/O Hold / peripheral I/O Hold "H" (if pull up) Hi-Z ( if not pull up) Hi-Z Port / capacitor connecting pin / peripheral I/O Hold / capacitor connecting pin / peripheral I/O Hold / capacitor connecting pin "H" (if pull up) Hi-Z (if not pull up) / capacitor connecting pin Hi-Z / capacitor connecting pin Port / LCD power pin / peripheral I/O Hold / LCD power pin / peripheral I/O Port / LCD common output Hold / LCD common output Hold Hi-Z / Hold Hi-Z Port / LCD segment output Hold / LCD segment output Hold Hi-Z / Hold Hi-Z P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/ITN25/ PWC P06/INT26/PPG P07/INT27/BUZ P20/PWM P21/SCK P22/SO P23/SI P24/C1/TO2 P25/C0/EC2 P26/V1/TO1 P27/V2/EC1 P30/COM2 P31/COM3 P40/SEG8 to P47/SEG15 P50/SEG16 to P56/SEG22 "H" (if pull up) Hold / LCD power pin Hi-Z (if not pull up) / LCD power pin LCD power pin P57 Port Hold Hold Hi-Z Hi-Z SEG1 to SEG7 LCD segment output LCD segment output Hold Hold "L" output COM0, COM1 LCD common output LCD common output Hold Hold "L" output V0/SEG0 LCD power pin / LCD segment output LCD power pin / LCD segment output Hold Hold LCD power pin / "L" output 393 APPENDIX E MB89480/480L Series Pin States 394 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 395 INDEX Index Numerics A 1/2 Bias, 1/2 Duty Output Waveform.................... 355 6-bit PPG 6-bit PPG Function........................................... 207 6-bit PPG Timer Function ................................. 206 Block Diagram of 6-bit PPG Timer .................... 209 Block Diagram of 6-bit PPG Timer Pin .............. 211 Notes on Using 6-bit PPG Timer........................ 217 Operation of 6-bit PPG Timer............................ 215 Pin of 6-bit PPG Timer ..................................... 211 Programming Example for 6-bit PPG Timer ....... 219 6-bit PPG Control Register 1 (PPGC1) ................ 213 6-bit PPG Control Register 2 (PPGC2) ................ 214 8-bit Receiving Operation..................................... 318 8-bit Transmission Operation ............................... 320 8/16-bit Timer/Counter 8/16-bit Timer/Counter Interrupt........................ 237 Block Diagram of 8/16-bit Timer/Counter .......... 224 Interrupt Source of 8/16-bit Timer/Counter ......... 228 Notes on Using 8/16-bit Timer/Counter .............. 247 Pins of 8/16-bit Timer/Counter .......................... 226 Registers and Vector Table for 8/16-bit Timer/Counter (11, 12, 21, 22) Interrupt ...................... 238 8-bit Mode Timer 11/21 Interrupt Operation ......... 237 8-bit PWM Timer 8-bit PWM Timer Interrupt Source .................... 163 Block Diagram of 8-bit PWM Timer .................. 160 Block Diagram of 8-bit PWM Timer Pin ............ 162 Pin of 8-bit PWM Timer ................................... 162 Registers and Vector Tables for 8-bit PWM Timer Interrupts ............................................ 168 A/D 396 A/D Control Register 1 (ADC1) ........................ 283 A/D Control Register 2 (ADC2) ........................ 285 A/D Conversion Function ................................. 278 A/D Converter Interrupt Source......................... 282 A/D Converter Power Supply Voltage ............... 280 A/D Data Registers (ADDL and ADDH)............ 287 Activating A/D Conversion Function ................. 289 Block Diagram of A/D Converter ...................... 279 Block Diagram of A/D Converter Pin ................ 281 Interrupt for A/D Conversion Function .............. 288 Notes on Using A/D Converter.......................... 291 Operation of A/D Conversion Function .............. 290 Pins of A/D Converter ...................................... 281 Program Example for A/D Conversion Function ......................................................... 293 Register and Vector Table for A/D Converter Interrupt ......................................................... 288 Addressing Modes ............................................... 373 Arithmetic Operation Arithmetic Operation Instructions...................... 383 B Block Diagram Block Diagram of 6-bit PPG Timer.................... 209 Block Diagram of 6-bit PPG Timer Pin .............. 211 Block Diagram of 8/16-bit Timer Counter Pins ......................................................... 227 Block diagram of 8/16-bit Timer/Counter........... 224 Block Diagram of 8-bit PWM Timer.................. 160 Block Diagram of 8-bit PWM Timer Pin ............ 162 Block Diagram of A/D Converter ...................... 279 Block Diagram of A/D Converter Pin ................ 281 Block Diagram of Buzzer Output ...................... 326 Block Diagram of Buzzer Output Pin................. 327 Block Diagram of Clock Controller ..................... 61 Block Diagram of External Interrupt 2 Circuit Pins ......................................................... 269 Block Diagram of External Interrupt Circuit 2 ......................................................... 267 Block Diagram of External Reset Pin................... 53 Block Diagram of LCD Controller/Driver .......... 333 Block Diagram of MB89480/480L Series............... 8 Block Diagram of of Pins of Port 0 ...................... 89 Block Diagram of of Pins of Port 1 ...................... 95 Block Diagram of of Pins of Port 2 .................... 101 Block Diagram of of Pins of Port 3 .................... 109 Block Diagram of of Pins of Port 4 .................... 113 Block Diagram of of Pins of Port 5 .................... 117 INDEX Block Diagram of Pulse Width Count Timer .......................................................... 180 Block Diagram of Pulse Width Count Timer Pins .......................................................... 182 Block Diagram of the External Interrupt 1 Circuit .......................................................... 255 Block Diagram of the External Interrupt 1 Circuit Pins .......................................................... 256 Block Diagram of Time-base Time .................... 124 Block Diagram of UART/SIO ........................... 297 Block Diagram of UART/SIO Pin ..................... 300 Block Diagram of Watch Prescaler .................... 148 Block Diagram of Watchdog Timer ................... 137 Block Diagrams of LCD Controller/Driver Pin .......................................................... 342 Branch Instructions .............................................. 385 Buzzer Block Diagram of Buzzer Output....................... 326 Block Diagram of Buzzer Output Pin ................. 327 Buzzer Output Function.................................... 324 Buzzer Output Pin............................................ 327 Buzzer Output Register..................................... 327 Buzzer Register (BUZR)................................... 328 Program Example for Buzzer Output ................. 329 C Changing to a Standby Mode and Interrupts ......... 81 Clock Block Diagram of Clock Controller ..................... 61 Clock Generator................................................. 60 Clock Mode Operating States .............................. 65 Clock Supply Function ............................. 123, 147 Clock Supply Map ............................................. 58 Configuration of System Clock Control Register (SYCC)................................................ 63 Main Clock Oscillation Stabilization Wait Time ............................................................ 69 Main Clock Oscillation Stabilization Wait Time and the Reset Source ................................... 50 Operation of Clock Supply Function .................. 129 Operation of Clock supply Function................... 152 Operation of Main Clock Mode ........................... 66 Operation of Sub clock Mode.............................. 66 Speed-Shift (Main Clock Speed-switching) Function ............................................................ 66 Sub clock Oscillation Stabilization Wait Time ............................................................ 70 Transmission Operation in Clock Asynchronous Mode ................................................. 316 Configuration of Dedicated Register ..................... 31 Configuration of General-purpose Registers ......... 37 Configuration of Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) .............................. 40 Configuration of Register Bank Pointer (RP) ......... 36 Configuration of System Clock Control Register (SYCC) .........................................................63 Continuous Receiving Operations ........................319 Continuous Transmission Operations ..................321 Counter Function ..................................................223 D Detecting the Start Bit during Receiving Operation ...................................................................315 Devices with Internal Voltage Boosters ................339 DIP-64P-M01 Package Dimensions .......................12 DIP-64P-M01 Pin Assignment ..................................9 Display Brightness Adjustment when Internal Divider Resistors are Used .....................................336 Display RAM and Output Pins ..............................351 E Effect of Reset on RAM Contents...........................55 EPROM for Use....................................................392 External Dividing Resistors...................................338 External Interrupt Block Diagram of External Interrupt 2 Circuit Pins ..........................................................269 Block Diagram of External Interrupt Circuit 2 ..........................................................267 Block Diagram of the External Interrupt 1 Circuit ..........................................................255 Block Diagram of the External Interrupt 1 Circuit Pins ..........................................................256 External Interrupt 1 Circuit Interrupt Sources ..........................................................257 External Interrupt 2 Circuit Function (Level Detection).................................266 External Interrupt 2 Circuit Interrupt Sources ..........................................................270 External Interrupt 2 Control Register (EIE2) ..........................................................271 External Interrupt 2 Flag Register (EIF2) ............273 External Interrupt Control Register 1 (EIC1) ..........................................................258 External Interrupt Control Register 2 (EIC2) ..........................................................260 Functions of the External Interrupt Circuit 1 ..........................................................254 Interrupts for External Interrupt 2 Circuit Operation ..........................................................274 Interrupts When the External Interrupt Circuit 1 is Operating ...........................................262 Operation of External Interrupt 2 Circuit.............275 Operation of the External Interrupt 1 Circuit ..........................................................263 Pins of External Interrupt 1 Circuit .....................256 Pins of External Interrupt 2 Circuit .....................268 397 INDEX Program Example for External Interrupt 2 Circuit .......................................................... 276 Program Example for the External Interrupt 1 Circuit .......................................................... 264 Register and Vector Table for External Interrupt 2 Circuit Interrupts ................................ 274 Register and Vector Table for the External Interrupt 1 Circuit Interrupts ................................ 262 External Reset Block Diagram of External Reset Pin ................... 53 Functions of External Reset Pin ........................... 53 F Features of General-purpose Registers ................. 38 FPT-64P-M09 Package Dimensions ...................... 13 FPT-64P-M09 Pin Assignment............................... 10 Functions of Dedicated Register ............................ 31 Functions of the External Interrupt Circuit 1 ......... 254 G General-purpose Register Areas (Addresses: 0100H to 01FFH) ...................... 28 Interval Timer Function (Square Wave Output Function) ................ 158 Interval Timer Function (Watch Interrupt) ............ 146 L LCD Control Register 1 (LCR1) ........................... 347 LCD Control Register 2 (LCR2) ........................... 349 LCD Controller/Driver Block Diagram of LCD Controller/Driver .......... 333 Block Diagrams of LCD Controller/Driver Pin ......................................................... 342 LCD Controller/Driver Function ....................... 332 LCD Controller/Driver Pins .............................. 341 LCD Controller/Driver RAM ............................ 346 LCD Controller/Driver Register ........................ 346 LCD Controller/Driver Supply Voltage.............. 334 Operation of LCD Controller/Driver .................. 353 Output Waveforms during LCD Controller/ Driver Operation (1/3 Duty Ratio) ........ 358 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) .................. 361 Program example for LCD Controller/Driver ......................................................... 364 LCD Driving Waveforms ...................................... 354 I I/O M Functions of I/O Port .......................................... 86 I/O map ........................................................... 368 Pin Functions ..................................................... 16 Program Example for I/O Ports.......................... 120 Instruction Cycle (tinst)............................................ 64 Instruction List Symbols ....................................... 371 Instruction Map..................................................... 386 Internal Dividing Resistors.................................... 335 Interrupt Acceptance Control Bit ............................ 34 Interrupt for A/D Conversion Function.................. 288 Interrupt for Pulse Width Measurement Function ................................................................... 191 Interrupt for the Interval Timer Function ............... 191 Interrupt Processing ............................................... 42 Interrupt Processing Time ...................................... 46 Interrupt Requests from Peripheral Functions........ 39 Interrupts for External Interrupt 2 Circuit Operation ................................................................... 274 Interrupts for Interval Timer Function .................. 168 Interrupts for Interval Timer Function (Watch Interrupt) ........................................ 151 Interrupts for Time-base Timer Function .............. 128 Interrupts When the External Interrupt Circuit 1 is Operating .................................................. 262 Interval Timer Function ........................ 122, 178, 222 Main Clock Oscillation Stabilization Wait Time ..................................................................... 69 Main Clock Oscillation Stabilization Wait Time and the Reset Source ........................................ 50 Mask Options ....................................................... 388 MB89480/480L Series Block Diagram of MB89480/480L Series............... 8 Features of MB89480/480L Series......................... 2 MB89480/480L Series Product Range ................... 4 MDP-64C-P02 Package Dimensions..................... 14 Measuring Long Pulse Widths ............................. 196 Memory Map .......................................................... 27 Memory Space..................................................... 392 Structure of Memory Space ................................... 26 Mode Data ............................................................. 83 Mode Fetch ............................................................ 55 Mode Pins .............................................................. 55 Mode Pins (MODE)................................................ 83 MQP-64C-P01 Package Dimensions..................... 15 MQP-64C-P01 Pin Assignment ............................. 11 Multiple Interrupts .................................................. 45 398 N Notes on Handling Devices.................................... 24 Notes on Setting Standby Mode ............................ 81 INDEX Notes on Using 6-bit PPG Timer.......................... 217 Notes on Using 8/16-bit Timer/Counter ............... 247 Notes on Using 8-bit PWM Timer ....................... 173 Notes on Using A/D Converter............................. 291 Notes on Using Pulse Width Count Timer ........... 199 Notes on Using Time-base Timer ........................ 131 Notes on Using Watch Prescaler ......................... 154 Notes on Using Watchdog Timer ......................... 142 Notes when changing edge polarity selection ................................................................... 262 O One-time PROM product ..................................... 389 Operating States in Standby Modes ...................... 73 Operation during Standby Mode or Operation Halt ................................................... 171, 198, 246 Operation for Selecting the Memory Access Mode ..................................................................... 84 Operation of 6-bit PPG Timer .............................. 215 Operation of A/D Conversion Function ................ 290 Operation of Clock Supply Function .................... 129 Operation of Clock supply Function ..................... 152 Operation of Counter Function............................. 241 Operation of External Interrupt 2 Circuit .............. 275 Operation of Interval Timer Function ................................................... 169, 192, 239 Operation of Interval Timer Function (Time-base Timer) ..................................... 129 Operation of Interval Timer Function (Watch Prescaler) ...................................... 152 Operation of LCD Controller/Driver...................... 353 Operation of Main Clock Mode .............................. 66 Operation of Operating Mode 0 ........................... 313 Operation of Operating Mode 1 ........................... 317 Operation of Port 0................................................. 92 Operation of Port 1................................................. 98 Operation of Port 2............................................... 106 Operation of Port 3............................................... 111 Operation of Port 4............................................... 115 Operation of Port 5............................................... 119 Operation of Pulse Width Measurement Function ................................................................... 195 Operation of PWM Timer Function ...................... 170 Operation of Sleep Mode ....................................... 74 Operation of Square Wave Output Initial Setting Function .................................................... 243 Operation of Stop Mode......................................... 75 Operation of Sub clock Mode................................. 66 Operation of the External Interrupt 1 Circuit ........ 263 Operation of Time-base Timer ............................. 129 Operation of UART/SIO ........................................312 Operation of watch Mode .......................................76 Operation of Watch Prescaler ..............................153 Operation of Watchdog Timer ..............................140 Oscillation Stabilization Wait in Reset State ...........55 Oscillation Stabilization Wait Time ...................68, 82 Oscillation Stabilization Wait Time and Time-base Timer Interrupt...................128 Oscillation Stabilization Wait Time and Watch Interrupt....................................151 Other Instructions .................................................385 OTP Programming Adaptor and Recommended ROM Write ...........................................................391 OTPROM Content Protection .......................390, 391 Output Waveforms during LCD Controller/ Driver Operation (1/3 Duty Ratio)...............358 Output Waveforms during LCD Controller/ Driver Operation (1/4 Duty Ratio)...............361 Overview of Reset Operation .................................54 P Package DIP-64P-M01 Package Dimensions......................12 FPT-64P-M09 Package Dimensions .....................13 MDP-64C-P02 Package Dimensions ....................14 MQP-64C-P01 Package Dimensions ....................15 Piggyback/Evaluation Device ...............................389 Pin States after Reading Mode Data ......................57 Pin States during Reset..........................................57 Pin States in Each Mode ......................................393 Port 0 Block Diagram of Pins of Port 0...........................89 Functions of Port 0 Register.................................90 Operation of Port 0 .............................................92 Pins of Port 0 .....................................................88 Port 0 Registers ..................................................89 Structure of Port 0 ..............................................88 Port 1 Block Diagram of Pins of Port 1...........................95 Functions of Port 1 Register.................................96 Operation of Port 1 .............................................98 Pins of Port 1 .....................................................94 Port 1 Registers ..................................................95 Structure of Port 1 ..............................................94 Port 2 Block Diagram of Pins of Port 2.........................101 Functions of Port 2 Register...............................104 Operation of Port 2 ...........................................106 Pins of Port 2 ...................................................100 Port 2 Registers ................................................103 Structure of Port 2 ............................................100 Port 3 Block Diagram of Pins of Port 3.........................109 399 INDEX Functions of Port 3 Register .............................. 110 Operation of Port 3 ........................................... 111 Pins of Port 3 ................................................... 108 Port 3 Register ................................................. 109 Structure of Port 3 ............................................ 108 Port 4 Block Diagram of Pins of Port 4 ........................ 113 Functions of Port 4 Register .............................. 114 Operation of Port 4 ........................................... 115 Pins of Port 4 ................................................... 112 Port 4 Register ................................................. 113 Structure of Port 4 ............................................ 112 Port 5 Block Diagram of Pins of Port 5 ........................ 117 Functions of Port 5 Register .............................. 118 Operation of Port 5 ........................................... 119 Pins of Port 5 ................................................... 116 Port 5 Register ................................................. 117 Structure of Port 5 ............................................ 116 Power-on Stabilization Time................................... 55 Power-on Stabilization Wait Time ......................... 68 Program Example for Watchdog Timer ................ 143 Differences between Products and Points to Note for Product Selection ........................................... 7 Program Example 1 for Interval Timer Function (Reload Timer Mode) ................................ 200 Program Example 2 for Interval Timer Function (One-shot Timer Mode).............................. 201 Program Example for A/D Conversion Function ................................................................... 293 Program Example for Buzzer Output ................... 329 Program Example for External Interrupt 2 Circuit ................................................................... 276 Program Example for I/O Ports ............................ 120 Program Example for Interval Timer Function ........................................................... 174, 249 Program example for LCD Controller/Driver ........ 364 Program Example for Pulse Counter Function ................................................................... 251 Program Example for Pulse Width Measurement Function .................................................... 203 Program Example for PWM Timer Function......... 175 Program Example for the External Interrupt 1 Circuit ................................................................... 264 Program Example for the Watch Prescaler .......... 156 Program Example for Time-base Timer ............... 133 Programming Adaptor for OTPROM .................... 390 Programming Example for 6-bit PPG Timer......... 219 Programming Socket Adaptor .............................. 392 Programming the OTPROM ................................. 390 Programming to EPROM...................................... 392 Programming Yield....................................... 390, 391 Pulse Width Count Timer Block Diagram of Pulse Width Count Timer ......................................................... 180 Block Diagram of Pulse Width Count Timer Pins ......................................................... 182 Notes on Using Pulse Width Count Timer .......... 199 Pins of Pulse Width Count Timer ...................... 182 Pulse Width Count Timer Interrupt Source ......... 183 Register and Vector Table for Pulse Width Count Timer Interrupt .................................. 191 Pulse Width Measurement Function .................... 179 PWC Pulse Width Control Register 1 (PCR1) ................................................................... 184 PWC Pulse Width Control Register 2 (PCR2) ................................................................... 187 PWC Reload Buffer Register (PLBR) .................. 189 PWM Compare Register (COMR)........................ 166 PWM Control Register (CNTR)............................ 164 PWM Timer Function ........................................... 159 R Read Source when Executing Bit Manipulation Instructions ................................................ 387 Read-modify-write Operation ............................... 387 Receive Interrupt.................................................. 311 Receiving Errors in Asynchronous Mode............. 315 Receiving Operation in Clock Asynchronous Mode ................................................................... 314 Register and Vector Table for A/D Converter Interrupt ................................................................... 288 Register and Vector Table for External Interrupt 2 Circuit Interrupts ....................................... 274 Register and Vector Table for Pulse Width Count Timer Interrupt .......................................... 191 Register and Vector Table for the External Interrupt 1 Circuit Interrupts ....................................... 262 Register and Vector Table for Time-base Timer Interrupts................................................... 128 Register and Vector Table for Watch Prescaler Interrupt .................................................... 151 Registers and Vector Table for 8/16-bit Timer/ Counter (11, 12, 21, 22) Interrupt .............. 238 Registers and Vector Tables for 8-bit PWM Timer Interrupts................................................... 168 Registers and Vector Table for UART/SIO Interrupts ................................................................... 311 Regulator Recovery Time ................................ 55, 68 Reset Flag Register (RSFR) .................................. 51 Reset Source ......................................................... 49 S Serial Input Data Register (SIDR)........................ 308 400 INDEX Serial Mode Control Register 1 (SMC1) .............. 302 Serial Mode Control Register 2 (SMC2) .............. 304 Serial Output Data Register (SODR) ................... 309 Serial rate control register (SRC)......................... 310 Serial Status and Data Register (SSD)................ 306 Single-chip Mode ................................................... 83 Special Instructions.............................................. 377 Speed-Shift (Main Clock Speed-switching) Function ..................................................................... 66 Stabilization Wait Time for Different Operation for Different Product.......................................... 68 Stack Area for Interrupt Processing ....................... 48 Stack Operation at Interrupt Return ....................... 47 Stack Operation during Interrupt Processing ......... 47 Standby Control Register (STBC).......................... 77 Standby Modes ...................................................... 71 State Transition Diagram ....................................... 79 Storing 16-bit Data in RAM .................................... 30 Storing 16-bit Data on Stack .................................. 30 Storing 16-bit Operands......................................... 30 Structure of Condition Code Register (CCR) ......... 33 Structure of Port 0.................................................. 88 Structure of Port 1.................................................. 94 Structure of Port 2................................................ 100 Structure of Port 3................................................ 108 Structure of Port 4................................................ 112 Structure of Port 5................................................ 116 Sub clock Oscillation Stabilization Wait Time ..................................................................... 70 T Time-base Timer Notes on Using Time-base Timer ...................... 131 Operation of Interval Timer Function (Time-base Timer) .............................. 129 Operation of Time-base Timer .......................... 129 Oscillation Stabilization Wait Time and Time-base Timer Interrupt ............. 128 Program Example for Time-base Timer.............. 133 Register and Vector Table for Time-base Timer Interrupts........................................... 128 Time-base Timer Control Register (TBTC) ........ 126 Timer 11/21 Control Register (T11CR/T21CR) ................................................................... 229 Timer 11/21 Data Register (T11DR/T21DR)........ 233 Timer 12/22 Control Register (T12CR/T22CR) ...................................................................231 Timer 12/22 Data Register (T12DR/T22DR) ........235 Timer Stop and Restart ........................................245 Transfer Instructions.............................................381 Transmission Data Format ...................................314 Transmission Operation in Clock Asynchronous Mode ..........................................................316 Transmit Interrupt .................................................311 U UART/SIO Block Diagram of UART/SIO............................297 Block Diagram of UART/SIO Pin ......................300 Function of UART/SIO .....................................296 Operation of UART/SIO ...................................312 Register and Vector Table for UART/SIO Interrupts ..........................................................311 Pin of UART/SIO .............................................299 Registers of UART/SIO ....................................301 Use of Internal Voltage Divider Resistors .............336 V Vector Table Area (Addresses: FFC0H to FFFFH) ................................................................................28 W Wake-up from Standby Mode by Interrupt..............81 Watch Prescaler Block Diagram of Watch Prescaler.....................148 Notes on Using Watch Prescaler ........................154 Operation of Interval Timer Function (Watch Prescaler) ................................152 Operation of Watch Prescaler ............................153 Program Example for the Watch Prescaler ..........156 Register and Vector Table for Watch Prescaler Interrupt.............................................151 Watch Prescaler Control Register (WPCR) .........149 Watchdog Timer Block Diagram of Watchdog Timer....................137 Notes on Using Watchdog Timer .......................142 Operation of Watchdog Timer ...........................140 Watchdog Timer Control Register (WDTC) ..........................................................139 Watchdog Timer Function .................................136 Writing Data to the OTPROM Using Writer from Minato Electronics Co., Ltd. .......................391 401 INDEX 402 CM25-10151-2E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-8L 8-BIT MICROCONTROLLER MB89480/480L Series HARDWARE MANUAL October 2007 the second edition Published FUJITSU LIMITED Edited Strategic Business Development Dept. Electronic Devices