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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
MN702-00005-2v0-E
New 8FX
8-BIT MICROCONTROLLER
MB95410H/470H Series
HARDWARE MANUAL
New 8FX
8-BIT MICROCONTROLLER
MB95410H/470H Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
PREFACE
■ The Purpose and Intended Readership of This Manual
Thank you very much for your continued special support for Fujitsu Semiconductor products.
The MB95410H/470H Series is a line of products developed as general-purpose products in the
New 8FX family of proprietary 8-bit single-chip microcontrollers applicable as applicationspecific integrated circuits (ASICs). The MB95410H/470H Series can be used for a wide range
of applications from consumer products including portable devices to industrial equipment.
Intended for engineers who actually develop products using the MB95410H/470H Series of
microcontrollers, this manual describes its functions, features, and operations. You should read
through the manual.
For details on individual instructions, refer to "F2MC-8FX Programming Manual".
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names in this document are the trademarks or registered
trademarks of their respective owners.
■ Sample Programs
Fujitsu Semiconductor provides sample programs free of charge to operate the peripheral
resources of the New 8FX family of microcontrollers. Feel free to use such sample programs to
check the operational specifications and usages of Fujitsu microcontrollers.
Note that sample programs are subject to change without notice. As these pieces of software
are offered to show standard operations and usages, evaluate them sufficiently before use with
your system. Fujitsu Semiconductor assumes no liability for any damages whatsoever arising
out of the use of sample programs.
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FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU
SEMICONDUCTOR") reserves the right to make changes to the information contained in this document without
notice. Please contact your FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU
SEMICONDUCTOR device.
Customers are advised to consult with sales representatives before ordering.
Information contained in this document, such as descriptions of function and application circuit examples is
presented solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device.
FUJITSU SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to
such information, including, without limitation, quality, accuracy, performance, proper operation of the device or
non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device
based on such information, you must assume any responsibility or liability arising out of or in connection with such
information or any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any
damages whatsoever arising out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents,
copyrights, or any other intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license
or otherwise, express or implied. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any
infringement of any intellectual property rights or other rights of third parties resulting from or in connection with
the information contained herein or use thereof.
The products described in this document are designed, developed and manufactured as contemplated for general
use including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical
damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic
control system, mass transport control system, medical life support system and military application), or (2) for use
requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial
satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or
damages arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate
designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety
design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of
overcurrent levels and other abnormal operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and
Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other
countries. You are responsible for ensuring compliance with such laws and regulations relating to export or reexport of the products and technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Copyright © 2010-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
OVERVIEW ...................................................................................... 1
Features of MB95410H/470H Series ................................................................................... 2
Product Line-up of MB95410H/470H Series ....................................................................... 5
Differences among Products and Notes on Product Selection .......................................... 10
Block Diagrams of MB95410H/470H Series ...................................................................... 11
Pin Assignment .................................................................................................................. 13
Package Dimension ........................................................................................................... 15
Pin Functions ..................................................................................................................... 18
I/O Circuit Types ................................................................................................................ 31
NOTES ON DEVICE HANDLING ................................................... 37
Notes on Device Handling ................................................................................................. 38
CHAPTER 3
MEMORY SPACE .......................................................................... 41
3.1
Memory Space .................................................................................................................. 42
3.1.1
Areas for Specific Applications ..................................................................................... 44
3.2
Memory Maps .................................................................................................................... 45
CHAPTER 4
4.1
MEMORY ACCESS MODE ............................................................ 47
Memory Access Mode ....................................................................................................... 48
CHAPTER 5
CPU ................................................................................................ 49
5.1
Dedicated Registers ..........................................................................................................
5.1.1
Register Bank Pointer (RP) ..........................................................................................
5.1.2
Direct Bank Pointer (DP) ..............................................................................................
5.1.3
Condition Code Register (CCR) ...................................................................................
5.2
General-purpose Register .................................................................................................
5.3
Placement of 16-bit Data in Memory .................................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
50
52
53
55
57
59
CLOCK CONTROLLER ................................................................. 61
Overview of Clock Controller .............................................................................................
Oscillation Stabilization Wait Time ....................................................................................
System Clock Control Register (SYCC) ............................................................................
PLL Control Register (PLLC) .............................................................................................
Oscillation Stabilization Wait Time Setting Register (WATR) ............................................
Standby Control Register (STBC) .....................................................................................
System Clock Control Register 2 (SYCC2) .......................................................................
Clock Modes ......................................................................................................................
Operations in Low-power Consumption Mode (Standby Mode) ........................................
Notes on Using Standby Mode .....................................................................................
Sleep Mode ..................................................................................................................
Stop Mode ....................................................................................................................
Time-base Timer Mode ................................................................................................
Watch Mode .................................................................................................................
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62
70
72
74
75
78
81
83
87
88
90
91
93
95
6.10
6.11
6.12
6.13
6.14
Clock Oscillator Circuit ...................................................................................................... 96
Overview of Prescaler ....................................................................................................... 97
Configuration of Prescaler ................................................................................................. 98
Operation of Prescaler ....................................................................................................... 99
Notes on Using Prescaler ................................................................................................ 100
CHAPTER 7
7.1
7.2
7.3
RESET .......................................................................................... 101
Reset Operation .............................................................................................................. 102
Reset Source Register (RSRR) ....................................................................................... 106
Notes on Using Reset ...................................................................................................... 109
CHAPTER 8
INTERRUPTS ............................................................................... 111
8.1
Interrupts .........................................................................................................................
8.1.1
Interrupt Level Setting Registers (ILR0 to ILR5) .........................................................
8.1.2
Interrupt Processing ...................................................................................................
8.1.3
Nested Interrupts ........................................................................................................
8.1.4
Interrupt Processing Time ..........................................................................................
8.1.5
Stack Operation During Interrupt Processing .............................................................
8.1.6
Interrupt Processing Stack Area .................................................................................
CHAPTER 9
112
114
115
117
118
119
120
I/O PORTS (MB95410H SERIES) ................................................ 121
9.1
Overview of I/O Ports ......................................................................................................
9.2
Port 0 ...............................................................................................................................
9.2.1
Port 0 Registers ..........................................................................................................
9.2.2
Operations of Port 0 ...................................................................................................
9.3
Port 1 ...............................................................................................................................
9.3.1
Port 1 Registers ..........................................................................................................
9.3.2
Operations of Port 1 ...................................................................................................
9.4
Port 2 ...............................................................................................................................
9.4.1
Port 2 Registers ..........................................................................................................
9.4.2
Operations of Port 2 ...................................................................................................
9.5
Port 4 ...............................................................................................................................
9.5.1
Port 4 Registers ..........................................................................................................
9.5.2
Operations of Port 4 ...................................................................................................
9.6
Port 5 ...............................................................................................................................
9.6.1
Port 5 Registers ..........................................................................................................
9.6.2
Operations of Port 5 ...................................................................................................
9.7
Port 6 ...............................................................................................................................
9.7.1
Port 6 Registers ..........................................................................................................
9.7.2
Operations of Port 6 ...................................................................................................
9.8
Port 9 ...............................................................................................................................
9.8.1
Port 9 Registers ..........................................................................................................
9.8.2
Operations of Port 9 ...................................................................................................
9.9
Port A ...............................................................................................................................
9.9.1
Port A Registers .........................................................................................................
9.9.2
Operations of Port A ...................................................................................................
9.10 Port B ...............................................................................................................................
9.10.1 Port B Registers .........................................................................................................
9.10.2 Operations of Port B ...................................................................................................
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122
124
128
129
132
135
136
138
140
141
143
145
146
148
150
151
153
155
156
158
160
161
163
165
166
168
170
171
9.11 Port C ..............................................................................................................................
9.11.1 Port C Registers .........................................................................................................
9.11.2 Operations of Port C ...................................................................................................
9.12 Port E ...............................................................................................................................
9.12.1 Port E Registers .........................................................................................................
9.12.2 Operations of Port E ...................................................................................................
9.13 Port F ...............................................................................................................................
9.13.1 Port F Registers ..........................................................................................................
9.13.2 Operations of Port F ...................................................................................................
9.14 Port G ..............................................................................................................................
9.14.1 Port G Registers .........................................................................................................
9.14.2 Operations of Port G ...................................................................................................
173
175
176
178
180
181
183
185
186
188
190
191
CHAPTER 10 I/O PORTS (MB95470H SERIES) ................................................ 193
10.1 Overview of I/O Ports ......................................................................................................
10.2 Port 0 ...............................................................................................................................
10.2.1 Port 0 Registers ..........................................................................................................
10.2.2 Operations of Port 0 ...................................................................................................
10.3 Port 1 ...............................................................................................................................
10.3.1 Port 1 Registers ..........................................................................................................
10.3.2 Operations of Port 1 ...................................................................................................
10.4 Port 2 ...............................................................................................................................
10.4.1 Port 2 Registers ..........................................................................................................
10.4.2 Operations of Port 2 ...................................................................................................
10.5 Port 6 ...............................................................................................................................
10.5.1 Port 6 Registers ..........................................................................................................
10.5.2 Operations of Port 6 ...................................................................................................
10.6 Port 9 ...............................................................................................................................
10.6.1 Port 9 Registers ..........................................................................................................
10.6.2 Operations of Port 9 ...................................................................................................
10.7 Port A ...............................................................................................................................
10.7.1 Port A Registers .........................................................................................................
10.7.2 Operations of Port A ...................................................................................................
10.8 Port B ...............................................................................................................................
10.8.1 Port B Registers .........................................................................................................
10.8.2 Operations of Port B ...................................................................................................
10.9 Port C ..............................................................................................................................
10.9.1 Port C Registers .........................................................................................................
10.9.2 Operations of Port C ...................................................................................................
10.10 Port E ...............................................................................................................................
10.10.1 Port E Registers .........................................................................................................
10.10.2 Operations of Port E ...................................................................................................
10.11 Port F ...............................................................................................................................
10.11.1 Port F Registers ..........................................................................................................
10.11.2 Operations of Port F ...................................................................................................
10.12 Port G ..............................................................................................................................
10.12.1 Port G Registers .........................................................................................................
10.12.2 Operations of Port G ...................................................................................................
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194
196
200
201
204
207
208
210
212
213
215
217
218
220
222
223
225
227
228
230
232
233
235
237
238
240
242
243
245
247
248
250
252
253
CHAPTER 11 TIME-BASE TIMER ...................................................................... 255
11.1 Overview of Time-base Timer .........................................................................................
11.2 Configuration of Time-base Timer ...................................................................................
11.3 Register of Time-base Timer ...........................................................................................
11.3.1 Time-base Timer Control Register (TBTC) .................................................................
11.4 Interrupts of Time-base Timer .........................................................................................
11.5 Operations of Time-base Timer and Setting Procedure Example ...................................
11.6 Notes on Using Time-base Timer ....................................................................................
CHAPTER 12
256
257
259
260
262
264
267
HARDWARE/SOFTWARE WATCHDOG TIMER ....................... 269
12.1 Overview of Watchdog Timer ..........................................................................................
12.2 Configuration of Watchdog Timer ....................................................................................
12.3 Register of Watchdog Timer ............................................................................................
12.3.1 Watchdog Timer Control Register (WDTC) ................................................................
12.4 Operations of Watchdog Timer and Setting Procedure Example ....................................
12.5 Notes on Using Watchdog Timer .....................................................................................
270
271
273
274
276
279
CHAPTER 13 WATCH PRESCALER ................................................................. 281
13.1 Overview of Watch Prescaler ..........................................................................................
13.2 Configuration of Watch Prescaler ....................................................................................
13.3 Register of Watch Prescaler ............................................................................................
13.3.1 Watch Prescaler Control Register (WPCR) ................................................................
13.4 Interrupts of Watch Prescaler ..........................................................................................
13.5 Operations of Watch Prescaler and Setting Procedure Example ....................................
13.6 Notes on Using Watch Prescaler .....................................................................................
13.7 Sample Settings for Watch Prescaler ..............................................................................
282
283
285
286
288
289
291
292
CHAPTER 14 WATCH COUNTER ...................................................................... 293
14.1 Overview of Watch Counter .............................................................................................
14.2 Configuration of Watch Counter ......................................................................................
14.3 Registers of Watch Counter ............................................................................................
14.3.1 Watch Counter Data Register (WCDR) ......................................................................
14.3.2 Watch Counter Control Register (WCSR) ..................................................................
14.4 Interrupts of Watch Counter ............................................................................................
14.5 Operations of Watch Counter and Setting Procedure Example ......................................
14.6 Notes on Using Watch Counter .......................................................................................
14.7 Sample Settings for Watch Counter ................................................................................
294
295
297
298
299
301
302
304
305
CHAPTER 15 WILD REGISTER FUNCTION ...................................................... 307
15.1 Overview of Wild Register Function ................................................................................
15.2 Configuration of Wild Register Function ..........................................................................
15.3 Registers of Wild Register Function ................................................................................
15.3.1 Wild Register Data Setting Registers (WRDR0 to WRDR2) ......................................
15.3.2 Wild Register Address Setting Registers (WRAR0 to WRAR2) .................................
15.3.3 Wild Register Address Compare Enable Register (WREN) .......................................
15.3.4 Wild Register Data Test Setting Register (WROR) ....................................................
15.4 Operations of Wild Register Function ..............................................................................
15.5 Typical Hardware Connection Example ..........................................................................
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308
309
311
313
314
315
316
317
318
CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT ............................................. 319
16.1 Overview of External Interrupt Circuit ..............................................................................
16.2 Configuration of External Interrupt Circuit .......................................................................
16.3 Channels of External Interrupt Circuit ..............................................................................
16.4 Pins of External Interrupt Circuit ......................................................................................
16.5 Registers of External Interrupt Circuit ..............................................................................
16.5.1 External Interrupt Control Register (EIC00) ................................................................
16.6 Interrupts of External Interrupt Circuit ..............................................................................
16.7 Operations of External Interrupt Circuit and Setting Procedure Example .......................
16.8 Notes on Using External Interrupt Circuit ........................................................................
16.9 Sample Settings for External Interrupt Circuit .................................................................
320
321
322
323
326
327
329
330
332
333
CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT ..................................... 335
17.1 Overview of Interrupt Pin Selection Circuit ......................................................................
17.2 Configuration of Interrupt Pin Selection Circuit ................................................................
17.3 Pins of Interrupt Pin Selection Circuit ..............................................................................
17.4 Register of Interrupt Pin Selection Circuit ........................................................................
17.4.1 Interrupt Pin Selection Circuit Control Register (WICR) .............................................
17.5 Operation of Interrupt Pin Selection Circuit .....................................................................
17.6 Notes on Using Interrupt Pin Selection Circuit ................................................................
336
337
338
339
340
342
343
CHAPTER 18 8/16-BIT COMPOSITE TIMER ..................................................... 345
18.1 Overview of 8/16-bit Composite Timer ............................................................................
18.2 Configuration of 8/16-bit Composite Timer ......................................................................
18.3 Channels of 8/16-bit Composite Timer ............................................................................
18.4 Pins of 8/16-bit Composite Timer ....................................................................................
18.5 Registers of 8/16-bit Composite Timer ............................................................................
18.5.1 8/16-bit Composite Timer 00/01 Status Control Register 0 (T00CR0/T01CR0) .........
18.5.2 8/16-bit Composite Timer 10/11 Status Control Register 0 (T10CR0/T11CR0) .........
18.5.3 8/16-bit Composite Timer 00/01 Status Control Register 1 (T00CR1/T01CR1) .........
18.5.4 8/16-bit Composite Timer 10/11 Status Control Register 1 (T10CR1/T11CR1) .........
18.5.5 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0) ..................
18.5.6 8/16-bit Composite Timer 10/11 Timer Mode Control Register (TMCR1) ..................
18.5.7 8/16-bit Composite Timer 00/01 Data Register (T00DR/T01DR) ...............................
18.5.8 8/16-bit Composite Timer 10/11 Data Register (T10DR/T11DR) ...............................
18.6 Interrupts of 8/16-bit Composite Timer ............................................................................
18.7 Operation of Interval Timer Function (One-shot Mode) ...................................................
18.8 Operation of Interval Timer Function (Continuous Mode) ...............................................
18.9 Operation of Interval Timer Function (Free-run Mode) ....................................................
18.10 Operation of PWM Timer Function (Fixed-cycle Mode) ..................................................
18.11 Operation of PWM Timer Function (Variable-cycle Mode) ..............................................
18.12 Operation of PWC Timer Function ..................................................................................
18.13 Operation of Input Capture Function ...............................................................................
18.14 Operation of Noise Filter ..................................................................................................
18.15 States in Each Mode during Operation ............................................................................
18.16 Notes on Using 8/16-bit Composite Timer .......................................................................
346
348
352
353
360
362
365
368
371
374
377
380
383
386
389
392
395
398
402
406
410
414
415
417
CHAPTER 19 16-BIT RELOAD TIMER .............................................................. 419
19.1
Overview of 16-bit Reload Timer ..................................................................................... 420
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19.2 Configuration of 16-bit Reload Timer ...............................................................................
19.3 Channels of 16-bit Reload Timer .....................................................................................
19.4 Pins of 16-bit Reload Timer .............................................................................................
19.5 Registers of 16-bit Reload Timer .....................................................................................
19.5.1 16-bit Reload Timer Control Status Register Upper (TMCSRH0) ..............................
19.5.2 16-bit Reload Timer Control Status Register Lower (TMCSRL0) ...............................
19.5.3 16-bit Reload Timer Timer Register Upper (TMRH0)/Lower (TMRL0) .......................
19.5.4 16-bit Reload Timer Reload Register Upper (TMRLRH0)/Lower (TMRLRL0) ...........
19.6 Interrupts of 16-bit Reload Timer .....................................................................................
19.7 Operations of 16-bit Reload Timer and Setting Procedure Example ...............................
19.7.1 Internal Clock Mode ....................................................................................................
19.7.2 Event Count Mode ......................................................................................................
19.8 Notes on Using 16-bit Reload Timer ...............................................................................
19.9 Sample Settings for 16-bit Reload Timer .........................................................................
422
424
425
428
429
431
433
434
435
436
438
442
444
445
CHAPTER 20 EVENT COUNTER ....................................................................... 449
20.1 Overview of Event Counter ..............................................................................................
20.2 Configuration of Event Counter .......................................................................................
20.3 Register of Event Counter ...............................................................................................
20.3.1 Event Counter Control Register (EVCR) ....................................................................
20.4 Operation of Event Counter Operation Mode ..................................................................
20.5 Setting Procedure Example .............................................................................................
20.6 Frequency Measurement Range and Precision ..............................................................
20.7 Notes on Using Event Counter ........................................................................................
450
451
452
453
455
457
458
459
CHAPTER 21 8/16-BIT PPG ............................................................................... 461
21.1 Overview of 8/16-bit PPG ................................................................................................
21.2 Configuration of 8/16-bit PPG ..........................................................................................
21.3 Channels of 8/16-bit PPG ................................................................................................
21.4 Pins of 8/16-bit PPG ........................................................................................................
21.5 Registers of 8/16-bit PPG ................................................................................................
21.5.1 8/16-bit PPG Timer 01 Control Register (PC01) ........................................................
21.5.2 8/16-bit PPG Timer 00 Control Register (PC00) ........................................................
21.5.3 8/16-bit PPG Timer 00/01 Cycle Setup Buffer Register (PPS01, PPS00) ..................
21.5.4 8/16-bit PPG Timer 00/01 Duty Setup Buffer Register (PDS01, PDS00) ...................
21.5.5 8/16-bit PPG Start Register (PPGS) ...........................................................................
21.5.6 8/16-bit PPG Output Inversion Register (REVC) ........................................................
21.6 Interrupts of 8/16-bit PPG ................................................................................................
21.7 Operations of 8/16-bit PPG and Setting Procedure Example ..........................................
21.7.1 8-bit PPG Independent Mode .....................................................................................
21.7.2 8-bit Prescaler + 8-bit PPG Mode ...............................................................................
21.7.3 16-bit PPG Mode ........................................................................................................
21.8 Notes on Using 8/16-bit PPG ..........................................................................................
21.9 Sample Settings for 8/16-bit PPG Timer .........................................................................
462
463
465
466
468
469
471
473
474
475
476
477
478
479
481
483
485
486
CHAPTER 22 UART/SIO ..................................................................................... 489
22.1
22.2
22.3
Overview of UART/SIO .................................................................................................... 490
Configuration of UART/SIO ............................................................................................. 491
Channels of UART/SIO ................................................................................................... 493
viii
22.4 Pins of UART/SIO ............................................................................................................
22.5 Registers of UART/SIO ...................................................................................................
22.5.1 UART/SIO Serial Mode Control Register 1 (SMC10) .................................................
22.5.2 UART/SIO Serial Mode Control Register 2 (SMC20) .................................................
22.5.3 UART/SIO Serial Status Register (SSR0) ..................................................................
22.5.4 UART/SIO Serial Input Data Register (RDR0) ...........................................................
22.5.5 UART/SIO Serial Output Data Register (TDR0) .........................................................
22.6 Interrupts of UART/SIO ...................................................................................................
22.7 Operations of UART/SIO and Setting Procedure Example .............................................
22.7.1 Operations in Operation Mode 0 ................................................................................
22.7.2 Operations in Operation Mode 1 ................................................................................
22.8 Sample Settings for UART/SIO .......................................................................................
494
497
498
500
502
504
505
506
508
509
516
522
CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR ................ 527
23.1 Overview of UART/SIO Dedicated Baud Rate Generator ...............................................
23.2 Channels of UART/SIO Dedicated Baud Rate Generator ...............................................
23.3 Registers of UART/SIO Dedicated Baud Rate Generator ...............................................
23.3.1 UART/SIO Dedicated Baud Rate Generator Prescaler Select Register (PSSR0) .....
23.3.2 UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register (BRSR0) ..
23.4 Operations of UART/SIO Dedicated Baud Rate Generator .............................................
528
529
530
531
532
533
CHAPTER 24 I2C ................................................................................................. 535
24.1 Overview of I2C ...............................................................................................................
24.2 I2C Configuration .............................................................................................................
24.3 I2C Channel .....................................................................................................................
24.4 Pins of I2C Bus Interface .................................................................................................
24.5 Registers of I2C ...............................................................................................................
24.5.1 I2C Bus Control Registers (IBCR00, IBCR10) ............................................................
24.5.2 I2C Bus Status Register (IBSR0) ................................................................................
24.5.3 I2C Data Register (IDDR0) .........................................................................................
24.5.4 I2C Address Register (IAAR0) ....................................................................................
24.5.5 I2C Clock Control Register (ICCR0) ...........................................................................
24.6 I2C Interrupts ...................................................................................................................
24.7 Operations of I2C and Setting Procedure Example .........................................................
24.7.1 l2C Interface ................................................................................................................
24.7.2 Function to Wake-up MCU from Standby Mode .........................................................
24.8 Notes on Using I2C Interface ...........................................................................................
24.9 Sample Settings for I2C ...................................................................................................
536
537
541
542
544
545
551
553
554
555
557
560
561
569
571
573
CHAPTER 25 8/10-BIT A/D CONVERTER ......................................................... 577
25.1 Overview of 8/10-bit A/D Converter .................................................................................
25.2 Configuration of 8/10-bit A/D Converter ..........................................................................
25.3 Pins of 8/10-bit A/D Converter .........................................................................................
25.4 Registers of 8/10-bit A/D Converter .................................................................................
25.4.1 8/10-bit A/D Converter Control Register 1 (ADC1) .....................................................
25.4.2 8/10-bit A/D Converter Control Register 2 (ADC2) .....................................................
25.4.3 8/10-bit A/D Converter Data Registers Upper/Lower (ADDH/ADDL) .........................
25.5 Interrupts of 8/10-bit A/D Converter .................................................................................
25.6 Operations of 8/10-bit A/D Converter and Setting Procedure Example ..........................
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579
581
584
585
587
589
590
591
25.7
25.8
Notes on Using 8/10-bit A/D Converter ........................................................................... 594
Sample Settings for 8/10-bit A/D Converter .................................................................... 596
CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT ........................ 599
26.1
26.2
26.3
26.4
Overview of Low-voltage Detection Reset Circuit ...........................................................
Configuration of Low-voltage Detection Reset Circuit .....................................................
Pins of Low-voltage Detection Reset Circuit ...................................................................
Operation of Low-voltage Detection Reset Circuit ...........................................................
600
601
602
603
CHAPTER 27 CLOCK SUPERVISOR COUNTER .............................................. 605
27.1 Overview of Clock Supervisor Counter ............................................................................
27.2 Configuration of Clock Supervisor Counter .....................................................................
27.3 Registers of Clock Supervisor Counter ...........................................................................
27.3.1 Clock Monitoring Data Register (CMDR) ....................................................................
27.3.2 Clock Monitoring Control Register (CMCR) ................................................................
27.4 Operations of Clock Supervisor Counter .........................................................................
27.5 Notes on Using Clock Supervisor Counter ......................................................................
606
607
609
610
611
613
619
CHAPTER 28 LCD CONTROLLER (MB95410H SERIES) ................................. 621
28.1 Overview of LCD Controller .............................................................................................
28.2 Configuration of LCD Controller ......................................................................................
28.2.1 Internal Divider Resistors for LCD Controller .............................................................
28.2.2 External Divider Resistors for LCD Controller ............................................................
28.3 Pins of LCD Controller .....................................................................................................
28.4 Registers of LCD Controller .............................................................................................
28.4.1 LCDC Control Register 1 (LCDCC1) ..........................................................................
28.4.2 LCDC Control Register 2 (LCDCC2) ..........................................................................
28.4.3 LCDC Enable Register 1 (LCDCE1) ...........................................................................
28.4.4 LCDC Enable Register 2 (LCDCE2) ...........................................................................
28.4.5 LCDC Enable Register 3 to LCDC Enable Register 6 (LCDCE3 to LCDCE6) ...........
28.4.6 LCDCE Enable Register 7 (LCDCE7) ........................................................................
28.4.7 LCDC Blinking Setting Register 1, LCDC Blinking Setting Register 2
(LCDCB1, LCDCB2) ...................................................................................................
28.5 LCD Controller Display RAM ...........................................................................................
28.6 Interrupts of LCD Controller .............................................................................................
28.7 Operations of LCD Controller ..........................................................................................
28.7.1 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/2 Bias, 1/2 Duty) .....................................................................................................
28.7.2 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/3 Bias, 1/3 Duty) .....................................................................................................
28.7.3 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/3 Bias, 1/4 Duty) .....................................................................................................
28.7.4 Output Waveform in LCD Controller Operation in 8 COM Mode
(1/4 Bias, 1/8 Duty) .....................................................................................................
28.7.5 Output Waveform in LCD Controller Operation in 8 COM Mode
(1/3 Bias, 1/8 Duty) .....................................................................................................
28.8 Notes on Using LCD Controller .......................................................................................
622
623
626
630
632
636
638
640
642
644
646
647
649
650
652
653
658
660
662
664
666
668
CHAPTER 29 LCD CONTROLLER (MB95470H SERIES) ................................. 669
29.1
Overview of LCD Controller ............................................................................................. 670
x
29.2 Configuration of LCD Controller ......................................................................................
29.2.1 Internal Divider Resistors for LCD Controller .............................................................
29.2.2 External Divider Resistors for LCD Controller ............................................................
29.3 Pins of LCD Controller .....................................................................................................
29.4 Registers of LCD Controller .............................................................................................
29.4.1 LCDC Control Register 1 (LCDCC1) ..........................................................................
29.4.2 LCDC Control Register 2 (LCDCC2) ..........................................................................
29.4.3 LCDC Enable Register 1 (LCDCE1) ...........................................................................
29.4.4 LCDC Enable Register 2 (LCDCE2) ...........................................................................
29.4.5 LCDC Enable Register 3 to LCDC Enable Register 5 (LCDCE3 to LCDCE5) ...........
29.4.6 LCDCE Enable Register 6 (LCDCE6) ........................................................................
29.4.7 LCDC Blinking Setting Register 1, LCDC Blinking Setting Register 2
(LCDCB1, LCDCB2) ...................................................................................................
29.5 LCD Controller Display RAM ...........................................................................................
29.6 Interrupts of LCD Controller .............................................................................................
29.7 Operations of LCD Controller ..........................................................................................
29.7.1 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/2 Bias, 1/2 Duty) .....................................................................................................
29.7.2 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/3 Bias, 1/3 Duty) .....................................................................................................
29.7.3 Output Waveform in LCD Controller Operation in 4 COM Mode
(1/3 Bias, 1/4 Duty) .....................................................................................................
29.7.4 Output Waveform in LCD Controller Operation in 8 COM Mode
(1/4 Bias, 1/8 Duty) .....................................................................................................
29.7.5 Output Waveform in LCD Controller Operation in 8 COM Mode
(1/3 Bias, 1/8 Duty) .....................................................................................................
29.8 Notes on Using LCD Controller .......................................................................................
CHAPTER 30
671
674
678
680
686
688
690
692
694
696
697
699
700
702
703
708
710
712
714
716
718
DUAL OPERATION FLASH MEMORY ...................................... 719
30.1 Overview of Dual Operation Flash Memory .....................................................................
30.2 Sector/Bank Configuration of Flash Memory ...................................................................
30.3 Registers of Flash Memory ..............................................................................................
30.3.1 Flash Memory Status Register 2 (FSR2) ....................................................................
30.3.2 Flash Memory Status Register (FSR) .........................................................................
30.3.3 Flash Memory Sector Write Control Register 0 (SWRE0) ..........................................
30.3.4 Flash Memory Status Register 3 (FSR3) ....................................................................
30.4 Starting the Flash Memory Automatic Algorithm .............................................................
30.5 Checking Automatic Algorithm Execution Status ............................................................
30.5.1 Data Polling Flag (DQ7) .............................................................................................
30.5.2 Toggle Bit Flag (DQ6) .................................................................................................
30.5.3 Execution Timeout Flag (DQ5) ...................................................................................
30.5.4 Sector Erase Timer Flag (DQ3) ..................................................................................
30.6 Writing/Erasing Flash Memory ........................................................................................
30.6.1 Placing Flash Memory in the Read/Reset State .........................................................
30.6.2 Writing Data to Flash Memory ....................................................................................
30.6.3 Erasing All Data from Flash Memory (Chip Erase) .....................................................
30.6.4 Erasing Arbitrary Data from Flash Memory (Sector Erase) ........................................
30.6.5 Suspending Sector Erasing from Flash Memory ........................................................
30.6.6 Resuming Sector Erasing from Flash Memory ...........................................................
30.7 Operations of Dual Operation Flash Memory ..................................................................
xi
720
722
723
724
727
730
734
741
743
745
747
748
749
750
751
752
754
755
757
758
759
30.8
30.9
Flash Security .................................................................................................................. 761
Notes on Using Dual Operation Flash Memory ............................................................... 762
CHAPTER 31 EXAMPLE OF SERIAL PROGRAMMING CONNECTION .......... 763
31.1
31.2
Basic Configuration of Serial Programming Connection ................................................. 764
Example of Serial Programming Connection ................................................................... 766
CHAPTER 32 NON-VOLATILE REGISTER (NVR) FUNCTION ......................... 769
32.1 Overview of NVR Interface ..............................................................................................
32.2 Configuration of NVR Interface ........................................................................................
32.3 Registers of NVR Interface ..............................................................................................
32.3.1 Main CR Clock Trimming Register (Upper) (CRTH) ...................................................
32.3.2 Main CR Clock Trimming Register (Lower) (CRTL) ...................................................
32.3.3 Watchdog Timer Selection ID Registers (WDTH,WDTL) ...........................................
32.4 Notes on Main CR Clock Trimming .................................................................................
32.5 Notes on Using NVR .......................................................................................................
770
771
772
773
775
776
778
780
CHAPTER 33 VOLTAGE COMPARATOR ......................................................... 781
33.1 Overview of Voltage Comparator ....................................................................................
33.2 Configuration of Voltage Comparator ..............................................................................
33.3 Pins of Voltage Comparator ............................................................................................
33.4 Register of Voltage Comparator ......................................................................................
33.4.1 Voltage Comparator Control Register (CMR0) ...........................................................
33.5 Interrupts of Voltage Comparator ....................................................................................
33.6 Operations of Voltage Comparator ..................................................................................
782
783
785
787
788
790
791
CHAPTER 34 SYSTEM CONFIGURATION CONTROLLER .............................. 793
34.1
34.2
34.3
Overview of System Configuration Register (SYSC) ....................................................... 794
System Configuration Register (SYSC) ........................................................................... 795
Notes on Using Controller ............................................................................................... 797
APPENDIX ............................................................................................................. 799
APPENDIX A I/O Maps ...............................................................................................................
APPENDIX B Table of Interrupt Sources ....................................................................................
APPENDIX C Memory Maps .......................................................................................................
APPENDIX D Pin States of MB95410H/470H Series ..................................................................
APPENDIX E Instruction Overview .............................................................................................
E.1 Addressing ......................................................................................................................
E.2 Special Instruction ...........................................................................................................
E.3 Bit Manipulation Instructions (SETB, CLRB) ...................................................................
E.4 F2MC-8FX Instructions ....................................................................................................
E.5 Instruction Map ................................................................................................................
APPENDIX F Mask Options ........................................................................................................
800
812
813
814
819
822
826
830
831
834
835
Register Index ........................................................................................................837
Pin Function Index .................................................................................................841
xii
Interrupt Vector Index ............................................................................................843
xiii
xiv
Major revisions in this edition
A change on a page is indicated by a vertical line drawn on the left of that page.
Page
4
5
8
21
26
28
31
39
Revisions (For details, see their respective pages.)
Revised the family name.
F2MC-8FX → New 8FX
CHAPTER 1 OVERVIEW
Added the section "● Power-on reset".
1.1 Features of MB95410H/470H
Series
■ Features of MB95410H/470H
Series
1.2 Product Line-up of
Renamed the parameter "ROM capacity" to "Flash memory
MB95410H/470H Series
capacity".
■ Product Line-up of MB95410H/ Added the parameter "Power-on reset".
470H Series
Table 1.2-1
1.2 Product Line-up of
Renamed the parameter "ROM capacity" to "Flash memory
MB95410H/470H Series
capacity".
■ Product Line-up of MB95410H/ Added the parameter "Power-on reset".
470H Series
Table 1.2-2
1.7 Pin Functions
Corrected details of the function of the RST pin.
External reset pin
■ Pin Functions (MB95410H
→
Series)
Reset pin
Table 1.7-1
Dedicated reset pin for MB95F414H/F416H/F418H
1.7 Pin Functions
Corrected details of the function of the TO01 pin.
■ Pin Functions (MB95470H
8/16-bit composite timer ch. 0 clock output pin
Series)
→
Table 1.7-2
8/16-bit composite timer ch. 0 output pin
Corrected details of the function of the RST pin.
Reset pin
→
Reset pin
Dedicated reset pin for MB95F474H/F476H/F478H
1.8 I/O Circuit Types
Corrected the cross reference in the section summary.
Table 1.8-1
→
Table 1.7-1 and Table 1.7-2
CHAPTER 2 NOTES ON DEVICE Revised details of "• DBG pin".
HANDLING
Revised details of "• RST pin".
2.1 Notes on Device Handling
■ Pin Connection
2.1 Notes on Device Handling
Corrected the following statement.
■ Pin Connection
The bypass capacitor for the VCC pin must have a capacitance
• C pin
larger than CS.
The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS.
42
CHAPTER 3 MEMORY SPACE
3.1 Memory Space
Added "an extended I/O area" to the section summary.
xv
Page
62
66
68
69
72
81
82
83
Revisions (For details, see their respective pages.)
CHAPTER 6 CLOCK
Corrected the following content.
CONTROLLER
This device has four source clocks:
6.1 Overview of Clock Controller →
■ Overview of Clock Controller
This device has five source clocks:
6.1 Overview of Clock Controller Corrected the following statement.
■ Clock Modes
There are five clock modes: main clock (or main PLL clock)
mode, main CR clock mode, subclock mode, and sub-CR
clock mode.
→
There are five clock modes: main clock mode, main PLL
clock mode, main CR clock mode, subclock mode and sub-CR
clock mode.
Revised Table 6.1-1.
6.1 Overview of Clock Controller Renamed the parameter "ROM" to "Flash memory".
■ Combinations of Clock Mode and
Standby Mode
Table 6.1-4
6.1 Overview of Clock Controller Renamed the parameter "ROM" to "Flash memory".
■ Combinations of Clock Mode and
Standby Mode
Table 6.1-5
6.3 System Clock Control Register Corrected the initial value of the SYCC register.
(SYCC)
0000X0011B → 0000X011B
■ Configuration of System Clock
Control Register (SYCC)
Figure 6.3-1
6.7 System Clock Control Register Corrected details of the MOSCE bit in the SYCC2 register.
2 (SYCC2)
■ Configuration of System Clock
Control Register 2 (SYCC2)
Figure 6.7-1
6.7 System Clock Control Register Revised the name of the MOSCE bit.
2 (SYCC2)
Main clock oscillation enable bit
■ Configuration of System Clock
→
Control Register 2 (SYCC2)
Main clock (or main PLL clock) oscillation enable bit
Table 6.7-1
6.8 Clock Modes
Corrected the following statement in the section summary.
There are five clock modes: main clock (or main PLL clock)
mode, main CR clock mode, subclock mode and sub-CR clock
mode.
→
There are five clock modes: main clock mode, main PLL
clock mode, main CR clock mode, subclock mode and sub-CR
clock mode.
6.8 Clock Modes
Corrected the following statement.
■ Operations in Subclock Mode
While the device is operating in subclock clock (or main PLL
clock) mode, it can be set to transit to one of the following
standby mode: sleep mode, stop mode, or watch mode.
→
While the device is operating in subclock clock mode, it can
be set to transit to one of the following standby mode: sleep
mode, stop mode, or watch mode.
xvi
Page
84
95
97
98
99
102
103
106
107
108
130
142
Revisions (For details, see their respective pages.)
6.8 Clock Modes
Corrected the following statement.
■ Clock Mode State Transition Dia- There are five clock modes: main clock (or main PLL clock)
gram
mode, main CR clock mode, subclock mode and sub-CR clock
mode.
→
There are five clock modes: main clock mode, main PLL
clock mode, main CR clock mode, subclock mode and sub-CR
clock mode.
6.9.5 Watch Mode
Corrected the following statement in the section summary.
In watch mode, only the subclock, the sub-CR clock and the
watch prescaler operate.
→
In watch mode, only the subclock, the sub-CR clock, the
watch prescaler and the LCD controller operate.
6.11 Overview of Prescaler
Added a remark on FCH.
■ Prescaler
6.12 Configuration of Prescaler
Added a remark on FCH.
■ Block Diagram of Prescaler
Figure 6.12-1
6.12 Configuration of Prescaler
Added a remark on FCH.
■ Block Diagram of Prescaler
6.13 Operation of Prescaler
Added a remark on FCH.
■ Operation of Prescaler
CHAPTER 7 RESET
Corrected the following statement.
7.1 Reset Operation
There are four reset sources for the reset.
■ Reset Sources
→
There are five reset sources for the reset.
Revised Table 7.1-1.
Added the section "● Power-on reset".
Deleted the section "● Power-on reset/low-voltage detection
reset (optional)".
Added the section "● Low-voltage detection reset (optional)".
7.2 Reset Source Register (RSRR) Corrected the initial value.
■ Configuration of Reset Source
XXXXXXXXB → 000XXXXXB
Register (RSRR)
Figure 7.2-1
7.2 Reset Source Register (RSRR) Corrected the following statement in details of the function of
■ Configuration of Reset Source
the PONR bit.
Register (RSRR)
The low-voltage detection reset function is available only in
Table 7.2-1
certain products.
→
The low-voltage detection reset function is only available on
MB95F414K/F416K/F418K/F474K/F476K/F478K.
7.2 Reset Source Register (RSRR) Revised Table 7.2-2.
■ State of Reset Source Register
(RSRR)
CHAPTER 9 I/O PORTS
Deleted the following statement.
(MB95410H SERIES)
In addition, set the corresponding bit in the PUL register to
9.2.2 Operations of Port 0
"0".
■ Operations of Port 0
● Operation as an analog input pin
9.4.2 Operations of Port 2
Corrected details of the section "● Operation as an analog
■ Operations of Port 2
input pin".
xvii
Page
146
148
151
156
157
161
166
171
176
181
182
183
186
191
195
Revisions (For details, see their respective pages.)
9.5.2 Operations of Port 4
Deleted the following statement.
■ Operations of Port 4
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
9.6 Port 5
Corrected the shared peripheral function of the P52/TI0/TO00
■ Port 5 Pins
pin.
Table 9.6-1
TI0: 16-bit reload timer output
→
TI0: 16-bit reload timer input
9.6.2 Operations of Port 5
Added the following statement.
■ Operations of Port 5
For a pin shared with other peripheral functions, disable the
● Operation as an input port
output of such peripheral functions.
9.7.2 Operations of Port 6
Deleted the following statement.
■ Operations of Port 6
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
9.7.2 Operations of Port 6
Deleted the section "● Operation as a peripheral function out■ Operations of Port 6
put pin".
9.8.2 Operations of Port 9
Deleted the following statement.
■ Operations of Port 9
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
9.9.2 Operations of Port A
Deleted the following statement.
■ Operations of Port A
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
9.10.2 Operations of Port B
Deleted the following statement.
■ Operations of Port B
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
9.10.2 Operations of Port B
Deleted the section "● Operation as a peripheral function out■ Operations of Port B
put pin".
9.11.2 Operations of Port C
Deleted the following statement.
■ Operations of Port C
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
Added the following statement.
9.12.2 Operations of Port E
For a pin shared with other peripheral functions, disable the
■ Operations of Port E
● Operation as an input port
output of such peripheral functions.
Deleted the following statement.
9.12.2 Operations of Port E
When using the analog input shared pin as another peripheral
■ Operations of Port E
● Operation as a peripheral function function input pin, configure it as an input port, which is the
input pin
same as the operation as an input port.
9.13 Port F
Corrected the shared peripheral function of the PF2/RST pin.
RST: External reset pin
■ Port F Pins
→
Table 9.13-1
RST: Reset pin
9.13.2 Operations of Port F
Added the following statement.
■ Operations of Port F
For a pin shared with other peripheral functions, disable the
● Operation as an input port
output of such peripheral functions.
9.14.2 Operations of Port G
Added the following statement.
■ Operations of Port G
For a pin shared with other peripheral functions, disable the
● Operation as an input port
output of such peripheral functions.
CHAPTER 10 I/O PORTS
Added details of the "Port G pull-up register".
(MB95470H SERIES)
10.1 Overview of I/O Ports
■ Overview of I/O Ports
Table 10.1-1
xviii
Page
197
209
214
218
223
228
233
238
243
245
248
253
Revisions (For details, see their respective pages.)
Corrected the shared peripheral function of the P01/INT01/
AN01/SEG28/UI2/TO00 pin.
SEG36: LCDC SEG28 output
→
SEG28: LCDC SEG28 output
10.3.2 Operations of Port 1
Corrected the following statement.
■ Operations of Port 1
When changing the input level of P10, ensure that the periph● Operation of the input level select eral function (UART/SIO ch. 0 output) has been stopped.
→
register
When changing the input level of P10, ensure that all its
shared peripheral functions have been stopped.
10.4.2 Operations of Port 2
Corrected details of the section "● Operation as an analog
■ Operations of Port 2
input pin".
10.5.2 Operations of Port 6
Deleted the following statement.
■ Operations of Port 6
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
10.5.2 Operations of Port 6
Deleted the section "● Operation as a peripheral function out■ Operations of Port 6
put pin".
10.6.2 Operations of Port 9
Deleted the following statement.
■ Operations of Port 9
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
10.7.2 Operations of Port A
Deleted the following statement.
■ Operations of Port A
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
10.8.2 Operations of Port B
Deleted the following statement.
■ Operations of Port B
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
10.8.2 Operations of Port B
Deleted the section "● Operation as a peripheral function out■ Operations of Port B
put pin".
10.9.2 Operations of Port C
Deleted the following statement.
■ Operations of Port C
For a pin shared with other peripheral functions, disable the
● Operation as an output port
output of such peripheral functions.
10.9.2 Operations of Port C
Deleted the section "● Operation as a peripheral function out■ Operations of Port C
put pin".
10.10.2 Operations of Port E
Added the following statement.
■ Operations of Port E
For a pin shared with other peripheral functions, disable the
output of such peripheral functions.
● Operation as an input port
10.10.2 Operations of Port E
Deleted the following statement.
■ Operations of Port E
When using the analog input shared pin as another peripheral
● Operation as a peripheral function function input pin, configure it as an input port, which is the
input pin
same as the operation as an input port.
Corrected the shared peripheral function of the PF2/RST pin.
10.11 Port F
RST: External reset pin
■ Port F Pins
→
Table 10.11-1
RST: Reset pin
10.11.2 Operations of Port F
Added the following statement.
■ Operations of Port F
For a pin shared with other peripheral functions, disable the
● Operation as an input port
output of such peripheral functions.
10.12.2 Operations of Port G
Added the following statement.
■ Operations of Port G
For a pin shared with other peripheral functions, disable the
● Operation as an input port
output of such peripheral functions.
10.2 Port 0
■ Port 0 Pins
Table 10.2-1
xix
Page
271
274
275
294
Revisions (For details, see their respective pages.)
CHAPTER 12 HARDWARE/
Revised Figure 12.2-1.
SOFTWARE WATCHDOG TIMER
12.2 Configuration of Watchdog
Timer
■ Block Diagram of Watchdog
Timer
12.3.1 Watchdog Timer Control Reg- Added a remark on FCH.
ister (WDTC)
■ Watchdog Timer Control Register
(WDTC)
Figure 12.3-2
12.3.1 Watchdog Timer Control Reg- Added a remark on FCH.
ister (WDTC)
■ Watchdog Timer Control Register
(WDTC)
Table 12.3-1
CHAPTER 14 WATCH COUNTER Corrected the frequencies of the count clock.
14.1 Overview of Watch Counter
FCL/212 → 212/FCL
■ Watch Counter
FCL/213 → 213/FCL
Table 14.1-1
FCL/214 → 214/FCL
FCL/215 → 215/FCL
295
14.2 Configuration of Watch Coun- Corrected the frequencies of the count clock.
ter
FCL/212 → 212/FCL
■ Block Diagram of Watch Counter
FCL/213 → 213/FCL
Figure 14.2-1
FCL/214 → 214/FCL
FCL/215 → 215/FCL
303
305
343
14.5 Operations of Watch Counter
Corrected the following statement.
and Setting Procedure Example Moreover, the clock counter stops, too, when subclock oscilla■ Operation in Main Stop Mode
tion stop bit (SYCC: SUBS) of the system clock control register is set to "1".
→
Moreover, the watch counter stops, too, when the subclock
oscillation enable bit (SOSCE) in the system clock control
register 2 (SYCC2) is set to "0".
14.7 Sample Settings for Watch
Corrected the name of the ISEL bit.
Counter
watch timer initialization bit
■ Sample Settings
→
● How to enable/stop the watch
watch counter start & interrupt request enable bit
counter
CHAPTER 17 INTERRUPT PIN
Deleted the following statement.
With multiple interrupt pin selected in the WICR register
SELECTION CIRCUIT
17.6 Notes on Using Interrupt Pin
simultaneously, if any of the signal input to one of the selected
Selection Circuit
interrupt pins is "H", an input to INT00 (ch. 0) of the external
interrupt circuit will be treated as "H" (as a result of the "OR"
logic of the signals that has been input to the selected pins).
xx
Page
363
366
422
Revisions (For details, see their respective pages.)
CHAPTER 18 8/16-BIT
Added the following statement to details of the function of the
COMPOSITE TIMER
IFE bit.
18.5.1 8/16-bit Composite Timer 00/ During timer operation (T00CR1/T01CR1:STA = 1), the write
01 Status Control Register 0 access to this bit has no effect on operation. Ensure that the
(T00CR0/T01CR0)
timer has stopped before modifying this bit.
■ 8/16-bit Composite Timer 00/01 Corrected the following statement.
Status Control Register 0
Depending on the settings of the SYCC2 register, the count
(T00CR0/T01CR0)
clock from the time-base timer can be generated from either
Table 18.5-1
main clock or main CR clock.
→
Depending on the settings of the SYCC2 register, the count
clock from the time-base timer can be generated from the
main clock, the main PLL clock or the main CR clock.
18.5.2 8/16-bit Composite Timer 10/ Added the following statement to details of the function of the
11 Status Control Register 0 IFE bit.
(T10CR0/T11CR0)
During timer operation (T10CR1/T11CR1:STA = 1), the write
■ 8/16-bit Composite Timer 10/11 access to this bit has no effect on operation. Ensure that the
Status Control Register 0
timer has stopped before modifying this bit.
(T10CR0/T11CR0)
Corrected the following statement.
Table 18.5-2
Depending on the settings of the SYCC2 register, the count
clock from the time-base timer can be generated from either
main clock or main CR clock.
→
Depending on the settings of the SYCC2 register, the count
clock from the time-base timer can be generated from the
main clock, the main PLL clock or the main CR clock.
Corrected the register name of the TMRH0 and TMRL0
CHAPTER 19 16-BIT RELOAD
registers.
TIMER
16-bit timer register (TMRH0, TMRL0)
19.2 Configuration of 16-bit
→
Reload Timer
16-bit reload timer timer register (TMRH0, TMRL0)
Corrected the register name of the TMRLRH0 and TMRLRL0
registers.
16-bit reload register (TMRLRH0, TMRLRL0)
→
16-bit reload timer reload register (TMRLRH0, TMRLRL0)
Corrected the register name of the TMCSRH0 and TMCSRL0
registers.
Timer control status register (TMCSRH0, TMCSRL0)
→
16-bit reload timer control status register (TMCSRH0,
TMCSRL0)
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455
Revisions (For details, see their respective pages.)
Configuration of 16-bit
Corrected the register name of the TMRLRH0 and TMRLRL0
Reload Timer
registers.
■ Block Diagram of 16-bit Reload 16-bit reload register (TMRLRH0, TMRLRL0)
Timer
→
Figure 19.2-1
16-bit reload timer reload register (TMRLRH0, TMRLRL0)
Corrected the register name of the TMRH0 and TMRL0
registers.
16-bit timer register (TMRH0, TMRL0)
→
16-bit reload timer timer register (TMRH0, TMRL0)
Deleted "Timer control status register (TMCSR).
Added "16-bit reload timer reload register upper
(TMRLRH0)" and "16-bit reload timer reload register lower
(TMRLRL0)".
Renamed the section "● 16-bit timer register (TMRH0,
19.2 Configuration of 16-bit
TMRL0)" to "● 16-bit reload timer timer register (TMRH0,
Reload Timer
■ Block Diagram of 16-bit Reload TMRL0)".
Timer
Renamed the section "● 16-bit reload register (TMRLRH0,
TMRLRL0)" to "● 16-bit reload timer reload register
(TMRLRH0, TMRLRL0)".
Renamed the section "● Timer control status register
(TMCSRH0, TMCSRL0)" to "● 16-bit reload timer control
status register (TMCSRH0, TMCSRL0)".
19.4 Pins of 16-bit Reload Timer
Corrected the following bit number.
■ Pins of 16-bit Reload Timer
DDRE:bit5 → DDR1:bit0
● TO0 pin
19.5.1 16-bit Reload Timer Control Revised Figure 19.5-2.
Status Register Upper
(TMCSRH0)
■ 16-bit Reload Timer Control Status Register Upper (TMCSRH0)
19.8 Notes on Using 16-bit Reload Deleted the section "● Precaution when Event Counter
Timer
operates in event counter mode".
■ Notes on Using 16-bit Reload
Timer
Added the section "● Note on the event counter operating in
● Note on the event counter operatevent counter operation mode".
ing in event counter operation
mode
CHAPTER 20 EVENT COUNTER Corrected the setting of the PCS[1:0] bits in "2.".
20.2 Configuration of Event Coun- 00 → 01, 10 or 11
ter
■ Block Diagram of Event Counter
● Composite timer count clock
(CK06/CK16) selection circuit
20.4 Operation of Event Counter
Corrected the name of the operation mode of the event
Operation Mode
counter.
event counter mode
→
event counter operation mode
20.4 Operation of Event Counter
Corrected the following timer name.
Operation Mode
timer 01 → timer 11
■ Operation of Event Counter
Operation Mode
19.2
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Revisions (For details, see their respective pages.)
Operation of Event Counter
Corrected the following timer name.
Operation Mode
timer 01 → timer 11
■ Operation of Event Counter
Corrected the following interrupt name.
Operation Mode
Timer 01 compare match interrupt
Figure 20.4-2
→
Timer 11 compare match interrupt
Corrected the following timer name.
timer 01 → timer 11
20.5 Setting Procedure Example
Corrected the following bit names in 12).
■ Setting Procedure Example
C2, C1 → C2 to C0
● Initial settings
Corrected the following timer name in 13).
timer 01 → timer 11
Corrected the following timer name.
20.5 Setting Procedure Example
timer 01 → timer 11
■ Setting Procedure Example
● Interrupt process of composite
timer (timer 11)
20.7 Notes on Using Event Counter Corrected the following register names.
■ Notes on Using Event Counter
T00CR1/T01CR1 → T10CR1/T11CR1
CHAPTER 21 8/16-BIT PPG
Added a remark on FCH.
21.2 Configuration of 8/16-bit PPG
■ Block Diagram of 8/16-bit PPG
Figure 21.2-1
21.5 Registers of 8/16-bit PPG
Corrected the R/W attribute of bit7 in the PPGS register.
■ Registers of 8/16-bit PPG
R0/WX → R/W
Figure 21.5-1
Corrected the R/W attribute of bit6 in the PPGS register.
R0/WX → R/W
Corrected the R/W attribute of bit5 in the PPGS register.
R0/WX → R/W
Corrected the R/W attribute of bit4 in the PPGS register.
R0/WX → R/W
Corrected the R/W attribute of bit7 in the REVC register.
R0/WX → R/W
Corrected the R/W attribute of bit6 in the REVC register.
R0/WX → R/W
Corrected the R/W attribute of bit5 in the REVC register.
R0/WX → R/W
Corrected the R/W attribute of bit4 in the REVC register.
R0/WX → R/W
21.5.1 8/16-bit PPG Timer 01 Con- Added a remark on FCH.
trol Register (PC01)
■ 8/16-bit PPG Timer 01 Control
Register (PC01)
Figure 21.5-2
21.5.1 8/16-bit PPG Timer 01 Con- Added a remark on FCH.
trol Register (PC01)
Corrected the following statement.
■ 8/16-bit PPG Timer 01 Control
Depending on the settings of the SYCC2 register, the count
Register (PC01)
clock from the time-base timer can be generated from either
Table 21.5-1
main clock or main CR clock.
20.4
→
Depending on the settings of the SYCC2 register, the count
clock from the time-base timer can be generated from the
main clock, the main PLL clock or the main CR clock.
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Revisions (For details, see their respective pages.)
21.5.2 8/16-bit PPG Timer 00 Con- Added a remark on FCH.
trol Register (PC00)
■ 8/16-bit PPG Timer 00 Control
Register (PC00)
Figure 21.5-3
21.5.2 8/16-bit PPG Timer 00 Con- Added a remark on FCH.
trol Register (PC00)
Corrected the following statement.
■ 8/16-bit PPG Timer 00 Control
Depending on the settings of the SYCC2 register, the count
Register (PC00)
clock from the time-base timer can be generated from either
Table 21.5-2
main clock or main CR clock.
21.6 Interrupts of 8/16-bit PPG
■ Registers and Vector Table
Addresses Related to Interrupts of
8/16-bit PPG
Table 21.6-2
CHAPTER 22 UART/SIO
22.4 Pins of UART/SIO
■ Block Diagrams of Pins of
UART/SIO
22.7 Operations of UART/SIO and
Setting Procedure Example
■ Operating Description of UART/
SIO Operation Mode 1
● Reception in UART/SIO operation mode 1
22.7 Operations of UART/SIO and
Setting Procedure Example
■ Operating Description of UART/
SIO Operation Mode 1
● Transmission in UART/SIO operation mode 1
→
Depending on the settings of the SYCC2 register, the count
clock from the time-base timer can be generated from the
main clock, the main PLL clock or the main CR clock.
Corrected the name of the UART/SIO channel in the remark.
UART/SIO ch. 1 (lower) → UART/SIO ch. 1
Revised Figure 22.4-1.
Revised Figure 22.7-12.
Added a title "Figure 22.7-13 Overrun Error" to the figure
below the section "Overrun error (OVE)".
Revised Figure 22.7-15.
Deleted the following statement from the section summary.
The I2C interface supports the I2C bus specification published
by Philips.
Corrected the R/W attribute of bit5 in the IBSR0 register.
R/WX→ R0/WX
536
CHAPTER 24 I2C
24.1 Overview of I2C
544
24.5 Registers of I2C
■ Registers of I2C
Figure 24.5-1
560
Operations of I2C and Setting Deleted the following statement.
It conforms to the I2C bus specification defined by Philips.
Procedure Example
2
■ Operations of I C
● I2C interface
Deleted the following statement from the section summary.
24.7.1 I2C Interface
It conforms to the I2C bus specification defined by Philips.
561
24.7
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Revisions (For details, see their respective pages.)
Corrected the name of the INTE bit.
24.9 Sample Settings for I2C
interrupt request enable bit
■ Sample Settings
● Enabling, disabling, and clearing →
transfer completion interrupt enable bit
interrupts
Corrected the name of the INT bit.
interrupt request flag bit
→
transfer completion interrupt request flag bit
Corrected the name of the BEIE bit.
interrupt request enable bit
→
bus error interrupt request enable bit
Corrected the name of the BER bit.
interrupt request flag bit
→
bus error interrupt request flag bit
Corrected the name of the SPE bit.
interrupt request enable bit
→
STOP detection interrupt enable bit
Corrected the name of the SPF bit.
interrupt request flag bit
→
STOP detection interrupt request flag bit
2
Corrected the name of the ALE bit.
24.9 Sample Settings for I C
interrupt request enable bit
■ Sample Settings
● Enabling, disabling, and clearing →
arbitration lost interrupt enable bit
interrupts
Corrected the name of the ALF bit.
interrupt request flag bit
→
arbitration lost interrupt request flag bit
Corrected the name of the WUE bit.
interrupt request enable bit
→
MCU standby-mode wakeup function enable bit
Corrected the name of the WUF bit.
interrupt request flag bit
→
MCU standby-mode wakeup interrupt request flag bit
CHAPTER 25 8/10-BIT A/D
Corrected the following statement.
CONVERTER
The start of the reset mode, the stop mode or the watch mode
25.7 Notes on Using 8/10-bit A/D causes the A/D converter to stop and the ADMV bit to be
Converter
cleared to "0".
■ Notes on Using 8/10-bit A/D
→
Converter
A reset, or the start of the stop mode or watch mode causes the
● Notes on setting the 8/10-bit A/D A/D converter to stop and the ADMV bit to be cleared to "0".
converter with a program
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Revisions (For details, see their respective pages.)
CHAPTER 27 CLOCK
Corrected the following statement.
SUPERVISOR COUNTER
The count clock of this module can be selected from the main
27.1 Overview of Clock Supervisor oscillation clock and the sub-oscillation clock.
Counter
→
The count clock of this module can be selected from the main
oscillation clock, the main PLL clock and the suboscillation
clock.
27.2 Configuration of Clock Super- Revised Figure 27.2-1.
visor Counter
■ Block Diagram of Clock Supervisor Counter
27.2 Configuration of Clock Super- Corrected the following statement.
visor Counter
This block is used to select the counter source clock from the
■ Block Diagram of Clock Supervi- main oscillation clock and the sub-oscillation clock.
sor Counter
→
● Counter source clock selector
This block is used to select the counter source clock from the
main oscillation clock, the main PLL clock and the suboscillation clock.
Revised Figure 27.3-3.
27.3.2 Clock Monitoring Control
Register (CMCR)
■ Clock Monitoring Control Register (CMCR)
27.3.2 Clock Monitoring Control
Revised details of the function of the CMCSEL bit.
Register (CMCR)
■ Clock Monitoring Control Register (CMCR)
Table 27.3-2
27.4 Operations of Clock Supervi- Corrected the following statement.
sor Counter
The count clock of this module can be selected from the main
■ Clock Supervisor Counter
oscillation clock and the sub-oscillation clock.
● Clock Supervisor Counter Opera- →
tion 1
The count clock of this module can be selected from the main
oscillation clock, the main PLL clock and the suboscillation
clock.
CHAPTER 28 LCD CONTROLLER Added the section "● LCDC blinking setting register 1
(MB95410H SERIES)
(LCDCB1), LCDC blinking setting register 2 (LCDCB2)".
28.2 Configuration of LCD Controller
■ LCD Controller Block Diagrams
28.2.1 Internal Divider Resistors for Corrected the following statement.
LCD Controller
To use only the internal divider resistors without connecting
■ Internal Divider Resistors
the external divider when using internal split resistors
→
To use only the internal divider resistors without any external
divider resistor
28.2.1 Internal Divider Resistors for Corrected the following statement.
LCD Controller
Figure 28.2-5 shows an example of connecting a VR to inter■ Use of Internal Divider Resistors nal divider resistors for brightness control.
and Brightness Control
→
Figure 28.2-5 illustrates connecting a VR to the V4 pin to control brightness.
Revised Figure 28.2-4.
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635
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643
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651
Revisions (For details, see their respective pages.)
28.2.1 Internal Divider Resistors for Revised the figure title from "Brightness Control with Internal
LCD Controller
Divider Resistors Used" to "Brightness Control by Connecting
■ Use of Internal Divider Resistors VR to V4 Pin".
and Brightness Control
Figure 28.2-5
28.2.2 External Divider Resistors for Corrected the following cross-reference.
LCD Controller
Figure 28.2-1 → Table 28.2-1
■ External Divider Resistors
Revised Figure 28.2-6.
28.2.2 External Divider Resistors for Revised Figure 28.2-7.
LCD Controller
■ Use of External Divider Resistors
28.3 Pins of LCD Controller
Deleted the following statement.
■ Pins of LCD Controller
In addition, COM0 to COM3 can also function as general-pur● COM0 to COM7 pins
pose I/O ports.
28.3 Pins of LCD Controller
Corrected Figure 28.3-4.
■ Block Diagrams of Pins of LCD Corrected Figure 28.3-5.
Controller
Corrected Figure 28.3-6.
28.4.1 LCDC Control Register 1
Revised details of the FP1 and FP0 bits.
(LCDCC1)
■ LCDC Control Register 1
(LCDCC1)
Figure 28.4-2
28.4.1 LCDC Control Register 1
Revised details of the function of the LCDEN bit.
(LCDCC1)
■ LCDC Control Register 1
Revised details of the function of the VSEL bit.
(LCDCC1)
Table 28.4-1
Revised Figure 28.4-4.
28.4.3 LCDC Enable Register 1
(LCDCE1)
■ LCDC Enable Register 1
(LCDCE1)
28.4.3 LCDC Enable Register 1
Revised details of the function of the VE4 bit.
(LCDCE1)
Revised details of the function of the VE3 bit.
■ LCDC Enable Register 1
Revised details of the function of the VE2 bit.
(LCDCE1)
Revised details of the function of the VE1 bit.
Table 28.4-3
Revised details of the function of the VE0 bit.
Revised details of "Note".
28.4.3 LCDC Enable Register 1
(LCDCE1)
■ LCDC Enable Register 1
(LCDCE1)
28.4.7 LCDC Blinking Setting Reg- Corrected the range of numbers represented by "m".
ister 1, LCDC Blinking Set0 to 8
ting Register 2 (LCDCB1,
→
LCDCB2)
0 to 7
■ LCDC Blinking Setting Register
1, LCDC Blinking Setting Register 2 (LCDCB1, LCDCB2)
Figure 28.4-8.
28.5 LCD Controller Display
Corrected the address of "n" in "Note".
RAM
0FCDH → 0FBDH
■ Display RAM and Output Pins
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680
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684
685
688
Revisions (For details, see their respective pages.)
28.7 Operations of LCD Controller Corrected the value to be set to the PICTL bit.
■ Operations of LCD Controller
0→1
Figure 28.7-2
28.7 Operations of LCD Controller Corrected the value to be set to the PICTL bit.
■ Operations of LCD Controller
0→1
Figure 28.7-4
CHAPTER 29 LCD CONTROLLER Added the section "● LCDC blinking setting register 1
(MB95470H SERIES)
(LCDCB1), LCDC blinking setting register 2 (LCDCB2)".
29.2 Configuration of LCD Controller
■ LCD Controller Block Diagrams
29.2.1 Internal Divider Resistors for Corrected the following content.
LCD Controller
To use only the internal divider resistors without connecting
■ Internal Divider Resistors
the external divider when using internal split resistors
→
To use only the internal divider resistors without any external
divider resistor
29.2.1 Internal Divider Resistors for Corrected the following content.
Figure 29.2-5 shows an example of connecting a VR to interLCD Controller
■ Use of Internal Divider Resistors nal divider resistors for brightness control.
→
and Brightness Control
Figure 29.2-5 illustrates connecting a VR to the V4 pin to control brightness.
Revised Figure 29.2-4.
29.2.1 Internal Divider Resistors for Revised the figure title from "Brightness Control with Internal
LCD Controller
Divider Resistors Used" to "Brightness Control by Connecting
■ Use of Internal Divider Resistors VR to V4 Pin".
and Brightness Control
Figure 29.2-5
29.2.2 External Divider Resistors for Corrected a cross-reference.
LCD Controller
Figure 29.2-1 → Table 29.2-1
■ External Divider Resistors
Revised Figure 29.2-6.
29.2.2 External Divider Resistors for Added the legend of "X".
LCD Controller
■ External Divider Resistors
Table 29.2-1
29.2.2 External Divider Resistors for Revised Figure 29.2-7.
LCD Controller
■ Use of External Divider Resistors
29.3 Pins of LCD Controller
Corrected a register abbreviation.
■ Pins of LCD Controller
LCDCE7 → LCDCE6
● COM0 to COM7 pins
Deleted the following statement.
In addition, COM0 to COM3 can also function as general-purpose I/O ports.
29.3 Pins of LCD Controller
Corrected Figure 29.3-5.
■ Block Diagrams of Pins of LCD Corrected Figure 29.3-6.
Controller
Corrected Figure 29.3-7.
Corrected Figure 29.3-8.
29.4.1 LCDC Control Register 1
Revised details of the FP1 and FP0 bits.
(LCDCC1)
■ LCDC Control Register 1
(LCDCC1)
Figure 29.4-2.
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701
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704
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Revisions (For details, see their respective pages.)
29.4.1 LCDC Control Register 1
Revised details of the function of the LCDEN bit.
(LCDCC1)
Revised details of the function of the VSEL bit.
■ LCDC Control Register 1
(LCDCC1)
Table 29.4-1
29.4.3 LCDC Enable Register 1
Revised Figure 29.4-4.
(LCDCE1)
■ LCDC Enable Register 1
(LCDCE1)
29.4.3 LCDC Enable Register 1
Revised details of the function of the VE4 bit.
(LCDCE1)
Revised details of the function of the VE3 bit.
■ LCDC Enable Register 1
Revised details of the function of the VE2 bit.
(LCDCE1)
Table 29.4-3
Revised details of the function of the VE1 bit.
29.4.3 LCDC Enable Register 1
(LCDCE1)
■ LCDC Enable Register 1
(LCDCE1)
29.4.5 LCDC Enable Register 3 to
LCDC Enable Register 5
(LCDCE3 to LCDCE5)
29.4.6 LCDC Enable Register 6
(LCDCE6)
29.4.7 LCDC Blinking Setting Register 1, LCDC Blinking Setting Register 2 (LCDCB1,
LCDCB2)
■ LCDC Blinking Setting Register
1, LCDC Blinking Setting Register 2 (LCDCB1, LCDCB2)
29.5 LCD Controller Display
RAM
■ Display RAM and Output Pins
29.6 Interrupts of LCD Controller
■ Register and Vector Table
Addresses Related to LCD Controller Interrupts
Figure 29.6-1
29.7 Operations of LCD Controller
■ Operations of LCD Controller
Figure 29.7-2
29.7 Operations of LCD Controller
■ Operations of LCD Controller
Figure 29.7-4
CHAPTER 30 DUAL OPERATION
FLASH MEMORY
30.1 Overview of Dual Operation
Flash Memory
30.3 Registers of Flash Memory
■ Registers of Flash Memory
Figure 30.3-1
Revised details of "Note".
Corrected the segment output pin name from "SEG31" to
"SEG23" in the section summary.
Corrected the segment output pin names from "SEG32 to
SEG39" to "SEG24 to SEG31" in the section summary.
Revised Figure 29.4-8.
Corrected the address in "Note".
0FCDH → 0FBDH
Corrected the legend.
V0 to V4: Voltages of V0 to V4 pins
→
V1 to V4: Voltages of V1 to V4 pins
Corrected the value to be set to the PICTL bit.
0→1
Corrected the value to be set to the PICTL bit.
0→1
Deleted the following statement from the section summary.
The Flash memory interface circuit enables read access and
write access from the CPU to the Flash memory.
Corrected the initial value of the FSR3 register.
X0000000B → 00000000B
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Revisions (For details, see their respective pages.)
30.3.2 Flash Memory Status Register Revised Figure 30.3-4.
(FSR)
■ Flash Memory Status Register
(FSR)
30.3.4 Flash Memory Status Register Corrected the initial value.
3 (FSR3)
X0000000B → 00000000B
■ Flash Memory Status Register 3
(FSR3)
Figure 30.3-7
30.6.1 Placing Flash Memory in the Deleted the following statement.
Read/Reset State
As is the case with masked ROM, program access from the
■ Placing Flash Memory in the
CPU can be made.
Read/Reset State
CHAPTER 31 EXAMPLE OF
Added a statement related to the use of the pull-up resistor.
SERIAL PROGRAMMING
CONNECTION
31.2 Example of Serial Programming Connection
■ Example of Serial Programming
Connection
CHAPTER 32 NON-VOLATILE
Revised details of the functions of the WDTH and WDTL regREGISTER (NVR) FUNCTION
isters.
32.3.3 Watchdog Timer Selection ID
Registers (WDTH, WDTL)
■ Watchdog Timer Selection ID
Registers (WDTH, WDTL)
Figure 32.3-4
CHAPTER 33 VOLTAGE
Corrected the following content in the section summary.
COMPARATOR
The voltage comparator is used to monitor the voltages of two
33.1 Overview of Voltage Compar- analog inputs, which can be either one internal output and one
external input or two external inputs,
ator
→
The voltage comparator is used to monitor the voltages of two
analog inputs, which can be either one internal input and one
external input or two external inputs,
Revised Figure 33.2-1.
33.2 Configuration of Voltage
Comparator
■ Block Diagram of Voltage Comparator
33.4 Register of Voltage Compara- Corrected the abbreviation of the voltage comparator control
tor
register.
■ Register of Voltage Comparator CMR → CMR0
Figure 33.4-1
33.5 Interrupts of Voltage Compar- Corrected the name of the IF bit in "Note".
ator
interrupt flag bit
■ Output Edge Detection Interrupt →
output edge detection interrupt flag bit
33.6 Operations of Voltage Com- Revised the statement below Figure 33.6-1.
After the voltage comparator is activated as shown above, it
parator
has to stabilize before starting to operate.
■ Software Activation of Voltage
→
Comparator
After the voltage comparator is activated as shown above, it
has to wait for the stabilization time to elapse before starting
to operate. For details of the stabilization wait time, refer to
the data sheet of the MB95410H/470H Series.
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Page
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Revisions (For details, see their respective pages.)
CHAPTER 34 SYSTEM
Corrected the following statement.
CONFIGURATION CONTROLLER Selection of the port/reset function for the PF2/RST pin
34.1 Overview of System Configu- →
ration Register (SYSC)
Selection of the general-purpose I/O port/reset function for the
■ Functions of SYSC
PF2/RST pin
Corrected the following statement.
Selection of the port/reset function for the PG1/X0A pin and
that for the PG2/XIA pin
→
Selection of the general-purpose I/O port/reset function for the
PG1/X0A pin and that for the PG2/XIA pin
Corrected the following statement.
Selection of the port/reset function for the PF0/X0 pin and that
for the PF1/XI pin
→
Selection of the general-purpose I/O port/reset function for the
PF0/X0 pin and that for the PF1/XI pin
34.2 System Configuration Regis- Revised details of the function of the VBGRSELX bit.
ter (SYSC)
■ System Configuration Register
(SYSC)
Table 34.2-1
34.3 Notes on Using Controller
Corrected the "P21 pin" to the "CMPP pin".
■ Notes on Using Controller
● Selecting the reference voltage
for the voltage comparator
xxxi
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Revisions (For details, see their respective pages.)
APPENDIX
Corrected the initial value of the RSRR register.
APPENDIX A I/O Map
XXXXXXXXB → 000XXXXXB
■ I/O Map
Corrected the initial value of the FSR3 register.
Table A-1
X0000000 → 00000000
B
804
805
B
Corrected the register name of the BRSR0 register.
UART/SIO dedicated baud rate generator setting register ch. 0
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
Corrected the register name of the BRSR1 register.
UART/SIO dedicated baud rate generator setting register ch. 1
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
Corrected the register name of the BRSR2 register.
UART/SIO dedicated baud rate generator setting register ch. 2
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 2
Corrected the initial value of the EVCR register.
XXXXXXX0B → 00000000B
Corrected the register name of the SYSC register.
System control register
→
System configuration register
Corrected the register name of the WICR register.
Interrupt pin control register
→
Interrupt pin selection circuit control register
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Revisions (For details, see their respective pages.)
APPENDIX A I/O Map
Corrected the initial value of the RSRR register.
■ I/O Map
XXXXXXXXB → 000XXXXXB
Table A-2
Corrected the initial value of the FSR3 register.
X0000000B → 00000000B
809
Corrected the register name of the BRSR0 register.
UART/SIO dedicated baud rate generator setting register ch. 0
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
Corrected the register name of the BRSR1 register.
UART/SIO dedicated baud rate generator setting register ch. 1
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
Corrected the register name of the BRSR2 register.
UART/SIO dedicated baud rate generator setting register ch. 2
→
UART/SIO dedicated baud rate generator baud rate setting
register ch. 2
Corrected the register abbreviation of the LCDC control register 1.
LCDCC → LCDCC1
Corrected the initial value of the LCDCC1 register.
00010000B → 00000000B
810
Corrected the initial value of the EVCR register.
XXXXXXX0B → 00000000B
812
APPENDIX B Table of Interrupt
Sources
■ Table of Interrupt Sources
Table B-1
Corrected the register name of the SYSC register.
System control register
→
System configuration register
Corrected the register name of the WICR register.
Interrupt pin control register
→
Interrupt pin selection circuit control register
Corrected the interrupt source for IRQ04.
xxxiii
Page
815
816
817
818
Revisions (For details, see their respective pages.)
APPENDIX D Pin States of
Deleted "TO01" from the P11/UO0/TO01 pin.
MB95410H/470H Series
Added the states of the P17/CMPO pin.
■ Pin States in Each Mode
Added remark *11 to details of the states of the P22/SCL pin
Table D-1
and the P23/SDA pin.
Revised the remark number from *11 to *12 for the following
pins: P40/SEG21, P41/SEG20, P42/SEG19, P43/SEG18, P50/
TO01, P51/EC0, P53/TO0.
Added remark *12 to details of the states of the P52/TI0/TO00
pin.
Revised the remark number from *11 to *12 for the following
pins: PB2/SEG37, PB3/SEG38, PB4/SEG39, PC4/SEG06,
PC5/SEG07, PC6/SEG08, PC7/SEG09
Corrected the pin name "TO01" to "TO00" in *2.
Corrected the pin name "PG0/X0A" to "PG1/X0A", and
"PG1/ X1A" to "PG2/X1A" in *5.
Corrected the pin name "P90" to "P94/V0" in *7.
Added remark *11.
Revised the remark number from *11 to *12.
Revised details of remark *12.
xxxiv
CHAPTER 1
OVERVIEW
This chapter describes the features and basic
specifications of the MB95410H/470H Series.
MN702-00005-2v0-E
1.1
Features of MB95410H/470H Series
1.2
Product Line-up of MB95410H/470H Series
1.3
Differences among Products and Notes on Product
Selection
1.4
Block Diagrams of MB95410H/470H Series
1.5
Pin Assignment
1.6
Package Dimension
1.7
Pin Functions
1.8
I/O Circuit Types
FUJITSU SEMICONDUCTOR LIMITED
1
CHAPTER 1 OVERVIEW
1.1 Features of MB95410H/470H Series
1.1
MB95410H/470H Series
Features of MB95410H/470H Series
In addition to a compact instruction set, the MB95410H/470H Series is a series
of general-purpose single-chip microcontrollers with a variety of peripheral
functions.
■ Features of MB95410H/470H Series
● F2MC-8FX CPU core
Instruction set optimized for controllers
•
Multiplication and division instructions
•
16-bit arithmetic operations
•
Bit test branch instructions
•
Bit manipulation instructions, etc.
● Clock
• Selectable main clock source
- Main oscillation clock (Up to 16.25 MHz, maximum machine clock frequency is
8.125 MHz)
- External clock (Up to 32.5 MHz, maximum machine clock frequency is 16.25 MHz)
- Main CR clock (1/8/10/12.5 MHz ±2%, maximum machine clock frequency is 12.5 MHz)
- Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz)
• Selectable subclock source
- Suboscillation clock (32.768 kHz)
- External clock (32.768 kHz)
- Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
● Timer
•
8/16-bit composite timer × 2 channels
•
8/16-bit PPG × 2 channels
•
16-bit reload timer × 1 channel
•
Event counter × 1 channel
•
Time-base timer × 1 channel
•
Watch prescaler × 1 channel
● UART/SIO
•
Capable of clock asynchronous (UART) and clock synchronous (SIO) serial data transfer
•
Full duplex double buffer
● I2C
Built-in wake-up function
2
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 1 OVERVIEW
1.1 Features of MB95410H/470H Series
● External interrupt
•
Interrupt by the edge detection (rising edge, falling edge, and both edges can be selected)
•
Can be used to wake up the device from different low-power consumption modes (also
called standby modes)
● 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
● LCD controller (LCDC)
•
On MB95F414H/F414K/F416H/F416K/F418H/F418K, LCD output can be selected from
40 SEG × 4 COM and 36 SEG × 8 COM.
•
On MB95F474H/F474K/F476H/F476K/F478H/F478K, LCD output can be selected from
32 SEG × 4 COM and 28 SEG × 8 COM.
•
Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ
through software
•
Interrupt event in sync with the LCD module frame frequency
•
Blinking function
•
Inverted display function
● Low power consumption (standby) modes
•
Stop mode
•
Sleep mode
•
Watch mode
•
Time-base timer mode
● I/O port
•
•
•
•
MB95F414H/F416H/F418H (no. of I/O ports: 74)
- General-purpose I/O ports (CMOS I/O)
: 71
- General-purpose I/O ports (N-ch open drain)
:3
MB95F414K/F416K/F418K (no. of I/O ports: 75)
- General-purpose I/O ports (CMOS I/O)
: 71
- General-purpose I/O ports (N-ch open drain)
:4
MB95F474H/F476H/F478H (no. of I/O ports: 58)
- General-purpose I/O ports (CMOS I/O)
: 55
- General-purpose I/O ports (N-ch open drain)
:3
MB95F474K/F476K/F478K (no. of I/O ports: 59)
- General-purpose I/O ports (CMOS I/O)
: 55
- General-purpose I/O ports (N-ch open drain)
:4
● On-chip debug
•
1-wire serial control
•
Serial writing supported (asynchronous mode)
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
3
CHAPTER 1 OVERVIEW
1.1 Features of MB95410H/470H Series
MB95410H/470H Series
● Hardware/software watchdog timer
•
Built-in hardware watchdog timer
•
Built-in software watchdog timer
● Power-on reset
A power-on reset is generated when the power is switched on.
● Low-voltage detection reset circuit (only available on MB95F414K/F416K/F418K/F474K/
F476K/F478K)
Built-in low-voltage detector
● Clock supervisor counter
Built-in clock supervisor counter function
● Programmable port input voltage level
CMOS input level / hysteresis input level
● Dual operation Flash memory
The erase/write operation and the read operation can be executed in different banks (upper
bank/lower bank) simultaneously.
● Flash memory security function
Protects the content of the Flash memory
4
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.2 Product Line-up of MB95410H/470H Series
MB95410H/470H Series
1.2
Product Line-up of MB95410H/470H Series
Table 1.2-1 and Table 1.2-2 list the product line-up of the MB95410H/470H
Series.
■ Product Line-up of MB95410H/470H Series
Table 1.2-1 Product Line-up of MB95410H Series (1 / 3)
Part Number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Parameter
Type
Flash memory product
Clock supervisor
It supervises the main clock oscillation.
counter
Flash memory
20 Kbyte
36 Kbyte
60 Kbyte
20 Kbyte
36 Kbyte
60 Kbyte
capacity
RAM capacity
496 bytes
1008 bytes
2032 bytes
496 bytes
1008 bytes
2032 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8, and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock = 16.25 MHz)
• I/O ports
: 75
• I/O ports
: 74
General-purpose
• CMOS I/O
: 71
• CMOS I/O
: 71
I/O
• N-ch open drain : 4
• N-ch open drain : 3
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock = 4 MHz)
Hardware/
• Reset generation cycle
software
- Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
2
I C
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator
and an error detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data
transfer are enabled.
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FUJITSU SEMICONDUCTOR LIMITED
5
CHAPTER 1 OVERVIEW
1.2 Product Line-up of MB95410H/470H Series
MB95410H/470H Series
Table 1.2-1 Product Line-up of MB95410H Series (2 / 3)
Part Number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Parameter
8 channels
8-bit or 10-bit resolution can be selected.
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
•
composite timer It has built-in timer function, PWC function, PWM function and capture function.
• Count clock: it can be selected from internal clocks (7 types) and external clocks.
• It can output square wave.
• COM output: 4 or 8 (selectable)
• SEG output: 36 or 40 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 40, and the
maximum number of pixels that can be displayed 160 (4×40).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 36, and the
maximum number of pixels that can be displayed 288 (8×36).
LCD controller • LCD drive power supply (bias) pins: 5 (Max)
(LCDC)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through
software
• Interrupt event in sync with the LCD module frame frequency
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
16-bit reload
• Square waveform output
timer
• Count clock: 7 internal clocks and external clock can be selected
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter
function can be implemented. When using the event counter function, the 16-bit reload timer and
the 8/16-bit composite timer ch. 1 is unavailable
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as "8-bit PPG × 2 channels" or "16-bit PPG × 1 channel"
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock
source of 1 second and setting counter value to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Watch prescaler Eight different time intervals can be selected. (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, write/erase/erase-suspend/eraseresume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of write/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash.
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
8/10-bit A/D
converter
6
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 1 OVERVIEW
1.2 Product Line-up of MB95410H/470H Series
Table 1.2-1 Product Line-up of MB95410H Series (3 / 3)
Part Number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Parameter
Package
MN702-00005-2v0-E
FPT-80P-M37
FUJITSU SEMICONDUCTOR LIMITED
7
CHAPTER 1 OVERVIEW
1.2 Product Line-up of MB95410H/470H Series
MB95410H/470H Series
Table 1.2-2 Product Line-up of MB95470H Series (1 / 2)
Part Number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Parameter
Type
Flash memory product
Clock supervisor
It supervises the main clock oscillation.
counter
Flash memory
20 Kbyte
36 Kbyte
60 Kbyte
20 Kbyte
36 Kbyte
60 Kbyte
capacity
RAM capacity
496 bytes
1008 bytes
2032 bytes
496 bytes
1008 bytes
2032 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8, and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock = 16.25 MHz)
• I/O ports
: 59
• I/O ports
: 58
General-purpose
• CMOS I/O
: 55
• CMOS I/O
: 55
I/O
• N-ch open drain : 4
• N-ch open drain : 3
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock = 4 MHz)
Hardware/
• Reset generation cycle
- Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
2C
I
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator
and an error detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data
transfer are enabled.
8 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
•
composite timer It has built-in timer function, PWC function, PWM function and capture function.
• Count clock: it can be selected from internal clocks (7 types) and external clocks.
• It can output square wave.
8
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 1 OVERVIEW
1.2 Product Line-up of MB95410H/470H Series
Table 1.2-2 Product Line-up of MB95470H Series (2 / 2)
Part Number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Parameter
• COM output: 4 or 8 (selectable)
• SEG output: 28 or 32 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 32, and the
maximum number of pixels that can be displayed 128 (4×32).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 28, and the
maximum number of pixels that can be displayed 224 (8×28).
LCD controller • LCD drive power supply (bias) pins: 4 (Max)
(LCDC)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through
software
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
16-bit reload
• Square waveform output
timer
• Count clock: 7 internal clocks and external clock can be selected
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter
function can be implemented. When using the event counter function, the 16-bit reload timer and
the 8/16-bit composite timer ch. 1 is unavailable
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as "8-bit PPG × 2 channels" or "16-bit PPG × 1 channel"
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock
source of 1 second and setting counter value to 60)
8 channels
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Watch prescaler Eight different time intervals can be selected. (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, write/erase/erase-suspend/eraseresume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of write/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory.
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-64P-M38
Package
FPT-64P-M39
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
9
CHAPTER 1 OVERVIEW
1.3 Differences among Products and Notes on Product
Selection
1.3
MB95410H/470H Series
Differences among Products and Notes on Product
Selection
The following describes differences among the products of the MB95410H/
470H Series and notes on product selection.
■ Differences among Products and Notes on Product Selection
•
Current consumption
When using the on-chip debug function, take account of the current consumption of flash
erase/write.
For details of current consumption, refer to "■ ELECTRICAL CHARACTERISTICS" in the
data sheet of the MB95410H/470H Series.
•
Package
For details of information on each package, see "1.6 Package Dimension".
•
Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, refer to "■ ELECTRICAL CHARACTERISTICS" in the
data sheet of the MB95410H/470H Series.
•
On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an
evaluation tool. For details of the connection method, see "CHAPTER 31 EXAMPLE OF
SERIAL PROGRAMMING CONNECTION".
10
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.4 Block Diagrams of MB95410H/470H Series
MB95410H/470H Series
1.4
Block Diagrams of MB95410H/470H Series
Figure 1.4-1 and Figure 1.4-2 are block diagrams of the MB95410H/470H Series.
■ Block Diagrams of MB95410H/470H Series
Figure 1.4-1 Block Diagram of MB95410H Series
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
PF1/X1*2
PF0/X0*2
Oscillator
circuit
PG2/X1A*2
RAM (2032/1008/496 bytes)
CR
oscillator
PG1/X0A*2
Interrupt controller
P52/TO00
Clock control
C
P50/TO01
8/16-bit composite timer ch. 0
Watch counter
P12*1/DBG
P51/EC0
On-chip debug
P00/AN00 to P07/AN07
8/10-bit A/D converter
P13/ADTG
Wild register
External interrupt
P14/UCK0
UART/SIO ch. 0
P11/UO0
P10/UI0
Internal bus
P00/INT00 to P07/INT07
LCDC
(4 COM or 8 COM)
P05/UCK1
UART/SIO ch. 1
P03/UO1
4 COM:
8 COM:
P90/V4 to P94/V0
P90/V4 to P94/V0
PA0/COM0 to PA3/COM3
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC7/SEG09
PC0/SEG02 to PC7/SEG09
P60/SEG10 to P67/SEG17
P60/SEG10 to P67/SEG17
P43/SEG18 to P40/SEG21
P43/SEG18 to P40/SEG21
PE0/SEG22 to PE7/SEG29
PE0/SEG22 to PE7/SEG29
P07/SEG30 to P01/SEG36
P07/SEG30 to P02/SEG35
PB2/SEG37 to PB4/SEG39
P04/UI1
*3
P02/UCK2
UART/SIO ch. 2
P00/UO2
16-bit reload timer
P01/UI2
P20/PPG00
8/16-bit PPG ch. 0
P21/PPG01
P52/TI0
P53/TO0
PE5/TO11
8/16-bit composite timer ch. 1
PE6/TO10
PE7/EC1
P16/PPG10
8/16-bit PPG ch. 1
P15/PPG11
P20/CMPN
P22/SCL*1
Voltage comparator
I2C
P23/SDA*1
P21/CMPP
P17/CMPO
Port
Vcc
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
11
CHAPTER 1 OVERVIEW
1.4 Block Diagrams of MB95410H/470H Series
MB95410H/470H Series
Figure 1.4-2 Block Diagram of MB95470H Series
F2MC-8FX CPU
PF2*1/RST*2
PF1/X1
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
RAM (2032/1008/496 bytes)
CR
oscillator
PG1/X0A*2
Interrupt controller
P01/TO00
Clock control
C
P13/TO01
8/16-bit composite timer ch. 0
Watch counter
P12*1/DBG
P14/EC0
On-chip debug
P00/AN00 to P07/AN07
8/10-bit A/D converter
P13/ADTG
Wild register
External interrupt
P14/UCK0
P11/UO0
UART/SIO ch. 0
P10/UI0
Internal bus
P00/INT00 to P07/INT07
LCDC
(4 COM or 8 COM)
P05/UCK1
P03/UO1
UART/SIO ch. 1
4 COM:
8 COM:
P90/V4 to P93/V1
P90/V4 to P93/V1
PA0/COM0 to PA3/COM3
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P00/SEG29
P07/SEG22 to P02/SEG27
P16/SEG30, P15/SEG31
P04/UI1
*3
P02/UCK2
P00/UO2
UART/SIO ch. 2
16-bit reload timer
P01/UI2
P20/PPG00
P21/PPG01
8/16-bit PPG ch. 0
P14/TI0
P10/TO0
PE5/TO11
8/16-bit composite timer ch. 1
PE6/TO10
PE7/EC1
P16/PPG10
P15/PPG11
8/16-bit PPG ch. 1
P20/CMPN
P22*1/SCL
Voltage comparator
I2C
*1
P23 /SDA
P21/CMPP
P17/CMPO
Port
Vcc
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
12
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.5 Pin Assignment
MB95410H/470H Series
1.5
Pin Assignment
Figure 1.5-1 and Figure 1.5-2 show the pin assignment of the MB95410H/470H
Series.
■ Pin Assignment of MB95410H Series
P61/SEG11
P62/SEG12
P63/SEG13
P64/SEG14
P65/SEG15
P66/SEG16
P67/SEG17
P43/SEG18
P42/SEG19
P41/SEG20
P40/SEG21
PE0/SEG22
PE1/SEG23
PE2/SEG24
PE3/SEG25
PE4/SEG26
PE5/SEG27/TO11
PE6/SEG28/TO10
PE7/SEG29/EC1
AVss
Figure 1.5-1 Pin Assignment of MB95410H Series
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc
1
60
P60/SEG10
P07/INT07/AN07/SEG30
2
59
PC7/SEG09
P06/INT06/AN06/SEG31
3
58
PC6/SEG08
P05/INT05/AN05/SEG32/UCK1
4
57
PC5/SEG07
P04/INT04/AN04/SEG33/UI1
5
56
PC4/SEG06
P03/INT03/AN03/SEG34/UO1
6
55
PC3/SEG05
P02/INT02/AN02/SEG35/UCK2
7
54
PC2/SEG04
P01/INT01/AN01/SEG36/UI2
8
53
PC1/SEG03
P00/INT00/AN00/UO2
9
52
PC0/SEG02
P16/PPG10
10
51
PB1/SEG01
P15/PPG11
11
50
PB0/SEG00
P14/UCK0
12
49
P17/CMPO
P13/ADTG
13
48
PF2/RST
P12/DBG
14
47
Vcc
P11/UO0
15
46
PG1/X0A
P10/UI0
16
45
PG2/X1A
P53/TO0
17
44
C
P52/TI0/TO00
18
43
PF0/X0
P51/EC0
19
42
PF1/X1
P50/TO01
20
41
Vss
(TOP VIEW)
MB95410H Series
(FPT-80P-M37)
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
PA7/COM7
PA6/COM6
PA5/COM5
PA4/COM4
PA3/COM3
PA2/COM2
PA1/COM1
PA0/COM0
PB4/SEG39
PB3/SEG38
PB2/SEG37
P94/V0
P93/V1
P92/V2
P91/V3
P90/V4
P20/PPG00/CMPN
P21/PPG01/CMPP
P22/SCL
P23/SDA
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
13
CHAPTER 1 OVERVIEW
1.5 Pin Assignment
MB95410H/470H Series
■ Pin Assignment of MB95470H Series
P61/SEG07
P62/SEG08
P63/SEG09
P64/SEG10
P65/SEG11
P66/SEG12
P67/SEG13
PE0/SEG14
PE1/SEG15
PE2/SEG16
PE3/SEG17
PE4/SEG18
PE5/SEG19/TO11
PE6/SEG20/TO10
PE7/SEG21/EC1
AVss
Figure 1.5-2 Pin Assignment of MB95470H Series
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
1
48
P60/SEG06
P07/INT07/AN07/SEG22
2
47
PC3/SEG05
P06/INT06/AN06/SEG23
3
46
PC2/SEG04
P05/INT05/AN05/SEG24/UCK1
4
45
PC1/SEG03
P04/INT04/AN04/SEG25/UI1
5
44
PC0/SEG02
P03/INT03/AN03/SEG26/UO1
6
43
PB1/SEG01
P02/INT02/AN02/SEG27/UCK2
7
42
PB0/SEG00
P01/INT01/AN01/SEG28/UI2/TO00
8
P00/INT00/AN00/SEG29/UO2
9
P16/PPG10/SEG30
10
P15/PPG11/SEG31
11
P14/UCK0/EC0/TI0
(TOP VIEW)
MB95470H Series
41
P17/CMPO
40
PF2/RST
39
Vcc
38
PG1/X0A
12
37
PG2/X1A
P13/ADTG/TO01
13
36
C
P12/DBG
14
35
PF0/X0
P11/UO0
15
34
PF1/X1
P10/UI0/TO0
16
33
Vss
(FPT-64P-M38)
(FPT-64P-M39)
14
FUJITSU SEMICONDUCTOR LIMITED
PA7/COM7
PA6/COM6
PA5/COM5
PA4/COM4
PA3/COM3
PA2/COM2
PA1/COM1
PA0/COM0
P93/V1
P92/V2
P91/V3
P90/V4
P20/PPG00/CMPN
P21/PPG01/CMPP
P22/SCL
P23/SDA
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.6 Package Dimension
MB95410H/470H Series
1.6
Package Dimension
The MB95410H/470H Series is available in three types of package.
■ Package Dimension of FPT-80P-M37 (MB95410H Series)
Figure 1.6-1 Package Dimension of FPT-80P-M37
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
21
"A"
1
20
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
M
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
15
CHAPTER 1 OVERVIEW
1.6 Package Dimension
MB95410H/470H Series
■ Package Dimension of FPT-64P-M38 (MB95470H Series)
Figure 1.6-2 Package Dimension of FPT-64P-M38
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
0.145±0.055
(.006±.002)
*10.00±0.10(.394±.004)SQ
48
33
Details of "A" part
32
49
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.08(.003)
0.25(.010)
0~8°
INDEX
1
0.22±0.05
(.009±.002)
0.10±0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
17
64
0.08(.003)
M
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
16
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.6 Package Dimension
MB95410H/470H Series
■ Package Dimension of FPT-64P-M39 (MB95470H Series)
Figure 1.6-3 Package Dimension of FPT-64P-M39
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
49
32
+0.20
1.50 –0.10
+.008
.059 –.004
0~8˚
0.10(.004)
0.10±0.10
(.004±.004)
INDEX
64
1
0.60±0.15
(.024±.006)
16
0.65(.026)
C
0.25(.010)BSC
17
0.32±0.06
(.013±.002)
"A"
0.13(.005)
M
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
17
CHAPTER 1 OVERVIEW
1.7 Pin Functions
1.7
MB95410H/470H Series
Pin Functions
Table 1.7-1 and Table 1.7-2 show pin functions of the MB95410H/470H Series.
The alphabets in "I/O circuit type" column of the above tables correspond to
those in "Type" column of Table 1.8-1.
■ Pin Functions (MB95410H Series)
Table 1.7-1 Pin Functions (MB95410H Series) (1 / 7)
Pin
no.
Pin name
I/O
circuit
type*
1
AVCC
—
P07
External interrupt input pin
S
AN07
A/D analog input pin
SEG30
LCDC SEG output pin
P06
General-purpose I/O port
INT06
3
External interrupt input pin
S
AN06
A/D analog input pin
SEG31
LCDC SEG output pin
P05
General-purpose I/O port
INT05
4
AN05
External interrupt input pin
S
LCDC SEG output pin
UCK1
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
INT04
AN04
External interrupt input pin
V
SEG33
UI1
UART/SIO ch. 1 data input pin
P03
General-purpose I/O port
AN03
SEG34
UO1
18
A/D analog input pin
LCDC SEG output pin
INT03
6
A/D analog input pin
SEG32
P04
5
A/D converter power supply pin
General-purpose I/O port
INT07
2
Function
External interrupt input pin
S
A/D analog input pin
LCDC SEG output pin
UART/SIO ch. 1 data output pin
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (2 / 7)
Pin
no.
Pin name
I/O
circuit
type*
P02
General-purpose I/O port
INT02
7
AN02
External interrupt input pin
S
A/D analog input pin
SEG35
LCDC SEG output pin
UCK2
UART/SIO ch. 2 clock I/O pin
P01
General-purpose I/O port
INT01
8
Function
AN01
External interrupt input pin
V
SEG36
A/D analog input pin
LCDC SEG output pin
UI2
UART/SIO ch. 2 data input pin
P00
General-purpose I/O port
INT00
9
External interrupt input pin
W
AN00
A/D analog input pin
UO2
UART/SIO ch. 2 data output pin
P16
10
General-purpose I/O port
Y
PPG10
8/16-bit PPG ch. 1 output pin
P15
11
General-purpose I/O port
Y
PPG11
8/16-bit PPG ch. 1 output pin
P14
12
General-purpose I/O port
H
UCK0
UART/SIO ch. 0 clock I/O pin
P13
13
General-purpose I/O port
H
ADTG
A/D trigger input (ADTG) pin
P12
14
General-purpose I/O port
D
DBG
DBG input pin
P11
15
General-purpose I/O port
H
UO0
UART/SIO ch. 0 data output pin
P10
16
General-purpose I/O port
G
UI0
UART/SIO ch. 0 data input pin
P53
17
General-purpose I/O port
H
TO0
MN702-00005-2v0-E
16-bit reload timer output pin
FUJITSU SEMICONDUCTOR LIMITED
19
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (3 / 7)
Pin
no.
Pin name
I/O
circuit
type*
P52
18
TI0
General-purpose I/O port
H
TO00
General-purpose I/O port
H
EC0
8/16-bit composite timer ch. 0 clock input pin
P50
20
General-purpose I/O port
H
TO01
8/16-bit composite timer ch. 0 output pin
P23
21
General-purpose I/O port
I
SDA
P22
22
23
SCL
I2C clock I/O pin
P21
General-purpose I/O port
PPG01
T
PPG00
General-purpose I/O port
T
CMPN
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
P90
25
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
P20
General-purpose I/O port
R
V4
LCDC drive power supply pin
P91
26
General-purpose I/O port
R
V3
LCDC drive power supply pin
P92
27
General-purpose I/O port
R
V2
LCDC drive power supply pin
P93
28
General-purpose I/O port
R
V1
LCDC drive power supply pin
P94
29
General-purpose I/O port
R
V0
LCDC drive power supply pin
PB2
30
General-purpose I/O port
M
SEG37
LCDC SEG output pin
PB3
31
General-purpose I/O port
M
SEG38
20
I2C data I/O pin
General-purpose I/O port
I
CMPP
24
16-bit reload timer input pin
8/16-bit composite timer ch. 0 output pin
P51
19
Function
LCDC SEG output pin
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (4 / 7)
Pin
no.
Pin name
I/O
circuit
type*
PB4
32
General-purpose I/O port
M
SEG39
LCDC SEG output pin
PA0
33
General-purpose I/O port
M
COM0
LCDC COM output pin
PA1
34
General-purpose I/O port
M
COM1
LCDC COM output pin
PA2
35
General-purpose I/O port
M
COM2
LCDC COM output pin
PA3
36
General-purpose I/O port
M
COM3
LCDC COM output pin
PA4
37
General-purpose I/O port
M
COM4
LCDC COM output pin
PA5
38
General-purpose I/O port
M
COM5
LCDC COM output pin
PA6
39
General-purpose I/O port
M
COM6
LCDC COM output pin
PA7
40
General-purpose I/O port
M
COM7
41
VSS
LCDC COM output pin
—
PF1
42
General-purpose I/O port
Main clock oscillation pin
PF0
43
General-purpose I/O port
B
X0
C
Main clock oscillation pin
—
PG2
45
Capacitor connection pin
General-purpose I/O port
C
X1A
Subclock oscillation pin (32 kHz)
PG1
46
General-purpose I/O port
C
X0A
47
Power supply pin (GND)
B
X1
44
Function
VCC
Subclock oscillation pin (32 kHz)
—
PF2
48
General-purpose I/O port
A
RST
MN702-00005-2v0-E
Power supply pin
Reset pin
Dedicated reset pin for MB95F414H/F416H/F418H
FUJITSU SEMICONDUCTOR LIMITED
21
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (5 / 7)
Pin
no.
Pin name
I/O
circuit
type*
P17
49
General-purpose I/O port
H
CMPO
Voltage comparator output pin
PB0
50
General-purpose I/O port
M
SEG00
LCDC SEG output pin
PB1
51
General-purpose I/O port
M
SEG01
LCDC SEG output pin
PC0
52
General-purpose I/O port
M
SEG02
LCDC SEG output pin
PC1
53
General-purpose I/O port
M
SEG03
LCDC SEG output pin
PC2
54
General-purpose I/O port
M
SEG04
LCDC SEG output pin
PC3
55
General-purpose I/O port
M
SEG05
LCDC SEG output pin
PC4
56
General-purpose I/O port
M
SEG06
LCDC SEG output pin
PC5
57
General-purpose I/O port
M
SEG07
LCDC SEG output pin
PC6
58
General-purpose I/O port
M
SEG08
LCDC SEG output pin
PC7
59
General-purpose I/O port
M
SEG09
LCDC SEG output pin
P60
60
General-purpose I/O port
M
SEG10
LCDC SEG output pin
P61
61
General-purpose I/O port
M
SEG11
LCDC SEG output pin
P62
62
General-purpose I/O port
M
SEG12
LCDC SEG output pin
P63
63
General-purpose I/O port
M
SEG13
22
Function
LCDC SEG output pin
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (6 / 7)
Pin
no.
Pin name
I/O
circuit
type*
P64
64
General-purpose I/O port
M
SEG14
LCDC SEG output pin
P65
65
General-purpose I/O port
M
SEG15
LCDC SEG output pin
P66
66
General-purpose I/O port
M
SEG16
LCDC SEG output pin
P67
67
General-purpose I/O port
M
SEG17
LCDC SEG output pin
P43
68
General-purpose I/O port
M
SEG18
LCDC SEG output pin
P42
69
General-purpose I/O port
M
SEG19
LCDC SEG output pin
P41
70
General-purpose I/O port
M
SEG20
LCDC SEG output pin
P40
71
General-purpose I/O port
M
SEG21
LCDC SEG output pin
PE0
72
General-purpose I/O port
M
SEG22
LCDC SEG output pin
PE1
73
General-purpose I/O port
M
SEG23
LCDC SEG output pin
PE2
74
General-purpose I/O port
M
SEG24
LCDC SEG output pin
PE3
75
General-purpose I/O port
M
SEG25
LCDC SEG output pin
PE4
76
General-purpose I/O port
M
SEG26
LCDC SEG output pin
PE5
77
Function
SEG27
TO11
MN702-00005-2v0-E
General-purpose I/O port
M
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
FUJITSU SEMICONDUCTOR LIMITED
23
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-1 Pin Functions (MB95410H Series) (7 / 7)
Pin
no.
Pin name
I/O
circuit
type*
PE6
78
SEG28
General-purpose I/O port
M
TO10
SEG29
General-purpose I/O port
M
EC1
80
AVSS
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
PE7
79
Function
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see "1.8 I/O Circuit Types".
24
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
■ Pin Functions (MB95470H Series)
Table 1.7-2 Pin Functions (MB95470H Series) (1 / 6)
Pin no.
Pin name
I/O
circuit
type*
1
AVCC
—
P07
External interrupt input pin
S
AN07
A/D analog input pin
SEG22
LCDC SEG output pin
P06
General-purpose I/O port
INT06
3
External interrupt input pin
S
AN06
A/D analog input pin
SEG23
LCDC SEG output pin
P05
General-purpose I/O port
INT05
4
AN05
External interrupt input pin
S
LCDC SEG output pin
UCK1
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
INT04
AN04
External interrupt input pin
V
SEG25
UI1
UART/SIO ch. 1 data input pin
P03
General-purpose I/O port
AN03
External interrupt input pin
S
SEG26
A/D analog input pin
LCDC SEG output pin
UO1
UART/SIO ch. 1 data output pin
P02
General-purpose I/O port
INT02
7
A/D analog input pin
LCDC SEG output pin
INT03
6
A/D analog input pin
SEG24
P04
5
A/D converter power supply pin
General-purpose I/O port
INT07
2
Function
AN02
External interrupt input pin
S
A/D analog input pin
SEG27
LCDC SEG output pin
UCK2
UART/SIO ch. 2 clock I/O pin
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
25
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-2 Pin Functions (MB95470H Series) (2 / 6)
Pin no.
Pin name
I/O
circuit
type*
P01
General-purpose I/O port
INT01
External interrupt input pin
AN01
8
A/D analog input pin
V
SEG28
LCDC SEG output pin
TO00
8/16-bit composite timer ch. 0 output pin
UI2
UART/SIO ch. 2 data input pin
P00
General-purpose I/O port
INT00
9
AN00
External interrupt input pin
S
SEG29
10
UO2
UART/SIO ch. 2 data output pin
P16
General-purpose I/O port
SEG30
M
SEG31
General-purpose I/O port
M
PPG11
General-purpose I/O port
UCK0
UART/SIO ch. 0 clock I/O pin
H
EC0
8/16-bit composite timer ch. 0 clock input pin
TI0
16-bit reload timer input pin
P13
General-purpose I/O port
ADTG
H
TO01
General-purpose I/O port
D
DBG
DBG input pin
P11
15
General-purpose I/O port
H
UO0
UART/SIO ch. 0 data output pin
P10
General-purpose I/O port
UI0
TO0
26
A/D trigger input (ADTG) pin
8/16-bit composite timer ch. 0 output pin
P12
14
16
LCDC SEG output pin
8/16-bit PPG ch. 1 output pin
P14
12
LCDC SEG output pin
8/16-bit PPG ch. 1 output pin
P15
13
A/D analog input pin
LCDC SEG output pin
PPG10
11
Function
G
UART/SIO ch. 0 data input pin
16-bit reload timer output pin
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-2 Pin Functions (MB95470H Series) (3 / 6)
Pin no.
Pin name
I/O
circuit
type*
P23
17
General-purpose I/O port
I
SDA
P22
18
19
I2C data I/O pin
General-purpose I/O port
I
SCL
I2C clock I/O pin
P21
General-purpose I/O port
PPG01
T
CMPP
PPG00
General-purpose I/O port
T
CMPN
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
P90
21
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
P20
20
Function
General-purpose I/O port
R
V4
LCDC drive power supply pin
P91
22
General-purpose I/O port
R
V3
LCDC drive power supply pin
P92
23
General-purpose I/O port
R
V2
LCDC drive power supply pin
P93
24
General-purpose I/O port
R
V1
LCDC drive power supply pin
PA0
25
General-purpose I/O port
M
COM0
LCDC COM output pin
PA1
26
General-purpose I/O port
M
COM1
LCDC COM output pin
PA2
27
General-purpose I/O port
M
COM2
LCDC COM output pin
PA3
28
General-purpose I/O port
M
COM3
LCDC COM output pin
PA4
29
General-purpose I/O port
M
COM4
LCDC COM output pin
PA5
30
General-purpose I/O port
M
COM5
MN702-00005-2v0-E
LCDC COM output pin
FUJITSU SEMICONDUCTOR LIMITED
27
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-2 Pin Functions (MB95470H Series) (4 / 6)
Pin no.
Pin name
I/O
circuit
type*
PA6
31
General-purpose I/O port
M
COM6
LCDC COM output pin
PA7
32
General-purpose I/O port
M
COM7
33
VSS
LCDC COM output pin
—
PF1
34
General-purpose I/O port
Main clock oscillation pin
PF0
35
General-purpose I/O port
B
X0
C
Main clock oscillation pin
—
PG2
37
General-purpose I/O port
Subclock oscillation pin (32 kHz)
PG1
38
General-purpose I/O port
C
X0A
VCC
Subclock oscillation pin (32 kHz)
—
PF2
40
A
P17
41
Power supply pin
General-purpose I/O port
RST
Reset pin
Dedicated reset pin for MB95F474H/F476H/F478H
General-purpose I/O port
H
CMPO
Voltage comparator output pin
PB0
42
General-purpose I/O port
M
SEG00
LCDC SEG output pin
PB1
43
General-purpose I/O port
M
SEG01
LCDC SEG output pin
PC0
44
General-purpose I/O port
M
SEG02
LCDC SEG output pin
PC1
45
General-purpose I/O port
M
SEG03
LCDC SEG output pin
PC2
46
General-purpose I/O port
M
SEG04
LCDC SEG output pin
PC3
47
General-purpose I/O port
M
SEG05
28
Capacitor connection pin
C
X1A
39
Power supply pin (GND)
B
X1
36
Function
LCDC SEG output pin
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-2 Pin Functions (MB95470H Series) (5 / 6)
Pin no.
Pin name
I/O
circuit
type*
P60
48
General-purpose I/O port
M
SEG06
LCDC SEG output pin
P61
49
General-purpose I/O port
M
SEG07
LCDC SEG output pin
P62
50
General-purpose I/O port
M
SEG08
LCDC SEG output pin
P63
51
General-purpose I/O port
M
SEG09
LCDC SEG output pin
P64
52
General-purpose I/O port
M
SEG10
LCDC SEG output pin
P65
53
General-purpose I/O port
M
SEG11
LCDC SEG output pin
P66
54
General-purpose I/O port
M
SEG12
LCDC SEG output pin
P67
55
General-purpose I/O port
M
SEG13
LCDC SEG output pin
PE0
56
General-purpose I/O port
M
SEG14
LCDC SEG output pin
PE1
57
General-purpose I/O port
M
SEG15
LCDC SEG output pin
PE2
58
General-purpose I/O port
M
SEG16
LCDC SEG output pin
PE3
59
General-purpose I/O port
M
SEG17
LCDC SEG output pin
PE4
60
General-purpose I/O port
M
SEG18
LCDC SEG output pin
PE5
61
Function
SEG19
TO11
MN702-00005-2v0-E
General-purpose I/O port
M
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
FUJITSU SEMICONDUCTOR LIMITED
29
CHAPTER 1 OVERVIEW
1.7 Pin Functions
MB95410H/470H Series
Table 1.7-2 Pin Functions (MB95470H Series) (6 / 6)
Pin no.
Pin name
I/O
circuit
type*
PE6
62
SEG20
General-purpose I/O port
M
TO10
SEG21
General-purpose I/O port
M
EC1
64
AVSS
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
PE7
63
Function
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see "1.8 I/O Circuit Types".
30
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
MB95410H/470H Series
1.8
I/O Circuit Types
Table 1.8-1 lists the I/O circuit types. The alphabets in "Type" column of Table
1.8-1 correspond to those in "I/O circuit type" column of Table 1.7-1 and Table
1.7-2.
■ I/O Circuit Types
Table 1.8-1 I/O Circuit Types (1 / 5)
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
Clock input
X1
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
31
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
MB95410H/470H Series
Table 1.8-1 I/O Circuit Types (2 / 5)
Type
Circuit
C
Remarks
Port select
R
Pull-up control
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 10 MΩ
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
D
Standby control
• N-ch open drain output
• Hysteresis input
Hysteresis input
Digital output
N-ch
G
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Digital output
N-ch
Standby control
Hysteresis input
CMOS input
H
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
32
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
MB95410H/470H Series
Table 1.8-1 I/O Circuit Types (3 / 5)
Type
Circuit
I
Remarks
Standby control
CMOS input
• N-ch open drain output
• CMOS input
• Hysteresis input
Hysteresis input
Digital output
N-ch
J
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Analog input
Pull-up control available
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
M
P-ch
Digital output
Digital output
• CMOS output
• LCD output
• Hysteresis input
N-ch
LCD output
LCD control
Standby control
Hysteresis input
N
P-ch
Digital output
Digital output
N-ch
•
•
•
•
CMOS output
LCD output
Hysteresis input
CMOS input
LCD output
LCD control
Standby control
Hysteresis input
CMOS input
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
33
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
MB95410H/470H Series
Table 1.8-1 I/O Circuit Types (4 / 5)
Type
Circuit
Q
Remarks
P-ch
Digital output
Digital output
• CMOS output
• LCD output
• Hysteresis input
N-ch
LCD output
LCD control
Standby control
External interrupt
control
Hysteresis input
R
P-ch
Digital output
Digital output
• CMOS output
• LCD power supply
• Hysteresis input
N-ch
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
S
P-ch
Digital output
Digital output
N-ch
•
•
•
•
CMOS output
LCD output
Hysteresis input
Analog input
•
•
•
•
CMOS output
Hysteresis input
Analog input
Pull-up control available
Analog input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
T
Pull-up control
R
P-ch
Digital output
Digital output
N-ch
Analog input
Analog input control
Standby control
Hysteresis input
34
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
MB95410H/470H Series
Table 1.8-1 I/O Circuit Types (5 / 5)
Type
V
Circuit
Remarks
P-ch
Digital output
Digital output
N-ch
•
•
•
•
•
CMOS output
LCD output
Hysteresis input
Analog input
CMOS input
Analog input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
CMOS input
W
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Analog input
N-ch
Analog input
Analog input control
Standby control
Hysteresis input
Y
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Standby control
Hysteresis input
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
35
CHAPTER 1 OVERVIEW
1.8 I/O Circuit Types
36
MB95410H/470H Series
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 2
NOTES ON DEVICE
HANDLING
This chapter provides notes on using the
MB95410H/470H Series.
2.1
MN702-00005-2v0-E
Notes on Device Handling
FUJITSU SEMICONDUCTOR LIMITED
37
CHAPTER 2 NOTES ON DEVICE HANDLING
2.1 Notes on Device Handling
2.1
MB95410H/470H Series
Notes on Device Handling
This section provides notes on power supply voltage and pin treatment.
■ Device Handling
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum
voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an
input/output pin that is neither a medium-withstand voltage pin nor a high-withstand
voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in 1.
"Absolute Maximum Ratings" of "■ ELECTRICAL CHARACTERISTICS" in the data
sheet of the MB95410H/470H Series is applied to the VCC pin or the VSS pin, a latch-up
may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a
component to be thermally destroyed.
Ensure that the analog power supply voltage (AVCC) and the analog input voltage do not
exceed the digital power supply voltage (VCC) even when turning on or off the analog
system power supply.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the
fluctuation is within the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC
ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the
standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a
momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on
reset, wakeup from subclock mode or stop mode.
■ Pin Connection
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due
to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a
resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it
unconnected, or set it to the input state and treat it the same as an unused input pin. If there
is an unused output pin, leave it unconnected.
• Treatment of power supply pins on A/D converter
Ensure that AVCC = VCC and AVSS = VSS when the A/D converter is not in use.
Any noise riding on the AVCC pin may cause accuracy degradation. Therefore, it is
advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between the
AVCC pin and the AVSS pin at a location close to this device.
38
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 2 NOTES ON DEVICE HANDLING
2.1 Notes on Device Handling
MB95410H/470H Series
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals
due to an increase in the ground level, and conform to the total output current standard,
always connect the VCC pin and the VSS pin to the power supply and ground outside the
device. In addition, connect the current supply source to the VCC pin and the VSS pin with
low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin to an external pull-up resistor of 2 kΩ or above.
After power-on, ensure that the DBG pin does not stay at "L" level until the reset output is
released.
The DBG pin becomes a communication pin in debug mode. Since the actual pull-up
resistance depends on the tool used and the interconnection length, refer to the tool
document when selecting a pull-up resistor.
• RST pin
Connect the RST pin to an external pull-up resistor of 2 kΩ or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize
the interconnection length between a pull-up resistor and the RST pin and that between a
pull-up resistor and the VCC pin when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the
reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and
the reset input function and the general purpose I/O function can be selected by the RSTEN
bit in the SYSC register.
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The
decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the
capacitance of CS. For the connection to a smoothing capacitor CS, see the diagram below.
To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS
pin when designing the layout of a printed circuit board.
Figure 2.1-1 DBG/RST/C Pins Connection
DBG
C
RST
Cs
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
39
CHAPTER 2 NOTES ON DEVICE HANDLING
2.1 Notes on Device Handling
MB95410H/470H Series
• Note on serial communication
In serial communication, reception of wrong data may occur due to noise or other causes.
Therefore, design a printed circuit board to prevent noise from occurring. Taking account of
the reception of wrong data, take measures such as adding a checksum to the end of data in
order to detect errors. If an error is detected, retransmit the data.
• Analog power supply
Always use the same potential for the AVCC pin and the VCC pin. If VCC is larger than AVCC,
current may flow through the analog input pins (AN).
40
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 3
MEMORY SPACE
This chapter describes the memory space.
MN702-00005-2v0-E
3.1
Memory Space
3.2
Memory Maps
FUJITSU SEMICONDUCTOR LIMITED
41
CHAPTER 3 MEMORY SPACE
3.1 Memory Space
3.1
MB95410H/470H Series
Memory Space
The memory space of the MB95410H/470H Series is 64 Kbyte in size and
consists of an I/O area, an extended I/O area, a data area, and a program area.
The memory space includes areas for specific applications such as generalpurpose registers and a vector table.
■ Configuration of Memory Space
● I/O area (addresses: 0000H to 007FH)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the I/O area forms part of the memory space, it can be accessed in the same way as the
memory. It can also be accessed at high-speed by using direct addressing instructions.
● Extended I/O area (addresses: 0F80H to 0FFFH)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the extended I/O area forms part of the memory space, it can be accessed in the same
way as the memory.
● Data area
• Static RAM is incorporated in the data area as the internal data area.
• The internal RAM size varies according to the product.
• The RAM area from 0090H to 00FFH can be accessed at high-speed by using the direct
addressing instruction.
• In MB95F414H/F414K/F474H/F474K, the area from 0100H to 027FH is an extended direct
addressing area. It can be accessed at high-speed by the direct addressing instruction with a
direct bank pointer set.
• In MB95F416H/F416K/F418H/F418K/F476H/F476K/F478H/F478K, the area from 0100H
to 047FH is an extended direct addressing area. It can be accessed at high-speed by the
direct addressing instruction with a direct bank pointer set.
• In MB95F418H/F418K/F478H/F478K, the area from 0480H to 087FH is an extended direct
addressing area. It cannot be accessed at high-speed by the direct addressing instruction
with a direct bank pointer set.
• The area from 0100H to 01FFH can be used as a general-purpose register area.
● Program area
• ROM is incorporated in the program area as the internal program area.
• The internal ROM size varies according to the product.
• The area from FFC0H to FFFFH is used as the vector table and FFFCH is the Flash security
byte.
• The area from FFBCH to FFBFH is used to store data of the non-volatile register.
42
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 3 MEMORY SPACE
3.1 Memory Space
MB95410H/470H Series
■ Memory Maps
Figure 3.1-1 Memory Maps
MB95F414H/F414K
MB95F474H/F474K
0000H
I/O area
0080H
MB95F416H/F416K
MB95F476H/F476K
Direct addressing
area
0100H
0000H
I/O area
0080H
0100H
Register banks
(General-purpose
register area)
0200H
Register banks
(General-purpose
register area)
Extended direct
addressing area
0200H
MB95F418H/F418K
MB95F478H/F478K
Direct addressing
area
0000H
I/O area
0080H
Access prohibited
0090H
0100H
Extended direct
addressing area 0200H
Register banks
(General-purpose
register area)
Extended direct
addressing area
Data area
027FH
Data area
Direct addressing
area
Data area
047FH
087FH
Access prohibited
Access prohibited
Access prohibited
0F80H
Extended I/O area
0FFFH
Program area
1FFFH
0F80H
Extended I/O area
0FFFH
Program area
1FFFH
0F80H
Extended I/O area
0FFFH
Vacant
Vacant
7FFFH
Program area
BFFFH
Program area
Program area
FFC0H
FFFFH
FFC0H
Vector table area
MN702-00005-2v0-E
FFFFH
FFC0H
Vector table area
FFFFH
FUJITSU SEMICONDUCTOR LIMITED
Vector table area
43
CHAPTER 3 MEMORY SPACE
3.1 Memory Space
3.1.1
MB95410H/470H Series
Areas for Specific Applications
The general-purpose register area and vector table area are used for the
specific applications.
■ General-purpose Register Area (Addresses: 0100H to 01FFH)
• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general-purpose registers, general-purpose register addressing
enables high-speed access with short instructions.
For details, see "5.1.1 Register Bank Pointer (RP)" and "5.2 General-purpose Register".
■ Non-volatile Register Data Area (Addresses: FFBCH to FFBFH)
The area from FFBCH to FFBFH is used to store data of the non-volatile register. For details,
see "CHAPTER 32 NON-VOLATILE REGISTER (NVR) FUNCTION".
■ Vector Table Area (Addresses: FFC0H to FFFFH)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and
resets. FFFCH is the Flash security byte.
• The top of the ROM area is allocated to the vector table area. The start address of a service
routine is set to an address in the vector table in the form of data.
Table 8.1-1 in "CHAPTER 8 INTERRUPTS" lists the vector table addresses corresponding to
vector call instructions, interrupts, and resets.
For details, see "CHAPTER 7 RESET", "CHAPTER 8 INTERRUPTS", and "● CALLV #vct"
in "E.2 Special Instruction" in "APPENDIX".
44
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 3 MEMORY SPACE
3.2 Memory Maps
MB95410H/470H Series
3.2
Memory Maps
This section shows the memory maps of the MB95410H/470H Series.
■ Memory Maps
Figure 3.2-1 Memory Maps of Different Products
MB95F414H/F414K
MB95F474H/F474K
MB95F416H/F416K
MB95F476H/F476K
0000H
0000H
0080H
0090H
0100H
Access prohibited
RAM 496 bytes
Access prohibited
RAM 1008 bytes
I/O area
0080H
0090H
0100H
Registers
Registers
0200H
0280H
0200H
Access prohibited
RAM 2032 bytes
Registers
0200H
0480H
Access prohibited
Access prohibited
0F80H
0F80H
0880H
0F80H
Extended I/O area
Extended I/O area
1000H
2000H
0000H
I/O area
I/O area
0080H
0090H
0100H
MB95F418H/F418K
MB95F478H/F478K
1000H
2000H
Flash 4 Kbyte
Flash 4 Kbyte
Access prohibited
Extended I/O area
1000H
Access prohibited
Access prohibited
8000H
Flash 60 Kbyte
Flash 32 Kbyte
C000H
Flash 16 Kbyte
FFFFH
FFFFH
Parameter
FFFFH
Flash memory
RAM
MB95F414H/F414K/F474H/F474K
20 Kbyte
496 bytes
MB95F416H/F416K/F476H/F476K
36 Kbyte
1008 bytes
MB95F418H/F418K/F478H/F478K
60 Kbyte
2032 bytes
Part number
MN702-00005-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
45
CHAPTER 3 MEMORY SPACE
3.2 Memory Maps
46
MB95410H/470H Series
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 4
MEMORY ACCESS MODE
This chapter describes the memory access
mode.
4.1
MN702-00005-2v0-E
Memory Access Mode
FUJITSU SEMICONDUCTOR LIMITED
47
CHAPTER 4 MEMORY ACCESS MODE
4.1 Memory Access Mode
4.1
MB95410H/470H Series
Memory Access Mode
The MB95410H/470H Series supports only one memory access mode: singlechip mode.
■ Single-chip Mode
In single-chip mode, only the internal RAM and ROM are used, and no external bus access is
executed.
● Mode data
Mode data is the data used to determine the memory access mode of the CPU.
The mode data address is fixed at "FFFDH". Always set the mode data of the internal ROM to
"00H" to select the single-chip mode.
Figure 4.1-1 Mode Data Settings
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FFFDH
Operation
Data
00H
Other than 00H
Selects single-chip mode.
Reserved. Do not set mode data to any
value other than 00H.
After a reset is released, the CPU fetches mode data first.
The CPU then fetches the reset vector after the mode data. It starts executing instructions from
the address set in the reset vector.
48
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 5
CPU
This chapter describes the functions and
operations of the CPU.
MN702-00005-2v0-E
5.1
Dedicated Registers
5.2
General-purpose Register
5.3
Placement of 16-bit Data in Memory
FUJITSU SEMICONDUCTOR LIMITED
49
CHAPTER 5 CPU
5.1 Dedicated Registers
5.1
MB95410H/470H Series
Dedicated Registers
The CPU has dedicated registers: a program counter (PC), two registers for
arithmetic operations (A and T), three address pointers (IX, EP, and SP), and the
program status (PS) register. Each of the registers is 16 bits long. The PS
register consists of the register bank pointer (RP), direct pointer (DP), and
condition code register (CCR).
■ Configuration of Dedicated Registers
The dedicated registers in the CPU consist of seven 16-bit registers. As for the accumulator (A)
and the temporary accumulator (T), using only the lower eight bits of the respective registers is
also supported.
Figure 5.1-1 shows the configuration of the dedicated registers.
Figure 5.1-1 Configuration of Dedicated Registers
16 bits
Initial value
: Program counter
PC
FFFDH
Indicates the address of the current instruction.
0000H
AH
AL
: Accumulator (A)
Temporary storage register for arithmetic operation and transfer
0000H
TH
TL
: Temporary accumulator (T)
Performs arithmetic operations with the accumulator.
: Index register
IX
0000H
Indicates an index address.
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
Indicates a memory address.
Indicates the current stack location.
0030H
RP
DP
CCR
: Program status
Stores a register bank pointer,
a direct bank pointer, and a condition code.
PS
■ Functions of Dedicated Registers
● Program counter (PC)
The program counter is a 16-bit counter which contains the memory address of the instruction
currently executed by the CPU. The program counter is updated whenever an instruction is
executed or an interrupt or a reset occurs. The initial value set immediately after a reset is the
mode data read address (FFFDH).
● Accumulator (A)
The accumulator is a 16-bit register for arithmetic operation. It is used for a variety of
arithmetic and transfer operations of data in memory or data in other registers such as the
temporary accumulator (T). The data in the accumulator can be handled either as word (16-bit)
data or byte (8-bit) data. For byte-length arithmetic and transfer operations, only the lower
eight bits (AL) of the accumulator are used with the upper eight bits (AH) left unchanged. The
initial value set immediately after a reset is "0000H".
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CHAPTER 5 CPU
5.1 Dedicated Registers
● Temporary accumulator (T)
The temporary accumulator is an auxiliary 16-bit register for arithmetic operation. It is used to
perform arithmetic operations with the data in the accumulator (A). The data in the temporary
accumulator is handled as word data for word-length (16-bit) operations with the accumulator
(A) and as byte data for byte-length (8-bit) operations. For byte-length operations, only the
lower eight bits (TL) of the temporary accumulator are used and the upper eight bits (TH) are
not used.
When a MOV instruction is used to transfer data to the accumulator (A), the previous contents
of the accumulator are automatically transferred to the temporary accumulator. When
transferring byte-length data, the upper eight bits (TH) of the temporary accumulator remain
unchanged. The initial value after a reset is "0000H".
● Index register (IX)
The index register is a 16-bit register used to hold the index address. The index register is used
with a single-byte offset (-128 to +127). The offset value is added to the index address to
generate the memory address for data access. The initial value after a reset is "0000H".
● Extra pointer (EP)
The extra pointer is a 16-bit register which contains the value indicating the memory address
for data access. The initial value after a reset is "0000H".
● Stack pointer (SP)
The stack pointer is a 16-bit register which holds the address referenced when an interrupt or a
sub-routine call occurs and by the stack push and pop instructions. During program execution,
the value of the stack pointer indicates the address of the most recent data pushed onto the
stack. The initial value after a reset is "0000H".
● Program status (PS)
The program status is a 16-bit control register. The upper eight bits consists of the register bank
pointer (RP) and direct bank pointer (DP); the lower eight bits consists of the condition code
register (CCR).
In the upper eight bits, the upper five bits consists of the register bank pointer used to contain
the address of the general-purpose register bank. The lower three bits consists of the direct
bank pointer which locates the area to be accessed at high-speed by direct addressing.
The lower eight bits consists of the condition code register (CCR) which consists of flags that
represent the state of the CPU.
The instructions that can access the program status are MOVW A,PS and MOVW PS,A. The
register bank pointer (RP) and direct bank pointer (DP) in the program status register can also
be read from and written to by accessing the mirror address (0078H).
Note that the condition code register (CCR) is a part of the program status register and cannot
be accessed independently.
Refer to the "F2MC-8FX Programming Manual" for details on using the dedicated registers.
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CHAPTER 5 CPU
5.1 Dedicated Registers
5.1.1
MB95410H/470H Series
Register Bank Pointer (RP)
The register bank pointer (RP) in bit15 to bit11 of the program status (PS)
register contains the address of the general-purpose register bank that is
currently in use and is translated into a real address when general-purpose
register addressing is used.
■ Configuration of Register Bank Pointer (RP)
Figure 5.1-2 shows the configuration of the register bank pointer.
Figure 5.1-2 Configuration of Register Bank Pointer
RP
DP
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS
R4
R3
R2
R1
R0
DP2
DP1
CCR
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
DP0
H
I
IL1
IL0
N
Z
V
RP
bit0 Initial value
00000B
C
The register bank pointer contains the address of the register bank currently in use. The content
of the register bank pointer is translated into a real address according to the rule shown in
Figure 5.1-3.
Figure 5.1-3 Rule for Translation into Real Addresses in General-purpose Register Area
Fixed value
Generated
address
RP: Upper
Op-code: Lower
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“1”
R4
R3
R2
R1
R0
b2
b1
b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
A8
A7
A6
A5
A4
A3
A2
A1
A0
A15 A14 A13 A12 A11 A10 A9
The register bank pointer specifies the register bank used as general-purpose registers in the
RAM area. There are a total of 32 register banks. The current register bank is specified by
setting a value between 0 and 31 in the upper five bits of the register bank pointer. Each
register bank has eight 8-bit general-purpose registers which are selected by the lower three
bits of the op-code.
The register bank pointer allows the space from "0100H" to "01FFH"(max) to be used as a
general-purpose register area. However, certain products have restrictions on the size of the
area available for the general-purpose register area. The initial value of the register bank
pointer after a reset is "0000H".
■ Mirror Address for Register Bank and Direct Bank Pointer
Values can be written to the register bank pointer (RP) and the direct bank pointer (DP) by
accessing the program status (PS) register with the "MOVW A,PS" instruction; the two
pointers can be read by accessing PS with the "MOVW PS,A" instruction. Values can also be
directly written to and read from the two pointers by accessing "0078H", the mirror address of
the register bank pointer.
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CHAPTER 5 CPU
5.1 Dedicated Registers
MB95410H/470H Series
5.1.2
Direct Bank Pointer (DP)
The direct bank pointer (DP) in bit10 to bit8 of the program status (PS) register
specifies the area to be accessed by direct addressing.
■ Configuration of Direct Bank Pointer (DP)
Figure 5.1-4 shows the configuration of the direct bank pointer.
Figure 5.1-4 Configuration of Direct Bank Pointer
RP
DP
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS
R4
R3
R2
R1
R0
DP2
DP1
CCR
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
DP0
H
I
IL1
IL0
N
Z
V
DP
bit0 initial value
000B
C
The area of "0000H to 007FH" and that of "0090H to 047FH" can be accessed by direct
addressing. Access to 0000H to 007FH is specified by an operand regardless of the value in the
direct bank pointer. Access to 0090H to 047FH is specified by the value of the direct bank
pointer and the operand.
Table 5.1-1 shows the relationship between the direct bank pointer (DP) and the access area;
Table 5.1-2 lists the direct addressing instructions.
Table 5.1-1 Direct Bank Pointer and Access Area
Direct bank pointer (DP[2:0])
Operand-specified dir
Access area
XXXB (It does not affect mapping. )
0000H to 007FH
0000H to 007FH
000B (Initial value)
0090H to 00FFH*1
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0090H to 00FFH
0200H to 027FH
100B
0280H to 02FFH*2
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
*1: Due to the memory size limit, it is "0090H to 00FFH" in the MB95410H/470H Series.
*2: The available access area is up to "0280H" in MB95F414H/F414K/F474H/F474K.
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CHAPTER 5 CPU
5.1 Dedicated Registers
MB95410H/470H Series
Table 5.1-2 Direct Address Instruction List
Applicable instructions
CLRB dir:bit
SETB dir:bit
BBC dir:bit,rel
BBS dir:bit,rel
MOV A,dir
CMP A,dir
ADDC A,dir
SUBC A,dir
MOV dir,A
XOR A,dir
AND A,dir
OR A,dir
MOV dir,#imm
CMP dir,#imm
MOVW A,dir
MOVW dir,A
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CHAPTER 5 CPU
5.1 Dedicated Registers
MB95410H/470H Series
5.1.3
Condition Code Register (CCR)
The condition code register (CCR) in the lower eight bits of the program status
(PS) register consists of the bits (H, N, Z, V, and C) containing information
about the arithmetic result or transfer data and the bits (I, IL1, and IL0) used to
control the acceptance of interrupt requests.
■ Configuration of Condition Code Register (CCR)
Figure 5.1-5 Configuration of Condition Code Register
RP
DP
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS
R4
R3
R2
R1
R0
DP2
DP1
CCR
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
DP0
H
I
IL1
IL0
N
Z
V
CCR
bit0 Initial value
C
00110000B
Half carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
The condition code register is a part of the program status (PS) register and therefore cannot be
accessed independently.
■ Bits Showing Operation Results
● Half carry flag (H)
This flag is set to "1" when a carry from bit3 to bit4 or a borrow from bit4 to bit3 occurs due to
the result of an operation. Otherwise, the flag is set to "0". Do not use this flag for any
operation other than addition and subtraction as the flag is intended for decimal-adjusted
instructions.
● Negative flag (N)
This flag is set to "1" when the value of the most significant bit is "1" due to the result of an
operation, and is set to "0" when the value of the most significant bit is "0".
● Zero flag (Z)
This flag is set to "1" when the result of an operation is "0", and is set to "0" when the result is
"1".
● Overflow flag (V)
This flag indicates whether the result of an operation has caused an overflow, with the operand
used in the operation being regarded as an integer expressed as a complement of two. If an
overflow occurs, the overflow flag is set to "1"; otherwise, it is set to "0".
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CHAPTER 5 CPU
5.1 Dedicated Registers
MB95410H/470H Series
● Carry flag (C)
This flag is set to "1" when a carry from bit7 or a borrow to bit7 occurs due to the result of an
operation. Otherwise, the flag is set to "0". When a shift instruction is executed, the flag is set
to the shift-out value.
Figure 5.1-6 shows how the carry flag is updated by a shift instruction.
Figure 5.1-6 Carry Flag Updated by Shift Instruction
• Left-shift (ROLC)
• Right-shift (RORC)
bit7
bit0
bit7
bit0
C
C
■ Interrupt Acceptance Control Bits
● Interrupt enable flag (I)
When this flag is set to "1", interrupts are enabled and accepted by the CPU. When this flag is
set to "0", interrupts are disabled and rejected by the CPU.
The initial value after a reset is "0".
The SETI and CLRI instructions set and clear the flag to "1" and "0", respectively.
● Interrupt level bits (IL1, IL0)
These bits indicate the level of the interrupt currently accepted by the CPU.
The interrupt level is compared with the value of the interrupt level setting register (ILR0 to
ILR5) that corresponds to the interrupt request (IRQ00 to IRQ23) of each peripheral function.
The CPU services an interrupt request only when its interrupt level is smaller than the value of
these bits with the interrupt enable flag set (CCR:I = 1). Table 5.1-3 lists interrupt level
priorities. The initial value after a reset is "11B".
Table 5.1-3 Interrupt Levels
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low (No interrupt)
The interrupt level bits (IL1, IL0) are usually "11B" when the CPU does not service an
interrupt (with the main program running).
For details of interrupts, see "8.1 Interrupts".
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CHAPTER 5 CPU
5.2 General-purpose Register
MB95410H/470H Series
5.2
General-purpose Register
The general-purpose registers are a memory block in which each bank consists
of eight 8-bit registers. Up to 32 register banks can be used in total. The
register bank pointer (RP) is used to specify a register bank.
Register banks are useful for interrupt handling, vector call processing, and
sub-routine calls.
■ Configuration of General-purpose Register
• The general-purpose register is an 8-bit register and is located in a register bank in the
general-purpose register area (in RAM).
• Up to 32 banks can be used, each of which consists of eight registers (R0 to R7).
• The register bank pointer (RP) specifies the register bank currently being used and the lower
three bits of the op-code specify the general-purpose register 0 (R0) to the general-purpose
register 7 (R7).
Figure 5.2-1 shows the configuration of the register banks.
Figure 5.2-1 Configuration of Register Banks
8 bits
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
R6
107H
R1
R2
R3
R4
R5
R6
R7
R1
R2
R3
R4
R5
R6
1FFH
R7
Bank 31
R7
Bank 0
32 banks
The number of banks
available is restricted by
the available RAM size.
Memory area
For information on the general-purpose register area available in each model, see "3.1.1 Areas
for Specific Applications".
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CHAPTER 5 CPU
5.2 General-purpose Register
MB95410H/470H Series
■ Features of General-purpose Registers
The general-purpose register has the following features.
• High-speed access to RAM with short instructions (general-purpose register addressing).
• Grouping registers into a block of register banks facilitates data protection and division of
registers in terms of functions.
A general-purpose register bank can be allocated exclusively to an interrupt service routine or a
vector call (CALLV #0 to #7) processing routine. For instance, the fourth register bank is
always assigned to the second interrupt.
Data of a general-purpose register before an interrupt can be saved to a dedicated register bank
by just specifying that register bank at the beginning of an interrupt service routine. This
therefore eliminates the need to save data of a general-purpose register in a stack, thereby
enabling the CPU to receive interrupts at high speed.
Notes:
In an interrupt service routine, include one of the following in a program to ensure that
values of the interrupt level bits (CCR:IL1, IL0) of the condition code register are not
modified when modifying a register bank pointer (RP) to specify a register bank.
• Read the interrupt level bits and save their values before writing a value to the RP.
• Directly write a new value to the RP mirror address "0078H" to update the RP.
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CHAPTER 5 CPU
5.3 Placement of 16-bit Data in Memory
MB95410H/470H Series
5.3
Placement of 16-bit Data in Memory
This section describes how 16-bit data is stored in memory.
■ Placement of 16-bit Data in Memory
● State of 16-bit data stored in RAM
When 16-bit data is written to memory, the upper byte of the data is stored at a smaller address
and the lower byte is stored at the next address. When 16-bit data is read, it is handled in the
same way.
Figure 5.3-1 shows how 16-bit data is placed in memory.
Figure 5.3-1 Placement of 16-bit Data in Memory
Before
execution
A 1 2 3 4H
Memory
MOVW 0081H, A
0080H
0081H
0082H
0083H
After
execution
A 1 2 3 4H
Memory
12H
34H
0080H
0081H
0082H
0083H
● Storage state of 16-bit data specified by an operand
Even when the operand in an instruction specifies 16-bit data, the upper byte is stored at the
address closer to the op-code (instruction) and the lower byte is stored at the address next to the
one at which the upper byte is stored.
That is true whether an operand is either a memory address or 16-bit immediate data.
Figure 5.3-2 shows how 16-bit data in an instruction is placed.
Figure 5.3-2 Placement of 16-bit Data in Instruction
[Example] MOV A, 5678H
; Extended address
MOVW A, #1234H ; 16-bit immediate data
Assemble
XXX0H
XXX2H
XXX5H
XXX8H
XX XX
60 56 78 ; Extended address
E4 12 34 ; 16-bit immediate data
XX
● Storage state of 16-bit data in the stack
When 16-bit register data is saved in a stack on an interrupt, the upper byte is stored at a lower
address in the same way as 16-bit data specified by an operand.
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CHAPTER 5 CPU
5.3 Placement of 16-bit Data in Memory
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CHAPTER 6
CLOCK CONTROLLER
This chapter describes the functions and
operations of the clock controller.
6.1
Overview of Clock Controller
6.2
Oscillation Stabilization Wait Time
6.3
System Clock Control Register (SYCC)
6.4
PLL Control Register (PLLC)
6.5
Oscillation Stabilization Wait Time Setting Register
(WATR)
6.6
Standby Control Register (STBC)
6.7
System Clock Control Register 2 (SYCC2)
6.8
Clock Modes
6.9
Operations in Low-power Consumption Mode (Standby
Mode)
6.10 Clock Oscillator Circuit
6.11 Overview of Prescaler
6.12 Configuration of Prescaler
6.13 Operation of Prescaler
6.14 Notes on Using Prescaler
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
6.1
MB95410H/470H Series
Overview of Clock Controller
The New 8FX family has a built-in clock controller that optimizes its power
consumption. It supports both the external main clock and the external
subclock.
The clock controller enables/disables clock oscillation, enables/disables the
supply of clock signals to the internal circuit, selects the clock source, and
controls the PLL, the CR oscillator and frequency divider circuits.
■ Overview of Clock Controller
The clock controller enables/disables clock oscillation, enables/disables clock supply to the
internal circuit, selects the clock source, and controls the PLL, the CR oscillator and frequency
divider circuits.
The clock controller controls the internal clock according to the clock mode, standby mode
settings and the reset operation. The clock mode is used to select an internal operating clock;
the standby mode is used to enable and disable clock oscillation and signal supply.
The clock controller selects the optimum power consumption and functions depending on the
combination of clock mode and standby mode.
This device has five source clocks: a main clock formed by dividing the main oscillation clock
by two, a main PLL clock formed by multiplying the main oscillation clock by the PLL
multiplier, a subclock formed by dividing the sub-oscillation clock by two, a main CR clock,
and a sub-CR clock formed by dividing the sub-CR oscillation by two.
Note:
Only either main clock or main PLL clock can be used at one time. They share the
MOSCE bit in the SYCC2 register, and the MRDY bit in the STBC register. The setting of
"11B" in SYCC2:RCS[1:0] and that of "11B" in SYCC2:RCM[1:0] are applicable to both
main clock and main PLL clock.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
MB95410H/470H Series
■ Block Diagrams of Clock Controller
Figure 6.1-1 shows a block diagram of the clock controller.
Figure 6.1-1 Block Diagram of Clock Controller
System clock control register 2 (SYCC2)
Standby control register (STBC)
RCM1 RCM0 RCS1 RCS0 SOSCE MOSCE SCRE MCRE
STP
SLP
SPL SRST TMD SCRDY MCRDY MRDY
Watch or time-base
timer mode
Sleep mode
Stop mode
Main CR
clock oscillator
circuit
(6)
Sub-CR
clock oscillator
circuit
Prescaler
(7)
No division
Divide by 2
(8) Divide by 4
Subclock
oscillator
circuit
Divide by 2
System clock selector
(5)
(2)
Divide by 2
Divide by 8
(4)
Supply to CPU
(9)
Divide by 16
(3)
Clock
control
circuit
Supply to peripheral resources
(10)
Source clock
selection
control circuit
(1)
Main clock
oscillator
circuit
Oscillation
stabilization
wait circuit
Main PLL clock
oscillator circuit
-
PCS1 PCS0
-
-
-
-
Clock for time-base timer
Clock for watch timer
-
PLL control register (PLLC)
-
-
-
-
SRDY
System clock control register (SYCC)
(1): Main clock (FCH)
(2): Subclock (FCL)
(3): Main clock
(4): Subclock
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DIV1
DIV0
SWT3 SWT2 SWT1 SWT0 MWT3 MWT2 MWT1 MWT0
Oscillation stabilization wait time setting register (WATR)
(5): Main CR clock (FCRH)
(6): Main CR reference clock (FCRHS)
(7): Sub-CR clock (FCRL)
(8): Source clock
(9) : Machine clock (MCLK)
(10): PCS[1:0]=00, main clock is selected ;
PCS[1:0] =01/10/11, main PLL clock is selected.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
MB95410H/470H Series
The clock controller consists of the following blocks:
● Main clock oscillator circuit
This block is the oscillator circuit for the main clock.
● Subclock oscillator circuit
This block is the oscillator circuit for the subclock.
● Main PLL clock oscillator circuit
This block is the oscillator circuit for the main PLL clock.
● Main CR clock oscillator circuit
This block is the oscillator circuit for the main CR clock.
● Sub-CR clock oscillator circuit
This block is the oscillator circuit for the sub-CR clock.
● System clock selector
This block selects a clock according to the clock mode used from the following five types of
source clock: main clock, main PLL clock, subclock, main CR clock and sub-CR clock. The
source clock selected is divided by the prescaler. The divided clock is called "machine clock",
which is to be supplied to the clock control circuit.
● Clock control circuit
This block controls the supply of the machine clock to the CPU and each peripheral resource
according to the standby mode used or oscillation stabilization wait time.
● Oscillation stabilization wait circuit
This block outputs one of the 14 types of oscillation stabilization signals created by a dedicated
timer in the oscillation stabilization wait circuit as the oscillation stabilization signal for the
main clock, or one of the 15 types of oscillation stabilization signals created by the same
dedicated timer as the oscillation stabilization wait time signal for the subclock.
● System clock control register (SYCC)
This register is used to select the machine clock divide ratio.
● Standby control register (STBC)
This register is used to control the transition from RUN state to standby mode, the setting of
pin states in stop mode, time-base timer mode, or watch mode, and the generation of software
resets.
● PLL control register (PLLC)
This register is used to set the multiplier of PLL oscillation.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
● System clock control register 2 (SYCC2)
This register is used to enable/disable the oscillations of the main clock, main CR clock,
subclock, and sub-CR clock, current clock mode display and clock mode selection.
● Oscillation stabilization wait time setting register (WATR)
This register is used to set the oscillation stabilization wait time for the main clock and
subclock.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
MB95410H/470H Series
■ Clock Modes
There are five clock modes: main clock mode, main PLL clock mode, main CR clock mode,
subclock mode and sub-CR clock mode.
Table 6.1-1 shows the relationships between the clock modes and the machine clock (operating
clock for the CPU and peripheral functions).
Table 6.1-1
Clock Modes and Machine Clock Selection
Clock mode
Machine clock
Main clock mode
The machine clock is generated by dividing the main clock by two.
Main PLL clock mode
The machine clock is generated by multiplying the main clock by the PLL
multiplier.
Main CR clock mode
The machine clock is generated from the main CR clock.
Subclock mode
The machine clock is generated by dividing the subclock by two.
Sub-CR clock mode
The machine clock is generated by dividing the sub-CR clock by two.
In any clock mode, the frequency of a selected clock can be divided. In addition, in a mode in
which the main CR clock is used, the clock frequency can also be selected.
■ Peripheral Function not Affected by Clock Mode
The peripheral function listed in the table below is not affected by the clock mode, division, or
CR multiplier settings. Table 6.1-2 lists the peripheral function not affected by the clock mode.
Table 6.1-2
Peripheral Function Not Affected by Clock Mode
Peripheral function
Watchdog timer
Operating clock
Main clock or main PLL clock (with time-base timer output selected)
Subclock (with watch prescaler output selected)
For some peripheral functions other than the one listed above, the time-base timer or the watch
prescaler can be selected as the count clock. Check the description of each peripheral resource
for details.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
MB95410H/470H Series
■ Standby Mode
The clock controller selects whether to enable or disable clock oscillation and clock supply to
the internal circuitry according to the standby mode selected. With the exception of time-base
timer mode and watch mode, the standby mode can be set independently of the clock mode.
Table 6.1-3 shows the relationships between standby modes and clock supply states.
Table 6.1-3
Standby Mode and Clock Supply States
Standby mode
Clock supply state
Sleep mode
Clock supply to the CPU is stopped. As a result, the CPU stops operating, but other
peripheral functions continue operating.
Time-base timer mode
Clock signals are only supplied to the time-base timer and the watch prescaler, while the
clock supply to other circuits is stopped. As a result, all the functions other than the timebase timer, watch prescaler, external interrupt, and low-voltage detection reset (option)
are stopped.
The time-base timer mode can be used in main clock (or main PLL clock) mode and
main CR clock mode.
Watch mode
Main clock (or main PLL clock) oscillation is stopped. Clock signals are supplied only
to the watch prescaler, while clock supply to other circuits is stopped. As a result, all the
functions other than the watch prescaler, external interrupt, and low-voltage detection
reset (option) are stopped.
The watch mode is the standby mode that can be used in subclock mode and sub-CR
clock mode.
Stop mode
Main clock (or main PLL clock) oscillation and subclock oscillation are stopped, and
clock supply to all circuits is stopped. As a result, all the functions other than external
interrupt and low-voltage detection reset (option) are stopped.
Note:
Clocks that are not mentioned in Table 6.1-3 are supplied under particular settings.
For example, with main clock (or main PLL clock) mode being used in stop mode, when
SYCC2:SOSCE and SYCC2:SCRE have been set to "1", the watch prescaler operates.
In addition, with the hardware watchdog timer already started, the watchdog timer
operates also in standby mode.
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CHAPTER 6 CLOCK CONTROLLER
6.1 Overview of Clock Controller
MB95410H/470H Series
■ Combinations of Clock Mode and Standby Mode
Table 6.1-4 and Table 6.1-5 list the combinations of clock mode and standby mode and the
respective operating states of different internal circuits with different combinations of clock
mode and standby mode.
Table 6.1-4
Combinations of Standby Mode and Clock Mode and Internal Operating States (1)
RUN
Function
Sleep
Main clock
Main clock
(or main
Main CR Subclock
Sub-CR
(or main
Main CR Subclock
Sub-CR
PLL clock) clock mode
mode
clock mode PLL clock) clock mode
mode
clock mode
mode
mode
Main clock (or
main PLL clock)
Operating
Stopped*1
Main CR clock
Stopped*2
Operating
Stopped
Operating
Stopped*1
Stopped
Stopped*2
Operating
Subclock
Operating*3
Operating
Sub-CR clock
Operating*4
Operating*4
CPU
Stopped
Stopped
Operating*3
Operating*3
Operating
Operating*3
Operating
Operating*4
Operating*4
Operating
Operating
Operating
Stopped
Stopped
Operating
Operating
Value held
Value held
Operating
Operating
Output held
Output held
Flash memory
RAM
I/O ports
Time-base timer
Watch prescaler
External interrupt
Hardware
watchdog timer
Software watchdog
timer
Low-voltage
detection reset
Other peripheral
functions
Operating
Stopped
Operating
Stopped
Operating*3, *4
Operating
Operating*3, *4
Operating
Operating
Operating
Operating
Operating
Operating
Operating
Operating*5
Operating*5
Operating
Operating
Stopped
Stopped
Operating
Operating
Operating
Operating
Operating
Operating
Operating
Operating
*1: The main clock (or main PLL clock) operates when the main clock oscillation enable bit in the system clock
control register 2 (SYCC2:MOSCE) is set to "1".
*2: The main CR clock operates when main CR clock oscillation enable bit in the system clock control register 2
(SYCC2:MCRE) is set to "1".
*3: The module operates when the subclock oscillation enable bit in the system clock control register 2
(SYCC2:SOSCE) is set to "1".
*4: The module operates when the sub-CR clock oscillation enable bit in the system clock control register 2
(SYCC2:SCRE) is set to "1".
*5: The hardware watchdog timer stops when the hardware watchdog timer is disabled by the non-volatile
register in standby mode.
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6.1 Overview of Clock Controller
MB95410H/470H Series
Table 6.1-5
Combinations of Standby Mode and Clock Mode and Internal Operating States (2)
Time-base timer
Function
Watch prescaler
Main clock
Main clock
(or main
Main CR Subclock
Sub-CR
(or main
Main CR Subclock
Sub-CR
PLL clock) clock mode
mode
clock mode PLL clock) clock mode
mode
clock mode
mode
mode
Main clock (or
main PLL clock)
Operating
Stopped*1
Main CR clock
Stopped*2
Operating
Stopped
Stopped
Stopped
Subclock
Operating*3
Operating
Sub-CR clock
Operating*4
Operating*4
CPU
Stop
Stopped
Operating*3
Operating*3
Operating
Operating*4
Stopped
Stopped
Stopped
Stopped
Stopped
Value held
Value held
Value held
Output held / Hi-Z
Output held
Output held/Hi-Z
Flash memory
RAM
I/O ports
Time-base timer
Watch prescaler
External interrupt
Hardware
watchdog timer
Software watchdog
timer
Low-voltage
detection reset
Other peripheral
functions
Operating
Stopped
Operating*3, *4
Operating
Stopped
Operating
Operating
Operating
Operating*5
Operating*5
Operating*5
Stopped
Stopped
Stopped
Operating
Operating
Operating
Stopped
Stopped
Stopped
Operating*3, 4
Stopped
*1: The main clock (or main PLL clock) operates when the main clock oscillation enable bit in the system clock
control register 2 (SYCC2:MOSCE) is set to "1".
*2: The main CR clock operates when main CR clock oscillation enable bit in the system clock control register 2
(SYCC2:MCRE) is set to "1".
*3: The module operates when the subclock oscillation enable bit in the system clock control register 2
(SYCC2:SOSCE) is set to "1".
*4: The module operates when the sub-CR clock oscillation enable bit in the system clock control register 2
(SYCC2:SCRE) is set to "1".
*5: The hardware watchdog timer stops when the hardware watchdog timer is disabled by the non-volatile
register in standby mode.
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CHAPTER 6 CLOCK CONTROLLER
6.2 Oscillation Stabilization Wait Time
MB95410H/470H Series
Oscillation Stabilization Wait Time
6.2
The oscillation stabilization wait time is the time after the oscillator circuit
stops oscillation until the oscillator resumes its stable oscillation at its natural
frequency. The clock controller obtains the oscillation stabilization wait time
after the start of oscillation by counting a specific number of oscillation clock
cycles. During the oscillation stabilization wait time, the clock controller stops
clock supply to internal circuits.
■ Oscillation Stabilization Wait Time
The clock controller obtains the oscillation stabilization wait time after the start of oscillation
by counting a specific number of oscillation clock cycles. During the oscillation stabilization
wait time, the clock controller stops clock supply to internal circuits.
When the power is switched on, or when a state transition request making the oscillator start
from the oscillation stop state is generated due to a change of clock mode caused by a reset, by
an interrupt in standby mode or by the software operation, the clock controller automatically
waits for the oscillation stabilization wait time of the main clock (or main PLL clock) or of the
subclock to elapse before making the clock mode transit to another mode.
Figure 6.2-1 shows how the oscillator operates immediately after starting oscillating.
Figure 6.2-1 Behavior of Oscillator Immediately after Starting Oscillation
Oscillation time of
oscillator
Normal operation
Operation after returning
Oscillation stabilization from stop mode or a reset
wait time
(
)
X1
Oscillation started
Oscillation stabilized
Oscillation stabilization wait time of main clock (or main PLL clock), subclock, main CR
clock, sub-CR clock is counted by using a dedicated counter. The count value can be set in the
oscillation stabilization wait time setting register (WATR). Set it in keeping with the oscillator
characteristics.
When a power-on reset occurs, the oscillation stabilization wait time is fixed at the initial
value.
Table 6.2-1 shows the length of oscillation stabilization wait time.
Table 6.2-1
Oscillation Stabilization Wait Time
Clock
Reset source
Power-on reset
Main clock (or main PLL clock)
Subclock
Oscillation stabilization wait time
Initial value: (214-2)/FCH (FCH: main clock frequency)
Register settings (WATR:MWT3, MWT2, MWT1, MWT0)*
Other than power-on reset *: MWT3-MWT0 are fixed at "1111B" if the main PLL
clock is used.
Power-on reset
Initial value: (215-2)/FCL (FCL: subclock frequency)
Other than power-on reset Register settings (WATR:SWT3, SWT2, SWT1, SWT0)
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6.2 Oscillation Stabilization Wait Time
MB95410H/470H Series
After the oscillation stabilization wait time of the main clock (or main PLL clock) ends, the
measurement of the oscillation stabilization wait time of the subclock is started.
■ PLL Clock Oscillation Stabilization Wait Time
As with the oscillation stabilization wait time of the oscillator, the clock controller
automatically waits for the PLL clock oscillation stabilization wait time to elapse after a
request for state transition from PLL oscillation stopped state to oscillation start is generated
via an interrupt in standby mode or a change of clock mode by software. Note that the PLL
clock oscillation stabilization wait time changes according to the PLL startup timing.
Table 6.2-2 shows the PLL oscillation stabilization wait time.
Table 6.2-2
PLL Oscillation Stabilization Wait Time
PLL oscillation stabilization wait time
Main PLL clock
(214-2)/FCH
■ CR Clock Oscillation Stabilization Wait Time
As with the oscillation stabilization wait time of the oscillator, when a state transition request
making CR oscillation start from the CR oscillation stop state is generated due to a change of
clock mode caused by an interrupt in standby mode or by the software operation, the clock
controller automatically waits for the CR oscillation stabilization wait time to elapse.
Table 6.2-3 shows the CR oscillation stabilization wait time.
Table 6.2-3
CR Oscillation Stabilization Wait Time
CR oscillation stabilization wait time
Main CR clock
28/FCRHS*
Sub-CR clock
25/FCRL
*: FCRHS: 1 MHz
■ Oscillation Stabilization Wait Time and Clock Mode/Standby Mode Transition
If state transition occurs, the clock controller automatically waits for the oscillation
stabilization wait time to elapse whenever necessary. Depending on the circumstances under
which state transition occurs, the clock controller does not wait for the oscillation stabilization
wait time to elapse even if state transition occurs.
For details on state transition, see "6.8 Clock Modes" and "6.9 Operations in Low-power
Consumption Mode (Standby Mode)".
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CHAPTER 6 CLOCK CONTROLLER
6.3 System Clock Control Register (SYCC)
6.3
MB95410H/470H Series
System Clock Control Register (SYCC)
The system clock control register (SYCC) is used to select the machine clock
divide ratio, and indicates the condition of subclock oscillation stabilization.
■ Configuration of System Clock Control Register (SYCC)
Figure 6.3-1 Configuration of System Clock Control Register (SYCC)
Address
0007H
bit7
-
bit6
-
bit5
-
bit4
-
bit3
SRDY
bit2
-
bit1
DIV1
bit0
DIV0
R0/WX
R0/WX
R0/WX
R0/WX
R/WX
R0/WX
R/W
R/W
DIV1
0
0
1
1
DIV0
0
1
0
1
Initial value
0000X011B
Machine clock divide ratio select bits
Source clock (No division)
Source clock / 4
Source clock / 8
Source clock / 16
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
SRDY
Subclock oscillation stabilization bit
0
Indicates the subclock oscillation stabilization wait state or
subclock oscillation has been stopped.
1
Indicates subclock oscillation has become stable.
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
R/W
R/WX
R0/WX
X
72
:
:
:
:
:
:
Readable/writable (The read value is the same as the write value.)
Read only (Readable. Writing a value to this bit has no effect on operation.)
The read value is always “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Indeterminate
Initial value
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6.3 System Clock Control Register (SYCC)
MB95410H/470H Series
Table 6.3-1
Functions of Bits in System Clock Control Register (SYCC)
Bit name
bit7
to
bit4
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
Undefined bits
bit3
SRDY:
Subclock oscillation
stabilization bit
This bit indicates whether subclock oscillation has become stable.
• When the SRDY bit is set to "1", that indicates the oscillation stabilization wait time for
the subclock has elapsed.
• When the SRDY bit is set to "0", that indicates that the clock controller is in the subclock
oscillation stabilization wait state or that subclock oscillation has been stopped.
This bit is read-only. Writing data to it has no effect on operation.
bit2
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
• These bits select the machine clock divide ratio for the source clock.
• The machine clock is generated from the source clock according to the divide ratio set by
these bits.
bit1,
bit0
DIV1, DIV0:
Machine clock divide
ratio select bits
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DIV1 DIV0
Machine clock divide ratio
0
0
Source clock (No division)
0
1
Source clock / 4
1
0
Source clock / 8
1
1
Source clock / 16
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CHAPTER 6 CLOCK CONTROLLER
6.4 PLL Control Register (PLLC)
6.4
MB95410H/470H Series
PLL Control Register (PLLC)
The PLL control register (PLLC) controls the main PLL clock multiplier setting.
■ Configuration of PLL Control Register (PLLC)
Figure 6.4-1 Configuration of PLL Control Register (PLLC)
Address
0006H
bit7
R0/WX
bit6
PCS1
R/W
bit5
PCS0
R/W
bit4
R0/WX
bit3
R0/WX
bit2
R0/WX
bit1
R0/WX
bit0
R0/WX
Initial value
00000000B
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
PCS1
0
0
1
1
PCS0
0
1
0
1
Main PLL clock multiplier setting bits
Main clock / 2
Main clock × 2
Main clock × 2.5
Main clock × 4
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
R/WX
R0/WX
-
Table 6.4-1
:
:
:
:
Read only (Readable. Writing a value to it has no effect on operation.)
The read value is always “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
Functions of Bits in PLL Control Register (PLLC)
Bit name
bit7
Undefined bit
Function
The read value is always "0". Writing a value to this bit has no effect on operation.
These bits set the multiplier of the main PLL clock.
PCS1 PCS0
bit6,
bit5
PCS1, PCS0:
Main PLL clock
multiplier setting bits
Main PLL clock multiplier
0
0
Main clock / 2
0
1
Main clock × 2
1
0
Main clock × 2.5
1
1
Main clock × 4
Note: The value of these bits can only be modified when main PLL clock is stopped.
Therefore, they are updated only in main CR clock mode, sub-CR clock mode and
subclock mode.
If there is a transition from main CR clock mode to main PLL mode and a change of
PLL clock multiplier, the MOSCE bit in SYCC2 is not allowed to be set to "1" until
the PLLC register is set.
bit4
to
bit0
74
Their read values are always "0". Writing values to these bits has no effect on operation.
Undefined bits
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6.5 Oscillation Stabilization Wait Time Setting Register
(WATR)
MB95410H/470H Series
6.5
Oscillation Stabilization Wait Time Setting Register
(WATR)
This register is used to set the oscillation stabilization wait time.
■ Configuration of Oscillation Stabilization Wait Time Setting Register (WATR)
Figure 6.5-1 Configuration of Oscillation Stabilization Wait Time Setting Register (WATR)
Address
bit7
bit6
bit5
bit4
0005H
SWT3
SWT2
SWT1
SWT0
R/W
R/W
R/W
R/W
MWT3MWT2MWT1MWT0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SWT3 SWT2 SWT1 SWT0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
bit3
bit2
bit1
bit0
MWT3 MWT2 MWT1 MWT0
R/W
Number
of cycles
214 - 2
213 - 2
212 - 2
211 - 2
210 - 2
29 - 2
28 - 2
27 - 2
26 - 2
25 - 2
24 - 2
23 - 2
22 - 2
21 - 2
21 - 2
21 - 2
Number
of cycles
215 - 2
214 - 2
213 - 2
212 - 2
211 - 2
210 - 2
29 - 2
28 - 2
27 - 2
26 - 2
25 - 2
24 - 2
23 - 2
22 - 2
21 - 2
21 - 2
R/W
R/W
Initial value
11111111B
R/W
Main Oscillation Clock FCH = 4 MHZ
(214 -
2)/FCH
(213 - 2)/FCH
(212 - 2)/FCH
(211 - 2)/FCH
(210 - 2)/FCH
(29 - 2)/FCH
(28 - 2)/FCH
(27 - 2)/FCH
(26 - 2)/FCH
(25 - 2)/FCH
(24 - 2)/FCH
(23 - 2)/FCH
(22 - 2)/FCH
(21 - 2)/FCH
(21 - 2)/FCH
(21 - 2)/FCH
About 4.10 ms
About 2.05 ms
About 1.02 ms
511.5 μs
255.5 μs
127.5 μs
63.5 μs
31.5 μs
15.5 μs
7.5 μs
3.5 μs
1.5 μs
0.5 μs
0.0 μs
0.0 μs
0.0 μs
Sub-oscillation Clock FCL = 32.768 kHZ
(215 -
2)/FCL
(214 - 2)/FCL
(213 - 2)/FCL
(212 - 2)/FCL
(211 - 2)/FCL
(210 - 2)/FCL
(29 - 2)/FCL
(28 - 2)/FCL
(27 - 2)/FCL
(26 - 2)/FCL
(25 - 2)/FCL
(24 - 2)/FCL
(23 - 2)/FCL
(22 - 2)/FCL
(21 - 2)/FCL
(21 - 2)/FCL
About 1.00 s
About 0.5 s
About 0.25 s
About 0.125 s
About 62.44 ms
About 31.19 ms
About 15.56 ms
About 7.75 ms
About 3.85 ms
About 1.89 ms
About 915.5 μs
About 427.2 μs
About 183.1 μs
About 61.0 μs
0.0 μs
0.0 μs
: Readable/writable (The read value is the same as the write value.)
: Initial value
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6.5 Oscillation Stabilization Wait Time Setting Register
(WATR)
Table 6.5-1
MB95410H/470H Series
Functions of Bits in Oscillation Stabilization Wait Time Setting Register (WATR)
(1 / 2)
Bit name
Function
These bits set the subclock oscillation stabilization wait time.
bit7
to
bit4
SWT3, SWT2,
SWT1, SWT0:
Subclock oscillation
stabilization wait time
select bits
SWT3, SWT2, SWT1,
SWT0
Number of
cycles
1111B
215-2
(215-2)/FCL
About 1.0 s
1110B
214-2
(214-2)/FCL
About 0.5 s
1101B
213-2
(213-2)/FCL
About 0.25 s
1100B
212-2
(212-2)/FCL
About 0.125 s
1011B
211-2
(211-2)/FCL
About 62.44 ms
1010B
210-2
(210-2)/FCL
About 31.19 ms
1001B
29-2
(29-2)/FCL
About 15.56 ms
1000B
28-2
(28-2)/FCL
About 7.75 ms
0111B
27-2
(27-2)/FCL
About 3.85 ms
0110B
26-2
(26-2)/FCL
About 1.89 ms
0101B
25-2
(25-2)/FCL
About 915.5 μs
0100B
24-2
(24-2)/FCL
About 427.2 μs
0011B
23-2
(23-2)/FCL
About 183.1 μs
0010B
22-2
(22-2)/FCL
About 61.0 μs
0001B
21-2
(21-2)/FCL
0.0 μs
0000B
21-2
(21-2)/FCL
0.0 μs
Subclock FCL = 32.768 kHz
The number of cycles in the above table is the minimum subclock oscillation stabilization
wait time. The maximum value is the number of cycles in the above table plus 1/FCL.
Note:
Do not modify these bits during subclock oscillation stabilization wait time.
Modify them either when the subclock oscillation stabilization bit in the system
clock control register (SYCC:SRDY) has been set to "1", or in main clock (or
main PLL clock) mode, main CR clock mode or sub-CR clock mode. These bits
can also be modified when the subclock is stopped with the subclock oscillation
stop bit in the system clock control register 2 (SYCC2:SOSCE) set to "0" in main
clock (or main PLL clock) mode, main CR clock mode or sub-CR clock mode.
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6.5 Oscillation Stabilization Wait Time Setting Register
(WATR)
Functions of Bits in Oscillation Stabilization Wait Time Setting Register (WATR)
(2 / 2)
MB95410H/470H Series
Table 6.5-1
Bit name
Function
These bits set the main clock oscillation stabilization wait time.
bit3
to
bit0
MWT3, MWT2,
MWT1, MWT0:
Main clock oscillation
stabilization wait time
select bits
MWT3, MWT2, MWT1,
MWT0
Number of
cycles
1111B
214-2
(214-2)/FCH
About 4.10 ms
1110B
213-2
(213-2)/FCH
About 2.05 ms
1101B
212-2
(212-2)/FCH
About 1.02 ms
1100B
211-2
(211-2)/FCH
511.5 μs
1011B
210-2
(210-2)/FCH
255.5 μs
1010B
29-2
(29-2)/FCH
127.5 μs
1001B
28-2
(28-2)/FCH
63.5 μs
1000B
27-2
(27-2)/FCH
31.5 μs
0111B
26-2
(26-2)/FCH
15.5 μs
0110B
25-2
(25-2)/FCH
7.5 μs
0101B
24-2
(24-2)/FCH
3.5 μs
0100B
23-2
(23-2)/FCH
1.5 μs
0011B
22-2
(22-2)/FCH
0.5 μs
0010B
21-2
(21-2)/FCH
0.0 μs
0001B
21-2
(21-2)/FCH
0.0 μs
0000B
21-2
(21-2)/FCH
0.0 μs
Main clock FCH = 4 MHz
The number of cycles in the above table is the minimum main clock oscillation stabilization
wait time. The maximum value is the number of cycles in the above table plus 1/FCH.
Note:
Do not modify these bits during main clock oscillation stabilization wait time.
Modify them either when the main clock oscillation stabilization bit in the standby
control register (STBC:MRDY) has been set to "1", or in main CR clock mode,
subclock mode or sub-CR clock mode. These bits can also be modified when the
main clock is stopped with the main clock oscillation stop bit in the system clock
control register 2 (SYCC2:MOSCE) set to "0" in main CR clock mode, subclock
mode or sub-CR clock mode. In main PLL mode, these bits are not usable, and the
PLL clock oscillation stabilization wait time is fixed at (214-2)/FCH.
■ Note on Setting WATR Register
When using the dual operation Flash function of a device not equipped with the low-voltage
detection reset, always set the main clock oscillation stabilization wait time to 90 μs or above
(set WATR:MWT[3:0] to "1010B" or above with the main clock frequency FCH being 4 MHz).
The above setting requirement applies to the following products:
MB95F414H/F416H/F418H/F474H/F476H/F478H
When a flash write/erase operation occurs with the main clock oscillation stabilization wait
time having ended within 90 μs, the operation may fail.
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CHAPTER 6 CLOCK CONTROLLER
6.6 Standby Control Register (STBC)
6.6
MB95410H/470H Series
Standby Control Register (STBC)
The standby control register (STBC) is used to control transition from the RUN
state to sleep mode, stop mode, time-base timer mode, or watch mode, to set
the pin state in stop mode, time-base timer mode, and watch mode, and to
control the generation of software resets.
■ Standby Control Register (STBC)
Figure 6.6-1 Standby Control Register (STBC)
Address
bit7
bit6
bit5
bit4
bit3
0008H
STP
SLP
SPL
SRST
TMD
R0,W
R0,W
R/W
R0,W
R0,W
MRDY
0
Indicates main clock oscillation stabilization wait state or main clock oscillation has been stopped.
1
bit2
bit1
bit0
Initial value
00000XXXB
SCRDY MCRDY MRDY
R/WX
R/WX
R/WX
Main clock oscillation stabilization bit
Indicates main clock oscillation has become stable.
MCRDY
Main CR clock oscillation stabilization bit
0
Indicates main CR clock oscillation stabilization wait state or main CR clock oscillation has been stopped.
1
Indicates main CR clock oscillation has become stable.
SCRDY
Sub-CR clock oscillation stabilization bit
0
Indicates sub-CR clock oscillation stabilization wait state or sub-CR clock oscillation has been stopped.
1
Indicates sub-CR clock oscillation has become stable.
Watch bit
TMD
Read
Write
0
"0" is always read.
Has no effect on operation.
1
-
Subclock mode/Sub-CR clock mode
Causes transition to watch mode
Software reset bit
SRST
Read
Write
0
"0" is always read.
Has no effect on operation
1
-
Generates a 3-machine clock reset signal
SPL
0
1
Pin state setting bit
Holds external pins in their immediately preceding state in stop mode, time-base timer mode, or watch mode.
Places external pins in a high impedance state in stop mode, time-base timer mode, or watch mode.
Sleep bit
SLP
Read
Write
0
"0" is always read.
Has no effect on operation
1
-
Causes transition to sleep mode
Stop bit
STP
0
1
R/W
R/WX
R0,W
X
78
Main clock mode/Main PLL mode/
Main CR clock mode
Causes transition to time-base
timer mode
:
:
:
:
:
Read
Write
"0" is always read.
Has no effect on operation
-
Causes transition to stop mode
Readable/writable (The read value is the same as the write value.)
Read only (Readable. Writing a value to this bit has no effect on operation.)
Write only (Writable. The read value is “0”.)
Indeterminate
Initial value
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
Table 6.6-1
CHAPTER 6 CLOCK CONTROLLER
6.6 Standby Control Register (STBC)
Functions of Bits in Standby Control Register (STBC)
Bit name
Function
STP:
Stop bit
This bit sets the transition to stop mode.
Writing "0": This bit is meaningless.
Writing "1": Causes the device to transit to stop mode.
When this bit is read, it always returns "0".
Note:
After an interrupt request is issued, writing "1" to this bit is ignored. For details,
see "6.9.1 Notes on Using Standby Mode".
SLP:
Sleep bit
This bit sets the transition to sleep mode.
Writing "0": This bit is meaningless.
Writing "1": Causes the device to transit to sleep mode.
When this bit is read, it always returns "0".
Note:
After an interrupt request is issued, writing "1" to this bit is ignored. For details,
see "6.9.1 Notes on Using Standby Mode".
bit5
SPL:
Pin state setting bit
This bit sets the states of external pins in stop mode, time-base timer mode, and watch
mode.
Writing "0": The state (level) of an external pin is kept in stop mode, time-base timer
mode and watch mode.
Writing "1": An external pin becomes high impedance in stop mode, time-base timer
mode and watch mode. (A pin for which connection to a pull-up resistor has
been selected in the pull-up register is pulled up.)
bit4
SRST:
Software reset bit
This bit sets a software reset.
Writing "0": Has no effect on operation.
Writing "1": Generates a 3-machine clock reset signal.
When this bit is read, it always returns "0".
bit3
TMD:
Watch bit
This bit sets transition to time-base timer mode or watch mode.
• Writing "1" to this bit in main clock (or main PLL clock) mode or main CR clock mode
causes the device to transit to time-base timer mode.
• Writing "1" to this bit in subclock mode or sub-CR clock mode causes the device to
transit to watch mode.
• Writing "0" to this bit has no effect on operation.
• When this bit is read, it always returns "0".
Note:
After an interrupt request is issued, writing "1" to this bit is ignored. For details,
see "6.9.1 Notes on Using Standby Mode".
bit2
This bit indicates whether sub-CR clock oscillation has become stable.
• When the SCRDY bit is set to "1", that indicates the oscillation stabilization wait time for
SCRDY:
the sub-CR clock has elapsed
Sub-CR clock
• When the SCRDY bit is set to "0", that indicates that the clock controller is in the sub-CR
oscillation stabilization
clock oscillation stabilization wait state or that sub-CR clock oscillation has been
bit
stopped.
This bit is read-only. Writing a value to it has no effect on operation.
bit1
This bit indicates whether main CR clock oscillation has become stable.
• When the MCRDY bit is set to "1", that indicates the oscillation stabilization wait time
MCRDY:
for the main CR clock has elapsed.
Main CR clock
• When the MCRDY bit is set to "0", that indicates that the clock controller in the main CR
oscillation stabilization
clock oscillation stabilization wait state or that main CR clock stabilization has been
bit
stopped.
This bit is read-only. Writing a value to it has no effect on operation.
bit0
This bit indicates whether main clock (or main PLL clock) oscillation has become stable.
• When the MRDY bit is set to "1", that indicates that the oscillation stabilization wait time
for the main clock (or main PLL clock) has elapsed.
• When the MRDY bit is set to "0", that indicates that the clock controller is in the main
clock (or main PLL clock) oscillation stabilization wait state or that main clock (or main
PLL clock) oscillation has been stopped.
This bit is read-only. Writing a value to it has no effect on operation.
bit7
bit6
MRDY:
Main clock (or main
PLL clock) oscillation
stabilization bit
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CHAPTER 6 CLOCK CONTROLLER
6.6 Standby Control Register (STBC)
MB95410H/470H Series
Notes:
• Set the standby mode after making sure that the transition to clock mode has been
completed by comparing the values of the clock mode monitor bits
(SYCC2:RCM1,RCM0) and clock mode select bits (SYCC2:RCS1,RCS0) in the
system clock control register 2.
• If two or more of the following bits, stop bit (STP), sleep bit (SLP), software reset bit
(SRST) and watch bit (TMD), are set to "1" together, the order of priority for such bits
is as follows:
(1) Software reset bit (SRST)
(2) Stop bit (STP)
(3) Watch bit (TMD)
(4) Sleep bit (SLP)
When released from standby mode, the device returns to the normal operating state.
80
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CHAPTER 6 CLOCK CONTROLLER
6.7 System Clock Control Register 2 (SYCC2)
MB95410H/470H Series
6.7
System Clock Control Register 2 (SYCC2)
The system clock control register 2 (SYCC2) is used to indicate the current
clock mode and switch the clock mode, and control subclock, sub-CR clock,
main clock (or main PLL clock), main CR clock oscillations.
■ Configuration of System Clock Control Register 2 (SYCC2)
Figure 6.7-1 Configuration of System Clock Control Register 2 (SYCC2)
Address
000DH
bit7
bit6
bit5
RCM1
RCM0
RCS1
R/WX
R/WX
R/W
bit4
bit3
bit2
bit1
RCS0 SOSCE MOSCE SCRE
R/W
Initial value
MCRE
XX100011B
R/W
R/W
MCRE
0
Main CR clock oscillation enable bit
Disables main CR clock oscillation.
1
SCRE
0
1
R/W
bit0
R/W
Enables main CR clock oscillation.
Sub-CR clock oscillation enable bit
Disables sub-CR clock oscillation.
Enables sub-CR clock oscillation.
MOSCE Main clock (or main PLL clock) oscillation enable bit
Disables main clock (or main PLL clock) oscillation.
0
1
Enables main clock (or main PLL clock) oscillation.
SOSCE
Subclock oscillation enable bit
Disables subclock oscillation.
0
1
R/W
R/WX
X
MN702-00005-2v0-E
:
:
:
:
Enables subclock oscillation.
RCS1
0
0
1
1
RCS0
0
1
0
1
Clock mode select bits
Sub-CR clock mode
Subclock mode
Main CR clock mode
Main clock (or main PLL clock) mode
RCM1
0
0
1
1
RCM0
0
1
0
1
Clock mode monitor bits
Sub-CR clock mode
Subclock mode
Main CR clock mode
Main clock (or main PLL clock) mode
Readable/writable (The read value is the same as the write value.)
Read only (Readable. Writing a value to it has no effect on operation.)
Indeterminate
Initial value
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CHAPTER 6 CLOCK CONTROLLER
6.7 System Clock Control Register 2 (SYCC2)
Table 6.7-1
Functions of Bits in System Clock Control Register 2 (SYCC2)
Bit name
bit7,
bit6
bit5,
bit4
bit3
bit2
bit1
bit0
82
MB95410H/470H Series
Function
RCM1, RCM0:
Clock mode monitor
bits
These bits indicate the current clock mode.
"00B": Indicates sub-CR clock mode.
"01B": Indicates subclock mode.
"10B": Indicates main CR clock mode.
"11B": Indicates main clock (or main PLL clock) mode.
These bits are read-only. Writing values to them has no effect on operation.
RCS1, RCS0:
Clock mode select bits
These bits select the current clock mode.
Writing "00B": Selects sub-CR clock mode
Writing "01B": Selects subclock mode
Writing "10B": Selects main CR clock mode
Writing "11B": Selects main clock (or main PLL clock) mode
SOSCE:
Subclock oscillation
enable bit
This bit enables/disables the subclock.
Writing "0": Disables subclock oscillation.
Writing "1": Enables subclock oscillation.
• If the RCS bits are set to "01B", this bit is set to "1".
• If the RCS or RCM bits are "01B", writing "0" to this bit is ignored, and its value remains
unchanged.
MOSCE:
Main clock (or main
PLL clock) oscillation
enable bit
This bit enables/disables the main clock (or main PLL clock).
Writing "0": Disables main clock (or main PLL clock) oscillation.
Writing "1": Enables main clock (or main PLL clock) oscillation.
• If the RCS bits are set to "11B", this bit is set to "1".
• If the RCS or RCM bits are "11B", writing "0" to this bit is ignored, and its value remains
unchanged.
• When the RCM bits are modified to other values from "11B", this bit is set to "0".
• If the RCM1 bit is "0", writing "1" to this bit is ignored.
SCRE:
Sub-CR clock
oscillation enable bit
This bit enables/disables the sub-CR clock.
Writing "0": Disables sub-CR clock oscillation.
Writing "1": Enables sub-CR clock oscillation.
• If the RCS bits are set to "00B", this bit is set to "1".
• If the RCS or RCM bits are "00B", writing "0" to this bit is ignored, and its value remains
unchanged.
• If the hardware watchdog timer is used, this bit is set to "1".
MCRE:
Main CR clock
oscillation enable bit
This bit enables/disables the main CR clock.
Writing "0": Disables main CR clock oscillation.
Writing "1": Enables main CR clock oscillation.
• If the RCS bits are set to "10B", the bit is set to "1".
• If the RCS or RCM bits are "10B", writing "0" to this bit is ignored, and its value remains
unchanged.
• When the RCM bits are modified to other values from "10B", the bit is set to "0".
• If the RCM1 bit is "0", writing "1" to this bit is ignored.
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
6.8
Clock Modes
CHAPTER 6 CLOCK CONTROLLER
6.8 Clock Modes
There are five clock modes: main clock, main PLL clock mode, subclock mode,
main CR clock mode and sub-CR clock mode. Mode switching occurs
according to the settings in the system clock control register 2 (SYCC2).
■ Operations in Main Clock (or main PLL Clock) Mode
In main clock (or main PLL clock) mode, the main clock (or the main PLL clock) is used as the
machine clock for the CPU and peripheral functions.
The time-base timer operates using the main clock (or the main PLL clock).
The watch prescaler and watch counter operate with the subclock or the sub-CR clock.
While the device is operating in main clock (or main PLL clock) mode, it can be set to transit
to one of the following standby mode: sleep mode, stop mode, or time-base timer mode.
After a reset, the device always enters main CR clock mode regardless of the clock mode used
before that reset.
■ Operations in Subclock Mode
In subclock mode, main clock (or main PLL clock) oscillation is stopped* and the subclock is
used as the machine clock for the CPU and peripheral functions. In this mode, the time-base
timer stops as it requires the main clock (or main PLL clock) for operation.
While the device is operating in subclock clock mode, it can be set to transit to one of the
following standby mode: sleep mode, stop mode, or watch mode.
■ Operations in Main CR Clock Mode
In main CR clock mode, the main CR clock is used as the machine clock for the CPU and
peripheral functions. The time-base timer and the watchdog timer operate using the main CR
clock.
The watch prescaler and watch counter operate with the subclock or the sub-CR clock.
While the device is operating in main CR clock mode, it can be set to transit to one of the
following standby mode: sleep mode, stop mode, or time-base timer mode.
■ Operations in Sub-CR Clock Mode
In sub-CR clock mode, main clock (or main PLL clock) oscillation is stopped* and the sub-CR
clock is used as the machine clock for the CPU and peripheral functions. In this mode, the
time-base timer stops as it requires the main clock (or main PLL clock) for operation. The
watch prescaler and watch counter operates using the sub-CR clock.
While the device is operating in sub-CR clock mode, it can be set to transit to one of the
following standby mode: sleep mode, stop mode, or watch mode.
*: The main clock (or main PLL clock) and the main CR clock are automatically disabled
(SYCC2:MOSCE is set to "0" or SYCC2:MCRE is set to "0") when the clock mode transits from main
clock (or main PLL clock) mode or main CR clock mode to another clock mode. If the new clock mode
is subclock mode or sub-CR clock mode, the main clock (or main PLL clock) and the main CR clock
cannot be enabled by writing "1" to SYCC2:MOSCE and "1" to SYCC2:MCRE respectively.
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CHAPTER 6 CLOCK CONTROLLER
6.8 Clock Modes
MB95410H/470H Series
■ Clock Mode State Transition Diagram
There are five clock modes: main clock mode, main PLL clock mode, subclock mode, main
CR clock mode and sub-CR clock mode. The device can switch between these modes
according to the settings in the system clock control register 2 (SYCC2).
Figure 6.8-1 Clock Mode State Transition Diagram
Power on
A reset occurs in any other state.
Reset state
<1>
Main CR clock
oscillation
stabilization
wait time
(10)
Main CR
clock oscillation
stabilization wait time
(8)
Main clock (or
main PLL clock)
mode
(7)
Main CR clock mode
(5)
(6)
(4)
(3)
(2)
Main clock (or
main PLL clock)
oscillation
stabilization
wait time
(9)
(12)
(11)
(1)
Sub-CR clock
oscillation
stabilization
wait time
Subclock
oscillation
stabilization
wait time
Main CR clock
oscillation
stabilization
wait time
Main clock (or
main PLL clock)
oscillation
stabilization
wait time
(13)
(18)
(17)
Sub-CR clock
oscillation
stabilization
wait time
Sub-CR clock mode
(20)
(19)
(15)
Subclock mode
(16)
Subclock
oscillation
stabilization
wait time
(14)
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MN702-00005-2v0-E
MB95410H/470H Series
Table 6.8-1
Clock Mode State Transition Table (1 / 2)
Current
State
<1> Reset state
Next State
Main CR clock
Sub-CR clock
The device transits to sub-CR clock mode when the clock mode select bits in
the system clock control register 2 (SYCC2:RCS1, RCS0) are set to "00B".
However, if the sub-CR has been stopped according to the setting of the subCR clock oscillation enable bit in the system clock control register 2
(SYCC2:SCRE), the device waits for the sub-CR clock oscillation stabilization
wait time to elapse before transiting to sub-CR clock mode. In other words, if
the sub-CR clock oscillation is enabled in advance and the sub-CR clock
oscillation stabilization bit in the standby control register (STBC:SCRDY) is
"1", the device transits to sub-CR clock mode immediately after the clock
mode select bits (SYCC2:RCS1, RCS0) are set to "00B".
Subclock
When the clock mode select bits in the system clock control register 2
(SYCC2:RCS1, RCS0) are set to "01B", the device transits to subclock mode
after waiting for the subclock oscillation stabilization wait time.
The device does not wait for the subclock oscillation stabilization wait time to
elapse if the subclock has been oscillating according to the setting of the
subclock oscillation enable bit in the system clock control register 2
(SYCC2:SOSCE). In other words, if subclock oscillation is enabled in advance
and the subclock oscillation stabilization bit in the system clock control
register (SYCC:SRDY) is "1", the device transits to subclock mode
immediately after the clock mode select bits (SYCC2:RCS1, RCS0) are set to
"01B".
(2)
(3)
Main CR
clock
(4)
(6)
Description
After a reset, the device waits for the main CR clock oscillation stabilization
wait time to elapse and transits to main CR clock mode. Even if that reset is a
watchdog reset, software reset or external reset caused in any clock mode, the
device waits for the sub-CR clock oscillation stabilization wait time and the
main CR clock oscillation stabilization wait time to elapse.
(1)
(5)
CHAPTER 6 CLOCK CONTROLLER
6.8 Clock Modes
When the clock mode select bits in the system clock control register 2
(SYCC2:RCS1, RCS0) are set to "11B", the device transits to main clock (or
main PLL clock) mode after waiting for the main clock (or main PLL clock)
oscillation stabilization wait time.
The device does not wait for the main clock (or main PLL clock) oscillation
stabilization wait time to elapse if the main clock (or main PLL clock) has been
Main clock (or main
oscillating according to the setting of the main clock (or main PLL clock)
PLL clock)
oscillation enable bit in the system clock control register 2 (SYCC2:MOSCE).
In other words, if main clock (or main PLL clock) oscillation is enabled in
advance and the main clock (or main PLL clock) oscillation stabilization bit in
the standby control register (STBC:MRDY) is "1", the device transits to main
clock (or main PLL clock) mode immediately after the clock mode select bits
(SYCC2:RCS1, RCS0) are set to "11B".
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CHAPTER 6 CLOCK CONTROLLER
6.8 Clock Modes
Table 6.8-1
Clock Mode State Transition Table (2 / 2)
Current
State
Next State
Main CR clock
Sub-CR clock
Same as (1) and (2)
Subclock
Same as (3) and (4)
Main CR clock
When the clock mode select bits in the system clock control register 2
(SYCC2:RCS1, RCS0) are set to "10B", the device transits to main CR clock
mode after waiting for the main CR clock oscillation stabilization wait time.
Main clock (or
main PLL
clock)
(9)
(10)
(11)
(12)
(13)
Description
When the clock mode select bits in the system clock control register 2
(SYCC2:RCS1, RCS0) are set to "10B", the device transits to main CR clock
mode after waiting for the main CR clock oscillation stabilization wait time.
The device does not wait for the main CR clock oscillation stabilization wait
time to elapse if the main CR clock has been oscillating according to the
setting of the main CR clock oscillation enable bit in the system clock control
register 2 (SYCC2:MCRE). In other words, if main CR clock oscillation is
enabled in advance and the main CR clock oscillation stabilization bit in the
standby control register (STBC:MCRDY) is "1", the device transits to main CR
clock mode immediately after the clock mode select bits (SYCC2:RCS1,
RCS0) are set to "10B".
(7)
(8)
MB95410H/470H Series
When the clock mode select bits in the system clock control register 2
(SYCC2:RCS1, RCS0) are set to "11B", the device transits to main clock (or
Main
clock
(or
main
Sub-CR clock
(14)
PLL clock)
main PLL clock) mode after waiting for the main clock (or main PLL clock)
oscillation stabilization wait time.
(15)
Subclock
Same as (3) and (4)
(17)
Main CR clock
Same as (13)
(18)
Main clock (or main
Same as (14)
PLL clock)
(16)
(19)
(20)
86
Subclock
Sub-CR clock
Same as (1) and (2)
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MN702-00005-2v0-E
CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
MB95410H/470H Series
6.9
Operations in Low-power Consumption Mode
(Standby Mode)
There are four standby modes: sleep mode, stop mode, time-base timer mode
and watch mode.
■ Overview of Transiting to and Returning from Standby Mode
There are four standby modes: sleep mode, stop mode, time-base timer mode, and watch mode.
The device transits to standby mode according to the settings in the standby control register
(STBC).
The device is released from standby mode by an interrupt or a reset. Before transiting to
normal operation, the device may wait for the oscillation stabilization wait time to elapse if
necessary.
If the clock mode returns from standby mode due to a reset, the device returns to main CR
clock mode. If the clock mode returns from standby mode due to an interrupt, before transiting
to standby mode, the device returns to the clock mode in which the device was operating.
■ Pin States in Standby Mode
The pin state setting bit (STBC:SPL) of the standby control register can be used to keep the
preceding state of an I/O port or a peripheral resource pin before its transition to stop mode,
time-base timer mode or watch mode, and to set an I/O port or a peripheral resource pin to high
impedance in stop mode, time-base timer mode or watch mode.
See "APPENDIX D Pin States of MB95410H/470H Series" for the states of all pins in standby
mode.
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
6.9.1
MB95410H/470H Series
Notes on Using Standby Mode
Even if the standby control register (STBC) sets standby mode, transition to
standby mode does not occur when an interrupt request has been generated
from a peripheral resource. When the device returns from standby mode to the
normal operating state in response to an interrupt, the operation that follows
varies depending on whether the interrupt request is accepted or not.
■ Insert at least three NOP instructions immediately after a standby mode
setting instruction.
The device requires four machine clock cycles before entering standby mode after it is set in
the standby control register. During that period, the CPU executes the program. To avoid
program execution during this transition to standby mode, insert at least three NOP
instructions.
The device still operates normally even if instructions other than NOP instructions are inserted
after the instruction that sets the device to transit to standby mode. On this occasion, the
following two events may occur. Firstly, an instruction that should be executed after the
standby mode is released may be executed before the device transits to standby mode.
Secondly, the device may transit to standby mode while an instruction is being executed, and
the execution of that same instruction resumes after the device is released from standby mode
(increasing the number of instruction execution cycles).
■ Check that clock mode transition has been completed before setting the
standby mode.
Before setting the standby mode, ensure that clock-mode transition has been completed by
comparing the values of the clock mode monitor bits (SYCC2:RCM1, RCM0) and clock mode
select bits (SYCC2:RCS1, RCS0) in the system clock control register 2.
■ An interrupt request may suppress the transition to standby mode.
When the standby mode is set with an interrupt request whose interrupt level is higher than
"11B" having been issued, the device ignores the value written to the standby control register
and continues executing instructions without transiting to the standby mode set. Even after the
interrupt of that interrupt request is processed, the device does not transit to the standby mode
set.
The same operations are executed when interrupts are disabled by the interrupt enable flag
(CCR:I) and the interrupt level bits (CCR:IL1, IL0) of the condition code register of the CPU.
■ The standby mode is also released when the CPU rejects interrupts.
When an interrupt request whose interrupt level is higher than "11B" is issued in standby mode,
the device is released from standby mode, regardless of the settings of the interrupt enable flag
(CCR:I) and the interrupt level bits (CCR:IL1, IL0) of the condition code register (CCR) of the
CPU.
After being released from standby mode, the device processes interrupts if interrupts are to be
accepted according to the settings of the condition code register (CCR) of the CPU. If
interrupts are not to be accepted according to the settings of CCR, the device resumes
instruction execution from the instruction following the one executed before the device transits
to standby mode.
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
MB95410H/470H Series
■ Standby Mode State Transition Diagram
Figure 6.9-1 shows a standby mode state transition diagram.
Figure 6.9-1 Standby Mode State Transition Diagram
Power on
Reset state
A reset occurs in any state.
<1>
Main CR clock oscillation
stabilization wait time
(3)
Stop mode
Main clock(or main
PLL clock)/main
CR clock
Subclock/sub-CR
clock oscillation
stabilization wait time
(4)
(7)
Normal
(RUN) state
(5)
(8)
Watch mode
(1)
(6)
(2)
Time-base
timer mode
Table 6.9-1
Sleep mode
State Transition Table (Transitions to and from Standby Modes)
State Transition
Description
After a reset, the device transits to main CR clock mode.
Normal operation after If the reset that has occurred is a power-on reset, a watchdog reset, a software reset, or an
<1>
reset state
external reset, the device always waits for the main CR clock oscillation stabilization wait
time and the sub-CR clock oscillation stabilization wait time to elapse.
The device transits to sleep mode when "1" is written to the sleep bit in the standby control
(1)
register (STBC:SLP).
Sleep mode
(2)
The device returns to the RUN state in response to an interrupt from a peripheral resource.
The device transits to stop mode when "1" is written to the stop bit in the standby control
(3)
register (STBC:STP).
Stop mode
In response to an external interrupt, after waiting for the elapse of the oscillation stabilization
(4)
wait time required according to the current clock mode, the device returns to the RUN state.
The device transits to time-base timer mode when "1" is written to the watch bit in the
(5)
Time-base timer mode standby control register (STBC:TMD) in main clock (or main PLL clock) mode or main CR
(6)
clock mode.
(7)
Watch mode
(8)
MN702-00005-2v0-E
The device transits to watch mode when "1" is written to the watch bit in the standby control
register (STBC:TMD) in subclock mode or sub-CR clock mode.
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
6.9.2
MB95410H/470H Series
Sleep Mode
In sleep mode, the operations of the CPU and watchdog timer are stopped.
■ Operations in Sleep Mode
In sleep mode, the CPU and the operating clock for the watchdog timer are stopped. The CPU
retains the contents of registers and RAM existing at the point immediately before the device
transits to sleep mode and stops; however, all peripheral functions except the watchdog timer
continue operating.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in sleep mode, the sub-CR clock does not stop and the hardware watchdog
timer operates. For details, see "CHAPTER 32 NON-VOLATILE REGISTER (NVR)
FUNCTION".
● Transition to sleep mode
Writing "1" to the sleep bit in the standby control register (STBC:SLP) causes the device to
enter sleep mode.
● Release from sleep mode
A reset or an interrupt from a peripheral function releases the device from sleep mode.
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6.9.3
Stop Mode
CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
In stop mode, the main clock (or main PLL clock), the main CR clock and the
subclock are stopped.
■ Operations in Stop Mode
In stop mode, the main clock (or main PLL clock), the main CR clock, and the subclock are
stopped. In this mode, while retaining the contents of registers and RAM existing at the point
immediately before the device transits to stop mode, the device stops all functions except
external interrupt and low-voltage detection reset.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in stop mode, the sub-CR clock does not stop and the hardware watchdog
timer operates. For details, see "CHAPTER 32 NON-VOLATILE REGISTER (NVR)
FUNCTION".
● Transition to stop mode
Writing "1" to the stop bit in the standby control register (STBC:STP) causes the device to
transit to stop mode. At that point, if the pin state setting bit in the standby control register
(STBC:SPL) is "0", the states of the external pins are kept; if the SPL bit is "1", the states of
the external pins become high impedance (a pin is pulled up if the pull-up resistor connection
for that pin is selected in the pull-up register).
In main clock (or main PLL clock) mode or main CR clock mode, while the device is waiting
for main clock (or main PLL clock) oscillation to stabilize after being released from stop mode
by an interrupt, a time-base timer interrupt request may be generated. If the interrupt interval
time of the time-base timer is shorter than the main clock (or main PLL clock) oscillation
stabilization wait time, it is advisable to prevent any unexpected interrupt from occurring by
disabling interrupt requests output from the time-base timer before making the device transit to
stop mode
It is also advisable to disable interrupt requests output from the watch prescaler before making
the device transit to stop mode from subclock mode or sub-CR clock mode.
● Release from stop mode
The device is released from stop mode by a reset or an external interrupt. In any clock mode, if
the hardware watchdog timer is enabled in standby mode by the non-volatile register function,
the sub-CR clock does not stop, and the watchdog timer and the watch prescaler operate in stop
mode. The device can also be released from stop mode by an interrupt from the watch
prescaler. For details, see "CHAPTER 32 NON-VOLATILE REGISTER (NVR)
FUNCTION".
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
MB95410H/470H Series
Note:
If the device is released from stop mode by an interrupt, a peripheral function having
transited to stop mode during operation resumes operating from the point at which it
transited to stop mode. Therefore, some settings of that peripheral function, such as the
initial interval time of the interval timer, become undefined. Initialize that peripheral
function if necessary after releasing the device from stop mode.
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
MB95410H/470H Series
6.9.4
Time-base Timer Mode
In time-base timer mode, only the main clock (or main PLL clock) oscillator, the
subclock oscillator, the time-base timer, and the watch prescaler operate. The
CPU and the operating clock for peripheral functions are stopped in this mode.
■ Operations in Time-base Timer Mode
The time-base timer mode is a mode in which main clock (or main PLL clock) supply is
stopped except the clock supply to the time-base timer. In this mode, while retaining the
contents of registers and RAM existing at the point immediately before the device transits to
time-base timer mode, the device stops all functions except the time-base timer, external
interrupt and low-voltage detection reset.
Subclock oscillation and sub-CR clock oscillation can be enabled or disabled by the subclock
oscillation enable bit and the sub-CR clock oscillation enable bit in the system clock control
register 2 (SYCC2:SOSCE, SCRE) respectively. If the subclock oscillates, the watch prescaler
operates.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in time-base timer mode, the sub-CR clock does not stop and the hardware
watchdog timer operates. For details, see "CHAPTER 32 NON-VOLATILE REGISTER
(NVR) FUNCTION".
● Transition to time-base timer mode
If the clock mode monitor bits in the system clock control register 2 (SYCC2:RCM1, RCM0)
are "10B" or "11B", writing "1" to the watch bit in the standby control register (STBC:TMD)
causes the device to transit to time-base timer mode.
The device can transit to time-base timer mode only when the clock mode is main clock (or
main PLL clock) mode or main CR clock mode.
After the device transits to time-base timer mode, if the pin state setting bit in the standby
control register (STBC:SPL) is "0", the states of the external pins are kept; if the SPL bit is "1",
the states of the external pins become high impedance (a pin is pulled up if the pull-up resistor
connection for that pin is selected in the pull-up register).
● Release from time-base timer mode
The device is released from time-base timer mode by a reset, a time-base timer interrupt, or an
external interrupt.
Subclock oscillation and sub-CR clock oscillation can be enabled or disabled by setting the
subclock oscillation enable bit (SOSCE) and the sub-CR clock oscillation enable bit (SCRE) in
the system clock control register 2 (SYCC2). When the subclock oscillates, the device can be
released from time-base timer mode by an interrupt from the watch prescaler.
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CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
MB95410H/470H Series
Note:
If the device is released from time-base timer mode by an interrupt, a peripheral function
having transited to time-base timer mode during operation resumes operating from the
point at which it transited to time-base timer mode. Therefore, some settings of that
peripheral function, such as the initial interval time of the interval timer, become
undefined. Initialize that peripheral function if necessary after releasing the device from
time-base timer mode.
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6.9.5
Watch Mode
CHAPTER 6 CLOCK CONTROLLER
6.9 Operations in Low-power Consumption Mode
(Standby Mode)
In watch mode, only the subclock, the sub-CR clock, the watch prescaler and
the LCD controller operate. The CPU and the operating clock for peripheral
functions are stopped in this mode.
■ Operations in Watch Mode
In watch mode, while retaining the contents of registers and RAM existing at the point
immediately before the device transits to watch mode, the device stops all functions except the
watch prescaler, external interrupt and low-voltage detection reset.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in watch mode, the sub-CR clock does not stop and the hardware watchdog
timer operates. For details, see "CHAPTER 32 NON-VOLATILE REGISTER (NVR)
FUNCTION".
● Transition to watch mode
If the clock mode monitor bits in the system clock control register 2 (SYCC2:RCM1, RCM0)
are "00B" or "01B", writing "1" to the watch bit in the standby control register (STBC:TMD)
causes the device to transit to watch mode.
The device can transit to watch mode only when the clock mode is subclock mode or sub-CR
clock mode.
After the device transits to watch mode, if the pin state setting bit in the standby control
register (STBC:SPL) is "0", the states of the external pins are kept; if the SPL bit is "1", the
states of the external pins become high impedance (a pin is pulled up if the pull-up resistor
connection for that pin is selected in the pull-up register).
● Release from watch mode
The device is released from watch mode by a reset, a watch interrupt, or an external interrupt.
Note:
If the device is released from watch mode by an interrupt, a peripheral function having
transited to watch mode during operation resumes operating from the point at which it
transited to watch mode. Therefore, some settings of that peripheral function, such as the
initial interval time of the interval timer, become undefined. Initialize that peripheral
function if necessary after releasing the device from watch mode.
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CHAPTER 6 CLOCK CONTROLLER
6.10 Clock Oscillator Circuit
6.10
MB95410H/470H Series
Clock Oscillator Circuit
The clock oscillator circuit generates an internal clock with an oscillator
connected to the clock oscillation pin or by inputting a clock signal to the clock
oscillation pin.
■ Clock Oscillator Circuit
● Using crystal oscillators and ceramic oscillators
Connect crystal oscillators or ceramic oscillators as shown in Figure 6.10-1.
Figure 6.10-1 Sample Connection of Crystal Oscillators and Ceramic Oscillators
Connecting to two external clocks
Main clock
oscillator circuit
X0
X1
C
C
Subclock
oscillator circuit
X0A
X1A
C
C
● Using external clock
As shown in Figure 6.10-2, connect the external clock to the X0 pin while leaving the X1 pin
unconnected or supplying inverted clock of the X0 pin to the X1 pin. (Refer to the data sheet of
the MB95410H/470H Series.) To supply clock signals to the subclock from an external clock,
connect that external clock to the X0A pin while leaving the X1A pin unconnected.
Figure 6.10-2 Sample Connection of External Clocks
X1 open
Main clock
oscillator circuit
X0
Subclock
oscillator circuit
X1
X0A
Open
96
Inverted X0 input to X1
X1A
Main clock
oscillator circuit
X0
X1
Open
FUJITSU SEMICONDUCTOR LIMITED
Subclock
oscillator circuit
X0A
X1A
Open
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MB95410H/470H Series
6.11
Overview of Prescaler
CHAPTER 6 CLOCK CONTROLLER
6.11 Overview of Prescaler
The prescaler generates the count clock source to be supplied to various
peripheral functions from the machine clock (MCLK) and the count clock
output from the time-base timer.
■ Prescaler
The prescaler generates the count clock source to be supplied to various peripheral functions
from the machine clock (MCLK) with which the CPU operates and from the count clock
(FCH*/27, FCH*/28, FCRH/26 or FCRH/27) output from the time-base timer. The count clock
source is a clock whose frequency is divided by the prescaler or a buffered clock. The
peripheral functions listed below use the clock whose frequency is divided by the prescaler as
the count clock source.
The prescaler has no control register and always operates with the machine clock (MCLK) and
the count clock (FCH*/27, FCH*/28, FCRH/26 or FCRH/27) of the time-base timer.
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
• 8/16-bit composite timer
• 8/10-bit A/D converter
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CHAPTER 6 CLOCK CONTROLLER
6.12 Configuration of Prescaler
6.12
MB95410H/470H Series
Configuration of Prescaler
Figure 6.12-1 is the block diagram of the prescaler.
■ Block Diagram of Prescaler
Figure 6.12-1 Block Diagram of Prescaler
Prescaler
MCLK/2
MCLK/4
Counter value
MCLK (machine clock)
From
time-base
timer
FCH*/27
MCLK/8
5-bit
counter
Output
control circuit
MCLK/16
MCLK/32
FCRH/26
FCH*/27 or FCRH/26
FCH*/28 or FCRH/27
or
FCH*/28
FCRH/27
Count
clock
source
to
different
peripheral
functions
MCLK : Machine clock (internal operating frequency)
FCH
: Main clock
: Main CR clock
FCRH
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
• 5-bit counter
This counter counts the machine clock (MCLK) and outputs the count value to the output
control circuit.
• Output control circuit
Based on the 5-bit counter value, this circuit supplies clocks generated by dividing the
machine clock (MCLK) by 2, 4, 8, 16, or 32 to individual peripheral functions. The circuit
also buffers the clock from the time-base timer (FCH*/27, FCH*/28, FCRH/26 or FCRH/27)
and supplies it to peripheral functions.
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
■ Input Clock
The prescaler uses the machine clock, or the output clock of the time-base timer as the input
clock.
■ Output Clock
The prescaler supplies clocks to the 8/16-bit composite timer and the 8/10-bit A/D converter.
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CHAPTER 6 CLOCK CONTROLLER
6.13 Operation of Prescaler
MB95410H/470H Series
6.13
Operation of Prescaler
The prescaler generates count clock sources to different peripheral functions.
■ Operation of Prescaler
The prescaler generates count clock sources from a clock whose frequency is generated by
dividing the machine clock (MCLK) and from buffered signals from the time-base timer
(FCH*/27, FCH*/28, FCRH/26 or FCRH/27), and supplies them to different peripheral functions.
The prescaler keeps operating while the machine clock and the clocks from the time-base timer
are being supplied.
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
Table 6.13-1 and Table 6.13-2 list the count clock sources generated by the prescaler.
Table 6.13-1 Count Clock Sources Generated by Prescaler (FCH)
Count clock
source frequency
MCLK/2
Frequency
(FCH = 20 MHz,
MCLK = 10 MHz)
5 MHz
Frequency
(FCH = 32 MHz,
MCLK = 16 MHz)
Frequency
(FCH = 32.5 MHz,
MCLK = 16.25 MHz)
8 MHz
8.125 MHz
MCLK/4
2.5 MHz
4 MHz
4.0625 MHz
MCLK/8
1.25 MHz
2 MHz
2.0313 MHz
MCLK/16
0.625 MHz
1 MHz
1.0156 MHz
MCLK/32
0.3125 MHz
0.5 MHz
0.5078 MHz
FCH/27
156.25 kHz
250 kHz
253.9 kHz
FCH/28
78.125 kHz
125 kHz
126.95 kHz
Table 6.13-2 Count Clock Sources Generated by Prescaler (FCRH)
Count clock
source frequency
MCLK/2
Frequency
(FCRH = 1 MHz,
MCLK = 1 MHz)
500 kHz
Frequency
(FCRH = 8 MHz,
MCLK = 8 MHz)
4 MHz
Frequency
(FCRH = 10 MHz,
MCLK = 10 MHz)
5 MHz
Frequency
(FCRH = 12.5 MHz,
MCLK = 12.5 MHz)
6.25 MHz
MCLK/4
250 kHz
2 MHz
2.5 MHz
3.125 MHz
MCLK/8
125 kHz
1 MHz
1.25 MHz
1.5625 MHz
MCLK/16
62.5 kHz
0.5 MHz
0.625 MHz
0.78125 MHz
MCLK/32
31.25 kHz
0.25 MHz
0.3125 MHz
0.390625 MHz
FCRH/26
15.625 kHz
125 kHz
156.25 kHz
195.3125 kHz
FCRH/27
7.8125 kHz
62.5 kHz
78.125 kHz
97.65625 kHz
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CHAPTER 6 CLOCK CONTROLLER
6.14 Notes on Using Prescaler
6.14
MB95410H/470H Series
Notes on Using Prescaler
This section provides notes on using the prescaler.
The prescaler operates with the machine clock and the clock generated from the time-base
timer, and keeps operating while those clocks are being supplied. Therefore, in the operation
immediately after a peripheral resource is started, an error of up to one cycle of the clock
source captured by that peripheral resource will occur, depending on the output value of the
prescaler.
Figure 6.14-1 Clock Capture Error Occurring Immediately after a Peripheral Function Starts
Prescaler output
Start of peripheral function
Clock captured by peripheral function
Clock capture error
immediately after
a peripheral function starts
The prescaler count value affects the following peripheral functions:
• 8/16-bit composite timer
• 8/10-bit A/D converter
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CHAPTER 7
RESET
This chapter describes the reset operation.
MN702-00005-2v0-E
7.1
Reset Operation
7.2
Reset Source Register (RSRR)
7.3
Notes on Using Reset
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CHAPTER 7 RESET
7.1 Reset Operation
7.1
MB95410H/470H Series
Reset Operation
When a reset source occurs, the CPU immediately stops the process being
executed and enters the reset release wait state. When the reset is released,
the CPU reads mode data and the reset vector from the internal ROM (mode
fetch). When the power is switched on or when the device is released from a
reset in subclock mode, sub-CR clock mode, or stop mode, the CPU performs
mode fetch after the oscillation stabilization wait time has elapsed.
■ Reset Sources
There are five reset sources for the reset.
Table 7.1-1
Reset Sources
Reset source
Reset condition
External reset
"L" level is input to the external reset pin.
Software reset
"1" is written to the software reset bit in the standby control register
(STBC:SRST).
Watchdog reset
The watchdog timer overflows.
Power-on reset
The power is switched on.
Low-voltage detection reset (optional)
The supply voltage falls below the detection voltage.
● External reset
An external reset is generated if "L" level is input to the external reset pin (RST).
An external input reset signal is received asynchronously with the operating clock of the
microcontroller via the internal noise filter and then generates an internal reset signal that is
synchronized with the machine clock to initialize the internal circuit. Therefore, the operating
clock of the microcontroller is necessary for initializing the internal circuit. In order to operate
with the external clock, external clock signals must be input. However, the external pins
(including I/O ports and peripheral functions) are reset asynchronously. In addition, there is a
standard value of the pulse width for external reset input. If the value is below the standard
value, a reset signal may not be accepted.
The standard value is shown in the data sheet of this series. Design an external reset circuit that
satisfies the standard value.
● Software reset
Writing "1" to the software reset bit of the standby control register (STBC:SRST) generates a
software reset.
● Watchdog reset
After the watchdog timer starts, a watchdog reset is generated if the watchdog timer is not
cleared within a predetermined period of time.
● Power-on reset
A power-on reset is generated when the power is switched on.
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CHAPTER 7 RESET
7.1 Reset Operation
● Low-voltage detection reset (optional)
The low-voltage detection reset circuit is only available on MB95F414K/F416K/F418K/
F474K/F476K/F478K.
The low-voltage detection reset circuit generates a reset if the power supply voltage falls below
a predetermined level.
The logical function of the low-voltage detection reset is equivalent to that of the power-on
reset. All information relating to the power-on reset of this hardware manual also applies to the
low-voltage detection reset.
For details of the low-voltage detection reset, see "CHAPTER 26 LOW-VOLTAGE
DETECTION RESET CIRCUIT".
■ Reset Time
In the case of a software reset or a watchdog reset, the reset time consists of three machine
clock cycles: one machine clock cycle at the machine clock frequency selected before the reset,
and two machine clock cycles at the initial machine clock frequency after the reset (1/32 of the
main clock frequency). However, the reset time may be extended by the RAM access
protection function, which suppresses resets during RAM access, by the machine clock cycle
of the frequency selected before the reset. In addition, when in main clock oscillation
stabilization standby mode, the reset time is further extended for the oscillation stabilization
wait time. Both the external reset and the reset are affected by the RAM access protection
function and the main clock oscillation stabilization wait time.
In the case of a power-on reset and a low-voltage detection reset, the reset state continues
during the oscillation stabilization wait time.
■ Reset Output
The reset pin outputs "L" level during a reset provided that the reset input function is enabled.
However, during an external reset, the reset pin cannot output "L" level. For details of the
settings of the reset input function and reset output function, see "CHAPTER 34 SYSTEM
CONFIGURATION CONTROLLER".
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CHAPTER 7 RESET
7.1 Reset Operation
MB95410H/470H Series
■ Overview of Reset Operation
Figure 7.1-1 Reset Operation Flow
Supress resets
during RAM access
Suppress resets
during RAM access
During reset
Power-on reset/
low-voltage delection
reset
External reset input
Software reset
Watchdog reset
Sub-CR clock is ready?
YES
Sub-CR clock is ready?
YES
NO
NO
Sub-CR clock
oscillation stabilization
wait time reset state
Sub-CR clock
oscillation stabilization
wait time reset state
Released from
external reset?
Sub-CR clock
oscillation stabilization
wait time reset state
NO
YES
Main CR clock oscillation
stabilization wait time
Mode fetch
Capture mode data
Capture reset vector
Capture instruction code from the
address indicated by the reset
vector and execute the instruction.
Normal operation
(Run state)
In any reset, the CPU performs mode fetch after the main CR clock oscillation stabilization
wait time elapses.
■ Effect of Reset on RAM Contents
When a reset occurs, the CPU halts the operation of the command currently being executed,
and enters the reset state. However, during RAM access execution, in order to protect the RAM
access, an internal reset signal synchronized with the machine clock is generated after an RAM
access ends. This function prevents a word-data write operation from being interrupted by a
reset while data of two bytes is being written.
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CHAPTER 7 RESET
7.1 Reset Operation
■ Pin State During a Reset
When a reset occurs, an I/O port or a peripheral resource pin remains high impedance until the
setting of that I/O port or that peripheral resource pin by software is executed after the reset is
released.
Note:
Connect a pull-up resistor to a pin that becomes high impedance during a reset to prevent
the device from malfunctioning.
For details of the states of all pins during a reset, see "APPENDIX D Pin States of MB95410H/
470H Series".
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CHAPTER 7 RESET
7.2 Reset Source Register (RSRR)
MB95410H/470H Series
Reset Source Register (RSRR)
7.2
The reset source register (RSRR) indicates the source of a reset generated.
■ Configuration of Reset Source Register (RSRR)
Figure 7.2-1 Configuration of Reset Source Register (RSRR)
Address
0009H
bit7
bit6
-
-
bit5
-
R0/WX R0/WX R0/WX
bit4
EXTS
R,W
SWR
0
1
HWR
0
1
PONR
0
1
WDTR
0
1
EXTS
0
1
bit3
bit2
bit1
WDTR PONR
R,W
R,W
HWR
R,W
bit0
Initial value
SWR
R,W
000XXXXXB
Software reset flag bit
Write
Read
A write access to this bit
sets it to “0”.
Source is software reset
Hardware reset flag bit
Write
Read
A write access to this bit
sets it to “0”.
Source is hardware reset
Power-on reset flag bit
Write
Read
A write access to this bit
sets it to “0”.
Source is power-on reset
Watchdog reset flag bit
Write
Read
A write access to this bit
sets it to “0”.
Source is watchdog reset
External reset flag bit
Read
Source is external reset
Write
A write access to this bit
sets it to “0”.
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
R,W
R0/WX
X
106
:
:
:
:
Readable/writable (The read value is different from the write value.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Indeterminate
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
Table 7.2-1
CHAPTER 7 RESET
7.2 Reset Source Register (RSRR)
Functions of Bits in Reset Source Register (RSRR)
Bit name
Function
bit7
to
bit5
Undefined bits
bit4
EXTS:
External reset flag bit
bit3
When this bit is set to "1", that indicates a watchdog reset has occurred.
WDTR:
When any other reset occurs, this bit retains the value that has existed before such reset
Watchdog reset flag bit occurs.
• A read access or a write access (writing 0 or 1) to this bit clears it to "0".
bit2
When this bit is set to "1", that indicates a power-on reset or a low-voltage detection reset
(optional) has occurred.
When any other reset occurs, this bit retains the value that has existed before such reset
PONR:
occurs.
Power-on reset flag bit
• The low-voltage detection reset function is only available on MB95F414K/F416K/
F418K/F474K/F476K/F478K.
• A read access or a write access (writing 0 or 1) to this bit clears it to "0".
bit1
When this bit is set to "1", that indicates a hardware reset (power-on reset, low-voltage
detection reset (optional), external reset or watchdog reset) other than software reset has
occurred. Therefore, when any of bit 2 to bit 5 is set to "1", this bit is set to "1" as well.
HWR:
Hardware reset flag bit When a software reset occurs, the bit retains the value that has existed before the software
reset occurs.
• A read access or a write access (writing 0 or 1) to this bit clears it to "0".
bit0
Their read values are always "0". Writing values to these bits has no effect on operation.
SWR:
Software reset flag bit
When this bit is set to "1", that indicates an external reset has occurred.
When any other reset occurs, this bit retains the value that has existed before such reset
occurs.
• A read access or a write access (writing 0 or 1) to this bit clears it to "0".
When this bit is set to "1", that indicates a software reset has occurred.
When a hardware reset occurs, the bit retains the value that has existed before the hardware
reset occurs.
• A read access or a write access (writing 0 or 1) to this bit or a power-on reset clears it to
"0".
Note:
Since reading the reset source register clears its contents, save the contents of this
register to the RAM before using those contents for calculation.
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CHAPTER 7 RESET
7.2 Reset Source Register (RSRR)
MB95410H/470H Series
■ State of Reset Source Register (RSRR)
Table 7.2-2
State of Reset Source Register
Reset source
EXTS
WDTR
PONR
HWR
SWR
Power-on reset
×
×
1
1
0
Low-voltage detection reset (optional)
×
×
1
1
0
Software reset
1
1
Watchdog reset
External reset
1:
1
1
1
Flag set
:
×:
Previous state kept
Indeterminate
EXTS: When this bit is set to "1", that indicates an external reset has occurred.
WDTR: When this bit is set to "1", that indicates a watchdog reset has occurred.
PONR: When this bit is set to "1", that indicates a power-on reset or low-voltage detection reset (optional) has
occurred.
HWR:
When this bit is set to "1", that indicates one of the following reset has occurred: an external reset, a
watchdog reset, a power-on reset or a low-voltage detection reset (optional).
SWR:
When this bit is set to "1", that indicates that a software reset has occurred.
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7.3
Notes on Using Reset
CHAPTER 7 RESET
7.3 Notes on Using Reset
This section provides notes on using the reset.
■ Notes on Using Reset
● Initialization of registers and bits by reset source
There are registers and bits that are not initialized by a reset source.
• The type of reset source determines which bit in the reset source register (RSRR) is to be
initialized.
• The oscillation stabilization wait time setting register (WATR) of the clock controller is
initialized only by a power-on reset.
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CHAPTER 7 RESET
7.3 Notes on Using Reset
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CHAPTER 8
INTERRUPTS
This chapter describes the interrupts.
8.1
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Interrupts
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
8.1
MB95410H/470H Series
Interrupts
This section describes the interrupts.
■ Overview of Interrupts
The New 8FX family has 24 interrupt request inputs for respective peripheral functions, for
each of which an interrupt level can be set independently to each other.
When a peripheral resource generates an interrupt request, the interrupt request is output to the
interrupt controller. The interrupt controller checks the interrupt level of that interrupt request
and then notifies the CPU of the generation of the interrupt. The CPU processes that interrupt
according to the interrupt acceptance status. The device is released from standby mode by an
interrupt request and resumes executing instructions.
■ Interrupt Requests from Peripheral Functions
Table 8.1-1 lists the interrupt requests of respective peripheral functions. When the CPU
receives an interrupt request, it branches to the interrupt service routine with the interrupt
vector table address corresponding to the interrupt request as the address of the branch
destination.
The priority of each interrupt request in interrupt processing can be set to one of the four levels
by the interrupt level setting registers (ILR0 to ILR5).
While an interrupt is being processed in the interrupt service routine, if another interrupt whose
interrupt request is of the same level or below the one of the interrupt being processed is
generated, it is processed after the current interrupt service routine is completed. In addition, if
multiple interrupt requests that are set to the same interrupt level are made, IRQ00 is at the top
of the priority order.
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
Table 8.1-1
Interrupt Requests and Interrupt Vectors
Vector table address
Upper
Lower
Bit name in interrupt level
setting register
IRQ00
FFFAH
FFFBH
L00[1:0]
IRQ01
FFF8H
FFF9H
L01[1:0]
IRQ02
FFF6H
FFF7H
L02[1:0]
IRQ03
FFF4H
FFF5H
L03[1:0]
IRQ04
FFF2H
FFF3H
L04[1:0]
IRQ05
FFF0H
FFF1H
L05[1:0]
IRQ06
FFEEH
FFEFH
L06[1:0]
IRQ07
FFECH
FFEDH
L07[1:0]
IRQ08
FFEAH
FFEBH
L08[1:0]
IRQ09
FFE8H
FFE9H
L09[1:0]
IRQ10
FFE6H
FFE7H
L10[1:0]
IRQ11
FFE4H
FFE5H
L11[1:0]
IRQ12
FFE2H
FFE3H
L12[1:0]
IRQ13
FFE0H
FFE1H
L13[1:0]
IRQ14
FFDEH
FFDFH
L14[1:0]
IRQ15
FFDCH
FFDDH
L15[1:0]
IRQ16
FFDAH
FFDBH
L16[1:0]
IRQ17
FFD8H
FFD9H
L17[1:0]
IRQ18
FFD6H
FFD7H
L18[1:0]
IRQ19
FFD4H
FFD5H
L19[1:0]
IRQ20
FFD2H
FFD3H
L20[1:0]
IRQ21
FFD0H
FFD1H
L21[1:0]
IRQ22
FFCEH
FFCFH
L22[1:0]
IRQ23
FFCCH
FFCDH
L23[1:0]
Interrupt request
Priority order of interrupt requests
of the same level (generated
simultaneously)
Highest
Lowest
For interrupt sources, see "APPENDIX B Table of Interrupt Sources".
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
Interrupt Level Setting Registers (ILR0 to ILR5)
8.1.1
The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of 2-bit data
assigned to the interrupt requests of different peripheral functions. Each pair
of bits (interrupt level setting bits) is used to set the interrupt level of an
interrupt request.
■ Configuration of Interrupt Level Setting Registers (ILR0 to ILR5)
Figure 8.1-1 Configuration of Interrupt Level Setting Registers
Register
ILR0
Address
00079H
bit7
bit6
L03[1:0]
bit5
bit4
L02[1:0]
bit3
bit2
L01[1:0]
bit1
bit0
L00[1:0]
Initial value
R/W 11111111B
ILR1
0007AH
L07[1:0]
L06[1:0]
L05[1:0]
L04[1:0]
R/W 11111111B
ILR2
0007BH
L11[1:0]
L10[1:0]
L09[1:0]
L08[1:0]
R/W 11111111B
ILR3
0007CH
L15[1:0]
L14[1:0]
L13[1:0]
L12[1:0]
R/W 11111111B
ILR4
0007DH
L19[1:0]
L18[1:0]
L17[1:0]
L16[1:0]
R/W 11111111B
ILR5
0007EH
L23[1:0]
L22[1:0]
L21[1:0]
L20[1:0]
R/W 11111111B
The interrupt level setting registers assign a pair of bits to every interrupt request. The values
of interrupt level setting bits in these registers represent the priority of an interrupt request
(interrupt level: 0 to 3) in interrupt processing.
The interrupt level setting bits are compared with the interrupt level bits in the condition code
register (CCR:IL1, IL0).
If the interrupt level of an interrupt request is 3, the CPU ignores that interrupt request.
Table 8.1-2 shows the relationships between interrupt level setting bits and interrupt levels.
Table 8.1-2
Relationships Between Interrupt Level Setting Bits and Interrupt Levels
LXX[1:0]
Interrupt level
Priority
00
0
Highest
01
1
10
2
11
3
Lowest (No interrupt)
XX:00 to 23 Number of an interrupt request
While the main program is being executed, the interrupt level bits in the condition code register
(CCR:IL1, IL0) are "11B".
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
8.1.2
Interrupt Processing
When an interrupt request is made by a peripheral resource, the interrupt
controller notifies the CPU of the interrupt level of that interrupt request. When
the CPU is ready to accept interrupts, it halts the program it is executing and
executes an interrupt service routine.
■ Interrupt Processing
The procedure for processing an interrupt is as follows: the generation of an interrupt source in a
peripheral resource, the execution of the main program, the setting of the interrupt request flag bit,
the evaluation of the interrupt request enable bit, the evaluation of the interrupt level (ILR0 to
ILR5 and CCR:IL1, IL0), the checking for interrupt requests of the same interrupt level made
simultaneously, and the evaluation of the interrupt enable flag (CCR:I).
Figure 8.1-2 shows the interrupt processing.
Internal data bus
Figure 8.1-2 Interrupt Processing
START
Condition code register (CCR)
I
IL
Check
CPU
(7)
Comparator
(5)
Release from stop
mode
Release from sleep
mode
Release from timebase
timer/watch mode
RAM
Initialize peripheral resources
Interrupt
from peripheral
resource?
NO
(6)
Interrupt request
flag
Interrupt request
enabled
YES
(3)
Peripheral
resource interrupt request
output enabled?
NO
(3)
AND
Each peripheral resource
Level comparator
(1)
(4)
Interrupt
controller
YES
Determine interrupt priority and
(4) transfer interrupt level to CPU
(5)
Compare interrupt level
with IL bit in PS
Interrupt level higher
than IL value?
YES
NO
(2)
YES
I flag = 1?
Run main program
NO
Interrupt service routine
Clear interrupt request
Save PC and PS to stack
(7) Restore PC and PS
Execute interrupt processing
(6)
PC ← interrupt vector
RETI
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Update IL in PS
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
(1) All interrupt requests are disabled immediately after a reset. In the peripheral resource
initialization program, initialize those peripheral functions that generate interrupts and set
their interrupt levels in their respective interrupt level setting registers (ILR0 to ILR5)
before starting operating such peripheral functions. The interrupt level can be set to 0, 1, 2,
or 3. Level 0 is given the highest priority, and level 1 the second highest. Assigning level 3
to a peripheral resource disables interrupts from that peripheral resource.
(2) Execute the main program (or the interrupt service routine in the case of nested interrupts).
(3) When an interrupt source is generated in a peripheral resource, the interrupt request flag bit
for that peripheral resource is set to "1". Provided that the interrupt request enable bit for
that peripheral resource has been set to the value that enables interrupts, an interrupt request
of that peripheral resource is output to the interrupt controller.
(4) The interrupt controller keeps monitoring interrupt requests from individual peripheral
functions and notifies the CPU of the interrupt level having priority over the others among
interrupt levels already made. If there are interrupt requests having the same interrupt level,
their positions in the priority order are also compared in the interrupt controller.
(5) If the interrupt level received has priority over (smaller interrupt level number) the level set
in the interrupt level bits (CCR:IL1, IL0) in the condition code register, the CPU checks the
content of the interrupt enable flag (CCR:I), and accepts the interrupt provided that
interrupts have been enabled (CCR:I = 1).
(6) The CPU saves the contents of the program counter (PC) and the program status (PS) to the
stack, captures the start address of the interrupt service routine from the corresponding
interrupt vector table address, modifies the values of the interrupt level bits in the condition
code register (CCR:IL1, IL0) to the values of the interrupt level received, then starts
executing the interrupt service routine.
(7) Finally, the CPU uses the RETI instruction to restore the values of the program counter
(PC) and the program status (PS) from the stack and resumes executing the instruction
following the one executed just before the interrupt.
Note:
The interrupt request flag bit for a peripheral resource is not automatically cleared to "0"
after an interrupt request is accepted. Therefore, such bit must be cleared to "0" by using
a program (writing "0" to the interrupt request flag bit) in the interrupt service routine.
The low-power consumption (standby mode) is released by an interrupt. For details, see "6.9
Operations in Low-power Consumption Mode (Standby Mode)".
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
8.1.3
Nested Interrupts
Different interrupt levels can be assigned to multiple interrupt requests from
peripheral functions in the interrupt level setting registers (ILR0 to ILR5) to
process nested interrupts.
■ Nested Interrupts
During the execution of an interrupt service routine, if another interrupt request whose interrupt
level has priority over the interrupt level of the interrupt being processed is made, the CPU
suspends the current interrupt processing and accepts the interrupt request given priority. The
interrupt level of an interrupt request can be set to 0 to 3. If it is set to 3, the CPU does not
accept that interrupt request.
[Example: Nested interrupts]
In the following example of nested interrupts, assuming that the external interrupt is to be
given priority over the timer interrupt, the interrupt level of the timer interrupt is set to 2 and
that of the external interrupt to 1. If the external interrupt is generated while the timer interrupt
is being processed, they are processed as shown in Figure 8.1-3.
Figure 8.1-3 Example of Nested Interrupts
Main Program
Timer Interrupt Processing
Interrupt level 2
(CCR:IL1,IL0=10B)
External Interrupt Processing
Interrupt level 1
(CCR:IL1,IL0=01B)
Initialize peripheral resources (1)
Timer interrupt occurs (2)
(3) External interrupt
occurs
(4) Process external interrupt
Suspend
Resume
Resume main program
(8)
(6) Process timer interrupt
(5) Return from external interrupt
(7) Return from timer interrupt
• While the timer interrupt is being processed, the interrupt level bits in the condition code
register (CCR: IL1, IL0) hold the same value as that of the interrupt level setting registers
(ILR0 to ILR5) corresponding to the timer interrupt (level 2 in this example). If an interrupt
request whose interrupt level has priority over the interrupt level of the timer interrupt (level
1 in the example) is made, that interrupt is processed first.
• To temporarily disable nested interrupts processing while the timer interrupt is being
processed, disable interrupts by setting the interrupt enable flag in the condition code
register (CCR:I) to "0", or set the interrupt level bits (CCR:IL1, IL0) to "00B".
• After the interrupt processing is completed, if the interrupt return instruction (RETI) is
executed, the value of the program counter (PC) and that of the program status (PS) are
restored, and the CPU resumes executing the program interrupted. In addition, the values of
the condition code register (CCR) return to the ones existing before the interrupt due to the
restoration of the value of the program status (PS).
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
8.1.4
MB95410H/470H Series
Interrupt Processing Time
Before the CPU enters the interrupt service routine after an interrupt request is
made, it needs to wait for the interrupt processing time, which consists of the
time between the occurrence of an interrupt request and the end of the
execution of the instruction being executed, and the interrupt handling time
(the time required to initiate interrupt processing) to elapse. The maximum
interrupt processing time is 26 machine clock cycles.
■ Interrupt Processing Time
Before executing the interrupt service routine after an interrupt request is made, the CPU needs
to wait for the interrupt request sampling wait time and the interrupt handling time to elapse.
● Interrupt request sampling wait time
The CPU decides whether an interrupt request has occurred by sampling the interrupt request
during the last cycle of an instruction. Therefore, the CPU cannot recognize interrupt requests
while executing an instruction. This sampling wait time reaches its maximum when an
interrupt request occurs immediately after the CPU starts executing the DIVU instruction,
whose execution cycle is the longest (17 machine clock cycles).
● Interrupt handling time
After accepting an interrupt, the CPU requires nine machine clock cycles to perform the
following interrupt processing setup:
• Saves the value of the program counter (PC) and that of the program status (PS) to the
stack.
• Sets the PC to the start address (interrupt vector) of interrupt service routine.
• Updates the interrupt level bits (PS:CCR:IL1, IL0) in the program status (PS).
Figure 8.1-4 Interrupt Processing Time
Normal instruction execution
Interrupt handling
Interrupt service routine
CPU operation
Interrupt wait time
Interrupt request
sampling wait time
Interrupt handling time
(9 machine clock cycles)
Interrupt request generated
: Last instruction cycle in which the interrupt request is sampled
When an interrupt request occurs immediately after the CPU starts executing the DIVU
instruction, whose execution cycle is the longest (17 machine clock cycles), the interrupt
processing time spans 26 machine clock cycles.
The span of a machine clock cycle varies depending on the clock mode and main clock speed
change (gear function). For details, see "CHAPTER 6 CLOCK CONTROLLER".
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
MB95410H/470H Series
8.1.5
Stack Operation During Interrupt Processing
This section describes how the contents of a register are saved and restored
during interrupt processing.
■ Stack Operation at the Start of Interrupt Processing
Once the CPU accepts an interrupt, it automatically saves the current value of the program
counter (PC) and that of the program status (PS) values to the stack.
Figure 8.1-5 shows the stack operation at the start of interrupt processing.
Figure 8.1-5 Stack Operation at Start of Interrupt Processing
Immediately before interrupt
Immediately after interrupt
Address Memory
PS 0870H
PC E000H
SP
0280H
027CH
027DH
027EH
027FH
0280H
0281H
XXH
XXH
XXH
XXH
XXH
XXH
Address Memory
SP 027CH
PS
0870H
PC E000H
027CH
027DH
027EH
027FH
0280H
0281H
08H
70H
E0H
00H
XXH
XXH
}
}
PS
PC
■ Stack Operation after Returning from Interrupt
When the CPU executes the interrupt return instruction (RETI) at the end of interrupt
processing, it restores from the stack the value of the program status (PS) first and that of the
program counter (PC), which is opposite to the sequence of saving the two values to the stack.
After the restoration, both PS and PC return to their states prior to the start of interrupt
processing.
Note:
Since the value of the accumulator (A) and that of the temporary accumulator (T) are not
automatically saved to the stack, use the PUSHW and POPW instructions to save and
restore the values of A and T.
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CHAPTER 8 INTERRUPTS
8.1 Interrupts
8.1.6
MB95410H/470H Series
Interrupt Processing Stack Area
The stack area in RAM is used for interrupt processing. The stack pointer (SP)
contains the start address of the stack area.
■ Interrupt Processing Stack Area
The stack area is also used for saving and restoring the program counter (PC) when the
subroutine call instruction (CALL) or the vector call instruction (CALLV) is executed, and for
saving temporarily and restoring register contents by the PUSHW and POPW instructions.
• The stack area is secured on the RAM together with the data area.
• Initialize the stack pointer (SP) so that it indicates the biggest RAM address and make the
data area start from the smallest RAM address.
Figure 8.1-6 shows an example of setting the interrupt processing stack area.
Figure 8.1-6 Example of Setting Interrupt Processing Stack Area
0000H
I/O
0080H
Data area
RAM
0100H
Stack area
Generalpurpose
register
0200H
Recommended SP value
(when the biggest RAM address is 027FH)
Product in this example: MB95F414H)
0280H
Access
prohibited
ROM
FFFFH
Note:
The stack area is utilized by interrupts, sub-routine calls, the PUSHW instruction, etc. in
descending of addresses. It is released by return instructions (RETI, RET), the POPW
instruction, etc. in ascending order of addresses. If the address value of the stack area
used decreases due to nested interrupts or subroutine calls, do not let the stack area
overlap the data area and the general-register area, both of which retain other data.
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CHAPTER 9
I/O PORTS
(MB95410H SERIES)
This chapter describes the functions and
operations of the I/O ports.
9.1
Overview of I/O Ports
9.2
Port 0
9.3
Port 1
9.4
Port 2
9.5
Port 4
9.6
Port 5
9.7
Port 6
9.8
Port 9
9.9
Port A
9.10 Port B
9.11 Port C
9.12 Port E
9.13 Port F
9.14 Port G
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.1 Overview of I/O Ports
9.1
MB95410H/470H Series
Overview of I/O Ports
I/O ports are used to control general-purpose I/O pins.
■ Overview of I/O Ports
The I/O port has functions to output data from the CPU and capture input signals into the CPU
with the port data register (PDR). The I/O direction of an individual I/O pin can be set as
desired by using the corresponding to that I/O pin in the port direction register (DDR).
Table 9.1-1 lists the registers for each pin.
Table 9.1-1
List of Port Registers (1 / 2)
Register name
Read/Write
Initial value
Port 0 data register
PDR0
R, RM/W
00000000B
Port 0 direction register
DDR0
R/W
00000000B
Port 1 data register
PDR1
R, RM/W
00000000B
Port 1 direction register
DDR1
R/W
00000000B
Port 2 data register
PDR2
R, RM/W
00000000B
Port 2 direction register
DDR2
R/W
00000000B
Port 4 data register
PDR4
R, RM/W
00000000B
Port 4 direction register
DDR4
R/W
00000000B
Port 5 data register
PDR5
R, RM/W
00000000B
Port 5 direction register
DDR5
R/W
00000000B
Port 6 data register
PDR6
R, RM/W
00000000B
Port 6 direction register
DDR6
R/W
00000000B
Port 9 data register
PDR9
R, RM/W
00000000B
Port 9 direction register
DDR9
R/W
00000000B
Port A data register
PDRA
R, RM/W
00000000B
Port A direction register
DDRA
R/W
00000000B
Port B data register
PDRB
R, RM/W
00000000B
Port B direction register
DDRB
R/W
00000000B
Port C data register
PDRC
R, RM/W
00000000B
Port C direction register
DDRC
R/W
00000000B
Port E data register
PDRE
R, RM/W
00000000B
Port E direction register
DDRE
R/W
00000000B
Port F data register
PDRF
R, RM/W
00000000B
Port F direction register
DDRF
R/W
00000000B
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Table 9.1-1
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.1 Overview of I/O Ports
List of Port Registers (2 / 2)
Register name
Read/Write
Initial value
Port G data register
PDRG
R, RM/W
00000000B
Port G direction register
DDRG
R/W
00000000B
Port 1 pull-up register
PUL1
R/W
00000000B
Port 2 pull-up register
PUL2
R/W
00000000B
Port 5 pull-up register
PUL5
R/W
00000000B
Port G pull-up register
PULG
R/W
00000000B
A/D input disable register (lower)
AIDRL
R/W
00000000B
ILSR
R/W
00000000B
Input level select register
R/W
: Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is
read by the read-modify-write (RMW) type of instruction.)
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
9.2
MB95410H/470H Series
Port 0
Port 0 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 0 Configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• A/D input disable register lower (AIDRL)
• Input level select register (ILSR)
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
MB95410H/470H Series
■ Port 0 Pins
Port 0 has eight I/O pins.
Table 9.2-1 lists the port 0 pins.
Table 9.2-1
Port 0 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
INT00: External interrupt input
P00/INT00/
P00: General-purpose I/O AN00:Analog input
AN00/UO2
UO2: UART/SIO ch. 2 data output
Output OD PU
Hysteresis/ CMOS/
analog
LCD
-
-
INT01: External interrupt input
P01/INT01/
AN01: Analog input
AN01/SEG36/ P01: General-purpose I/O
SEG36: LCDC SEG36 output
UI2
UI2: UART/SIO ch. 2 data input
Hysteresis/
CMOS/
CMOS/
LCD
analog
-
-
INT02: External interrupt input
P02/INT02/
AN02: Analog input
AN02/SEG35/ P02: General-purpose I/O
SEG35: LCDC SEG35 output
UCK2
UCK2: UART/SIO ch. 2 clock I/O
Hysteresis/ CMOS/
analog
LCD
-
-
INT03: External interrupt input
P03/INT03/
AN03: Analog input
AN03/SEG34/ P03: General-purpose I/O
SEG34: LCDC SEG34 output
UO1
UO1: UART/SIO ch. 1 data output
Hysteresis/ CMOS/
analog
LCD
-
-
INT04: External interrupt input
P04/INT04/
AN04: Analog input
AN04/SEG33/ P04: General-purpose I/O
SEG33: LCDC SEG33 output
UI1
UI1: UART/SIO ch. 1 data input
Hysteresis/
CMOS/
CMOS/
LCD
analog
-
-
INT05: External interrupt input
P05/INT05/
AN05: Analog input
AN05/SEG32/ P05: General-purpose I/O
SEG32: LCDC SEG32 output
UCK1
UCK1: UART/SIO ch. 1 clock I/O
Hysteresis/ CMOS/
analog
LCD
-
-
INT06: External interrupt input
P06/INT06/
P06: General-purpose I/O AN06: Analog input
AN06/SEG31
SEG31: LCDC SEG31 output
Hysteresis/ CMOS/
analog
LCD
-
-
INT07: External interrupt input
P07/INT07/
P07: General-purpose I/O AN07: Analog input
AN07/SEG30
SEG30: LCDC SEG30 output
Hysteresis/ CMOS/
analog
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
MB95410H/470H Series
■ Block Diagrams of Port 0
Figure 9.2-1 Block Diagram of P01 and P04
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
CMOS
Peripheral function output
0
1
PDR read
1
Hysteresis
pin
PDR
0
PDR write
Executing bit manipulation instruction
Only for INT01
and INT04
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
ILSR read
ILSR
ILSR write
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9.2 Port 0
MB95410H/470H Series
Figure 9.2-2 Block Diagram of P00, P02, P03, P05, P06 and P07
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
PDR
0
PDR write
Internal bus
Executing bit manipulation instruction
Only for INT00,
INT02, INT03,
INT05 to INT07
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
9.2.1
MB95410H/470H Series
Port 0 Registers
This section describes the registers of port 0.
■ Port 0 Register Functions
Table 9.2-2 lists the functions of the port 0 register.
Table 9.2-2
Port 0 Register Functions
Register
Data
abbr.
PDR0
DDR0
AIDRL
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
0
Analog input enabled
1
Port input enabled
0
Hysteresis input level selected
1
CMOS input level selected
Table 9.2-3 lists the correspondence between port 0 pins and each register bit.
Table 9.2-3
Correspondence between Registers and Pins for Port 0
Correspondence between related register bits and pins
Pin name
P07
P06
P05
P04
P03
P02
P01
P00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
bit4
-
-
bit1
-
PDR0
DDR0
AIDRL
ILSR
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9.2.2
Operations of Port 0
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
This section describes the operations of port 0.
■ Operations of Port 0
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR register value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 6 (LCDCE6:SEG31, SEG30) or in the LCDC enable
register 7 (LCDCE7:SEG36 to SEG32) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When using an analog input shared pin as an input port, set the corresponding bit in the A/D
input disable register lower (AIDRL) to "1".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 6 (LCDCE6:SEG31, SEG30) or in the LCDC enable
register 7 (LCDCE7:SEG36 to SEG32) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.2 Port 0
MB95410H/470H Series
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register bit corresponding to the input
pin of a peripheral function to "0".
• When using the analog input shared pin as another peripheral function input pin, configure
it as an input port, which is the same as the operation as an input port.
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 6 (LCDCE6:SEG31, SEG30) or in the LCDC enable register 7 (LCDCE7:SEG36 to
SEG32) to "1", and then set the port input control bit (PICTL) in the LCDC enable register
1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
As for a pin shared with analog input, its port input is disabled because the A/D input disable
register lower (AIDRL) is initialized to "0".
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open. However, if the interrupt input
is enabled for the external interrupt (INT07 to INT00), the input is enabled and not blocked.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation as an analog input pin
• Set the bit in the DDR register corresponding to the analog input pin to "0" and the bit
corresponding to that pin in the AIDRL register to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
● Operation as an external interrupt input pin
• Set the bit in the DDR register corresponding to the external interrupt input pin to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a
function other than the interrupt, disable the external interrupt function corresponding to
that pin.
● Operation of the input level select register
• Setting bit1 and bit4 in ILSR to "1" changes P01 and P04 respectively from the hysteresis
input level to the CMOS input level.
• For pins other than P01 and P04, the CMOS input level cannot be selected, but only the
hysteresis input level can be selected.
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9.2 Port 0
MB95410H/470H Series
• When changing the input level of P01 or of P04, ensure that all shared peripheral functions
have been stopped.
Table 9.2-4 shows the pin states of port 0.
Table 9.2-4
Operating
state
Pin state
Pin State of Port 0
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
Hi-Z
(the pull-up setting is enabled)
I/O port/
Input cutoff
peripheral function I/O
(If the external interrupt function is enabled,
the external interrupt can be input.)
At reset
Hi-Z
Input disabled*
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input disabled" means the state that the operation of the input gate adjacent to the pin is disabled.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.3 Port 1
9.3
MB95410H/470H Series
Port 1
Port 1 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 1 Configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
• Input level select register (ILSR)
■ Port 1 Pins
Port 1 has eight I/O pins.
Table 9.3-1 lists the port 1 pins.
Table 9.3-1
Port 1 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P10/UI0
P10: General-purpose I/O UI0: UART/SIO ch. 0 data input
Hysteresis/
CMOS
CMOS
-
❍
P11/UO0
P11: General-purpose I/O UO0: UART/SIO ch. 0 data output
Hysteresis CMOS
-
❍
P12/DBG
P12: General-purpose I/O
Hysteresis CMOS ❍
-
DBG: On-chip debug
communication pin
P13/ADTG
P13: General-purpose I/O ADTG: A/D trigger input
Hysteresis CMOS
-
❍
P14/UCK0
P14: General-purpose I/O UCK0: UART/SIO ch. 0 clock I/O
Hysteresis CMOS
-
❍
P15/PPG11 P15: General-purpose I/O PPG11: 8/16-bit PPG ch. 1 output
Hysteresis CMOS
-
-
P16/PPG10 P16: General-purpose I/O PPG10: 8/16-bit PPG ch. 1 output
Hysteresis CMOS
-
-
P17/CMPO P17: General-purpose I/O CMPO: Voltage comparator output
Hysteresis CMOS
-
❍
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.3 Port 1
■ Block Diagrams of Port 1
Figure 9.3-1 Block Diagram of P10
Peripheral function input
Peripheral function input enable
Hysteresis
Pull-up
0
1
PDR read
CMOS
pin
PDR
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
ILSR read
ILSR
ILSR write
Figure 9.3-2 Block Diagram of P12
0
1
PDR read
pin
Internal bus
PDR
OD
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.3 Port 1
MB95410H/470H Series
Figure 9.3-3 Block Diagram of P11, P13, P14 and P17
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
PDR write
Only for
P13 and P14
Executing bit manipulation instruction
Internal bus
pin
0
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 9.3-4 Block Diagram of P15 and P16
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
Internal bus
PDR
0
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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Stop, Watch (SPL=1)
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.3 Port 1
MB95410H/470H Series
9.3.1
Port 1 Registers
This section describes the registers of port 1.
■ Port 1 Register Functions
Table 9.3-2 lists the port 1 register functions.
Table 9.3-2
Port 1 Register Functions
Register
Data
abbr.
PDR1
DDR1
PUL1
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Hysteresis input level selected
1
CMOS input level selected
*: For the N-ch open drain pin, this should be Hi-Z.
Table 9.3-3 lists the correspondence between port 1 pins and each register bit.
Table 9.3-3
Correspondence between Registers and Pins for Port 1
Correspondence between related register bits and pins
Pin name
P17
P16
P15
P14
P13
P12
P11
P10
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PUL1
bit7
-
-
bit4
bit3
-
bit1
bit0
ILSR
-
-
-
-
-
-
-
bit0
PDR1
DDR1
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.3 Port 1
9.3.2
MB95410H/470H Series
Operations of Port 1
This section describes the operations of port 1.
■ Operations of Port 1
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR register value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register corresponding to the input pin
of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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9.3 Port 1
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation of the pull-up register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
● Operation of the input level select register
• Setting bit0 in ILSR to "1" changes only P10 from the hysteresis input level to the CMOS
input level. When the same bit is set to "0", the input level of P10 should become the
hysteresis input level.
• For pins other than P10, the CMOS input level cannot be selected, but only the hysteresis
input level can be selected.
• When changing the input level of P10, ensure that the peripheral function (UART/SIO ch. 0
output) has been stopped.
Table 9.3-4 shows the pin states of port 1.
Table 9.3-4
Pin State of Port 1
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port/
peripheral function I/O
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.4 Port 2
9.4
MB95410H/470H Series
Port 2
Port 2 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 2 Configuration
Port 2 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• Port 2 pull-up register (PUL2)
• Input level select register (ILSR)
■ Port 2 Pins
Port 2 has four I/O pins.
Table 9.4-1 lists the port 2 pins.
Table 9.4-1
Port 2 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PPG00: 8/16-bit PPG ch. 0 output
P20/PPG00/
P20: General-purpose I/O CMPN: Voltage comparator N ch
CMPN
input
Hysteresis/
CMOS
analog
-
❍
PPG01: 8/16-bit PPG ch. 0 output
P21/PPG01/
P21: General-purpose I/O CMPP: Voltage comparator P ch
CMPP
input
Hysteresis/
CMOS
analog
-
❍
P22/SCL
P22: General-purpose I/O SCL: I2C clock I/O
Hysteresis/
CMOS ❍
CMOS
-
P23/SDA
P23: General-purpose I/O SDA: I2C data I/O
Hysteresis/
CMOS ❍
CMOS
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.4 Port 2
MB95410H/470H Series
■ Block Diagrams of Port 2
Figure 9.4-1 Block Diagram of P20 and P21
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Analog input enable
Analog input
Figure 9.4-2 Block Diagram of P22 and P23
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Hysteresis
Peripheral function output
0
1
PDR read
1
PDR
pin
CMOS
OD
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
ILSR read
ILSR
ILSR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.4 Port 2
9.4.1
MB95410H/470H Series
Port 2 Registers
This section describes the registers of port 2.
■ Port 2 Register Functions
Table 9.4-2 lists the port 2 register functions.
Table 9.4-2
Port 2 Register Functions
Register
Data
abbr.
PDR2
DDR2
PUL2
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Hysteresis input level selected
1
CMOS input level selected
*: For the N-ch open drain pin, this should be Hi-Z.
Table 9.4-3 lists the correspondence between port 2 pins and each register bit.
Table 9.4-3
Correspondence Between Registers and Pins for Port 2
Correspondence between related register bits and pins
Pin name
-
-
-
-
P23
P22
P21
P20
-
-
-
-
bit3
bit2
bit1
bit0
PUL2
-
-
-
-
-
-
bit1
bit0
ILSR
-
-
-
-
bit3
bit2
-
-
PDR2
DDR2
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9.4.2
Operations of Port 2
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.4 Port 2
This section describes the operations of port 2.
■ Operations of Port 2
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register corresponding to the input pin
of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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9.4 Port 2
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation as an analog input pin
• Setting the voltage comparator analog input disable bit in the voltage comparator control
register (CMR0:VCID) to "0" enables the analog input function of an analog input pin
regardless of the settings of the PDR register.
• To disable the analog input function of an analog input pin, set the VCID bit in the CMR0
register to "1".
● Operation of the pull-up register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
● Operation of the input level select register
• Setting bit2 and bit3 in ILSR to "1" changes P22 and P23 respectively from the hysteresis
input level to the CMOS input level. When the same bit is set to "0", the input levels of P22
and P23 become the hysteresis input level.
• For pins other than P22 and P23, the CMOS input level cannot be selected, but only the
hysteresis input level can be selected.
• When changing the input levels of P22 and P23, ensure that all shared peripheral functions
have been stopped.
Table 9.4-4 shows the pin states of port 2.
Table 9.4-4
Pin State of Port 2
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port/peripheral
function I/O
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.5 Port 4
MB95410H/470H Series
9.5
Port 4
Port 4 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 4 Configuration
Port 4 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Port 4 Pins
Port 4 has four I/O pins.
Table 9.5-1 list the port 4 pins.
Table 9.5-1
Port 4 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P40/SEG21 P40: General-purpose I/O SEG21: LCDC SEG21 output
Hysteresis
CMOS/
LCD
-
-
P41/SEG20 P41: General-purpose I/O SEG20: LCDC SEG20 output
Hysteresis
CMOS/
LCD
-
-
P42/SEG19 P42: General-purpose I/O SEG19: LCDC SEG19 output
Hysteresis
CMOS/
LCD
-
-
P43/SEG18 P43: General-purpose I/O SEG18: LCDC SEG18 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.5 Port 4
MB95410H/470H Series
■ Block Diagram of Port 4
Figure 9.5-1 Block Diagram of P40, P41, P42 and P43
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.5 Port 4
MB95410H/470H Series
9.5.1
Port 4 Registers
This section describes the registers of port 4.
■ Port 4 Register Functions
Table 9.5-2 lists the port 4 register functions.
Table 9.5-2
Port 4 Register Functions
Register
Data
abbr.
PDR4
DDR4
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.5-3 lists the correspondence between port 4 pins and each register bit.
Table 9.5-3
Correspondence between Registers and Pins for Port 4
Correspondence between related register bits and pins
Pin name
PDR4
DDR4
-
-
-
-
P43
P42
P41
P40
-
-
-
-
bit3
bit2
bit1
bit0
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.5 Port 4
9.5.2
MB95410H/470H Series
Operations of Port 4
This section describes the operations of port 4.
■ Operations of Port 4
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit (SEG21 to SEG18) in the LCDC enable register 5 (LCDCE5) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit (SEG21 to SEG18) in the LCDC enable register 5 (LCDCE5) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit (SEG21 to SEG18)
in the LCDC enable register 5 (LCDCE5) to "1", and then set the port input control bit
(PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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9.5 Port 4
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 9.5-4 shows the pin states of port 4.
Table 9.5-4
Pin State of Port 4
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.6 Port 5
9.6
MB95410H/470H Series
Port 5
Port 5 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 5 Configuration
Port 5 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Port 5 pull-up register (PUL5)
■ Port 5 Pins
Port 5 has four I/O pins.
Table 9.6-1 lists the port 5 pins.
Table 9.6-1
Port 5 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P50/TO01
P50: General-purpose I/O
TO01: 8/16-bit composite timer ch. 0
Hysteresis CMOS
output
-
❍
P51/EC0
P51: General-purpose I/O
EC0: 8/16-bit composite timer ch. 0
clock input
Hysteresis CMOS
-
❍
P52/TI0/TO00 P52: General-purpose I/O TO00: 8/16-bit composite timer ch. 0 Hysteresis CMOS
output
-
❍
-
❍
TI0: 16-bit reload timer input
P53/TO0
P53: General-purpose I/O TO0: 16-bit reload timer output
Hysteresis CMOS
OD: N-ch open drain, PU: Pull-up
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9.6 Port 5
MB95410H/470H Series
■ Block Diagram of Port 5
Figure 9.6-1 Block Diagram of P50, P51, P52 and P53
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
PDR write
Executing bit manipulation instruction
Internal bus
pin
0
Only for
P51 and P52
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.6 Port 5
9.6.1
MB95410H/470H Series
Port 5 Registers
This section describes the registers of port 5.
■ Port 5 Register Functions
Table 9.6-2 lists the port 5 register functions.
Table 9.6-2
Port 5 Register Functions
Register
Data
abbr.
PDR5
DDR5
PUL5
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
Table 9.6-3 lists the correspondence between port 5 pins and each register bit.
Table 9.6-3
Correspondence between Registers and Pins for Port 5
Correspondence between related register bits and pins
Pin name
-
-
-
-
P53
P52
P51
P50
-
-
-
-
bit3
bit2
bit1
bit0
PDR5
DDR5
PUL5
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9.6.2
Operations of Port 5
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.6 Port 5
This section describes the operations of port 5.
■ Operations of Port 5
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register corresponding to the input pin
of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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9.6 Port 5
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation of the pull-up register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
Table 9.6-4 shows the pin states of port 5.
Table 9.6-4
Pin State of Port 5
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.7 Port 6
MB95410H/470H Series
9.7
Port 6
Port 6 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 6 Configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
■ Port 6 Pins
Port 6 has eight I/O pins.
Table 9.7-1 lists the port 6 pins.
Table 9.7-1
Port 6 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P60/SEG10 P60: General-purpose I/O SEG10: LCDC SEG10 output
Hysteresis
CMOS/
LCD
-
-
P61/SEG11 P61: General-purpose I/O SEG11: LCDC SEG11 output
Hysteresis
CMOS/
LCD
-
-
P62/SEG12 P62: General-purpose I/O SEG12: LCDC SEG12 output
Hysteresis
CMOS/
LCD
-
-
P63/SEG13 P63: General-purpose I/O SEG13: LCDC SEG13 output
Hysteresis
CMOS/
LCD
-
-
P64/SEG14 P64: General-purpose I/O SEG14: LCDC SEG14 output
Hysteresis
CMOS/
LCD
-
-
P65/SEG15 P65: General-purpose I/O SEG15: LCDC SEG15 output
Hysteresis
CMOS/
LCD
-
-
P66/SEG16 P66: General-purpose I/O SEG16: LCDC SEG16 output
Hysteresis
CMOS/
LCD
-
-
P67/SEG17 P67: General-purpose I/O SEG17: LCDC SEG17 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.7 Port 6
MB95410H/470H Series
■ Block Diagram of Port 6
Figure 9.7-1 Block Diagram of P60, P61, P62, P63, P64, P65, P66 and P67
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.7 Port 6
MB95410H/470H Series
9.7.1
Port 6 Registers
This section describes the registers of port 6.
■ Port 6 Register Functions
Table 9.7-2 lists the port 6 register functions.
Table 9.7-2
Port 6 Register Functions
Register
Data
abbr.
PDR6
DDR6
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.7-3 lists the correspondence between port 6 pins and each register bit.
Table 9.7-3
Correspondence between Registers and Pins for Port 6
Correspondence between related register bits and pins
Pin name
PDR6
DDR6
P67
P66
P65
P64
P63
P62
P61
P60
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.7 Port 6
9.7.2
MB95410H/470H Series
Operations of Port 6
This section describes the operations of port 6.
■ Operations of Port 6
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 4 (LCDCE4:SEG15 to SEG10) or in the LCDC
enable register 5 (LCDCE5:SEG17, SEG16) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 4 (LCDCE4:SEG15 to SEG10) or in the LCDC
enable register 5 (LCDCE5:SEG17, SEG16) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 4 (LCDCE4:SEG15 to SEG10) or in the LCDC enable register 5 (LCDCE5:SEG17,
SEG16) to "1", and then set the port input control bit (PICTL) in the LCDC enable
register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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9.7 Port 6
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 9.7-4 shows the pin states of port 6.
Table 9.7-4
Pin State of Port 6
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.8 Port 9
9.8
MB95410H/470H Series
Port 9
Port 9 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 9 Configuration
Port 9 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 9 data register (PDR9)
• Port 9 direction register (DDR9)
■ Port 9 Pins
Port 9 has five I/O pins.
Table 9.8-1 lists the port 9 pins.
Table 9.8-1
Port 9 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P90/V4
P90: General-purpose I/O
V4: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P91/V3
P91: General-purpose I/O
V3: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P92/V2
P92: General-purpose I/O
V2: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P93/V1
P93: General-purpose I/O
V1: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P94/V0
P94: General-purpose I/O
V0: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.8 Port 9
■ Block Diagrams of Port 9
Figure 9.8-1 Block Diagram of P90, P91, P92, P93 and P94
LCD power supply
LCD power supply
enable
0
1
PDR read
pin
Internal bus
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.8 Port 9
9.8.1
MB95410H/470H Series
Port 9 Registers
This section describes the registers of port 9.
■ Port 9 Register Functions
Table 9.8-2 lists the port 9 register functions.
Table 9.8-2
Port 9 Register Functions
Register
Data
abbr.
PDR9
DDR9
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.8-3 lists the correspondence between port 9 pins and each register bit.
Table 9.8-3
Correspondence between Registers and Pins for Port 9
Correspondence between related register bits and pins
Pin name
PDR9
DDR9
160
-
-
-
P94
P93
P92
P91
P90
-
-
-
bit4
bit3
bit2
bit1
bit0
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9.8.2
Operations of Port 9
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.8 Port 9
This section describes the operations of port 9.
■ Operations of Port 9
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set the bit (VE4 to VE0)
corresponding to that pin in the LCDC enable register 1 (LCDCE1) to "0".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set the bit (VE4 to VE0)
corresponding to that pin in the LCDC enable register 1 (LCDCE1) to "0".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operations as LCDC pins
• Set the DDR register bit corresponding to a desired LCDC pin to "0".
• Set the V0 select bit (VE0), the V1 select bit (VE1), the V2 select bit (VE2), the V3 select
bit (VE3) and the V4 select bit (VE4) in the LCDC enable register 1 (LCDCE1) to "1".
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9.8 Port 9
MB95410H/470H Series
Table 9.8-4 shows the pin states of port 9.
Table 9.8-4
Pin State of Port 9
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.9 Port A
MB95410H/470H Series
9.9
Port A
Port A is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port A Configuration
Port A is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port A data register (PDRA)
• Port A direction register (DDRA)
■ Port A Pins
Port A has eight I/O pins.
Table 9.9-1 lists the port A pins.
Table 9.9-1
Port A Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PA0/COM0 PA0: General-purpose I/O COM0: LCDC COM0 output
Hysteresis
CMOS/
LCD
-
-
PA1/COM1 PA1: General-purpose I/O COM1: LCDC COM1 output
Hysteresis
CMOS/
LCD
-
-
PA2/COM2 PA2: General-purpose I/O COM2: LCDC COM2 output
Hysteresis
CMOS/
LCD
-
-
PA3/COM3 PA3: General-purpose I/O COM3: LCDC COM3 output
Hysteresis
CMOS/
LCD
-
-
PA4/COM4 PA4: General-purpose I/O COM4: LCDC COM4 output
Hysteresis
CMOS/
LCD
-
-
PA5/COM5 PA5: General-purpose I/O COM5: LCDC COM5 output
Hysteresis
CMOS/
LCD
-
-
PA6/COM6 PA6: General-purpose I/O COM6: LCDC COM6 output
Hysteresis
CMOS/
LCD
-
-
PA7/COM7 PA7: General-purpose I/O COM7: LCDC COM7 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.9 Port A
MB95410H/470H Series
■ Block Diagram of Port A
Figure 9.9-1 Block Diagram of PA0, PA1, PA2, PA3, PA4, PA5, PA6 and PA7
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
164
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.9 Port A
MB95410H/470H Series
9.9.1
Port A Registers
This section describes the registers of port A.
■ Port A Register Functions
Table 9.9-2 lists the port A register functions.
Table 9.9-2
Port A Register Functions
Register
Data
abbr.
PDRA
DDRA
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.9-3 lists the correspondence between port A pins and each register bit.
Table 9.9-3
Correspondence between Registers and Pins for Port A
Correspondence between related register bits and pins
Pin name
PDRA
DDRA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.9 Port A
9.9.2
MB95410H/470H Series
Operations of Port A
This section describes the operations of port A.
■ Operations of Port A
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding common
select bit (COM7 to COM0) in the LCDC enable register 2 (LCDCE2) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding common
select bit (COM7 to COM0) in the LCDC enable register 2 (LCDCE2) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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9.9 Port A
MB95410H/470H Series
● Operation as an LCDC common output
• Set the DDR register bit corresponding to a desired LCDC common output pin to "0".
• Select the common output by setting a corresponding common select bit (COM7 to COM0)
in the LCDC enable register 2 (LCDCE2) to "1", and then set the port input control bit
(PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
Table 9.9-4 shows the pin states of port A.
Table 9.9-4
Pin State of Port A
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.10 Port B
9.10
MB95410H/470H Series
Port B
Port B is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port B Configuration
Port B is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port B data register (PDRB)
• Port B direction register (DDRB)
■ Port B Pins
Port B has five I/O pins.
Table 9.10-1 lists the port B pins.
Table 9.10-1 Port B Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PB0/SEG00 PB0: General-purpose I/O SEG00: LCDC SEG00 output
Hysteresis
CMOS/
LCD
-
-
PB1/SEG01 PB1: General-purpose I/O SEG01: LCDC SEG01 output
Hysteresis
CMOS/
LCD
-
-
PB2/SEG37 PB2: General-purpose I/O SEG37: LCDC SEG37 output
Hysteresis
CMOS/
LCD
-
-
PB3/SEG38 PB3: General-purpose I/O SEG38: LCDC SEG38 output
Hysteresis
CMOS/
LCD
-
-
PB4/SEG39 PB4: General-purpose I/O SEG39: LCDC SEG39 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.10 Port B
■ Block Diagram of Port B
Figure 9.10-1 Block Diagram of PB0, PB1, PB2, PB3 and PB4
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.10 Port B
9.10.1
MB95410H/470H Series
Port B Registers
This section describes the registers of port B.
■ Port B Register Functions
Table 9.10-2 lists the port B register functions.
Table 9.10-2 Port B Register Functions
Register
Data
abbr.
PDRB
DDRB
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.10-3 lists the correspondence between port B pins and each register bit.
Table 9.10-3 Correspondence between Registers and Pins for Port B
Correspondence between related register bits and pins
Pin name
PDRB
DDRB
170
-
-
-
PB4
PB3
PB2
PB1
PB0
-
-
-
bit4
bit3
bit2
bit1
bit0
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9.10.2
Operations of Port B
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.10 Port B
This section describes the operations of port B.
■ Operations of Port B
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 3 (LCDCE3:SEG01, SEG00) or in the LCDC enable
register 7 (LCDCE7:SEG39 to SEG37) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit the LCDC enable register 3 (LCDCE3:SEG01, SEG00) or in the LCDC enable
register 7 (LCDCE7:SEG39 to SEG37) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit the LCDC enable
register 3 (LCDCE3:SEG01, SEG00) or in the LCDC enable register 7 (LCDCE7:SEG39 to
SEG37) to "1", and then set the port input control bit (PICTL) in LCDC enable register 1
(LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.10 Port B
MB95410H/470H Series
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 9.10-4 shows the pin states of port B.
Table 9.10-4 Pin State of Port B
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.11 Port C
MB95410H/470H Series
9.11
Port C
Port C is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port C Configuration
Port C is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port C data register (PDRC)
• Port C direction register (DDRC)
■ Port C Pins
Port C has eight I/O pins.
Table 9.11-1 lists the port C pins.
Table 9.11-1 Port C Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PC0/SEG02 PC0: General-purpose I/O SEG02: LCDC SEG02 output
Hysteresis
CMOS/
LCD
-
-
PC1/SEG03 PC1: General-purpose I/O SEG03: LCDC SEG03 output
Hysteresis
CMOS/
LCD
-
-
PC2/SEG04 PC2: General-purpose I/O SEG04: LCDC SEG04 output
Hysteresis
CMOS/
LCD
-
-
PC3/SEG05 PC3: General-purpose I/O SEG05: LCDC SEG05 output
Hysteresis
CMOS/
LCD
-
-
PC4/SEG06 PC4: General-purpose I/O SEG06: LCDC SEG06 output
Hysteresis
CMOS/
LCD
-
-
PC5/SEG07 PC5: General-purpose I/O SEG07: LCDC SEG07 output
Hysteresis
CMOS/
LCD
-
-
PC6/SEG08 PC6: General-purpose I/O SEG08: LCDC SEG08 output
Hysteresis
CMOS/
LCD
-
-
PC7/SEG09 PC7: General-purpose I/O SEG09: LCDC SEG09 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.11 Port C
MB95410H/470H Series
■ Block Diagram of Port C
Figure 9.11-1 Block Diagram of PC0, PC1, PC2, PC3, PC4, PC5, PC6 and PC7
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
174
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.11 Port C
MB95410H/470H Series
9.11.1
Port C Registers
This section describes the registers of port C.
■ Port C Register Functions
Table 9.11-2 lists the port C register functions.
Table 9.11-2 Port C Register Functions
Register
Data
abbr.
PDRC
DDRC
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.11-3 lists the correspondence between port C pins and each register bit.
Table 9.11-3 Correspondence between Registers and Pins for Port C
Correspondence between related register bits and pins
Pin name
PDRC
DDRC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.11 Port C
9.11.2
MB95410H/470H Series
Operations of Port C
This section describes the operations of port C.
■ Operations of Port C
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 3 (LCDCE3:SEG07 to SEG02) or in the LCDC
enable register 4 (LCDCE4:SEG09, SEG08) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 3 (LCDCE3:SEG07 to SEG02) or in the LCDC
enable register 4 (LCDCE4:SEG09, SEG08) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 3 (LCDCE3:SEG07 to SEG02) or in the LCDC enable register 4 (LCDCE4:SEG09,
SEG08) to "1", and then set the port input control bit (PICTL) in LCDC enable register 1
(LCDCE1) to "1".
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.11 Port C
MB95410H/470H Series
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 9.11-4 shows the pin states of port C.
Table 9.11-4 Pin State of Port C
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.12 Port E
9.12
MB95410H/470H Series
Port E
Port E is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port E Configuration
Port E is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port E data register (PDRE)
• Port E direction register (DDRE)
■ Port E Pins
Port E has eight I/O pins.
Table 9.12-1 lists the port E pins.
Table 9.12-1 Port E Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PE0/SEG22 PE0: General-purpose I/O SEG22: LCDC SEG22 output
Hysteresis
CMOS/
LCD
-
-
PE1/SEG23 PE1: General-purpose I/O SEG23: LCDC SEG23 output
Hysteresis
CMOS/
LCD
-
-
PE2/SEG24 PE2: General-purpose I/O SEG24: LCDC SEG24 output
Hysteresis
CMOS/
LCD
-
-
PE3/SEG25 PE3: General-purpose I/O SEG25: LCDC SEG25 output
Hysteresis
CMOS/
LCD
-
-
PE4/SEG26 PE4: General-purpose I/O SEG26: LCDC SEG26 output
Hysteresis
CMOS/
LCD
-
-
SEG27: LCDC SEG27 output
PE5/SEG27/
CMOS/
PE5: General-purpose I/O TO11: 8/16-bit composite timer ch. 1 Hysteresis
TO11
LCD
output
-
-
SEG28: LCDC SEG28 output
PE6/SEG28/
CMOS/
PE6: General-purpose I/O TO10: 8/16-bit composite timer ch. 1 Hysteresis
TO10
LCD
output
-
-
SEG29: LCDC SEG29 output
PE7/SEG29/
PE7: General-purpose I/O EC1: 8/16-bit composite timer ch. 1
EC1
clock input
-
-
Hysteresis
CMOS/
LCD
OD: N-ch open drain, PU: Pull-up
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.12 Port E
MB95410H/470H Series
■ Block Diagrams of Port E
Figure 9.12-1 Block Diagram of PE0, PE1, PE2, PE3 and PE4
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
Figure 9.12-2 Block Diagram of PE5, PE6 and PE7
LCD output
Peripheral function input
Peripheral function input enable
LCD output enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
Internal bus
PDR
0
PDR write
Executing bit manipulation instruction
Only for PE7
DDR read
DDR
DDR write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.12 Port E
9.12.1
MB95410H/470H Series
Port E Registers
This section describes the registers of port E.
■ Port E Register Functions
Table 9.12-2 lists the port E register functions.
Table 9.12-2 Port E Register Functions
Register
Data
abbr.
PDRE
DDRE
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 9.12-3 lists the correspondence between port E pins and each register bit.
Table 9.12-3 Correspondence between Registers and Pins for Port E
Correspondence between related register bits and pins
Pin name
PDRE
DDRE
180
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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9.12.2
Operations of Port E
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.12 Port E
This section describes the operations of port E.
■ Operations of Port E
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable
register 6 (SEG29 to SEG24) to "0" to select the general-purpose I/O port function, and then
set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable
register 6 (SEG29 to SEG24) to "0" to select the general-purpose I/O port function, and then
set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
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9.12 Port E
MB95410H/470H Series
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register bit corresponding to the input
pin of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable register 6 (SEG29 to SEG24)
to "1", and then set the port input control bit (PICTL) in LCDC enable register 1 (LCDCE1)
to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 9.12-4 shows the pin states of port E.
Table 9.12-4 Pin State of Port E
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.13 Port F
MB95410H/470H Series
9.13
Port F
Port F is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port F Configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
■ Port F Pins
Port F has three I/O pins.
Table 9.13-1 lists the port F pins.
Table 9.13-1 Port F Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PF0/X0*1
PF0: General-purpose I/O X0: Main clock oscillation pin
Hysteresis CMOS
-
-
PF1/X1*1
PF1: General-purpose I/O X1: Main clock oscillation pin
Hysteresis CMOS
-
-
PF2: General-purpose I/O RST: Reset pin
Hysteresis CMOS ❍
-
PF2/RST
*2
OD: N-ch open drain, PU: Pull-up
*1: If the main oscillation clock is selected (SYSC:PFSEL = 0), the port function cannot be used.
*2: If the external reset is selected (SYSC:RSTEN = 1), the port function cannot be used. This pin is a
dedicated reset pin in MB95F414H/F416H/F418H.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.13 Port F
MB95410H/470H Series
■ Block Diagrams of Port F
Figure 9.13-1 Block Diagram of PF0 and PF1
0
1
PDR read
Internal bus
PDR
pin
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
Figure 9.13-2 Block Diagram of PF2
Reset input
Reset input enable
Reset output enable
Reset output
0
1
PDR read
1
0
Internal bus
PDR
pin
OD
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
184
Stop, Watch (SPL=1)
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.13 Port F
MB95410H/470H Series
9.13.1
Port F Registers
This section describes the registers of port F.
■ Port F Register Functions
Table 9.13-2 lists the port F register functions.
Table 9.13-2 Port F Register Functions
Register
Data
abbr.
PDRF
DDRF
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
*: For the N-ch open drain pin, this should be Hi-Z.
Table 9.13-3 lists the correspondence between port F pins and each register bit.
Table 9.13-3 Correspondence between Registers and Pins for Port F
Correspondence between related register bits and pins
Pin name
PDRF
DDRF
-
-
-
-
-
PF2*
PF1
PF0
-
-
-
-
-
bit2
bit1
bit0
*: PF2/RST is a dedicated reset pin in MB95F414H/F416H/F418H.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.13 Port F
9.13.2
MB95410H/470H Series
Operations of Port F
This section describes the operations of port F.
■ Operations of Port F
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.13 Port F
Table 9.13-4 shows the pin states of port F.
Table 9.13-4 Pin State of Port F
Operating
state
Pin state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
I/O port
Stop (SPL=1)
Watch (SPL=1)
At reset
Hi-Z
Input cutoff
Hi-Z
Input enabled*1
(Not functional)
Low*2
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*1: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
*2: Only for PF2 at power-on reset.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.14 Port G
9.14
MB95410H/470H Series
Port G
Port G is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port G Configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
■ Port G Pin
Port G has two I/O pin.
Table 9.14-1 lists the port G pins.
Table 9.14-1 Port G Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PG1/X0A*
PG1: General-purpose I/O X0A: Subclock oscillation pin
Hysteresis
CMOS
-
❍
PG2/X1A*
PG2: General-purpose I/O X1A: Subclock oscillation pin
Hysteresis
CMOS
-
❍
OD: N-ch open drain, PU: Pull-up
*: If the sub-oscillation clock is selected (SYSC:PGSEL = 0), the port function cannot be used.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.14 Port G
■ Block Diagram of Port G
Figure 9.14-1 Block Diagram of PG2 and PG2
0
Pull-up
1
PDR read
PDR
pin
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.14 Port G
9.14.1
MB95410H/470H Series
Port G Registers
This section describes the registers of port G.
■ Port G Register Functions
Table 9.14-2 lists the port G register functions.
Table 9.14-2 Port G Register Functions
Register
Data
abbr.
PDRG
DDRG
PULG
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
Table 9.14-3 lists the correspondence between port G pins and each register bit.
Table 9.14-3 Correspondence between Registers and Pins for Port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
-
-
-
-
-
bit2
bit1
-
PDRG
DDRG
PULG
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9.14.2
Operations of Port G
CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.14 Port G
This section describes the operations of port G.
■ Operations of Port G
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation of the pull-up register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
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CHAPTER 9 I/O PORTS (MB95410H SERIES)
9.14 Port G
MB95410H/470H Series
Table 9.14-4 shows the pin states of port G.
Table 9.14-4 Pin State of Port G
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10
I/O PORTS
(MB95470H SERIES)
This chapter describes the functions and
operations of the I/O ports.
10.1 Overview of I/O Ports
10.2 Port 0
10.3 Port 1
10.4 Port 2
10.5 Port 6
10.6 Port 9
10.7 Port A
10.8 Port B
10.9 Port C
10.10 Port E
10.11 Port F
10.12 Port G
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.1 Overview of I/O Ports
10.1
MB95410H/470H Series
Overview of I/O Ports
I/O ports are used to control general-purpose I/O pins.
■ Overview of I/O Ports
The I/O port has functions to output data from the CPU and capture input signals into the CPU
with the port data register (PDR). The I/O direction of an individual I/O pin can be set as
desired by using the corresponding to that I/O pin in the port direction register (DDR).
Table 10.1-1 lists the registers for each pin.
Table 10.1-1
List of Port Registers (1 / 2)
Register name
Read/Write
Initial value
Port 0 data register
PDR0
R, RM/W
00000000B
Port 0 direction register
DDR0
R/W
00000000B
Port 1 data register
PDR1
R, RM/W
00000000B
Port 1 direction register
DDR1
R/W
00000000B
Port 2 data register
PDR2
R, RM/W
00000000B
Port 2 direction register
DDR2
R/W
00000000B
Port 6 data register
PDR6
R, RM/W
00000000B
Port 6 direction register
DDR6
R/W
00000000B
Port 9 data register
PDR9
R, RM/W
00000000B
Port 9 direction register
DDR9
R/W
00000000B
Port A data register
PDRA
R, RM/W
00000000B
Port A direction register
DDRA
R/W
00000000B
Port B data register
PDRB
R, RM/W
00000000B
Port B direction register
DDRB
R/W
00000000B
Port C data register
PDRC
R, RM/W
00000000B
Port C direction register
DDRC
R/W
00000000B
Port E data register
PDRE
R, RM/W
00000000B
Port E direction register
DDRE
R/W
00000000B
Port F data register
PDRF
R, RM/W
00000000B
Port F direction register
DDRF
R/W
00000000B
Port G data register
PDRG
R, RM/W
00000000B
Port G direction register
DDRG
R/W
00000000B
Port 1 pull-up register
PUL1
R/W
00000000B
Port 2 pull-up register
PUL2
R/W
00000000B
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Table 10.1-1
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.1 Overview of I/O Ports
List of Port Registers (2 / 2)
Register name
Read/Write
Initial value
Port G pull-up register
PULG
R/W
00000000B
A/D input disable register (lower)
AIDRL
R/W
00000000B
ILSR
R/W
00000000B
Input level select register
R/W
: Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is
read by the read-modify-write (RMW) type of instruction.)
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.2 Port 0
10.2
MB95410H/470H Series
Port 0
Port 0 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 0 Configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• A/D input disable register lower (AIDRL)
• Input level select register (ILSR)
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.2 Port 0
MB95410H/470H Series
■ Port 0 Pins
Port 0 has eight I/O pins.
Table 10.2-1 lists the port 0 pins.
Table 10.2-1
Port 0 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
INT00: External interrupt input
P00/INT00/
AN00:Analog input
AN00/SEG29/ P00: General-purpose I/O
SEG29: LCDC SEG29 output
UO2
UO2: UART/SIO ch. 2 data output
Output OD PU
Hysteresis/ CMOS/
analog
LCD
-
-
-
-
INT01: External interrupt input
AN01: Analog input
P01/INT01/
Hysteresis/
SEG28: LCDC SEG28 output
CMOS/
AN01/SEG28/ P01: General-purpose I/O
CMOS/
LCD
UI2: UART/SIO ch. 2 data input
UI2/TO00
analog
TO00: 8/16-bit composite timer ch. 0
output
INT02: External interrupt input
P02/INT02/
AN02: Analog input
AN02/SEG27/ P02: General-purpose I/O
SEG27: LCDC SEG27 output
UCK2
UCK2: UART/SIO ch. 2 clock I/O
Hysteresis/ CMOS/
analog
LCD
-
-
INT03: External interrupt input
P03/INT03/
AN03: Analog input
AN03/SEG26/ P03: General-purpose I/O
SEG26: LCDC SEG26 output
UO1
UO1: UART/SIO ch. 1 data output
Hysteresis/ CMOS/
analog
LCD
-
-
INT04: External interrupt input
P04/INT04/
AN04: Analog input
AN04/SEG25/ P04: General-purpose I/O
SEG25: LCDC SEG25 output
UI1
UI1: UART/SIO ch. 1 data input
Hysteresis/
CMOS/
CMOS/
LCD
analog
-
-
INT05: External interrupt input
P05/INT05/
AN05: Analog input
AN05/SEG24/ P05: General-purpose I/O
SEG24: LCDC SEG24 output
UCK1
UCK1: UART/SIO ch. 1 clock I/O
Hysteresis/ CMOS/
analog
LCD
-
-
INT06: External interrupt input
P06/INT06/
P06: General-purpose I/O AN06: Analog input
AN06/SEG23
SEG23: LCDC SEG23 output
Hysteresis/ CMOS/
analog
LCD
-
-
INT07: External interrupt input
P07/INT07/
P07: General-purpose I/O AN07: Analog input
AN07/SEG22
SEG22: LCDC SEG22 output
Hysteresis/ CMOS/
analog
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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10.2 Port 0
MB95410H/470H Series
■ Block Diagrams of Port 0
Figure 10.2-1 Block Diagram of P01 and P04
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
CMOS
Peripheral function output
0
1
PDR read
1
Hysteresis
pin
PDR
0
PDR write
Executing bit manipulation instruction
Only for INT01
and INT04
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
ILSR read
ILSR
ILSR write
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10.2 Port 0
MB95410H/470H Series
Figure 10.2-2 Block Diagram of P00, P02, P03, P05, P06 and P07
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
PDR
0
PDR write
Internal bus
Executing bit manipulation instruction
Only for INT00,
INT02, INT03,
INT05 to INT07
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.2 Port 0
10.2.1
MB95410H/470H Series
Port 0 Registers
This section describes the registers of port 0.
■ Port 0 Register Functions
Table 10.2-2 lists the functions of the port 0 register.
Table 10.2-2
Port 0 Register Functions
Register
Data
abbr.
PDR0
DDR0
AIDRL
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
0
Analog input enabled
1
Port input enabled
0
Hysteresis input level selected
1
CMOS input level selected
Table 10.2-3 lists the correspondence between port 0 pins and each register bit.
Table 10.2-3
Correspondence between Registers and Pins for Port 0
Correspondence between related register bits and pins
Pin name
P07
P06
P05
P04
P03
P02
P01
P00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
bit4
-
-
bit1
-
PDR0
DDR0
AIDRL
ILSR
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10.2.2
Operations of Port 0
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.2 Port 0
This section describes the operations of port 0.
■ Operations of Port 0
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR register value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable
register 6 (LCDCE6:SEG29 to SEG24) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When using an analog input shared pin as an input port, set the corresponding bit in the A/D
input disable register lower (AIDRL) to "1".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable
register 6 (LCDCE6:SEG29 to SEG24) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register bit corresponding to the input
pin of a peripheral function to "0".
• When using the analog input shared pin as another peripheral function input pin, configure
it as an input port, which is the same as the operation as an input port.
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
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10.2 Port 0
MB95410H/470H Series
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 5 (LCDCE5:SEG23, SEG22) or in the LCDC enable register 6 (LCDCE6:SEG29 to
SEG24) to "1", and then set the port input control bit (PICTL) in the LCDC enable register
1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
As for a pin shared with analog input, its port input is disabled because the A/D input disable
register lower (AIDRL) is initialized to "0".
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open. However, if the interrupt input
is enabled for the external interrupt (INT07 to INT00), the input is enabled and not blocked.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation as an analog input pin
• Set the bit in the DDR register corresponding to the analog input pin to "0" and the bit
corresponding to that pin in the AIDRL register to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions. In addition, set the corresponding bit in the PUL register to "0".
● Operation as an external interrupt input pin
• Set the bit in the DDR register corresponding to the external interrupt input pin to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a
function other than the interrupt, disable the external interrupt function corresponding to
that pin.
● Operation of the input level select register
• Setting bit1 and bit4 in ILSR to "1" changes P01 and P04 respectively from the hysteresis
input level to the CMOS input level.
• For pins other than P01 and P04, the CMOS input level cannot be selected, but only the
hysteresis input level can be selected.
• When changing the input level of P01 or of P04, ensure that all shared peripheral functions
have been stopped.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.2 Port 0
Table 10.2-4 shows the pin states of port 0.
Table 10.2-4
Operating
state
Pin state
Pin State of Port 0
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
Hi-Z
(the pull-up setting is enabled)
I/O port/
Input cutoff
peripheral function I/O
(If the external interrupt function is enabled,
the external interrupt can be input.)
At reset
Hi-Z
Input disabled*
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input disabled" means the state that the operation of the input gate adjacent to the pin is disabled.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.3 Port 1
10.3
MB95410H/470H Series
Port 1
Port 1 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 1 Configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
• Input level select register (ILSR)
■ Port 1 Pins
Port 1 has eight I/O pins.
Table 10.3-1 lists the port 1 pins.
Table 10.3-1
Port 1 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
P10/UI0/TO0 P10: General-purpose I/O
UI0: UART/SIO ch. 0 data input
TO0: 16-bit reload timer output
P11/UO0
P11: General-purpose I/O UO0: UART/SIO ch. 0 data output
P12/DBG
P12: General-purpose I/O
DBG: On-chip debug
communication pin
Output OD PU
Hysteresis/
CMOS
CMOS
-
❍
Hysteresis CMOS
-
❍
Hysteresis CMOS ❍
-
ADTG: A/D trigger input
P13/ADTG/
P13: General-purpose I/O TO01: 8/16-bit composite timer ch. 0 Hysteresis CMOS
TO01
output
-
❍
Hysteresis CMOS
-
❍
UCK0: UART/SIO ch. 0 clock I/O
P14/UCK0/
EC0: 8/16-bit composite timer ch. 0
P14: General-purpose I/O
EC0/TI0
clock input
TI0: 16-bit reload timer input
PPG11: 8/16-bit PPG ch. 1 output
P15/PPG11/
P15: General-purpose I/O
SEG31
SEG31: LCDC SEG31 output
Hysteresis
CMOS/
LCD
-
-
PPG10: 8/16-bit PPG ch. 1 output
P16/PPG10/
P16: General-purpose I/O
SEG30
SEG30: LCDC SEG30 output
Hysteresis
CMOS/
LCD
-
-
P17/CMPO P17: General-purpose I/O CMPO: Voltage comparator output
Hysteresis CMOS
-
❍
OD: N-ch open drain, PU: Pull-up
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10.3 Port 1
MB95410H/470H Series
■ Block Diagrams of Port 1
Figure 10.3-1 Block Diagram of P10
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Hysteresis
Peripheral function output
Pull-up
0
1
PDR read
1
CMOS
pin
PDR
0
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
ILSR read
ILSR
ILSR write
Figure 10.3-2 Block Diagram of P12
0
1
PDR read
pin
Internal bus
PDR
OD
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
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10.3 Port 1
MB95410H/470H Series
Figure 10.3-3 Block Diagram of P11, P13, P14 and P17
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
PDR write
Only for
P13 and P14
Executing bit manipulation instruction
Internal bus
pin
0
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 10.3-4 Block Diagram of P15 and P16
LCD output
LCD output enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
Internal bus
PDR
0
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
206
Stop, Watch (SPL=1)
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.3 Port 1
MB95410H/470H Series
10.3.1
Port 1 Registers
This section describes the registers of port 1.
■ Port 1 Register Functions
Table 10.3-2 lists the port 1 register functions.
Table 10.3-2
Port 1 Register Functions
Register
Data
abbr.
PDR1
DDR1
PUL1
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Hysteresis input level selected
1
CMOS input level selected
*: For the N-ch open drain pin, this should be Hi-Z.
Table 10.3-3 lists the correspondence between port 1 pins and each register bit.
Table 10.3-3
Correspondence between Registers and Pins for Port 1
Correspondence between related register bits and pins
Pin name
P17
P16
P15
P14
P13
P12
P11
P10
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PUL1
bit7
-
-
bit4
bit3
-
bit1
bit0
ILSR
-
-
-
-
-
-
-
bit0
PDR1
DDR1
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.3 Port 1
10.3.2
MB95410H/470H Series
Operations of Port 1
This section describes the operations of port 1.
■ Operations of Port 1
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR register value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit (SEG31, SEG30) in the LCDC enable register 6 (LCDCE6) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set aa corresponding segment
select bit (SEG31, SEG30) in the LCDC enable register 6 (LCDCE6) "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register corresponding to the input pin
of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.3 Port 1
MB95410H/470H Series
to read the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit (SEG31, SEG30) in
the LCDC enable register 6 (LCDCE6) to "1", and then set the port input control bit
(PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation of the pull-up control register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
● Operation of the input level select register
• Setting bit0 in ILSR to "1" changes only P10 from the hysteresis input level to the CMOS
input level. When the same bit is set to "0", the input level of P10 should become the
hysteresis input level.
• For pins other than P10, the CMOS input level cannot be selected, but only the hysteresis
input level can be selected.
• When changing the input level of P10, ensure that all its shared peripheral functions have
been stopped.
Table 10.3-4 shows the pin states of port 1.
Table 10.3-4
Pin State of Port 1
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port/
peripheral function I/O
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.4 Port 2
10.4
MB95410H/470H Series
Port 2
Port 2 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 2 Configuration
Port 2 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• Port 2 pull-up register (PUL2)
• Input level select register (ILSR)
■ Port 2 Pins
Port 2 has four I/O pins.
Table 10.4-1 lists the port 2 pins.
Table 10.4-1
Port 2 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PPG00: 8/16-bit PPG ch. 0 output
P20/PPG00/
P20: General-purpose I/O CMPN: Voltage comparator N ch
CMPN
input
Hysteresis/
CMOS
analog
-
❍
PPG01: 8/16-bit PPG ch. 0 output
P21/PPG01/
P21: General-purpose I/O CMPP: Voltage comparator P ch
CMPP
input
Hysteresis/
CMOS
analog
-
❍
P22/SCL
P22: General-purpose I/O SCL: I2C clock I/O
Hysteresis/
CMOS ❍
CMOS
-
P23/SDA
P23: General-purpose I/O SDA: I2C data I/O
Hysteresis/
CMOS ❍
CMOS
-
OD: N-ch open drain, PU: Pull-up
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10.4 Port 2
MB95410H/470H Series
■ Block Diagrams of Port 2
Figure 10.4-1 Block Diagram of P20 and P21
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Analog input enable
Analog input
Figure 10.4-2 Block Diagram of P22 and P23
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Hysteresis
Peripheral function output
0
1
PDR read
1
PDR
pin
CMOS
OD
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
ILSR read
ILSR
ILSR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.4 Port 2
10.4.1
MB95410H/470H Series
Port 2 Registers
This section describes the registers of port 2.
■ Port 2 Register Functions
Table 10.4-2 lists the port 2 register functions.
Table 10.4-2
Port 2 Register Functions
Register
Data
abbr.
PDR2
DDR2
PUL2
ILSR
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Hysteresis input level selected
1
CMOS input level selected
*: For the N-ch open drain pin, this should be Hi-Z.
Table 10.4-3 lists the correspondence between port 2 pins and each register bit.
Table 10.4-3
Correspondence Between Registers and Pins for Port 2
Correspondence between related register bits and pins
Pin name
-
-
-
-
P23
P22
P21
P20
-
-
-
-
bit3
bit2
bit1
bit0
PUL2
-
-
-
-
-
-
bit1
bit0
ILSR
-
-
-
-
bit3
bit2
-
-
PDR2
DDR2
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10.4.2
Operations of Port 2
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.4 Port 2
This section describes the operations of port 2.
■ Operations of Port 2
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register corresponding to the input pin
of a peripheral function to "0".
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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10.4 Port 2
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation as an analog input pin
• Setting the voltage comparator analog input disable bit in the voltage comparator control
register (CMR0:VCID) to "0" enables the analog input function of an analog input pin
regardless of the settings of the PDR register.
• To disable the analog input function of an analog input pin, set the VCID bit in the CMR0
register to "1".
● Operation of the pull-up control register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
● Operation of the input level select register
• Setting bit2 and bit3 in ILSR to "1" changes P22 and P23 respectively from the hysteresis
input level to the CMOS input level. When the same bit is set to "0", the input levels of P22
and P23 become the hysteresis input level.
• For pins other than P22 and P23, the CMOS input level cannot be selected, but only the
hysteresis input level can be selected.
• When changing the input levels of P22 and P23, ensure that all shared peripheral functions
have been stopped.
Table 10.4-4 shows the pin states of port 2.
Table 10.4-4
Pin State of Port 2
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port/peripheral
function I/O
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.5 Port 6
MB95410H/470H Series
10.5
Port 6
Port 6 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 6 Configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
■ Port 6 Pins
Port 6 has eight I/O pins.
Table 10.5-1 lists the port 6 pins.
Table 10.5-1
Port 6 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P60/SEG06 P60: General-purpose I/O SEG06: LCDC SEG06 output
Hysteresis
CMOS/
LCD
-
-
P61/SEG07 P61: General-purpose I/O SEG07: LCDC SEG07 output
Hysteresis
CMOS/
LCD
-
-
P62/SEG08 P62: General-purpose I/O SEG08: LCDC SEG08 output
Hysteresis
CMOS/
LCD
-
-
P63/SEG09 P63: General-purpose I/O SEG09: LCDC SEG09 output
Hysteresis
CMOS/
LCD
-
-
P64/SEG10 P64: General-purpose I/O SEG10: LCDC SEG10 output
Hysteresis
CMOS/
LCD
-
-
P65/SEG11 P65: General-purpose I/O SEG11: LCDC SEG11 output
Hysteresis
CMOS/
LCD
-
-
P66/SEG12 P66: General-purpose I/O SEG12: LCDC SEG12 output
Hysteresis
CMOS/
LCD
-
-
P67/SEG13 P67: General-purpose I/O SEG13: LCDC SEG13 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.5 Port 6
MB95410H/470H Series
■ Block Diagram of Port 6
Figure 10.5-1 Block Diagram of P60, P61, P62, P63, P64, P65, P66 and P67
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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10.5.1
Port 6 Registers
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.5 Port 6
This section describes the registers of port 6.
■ Port 6 Register Functions
Table 10.5-2 lists the port 6 register functions.
Table 10.5-2
Port 6 Register Functions
Register
Data
abbr.
PDR6
DDR6
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.5-3 lists the correspondence between port 6 pins and each register bit.
Table 10.5-3
Correspondence between Registers and Pins for Port 6
Correspondence between related register bits and pins
Pin name
PDR6
DDR6
P67
P66
P65
P64
P63
P62
P61
P60
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.5 Port 6
10.5.2
MB95410H/470H Series
Operations of Port 6
This section describes the operations of port 6.
■ Operations of Port 6
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 3 (LCDCE3:SEG07, SEG06) or in the LCDC enable
register 4 (LCDCE4:SEG13 to SEG08) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 3 (LCDCE3:SEG07, SEG06) or in the LCDC enable
register 4 (LCDCE4:SEG13 to SEG08) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 3 (LCDCE3:SEG07, SEG06) or in the LCDC enable register 4 (LCDCE4:SEG13 to
SEG08) to "1", and then set the port input control bit (PICTL) in the LCDC enable register
1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
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10.5 Port 6
MB95410H/470H Series
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 10.5-4 shows the pin states of port 6.
Table 10.5-4
Pin State of Port 6
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.6 Port 9
10.6
MB95410H/470H Series
Port 9
Port 9 is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port 9 Configuration
Port 9 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 9 data register (PDR9)
• Port 9 direction register (DDR9)
■ Port 9 Pins
Port 9 has four I/O pins.
Table 10.6-1 lists the port 9 pins.
Table 10.6-1
Port 9 Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
P90/V4
P90: General-purpose I/O
V4: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P91/V3
P91: General-purpose I/O
V3: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P92/V2
P92: General-purpose I/O
V2: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
P93/V1
P93: General-purpose I/O
V1: Power supply pin for LCDC
drive
Hysteresis CMOS
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.6 Port 9
■ Block Diagrams of Port 9
Figure 10.6-1 Block Diagram of P90, P91, P92 and P93
LCD power supply
LCD power supply
enable
0
1
PDR read
pin
Internal bus
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.6 Port 9
10.6.1
MB95410H/470H Series
Port 9 Registers
This section describes the registers of port 9.
■ Port 9 Register Functions
Table 10.6-2 lists the port 9 register functions.
Table 10.6-2
Port 9 Register Functions
Register
Data
abbr.
PDR9
DDR9
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.6-3 lists the correspondence between port 9 pins and each register bit.
Table 10.6-3
Correspondence between Registers and Pins for Port 9
Correspondence between related register bits and pins
Pin name
PDR9
DDR9
222
-
-
-
-
P93
P92
P91
P90
-
-
-
-
bit3
bit2
bit1
bit0
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10.6.2
Operations of Port 9
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.6 Port 9
This section describes the operations of port 9.
■ Operations of Port 9
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set the bit (VE4 to VE1)
corresponding to that pin in the LCDC enable register 1 (LCDCE1) to "0".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set the bit (VE4 to VE1)
corresponding to that pin in the LCDC enable register 1 (LCDCE1) to "0".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operations as LCDC pins
• Set the DDR register bit corresponding to a desired LCDC pin to "0".
• Set the V1 select bit (VE1), the V2 select bit (VE2), the V3 select bit (VE3) and the V4
select bit (VE4) in the LCDC enable register 1 (LCDCE1) to "1".
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10.6 Port 9
MB95410H/470H Series
Table 10.6-4 shows the pin states of port 9.
Table 10.6-4
Pin State of Port 9
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.7 Port A
MB95410H/470H Series
10.7
Port A
Port A is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port A Configuration
Port A is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port A data register (PDRA)
• Port A direction register (DDRA)
■ Port A Pins
Port A has eight I/O pins.
Table 10.7-1 lists the port A pins.
Table 10.7-1
Port A Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PA0/COM0 PA0: General-purpose I/O COM0: LCDC COM0 output
Hysteresis
CMOS/
LCD
-
-
PA1/COM1 PA1: General-purpose I/O COM1: LCDC COM1 output
Hysteresis
CMOS/
LCD
-
-
PA2/COM2 PA2: General-purpose I/O COM2: LCDC COM2 output
Hysteresis
CMOS/
LCD
-
-
PA3/COM3 PA3: General-purpose I/O COM3: LCDC COM3 output
Hysteresis
CMOS/
LCD
-
-
PA4/COM4 PA4: General-purpose I/O COM4: LCDC COM4 output
Hysteresis
CMOS/
LCD
-
-
PA5/COM5 PA5: General-purpose I/O COM5: LCDC COM5 output
Hysteresis
CMOS/
LCD
-
-
PA6/COM6 PA6: General-purpose I/O COM6: LCDC COM6 output
Hysteresis
CMOS/
LCD
-
-
PA7/COM7 PA7: General-purpose I/O COM7: LCDC COM7 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.7 Port A
MB95410H/470H Series
■ Block Diagram of Port A
Figure 10.7-1 Block Diagram of PA0, PA1, PA2, PA3, PA4, PA5, PA6 and PA7
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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10.7.1
Port A Registers
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.7 Port A
This section describes the registers of port A.
■ Port A Register Functions
Table 10.7-2 lists the port A register functions.
Table 10.7-2
Port A Register Functions
Register
Data
abbr.
PDRA
DDRA
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.7-3 lists the correspondence between port A pins and each register bit.
Table 10.7-3
Correspondence between Registers and Pins for Port A
Correspondence between related register bits and pins
Pin name
PDRA
DDRA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.7 Port A
10.7.2
MB95410H/470H Series
Operations of Port A
This section describes the operations of port A.
■ Operations of Port A
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding common
select bit (COM7 to COM0) in the LCDC enable register 2 (LCDCE2) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding common
select bit (COM7 to COM0) in the LCDC enable register 2 (LCDCE2) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.7 Port A
MB95410H/470H Series
● Operation as an LCDC common output
• Set the DDR register bit corresponding to a desired LCDC common output pin to "0".
• Select the common output by setting a corresponding common select bit (COM7 to COM0)
in the LCDC enable register 2 (LCDCE2) to "1", and then set the port input control bit
(PICTL) in the LCDC enable register 1 (LCDCE1) to "1".
Table 10.7-4 shows the pin states of port A.
Table 10.7-4
Pin State of Port A
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.8 Port B
10.8
MB95410H/470H Series
Port B
Port B is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port B Configuration
Port B is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port B data register (PDRB)
• Port B direction register (DDRB)
■ Port B Pins
Port B has two I/O pins.
Table 10.8-1 lists the port B pins.
Table 10.8-1
Port B Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PB0/SEG00 PB0: General-purpose I/O SEG00: LCDC SEG00 output
Hysteresis
CMOS/
LCD
-
-
PB1/SEG01 PB1: General-purpose I/O SEG01: LCDC SEG01 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.8 Port B
■ Block Diagram of Port B
Figure 10.8-1 Block Diagram of PB0 and PB1
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.8 Port B
10.8.1
MB95410H/470H Series
Port B Registers
This section describes the registers of port B.
■ Port B Register Functions
Table 10.8-2 lists the port B register functions.
Table 10.8-2
Port B Register Functions
Register
Data
abbr.
PDRB
DDRB
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.8-3 lists the correspondence between port B pins and each register bit.
Table 10.8-3
Correspondence between Registers and Pins for Port B
Correspondence between related register bits and pins
Pin name
PDRB
DDRB
232
-
-
-
-
-
-
PB1
PB0
-
-
-
-
-
-
bit1
bit0
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10.8.2
Operations of Port B
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.8 Port B
This section describes the operations of port B.
■ Operations of Port B
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit (SEG01, SEG00) in the LCDC enable register 3 (LCDCE3) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit (SEG01, SEG00) in the LCDC enable register 3 (LCDCE3) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit (SEG01, SEG00) in
the LCDC enable register 3 (LCDCE3) "1", and then set the port input control bit (PICTL)
in LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.8 Port B
MB95410H/470H Series
Table 10.8-4 shows the pin states of port B.
Table 10.8-4
Pin State of Port B
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
234
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.9 Port C
MB95410H/470H Series
10.9
Port C
Port C is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port C Configuration
Port C is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port C data register (PDRC)
• Port C direction register (DDRC)
■ Port C Pins
Port C has four I/O pins.
Table 10.9-1 lists the port C pins.
Table 10.9-1
Port C Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PC0/SEG02 PC0: General-purpose I/O SEG02: LCDC SEG02 output
Hysteresis
CMOS/
LCD
-
-
PC1/SEG03 PC1: General-purpose I/O SEG03: LCDC SEG03 output
Hysteresis
CMOS/
LCD
-
-
PC2/SEG04 PC2: General-purpose I/O SEG04: LCDC SEG04 output
Hysteresis
CMOS/
LCD
-
-
PC3/SEG05 PC3: General-purpose I/O SEG05: LCDC SEG05 output
Hysteresis
CMOS/
LCD
-
-
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.9 Port C
MB95410H/470H Series
■ Block Diagram of Port C
Figure 10.9-1 Block Diagram of PC0, PC1, PC2 and PC3
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
236
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.9 Port C
MB95410H/470H Series
10.9.1
Port C Registers
This section describes the registers of port C.
■ Port C Register Functions
Table 10.9-2 lists the port C register functions.
Table 10.9-2
Port C Register Functions
Register
Data
abbr.
PDRC
DDRC
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.9-3 lists the correspondence between port C pins and each register bit.
Table 10.9-3
Correspondence between Registers and Pins for Port C
Correspondence between related register bits and pins
Pin name
PDRC
DDRC
-
-
-
-
PC3
PC2
PC1
PC0
-
-
-
-
bit3
bit2
bit1
bit0
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.9 Port C
10.9.2
MB95410H/470H Series
Operations of Port C
This section describes the operations of port C.
■ Operations of Port C
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit (SEG05 to SEG02) in the LCDC enable register 3 (LCDCE3) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit (SEG05 to SEG02) in the LCDC enable register 3 (LCDCE3) to "0" to select the
general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to "1".
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit (SEG05 to SEG02)
in the LCDC enable register 3 (LCDCE3) to "1", and then set the port input control bit
(PICTL) in LCDC enable register 1 (LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.9 Port C
Table 10.9-4 shows the pin states of port C.
Table 10.9-4
Pin State of Port C
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.10 Port E
10.10
MB95410H/470H Series
Port E
Port E is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port E Configuration
Port E is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port E data register (PDRE)
• Port E direction register (DDRE)
■ Port E Pins
Port E has eight I/O pins.
Table 10.10-1 lists the port E pins.
Table 10.10-1 Port E Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PE0/SEG14 PE0: General-purpose I/O SEG14: LCDC SEG14 output
Hysteresis
CMOS/
LCD
-
-
PE1/SEG15 PE1: General-purpose I/O SEG15: LCDC SEG15 output
Hysteresis
CMOS/
LCD
-
-
PE2/SEG16 PE2: General-purpose I/O SEG16: LCDC SEG16 output
Hysteresis
CMOS/
LCD
-
-
PE3/SEG17 PE3: General-purpose I/O SEG17: LCDC SEG17 output
Hysteresis
CMOS/
LCD
-
-
PE4/SEG18 PE4: General-purpose I/O SEG18: LCDC SEG18 output
Hysteresis
CMOS/
LCD
-
-
SEG19: LCDC SEG19 output
PE5/SEG19/
CMOS/
PE5: General-purpose I/O TO11: 8/16-bit composite timer ch. 1 Hysteresis
TO11
LCD
output
-
-
SEG20: LCDC SEG20 output
PE6/SEG20/
CMOS/
PE6: General-purpose I/O TO10: 8/16-bit composite timer ch. 1 Hysteresis
TO10
LCD
output
-
-
SEG21: LCDC SEG21 output
PE7/SEG21/
PE7: General-purpose I/O EC1: 8/16-bit composite timer ch. 1
EC1
clock input
-
-
Hysteresis
CMOS/
LCD
OD: N-ch open drain, PU: Pull-up
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.10 Port E
MB95410H/470H Series
■ Block Diagrams of Port E
Figure 10.10-1 Block Diagram of PE0, PE1, PE2, PE3 and PE4
LCD output
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
Figure 10.10-2 Block Diagram of PE5, PE6 and PE7
LCD output
Peripheral function input
Peripheral function input enable
LCD output enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
Internal bus
PDR
0
PDR write
Executing bit manipulation instruction
Only for PE7
DDR read
DDR
DDR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.10 Port E
10.10.1
MB95410H/470H Series
Port E Registers
This section describes the registers of port E.
■ Port E Register Functions
Table 10.10-2 lists the port E register functions.
Table 10.10-2 Port E Register Functions
Register
Data
abbr.
PDRE
DDRE
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
Table 10.10-3 lists the correspondence between port E pins and each register bit.
Table 10.10-3 Correspondence between Registers and Pins for Port E
Correspondence between related register bits and pins
Pin name
PDRE
DDRE
242
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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10.10.2 Operations of Port E
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.10 Port E
This section describes the operations of port E.
■ Operations of Port E
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
• To use a pin shared with the LCD controller as an output port, set a corresponding segment
select bit in the LCDC enable register 4 (LCDCE4:SEG15, SEG14) or in the LCDC enable
register 5 (LCDCE5:SEG21 to SEG16) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
• To use a pin shared with the LCD controller as an input port, set a corresponding segment
select bit in the LCDC enable register 4 (LCDCE4:SEG15, SEG14) or in the LCDC enable
register 5 (LCDCE5:SEG21 to SEG16) to "0" to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1
(LCDCE1) to "1".
● Operation as a peripheral function output pin
• A pin will become a peripheral function output pin if the peripheral output function is
enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR register even if the peripheral function output is
enabled. Therefore, the output value of a peripheral function can be read by the read
operation on the PDR register. However, if the read-modify-write instruction is used to read
the PDR register, the PDR register value is returned.
● Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR register bit corresponding to the input
pin of a peripheral function to "0".
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.10 Port E
MB95410H/470H Series
• Reading the PDR register returns the pin value, regardless of whether the peripheral
function uses that pin as its input pin. However, if the read-modify-write instruction is used
to read the PDR register, the PDR register value is returned.
● Operation as an LCDC segment output
• Set the DDR register bit corresponding to a desired LCDC segment output pin to "0".
• Select the segment output by setting a corresponding segment select bit in the LCDC enable
register 4 (LCDCE4:SEG15, SEG14) or in the LCDC enable register 5 (LCDCE5:SEG21 to
SEG16) to "1", and then set the port input control bit (PICTL) in LCDC enable register 1
(LCDCE1) to "1".
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Table 10.10-4 shows the pin states of port E.
Table 10.10-4 Pin State of Port E
Operating
state
Pin state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.11 Port F
MB95410H/470H Series
10.11 Port F
Port F is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port F Configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
■ Port F Pins
Port F has three I/O pins.
Table 10.11-1 lists the port F pins.
Table 10.11-1 Port F Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PF0/X0*1
PF0: General-purpose I/O X0: Main clock oscillation pin
Hysteresis CMOS
-
-
PF1/X1*1
PF1: General-purpose I/O X1: Main clock oscillation pin
Hysteresis CMOS
-
-
PF2: General-purpose I/O RST: Reset pin
Hysteresis CMOS ❍
-
PF2/RST
*2
OD: N-ch open drain, PU: Pull-up
*1: If the main oscillation clock is selected (SYSC:PFSEL = 0), the port function cannot be used.
*2: If the external reset is selected (SYSC:RSTEN = 1), the port function cannot be used. This pin is a
dedicated reset pin in MB95F474H/F476H/F478H.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.11 Port F
MB95410H/470H Series
■ Block Diagrams of Port F
Figure 10.11-1 Block Diagram of PF0 and PF1
0
1
PDR read
Internal bus
PDR
pin
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
Figure 10.11-2 Block Diagram of PF2
Reset input
Reset input enable
Reset output enable
Reset output
0
1
PDR read
1
0
Internal bus
PDR
pin
OD
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.11 Port F
MB95410H/470H Series
10.11.1 Port F Registers
This section describes the registers of port F.
■ Port F Register Functions
Table 10.11-2 lists the port F register functions.
Table 10.11-2 Port F Register Functions
Register
Data
abbr.
PDRF
DDRF
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.*
0
Port input enabled
1
Port output enabled
*: For the N-ch open drain pin, this should be Hi-Z.
Table 10.11-3 lists the correspondence between port F pins and each register bit.
Table 10.11-3 Correspondence between Registers and Pins for Port F
Correspondence between related register bits and pins
Pin name
PDRF
DDRF
-
-
-
-
-
PF2*
PF1
PF0
-
-
-
-
-
bit2
bit1
bit0
*: PF2/RST is a dedicated reset pin in MB95F474H/F476H/F478H.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.11 Port F
10.11.2
MB95410H/470H Series
Operations of Port F
This section describes the operations of port F.
■ Operations of Port F
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.11 Port F
Table 10.11-4 shows the pin states of port F.
Table 10.11-4 Pin State of Port F
Operating
state
Pin state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
I/O port
Stop (SPL=1)
Watch (SPL=1)
At reset
Hi-Z
Input cutoff
Hi-Z
Input enabled*1
(Not functional)
Low*2
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*1: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
*2: Only for PF2 at power-on reset.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.12 Port G
10.12
MB95410H/470H Series
Port G
Port G is a general-purpose I/O port.
This section focuses on its functions as a general-purpose I/O port.
For details of peripheral functions, see their respective chapters.
■ Port G Configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
■ Port G Pin
Port G has two I/O pin.
Table 10.12-1 lists the port G pins.
Table 10.12-1 Port G Pins
I/O type
Pin name
Function
Shared peripheral function
Input
Output OD PU
PG1/X0A*
PG1: General-purpose I/O X0A: Subclock oscillation pin
Hysteresis
CMOS
-
❍
PG2/X1A*
PG2: General-purpose I/O X1A: Subclock oscillation pin
Hysteresis
CMOS
-
❍
OD: N-ch open drain, PU: Pull-up
*: If the sub-oscillation clock is selected (SYSC:PGSEL = 0), the port function cannot be used.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.12 Port G
■ Block Diagram of Port G
Figure 10.12-1 Block Diagram of PG1 and PG2
0
Pull-up
1
PDR read
PDR
pin
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.12 Port G
10.12.1
MB95410H/470H Series
Port G Registers
This section describes the registers of port G.
■ Port G Register Functions
Table 10.12-2 lists the port G register functions.
Table 10.12-2 Port G Register Functions
Register
Data
abbr.
PDRG
DDRG
PULG
Read
Read by read-modify-write
instruction
Write
0
Pin state is "L" level.
PDR value is "0".
As output port, outputs "L" level.
1
Pin state is "H" level.
PDR value is "1".
As output port, outputs "H" level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
Table 10.12-3 lists the correspondence between port G pins and each register bit.
Table 10.12-3 Correspondence between Registers and Pins for Port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
-
-
-
-
-
bit2
bit1
-
PDRG
DDRG
PULG
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10.12.2 Operations of Port G
CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.12 Port G
This section describes the operations of port G.
■ Operations of Port G
● Operation as an output port
• A pin will become an output port if the bit in the DDR register corresponding to that pin is
set to "1".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• When a pin is used as an output port, it outputs the value of the PDR register to external
pins.
• If data is written to the PDR register, the value is stored in the output latch and is output to
the pin set as an output port as it is.
• Reading the PDR register returns the PDR value.
● Operation as an input port
• A pin will become an input port if the bit in the DDR register corresponding to that pin is
set to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• If data is written to the PDR register, the value is stored in the output latch but is not output
to the pin set as an input port.
• Reading the PDR register returns the pin value. However, if the read-modify-write
instruction is used to read the PDR register, the PDR register value is returned.
● Operation at reset
If the CPU is reset, all bits in the DDR register are initialized to "0" and port input is enabled.
● Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" when the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDR register value. The input of that pin is locked to "L"
level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
● Operation of the pull-up register
Setting the bit in the PUL register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PUL register.
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CHAPTER 10 I/O PORTS (MB95470H SERIES)
10.12 Port G
MB95410H/470H Series
Table 10.12-4 shows the pin states of port G.
Table 10.12-4 Pin State of Port G
Operating
state
Normal operation
Sleep
Stop (SPL=0)
Watch (SPL=0)
Stop (SPL=1)
Watch (SPL=1)
At reset
Pin state
I/O port
Hi-Z
Input cutoff
Hi-Z
Input enabled*
(Not functional)
SPL: Pin state setting bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled. After a reset, setting the port for internal pullup or as an output pin is recommended.
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CHAPTER 11
TIME-BASE TIMER
This chapter describes the functions and
operations of the time-base timer.
11.1 Overview of Time-base Timer
11.2 Configuration of Time-base Timer
11.3 Register of Time-base Timer
11.4 Interrupts of Time-base Timer
11.5 Operations of Time-base Timer and Setting Procedure
Example
11.6 Notes on Using Time-base Timer
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CHAPTER 11 TIME-BASE TIMER
11.1 Overview of Time-base Timer
11.1
MB95410H/470H Series
Overview of Time-base Timer
The time-base timer is a 24-bit free-run down-counting counter. It is
synchronized with the main clock divided by 2, or with the main PLL clock, or
with the main CR clock. The clock can be selected by the RCS[1:0] bits in the
SYCC2 register and the PCS1 bit and PCS0 bit in the PLLC register. The timebase timer has an interval timer function that can repeatedly generate interrupt
requests at regular intervals.
■ Interval Timer Function
The interval timer function repeatedly generates interrupt requests at regular intervals by using
the main clock divided by 2, or the main PLL clock, or the main CR clock as the count clock.
• The counter of the time-base timer counts down so that an interrupt request is generated
whenever a selected interval time elapses.
• The length of an interval time can be selected from the following 16 values.
Table 11.1-1 shows the interval times available for the time-base timer.
Table 11.1-1 Interval Times of Time-base Timer
Interval time if the main CR clock is used
(2n × 1/FCRH*1)
Interval time if the main clock is used
(2n × 2/FCH*2, *3)
n=9
64 μs
256 μs
n=10
128 μs
512 μs
n=11
256 μs
1.024 ms
n=12
512 ms
2.048 ms
n=13
1.024 ms
4.096 ms
n=14
2.048 ms
8.192 ms
n=15
4.096 ms
16.384 ms
n=16
8.192 ms
32.768 ms
n=17
16.384 ms
65.536 ms
n=18
32.768 ms
131.072 ms
n=19
65.536 ms
262.144 ms
n=20
131.072 ms
524.288 ms
n=21
262.144 ms
1.049 s
n=22
524.288 ms
2.097 s
n=23
1.049 s
4.194 s
n=24
2.097 s
8.389 s
*1: 1/FCRH = 0.125 μs when FCRH = 8 MHz
*2: 2/FCH = 0.5 μs when FCH = 4 MHz
*3: When PLLC:PCS[1:0] = 00, the main clock divided by 2 (FCH/2) is used as the count clock; when PLLC:PCS[1:0] = 01,
10 or 11, the main PLL clock is used as the count clock.
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CHAPTER 11 TIME-BASE TIMER
11.2 Configuration of Time-base Timer
MB95410H/470H Series
11.2
Configuration of Time-base Timer
The time-base timer consists of the following blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of Time-base Timer
Figure 11.2-1 Block Diagram of Time-base Timer
Time-base timer counter
FCH divided by 2 or
main PLL clock
To prescaler
To software watchdog timer
×21 ×22 ×23 ×24 ×25 ×26 ×27 ×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218 ×219 ×220 ×221 ×222 ×223
FCRH
RCM1
RCM0
RCS1
RCS0 SOSCE MOSCE SCRE
System clock control register 2 (SYCC2)
MCRE
Counter clear
Software watchdog timer clear
Counter
clear circuit
Resets
Stops main clock oscillation or main CR clock oscillation
Interval timer
selector
Time-base timer interrupt
TBIF
TBIE
-
TBC3
TBC2
TBC1
TBC0
TCLR
Time-base timer control register (TBTC)
FCH : Main clock
FCRH : Main CR clock
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CHAPTER 11 TIME-BASE TIMER
11.2 Configuration of Time-base Timer
MB95410H/470H Series
● Time-base timer counter
This is a 24-bit down-counter using the main clock divided by 2 or the main PLL clock or the
main CR clock as its count clock.
● Counter clear circuit
This circuit controls the clearing of the time-base timer counter.
● Interval timer selector
This circuit selects one bit out of 16 bits in the 24 bits of the time-base timer counter as the
interval timer.
● Time-base timer control register (TBTC)
This register selects the interval time, clears the counter, controls interrupts and checks the
status of the time-base timer.
■ Input Clock
The time-base timer uses the main clock divided by two or the main CR clock as its input clock
(count clock).
■ Output Clock
The time-base timer supplies clocks to the main clock, the software watchdog timer and the
prescaler.
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CHAPTER 11 TIME-BASE TIMER
11.3 Register of Time-base Timer
MB95410H/470H Series
11.3
Register of Time-base Timer
Figure 11.3-1 shows the register of the time-base timer.
■ Register of Time-base Timer
Figure 11.3-1 Register of Time-base Timer
Time-base timer control (TBTC)
Address
bit7
bit6
000AH
TBIF
TBIE
R(RM1),W
R/W
R/W
R(RM1),W
R0,W
R0/WX
-
bit5
R0/WX
bit4
TBC3
R/W
bit3
TBC2
R/W
bit2
TBC1
R/W
bit1
TBC0
R/W
bit0
TCLR
R0,W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the readmodify-write (RMW) type of instruction.)
: Write only (Writable. The read value is "0".
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 11 TIME-BASE TIMER
11.3 Register of Time-base Timer
MB95410H/470H Series
Time-base Timer Control Register (TBTC)
11.3.1
The time-base timer control register (TBTC) selects the interval time, clears the
counter, controls interrupts and checks the status of the time-base timer.
■ Time-base Timer Control Register (TBTC)
Figure 11.3-2 Time-base Timer Control Register (TBTC)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000AH
TBIF
TBIE
-
TBC3
TBC2
TBC1
TBC0
TCLR
00000000B
R(RM1),W
R/W
R0/WX
R/W
R/W
R/W
R/W
R0,W
Time-base timer initialization bit
Read
Write
TCLR
0
"0" is always read.
1
-
TBC3 TBC2 TBC1 TBC0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Has no effect on operation.
Clears all counter bits of the
time-base timer to "1".
Interval time*
(Main clock FCH = 4 MHZ)
29 × 2/FCH (256 μs)
210 × 2/FCH (512 μs)
211 × 2/FCH (1.024 ms)
212 × 2/FCH (2.048 ms)
213 × 2/FCH (4.096 ms)
214 × 2/FCH (8.192 ms)
215 × 2/FCH (16.384 ms)
216 × 2/FCH (32.768 ms)
217 × 2/FCH (65.536 ms)
218 × 2/FCH (131.072 ms)
219 × 2/FCH (262.144 ms)
220 × 2/FCH (524.288 ms)
221 × 2/FCH (1.049 s)
222 × 2/FCH (2.197 s)
223 × 2/FCH (4.194 s)
224 × 2/FCH (8.389 s)
Interval time
(Main CR clock FCRH = 8 MHZ)
29 × 1/FCRH (64 μs)
210 × 1/FCRH (128 μs)
211 × 1/FCRH (256 μs)
212 × 1/FCRH (512 μs)
213 × 1/FCRH (1.024 ms)
214 × 1/FCRH (2.048 ms)
215 × 1/FCRH (4.096 ms)
216 × 1/FCRH (8.192 ms)
217 × 1/FCRH (16.384 ms)
218 × 1/FCRH (32.768 ms)
219 × 1/FCRH (65.536 ms)
220 × 1/FCRH (131.072 ms)
221 × 1/FCRH (262.144 ms)
222 × 1/FCRH (524.288 ms)
223 × 1/FCRH (1.049 s)
224 × 1/FCRH (2.097 s)
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
TBIE
Time-base timer interrupt request enable bit
Disables output of interrupt request
0
Enables output of interrupt request
1
TBIF
Time-base timer interrupt request enable bit
Read
Write
0
Interval time has not elapsed
Clears the bit
1
Interval time has elapsed
Has no effect on operation
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R0,W
R0/WX
-
:
:
:
:
Write only (Writable. The read value is “0”.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
* : When the PLLC:PCS[1:0] bits are set to “00”, the main clock divided by 2 (FCH/2) is used as the count clock.
When the PLLC:PCS[1:0] bits are set to “01”, “10” or “11”, the main PLL clock is used as the count clock.
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CHAPTER 11 TIME-BASE TIMER
11.3 Register of Time-base Timer
MB95410H/470H Series
Table 11.3-1 Functions of Bits in Time-base Timer Control Register (TBTC)
Bit name
Function
This flag is set to "1" when the interval time selected by the time-base timer elapses.
An interrupt request is output if this bit and the time-base timer interrupt request enable bit
(TBIE) are set to "1".
Writing "0": Clears this bit to "0".
Writing "1": Has no effect on operation.
If this bit is read by the read-modify-write (RMW) type of instruction, it always returns "1".
bit7
TBIF:
Time-base timer
interrupt request flag
bit
bit6
This bit enables or disables output of interrupt requests to interrupt controller.
TBIE:
Writing "0": Disables the output of time-base timer interrupt requests.
Time-base timer
Writing "1": Enables the output of time-base timer interrupt requests.
interrupt request enable
An interrupt request is output if this bit and the time-base timer interrupt request flag bit
bit
(TBIF) are set to "1".
bit5
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
These bits select interval time.
TBC3 TBC2 TBC1 TBC0
bit4
to
bit1
TBC3 to TBC0:
Interval time select bits
Interval time*
(Main clock FCH = 4 MHz)
Interval time
(Main CR clock FCRH = 8 MHz)
0
1
0
0
29 × 2/FCH (256 μs)
29 × 1/FCRH (64 μs)
0
0
0
0
210 × 2/FCH (512 μs)
210 × 1/FCRH (128 μs)
0
1
0
1
211 × 2/FCH (1.024 ms)
211 × 1/FCRH (256 μs)
0
0
0
1
212 × 2/FCH (2.048 ms)
212 × 1/FCRH (512 μs)
0
1
1
0
213 × 2/FCH (4.096 ms)
213 × 1/FCRH (1.024 ms)
0
0
1
0
214× 2/FCH (8.192 ms)
214 × 1/FCRH (2.048 ms)
15
0
1
1
1
2 × 2/FCH (16.384 ms)
215 × 1/FCRH (4.096 ms)
0
0
1
1
216 × 2/FCH (32.768 ms)
216× 1/FCRH (8.192 ms)
1
0
0
0
217 × 2/FCH (65.536 ms)
217 × 1/FCRH (16.384 ms)
1
0
0
1
218 × 2/FCH (131.072 ms)
218 × 1/FCRH (32.768 ms)
1
0
1
0
219 × 2/FCH (262.144 ms)
219 × 1/FCRH (65.536 ms)
1
0
1
1
220 × 2/FCH (524.288 ms)
220 × 1/FCRH (131.072 ms)
1
1
0
0
221 × 2/FCH (1.049 s)
221 × 1/FCRH (262.144 ms)
1
1
0
1
222 × 2/FCH (2.097 s)
222 × 1/FCRH (524.288 ms)
1
1
1
0
223 × 2/FCH (4.194 s)
223 × 1/FCRH (1.049 s)
1
1
1
1
224 × 2/FCH (8.389 s)
224 × 1/FCRH (2.097 s)
*: When the PLLC:PCS[1:0] bits are set to "00", the main clock divided by 2 (FCH/2) is
used as the count clock.
When the PLLC:PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used
as the count clock.
bit0
TCLR:
Time-base timer
initialization bit
MN702-00005-2v0-E
This bit clears all counter bits of the time-base timer to "1".
Writing "0": Has no effect on the operation.
Writing "1": Initializes all counter bits to "1".
When this bit is read, it always returns "0".
Note:
When the output of the time-base timer is selected as the count clock for the
watchdog timer, using this bit to clear the time-base timer also clears the software
watchdog timer.
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CHAPTER 11 TIME-BASE TIMER
11.4 Interrupts of Time-base Timer
11.4
MB95410H/470H Series
Interrupts of Time-base Timer
An interrupt request is generated when the interval time selected by the timebase timer elapses (interval timer function).
■ Interrupts when Interval Function is in Operation
When the time-base timer counter counts down by using the internal count clock and the
selected time-base timer counter underflows, the time-base timer interrupt request flag bit
(TBTC:TBIF) is set to "1". With the TBIF bit set to "1", if the time-base timer interrupt request
enable bit is also enabled (TBTC:TBIE = 1), an interrupt request (IRQ19) will be generated to
the interrupt controller.
• Regardless of the value of the TBIE bit, the TBIF bit is set to "1" when the selected bit
underflows.
• With the TBIF bit set to "1", if the TBIE bit is changed from the disable state to the enable
state (0 → 1), an interrupt request is generated immediately.
• The TBIF bit will not be set to "1" if the clearing of a counter (TBTC:TCLR = 1) and the
underflow of the time-base timer counter occur simultaneously.
• In the interrupt service routine, write "0" to the TBIF bit to clear an interrupt request.
Note:
When enabling the output of interrupt requests after canceling a reset (TBTC:TBIE = 1),
always clear the TBIF bit at the same time (TBTC:TBIF = 0).
Table 11.4-1 Interrupts of Time-base Timer
Item
Description
Interrupt condition
The interval time set by "TBTC:TBC3-TBC0" has elapsed.
Interrupt flag
TBTC:TBIF
Interrupt enable
TBTC:TBIE
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CHAPTER 11 TIME-BASE TIMER
11.4 Interrupts of Time-base Timer
MB95410H/470H Series
■ Register and Vector Table Addresses for Interrupts of Time-base Timer
Table 11.4-2 Register and Vector Table Addresses for Interrupts of Time-base Timer
Interrupt source
Time-base timer
Interrupt
request no.
IRQ19
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
ILR4
L19
FFD4H
FFD5H
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 11 TIME-BASE TIMER
11.5 Operations of Time-base Timer and Setting
Procedure Example
11.5
MB95410H/470H Series
Operations of Time-base Timer and Setting
Procedure Example
This section describes the operations of the interval timer function of the timebase timer.
■ Operations of Time-base Timer
The counter of the time-base timer is initialized to "FFFFFFH" after a reset and starts counting
while being synchronized with the main clock divided by two.
The time-base timer continues to count down as long as the main clock is oscillating. Once the
main clock halts, the counter stops counting and is initialized to "FFFFFFH".
The settings shown in Figure 11.5-1 are required to use the interval timer function.
Figure 11.5-1 Settings of Interval Timer Function
Address
000AH
TBTC
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TBIF
TBIE
-
TBC3
TBC2
TBC1
TBC0
TCLR
0
1
0
: Bit to be used
1 : Set to "1"
0 : Set to "0"
When the time-base timer initialization bit in the time-base timer control register
(TBTC:TCLR) is set to "1", the counter of the time-base timer is initialized to "FFFFFFH" and
continues to count down. When the selected interval time has elapsed, the time-base timer
interrupt request flag bit of the time-base timer control register (TBTC:TBIF) becomes "1". In
other words, an interrupt request is generated at each interval time selected, based on the time
when the counter was last cleared.
■ Clearing Time-base Timer
If the time-base timer is cleared when the output of the time-base timer is used in other
peripheral functions, this will affect the operation by changing the count time or in other
manners.
When clearing the counter by using the time-base timer initialization bit (TBTC:TCLR),
modify the settings of other peripheral functions whenever necessary so that clearing the
counter does not have any unexpected effect on them.
When the output of the time-base timer is selected as the count clock for the watchdog timer,
clearing the time-base timer also clears the watchdog timer.
The time-base timer is cleared not only by the time-base timer initialization bit (TBTC:TCLR),
but also when the main clock is stopped and the oscillation stabilization wait time is necessary.
The time-base timer is cleared in the following situations:
• When the device transits from the main clock mode or main CR clock mode to the stop
mode
• When the device transits from the main clock mode or main CR clock mode to the subclock
mode or sub-CR clock mode
• At power on
• At low-voltage detection reset
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CHAPTER 11 TIME-BASE TIMER
11.5 Operations of Time-base Timer and Setting
Procedure Example
MB95410H/470H Series
■ Operation Examples of Time-base Timer
Figure 11.5-2 shows examples of operations under the following conditions:
1) When a power-on reset is generated
2) When the device enters the sleep mode during the operation of the interval timer function in
the main clock mode or main CR clock mode
3) When the device enters the stop mode during the main clock mode or main CR clock mode
4) When a request is generated to clear the counter
If the device transits to the time-base time mode, the same operations are executed as those
executed when the device transits to the sleep mode.
In stop mode in which the clock mode is subclock mode, sub-CR clock mode, main clock
mode or main CR clock mode, the timer operation stops because it is cleared and the main
clock stops.
Figure 11.5-2 Operations of Time-base Timer
Counter value
(count down)
FFFFFFH
Count value detected in
WATR:MWT3 to MWT0
Count value detected in
TBTC:TBC3 to TBC0
Interval cycle
(TBTC:TBC3 to TBC0=0011B)
Cleared by
transition
to stop mode
000000H
Oscillation
stabilization wait time
Oscillation
stabilization wait time
4) Counter cleared
(TBTC:TCLR=1)
1) Power-on reset
Cleared at
interval setting
Cleared in interrupt
service routine
TBIF bit
TBIE bit
Sleep
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
Stop
Sleep mode released by
time-base timer interrupt
Stop mode released by external interrupt
• When setting the interval time select bits in time-base timer control register (TBTC:TBC3 to TBC0) to "0011B" (216 × 2/FCH)
•
•
•
•
•
•
•
TBTC:TBC3 to TBC0
TBTC:TCLR
TBTC:TBIF
TBTC:TBIE
STBC:SLP
STBC:STP
WATR:MWT3 to MWT0
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: Interval time select bits in time-base timer control register
: Time-base timer initialization bit in time-base timer control register
: Time-base timer interrupt request flag bit in time-base timer control register
: Time-base timer interrupt request enable bit in time-base timer control register
: Sleep bit in standby control register
: Stop bit in standby control register
: Main clcok oscillation stabilization wait time select bits in oscillation stabilization wait time setting register
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CHAPTER 11 TIME-BASE TIMER
11.5 Operations of Time-base Timer and Setting
Procedure Example
MB95410H/470H Series
■ Setting Procedure Example
Below is an example of procedure for setting the time-base timer.
● Initial settings
1) Disable interrupts.
(TBTC:TBIE = 0)
2) Set the interval time.
(TBTC:TBC3 to TBC0)
3) Enable interrupts.
(TBTC:TBIE = 1)
4) Clear the counter.
(TBTC:TCLR = 1)
● Processing interrupts
266
1) Clear the interrupt request flag.
(TBTC:TBIF = 0)
2) Clear the counter.
(TBTC:TCLR = 1)
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CHAPTER 11 TIME-BASE TIMER
11.6 Notes on Using Time-base Timer
MB95410H/470H Series
11.6
Notes on Using Time-base Timer
This section provides notes on using the time-base timer.
■ Notes on Using Time-base Timer
● When setting the timer by program
The timer cannot be waken up from interrupt processing when the time-base timer interrupt
request flag bit (TBTC:TBIF) is set to "1" and the interrupt request enable bit is enabled
(TBTC:TBIE = 1). Always clear the TBIF bit in the interrupt service routine.
● Clearing Time-base Timer
The time-base timer is cleared not only by the time-base timer initialization bit (TBTC:TCLR =
1) but also when the oscillation stabilization wait time of the main clock is required. When the
time-base timer is selected as the count clock of the software watchdog timer (WDTC:CS1,
CS0 = 00B or 01B), clearing the time-base timer also clears the software watchdog timer.
● Peripheral functions receiving clock from time-base timer
In the mode where the source oscillation of the main clock is stopped, the counter is cleared
and the time-base timer stops operating. In addition, if the counter of the time-base timer is
cleared with the output of the time-base timer being used in other peripheral functions, that will
affect the operations of such peripheral operations such as the changing of their operating
cycles.
After the counter of the time-base timer is cleared, the clock that is output from the time-base
timer for the software watchdog timer returns to the initial state. However, since the software
watchdog timer counter is also cleared at the same time as the clock for the software watchdog
timer returns to the initial state, the software watchdog timer operates in its normal cycle.
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CHAPTER 11 TIME-BASE TIMER
11.6 Notes on Using Time-base Timer
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CHAPTER 12
HARDWARE/SOFTWARE
WATCHDOG TIMER
This chapter describes the functions and
operations of the watchdog timer.
12.1 Overview of Watchdog Timer
12.2 Configuration of Watchdog Timer
12.3 Register of Watchdog Timer
12.4 Operations of Watchdog Timer and Setting Procedure
Example
12.5 Notes on Using Watchdog Timer
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.1 Overview of Watchdog Timer
MB95410H/470H Series
12.1
Overview of Watchdog Timer
The watchdog timer serves as a counter used to prevent programs from
running out of control.
■ Watchdog Timer Function
The watchdog timer functions as a counter used to prevent programs from running out of
control. Once the watchdog timer is activated, its counter needs to be cleared at specified
intervals regularly. A watchdog reset is generated if the timer is not cleared within a certain
amount of time due to a problem such as a program entering an infinite loop.
● Count clock for the software/hardware watchdog timer
• For the software watchdog timer, the output of the time-base timer or of the watch prescaler
or of the sub-CR timer can be used as the count clock.
• For the hardware watchdog timer, only the output of the sub-CR timer can be used as the
count clock.
● Activation of the software/hardware watchdog timer
• The software/hardware watchdog timer is to be activated according to the values at the
addresses FFBEH and FFBFH on the Flash memory, which are copied to the watchdog timer
selection ID registers WDTH/WDTL (0FEBH/0FECH).
• In the case of software activation (software watchdog), the watchdog timer register
(WDTC) must be set to start the watchdog timer function.
• In the case of hardware activation (hardware watchdog), the watchdog timer starts
automatically after a reset. It can also stop or run in stop mode according to the values at the
addresses FFBEH and FFBFH on the Flash memory, which are copied to the watchdog timer
selection ID registers WDTH/WDTL (0FEBH/0FECH). See "CHAPTER 32 NONVOLATILE REGISTER (NVR) FUNCTION" for details of the watchdog timer selection
ID.
• The intervals of the watchdog timer are shown in Table 12.1-1. If the counter of the
watchdog timer is not cleared, a watchdog reset is generated between the minimum time
and the maximum time. Clear the counter of the watchdog timer within the minimum time.
Table 12.1-1 Interval Times of Watchdog Timer
Count clock type
Time-base timer output
(main clock = 4 MHz)
Watch prescaler output
(subclock = 32.768 kHz)
Sub-CR timer
(sub-CR clock = 50 kHz to 200 kHz)
Interval time
Count clock switch bits
CS[1:0], CSP
Minimum time
Maximum time
000B (SWWDT)
524 ms
1.05 s
010B (SWWDT)
262 ms
524 ms
100B (SWWDT)
500 ms
1.00 s
110B (SWWDT)
250 ms
500 ms
328 ms
2.62 s
XX1B (SWWDT) or
HWWDT*1
*1: CS[1:0] = 00B, CSP = 1 (read only)
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.2 Configuration of Watchdog Timer
MB95410H/470H Series
12.2
Configuration of Watchdog Timer
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter
• Reset control circuit
• Watchdog timer clear selector
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 12.2-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
CS1 CS0 CSP HWWDT WTE3 WTE2 WTE1 WTE0
Watchdog timer
221/FCH*, 220/FCH*
(Time-base timer output)
214/FCL, 213/FCL
(Watch prescaler output)
Count clock
selector
Clear Activate
16
2 /FCRL
(Sub-CR timer)
Watchdog
timer counter
Clear signal from
time-base timer
Watchdog timer
clear selector
Reset
control
circuit
Reset
signal
Overflow
Clear signal from
watch prescaler
Sleep mode starts
Stop mode starts
Time-base timer/watch mode starts
Stopping or running in stop mode
Counter clear
control circuit
FCH : Main clock
FCL : Subclock
FCRL : Sub-CR clock
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.2 Configuration of Watchdog Timer
MB95410H/470H Series
● Count clock selector
This selector selects the count clock of the watchdog timer counter.
● Watchdog timer counter
This is a 1-bit counter that uses the output of the time-base timer or of the watch prescaler or of
the sub-CR timer as the count clock.
● Reset control circuit
This circuit generates a reset signal when the watchdog timer counter overflows.
● Watchdog timer clear selector
This selector selects the watchdog timer clear signal.
● Counter clear control circuit
This circuit controls the clearing and stopping of the watchdog timer counter.
● Watchdog timer control register (WDTC)
This register performs setup for activating/clearing the watchdog timer counter as well as for
selecting the count clock.
■ Input Clock
The watchdog timer uses the output clock of the time-base timer or of the watch prescaler or of
the sub-CR timer as the input clock (count clock).
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.3 Register of Watchdog Timer
MB95410H/470H Series
12.3
Register of Watchdog Timer
Figure 12.3-1 shows the register of the watchdog timer.
■ Register of Watchdog Timer
Figure 12.3-1 Register of Watchdog Timer
Watchdog timer control register (WDTC)
Address
000CH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CS1
CS0
CSP
HWWDT
WTE3
WTE2
WTE1
WTE0
Software
R/W
R/W
R/W
R0/WX
R0,W
R0,W
R0,W
R0,W
00000000B
Hardware
R0/WX
R0/WX
R1/WX
R1/WX
R0,W
R0,W
R0,W
R0,W
00110000B
R/W
R0/WX
R1/WX
R0,W
:
:
:
:
Initial value
Readable/writable (The read value is the same as the write value.)
The read value is "0". Writing a value to it has no effect on operation.
The read value is "1". Writing a value to it has no effect on operation.
Write only (Writable. The read value is "0".)
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.3 Register of Watchdog Timer
12.3.1
MB95410H/470H Series
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates or clears the watchdog
timer.
■ Watchdog Timer Control Register (WDTC)
Figure 12.3-2 Watchdog Timer Control Register (WDTC)
bit6
bit5
Address bit7
bit4
bit3
000CH
CS0
CSP HWWDT WTE3
CS1
Software R/W
R/W
R/W R0/WX R0,W
Hardware R0/WX R0/WX R1/WX R1/WX R0,W
bit2
WTE2
R0,W
R0,W
WTE3 WTE2 WTE1 WTE0
0
1
0
1
bit1
WTE1
R0,W
R0,W
bit0
WTE0
R0,W
R0,W
Initial value
00000000B
00110000B
Watchdog control bits
• Activates software watchdog timer
(at the first write access after a reset)
• Clears watchdog timer
Software: from the second write access after a reset
Hardware: from the first write access after a reset
Other than above
HWWDT
R/W
R0,W
R0/WX
R1/WX
X
FCH
FCL
FCRL
:
:
:
:
:
:
:
:
:
No effect on operation
Hardware watchdog timer activation bit
1
Hardware watchdog timer is activated
0
Hardware watchdog timer stops
(software watchdog timer can be activated)
CS1
0
0
1
1
CS0
0
1
0
1
CSP
0
0
0
0
X
X
1
Count clock switch bits
Output cycle of time-base timer (221/*FCH*)
Output cycle of time-base timer (220/FCH*)
Output cycle of watch prescaler (214/FCL)
Output cycle of watch prescaler (213/FCL)
Output cycle of sub-CR timer (216/FCRL)
Readable/writable (The read value is the same as the write value.)
Write only (Writable. The read value is “0”.)
The read value is “0”. Writing a value to it has no effect on operation.
The read value is “1”. Writing a value to it has no effect on operation.
Don’t care
Initial value for the software watchdog timer
Main clock
Subclock
Sub-CR clock
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.3 Register of Watchdog Timer
MB95410H/470H Series
Table 12.3-1 Functions of Bits in Watchdog Timer Control Register (WDTC)
Bit name
bit7,
bit6
bit5
Function
CS1, CS0:
These bits select the count clock of the watchdog timer.
Count clock switch bits
CS1
CS0
CSP
Count clock switch bits
0
0
0
Output cycle of time-base timer (221/FCH*)
0
1
0
Output cycle of time-base timer (220/FCH*)
1
0
0
Output cycle of watch prescaler (214/FCL)
1
1
0
Output cycle of watch prescaler (213/FCL)
CSP:
X
X
1
Output cycle of sub-CR timer (216/FCRL)
Count clock select subCR selector bit
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by
two is used. When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is
used.
• Write to these bits at the same time as activating the watchdog timer by the watchdog
control bits.
• No change can be made once the watchdog timer is activated.
Note:
Since the time-base timer in stopped in subclock mode, always select the output of
the watch prescaler in subclock mode.
The bit is a read-only bit, used to confirm the start/stop of the hardware watchdog timer.
"1": The hardware watchdog timer has been activated.
"0": The hardware watchdog timer has stopped (The software watchdog timer can be
activated).
bit4
HWWDT:
Hardware watchdog
activation bit
bit3
to
bit0
These bits are used to control the watchdog timer.
WTE3, WTE2, WTE1, Writing "0101B":Activates the watchdog timer (in first write after reset) or clears it (from
second write after reset).
WTE0:
Watchdog control bits Writing other than "0101B": Has no effect on operation.
• When these bits are read, they always return "0000B".
Note:
Using the read-modify-write (RMW) type of instruction to access the WDTC register is
prohibited.
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.4 Operations of Watchdog Timer and Setting
Procedure Example
12.4
MB95410H/470H Series
Operations of Watchdog Timer and Setting
Procedure Example
The watchdog timer generates a watchdog reset when the watchdog timer
counter overflows.
■ Operations of Watchdog Timer
● How to activate the watchdog timer
To activate the software watchdog timer
• The watchdog timer is activated when "0101B" is written to the watchdog control bits of the
watchdog timer control register (WDTC:WTE3 to WTE0) for the first time after a reset.
The count clock switch bits of the watchdog timer control register (WDTC:CS1,CS0,CSP)
should also be set at the same time.
• Once the watchdog timer is activated, a reset is the only way to stop its operation.
To activate the hardware watchdog timer
• To activate the hardware watchdog timer, write any value except "A596H" to the addresses
FFBEH and FFBFH on the Flash memory. After a reset, the data in FFBEH and FFBFH on
the Flash memory are copied to the watchdog timer selection ID registers WDTH/WDTL
(0FEBH /0FECH). Writing "A597H" to the addresses FFBEH and FFBFH on the Flash
memory enables the hardware watchdog timer except in one of the standby modes; writing
any value other than "A596H" and "A597H" enables the hardware watchdog timer in all
modes. See "CHAPTER 32 NON-VOLATILE REGISTER (NVR) FUNCTION" for details
of the watchdog timer selection ID.
• Start operation after a reset.
• CS1, CS0, CSP bits are read-only bits, fixed at "001B".
• The timer is cleared by a reset and resumes operation after the reset is released.
● Clearing the watchdog timer
• When the counter of the watchdog timer is not cleared within the interval time, it overflows,
allowing the watchdog timer to generate a watchdog reset.
• The counter of the hardware watchdog timer is cleared when "0101B" is written to the
watchdog control bits of the watchdog timer control register (WDTC:WTE3 to WTE0). The
counter of the software watchdog timer is cleared when "0101B" is written to the watchdog
control bits of the watchdog timer control register (WDTC:WTE3 to WTE0) for the second
time and from the second time onward.
• The watchdog timer is cleared at the same time as the timer selected as the count clock
(time-base timer or watch prescaler) is cleared.
● Operation in standby mode
Regardless of the clock mode selected, the watchdog timer clears its counter and stops the
operation when transiting to standby mode (sleep/stop/time-base timer/watch), except in the
case of selecting the hardware activation with the hardware watchdog timer running in standby
mode.
Once released from standby mode, the timer restarts the operation, except in the case of
selecting the hardware activation with the hardware watchdog timer running in standby mode.
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.4 Operations of Watchdog Timer and Setting
Procedure Example
MB95410H/470H Series
Note:
The watchdog timer is also cleared when the timer selected as the count clock (timebase timer or watch prescaler) is cleared. For this reason, the watchdog timer cannot
function if the software is set to repeatedly clear the timer selected as the count clock
of the watchdog timer at the interval time selected for the watchdog timer.
● Interval time
The interval time varies depending on the timing of clearing the watchdog timer. Figure 12.4-1
shows the relation between the timing of clearing timing the watchdog timer and the interval
time when the time-base timer output 221/FCH (FCH: main clock) is selected as the count clock
(main clock = 4 MHz).
Figure 12.4-1 Clearing Timing and Interval Time of Watchdog Timer
524 ms
Minimum time
Time-base timer
count clock output
Watchdog cleared
Overflow
Watchdog 1-bit
counter
Watchdog reset
Maximum time
1.05 s
Time-base timer
count clock output
Watchdog cleared
Overflow
Watchdog 1-bit
counter
Watchdog reset
● Operation in subclock mode
When a watchdog reset is generated in subclock mode, the timer starts operating in main clock
mode after the oscillation stabilization wait time has elapsed. The reset signal is output during
this oscillation stabilization wait time.
■ Setting Procedure Example
Below is an example of procedure for setting the software watchdog timer.
1) Select the count clock.
(WDTC:CS1, CS0, CSP)
2) Activate the watchdog timer.
(WDTC:WTE3 to WTE0 = 0101B)
3) Clear the watchdog timer.
(WDTC:WTE3 to WTE0 = 0101B)
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.4 Operations of Watchdog Timer and Setting
Procedure Example
MB95410H/470H Series
Below is the procedure for setting the hardware watchdog timer.
1) Write any value except "A596H" to the addresses FFBEH and FFBFH on the Flash memory.
After a reset, the data in FFBEH and FFBFH on the Flash memory are copied to the
watchdog timer selection ID registers WDTH/WDTL (0FEBH /0FECH). Writing "A597H"
to the addresses FFBEH and FFBFH on the Flash memory enables the hardware watchdog
timer except in one of the standby modes; writing any value other than "A596H" and
"A597H" enables the hardware watchdog timer in all modes. See "CHAPTER 32 NONVOLATILE REGISTER (NVR) FUNCTION" for details of the watchdog timer selection
ID.
2) Clear the watchdog timer.
278
(WDTC:WTE3 to WTE0 = 0101B)
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.5 Notes on Using Watchdog Timer
MB95410H/470H Series
12.5
Notes on Using Watchdog Timer
This section provides notes on using the watchdog timer.
■ Notes on Using Watchdog Timer
● Stopping the watchdog timer
Software watchdog timer
Once activated, the watchdog timer cannot be stopped until a reset is generated.
● Selecting the count clock
Software watchdog timer
The count clock switch bits (WDTC:CS1, CS0, CSP) can be modified only when the watchdog
control bits (WDTC:WTE3 to WTE0) are set to "0101B" after the activation of the watchdog
timer. The count clock switch bits cannot be set by a bit manipulation instruction. Moreover,
the bit settings should not be changed once the timer is activated.
In subclock mode, the time-base timer does not operate because the main clock stops
oscillating.
In order to make the watchdog timer operate in subclock mode, it is necessary to select the
watch prescaler as the count clock beforehand and set WDTC:CS1,CS0,CSP to "100B" or
"110B" or "XX1B".
● Clearing the watchdog timer
Clearing the counter used as the count clock of the watchdog timer (time-base timer or watch
prescaler or sub-CR timer) also clears the counter of the watchdog timer.
The counter of the watchdog timer is cleared when the watchdog timer transits to the sleep
mode, stop mode or watch mode, except in the case of selecting the hardware activation with
the hardware watchdog timer running in standby mode.
● Programming precaution
When creating a program in which the watchdog timer is cleared repeatedly in the main loop,
set the processing time of the main loop including the interrupt processing time to the
minimum watchdog timer interval time or shorter.
● Hardware watchdog timer (with timer running in standby mode)
The watchdog timer does not stop in stop mode, sleep mode, time-base timer mode or watch
mode. Therefore, the watchdog timer is not to be cleared by the CPU even if the internal clock
stops. (in stop mode, sleep mode, time-base timer mode or watch mode).
Regularly release the device from standby mode and clear the watchdog timer. However,
depending on the setting of the oscillation stabilization wait time setting register, a watchdog
reset may be generated after the CPU wakes up from stop mode in subclock mode or sub-CR
clock mode.
Take account of the setting of the subclock stabilization wait time when selecting the subclock.
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CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER
12.5 Notes on Using Watchdog Timer
MB95410H/470H Series
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CHAPTER 13
WATCH PRESCALER
This chapter describes the functions and
operations of the watch prescaler.
13.1 Overview of Watch Prescaler
13.2 Configuration of Watch Prescaler
13.3 Register of Watch Prescaler
13.4 Interrupts of Watch Prescaler
13.5 Operations of Watch Prescaler and Setting Procedure
Example
13.6 Notes on Using Watch Prescaler
13.7 Sample Settings for Watch Prescaler
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CHAPTER 13 WATCH PRESCALER
13.1 Overview of Watch Prescaler
13.1
MB95410H/470H Series
Overview of Watch Prescaler
The watch prescaler is a 16-bit down-counting, free-run counter, which is
synchronized with the subclock divided by two or the sub-CR clock divided by
two. It has an interval timer function that continuously generates interrupt
requests at regular intervals.
■ Interval Timer Function
The interval timer function continuously generates interrupt requests at regular intervals, using
the subclock divided by two or the sub-CR clock divided by two as its count clock.
• The counter of the watch prescaler counts down and an interrupt request is generated
whenever the selected interval time has elapsed.
• The interval time can be selected from the following eight types:
Table 13.1-1 shows the interval times of the watch prescaler.
Table 13.1-1 Interval Times of Watch Prescaler
Interval time
(Sub-CR clock)
(2n × 2/FCRL*1)
n=10
n=11
n=12
n=13
n=14
n=15
n=16
n=17
20.48 ms
40.96 ms
81.92 ms
163.84 ms
327.68 ms
655.36 ms
1.311 s
2.621 s
Interval time
(Subclock)
(2n × 2/FCL*2)
62.5 ms
125 ms
250 ms
500 ms
1s
2s
4s
8s
*1: 2/FCRL = 20 µs when FCRL = 100 kHz
*2: 2/FCL = 61.035 µs when FCL = 32.768 kHz
Note:
Refer to the data sheet of the MB95410H/470H Series for the accuracy of the sub-CR
clock frequency.
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CHAPTER 13 WATCH PRESCALER
13.2 Configuration of Watch Prescaler
MB95410H/470H Series
13.2
Configuration of Watch Prescaler
The watch prescaler consists of the following blocks:
• Watch prescaler counter
• Counter clear circuit
• Interval timer selector
• Watch prescaler control register (WPCR)
■ Block Diagram of Watch Prescaler
Figure 13.2-1 Block Diagram of Watch Prescaler
Software watchdog timer
Watch prescaler counter (counter)
FCL divided by 2
FCRL divided by 2
× 21
× 22
× 23
× 24
× 25
× 26
× 27
× 28
× 29
× 210 × 211 × 212 × 213 × 214 × 215 × 216
Counter clear
SYCC2:RCM[1:0]
SYCC:SRDY,
STBC:SCRDY
Watchdog timer clear
Resets, or stops
subclock oscillation or
sub-CR clock oscillation
Interrupt
of watch
prescaler
(To the selector of
watch counter)
WTIF
Counter clear
circuit
WTIE
-
Interval timer
selector
-
WTC2
WTC1
WTC0
WCLR
Watch prescaler control register (WPCR)
FCL : Subclock
FCRL : Sub-CR clock
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CHAPTER 13 WATCH PRESCALER
13.2 Configuration of Watch Prescaler
MB95410H/470H Series
● Watch prescaler counter (counter)
This is a 16-bit down-counter that uses the subclock divided by two or the sub-CR clock
divided by two as its count clock.
● Counter clear circuit
This circuit controls the clearing of the watch prescaler.
● Interval timer selector
This circuit selects one out of the eight bits used for the interval timer among 16 bits available
in the watch prescaler counter.
● Watch prescaler control register (WPCR)
This register selects the interval time, clears the counter, controls interrupts and checks the
status.
■ Input Clock
The watch prescaler uses the subclock divided by two or the sub-CR clock divided by two as
its input clock (count clock).
■ Output Clock
The watch prescaler supplies its clock to the timer for the software watchdog timer and the
watch counter.
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13.3
Register of Watch Prescaler
CHAPTER 13 WATCH PRESCALER
13.3 Register of Watch Prescaler
Figure 13.3-1 shows the register of the watch prescaler.
■ Register of Watch Prescaler
Figure 13.3-1 Register of Watch Prescaler
Watch prescaler control register (WPCR)
Address
bit7
bit6
bit5
000BH
WTIF
WTIE
R(RM1),W
R/W
R0/WX
R/W
R(RM1),W
R0,W
R0/WX
-
bit4
R0/WX
bit3
WTC2
R/W
bit2
WTC1
R/W
bit1
WTC0
R/W
bit0
WCLR
R0,W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the readmodify-write (RMW) type of instruction.)
: Write only (Writable. The read value is "0".)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 13 WATCH PRESCALER
13.3 Register of Watch Prescaler
13.3.1
MB95410H/470H Series
Watch Prescaler Control Register (WPCR)
The watch prescaler control register (WPCR) is a register used to select the
interval time, clear the counter, control interrupts and check the status of the
watch prescaler.
■ Watch Prescaler Control Register (WPCR)
Figure 13.3-2 Watch Prescaler Control Register (WPCR)
Address
000BH
bit7
bit6
WTIF WTIE
R(RM1),W R/W
bit2
bit1
bit0
bit5
bit4
bit3
WTC2 WTC1 WTC0 WCLR
R/W
R/W
R0,W
R0/WX R0/WX R/X
WCLR
0
1
Watch timer initialization bit
Read
Write
No change
"0" is always read.
No effect on operation
Clears all counter bits of
the watch prescaler to "1".
WTC2 WTC1 WTC0
1
Initial value
00000000B
0
Interval time
Interval time
(Subclock FCL=32.768 kHz) (Sub-CR clock FCRL=100 kHz)
0
210 × 2/FCL (62.5ms)
210 × 2/FCRL (20.48 ms)
0
0
0
211
× 2/FCL (125 ms)
211 × 2/FCRL (40.96 ms)
0
0
1
212 × 2/FCL (250 ms)
212 × 2/FCRL (81.92 ms)
0
213
× 2/FCL (500 ms)
213 × 2/FCRL (163.84 ms)
1
214
× 2/FCL (1 s)
214 × 2/FCRL (327.68 ms)
× 2/FCL (2 s)
215 × 2/FCRL (655.36 ms)
0
0
1
1
1
0
1
215
1
1
1
1
0
1
216 × 2/FCL (4 s)
216 × 2/FCRL (1.311 s)
× 2/FCL (8 s)
217 × 2/FCRL (2.621 s)
WTIE
0
1
WTIF
0
1
217
Interrupt request enable bit
Disables interrupt request output.
Enables interrupt request output.
Watch interrupt request flag bit
Read
Write
Interval time has not
Clears the bit.
elapsed.
Interval time has
No change
elapsed.
No effect on operation
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R0,W
R0/WX
-
286
:
:
:
:
Write only (Writable. The read value is “0”.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
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CHAPTER 13 WATCH PRESCALER
13.3 Register of Watch Prescaler
MB95410H/470H Series
Table 13.3-1 Functions of Bits in Watch Prescaler Control Register (WPCR)
Bit name
Function
bit7
This bit becomes "1" when the selected interval time of the watch prescaler has elapsed.
• An interrupt request is generated when this bit and the interrupt request enable bit (WTIE)
WTIF:
are set to "1".
Watch interrupt request Writing "0": Clears this bit to "0".
flag bit
Writing "1": Has no effect on operation.
• If this bit is read by the read-modify-write (RMW) type of instruction, it always returns
"1".
bit6
WTIE:
Interrupt request
enable bit
bit5,
bit4
Undefined bits
This bit enables or disables the output of interrupt requests to interrupt controller.
Writing "0": Disables the interrupt request output of the watch prescaler.
Writing "1": Enables the interrupt request output of the watch prescaler.
An interrupt request is output when this bit and the watch interrupt request flag bit (WTIF)
are set to "1".
Their read values are always "0". Writing a value to these bits has no effect on operation.
These bits select the interval time.
WTC2 WTC1 WTC0
bit3
to
bit1
bit0
WTC2 to WTC0:
Watch interrupt
interval time select bits
WCLR:
Watch timer
initialization bit
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Interval time
(Subclock FCL = 32.768 kHz)
Interval time
(Sub-CR clock FCRL = 100 kHz)
1
0
0
210 × 2/FCL (62.5 ms)
210 × 2/FCRL (20.48 ms)
0
0
0
211 × 2/FCL (125 ms)
211 × 2/FCRL (40.96 ms)
0
0
1
212 × 2/FCL (250 ms)
212 × 2/FCRL (81.92 ms)
0
1
0
213 × 2/FCL (500 ms)
213 × 2/FCRL (163.84 ms)
0
1
1
214 × 2/FCL (1 s)
214 × 2/FCRL (327.68 ms)
1
0
1
215 × 2/FCL (2 s)
215 × 2/FCRL (655.36 ms)
1
1
0
216 × 2/FCL (4 s)
216 × 2/FCRL (1.311 s)
1
1
1
217 × 2/FCL (8 s)
217 × 2/FCRL (2.621 s)
This bit clears all counter bits of the watch prescaler to "1".
Writing "0": Has no effect on operation.
Writing "1": Initializes all counter bits to "1".
When this bit is read, it always returns "0".
Note:
When the output of the watch prescaler is selected as the count clock of the
software watchdog timer, clearing the watch prescaler with this bit also clears the
software watchdog timer.
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13.4 Interrupts of Watch Prescaler
13.4
MB95410H/470H Series
Interrupts of Watch Prescaler
An interrupt request is generated when the selected interval time of the watch
prescaler has elapsed (interval timer function).
■ Interrupts in Operation of Interval Timer Function (Watch Interrupts)
In any mode except the stop mode in which the subclock mode is used, if the watch prescaler
counter counts up using the source oscillation of the subclock and the time of the interval timer
has elapsed, the watch interrupt request flag bit is set to "1" (WPCR:WTIF = 1). At that time, if
the interrupt request enable bit has been enabled (WPCR:WTIE = 1), an interrupt request
(IRQ20) is output from the watch prescaler to the interrupt controller.
• Regardless of the value in the WTIE bit, the WTIF bit is set to "1" as soon as the time set by
the watch interrupt interval time select bits has elapsed.
• When the WTIF bit is set to "1", changing the WTIE bit from the disable state to the enable
state (WPCR:WTIE = 0 → 1) immediately generates an interrupt request.
• The WTIF bit will not be set to "1" if the counter is cleared (WPCR:WCLR = 1) at the same
time as the selected bit overflows.
• Write "0" to the WTIF bit in the interrupt service routine to clear an interrupt request to "0".
Note:
To enable the output of interrupt requests after releasing a reset, set the WTIE bit in the
WPCR register to "1" and clear the WTIF bit in the same register simultaneously.
■ Interrupts of Watch Prescaler
Table 13.4-1 Interrupts of Watch Prescaler
Item
Description
Interrupt condition
Interval time set by "WPCR:WTC2 to WTC0" has elapsed.
Interrupt flag
WPCR:WTIF
Interrupt enable
WPCR:WTIE
■ Register and Vector Table Addresses Related to Interrupts of Watch Prescaler
Table 13.4-2 Register and Vector Table Addresses Related to Interrupts of Watch Prescaler
Interrupt source
Watch prescaler*
Interrupt
request no.
IRQ20
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
ILR5
L20
FFD2H
FFD3H
*: The watch prescaler uses the same interrupt request number and vector table addresses as the watch
counter.
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 13 WATCH PRESCALER
13.5 Operations of Watch Prescaler and Setting
Procedure Example
MB95410H/470H Series
13.5
Operations of Watch Prescaler and Setting
Procedure Example
The watch prescaler operates as an interval timer.
■ Operations of Interval Timer Function (Watch Prescaler)
The counter of the watch prescaler continues to count down using the subclock divided by two
as its count clock as long as the subclock oscillates.
When cleared (WPCR:WCLR = 1), the counter starts counting down from "FFFFH". Once it
reaches "0000H", it returns to "FFFFH" to continue counting. As soon as the time set by the
interrupt interval time select bits has elapsed during the counting down, the watch interrupt
request flag bit (WPCR:WTIF) is set to "1" in any mode except the stop mode in which the
subclock mode is used. In other words, a watch interrupt request is generated at every selected
interval time, based on the time when the counter was last cleared.
■ Clearing Watch Prescaler
If the watch prescaler is cleared, other peripheral functions that are using the watch prescaler
output are affected by changes in count time and by other factors.
When clearing the counter using the watch prescaler initialization bit (WPCR:WCLR), modify
the settings of other peripheral functions so that clearing the counter does not have any
unexpected effect on them.
When the output of the watch prescaler is selected as the count clock, clearing the watch
prescaler also clears the watchdog timer.
The watch prescaler is cleared not only by the watch prescaler initialization bit
(WPCR:WCLR) but also when the subclock is stopped and the oscillation stabilization wait
time is necessary. The watch prescaler is cleared in the following situations:
• When the device transits from the subclock mode or sub-CR clock mode to the stop mode
• When the subclock oscillation enable bits in the system clock control register 2
(SYCC2:SOSCE or SCRE) is set to "0" in main clock mode or main CR clock mode.
In addition, the counter of the watch prescaler is cleared and stops operating when a reset is
generated.
■ Operation Examples of Watch Prescaler
Figure 13.5-1 shows operating examples under the following conditions:
1) When a power-on reset occurs
2) When the device transits to the sleep mode during the operation of the interval timer
function in subclock mode or sub-CR clock mode
3) When the device transits to the stop mode during the operation of the interval timer function
in subclock mode or sub-CR clock mode
4) When a request for clearing the counter is issued
The same operation is performed when changing to the watch mode as for when changing to
the sleep mode.
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CHAPTER 13 WATCH PRESCALER
13.5 Operations of Watch Prescaler and Setting
Procedure Example
Figure 13.5-1 Operation Examples of Watch Prescaler
MB95410H/470H Series
Counter value
(count down)
FFFFH
Count value detected in
WATR:SWT3 to SWT0
Count value detected in
WPCR:WTC2 to WTC0
Interval cycle
(WPCR:WTC2 to WTC0=011B)
0000H
Subclock oscillation
stabilization wait time
Cleared by transition
to stop mode
4) Counter cleared
(WPCR:WCLR=1)
Subclock oscillation
stabilization wait time
1) Power-on reset
Cleared in interrupt
service routine
Cleared at interval
setting
WTIF bit
WTIE bit
Sleep
Sleep mode
released by
watch interrupt
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
Stop mode released by external interrupt
• When setting interval time select bits in the watch prescaler control register (WPCR:WTC2 to WTC0) to "011B" (2
• WPCR:WTC2 to WTC0
• WPCR:WCLR
• WPCR:WTIF
• WPCR:WTIE
• STBC:SLP
• STBC:STP
• WATR:SWT3 to SWT0
Stop
14
× 2/FCL)
: Interval time select bits in watch prescaler control register
: Watch timer initialization bit in watch prescaler control register
: Watch interrupt request flag bit in watch prescaler control register
: Watch interrupt request enable bit in watch prescaler control register
: Sleep bit in standby control register
: Stop bit in standby control register
: Subclock oscillation stabilization wait time select bits in oscillation stabilization wait time setting register
■ Setting Procedure Example
Below is an example of procedure for setting the watch prescaler.
● Initial settings
1) Set the interrupt level.
(ILR5)
2) Set the interval time.
(WPCR:WTC2 to WTC0)
3) Enable interrupts.
(WPCR:WTIE = 1)
4) Clear the counter.
(WPCR:WCLR = 1)
● Processing interrupts
1) Clear the interrupt request flag.
(WPCR:WTIF = 0)
2) Process an interrupt.
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13.6 Notes on Using Watch Prescaler
MB95410H/470H Series
13.6
Notes on Using Watch Prescaler
This section provides notes on using the watch prescaler.
■ Notes on Using Watch Prescaler
● When setting interrupt processing in a program
The watch prescaler cannot be waken up from interrupt processing if the watch interrupt
request flag bit (WPCR:WTIF) is set to "1" and the interrupt request is enabled
(WPCR:WTIE = 1). Always clear the WTIF bit in the interrupt routine.
● Clearing the watch prescaler
When the watch prescaler is selected as the count clock of the software watchdog timer
(WDTC:CS1, CS0, CSP = 100B or 110B), clearing the watch prescaler also clears the software
watchdog timer.
● Watch interrupts
In stop mode in which the main clock is used, the watch prescaler performs counting and
generates the watch prescaler interrupt (IRQ20).
● Peripheral functions receiving clock from the watch prescaler
If the counter of the watch prescaler is cleared when the output of the watch prescaler is used in
other peripheral functions, the operations of such peripheral functions may be affected such as
the changing of their operating cycles.
After the counter of the watch prescaler is cleared, the clock for the software watchdog timer
output from the watch prescaler returns to the initial state. However, since the software
watchdog timer counter is also cleared at the same time as the clock for the software watchdog
timer returns to the initial state, the software watchdog timer operates in its normal cycle.
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13.7 Sample Settings for Watch Prescaler
13.7
MB95410H/470H Series
Sample Settings for Watch Prescaler
This section provides sample settings for the watch prescaler.
■ Sample Settings
● How to initialize the watch prescaler
The watch timer initialization bit (WPCR:WCLR) is used.
Operation
Watch timer initialization bit (WCLR)
To initialize the watch prescaler
Set the bit to "1".
● How to select the interval time
The watch interrupt interval time select bits (WPCR:WTC2 to WTC0) are used to select the
interval time.
● Interrupt-related register
The interrupt level setting register shown in the following table is used to select the interrupt
level.
Interrupt source
Interrupt level setting register
Interrupt vector
Watch prescaler
Interrupt level setting register (ILR5)
Address: 0007EH
#20
Address: 0FFD2H
● How to enable/disable/clear interrupts
Interrupt request enable bit, Watch interrupt request flag
The interrupt request enable bit (WPCR:WTIE) is used to enable interrupts.
Operation
Interrupt request enable bit (WTIE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
The watch interrupt request flag (WPCR:WTIF) is used to clear interrupt requests.
292
Operation
Watch interrupt request flag (WTIF)
To clear an interrupt request
Set the bit to "0".
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CHAPTER 14
WATCH COUNTER
This chapter describes the functions and
operations of the watch counter.
14.1 Overview of Watch Counter
14.2 Configuration of Watch Counter
14.3 Registers of Watch Counter
14.4 Interrupts of Watch Counter
14.5 Operations of Watch Counter and Setting Procedure
Example
14.6 Notes on Using Watch Counter
14.7 Sample Settings for Watch Counter
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CHAPTER 14 WATCH COUNTER
14.1 Overview of Watch Counter
14.1
MB95410H/470H Series
Overview of Watch Counter
The watch counter can generate interrupt requests ranging from min. 125 ms to
max. 63 s intervals.
■ Watch Counter
The watch counter performs counting for the number of times specified in the register by using
the selected count clock and generates an interrupt request. The count clock can be selected
from the four types shown in Table 14.1-1. The count value can be set to any number from 0 to
63. When "0" is selected, no interrupt is generated.
When the count clock is set to 1s and the count value is set to "60", an interrupt is generated
every one minute.
Table 14.1-1 Count Clock Types
Count clock
Count cycle when FCL operates at 32.768 kHz
212/FCL
125 ms
213/FCL
250 ms
214/FCL
500 ms
215/FCL
1s
FCL: Subclock
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CHAPTER 14 WATCH COUNTER
14.2 Configuration of Watch Counter
MB95410H/470H Series
14.2
Configuration of Watch Counter
Figure 14.2-1 shows the block diagram of the watch counter.
■ Block Diagram of Watch Counter
Figure 14.2-1 Block Diagram of Watch Counter
Watch counter control register (WCSR)
ISEL WCFLG CTR5
CTR4
Interrupt of
watch
prescaler
Interrupt of
watch counter
Underflow
Internal bus
Counter clear
From
watch
prescaler
CTR1 CTR0
Counter value
Interrupt
enabled
Count clock
selected
CTR3 CTR2
212/FCL
213/FCL
214/FCL
215/FCL
CS1
CS0
Counter
(6-bit counter)
Reload value
RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTR0
Watch counter data register (WCDR)
FCL: Subclock
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CHAPTER 14 WATCH COUNTER
14.2 Configuration of Watch Counter
MB95410H/470H Series
● Counter
This is a 6-bit down-counter that uses the output clock of the watch prescaler as its count clock.
● Watch counter control register (WCSR)
This register controls interrupts and checks the status.
● Watch counter data register (WCDR)
This register sets the interval time and selects the count clock.
■ Input Clock
The watch counter uses the output clock of the watch prescaler as its input clock (count clock).
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14.3
Registers of Watch Counter
CHAPTER 14 WATCH COUNTER
14.3 Registers of Watch Counter
Figure 14.3-1 shows the registers of the watch counter.
■ Registers of Watch Counter
Figure 14.3-1 Registers of Watch Counter
Watch counter data register (WCDR)
Address
bit7
bit6
bit5
0FE3H
CS1
CS0
RCTR5
R/W
R/W
R/W
bit4
RCTR4
R/W
Watch counter control register (WCSR)
Address
bit7
bit6
bit5
bit4
0070H
ISEL
WCFLG CTR5
CTR4
R(RM1),W
R/W
R/WX
R/WX
bit3
RCTR3
R/W
bit2
RCTR2
R/W
bit1
RCTR1
R/W
bit0
RCTR0
R/W
Initial value
00111111B
bit3
CTR3
R/WX
bit2
CTR2
R/WX
bit1
CTR1
R/WX
bit0
CTR0
R/WX
Initial value
00000000B
R/W
: Readable/writable (The read value is the same as the write value.)
R(RM1),W : Readable/writable (The read value is different from the write value. "1" is read by the readmodify-write (RMW) type of instruction.)
R/WX
: Read only (Readable. Writing a value to it has no effect on operation.)
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CHAPTER 14 WATCH COUNTER
14.3 Registers of Watch Counter
14.3.1
MB95410H/470H Series
Watch Counter Data Register (WCDR)
The watch counter data register (WCDR) is used to select the count clock and
set the counter reload value.
■ Watch Counter Data Register (WCDR)
Figure 14.3-2 Watch Counter Data Register (WCDR)
Address
0FE3H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CS1
CS0 RCTR5 RCTR4 RCTR3 RCTR2 RCTR1RCTR0 00111111B
R/W R/W R/W R/W R/W R/W R/W R/W
RCTR5 to
These bits set the counter reload value.
RCTR0
(Initial value = 3FH)
CS1 CS0
R/W
FCL
Count clock select bits (FCL = 32.768 kHz)
12
0
0
2 /FCL (125 ms)
0
1
213/FCL (250 ms)
1
0
214/FCL (500 ms)
1
1
215/FCL (1 s)
: Readable/writable (The read value is the same as the write value.)
: Initial value
: Subclock
Table 14.3-1 Functions of Bits in Watch Counter Data Register (WCDR)
Bit name
bit7,
bit6
bit5
to
bit0
298
Function
CS1, CS0:
Count clock select bits
These bits select the clock for the watch counter.
"00" = 212/FCL, "01" = 213/FCL, "10" = 214/FCL, "11" = 215/FCL
(FCL: Subclock)
These bits should be modified when the WCSR:ISEL bit is "0".
RCTR5 to RCTR0:
Counter reload value
setting bits
These bits set the counter reload value.
If the value is modified during counting, the modified value will become effective upon a
reload after the counter underflows.
Writing "0": Generates no interrupt request.
If the reload value (RCTR5 to RCTR0) is modified at the same time as an interrupt is
generated (WCSR:WCFLG = 1), the correct value will not be reloaded. Therefore, the
reload value must be modified before an interrupt is generated, such as when the watch
counter is stopped (WCSR:ISEL = 0), or during the interrupt routine.
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CHAPTER 14 WATCH COUNTER
14.3 Registers of Watch Counter
MB95410H/470H Series
14.3.2
Watch Counter Control Register (WCSR)
The watch counter control register (WCSR) is used to control the operation and
interrupts of the watch counter. It can also read the count value.
■ Watch Counter Control Register (WCSR)
Figure 14.3-3 Watch Counter Control Register (WCSR)
bit7
Address
0070H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
Initial value
00000000B
R/W R(RM1)/W R/WX R/WX R/WX R/WX R/WX R/WX
CTR5 to
CTR0
These bits read the counter value.
Interrupt request flag bit
WCFLG
ISEL
Write
Read
0
No interrupt request generated
Clears this bit
1
An interrupt request generated
No change, no effect on operation
Watch counter start & interrupt request enable bit
0
Stops watch counter and disables interrupt request of watch counter (Enables interrupt request of watch prescaler)
1
Activates watch counter and enables interrupt request of watch counter (Disables interrupt request of watch prescaler)
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R/WX
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: Read only (Readable. Writing a value to it has no effect on operation.)
: Initial value
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14.3 Registers of Watch Counter
MB95410H/470H Series
Table 14.3-2 Functions of Bits in Watch Counter Status Register (WCSR)
Bit name
Function
bit7
• This bit activates the watch counter and selects whether to enable interrupts of the watch
counter or those of the watch prescaler.
Writing "0": The watch counter is cleared and stopped. Moreover, interrupt requests of
the watch counter are disabled, while interrupt requests of the watch
prescaler are enabled.
ISEL:
Writing "1": The interrupt request output of the watch counter is enabled and the counter
Watch counter start &
starts operation.
interrupt request enable
On the other hand, interrupt requests of the watch prescaler are disabled.
bit
• Always disable interrupts of the watch prescaler before setting this bit to "1" to select
interrupts of the watch counter.
• The watch counter performs counting, using an asynchronous clock from the watch
prescaler. For this reason, an error of up to one count clock may occur at the beginning of
a count cycle, depending on the timing for setting ISEL bit to "1".
bit6
WCFLG:
Interrupt request flag
bit
• This bit is set to "1" when the counter underflows.
• When this bit and the ISEL bit are both set to "1", a watch counter interrupt is generated.
Writing "0": Clears the bit.
Writing "1": Has no effect on the operation.
• "1" is always read in read-modify-write operation.
CTR5 to CTR0:
Counter read bits
• These bits can read the counter value during counting. It should be noted that the correct
counter value may not be read if a read is attempted while the counter value is being
changed. Therefore, read the counter value twice to check if the same value is read on
both occasions before using it.
• Write has no effect on the operation.
bit5
to
bit0
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14.4
Interrupts of Watch Counter
CHAPTER 14 WATCH COUNTER
14.4 Interrupts of Watch Counter
The watch counter outputs interrupt requests when the counter underflows
(counter value = 000001B).
■ Interrupts of Watch Counter
When the counter of the watch counter underflows, the interrupt request flag bit (WCFLG) in
the watch counter control register (WCSR) is set to "1". If the interrupt request enable bit
(ISEL) of the watch counter is set to "1", an interrupt request of the watch counter is outputted
to the interrupt controller.
Table 14.4-1 shows the interrupt control bits and interrupt sources of the watch counter.
Table 14.4-1 Interrupt Control Bits and Interrupt Sources of Watch Counter
Item
Description
Interrupt request flag bit
WCFLG bit in the WCSR register
Interrupt request enable bit
ISEL bit in the WCSR register
Interrupt source
Counter underflow
■ Register and Vector Table Addresses Related to Interrupts of Watch Counter
Table 14.4-2 Register and Vector Table Addresses Related to Interrupts of Watch Counter
Interrupt source
Watch counter*
Interrupt
request no.
IRQ20
Interrupt level setup register
Register
ILR5
Vector table address
Setting bit
Upper
Lower
L20
FFD2H
FFD3H
*: The watch counter uses the same interrupt request number and vector table addresses as the
watch prescaler.
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 14 WATCH COUNTER
14.5 Operations of Watch Counter and Setting Procedure
Example
14.5
MB95410H/470H Series
Operations of Watch Counter and Setting Procedure
Example
The watch counter counts down for the number of times specified in the count
value by RCTR5 to RCTR0 bits, using the count clock selected by CS1 and CS0
bits, when the ISEL bit is set to "1". Once the counter underflows, WCFLG bit in
the WCSR register is set to "1", generating an interrupt.
■ Setting Procedure of Watch Counter
The setting procedure of the watch counter is described below.
(1) Select the count clock (CS1 and CS0 bits) and set the counter reload value (RCTR5 to
RCTR0 bits).
(2) Set the ISEL bit in the WCSR register to "1" to start a down count and enable interrupts.
Also disable interrupts of the watch prescaler.
The watch counter performs counting by using a divided clock (asynchronous) from the
watch prescaler. An error of up to one count clock may occur at the beginning of a count
cycle, depending on the timing for setting the ISEL bit to "1".
(3) When the counter underflows, the WCFLG bit in the WCSR register is set to "1",
generating an interrupt.
(4) Write "0" to the WCFLG bit to clear it.
(5) If RCTR5 to RCTR0 bits are modified during counting, the reload value will be updated
during a reload after the counter is set to "1".
(6) When writing "0" to the ISEL bit, the counter becomes "0" and stops operation.
Figure 14.5-1 Watch Counter Operation
(6)
(2)
ISEL
Count clock
“11B”
CS1,CS0
(1)
RCTR5 to RCTR0
7
9
(5)
CTR5 to CTR0
0
7 6 5 4 3 2 1
9 8 7 6 5 4
0
WCFLG
(3)
302
(4)
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CHAPTER 14 WATCH COUNTER
14.5 Operations of Watch Counter and Setting Procedure
Example
Note:
To re-activate the counter by setting WCSR:ISEL to "1" after stopping it by setting
WCSR:ISEL to "0", read WCSR:CTR[5:0] twice to ensure that WCSR:CTR[5:0] have
been cleared to "000000B".
■ Operation in Substop Mode
When the device enters the substop mode, the watch counter stops the count operation and the
watch prescaler is also cleared. Therefore, the watch counter cannot count the correct value after
the substop mode is cancelled. After the substop mode is cancelled, the ISEL bit must always be
set to "0" to clear the counter before use. In any standby mode other than the substop mode, the
watch counter continues to operate.
■ Operation in Main Stop Mode
The interrupt is not generated though the watch counter continues the count operation when
entering the main stop mode. Moreover, the watch counter stops, too, when the subclock
oscillation enable bit (SOSCE) in the system clock control register 2 (SYCC2) is set to "0".
■ Setting Procedure Example
Below is an example of procedure for setting the watch counter.
● Initial settings
1) Set the interrupt level. (ILR5)
2) Select the count clock. (WCDR:CS1, CS0)
3) Set the counter reload value. (WCDR:RCTR5 to RCTR0)
4) Activate the watch counter and enable interrupts. (WCSR:ISEL = 1)
● Interrupt processing
1) Clear the interrupt request flag. (WCSR:WCFLG = 0)
2) Process any interrupt.
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CHAPTER 14 WATCH COUNTER
14.6 Notes on Using Watch Counter
14.6
MB95410H/470H Series
Notes on Using Watch Counter
This section provides notes on using the watch counter.
• If the watch prescaler is cleared during the operation of the watch counter, the watch
counter may not be able to perform normal operation. When clearing the watch prescaler,
set the ISEL bit in the WCSR register to "0" to stop the watch counter in advance.
• To re-activate the counter by setting WCSR:ISEL to "1" after stopping it by setting
WCSR:ISEL to "0", read WCSR:CTR[5:0] twice to ensure that WCSR:CTR[5:0] have been
cleared to "000000B".
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CHAPTER 14 WATCH COUNTER
14.7 Sample Settings for Watch Counter
MB95410H/470H Series
14.7
Sample Settings for Watch Counter
This section provides sample settings for the watch counter.
■ Sample Settings
● How to enable/stop the watch counter
Use the watch counter start & interrupt request enable bit (WCSR:ISEL).
Operation
Watch counter start & interrupt request enable bit (ISEL)
To enable the watch counter
Set the bit to "1".
To stop the watch counter
Set the bit to "0".
● How to select the count clock
Use the count clock select bits (WCDR:CS1, CS0) to select a count clock.
● Interrupt-related register
The interrupt level is set in the interrupt level setting register shown in the following table.
Interrupt source
Interrupt level setting register
Interrupt vector
Watch counter
Interrupt level setting register (ILR5)
Address: 0007EH
#20
Address: 0FFD2H
● How to enable/disable/clear interrupts
Interrupt request enable bit, Interrupt request flag bit
Use the watch counter start & interrupt request enable bit (WCSR:ISEL) to enable interrupts.
Operation
Watch counter start & interrupt request enable bit (ISEL)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
Use the interrupt request flag bit (WCSR:WCFLG) to clear the interrupt request.
Operation
Interrupt request flag bit (WCFLG)
To clear an interrupt request
Set the bit to "0".
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14.7 Sample Settings for Watch Counter
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CHAPTER 15
WILD REGISTER
FUNCTION
This chapter describes the functions and
operations of the wild register function.
15.1 Overview of Wild Register Function
15.2 Configuration of Wild Register Function
15.3 Registers of Wild Register Function
15.4 Operations of Wild Register Function
15.5 Typical Hardware Connection Example
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CHAPTER 15 WILD REGISTER FUNCTION
15.1 Overview of Wild Register Function
15.1
MB95410H/470H Series
Overview of Wild Register Function
The wild register function can be used to patch bugs in a program with
addresses and amendment data, both of which are to be set in built-in registers.
This section describes the wild register function.
■ Wild Register Function
The wild register consists of three wild register data setting registers, three wild register
address setting registers, a 1-byte address compare enable register and a 1-byte wild register
data test setting register. If addresses and data that are to be modified are set to these registers,
the ROM data can be replaced with modification data set in the registers. Data of up to three
different addresses can be modified.
The wild register function can be used to debug a program after creating the mask and to patch
bugs in the program.
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CHAPTER 15 WILD REGISTER FUNCTION
15.2 Configuration of Wild Register Function
MB95410H/470H Series
15.2
Configuration of Wild Register Function
The block diagram of the wild register is shown below. The wild register
consists of the following blocks:
• Memory area block
Wild register data setting register (WRDR0 to WRDR2)
Wild register address setting register (WRAR0 to WRAR2)
Wild register address compare enable register (WREN)
Wild register data test setting register (WROR)
• Control circuit block
■ Block Diagram of Wild Register Function
Figure 15.2-1 Block Diagram of Wild Register Function
Wild register function
Control circuit block
Decoder and logic
control circuit
Access
control circuit
Address
compare circuit
Memory area block
Internal bus
Wild register address
setting register
(WRAR)
Wild register data setting
register
(WRDR)
Access
control circuit
Wild register address
compare enable register
(WREN)
Wild register data test
setting register
(WROR)
Memory space
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CHAPTER 15 WILD REGISTER FUNCTION
15.2 Configuration of Wild Register Function
MB95410H/470H Series
● Memory area block
The memory area block consists of the wild register data setting registers (WRDR), wild
register address setting registers (WRAR), wild register address compare enable register
(WREN) and wild register data test setting register (WROR). The wild register function is used
to specify the addresses and data that need to be replaced. The wild register address compare
enable register (WREN) enables the wild register function for each wild register data setting
register (WRDR). In addition, the wild register data test setting register (WROR) enables the
normal read function for each wild register data setting register (WRDR).
● Control circuit block
This circuit compares the actual address data with addresses set in the wild register address
setting registers (WRAR). If they match, the circuit outputs the data from the wild register data
setting register (WRDR) to the data bus. The operation of the control circuit block is controlled
by the wild register address compare enable register (WREN).
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CHAPTER 15 WILD REGISTER FUNCTION
15.3 Registers of Wild Register Function
MB95410H/470H Series
15.3
Registers of Wild Register Function
The registers of the wild register function include the wild register data setting
registers (WRDR), wild register address setting registers (WRAR), wild register
address compare enable register (WREN) and wild register data test setting
register (WROR).
■ Registers of Wild Register Function
Figure 15.3-1 Registers of Wild Register Function
Wild register data setting registers (WRDR0 to WRDR2)
Address
bit7
bit6
bit5
bit4
0F82H
WRDR0
RD7
RD6
RD5
RD4
0F85H
WRDR1
R/W
R/W
R/W
R/W
0F88H
WRDR2
Wild register address setting registers (WRAR0 to WRAR2)
Address
bit15
bit14
bit13
bit12
WRAR0 0F80H, 0F81H RA15 RA14 RA13 RA12
WRAR1 0F83H, 0F84H
R/W
R/W
R/W
R/W
,
0F87
0F86
bit7
bit6
bit5
bit4
WRAR2
H
H
RA7
RA6
RA5
RA4
R/W
R/W
R/W
R/W
bit3
RD3
R/W
bit2
RD2
R/W
bit1
RD1
R/W
bit0
RD0
R/W
Initial value
00000000B
bit11
RA11
R/W
bit3
RA3
R/W
bit10
RA10
R/W
bit2
RA2
R/W
bit9
RA9
R/W
bit1
RA1
R/W
bit8
RA8
R/W
bit0
RA0
R/W
Initial value
00000000B
bit2
EN2
R/W
bit1
EN1
R/W
bit0
EN0
R/W
Initial value
00000000B
bit1
DRR1
R/W
bit0
DRR0
R/W
Initial value
00000000B
Wild register address compare enable register (WREN)
Address
bit7
bit6
bit5
bit4
bit3
0076H
Reserved Reserved Reserved
R0/WX R0/WX R/W0 R/W0 R/W0
Wild register data test setting register (WROR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
0077H
Reserved Reserved Reserved DRR2
R0/WX R0/WX R/W0 R/W0 R/W0
R/W
R/W
R/W0
R0/WX
-
:
:
:
:
Initial value
00000000B
Readable/writable (The read value is the same as the write value.)
The write value is "0". The read value is the same as the write value.
The read value is "0". Writing a value to this bit has no effect on operation.
Undefined bit
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CHAPTER 15 WILD REGISTER FUNCTION
15.3 Registers of Wild Register Function
MB95410H/470H Series
■ Wild Register Number
A wild register number is assigned to each wild register address setting register (WRAR) and
each wild register data setting register (WRDR).
Table 15.3-1 Wild Register Numbers Corresponding to Wild Register Address Setting Registers
and Wild Register Data Setting Registers
312
Wild register
number
Wild register address setting register
(WRAR)
Wild register data setting register
(WRDR)
0
WRAR0
WRDR0
1
WRAR1
WRDR1
2
WRAR2
WRDR2
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CHAPTER 15 WILD REGISTER FUNCTION
15.3 Registers of Wild Register Function
MB95410H/470H Series
15.3.1
Wild Register Data Setting Registers (WRDR0 to
WRDR2)
The wild register data setting registers (WRDR0 to WRDR2) are used to specify
the data to be amended by the wild register function.
■ Wild Register Data Setting Registers (WRDR0 to WRDR2)
Figure 15.3-2 Wild Register Data Setting Registers (WRDR0 to WRDR2)
WRDR0
Address
0F82H
WRDR1
Address
0F85H
WRDR2
Address
0F88H
bit7
RD7
R/W
bit6
RD6
R/W
bit5
RD5
R/W
bit4
RD4
R/W
bit3
RD3
R/W
bit2
RD2
R/W
bit1
RD1
R/W
bit0
RD0
R/W
Initial value
00000000B
bit7
RD7
R/W
bit6
RD6
R/W
bit5
RD5
R/W
bit4
RD4
R/W
bit3
RD3
R/W
bit2
RD2
R/W
bit1
RD1
R/W
bit0
RD0
R/W
Initial value
00000000B
bit7
RD7
R/W
bit6
RD6
R/W
bit5
RD5
R/W
bit4
RD4
R/W
bit3
RD3
R/W
bit2
RD2
R/W
bit1
RD1
R/W
bit0
RD0
R/W
Initial value
00000000B
R/W
: Readable/writable (The read value is the same as the write value.)
Table 15.3-2 Functions of Bits in Wild Register Data Setting Register (WRDR)
Bit name
bit7
to
bit0
RD7 to RD0:
Wild register data
setting bits
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Function
These bits specify the data to be amended by the wild register function.
• These bits are used to set the amendment data at the address assigned by the wild register
address setting register (WRAR). Data is valid at an address corresponding to one of the
wild register numbers.
• The read access to one of these bits is enabled only when the data test setting bit in the
wild register data test setting register (WROR) corresponding to the bit to be read is set to
"1".
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15.3 Registers of Wild Register Function
MB95410H/470H Series
Wild Register Address Setting Registers (WRAR0
to WRAR2)
15.3.2
The wild register address setting registers (WRAR0 to WRAR2) are used to set
the address to be amended by the wild register function.
■ Wild Register Address Setting Registers (WRAR0 to WRAR2)
Figure 15.3-3 Wild Register Address Setting Registers (WRAR0 to WRAR2)
WRAR0
Address
0F80H
Address
0F81H
WRAR1
Address
0F83H
Address
0F84H
WRAR2
Address
0F86H
Address
0F87H
R/W
bit15
RA15
R/W
bit14
RA14
R/W
bit13
RA13
R/W
bit12
RA12
R/W
bit11
RA11
R/W
bit10
RA10
R/W
bit9
RA9
R/W
bit8
RA8
R/W
Initial value
00000000B
bit7
RA7
R/W
bit6
RA6
R/W
bit5
RA5
R/W
bit4
RA4
R/W
bit3
RA3
R/W
bit2
RA2
R/W
bit1
RA1
R/W
bit0
RA0
R/W
Initial value
00000000B
bit15
RA15
R/W
bit14
RA14
R/W
bit13
RA13
R/W
bit12
RA12
R/W
bit11
RA11
R/W
bit10
RA10
R/W
bit9
RA9
R/W
bit8
RA8
R/W
Initial value
00000000B
bit7
RA7
R/W
bit6
RA6
R/W
bit5
RA5
R/W
bit4
RA4
R/W
bit3
RA3
R/W
bit2
RA2
R/W
bit1
RA1
R/W
bit0
RA0
R/W
Initial value
00000000B
bit15
RA15
R/W
bit14
RA14
R/W
bit13
RA13
R/W
bit12
RA12
R/W
bit11
RA11
R/W
bit10
RA10
R/W
bit9
RA9
R/W
bit8
RA8
R/W
Initial value
00000000B
bit7
RA7
R/W
bit6
RA6
R/W
bit5
RA5
R/W
bit4
RA4
R/W
bit3
RA3
R/W
bit2
RA2
R/W
bit1
RA1
R/W
bit0
RA0
R/W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
Table 15.3-3 Functions of Bits in Wild Register Address Setting Register (WRAR)
Bit name
bit15 RA15 to RA0:
to
Wild register address
bit0 setting bits
314
Function
These bits set the address to be amended by the wild register function.
The address to be assigned to amendment data is set to these bits. The address is to be
specified according to the wild register number corresponding to a wild register address
setting register.
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15.3 Registers of Wild Register Function
MB95410H/470H Series
15.3.3
Wild Register Address Compare Enable Register
(WREN)
The wild register address compare enable register (WREN) enables/disables
the operations of wild register functions using their respective wild register
numbers.
■ Wild Register Address Compare Enable Register (WREN)
Figure 15.3-4 Wild Register Address Compare Enable Register (WREN)
Address
0076H
bit7
R0/WX
R/W
R/W0
R0/WX
-
:
:
:
:
bit6
bit5
bit4
bit3
Reserved Reserved Reserved
R0/WX
R/W0
R/W0
R/W0
bit2
bit1
bit0
Initial value
EN2
R/W
EN1
R/W
EN0
R/W
00000000B
Readable/writable (The read value is the same as the write value.)
The write value is "0". The read value is the same as the write value.
The read value is "0". Writing a value to this bit has no effect on operation.
Undefined bit
Table 15.3-4 Functions of Bits in Wild Register Address Compare Enable Register (WREN)
Bit name
bit7,
bit6
Undefined bits
bit5
to
bit3
Reserved bits
bit2
to
bit0
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
Always set these bits to "0".
EN2, EN1, EN0:
Wild register address
compare enable bits
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These bits enable/disable the operation of the wild register.
• EN0 corresponds to wild register number 0.
• EN1 corresponds to wild register number 1.
EN2 corresponds to wild register number 2.
Writing "0": Disables the operation of the wild register function.
Writing "1": Enables the operation of the wild register function.
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15.3 Registers of Wild Register Function
15.3.4
MB95410H/470H Series
Wild Register Data Test Setting Register (WROR)
The wild register data test setting register (WROR) enables/disables reading
data from the corresponding wild register data setting register (WRDR0 to
WRDR2).
■ Wild Register Data Test Setting Register (WROR)
Figure 15.3-5 Wild Register Data Test Setting Register (WROR)
Address
0077H
bit7
R0/WX
R/W
R/W0
R0/WX
-
:
:
:
:
bit6
bit5
bit4
bit3
Reserved Reserved Reserved
R0/WX
R/W0
R/W0
R/W0
bit2
bit1
bit0
Initial value
DRR2
R/W
DRR1
R/W
DRR0
R/W
00000000B
Readable/writable (The read value is the same as the write value.)
The write value is "0". The read value is the same as the write value.
The read value is "0". Writing a value to this bit has no effect on operation.
Undefined bit
Table 15.3-5 Functions of Bits in Wild Register Data Test Setting Register (WROR)
Bit name
bit7,
bit6
Undefined bits
bit5
to
bit3
Reserved bits
bit2
to
bit0
316
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
Always set these bits to "0".
DRR2, DRR1, DRR0:
Wild register data test
setting bits
These bits enable/disable the normal reading from the corresponding data setting register of
the wild register.
• DRR0 enables/disables reading from the wild register data setting register (WRDR0).
• DRR1 enables/disables reading from the wild register data setting register (WRDR1).
• DRR2 enables/disables reading from the wild register data setting register (WRDR2).
Writing "0": Disables reading.
Writing "1": Enables reading.
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15.4 Operations of Wild Register Function
MB95410H/470H Series
15.4
Operations of Wild Register Function
This section describes the procedure for setting the wild register function.
■ Procedure for Setting Wild Register Function
Prepare a program that can read the value to be set in the wild register from external memory
(e.g. EEPROM or FRAM) in the user program before using the wild register function. The
setting method for the wild register is shown below.
This section does not include information on the method of communications between the
external memory and the device.
• Write the address of the built-in ROM code that will be modified to the wild register
address setting register (WRAR0 to WRAR2).
• Write a new code to the wild register data setting register (WRDR0 to WRDR2)
corresponding to the wild register address setting register to which the address has been
written.
• Write "1" to the EN bit in the wild register address compare enable register (WREN)
corresponding to the wild register number to enable the wild register function represented
by that wild register number.
Table 15.4-1 shows the procedure for setting the registers of the wild register function.
Table 15.4-1 Procedure for Setting Registers of Wild Register Function
Step
Operation
Operation example
1
Read replacement data from a peripheral function
outside through a certain communication method.
Suppose the built-in ROM code to be modified is at the
address F011H and the data to be modified is "B5H", and
there are three built-in ROM codes to be modified.
2
Write the replacement address to a wild register
address setting register (WRAR0 to WRAR2).
Set wild register address setting registers (WRAR0 = F011H,
WRAR1 = ..., WRAR2 = ...).
3
Write a new ROM code (replacement for the built-in
ROM code) to a wild register data setting register
(WRDR0 to WRDR2).
Set the wild register data setting registers (WRDR0 = B5H,
WRDR1 =..., WRDR2 =...).
4
Setting bit 0 of the address compare enable register (WREN)
to "1" enables the wild register function of the wild register
number 0. If the address matches the value set in the wild
Enable the EN bit in the wild register address
register address setting register (WRAR), the value of the
compare enable register (WREN) corresponding to
wild register data setting register (WRDR) will be replaced
the wild register number of the wild register function
with the built-in ROM code. When replacing more than one
used.
built-in ROM code, enable the related EN bits in the wild
register address compare enable register (WREN)
corresponding to respective built-in ROM codes.
■ Wild Register Function Applicable Addresses
The wild register function can be applied to all address space except the address "0078H".
Since the address "0078H" is used as a mirror address for the register bank pointer and the
direct bank pointer, this address cannot be patched.
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CHAPTER 15 WILD REGISTER FUNCTION
15.5 Typical Hardware Connection Example
15.5
MB95410H/470H Series
Typical Hardware Connection Example
Below is an example of typical hardware connection for the application of the
wild register function.
■ Hardware Connection Example
Figure 15.5-1 Typical Hardware Connection Example
EEPROM
(Storing correction program)
SO
SI
SCK
318
UI0
UO0
UCK0
MB95410H/470H Series
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CHAPTER 16
EXTERNAL INTERRUPT
CIRCUIT
This chapter describes the functions and
operations of the external interrupt circuit.
16.1 Overview of External Interrupt Circuit
16.2 Configuration of External Interrupt Circuit
16.3 Channels of External Interrupt Circuit
16.4 Pins of External Interrupt Circuit
16.5 Registers of External Interrupt Circuit
16.6 Interrupts of External Interrupt Circuit
16.7 Operations of External Interrupt Circuit and Setting
Procedure Example
16.8 Notes on Using External Interrupt Circuit
16.9 Sample Settings for External Interrupt Circuit
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.1 Overview of External Interrupt Circuit
16.1
MB95410H/470H Series
Overview of External Interrupt Circuit
The external interrupt circuit detects edges on the signal that is input to the
external interrupt pin, and outputs interrupt requests to the interrupt controller.
■ Function of External Interrupt Circuit
The function of the external interrupt circuit is to detect any edge of a signal that is input to an
external interrupt pin and to generate an interrupt request to the interrupt controller. The
interrupt generated according to this interrupt request can cause the device to wake up from
standby mode and return to its normal operating state. Therefore, the operating mode of the
device can be changed when a signal is input to the external interrupt pin.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.2 Configuration of External Interrupt Circuit
MB95410H/470H Series
16.2
Configuration of External Interrupt Circuit
The external interrupt circuit consists of the following blocks:
• Edge detection circuit
• External interrupt control register
■ Block Diagram of External Interrupt Circuit
Figure 16.2-1 is the block diagram of the external interrupt circuit.
Figure 16.2-1 Block Diagram of External Interrupt Circuit
Edge detection circuit 1
01
11
External interrupt
control register
(EIC)
EIR1
SL11
SL10
11
EIE1
EIR0
SL01
SL00
EIE0
Internal data bus
01
Pin
INT01
10
Selector
10
Edge detection circuit 0
Selector
Pin
INT00
Interrupt request 0
Interrupt request 1
● Edge detection circuit
When the polarity of the edge detected on a signal input to an external interrupt circuit pin
(INT) matches the polarity of the edge selected in the interrupt control register (EIC), a
corresponding external interrupt request flag bit (EIR) is set to "1".
● External interrupt control register (EIC)
This register is used to select an edge, enable or disable interrupt requests, check for interrupt
requests, etc.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.3 Channels of External Interrupt Circuit
MB95410H/470H Series
Channels of External Interrupt Circuit
16.3
This section describes the channels of the external interrupt circuit.
■ Channels of External Interrupt Circuit
The MB95410H/470H Series has 4 units of external interrupt circuit.
Table 16.3-1 shows the pins of the external interrupt circuit.
Table 16.3-1 Pins of External Interrupt Circuit
Unit
1
2
3
4
Pin name
Pin function
INT00
External interrupt input ch. 0
INT01
External interrupt input ch. 1
INT02
External interrupt input ch. 2
INT03
External interrupt input ch. 3
INT04
External interrupt input ch. 4
INT05
External interrupt input ch. 5
INT06
External interrupt input ch. 6
INT07
External interrupt input ch. 7
Table 16.3-2 Registers of External Interrupt Circuit
Unit
Register abbreviation
1
EIC00
2
EIC10
3
EIC20
4
EIC30
Corresponding register (Name in this manual)
EIC: External Interrupt Control register
In the following sections, only details of unit 1of the external interrupt circuit are provided.
Details of other units of the external interrupt circuit are the same as those of unit 1.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.4 Pins of External Interrupt Circuit
MB95410H/470H Series
16.4
Pins of External Interrupt Circuit
This section provides details of the pins of the external interrupt circuit and the
block diagrams of such pins.
■ Pins of External Interrupt Circuit
In the MB95410H/470H Series, the pins of the external interrupt circuit are the INT00 to
INT07 pins.
● INT00 to INT07 pins
These pins serve both as external interrupt input pins and as general-purpose I/O ports.
INT00 to INT07:
If a pin of INT00 to INT07 is set as an input port by the port direction
register (DDR) and the corresponding external interrupt input is enabled
by the external interrupt control register (EIC), that pin functions as an
external interrupt input pin (INT00 to INT07).
The state of a pin can always be read from the port data register (PDR)
when that pin is set as an input port. However, the value of PDR is read
when the read-modify-write (RMW) type of instruction is used.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.4 Pins of External Interrupt Circuit
MB95410H/470H Series
■ Block Diagrams of Pins of External Interrupt Circuit
Figure 16.4-1 Block Diagram of INT01 and INT04 of External Interrupt Circuit
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
CMOS
Peripheral function output
0
1
PDR read
1
Hysteresis
pin
PDR
0
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
ILSR read
ILSR
ILSR write
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.4 Pins of External Interrupt Circuit
MB95410H/470H Series
Figure 16.4-2 Block Diagram of Pins INT00, INT02, INT03, INT05, INT06 and INT07 of External
Interrupt Circuit
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
PDR
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.5 Registers of External Interrupt Circuit
16.5
MB95410H/470H Series
Registers of External Interrupt Circuit
This section describes the registers of the external interrupt circuit.
■ Registers of External Interrupt Circuit
Figure 16.5-1 shows the registers of the external interrupt circuit.
Figure 16.5-1 Registers of External Interrupt Circuit
External interrupt control register (EIC)
Address
bit7
bit6
0048H
EIR1
SL11
EIC00
R(RM1),W
R/W
bit7
bit6
0049H
EIC10
EIR1
SL11
R(RM1),W
R/W
bit7
bit6
004AH
EIR1
SL11
EIC20
R(RM1),W
R/W
bit7
bit6
004BH
EIC30
EIR1
SL11
R(RM1),W
R/W
R/W
R(RM1), W
326
bit5
SL10
R/W
bit5
SL10
R/W
bit5
SL10
R/W
bit5
SL10
R/W
bit4
EIE1
R/W
bit4
EIE1
R/W
bit4
EIE1
R/W
bit4
EIE1
R/W
bit3
EIR0
R(RM1),W
bit3
EIR0
R(RM1),W
bit3
EIR0
R(RM1),W
bit3
EIR0
R(RM1),W
bit2
SL01
R/W
bit2
SL01
R/W
bit2
SL01
R/W
bit2
SL01
R/W
bit1
SL00
R/W
bit1
SL00
R/W
bit1
SL00
R/W
bit1
SL00
R/W
bit0
EIE0
R/W
bit0
EIE0
R/W
bit0
EIE0
R/W
bit0
EIE0
R/W
Initial value
00000000B
Initial value
00000000B
Initial value
00000000B
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the read-modifywrite (RMW) type of instruction.)
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.5 Registers of External Interrupt Circuit
MB95410H/470H Series
16.5.1
External Interrupt Control Register (EIC00)
The external interrupt control register (EIC00) is used to select the edge
polarity for the external interrupt input and control interrupts.
■ External Interrupt Control Register (EIC00)
Figure 16.5-2 External Interrupt Control Register (EIC00)
EIC00
EIC10
EIC20
EIC30
Address bit7
bit6
0048H
0049H
EIR1 SL11
004AH
004BH R(RM1),W R/W
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
SL10
EIE1
EIR0
SL01
SL00
EIE0
00000000B
R/W
R/W R(RM1),W R/W
R/W
R/W
EIE0
0
1
SL01
0
0
1
1
Interrupt request enable bit 0
Disables output of interrupt request.
Enables output of interrupt request.
SL00
0
1
0
1
Edge polarity select bits 0
No edge detection
Rising edge
Falling edge
Both edges
External interrupt request flag bit 0
Write
Read
EIR0
0
Specified edge not input
Clears this bit
1
Specified edge input
No change, no effect on others
EIE1
0
1
SL11
0
0
1
1
Interrupt request enable bit 1
Disables output of interrupt request.
Enables output of interrupt request.
SL10
0
1
0
1
Edge polarity select bits 1
No edge detection
Rising edge
Falling edge
Both edges
0
External interrupt request flag bit 1
Read
Write
Specified edge not input
Clears this bit
1
Specified edge input
EIR1
No change, no effect on others
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
: Initial value
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.5 Registers of External Interrupt Circuit
MB95410H/470H Series
Table 16.5-1 Functions of Bits in External Interrupt Control Register (EIC00)
Bit name
bit7
bit6,
bit5
bit4
bit3
bit2,
bit1
bit0
328
Function
EIR1:
External interrupt
request flag bit 1
This flag is set to "1" when the edge selected by the edge polarity select bits (SL11, SL10)
is input to the external interrupt pin INT01.
• When this bit and the interrupt request enable bit 1 (EIE1) are set to "1", an interrupt
request is output.
• Writing "0" clears the bit. Writing "1" has no effect on operation.
• If this bit is read by the read-modify-write (RMW) type of instruction, it returns "1".
SL11, SL10:
Edge polarity select
bits 1
These bits select the polarity of an edge of the pulse input to the external interrupt pin
INT01. The edge selected is to be the interrupt source.
• If these bits are set to "00B", edge detection is not performed and no interrupt request is
made.
• If these bits are set to "01B", rising edges are to be detected; if "10B", falling edges are to
be detected; if "11B", both edges are to be detected.
EIE1:
Interrupt request
enable bit 1
This bit is used to enable and disable output of interrupt requests to the interrupt controller.
When this bit and the external interrupt request flag bit 1 (EIR1) are "1", an interrupt
request is output.
• When using an external interrupt pin, write "0" to the corresponding bit in the port
direction register (DDR) to set the pin as an input port.
• The status of the external interrupt pin can be read directly from the port data register,
regardless of the status of the interrupt request enable bit.
EIR0:
External interrupt
request flag bit 0
This flag is set to "1" when the edge selected by the edge polarity select bits (SL01, SL00)
is input to the external interrupt pin INT00.
• When this bit and the interrupt request enable bit 0 (EIE0) are set to "1", an interrupt
request is output.
• Writing "0" clears the bit. Writing "1" has no effect on operation.
• If this bit is read by the read-modify-write (RMW) type of instruction, it returns "1".
SL01, SL00:
Edge polarity select
bits 0
These bits select the polarity of an edge of the pulse input to the external interrupt pin
INT00. The edge selected is to be the interrupt source.
• If these bits are set to "00B", edge detection is not performed and no interrupt request is
made.
• If these bits are set to "01B", rising edges are to be detected; if "10B", falling edges are to
be detected; if "11B", both edges are to be detected.
EIE0:
Interrupt request
enable bit 0
This bit enables or disables the output of interrupt requests to the interrupt controller. An
interrupt request is output when this bit and the external interrupt request flag bit 0 (EIR0)
are "1".
• When using an external interrupt pin, write "0" to the corresponding bit in the port
direction register (DDR) to set the pin as an input port.
• The status of the external interrupt pin can be read directly from the port data register,
regardless of the status of the interrupt request enable bit.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.6 Interrupts of External Interrupt Circuit
MB95410H/470H Series
16.6
Interrupts of External Interrupt Circuit
The interrupt sources for the external interrupt circuit include detection of the
specified edge of the signal input to an external interrupt pin.
■ Interrupt During Operation of External Interrupt Circuit
When the specified edge of external interrupt input is detected, the corresponding external
interrupt request flag bit (EIC: EIR0, EIR1) is set to "1". In this case, if the interrupt request
enable bit (EIC: EIE0, EIE1 = 1) corresponding to that external interrupt request flag bit is
enabled, an interrupt request is generated to the interrupt controller. In an interrupt service
routine, write "0" to the external interrupt request flag bit corresponding to that interrupt
request generated to clear the interrupt request.
■ Registers and Vector Table Addresses Related to Interrupts of External
Interrupt Circuit
Table 16.6-1 Registers and Vector Table Addresses Related to Interrupts of External Interrupt
Circuit
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
Interrupt
request no.
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
IRQ00
ILR0
L00
FFFAH
FFFBH
IRQ01
ILR1
L01
FFF8H
FFF9H
IRQ02
ILR2
L02
FFF6H
FFF7H
IRQ03
ILR3
L03
FFF4H
FFF5H
ch.: Channel
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.7 Operations of External Interrupt Circuit and Setting
Procedure Example
16.7
MB95410H/470H Series
Operations of External Interrupt Circuit and Setting
Procedure Example
This section describes the operations of the external interrupt circuit.
■ Operations of External Interrupt Circuit
When the polarity of an edge of a signal input from one of the external interrupt pins (INT00,
INT01) matches the polarity of the edge selected by the external interrupt control register
(EIC:SL00, SL01, SL10, SL11), the corresponding external interrupt request flag bit
(EIC:EIR0, EIR1) is set to "1" and the interrupt request is generated.
Always set the interrupt request enable bit to "0" when not using an external interrupt to wake
up the device from standby mode.
When setting the edge polarity select bit (SL), set the interrupt request enable bit (EIE) to "0"
to prevent the interrupt request from being generated accidentally. Also clear the interrupt
request flag bit (EIR) to "0" after changing the edge polarity.
Figure 16.7-1 shows the operations for setting the INT00 pin as an external interrupt input.
Figure 16.7-1 Operations of External Interrupt
Input waveform
to INT00 pin
Cleared by
program
Interrupt request flag bit cleared
by program
EIR0 bit
EIE0 bit
SL01 bit
SL00 bit
IRQ
No edge
detection
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Rising edge
Falling edge
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Both edges
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■ Setting Procedure Example
CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.7 Operations of External Interrupt Circuit and Setting
Procedure Example
Below is an example of procedure for setting the external interrupt circuit.
● Initial settings
1) Set the interrupt level. (ILR0)
2) Select the edge polarity. (EIC:SL01, SL00)
3) Enable interrupt requests. (EIC:EIE0 = 1)
● Interrupt processing
1) Clear the interrupt request flag. (EIC:EIR0 = 0)
2) Process any interrupt.
Note:
An external interrupt input port shares the same pin with an I/O port. Therefore, when
using the pin as an external interrupt input port, set the bit in the port direction register
(DDR) corresponding to that pin to "0" (input).
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.8 Notes on Using External Interrupt Circuit
16.8
MB95410H/470H Series
Notes on Using External Interrupt Circuit
This section provides notes on using the external interrupt circuit.
■ Notes on Using External Interrupt Circuit
• Prior to setting the edge polarity select bit (SL), set the interrupt request enable bit (EIE) to
"0" (disabling interrupt requests). In addition, clear the external interrupt request flag bit
(EIR) to "0" after setting the edge polarity.
• The external interrupt circuit cannot wake up from the interrupt service routine if the
external interrupt request flag bit is "1" and the interrupt request enable bit is enabled. In the
interrupt service routine, always clear the external interrupt request flag bit.
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.9 Sample Settings for External Interrupt Circuit
MB95410H/470H Series
16.9
Sample Settings for External Interrupt Circuit
This section provides sample settings for the external interrupt circuit.
■ Sample Settings
● Detection levels and setting methods
Four detection levels are available: no edge detection, rising edge, falling edge, both edges
The detection level bits (EIC:SL01, SL00 or EIC:SL11, SL10) are used.
Operating mode
Detection level bits (SL01, SL00 or SL11, SL10)
No edge detection
Set the bits to "00B"
Detecting rising edges
Set the bits to "01B"
Detecting falling edges
Set the bits to "10B"
Detecting both edges
Set the bits to "11B"
● How to use the external interrupt pin
Set a corresponding bit in the data direction register (DDR0) to "0".
Operation
Direction bit
(P00 to P07)
Setting
Using INT00 pin for external interrupt
DDR0: P00
Set the bit to "0".
Using INT01 pin for external interrupt
DDR0: P01
Set the bit to "0".
Using INT02 pin for external interrupt
DDR0: P02
Set the bit to "0".
Using INT03 pin for external interrupt
DDR0: P03
Set the bit to "0".
Using INT04 pin for external interrupt
DDR0: P04
Set the bit to "0".
Using INT05 pin for external interrupt
DDR0: P05
Set the bit to "0".
Using INT06 pin for external interrupt
DDR0: P06
Set the bit to "0".
Using INT07 pin for external interrupt
DDR0: P07
Set the bit to "0".
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CHAPTER 16 EXTERNAL INTERRUPT CIRCUIT
16.9 Sample Settings for External Interrupt Circuit
MB95410H/470H Series
● Interrupt-related registers
The interrupt level is set by the interrupt level setting registers shown in the following table.
Channel
Interrupt level setting register
Interrupt vector
ch. 0
Interrupt level setting register (ILR0)
Address: 00079H
#0
Address: 0FFFAH
ch. 1
Interrupt level setting register (ILR0)
Address: 00079H
#1
Address: 0FFF8H
ch. 2
Interrupt level setting register (ILR0)
Address: 00079H
#2
Address: 0FFF6H
ch. 3
Interrupt level setting register (ILR0)
Address: 00079H
#3
Address: 0FFF4H
ch. 4
Interrupt level setting register (ILR0)
Address: 00079H
#0
Address: 0FFFAH
ch. 5
Interrupt level setting register (ILR0)
Address: 00079H
#1
Address: 0FFF8H
ch. 6
Interrupt level setting register (ILR0)
Address: 00079H
#2
Address: 0FFF6H
ch. 7
Interrupt level setting register (ILR0)
Address: 00079H
#3
Address: 0FFF4H
● How to enable/disable/clear interrupt requests
Interrupts requests are enabled/disabled by the interrupt request enable bit (EIC00:EIE0 or
EIE1).
Operation
Interrupt request enable bit (EIE0 or EIE1)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
Interrupt requests are cleared by the interrupt request bit (EIC00: EIR0 or EIR1).
334
Operation
Interrupt request bit (EIR0 or EIR1)
To clear an interrupt request
Set the bit to "0".
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CHAPTER 17
INTERRUPT PIN
SELECTION CIRCUIT
This chapter describes the functions and
operations of the interrupt pin selection circuit.
17.1 Overview of Interrupt Pin Selection Circuit
17.2 Configuration of Interrupt Pin Selection Circuit
17.3 Pins of Interrupt Pin Selection Circuit
17.4 Register of Interrupt Pin Selection Circuit
17.5 Operation of Interrupt Pin Selection Circuit
17.6 Notes on Using Interrupt Pin Selection Circuit
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.1 Overview of Interrupt Pin Selection Circuit
17.1
MB95410H/470H Series
Overview of Interrupt Pin Selection Circuit
The interrupt pin selection circuit selects pins to be used as interrupt input
pins from among various peripheral input pins.
■ Interrupt Pin Selection Circuit
The interrupt pin selection circuit is used to select interrupt input pins from amongst various
peripheral inputs (UCK0, UI0, EC0, INT00). The input signal from each peripheral function
pin is selected by this circuit and the signal is used as the INT00 (channel 0) input of external
interrupt. This enables the input signals to the peripheral function pins to also serve as external
interrupt pins.
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.2 Configuration of Interrupt Pin Selection Circuit
MB95410H/470H Series
17.2
Configuration of Interrupt Pin Selection Circuit
Figure 17.2-1 shows the block diagram of the interrupt pin selection circuit.
■ Block Diagram of Interrupt Pin Selection Circuit
Figure 17.2-1 Block Diagram of Interrupt Pin Selection Circuit
To each peripheral function
External
interrupt
circuit
INT01
INT01
P01
Interrupt pin selection circuit
Selection circuit
INT00
P00
UI0
P10
INT00
(Unit 0)
Internal data bus
UCK0
P14
EC0
P51
WICR register
• WICR register (interrupt pin selection circuit control register)
This register is used to determine which of the available peripheral input pins should be
outputted to the interrupt circuit and which interrupt pins they should serve as.
• Selection circuit
This circuit outputs the input from the pin selected by the WICR register to the INT00 input
of the external interrupt circuit (channel 0).
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.3 Pins of Interrupt Pin Selection Circuit
17.3
MB95410H/470H Series
Pins of Interrupt Pin Selection Circuit
This section describes the pins of the interrupt pin selection circuit.
■ Pins of Interrupt Pin Selection Circuit
The peripheral function pins of the interrupt pin selection circuit are the UCK0, UI0, EC0 and
INT00 pins. These inputs (except INT00) are also connected to their respective peripheral units
in parallel and can be used for both functions simultaneously. Table 17.3-1 shows the
correspondence between the peripheral functions and peripheral input pins.
Table 17.3-1 Correspondence between Peripheral Functions and Peripheral
Input Pins
Peripheral input pin
name
INT00
338
Peripheral functions name
Interrupt pin selection circuit
UCK0
UART/SIO (clock input/output)
UI0
UART/SIO (data input)
EC0
8/16-bit composite timer (event input)
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.4 Register of Interrupt Pin Selection Circuit
MB95410H/470H Series
17.4
Register of Interrupt Pin Selection Circuit
Figure 17.4-1 shows the register of the interrupt pin selection circuit.
■ Register of Interrupt Pin Selection Circuit
Figure 17.4-1 Register of Interrupt Pin Selection Circuit
Interrupt pin selection circuit control register (WICR)
Address bit7
bit6
bit5
bit4
bit3
0FEFH
INT00
EC0
R0/WX R/W R0/WX R0/WX R/W
R/W
R0/WX
-
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bit2
UI0
R/W
bit1
bit0
UCK0
R/W R0/WX
Initial value
01000000B
: Readable/writable (The read value is the same as the write value.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.4 Register of Interrupt Pin Selection Circuit
17.4.1
MB95410H/470H Series
Interrupt Pin Selection Circuit Control Register
(WICR)
This register is used to determine which of the available peripheral input pins
should be outputted to the interrupt circuit and which interrupt pins they
should serve as.
■ Interrupt Pin Selection Circuit Control Register (WICR)
Figure 17.4-2 Interrupt Pin Selection Circuit Control Register (WICR)
Address
0FEFH
bit7
-
bit6
INT00
bit5
-
bit4
-
bit3
EC0
bit2
UI0
R0WX R/W R0/WX R0/WX R/W
R/W
bit1
UCK0
Deselects UCK0 as an interrupt input pin.
1
Selects UCK0 as an interrupt input pin.
UI0 interrupt pin select bit
0
Deselects UI0 as an interrupt input pin.
1
Selects UI0 as an interrupt input pin.
EC0
340
UCK0 interrupt pin select bit
0
UI0
:
:
:
:
Initial value
01000000B
R/W R0/WX
UCK0
R/W
R0/WX
-
bit0
-
EC0 interrupt pin select bit
0
Deselects EC0 as an interrupt input pin.
1
Selects EC0 as an interrupt input pin.
INT00
INT00 interrupt pin select bit
0
Deselects INT00 as an interrupt input pin.
1
Selects INT00 as an interrupt input pin.
Readable/writable (The read value is the same as the write value.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.4 Register of Interrupt Pin Selection Circuit
Table 17.4-1 Functions of Bits in Interrupt Pin Selection Circuit Control Register (WICR)
Bit name
bit7
Function
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
bit6
INT00:
INT00 interrupt pin
select bit
This bit is used to determine whether to select the INT00 pin as an interrupt input pin.
Writing "0": Deselects the INT00 pin as an interrupt input pin and the circuit treats the
INT00 pin input as being fixed at "0".
Writing "1": Selects the INT00 pin as an interrupt input pin and the circuit passes the
INT00 pin input to INT00 (channel 0) of the external interrupt circuit. In this
case, the input signal to the INT00 pin can generate an external interrupt if
INT00 (channel 0) operation is enabled in the external interrupt circuit.
bit5,
bit4
Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
This bit is used to determine whether to select the EC0 pin as an interrupt input pin.
Writing "0": Deselects the EC0 pin as an interrupt input pin and the circuit treats the EC0
pin input as being fixed at "0".
Writing "1": Selects the EC0 pin as an interrupt input pin and the circuit passes the EC0
pin input to INT00 (channel 0) of the external interrupt circuit. In this case,
the input signal to the EC0 pin can generate an external interrupt if INT00
(channel 0) operation is enabled in the external interrupt circuit.
bit3
EC0:
EC0 interrupt pin
select bit
bit2
This bit is used to determine whether to select the UI0 pin as an interrupt input pin.
Writing "0": Deselects the UI0 pin as an interrupt input pin and the circuit treats the UI0
UI0:
pin input as being fixed at "0".
UI0 interrupt pin select Writing "1": Selects the UI0 pin as an interrupt input pin and the circuit passes the UI0
bit
pin input to INT00 (channel 0) of the external interrupt circuit. In this case,
the input signal to the UI0 pin can generate an external interrupt if INT00
(channel 0) operation is enabled in the external interrupt circuit.
bit1
UCK0:
UCK0 interrupt pin
select bit
This bit is used to determine whether to select the UCK0 pin as an interrupt input pin.
Writing "0": Deselects the UCK0 pin as an interrupt input pin and the circuit treats the
UCK0 pin input as being fixed at "0".
Writing "1": Selects the UCK0 pin as an interrupt input pin and the circuit passes the
UCK0 pin input to INT00 (channel 0) of the external interrupt circuit. In this
case, the input signal to the UCK0 pin can generate an external interrupt if
INT00 (channel 0) operation is enabled in the external interrupt circuit.
bit0
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
When these bits are set to "1" and the operation of INT00 (ch. 0) of the external interrupt
circuit is enabled in MCU standby mode, the selected pins are enabled to perform input
operation. The MCU wakes up from the standby mode when a valid edge pulse is input to the
pins. For information about the standby modes, see "6.9 Operations in Low-power
Consumption Mode (Standby Mode)".
Note:
The input signals to the peripheral pins do not generate an external interrupt even when
"1" is written to these bits if the INT00 (ch. 0) of the external interrupt circuit is disabled.
Do not modify the values of these bits while the INT00 (ch. 0) of the external interrupt
circuit is enabled. If modified, the external interrupt circuit may detect a valid edge,
depending on the pin input level.
If multiple interrupt pins are selected in the WICR register simultaneously and the
operation of INT00 (channel 0) of the external interrupt circuit is enabled (the values other
than "00B" are set to SL01, SL00 bits in EIC00 register of external interrupt circuit.), the
selected pins will remain enabled to perform input so as to accept interrupts even in a
standby mode.
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CHAPTER 17 INTERRUPT PIN SELECTION CIRCUIT
17.5 Operation of Interrupt Pin Selection Circuit
17.5
MB95410H/470H Series
Operation of Interrupt Pin Selection Circuit
The interrupt pins are selected by setting WICR (interrupt pin selection circuit
control register).
■ Operation of Interrupt Pin Selection Circuit
The WICR (interrupt pin selection circuit control register) setting is used to select the input
pins to be input to INT00 of the external interrupt circuit (ch. 0). Shown below is the setup
procedure for the interrupt pin selection circuit and external interrupt circuit (channel 0), which
must be followed when selecting the UCK0 pin as an interrupt pin.
1) Write "0" to the corresponding bit in the port direction register (DDR) to set the pin as an
input.
2) Select the UCK0 pin as an interrupt input pin in WICR (interrupt pin selection circuit
control register).
- Write "02H" to the WICR register. At this point, after writing "0" in the EIE0 bit of the
EIC00 register of the external interrupt circuit, the operation of the external interrupt
circuit is disabled.)
3) Enable the operation of INT00 of the external interrupt circuit (ch. 0).
- Set the SL01 and SL00 bits of the EIC00 register to any value other than "00B" in the
external interrupt circuit to select the valid edge. Also write "1" to the EIE0 bit to enable
interrupts).
4) The subsequent interrupt operation is the same as for the external interrupt circuit.
- When a reset is released, the WICR register is initialized to "40H" and the INT00 bit is
selected as the only available interrupt pin. Update the value of this register before
enabling the operation of the external interrupt circuit, when using any pins other than
the INT00 pin as external interrupt pins.
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17.6 Notes on Using Interrupt Pin Selection Circuit
MB95410H/470H Series
17.6
Notes on Using Interrupt Pin Selection Circuit
This section provides notes on using the interrupt pin selection circuit.
• The WICR register is initialized to "40H" after a reset. This selects the INT00 bit only as an
interrupt pin. If using pins other than the INT00 pin as external interrupt pins, update the
value of this register before enabling the operation of the external interrupt circuit.
• If multiple interrupt pins are selected in the WICR register simultaneously and the operation
of INT00 (ch. 0) of the external interrupt circuit is enabled (Set the SL01 and SL00 bits in
the EIC00 register to any value other than "00B" in the external interrupt circuit to select the
valid edge. Also write "1" to the EIE0 bit to enable interrupts.), the selected pins will remain
enabled to perform input so as to accept interrupts even in a standby mode.
• If multiple interrupt pins are selected in the WICR register simultaneously, an input to
INT00 (ch. 0) of the external interrupt circuit is treated as "H" if a signal input to one of the
selected interrupt pins is "H". (It becomes "OR" of the signals input to the selected pins.)
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17.6 Notes on Using Interrupt Pin Selection Circuit
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CHAPTER 18
8/16-BIT COMPOSITE
TIMER
This chapter describes the functions and
operations of the 8/16-bit composite timer.
18.1 Overview of 8/16-bit Composite Timer
18.2 Configuration of 8/16-bit Composite Timer
18.3 Channels of 8/16-bit Composite Timer
18.4 Pins of 8/16-bit Composite Timer
18.5 Registers of 8/16-bit Composite Timer
18.6 Interrupts of 8/16-bit Composite Timer
18.7 Operation of Interval Timer Function (One-shot Mode)
18.8 Operation of Interval Timer Function (Continuous
Mode)
18.9 Operation of Interval Timer Function (Free-run Mode)
18.10 Operation of PWM Timer Function (Fixed-cycle Mode)
18.11 Operation of PWM Timer Function (Variable-cycle
Mode)
18.12 Operation of PWC Timer Function
18.13 Operation of Input Capture Function
18.14 Operation of Noise Filter
18.15 States in Each Mode during Operation
18.16 Notes on Using 8/16-bit Composite Timer
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.1 Overview of 8/16-bit Composite Timer
18.1
MB95410H/470H Series
Overview of 8/16-bit Composite Timer
The 8/16-bit composite timer consists of two 8-bit counters. It can be used as
two 8-bit timers, or as a 16-bit timer if the two counters are connected in
cascade.
The 8/16-bit composite timer has the following functions:
• Interval timer function
• PWM timer function
• PWC timer function (pulse width measurement)
• Input capture function
■ Interval Timer Function (One-shot Mode)
When the interval timer function (one-shot mode) is selected, the counter starts counting from
"00H" as the timer is started. When the counter value matches the value of the 8/16-bit
composite timer 00/01 data register, the timer output is inverted, an interrupt request occurs,
and the counter stops counting.
■ Interval Timer Function (Continuous Mode)
When the interval timer function (continuous mode) is selected, the counter starts counting
from "00H" as the timer is started. When the counter value matches the value of the 8/16-bit
composite timer 00/01 data register, the timer output is inverted, an interrupt request occurs,
and the counter counts from "00H" again. The timer outputs square wave as a result of this
repeated operation.
■ Interval Timer Function (Free-run Mode)
When the interval timer function (free-run mode) is selected, the counter starts counting from
"00H". When the counter value matches the value of the 8/16-bit composite timer 00/01 data
register, the timer output is inverted and an interrupt request occurs. Under these conditions, if
the counter continues to count and reaches "FFH", it restarts counting from "00H". The timer
outputs square wave as a result of this repeated operation.
■ PWM Timer Function (Fixed-cycle Mode)
When the PWM timer function (fixed-cycle mode) is selected, a PWM signal with a variable
"H" pulse width is generated in fixed cycles. The cycle is fixed to be "FFH" during 8-bit
operation or "FFFFH" during 16-bit operation. The time is determined by the count clock
selected. The "H" pulse width is specified by setting a specific register.
■ PWM Timer Function (Variable-cycle Mode)
When the PWM timer function (variable-cycle mode) is selected, two 8-bit counters are used to
generate an 8-bit PWM signal of variable cycle and duty depending on the cycle and "L" pulse
width specified by registers.
In this operating mode, since the two 8-bit counters have to be used separately, the composite
timer cannot operate as a 16-bit counter.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.1 Overview of 8/16-bit Composite Timer
■ PWC Timer Function
When the PWC timer function is selected, the width and cycle of an external input pulse can be
measured.
In this operating mode, the counter starts counting from "00H" immediately after a count start
edge of an external input signal is detected. Afterward, when a count end edge is detected, the
counter transfers its value to a register to generate an interrupt.
■ Input Capture Function
When the input capture function is selected, the counter value is stored in a register
immediately after the detection of an edge of an external input signal.
This function is available in either free-run mode or clear mode for count operation.
In clear mode, the counter starts counting from "00H", and transfers its value to a register to
generate an interrupt after an edge is detected. Afterward, the counter restarts counting from
"00H".
In free-run mode, the counter transfers its value to a register to generate an interrupt
immediately after the detection of an edge. Afterward, unlike in clear mode, the counter
continues to count without being cleared to "00H".
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.2 Configuration of 8/16-bit Composite Timer
18.2
MB95410H/470H Series
Configuration of 8/16-bit Composite Timer
The 8/16-bit composite timer consists of the following blocks:
• 8-bit counter × 2 channels
• 8-bit comparator (including a temporary latch) × 2 channels
• 8/16-bit composite timer 00/01 data register × 2 channels (T00DR/T01DR),
(T10DR/T11DR)
• 8/16-bit composite timer 00/01 status control register 0 × 2 channels (T00CR0/
T01CR0), (T10CR0/T11CR0)
• 8/16-bit composite timer 00/01 status control register 1 × 2 channels (T00CR1/
T01CR1), (T10CR1/T11CR1)
• 8/16-bit composite timer 00/01 timer mode control register (TMCR0), (TMCR1)
• Output controller × 2 channels
• Control logic × 2 channels
• Count clock selector × 2 channels
• Edge detector × 2 channels
• Noise filter × 2 channels
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18.2 Configuration of 8/16-bit Composite Timer
MB95410H/470H Series
■ Block Diagram of 8/16-bit Composite Timer
Figure 18.2-1 Block Diagram of 8/16-bit Composite Timer
T00CR0
IFE C2 C1 C0 F3 F2 F1 F0
(T10CR0)
CK00
:
:
Count
clock
selector
CK07
Noise
filter
Control logics
8-bit counter
Clocks from
:
prescaler/
:
Time Base Timer CK06
EC00
(EC10)
Timer 00(Timer 10)
8-bit comparator
Output
controller
Timer output
TO00(TO10)
ENO0
8-bit data register
Edge
detector
STA HO IE
IR BF IF SO OE
T00CR1
(T10CR1)
IRQ05(IRQ22)
IRQ
logic
TMCR0(TMCR1)
TO1 TO0
EC0
(EC1)
TIS MOD FE11 FE10 FE01 FE00
T01CR0
IFE C2 C1 C0 F3 F2 F1 F0
(T11CR0)
IRQ06(IRQ14)
16-bit mode control signal
Timer 01(Timer 11)
16-bit mode clock
8-bit counter
:
:
Count
clock
selector
CK17
External
input
EC01
(EC11)
Noise
filter
Control logics
CK10
Clocks from
:
prescaler/
:
Time Base CK16
Timer
8-bit comparator
Output
controller
Timer output
TO01(TO11)
ENO1
8-bit data register
Edge
detector
T01CR1
STA HO IE IR BF IF SO OE
(T11CR1)
Note: Names in parentheses are those used in timer 10 and timer 11.
● 8-bit counter
This counter serves as the basis for various timer operations. It can be used either as two 8-bit
counters or as a 16-bit counter.
● 8-bit comparator
The comparator compares the value in the 8/16-bit composite timer 00/01 data register and that
in the counter. It incorporates a latch that temporarily stores the 8/16-bit composite timer 00/01
data register value.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.2 Configuration of 8/16-bit Composite Timer
MB95410H/470H Series
● 8/16-bit composite timer 00/01 data register (T00DR/T01DR) [8/16-bit composite timer 10/
11 data register (T10DR/T11DR)]
This register is used to write the maximum value counted during interval timer operation or
PWM timer operation and to read the count value during PWC timer operation or input capture
operation.
● 8/16-bit composite timer 00/01 status control registers 0 (T00CR0/T01CR0) [8/16-bit
composite timer 10/11 status control registers 0 (T10CR0/T11CR0)]
These registers are used to select the timer operating mode and the count clock, and to enable
or disable IF flag interrupts.
● 8/16-bit composite timer 00/01 status control registers 1 (T00CR1/T01CR1) [8/16-bit
composite timer 10/11 status control registers 1 (T10CR1/T11CR1)]
These registers are used to control interrupt flags, timer output, and timer operation.
● 8/16-bit composite timer 00/01 timer mode control register (TMCR0) [8/16-bit composite
timer 10/11 timer mode control register (TMCR1)]
This register is used to select the noise filter function, 8-bit or 16-bit operating mode, and
signal input to timer 00 and to indicate the timer output value.
● Output controller
The output controller controls timer output. The timer output is supplied to the external pin
when the pin output has been enabled.
● Control logic
The control logic controls timer operation.
● Count clock selector
The selector selects the counter operating clock signal from different prescaler output signals
(divided machine clock signal and time-base timer output signal).
● Edge detector
The edge detector selects the edge of an external input signal to be used as an event for PWC
timer operation or input capture operation.
● Noise filter
This filter serves as a noise filter for external input signals. The filter function can be selected
from "H" pulse noise elimination, "L" pulse noise elimination, and "H"/"L"-pulse noise
elimination.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.2 Configuration of 8/16-bit Composite Timer
■ Input Clock
The 8/16-bit composite timer uses the output clock from the prescaler as its input clock (count
clock).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.3 Channels of 8/16-bit Composite Timer
MB95410H/470H Series
Channels of 8/16-bit Composite Timer
18.3
This section describes the channels of the 8/16-bit composite timer.
■ Channels of 8/16-bit Composite Timer
The MB95410H/470H Series has two channels of 8/16-bit composite timer.
In a channel, there are two 8-bit counters. They can be used as two 8-bit timers or one 16-bit
timer. The following table lists the external pins and registers corresponding to each channel.
Table 18.3-1 8/16-bit Composite Timer Channels and Corresponding External Pins
Channel
0
1
Pin name
Pin function
TO00
Timer 00 output
TO01
Timer 01 output
EC0
Timer 00 input and timer 01 input
TO10
Timer 10 output
TO11
Timer 11 output
EC1
Timer 10 input and timer 11 input
Table 18.3-2 8/16-bit Composite Timer Channels and Corresponding Registers
Channel
0
1
Register
abbreviation
Corresponding register (Name in this manual)
T00CR0
Timer 00 status control register 0
T01CR0
Timer 01 status control register 0
T00CR1
Timer 00 status control register 1
T01CR1
Timer 01 status control register 1
T00DR
Timer 00 data register
T01DR
Timer 01 data register
TMCR0
Timer 00/01 timer mode control register
T10CR0
Timer 10 status control register 0
T11CR0
Timer 11 status control register 0
T10CR1
Timer 10 status control register 1
T11CR1
Timer 11 status control register 1
T10DR
Timer 10 data register
T11DR
Timer 11 data register
TMCR1
Timer 10/11 timer mode control register
In the following sections in this chapter, only details of channel 0 of the 8/16-bit composite
timer are provided.
Channel 0 and channel 1 have identical configuration. The 2-digit number in a pin name and a
register abbreviation corresponds to channel and timer. The upper number corresponds to
channel and the lower number corresponds to timer.
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18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
18.4
Pins of 8/16-bit Composite Timer
This section describes the pins of the 8/16-bit composite timer.
■ Pins of 8/16-bit Composite Timer
The external pins of the 8/16-bit composite timer are TO00, TO01, TO10, TO11, EC0 and
EC1.
● TO00 pin
TO00:
This pin serves as the timer output pin for timer 00 in 8-bit operation or for timers 00 and 01
in 16-bit operation. When the output is enabled (T00CR1:OE = 1) in the interval timer
function, PWM timer function, or PWC timer function, this pin becomes an output pin
automatically regardless of the setting of the port direction register (DDR5:bit2 in the
MB95410H Series, DDR0:bit1 in the MB95470H Series) and functions as the timer output
TO00 pin.
The output becomes undetermined if output is enabled with the input capture function in
use.
● TO01 pin
TO01:
This pin serves as the timer output pin for timer 01 in 8-bit operation. When the output is
enabled (T01CR1:OE = 1) in interval timer function, PWM timer function (fixed-cycle
mode), the pin becomes an output pin automatically regardless of the setting of the port
direction register (DDR5:bit0 in the MB95410H Series, DDR1:bit3 in the MB95470H
Series) and functions as the timer output TO01 pin.
In 16-bit operation, if output is enabled with the PWM timer function (variable-cycle mode)
or input capture function in use, the output becomes undetermined.
● EC0 pin
The EC0 pin is connected to the EC00 and EC01 internal pins.
EC00 internal pin:
This pin serves as the external count clock input pin for timer 00 when the interval timer
function or PWM timer function is selected, or as the signal input pin for timer 00 when the
PWC timer function or input capture function is selected. The pin cannot be set to serve as
the external count clock input pin when the PWC timer function or input capture function is
selected.
To use the input function mentioned above, set the bit in the port direction register
corresponding to EC0 pin to "0" to make the pin as an input port.
EC01 internal pin:
This pin serves as the external count clock input pin for timer 01 when the interval timer
function or PWM timer function is selected, or as the signal input pin for timer 01 when the
PWC timer function or input capture function is selected. The pin cannot be set to serve as
the external count clock input pin when the PWC timer function or input capture function is
selected.
In 16-bit operation, the input function of this pin is not used. If the PWM timer function
(variable-cycle mode) is selected, the input function of this pin can also be used.
To use the input function mentioned above, set the bit in the port direction register
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18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
corresponding to EC0 pin to "0" to make the pin as an input port.
● TO10 pin
TO10:
This pin serves as the timer output pin for timer 10 in 8-bit operation or for timers 10 and 11
in 16-bit operation. When the output is enabled (T10CR1:OE = 1) in the interval timer
function, PWM timer function, or PWC timer function, this pin becomes an output pin
automatically regardless of the setting of the port direction register (DDRE:bit6) and
functions as the timer output TO10 pin.
The output becomes undetermined if output is enabled with the input capture function in
use.
● TO11 pin
TO11:
This pin serves as the timer output pin for timer 11 in 8-bit operation. When the output is
enabled (T11CR1:OE = 1) in interval timer function, PWM timer function (fixed-cycle
mode), or PWC timer function, the pin becomes an output pin automatically regardless of
the setting of the port direction register (DDRE:bit5) and functions as the timer output
TO11 pin.
In 16-bit operation, if output is enabled with the PWM timer function (variable-cycle mode)
or input capture function in use, the output becomes undetermined.
● EC1 pin
The EC1 pin is connected to the EC10 and EC11 internal pins.
EC10 internal pin:
This pin serves as the external count clock input pin for timer 10 when the interval timer
function or PWM timer function is selected, or as the signal input pin for timer 10 when the
PWC timer function or input capture function is selected. The pin cannot be set to serve as
the external count clock input pin when the PWC timer function or input capture function is
selected.
To use the input function mentioned above, set the bit in the port direction register
corresponding to EC1 pin to "0" to make the pin as an input port.
EC11 internal pin:
This pin serves as the external count clock input pin for timer 11 when the interval timer
function or PWM timer function is selected, or as the signal input pin for timer 11 when the
PWC timer function or input capture function is selected. The pin cannot be set to serve as
the external count clock input pin when the PWC timer function or input capture function is
selected.
In 16-bit operation, the input function of this pin is not used. If the PWM timer function
(variable-cycle mode) is selected, the input function of this pin can also be used.
To use the input function mentioned above, set the bit in the port direction register
corresponding to EC1 pin to "0" to make the pin as an input port.
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18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
■ Block Diagrams of Pins of 8/16-bit Composite Timer (MB95410H Series)
Figure 18.4-1 Block Diagram of EC0 of 8/16-bit Composite Timer
Peripheral function input
Peripheral function input enable
Pull-up
0
1
PDR read
PDR
pin
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 18.4-2 Block Diagram of TO00 and TO01 of 8/16-bit Composite Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
Figure 18.4-3 Block Diagram of EC1 of 8/16-bit Composite Timer
LCD output
Peripheral function input
Peripheral function input enable
LCD output enable
0
1
PDR read
pin
Internal bus
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
Figure 18.4-4 Block Diagram of TO10 and TO11 of 8/16-bit Composite Timer
LCD output
Peripheral function output enable
LCD output enable
Peripheral function output
0
1
PDR read
1
Internal bus
PDR
pin
0
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
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Stop, Watch (SPL=1)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
■ Block Diagrams of Pins of 8/16-bit Composite Timer (MB95470H Series)
Figure 18.4-5 Block Diagram of EC0 of 8/16-bit Composite Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 18.4-6 Block Diagram of TO00 of 8/16-bit Composite Timer
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
CMOS
Peripheral function output
0
1
PDR read
1
Hysteresis
pin
PDR
0
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
ILSR read
ILSR
ILSR write
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
Figure 18.4-7 Block Diagram of TO01 of 8/16-bit Composite Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 18.4-8 Block Diagram of EC1 of 8/16-bit Composite Timer
LCD output
Peripheral function input
Peripheral function input enable
LCD output enable
0
1
Internal bus
PDR read
pin
PDR
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
358
Stop, Watch (SPL=1)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.4 Pins of 8/16-bit Composite Timer
MB95410H/470H Series
Figure 18.4-9 Block Diagram of Pins TO10 and TO11 of 8/16-bit Composite Timer
LCD output
LCD output enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
Internal bus
PDR
0
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
MN702-00005-2v0-E
Stop, Watch (SPL=1)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
18.5
MB95410H/470H Series
Registers of 8/16-bit Composite Timer
This section describes the registers of the 8/16-bit composite timer.
■ Registers of 8/16-bit Composite Timer 0
Figure 18.5-1 Registers of 8/16-bit Composite Timer 0
8/16-bit composite timer 00/01 status control register 0 (T00CR0/T01CR0)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit0
T01CR0 0F92H
IFE
C2
C1
C0
F3
F2
F1
T00CR0 0F93H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit0
F0
R/W
Initial value
00000000B
8/16-bit composite timer 00/01 status control register 1 (T00CR1/T01CR1)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit0
STA
HO
IE
IR
BF
IF
SO
T01CR1 0036H
T00CR1 0037H
R/W
R/W
R/W R(RM1),W R/WX R(RM1),W R/W
bit0
OE
R/W
Initial value
00000000B
8/16-bit composite timer 00/01 data register (T00DR/T01DR)
Address
bit7
bit6
bit5
bit4
bit3
T01DR 0F94H TDR7 TDR6 TDR5 TDR4 TDR3
T00DR 0F95H
R,W
R,W
R,W
R,W
R,W
bit2
TDR2
R,W
bit0
TDR1
R,W
bit0
TDR0
R,W
Initial value
00000000B
8/16-bit composite timer 00/01 timer mode control register (TMCR0)
Address
bit7
bit6
bit5
bit4
bit3
bit2
0F96H
TO1
TO0
TIS
MOD FE11 FE10
R/WX R/WX
R/W
R/W
R/W
R/W
bit0
FE01
R/W
bit0
FE00
R/W
Initial value
00000000B
R/W
R(RM1), W
R/WX
R,W
360
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the
read-modify-write (RMW) type of instruction.)
: Read only (Readable. Writing a value to it has no effect on operation.)
: Readable/writable (The read value is different from the write value.)
FUJITSU SEMICONDUCTOR LIMITED
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MB95410H/470H Series
CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
■ Registers of 8/16-bit Composite Timer 1
Figure 18.5-2 Registers of 8/16-bit Composite Timer 1
8/16-bit composite timer 10/11 status control register 0 (T10CR0/T11CR0)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit0
T11CR0 0F97H
IFE
C2
C1
C0
F3
F2
F1
0F98
T10CR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
H
bit0
F0
R/W
Initial value
00000000B
8/16-bit composite timer 10/11 status control register 1 (T10CR1/T11CR1)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit0
STA
HO
IE
IR
BF
IF
SO
T11CR1 0038H
T10CR1 0039H
R/W
R/W
R/W R(RM1),W R/WX R(RM1),W R/W
bit0
OE
R/W
Initial value
00000000B
8/16-bit composite timer 10/11 data register (T10DR/T11DR)
Address
bit7
bit6
bit5
bit4
bit3
T11DR 0F99H TDR7 TDR6 TDR5 TDR4 TDR3
T10DR 0F9AH
R,W
R,W
R,W
R,W
R,W
bit2
TDR2
R,W
bit0
TDR1
R,W
bit0
TDR0
R,W
Initial value
00000000B
8/16-bit composite timer 10/11 timer mode control register (TMCR1)
Address
bit7
bit6
bit5
bit4
bit3
bit2
0F9BH
TO1
TO0
TIS
MOD FE11 FE10
R/WX R/WX
R/W
R/W
R/W
R/W
bit0
FE01
R/W
bit0
FE00
R/W
Initial value
00000000B
R/W
R(RM1),W
R/WX
R,W
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the
read-modify-write (RMW) type of instruction.)
: Read only (Readable. Writing a value to it has no effect on operation.)
: Readable/writable (The read value is different from the write value.)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
18.5.1
MB95410H/470H Series
8/16-bit Composite Timer 00/01 Status Control
Register 0 (T00CR0/T01CR0)
The 8/16-bit composite timer 00/01 status control register 0 (T00CR0/T01CR0)
selects the timer operation mode, selects the count clock, and enables or
disables IF flag interrupts. The T00CR0 and T01CR0 registers correspond to
timers 00 and 01 respectively.
■ 8/16-bit Composite Timer 00/01 Status Control Register 0 (T00CR0/T01CR0)
Figure 18.5-3 8/16-bit Composite Timer 00/01 Status Control Register 0 (T00CR0/T01CR0)
T01CR0
T00CR0
Address
0F92H
0F93H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
IFE
C2
C1
C0
F3
F2
F1
F0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F3
F2
F1
F0
0
0
0
0
Interval timer (one-shot mode)
0
0
0
1
Interval timer (continuous mode)
0
0
1
0
Interval timer (free-run mode)
0
0
1
1
PWM timer (fixed-cycle mode)
0
1
0
0
PWM timer (variable-cycle mode)
0
1
0
1
PWC timer ("H" pulse = rising to falling)
0
1
1
0
PWC timer ("L" pulse = falling to rising)
0
1
1
1
PWC timer (cycle = rising to rising)
1
0
0
0
PWC timer (cycle = falling to falling)
1
0
0
1
PWC timer ("H" pulse = rising to falling; Cycle = rising to rising)
1
0
1
0
Input capture (rising, free-run counter)
1
0
1
1
Input capture (falling, free-run counter)
1
1
0
0
Input capture (both edges, free-run counter)
1
1
0
1
Input capture (rising, counter clear)
1
1
1
0
Input capture (falling, counter clear)
1
1
1
1
Input capture (both edges, counter clear)
C2
C1
C0
0
0
0
1 × MCLK (machine clock)
0
0
1
1/2 × MCLK (machine clock)
0
1
0
1/4 × MCLK (machine clock)
0
1
1
1/8 × MCLK (machine clock)
1
0
0
1/16 × MCLK (machine clock)
1
0
1
1/32 × MCLK (machine clock)
1
1
0
1/128 × FCH or 1/64 × FCRH*
1
1
1
External clock
IFE
R/W
Timer operating mode select bits
Count clock select bits
IF flag interrupt enable bit
0
Disables the IF flag interrupt
1
Enables the IF flag interrupt
: Readable/writable (The read value is the same as the write value.)
: Initial value
* : The value to be used as the count clock is decided according to the settings of the SYCC2 register.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-1 Functions of Bits in 8/16-bit Composite Timer 00/01 Status Control Register 0
(T00CR0/T01CR0) (1 / 2)
Bit name
bit7
bit6
to
bit4
Function
This bit enables or disables IF flag interrupts.
During timer operation (T00CR1/T01CR1:STA = 1), the write access to this bit has no
IFE:
effect on operation. Ensure that the timer has stopped before modifying this bit.
IF flag interrupt enable
Writing "0": Disables IF flag interrupts.
bit
Writing "1": An IF flag interrupt request is output when both the IE bit (T00CR1/
T01CR1:IE) and the IF flag (T00CR1/T01CR1:IF) are set to "1".
C2, C1, C0:
Count clock select bits
MN702-00005-2v0-E
These bits select the count clock.
• The count clock is generated by the prescaler. See "6.13 Operation of Prescaler".
• Write access to these bits is nullified in timer operation (T00CR1/T01CR1:STA = 1).
• The clock selection of T01CR0 (timer 01) is nullified in 16-bit operation.
• These bits cannot be set to "111B" when the PWC function or input capture function is
used. An attempt to write "111B" with the PWC function or input capture function in use
resets the bits to "000B". The bits are also reset to "000B" if the timer enters the input
capture operation mode with the bits set to "111B".
• When these bits are set to "110B", the count clock from the time-base timer will be used
as the count clock. Depending on the settings of the SYCC2 register, the count clock from
the time-base timer can be generated from the main clock, the main PLL clock or the
main CR clock. In the case of using the count clock from the time-base timer as the count
clock, resetting the time-base timer by writing "1" to the time-base timer initialization bit
in the time-base timer control register (TBTC:TCLR) will affect the count time.
C2
C1
C0
Count clock
0
0
0
1 × MCLK (machine clock)
0
0
1
1/2 × MCLK (machine clock)
0
1
0
1/4 × MCLK (machine clock)
0
1
1
1/8 × MCLK (machine clock)
1
0
0
1/16 × MCLK (machine clock)
1
0
1
1/32 × MCLK (machine clock)
1
1
0
1/128 × FCH or 1/64 × FCRH
1
1
1
External clock
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-1 Functions of Bits in 8/16-bit Composite Timer 00/01 Status Control Register 0
(T00CR0/T01CR0) (2 / 2)
Bit name
Function
These bits select the timer operating mode.
• The PWM timer function (variable-cycle mode; F3, F2, F1, F0 = 0100B) is set by either
the T00CR0 (timer 00) register or T01CR0 (timer 01) register. If one of the timers starts
operating (T00CR1/T01CR1: STA= 1), the F3, F2, F1 and F0 bits of the other timer are
automatically set to "0100B".
• With the 16-bit operation having been selected (TMCR0:MOD = 1), if the composite timer
starts operating using the PWM timer function (variable-cycle mode) (T00CR1/
T01CR1:STA = 1), the MOD bit is set to "0" automatically.
• Write access to these bits is nullified in timer operation (T00CR1/T01CR1:STA = 1).
bit3
to
bit0
364
F3, F2, F1, F0:
Timer operating mode
select bits
F3
F2
F1
F0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Timer operating mode select bits
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-run mode)
PWM timer (fixed-cycle mode)
PWM timer (variable-cycle mode)
PWC timer ("H" pulse = rising to falling)
PWC timer ("L" pulse = falling to rising)
PWC timer (cycle = rising to rising)
PWC timer (cycle = falling to falling)
PWC timer
("H" pulse = rising to falling; Cycle = rising to
rising)
Input capture
(rising, free-run counter)
Input capture
(falling, free-run counter)
Input capture
(both edges, free-run counter)
Input capture
(rising, counter clear)
Input capture
(falling, counter clear)
Input capture
(both edges, counter clear)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
18.5.2
8/16-bit Composite Timer 10/11 Status Control
Register 0 (T10CR0/T11CR0)
The 8/16-bit composite timer 10/11 status control register 0 (T10CR0/T11CR0)
selects the timer operation mode, selects the count clock, and enables or
disables IF flag interrupts. The T10CR0 and T11CR0 registers correspond to
timers 10 and 11 respectively.
■ 8/16-bit Composite Timer 10/11 Status Control Register 0 (T10CR0/T11CR0)
Figure 18.5-4 8/16-bit Composite Timer 10/11 Status Control Register 0 (T10CR0/T11CR0)
T11CR0
T10CR0
Address
0F97H
0F98H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
IFE
C2
C1
C0
F3
F2
F1
F0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F3
F2
F1
F0
0
0
0
0
Interval timer (one-shot mode)
Timer operating mode select bits
0
0
0
1
Interval timer (continuous mode)
0
0
1
0
Interval timer (free-run mode)
0
0
1
1
PWM timer (fixed-cycle mode)
0
1
0
0
PWM timer (variable-cycle mode)
0
1
0
1
PWC timer ("H" pulse = rising to falling)
0
1
1
0
PWC timer ("L" pulse = falling to rising)
0
1
1
1
PWC timer (cycle = rising to rising)
1
0
0
0
PWC timer (cycle = falling to falling)
1
0
0
1
PWC timer ("H" pulse = rising to falling; Cycle = rising to rising)
1
0
1
0
Input capture (rising, free-run counter)
1
0
1
1
Input capture (falling, free-run counter)
1
1
0
0
Input capture (both edges, free-run counter)
1
1
0
1
Input capture (rising, counter clear)
1
1
1
0
Input capture (falling, counter clear)
1
1
1
1
Input capture (both edges, counter clear)
C2
C1
C0
0
0
0
1 × MCLK (machine clock)
0
0
1
1/2 × MCLK (machine clock)
0
1
0
1/4 × MCLK (machine clock)
0
1
1
1/8 × MCLK (machine clock)
1
0
0
1/16 × MCLK (machine clock)
1
0
1
1/32 × MCLK (machine clock)
1
1
0
CK06/CK16 clock*
1
1
1
External clock
Count clock select bits
IFE
R/W
IF flag interrupt enable bit
0
Disables the IF flag interrupt
1
Enables the IF flag interrupt
: Readable/writable (The read value is the same as the write value.)
: Initial value
* : In main clock mode, the CK06/CK16 clock is a clock source to be selected from the following three
prescaler clocks: 1/27 × FCH, 1/29 × FCH and 1/211 × FCH, in the SEL[1:0] bits in the EVCR register of the event counter.
In main CR clock mode, the CK06/CK16 clock is a clock source to be selected from the following three
prescaler clocks: 1/26 × FCRH, 1/28 × FCRH and 1/210 × FCRH, in the SEL[1:0] bits in the EVCR register of the event counter.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-2 Functions of Bits in 8/16-bit Composite Timer 10/11 Status Control Register 0
(T10CR0/T11CR0) (1 / 2)
Bit name
bit7
Function
This bit enables or disables IF flag interrupts.
During timer operation (T10CR1/T11CR1:STA = 1), the write access to this bit has no
IFE:
effect on operation. Ensure that the timer has stopped before modifying this bit.
IF flag interrupt enable
Writing "0": Disables IF flag interrupts.
bit
Writing "1": An IF flag interrupt request is output when both the IE bit (T10CR1/
T11CR1:IE) and the IF flag (T10CR1/T11CR1:IF) are set to "1".
These bits select the count clock.
• The count clock is generated by the prescaler. See "6.13 Operation of Prescaler".
• Write access to these bits is nullified in timer operation (T10CR1/T11CR1:STA = 1).
• The clock selection of T11CR0 (timer 11) is nullified in 16-bit operation.
• These bits cannot be set to "111B" when the PWC function or input capture function is
used. An attempt to write "111B" with the PWC function or input capture function in use
resets the bits to "000B". The bits are also reset to "000B" if the timer enters the input
capture operation mode with the bits set to "111B".
• When these bits are set to "110B", the count clock from the time-base timer will be used
as the count clock. Depending on the settings of the SYCC2 register, the count clock from
the time-base timer can be generated from the main clock, the main PLL clock or the
main CR clock. In the case of using the count clock from the time-base timer as the count
clock, resetting the time-base timer by writing "1" to the time-base timer initialization bit
in the time-base timer control register (TBTC:TCLR) will affect the count time.
bit6
to
bit4
C2, C1, C0:
Count clock select bits
C2
C1
C0
Count clock
0
0
0
1 × MCLK (machine clock)
0
0
1
1/2 × MCLK (machine clock)
0
1
0
1/4 × MCLK (machine clock)
0
1
1
1/8 × MCLK (machine clock)
1
0
0
1/16 × MCLK (machine clock)
1
0
1
1/32 × MCLK (machine clock)
1
1
0
CK06/CK16 clock*
1
1
1
External clock
*: In main clock mode, the CK06/CK16 clock is a clock source to be selected from the
following three prescaler clocks: 1/27 × FCH, 1/29 × FCH and 1/211 × FCH, in the
SEL[1:0] bits in the EVCR register of the event counter.
In main CR clock mode, the CK06/CK16 clock is a clock source to be selected from the
following three prescaler clocks: 1/26 × FCRH, 1/28 × FCRH and 1/210 × FCRH, in the
SEL[1:0] bits in the EVCR register of the event counter.
For details of the CK06/CK16 clock, see "20.3.1 Event Counter Control Register
(EVCR)".
366
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-2 Functions of Bits in 8/16-bit Composite Timer 10/11 Status Control Register 0
(T10CR0/T11CR0) (2 / 2)
Bit name
Function
These bits select the timer operating mode.
• The PWM timer function (variable-cycle mode; F3, F2, F1, F0 = 0100B) is set by either
the T10CR0 (timer 10) register or T11CR0 (timer 11) register. If one of the timers starts
operating (T10CR1/T11CR1: STA= 1), the F3, F2, F1 and F0 bits of the other timer are
automatically set to "0100B".
• With the 16-bit operation having been selected (TMCR1:MOD = 1), if the composite timer
starts operating using the PWM timer function (variable-cycle mode) (T10CR1/
T11CR1:STA = 1), the MOD bit is set to "0" automatically.
• Write access to these bits is nullified in timer operation (T10CR1/T11CR1:STA = 1).
bit3
to
bit0
F3, F2, F1, F0:
Timer operating mode
select bits
MN702-00005-2v0-E
F3
F2
F1
F0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Timer operating mode select bits
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-run mode)
PWM timer (fixed-cycle mode)
PWM timer (variable-cycle mode)
PWC timer ("H" pulse = rising to falling)
PWC timer ("L" pulse = falling to rising)
PWC timer (cycle = rising to rising)
PWC timer (cycle = falling to falling)
PWC timer
("H" pulse = rising to falling; Cycle = rising to
rising)
Input capture
(rising, free-run counter)
Input capture
(falling, free-run counter)
Input capture
(both edges, free-run counter)
Input capture
(rising, counter clear)
Input capture
(falling, counter clear)
Input capture
(both edges, counter clear)
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
18.5.3
MB95410H/470H Series
8/16-bit Composite Timer 00/01 Status Control
Register 1 (T00CR1/T01CR1)
The 8/16-bit composite timer 00/01 status control register 1 (T00CR1/T01CR1)
controls the interrupt flag, timer output, and timer operations. T00CR1 and
T01CR1 registers correspond to timers 00 and 01 respectively.
■ 8/16-bit Composite Timer 00/01 Status Control Register 1 (T00CR1/T01CR1)
Figure 18.5-5 8/16-bit Composite Timer 00/01 Status Control Register 1 (T00CR1/T01CR1)
Address
T01CR1 0036H
T00CR1 0037H
bit7
bit6
STA
HO
R/W
R/W
bit5
bit4
bit3
bit2
bit1
IE
IR
BF
IF
SO
R/W R(RM1),W R/WX R(RM1),W R/W
bit0
Initial value
OE
00000000 B
R/W
Timer output enable bit
OE
0
Disables timer output
1
Enables timer output
Timer output initial value bit
SO
0
Timer initial value "0"
1
Timer initial value "1"
Timer reload/overflow flag
IF
Read
Write
0
No reload or overflow
Flag clear
1
Reload and overflow
No effect on operation
BF
Data register full flag
0
No measurement data in data register
1
Measurement data present in data register
IR
Pulse width measurement completion/edge detection flag
Read
Write
0
Measurement complete, edge undetected
Flag clear
1
Measurement complete, edge detected
No effect on operation
IE
Interrupt request bit
0
Disables interrupt requests
1
Enables interrupt requests
HO
Timer suspend bit
0
Resumes timer operation
1
Suspends timer
STA
Timer operation enable bit
0
Stops timer
1
Enables timer
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R/WX
368
: Read only (Readable. Writing a value to it has no effect on operation.)
: Initial value
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
Table 18.5-3 Functions of Bits in 8/16-bit Composite Timer 00/01 Status Control Register 1
(T00CR1/T01CR1) (1 / 2)
Bit name
Function
bit7
This bit enables or stops the timer operation.
Writing "0": Stops the timer operation and sets the count value to "00H".
• With the PWM timer function (variable-cycle mode) in use (T00CR0/T01CR0: F3, F2,
F1, F0 = 0100B), the STA bit in either the T00CR1 (timer 10) or the T01CR1 (timer 11)
register can be used to enable or disable the timer operation. If the STA bit in one of the
registers is set to "0", the STA bit in the other one is automatically set to the same value.
STA:
• During 16-bit operation (TMCR0:MOD = 1), use the STA bit in the T00CR1 (timer 10)
Timer operation enable
register to enable or disable timer operation. If the STA bit of one of the timers is set to
bit
"0", the STA bit in the other one is automatically set to the same value.
Writing "1": allows timer operation to start from count value "00H".
• Before setting this bit to "1", set the count clock select bits (T00CR0/T01CR0:C2, C1,
C0), timer operation select bits (T00CR0/T01CR0:F3, F2, F1, F0), timer output initial
value bit (T00CR1/T01CR1:SO), 16-bit mode enable bit (TMCR0:MOD), and filter
function select bits (TMCR0:FE11, FE10, FE01, FE00).
bit6
HO:
Timer suspend bit
This bit suspends or resumes the timer operation.
• Writing "1" to this bit during timer operation suspends the timer operation.
• When the timer operation has been enabled (T00CR1/T01CR1:STA = 1), writing "0" to
the bit resumes the timer operation.
• With the PWM timer function (variable-cycle mode) in used (T00CR0/T01CR0: F3, F2,
F1, F0=0100B), the HO bit in either T00CR1 (timer 00) or T01CR1 (timer 01) can be
used to suspend or resume timer operation. If the HO bit in one of the registers is set to
"0" or "1", the HO bit in the other one is automatically set to the same value.
• In 16-bit operation (TMCR0:MOD = 1), use the HO bit in the T00CR1 (timer 00) register
to suspend or resume timer operation. If the HO bit in one of the registers is set to "0" or
"1", the HO bit in the other one is automatically set to the same value.
IE:
Interrupt request
enable bit
This bit enables or disables the output of interrupt requests.
Writing "0": Disables interrupt request.
Writing "1": Outputs an interrupt request when the pulse width measurement completion/
edge detection flag (T00CR1/T01CR1:IR) or timer reload/overflow flag
(T00CR1/T01CR1:IF) is "1".
However, an interrupt request from the timer reload/overflow flag (T00CR1/
T01CR1:IF) is not output unless the IF flag interrupt enable (T00CR0/
T01CR0:IFE) bit is also set to "1".
IR:
Pulse width
measurement
completion/edge
detection flag
This bit indicates the completion of pulse width measurement or the detection of an edge.
• With the PWC timer function in use, this bit is set to "1" immediately after pulse width
measurement is complete.
• With the input capture function in use, this bit is set to "1" immediately after an edge is
detected.
• The bit is set to "0" when the function of the composite timer selected is neither the PWC
timer function nor the input capture function.
• If this bit is read by the read-modify-write (RMW) type of instruction, it always returns
"1".
• The IR bit in the T01CR1 (timer 01) register is set to "0" in 16-bit operation.
• Writing "0" to this bit sets it to "0".
• Writing "1" to this bit is ignored.
bit5
bit4
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-3 Functions of Bits in 8/16-bit Composite Timer 00/01 Status Control Register 1
(T00CR1/T01CR1) (2 / 2)
Bit name
Function
BF:
Data register full flag
• With the PWC timer function in use, this bit is set to "1" when a count value is stored in
the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) immediately after pulse
width measurement is complete.
• In 8-bit operation, this bit is set to "0" when the 8/16-bit composite timer 00/01 data
register (T00DR/T01DR) is read.
• The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) holds data if this bit is
set to "1". With this bit being "1", even when the next edge is detected, the count value is
not transferred to the 8/16-bit composite timer 00/01 data register (T00DR/T01DR), and
the next measurement result is thus lost. Nonetheless, there is an exception. With the F3
bit to F0 bit in the T00CR0/T01CR0 register having been set to "1001B", even though the
BF bit is set to "1", the "H" pulse measurement result is transferred to the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR), while the cycle measurement result
is not transferred to the 8/16-bit composite timer 00/01 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a
cycle is completed. In addition, the result of "H" pulse measurement and that of cycle
measurement are lost if they are not read before the completion of the next "H" pulse.
• The BF bit in the T00CR1 (timer 00) register is set to "0" when the T01DR (timer 01)
register is read during 16-bit operation.
• The BF bit in T01CR1 (timer 01) register is set to "0" during 16-bit operation.
• This bit is "0" when any timer function other than the PWC timer function is selected.
• Writing a value to this bit has no effect on operation.
IF:
Timer reload/overflow
flag
This bit is used to detect the count value match and the counter overflow.
• With the interval timer function (one-shot or continuous) or the PWM timer function
(variable-cycle mode) in use, this bit is set to "1" if the 8/16-bit composite timer 00/01
data register (T00DR/T01DR) value matches the count value.
• With the PWC timer function of the input capture function in use, this bit is set to "1" if a
counter overflow occurs.
• If this bit is read by a read-modify-write (RMW) instruction, it always returns "1".
• Writing "0" to this bit sets it to "0".
• Writing "1" to this bit has no effect on operation.
• The bit becomes "0" if the PWM function (variable-cycle mode) is selected.
• The IF bit in the T01CR1 (timer 01) register is "0" in 16-bit operation.
bit1
SO:
Timer output initial
value bit
The timer output (TMCR0:TO1/TO0) initial value is set by writing a value to this bit. The
value in this bit is reflected in the timer output when the timer operation enable bit
(T00CR1/T01CR1:STA) changes from "0" to "1".
• In 16-bit operation (TMCR0:MOD = 1), use the SO bit in the T00CR1 (timer 00) register
to set the timer output initial value. In this case, the value of the SO bit in the other one
has no effect on operation.
• During timer operation (T00CR1:STA = 1 or T01CR1:STA = 1), the write access to this
bit is invalid. However, in 16-bit operation, although a value can be written to the SO bit
in the T01CR1 (timer 01) register even during timer operation, the value written has no
direct effect on the timer output.
• When the PWM timer function (fixed cycle mode or variable cycle mode) or the input
capture function is in use, the value of this bit has no effect on operation.
bit0
This bit enables or disables timer output.
Writing "0": No timer output is supplied to the external pin. In this case, the external pin
OE:
serves as a general-purpose port.
Timer output enable bit
Writing "1": The time output (TMCR0:TO1/TO0) is supplied to the external pin.
bit3
bit2
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
18.5.4
8/16-bit Composite Timer 10/11 Status Control
Register 1 (T10CR1/T11CR1)
The 8/16-bit composite timer 10/11 status control register 1 (T10CR1/T11CR1)
controls the interrupt flag, timer output, and timer operations. T10CR1 and
T11CR1 registers correspond to timers 10 and 11 respectively.
■ 8/16-bit Composite Timer 10/11 Status Control Register 1 (T10CR1/T11CR1)
Figure 18.5-6 8/16-bit Composite Timer 10/11 Status Control Register 1 (T10CR1/T11CR1))
Address
T11CR1 0038H
T10CR1 0039H
bit7
bit6
STA
HO
R/W
R/W
bit5
bit4
bit3
bit2
bit1
IE
IR
BF
IF
SO
R/W R(RM1),W R/WX R(RM1),W R/W
bit0
Initial value
OE
00000000 B
R/W
Timer output enable bit
OE
0
Disables timer output
1
Enables timer output
Timer output initial value bit
SO
0
Timer initial value "0"
1
Timer initial value "1"
Timer reload/overflow flag
IF
Read
Write
0
No reload or overflow
Flag clear
1
Reload and overflow
No effect on operation
BF
Data register full flag
0
No measurement data in data register
1
Measurement data present in data register
IR
Pulse width measurement completion/edge detection flag
Read
Write
0
Measurement complete, edge undetected
Flag clear
1
Measurement complete, edge detected
No effect on operation
IE
Interrupt request bit
0
Disables interrupt requests
1
Enables interrupt requests
HO
Timer suspend bit
0
Resumes timer operation
1
Suspends timer
STA
Timer operation enable bit
0
Stops timer
1
Enables timer
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R/WX
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: Read only (Readable. Writing a value to it has no effect on operation.)
: Initial value
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-4 Functions of Bits in 8/16-bit Composite Timer 10/11 Status Control Register 1
(T10CR1/T11CR1) (1 / 2)
Bit name
Function
bit7
This bit enables or stops the timer operation.
Writing "0": Stops the timer operation and sets the count value to "00H".
• With the PWM timer function (variable-cycle mode) in use (T10CR0/T11CR0: F3, F2,
F1, F0 = 0100B), the STA bit in either the T10CR1 (timer 10) or the T11CR1 (timer 11)
register can be used to enable or disable the timer operation. If the STA bit in one of the
registers is set to "0", the STA bit in the other one is automatically set to the same value.
STA:
• During 16-bit operation (TMCR1:MOD = 1), use the STA bit in the T10CR1 (timer 10)
Timer operation enable
register to enable or disable timer operation. If the STA bit of one of the timers is set to
bit
"0", the STA bit in the other one is automatically set to the same value.
Writing "1": Allows timer operation to start from count value "00H".
• Before setting this bit to "1", set the count clock select bits (T10CR0/T11CR0:C2, C1,
C0), timer operation select bits (T10CR0/T11CR0:F3, F2, F1, F0), timer output initial
value bit (T10CR1/T11CR1:SO), 16-bit mode enable bit (TMCR1:MOD), and filter
function select bits (TMCR1:FE11, FE10, FE01, FE00).
bit6
HO:
Timer suspend bit
This bit suspends or resumes the timer operation.
• Writing "1" to this bit during timer operation suspends the timer operation.
• When the timer operation has been enabled (T10CR1/T11CR1:STA = 1), writing "0" to
the bit resumes the timer operation.
• With the PWM timer function (variable-cycle mode) in used (T10CR0/T11CR0: F3, F2,
F1, F0=0100B), the HO bit in either T10CR1 (timer 10) or T11CR1 (timer 11) can be
used to suspend or resume timer operation. If the HO bit in one of the registers is set to
"0" or "1", the HO bit in the other one is automatically set to the same value.
• In 16-bit operation (TMCR1:MOD = 1), use the HO bit in the T10CR1 (timer 10) register
to suspend or resume timer operation. If the HO bit in one of the registers is set to "0" or
"1", the HO bit in the other one is automatically set to the same value.
IE:
Interrupt request
enable bit
This bit enables or disables the output of interrupt requests.
Writing "0": Disables interrupt request.
Writing "1": Outputs an interrupt request when the pulse width measurement completion/
edge detection flag (T10CR1/T11CR1:IR) or timer reload/overflow flag
(T10CR1/T11CR1:IF) is "1".
However, an interrupt request from the timer reload/overflow flag (T10CR1/
T11CR1:IF) is not output unless the IF flag interrupt enable (T10CR0/
T11CR0:IFE) bit is also set to "1".
IR:
Pulse width
measurement
completion/edge
detection flag
This bit indicates the completion of pulse width measurement or the detection of an edge.
• With the PWC timer function in use, this bit is set to "1" immediately after pulse width
measurement is complete.
• With the input capture function in use, this bit is set to "1" immediately after an edge is
detected.
• The bit is set to "0" when the function of the composite timer selected is neither the PWC
timer function nor the input capture function.
• If this bit is read by the read-modify-write (RMW) type of instruction, it always returns
"1".
• The IR bit in the T11CR1 (timer 01) register is set to "0" in 16-bit operation.
• Writing "0" to this bit sets it to "0".
• Writing "1" to this bit is ignored.
bit5
bit4
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
Table 18.5-4 Functions of Bits in 8/16-bit Composite Timer 10/11 Status Control Register 1
(T10CR1/T11CR1) (2 / 2)
Bit name
Function
BF:
Data register full flag
• With the PWC timer function in use, this bit is set to "1" when a count value is stored in
the 8/16-bit composite timer 10/11 data register (T10DR/T11DR) immediately after pulse
width measurement is complete.
• In 8-bit operation, this bit is set to "0" when the 8/16-bit composite timer 10/11 data
register (T10DR/T11DR) is read.
• The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) holds data if this bit is
set to "1". With this bit being "1", even when the next edge is detected, the count value is
not transferred to the 8/16-bit composite timer 10/11 data register (T10DR/T11DR), and
the next measurement result is thus lost. Nonetheless, there is an exception. With the F3
bit to F0 bit in the T10CR0/T11CR0 register having been set to "1001B", even though the
BF bit is set to "1", the "H" pulse measurement result is transferred to the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR), while the cycle measurement result
is not transferred to the 8/16-bit composite timer 10/11 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a
cycle is completed. In addition, the result of "H" pulse measurement and that of cycle
measurement are lost if they are not read before the completion of the next "H" pulse.
• The BF bit in the T10CR1 (timer 10) register is set to "0" when the T11DR (timer 11)
register is read during 16-bit operation.
• The BF bit in T11CR1 (timer 11) register is set to "0" during 16-bit operation.
• This bit is "0" when any timer function other than the PWC timer function is selected.
• Writing a value to this bit has no effect on operation.
IF:
Timer reload/overflow
flag
This bit is used to detect the count value match and the counter overflow.
• With the interval timer function (one-shot or continuous) or the PWM timer function
(variable-cycle mode) in use, this bit is set to "1" if the 8/16-bit composite timer 10/11
data register (T10DR/T11DR) value matches the count value.
• With the PWC timer function of the input capture function in use, this bit is set to "1" if a
counter overflow occurs.
• If this bit is read by a read-modify-write (RMW) instruction, it always returns "1".
• Writing "0" to this bit sets it to "0".
• Writing "1" to this bit has no effect on operation.
• The bit becomes "0" if the PWM function (variable-cycle mode) is selected.
• The IF bit in the T11CR1 (timer 11) register is "0" in 16-bit operation.
bit1
SO:
Timer output initial
value bit
The timer output (TMCR1:TO1/TO0) initial value is set by writing a value to this bit. The
value in this bit is reflected in the timer output when the timer operation enable bit
(T10CR1/T11CR1:STA) changes from "0" to "1".
• In 16-bit operation (TMCR1:MOD = 1), use the SO bit in the T10CR1 (timer 10) register
to set the timer output initial value. In this case, the value of the SO bit in the other one
has no effect on operation.
• During timer operation (T10CR1:STA = 1 or T11CR1:STA = 1), the write access to this
bit is invalid. However, in 16-bit operation, although a value can be written to the SO bit
in the T11CR1 (timer 11) register even during timer operation, the value written has no
direct effect on the timer output.
• When the PWM timer function (fixed cycle mode or variable cycle mode) or the input
capture function is in use, the value of this bit has no effect on operation.
bit0
This bit enables or disables timer output.
Writing "0": No timer output is supplied to the external pin. In this case, the external pin
OE:
serves as a general-purpose port.
Timer output enable bit
Writing "1": The time output (TMCR1:TO1/TO0) is supplied to the external pin.
bit3
bit2
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
18.5.5
MB95410H/470H Series
8/16-bit Composite Timer 00/01 Timer Mode
Control Register (TMCR0)
The 8/16-bit composite timer 00/01 timer mode control register (TMCR0) selects
the filter function, 8-bit or 16-bit operating mode, and signal input to timer 00
and indicates the timer output value. This register serves both timer 00 and
timer 01.
■ 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0)
Figure 18.5-7 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0)
Address
0F96H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
00000000 B
R/WX
R/WX
R/W
R/W
R/W
R/W
R/W
R/W
Timer 00 filter function select bits
FE01
FE00
0
0
No filtering.
0
1
Removes "H" pulse noise.
1
0
Removes "L" pulse noise.
1
1
Removes "H"/"L" pulse noise.
FE11
FE10
0
0
No filtering.
0
1
Removes "H" pulse noise.
1
0
Removes "L" pulse noise.
1
1
Removes "H"/"L" pulse noise.
Timer 01 filter function select bits
MOD
8-bit/16-bit operating mode select bit
0
8-bit operation
1
16-bit operation
TIS
Timer 00 internal signal select bit
0
Selects external signal (EC0) as timer 00 input.
1
Setting prohibited.
TO0
0
Timer 00 output bit
Output value of timer 00
1
TO1
0
Timer 01 output bit
Output value of timer 01
1
R/W
R/WX
374
: Readable/writable (The read value is the same as the write value.)
: Read only (Readable. Writing a value to it has no effect on operation.)
: Initial value
FUJITSU SEMICONDUCTOR LIMITED
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MB95410H/470H Series
CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
.
Table 18.5-5 Functions of Bits in 8/16-bit Composite Timer 00/01 Timer Mode Control Register
(TMCR0) (1 / 2)
Bit name
Function
TO1:
Timer 01 output bit
This bit indicates the output value of timer 01. When the timer starts operation (T00CR1/
T01CR1:STA = 1), the value in the bit changes depending on the timer function selected.
• Writing a value to this bit has no effect on operation.
• In 16-bit operation, if the PWM timer function (variable-cycle mode) or the input capture
function is selected, the value in the bit becomes undefined.
• With the interval timer function or the PWC timer function having been selected, if the
timer stops operating (T00CR1/T01CR1:STA = 0), this bit holds the last value.
• With the PWM timer function (variable-cycle mode) having been selected, if the timer
stops operating (T00CR1/T01CR1:STA = 0), this bit holds the last value.
• When the timer operating mode select bits (T00CR0/T01CR0: F3, F2, F1, F0) are
modified with the timer stopping operating, this bit indicates the last value of timer
operation if the same timer operation has been performed; otherwise it indicates "0", its
initial value.
bit6
TO0:
Timer 00 output bit
This bit indicates the output value of timer 00. When the timer starts operation (T00CR1/
T01CR1:STA = 1), the value in the bit changes depending on the selected timer function.
• Writing a value to this bit has no effect on operation.
• If the input capture function is selected, the value in the bit becomes undefined.
• With the interval timer function or the PWM timer (variable-cycle mode) or the PWC
timer function having been selected, if the timer stops operating (T00CR1/T01CR1:STA
= 0), this bit holds the last value.
• With the PWM timer function (variable-cycle mode) having been selected, if the timer
stops operating (T00CR1/T01CR1:STA = 0), this bit holds the last value.
• When the timer operating mode select bits (T00CR0/T01CR0: F3, F2, F1, F0) are
modified with the timer stopping operating, this bit indicates the last value of timer
operation if the same timer operation has been performed; otherwise it indicates "0", its
initial value.
bit5
TIS:
Timer 00 internal
signal select bit
This bit selects the signal input to timer 00 when the PWC timer function or input capture
function is selected.
Writing "0": Selects the external signal (EC0) as the signal input for timer 00.
Writing "1": Setting prohibited.
MOD:
16-bit mode enable bit
This bit selects 8-bit or 16-bit operation mode.
Writing "0": Allows timers 00 and 01 to operate as separate 8-bit timers.
Writing "1": Allows timers 00 and 01 to operate as a 16-bit timer.
• While this bit is "1", if the timer starts operating (T00CR1/T01CR1:STA = 1) with the
PWM timer function (variable-cycle mode), this bit is automatically set to "0".
• During timer operation (T00CR1:STA = 1 or T01CR1:STA = 1), the write access to this
bit is invalid.
bit7
bit4
These bits select the filter function for the external signal (EC0) to timer 01 when the PWC
timer function or the input capture function is selected.
bit3,
bit2
FE11, FE10:
Timer 01 filter function
select bits
FE11
FE10
Timer 01 filter
0
0
No filtering out.
0
1
Filters out "H" pulse noise.
1
0
Filters out "L" pulse noise.
1
1
Filters out both "H" pulse noise and "L" pulse noise.
• During timer operation (T00CR1:STA = 1), the write access to these bits is invalid.
• The settings of the bits have no effect on operation when the interval timer function or the
PWM timer function is selected (the filter function does not operate.).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-5 Functions of Bits in 8/16-bit Composite Timer 00/01 Timer Mode Control Register
(TMCR0) (2 / 2)
Bit name
Function
These bits select the filter function for the external signal (EC0) to timer 00 when the PWC
timer function or the input capture function is selected.
bit1,
bit0
FE01, FE00:
Timer 00 filter function
select bits
FE01
FE00
Timer 00 filter
0
0
No filtering out.
0
1
Filters out "H" pulse noise.
1
0
Filters out "L" pulse noise.
1
1
Filters out both "H" pulse noise and "L" pulse noise.
• During timer operation (T00CR1:STA = 1), the write access to these bits is invalid.
• The settings of these bits have no effect on operation when the interval timer function or
the PWM timer function is selected (the filter function does not operate.).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
18.5.6
8/16-bit Composite Timer 10/11 Timer Mode
Control Register (TMCR1)
The 8/16-bit composite timer 10/11 timer mode control register (TMCR1) selects
the filter function, 8-bit or 16-bit operating mode, and signal input to timer 10
and indicates the timer output value. This register serves both timer 10 and
timer 11.
■ 8/16-bit Composite Timer 10/11 Timer Mode Control Register (TMCR1)
Figure 18.5-8 8/16-bit Composite Timer 10/11 Timer Mode Control Register (TMCR1)
Address
0F9BH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
00000000 B
R/WX
R/WX
R/W
R/W
R/W
R/W
R/W
R/W
Timer 10 filter function select bits
FE01
FE00
0
0
No filtering.
0
1
Removes "H" pulse noise.
1
0
Removes "L" pulse noise.
1
1
Removes "H"/"L" pulse noise.
FE11
FE10
0
0
No filtering.
0
1
Removes "H" pulse noise.
1
0
Removes "L" pulse noise.
1
1
Removes "H"/"L" pulse noise.
Timer 11 filter function select bits
MOD
8-bit/16-bit operating mode select bit
0
8-bit operation
1
16-bit operation
TIS
Timer 10 internal signal select bit
0
Selects external signal (EC1) as timer 10 input.
1
Setting prohibited.
TO0
0
Timer 10 output bit
Output value of timer 10
1
TO1
0
Timer 11 output bit
Output value of timer 11
1
R/W
R/WX
: Readable/writable (The read value is the same as the write value.)
: Read only (Readable. Writing a value to it has no effect on operation.)
: Initial value
.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
Table 18.5-6 Functions of Bits in 8/16-bit Composite Timer 10/11 Timer Mode Control Register
(TMCR1) (1 / 2)
Bit name
Function
TO1:
Timer 11 output bit
This bit indicates the output value of timer 11. When the timer starts operation (T10CR1/
T11CR1:STA = 1), the value in the bit changes depending on the timer function selected.
• Writing a value to this bit has no effect on operation.
• In 16-bit operation, if the PWM timer function (variable-cycle mode) or the input capture
function is selected, the value in the bit becomes undefined.
• With the interval timer function or the PWC timer function having been selected, if the
timer stops operating (T10CR1/T11CR1:STA = 0), this bit holds the last value.
• With the PWM timer function (variable-cycle mode) having been selected, if the timer
stops operating (T10CR1/T11CR1:STA = 0), this bit holds the last value.
• When the timer operating mode select bits (T10CR0/T11CR0: F3, F2, F1, F0) are
modified with the timer stopping operating, this bit indicates the last value of timer
operation if the same timer operation has been performed; otherwise it indicates "0", its
initial value.
bit6
TO0:
Timer 10 output bit
This bit indicates the output value of timer 10. When the timer starts operation (T10CR1/
T11CR1:STA = 1), the value in the bit changes depending on the selected timer function.
• Writing a value to this bit has no effect on operation.
• If the input capture function is selected, the value in the bit becomes undefined.
• With the interval timer function or the PWM timer (variable-cycle mode) or the PWC
timer function having been selected, if the timer stops operating (T10CR1/T11CR1:STA
= 0), this bit holds the last value.
• With the PWM timer function (variable-cycle mode) having been selected, if the timer
stops operating (T10CR1/T11CR1:STA = 0), this bit holds the last value.
• When the timer operating mode select bits (T10CR0/T11CR0: F3, F2, F1, F0) are
modified with the timer stopping operating, this bit indicates the last value of timer
operation if the same timer operation has been performed; otherwise it indicates "0", its
initial value.
bit5
TIS:
Timer 10 internal
signal select bit
This bit selects the signal input to timer 10 when the PWC timer function or input capture
function is selected.
Writing "0": Selects the external signal (EC1) as the signal input for timer 10.
Writing "1": Setting prohibited.
MOD:
16-bit mode enable bit
This bit selects 8-bit or 16-bit operation mode.
Writing "0": Allows timers 10 and 11 to operate as separate 8-bit timers.
Writing "1": Allows timers 10 and 11 to operate as a 16-bit timer.
• While this bit is "1", if the timer starts operating (T10CR1/T11CR1:STA = 1) with the
PWM timer function (variable-cycle mode), this bit is automatically set to "0".
• During timer operation (T10CR1:STA = 1 or T11CR1:STA = 1), the write access to this
bit is invalid.
bit7
bit4
These bits select the filter function for the external signal (EC1) to timer 11 when the PWC
timer function or the input capture function is selected.
bit3,
bit2
FE11, FE10:
Timer 11 filter function
select bits
FE11
FE10
Timer 11 filter
0
0
No filtering out.
0
1
Filters out "H" pulse noise.
1
0
Filters out "L" pulse noise.
1
1
Filters out both "H" pulse noise and "L" pulse noise.
• During timer operation (T10CR1:STA = 1), the write access to these bits is invalid.
• The settings of the bits have no effect on operation when the interval timer function or the
PWM timer function is selected (the filter function does not operate.).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
Table 18.5-6 Functions of Bits in 8/16-bit Composite Timer 10/11 Timer Mode Control Register
(TMCR1) (2 / 2)
Bit name
Function
These bits select the filter function for the external signal (EC1) to timer 10 when the PWC
timer function or the input capture function is selected.
bit1,
bit0
FE01, FE00:
Timer 10 filter function
select bits
FE01
FE00
Timer 10 filter
0
0
No filtering out.
0
1
Filters out "H" pulse noise.
1
0
Filters out "L" pulse noise.
1
1
Filters out both "H" pulse noise and "L" pulse noise.
• During timer operation (T10CR1:STA = 1), the write access to these bits is invalid.
• The settings of these bits have no effect on operation when the interval timer function or
the PWM timer function is selected (the filter function does not operate.).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
8/16-bit Composite Timer 00/01 Data Register
(T00DR/T01DR)
18.5.7
The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to set
the maximum count value during the interval timer operation or the PWM timer
operation and to read the count value during the PWC timer operation or the
input capture operation. The T00DR and T01DR registers correspond to timers
00 and 01 respectively.
■ 8/16-bit Composite Timer 00/01 Data Register (T00DR/T01DR)
Figure 18.5-9 8/16-bit Composite Timer 00/01 Data Register (T00DR/T01DR)
T01DR
T00DR
R,W
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0F94H TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 00000000B
0F95H
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
: Readable/writable (The read value is different from the write value.)
● Interval timer function
The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to set the interval
time. When the timer starts operating (T00CR1/T01CR1:STA = 1), the value of this register is
transferred to the latch in the 8-bit comparator and the counter starts counting. When the count
value matches the value held in the latch in the 8-bit comparator, the value of this register is
transferred again to the latch, and the counter returns to "00H" and continues to count.
The current count value can be read from this register.
An attempt to write "00H" to this register is disabled in interval timer function.
In 16-bit operation, write the upper timer data to T01DR and lower timer data to T00DR, and
write or read T01DR first and then T00DR.
● PWM timer function (fixed-cycle)
The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to set "H" pulse
width time. When the timer starts operating (T00CR1/T01CR1:STA = 1), the value of this
register is transferred to the latch in the 8-bit comparator and the counter starts counting from
timer output "H". When the count value matches the value transferred to the latch, the timer
output becomes "L" and the counter continues to count until the count value reaches "FFH".
When an overflow occurs, the value of this register is transferred again to the latch in the 8-bit
comparator and the counter performs the next cycle of counting.
The current value can be read from this register. In 16-bit operation, write the upper timer data
to T01DR and lower timer data to T00DR, and write or read T01DR first and then T00DR.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
● PWM timer function (variable-cycle)
The 8/16-bit composite timer 00 data register (T00DR) and 8/16-bit composite timer 01 data
register (T01DR) are used to set "L" pulse width time and cycle respectively. When the timer
starts operating (T00CR1/T01CR1:STA = 1), the value of each register is transferred to the
latch in the 8-bit comparator and the two counters start counting from timer output "L". When
the T00DR value transferred to the latch matches the timer 00 counter value, the timer output
becomes "H" and the counting continues until the T01DR value transferred to the latch
matches the timer 01 counter value. When the T01DR value transferred to the latch of the 8-bit
comparator matches the timer 01 counter value, the values of the T00DR register and the
T01DR register are transferred again to the latch and the counter performs the next PWM cycle
of counting.
The current count value can be read from this register. In 16-bit operation, write the upper
timer data to T01DR and lower timer data to T00DR, and read T01DR first and then T00DR.
● PWC timer function
The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to read PWC
measurement results. When PWC measurement is completed, the counter value is transferred
to this register and the BF bit is set to "1".
When the 8/16-bit composite timer 00/01 data register is read, the BF bit is set to "0". While
the BF bit is "1", no data is transferred to the 8/16-bit composite timer 00/01 data register.
There is an exception. With the F3 bit to F0 bit in the T00CR0/T01CR0 register having been
set to "1001B", even though the BF bit is set to "1", the "H" pulse measurement result is
transferred to the 8/16-bit composite timer 00/01 data register, while the cycle measurement
result is not transferred to the 8/16-bit composite timer 00/01 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a cycle is
completed. In addition, the result of "H" pulse measurement and that of cycle measurement are
lost if they are not read before the completion of the next "H" pulse.
When reading the 8/16-bit composite timer 00/01 data register, ensure that the BF bit is not
cleared accidentally.
If new data is written to the 8/16-bit composite timer 00/01 data register, the stored
measurement data is replaced with the new data. Therefore, do not write data to the register. In
16-bit operation, write the upper timer data to T01DR and lower timer data to T00DR, and read
T01DR first and then T00DR.
● Input capture function
The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to read input capture
results. When an edge specified is detected, the counter value is transferred to the 8/16-bit
composite timer 00/01 data register.
If new data is written to the 8/16-bit composite timer 00/01 data register, the stored
measurement data is replaced with the new data. Therefore, do not write data to the register. In
16-bit operation, write the upper timer data to T01DR and lower timer data to T00DR, and read
T01DR first and then T00DR.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
● Read and write operations
Read and write operations of T00DR and T01DR are performed in the following manner in 16bit operation or when the PWM timer function (variable-cycle) is selected.
• Read from T01DR:
In addition to the read access to T01DR, the value of T00DR is also
stored in the internal read buffer at the same time.
• Read from T00DR:
The internal read buffer is read.
• Write to T01DR:
Data is written to the internal write buffer.
• Write to T00DR:
In addition to the write access to T00DR, the value of the internal
write buffer is stored in T01DR at the same time.
Figure 18.5-10 shows the T00DR and T01DR registers read from and written to during 16-bit
operation.
Figure 18.5-10 Read and write operations of T00DR and T01DR registers during 16-bit
operation
T00DR
register
Write
data
382
Read data
T01DR
register
Write
buffer
T01DR
write
Read
buffer
T00DR
write
T01DR
read
FUJITSU SEMICONDUCTOR LIMITED
T00DR
read
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
18.5.8
8/16-bit Composite Timer 10/11 Data Register
(T10DR/T11DR)
The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is used to set
the maximum count value during the interval timer operation or the PWM timer
operation and to read the count value during the PWC timer operation or the
input capture operation. The T10DR and T11DR registers correspond to timers
10 and 11 respectively.
■ 8/16-bit Composite Timer 10/11 Data Register (T10DR/T11DR)
Figure 18.5-11 8/16-bit Composite Timer 10/11 Data Register (T10DR/T11DR)
T11DR
T10DR
R,W
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0F99H TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 00000000B
0F9AH R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
: Readable/writable (The read value is different from the write value.)
● Interval timer function
The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is used to set the interval
time. When the timer starts operating (T10CR1/T11CR1:STA = 1), the value of this register is
transferred to the latch in the 8-bit comparator and the counter starts counting. When the count
value matches the value held in the latch in the 8-bit comparator, the value of this register is
transferred again to the latch, and the counter returns to "00H" and continues to count.
The current count value can be read from this register.
An attempt to write "00H" to this register is disabled in interval timer function.
In 16-bit operation, write the upper timer data to T11DR and lower timer data to T10DR, and
write or read T11DR first and then T10DR.
● PWM timer function (fixed-cycle)
The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is used to set "H" pulse
width time. When the timer starts operating (T10CR1/T11CR1:STA = 1), the value of this
register is transferred to the latch in the 8-bit comparator and the counter starts counting from
timer output "H". When the count value matches the value transferred to the latch, the timer
output becomes "L" and the counter continues to count until the count value reaches "FFH".
When an overflow occurs, the value of this register is transferred again to the latch in the 8-bit
comparator and the counter performs the next cycle of counting.
The current value can be read from this register. In 16-bit operation, write the upper timer data
to T11DR and lower timer data to T10DR, and write or read T11DR first and then T10DR.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
● PWM timer function (variable-cycle)
The 8/16-bit composite timer 10 data register (T10DR) and 8/16-bit composite timer 11 data
register (T11DR) are used to set "L" pulse width time and cycle respectively. When the timer
starts operating (T10CR1/T11CR1:STA = 1), the value of each register is transferred to the
latch in the 8-bit comparator and the two counters start counting from timer output "L". When
the T10DR value transferred to the latch matches the timer 10 counter value, the timer output
becomes "H" and the counting continues until the T11DR value transferred to the latch
matches the timer 11 counter value. When the T11DR value transferred to the latch of the 8-bit
comparator matches the timer 11 counter value, the values of the T10DR register and the
T11DR register are transferred again to the latch and the counter performs the next PWM cycle
of counting.
The current count value can be read from this register. In 16-bit operation, write the upper
timer data to T11DR and lower timer data to T10DR, and read T11DR first and then T10DR.
● PWC timer function
The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is used to read PWC
measurement results. When PWC measurement is completed, the counter value is transferred
to this register and the BF bit is set to "1".
When the 8/16-bit composite timer 10/11 data register is read, the BF bit is set to "0". While
the BF bit is "1", no data is transferred to the 8/16-bit composite timer 10/11 data register.
There is an exception. With the F3 bit to F0 bit in the T10CR0/T11CR0 register having been
set to "1001B", even though the BF bit is set to "1", the "H" pulse measurement result is
transferred to the 8/16-bit composite timer 10/11 data register, while the cycle measurement
result is not transferred to the 8/16-bit composite timer 10/11 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a cycle is
completed. In addition, the result of "H" pulse measurement and that of cycle measurement are
lost if they are not read before the completion of the next "H" pulse.
When reading the 8/16-bit composite timer 10/11 data register, ensure that the BF bit is not
cleared accidentally.
If new data is written to the 8/16-bit composite timer 10/11 data register, the stored
measurement data is replaced with the new data. Therefore, do not write data to the register. In
16-bit operation, write the upper timer data to T11DR and lower timer data to T10DR, and read
T11DR first and then T10DR.
● Input capture function
The 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is used to read input capture
results. When an edge specified is detected, the counter value is transferred to the 8/16-bit
composite timer 10/11 data register.
If new data is written to the 8/16-bit composite timer 10/11 data register, the stored
measurement data is replaced with the new data. Therefore, do not write data to the register. In
16-bit operation, write the upper timer data to T11DR and lower timer data to T10DR, and read
T11DR first and then T10DR.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.5 Registers of 8/16-bit Composite Timer
MB95410H/470H Series
● Read and write operations
Read and write operations of T10DR and T11DR are performed in the following manner in 16bit operation or when the PWM timer function (variable-cycle) is selected.
• Read from T11DR:
In addition to the read access to T11DR, the value of T10DR is also
stored in the internal read buffer at the same time.
• Read from T10DR:
The internal read buffer is read.
• Write to T11DR:
Data is written to the internal write buffer.
• Write to T10DR:
In addition to the write access to T10DR, the value of the internal
write buffer is stored in T11DR at the same time.
Figure 18.5-12 shows the T10DR and T11DR registers read from and written to during 16-bit
operation.
Figure 18.5-12 Read and write operations of T10DR and T11DR registers during 16-bit
operation
T10DR
register
Write
data
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Read data
T11DR
register
Write
buffer
T11DR
write
Read
buffer
T10DR
write
T11DR
read
FUJITSU SEMICONDUCTOR LIMITED
T10DR
read
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.6 Interrupts of 8/16-bit Composite Timer
MB95410H/470H Series
Interrupts of 8/16-bit Composite Timer
18.6
The 8/16-bit composite timer generates the following types of interrupts. An
interrupt number and an interrupt vector are assigned to each type of
interrupts.
• Timer 00 interrupt
• Timer 01 interrupt
• Timer 10 interrupt
• Timer 11 interrupt
■ Timer 00 Interrupt
Table 18.6-1 shows the timer 00 interrupt and its sources.
Table 18.6-1 Timer 00 Interrupt
Description
Item
Overflow in the PWC timer
operation or the input capture
operation
Completion of
measurement in the PWC
timer operation or edge
detection in the input
capture operation
Interrupt generating
condition
Comparison match in the
interval timer operation or the
PWM timer operation
(variable-cycle mode)
Interrupt flag
T00CR1:IF
T00CR1:IF
T00CR1:IR
Interrupt enable
T00CR1:IE and T00CR0:IFE
T00CR1:IE and T00CR0:IFE
T00CR1:IE
■ Timer 01 Interrupt
Table 18.6-2 shows the timer 01 interrupt and its sources.
Table 18.6-2 Timer 01 Interrupt
Description
Item
Interrupt generating
condition
Comparison match in the
interval timer operation or the
PWM timer operation
(variable-cycle mode), except
in 16-bit operation
Overflow in the PWC timer
operation or the input capture
operation, except in 16-bit
operation
Completion of
measurement in the PWC
timer operation or edge
detection in the input
capture operation, except
in 16-bit operation
Interrupt flag
T01CR1:IF
T01CR1:IF
T01CR1:IR
Interrupt enable
T01CR1:IE and T01CR0:IFE
T01CR1:IE and T01CR0:IFE
T01CR1:IE
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.6 Interrupts of 8/16-bit Composite Timer
MB95410H/470H Series
■ Timer 10 Interrupt
Table 18.6-3 shows the timer 10 interrupt and its sources.
Table 18.6-3 Timer 10 Interrupt
Description
Item
Interrupt generating
condition
Comparison match in the
interval timer operation or the
PWM timer operation
(variable-cycle mode)
Overflow in the PWC timer
operation or the input capture
operation
Completion of
measurement in the PWC
timer operation or edge
detection in the input
capture operation
Interrupt flag
T10CR1:IF
T10CR1:IF
T10CR1:IR
Interrupt enable
T10CR1:IE and T10CR0:IFE
T10CR1:IE and T10CR0:IFE
T10CR1:IE
■ Timer 11 Interrupt
Table 18.6-4 shows the timer 11 interrupt and its sources.
Table 18.6-4 Timer 11 Interrupt
Description
Item
Overflow in the PWC timer
operation or the input capture
operation, except in 16-bit
operation
Completion of
measurement in the PWC
timer operation or edge
detection in the input
capture operation, except
in 16-bit operation
Interrupt generating
condition
Comparison match in the
interval timer operation or the
PWM timer operation
(variable-cycle mode), except
in 16-bit operation
Interrupt flag
T11CR1:IF
T11CR1:IF
T11CR1:IR
Interrupt enable
T11CR1:IE and T11CR0:IFE
T11CR1:IE and T11CR0:IFE
T11CR1:IE
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.6 Interrupts of 8/16-bit Composite Timer
MB95410H/470H Series
■ Registers and Vector Table Addresses Related to Interrupts of 8/16-bit
Composite Timer
Table 18.6-5 Registers and Vector Table Addresses Related to Interrupts of 8/16-bit Composite
Timer
Interrupt source
Interrupt
request no.
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
8/16-bit composite
timer ch. 0 (lower) /
Timer 00
IRQ05
ILR1
L05
FFF0H
FFF1H
8/16-bit composite
timer ch. 0 (upper) /
Timer 01
IRQ06
ILR1
L06
FFEEH
FFEFH
8/16-bit composite
timer ch. 1 (lower) /
Timer 10
IRQ22
ILR5
L22
FFCEH
FFCFH
8/16-bit composite
timer ch. 1 (upper) /
Timer 11
IRQ14
ILR3
L14
FFDEH
FFDFH
ch.: Channel
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.7 Operation of Interval Timer Function (One-shot
Mode)
MB95410H/470H Series
18.7
Operation of Interval Timer Function (One-shot
Mode)
This section describes the operation of the interval timer function (one-shot
mode) of the 8/16-bit composite timer.
■ Operation of Interval Timer Function (One-shot Mode) (Timer 0)
To use the interval timer function (one-shot mode), do the settings shown in Figure 18.7-1.
Figure 18.7-1 Settings of Interval Timer Function (One-shot Mode) (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
0
0
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
❍
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
❍
❍
❍
❍
❍
❍
T00DR/T01DR
Sets interval time (counter compare value)
❍: Used bit
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (one-shot mode), enabling timer operation (T00CR1/
T01CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value of the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR), the timer output (TMCR0:TO0/TO1) is
inverted, the interrupt flag (T00CR1/T01CR1:IF) is set to "1", the start bit (T00CR1/
T01CR1:STA) is set to "0", and the counter stops counting.
The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator when the counter
starts counting. Do not write "00H" to the 8/16-bit composite timer 00/01 data register.
Figure 18.7-2 shows the operation of the interval timer function in 8-bit operation (Timer 0).
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18.7 Operation of Interval Timer Function (One-shot
Mode)
Figure 18.7-2 Operation of Interval Timer Function in 8-bit Mode (One-shot Mode) (Timer 0)
MB95410H/470H Series
Counter value FFH
80H
00H
Time
T00DR/T01DR
value (FFH)
Timer cycle
T00DR/T01DR value modified (FFH→80H)*
Cleared
by program
IF bit
STA bit
Automatically cleared
Inverted
Reactivated
Automatically cleared Reactivated
Reactivated with output initial value unchanged ("0")
Timer output pin
For initial value "1" on activation
*: If the T00DR/T01DR data register value is modified during operation, the new value is used from the next active cycle.
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18.7 Operation of Interval Timer Function (One-shot
Mode)
MB95410H/470H Series
■ Operation of Interval Timer Function (One-shot Mode) (Timer 1)
To use the interval timer function (one-shot mode), do the settings shown in Figure 18.7-3.
Figure 18.7-3 Settings of Interval Timer Function (One-shot Mode) (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
0
0
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
❍
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
❍
❍
❍
❍
❍
❍
T10DR/T11DR
Sets interval time (counter compare value)
❍: Used bit
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (one-shot mode), enabling timer operation (T10CR1/
T11CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value of the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR), the timer output (TMCR1:TO0/TO1) is
inverted, the interrupt flag (T10CR1/T11CR1:IF) is set to "1", the start bit (T10CR1/
T11CR1:STA) is set to "0", and the counter stops counting.
The value of the 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator when the counter
starts counting. Do not write "00H" to the 8/16-bit composite timer 10/11 data register.
Figure 18.7-4 shows the operation of the interval timer function in 8-bit operation (Timer 1).
Figure 18.7-4 Operation of Interval Timer Function in 8-bit Mode (One-shot Mode) (Timer 1)
Counter value FFH
80H
00H
Time
T10DR/T11DR
value (FFH)
Timer cycle
T10DR/T11DR value modified (FFH→80H)*
Cleared
by program
IF bit
STA bit
Automatically cleared
Inverted
Reactivated
Automatically cleared Reactivated
Reactivated with output initial value unchanged ("0")
Timer output pin
For initial value "1" on activation
*: If the T10DR/T11DR data register value is modified during operation, the new value is used from the next active cycle.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.8 Operation of Interval Timer Function (Continuous
Mode)
18.8
MB95410H/470H Series
Operation of Interval Timer Function (Continuous
Mode)
This section describes the interval timer function (continuous mode operation)
of the 8/16-bit composite timer.
■ Operation of Interval Timer Function (Continuous Mode) (Timer 0)
To use the interval timer function (continuous mode), do the settings shown in Figure 18.8-1.
Figure 18.8-1 Settings for Interval Timer Function (Continuous Mode) (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
0
1
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T00DR/T01DR
Sets interval time (counter compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (continuous mode), enabling timer operation (T00CR1/
T01CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value in the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR), the timer output bit (TMCR0:TO0/TO1)
is inverted, the interrupt flag (T00CR1/T01CR1:IF) is set to "1", and the counter returns to
"00H" and restarts counting. The timer outputs square wave as a result of this continuous
operation.
The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected. Do not write
"00H" to the 8/16-bit composite timer 00/01 data register while the counter is counting.
When the timer stops operating, the timer output bit (TMCR0:TO0/TO1) holds the last value.
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18.8 Operation of Interval Timer Function (Continuous
Mode)
Figure 18.8-2 Operation Diagram of Interval Timer Function (Continuous Mode) (Timer 0)
MB95410H/470H Series
Compare value
Compare value
(E0H)
Compare value
(80H)
Compare value
(FFH)
FFH
E0H
80H
00H
Time
T00DR/T01DR value modified (FFH→80H)*1
T00DR/T01DR value (E0H)
Cleared by program
IF bit
STA bit
Activated
Matched
Matched
Matched
Matched
Matched
Counter clear *2
Timer output pin
*1: If the T00DR/T01DR data register value is modified during operation, the new value is used from the next active cycle.
*2: The counter is cleared and the data register settings are loaded into the comparison data latch whenever a match is detected during operation.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.8 Operation of Interval Timer Function (Continuous
Mode)
MB95410H/470H Series
■ Operation of Interval Timer Function (Continuous Mode) (Timer 1)
To use the interval timer function (continuous mode), do the settings shown in Figure 18.8-3.
Figure 18.8-3 Settings for Interval Timer Function (Continuous Mode) (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
0
1
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T10DR/T11DR
Sets interval time (counter compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (continuous mode), enabling timer operation (T10CR1/
T11CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value in the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR), the timer output bit (TMCR1:TO0/TO1)
is inverted, the interrupt flag (T10CR1/T11CR1:IF) is set to "1", and the counter returns to
"00H" and restarts counting. The timer outputs square wave as a result of this continuous
operation.
The value of the 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected. Do not write
"00H" to the 8/16-bit composite timer 10/11 data register while the counter is counting.
When the timer stops operating, the timer output bit (TMCR1:TO0/TO1) holds the last value.
Figure 18.8-4 Operation Diagram of Interval Timer Function (Continuous Mode) (Timer 1)
Compare value
Compare value
(E0H)
Compare value
(80H)
Compare value
(FFH)
FFH
E0H
80H
00H
Time
T10DR/T11DR value modified (FFH→80H)*1
T10DR/T11DR value (E0H)
Cleared by program
IF bit
STA bit
Activated
Matched
Matched
Matched
Matched
Matched
Counter clear *2
Timer output pin
*1: If the T10DR/T11DR data register value is modified during operation, the new value is used from the next active cycle.
*2: The counter is cleared and the data register settings are loaded into the comparison data latch whenever a match is detected during operation.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.9 Operation of Interval Timer Function (Free-run Mode)
MB95410H/470H Series
18.9
Operation of Interval Timer Function (Free-run
Mode)
This section describes the operation of the interval timer function (free-run
mode) of the 8/16-bit composite timer.
■ Operation of Interval Timer Function (Free-run Mode) (Timer 0)
To use the interval timer function (free-run mode), do the settings shown in Figure 18.9-1.
Figure 18.9-1 Settings for Interval Timer Function (Free-run Mode) (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
1
0
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T00DR/T01DR
Sets interval time (counter compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (free-run mode), enabling timer operation (T00CR1/
T00CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value in the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR), the timer output bit (TMCR0:TO0/TO1)
is inverted and the interrupt flag (T00CR1/T01CR1:IF) is set to "1". If the counter continues to
count with the above settings and then reaches "FFH", it returns to "00H" and restarts counting.
The timer outputs square wave as a result of this continuous operation.
The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected. Do not write
"00H" to the 8/16-bit composite timer 00/01 data register.
When the timer stops operation, the timer output bit (TMCR0:TO0/TO1) holds the last value.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.9 Operation of Interval Timer Function (Free-run Mode)
MB95410H/470H Series
Figure 18.9-2 Operation Diagram of Interval Timer Function (Free-run Mode) (Timer 0)
(E0H)
Counter value
FFH
E0H
80H
00H
Time
Though the T00DR/T01DR value is modified, the new value is not transferred to the comparison data latch.
T00DR/T01DR value (E0H)
Cleared by program
IF bit
STA bit
Activated
Matched
Matched
Matched
Matched
Counter value match *
Timer output pin
*: Even though a match is detected during operation, the counter is not cleared and the data register settings are not reloaded into the comparison data latch.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.9 Operation of Interval Timer Function (Free-run Mode)
■ Operation of Interval Timer Function (Free-run Mode) (Timer 1)
To use the interval timer function (free-run mode), do the settings shown in Figure 18.9-3.
Figure 18.9-3 Settings for Interval Timer Function (Free-run Mode) (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
1
0
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
❍
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T10DR/T11DR
Sets interval time (counter compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the interval timer function (free-run mode), enabling timer operation (T10CR1/
T11CR1:STA = 1) causes the counter to start counting from "00H" at the rising edge of a
selected count clock signal. When the counter value matches the value in the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR), the timer output bit (TMCR1:TO0/TO1)
is inverted and the interrupt flag (T10CR1/T11CR1:IF) is set to "1". If the counter continues to
count with the above settings and then reaches "FFH", it returns to "00H" and restarts counting.
The timer outputs square wave as a result of this continuous operation.
The value of the 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected. Do not write
"00H" to the 8/16-bit composite timer 10/11 data register.
When the timer stops operation, the timer output bit (TMCR1:TO0/TO1) holds the last value.
Figure 18.9-4 Operation Diagram of Interval Timer Function (Free-run Mode) (Timer 1)
(E0H)
Counter value
FFH
E0H
80H
00H
Time
Though the T10DR/T11DR value is modified, the new value is not transferred to the comparison data latch.
T10DR/T11DR value (E0H)
Cleared by program
IF bit
STA bit
Activated
Matched
Matched
Matched
Matched
Counter value match *
Timer output pin
*: Even though a match is detected during operation, the counter is not cleared and the data register settings are not reloaded into the comparison data latch.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.10 Operation of PWM Timer Function (Fixed-cycle
Mode)
18.10
MB95410H/470H Series
Operation of PWM Timer Function (Fixed-cycle
Mode)
This section describes the operation of the PWM timer function (fixed-cycle
mode) of the 8/16-bit composite timer.
■ Operation of PWM Timer Function (Fixed-cycle Mode) (Timer 0)
To use the PWM timer function (fixed-cycle mode), do the settings shown in Figure 18.10-1.
Figure 18.10-1 Settings for PWM Timer Function (Fixed-cycle Mode) (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
1
1
STA
HO
IE
IR
BF
IF
SO
OE
❍
❍
×
×
×
×
×
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T00DR/T01DR
Sets "H" pulse width (compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the PWM timer function (fixed-cycle mode), PWM signal that has a fixed cycle and
variable "H" pulse width is output from the timer output pin (TO00/TO01). The cycle is fixed
at "FFH" in 8-bit operation or "FFFFH" in 16-bit operation. The time is determined by the count
clock selected. The "H" pulse width is specified by the value in the 8/16-bit composite timer
00/01 data register (T00DR/T01DR).
This function has no effect on the interrupt flag (T00CR1/T01CR1:IF). Since each cycle
always starts with "H" pulse output, the timer output initial value setting bit (T00CR1/
T01CR1:SO) has no effect on operation.
The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected.
When the timer stops operation, the timer output bit (TMCR0:TO0/TO1) holds the last value.
The "H" pulse is one count clock shorter than the setting value in the output waveform
immediately after activation of the timer (write "1" to the STA bit), the "H" pulse is one count
clock shorter than the value set in the T00DR/T01DR register.
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18.10 Operation of PWM Timer Function (Fixed-cycle
Mode)
Figure 18.10-2 Operation Diagram of PWM Timer Function (Fixed-cycle Mode) (Timer 0)
MB95410H/470H Series
T00DR/T01DR register value: "00H" (duty ratio = 0%)
Counter value
FFH 00H
00H
PWM waveform
"H"
"L"
T00DR/T01DR register value: "80H" (duty ratio = 50%)
Counter value
00H
PWM waveform
80H
FFH 00H
"H"
"L"
T00DR/T01DR register value: "FFH" (duty ratio = 99.6%)
Counter value
00H
FFH 00H
"H"
PWM waveform
"L"
One count width
Note: When the PWM function has been selected, the timer output pin holds the level at the point when the counter stops
(T00CR0/T01CR0:STA = 0).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.10 Operation of PWM Timer Function (Fixed-cycle
Mode)
MB95410H/470H Series
■ Operation of PWM Timer Function (Fixed-cycle Mode) (Timer 1)
To use the PWM timer function (fixed-cycle mode), do the settings shown in Figure 18.10-3.
Figure 18.10-3 Settings for PWM Timer Function (Fixed-cycle Mode) (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
0
1
1
STA
HO
IE
IR
BF
IF
SO
OE
❍
❍
×
×
×
×
×
❍
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
❍
❍
❍
❍
❍
T10DR/T11DR
Sets "H" pulse width (compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the PWM timer function (fixed-cycle mode), PWM signal that has a fixed cycle and
variable "H" pulse width is output from the timer output pin (TO10/TO11). The cycle is fixed
at "FFH" in 8-bit operation or "FFFFH" in 16-bit operation. The time is determined by the count
clock selected. The "H" pulse width is specified by the value in the 8/16-bit composite timer
10/11 data register (T10DR/T11DR).
This function has no effect on the interrupt flag (T10CR1/T11CR1:IF). Since each cycle
always starts with "H" pulse output, the timer output initial value setting bit (T10CR1/
T11CR1:SO) has no effect on operation.
The value of the 8/16-bit composite timer 10/11 data register (T10DR/T11DR) is transferred to
the temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected.
When the timer stops operation, the timer output bit (TMCR1:TO0/TO1) holds the last value.
The "H" pulse is one count clock shorter than the setting value in the output waveform
immediately after activation of the timer (write "1" to the STA bit), the "H" pulse is one count
clock shorter than the value set in the T10DR/T11DR register.
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18.10 Operation of PWM Timer Function (Fixed-cycle
Mode)
Figure 18.10-4 Operation Diagram of PWM Timer Function (Fixed-cycle Mode) (Timer 1)
MB95410H/470H Series
T10DR/T11DR register value: "00H" (duty ratio = 0%)
Counter value
FFH 00H
00H
PWM waveform
"H"
"L"
T10DR/T11DR register value: "80H" (duty ratio = 50%)
Counter value
00H
PWM waveform
80H
FFH 00H
"H"
"L"
T10DR/T11DR register value: "FFH" (duty ratio = 99.6%)
Counter value
00H
FFH 00H
"H"
PWM waveform
"L"
One count width
Note: When the PWM function has been selected, the timer output pin holds the level at the point when the counter stops
(T10CR0/T11CR0:STA = 0).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.11 Operation of PWM Timer Function (Variable-cycle
Mode)
18.11
MB95410H/470H Series
Operation of PWM Timer Function (Variable-cycle
Mode)
This section describes the operation of the PWM timer function (variable-cycle
mode) of the 8/16-bit composite timer.
■ Operation of PWM Timer Function (Variable-cycle Mode) (Timer 0)
To use the PWM timer function (variable-cycle mode), do the settings shown in
Figure 18.11-1.
Figure 18.11-1 Settings for PWM Timer Function (Variable-cycle Mode) (Timer 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
1
0
0
T00CR1/T01CR1
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
×
×
TMCR0
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
×
❍
❍
❍
❍
T00CR0/T01CR0
T00DR
Sets "L" pulse width (compare value)
T01DR
Sets the cycle of PWM waveform (compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the PWM timer function (variable-cycle mode), both timers 00 and 01 are used. PWM
signal of any cycle and of any duty is output from the timer output pin (TO00). The cycle is
specified by the 8/16-bit composite timer 01 data register (T01DR), and the "L" pulse width is
specified by the 8/16-bit composite timer 00 data register (T00DR).
Since both the 8-bit counters are used for this function, the composite timer cannot form a 16bit counter.
Enabling timer operation (by setting either T00CR1:STA = 1 or T01CR1:STA = 1) sets the
mode bit (TMCR0:MOD) to "0". As the first cycle always begins with "L" pulse output, the
timer initial value setting bit (T00CR1/T01CR1:SO) has no effect on operation.
An interrupt flag (T00CR1/T01CR1:IF) is set when the 8-bit counter corresponding to that
interrupt flag matches the value in its corresponding 8/16-bit composite timer 00/01 data
register (T00DR/T01DR).
The 8/16-bit composite timer 00/01 data register value is transferred to the temporary storage
latch (comparison data storage latch) in the comparator either when the counter starts counting
or when a comparison match with each counter value is detected.
"H" is not output when the "L" pulse width setting value is greater than the cycle setting value.
The count clock must be selected for both of timers 00 and 01. Selecting different count clocks
for the two timers is prohibited.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.11 Operation of PWM Timer Function (Variable-cycle
Mode)
When the timer stops operating, the timer output bit (TMCR0:TO0) holds the last output value.
MB95410H/470H Series
If the 8/16-bit composite timer 00/01 data register is modified during operation, the data
written will become valid from the cycle immediately after the detection of a synchronous
match.
Figure 18.11-2 Operation Diagram of PWM Timer Function (Variable-cycle Mode) (Timer 0)
T00DR register value: "80H", and T01DR register value: "80H" (duty ratio = 0%)
(timer 00 value >= timer 01 value)
Counter timer 00 value
Counter timer 01 value
PWM waveform
00H
00H
"H"
80H,00H
80H,00H
80H,00H
80H,00H
"L"
T00DR register value: "40H", and T01DR register value: "80H" (duty ratio = 50%)
Counter timer 00 value
Counter timer 01 value
00H
00H
40H
00H
80H,00H
40H
00H
80H,00H
"H"
PWM waveform
"L"
T00DR register value: "00H", and T01DR register value: "FFH" (duty ratio = 99.6%)
Counter timer 00 value
Counter timer 01 value
00H
FFH,00H
00H
00H
"H"
PWM waveform
"L"
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One count width
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.11 Operation of PWM Timer Function (Variable-cycle
Mode)
MB95410H/470H Series
■ Operation of PWM Timer Function (Variable-cycle Mode) (Timer 1)
To use the PWM timer function (variable-cycle mode), do the settings shown in
Figure 18.11-3.
Figure 18.11-3 Settings for PWM Timer Function (Variable-cycle Mode) (Timer 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T10CR0/T11CR0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
0
1
0
0
T10CR1/T11CR1
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
×
×
TMCR1
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
×
❍
❍
❍
❍
T10DR
Sets "L" pulse width (compare value)
T11DR
Sets the cycle of PWM waveform (compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
As for the PWM timer function (variable-cycle mode), both timers 10 and 11 are used. PWM
signal of any cycle and of any duty is output from the timer output pin (TO10). The cycle is
specified by the 8/16-bit composite timer 11 data register (T11DR), and the "L" pulse width is
specified by the 8/16-bit composite timer 10 data register (T10DR).
Since both the 8-bit counters are used for this function, the composite timer cannot form a 16bit counter.
Enabling timer operation (by setting either T10CR1:STA = 1 or T11CR1:STA = 1) sets the
mode bit (TMCR1:MOD) to "0". As the first cycle always begins with "L" pulse output, the
timer initial value setting bit (T10CR1/T11CR1:SO) has no effect on operation.
An interrupt flag (T10CR1/T11CR1:IF) is set when the 8-bit counter corresponding to that
interrupt flag matches the value in its corresponding 8/16-bit composite timer 10/11 data
register (T10DR/T11DR).
The 8/16-bit composite timer 10/11 data register value is transferred to the temporary storage
latch (comparison data storage latch) in the comparator either when the counter starts counting
or when a comparison match with each counter value is detected.
"H" is not output when the "L" pulse width setting value is greater than the cycle setting value.
The count clock must be selected for both of timers 10 and 11. Selecting different count clocks
for the two timers is prohibited.
When the timer stops operating, the timer output bit (TMCR1:TO0) holds the last output value.
If the 8/16-bit composite timer 10/11 data register is modified during operation, the data
written will become valid from the cycle immediately after the detection of a synchronous
match.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.11 Operation of PWM Timer Function (Variable-cycle
Mode)
Figure 18.11-4 Operation Diagram of PWM Timer Function (Variable-cycle Mode) (Timer 1)
MB95410H/470H Series
T10DR register value: "80H", and T11DR register value: "80H" (duty ratio = 0%)
(timer 10 value >= timer 11 value)
Counter timer 10 value
Counter timer 11 value
PWM waveform
00H
00H
"H"
80H,00H
80H,00H
80H,00H
80H,00H
"L"
T10DR register value: "40H", and T11DR register value: "80H" (duty ratio = 50%)
Counter timer 10 value
Counter timer 11 value
00H
00H
40H
00H
80H,00H
40H
00H
80H,00H
"H"
PWM waveform
"L"
T10DR register value: "00H", and T11DR register value: "FFH" (duty ratio = 99.6%)
Counter timer 10 value
Counter timer 11 value
00H
FFH,00H
00H
00H
"H"
PWM waveform
"L"
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One count width
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.12 Operation of PWC Timer Function
18.12
MB95410H/470H Series
Operation of PWC Timer Function
This section describes the operation of the PWC timer function of the 8/16-bit
composite timer.
■ Operation of PWC Timer Function (Timer 0)
To use the PWC timer function, do the settings shown in Figure 18.12-1.
Figure 18.12-1 Settings for PWC Timer Function (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
❍
❍
❍
❍
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
❍
❍
❍
×
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
❍
❍
❍
❍
❍
❍
T00DR/T01DR
Holds pulse width measurement value
❍: Bit to be used
×: Unused bit
1: Set to "1"
When the PWC timer function is selected, the width and cycle of an external input pulse can be
measured. The edges at which counting starts and ends are selected by the timer operating
mode select bits (T00CR0/T01CR0:F3, F2, F1, F0).
In the operation of this function, the counter starts counting from "00H" immediately after a
specified count start edge of an external input signal is detected. Upon the detection of a
specified count end edge, the count value is transferred to the 8/16-bit composite timer 00/01
data register (T00DR/T01DR), and the interrupt flag (T00CR1/T01CR1:IR) and the buffer full
flag (T00CR1/T01CR1:BF) are set to "1". The buffer full flag is set to "0" when the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR) is read.
If the buffer full flag is set to "1", the 8/16-bit composite timer 00/01 data register holds data.
Even if the next edge is detected during that time, the next measurement result is lost since the
count value has not been transferred to the 8/16-bit composite timer 00/01 data register.
There is an exception. With the F3 bit to F0 bit in the T00CR0/T01CR0 register having been
set to "1001B", even though the BF bit is set to "1", the "H" pulse measurement result is
transferred to the 8/16-bit composite timer 00/01 data register, while the cycle measurement
result is not transferred to the 8/16-bit composite timer 00/01 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a cycle is
completed. In addition, the result of "H" pulse measurement and that of cycle measurement are
lost if they are not read before the completion of the next "H" pulse.
To measure the time exceeding the range of the counter, software can be used to count the
number of counter overflows. When the counter overflows, the interrupt flag (T00CR1/
T01CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the
number of overflows. In addition, the timer output is inverted due to the overflow. The timer
output initial value can be set by the timer output initial value bit (T00CR1/T01CR1:SO).
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MB95410H/470H Series
CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.12 Operation of PWC Timer Function
When the timer stops operating, the timer output bit (TMCR0:TO1/TO0) holds the last value.
Figure 18.12-2 Operation Diagram of PWC Timer (Example of H-pulse Width Measurement)
(Timer 0)
"H" width
Pulse input
(Input waveform to PWC pin)
Counter value
FFH
Time
STA bit
Counter
operation
Cleared by program
IR bit
BF bit
Data transferred from
counter to T00DR/T01DR T00DR/T01DR data register read
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.12 Operation of PWC Timer Function
MB95410H/470H Series
■ Operation of PWC Timer Function (Timer 1)
To use the PWC timer function, do the settings shown in Figure 18.12-3.
Figure 18.12-3 Settings for PWC Timer Function (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
❍
❍
❍
❍
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
❍
❍
❍
×
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
❍
❍
❍
❍
❍
❍
T10DR/T11DR
Holds pulse width measurement value
❍: Bit to be used
×: Unused bit
1: Set to "1"
When the PWC timer function is selected, the width and cycle of an external input pulse can be
measured. The edges at which counting starts and ends are selected by the timer operating
mode select bits (T10CR0/T11CR0:F3, F2, F1, F0).
In the operation of this function, the counter starts counting from "00H" immediately after a
specified count start edge of an external input signal is detected. Upon the detection of a
specified count end edge, the count value is transferred to the 8/16-bit composite timer 10/11
data register (T10DR/T11DR), and the interrupt flag (T10CR1/T11CR1:IR) and the buffer full
flag (T10CR1/T11CR1:BF) are set to "1". The buffer full flag is set to "0" when the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR) is read.
If the buffer full flag is set to "1", the 8/16-bit composite timer 10/11 data register holds data.
Even if the next edge is detected during that time, the next measurement result is lost since the
count value has not been transferred to the 8/16-bit composite timer 10/11 data register.
There is an exception. With the F3 bit to F0 bit in the T10CR0/T11CR0 register having been
set to "1001B", even though the BF bit is set to "1", the "H" pulse measurement result is
transferred to the 8/16-bit composite timer 10/11 data register, while the cycle measurement
result is not transferred to the 8/16-bit composite timer 10/11 data register. Therefore, in order
to perform cycle measurement, the "H" pulse measurement result must be read before a cycle is
completed. In addition, the result of "H" pulse measurement and that of cycle measurement are
lost if they are not read before the completion of the next "H" pulse.
To measure the time exceeding the range of the counter, software can be used to count the
number of counter overflows. When the counter overflows, the interrupt flag (T10CR1/
T11CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the
number of overflows. In addition, the timer output is inverted due to the overflow. The timer
output initial value can be set by the timer output initial value bit (T10CR1/T11CR1:SO).
When the timer stops operating, the timer output bit (TMCR1:TO1/TO0) holds the last value.
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MB95410H/470H Series
CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.12 Operation of PWC Timer Function
Figure 18.12-4 Operation Diagram of PWC Timer (Example of H-pulse Width Measurement)
(Timer 1)
"H" width
Pulse input
(Input waveform to PWC pin)
Counter value
FFH
Time
STA bit
Counter
operation
Cleared by program
IR bit
BF bit
Data transferred from
counter to T10DR/T11DR T10DR/T11DR data register read
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.13 Operation of Input Capture Function
18.13
MB95410H/470H Series
Operation of Input Capture Function
This section describes the operation of the input capture function of the 8/16bit composite timer.
■ Operation of Input Capture Function (Timer 0)
To use the input capture function, do the settings shown in Figure 18.13-1.
Figure 18.13-1 Settings for Input Capture Function (Timer 0)
T00CR0/T01CR0
T00CR1/T01CR1
TMCR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
❍
❍
❍
❍
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
×
❍
×
×
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
×
×
❍
❍
❍
❍
❍
❍
T00DR/T01DR
Holds pulse width measurement value
❍: Bit to be used
×: Unused bit
1: Set to "1"
When the input capture function is selected, the counter value is stored to the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR) immediately after an edge of the external
signal input is detected. The target edge to be detected is selected by the timer operating mode
select bits (T00CR0/T01CR0:F3, F2, F1, F0).
This function is available in free-run mode and clear mode, which can be selected by the timer
operating mode select bits.
In clear mode, the counter starts counting from "00H". When an edge is detected, the counter
value is transferred to the 8/16-bit composite timer 00/01 data register (T00DR/T01DR), the
interrupt flag (T00CR1/T01CR1:IR) is set to "1", and the counter returns to "00H" and restarts
counting.
In free-run mode, when an edge is detected, the counter value is transferred to the 8/16-bit
composite timer 00/01 data register (T00DR/T01DR) and the interrupt flag (T00CR1/
T01CR1:IR) is set to "1". In this case, the counter continues to count without being cleared.
This function has no effect on the buffer full flag (T00CR1/T01CR1:BF).
To measure the time exceeding the range of the counter, software can be used to count the
number of counter overflows. When the counter overflows, the interrupt flag (T00CR1/
T01CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the
number of overflows. In addition, the timer output is inverted due to the overflow. The timer
output initial value can be set by the timer output initial value bit (T00CR1/T01CR1:SO).
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.13 Operation of Input Capture Function
MB95410H/470H Series
Note:
See "18.16 Notes on Using 8/16-bit Composite Timer" for notes on using the input
capture function.
Figure 18.13-2 Operating Diagram of Input Capture Function (Timer 0)
FFH
BFH
9FH
7FH
3FH
Capture value
in T00DR/T01DR
BFH
Falling edge of capture
External input
Counter clear mode
MN702-00005-2v0-E
7FH
3FH
Rising edge of capture
Falling edge of
capture
9FH
Rising edge of
capture
Counter free-run mode
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.13 Operation of Input Capture Function
MB95410H/470H Series
■ Operation of Input Capture Function (Timer 1)
To use the input capture function, do the settings shown in Figure 18.13-3.
Figure 18.13-3 Settings for Input Capture Function (Timer 1)
T10CR0/T11CR0
T10CR1/T11CR1
TMCR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
❍
❍
❍
❍
❍
❍
❍
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
❍
×
❍
×
×
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
×
×
❍
❍
❍
❍
❍
❍
T10DR/T11DR
Holds pulse width measurement value
❍: Bit to be used
×: Unused bit
1: Set to "1"
When the input capture function is selected, the counter value is stored to the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR) immediately after an edge of the external
signal input is detected. The target edge to be detected is selected by the timer operating mode
select bits (T10CR0/T11CR0:F3, F2, F1, F0).
This function is available in free-run mode and clear mode, which can be selected by the timer
operating mode select bits.
In clear mode, the counter starts counting from "00H". When an edge is detected, the counter
value is transferred to the 8/16-bit composite timer 10/11 data register (T10DR/T11DR), the
interrupt flag (T10CR1/T11CR1:IR) is set to "1", and the counter returns to "00H" and restarts
counting.
In free-run mode, when an edge is detected, the counter value is transferred to the 8/16-bit
composite timer 10/11 data register (T10DR/T11DR) and the interrupt flag (T10CR1/
T11CR1:IR) is set to "1". In this case, the counter continues to count without being cleared.
This function has no effect on the buffer full flag (T10CR1/T11CR1:BF).
To measure the time exceeding the range of the counter, software can be used to count the
number of counter overflows. When the counter overflows, the interrupt flag (T10CR1/
T11CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the
number of overflows. In addition, the timer output is inverted due to the overflow. The timer
output initial value can be set by the timer output initial value bit (T10CR1/T11CR1:SO).
Note:
See "18.16 Notes on Using 8/16-bit Composite Timer" for notes on using the input
capture function.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.13 Operation of Input Capture Function
MB95410H/470H Series
Figure 18.13-4 Operating Diagram of Input Capture Function (Timer 1)
FFH
BFH
9FH
7FH
3FH
Capture value
in T10DR/T11DR
BFH
Falling edge of capture
External input
Counter clear mode
MN702-00005-2v0-E
7FH
3FH
Rising edge of capture
Falling edge of
capture
9FH
Rising edge of
capture
Counter free-run mode
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.14 Operation of Noise Filter
18.14
MB95410H/470H Series
Operation of Noise Filter
This section describes the operation of the noise filter of the 8/16-bit composite
timer.
When the input capture function or PWC timer function is selected, a noise filter can be used to
eliminate the pulse noise of the signal from the external input pin (EC0/EC1). H-pulse noise,
L-pulse noise, or H/L-pulse noise elimination can be selected by setting the FE11, FE10, FE01
and FE00 bits in the TMCR0 and TMCR1 register. The maximum pulse width that can be
eliminated is three machine clock cycles. If the noise filter function is activated, the signal
input will be delayed for four machine clock cycles.
Figure 18.14-1 Operation of Noise Filter
Sample
filter clock
External
input signal
Output filter
"H" noise
Output filter
"L" noise
Output filter
"H"/"L" noise
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.15 States in Each Mode during Operation
MB95410H/470H Series
18.15 States in Each Mode during Operation
This section describes how the 8/16-bit composite timer behaves when the
microcontroller transits to watch mode or stop mode or when a suspend
(T00CR1/T01CR1/T10CR1/T11CR1:HO = 1) request is made during operation.
■ When Interval Timer, Input Capture, or PWC Function Is Selected
Figure 18.15-1 shows how the counter value changes when the microcontroller transits to
watch mode or stop mode, or a suspend request is made during the operation of the 8/16-bit
composite timer.
The counter stops operating while holding the value when the microcontroller transits to stop
mode or watch mode. When the stop mode or watch mode is released by an interrupt, the
counter resumes operating with the last value that it holds. Therefore, the first interval time or
the initial external clock count value is incorrect. Always initialize the counter value after the
microcontroller is released from stop mode or watch mode.
Figure 18.15-1 Operations of Counter in Standby Mode or in Pause (Not Serving as PWM
Timer)
T00DR/T01DR data register value (FFH)
Counter value
FFH
80H
00H
Timer cycle
Time
Request ends
HO request
HO request ends
Delay of oscillation stabilization wait time
Interval time after wake-up
from stop mode (indeterminate)
IF bit
Operation halts
Cleared by program
STA bit
Operation history
Operation reactivated
HO bit
IE bit
Sleep mode
SLP bit
(STBC register)
Wake-up from stop mode by external interrupt
Wake-up from sleep mode by interrupt
STP bit
(STBC register)
Stop mode
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.15 States in Each Mode during Operation
MB95410H/470H Series
Figure 18.15-2 Operations of Counter in Standby Mode or in Pause (Serving as PWM Timer)
(FFH)
Counter value
FFH
00H
Delay of oscillation stabilization wait time
T00DR/T01DR value (FFH)
STA bit
Time
*
PWM timer output pin
SLP bit
Sleep mode
Maintains the level prior to stop
Maintains the level prior to hold
(STBC register)
Wake-up from stop mode by external interrupt
Wake-up from sleep mode by interrupt
STP bit
(STBC register)
HO bit
*: The PWM timer output maintains the value held before it enters the stop mode.
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.16 Notes on Using 8/16-bit Composite Timer
MB95410H/470H Series
18.16 Notes on Using 8/16-bit Composite Timer
This section provides notes on using the 8/16-bit composite timer.
■ Notes on Using 8/16-bit Composite Timer
• To switch the timer function with the timer operating mode select bits (T00CR0/T01CR0/
T10CR0/T11CR0:F3, F2, F1, F0), stop the timer operation first (T00CR1/T01CR1/
T10CR1/T11CR1:STA = 0), then clear the interrupt flag (T00CR1/T01CR1/T10CR1/
T11CR1:IF, IR), the interrupt enable bits (T00CR1/T01CR1/T10CR1/T11CR1:IE,
T00CR0/T01CR0/T10CR0/T11CR0:IFE) and the buffer full flag (T00CR1/T01CR1/
T10CR1/T11CR1:BF).
• In the case of using the input capture function, when both edges of the external input signal
is selected as the timing at which the 8/16-bit composite timer captures a counter value
(T00CR0/T01CR0/T10CR0/T11CR0:F3, F2, F1, F0 = 1100B or 1111B) while "H" level
external input signal is being input, the first falling edge will be ignored, no counter value
will be transferred to the data register (T00DR/T01DR/T10DR/T11DR), and pulse width
measurement completion/edge detection flag (T00CR1/T01CR1/T10CR1/T11CR1:IR) will
not be set either.
- In counter clear mode, the counter will not be cleared at the first falling edge and no data
will be transferred to the data register either. The 8/16-bit composite timer will start the
input capture operation from the next rising edge.
- In counter free-run mode, no data will be transferred to the data register at the first falling
edge. The 8/16-bit composite timer will start the input capture operation from the next
rising edge.
• In 8-bit operating mode (TMCR0/TMCR1:MOD = 0) of the PWM timer function (variablecycle mode), when modifying the 8/16-bit composite timer 00/01 data register (T00DR/
T01DR) during counter operation, modify T01DR first and then T00DR. The same setting
sequence requirement is also applicable to the 8/16-bit composite timer 10/11 data register
(T10DR/T11DR).
• Note that 8/16-bit composite timer ch. 1 is to be used when Event Counter operates in event
counter mode. For details on Event Counter, see "CHAPTER 20 EVENT COUNTER".
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CHAPTER 18 8/16-BIT COMPOSITE TIMER
18.16 Notes on Using 8/16-bit Composite Timer
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CHAPTER 19
16-BIT RELOAD TIMER
This chapter describes the functions and
operations of the 16-bit reload timer.
19.1 Overview of 16-bit Reload Timer
19.2 Configuration of 16-bit Reload Timer
19.3 Channels of 16-bit Reload Timer
19.4 Pins of 16-bit Reload Timer
19.5 Registers of 16-bit Reload Timer
19.6 Interrupts of 16-bit Reload Timer
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
19.8 Notes on Using 16-bit Reload Timer
19.9 Sample Settings for 16-bit Reload Timer
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CHAPTER 19 16-BIT RELOAD TIMER
19.1 Overview of 16-bit Reload Timer
19.1
MB95410H/470H Series
Overview of 16-bit Reload Timer
The 16-bit reload timer has two counter operation modes available in the
following two clock modes.
The 16-bit reload timer can be used as an interval timer by generating an
interrupt when an underflow occurs in the timer.
■ Operation Modes of 16-bit Reload Timer
Table 19.1-1 shows the operation modes of the 16-bit reload timer.
Table 19.1-1 Operation Modes of 16-bit Reload Timer
Clock mode
Counter operation mode
Trigger operation mode
Reload mode
Software trigger operation
External trigger input operation
External gate input operation
Internal clock mode
One-shot mode
Reload mode
Event count mode
(external clock mode)
One-shot mode
Software trigger operation
■ Internal Clock Mode
Internal clock mode is selected when any value other than "111B" is set in the count clock
setting bits (CSL2 to CSL0) of the 16-bit reload timer control status register upper
(TMCSRH0).
In internal clock mode, the following three trigger operation modes are available.
● Software trigger operation
With the count enable bit (CNTE) in the 16-bit reload timer control status register lower
(TMCSRL0) set to "1", the counter starts when the software trigger bit (TRG) in the
TMCSRL0 register is set to "1".
● External trigger input operation
When the count enable bit (CNTE) in the 16-bit reload timer control status register lower
(TMCSRL0) is set to "1", the count will start if a valid edge (rising, falling, or both selectable)
specified by the operation mode setting bits (MOD2 to MOD0) is input to the TI0 pin.
● External gate input operation
When the count enable bit (CNTE) in the 16-bit reload timer control status register lower
(TMCSRL0) is set to "1", the count will start if a valid trigger input level ("L" or "H"
selectable) specified by the operation mode setting bits (MOD2 to MOD0) is input to the TI0
pin.
■ Event Count Mode (External Clock Mode)
When the count clock setting bits (CSL2 to CSL0) in the 16-bit reload timer control status
register upper (TMCSRH0) are set to "111B", the count will start if a valid edge of trigger input
(rising, falling, or both) specified by the operation mode setting bits (MOD2 to MOD0) is input
to the TI0 pin. When an external clock is input in regular cycles, the reload timer can also be
used as an interval timer.
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CHAPTER 19 16-BIT RELOAD TIMER
19.1 Overview of 16-bit Reload Timer
■ Counter Operation Mode
● Reload mode
The value of the 16-bit reload timer reload register (TMRLRH0/TMRLRL0) is loaded to the
16-bit down-counter and the count continues when an underflow occurs on the 16-bit downcounter ("0000H" → "FFFFH"). Also, the interrupt request is output by an underflow, so the
mode can be used as the interval timer.
● One-shot mode
An interrupt is outputted when an underflow occurs on the 16-bit down-counter.
During counter operation, the TO0 pin outputs a square waveform indicating that the counter is
currently running.
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CHAPTER 19 16-BIT RELOAD TIMER
19.2 Configuration of 16-bit Reload Timer
19.2
MB95410H/470H Series
Configuration of 16-bit Reload Timer
The 16-bit reload timer consists of the following blocks:
• Count clock generation circuit
• Reload control circuit
• Output control circuit
• Operation control circuit
• 16-bit reload timer timer register (TMRH0, TMRL0)
• 16-bit reload timer reload register (TMRLRH0, TMRLRL0)
• 16-bit reload timer control status register (TMCSRH0, TMCSRL0)
■ Block Diagram of 16-bit Reload Timer
Figure 19.2-1 shows the block diagram of the 16-bit reload timer.
Figure 19.2-1 Block Diagram of 16-bit Reload Timer
Internal bus
16-bit reload timer reload register
(TMRLRH0, TMRLRL0)
Reload
Reload
control circuit
16-bit reload timer timer register
(TMRH0, TMRL0)
CLK
Count clock generation circuit
Pin
Output control circuit
Input
control circuit
Valid clock
judgment
circuit
TI0
Clock
selection
Internal clock
Inversion
Output signal
generation
circuit
Pin
Enable
CLK
Wait
Operation
control
circuit
Select
Function
selection
16-bit reload timer control
status register upper (TMCSRH0)
CSL2
TO0
CSL1 CSL0 MOD2 MOD1 MOD0
OUTE OUTL RELD INTE
UF CNTE TRG
16-bit reload timer control
status register lower (TMCSRL0)
Interrupt request
signal
Internal bus
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CHAPTER 19 16-BIT RELOAD TIMER
19.2 Configuration of 16-bit Reload Timer
● Count clock generation circuit
The count clock for the 16-bit reload timer is outputted from the internal clock or TI0 pin input
signal.
● Reload control circuit
This circuit controls reload operation when the timer is started or an underflow occurs.
● Output control circuit
This circuit controls the inversion of TO0 pin output by an underflow of the 16-bit downcounter and the enabling and disabling of TO0 pin output.
● Operation control circuit
This circuit controls the starting and stopping of the 16-bit down-counter.
● 16-bit reload timer timer register (TMRH0, TMRL0)
TMRH0 and TMRL0 form a 16-bit down-counter. Reading returns the current count value.
● 16-bit reload timer reload register (TMRLRH0, TMRLRL0)
This register sets the load value to the 16-bit down-counter. The register loads the setting value
of the 16-bit reload timer reload register to the 16-bit down-counter to down count.
● 16-bit reload timer control status register (TMCSRH0, TMCSRL0)
This register controls the count clock operation mode, clock selection, interrupts and other
aspects of the 16-bit reload timer as well as indicates the current operation status.
■ Input Clock
The 16-bit reload timer uses the output clock from the prescaler or the input signal from the
TI0 pin as its input clock (count clock).
When Event Counter operates in event counter mode, external clock input from the TI0 pin is
gated by the PWM output signal of 8/16-bit composite timer ch.1, and then input to the 16-bit
reload timer as count clock. For details on this function, See "CHAPTER 20 EVENT
COUNTER".
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CHAPTER 19 16-BIT RELOAD TIMER
19.3 Channels of 16-bit Reload Timer
MB95410H/470H Series
Channels of 16-bit Reload Timer
19.3
This section describes the channels of the 16-bit reload timer.
■ Channels of 16-bit Reload Timer
The MB95410H/470H Series has one channel of the 16-bit reload timer. Table 19.3-1 and
Table 19.3-2 show the correspondence of the channel, pin and register.
Table 19.3-1 Pins of 16-bit Reload Timer
Channel
0
Pin name
Pin function
TO0
16-bit reload timer output
TI0
16-bit reload timer input
Table 19.3-2 Registers of 16-bit Reload Timer
Channel
0
424
Register
abbreviation
Register
TMCSRH0
16-bit reload timer control status register upper
TMCSRL0
16-bit reload timer control status register lower
TMRH0
16-bit reload timer timer register upper
TMRL0
16-bit reload timer timer register lower
TMRLRH0
16-bit reload timer reload register upper
TMRLRL0
16-bit reload timer reload register lower
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19.4
Pins of 16-bit Reload Timer
CHAPTER 19 16-BIT RELOAD TIMER
19.4 Pins of 16-bit Reload Timer
This section describes the pins of the 16-bit reload timer and shows the block
diagram of these pins.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer are namely the TI0 and TO0 pins.
● TI0 pin
This pin is used both as a general-purpose I/O port and as an external pulse input pin for the
counter (TI0).
TI0: Any pulse edge input to this pin is counted during counter operation. To use it as the TI0
pin in counter operation, set the port direction register (DDR5:bit2 in the MB95410H
Series, DDR1:bit4 in the MB95470H Series) to "0" and use the pin as an input port.
● TO0 pin
This pin is used both as a general-purpose I/O port and as the output pin of the 16-bit reload
timer (TO0).
TO0: The pin outputs a waveform of the 16-bit reload timer.
When using this pin as the TO0 pin for the 16-bit reload timer, enabling timer output
(TMCSRL0:OUTE = 1) allows output to be performed automatically regardless of the
setting of the port direction register (DDR5:bit3 in the MB95410H Series, DDR1:bit0 in
the MB95470H Series) and the pin to serve as the TO0 pin of the timer output.
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CHAPTER 19 16-BIT RELOAD TIMER
19.4 Pins of 16-bit Reload Timer
MB95410H/470H Series
■ Block Diagrams of Pins of 16-bit Reload Timer (MB95410H Series)
Figure 19.4-1 Block Diagram of TO0 of 16-bit Reload Timer
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 19.4-2 Block Diagram of TI0 of 16-bit Reload Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 19 16-BIT RELOAD TIMER
19.4 Pins of 16-bit Reload Timer
MB95410H/470H Series
■ Block Diagrams of Pins of 16-bit Reload Timer (MB95470H Series)
Figure 19.4-3 Block Diagram of TO0 of 16-bit Reload Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Hysteresis
Peripheral function output
Pull-up
0
1
PDR read
CMOS
1
pin
PDR
0
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
ILSR read
ILSR
ILSR write
Figure 19.4-4 Block Diagram of TI0 of 16-bit Reload Timer
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
19.5
MB95410H/470H Series
Registers of 16-bit Reload Timer
This section describes the registers of the 16-bit reload timer.
■ Registers of 16-bit Reload Timer
Figure 19.5-1 shows the registers of the 16-bit reload timer.
Figure 19.5-1 Registers of 16-bit Reload Timer
16-bit reload timer control status register upper (TMCSRH0)
Address
bit7
bit6
bit5
bit4
bit3
bit2
003EH
CSL2
CSL1
CSL0
MOD2
R0/WX R0/WX
R/W
R/W
R/W
R/W
bit1
MOD1
R/W
bit0
MOD0
R/W
Initial value
00000000B
16-bit reload timer control status register lower (TMCSRL0)
Address
bit7
bit6
bit5
bit4
bit3
003FH
OUTE
OUTL
RELD
INTE
R0/WX
R/W
R/W
R/W
R/W
bit0
TRG
R0,W
Initial value
00000000B
R(RM1),W
bit1
CNTE
R/W
bit2
UF
16-bit reload timer timer register upper (TMRH0)
Address
bit7
bit6
bit5
bit4
0FA6H
D15
D14
D13
D12
R/W
R/W
R/W
R/W
bit3
D11
R/W
bit2
D10
R/W
bit1
D9
R/W
bit0
D8
R/W
Initial value
00000000B
16-bit reload timer timer register lower (TMRL0)
Address
bit7
bit6
bit5
bit4
0FA7H
D7
D6
D5
D4
R/W
R/W
R/W
R/W
bit3
D3
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
16-bit reload timer reload register upper (TMRLRH0)
Address
bit7
bit6
bit5
bit4
bit3
0FA6H
D15
D14
D13
D12
D11
R/W
R/W
R/W
R/W
R/W
bit2
D10
R/W
bit1
D9
R/W
bit0
D8
R/W
Initial value
00000000B
16-bit reload timer reload register lower (TMRLRL0)
Address
bit7
bit6
bit5
bit4
bit3
0FA7H
D7
D6
D5
D4
D3
R/W
R/W
R/W
R/W
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
R/W
R(RM1), W
R0,W
R0/WX
-
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the
read-modify-write (RMW) type of instruction.)
: Write only (Writable. The read value is "0".)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
Note: TMRH0 and TMRLRH0 are assigned to the same address.
TMRL0 and TMRLRL0 are assigned to the same address.
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
MB95410H/470H Series
19.5.1
16-bit Reload Timer Control Status Register Upper
(TMCSRH0)
The 16-bit reload timer control status register upper (TMCSRH0) sets the
operation mode and operating conditions of the 16-bit reload timer.
■ 16-bit Reload Timer Control Status Register Upper (TMCSRH0)
Figure 19.5-2 16-bit Reload Timer Control Status Register Upper (TMCSRH0)
bit7
bit6
bit5
bit4
-
-
CSL2
CSL1
CSL0 MOD2 MOD1 MOD0
R/W
R/W
Address
003EH
R0/WX R0/WX R/W
bit3
bit2
R/W
bit1
R/W
bit0
Initial value
00000000B
R/W
Operation mode select bits
MOD2 MOD1 MOD0
(In internal clock mode, CSL2,1,0 = any value other than 111B)
Input pin function Valid edge, level
0
0
0
0
1
1
0
0
1
1
X*1
X*1
0
1
0
1
0
1
External input invalid
Trigger input
Gate input
Rising edge
Falling edge
Both edges
"L" level
"H" level
Operation mode select bits
MOD2 MOD1 MOD0
(In event count mode, CSL2,1,0 = 111B)
Input pin function
MCLK
FCH
FCRH
R/W
R0/WX
-
:
:
:
:
:
:
:
0
0
0
0
1
0
0
1
1
X*1
0
1
0
1
X*1
CSL2
CSL1
CSL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
External input invalid
Trigger input
Valid edge
Rising edge
Falling edge
Both edges
Setting disabled
Count clock select bits
Operation mode
Count clock
MCLK
MCLK/2
MCLK/4
Internal clock
MCLK/8
MCLK/16
MCLK/32
FCH*2/27 or FCRH/26 *3
Event count
TIx pin
Machine clock
Main clock
Main CR clock
Readable/writable (The read value is the same as the write value.)
The read value is "0". Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
*1 : Either "0" or "1" can be selected.
*2 : When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
*3 : The value to be used as the count clock is decided according to the settings of the SYCC2 register.
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
MB95410H/470H Series
Table 19.5-1 Functions of Bits in 16-bit Reload Timer Timer Control Status Register Upper
(TMCSRH0)
Bit name
bit7,
bit6
Undefined bits
bit5
to
bit3
CSL2, CSL1,
CSL0:
Count clock select bits
bit2
to
bit0
MOD2, MOD1,
MOD0:
Operation mode select
bits
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
These bits select the count clock for the 16-bit reload timer.
Writing any value other than "111": Internal clock is counted (internal clock mode). The
internal clock is generated by the prescaler. See
"6.13 Operation of Prescaler".
Writing "111": Edge of the external event clock is counted (event count mode).
These bits set the operating conditions of the 16-bit reload timer.
• Internal clock mode (CSL2 to CSL0 = any value other than 111B)
The MOD2 bit selects the input pin function.
Writing "0" to the MOD2 bit:
- TI0 pin serves as a trigger input.
- MOD1 and MOD0 bits are used to select the edge to be detected.
- When the edge is detected, the value set in the 16-bit reload timer reload register is
reloaded in the 16-bit reload timer timer register (TMR) and the TMR starts counting.
Writing "1" to the MOD2 bit:
- TI0 pin serves as a gate input.
- Setting the MOD1 bit is invalid.
- The MOD0 bit is used to select the valid signal level (H or L).
The TMR only counts while the valid signal level is being input.
Note:
External input is disabled when MOD2 to MOD0 are "000". In this case, the TRG
bit is used to start operation by software.
• Event count mode (CSL2 to CSL0 = 111B)
- The MOD2 bit is always fixed to "0".
- The external event clock is input from the TI0 pin.
- The MOD1 and MOD0 bits are used to select the edge to be detected.
*: When Event Counter operates in event counter mode, external clock input from the TI0
pin is gated by the PWM output signal of 8/16-bit composite timer ch.1, and then input
to 16-bit reload timer as count clock. For detail on this function, see "CHAPTER 20
EVENT COUNTER".
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
MB95410H/470H Series
19.5.2
16-bit Reload Timer Control Status Register Lower
(TMCSRL0)
The 16-bit reload timer control status register lower (TMCSRL0) sets the
operating conditions of the 16-bit reload timer, enables or disables counting,
controls interrupts, and checks the interrupt request status.
■ 16-bit Reload Timer Control Status Register Lower (TMCSRL0)
Figure 19.5-3 16-bit Reload Timer Control Status Register Lower (TMCSRL0)
bit7
Address
003FH
-
bit6
bit5
bit4
OUTE OUTL RELD
R0/WX R/W
R/W
R/W
TRG
0
1
CNTE
0
1
UF
0
1
bit3
bit2
bit1
bit0
Initial value
INTE
UF
CNTE
TRG
00000000B
R/W
R(RM1),W
R/W
R0,W
Software trigger bit
Read
Always reads "0"
Write
No effect on operation
Starts counting after reloading
Count enable bit
Stops count
Enables count (waiting for start trigger)
Underflow interrupt request flag bit
Read
Write
No underflow
Clears this bit
Underflow
No effect on operation
INTE
0
1
Underflow interrupt request enable bit
Disables underflow interrupt
Enables underflow interrupt
RELD
0
1
Reload selection bit
One-shot mode
Reload mode
OUTL
0
1
OUTE
0
1
Pin output level selection bit
One-shot mode
Reload mode
Outputs "H" square waveform during counting
Outputs "L" toggle when counting starts
Outputs "L" square waveform during counting
Outputs "H" toggle when counting starts
Timer output enable bit
Disables timer output (general-purpose I/O port)
Enables timer output
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R0,W
R0/WX
-
:
:
:
:
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Write only (Writable. The read value is “0”.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
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19.5 Registers of 16-bit Reload Timer
MB95410H/470H Series
Table 19.5-2 Functions of Bits in 16-bit Reload Timer Control Status Register Lower
(TMCSRL0)
Bit name
Function
The read value is always "0". Writing a value to this bit has no effect on operation.
bit7
Undefined bit
bit6
This bit sets the TO0 pin function of the 16-bit reload timer.
OUTE:
Writing "0": Sets the pin as a general-purpose I/O port.
Timer output enable bit
Writing "1": Sets the pin as the TO0 pin of the 16-bit reload timer.
This bit sets the output level of the output pin of the 16-bit reload timer.
• When one-shot mode is selected (RELD = 0):
"0": Outputs "H" level square waveform while the 16-bit reload timer counts.
"1": Outputs "L" level square waveform while the 16-bit reload timer counts.
When reload mode is selected (RELD = 1):
OUTL:
Pin output level
selection bit
•
bit4
RELD:
Reload selection bit
This bit sets reload operation when an underflow occurs.
"0": When an underflow occurs, counting is suspended. (One-shot mode)
"1": When an underflow occurs, the value that has been set to the 16-bit reload timer
reload register is loaded to the 16-bit reload timer timer register, and counting
continues. (Reload mode)
bit3
INTE:
Underflow interrupt
request enable bit
This bit enables or disables underflow interrupts.
Writing "0": Disables interrupt requests.
Writing "1": Enables interrupt requests.
bit2
UF:
Underflow interrupt
request flag bit
This bit indicates that an underflow has occurred on the 16-bit reload timer.
Writing "0": Clears the UF bit.
Writing "1": Has no effect on operation.
• "1" is always read in read-modify-write instructions.
bit1
CNTE:
Count enable bit
This bit enables or disables the operation of the 16-bit reload timer.
Writing "0": Stops counting.
Writing "1": The unit goes to standby to wait for a start trigger. When a start trigger is
input, the 16-bit reload timer timer register starts counting.
TRG:
Software trigger bit
This bit allows the 16-bit reload timer to be started by software.
The TRG bit is valid only when timer operation is enabled (CNTE = 1).
Writing "0": Has no effect on operation.
Writing "1": The value set in the 16-bit reload timer reload register is reloaded to the 16bit reload timer timer register and then the 16-bit reload timer timer register
starts counting from the next count clock input.
Note:
This bit can be set to "1" at the same time as the CNTE bit without affecting the
operation.
• This bit always returns "0" when read. However, "1" is read during the time between
writing "1" to start the timer and the timer count actually starting.
bit5
bit0
432
"0": Outputs an "L" when the 16-bit reload timer is started and then toggles each time
an underflow occurs.
"1": Outputs an "H" when the 16-bit reload timer is started and then toggles each time
an underflow occurs.
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
MB95410H/470H Series
19.5.3
16-bit Reload Timer Timer Register Upper
(TMRH0)/Lower (TMRL0)
The 16-bit reload timer timer register upper (TMRH0)/lower (TMRL0) can be
used to read the value of the 16-bit down-counter.
■ 16-bit Reload Timer Timer Register Upper (TMRH0)/Lower (TMRL0)
Figure 19.5-4 16-bit Reload Timer Timer Register Upper (TMRH0)/Lower (TMRL0)
TMRH0
Address
0FA6H
bit7
D15
R/W
bit6
D14
R/W
bit5
D13
R/W
bit4
D12
R/W
bit3
D11
R/W
bit2
D10
R/W
bit1
D9
R/W
bit0
D8
R/W
Initial value
00000000B
TMRL0
Address
0FA7H
bit7
D7
R/W
bit6
D6
R/W
bit5
D5
R/W
bit4
D4
R/W
bit3
D3
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
R/W
: Readable/writable (The read value is the same as the write value.)
The 16-bit reload timer timer registers can read the count value of the 16-bit down-counter.
If counting is enabled (TMCSRL0:CNTE=1) at the beginning of a count, the value written in
the 16-bit reload timer reload registers will be reloaded to these registers and the timer will
start counting down.
Notes:
• The registers can read the count value even during counting. To make a read access
to these registers, use a word transfer instruction, or read the upper byte first and the
lower byte second. The circuit is configured so that the value in the lower byte is saved
when the upper byte is read.
• The registers are read-only and located at the same addresses as the 16-bit reload
timer reload registers. Accordingly, a write access to these registers is also a write
access to the 16-bit reload timer reload registers.
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CHAPTER 19 16-BIT RELOAD TIMER
19.5 Registers of 16-bit Reload Timer
19.5.4
MB95410H/470H Series
16-bit Reload Timer Reload Register Upper
(TMRLRH0)/Lower (TMRLRL0)
The 16-bit reload timer reload upper (TMRLRH0)/lower (TMRLRL0) register set
the reload value for the 16-bit down-counter. The value set in the 16-bit reload
timer reload registers is reloaded to the 16-bit down-counter to down count.
■ 16-bit Reload Timer Reload Register Upper (TMRLRH0)/Lower (TMRLRL0)
Figure 19.5-5 16-bit Reload Timer Reload Register Upper (TMRLRH0)/Lower (TMRLRL0)
TMRLRH0
Address
0FA6H
bit7
D15
R/W
bit6
D14
R/W
bit5
D13
R/W
bit4
D12
R/W
bit3
D11
R/W
bit2
D10
R/W
bit1
D9
R/W
bit0
D8
R/W
Initial value
00000000B
TMRLRL0
Address
0FA7H
bit7
D7
R/W
bit6
D6
R/W
bit5
D5
R/W
bit4
D4
R/W
bit3
D3
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
R/W
: Readable/writable (The read value is the same as the write value.)
These registers set the reload value to the 16-bit down-counter.
The value set in the 16-bit reload timer reload registers is reloaded to the 16-bit down-counter
to start down-counting at the timing of start or underflow. (The value can be modified during
counter operation)
Notes:
• The registers can be written to even while the counter is running. To make a write
access to these registers, use a word transfer instruction or write the upper byte first
and lower byte second. (The circuit is implemented so that the upper byte is not used
until the lower byte is written.)
• The registers are write-only and located at the same addresses as the 16-bit reload
timer timer registers. Therefore, a read access to these registers is also a read access
to the 16-bit reload timer timer registers.
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CHAPTER 19 16-BIT RELOAD TIMER
19.6 Interrupts of 16-bit Reload Timer
MB95410H/470H Series
19.6
Interrupts of 16-bit Reload Timer
The 16-bit reload timer outputs an interrupt request when an underflow occurs
on the 16-bit down-counter.
■ Interrupts of 16-bit Reload Timer
Table 19.6-1 shows the interrupt control bits and interrupt sources of the 16-bit reload timer.
Table 19.6-1 Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer
Item
Description
Interrupt request flag bit
UF bit in TMCSRL0 register
Interrupt request enable bit
INTE bit in TMCSRL0 register
Interrupt source
Underflow of down-counter (TMRH0/TMRL0)
The 16-bit reload timer sets the underflow interrupt request flag bit (UF) in the 16-bit reload
timer control status register lower (TMCSRL0) to "1" when an underflow occurs in the 16-bit
down-counter ("0000H" → "FFFFH"). If the underflow interrupt request enable bit is enabled
(INTE = 1), the interrupt request will be outputted to the interrupt controller.
■ Register and Vector Table Addresses Related to Interrupts of 16-bit Reload
Timer
Table 19.6-2 Register and Vector Table Addresses Related to Interrupts of 16-bit Reload Timer
Interrupt source
16-bit reload timer
ch. 0
Interrupt
request no.
IRQ11
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
ILR2
L11
FFE4H
FFE5H
ch.: Channel
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
19.7
MB95410H/470H Series
Operations of 16-bit Reload Timer and Setting
Procedure Example
This section describes the operating status of the 16-bit reload timer counter.
■ Operating Status of Counter
The counter status is determined by the value of the count enable bit (CNTE) in the 16-bit
reload timer control status register (TMCSRL0) and the internal signal start trigger wait signal
(WAIT). The STOP state (halted), WAIT state (waiting for a start trigger) and RUN state
(operating state) can be set.
Figure 19.7-1 shows the status transition of these counters.
Figure 19.7-1 Diagram of Counter State Transition
Reset
STOP state
CNTE = 0, WAIT = 1
TI0 pin: Input disabled
TO0 pin: General-purpose I/O port
16-bit reload timer timer register:
Holds the value at stop
Value immediately after reset = 0000H
CNTE = 0
CNTE = 0
CNTE = 0
CNTE = 1
TRG = 0
WAIT state
CNTE = 1
TRG = 1
CNTE = 1, WAIT = 1
RUN state
TI0 pin: Only trigger input is valid
TO0 pin: 16-bit reload timer reload register output
16-bit reload timer timer register:
Holds the value at stop
until loaded immediately after reset = 0000H
CNTE = 1, WAIT = 0
TI0 pin: 16-bit reload timer input
UF = 1 &
RELD = 0
(One-shot mode)
TO0 pin: 16-bit reload timer reload register output
16-bit reload timer timer register:
count operation
UF = 1 &
RELD = 1
(Reload mode)
TRG = 1
(Software trigger)
LOAD
External trigger from TI0 pin
WAIT
TRG
CNTE
UF
RELD
436
TRG = 1
(Software trigger)
CNTE = 1, WAIT = 0
16-bit reload timer reload register
value loaded to
16-bit reload timer timer register
External trigger from TI0 pin
Load completed
: State transition by hardware
: State transition by register access
: WAIT signal (internal signal)
: Software trigger bit (TMCSRL0)
: Timer operation enable bit (TMCSRL0)
: Underflow generation flag bit (TMCSRL0)
: Reload selection bit (TMCSRL0)
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■ Setting Procedure Example
CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
Below is an example of procedure for setting the 16-bit reload timer.
● Initial settings
1) Set the interrupt level. (ILR2)
2) Set the reload value. (TMR0)
3) Select the clock. (TMCSRH0:CSL2 to CSL0)
4) Select the operation mode. (TMCSRH0:MOD2 to MOD0)
5) Enable the output. (TMCSRL0:OUTE = 1)
6) Select the output level. (TMCSRL0:OUTL)
7) Select reload. (TMCSRL0:RELD)
8) Enable a count. (TMCSRL0:CNTE = 1)
9) Perform the software trigger. (TMCSRL0:TRG = 1)
10) Enable underflow interrupt. (TMCSRL0:INTE = 1)
● Interrupt processing
1) Clear the underflow interrupt request flag. (TMCSRL0:UF=0)
2) Disable underflow interrupt. (TMCSRL0:INTE = 0)
3) Process any interrupt.
4) Enable underflow interrupt. (TMCSRL0:INTE = 1)
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
19.7.1
MB95410H/470H Series
Internal Clock Mode
In this mode, the 16-bit down-counter counts down while being synchronized
with the internal count clock, and outputs an interrupt request to the interrupt
controller every time an underflow occurs ("0000H" → "FFFFH"). In addition, the
TO0 pin can output the toggle waveform.
■ Setting Internal Clock Mode
The timer requires the register settings shown in Figure 19.7-2 to operate as an interval timer.,
Figure 19.7-2 Internal Clock Mode Setup
bit7
-
bit6
-
bit7
0
bit6
OUTE
bit1
CNTE
1
bit0
TRG
TMRLRH0
bit7
D15
bit6
bit5
bit4
bit3
bit2
bit1
D14
D13
D12
D11
D10
D9
Set initial value of counter (reload value) (upper)
bit0
D8
TMRLRL0
bit7
D7
bit6
bit5
bit4
bit3
bit2
bit1
D6
D5
D4
D3
D2
D1
Set initial value of counter (reload value) (lower)
bit0
D0
TMCSRH0
TMCSRL0
bit5
bit4
bit3
CSL2 CSL1 CSL0
Other than "111"
bit5
OUTL
bit4
RELD
bit3
INTE
bit2
bit1
bit0
MOD2 MOD1 MOD0
0
bit2
UF
: Used bit
0 : Set "0"
1 : Set "1"
■ Operation of Internal Clock Mode (Reload Mode)
When "1" is set to the count enable bit (CNTE) to enable counting, and the timer is started by
setting "1" to the software trigger bit (TRG) or by an external trigger, the value set in the 16-bit
reload timer reload register lower (TMRLR0) is reloaded to the 16-bit down-counter and
down-counting starts. If counting is enabled when the count enable bit (CNTE) and software
trigger bit (TRG) are set to "1" at the same time, the count is started at the same time.
If the reload selection bit (RELD) is "1", the value of the 16-bit reload timer reload register
lower (TMRLR0) is reloaded to the 16-bit down-counter and the count continues when the 16bit counter underflows ("0000H" → "FFFFH"). If the underflow interrupt request flag bit (UF)
is "1" when the underflow interrupt request enable bit (INTE) is set to "1", an interrupt request
is outputted.
The TO0 pin can output a toggle waveform that is inverted every time an underflow occurs.
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
MB95410H/470H Series
● Software trigger operation
When the count enable bit (CNTE) is set to "1", setting "1" to the software trigger bit (TRG)
starts counting.
Figure 19.7-3 shows the software trigger operation in reload mode.
Figure 19.7-3 Count Operation in Reload Mode (Software Trigger Operation)
Count clock
-1
Counter
Data load signal
0000
Reload data
-1
0000
Reload data
-1
0000
Reload data
-1
Reload data
UF bit
CNTE bit
TRG bit
TO0 pin
● External trigger input operation
The count starts when the count enable bit (CNTE) is set to "1" and a valid edge of trigger
input (rising, falling, or both selectable) set by the operation mode selection bits (MOD2 to
MOD0) is input to the TI0 pin.
The timer which starts with the software trigger also becomes effective as well as the start with
an external trigger.
Figure 19.7-4 shows the external trigger input operation in reload mode.
Figure 19.7-4 Count Operation in Reload Mode (External Trigger Input Operation)
Count clock
-1
Counter
Data load signal
Reload data
0000
-1
Reload data
0000
-1
Reload data
0000
-1
Reload data
UF bit
CNTE bit
TI0 pin
TO0 pin
● Gate input operation
The count starts when the count enable bit (CNTE) is set to "1" and the software trigger bit
(TRG) is also set to "1".
The timer continues counting while the valid gate input level ("L" or "H" selectable) set by the
operation mode selection bits (MOD2 to MOD0) is being input to the TI0 pin.
The timer start with the software trigger becomes effective as well as the start with an external
trigger, too.
Figure 19.7-5 shows the gate input operation in reload mode.
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
Figure 19.7-5 Count Operation in Reload Mode (External Gate Input Operation)
MB95410H/470H Series
Count clock
Counter
Reload data
-1
-1
-1
0000
-1
-1
Reload data
Data load signal
UF bit
CNTE bit
TRG bit
TI0 pin
TO0 pin
■ Operation of Internal Clock Mode (One-shot Mode)
When the count enable bit (CNTE) is set to "1" and the software trigger bit (TRG) is set to "1"
or the valid edge (rising, falling or both edges selectable) specified by the operation mode
selection bits (MOD2 to MOD0) is input to the TI0 pin, the value set in the 16-bit reload timer
reload register is reloaded to the 16-bit down-counter and down-counting starts. When the
count enable bit (CNTE) and software trigger bit (TRG) are set to "1" at the same time and
then counting is enabled, the count is started simultaneously.
If the reload selection bit (RELD) is "0", the 16-bit counter halts at "FFFFH" when the 16-bit
counter underflows ("0000H" → "FFFFH"). In this case, the underflow interrupt request flag bit
(UF) is set to "1" and if the underflow interrupt request enable bit (INTE) is "1", an interrupt
request is outputted.
A square waveform can be outputted from the TO0 pin to indicate that the count is in progress.
● Software trigger operation
The count starts when the count enable bit (CNTE) is "1" and the software trigger bit (TRG) is
set to "1".
Figure 19.7-6 shows the software trigger operation in one-shot mode.
Figure 19.7-6 Count Operation in One-shot Mode (Software Trigger Operation)
Count clock
Counter
Data load signal
-1
0000 FFFF
Reload data
-1
0000 FFFF
Reload data
UF bit
CNTE bit
TRG bit
TO0 pin
Wait for start trigger input
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
MB95410H/470H Series
● External trigger input
The count starts when the count enable bit (CNTE) is "1" and the valid edge of trigger input
(rising, falling, or both edges) specified by the operation mode selection bits (MOD2 to
MOD0) is input to the TI0 pin.
Figure 19.7-7 shows the external trigger input operation in one-shot mode.
Figure 19.7-7 Count Operation in One-shot Mode (External Trigger Input Operation)
Count clock
-1
Counter
Data load signal
-1
0000 FFFF
Reload data
0000 FFFF
Reload data
UF bit
CNTE bit
TI0 pin
TO0 pin
Wait for start trigger input
● Gate input operation
The count starts when the count enable bit (CNTE) is "1" and the software trigger bit (TRG) is
also set to "1".
The timer continues counting as long as the trigger input enable level ("L" or "H" selectable)
specified by the operation mode selection bits (MOD2 to MOD0) is input to the TI0 pin.
Figure 19.7-8 shows the external gate input operation in one-shot mode.
Figure 19.7-8 Count Operation in One-shot Mode (External Gate Input Operation)
Count clock
Counter
Data load signal
Reload data
-1
-1
0000 FFFF
-1
Reload data
UF bit
CNTE bit
TRG bit
TI0 pin
TO0 pin
Wait for start trigger input
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
19.7.2
MB95410H/470H Series
Event Count Mode
In this mode, the 16-bit down-counter counts down each time the valid edge is
detected on the pulses input to the TI0 pin, and an interrupt request is
outputted to the interrupt controller when an underflow occurs ("0000H" →
"FFFFH"). In addition, a toggle waveform or square waveform can be outputted
from the TO0 pin.
■ Event Count Mode Setup
The timer requires the register settings shown in Figure 19.7-9 to operate as an event counter.
Figure 19.7-9 Event Count Mode Setup
TMCSRH0
bit7
-
bit6
-
bit5
CSL2
1
bit4
CSL1
1
bit3
CSL0
1
bit2
bit1
bit0
MOD2 MOD1 MOD0
TMCSRL0
bit7
-
bit6
OUTE
bit5
OUTL
bit4
RELD
bit3
INTE
bit1
CNTE
1
bit0
TRG
TMRLRH0
bit7
D15
bit6
bit5
bit4
bit3
bit2
bit1
D14
D13
D12
D11
D10
D9
Set initial value of counter (reload value) (upper)
bit0
D8
TMRLRL0
bit7
D7
bit6
bit5
bit4
bit3
bit2
bit1
D6
D5
D4
D3
D2
D1
Set initial value of counter (reload value) (lower)
bit0
D0
bit2
UF
: Used bit
1 : Set "1"
■ Event Count Mode
The value set in the 16-bit reload timer reload register (TMRLRH0/TMRLRL0) is reloaded to
the 16-bit counter when the count enable bit (CNTE) is set to "1" and the software trigger bit
(TRG) is set to "1". The counter counts each time the valid edge (rising, falling, or both edges
selectable) is detected on the pulses input to the TI0 pin (external count clock).
● Operation of reload mode
If the reload selection bit (RELD) is "1", the value set in the 16-bit reload timer reload register
(TMRLRH0/TMRLRL0) is reloaded to the 16-bit counter and the count continues when the
16-bit counter underflows ("0000H" → "FFFFH").
The underflow interrupt request flag bit (UF) in the 16-bit reload timer control status register
lower(TMCSRL0) is set to "1" when an underflow occurs ("0000H" → "FFFFH") in the 16-bit
counter, and an interrupt request is outputted if the underflow interrupt enable bit (INTE) is set
to "1".
The TO0 pin can output a toggle waveform that is inverted each time an underflow occurs.
Figure 19.7-10 shows the count operation in reload mode.
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CHAPTER 19 16-BIT RELOAD TIMER
19.7 Operations of 16-bit Reload Timer and Setting
Procedure Example
Figure 19.7-10 Count Operation in Reload Mode (Event Count Mode)
MB95410H/470H Series
TI0 pin
-1
Counter
Data load signal
Reload data
-1
0000
-1
0000
Reload data
Reload data
-1
0000
Reload data
UF bit
CNTE bit
TRG bit
TO0 pin
● Operation of one-shot mode
If the reload selection bit (RELD) is "0", the value of the 16-bit counter halts at "FFFFH" when
the 16-bit counter underflows ("0000H" → "FFFFH").
An interrupt request is outputted when the underflow request flag bit (UF) in the lower timer
control status register (TMCSRL0) is set to "1" with the underflow interrupt enable bit (INTE)
set to "1".
The TO0 pin outputs a square waveform indicating that counting is in progress. Figure 19.7-11
shows the count operation in one-shot mode.
Figure 19.7-11 Count Operation in One-shot Mode (Event Count Mode)
TI0 pin
Counter
Data load signal
-1
0000 FFFF
Reload data
-1
0000 FFFF
Reload data
UF bit
CNTE bit
TRG bit
TO0 pin
Wait for start trigger input
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CHAPTER 19 16-BIT RELOAD TIMER
19.8 Notes on Using 16-bit Reload Timer
19.8
MB95410H/470H Series
Notes on Using 16-bit Reload Timer
This section provides notes on using the 16-bit reload timer.
■ Notes on Using 16-bit Reload Timer
● Precautions when setting the program
• A value can be read from the 16-bit reload timer timer register even during counting. As for
read access, use a word transfer instruction or read the upper byte first and the lower byte
second.
• A value can be written to the 16-bit reload timer reload register even during counting. As
for write access, use a word transfer instruction or write the upper byte first and the lower
byte second.
● Precaution for interrupts
The unit cannot recover from interrupt processing when the underflow interrupt request enable
bit (INTE) is set to "1" and "1" is set to the underflow interrupt request flag bit (UF) in the 16bit reload timer control status register lower (TMCSRL0). Always set the underflow interrupt
request flag bit (UF) to "0".
● Note on the event counter operating in event counter operation mode
When the event counter operates in event counter operation mode, the 16-bit reload timer
cannot be used.
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CHAPTER 19 16-BIT RELOAD TIMER
19.9 Sample Settings for 16-bit Reload Timer
MB95410H/470H Series
19.9
Sample Settings for 16-bit Reload Timer
This section provides sample settings for the 16-bit reload timer.
■ Sample Settings
● How to select the count clock
The count clock selection bits (TMCSRH0:CSL[2:0]) are used.
Operation
Count clock selection bits (CSL[2:0])
To select the internal clock
Set the bits to any value other than "111B".
To select the external event clock
Set the bits to "111B".
● How to select the operating conditions of internal clock mode
The operation mode selection bits (TMCSRH0:MOD[2:0]) are used to set the conditions.
Operating condition
Operation mode selection bits (MOD[2:0])
Trigger input from TI0 pin
(rising edge)
Set the bits to "001B".
Trigger input from TI0 pin
(falling edge)
Set the bits to "010B".
Trigger input from TI0 pin
(both edges)
Set the bits to "011B".
Gate input from TI0 pin (L level)
Set the bits to "1x0B".
Gate input from TI0 pin (H level)
Set the bits to "1x1B".
● How to select the operating conditions of event count mode
The operation mode selection bits (TMCSRH0:MOD[1:0]) are used to set the conditions.
Operating condition
Operation mode selection bits (MOD[1:0])
Rising edge
Set the bits to "01B".
Falling edge
Set the bits to "10B".
Both edges
Set the bits to "11B".
The setting of MOD2 has no effect on operation, whether it is "0" or "1".
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CHAPTER 19 16-BIT RELOAD TIMER
19.9 Sample Settings for 16-bit Reload Timer
MB95410H/470H Series
● How to enable/stop the count operation of the reload timer
The count enable bit of the timer (TMCSRL0:CNTE) is used.
Operation
Operation enable bit (CNTE)
To stop the reload timer
Set the bit to "0".
To enable the count operation of
the reload timer
Set the bit to "1".
The count cannot be resumed from the stop state. Enable the operation before or at the same
time as the activation.
● How to set reload the timer mode (reload/one-shot)
The reload selection bit (TMCSRL0:RELD) is used.
Operation
Reload selection bit (RELD)
To select one-shot mode
Set the bit to "0".
To select reload mode
Set the bit to "1".
● How to invert the output level
The output level is specified as shown in the following table.
The pin output level selection bit (TMCSRL0:OUTL) is used to set the output level.
Pin output level selection bit
(OUTL)
Output level
"L" toggle output when count starts in reload mode
Set the bit to "0".
"H" toggle output when count starts in reload mode
Set the bit to "1".
Outputting "H" square waveform during counting in
one-shot mode
Set the bit to "0".
Outputting "L" square waveform during counting in
one-shot mode
Set the bit to "1".
● How to switch the TI0 pin to an external event input pin or to an external trigger input pin
"0" is set to the data direction specification bit (DDR5:bit2 in the MB95410H Series and
DDR1:bit4 in the MB95470H Series).
Pin
Control bit
Data direction register (DDR5)
(MB95410H Series)
Data direction specification bit (P52)
(MB95410H Series)
Data direction register (DDR1)
(MB95470H Series)
Data direction specification bit (P14)
(MB95470H Series)
TI0 pin
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CHAPTER 19 16-BIT RELOAD TIMER
19.9 Sample Settings for 16-bit Reload Timer
MB95410H/470H Series
● How to enable/disable the TO0 pin
The timer output enable bit (TMCSRL0:OUTE) is used.
Operation
Timer output enable bit (OUTE)
To enable the TO0 pin
Set the bit to "1".
To disable the TO0 pin
Set the bit to "0".
● How to generate a start trigger
• How to generate the software trigger
The software trigger bit (TMCSRL0:TRG) is used.
Writing "1" to the software trigger bit (TRG) generates a trigger.
When enabling and starting operation at the same time, set the count enable bit
(TMCSLR0:CNTE) and the software trigger bit (TMCSRL0:TRG) at the same time.
• How to generate an external trigger
An external trigger is outputted when the edge specified by the operation mode selection
bits is input to the trigger pin corresponding to each reload timer.
Timer
Trigger pin
Reload timer
TI0
● Interrupt-related registers
The interrupt level is set by the interrupt level setting register shown in the following table.
Reload timer ch. 0
Interrupt level setting register
Interrupt vector
Interrupt level setting register (ILR2)
Address: 0007BH
#11
Address: 0FFE4H
● How to enable interrupts
Interrupt request enable bit, Interrupt request flag
The interrupt request enable bit (TMCSRL0:INTE) is used to enable interrupts.
Interrupt request enable bit (INTE)
When disabling interrupt requests
Set the bit to "0".
When enabling interrupt requests
Set the bit to "1".
The interrupt request bit (TMCSRL0:UF) is used to clear interrupt requests.
Interrupt request bit (UF)
When disabling interrupt requests
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Set the bit to "0".
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19.9 Sample Settings for 16-bit Reload Timer
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CHAPTER 20
EVENT COUNTER
This chapter describes the functions and
operations of the event counter.
20.1 Overview of Event Counter
20.2 Configuration of Event Counter
20.3 Register of Event Counter
20.4 Operation of Event Counter Operation Mode
20.5 Setting Procedure Example
20.6 Frequency Measurement Range and Precision
20.7 Notes on Using Event Counter
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CHAPTER 20 EVENT COUNTER
20.1 Overview of Event Counter
20.1
MB95410H/470H Series
Overview of Event Counter
The event counter is mainly used to measure the frequency of external clock
with configurable measure period. 16-bit reload timer and 8/16-bit composite
timer ch. 1 are configured to provide an event counter operation mode in the
event counter.
■ Overview of Event Counter
The function of the event counter is summarized below.
● Event counter operation mode
In this mode, 8/16-bit composite timer ch. 1 is used to generate a PWM signal. Then external
clock will be gated by this PWM signal, and then input to the 16-bit reload timer as count
clock. 16-bit reload timer operates in external clock mode (reload mode). The frequency of
external clock could be calculated with configured measure period in the interrupt service
subroutine of 8/16-bit composite timer ch. 1.
Note:
In the following sections of this chapter, the term "composite timer" represents "8/16-bit
composite timer ch. 1" and the term "reload timer" "16-bit reload timer".
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20.2 Configuration of Event Counter
MB95410H/470H Series
20.2
Configuration of Event Counter
The event counter consists of the following blocks:
• Reload timer count clock generation circuit
• Composite timer count clock (CK06/CK16) selection circuit
• Event counter control register (EVCR)
■ Block Diagram of Event Counter
Figure 20.2-1 Block Diagram of Event Counter
EVCR
SEL1 SEL0 MD
External clock
From
time-base
timer
FCH/27 *
FCRH/26
9
FCH/2 * or
FCRH/2
11
FCH/2 *
8
10
FCRH/2
Reload timer
count clock (TI)
Reload timer
count clock
generation
circuit
PWM signal
from composite timer
Composite
timer count
clock selector
Composite timer
count clock
(CK06/CK16)
*: In main clock mode, if PLLC:PCS[1:0] are set to “00”, the main clock divided by 2 (FCH/2) is used as the count clock;
if PLLC:PCS[1:0] are set to “01” or “10” or “11”, the main PLL clock is used as the count clock.
● Reload timer count clock generation circuit
When the MD bit in the EVCR register is set to "1", external clock input is gated by PWM
output from composite timer, then output to reload timer as count clock. When the MD bit is
set to "0", external clock is output to reload timer directly as external clock.
● Composite timer count clock (CK06/CK16) selection circuit
The event counter uses one of the following time-base timer output signals (divided machine
clock signal) as the CK06/CK16 count clock according to the settings of the SEL[1:0] bits in
the EVCR register:
1. FCH/27 or FCH/29 or FCH/211 (Main clock mode, PCS[1:0] = 00)
2. Main PLL clock divided by 26 or 28 or 210 (Main clock mode, PCS[1:0] = 01, 10 or 11)
3. FCRH/26, FCRH/28 or FCRH/210 (Main CR clock mode)
● Event counter control register (EVCR)
The event counter control register enables or disables the event counter operation mode and
selects composite timer count clock source (CK06/CK16).
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CHAPTER 20 EVENT COUNTER
20.3 Register of Event Counter
20.3
MB95410H/470H Series
Register of Event Counter
This section describes the register of the event counter.
■ Event Counter Register
Figure 20.3-1 shows the register of the event counter.
Figure 20.3-1 Register of Event Counter
Event counter control register (EVCR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
0FE2H
SEL1
R0/WX R0/WX R0/WX R0/WX R0/WX R/W
R/W
R0/WX
-
452
bit0
SEL0
R/W
bit0
MD
R/W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 20 EVENT COUNTER
20.3 Register of Event Counter
MB95410H/470H Series
20.3.1
Event Counter Control Register (EVCR)
The event counter control register (EVCR) enables or disables the event
counter operation mode, and selects a count clock from the CK06/CK16 clock
sources of the composite timer.
■ Event Counter Control Register (EVCR)
Figure 20.3-2 Event Counter Control Register (EVCR)
Address
0FE2H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
-
-
-
-
-
SEL1
SEL0
MD
R/W
R/W
R/W
R0/WX R0/WX R0/WX R0/WX R0/WX
:
:
:
:
Initial value
00000000B
MD
Event counter operation mode enable bit
0
The event counter operation mode is disabled.
1
The event counter operation mode is enabled.
SEL1
R/W
R0/WX
-
bit0
SEL0
Composite timer count clock
(CK06/CK16) select bits
0
0
FCH/27 or FCRH/26 *
0
1
FCH/29 or FCRH/28 *
1
0
FCH/211 or FCRH/210 *
1
1
FCH/27 or FCRH/26 *
Readable/writable (The read value is the same as the write value.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
* : The clock to be used as the composite timer count clock is decided according to the settings of the SYCC2 register.
In the case of using the main clock or the main PLL clock as the composite timer count clock, the settings of PLLC:PCS[1:0]
decide whether the main clock divided by 2 (FCH/2) or the main PLL clock will be used.
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CHAPTER 20 EVENT COUNTER
20.3 Register of Event Counter
MB95410H/470H Series
Table 20.3-1 Functions of Bits in Event Counter Control Register (EVCR)
Bit name
bit7
to
bit3
bit2,
bit1
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
Undefined bits
SEL1, SEL0:
Composite timer count
clock (CK06/CK16)
select bits
These bits select the composite timer count clock (CK06/CK16).
• The count clock is generated by the prescaler. See "6.13 Operation of Prescaler".
• Write access to these bits is prohibited when composite timer and reload timer are in
timer operation (T00CR1/T01CR1:STA = 1 or TMCSRL0:CNTE=1).
• These bits are in effect even if MD bit in the EVCR register is set to "0".
• The count clock from the time-base timer will be used as the count clock. Depending on
the settings of the SYCC2 register, the count clock from the time-base timer can be
generated from either main clock or main CR clock. When the count clock from the timebase timer is used as the count clock, resetting the time-base timer by writing "1" to the
time-base timer initialization bit in the time-base timer control register (TBTC:TCLR)
will affect the count time.
SEL1
SEL0
Composite timer count clock (CK06/CK16)
0
0
FCH/27or FCRH/26 *
0
1
FCH/29 or FCH/28 *
1
0
FCH/211 or FCH/210 *
1
1
FCH/27or FCRH/26 *
*: The clock to be used as the composite timer count clock is decided according to the
settings of the SYCC2 register. In the case of using the main clock or the main PLL
clock as the composite timer count clock, the settings of PLLC:PCS[1:0] decide
whether the main clock divided by 2 (FCH/2) or the main PLL clock will be used.
bit0
454
MD:
Event counter
operation mode select
bit
This bit selects the event counter operation mode.
Writing "0": The event counter operation mode is disabled, and the composite timer and
reload timer will work independently.
Writing "1": The event counter operation mode is enabled, and the composite timer and
reload timer work together to implement the event counter function.
• Write access to this bit is prohibited when composite timer and reload timer are in timer
operation (T00CR1/T01CR1:STA = 1 or TMCSRL0:CNTE=1).
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CHAPTER 20 EVENT COUNTER
20.4 Operation of Event Counter Operation Mode
MB95410H/470H Series
20.4
Operation of Event Counter Operation Mode
This section describes the operation of the event counter operation mode.
■ Operation of Event Counter Operation Mode
The event counter, reload timer and composite timer require the register setting shown in
Figure 20.4-1 to serve as an event counter (for frequency measurement).
Figure 20.4-1 Settings of Event Counter Operation Mode
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
SEL1
SEL0
MD
❍
❍
1
Event Counter Register
EVCR
-
Reload Timer Registers
TMCSRH0
TMCSRL0
-
-
-
CSL2
CSL1
CSL0
MOD2
MOD1
MOD0
1
1
1
❍*
❍*
❍*
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
×
×
1
❍*
❍
1
❍
TMRLRH0
Sets the reload value (upper)
TMRLRL0
Sets the reload value (lower)
Composite Timer Registers
T10CR0/T11CR0
IFE
C2
C1
C0
F3
F2
F1
F0
❍
1
1
0
0
1
0
0
T10CR1/T11CR1
STA
HO
IE
IR
BF
IF
SO
OE
1
❍
❍
×
×
❍
×
×
TMCR1
TO1
TO0
TIS
MOD
FE11
FE10
FE01
FE00
❍
❍
×
×
×
×
×
×
T10DR
Sets "L" pulse width (compare value)
T11DR
Sets the cycle of PWM waveform (compare value)
❍: Used bit
×: Unused bit
1: Set to "1"
0: Set to "0"
In event counter operation mode, the reload timer and the composite timer are used, therefore,
they cannot be used for other function any more.
The reload timer should operate in event count mode (reload mode). In other words,
TMCSRL0:MOD2 to MOD0 should be set one of the following values: "001B", "010B",
"011B", and TMCSRL0:RELD should be set "1". The reload timer interrupt should be enabled
in order to record the reload timer underflow times.
The composite timer should operate in PWM operation mode (variable-cycle mode), count
clock select source must be selected from CK06/CK16. It means T10CR0/11CR0:C2 to C0
must be set to "110B", and T10CR0/11CR0:F3 to F0 must be set to "0100B". In the composite
timer, timer 11 interrupt should be enabled in order to calculate the frequency of external
clock.
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CHAPTER 20 EVENT COUNTER
20.4 Operation of Event Counter Operation Mode
MB95410H/470H Series
When the reload timer underflows, record the underflow times and clear underflow flag (UF)
in reload timer interrupt service subroutine. When timer 11 interrupt occurs in the composite
timer, clear IF flag in T11CR1, read the reload timer count value, and calculate the frequency
of external clock in the interrupt service subroutine.
Figure 20.4-2 shows the operation of event counter operation mode.
Figure 20.4-2 Operation of Event Counter Operation Mode
External clock
PWM signal
Reload timer
count clock
Reload timer
counter
reload value
count down
0000
reload value count down
Reload timer
underflow interrupt
Timer 11 compare
match interrupt
Notes:
• In reload timer underflow interrupt service subroutine, clear the UF flag, count the times of underflow
and write the reload register with reload value.
• In the timer 11 (composite timer ch. 1) compare match interrupt service subroutine, clear IF flag, read
reload timer value and calculate the frequency.
Figure 20.4-3 shows the calculation of external clock frequency.
Figure 20.4-3 Calculation of external clock frequency
Count value of reload timer
Frequency of external clock =
“H” pulse width of PWM signal
In the above expression:
(count value of reload timer) = (TMRLRH0/TMRLRL0 set value) × (underflow times)
+ (TMRLRH0/TMRLRL0 set value) - (read value of TMRH0/TMRL0)
(“H” pulse width of PWM signal) =
(T11DR set value - T10DR set value)
(frequency of composite timer count clock source)
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20.5
Setting Procedure Example
CHAPTER 20 EVENT COUNTER
20.5 Setting Procedure Example
This section describes the setting procedure example of the event counter
function.
■ Setting Procedure Example
Below is an example of procedure for setting the event counter.
● Initial settings
1) Select the event counter operation mode. (EVCR:MD)
2) Select the composite timer CK06/CK16 source. (EVCR:SEL1, SEL0)
3) Set the interrupt level of reload timer and composite timer. (ILRx)
4) Set the reload value of reload timer. (TMRLRH0 and TMRLRL0)
5) Select the reload timer count clock. (TMCSRH0:CSL2 to CSL0)
6) Select the reload timer operation mode. (TMCSRH0:MOD2 to MOD0)
7) Select reload mode. (TMCSRL0:RELD)
8) Enable underflow interrupt. (TMCSRL0:INTE)
9) Enable reload timer count. (TMCSRL0:CNTE)
10) Perform the software trigger. (TMCSRL0:TRG=1)
11) Select composite timer operation mode. (T10CR0/T11CR0:F3 to F0)
12) Select composite timer count clock. (T10CR0/T11CR0:C2 to C0)
13) Enable the interrupt of timer 11. (T11CR1:IE)
14) Start the composite timer operation. (either T10CR1:STA or T11CR1:STA)
● Interrupt process of reload timer
1) Clear the underflow interrupt request flag. (TMCSRL0:UF)
2) Disable underflow interrupt. (TMCSRL0:INTE)
3) Record the underflow times.
4) Enable underflow interrupt. (TMCSRL0:INTE)
● Interrupt process of composite timer (timer 11)
1) Clear the interrupt request flag. (T11CR1:IF)
2) Disable the interrupt. (T11CR1:IE)
3) Read counter value of reload timer. (TMRH0, TMRL0)
4) Calculate the frequency of external clock.
5) Enable the interrupt. (T11CR1:IE)
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CHAPTER 20 EVENT COUNTER
20.6 Frequency Measurement Range and Precision
20.6
MB95410H/470H Series
Frequency Measurement Range and Precision
This section describes the frequency measurement range and precision of the
event counter.
■ Frequency measurement range
The maximum measurable frequency is limited by peripheral resource clock. When peripheral
resource clock frequency is FPCLK, the maximum measurable frequency is FPCLK/4.
The minimum measurable frequency is limited by the measure period, in order to ensure the
frequency measurement precision.
■ Frequency measurement precision
The frequency measurement precision is determined by the main clock frequency and the
precision of the reload timer counter. The more the reload timer counter counts, the more
precise the calculated frequency becomes.
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20.7
Notes on Using Event Counter
CHAPTER 20 EVENT COUNTER
20.7 Notes on Using Event Counter
This section provides notes on using the event counter.
■ Notes on Using Event Counter
To switch the event counter operation mode with MD bit in the EVCR register, stop the
composite timer and the reload timer first (T10CR1/T11CR1:STA=0, TMCSRL0:CNTE=0),
then clear the interrupt flags (T10CR1/T11CR1:IF, IR, TMCSRL0:UF), and interrupt enable
bits (T10CR1/T11CR1:IE, T10CR0/T11CR0:IFE, TMCSRL0:INTE) in the composite timer
and the reload timer.
Set the L pulse width of PWM long enough so that the external clock frequency can be
calculated within the interrupt service subroutine.
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20.7 Notes on Using Event Counter
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CHAPTER 21
8/16-BIT PPG
This chapter describes the functions and
operations of the 8/16-bit PPG.
21.1 Overview of 8/16-bit PPG
21.2 Configuration of 8/16-bit PPG
21.3 Channels of 8/16-bit PPG
21.4 Pins of 8/16-bit PPG
21.5 Registers of 8/16-bit PPG
21.6 Interrupts of 8/16-bit PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
21.8 Notes on Using 8/16-bit PPG
21.9 Sample Settings for 8/16-bit PPG Timer
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CHAPTER 21 8/16-BIT PPG
21.1 Overview of 8/16-bit PPG
21.1
MB95410H/470H Series
Overview of 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that uses pulse output control
based on timer operation to perform PPG output. The 8/16-bit PPG also
operates in cascade (8 bits + 8 bits) as a 16-bit PPG.
■ Overview of 8/16-bit PPG
The functions of the 8/16-bit PPG are summarized below.
● 8-bit PPG output independent operation mode
In this mode, the unit can operate as 2 8-bit PPG (PPG timer 00 and PPG timer 01).
● 8-bit prescaler + 8-bit PPG output operation mode
The rising and falling edge detection pulses from the PPG timer 01 output can be input to the
downcounter of the PPG timer 00 to enable variable-cycle 8-bit PPG output.
● 16-bit PPG output operation mode
The unit can also operate in cascade (PPG timer 01 (upper 8 bits) + PPG timer 00 (lower 8
bits)) as 16-bit PPG output.
● PPG output operation
In this operation, a variable-cycle pulse waveform is output in any duty ratio.
The unit can also be used as a D/A converter in conjunction with an external circuit.
● Output inversion mode
This mode can invert the PPG output value.
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CHAPTER 21 8/16-BIT PPG
21.2 Configuration of 8/16-bit PPG
MB95410H/470H Series
21.2
Configuration of 8/16-bit PPG
This section shows the block diagram of 8/16-bit PPG.
■ Block Diagram of 8/16-bit PPG
Figure 21.2-1 shows the block diagram of the 8/16-bit PPG.
Figure 21.2-1 Block Diagram of 8/16-bit PPG
CKS02
CKS01
Duty setup register
CKS00
Cycle setup register
Prescaler
MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
FCH*/27
FCH*/28
Duty setup buffer register
PPG timer 00
Comparator
circuit
01
CLK
LOAD
00
10
11
REV00
8-bit down-counter
(PPG timer 00)
0
STOP
PEN00
S Q
R
1
Pin
PPG00
Edge
detection
BORROW
START
0
1
0
1
PIE0
MD1
PUF0
POEN0
POEN0
MD0
IRQ13
Used as the select signal of each selector
Duty setup register
Cycle setup register
CKS12
CKS11
CKS10
Cycle setup
buffer register
Prescaler
MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
FCH*/27 or FCRH/26
FCH*/28 or FCRH/27
1
1
0
Edge
detection
CLK
1
STOP
PPG timer 01
0
LOAD
1
0
PEN01
Duty register buffer
cycle setup
Comparator
circuit
Edge
detection
8-bit down-counter
(PPG timer 01)
START
1
S Q
R
REV01
0
Pin
PPG01
BORROW
0
PIE1
PUF1
POEN1
POEN1
IRQ12
* : When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
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CHAPTER 21 8/16-BIT PPG
21.2 Configuration of 8/16-bit PPG
MB95410H/470H Series
● Counter clock selector
The clock for the countdown of 8-bit down counter is selected from eight types of internal
count clocks.
● 8-bit downcounter
It counts down with the count clock selected with the count clock selector.
● Comparator circuit
The output is kept "H" level until the value of 8-bit down counter is corresponding to the value
of 8/16-bit PPG duty setup buffer register from the value of 8/16-bit set buffer register of PPG
cycle.
Afterwards, after keep "L" level the output until the counter value is corresponding to "1", it
keeps counting 8-bit down counter from the value of 8/16-bit PPG cycle setup buffer register.
● 8/16-bit PPG timer 01 control register (PC01)
The operation condition on the PPG timer 01 side of 8/16-bit PPG timer is set.
● 8/16-bit PPG timer 00 control register (PC00)
The operation mode of 8/16-bit PPG timer and the operation condition on the PPG timer 00
side are set.
● 8/16-bit PPG timer 01/00 cycle setup buffer register ch. 0 (PPS01, PPS00)
The compare value for the cycle of 8/16-bit PPG timer is set.
● 8/16-bit PPG timer 01/00 duty setup buffer register ch. 0 (PDS01, PDS00)
The compare value for "H" width of 8/16-bit PPG timer is set.
● 8/16-bit PPG start register
The start or the stop of 8/16-bit PPG timer is set.
● 8/16-bit PPG output inversion register
An initial level also includes the output of 8/16-bit PPG timer and it is reversed.
■ Input Clock
The 8/16-bit PPG uses the output clock from the prescaler as its input clock (count clock).
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CHAPTER 21 8/16-BIT PPG
21.3 Channels of 8/16-bit PPG
MB95410H/470H Series
21.3
Channels of 8/16-bit PPG
This section describes the channels of the 8/16-bit PPG.
■ Channels of 8/16-bit PPG
The MB95410H/470H Series has two channels of 8/16-bit PPG. There are 8-bit PPG timer 00
and 8-bit PPG timer 01 in each channel. They can be used respectively as two 8-bit PPGs.
Also, they can be used as a 16-bit PPG.
Table 21.3-1 and Table 21.3-2 show the channels and their corresponding pins and registers.
Table 21.3-1 Pins of 8/16-bit PPG
Channel
0
1
Pin name
Pin function
PPG00
PPG timer 00 output (8-bit PPG (00), 16-bit PPG)
PPG01
PPG timer 01 output (8-bit PPG (01), 8-bit prescaler)
PPG10
PPG timer 10 output (8-bit PPG (10), 16-bit PPG)
PPG11
PPG timer 11 output (8-bit PPG (11), 8-bit prescaler)
Table 21.3-2 Registers of 8/16-bit PPG
Channel
0
1
Both channels
Register
abbreviation
Corresponding register (Name in this manual)
PC01
8/16-bit PPG timer 01 control register
PC00
8/16-bit PPG timer 00 control register
PPS01
8/16-bit PPG timer 01 cycle setup buffer register
PPS00
8/16-bit PPG timer 00 cycle setup buffer register
PDS01
8/16-bit PPG timer 01 duty setup buffer register
PDS00
8/16-bit PPG timer 00 duty setup buffer register
PC11
8/16-bit PPG timer 11 control register
PC10
8/16-bit PPG timer 10 control register
PPS11
8/16-bit PPG timer 11 cycle setup buffer register
PPS10
8/16-bit PPG timer 10 cycle setup buffer register
PDS11
8/16-bit PPG timer 11 duty setup buffer register
PDS10
8/16-bit PPG timer 10 duty setup buffer register
PPGS
8/16-bit PPG start register
REVC
8/16-bit PPG output inversion register
The following sections describe only the 8/16-bit PPG on ch. 0.
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CHAPTER 21 8/16-BIT PPG
21.4 Pins of 8/16-bit PPG
21.4
MB95410H/470H Series
Pins of 8/16-bit PPG
This section describes the pins of the 8/16-bit PPG.
■ Pins of 8/16-bit PPG
● PPG00 pin and PPG01 pin
These pins function both as general-purpose I/O ports and 8/16-bit PPG outputs.
PPG00, PPG01: A PPG waveform is output to these pins. The PPG waveform can be output
by enabling the output by the 8/16-bit PPG timer 01/00 control registers
(PC00: POEN0 = 1, PC01: POEN1 = 1).
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CHAPTER 21 8/16-BIT PPG
21.4 Pins of 8/16-bit PPG
MB95410H/470H Series
■ Block Diagrams of Pins of 8/16-bit PPG
Figure 21.4-1 Block Diagram of PPG00 and PPG01 of 8/16-bit PPG
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Analog input enable
Analog input
Figure 21.4-2 Block Diagram of PPG10 and PPG11 of 8/16-bit PPG
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
PDR
0
Internal bus
PDR write
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
LCD output enable
LCD output
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
21.5
MB95410H/470H Series
Registers of 8/16-bit PPG
This section describes the registers of the 8/16-bit PPG.
■ Registers of 8/16-bit PPG
Figure 21.5-1 shows the registers of the 8/16-bit PPG.
Figure 21.5-1 Registers of 8/16-bit PPG
8/16-bit PPG timer 01 control register (PC01)
Address
bit7
bit6
bit5
bit4
bit3
003AH
PIE1
PUF1 POEN1
R(RM1),W
R0/WX R0/WX
R/W
R/W
bit2
CKS12
R/W
bit1
CKS11
R/W
bit0
CKS10
R/W
Initial value
00000000B
8/16-bit PPG timer 00 control register (PC00)
Address
bit7
bit6
bit5
bit4
bit3
003BH
MD1
MD0
PIE0
PUF0 POEN0
R(RM1),W
R/W
R/W
R/W
R/W
bit2
CKS02
R/W
bit1
CKS01
R/W
bit0
CKS00
R/W
Initial value
00000000B
8/16-bit PPG timer 01 cycle setup buffer register (PPS01)
Address
bit7
bit6
bit5
bit4
bit3
0F9CH
PH7
PH6
PH5
PH4
PH3
R/W
R/W
R/W
R/W
R/W
bit2
PH2
R/W
bit1
PH1
R/W
bit0
PH0
R/W
Initial value
11111111B
8/16-bit PPG timer 00 cycle setup buffer register (PPS00)
Address
bit7
bit6
bit5
bit4
bit3
0F9DH
PL7
PL6
PL5
PL4
PL3
R/W
R/W
R/W
R/W
R/W
bit2
PL2
R/W
bit1
PL1
R/W
bit0
PL0
R/W
Initial value
11111111B
8/16-bit PPG timer 01 duty setup buffer register (PDS01)
Address
bit7
bit6
bit5
bit4
bit3
0F9EH
DH7
DH6
DH5
DH4
DH3
R/W
R/W
R/W
R/W
R/W
bit2
DH2
R/W
bit1
DH1
R/W
bit0
DH0
R/W
Initial value
11111111B
8/16-bit PPG timer 00 duty setup buffer register (PDS00)
Address
bit7
bit6
bit5
bit4
bit3
0F9FH
DL7
DL6
DL5
DL4
DL3
R/W
R/W
R/W
R/W
R/W
bit2
DL2
R/W
bit1
DL1
R/W
bit0
DL0
R/W
Initial value
11111111B
8/16-bit PPG start register (PPGS)
Address
bit7
bit6
bit5
0FA4H
R/W
R/W
R/W
bit4
R/W
bit3
PEN11
R/W
bit2
PEN10
R/W
bit1
PEN01
R/W
bit0
PEN00
R/W
Initial value
00000000B
8/16-bit PPG output inversion register (REVC)
Address
bit7
bit6
bit5
bit4
0FA5H
R/W
R/W
R/W
R/W
bit3
REV11
R/W
bit2
REV10
R/W
bit1
REV01
R/W
bit0
REV00
R/W
Initial value
00000000B
R/W
R(RM1), W
R0/WX
-
468
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the
read-modify-write (RMW) type of instruction.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
21.5.1
8/16-bit PPG Timer 01 Control Register (PC01)
The 8/16-bit PPG timer 01 control register (PC01) sets the operating conditions
for PPG timer 01.
■ 8/16-bit PPG Timer 01 Control Register (PC01)
Figure 21.5-2 8/16-bit PPG Timer 01 Control Register (PC01)
Address
PC01 003AH
PC11 003CH
bit7
bit6
bit5
-
-
PIE1
R0/WX
R0/WX
bit4
bit3
bit2
bit1
bit0
Initial value
PUF1 POEN1 CKS12 CKS11 CKS10
R/W R(RM1),W R/W
R/W
CKS12 CKS11 CKS10
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
POEN1
0
1
PUF1
0
1
PIE1
0
1
R/W
00000000B
R/W
Operating clock select bits
MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
FCH*1/27 or FCRH/26 *2
FCH*1/28 or FCRH/27 *2
Output enable bit
Output disabled (general-purpose port)
Output enabled
Counter borrow detection flag bit for PPG cycle downcounter
Read
Counter borrow undetected
Counter borrow detected
Write
Flag cleared
No effect on operation
Interrupt request enable bit
Interrupt disabled
Interrupt enabled
MCLK
FCH
FCRH
R/W
R(RM1),W
:
:
:
:
:
Machine clock
Main clock
Main CR clock
Readable/writable (The read value is the same as the write value.)
Readable/writable (The read value is different from the write value. "1" is read by
the read-modify-write (RMW) type of instruction.)
R0/WX
-
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
: Initial value
*1 : When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
*2 : The value to be used as the operating clock is decided according to the settings of the SYCC2 register.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
Table 21.5-1 Functions of Bits in 8/16-bit PPG Timer 01 Control Register (PC01)
Bit name
Function
bit7,
bit6
Undefined bits
bit5
PIE1:
Interrupt request
enable bit
This bit controls interrupts of PPG timer 01.
Writing "0": Disables interrupts of PPG timer 01.
Writing "1": Enables interrupts of PPG timer 01.
The bit outputs an interrupt request (IRQ12) when the counter borrow detection bit (PUF1)
and the PIE1 bit are both set to "1".
PUF1:
Counter borrow
detection flag bit for
PPG cycle
downcounter
This bit serves as the counter borrow detection flag for the PPG cycle downcounter of PPG
timer 01.
• This bit is set to "1" when a counter borrow occurs during 8-bit prescaler + 8-bit PPG
mode.
• In 16-bit PPG mode, this bit is not set to "1" even when a counter borrow occurs.
• Writing "1" to the bit is meaningless.
• Writing "0" clears the bit.
• "1" is read in read-modify-write (RMW) instruction.
Reading "0": No counter borrow of PPG timer 01 is detected.
Reading "1": A counter borrow of PPG timer 01 is detected.
POEN1:
Output enable bit
This bit enables or disables the output of PPG timer 01 pin.
Writing "0": The PPG timer 01 pin is used as a general-purpose port.
Writing "1": The PPG timer 01 pin is used as the PPG output pin.
Setting this bit to "1" during 16-bit PPG operation mode sets the PPG timer 01 pin as an
output pin. (The setting value of REV01 is output. "L" output is supplied when REV01 is
"0".)
bit4
bit3
Their read values are always "0". Writing values to these bits has no effect on operation.
These bits select the operating clock for 8-bit downcounter of PPG timer 01.
• The operating clock is generated from the prescaler. See "CHAPTER 6 CLOCK
CONTROLLER".
• In 16-bit PPG operation mode, the settings of these bits have no effect on the operation.
"000B": MCLK
"001B": MCLK/2
"010B": MCLK/4
"011B": MCLK/8
"100B": MCLK/16
"101B": MCLK/32
bit2
to
bit0
470
CKS12, CKS11,
CKS10:
Operating clock select
bits
"110B": FCH*/27 or FCRH/26
"111B": FCH*/28 or FCRH/27
Note:
• The use of the subclock will stop the time-base timer operation. Therefore,
selecting "110B" or "111B" is prohibited.
• When these bits are set to "110B" or "111B", the count clock from the time-base
timer will be used as the operating clock. Depending on the settings of the
SYCC2 register, the count clock from the time-base timer can be generated
from the main clock, the main PLL clock or the main CR clock. In the case of
using the count clock from the time-base timer as the operating clock, resetting
the time-base timer by writing "1" to the time-base timer initialization bit in the
time-base timer control register (TBTC:TCLR) will affect the count time.
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by
two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
21.5.2
8/16-bit PPG Timer 00 Control Register (PC00)
The 8/16-bit PPG timer 00 control register (PC00) sets the operating conditions
and the operation mode for PPG timer 00.
■ 8/16-bit PPG Timer 00 Control Register (PC00)
Figure 21.5-3 8/16-bit PPG Timer 00 Control Register (PC00)
Address
PC00 003BH
PC10 003DH
bit7
bit6
bit5
bit4
bit3
MD1
MD0
PIE0
R/W
R/W
R/W R(RM1),W R/W
bit2
bit1
PUF0 POEN0 CKS02 CKS01 CKS00
R/W
CKS02 CKS01 CKS00
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PUF0
0
1
:
:
:
:
:
00000000B
R/W
Operating clock select bits
MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
FCH*1/27 or FCRH/26 *2
FCH*1/28 or FCRH/27 *2
Counter borrow detection flag bit for PPG cycle downcounter
Read
Counter borrow undetected
Counter borrow detected
PIE0
0
1
MD1
0
0
1
1
R/W
Initial value
Output enable bit
Output disabled (general-purpose port)
Output enabled
POEN0
0
1
MCLK
FCH
FCRH
R/W
R(RM1),W
bit0
Write
Flag cleared
No effect on operation
Interrupt request enable bit
Interrupt disabled
Interrupt enabled
MD0
0
1
0
1
Operation mode select bits
8-bit PPG independent mode
8-bit prescaler + 8-bit PPG mode
16-bit PPG mode
Machine clock
Main clock
Main CR clock
Readable/writable (The read value is the same as the write value.)
Readable/writable (The read value is different the write value. "1" is read by
the read-modify-write (RMW) type of instruction.)
: Initial value
*1 : When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
*2 : The value to be used as the operating clock is decided according to the settings of the SYCC2 register.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
Table 21.5-2 Functions of Bits in 8/16-bit PPG Timer 00 Control Register (PC00)
Bit name
bit7,
bit6
bit5
bit4
bit3
bit2
to
bit0
472
Function
MD1,
MD0:
Operation mode select
bits
These bits select the PPG operation mode.
Do not modify the bit settings during counting.
Writing "00B": 8-bit PPG independent mode
Writing "01B": 8-bit prescaler + 8-bit PPG mode
Writing "10B" or "11B": 16-bit PPG mode
PIE0:
Interrupt request
enable bit
This bit controls interrupts of PPG timer 00.
• Set this bit in 16-bit PPG operation mode.
Writing "0": Disables interrupts of PPG timer 00.
Writing "1": Enables interrupts of PPG timer 00.
• An interrupt request (IRQ13) is output when the counter borrow detection bit (PUF0) and
PIE0 bit are both set to "1".
PUF0:
Counter borrow
detection flag bit for
PPG cycle
downcounter
This is the counter borrow detection flag for the PPG cycle downcounter of PPG timer 00.
• Only this bit is effective in 16-bit PPG operation mode (PC1:PUF1 is not operable).
Note: Always effective in 8-bit mode
• Writing "1" to this bit has no effect on operation.
• Writing "0" clears the bit.
• "1" is read by the read-modify-write (RMW) type of instruction.
Reading "0": No counter borrow of PPG timer 00 is detected.
Reading "1": A counter borrow of PPG timer 00 has been detected.
POEN0:
Output enable bit
This bit enables or disables the output of PPG timer 00 pin.
Writing "0": PPG timer 00 pin is used as a general-purpose port.
Writing "1": PPG timer 00 pin is used as the PPG output pin.
As the output is supplied from the PPG timer 00 pin in 16-bit PPG operation mode, this bit
is used to control the operation.
CKS02,
CKS01,
CKS00:
Operating clock select
bits
These bits select the operating clock for PPG downcounter of PPG timer 00.
• The operating clock is generated from the prescaler. See "CHAPTER 6 CLOCK
CONTROLLER".
• The rising and falling edge detection pulses from the PPG timer 01 output are used as the
count clock for PPG timer 00 when the 8-bit prescaler + 8-bit PPG mode has been
selected. Therefore, the setting of this bit has no effect on the operation.
• Set these bits in 16-bit PPG operation mode.
"000B": MCLK
"001B": MCLK/2
"010B": MCLK/4
"011B": MCLK/8
"100B": MCLK/16
"101B": MCLK/32
"110B": FCH*/27 or FCRH/26
"111B": FCH*/28 or FCRH/27
Note:
• The use of the subclock will stop the time-base timer operation. Therefore,
selecting "110B" or "111B" is prohibited.
• When these bits are set to "110B" or "111B", the count clock from the time-base
timer will be used as the operating clock. Depending on the settings of the
SYCC2 register, the count clock from the time-base timer can be generated
from the main clock, the main PLL clock or the main CR clock. In the case of
using the count clock from the time-base timer as the operating clock, resetting
the time-base timer by writing "1" to the time-base timer initialization bit in the
time-base timer control register (TBTC:TCLR) will affect the count time.
*: When the PCS[1:0] bits in the PLLC register are set to "00", the main clock divided by
two is used.
When the PCS[1:0] bits are set to "01", "10" or "11", the main PLL clock is used.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
21.5.3
8/16-bit PPG Timer 00/01 Cycle Setup Buffer
Register (PPS01, PPS00)
The 8/16-bit PPG timer 00/01 cycle setup buffer register (PPS01, PPS00) sets
the PPG output cycle.
■ 8/16-bit PPG Timer 00/01 Cycle Setup Buffer Register (PPS01, PPS00)
Figure 21.5-4 8/16-bit PPG Timer 00/01 Cycle Setup Buffer Register (PPS01, PPS00)
PPS01
PPS11
Address
0F9CH
0FA0H
bit7
PH7
R/W
bit6
PH6
R/W
bit5
PH5
R/W
bit4
PH4
R/W
bit3
PH3
R/W
bit2
PH2
R/W
bit1
PH1
R/W
bit0
PH0
R/W
Initial value
11111111B
PPS00
PPS10
0F9DH
0FA1H
bit7
PL7
R/W
bit6
PL6
R/W
bit5
PL5
R/W
bit4
PL4
R/W
bit3
PL3
R/W
bit2
PL2
R/W
bit1
PL1
R/W
bit0
PL0
R/W
Initial value
11111111B
R/W
: Readable/writable (The read value is the same as the write value.)
This register is used to set the PPG output cycle.
• In 16-bit PPG mode, PPS01 serves as the upper 8 bits, while PPS00 serves as the lower 8
bits.
• In 16-bit PPG mode, write the upper bits before the lower bits. When only the upper bits are
written, the previously written value is reused in the next load.
• 8-bit mode: Cycle = max. 255 (FFH) × Input clock cycle
• 16-bit mode: Cycle = max. 65535 (FFFFH) × Input clock cycle
• PPS01 and PPS00 are initialized upon reset.
• Do not set the cycle to "00H" or "01H" when using the unit in 8-bit PPG independent mode,
or in 8-bit prescaler mode + 8-bit PPG mode
• Do not set the cycle to "0000H" or "0001H" when using the unit in 16-bit PPG mode.
• If the cycle settings are modified during the operation, the modified settings will be
effective from the next PPG cycle.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
21.5.4
MB95410H/470H Series
8/16-bit PPG Timer 00/01 Duty Setup Buffer
Register (PDS01, PDS00)
The 8/16-bit PPG timer 00/01 duty setup buffer register (PDS01, PDS00) sets the
duty of the PPG output.
■ 8/16-bit PPG Timer 00/01 Duty Setup Buffer Register (PDS01, PDS00)
Figure 21.5-5 8/16-bit PPG Timer 00/01 Duty Setup Buffer Register (PDS01, PDS00)
PDS01
PDS11
Address
0F9EH
0FA2H
bit7
DH7
R/W
bit6
DH6
R/W
bit5
DH5
R/W
bit4
DH4
R/W
bit3
DH3
R/W
bit2
DH2
R/W
bit1
DH1
R/W
bit0
DH0
R/W
Initial value
11111111B
PDS00
PDS10
0F9FH
0FA3H
bit7
DL7
R/W
bit6
DL6
R/W
bit5
DL5
R/W
bit4
DL4
R/W
bit3
DL3
R/W
bit2
DL2
R/W
bit1
DL1
R/W
bit0
DL0
R/W
Initial value
11111111B
R/W
: Readable/writable (The read value is the same as the write value.)
This register is used to set the duty of the PPG output ("H" pulse width when normal polarity).
• In 16-bit PPG mode, PDS01 serves as the upper 8 bits while PDS00 serves as the lower 8
bits.
• In 16-bit PPG mode, write the upper bits before the lower bits. When only the upper bits are
written, the previously written value is reused in the next load. Writing data to PDF00 also
updates PDS01 at the same time.
• PDS01 and PDS00 are initialized at reset.
• To set the duty to 0%, select "00H".
• To set the duty to 100%, set it to the same value as the 8/16-bit PPG timer 00/01 cycle setup
register (PPS00, PPS01).
• When the 8/16-bit PPG timer 00/01 duty setup register (PDS) is set to a larger value than
the setting value of the 8/16-bit PPG cycle setup buffer register (PPS), the PPG output
becomes "L" output in the normal polarity (when the output level inversion bit of 8/16-bit
PPG output inversion register is "0").
• If the duty settings are modified during operation, the modified value will be effective from
the next PPG cycle.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
MB95410H/470H Series
21.5.5
8/16-bit PPG Start Register (PPGS)
The 8/16-bit PPG start register (PPGS) starts or stops the downcounter. The
operation enable bit of each channel is assigned to the PPGS register, allowing
simultaneous activation of the PPG channels.
■ 8/16-bit PPG Start Register (PPGS)
Figure 21.5-6 8/16-bit PPG Start Register (PPGS)
Address
0FA4H
bit7
bit6
bit5
bit4
- *
-*
- *
- *
R/W
R/W
R/W
R/W
bit3
bit2
bit1
bit0
PEN11 PEN10 PEN01 PEN00
R/W
R/W
R/W
Initial value
00000000B
R/W
PEN00 PPG timer 00 (ch. 0) downcounter operation enable bit
0
Stops operation
1
Enables operation
PEN01 PPG timer 01 (ch. 0) downcounter operation enable bit
0
Stops operation
1
Enables operation
PEN10 PPG timer 10 (ch. 1) downcounter operation enable bit
0
Stops operation
1
Enables operation
PEN11 PPG timer 11 (ch. 1) downcounter operation enable bit
0
Stops operation
1
Enables operation
R/W
*
MN702-00005-2v0-E
: Readable/writable (The read value is the same as the write value.)
: Initial value
: Writing any value to bit7 to bit4 has no effect on operation.
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CHAPTER 21 8/16-BIT PPG
21.5 Registers of 8/16-bit PPG
21.5.6
MB95410H/470H Series
8/16-bit PPG Output Inversion Register (REVC)
The 8/16-bit PPG output inversion register (REVC) inverts the PPG output
including the initial level.
■ 8/16-bit PPG Output Inversion Register (REVC)
Figure 21.5-7 8/16-bit PPG Output Inversion Register (REVC)
bit7
Address
0FA5H
-*
- *
R/W
R/W
R/W
*
476
bit6
bit5
-*
R/W
bit4
bit3
bit2
bit1
bit0
- * REV11 REV10 REV01 REV00
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W
REV00
0
1
PPG timer 00 (ch. 0) output level inversion bit
Normal
Inversion
REV01
0
1
PPG timer 01 (ch. 0) output level inversion bit
Normal
Inversion
REV10
0
1
PPG timer 10 (ch. 1) output level inversion bit
Normal
Inversion
REV11
0
1
PPG timer 11 (ch. 1) output level inversion bit
Normal
Inversion
: Readable/writable (The read value is the same as the write value.)
: Initial value
: Writing any value to bit7 to bit4 has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 21 8/16-BIT PPG
21.6 Interrupts of 8/16-bit PPG
MB95410H/470H Series
21.6
Interrupts of 8/16-bit PPG
The 8/16-bit PPG outputs an interrupt request when a counter borrow is
detected.
■ Interrupts of 8/16-bit PPG
Table 21.6-1 shows the interrupt control bits and interrupt sources of the 8/16-bit PPG.
Table 21.6-1 Interrupt Control Bits and Interrupt Sources of 8/16-bit PPG
Description
Item
PPG timer 01
(8-bit PPG, 8-bit prescaler)
PPG timer 00
(8-bit PPG, 16-bit PPG)
Interrupt request flag bit
PUF1 bit in PC01
PUF0 bit in PC00
Interrupt request enable bit
PIE1 bit in PC01
PIE0 bit in PC00
Interrupt source
Counter borrow of PPG cycle downcounter
When a counter borrow occurs on the downcounter, the 8/16-bit PPG sets the counter borrow
detection flag bit (PUF) in the 8/16-bit PPG timer 00/01 control register (PC) to "1". When the
interrupt request enable bit is enabled (PIE = 1), an interrupt request is output to the interrupt
controller.
In 16-bit PPG mode, the 8/16-bit PPG timer 00 control register (PC00) is available.
■ Registers and Vector Table Addresses Related to Interrupts of 8/16-bit PPG
Table 21.6-2 Registers and Vector Table Addresses Related to Interrupts of 8/16-bit PPG
Interrupt source
Interrupt
request no.
Interrupt level setup register
Vector table address
Register
Setting bit
Upper
Lower
8/16-bit PPG ch. 1
(lower)*
IRQ09
ILR2
L09
FFE8H
FFE9H
8/16-bit PPG ch. 1
(upper)
IRQ10
ILR2
L10
FFE6H
FFE7H
8/16-bit PPG ch. 0
(upper)
IRQ12
ILR3
L12
FFE2H
FFE3H
8/16-bit PPG ch. 0
(lower)
IRQ13
ILR3
L13
FFE0H
FFE1H
ch.: Channel
*: 8/16-bit PPG ch. 1 (lower) uses the same interrupt request number and vector table addresses as
UART/SIO ch. 1.
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
21.7
MB95410H/470H Series
Operations of 8/16-bit PPG and Setting Procedure
Example
This section describes the operations of the 8/16-bit PPG.
■ Setting Procedure Example
Below is an example of procedure for setting the 8/16-bit PPG.
● Initial settings
1) Set the port output. (DDR1, DDR2)
2) Set the interrupt level (ILR2, ILR3)
3) Select the operating clock, enable the output and interrupt. (PC01)
4) Select the operating clock, enable the output and interrupt, select the operation mode.
(PC00)
5) Set the cycle. (PPS)
6) Set the duty. (PDS)
7) Set the output inversion. (REVC)
8) Start PPG. (PPGS)
● Interrupt processing
1) Process any interrupt.
2) Clear the interrupt request flag. (PC01: PUF1, PC00: PUF0)
3) Start PPG. (PPGS)
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
MB95410H/470H Series
21.7.1
8-bit PPG Independent Mode
In this mode, the unit operates as two channels (PPG timer 00 and PPG timer
01) of the 8-bit PPG.
■ Setting 8-bit Independent Mode
The unit requires the register settings shown in Figure 21.7-1 to operate in 8-bit independent
mode.
Figure 21.7-1 8-bit Independent Mode
bit7
-
bit6
-
bit5
PIE1
bit4
bit3
bit2
bit1
bit0
PUF1 POEN1 CKS12 CKS11 CKS10
PC00
MD1
0
MD0
0
PIE0
PUF0 POEN0 CKS02 CKS01 CKS00
PPS01
PH7
PH6
PH5
PH4
PH3
PH2
PH1
Set PPG output cycle for PPG timer 01
PH0
PPS00
PL7
PL6
PL5
PL4
PL3
PL2
PL1
Set PPG output cycle for PPG timer 00
PL0
PDS01
DH7
DH6
DH5
DH4
DH3
DH2
DH1
Set PPG output duty for PPG timer 01
DH0
PDS00
DL7
DL6
DL0
PPGS
*
*
*
*
PEN11 PEN10 PEN01 PEN00
*
*
REVC
*
*
*
*
REV11 REV10 REV01 REV00
*
*
PC01
DL5
DL4
DL3
DL2
DL1
Set PPG output duty for PPG timer 00
: Used bit
0 : Set "0"
* : The bit status depends on the number of channels provided.
■ Operation of 8-bit PPG Independent Mode
• This mode is selected when the operation mode select bits (MD1, MD0) in the 8/16-bit PPG
timer 00 control register (PC00) are set to "00B".
• When the corresponding bit (PEN) in the 8/16-bit PPG start register (PPGS) is set to "1",
the value in the 8/16-bit PPG cycle setup buffer register (PPS) is loaded to start down-count
operation. When the count value reaches "1", the value in the cycle setup register is
reloaded to repeat the counting.
• "H" is output to the PPG output synchronizing with the count clock. When the downcounter
value matches the value in the 8/16-bit PPG timer 00/01 duty setup buffer register (PDS).
After "H" which is the value of duty setting is output, "L" is output to the PPG output.
If, however, the PPG output inversion bit is set to "1", the PPG output is set and reset inversely
from the above process.
Figure 21.7-2 shows the operation of the 8-bit PPG independent mode.
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
Figure 21.7-2 Operation of 8-bit PPG Independent Mode
MB95410H/470H Series
Count clock
(Cycle T)
PEN
(Counter start)
Stop
Cycle setting
m=5
(PPS)
Duty setting
n=4
(PDS)
PPG timer 00 counter value
5
4
3
2
1
5
4
3
2
1
5
4
3
2
Downcounter value matches
matches duty setting value
Counter borrow
PPG output source
Synchronizing with machine clock
Stop
PPG00 Pin
(Normal polarity)
(Reverse polarity)
(1)
α
(2)
(1) = n × T
(2) = m × T
T:
m:
n:
α:
Count clock cycle
PPS register value
PDS register value
The value changes depending
on the count clock selected and
the start timing.
Example of setting the duty to 50%
When PDS is set to "02H" with PPS set to "04H", the PPG output is set at a duty ratio of
50% (PPS setting value /2 set to PDS).
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
MB95410H/470H Series
21.7.2
8-bit Prescaler + 8-bit PPG Mode
In this mode, the rising and falling edge detection pulses from the PPG timer 01
output can be used as the count clock of the PPG timer 00 downcounter to
allow variable-cycle 8-bit PPG output from PPG timer 00.
■ Setting 8-bit Prescaler + 8-bit PPG Mode
The unit requires the register settings shown in Figure 21.7-3 to operate in 8-bit prescaler + 8bit PPG mode.
Figure 21.7-3 Setting 8-bit Prescaler + 8-bit PPG Mode
bit7
-
bit6
-
bit5
PIE1
bit4
bit3
bit2
bit1
bit0
PUF1 POEN1 CKS12 CKS11 CKS10
PC00
MD1
0
MD0
1
PIE0
PUF0 POEN0 CKS02 CKS01 CKS00
×
×
×
PPS01
PH7
PH6
PH5
PH4
PH3
PH2
PH1
Set PPG output cycle for PPG timer 01
PH0
PPS00
PL7
PL6
PL5
PL4
PL3
PL2
PL1
Set PPG output cycle for PPG timer 00
PL0
PDS01
DH7
DH6
DH5
DH4
DH3
DH2
DH1
Set PPG output duty for PPG timer 01
DH0
PDS00
DL7
DL6
DL0
PPGS
*
*
*
*
PEN11 PEN10 PEN01 PEN00
*
*
REVC
*
*
*
*
REV11 REV10 REV01 REV00
*
*
PC01
0
1
×
*
DL5
DL4
DL3
DL2
DL1
Set PPG output duty for PPG timer 00
: Used bit
: Set "0"
: Set "1"
: Setting nullified
: The bit status varies depending of the number of channels implemented
■ Operation of 8-bit Prescaler + 8-bit PPG Mode
• This mode is selected by setting the operation mode select bits (MD1, MD0) of the 8/16-bit
PPG timer 00 control register (PC00) to "01B". This allows PPG timer 01 to be used as an
8-bit prescaler and PPG timer 00 to be used as an 8-bit PPG.
• When the PPG timer 01 (ch. 0) down counter operation enable bit (PEN01) is set to "1", the
8-bit prescaler (PPG timer 01) loads the value in the 8/16-bit PPG timer 01 cycle setup
buffer register (PPS01) and starts down-count operation. When the value of the
downcounter matches the value in the 8/16-bit PPG timer 01 duty setup buffer register
(PDS01), the PPG01 output is set to "H" synchronizing with the count clock. After "H"
which is the value of duty setting is output, the PPG01 output is set to "L". If the output
inversion signal (REV01) is "0", the polarity will remain the same. If it is "1", the polarity
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
will be inverted and the signal will be output to the PPG pin.
MB95410H/470H Series
• When the PPG operation enable bit (PEN00) is set to "1", the 8-bit PPG (PPG timer 00)
loads the value in the 8/16-bit PPG timer 00 cycle setup buffer register (PPS00) and starts
down-count operation (count clock = rising and falling edge detection pulses of PPG01
output after PPG timer 01 operation is enabled). When the count value reaches "1", the
value in the 8/16-bit PPG timer 00 cycle setup buffer register is reloaded to repeat the
counting. When the value of the downcounter matches the value in the 8/16-bit PPG timer
00 duty setup buffer register (PDS00), the PPG00 output is set to "H" synchronizing with
the count clock. After "H" which is the value of duty setting is output, the PPG00 output is
reset to "L". If the output inversion signal (REV00) is "0", the polarity will remain the same.
If the output inversion signal (REV00) is "1", the polarity will be inverted and the signal
will be output to the PPG00 pin.
• Set that the duty of the 8-bit prescaler (PPG timer 01) output to 50%.
• When PPG timer 00 is started with the 8-bit prescaler (PPG timer 01) being stopped, PPG
timer 00 does not count.
• When the duty of the 8-bit prescaler (PPG timer 01) is set to 0% or 100%, PPG timer 00
does not perform counting as the 8-bit prescaler (PPG timer 01) output does not toggle.
Figure 21.7-4 shows the operation of 8-bit prescaler + 8-bit PPG mode.
Figure 21.7-4 Operation of 8-bit Prescaler + 8-bit PPG Mode
Count clock
(Cycle T)
PEN01
Cycle setting
(PPS01)
Duty setting
(PDS01)
PPG timer 01
counter value
m1=4
n1=2
4
3
2
1
4
3
2
1
4
3
2
1
4
3
1
2
4
Downcounter value
matches matches duty
setting value
Counter borrow
PPG output source
Synchronizing with machine clock
PPG01
(Normal polarity)
(Reverse polarity)
(1)
α
(2)
PEN00
Cycle setting
m0=3
(PPS00)
Duty setting
n0=2
(PDS00)
PPG timer 00
counter value
Downcounter value
matches matches duty
setting value
Counter borrow
3
2
1
3
2
3
1
2
PPG output source
Synchronizing with machine clock
PPG00
(Normal polarity)
(Reverse polarity)
(3)
β
(4)
(1) = n1 × T
(2) = m1 × T
(3) = (1) × n0
(4) = (1) × m0
482
T:
m0:
n0:
m1:
n1:
Count clock cycle
PPS00 register value
PDS00 register value
PPS01 register value
PDS01 register value
α:
β:
FUJITSU SEMICONDUCTOR LIMITED
The value changes depending on the count
clock selected and the PEN01 start timing.
The value changes depending on the
PPG01 output (ch.1) waveform and the
PEN00 start timing.
MN702-00005-2v0-E
MB95410H/470H Series
21.7.3
16-bit PPG Mode
CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
In this mode, the unit can operate as a 16-bit PPG when PPG timer 01 and PPG
timer 00 are assigned to the upper and lower bits respectively.
■ Setting 16-bit PPG Mode
The unit requires the register settings shown in Figure 21.7-5 to operate in 16-bit PPG mode.
Figure 21.7-5 Setting 16-bit PPG Mode
bit7
-
bit6
-
bit5
PIE1
bit4
bit3
bit2
bit1
bit0
PUF1 POEN1 CKS12 CKS11 CKS10
PC00
MD1
0
MD0
0/1
PIE0
PUF0 POEN0 CKS02 CKS01 CKS00
PPS01
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Set PPG output cycle (Upper 8 bits) for PPG timer 01
PPS00
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Set PPG output cycle (Lower 8 bits) for PPG timer 00
PDS01
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
Set PPG output duty (Upper 8 bits) for PPG timer 01
PDS00
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DL0
Set PPG output duty (Lower 8 bits) for PPG timer 00
PPGS
*
*
*
*
PEN11 PEN10 PEN01 PEN00
*
*
×
REVC
*
*
*
*
REV11 REV10 REV01 REV00
*
*
×
PC01
0
1
×
*
: Used bit
: Set "0"
: Set "1"
: Setting nullified
: The bit status changes depending on the number of channels implemented.
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CHAPTER 21 8/16-BIT PPG
21.7 Operations of 8/16-bit PPG and Setting Procedure
Example
MB95410H/470H Series
■ Operation of 16-bit PPG Mode
• This mode is selected by setting the operation mode select bits (MD1, MD0) of the PPG
timer 00 control register (PC00) to "10B" or "11B".
• When the PPG operation enable bit (PEN00) is set to "1" in 16-bit PPG mode, the 8-bit
downcounters (PPG timer 00) and 8-bit downcounter (PPG timer 01) load the values in the
8/16-bit PPG timer 00/01 cycle setup buffer registers (PPS01 for PPG timer 01 and PPS00
for PPG timer 00) and start down-count operation. When the count value reaches "1", the
values in the cycle setup register are reloaded and the counters repeat the counting.
• When the values of the downcounters match the values in the 8/16-bit PPG timer duty setup
buffer registers (both the value in PDS01 for PPG timer 01 and the value in PDS00 for PPG
timer 00), the PPG00 pin is set to "H" synchronizing with the count clock. After "H" which
is the value of duty setting is output, the PPG00 pin is set to "L". If the output inversion
signal (REV00) is "0", the signal will be output to the PPG00 with the polarity unchanged.
If it is set to "1", the polarity will be inverted and the signal will be output to the PPG00 pin.
(This applies to ch. 0 only. Ch. 1 will be set to the initial value <"L" if REV01 is "0", or "H"
if it is "1">.)
Figure 21.7-6 shows the operation of 16-bit PPG mode.
Figure 21.7-6 Operation of 16-bit PPG Mode
Count clock
(Cycle T)
PEN00
Cycle setup
(PPS01 and PPS00)
m=256
Duty setup
(PDS01 and PDS00)
n=2
Counter value
256
255
254
...
2
1
256
255
...
2
1
256
255
Downcounter value matches
matches duty setting value
Counter borrow
PPG output source
Synchronizing with
machine clock
PPG00
(Normal polarity)
(Reverse polarity)
(1)
α
(2)
(1) = n × T
(2) = m × T
484
T:
m:
n:
α:
FUJITSU SEMICONDUCTOR LIMITED
Count clock cycle
PPS01 & PPS00
PDS01 & PDS00
The value changes depending on the count
clock selected and the start timing.
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MB95410H/470H Series
21.8
Notes on Using 8/16-bit PPG
CHAPTER 21 8/16-BIT PPG
21.8 Notes on Using 8/16-bit PPG
This section provides notes on using the 8/16-bit PPG.
■ Notes on Using 8/16-bit PPG
● Operational precaution
Depending on the timing between the activation of PPG and count clock, an error may occur in
the first cycle of the PPG output immediately after the activation. The error varies depending
on the count clock selected. The output, however, is performed properly in the succeeding
cycles.
● Precaution regarding interrupts
A PPG interrupt is generated when the interrupt enable bit (PIE1/PIE0) is set to "1" and the
interrupt request flag bit (PUF1/PUF0) in the 8/16-bit PPG timer 01/00 control register (PC01/
PC00) is also set to "1". Always clear the interrupt request flag bit (PUF1/PUF0) to "0" in the
interrupt routine.
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CHAPTER 21 8/16-BIT PPG
21.9 Sample Settings for 8/16-bit PPG Timer
21.9
MB95410H/470H Series
Sample Settings for 8/16-bit PPG Timer
This section provides sample settings for the 8/16-bit PPG timer.
■ Sample Settings
● How to enable/stop PPG operation
The PPG operation enable bit (PPGS:PEN00 or PEN10) is used for PPG00.
Operation
PPG operation enable bit (PEN00 or PEN10)
To stop PPG operation
Set the bit to "0".
To enable PPG operation
Set the bit to "1".
PPG operation must be enabled before the PPG is activated.
The PPG operation enable bit (PPGS:PEN01 or PEN11) is used for PPG01.
Operation
PPG operation enable bit (PEN01 or PEN11)
To stop PPG operation
Set the bit to "0".
To enable PPG operation
Set the bit to "1".
PPG operation must be enabled before the PPG is activated.
● How to set the PPG operation mode
The operation mode select bits (PC00:MD[1:0]) are used.
● How to select the operating clock
Ch. 1 is selected by the operating clock select bits (PC01:CKS12/CKS11/CKS10).
Ch. 0 is selected by the operating clock select bits (PC00:CKS02/CKS01/CKS00).
● How to enable/disable the PPG output pin
The output enable bit (PC00:POEN0 or PC01:POEN1) is used.
486
Operation
Output enable bit (POEN0 or POEN1)
To enable PPG output
Set the bit to "1".
To disable PPG output
Set the bit to "0".
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CHAPTER 21 8/16-BIT PPG
21.9 Sample Settings for 8/16-bit PPG Timer
MB95410H/470H Series
● How to invert the PPG output
The output level inversion bit (REVC:REV00 or REV10) is used for PPG00.
Operation
Output level inversion bit (REV00 or REV10)
To invert PPG output
Set the bit to "1".
The output level inversion bit (REVC:REV01 or REV11) is used for PPG01.
Operation
Output level inversion bit (REV01 or REV11)
To invert PPG output
Set the bit to "1".
● Interrupt-related register
The interrupt level is set by the interrupt level setting register shown in the following table.
Interrupt source
Interrupt level setting register
Interrupt vector
ch. 1 (lower)
Interrupt level setting register (ILR2)
Address: 0007BH
#09
Address: 0FFE8H
ch. 1 (upper)
Interrupt level setting register (ILR2)
Address: 0007BH
#10
Address: 0FFE6H
ch. 0 (lower)
Interrupt level setting register (ILR3)
Address: 0007CH
#13
Address: 0FFE0H
ch. 0 (upper)
Interrupt level setting register (ILR3)
Address: 0007CH
#12
Address: 0FFE2H
● How to enable/disable/clear interrupts
Interrupt request enable flag, Interrupt request flag
The interrupt request enable bit (PC00:PIE0 or PC01:PIE1) is used to enable or disable
interrupts.
Operation
Interrupt request enable bit (PIE0 or PIE1)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
The interrupt request flag (PC00:PUF0 or PC01:PUF1) is used to clear interrupt requests.
Operation
Interrupt request flag (PUF0 or PUF1)
To clear an interrupt request
Set the bit to "0".
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CHAPTER 21 8/16-BIT PPG
21.9 Sample Settings for 8/16-bit PPG Timer
488
MB95410H/470H Series
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 22
UART/SIO
This chapter describes the functions and
operations of UART/SIO.
22.1 Overview of UART/SIO
22.2 Configuration of UART/SIO
22.3 Channels of UART/SIO
22.4 Pins of UART/SIO
22.5 Registers of UART/SIO
22.6 Interrupts of UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
22.8 Sample Settings for UART/SIO
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CHAPTER 22 UART/SIO
22.1 Overview of UART/SIO
22.1
MB95410H/470H Series
Overview of UART/SIO
The UART/SIO is a general-purpose serial data communication interface. Serial
data transfers of variable-length data can be made with a synchronous or
asynchronous clock. The transfer format is NRZ. The transfer rate can be set
with the dedicated baud rate generator or external clock (in clock synchronous
mode).
■ Functions of UART/SIO
The UART/SIO is capable of serial data transmission/reception (serial input/output) to and
from another CPU or peripheral device.
• Equipped with a full-duplex double buffer that allows 2-way full-duplex communication.
• The synchronous or asynchronous transfer mode can be selected.
• The optimum baud rate can be selected with the dedicated baud rate generator.
• The data length is variable; it can be set to 5 to 8 bits when no parity is used or to 6 to 9 bits
when parity is used. (See Table 22.1-1.)
• The serial data direction (endian) can be selected.
• The data transfer format is NRZ (Non-Return-to-Zero).
• Two operation modes (operation modes 0 and 1) are available.
Operation mode 0 operates as asynchronous clock mode (UART).
Operation mode 1 operates as clock synchronous mode (SIO).
Table 22.1-1 UART/SIO Operation Modes
Data length
Operation mode
No parity
With parity
5
6
6
7
7
8
8
9
5
-
6
-
7
-
8
-
0
1
490
Synchronization
mode
Length of stop bit
Asynchronous
1 bit or 2 bits
Synchronous
1 bit or 2 bits
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CHAPTER 22 UART/SIO
22.2 Configuration of UART/SIO
MB95410H/470H Series
22.2
Configuration of UART/SIO
The UART/SIO consists of the following blocks:
• UART/SIO serial mode control register 1 (SMC10/SMC11/SMC12)
• UART/SIO serial mode control register 2 (SMC20/SMC21/SMC22)
• UART/SIO serial status register (SSR0/SSR1/SSR2)
• UART/SIO serial input data register (RDR0/RDR1/RDR2)
• UART/SIO serial output data register (TDR0/TDR1/TDR2)
■ Block Diagram of UART/SIO
Figure 22.2-1 Block Diagram of UART/SIO
PER
State from
each block
Reception
state
decision
circuit
OVE
FER
RDRF
RIE
Dedicated baud rate generator
1/4
External clock input
UCK
Reception
interrupt
TDRE
Clock
selector
State from
each block
Pin
Transmission state
decision
circuit
TEIE
TCPL
Transmission
interrupt
TCIE
Serial clock output
Serial data input
UI
Reception bit
count
Shift
register
for
reception
Pin
Data sample clock input
Serial data output
UO
Pin
UART/SIO
serial
status
register
Parity
operation
Shift
register
for transmission
Parity
operation
UART/SIO
serial
output data
register
Transmission bit
count
Port control
Set to
each block
MN702-00005-2v0-E
UART/SIO
serial
input data
register
Internal bus
Start
bit
detection
UART/SIO
serial
mode
control
registers
1, 2
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CHAPTER 22 UART/SIO
22.2 Configuration of UART/SIO
MB95410H/470H Series
● UART/SIO serial mode control register 1 (SMC10/SMC11/SMC12)
This register controls UART/SIO operation mode. It is used to set the serial data direction
(endian), parity and its polarity, stop bit length, operation mode (synchronous/asynchronous),
data length, and serial clock.
● UART/SIO serial mode control register 2 (SMC20/SMC21/SMC22)
This register controls UART/SIO operation mode. It is used to enable/disable serial clock
output, serial data output, transmission/reception, and interrupts and to clear the reception error
flag.
● UART/SIO serial status register (SSR0/SSR1/SSR2)
This register indicates the transmission/reception status and error status of UART/SIO.
● UART/SIO serial input data register (RDR0/RDR1/RDR2)
This register holds the receive data. The serial input is converted and then stored in this
register.
● UART/SIO serial output data register (TDR0/TDR1/TDR2)
This register sets the transmit data. Data written to this register is serial-converted and then
outputted.
■ Input Clock
The UART/SIO uses the output clock (internal clock) from the dedicated baud rate generator or
the input signal (external clock) from the UCK pin as its input clock (serial clock).
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CHAPTER 22 UART/SIO
22.3 Channels of UART/SIO
MB95410H/470H Series
22.3
Channels of UART/SIO
This section describes the channels of UART/SIO.
■ Channels of UART/SIO
The MB95410H/470H Series has 3 channels of UART/SIO. The following table shows the
correspondence of the channel, pin, and register.
Table 22.3-1 Pins of UART/SIO
Channel
Pin name
UCK0
0
1
2
Pin function
Clock input/output
UO0
Data output
UI0
Data input
UCK1
Clock input/output
UO1
Data output
UI1
Data input
UCK2
Clock input/output
UO2
Data output
UI2
Data input
Table 22.3-2 Registers of UART/SIO
Channel
0
1
2
Register
abbreviation
Corresponding register (Name in this manual)
SMC10
UART/SIO serial mode control register 1
SMC20
UART/SIO serial mode control register 2
SSR0
UART/SIO serial status register
TDR0
UART/SIO serial output data register
RDR0
UART/SIO serial input data register
SMC11
UART/SIO serial mode control register 1
SMC21
UART/SIO serial mode control register 2
SSR1
UART/SIO serial status register
TDR1
UART/SIO serial output data register
RDR1
UART/SIO serial input data register
SMC12
UART/SIO serial mode control register 1
SMC22
UART/SIO serial mode control register 2
SSR2
UART/SIO serial status register
TDR2
UART/SIO serial output data register
RDR2
UART/SIO serial input data register
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CHAPTER 22 UART/SIO
22.4 Pins of UART/SIO
22.4
MB95410H/470H Series
Pins of UART/SIO
This section describes the pins of the UART/SIO.
■ Pins of UART/SIO
The pins associated with UART/SIO are the clock input and output pin (UCK), serial data
output pin (UO) and serial data input pin (UI).
The following sections describe only ch. 0 of UART/SIO.
The functions of UCK1, UO1 and UI1 of ch. 1 and those of UCK2, UO2 and UI2 of ch. 2 are
identical to those of UCK0, UO0 and UI0 of ch. 0 respectively.
UCK0:
Clock input/output pin for UART/SIO.
When the clock output is enabled (SMC20:SCKE=1), it serves as a UART/SIO clock output
pin regardless of the value of the corresponding port direction register. At this time, do not
select the external clock (SMC10:CKS = 0).
When it is to be used as a UART/SIO clock input pin, disable the clock output
(SMC20:SCKE = 0) and make sure that it is set as input port by the corresponding port
direction register. At this time, be sure to select the external clock (SMC10:CKS = 0).
UO0:
Serial data output pin for UART/SIO. When the serial data output is enabled
(SMC20:TXOE = 1), it serves as a UART/SIO serial data output pin regardless of the value
of the corresponding port direction register.
UI0:
Serial data input pin for UART/SIO. When it is to be used as a UART/SIO serial data input
pin, make sure that it is set as input port by the corresponding port direction register.
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CHAPTER 22 UART/SIO
22.4 Pins of UART/SIO
MB95410H/470H Series
■ Block Diagrams of Pins of UART/SIO
Figure 22.4-1 Block Diagram of UO0 of UART/SIO
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
Figure 22.4-2 Block Diagram of UCK0 of UART/SIO
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
0
1
PDR read
1
PDR
pin
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
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CHAPTER 22 UART/SIO
22.4 Pins of UART/SIO
MB95410H/470H Series
Figure 22.4-3 Block Diagram of UI0 of UART/SIO
Peripheral function input
Peripheral function input enable
Hysteresis
Pull-up
0
1
PDR read
CMOS
pin
PDR
PDR write
Executing bit manipulation instruction
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
PUL read
PUL
PUL write
ILSR read
ILSR
ILSR write
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CHAPTER 22 UART/SIO
22.5 Registers of UART/SIO
MB95410H/470H Series
22.5
Registers of UART/SIO
The registers of UART/SIO are UART/SIO serial mode control register 1 (SMC1),
UART/SIO serial mode control register 2 (SMC2), UART/SIO serial status
register (SSR), UART/SIO serial output data register (TDR), and UART/SIO serial
input data register (RDR).
■ Registers of UART/SIO
Figure 22.5-1 Registers of UART/SIO
UART/SIO serial mode control register 1 (SMC1)
Address bit7
bit6
bit5
bit4
SMC10 0056H
BDS
PEN
TDP
SBL
SMC11 005BH
R/W
R/W
R/W
R/W
SMC12 0066H
bit3
CBL1
R/W
bit2
CBL0
R/W
bit1
CKS
R/W
bit0
MD
R/W
Initial value
00000000B
UART/SIO serial mode control register 2 (SMC2)
Address bit7
bit6
bit5
bit4
SMC20 0057H SCKE TXOE RERC RXE
SMC21 005CH
R/W
R/W
R1/W
R/W
0067
SMC22
H
bit3
TXE
R/W
bit2
RIE
R/W
bit1
TCIE
R/W
bit0
TEIE
R/W
Initial value
00100000B
bit1
TCPL
Initial value
00000001B
UART/SIO serial status register (SSR)
Address bit7
bit6
bit5
0058H
SSR0
PER
005DH R0/WX R0/WX R/WX
SSR1
0068H
SSR2
bit4
OVE
R/WX
bit3
FER
R/WX
bit2
RDRF
R/WX
R(RM1), W
bit0
TDRE
R/WX
UART/SIO serial output data register (TDR)
Address bit7
bit6
bit5
0059H
TD7
TD6
TD5
TDR0
005EH
TDR1
R/W
R/W
R/W
0069
TDR2
H
bit4
TD4
R/W
bit3
TD3
R/W
bit2
TD2
R/W
bit1
TD1
R/W
bit0
TD0
R/W
Initial value
XXXXXXXXB
UART/SIO serial input data register (RDR)
Address bit7
bit6
bit5
005AH
RDR0
RD7
RD6
RD5
005FH R/WX R/WX R/WX
RDR1
006AH
RDR2
bit4
RD4
R/WX
bit3
RD3
R/WX
bit2
RD2
R/WX
bit1
RD1
R/WX
bit0
RD0
R/WX
Initial value
00000000B
R/W
R(RM1), W
R/WX
R0/WX
R1/W
-
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from write value. "1" is read by the readmodify-write (RMW) type of instruction.)
: Read only (Readable. Writing a value to this bit has no effect on operation.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Readable/writable (The read value is "1".)
: Undefined bit
The following sections describe only UART/SIO ch. 0.
Ch. 1 and ch. 2 have the same configuration as ch. 0.
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CHAPTER 22 UART/SIO
22.5 Registers of UART/SIO
22.5.1
MB95410H/470H Series
UART/SIO Serial Mode Control Register 1 (SMC10)
The UART/SIO serial mode control register 1(SMC10) controls the UART/SIO
operation mode. The register is used to set the serial data direction (endian),
parity and its polarity, stop bit length, operation mode (clock synchronous
mode/clock asynchronous mode), data length, and serial clock.
■ UART/SIO Serial Mode Control Register 1 (SMC10)
Figure 22.5-2 UART/SIO Serial Mode Control Register 1 (SMC10)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Address
0056H BDS PEN TDP SBL CBL1 CBL0 CKS
bit0
Initial value
MD
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
MD
0
1
Operating mode select bit
Clock asynchronous mode (UART)
Clock synchronous mode (SIO)
Clock select bit
CKS
0
Dedicated baud rate generator
1
External clock (cannot be used in clock asynchronous mode)
CBL1 CBL0
Character bit length control bits
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Stop bit length control bit
SBL
R/W
498
0
1-bit length
1
2-bit length
TDP
0
Even parity
1
Odd parity
Parity polarity bit
PEN
0
No parity
1
With parity
Parity control bit
Serial data direction control bit
BDS
0
Transmit/receive data from LSB side sequentially
1
Transmit/receive data from MSB side sequentially
: Readable/writable (The read value is the same as the write value.)
: Initial value
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22.5 Registers of UART/SIO
MB95410H/470H Series
Table 22.5-1 Functions of Bits in UART/SIO Serial Mode Control Register 1 (SMC10)
Bit name
Function
bit7
BDS:
Serial data direction
control bit
This bit sets the serial data direction (endian).
Writing "0": The bit specifies transmission or reception to be performed sequentially
starting from the LSB side in the serial data register.
Writing "1": The bit specifies transmission or reception to be performed sequentially
starting from the MSB side in the serial data register.
bit6
PEN:
Parity control bit
This bit enables or disables parity in clock asynchronous mode.
Writing "0": No parity
Writing "1": With parity
bit5
TDP:
Parity polarity bit
This bit controls even/odd parity.
Writing "0": Specifies even parity.
Writing "1": Specifies odd parity.
SBL:
Stop bit length control
bit
This bit controls the length of the stop bit in clock asynchronous mode.
Writing "0": Sets the stop bit length to "1".
Writing "1": Sets the stop bit length to "2".
Note:
The setting of this bit is only valid for transmission operation in clock
asynchronous mode.
For receiving operation, reception data register full flag is set to "1" after detecting
stop bit(1-bit) and completing the reception regardless of this bit.
bit4
These bits select the character bit length as shown in the following table:
bit3,
bit2
CBL1, CBL0:
Character bit length
control bits
CBL1
CBL0
Character bit length
0
0
5
0
1
6
1
0
7
1
1
8
• The above setting is valid in both clock asynchronous mode and clock synchronous
modes.
bit1
CKS:
Clock select bit
This bit selects the external clock or dedicated baud rate generator.
Writing "0": Selects the dedicated baud rate generator.
Writing "1": Selects the external clock.
Note:
Setting this bit to "1" forcibly disables the output of the UCK0 pin.
The external clock cannot be used in clock asynchronous mode (UART).
bit0
MD:
Operating mode select
bit
This bit selects clock asynchronous mode (UART) or clock synchronous mode (SIO).
Writing "0": Selects clock asynchronous mode (UART).
Writing "1": Selects clock synchronous mode (SIO).
Note:
When modifying the UART/SIO serial mode control register 1 (SMC10), do not perform
the modification during data transmission or reception.
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CHAPTER 22 UART/SIO
22.5 Registers of UART/SIO
MB95410H/470H Series
UART/SIO Serial Mode Control Register 2 (SMC20)
22.5.2
The UART/SIO serial mode control register 2 (SMC20) controls the UART/SIO
operation mode. The register is used to enable/disable serial clock output,
serial data output, transmission/reception, and interrupts and to clear the
reception error flag.
■ UART/SIO Serial Mode Control Register 2 (SMC20)
Figure 22.5-3 UART/SIO Serial Mode Control Register 2 (SMC20)
bit7 bit6 bit5 bit4
Address
0057H SCKE TXOE RERC RXE
R/W
R/W
R1/W R/W
bit3
bit2
bit1
bit0
Initial value
TXE
RIE
TCIE TEIE
00100000B
R/W R/W
R/W
R/W
Transmission data register empty interrupt enable bit
TEIE
0
Disables transmission data register empty interrupts.
1
Enables transmission data register empty interrupts.
Transmission completion interrupt enable bit
TCIE
0
Disables transmission completion interrupts.
1
Enables transmission completion interrupts.
Disables reception interrupts.
1
Enables reception interrupts.
Disables transmission operation.
1
Enables transmission operation.
Reception operation enable bit
RXE
0
Disables reception operation.
1
Enables reception operation.
Reception error flag clear bit
0
Clears the error flags in the SSR0 register.
1
Has no effect on operation.
TXOE
Serial data output enable bit
0
Disables serial data output (usable as a general-purpose port).
1
Enables serial data output.
SCKE
500
Transmission operation enable bit
TXE
0
RERC
R/W
R1/W
Reception interrupt enable bit
RIE
0
Serial clock output enable bit
0
Disables serial clock output (usable as a general-purpose port).
1
Enables serial clock output.
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is “1”.)
: Initial value
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22.5 Registers of UART/SIO
MB95410H/470H Series
Table 22.5-2 Functions of Bits in UART/SIO Serial Mode Control Register 2 (SMC20)
Bit name
Function
bit7
SCKE:
Serial clock output
enable bit
This bit controls the input/output of the serial clock pin (UCK0) in clock synchronous
mode.
Writing "0": Allows the pin to be used as a general-purpose port.
Writing "1": Enables clock output.
Note:
When CKS is "1", the internal clock signal is not outputted even with this bit set to
"1".
If this bit is set to "1" with SMC10:MD set to "0"(asynchronous mode), the output
from the port will always be "H".
bit6
TXOE:
Serial data output
enable bit
This bit controls the output of the serial data pin (UO0).
Writing "0": Allows the pin to be used as a general-purpose port.
Writing "1": Enables serial data output.
bit5
RERC:
Reception error flag
clear bit
Writing "0": Clears the error flags (PER, OVE, FER) in the SSR0 register.
Writing "1": Has no effect on operation.
• Reading this bit always returns "1".
bit4
RXE:
Reception operation
enable bit
Writing "0": Disables the reception of serial data.
Writing "1": Enables the reception of serial data.
• If this bit is set to "0" during reception, the reception operation will be immediately
disabled and initialization will be performed. The data received up to that point will not
be transferred to the UART/SIO serial input data register.
Note:
Setting this bit to "0" initializes reception operation. It has no effect on the error
flags (PER, OVE, FER, RDRF).
bit3
Writing "0": Disables the transmission of serial data.
Writing "1": Enables the transmission of serial data.
TXE:
• If this bit is set to "0" during transmission, the transmission operation will be immediately
Transmission operation
disabled and initialization will be performed. The transmission completion flag (TCPL)
enable bit
will be set to "1" and the transmission data register empty (TDRE) bit will also be set to
"1".
bit2
RIE:
Reception interrupt
enable bit
Writing "0": Disables reception interrupts.
Writing "1": Enables reception interrupts.
• A reception interrupt occurs immediately after either the receive data register full (RDRF)
bit or an error flag (PER, OVE, FER, or RDRF) is set to "1" with this bit set to "1"
(enabled).
bit1
TCIE:
Transmission
completion interrupt
enable bit
Writing "0": Disables interrupts by the transmission completion flag.
Writing "1": Enables interrupts by the transmission completion flag.
• A transmission interrupt occurs immediately after the transmission completion flag
(TCPL) bit is set to "1" with this bit set to "1" (enabled).
bit0
TEIE:
Writing "0": Disables interrupts by the transmission data register empty.
Transmission data
Writing "1": Enables interrupts by the transmission data register empty.
register empty interrupt • A transmission interrupt occurs immediately after the transmission data register empty
enable bit
(TDRE) bit is set to "1" with this bit set to "1" (enabled).
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22.5 Registers of UART/SIO
22.5.3
MB95410H/470H Series
UART/SIO Serial Status Register (SSR0)
The UART/SIO serial status register (SSR0) indicates the transmission/
reception status and error status of the UART/SIO.
■ UART/SIO Serial Status Register (SSR0)
Figure 22.5-4 UART/SIO Serial Status Register (SSR0)
Address
0058H
bit7
bit6
-
-
bit5
bit4
bit3
bit2
bit1
bit0
PER OVE FER RDRF TCPL TDRE
Initial value
00000001B
R0/WX R0/WX R/WX R/WX R/WX R/WX R(RM1), W R/WX
TDRE
Transmit data register empty flag
0
Transmit data present
1
Transmit data absent
Transmission completion flag
TCPL
0
Cleared by writing "0"
1
Serial transmission complete
Receive data register full flag
RDRF
0
Receive data absent
1
Receive data present
Framing error flag
FER
0
Framing error absent
1
Framing error present
Overrun error flag
OVE
0
Overrun error absent
1
Overrun error present
Parity error flag
PER
0
Parity error absent
1
Parity error present
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R/WX
R0/WX
-
502
:
:
:
:
Read only (Readable. Writing a value to this bit has no effect on operation.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
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22.5 Registers of UART/SIO
MB95410H/470H Series
Table 22.5-3 Functions of Bits in UART/SIO Serial Status Register (SSR0)
Bit name
bit7,
bit6
Undefined bits
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
PER:
Parity error flag
This flag detects a parity error in receive data.
• The bit is set when a parity error occurs during reception. Writing "0" to the RERC bit
clears this flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set
preferentially.
OVE:
Overrun error flag
This flag detects an overrun error in receive data.
• The flag is set when an overrun error occurs during reception. Writing "0" to the RERC
bit clears this flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set
preferentially.
bit3
FER:
Framing error flag
This flag detects a framing error in receive data.
• The bit is set when a framing error occurs during reception. Writing "0" to the RERC bit
clears this flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set
preferentially.
bit2
RDRF:
Receive data register
full flag
This flag indicates the status of the UART/SIO serial input data register.
• The bit is set to "1" when receive data is loaded to the serial input data register.
• The bit is cleared to "0" when data is read from the serial input data register.
bit1
TCPL:
Transmission
completion flag
This flag indicates the data transmission status.
• The bit is set to "1" upon completion of serial transmission. Note, however, that the bit is
not set to "1" even upon completion of transmission when the UART/SIO serial output
data register contains data to be transmitted in succession.
• Writing "0" to this bit clears its flag.
• If events to set and clear the flag occur at the same time, it is set preferentially.
• Writing "1" to this bit has no effect on operation.
bit0
TDRE:
Transmit data register
empty flag
This flag indicates the status of the UART/SIO serial output data register.
• The bit is set to "0" when transmit data is written to the serial output register.
• The bit is set to "1" when data is loaded to the transmission shift register and transmission
starts.
bit5
bit4
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22.5 Registers of UART/SIO
22.5.4
MB95410H/470H Series
UART/SIO Serial Input Data Register (RDR0)
The UART/SIO serial input data register (RDR0) is used to input (receive) serial
data.
■ UART/SIO Serial Input Data Register (RDR0)
Figure 22.5-5 shows the bit configuration of the UART/SIO serial input data register.
Figure 22.5-5 UART/SIO Serial Input Data Register (RDR0)
Address
005AH
R/WX
bit7
RD7
R/WX
bit6
RD6
R/WX
bit5
RD5
R/WX
bit4
RD4
R/WX
bit3
RD3
R/WX
bit2
RD2
R/WX
bit1
RD1
R/WX
bit0
RD0
R/WX
Initial value
00000000B
: Read only (Readable. Writing a value to it has no effect on operation.)
This register stores received data. The serial data signals sent to the serial data input pin (UI0)
is converted by the shift register and stored in this register.
When received data is set correctly in this register, the receive data register full (RDRF) bit is
set to "1". At this time, an interrupt occurs if reception interrupt requests have been enabled. If
an RDRF bit check by the program or using an interruption shows that received data is stored
in this register, the reading of the content for this register clears the RDRF flag to "0".
When the character bit length (CBL1, CBL0) is set to shorter than 8 bits, the excess upper bits
(beyond the set bit length) are set to "0".
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22.5 Registers of UART/SIO
MB95410H/470H Series
22.5.5
UART/SIO Serial Output Data Register (TDR0)
The UART/SIO serial output data register (TDR0) is used to output (transmit)
serial data.
■ UART/SIO Serial Output Data Register (TDR0)
Figure 22.5-6 shows the bit configuration of the UART/SIO serial output data register.
Figure 22.5-6 UART/SIO Serial Output Data Register (TDR0)
Address
0059H
bit7
TD7
R/W
R/W
bit6
TD6
R/W
bit5
TD5
R/W
bit4
TD4
R/W
bit3
TD3
R/W
bit2
TD2
R/W
bit1
TD1
R/W
bit0
TD0
R/W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
This register holds data to be transmitted. The register accepts a write when the transmission
data register empty (TDRE) bit contains "1". An attempt to write to the bit is ignored when the
bit contains "0".
When this register is updated at writting complete the transmission data and TDRE=0 (without
depending on TXE of the UART/SIO serial mode control register2 is "1" or "0"), the
transmission operation is initialized by writing "0" to TXE, TDRE becomes "1", and updating
this register is enabled.
Moreover, when "0" is written in TXE without the starting transmission (when the transmission
data is written in TDR0, and it has not transmitted TXE to "1" yet), TCPL is not set in "1". The
transmission data is transferred to the shift register for the transmission, it is converted into the
serial data, and it is transmitted from the serial data output terminal.
When transmit data is written to the UART/SIO serial output data register (TDR0), the
transmission data register empty bit (TDRE) is set to "0". Upon completion of transfer of
transmit data to the transmission shift register, the transmission data register empty bit (TDRE)
is set to "1", allowing the next piece of transmit data to be written. At this time, an interrupt
occurs if transmission data register empty interrupts have been enabled. Write the next transmit
data when transmit data empty occurs or the TDRE bit is set to "1".
When the character bit length (CBL1, CBL0) is set to shorter than 8 bits, the excess upper bits
(beyond the set bit length) are ignored.
Note:
The data in this register cannot be updated when TDRE in UART/SIO serial status data
register is "0".
When this register is updated at writing complete the transmission data and TDRE=0
(without depending on TXE of the UART/SIO serial mode control register 2 is "1" or "0"),
the transmission operation is initialized by writing "0" to TXE, TDRE becomes "1", and the
update of this register becomes possible.
Moreover, when "0" is written in TXE without the starting transmission (when the
transmission data is written in TDR0, and it has not transmitted TXE to "1" yet), TCPL is
not set in "1". And, to change data, please write it after making TDRE "1" once by writing
TXE =0.
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CHAPTER 22 UART/SIO
22.6 Interrupts of UART/SIO
22.6
MB95410H/470H Series
Interrupts of UART/SIO
The UART/SIO has six interrupt-related bits: error flag bits (PER, OVE, FER),
receive data register full bit (RDRF), transmission data register empty bit
(TDRE), and transmission completion flag (TCPL).
■ Interrupts of UART/SIO
Table 22.6-1 lists the UART/SIO interrupt control bits and interrupt sources.
Table 22.6-1 UART/SIO Interrupt Control Bits and Interrupt Sources
Item
Description
Interrupt
request flag bit
SSR0: TDRE
SSR0: TCPL
SSR0: RDRF
SSR0: PER
SSR0: OVE
SSR0: FER
Interrupt
request enable
bit
SMC20: TEIE
SMC20: TCIE
SMC20: RIE
SMC20: RIE
SMC20: RIE
SMC20: RIE
Interrupt
source
Transmission
data register
empty
Transmission
completion
Receive data
full
Parity error
Overrun error
Framing error
■ Transmission Interrupt
When transmit data is written to the UART/SIO serial output data register (TDR0), the data is
transferred to the transmission shift register. When the next piece of data can be written, the
TDRE bit is set to "1". At this time, an interrupt request to the interrupt controller occurs when
transmit data register empty interrupt enable bit has been enabled (SMC20:TEIE = 1).
The TCPL bit is set to "1" upon completion of transmission of all pieces of transmit data. At
this time, an interrupt request to the interrupt controller occurs when transmission completion
interrupt enable bit has been enabled (SMC20:TCIE = 1).
■ Reception Interrupt
If the data is input successfully up to the stop bit, the RDRF bit is set to "1". If an overrun,
parity, or framing error occurs, the corresponding error flag bit (PER, OVE, or FER) is set to
"1".
These bits are set when a stop bit is detected. If reception interrupt enable bit has been enabled
(SMC20:RIE = 1), an interrupt request to the interrupt controller will be generated.
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CHAPTER 22 UART/SIO
22.6 Interrupts of UART/SIO
MB95410H/470H Series
■ Registers and Vector Table Addresses Related to UART/SIO Interrupts
Table 22.6-2 Registers and Vector Table Addresses Related to UART/SIO Interrupts
Interrupt source
Interrupt
request no.
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
UART/SIO ch. 0
IRQ04
ILR1
L04
FFF2H
FFF3H
UART/SIO ch. 1*
IRQ09
ILR2
L09
FFE8H
FFE9H
UART/SIO ch. 2
IRQ07
ILR1
L07
FFECH
FFEDH
ch.: Channel
*: UART/SIO ch. 1 uses the same interrupt request number and vector table addresses as 8/16-bit PPG
ch. 1 (lower).
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
MB95410H/470H Series
Operations of UART/SIO and Setting Procedure
Example
22.7
The UART/SIO has a serial communication function (operation mode 0, 1).
■ Operation of UART/SIO
● Operation mode
Two operation modes are available in the UART/SIO. Clock synchronous mode (SIO) or clock
asynchronous mode (UART) can be selected (see Table 22.7-1).
Table 22.7-1 Operation Modes of UART/SIO
Data length
Operation mode
No parity
With parity
5
6
6
7
7
8
8
9
5
6
6
7
7
8
8
9
0
1
Synchronization
mode
Length of stop bit
Asynchronous
1 bit or 2 bits
Synchronous
1 bit or 2 bits
■ Setting Procedure Example
Below is an example of procedure for setting the UART/SIO.
● Initial settings
1) Set the port input. (DDR1, DDR9, DDRG)
2) Set the interrupt level. (ILR1, ILR2)
3) Set the prescaler. (PSSR0)
4) Set the baud rate. (BRSR0)
5) Select the clock. (SMC10:CKS)
6) Set the operation mode. (SMC10:MD)
7) Enable/disable the serial clock output. (SMC20:SCKE)
8) Enable reception. (SMC20:RXE = 1)
9) Enable interrupts. (SMC20:RIE = 1)
● Interrupt processing
Read receive data. (RDR0)
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
MB95410H/470H Series
22.7.1
Operations in Operation Mode 0
Operation mode 0 operates as clock asynchronous mode (UART).
■ Operating Description of UART/SIO Operation Mode 0
Clock asynchronous mode (UART) is selected when the MD bit in the UART/SIO serial mode
control register 1 (SMC10) is set to "0".
● Baud rate
The serial clock is selected by the CKS bit in the SMC10 register. Be sure to select the
dedicated baud rate generator at this time.
The baud rate is equivalent to the output clock frequency of the dedicated baud rate generator,
divided by four. The UART can perform communication within the range from -2% to +2% of
the selected baud rate.
The baud rate generated by the dedicated baud rate generator is obtained from the equation
illustrated below. (For information about the dedicated baud rate generator, see "CHAPTER 23
UART/SIO DEDICATED BAUD RATE GENERATOR".)
Figure 22.7-1 Baud Rate Calculation when Using Dedicated Baud Rate Generator
Machine clock (MCLK)
Baud rate value =
[bps]
4×
1
2
4
8
2
:
255
×
UART baud rate setting register
(BRSR0)
Baud rate setting (BRS7 to BRS0)
UART prescaler select register (PSSR0)
Prescaler select (PSS1, PSS0)
Table 22.7-2 Sample Asynchronous Transfer Rates Based on Dedicated Baud Rate Generator
(Clock Gear = 4/FCH, Machine Clock = 10 MHz)
Dedicated baud rate generator setting
UART internal Total division ratio
Baud rate
division
(PSS × BRS × 4) (10 MHz / Total division ratio)
Prescaler select
PSS[1:0]
Baud rate counter setting
BRS[7:0]
1 (Setting value: 0,0)
20
4
80
125000
1 (Setting value: 0,0)
22
4
88
113636
1 (Setting value: 0,0)
44
4
176
56818
1 (Setting value: 0,0)
87
4
348
28736
1 (Setting value: 0,0)
130
4
520
19231
2 (Setting value: 0,1)
130
4
1040
9615
4 (Setting value: 1,0)
130
4
2080
4808
8 (Setting value: 1,1)
130
4
4160
2404
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22.7 Operations of UART/SIO and Setting Procedure
Example
The baud rate in clock asynchronous mode can be set in the following range.
MB95410H/470H Series
Table 22.7-3 Baud Rate Setting Range in Clock Asynchronous Mode
PSS[1:0]
BRS[7:0]
"00B" to "11B"
02H (2) to FFH (255)
● Transfer data format
UART can treat data only in NRZ (Non-Return-to-Zero) format. Figure 22.7-2 shows the data
format.
The character bit length can be selected from among 5 to 8 bits depending on the CBL1 and
CBL0 settings.
The stop bit length can be set to 1 or 2 bits depending on the SBL setting.
PEN and TDP can be used to enable/disable parity and to select parity polarity.
As shown in Figure 22.7-2, the transfer data always starts from the start bit ("L" level) and ends
with the stop bit ("H" level) by performing the specified data bit length transfer with MSB or
LSB first ("LSB first" or "MSB first" can be selected by the BDS bit). It becomes "H" level at
the idle state.
Figure 22.7-2 Transfer Data Format
ST
D0
D1
D2
D3
D4
SP
ST
D0
D1
D2
D3
D4
SP
SP
ST
D0
D1
D2
D3
D4
P
SP
ST
D0
D1
D2
D3
D4
P
SP
SP
Without P
5-bit data
With P
...
6-bit and 8-bit data is also the same.
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
Without P
SP
8-bit data
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
With P
SP
ST : Start bit
SP : Stop bit
P : Parity bit
D0 to D7: Data. The sequence can be selected from "LSB first" or "MSB first" by the
direction control register (BDS bit)
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
Receiving operation in asynchronous clock mode (UART)
MB95410H/470H Series
●
Use UART/SIO serial mode control register 1 (SMC10) to select the serial data direction
(endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.
Reception remains performed as long as the reception operation enable bit (RXE) contains "1".
Upon detection of a start bit in receive data with the reception operation enable bit (RXE) set to
"1", one frame of data is received according to the data format set in UART/SIO serial control
register 1 (SMC10).
When the reception of one frame of data has been completed, the received data is transferred to
the UART/SIO serial input data register (RDR0) and the next frame of serial data can be
received.
When the UART/SIO serial input data register (RDR0) stores data, the receive data register full
(RDRF) bit is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1"
when the reception interrupt enable bit (RIE) contains "1".
Received data is read from the UART/SIO serial input data register (RDR0) after each error
flag (PER, OVE, FER) in the UART/SIO serial status register is checked.
When received data is read from the UART/SIO serial input data register (RDR0), the receive
data register full (RDRF) bit is cleared to "0".
Note that modifying UART/SIO serial mode control register 1 (SMC10) during reception may
result in unpredictable operation.
If the RXE bit is set to "0" during reception, the reception is immediately disabled and
initialization will be performed. The data received up to that point will not be transferred to the
serial input data register.
Figure 22.7-3 Receiving Operation in Asynchronous Clock Mode
RXE
UI0
St
D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St
D0 D1 D2
RDR0
read
RDRF
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22.7 Operations of UART/SIO and Setting Procedure
Example
● Reception error in asynchronous clock mode (UART)
MB95410H/470H Series
If any of the following three error flags (PER, FER, OVE) has been set, receive data is not
transferred to the UART/SIO serial input data register (RDR0) and the receive data register full
(RDRF) bit is not set to "1" either.
1. Parity error (PER)
The parity error (PER) bit is set to "1" if the parity bit in received serial data does not match
the parity polarity bit (TDP) when the parity control bit (PEN) contains "1".
2. Framing error (FER)
The framing error (FER) bit is set to "1" if "1" is not detected at the position of the first stop
bit in serial data received in the set character bit length (CBL) under parity control (PEN).
Note that the stop bit is not checked if it appears at the second bit or later.
3. Overrun error (OVE)
Upon completion of reception of serial data, the overrun error (OVE) bit is set to "1" if the
reception of the next data is performed before the previous receive data is read.
Each flag is set at the position of the first stop bit.
Figure 22.7-4 Setting Timing for Receiving Errors
UI0
D5
D6
D7
P
SP
SP
PER
OVE
FER
Reception
interrupt
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
Start bit detection and confirmation of receive data during reception
MB95410H/470H Series
●
The start bit is detected by a falling of the serial input followed by a succession of three "L"
levels after the serial data input is sampled according to the clock (BRCLK) signal provided by
the dedicated baud rate generator with the reception operation enable bit (RXE) set to "1".
When the first "H, L, L, L" train is detected in a BRCLK sample, therefore, the current bit is
regarded as the start bit.
The frequency-quartered circuit is activated upon detection of the start bit and serial data is
input to the reception shift register at intervals of four periods of BRCLK.
When data is received, sampling is performed at three points of the baud rate clock (BRCLK)
and data sampling clock (DSCLK) and received data is confirmed on a majority basis when
two bits out of three match.
Figure 22.7-5 Start Bit Detection and Serial Data Input
RXE
Start bit
Serial data input
D1
D0
(UI0)
Baud rate clock
(BRCLK)
H
L
L
L
L
Start bit detection
Counter divided by 4
X
0
1
2
3
0
1
2
3
Data sampling clock
(DSCLK)
Sampling at three points to determine "0" or "1" on a majority basis
when two bits out of three match
Reception shift register
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
● Transmission in asynchronous clock mode
MB95410H/470H Series
Use UART/SIO serial mode control register 1 (SMC10) to select the serial data direction
(endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.
Either of the following two procedures can be used to initiate the transmission process:
• Set the transmission operation enable bit (TXE) to "1", and then write transmit data to the
serial output data register to start transmission.
• Write transmit data to the UART/SIO serial output data register, and then set the
transmission operation enable bit (TXE) to "1" to start transmission.
Transmit data is written to the UART/SIO serial output data register (TDR0) after it is checked
that the transmit data register empty (TDRE) bit set to "1".
When the transmit data is written to the UART/SIO serial output data register (TDR0), the
transmit data register empty (TDRE) bit is cleared to "0".
The transmit data is transferred from the UART/SIO serial output data register (TDR0) to the
transmission shift register, and the transmit data register empty (TDRE) is set to "1".
When the transmission interrupt enable bit (TIE) contains "1", a transmission interrupt occurs
if the transmit data register empty (TDRE) bit is set to "1". This allows the next piece of
transmit data to be written to the UART/SIO serial output data register (TDR0) by interrupt
handling.
To detect the completion of serial transmission by transmission interrupt, set the transmission
completion interrupt enable bits as follows: TEIE = 0, TCIE = 1. Upon completion of
transmission, the transmission completion flag (TCPL) is set to 1 and a transmission interrupt
occurs.
Both the transmission completion flag (TCPL) and the transmission data register empty flag
(TDRE), when transmitting data consecutively, are set at the position which the transmission of
the last bit was completed (it varies depending on the data length, parity enable, or stop bit
length setting), as shown in Figure 22.7-6 below.
Note that modifying UART/SIO serial mode control register 1 (SMC10) during transmission
may result in unpredictable operation.
Figure 22.7-6 Transmission in Asynchronous Clock Mode (UART)
UO0
D5
D6
D7
P
SP
SP
TCPL
TDRE
Transmission
interrupt
When the STOP bit length is set to 1 bit
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
The TDRE flag is set at the point indicated in the following figure if the preceding piece of
transmit data does not exist in the transmission shift register.
MB95410H/470H Series
Figure 22.7-7 Setting Timing 1 for Transmit Data Register Empty Flag (TDRE) (When TXE is "1")
"1"
TXE
Writing of
transmit data
UO0
D0
D1
D2
D3
TDRE
Transmission
interrupt
Data transfer from UART/SIO serial output data register (TDR0) toransmission
t
shift register is performed in one machine clock (MCLK) cycle.
Figure 22.7-8 Setting Timing 2 for Transmit Data Register Empty Flag (TDRE)
(When TXE Is Switched from "0" to "1")
TXE
Writing of
transmit data
UO0
D0
D1
D2
D3
TDRE
Transmission
interrupt
● Concurrent transmission and reception
In asynchronous clock mode (UART), transmission and reception can be performed
independently. Therefore, transmission and reception can be performed at the same time or
even with transmitting and receiving frames overlapping each other in shifted phases.
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
22.7.2
MB95410H/470H Series
Operations in Operation Mode 1
Operation mode 1 operates in synchronous clock mode.
■ Operating Description of UART/SIO Operation Mode 1
Setting the MD bit in UART/SIO serial mode control register 1 (SMC10) to "1" selects
synchronous clock mode (SIO).
The character bit length in synchronous clock mode (SIO) is variable between 5 and 8 bits.
Note, however, that parity is disabled and no stop bit is used.
The serial clock is selected by the CKS bit in the SMC10 register. Select the dedicated baud
rate generator or external clock. The SIO performs shift operation using the selected serial
clock as a shift clock.
To input the external clock signal, set the SCKE bit to "0".
To output the dedicated baud rate generator output as a shift clock signal, set the SCKE bit to
"1". The serial clock signal is obtained by dividing clock by two, which is supplied by the
dedicated baud rate generator. The baud rate in the SIO mode can be set in the following range.
(For more information about the dedicated baud rate generator, also see "CHAPTER 23
UART/SIO DEDICATED BAUD RATE GENERATOR".)
Table 22.7-4 Baud Rate Setting Range in SIO Mode
PSS[1:0]
BRS[7:0]
"00B" to "11B"
01H(1) to FFH(255), 00H(256)
(The highest and lowest baud rate settings are 01H and 00H, respectively.)
The baud rate applied when the external clock or dedicated baud rate generator is used is
obtained from the corresponding equation illustrated below.
Figure 22.7-9 Calculating Baud Rate Based on External Clock
1
Baud rate value =
[bps]
External clock*
More than 4 machine clock
*: External clock
More than 4 machine clock
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
Figure 22.7-10 Baud Rate Calculation Formula for Using Dedicated Baud Rate Generator
MB95410H/470H Series
Machine clock (MCLK)
[bps]
Baud rate value =
2×
1
2
4
8
UART prescaler select register(PSSR0)
Prescaler select (PSS1, PSS0)
×
1
:
256
UART baud rate setting register
(BRSR0)
Baud rate setting (BRS7 to BRS0)
● Serial clock
The serial clock signal is outputted under control of the output for transmit data. When only
reception is performed, therefore, set transmission control (TXE = 1) to write dummy transmit
data to the UART/SIO serial output register.MB95410H/470H Series
Refer to the data sheet of the MB95410H/470H Series for the UCK0 clock value.
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
MB95410H/470H Series
● Reception in UART/SIO operation mode 1
For reception in operation mode 1, each register is used as follows.
Figure 22.7-11 Registers Used for Reception in Operation Mode 1
SMC10 (UART/SIO serial mode control register 1)
bit7
BDS
bit6
PEN
×
bit5
TDP
×
bit4
SBL
×
bit3
CBL1
bit2
CBL0
bit1
CKS
bit0
MD
1
bit4
RXE
bit3
TXE
bit2
RIE
bit1
TCIE
×
bit0
TEIE
×
bit4
OVE
bit3
FER
×
bit2
RDRF
bit1
TCPL
×
bit0
TDRE
×
bit4
TD4
×
bit3
TD3
×
bit2
TD2
×
bit1
TD1
×
bit0
TD0
×
bit4
RD4
bit3
RD3
bit2
RD2
bit1
RD1
bit0
RD0
SMC20 (UART/SIO serial mode control register 2)
bit7
SCKE
bit6
TXOE
0
bit5
RERC
SSR0 (UART/SIO serial status register)
bit7
×
bit6
×
bit5
PER
×
TDR0 (UART/SIO serial output data register)
bit7
TD7
×
bit6
TD6
×
bit5
TD5
×
RDR0 (UART/SIO serial input data register)
bit7
RD7
bit6
RD6
bit5
RD5
: Used bit
× : Unused bit
1 : Set "1"
0 : Set "0"
The reception depends on whether the serial clock has been set to external or internal clock.
<When external clock is enabled>
When the reception operation enable bit (RXE) contains "1", serial data is received always
at the rising edge of the external clock signal.
<When internal clock is enabled>
The serial clock signal is outputted in accordance with transmission. Therefore,
transmission must be performed even when only performing reception. The following two
procedures can be used.
• Set the transmission operation enable bit (TXE) to "1", then write transmit data to the
UART/SIO serial output data register to generate the serial clock signal and start reception.
• Write transmit data to the UART/SIO serial output data register, then set the transmission
operation enable bit (TXE) to "1" to generate the serial clock signal and start reception.
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
When 5 to 8-bit serial data is received by the reception shift register, the received data is
transferred to the UART/SIO serial input data register (RDR0) and the next piece of serial data
can be received.
MB95410H/470H Series
When the UART/SIO serial input data register stores data, the receive data register full
(RDRF) bit is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1"
when the reception interrupt enable bit (RIE) contains "1".
To read received data, read it from the UART/SIO serial input data register after checking the
error flag (OVE) in the UART/SIO serial status register.
When received data is read from the UART/SIO serial input data register (RDR0), the receive
data register full (RDRF) bit is cleared to "0".
Figure 22.7-12 8-bit Reception of Synchronous Clock Mode
UCK0
UI0
D0 D1 D2 D3 D4 D5 D6 D7
Read to RDR0
RDRF
Interrupt to interrupt controller
Operation when reception error occurs
When an overrun error (OVE) exists, received data is not transferred to the UART/SIO
serial input data register (RDR0).
Overrun error (OVE)
Upon completion of reception for serial data, the overrun error (OVE) bit is set to "1" if the
receive data register full (RDRF) bit has been set to "1" by the reception for the preceding
piece of data.
Figure 22.7-13 Overrun Error
UCK0
UI0
...
...
...
D0 D1 ... D6 D7
D0 D1 ... D6 D7
D0 D1 ... D6 D7
Read to
RDR0
RDRF
OVE
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
● Transmission in UART/SIO operation mode 1
MB95410H/470H Series
For transmission in operation mode 1, each register is used as follows.
Figure 22.7-14 Registers Used for Transmission in Operation Mode 1
SMC10 (UART/SIO serial mode control register 1)
bit7
BDS
bit6
PEN
×
bit5
TDP
×
bit4
SBL
×
bit3
CBL1
bit2
CBL0
bit1
CKS
bit0
MD
1
bit4
RXE
bit3
TXE
bit2
RIE
bit1
TCIE
×
bit0
TEIE
×
bit4
OVE
bit3
FER
×
bit2
RDRF
bit1
TCPL
×
bit0
TDRE
×
bit4
TD4
×
bit3
TD3
×
bit2
TD2
×
bit1
TD1
×
bit0
TD0
×
bit4
RD4
bit3
RD3
bit2
RD2
bit1
RD1
bit0
RD0
SMC20 (UART/SIO serial mode control register 2)
bit7
SCKE
bit6
TXOE
0
bit5
RERC
SSR0 (UART/SIO serial status register)
bit7
×
bit6
×
bit5
PER
×
TDR0 (UART/SIO serial output data register)
bit7
TD7
×
bit6
TD6
×
bit5
TD5
×
RDR0 (UART/SIO serial input data register)
bit7
RD7
bit6
RD6
bit5
RD5
: Used bit
× : Unused bit
1 : Set "1"
0 : Set "0"
The following two procedures can be used to initiate the transmission process:
• Set the transmission operation enable bit (TXE) to "1", then write transmit data to the
UART/SIO serial output data register to start transmission.
• Write transmit data to the UART/SIO serial output data register, then set the transmission
operation enable bit (TXE) to "1" to start transmission.
Transmit data is written to the UART/SIO serial output data register (TDR0) after it is checked
that the transmit data register empty (TDRE) bit is set to "1".
When the transmit data is written to the UART/SIO serial output data register (TDR0), the
transmit data register empty (TDRE) bit is cleared to "0".
When serial transmission is started after transmit data is transferred from the UART/SIO serial
output data register (TDR0) to the transmission shift register, the transmit data register empty
(TDRE) bit is set to "1".
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CHAPTER 22 UART/SIO
22.7 Operations of UART/SIO and Setting Procedure
Example
When the use of the external clock signal has been set, serial data transmission starts at the fall
of the first serial clock signal after the transmission process is started.
MB95410H/470H Series
A transmission completion interrupt occurs the moment the transmit data register empty
(TDRE) bit is set to "1" when the transmission interrupt enable bit (TIE) contains "1". At this
time, the next piece of transmit data can be written to the UART/SIO serial output data register
(TDR0). Serial transmission can be continued with the transmission operation enable bit (TXE)
set to "1".
To use a transmission completion interrupt to detect the completion of serial transmission,
enable transmission completion interrupt output this way: TEIE = 0, TCIE = 1. Upon
completion of transmission, the transmission completion flag (TCPL) is set to "1" and a
transmission completion interrupt occurs.
Figure 22.7-15 8-bit Transmission in Synchronous Clock Mode
Writing
to TDR0
UCK0
UI0
D0 D1 D2 D3 D4 D5 D6 D7
TDRE
TCPL
Interrupt
to interrupt
controller
After falling of UCK0 Interrupt
After last 1-bit cycle
when external clock to interrupt when internal clock
is enabled.
controller is enabled.
● Concurrent transmission and reception
<When external clock is enabled>
Transmission and reception can be performed independently of each other. Transmission
and reception can therefore be performed at the same time or even when their phases are
shifted from each other and overlapping.
<When internal clock is enabled>
As the transmitting side generates a serial clock, reception is influenced.
If transmission stops during reception, the receiving side is suspended. It resumes reception
when the transmitting side is restarted.
• See "22.4 Pins of UART/SIO" for the operation with serial clock output and the operation
with serial clock input.
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CHAPTER 22 UART/SIO
22.8 Sample Settings for UART/SIO
22.8
MB95410H/470H Series
Sample Settings for UART/SIO
This section provides sample settings for the UART/SIO.
■ Sample Settings
● How to select the operation mode
The operation mode selection bit (SMC10:MD) is used.
Operating mode
Operating mode select bit (MD)
Mode 0 Asynchronous clock mode (UART)
Set the bit to "0".
Mode 1 Synchronous clock mode (SIO)
Set the bit to "1".
● Operating clock types and selection method
The clock select bit (SMC10:CKS) is used.
Operation
Clock select bit (CKS)
To select the dedicated baud rate
generator
Set the bit to "0".
To select the external clock
Set the bit to "1".
● How to use the UCK0, UI0, or UO0 pin
The following settings are used.
UART
To set the UCK0 pin as an input pin
DDR1:P14 = 0
SMC20:SCKE = 0
To set the UCK0 pin as an output pin
SMC20:SCKE = 1
To use the UI0 pin
DDR1:P10 = 0
To use the UO0 pin
SMC20:TXOE = 1
● How to enable/stop UART operation
The reception operation enable bit (SMC20:RXE) is used.
522
Operation
Reception operation enable bit (RXE)
To disable (stop) reception
Set the bit to "0".
To enable reception
Set the bit to "1".
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CHAPTER 22 UART/SIO
22.8 Sample Settings for UART/SIO
MB95410H/470H Series
The transmission operation control bit (SMC20:TXE) is used.
Operation
Transmission operation control bit (TXE)
To disable (stop) transmission
Set the bit to "0".
To enable transmission
Set the bit to "1".
● How to set parity
The parity control (SMC10:PEN) and parity polarity (SMC10:TDP) bits are used.
Operation
Parity control
(SMC10:PEN)
Parity polarity
(SMC10:TDP)
To select no parity
Set the bit to "0"
-
To select even parity
Set the bit to "1"
Set the bit to "0".
To select odd parity
Set the bit to "1"
Set the bit to "1".
● How to set the data length
The character bit length control bits (SMC10:CBL[1:0]) are used.
Operation
Character bit length control bits (CBL[1:0])
To select 5-bit length
Set the bits to "00B".
To select 6-bit length
Set the bits to "01B".
To select 7-bit length
Set the bits to "10B".
To select 8-bit length
Set the bits to "11B".
● How to select the STOP bit length
The STOP bit length control bit (SMC10:SBL) is used.
Operation
STOP bit length control (SBL)
To set the STOP bit length to 1 bit
Set the bit to "0".
To set the STOP bit length to 2
bits
Set the bit to "1".
● How to clear error flags
The reception error flag clear bit (SMC20:RERC) is used.
MN702-00005-2v0-E
Operation
Reception error flag clear bit (RERC)
To clear error flags
(PER, OVE, FER)
Set the bit to "0".
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CHAPTER 22 UART/SIO
22.8 Sample Settings for UART/SIO
MB95410H/470H Series
● How to set the transfer direction
The serial data direction control bit (SMC10:BDS) is used.
LSB or MSB can be selected for the transfer direction in any operation mode.
Operation
Serial data direction control (BDS)
To select LSB transfer
(from least significant bit)
Set the bit to "0".
To select MSB transfer
(from most significant bit)
Set the bit to "1".
● How to clear the reception completion flag
The following setup is performed.
Operation
Method
To clear the reception completion
flag
Read from the RDR0 register.
When the first read from the RDR0 register is performed, reception starts.
● How to clear the transmission buffer empty flag
The following operation is performed.
Operation
Method
To clear the transmission buffer
empty flag
Write to the TDR0 register.
When the first write to TDR0 register is performed, transmission starts.
● How to set the baud rate
See "22.7.1 Operations in Operation Mode 0".
● Interrupt-related registers
The interrupt level setting registers shown in the following table are used to set the interrupt
level.
524
Interrupt level setting register
Interrupt vector
ch. 0
Interrupt level setting register (ILR1)
Address: 0007AH
#4
Address: 0FFF2H
ch. 1
Interrupt level setting register (ILR2)
Address: 0007BH
#9
Address: 0FFE8H
ch. 2
Interrupt level setting register (ILR1)
Address: 0007AH
#7
Address: 0FFECH
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CHAPTER 22 UART/SIO
22.8 Sample Settings for UART/SIO
MB95410H/470H Series
● How to enable/disable/clear interrupts
Interrupt request enable flag, interrupt request flag
The interrupt request enable bits (SMC20:RIE, SMC20:TCIE, SMC20:TEIE) are used to
enable interrupts.
UART reception
Reception interrupt
enable bit (RIE)
UART transmission
Transmission completion
interrupt enable bit (TCIE)
To disable interrupt
requests
Select "0".
To enable interrupt
requests
Select "1".
Transmission data register
empty interrupt enable bit
(TEIE)
Interrupt requests are cleared in the following setup procedure.
UART reception
To clear an
interrupt request
Read from UART/SIO serial input register (RDR0) to
clear reception data register full bit (RDRF).
Write "0" to error flag clear bit (RERC) to clear error
flags (PER, OVE, FER) to "0".
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UART transmission
Write data to UART/SIO serial
output data register (TDR0) to
clear transmission data register
empty bit (TDRE) to "0".
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22.8 Sample Settings for UART/SIO
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CHAPTER 23
UART/SIO DEDICATED
BAUD RATE GENERATOR
This chapter describes the functions and
operations of the dedicated baud rate generator
of UART/SIO.
23.1 Overview of UART/SIO Dedicated Baud Rate
Generator
23.2 Channels of UART/SIO Dedicated Baud Rate
Generator
23.3 Registers of UART/SIO Dedicated Baud Rate
Generator
23.4 Operations of UART/SIO Dedicated Baud Rate
Generator
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.1 Overview of UART/SIO Dedicated Baud Rate
Generator
23.1
MB95410H/470H Series
Overview of UART/SIO Dedicated Baud Rate
Generator
The UART/SIO dedicated baud rate generator generates the baud rate for the
UART/SIO.
The generator consists of the UART/SIO dedicated baud rate generator
prescaler select register (PSSR) and UART/SIO dedicated baud rate generator
baud rate setting register (BRSR).
■ Block Diagram of UART/SIO Dedicated Baud Rate Generator
Figure 23.1-1 Block Diagram of UART/SIO Dedicated Baud Rate Generator
Baud rate generator
PSS1,PSS0
MCLK
(Machine clock)
BRS7 to BRS0
CLK
MCLK/2
Prescaler
UART/SIO
MCLK/4
8-bit
down-counter
BRCLK
1/4
MCLK/8
■ Input Clock
The UART/SIO dedicated baud rate generator uses the output clock from the prescaler or the
machine clock as its input clock.
■ Output Clock
The UART/SIO dedicated baud rate generator supplies its clock to the UART/SIO.
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.2 Channels of UART/SIO Dedicated Baud Rate
Generator
MB95410H/470H Series
23.2
Channels of UART/SIO Dedicated Baud Rate
Generator
This section describes the channels of the UART/SIO dedicated baud rate
generator.
■ Channels of UART/SIO Dedicated Baud Rate Generator
The MB95410H/470H Series has 3 channels of UART/SIO dedicated baud rate generator.
The following table shows the correspondence the channel and registers.
Table 23.2-1 Registers of Dedicated Baud Rate Generator
Channel
Register
abbreviation
Corresponding register (Name in this manual)
PSSR0
UART/SIO dedicated baud rate generator prescaler select register ch. 0
BRSR0
UART/SIO dedicated baud rate generator baud rate setting register ch. 0
PSSR1
UART/SIO dedicated baud rate generator prescaler select register ch. 1
BRSR1
UART/SIO dedicated baud rate generator baud rate setting register ch. 1
PSSR2
UART/SIO dedicated baud rate generator prescaler select register ch. 2
BRSR2
UART/SIO dedicated baud rate generator baud rate setting register ch. 2
0
1
2
ch.: Channel
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.3 Registers of UART/SIO Dedicated Baud Rate
Generator
23.3
MB95410H/470H Series
Registers of UART/SIO Dedicated Baud Rate
Generator
The registers of the UART/SIO dedicated baud rate generator are namely the
UART/SIO dedicated baud rate generator prescaler select register (PSSR) and
UART/SIO dedicated baud rate generator baud rate setting register (BRSR).
■ Registers of UART/SIO Dedicated Baud Rate Generator
Figure 23.3-1 Registers of UART/SIO Dedicated Baud Rate Generator
UART/SIO dedicated baud rate generator prescaler select register (PSSR)
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
PSSR0 0FA8H
BRGE PSS1
PSSR1 0FAAH R0/WX R0/WX R0/WX R0/WX R0/WX R/W
R/W
PSSR2 0FACH
bit0
PSS0
R/W
Initial value
00000000B
UART/SIO dedicated baud rate generator baud rate setting register (BRSR)
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
BRSR0 0FA9H BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1
BRSR1 0FABH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRSR2 0FADH
bit0
BRS0
R/W
Initial value
00000000B
R/W
R0/WX
-
: Readable/writable (The read value is the same as the write value.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
The following sections describe only UART/SIO ch. 0.
Ch. 1 and ch. 2 have the same configuration as ch. 0.
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.3 Registers of UART/SIO Dedicated Baud Rate
Generator
MB95410H/470H Series
23.3.1
UART/SIO Dedicated Baud Rate Generator
Prescaler Select Register (PSSR0)
The UART/SIO dedicated baud rate generator prescaler select register (PSSR0)
controls the output of the baud rate clock and the prescaler.
■ UART/SIO Dedicated Baud Rate Generator Prescaler Select Register (PSSR0)
Figure 23.3-2 UART/SIO Dedicated Baud Rate Generator Prescaler Select Register (PSSR0)
bit7
bit6
bit5
bit4
bit3
-
-
-
-
-
Address
0FA8H
bit2
R/W
Initial value
00000000B
R/W
Prescaler select bits
PSS1 PSS0
0
0
1/1
0
1
1/2
1
0
1/4
1
1
1/8
Baud rate clock output enable bit
BRGE
:
:
:
:
bit0
BRGE PSS1 PSS0
R0/WX R0/WX R0/WX R0/WX R0/WX R/W
R/W
R0/WX
-
bit1
0
Disables baud rate output.
1
Enables baud rate output.
Readable/writable (The read value is the same as the write value.)
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
Table 23.3-1 Functions of Bits in UART/SIO Dedicated Baud Rate Generator Prescaler Select
Register (PSSR0)
Bit name
bit7
to
bit3
Undefined bits
bit2
BRGE:
Baud rate clock output
enable
bit1,
bit0
Function
Their read values are always "0". Writing values to these bits has no effect on operation.
PSS1, PSS0:
Prescaler select bits
MN702-00005-2v0-E
• This bit enables the output of the baud rate clock "BRCLK".
Writing "0": Stops the output of "BRCLK".
Writing "1": Loads BRS[7:0] to the 8-bit down-counter and outputs "BRCLK", which is
supplied to the UART/SIO.
PSS1
PSS0
Prescaler select
0
0
1/1
0
1
1/2
1
0
1/4
1
1
1/8
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.3 Registers of UART/SIO Dedicated Baud Rate
Generator
23.3.2
MB95410H/470H Series
UART/SIO Dedicated Baud Rate Generator Baud
Rate Setting Register (BRSR0)
The UART/SIO dedicated baud rate generator dedicated baud rate generator
baud rate setting register (BRSR0) controls the baud rate settings.
■ UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register
(BRSR0)
Figure 23.3-3 UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register (BRSR0)
Address bit7
0FA9H BRS7
R/W
R/W
bit6
BRS6
R/W
bit5
BRS5
R/W
bit4
BRS4
R/W
bit3
BRS3
R/W
bit2
BRS2
R/W
bit1
BRS1
R/W
bit0
BRS0
R/W
Initial value
00000000B
: Readable/writable (The read value is the same as the write value.)
This register sets the cycle of the 8-bit down-counter and can be used to set any baud rate
clock. Write to the register when the UART is stopped.
Do not set BRS[7:0] to "00H" or "01H" in clock asynchronous mode.
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CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
23.4 Operations of UART/SIO Dedicated Baud Rate
Generator
MB95410H/470H Series
23.4
Operations of UART/SIO Dedicated Baud Rate
Generator
The UART/SIO dedicated baud rate generator serves as the baud rate generator
for asynchronous clock mode.
■ Baud Rate Setting
The SMC10 register (CKS bit) of the UART/SIO is used to select the serial clock. This selects
the UART/SIO dedicated baud rate generator.
In asynchronous clock mode, the shift clock that is selected by the CKS bit and divided by four
is used and transfers can be performed within the range from -2% to +2%. The baud rate
calculation formula for the UART/SIO dedicated baud rate generator is shown below.
Figure 23.4-1 Baud Rate Calculation Formula when UART/SIO Dedicated Baud Rate Generator
Is Used
Machine clock (MCLK)
Baud rate =
[bps]
4×
1
2
4
8
×
2
:
255
UART dedicated baud rate generator
baud rate setting register (BRSR0)
Baud rate setting (BRS7 to BRS0)
UART dedicated baud rate generator
prescaler select register (PSSR0)
Prescaler select (PSS1, PSS0)
Table 23.4-1 Sample Asynchronous Transfer Rates by Baud Rate Generator
(Machine Clock = 10 MHz)
UART/SIO dedicated baud rate generator
setting
Prescaler select
PSS[1:0]
UART internal Total division ratio
Baud rate
division
(PSS
×
BRS
×
4)
(10
MHz/Total
division ratio)
Baud rate counter setting
BRS[7:0]
1 (Setting value: 0, 0)
20
4
80
125000
1 (Setting value: 0, 0)
22
4
88
113636
1 (Setting value: 0, 0)
44
4
176
56818
1 (Setting value: 0, 0)
87
4
348
28736
1 (Setting value: 0, 0)
130
4
520
19231
2 (Setting value: 0, 1)
130
4
1040
9615
4 (Setting value: 1, 0)
130
4
2080
4808
8 (Setting value: 1, 1)
130
4
4160
2404
The baud rate can be set in UART mode within the following range.
Table 23.4-2 Permissible Baud Rate Range in UART Mode
MN702-00005-2v0-E
PSS[1:0]
BRS[7:0]
"00B" to "11B"
02H (2) to FFH (255)
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23.4 Operations of UART/SIO Dedicated Baud Rate
Generator
MB95410H/470H Series
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CHAPTER 24
I 2C
This chapter describes functions and
operations of the I2C.
24.1 Overview of I2C
24.2 I2C Configuration
24.3 I2C Channel
24.4 Pins of I2C Bus Interface
24.5 Registers of I2C
24.6 I2C Interrupts
24.7 Operations of I2C and Setting Procedure Example
24.8 Notes on Using I2C Interface
24.9 Sample Settings for I2C
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CHAPTER 24 I2C
24.1 Overview of I2C
24.1
MB95410H/470H Series
Overview of I2C
The I2C interface provides the functions of transmission and reception in
master and slave modes, detection of arbitration lost, detection of slave
address and general call address, generation and detection of start and stop
conditions, bus error detection, and MCU standby wakeup.
■ I2C Functions
The I2C interface is a two-wire, bi-directional bus consisting of a serial data line (SDA) and
serial clock line (SCL). The devices connected to the bus via these two wires can exchange
data, and each device can operate as a sender or receiver in accordance with their respective
functions based on the unique address assigned to each device. Furthermore, the interface
establishes a master/slave relationship between devices.
Also, the I2C interface can connect multiple devices provided the bus capacitance does not
exceed an upper limit of 400 pF. The I2C interface is a true multi-master bus with collision
detection and a communication control protocol that prevent loss of data even if more than one
master attempts to start a data transfer at the same time.
The communication control protocol ensures that only one master is able to take control of the
bus at a time, even if multiple masters attempt to take control of the bus simultaneously,
without messages being lost or data being altered. Multi-master means that more than one
master can attempt to take control of the bus at the same time without causing messages to be
lost.
Also, the I2C interface includes a function to wake up the MCU from standby mode.
Figure 24.1-1 I2C Interface Configuration
Microcontroller
A
Static RAM/
E2PROM
LCD driver
SDA
SCL
Gate array
536
A/D converter
FUJITSU SEMICONDUCTOR LIMITED
Microcontroller
B
MN702-00005-2v0-E
MB95410H/470H Series
24.2
CHAPTER 24 I2C
24.2 I2C Configuration
I2C Configuration
I2C consists of the following blocks:
• Clock selector
• Clock divider
• Shift clock generator
• Start/stop condition generation circuit
• Start/stop condition detection circuit
• Arbitration lost detection circuit
• Slave address comparison circuit
• IBSR register
• IBCR registers (IBCR00, IBCR10)
• ICCR0 register
• IAAR0 register
• IDDR0 register
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CHAPTER 24 I2C
24.2 I2C Configuration
MB95410H/470H Series
■ I2C Block Diagram
Figure 24.2-1 I2C Block Diagram
I2C enable
ICCR0
5
EN
6
7
8
Clock selector 1
CS4
CS3
CS2
CS1
CS0
Machine clock
Clock divider 1
DMBP
Clock divider 2
4
22 38
8
98
128
256
Clock selector 2
IBSR0
BB
RSC
LRB
Sync
512
Shift clock
generator
Shift clock edge
Bus busy
Repeat start
Start/stop condition
detection circuit
Last bit
Transmit/receive
Error
TRX
First byte
FBT
BER
BEIE
Transfer interrupt
INTE
INT
2
F MC8FX internal bus
Arbitration lost detection circuit
IBCR10
SCC
MSS
DACKE
End
Start
Master
ACK enable
Start/stop condition
generation circuit
GC-ACK enable
Address ACK enable
GACKE
INT timing select
IDDR0 register
IBSR0
AAS
Slave
GCA
General
call
Slave address
comparison circuit
IAAR0 register
IBCR00
AACKX
INTS
SCL line
ALF
SDA line
ALE
SPF
Stop interrupt
SPE
WUF
WUE
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CHAPTER 24 I2C
24.2 I2C Configuration
● Clock selector, clock divider, and shift clock generator
This circuit uses the machine clock to generate the shift clock for the I2C bus.
● Start/stop condition generation circuit
When a start condition is transmitted with the bus idle (SCL and SDA at the "H" level), a
master starts communications. When SCL = "H", a start condition is generated by changing the
SDA line from "H" to "L". The master can terminate its communication by generating a stop
condition. When SCL = "H", a stop condition is generated by changing the SDA line from "L"
to "H".
● Start/stop condition detection circuit
This circuit detects a start/stop condition for data transfer.
● Arbitration lost detection circuit
This interface circuit supports multi-master systems. If two or more masters attempt to transmit
at the same time, the arbitration lost condition (if logic level "1" is sent when the SDA line
goes to the "L" level) occurs. When the arbitration lost is detected, IBCR00:ALF is set to "1"
and the master changes to a slave automatically.
● Slave address comparison circuit
The slave address comparison circuit receives the slave address after the start condition to
compare it with its own slave address. The address is seven-bit data followed by a data
direction (R/W) bit in the eighth bit position. If the received address matches the own slave
address, the comparison circuit transmits an acknowledgment.
● IBSR0 register
The IBSR0 register shows the status of the I2C interface.
● IBCR registers (IBCR00, IBCR10)
The IBCR registers are used to select the operating mode and to enable or disable interrupts,
acknowledgment, general call acknowledgment, and the function to wake up the MCU from
standby mode.
● ICCR0 register
The ICCR0 register is used to enable I2C interface operations and select the shift clock
frequency.
● IAAR0 register
The IAAR0 register is used to set the slave address.
● IDDR0 register
The IDDR0 register holds the transmit or receive shift data or address. When transmitted, the
data or address written to this register is transferred from the MSB to the bus.
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CHAPTER 24 I2C
24.2 I2C Configuration
MB95410H/470H Series
■ Input Clock
I2C uses the machine clock as the input clock (shift clock).
540
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CHAPTER 24 I2C
24.3 I2C Channel
MB95410H/470H Series
I2C Channel
24.3
This section describes the I2C channel.
■ I2C Channel
The MB95410H/470H Series has one channel of I2C.
Table 24.3-1 and Table 24.3-2 show the correspondence among the channel, pins, and registers
respectively.
Table 24.3-1 I2C Pins
Channel
0
Pin name
SCL
SDA
Pin function
I2C bus I/O
Table 24.3-2 I2C Registers
Channel
Register
abbreviation
Corresponding register (Name in this manual)
IBCR00
I2C bus control register 0
IBCR10
I2C bus control register 1
IBSR0
I2C bus status register
IDDR0
I2C data register
IAAR0
I2C address register
ICCR0
I2C clock control register
0
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CHAPTER 24 I2C
24.4 Pins of I2C Bus Interface
24.4
MB95410H/470H Series
Pins of I2C Bus Interface
This section describes the pins of the I2C bus interface and gives their block
diagram.
■ Pins of I2C Bus Interface
The pins of the I2C bus interface are the SDA and SCL pins.
● SDA pin
The SDA pin can serve as a general-purpose I/O port, external interrupt input (hysteresis
input), serial data output pin (N-ch open-drain) for 8-bit serial I/O, and I2C data I/O pin (SDA).
SDA: When I2C is enabled (ICCR0:EN = 1), the SDA pin is automatically set as a data I/O pin
to function as the SDA terminal.
To use it as an input pin, enable the I2C operation (ICCR0: EN = 1) and write "0" to the
corresponding bit in the port direction register (DDR).
● SCL pin
The SCL pin can serve as a N-ch open drain I/O port, external interrupt input (hysteresis input),
serial data input (hysteresis input) for eight-bit serial I/O, or I2C serial clock I/O pin (SCL).
SCL: When I2C is enabled (ICCR0:EN = 1), the SCL pin is automatically set as the shift clock
I/O pin to function as the SCL terminal.
To use it as an input pin, enable the I2C operation (ICCR0: EN = 1) and write "0" to the
corresponding bit in the port direction register (DDR).
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CHAPTER 24 I2C
24.4 Pins of I2C Bus Interface
MB95410H/470H Series
■ Block Diagram of Pins of I2C Bus Interface
Figure 24.4-1 Block Diagram of SCL and SDA of I2C Bus Interface
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Hysteresis
Peripheral function output
0
1
PDR read
1
PDR
pin
CMOS
OD
0
PDR write
Internal bus
Executing bit manipulation instruction
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
ILSR read
ILSR
ILSR write
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CHAPTER 24 I2C
24.5 Registers of I2C
24.5
MB95410H/470H Series
Registers of I2C
This section describes the registers of I2C.
■ Registers of I2C
Figure 24.5-1 Registers of I2C
I2C bus control register 0 (IBCR00)
Address
bit7
bit6
bit5
0060H AACKX
INTS
ALF
R/W
R/W R(RM1),W
bit4
ALE
R/W
I2C bus control register 1 (IBCR10)
Address
bit7
bit6
bit5
0061H
BER
BEIE
SCC
R(RM1),W
R/W
R0,W
bit4
MSS
R/W
I2C bus status register (IBSR0)
Address
bit7
bit6
bit5
0062H
BB
RSC
R/WX
R/WX
R0/WX
bit4
LRB
R/WX
bit3
TRX
R/WX
R(RM1),W
bit2
SPE
R/W
bit3
bit2
DACKE GACKE
R/W
R/W
bit1
WUF
R(RM1),W
bit0
WUE
R/W
Initial value
00000000B
bit0
INT
Initial value
00000000B
bit1
INTE
R/W
R(RM1),W
bit2
AAS
R/WX
bit1
GCA
R/WX
bit0
FBE
R/WX
Initial value
00000000B
I2C data register (IDDR0)
Address
bit7
bit6
0063H
D7
D6
R/W
R/W
bit5
D5
R/W
bit4
D4
R/W
bit3
D3
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
I2C address register (IAAR0)
Address
bit7
bit6
0064H
A6
R0/WX
R/W
bit5
A5
R/W
bit4
A4
R/W
bit3
A3
R/W
bit2
A2
R/W
bit1
A1
R/W
bit0
A0
R/W
Initial value
00000000B
I2C clock control register (ICCR0)
Address
bit7
bit6
bit5
0065H
DMBP
EN
R/W
R0/WX
R/W
bit4
CS4
R/W
bit3
CS3
R/W
bit2
CS2
R/W
bit1
CS1
R/W
bit0
CS0
R/W
Initial value
00000000B
R/W
R(RM1),W
R0,W
R/WX
R0/WX
-
544
bit3
SPF
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from write value. "1" is read by the readmodify-write (RMW) type of instruction.)
: Write only (Writable. The read value is "0".)
: Read only (Readable. Writing a value to this bit has no effect on operation.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
24.5.1
I2C Bus Control Registers (IBCR00, IBCR10)
The I2C bus control registers are used to select the operating mode and to
enable or disable interrupts, acknowledgment, general call acknowledgment,
and MCU standby wakeup function.
■ I2C Bus Control Register 0 (IBCR00)
Figure 24.5-2 I2C Bus Control Register 0 (IBCR00)
Address
0060H
bit7
bit6
AACKX INTS
R/W
R/W
bit5
bit4
bit3
bit2
ALF
ALE
SPF
SPE
R(RM1),W
R/W R(RM1),W R/W
bit1
bit0
Initial value
WUF
WUE
00000000B
R(RM1),W
R/W
WUE
MCU standby-mode wakeup function enable bit
0
Disables the MCU standby-mode wakeup function in stop/watch mode
1
Enables the MCU standby-mode wakeup function in stop/watch mode
MCU standby-mode wakeup interrupt request flag bit
WUF
Read
Write
0
START condition not detected
Clear
1
START condition detected
Unchanged
SPE
STOP detection interrupt enable bit
0
Disables STOP detection interrupts.
1
Enables STOP detection interrupts.
STOP detection interrupt request flag bit
SPF
Read
Write
0
STOP condition not detected
Clear
1
STOP condition detected
Unchanged
ALE
Arbitration lost interrupt enable bit
0
Disables arbitration lost interrupts.
1
Enables arbitration lost interrupts.
Arbitration lost interrupt request flag bit
ALF
Read
0
1
R/W
: Readable/writable (The read value
is the same as the write value.)
R(RM1),W : Readable/writable (The read value is different
from the write value. “1” is read by the
read-modify-write (RMW) type of instruction.)
: Initial value
MN702-00005-2v0-E
Arbitration lost not detected
Arbitration lost detected
Write
Clear
Unchanged
INTS
Timing select bit for data reception transfer completion flag (INT)
0
Sets INT in 9th SCL cycle.
1
Sets INT in 8th SCL cycle.
AACKX
Address acknowledge disable bit
0
Enables address ACK.
1
Disables address ACK.
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-1 Functions of Bits in I2C Bus Control Register 0 (IBCR00) (1 / 2)
Bit name
bit7
AACKX:
Address acknowledge
disable bit
bit6
INTS:
Timing select bit for
data reception transfer
completion flag (INT)
bit5
ALF:
Arbitration lost
interrupt request flag
bit
bit4
ALE:
Arbitration lost
interrupt enable bit
bit3
SPF:
STOP detection
interrupt request flag
bit
546
Function
This bit controls the address ACK when the first byte is transmitted.
Writing "0": Causes the address ACK to be output automatically. (The address ACK is
returned automatically if the slave address matches.)
Writing "1": Prevents the address ACK from being output.
• Write "1" to this bit in either of the following ways:
- Write "1" to the bit in master mode.
- Clear the bit to "0" after making sure that the bus busy bit is "0" (IBSR0:BB = 0).
Note:
• If AACKX = "1" and IBSR0:FBT = "0" when an IBCR10:INT bit interrupt
occurs, no address ACK is output even though the I2C address matches the
slave address. Clear the IBCR10:INT bit to "0" as an interrupt is generated upon
completion of transfer of each byte of address/data in the same way as during
addressing.
• If AACKX = "1" and IBSR0:FBT = "1" when an IBCR10:INT bit interrupt
occurs, "1" might be written to AACKX after addressing as in slave mode.
Either continue normal communication after setting AACKX to "0" again or
restart communication after disabling I2C operation (ICCR0:EN = 0).
This bit selects the timing of the transfer completion interrupt (IBCR10:INT) when data is
received. Change the bit only when IBSR0:TRX = 0 and IBSR1:FBT = 0.
Writing "0": Sets the transfer completion interrupt (IBCR10:INT) in the ninth SCL cycle.
Writing "1": Sets the transfer completion interrupt (IBCR10:INT) in the eighth SCL
cycle.
Note:
• The transfer completion interrupt (IBCR10:INT) is set always in the ninth SCL
cycle except during data reception (IBSR1:TRX = 1 or IBSR1:FBT = 1).
• If the data ACK depends on the content of the received data (such as packet
error checking used by the SM bus), control the data ACK by setting the data
ACK enable bit (IBCR10:DACKE) after writing "1" to this bit (for example,
using a previous transfer completion interrupt) to read latest received data.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received
(IBSR0:LRB must be read during the transfer completion interrupt in the ninth
SCL cycle.) If ACK is read when this bit is "1", therefore, you must write "0" to
this bit in the transfer completion interrupt in the eighth SCL cycle so that
another transfer completion interrupt will occur in the ninth SCL cycle.
This bit is used to detect when arbitration is lost.
• An arbitration lost interrupt request is generated if this bit and the IBCR00:ALE bit are
both "1".
• This bit is set to "1" in the following cases:
- When arbitration lost is detected during data/address transmission as a master
- When "1" is written to the IBCR10:MSS bit with the bus being used by another system.
However, the bit is not set when "1" is written to the MSS bit after the system returns
AACK or GACK as a slave.
• This bit is set to "0" in the following cases:
- When "0" is written to the IBCR00:ALF bit with IBSR0:BB = 0.
- When "0" is written to the IBCR10:INT bit to clear the transmission completion flag.
• Writing "1" to this bit leaves its value unchanged and has no effect on the operation.
• The bit returns "1" when read by a read-modify-write (RMW) type of instruction.
This bit enables or disables arbitration lost interrupts.
• An arbitration lost interrupt request is generated if this bit and the IBCR00:ALF bit are
both "1".
Writing "0": Disables arbitration lost interrupts.
Writing "1": Enables arbitration lost interrupts.
This bit is used to detect a STOP condition.
• A STOP detection interrupt request is generated if this bit and the IBCR00:SPE bit are
both "1".
• This bit is set to "1" if a valid STOP condition is detected when the bus is busy.
Writing "0": Clears itself (changes the value to "0").
Writing "1": Leaves its value unchanged without affecting the operation.
• The bit returns "1" when read by a read-modify-write (RMW) type of instruction.
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-1 Functions of Bits in I2C Bus Control Register 0 (IBCR00) (2 / 2)
Bit name
bit2
SPE:
STOP detection
interrupt enable bit
bit1
WUF:
MCU standby-mode
wakeup interrupt
request flag bit
Function
This bit enables or disables STOP detection interrupts.
• A STOP detection interrupt request is generated if this bit and the IBCR00:SPF bit are
both "1".
Writing "0": Disables STOP detection interrupts.
Writing "1": Enables STOP detection interrupts.
This bit is used to detect MCU wakeup from a standby mode (stop or watch mode).
• A wakeup interrupt request is generated if this bit and the IBCR00:WUE bit are both "1".
• This bit is set to "1" if a START condition is detected with the wakeup function enabled
(IBCR00:WUE = 1).
Writing "0": Clears itself (changes the value to "0").
Writing "1": Leaves its value unchanged without affecting the operation.
• The bit returns "1" when read by a read-modify-write (RMW) type of instruction.
This bit enables or disables the function to wake up the MCU from standby mode (stop or
watch mode).
Writing "0": Disables the wakeup function.
Writing "1": Enables the wakeup function.
• If a start condition is detected in stop or watch mode when this bit is "1", a wakeup
interrupt request is generated to start I2C operation.
Note:
• Write "1" to this bit immediately before the MCU enters the stop or
watch mode. To ensure that I2C operation can restart immediately after
the MCU wakes up from stop or watch mode, clear (write "0" to) this
bit as soon as possible.
bit0
WUE:
MCU standby-mode
wakeup function
enable bit
• When a wakeup interrupt request occurs, the MCU wakes up after the
oscillation stabilization wait time elapses. To prevent the data loss immediately
after wakeup, therefore, the SCL must rise as the first cycle and the first bit
must be received as data after 100 μs (assuming that the minimum oscillation
stabilization wait time is 100 μs) from the wakeup due to the start of I2C
transmission (upon detection of the falling edge of SDA).
• During a MCU standby mode, the status flags, state machine, and I2C bus
outputs for the I2C function retain the states they had prior to entering the
standby mode. To prevent a hang-up of the entire I2C bus system, make sure
that IBSR0:BB = 0 before entering standby mode.
• The wakeup function does not support the transition of the MCU to stop or
watch mode with IBSR0:BB = 1. If the MCU enters stop or watch mode with
IBSR0:BB = 1, a bus error will occur upon detection of a start condition.
• The wakeup function is useful only when the MCU remains in stop/watch
mode. (In PLL stop mode, for example, the time from wakeup to the start of
communication becomes longer than in stop/watch mode as the PLL oscillation
stabilization wait time is required in addition to the oscillation stabilization wait
time.)
Note:
The AACKX, INTS, and WUE bits in the IBCR00 register are set to "0" and cannot be
written to either when I2C operation is disabled (ICCR0:EN = 0) or when a bus error
occurs (IBCR10:BER = 1).
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
■ I2C Bus Control Register 1 (IBCR10)
Figure 24.5-3 I2C Bus Control Register 1 (IBCR10)
Address
0061H
bit7
bit6
bit5
bit4
BER
BEIE
SCC
MSS
R(RM1),W
R/W
R0,W
R/W
bit3
bit2
DACKE GACKE
R/W
R/W
bit1
bit0
Initial value
INTE
INT
00000000B
R/W
R(RM1),W
Transfer completion interrupt request flag bit
INT
0
1
Read
Write
Data transfer not completed
Clear
1-byte data (including acknowledgment) transfer completed Unchanged
INTE
Transfer completion interrupt enable bit
0
Disables data transfer completion interrupt requests.
1
Enables data transfer completion interrupt requests.
GACKE
General call address acknowledge enable bit
0
Disables general call address ACK.
1
Enables general call address ACK.
DACKE
Data acknowledge enable bit
0
Disables data ACK.
1
Enables data ACK.
MSS
Master/slave select bit
0
Selects slave mode.
1
Selects master mode.
Start condition generation bit
SCC
Read
Write
0
Unchanged
Always "0"
1
Generates master-mode repeated start condition.
BEIE
Bus error interrupt request enable bit
0
Disables bus error interrupt requests.
1
Enables bus error interrupt requests.
Bus error interrupt request flag bit
BER
R/W
: Readable/writable (The read value
is the same as the write value.)
R(RM1),W : Readable/writable (The read value is different
from the write value. “1” is read by the
read-modify-write (RMW) type of instruction.)
R0,W
: Write only (Writable. The read value is “0”.)
: Initial value
548
Read
Write
0
No bus error
Clear
1
Invalid start/stop condition detected
Unchanged
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-2 Functions of Bits in I2C Bus Control Register 1 (IBCR10) (1 / 2)
Bit name
Function
bit7
BER:
Bus error interrupt
request flag bit
This bit is used to detect bus errors.
• A bus error interrupt request is generated if this bit and the IBCR10:BEIE bit are both "1".
• This bit is set to "1" when an invalid start or stop condition is detected.
Writing "0": Clears itself (changes the value to "0").
Writing "1": Leaves its value unchanged without affecting the operation.
• The bit returns "1" when read by a read-modify-write operation.
• When this bit is set to "1", ICCR0:EN is set to "0", and the I2C interface enters halt mode
to terminate data transfer.
bit6
BEIE:
Bus error interrupt
request enable bit
This bit enables or disables bus error interrupts.
• A bus error interrupt request is generated if this bit and the IBCR10:BER bit are both "1".
Writing "0": Disables bus error interrupts.
Writing "1": Enables bus error interrupts.
SCC:
Start condition
generation bit
This bit can be used to generate a start condition repeatedly to restart communications in
master mode.
• Writing "1" to the bit in master mode generates a start condition repeatedly.
• Writing "0" to the bit is meaningless.
• When read, the bit returns "0".
Note:
• Do not set IBCR10:SCC = 1 and IBCR10:MSS = 0 at the same time.
• An attempt to write "1" to this bit is ignored when IBCR10:INT = 0 (no start
condition is generated). If you write "1" to this bit and "0" to the IBCR10:INT
bit at the same time when the IBCR10:INT = 1, this bit takes priority and
generates a start condition.
MSS:
Master/slave select bit
This bit selects master mode or slave mode.
• Writing "1" to this bit while the I2C bus is in the idle state (IBSR0:BB = 0) selects master
mode, generates a start condition, and then starts address transfer.
• Writing "0" to the bit while the I2C bus is in the busy state (IBSR0:BB = 1) selects slave
mode, generates a stop condition, and then ends data transfer.
• If arbitration lost occurs during data or address transfer in master mode, this bit is cleared
to "0" and the mode changes to slave mode.
Note:
• Do not set IBCR10:SCC = 1 and IBCR10:MSS = 0 at the same time.
• An attempt to write "0" to this bit is ignored when IBCR10:INT = 0. If you
write "0" to this bit and "0" to the IBCR10:INT bit at the same time when the
IBCR10:INT = 1, this bit takes priority and generates a stop condition.
• The IBCR00:ALF bit is not set even though you write "1" to the MSS bit during
transmission or reception in slave mode. Do not write "1" to the MSS bit during
transmission or reception in slave mode.
bit3
DACKE:
Data acknowledge
enable bit
This bit controls data acknowledgment during data reception.
Writing "0": Disables data acknowledge output.
Writing "1": Enables data acknowledge output. In this case, data acknowledgment is
output in the ninth SCL cycle during data reception in master mode. In slave
mode, data acknowledgment is output in the ninth SCL cycle only if address
acknowledgment has already been output.
bit2
This bit controls general call address acknowledgment.
GACKE:
Writing "0": Disables output of general call address acknowledge.
General call address
Writing "1": Causes a general call address acknowledgment to be output if a general call
acknowledge enable bit
address (00H) is received in master or slave mode.
bit1
INTE:
Transfer completion
interrupt enable bit
bit5
bit4
MN702-00005-2v0-E
This bit enables or disables transfer completion interrupts.
Writing "0": Disables transfer completion interrupts.
Writing "1": Enables transfer completion interrupts.
• A transfer completion interrupt request is generated if this bit and the IBCR10:INT bit are
both "1".
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-2 Functions of Bits in I2C Bus Control Register 1 (IBCR10) (2 / 2)
Bit name
bit0
INT:
Transfer completion
interrupt request flag
bit
Function
This bit is used to detect transfer completion.
• A transfer completion interrupt request is generated if this bit and the IBCR10:INTE bit
are both "1".
• This bit is set to "1" upon completion of transfer of 1-byte address or data (whether or not
this includes an acknowledgment depends on the IBCR00:INTS setting) if any of the
following four conditions is satisfied.
- In bus master mode
- Addressed as slave
- General call address received
- Arbitration lost detected
• This bit is set to "0" in the following cases:
- "0" written to the bit
- Repeated start condition (IBCR10:SCC = 1) or stop condition (IBCR10:MSS = 0)
occurred in master mode.
• An attempt to write "1" to this bit leaves its value unchanged and has no effect on the
operation.
• The bit returns "1" when read by a read-modify-write (RMW) type of instruction.
• The SCL line remains at "L" while this bit is "1".
• Writing "0" to clear the bit (change the value to "0") releases the SCL line to enable
transmission for the next byte of data.
Note:
• If "1" is written to IBCR10:SCC when this bit is "0", the IBCR10:SCC bit has
priority and the start condition is generated.
• If "0" is written to IBCR10:MSS when this bit is "0", the IBCR10:MSS bit has
priority and the stop condition is generated.
• If IBCR00:INTS = 1 when data is received, this bit is set to "1" upon
completion of transfer of one-byte data (including no acknowledgment). In
other cases, this bit is set to "1" upon completion of transmission or reception of
one-byte data/address including an acknowledgment.
Notes:
• When clearing the interrupt request flag (IBCR10:BER) by writing "0", do not update
the interrupt request enable bit (IBCR10:BEIE) at the same time.
• All the bits in IBCR10 except the BER and BEIE bits are cleared to "0" either when
operation is disabled (ICCR0:EN = 0) or when a bus error occurs (IBCR10:BER = 1).
550
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CHAPTER 24 I2C
24.5 Registers of I2C
MB95410H/470H Series
24.5.2
I2C Bus Status Register (IBSR0)
The IBSR0 register contains the status of the I2C interface.
■ I2C Bus Status Register (IBSR0)
Figure 24.5-4 I2C Bus Status Register (IBSR0)
Address
0062H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
BB
RSC
-
LRB
TRX
AAS GCA
R/WX
R/WX
R0/WX
R/WX
R/WX
R/WX
R/WX
bit0
Initial value
BTF
00000000B
R/WX
FBT
First byte detection bit
0
Data received is not the first byte.
1
Data received is the first byte (address data)
GCA
General call address detection bit
0
General call address (00H) not received in slave mode.
1
General call address (00H) received in slave mode.
AAS
Addressing detection bit
0
Not addressed in slave mode.
1
Addressed in slave mode.
TRX
Data transfer status bit
0
Receive mode
1
Transmit mode
LRB
Acknowledge storage bit
0
Acknowledgment detected in ninth shift clock cycle.
1
Acknowledgment not detected in ninth shift clock cycle.
RSC
Repeated start condition detection bit
0
Repeated start condition not detected
1
Repeated start condition detected with bus in use
R/WX
: Read only (Readable. Writing a value to
this bit has no effect on operation.)
BB
Bus busy bit
R0/WX
: (The read value is “0”. Writing a value to
ths bit has no effect on operation.)
: Undefined bit
: Initial value
0
Bus idle
1
Bus busy
-
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24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-3 Functions of Bits in I2C Bus Status Register (IBSR0)
Bit name
Function
BB:
Bus busy bit
This bit indicates the bus status.
• This bit is set to "1" when a start condition is detected.
• This bit is set to "0" when a stop condition is detected.
bit6
RSC:
Repeated start
condition detection bit
This bit is used to detect repeated start conditions.
• This bit is set to "1" when a repeated start condition is detected.
• This bit is set to "0" in the following cases:
- When "0" is written to IBCR10:INT.
- When the slave address does not match the address set in IAAR0 in slave mode.
- When the slave address matches the address set in IAAR0 but IBCR00:AACKX = 1 in
slave mode.
- When the general call address is received but IBCR10:GACKE = 0 in slave mode.
- When a stop condition is detected.
bit5
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
bit7
LRB:
bit4
Acknowledge
storage bit
This bit saves the value of the SDA line in the ninth shift clock cycle during data byte
transfer.
• This bit is set to "1" when no acknowledgment is detected (SDA = H).
• This bit is set to "0" in the following cases:
- When acknowledgment is detected (SDA = L)
- When a start or stop condition is detected.
Note:
It follows from the above that this bit must be read after ACK. (Read the value in
response to the transfer completion interrupt in the ninth SCL cycle.) Accordingly,
if ACK is read when the IBCR00:INTS bit is "1", you must write "0" to the
IBCR00:INTS bit in the transfer completion interrupt triggered by the eighth SCL
cycle so that another transfer completion interrupt will be triggered by the ninth
SCL cycle.
bit3
TRX:
Data transfer status bit
This bit indicates the data transfer mode.
• This bit is set to "1" when data transfer is performed in transfer mode.
• This bit is set to "0" in the following cases:
- Data is transferred in receive mode.
- NACK is received in slave transmit mode.
bit2
AAS:
Addressing detection
bit
This bit indicates that the MCU has been addressed in slave mode.
• This bit is set to "1" if the MCU is addressed in slave mode.
• This bit is set to "0" when a start or stop condition is detected.
GCA:
General call address
detection bit
This bit is used to detect a general call address.
• This bit is set to "1" in the following cases:
- When the general call address (00H) is received in slave mode.
- When the general call address (00H) is received in master mode with IBCR10:GACKE
= 1.
- When arbitration lost is detected during transmission of the second byte of the general
call address in master mode.
• This bit is set to "0" in the following cases:
- When a start or stop condition is detected.
- When arbitration lost is not detected during transmission of the second byte of the
general call address in master mode.
FBT:
First byte detection bit
This bit is used to detect first byte.
• This bit is set to "1" when a start condition is detected.
• This bit is set to "0" in the following cases:
- When "0" is written to the IBCR10:INT bit.
- When the slave address does not match the address set in IAAR0 in slave mode.
- When the slave address matches the address set in IAAR0 but IBCR00:AACKX = 1 in
slave mode.
- When the general call address is received with IBCR10:GACKE = 0 in slave mode.
bit1
bit0
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24.5.3
CHAPTER 24 I2C
24.5 Registers of I2C
I2C Data Register (IDDR0)
The IDDR0 register is used to set the data or address to send and to hold the
data or address received.
■ I2C Data Register (IDDR0)
Figure 24.5-5 I2C Data Register (IDDR0)
Address
0063H
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable (The read value is the same as the write value.)
In transmit mode, each bit of the data or address value written to the register is shifted to the
SDA line, starting with the MSB. The write side of this register is double-buffered, where if the
bus is in use (IBSR0:BB=1), the write data is loaded to the 8-bit shift register either when the
current data transfer completion interrupt is cleared (writing "0" to the IBCR10:INT bit) or
when a repeated start condition is generated (writing "1" to the IBCR10:SCC bit). Each bit of
the shift register data is output (shifted) to the SDA line. Note that writing to this register has
no effect on the current data transfer. In slave mode, however, data is transferred to the shift
register after the address is determined.
The received data or address can be read from this register during the transfer completion
interrupt (IBCR10:INT = 1). When it is read, however, the serial transfer register is directly
read from, the receive data is valid only while IBCR10:INT = 1.
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CHAPTER 24 I2C
24.5 Registers of I2C
24.5.4
MB95410H/470H Series
I2C Address Register (IAAR0)
The IAAR0 register is used to set the slave address.
■ I2C Address Register (IAAR0)
Figure 24.5-6 I2C Address Register (IAAR0)
Address
0064H
R/W
R0/WX
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
A6
A5
A4
A3
A2
A1
A0
R0/WX R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable (The read value is the same as the write value.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
The I2C address register (IAAR0) is used to set the slave address. In slave mode, address data
from the master is recieved and then compared with the value of the IAAR0 register.
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24.5 Registers of I2C
MB95410H/470H Series
I2C Clock Control Register (ICCR0)
24.5.5
The ICCR0 register is used to enable I2C operation and select the shift clock
frequency.
■ I2C Clock Control Register (ICCR0)
Figure 24.5-7 I2C Clock Control Register (ICCR0)
bit7
Address
DMBP
0065H
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
EN
CS4
CS3
CS2
CS1
CS0
00000000B
R0/WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable (The read value
is the same as the write value.)
R0/WX
: The read value is “0”. Writing a value
to this bit has no effect on operation.
-
: Undefined bit
: Initial value
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CS2
CS1
CS0
Clock-2 select bits (Divider n)
0
0
0
4
0
0
1
8
0
1
0
22
0
1
1
38
1
0
0
98
1
0
1
128
1
1
0
256
1
1
1
512
CS4
CS3
Clock-1 select bits (Divider m)
0
0
5
0
1
6
1
0
7
1
1
8
EN
I2C operation enable bit
0
Disables I2C operation.
1
Enables I 2C operation.
DMBP
Divider m bypass bit
0
Disables bypassing.
1
Bypasses divider m.
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24.5 Registers of I2C
MB95410H/470H Series
Table 24.5-4 Functions of Bits in I2C Clock Control Register (ICCR0)
Bit name
Function
bit7
DMBP:
Divider m bypass bit
This bit is used to bypass the divider m to generate the shift clock frequency.
Writing "0": Sets the value set in CS3 and CS4 as the divider m value. (m = ICCR0:CS4,
CS3)
Writing "1": Bypasses the divider m.
Note:
Do not set this bit to "1" when divider n = 4 (ICCR0:CS2 to CS0 = 000B).
bit6
Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
bit5
EN:
I2C operation enable
bit
• This bit enables I2C interface operation.
Writing "0": Disables operation of the I2C interface and clears the following bits to "0".
- AACKX, INTS, and WUE bits in the IBCR00 register
- All the bits in the IBCR10 register except the BER and BEIE bits
- All bits in the IBSR0 register
Writing "1": Enables operation of the I2C interface.
• This bit is set to "0" in the following cases:
- When "0" is written to this bit.
- When IBCR10:BER is "1".
bit4,
bit3
CS4, CS3:
Clock-1 select bits
(Divider m)
bit2
to
bit0
CS2, CS1, CS0:
Clock-2 select bits
(Divider n)
These bits set the shift clock frequency.
• Shift clock frequency (Fsck) is set as shown by the following equation:
φ
Fsck =
(m × n + 2)
φ represents the machine clock frequency (MCLK).
Note:
If the standby mode wakeup function is not used, disable I2C operation before switching
the MCU to stop or watch mode.
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CHAPTER 24 I2C
24.6 I2C Interrupts
MB95410H/470H Series
24.6
I2C Interrupts
The I2C interface has a transfer interrupt and a stop interrupt which are
triggered by the following events.
• Transfer interrupt
A transfer interrupt occurs either upon completion of data transfer or when a
bus error occurs.
• Stop interrupt
A stop interrupt occurs upon detection of a stop condition or arbitration lost
or upon access to the I2C interface in stop/watch mode.
■ Transfer Interrupt
Table 24.6-1 shows the transfer interrupt control bits and I2C interrupt sources.
Table 24.6-1 Transfer Interrupt Control Bits and I2C Interrupt Sources
End of transfer
Bus error
Interrupt request flag bit
IBCR10:INT = "1"
IBCR10:BER = "1"
Interrupt request enable bit
IBCR10:INTE = "1"
IBCR10:BEIE = "1"
Interrupt source
Data transfer complete
Bus error occurred
• Interrupt upon completion of transfer
An interrupt request is output to the CPU upon completion of data transfer if the transfer
completion interrupt request enable bit has been set to enable (IBCR10:INTE = 1). In the
interrupt service routine, write "0" to the transfer completion interrupt request flag bit
(IBCR10:INT) to clear the interrupt request. When data transfer is completed, the
IBCR10:INT bit is set to "1" regardless of the value of the IBCR10:INTE bit.
• Interrupt in response to a bus error
When the following conditions are met, a bus error is deemed to have occurred, and the I2C
interface will be stopped.
- When a stop condition is detected in master mode.
- When a start or stop condition is detected during transmission or reception of the first
byte.
- When a start or stop condition is detected during transmission or reception of data
(excluding the start, first data, and stop bits).
In these cases, an interrupt request is output to the CPU if the bus error interrupt request enable
bit has been set to enable (IBCR10:BEIE = 1). In the interrupt service routine, write "0" to the
bus error interrupt request flag bit (IBCR10:BER) to clear the interrupt request. When a bus
error occurs, the IBCR10:BER bit is set to "1" regardless of the value of the IBCR10:BEIE bit.
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CHAPTER 24 I2C
24.6 I2C Interrupts
MB95410H/470H Series
■ Stop Interrupt
Table 24.6-2 shows the stop interrupt control bits and I2C interrupt sources (trigger events).
Table 24.6-2 Stop Interrupt Control Bits and I2C Interrupt Sources
Detection of stop condition
Detection of
arbitration lost
MCU wakeup from
stop/watch mode
Interrupt request flag bit
IBCR00:SPF = "1"
IBCR00:ALF = "1"
IBCH00:WUF = "1"
Interrupt request enable bit
IBCR00:SPE = "1"
IBCR00:ALE = "1"
IBCR00:WUE = "1"
Interrupt source
Stop condition detected
Arbitration lost detected
Start condition detected
• Interrupt upon detection of a stop condition
A stop condition is considered to be valid if all of the following conditions are satisfied
when the stop condition is detected.
- The bus is busy (state which the start condition is detected).
- IBCR10:MSS = 0
- After transfer of one byte of data completes, including the acknowledgment.
In this case, an interrupt request is output to the CPU if the stop condition detection interrupt
request enable bit has been set to enable (IBCR00:SPE = 1). In the interrupt service routine,
write "0" to the IBCR00:SPF bit to clear the interrupt request.
The IBCR00:SPF bit is set to "1" when a valid stop condition occurs regardless of the value of
the IBCR00:SPE bit.
• Interrupt upon detection of arbitration lost
When arbitration lost is detected, an interrupt request is output to the CPU if the arbitration
lost detection interrupt request enable bit has been set to enable (IBCR00:ALE = 1). Either
write "0" to the arbitration lost interrupt request flag bit (IBCR00:ALF) while the bus is idle
or write "0" to the IBCR10:INT bit from the interrupt service routine while the bus is busy
to clear the interrupt request.
When arbitration lost occurs, the IBCR00:ALF bit is set to "1" regardless of the value for
the IBCR00:ALE bit.
• Interrupt for MCU wakeup from stop/watch mode
When a start condition is detected, an interrupt request is output to the CPU if the function
to wake up the MCU from stop or watch mode has been enabled (IBCR00:WUE = 1).
In the interrupt service routine, write "0" to the MCU standby mode wakeup interrupt
request flag bit (IBCR00:WUF) to clear the interrupt request.
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24.6 I2C Interrupts
MB95410H/470H Series
■ Register and Vector Table Addresses Related to I2C Interrupts
Table 24.6-3 Register and Vector Table Addresses Related to I2C Interrupts
Interrupt source
2
Interrupt
request no.
IRQ16
I C
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
ILR4
L16
FFDAH
FFDBH
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 24 I2C
24.7 Operations of I2C and Setting Procedure Example
24.7
MB95410H/470H Series
Operations of I2C and Setting Procedure Example
This section describes the operations of I2C.
■ Operations of I2C
● I2C interface
The I2C interface is an eight-bit serial interface synchronized with a shift clock.
● MCU standby mode wakeup function
The wakeup function wakes up the MCU upon detection of a start condition, from low power
consumption mode such as stop or watch mode.
■ Setting Procedure Example
Below is an example of procedure for setting I2C.
● Initial settings
1) Set the port for input (DDR2).
2) Set the interrupt level (ILR4).
3) Set the slave address (IAAR0).
4) Select the clock and enable I2C operation (ICCR0).
5) Enable bus error interrupt requests (IBCR10:BEIE = 1).
● Interrupt processing
1) Arbitrary processing
2) Clear the bus error interrupt request flag (IBCR10:BER = 0).
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24.7 Operations of I C and Setting Procedure Example
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MB95410H/470H Series
l2C Interface
24.7.1
The I2C interface is an eight-bit serial interface synchronized with the shift
clock.
■ I2C System
The I2C bus system uses the serial data line (SDA) and serial clock line (SCL) for data
transfers. All the devices connected to the bus require open drain or open collector outputs
which must be connected with a pull-up resistor.
Each of the devices connected to the bus has a unique address which can be set up using
software. The devices always operate in a simple master/slave relationship, where the master
functions as the master transmitter or master receiver. The I2C interface is a true multi-master
bus with a collision detection function and arbitration function to prevent data from being lost
if more than one master attempts to start data transfer at the same time.
■ I2C Protocol
Figure 24.7-1 shows the format required for data transfer.
Figure 24.7-1 Data Transfer Example
MSB
LSB
MSB
LSB
SDA
SCL
Start
condition (S)
7-bit address
R/W
Acknowledge bit
8-bit data
Stop
condition (P)
No acknowledge
The slave address is transmitted after a start condition (S) is generated. This address is seven
bits followed by the data direction bit (R/W) in the eighth bit position. Data is transmitted after
the address. The data is eight bits followed by an acknowledgment.
Data can be transmitted continuously to the same slave address in consecutive units of eight
bits plus acknowledgment.
Data transfer is always ended in the master stop condition (P). However, the repeated start
condition (S) can be used to transmit the address which indicates a different slave without
generating a stop condition.
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24.7 Operations of I2C and Setting Procedure Example
MB95410H/470H Series
■ Start Conditions
While the bus is idle (SCL and SDA are both at the logical "H" level), the master generates a
start condition to start transmission. As shown in Figure 24.7-1, a start condition is triggered
when the SDA line is changed from "H" to "L" while SCL = "H". This starts a new data
transfer and commences master/slave operation.
A start condition can be generated in either of the following two ways.
• By writing "1" to the IBCR10:MSS bit while the I2C bus is not in use (IBCR10:MSS = 0,
IBSR0:BB = 0, IBCR10:INT = 0, and IBCR00:ALF = 0). (Next, IBSR0:BB is set to "1" to
indicate that the bus is busy.)
• By writing "1" to the IBCR10:SCC bit during an interrupt while in bus master mode
(IBCR10:MSS = 1, IBSR0:BB = 1, IBCR10:INT = 1, and IBCR00:ALF = 0). (This
generates a repeated START condition.)
Writing "1" to the IBCR10:MSS or IBCR10:SCC bit is ignored in other than the above cases.
If another system is using the bus when "1" is written to the IBCR10:MSS bit, the
IBCR00:ALF bit is set to "1".
■ Addressing
● Slave addressing in master mode
In master mode, IBSR0:BB and IBSR0:TRX are set to "1" after the start condition is generated,
and the slave address in the IDDR0 register is output to the bus starting with the MSB. The
address data consists of eight bits: the 7-bit slave address and the data transfer direction R/W
bit (bit 0 in the IDDR0 register).
The acknowledgment from the slave is received after the address data is sent. SDA goes to "L"
in the ninth clock cycle and the acknowledge bit from the receiving device is received (see
Figure 24.7-1). In this case, the R/W bit (IDDR0:bit0) is inverted logically and stored in the
IBSR0:TRX bit as "1" if the SDA level is "L".
● Addressing in slave mode
In slave mode, after the start condition is detected, IBSR0:BB is set to "1" and IBSR0:TRX is
set to "0", and the data received from the master is stored in the IDDR0 register. After the
address data is received, the IDDR0 and IAAR0 registers are compared. If the addresses match,
IBSR0:AAS is set to "1" and an acknowledgment is sent to the master. Next, bit 0 of the
receive data (bit 0 in the IDDR0 register) is saved in the IBSR0:TRX bit.
■ Data Transfer
If the MCU is addressed as a slave, data can be sent or received byte by byte with the direction
determined by the R/W bit sent by the master.
Each byte to be output on the SDA line is fixed at eight bits. As shown in Figure 24.7-1, the
receiver sends an acknowledgment to the sender by forcing the SDA line to the stable "L" level
while the acknowledge clock pulse is "H". Data is transferred at one clock pulse per bit with
MSB at the head. Sending and receiving an acknowledgment is required after each byte is
transferred. Accordingly, nine clock pulses are required to transfer one complete data byte.
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■ Acknowledgment
An acknowledgment is sent by the receiver in the ninth clock cycle for data byte transfer by the
sender based on the following conditions.
An address acknowledgment is generated in the following cases.
• The received address matches the address set in IAAR0, and the address acknowledgment is
output automatically (IBCR00:AACKX = 0).
• A general call address (00H) is received and the general call address acknowledgment
output is enabled (IBCR10:GACKE = 1).
A data acknowledge bit used when data is received can be enabled or disabled by the
IBCR10:DACKE bit. In master mode, a data acknowledgment is generated if IBCR10:DACKE
= 1. In slave mode, a data acknowledgment is generated if an address acknowledgment has
already been generated and IBCR10:DACKE = 1. The received acknowledgment is saved in
IBSR0:LRB in the ninth SCL cycle.
• If the data ACK depends on the content of received data (such as packet error checking used
by the SM bus), control the data ACK by setting the data ACK enable bit
(IBCR10:DACKE) after writing "1" to the IBCR00:INTS bit (for example, by a previous
transfer completion interrupt) so that the latest received data can be read.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received
(IBSR0:LRB must be read during the transfer completion interrupt triggered by the ninth
SCL cycle). Accordingly, if ACK is read when the IBCR00:INTS bit is "1", you must write
"0" to this bit in the transfer completion interrupt triggered by the eighth SCL cycle so that
another transfer completion interrupt will be triggered by the ninth SCL cycle.
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24.7 Operations of I2C and Setting Procedure Example
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■ General Call Address
A general call address consists of the start address byte (00H) and the second address byte that
follows. To use a general call address, you must set IBCR10:GACKE=1 before the
acknowledge of the first byte general call address. Also, the acknowledgment for the second
address byte can be controlled as shown below.
Figure 24.7-2 General Call Operation
Slave mode
First-byte general call address
Second-byte general call address
ACK
ACK/NACK
IBCR10:INT is set at 9th SCL↓.
Read IBSR0: LRB.
IBCR10:INT is set at 9th SCL↓.
Set IBCR00:INTS = 1.
When IBCR10:GACKE = 1,
ACK is given and IBSR0:GCA is set.
IBCR10:INT is set at 8th SCL↓.
Read IDDR0 and control ACK/NACK by IBCR10:DACKE.
To read IBSR10:LRB, set INTS = 0.
(a) General call operation in slave mode
Master mode
GACKE=1
First-byte general call address
ACK
Second-byte general call address
ACK/NACK
IBCR10:INT is set at 9th SCL↓.
Read IBSR0:LRB.
IBCR10:INT is set at 9th SCL↓.
Set IBCR00:INTS = 1 and GACKE = 0.
GCA is cleared.
IBCR10:INT is set at 8th SCL↓.
To read IBSR10:LRB, set INTS = 0.
ACK is given and IBSR0:GCA is set.
(b) General call operation in master mode (Start from GACKE = 1 with no AL.)
Master mode
GACKE=1
First-byte general call address
ACK
Second-byte general call address
ACK/NACK
IBCR10:INT is set at 9th SCL↓.
Read IBSR0:LRB.
IBCR10:INT is set at 9th SCL↓.
Set IBCR00:INTS = 1 and GACKE = 0.
IBCR10:INT is set at 8th SCL↓.
Read IDDR0 and control ACK/NACK by IBCR10:DACKE.
To read IBSR10:LRB, set INTS = 0.
ACK is given and IBSR0:GCA is set.
AL is generated by second address and switches to slave mode.
(c) General call operation in master mode (Start from GACKE = 1 with AL generated by second address.)
Master mode
GACKE=0
First-byte general call address
ACK
Second-byte general call address
ACK/NACK
IBCR10:INT is set at 9th SCL↓.
Read IBSR0:LRB.
IBCR10:INT is set at 9th SCL↓.
Set IBCR00:INTS = 1.
IBCR10:INT is set at 8th SCL↓.
Set INTS = 0 to read IBSR10:LRB.
ACK is not given and IBSR0:GCA is not set.
(d) General call operation in master mode (Start from GACKE = 0 with no AL.)
Master mode
GACKE=0
First-byte general call address
ACK
Second-byte general call address
IBCR10:INT is set at 9th SCL↓.
Set IBCR00:INTS = 1.
ACK is not given and IBSR0:GCA is not set.
ACK/NACK
IBCR10:INT is set at 9th SCL↓.
Read IBSR0:LRB.
IBCR10:INT is set at 8th SCL↓.
Read IDDR0 and control ACK/NACK by IBCR10:DACKE.
To read IBSRl:LRB, set INT S = 0.
AL is generated by second address, IBSR0:GCA is set,
and switches to slave mode.
(e) General call operation in master mode (Start from GACKE = 0 with AL generated by second address.)
ACK
NACK
GCA
AL
: Acknowledgment
: No acknowledgment
: General call address
: Arbitration lost
If this module sends a general call address at the same time as another device, you can
determine whether the module successfully seized control of the bus by checking whether
arbitration lost was detected when the second address byte was transferred. If arbitration lost
was detected, the module goes to slave mode and continues to receive data from the master.
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CHAPTER 24 I2C
24.7 Operations of I C and Setting Procedure Example
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■ Stop Condition
The master can release the bus and end communications by generating a stop condition.
Changing the SDA line from "L" to "H" while SCL is "H" generates a stop condition. This
signals to the other devices on the bus that the master has finished communications (referred to
below as "bus free"). However, the master can continue to generate start conditions without
generating a stop condition. This is called a repeated start condition.
Writing "0" to the IBCR10:MSS bit during an interrupt while in bus master mode
(IBCR10:MSS = 1, IBSR0:BB = 1, IBCR10:INT = 1, and IBCR00:ALF = 0) generates a stop
condition and changes to slave mode. In other cases, writing "0" to the IBCR10:MSS bit is
ignored.
■ Arbitration
The interface circuit is a true multi-master bus able to connect multiple master devices.
Arbitration occurs when another master within the system simultaneously transfers data during
a master transfer.
Arbitration occurs on the SDA line while the SCL line is at the "H" level. When the send data
is "1" and the data on the SDA line is "L" at the master, this is treated as arbitration lost. In this
case, data output is halted and IBCR00:ALF is set to "1". If this occurs, an interrupt is
generated if arbitration lost interrupts have been enabled (IBCR00:ALE = 1). If IBCR00:ALF
is set to "1", the module sets IBCR10:MSS = 0 and IBSR0:TRX = 0, clears TRX, and goes to
slave receive mode.
If IBCR00:ALF is set to "1" when IBSR0:BB = 0, IBCR00:ALF is cleared only by writing "0".
If IBCR00:ALF is set to "1" when IBSR0:BB = 1, IBCR00:ALF is cleared only by clearing
IBCR10:INT to "0".
● Conditions for generating an arbitration lost interrupt when IBSR0:BB = "0"
When a start condition is generated by the program (by setting the IBCR10:MSS bit to "1") at
the timing shown in Figure 24.7-3 or Figure 24.7-4, interrupt generation (IBCR10:INT bit = 1)
is prohibited by arbitration lost detection (IBCR00:ALF = 1).
• Conditions (1) in which no interrupt is generated due to arbitration lost
If the program triggers a start condition (by setting the IBCR10:MSS bit to "1") when no start
condition has been detected (IBSR0:BB bit = 0) and the SDA and SCL line pins are at the "L"
level.
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24.7 Operations of I2C and Setting Procedure Example
MB95410H/470H Series
Figure 24.7-3 Timing Diagram with No Interrupt Generated with IBCR00:ALF = 1
SCL or SDA pin at "L" level
"L"
SCL pin
"L"
SDA pin
1
I2C
operation enabled (ICCR0:EN bit = 1)
Master mode set (IBCR10:MSS bit = 1)
Arbitration lost detection bit
(IBCR00:ALF bit = 1)
566
Bus busy (IBSR0:BB bit)
0
Interrupt (IBCR10:INT bit)
0
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CHAPTER 24 I2C
24.7 Operations of I C and Setting Procedure Example
2
• Conditions (2) in which no interrupt is generated due to arbitration lost
If the program enables I2C operation (by setting the ICCR0:EN bit to "1") and triggers a start
condition (by setting the IBCR10:MSS bit to "1") when the I2C bus is in use by another master.
This is because, as shown in Figure 24.7-4, this I2C module cannot detect the start condition
(IBSR0:BB bit= 0) if another master starts communications on the I2C bus when the operation
of this I2C module has been disabled (ICCR0:EN bit = 0).
Figure 24.7-4 Timing Diagram with No Interrupt Generated with IBCR0:ALF = 1
Start condition
IBCR10:INT bit interrupt
does not occur in 9th clock cycle.
Stop
condition
SCL pin
Slave address
SDA pin
ACK
Data
ACK
ICCR0:EN bit
IBCR10:MSS bit
IBCR00:ALF bit
IBSR0:BB bit
0
IBCR10:INT bit
0
If this situation can occur, use the following procedure to set up the module from the software.
1) Trigger a start condition from the program (by setting the IBCR10:MSS bit to "1").
2) Check the IBCR00:ALF and IBSR0:BB bits in the arbitration lost interrupt.
If IBCR00:ALF = 1 and IBSR0:BB = 0, clear the IBCR00:ALF bit to "0".
If IBCR00:ALF = 1 and IBSR0:BB = 1, clear the IBCR00:ALE bit to "0" and perform
control as normal. (Normal control means writing "0" to the IBCR00:INT bit in the INT
interrupt to clear IBCR00:ALF.)
In other cases, perform control as normal (Normal control means writing "0" to the
IBCR00:INT bit in the INT interrupt to clear IBCR00:ALF.)
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24.7 Operations of I2C and Setting Procedure Example
MB95410H/470H Series
The following sample flow chart illustrates the procedure:
Figure 24.7-5 Sample Flow Chart of Setting
Enable AL interrupts (IBCR00:ALE = "1").
Set master mode.
Set the MSS bit in I C bus control register 1 (IBCR10) to "1".
2
IBCR00:ALF = 1
NO
YES
NO
IBSR0:BB = 0
YES
Write "0" to IBCR00:ALF to
clear AL flag and interrupt.
Write "0" to IBCR00:ALE to
clear AL interrupt.
Normal control
● Example of generating an interrupt (IBCR10:INT = 1) with "IBCR00:ALF = 1" detected
If a start condition is generated by the program (by setting the IBCR10:MSS bit to "1") with
the bus busy (IBSR0:BB = 1) and arbitration lost detected, a IBCR10:INT bit interrupt occurs
upon detection of "IBCR00:ALF = 1".
Figure 24.7-6 Timing Diagram with Interrupt Generated with "IBCR00:ALF = 1" Detected
Start condition
Interrupt in 9th clock cycle
SCL pin
SDA pin
Slave address
ACK
Data
ICCR0:EN
IBCR10:MSS
IBCR00:ALF
Clear IBCR00:ALF by software.
IBSR0:BB
IBCR10:INT
568
Clear IBCR10:INT by software
and release SCL line.
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CHAPTER 24 I2C
24.7 Operations of I C and Setting Procedure Example
2
MB95410H/470H Series
24.7.2
Function to Wake-up MCU from Standby Mode
The wakeup function enables the I2C macro to be accessed while the MCU is in
stop or watch mode.
■ Function to Wake Up the MCU from Standby Mode
The I2C macro includes a function to wake up the MCU from standby mode. The function is
enabled by writing "1" to the IBCR00:WUE bit.
When the MCU is in stop/watch mode with the IBCR00:WUE bit containing "1", if a start
condition is detected on the I2C bus, the wakeup interrupt request flag bit (IBCR00:WUF) is
set to "1" and the wakeup interrupt request is generated to wake up the MCU from stop/watch
mode.
• Set IBCR00:WUE to "1" immediately prior to setting the MCU to stop or watch mode.
Similarly, clear IBCR00:WUE (by writing "0") after the MCU wakes up from stop or watch
mode so that I2C operation can restart as soon as possible.
• The wakeup function only applies to the MCU stop and watch modes.
Note:
In PLL stop mode, a PLL oscillation stabilization wait time is required in addition to the
oscillation stabilization wait time. This causes a very long delay between the MCU waking
up and communications restarting.
Figure 24.7-7 Comparison of Normal I2C Operation and Wakeup Operation
SDA
SCL
5
IRQ by
IBCR00:WUF
Machine
Clock
1
2
3
4
1
Set the IBCR00:WUE bit to "1" immediately before entering stop/watch mode and make sure that IBSR0:BB = 0.
2
Set the MCU to stop/watch mode and the machine clock stops.
3
Detect a start condition in stop/watch mode. IBCR00:WUF is set to 1 and a wakeup IRQ is generated. After the
oscillation stabilization wait time, the MCU wakes up and enters main clock mode.
4
Clear the IBCR00:WUE bit to "0" so that I2C can restart the normal operation, and clear the IBCR00:WUF bit to
"0" to clear the wakeup interrupt.
5
To receive the data byte correctly, the SCL must be released in the first cycle after 100 μs (assuming a minimum
oscillation stabilization wait time of 100 μs) from the start of I2C transmission (falling edge detection of SDA).
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24.7 Operations of I2C and Setting Procedure Example
MB95410H/470H Series
The following sample flow chart illustrates the wakeup function.
Figure 24.7-8 Sample Flow Chart of Wakeup Function
Procedure for transition
to stop/watch mode
IBSR0:BB = 0
NO
YES
Enable wakeup function by setting
IBCR00:WUE = "1".
IBSR0:BB = 0
NO
IBCR00:WUE = 0
YES
Go to stop/watch mode.
570
Write "0" to IBCR00:ALE
and clear AL interrupt
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CHAPTER 24 I2C
24.8 Notes on Using I2C Interface
MB95410H/470H Series
24.8
Notes on Using I2C Interface
This section provides notes on using the I2C interface.
■ Notes on Using I2C Interface
● Notes on setting I2C interface registers
• Operation of the I2C interface must be enabled (ICCR0:EN) before setting the I2C bus
control registers (IBCR00 and IBCR10).
• Setting the master/slave select bit (IBCR10:MSS) (by writing "1") starts data transfer.
● Notes on setting the shift clock frequency
• The shift clock frequency can be calculated by determining the m, n, and DMBP values
using the Fsck equation in Table 24.5-4.
• "DMBP=1" may not be selected if the value of n is 4 (ICCR0:CS2 = CS1 = CS = 0).
● Notes on priority for simultaneous writes
• Contention between next byte transfer and stop condition
When "0" is written to IBCR10:MSS with IBCR10:INT cleared, the MSS bit takes priority
and a stop condition develops.
• Contention between next byte transfer and start condition
When "1" is written to IBCR10:SCC with IBCR10:INT cleared, the SCC bit takes priority
and a start condition develops.
● Notes on setup using software
• Do not select a repeated start
(IBCR10:MSS=0) simultaneously.
condition
(IBCR10:SCC=1)
and
slave
mode
• Execution cannot return from interrupt processing if the interrupt request enable bit is
enabled (IBCR10:BEIE=1/IBCR10:INTE=1) with the interrupt request flag bit
(IBCR10:BER/IBCR10:INT) containing "1". Be sure to clear the IBCR10:BER/
IBCR10:INT bit.
• The following bits are cleared to "0" when I2C operation is disabled (ICCR0:EN=0):
- AACKX, INTS, and WUE bits in the IBCR00 register
- All the bits in the IBCR10 register except the BER and BEIE bits
- All bits in the IBSR0 register
● Notes on data acknowledgment
In slave mode, a data acknowledgment is generated in either of the following cases:
- When the received address matches the value in the address register (IAAR0) and
IBCR00:AACKX = 0.
- When a general call address (00H) is received and IBCR10:GACKE = 1.
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24.8 Notes on Using I2C Interface
MB95410H/470H Series
● Notes on selecting the transfer complete timing
• The transfer complete timing select bit (IBCR00:INTS) is valid only during data reception
(IBSR10:TRX = 0 and IBSR10:FBT = 0).
• In cases other than data reception (IBSR10:TRX = 1 or IBSR10:FBT = 1), the transfer
completion interrupt (IBCR10:INT) is always generated in the ninth SCL cycle.
• If the data ACK depends on the content of the received data (such as packet error checking
used by the SM bus), control the data ACK by setting the data ACK enable bit
(IBCR10:DACKE) after writing "1" to the IBCR00:INTS bit (for example, using a previous
transfer completion interrupt) to read latest received data.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received
(IBSR0:LRB must be read during the transfer completion interrupt in the ninth SCL cycle.)
If ACK is read when the IBCR0:INTS bit is "1", therefore, you must write "0" to the
IBCR00:INTS bit in the transfer completion interrupt in the eighth SCL cycle so that
another transfer completion interrupt will occur in the ninth SCL cycle.
● Notes on using the MCU standby mode wakeup function
• Set IBCR00:WUE to "1" immediately prior to setting the MCU to stop or watch mode.
Similarly, clear IBCR00:WUE (by writing "0") after the MCU wakes up from stop or watch
mode so that I2C operation can restart as soon as possible.
• When a wakeup interrupt request occurs, the MCU wakes up after the oscillation
stabilization wait time elapses. To prevent the data loss immediately after wakeup, design
the system so that the SCL rises as the first cycle and the first bit must be transmitted as
data after 100 μs (assuming a minimum oscillation stabilization wait time of 100 μs) from
the wakeup due to start of I2C transmission (upon detection of the falling edge of SDA).
• During a MCU standby mode, the status flags, state machine, and I2C bus outputs for the
I2C function retain the states they had prior to entering the standby mode. To prevent a
hang-up of the entire I2C bus system, make sure that IBSR0:BB = 0 before entering standby
mode.
• The wakeup function does not support the transition of the MCU to stop or watch mode
with IBSR0:BB = 1. If the MCU enters stop or watch mode with IBSR0:BB = 1, a bus error
will occur upon detection of a start condition.
• In PLL stop mode, for example, the time from wakeup to the start of communication
becomes longer than in stop/watch mode by the PLL oscillation stabilization wait time as
the PLL oscillation stabilization wait time is required in addition to the oscillation
stabilization wait time.
• To ensure correct operation of the I2C interface, always clear IBCR00:WUE to "0" after the
MCU wakes up from stop or watch mode, regardless of whether this occurs due to the I2C
wakeup function or the wakeup function for some other resource (such as an external
interrupt).
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CHAPTER 24 I2C
24.9 Sample Settings for I2C
MB95410H/470H Series
24.9
Sample Settings for I2C
This section provides sample settings for the I2C interface.
■ Sample Settings
● Enabling/disabling I2C operation
Use the I2C operation enable bit (ICCR0:EN).
Operation
I2C operation enable bit (EN)
To disable I2C operation
Set the bit to "0".
To enable I2C operation
Set the bit to "1".
● Selecting the I2C master or slave mode
Use the master/slave select bit (IBCR10:MSS).
Operation
Master/slave select bit (MSS)
To select master mode
Set the bit to "1".
To select slave mode
Set the bit to "0".
● Selecting the shift clock
Use the clock select bits (ICCR0:CS4/CS3/CS2/CS1/CS0).
● Bypassing the m divider when the shift clock frequency is generated
Use the divider-m bypass bit (ICCR0:DMBP).
Operation
Divider m bypass bit (DMBP)
To bypass divider m
Set the bit to "1".
● Controlling I2C address acknowledgment
Use the address acknowledge disable bit (IBCR00:AACKX).
Operation
Address acknowledge disable bit (AACKX)
To enable address acknowledge
output
Set the bit to "0".
To disable address acknowledge
output
Set the bit to "1".
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24.9 Sample Settings for I2C
MB95410H/470H Series
● Controlling I2C data acknowledgment
Use the data acknowledge enable bit (IBCR10:DACKE).
Operation
Data acknowledge enable bit (DACKE)
To enable data acknowledge
output
Set the bit to "1".
To disable data acknowledge
output
Set the bit to "0".
● Controlling I2C general call address acknowledgment
Use the general call address acknowledge enable bit (IBCR10:GACKE).
Operation
General call address acknowledge enable bit
(GACKE)
To enable general call address
acknowledge output
Set the bit to "1".
To disable general call address
acknowledge output
Set the bit to "0".
● Restarting I2C communication
Use the start condition generation bit (IBCR10:SCC).
Operation
Start condition generation bit (SCC)
To restart communication
Set the bit to "1".
● Selecting the I2C data reception transfer completion flag (INT)
Use the timing select bit (IBCR00:INTS) for the data reception transfer completion flag (INT).
Operation
Timing select bit (INTS) for data reception transfer
completion flag (INT)
To cause a transfer interrupt in
the 9th SCL cycle
Set the bit to "0".
To cause a transfer interrupt in
the 8th SCL cycle
Set the bit to "1".
● Interrupt related register
To set the interrupt level, use the following interrupt level setting register.
574
Interrupt source
Interrupt level setting register
Interrupt vector
ch. 0
Interrupt level setting register (ILR4)
Address: 0007DH
#16
Address: 0FFDAH
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24.9 Sample Settings for I2C
MB95410H/470H Series
● Enabling, disabling, and clearing interrupts
Interrupt request enable flag and interrupt request flag
• Transfer interrupt
(Data transfer completion interrupt)
To enable interrupts, use the transfer completion interrupt enable bit (IBCR10:INTE).
Operation
Transfer completion interrupt enable bit (INTE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
To clear interrupt requests, use the transfer completion interrupt request flag bit
(IBCR10:INT).
Operation
Transfer completion interrupt request flag bit (INT)
To clear an interrupt request
Set the bit to "0".
(Bus error generation interrupt)
To enable interrupts, use the bus error interrupt request enable bit (IBCR10:BEIE).
Operation
Bus error interrupt request enable bit (BEIE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
To clear interrupt requests, use the bus error interrupt request flag bit (IBCR10:BER).
Operation
Bus error interrupt request flag bit (BER)
To clear an interrupt request
Set the bit to "0".
• Stop interrupt
(Stop condition detection interrupt)
To enable interrupts, use the STOP detection interrupt enable bit (IBCR00:SPE).
Operation
STOP detection interrupt enable bit (SPE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
To clear interrupt requests, use the STOP detection interrupt request flag bit (IBCR00:SPF).
Operation
STOP detection interrupt request flag bit (SPF)
To clear an interrupt request
Set the bit to "0".
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24.9 Sample Settings for I2C
MB95410H/470H Series
(Arbitration lost detection interrupt)
To enable interrupts, use the arbitration lost interrupt enable bit (IBCR00:ALE).
Operation
Arbitration lost interrupt enable bit (ALE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
To clear interrupt requests, use the arbitration lost interrupt request flag bit (IBCR00:ALF).
Operation
Arbitration lost interrupt request flag bit (ALF)
To clear an interrupt request
Write "0" to the flag.
(Start condition detection interrupt)
To enable interrupts, use the MCU standby-mode wakeup function enable bit
(IBCR00:WUE).
Operation
MCU standby-mode wakeup function enable bit
(WUE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
To clear interrupt requests, use the MCU standby-mode wakeup interrupt request flag bit
(IBCR00:WUF).
576
Operation
MCU standby-mode wakeup interrupt request flag bit
(WUF)
To clear an interrupt request
Set the bit to "0".
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CHAPTER 25
8/10-BIT A/D CONVERTER
This chapter describes the functions and
operations of the 8/10-bit A/D converter.
25.1 Overview of 8/10-bit A/D Converter
25.2 Configuration of 8/10-bit A/D Converter
25.3 Pins of 8/10-bit A/D Converter
25.4 Registers of 8/10-bit A/D Converter
25.5 Interrupts of 8/10-bit A/D Converter
25.6 Operations of 8/10-bit A/D Converter and Setting
Procedure Example
25.7 Notes on Using 8/10-bit A/D Converter
25.8 Sample Settings for 8/10-bit A/D Converter
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.1 Overview of 8/10-bit A/D Converter
25.1
MB95410H/470H Series
Overview of 8/10-bit A/D Converter
The 8/10-bit A/D converter is a 10-bit successive approximation type of 8/10-bit
A/D converter. It can be started by the software and internal clock, with one
input signal selected from multiple analog input pins.
■ A/D Conversion Function
The A/D converter converts analog voltage (input voltage) input through an analog input pin to
an 8-bit or 10-bit digital value.
• The input signal can be selected from multiple analog input pins.
• The conversion speed can be set in a program. (can be selected according to operating
voltage and frequency).
• An interrupt is generated when A/D conversion is completed.
• The completion of conversion can be determined according to the ADI bit in the ADC1
register.
To activate the A/D conversion function, use one of the following methods.
• Activation using the AD bit in the ADC1 register
• Continuous activation using the external pin (ADTG)
• Continuous activation using the 8/16-bit composite timer output TO00
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25.2 Configuration of 8/10-bit A/D Converter
MB95410H/470H Series
25.2
Configuration of 8/10-bit A/D Converter
The 8/10-bit A/D converter consists of the following blocks:
• Clock selector (input clock selector for starting A/D conversion)
• Analog channel selector
• Sample-and-hold circuit
• Control circuit
• 8/10-bit A/D converter data registers (ADDH/ADDL)
• 8/10-bit A/D converter control register 1 (ADC1)
• 8/10-bit A/D converter control register 2 (ADC2)
■ Block Diagram of 8/10-bit A/D Converter
Figure 25.2-1 is the block diagram of the 8/10-bit A/D converter.
Figure 25.2-1 Block Diagram of 8/10-bit A/D Converter
8/10-bit A/D converter control register 2 (ADC2)
AD8
8/16-bit
composite timer
output pin (TO00)
AN00 to AN07
TIM0
ADCK
ADIE
EXT CKDIV1 CKDIV0
Startup
signal
selector
Analog
channel
selector
Sampleand-hold
circuit
Internal data bus
ADTG pin
TIM1
Control circuit
8/10-bit A/D converter data
registers (ADDH/ADDL)
ANS3
ANS2
ANS1
ANS0
ADI
ADMV ADMVX
AD
8/10-bit A/D converter control register 1 (ADC1)
IRQ
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25.2 Configuration of 8/10-bit A/D Converter
MB95410H/470H Series
● Clock selector
This selects the A/D conversion clock with continuous activation having been enabled
(ADC2:EXT = 1).
● Analog channel selector
This is the circuit selecting an input channel from several analog input pins.
● Sample-and-hold circuit
This circuit holds input voltage selected by the analog channel selector. By sampling the input
voltage and holding it immediately after A/D conversion starts, this circuit prevents A/D
conversion from being affected by the fluctuation in input voltage during the conversion
(comparison).
● Control circuit
The A/D conversion function determines the values in the 10-bit A/D data register sequentially
from MSB to LSB based on the voltage compare signal from the comparator. When A/D
conversion is completed, the A/D conversion function sets the interrupt request flag bit (ADC1:
ADI) to "1".
● 8/10-bit A/D converter data registers (ADDH/ADDL)
The upper two bits of 10-bit A/D data are stored in the ADDH register; the lower eight bits in
the ADDL register.
If the A/D conversion precision bit (ADC2:AD8) is set to "1", the A/D conversion precision
becomes 8-bit precision, and the upper eight bits of 10-bit A/D data are to be stored in the
ADDL register.
● 8/10-bit A/D converter control register 1 (ADC1)
This register is used to enable and disable different functions, select an analog input pin, and
check the status of the A/D converter.
● 8/10-bit A/D converter control register 2 (ADC2)
This register is used to select an input clock, enable and disable interrupts and control different
A/D conversion functions.
■ Input Clock
The 8/10-bit A/D converter uses an output clock from the prescaler as the input clock
(operating clock).
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.3 Pins of 8/10-bit A/D Converter
MB95410H/470H Series
25.3
Pins of 8/10-bit A/D Converter
This section describes the pins of the 8/10-bit A/D converter.
■ Pins of 8/10-bit A/D Converter
The MB95410H/470H Series has 8 channels of analog input pin.
The analog input pins are also used as general-purpose I/O ports.
● AN07 pin to AN00 pin
AN07 to AN00:
When using the A/D conversion function, input to one of these pins the
analog voltage to be converted. A pin of AN07 to AN00 functions as an
analog input pin if the bit in the port direction register (DDR) corresponding
to that pin is set to "0" and the analog input pin select bits (ADC1:ANS0 to
ANS3) are set to the values representing that pin. A pin not used as an
analog input pin can be used as a general-purpose I/O port also when the 8/
10-bit A/D converter is used.
● ADTG pin
ADTG:
This is a pin used to activate the A/D conversion function with an external
trigger. Before using the ADTG pin for activating the A/D conversion with
an external trigger, set the pin as an input port using the corresponding port
direction register (DDR).
● AVCC pin
AVCC:
This is an 8/10-bit A/D converter power supply pin. Use this at the same
potential as VCC. If A/D conversion precision is required, ensure that VCC
noise does not enter AVCC, or use a separate power source. Connect this pin
to a power source even when the 8/10-bit A/D converter is not in use.
● AVSS pin
AVSS:
This is a ground pin of the 8/10-bit A/D converter. Use this at the same
potential as VSS. If A/D conversion precision is required, ensure that VSS
noise does not enter AVSS. Connect this pin to a ground (GND) even when
the 8/10-bit A/D converter is not in use.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.3 Pins of 8/10-bit A/D Converter
MB95410H/470H Series
■ Block Diagram of Pins of 8/10-bit A/D Converter
Figure 25.3-1 Block Diagram of AN01 and AN04 of 8/10-bit A/D Converter
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
CMOS
Peripheral function output
0
1
PDR read
1
Hysteresis
pin
PDR
0
PDR write
Executing bit manipulation instruction
Only for INT01
and INT04
Internal bus
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
ILSR read
ILSR
ILSR write
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25.3 Pins of 8/10-bit A/D Converter
MB95410H/470H Series
Figure 25.3-2 Block Diagram of AN00, AN02, AN03, AN05, AN06 and AN07 of 8/10-bit A/D
Converter
LCD output
A/D analog input
LCD output enable
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
0
1
PDR read
1
pin
PDR
0
PDR write
Internal bus
Executing bit manipulation instruction
Only for INT00,
INT02, INT03,
INT05 to INT07
DDR read
DDR
DDR write
Stop, Watch (SPL=1)
AIDR read
AIDR
AIDR write
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.4 Registers of 8/10-bit A/D Converter
25.4
MB95410H/470H Series
Registers of 8/10-bit A/D Converter
The 8/10-bit A/D converter has four registers: A/D converter control register 1
(ADC1), A/D converter control register 2 (ADC2), A/D converter data register
upper (ADDH) and A/D converter data register lower (ADDL).
■ Registers of 8/10-bit A/D Converter
Figure 25.4-1 lists the registers of the 8/10-bit A/D converter.
Figure 25.4-1 Registers of 8/10-bit A/D Converter.
8/10-bit A/D converter control register 1 (ADC1)
Address
bit7
bit6
bit5
bit4
bit3
bit2
006CH
ANS3
ANS2
ANS1
ANS0
ADI
ADMV
R/W
R/W
R/W
R/W R(RM1),W R/WX
bit1
ADMVX
R/W
8/10-bit A/D converter control register 2 (ADC2)
Address
bit7
bit6
bit5
bit4
006DH
AD8
TIM1
TIM0
ADCK
R/W
R/W
R/W
R/W
bit1
bit0
CKDIV1 CKDIV0
R/W
R/W
bit2
EXT
R/W
Initial value
00000000B
Initial value
00000000B
8/10-bit A/D converter data register upper (ADDH)
Address
bit7
bit6
bit5
bit4
bit3
006EH
R0/WX R0/WX R0/WX R0/WX R0/WX
bit2
R0/WX
bit1
SAR9
R/WX
bit0
SAR8
R/WX
Initial value
00000000B
8/10-bit A/D converter data register lower (ADDL)
Address
bit7
bit6
bit5
bit4
bit3
006FH
SAR7
SAR6
SAR5
SAR4
SAR3
R/WX
R/WX
R/WX
R/WX
R/WX
bit2
SAR2
R/WX
bit1
SAR1
R/WX
bit0
SAR0
R/WX
Initial value
00000000B
R/W
R(RM1), W
R/WX
R0,W
R0/WX
-
584
bit3
ADIE
R/W
bit0
AD
R0,W
: Readable/writable (The read value is the same as the write value.)
: Readable/writable (The read value is different from the write value. "1" is read by the
read-modify-write (RMW) type of instruction.)
: Read only (Readable. Writing a value to this bit has no effect on operation.)
: Write only (Writable. The read value is "0".)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.4 Registers of 8/10-bit A/D Converter
MB95410H/470H Series
25.4.1
8/10-bit A/D Converter Control Register 1 (ADC1)
The 8/10-bit A/D converter control register 1 (ADC1) is used to enable and
disable individual functions of the 8/10-bit A/D converter, select an analog input
pin and check the status of the converter.
■ 8/10-bit A/D Converter Control Register 1 (ADC1)
Figure 25.4-2 8/10-bit A/D Converter Control Register 1 (ADC1)
Address
bit7
bit6
bit5
bit4
bit3
006CH
ANS3
ANS2
ANS1
ANS0
ADI
R/W
R/W
R/W
bit2
bit1
ADMV ADMVX
R/W R(RM1),W R/WX
R/W
bit0
Initial value
AD
00000000B
R0,W
AD
0
1
A/D conversion start bit
Do not start A/D conversion.
Start A/D conversion.
ADMVX
0
1
Current cutoff analog switch control bit
Turn on the analog switch only during conversion.
Always turn on the analog switch.
ADMV
0
1
Conversion flag bit
No conversion
Conversion in progress
ADI
Interrupt request flag bit
Read
Write
0
Conversion not completed
1
Conversion completed
ANS3 ANS2 ANS1 ANS0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Clears this bit.
Writing “1” does not change
ADI or affect other bits.
Analog input pin select bits
AN00 pin
AN01 pin
AN02 pin
AN03 pin
AN04 pin
AN05 pin
AN06 pin
AN07 pin
: Readable/writable (The read value is the same as the write value.)
R/W
R(RM1),W : Readable/writable (The read value is different from the write value. “1” is read by
the read-modify-write (RMW) type of instruction.)
R/WX
R0,W
: Read only (Readable. Writing a value to this bit has no effect on operation.)
: Write only (Writable. The read value is “0”.)
: Initial value
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.4 Registers of 8/10-bit A/D Converter
MB95410H/470H Series
Table 25.4-1 Functions of Bits in 8/10-bit A/D Converter Control Register 1 (ADC1)
Bit name
bit7
to
bit4
Function
These bits select an analog input pin to be used from AN00 to AN07.
ANS3, ANS2,
When A/D conversion is started (AD = 1) by the software (ADC2:EXT = 0), these bits can
ANS1, ANS0:
be modified simultaneously.
Analog input pin select
Note:
When the ADMV bit is "1", do not modify these bits.
bits
Pins not used as analog input pins can be used as general-purpose ports.
bit3
ADI:
Interrupt request flag
bit
This bit detects the completion of A/D conversion.
• When the A/D conversion function is used, the bit is set to "1" immediately after A/D
conversion is complete.
• Interrupt requests are output when this bit and the interrupt request enable bit
(ADC2:ADIE) are both set to "1".
• When "0" is written to this bit, it is cleared. Writing "1" to this bit does not change it or
affect other bits.
• When read by the read-modify-write (RMW) type of instruction, this bit returns "1".
bit2
ADMV:
Conversion flag bit
This bit indicates that A/D conversion is in progress.
The bit is set to "1" during A/D conversion.
This bit is read-only. A value written to this bit is meaningless and has no effect on
operation.
bit1
ADMVX:
Current cutoff analog
switch control bit
This bit controls the analog switch for cutting off the internal reference power supply.
Since rush current flows immediately after A/D conversion starts, when the external
impedance of Vcc pin is high, A/D conversion precision may be affected. This can be
avoided by setting this bit to "1" before A/D conversion starts. In addition, in order to
reduce current consumption, set the bit to "0" before transiting to standby mode.
AD:
A/D conversion start
bit
This bit activates A/D conversion function with the software.
Writing "1" to the bit activates the A/D conversion function.
When EXT = 1, starting the A/D conversion with this bit is disabled.
With EXT = 0, when "1" is written to this bit while A/D conversion is in progress, A/D
conversion restarts.
Note:
Writing "0" to this bit cannot stop the operation of the A/D conversion function.
The read value of this bit is always "0".
bit0
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25.4 Registers of 8/10-bit A/D Converter
MB95410H/470H Series
25.4.2
8/10-bit A/D Converter Control Register 2 (ADC2)
The 8/10-bit A/D converter control register 2 (ADC2) is used to control different
functions of the 8/10-bit A/D converter, select the input clock, enable and
disable interrupts.
■ 8/10-bit A/D Converter Control Register 2 (ADC2)
Figure 25.4-3 8/10-bit A/D Converter Control Register 2 (ADC2)
Address
bit7
bit6
bit5
006DH
AD8
TIM1
TIM0
R/W
R/W
R/W
bit4
bit3
ADCK ADIE
R/W
R/W
CKDIV1 CKDIV0
0
0
1
1
EXT
0
1
0
1
0
1
bit2
bit1
bit0
EXT CKDIV1 CKDIV0
R/W
R/W
Initial value
00000000B
R/W
Clock (CKIN) select bits
1 × MCLK
1/2 × MCLK
1/4 × MCLK
1/8 × MCLK
Continuous activation enable bit
Start by the AD bit in ADC1 register
Continuous activation by the clock selected by the ADCK bit in the ADC2 register
Interrupt request enable bit
Disables interrupt request output.
Enables interrupt request output.
ADIE
0
1
ADCK
External start signal select bit
0
Starts via the ADTG input pin.
1
Starts by 8/16-bit composite timer output pin (TO00).
TIM1
0
0
1
1
AD8
0
1
MCLK
R/W
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TIM0
0
1
0
1
Sampling time select bits
CKIN × 4
CKIN × 7
CKIN × 10
CKIN × 16
Precision select bit
10-bit precision
8-bit precision
: Machine clock
: Readable/writable (The read value is the same as the write value.)
: Initial value
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25.4 Registers of 8/10-bit A/D Converter
MB95410H/470H Series
Table 25.4-2 Functions of Bits in 8/10-bit A/D Converter Control Register 2 (ADC2)
Bit name
Function
bit7
AD8:
Precision select bit
This bit selects the resolution of A/D conversion.
Writing "0": Selects 10-bit precision.
Writing "1": Selects 8-bit precision. Reading the ADDL register can obtain 8-bit data.
Note:
The data bits to be used are different depending on the resolution selected.
Modify this bit only when the A/D converter has stopped operating.
bit6,
bit5
TIM1, TIM0:
Sampling time select
bits
These bits set the sampling time.
• Modify the sampling time according to operating conditions (voltage and frequency).
• The CKIN value is determined by the clock select bits (ADC2:CKDIV1, CKDIV0).
Note:
Modify these bits only when the A/D converter has stopped operating.
ADCK:
External start signal
select bit
This bit selects the start signal for external start (ADC2:EXT = 1).
bit4
bit3
ADIE:
Interrupt request
enable bit
This bit enables or disables outputting interrupts to the interrupt controller.
• Interrupt requests are output when both this bit and the interrupt request flag bit (ADC1:
ADI) have been set to "1".
bit2
EXT:
Continuous activation
enable bit
This bit selects whether to activate the A/D conversion function with the software, or to
continuously activate the A/D conversion function whenever a rising edge of the input clock
is detected.
bit1,
bit0
CKDIV1,
CKDIV0:
Clock select bits
These bits select the clock to be used for A/D conversion. The input clock is generated by
the prescaler. See "CHAPTER 6 CLOCK CONTROLLER" for details.
• The sampling time varies according to the clock selected by these bits.
• Modify these bits according to operating conditions (voltage and frequency).
Note:
Modify these bits only when the A/D converter has stopped operating.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.4 Registers of 8/10-bit A/D Converter
MB95410H/470H Series
25.4.3
8/10-bit A/D Converter Data Registers Upper/
Lower (ADDH/ADDL)
The 8/10-bit A/D converter data registers upper/lower (ADDH, ADDL) store the
results of 10-bit A/D conversion during 10-bit A/D conversion.
The upper two bits of 10-bit data are stored in the ADDH register and the lower
eight bits the ADDL register.
■ 8/10-bit A/D Converter Data Registers Upper/Lower (ADDH, ADDL)
Figure 25.4-4 8/10-bit A/D Converter Data Registers Upper/Lower (ADDH, ADDL)
ADDH
bit7
bit6
bit5
bit4
bit3
bit2
Address
006EH R0/WX R0/WX R0/WX R0/WX R0/WX R0/WX
bit1
SAR9
R/WX
bit0
SAR8
R/WX
Initial value
00000000B
ADDL
Address
006FH
bit1
SAR1
R/WX
bit0
SAR0
R/WX
Initial value
00000000B
R/WX
R0/WX
-
bit7
SAR7
R/WX
bit6
SAR6
R/WX
bit5
SAR5
R/WX
bit4
SAR4
R/WX
bit3
SAR3
R/WX
bit2
SAR2
R/WX
: Read only (Readable. Writing a value to this bit has no effect on operation.)
: The read value is "0". Writing a value to this bit has no effect on operation.
: Undefined bit
The upper two bits of 10-bit A/D data correspond to bit1 and bit0 in the ADDH register and the
lower eight bits bit7 to bit0 in the ADDL register.
If the AD8 bit in ADC2 register is set to "1", 8-bit precision is selected. Reading the ADDL
register can obtain 8-bit data.
These two registers are read-only registers. Writing data to them has no effect on operation.
In A/D conversion in which 8-bit precision is selected, SAR8 and SAR9 in the ADDH register
become "0".
● A/D conversion function
When A/D conversion is started, the results of conversion are finalized and stored in the
ADDH and ADDL registers after the conversion time according to the register settings elapses.
After A/D conversion is completed and before the next A/D conversion is completed, read A/D
data registers (conversion results), and clear the interrupt request flag bit (ADI) in the ADC1
register. During A/D conversion, the values of the ADDH and ADDL registers are results of
the last A/D conversion.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.5 Interrupts of 8/10-bit A/D Converter
25.5
MB95410H/470H Series
Interrupts of 8/10-bit A/D Converter
The completion of conversion during the operation of the A/D converter is an
interrupt source of the 8/10-bit A/D converter.
■ Interrupts During 8/10-bit A/D Converter Operation
When A/D conversion is completed, the interrupt request flag bit (ADC1:ADI) is set to "1".
Then if the interrupt request enable bit has been enabled (ADC2:ADIE = 1), an interrupt
request is made to the interrupt controller. Write "0" to the ADI bit using the interrupt service
routine to clear the interrupt request.
The ADI bit is set to "1" when A/D conversion is completed, irrespective of the value of the
ADIE bit.
The CPU cannot return from interrupt processing if the interrupt request flag bit (ADC1: ADI)
is "1" with interrupt requests having been enabled (ADC2:ADIE = 1). Always clear the ADI bit
in the interrupt service routine.
■ Register and Vector Table Addresses Related to 8/10-bit A/D Converter
Interrupts
Table 25.5-1 Register and Vector Table Addresses Related to 8/10-bit A/D Converter Interrupts
Interrupt source
Interrupt
request no.
8/10-bit A/D converter
IRQ18
Interrupt level setting register
Vector table address
Register
Setting bit
Upper
Lower
ILR4
L18
FFD6H
FFD7H
See "APPENDIX B Table of Interrupt Sources" for the respective interrupt request numbers
and vector table addresses of different peripheral functions.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.6 Operations of 8/10-bit A/D Converter and Setting
Procedure Example
MB95410H/470H Series
25.6
Operations of 8/10-bit A/D Converter and Setting
Procedure Example
The 8/10-bit A/D converter can activate A/D conversion with the software or
activate A/D conversion continuously according to the setting of the EXT bit in
the ADC2 register.
■ Operations of 8/10-bit A/D Converter Conversion Function
● Software activation
To activate the A/D conversion function with the software, do the settings shown in
Figure 25.6-1.
Figure 25.6-1 Settings for A/D Conversion Function (Software Activation)
ADC1
bit7
ANS3
bit6
ANS2
bit5
ANS1
bit4
ANS0
bit3
ADI
bit2
ADMV
ADC2
AD8
TIM1
TIM0
ADCK
×
ADIE
EXT
0
CKDIV1 CKDIV0
ADDH
-
-
-
-
-
-
A/D converted value retained
ADDL
bit1
ADMVX
bit0
AD
1
A/D converted value retained
: Bit to be used
× : Unused bit
1 : Set to "1"
0 : Set to "0"
When the A/D conversion function is activated, A/D conversion starts. In addition, the A/D
conversion function can be re-activated even during conversion.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.6 Operations of 8/10-bit A/D Converter and Setting
Procedure Example
● Continuous activation
MB95410H/470H Series
To execute continuous activation of the A/D conversion function, do the settings shown in
Figure 25.6-2.
Figure 25.6-2 Settings for A/D Conversion Function (Continuous Activation)
ADC1
bit7
ANS3
bit6
ANS2
bit5
ANS1
bit4
ANS0
bit3
ADI
bit2
ADMV
ADC2
AD8
TIM1
TIM0
ADCK
ADIE
EXT
1
CKDIV1 CKDIV0
ADDH
-
-
-
-
-
-
A/D converted value retained
ADDL
bit1
ADMVX
bit0
AD
×
A/D converted value retained
: Bit to be used
× : Unused bit
1 : Set to "1"
When continuous activation is enabled, the A/D conversion function is activated at the rising
edge of the input clock selected to start A/D conversion. Continuous activation is stopped when
disabled (ADC2:EXT = 0).
■ Operations of A/D Conversion Function
This section explains the operations of 8/10-bit A/D converter.
1) When A/D conversion is started, the conversion flag bit is set (ADC1:ADMV = 1) and the
selected analog input pin is connected to the sample-and-hold circuit.
2) The voltage in the analog input pin is loaded into a sample-and-hold capacitor in the
sample-and-hold circuit during the sampling cycle. This voltage is held until A/D
conversion is completed.
3) The comparator in the control circuit compares the voltage loaded into sample-and-hold
capacitor with the A/D conversion reference voltage, from the most significant bit (MSB) to
the least significant bit (LSB), and then transfers the results to the ADDH and ADDL
registers.
After the results have been transferred to the two registers, the conversion flag bit is cleared
(ADC1:ADMV = 0) and the interrupt request flag bit is set to "1" (ADC1:ADI = 1).
Notes:
• The contents of the ADDH and ADDL registers are retained until the end of A/D
conversion. Therefore, during A/D conversion, the values resulting from last
conversion will be returned if the two registers are read.
• Do not change the analog input pin (ADC1:ANS3 to ANS0) while AD conversion
function is being used. During continuous activation in particular, disable continuous
activation (ADC2:EXT = 0) before changing the analog input pin.
• The start of the reset mode, the stop mode or the watch mode causes the A/D
converter to stop and the ADMV bit to be cleared to "0".
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■ Setting Procedure Example
CHAPTER 25 8/10-BIT A/D CONVERTER
25.6 Operations of 8/10-bit A/D Converter and Setting
Procedure Example
Below is an example of procedure for setting the 8/10-bit A/D converter:
● Initial settings
1) Set the input port (DDR0).
2) Set the interrupt level (ILR4).
3) Enable A/D input (ADC1:ANS0 to ANS3).
4) Set the sampling time (ADC2:TIM1, TIM0).
5) Select the clock (ADC2:CKDIV1, CKDIV0).
6) Set A/D conversion precision (ADC2:AD8).
7) Select the operating mode (ADC2:EXT).
8) Select the start trigger (ADC2:ADCK).
9) Enable interrupts (ADC2:ADIE = 1).
10)Activate the A/D conversion function (ADC1:AD = 1).
● Interrupt processing
1) Clear the interrupt request flag (ADC1:ADI = 0).
2) Read converted values (ADDH, ADDL).
3) Activate the A/D conversion function (ADC1:AD = 1).
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.7 Notes on Using 8/10-bit A/D Converter
25.7
MB95410H/470H Series
Notes on Using 8/10-bit A/D Converter
This section provides notes on using the 8/10-bit A/D converter.
■ Notes on Using 8/10-bit A/D Converter
● Notes on setting the 8/10-bit A/D converter with a program
• The contents of the ADDH and ADDL registers are retained until the end of A/D
conversion. Therefore, during A/D conversion, the values resulting from last conversion
will be returned if the two registers are read.
• Do not change the analog input pin (ADC1:ANS3 to ANS0) while AD conversion function
is being used. During continuous activation in particular, disable continuous activation
(ADC2:EXT = 0) before changing the analog input pin.
• A reset, or the start of the stop mode or watch mode causes the A/D converter to stop and
the ADMV bit to be cleared to "0".
• The CPU cannot return from interrupt processing if the interrupt request flag bit
(ADC1:ADI) is "1" with interrupt requests having been enabled (ADC2:ADIE = 1). Always
clear the ADI bit in the interrupt service routine.
● Note on interrupt requests
If the restart of A/D conversion (ADC1:AD = 1) and the completion of A/D conversion occur
simultaneously, the interrupt request flag bit (ADC1:ADI) is set.
● A/D conversion error
As | Vcc - Vss | decreases, the A/D conversion error increases proportionately.
● 8/10-bit A/D converter analog input sequences
Apply the analog input (AN00 to AN07) and the digital power supply (VCC) simultaneously, or
apply the analog input after applying the digital power supply.
Disconnect the digital power supply (VCC) at the same time as the analog input (AN00 to
AN07), or after disconnecting analog input (AN00 to AN07).
Ensure that the analog input voltage does not exceed the voltage of digital power supply when
turning on or off the power of the 8/10-bit A/D converter.
● Conversion time
The conversion speed of A/D conversion function is affected by clock mode, main clock
oscillation frequency and main clock speed switching (gear function).
Example: Sampling time = CKIN × (ADC2:TIM1/TIM0 setting)
Compare time = CKIN × 10 (fixed value) + MCLK
A/D converter startup time:
minimum = MCLK + MCLK
maximum =MCLK + CKIN
Conversion time = A/D converter startup time + sampling time + compare time
• The conversion time may have an error of up to (1 CKIN – 1 MCLK), depending on the
time at which A/D conversion starts.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.7 Notes on Using 8/10-bit A/D Converter
• When setting the A/D converter in software, ensure that the settings satisfy the
specifications of "sampling time" and "compare time" of the A/D converter mentioned in
the data sheet of the MB95410H/470H Series.
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.8 Sample Settings for 8/10-bit A/D Converter
25.8
MB95410H/470H Series
Sample Settings for 8/10-bit A/D Converter
This section provides sample settings for the 8/10-bit A/D converter.
■ Sample Settings
● Method of selecting an operating clock for the 8/10-bit A/D converter
Use the clock select bits (ADC2:CKDIV1, CKDIV0) to select an operating clock.
● Method of selecting the sampling time of the 8/10-bit A/D converter
Use the sampling time select bits (ADC2:TIM1, TIM0) to select sampling time.
● Method of controlling the analog switch for cutting off the internal reference power supply of
the 8/10-bit A/D converter
Use the current cutoff analog switch control bit (ADC1:ADMVX) to control the analog switch
for cutting off internal reference power supply.
Operation
Current cutoff analog switch control bit (ADMVX)
To switch off internal reference
power supply
Set the bit to "0".
To switch on internal reference
power supply
Set the bit to "1".
● Method of selecting the method of activating the 8/10-bit A/D conversion function
Use the continuous activation enable bit (ADC2:EXT) to select an activation trigger.
A/D conversion activation
source
Continuous activation enable bit (EXT)
To select the software trigger
Set the bit to "0".
To select the input clock rising
signal
Set the bit to "1".
• Method of generating a software trigger
Use the A/D conversion start bit (ADC1:AD) to generate a software trigger.
596
Operation
A/D conversion start bit (AD)
To generate a software trigger
Set the bit to "1".
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.8 Sample Settings for 8/10-bit A/D Converter
• Method of activating the A/D conversion function using the input clock
An activation trigger is generated at the rising edge of the input clock.
To select the input clock, use external start signal select bit (ADC2:ADCK).
Input clock
External start signal select bit (ADCK)
Do not use any external start
signal
Set the bit to "0".
To select the 8/16-bit composite
timer output pin (TO00)
Set the bit to "1".
● Method of selecting A/D conversion precision
Use the precision select bit (ADC2:AD8) to select the precision of conversion results.
Operation
Precision select bit (AD8)
To select 10-bit precision
Set the bit to "0".
To select 8-bit precision
Set the bit to "1".
● Method of using analog input pins
Use the analog input pin select bits (ADC1:ANS3 to ANS0) to select an analog input pin.
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Operation
Analog input pin select bits (ANS3 to ANS0)
To use the AN00 pin
Set the bits to "0000B".
To use the AN01 pin
Set the bits to "0001B".
To use the AN02 pin
Set the bits to "0010B".
To use the AN03 pin
Set the bits to "0011B".
To use the AN04 pin
Set the bits to "0100B".
To use the AN05 pin
Set the bits to "0101B".
To use the AN06 pin
Set the bits to "0110B".
To use the AN07 pin
Set the bits to "0111B".
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CHAPTER 25 8/10-BIT A/D CONVERTER
25.8 Sample Settings for 8/10-bit A/D Converter
MB95410H/470H Series
● Method of checking the completion of conversion
There are two methods of checking whether conversion has been completed or not.
• Checking with the interrupt request flag bit (ADC1:ADI)
Interrupt request flag bit (ADI)
Meaning
The read value is "0".
No A/D conversion completion interrupt request
The read value is "1".
A/D conversion completion interrupt request made
• Checking with the conversion flag bit (ADC1:ADMV)
Conversion flag bit (ADMV)
Meaning
The read value is "0".
A/D conversion completed (stopped)
The read value is "1".
A/D conversion in progress
● Interrupted-related register
Use the following interrupt level setting register to set the interrupt level.
Interrupt source
Interrupt level setting register
Interrupt vector
8/10-bit AD converter
Interrupt level setting register (ILR4)
Address: 0007DH
#18
Address: 0FFD6H
● Method of enabling, disabling, and clearing interrupts
Use the interrupt request enable bit (ADC2:ADIE) to enable interrupts.
Operation
Interrupt request enable bit (ADIE)
To disable interrupt requests
Set the bit to "0".
To enable interrupt requests
Set the bit to "1".
Use the interrupt request bit (ADC1:ADI) to clear an interrupt request.
598
Operation
Interrupt request bit (ADI)
To clear an interrupt request
Set the bit to "0".
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CHAPTER 26
LOW-VOLTAGE
DETECTION RESET
CIRCUIT
This chapter describes the function and
operation of the low-voltage detection reset
circuit (only available on MB95F414K/F416K/
F418K/F474K/F476K/F478K).
26.1 Overview of Low-voltage Detection Reset Circuit
26.2 Configuration of Low-voltage Detection Reset Circuit
26.3 Pins of Low-voltage Detection Reset Circuit
26.4 Operation of Low-voltage Detection Reset Circuit
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CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT
26.1 Overview of Low-voltage Detection Reset Circuit
26.1
MB95410H/470H Series
Overview of Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit monitors power supply voltage and
generates a reset signal if the power supply voltage drops below the lowvoltage detection voltage level.
This circuit is only available on MB95F414K/F416K/F418K/F474K/F476K/F478K.
■ Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit monitors power supply voltage and generates a reset
signal if the power supply voltage drops below the low-voltage detection voltage level.
This circuit is only available on MB95F414K/F416K/F418K/F474K/F476K/F478K.
Refer to the data sheet of the MB95410H/470H Series for details of the electrical
characteristics of this circuit.
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CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT
26.2 Configuration of Low-voltage Detection Reset Circuit
MB95410H/470H Series
26.2
Configuration of Low-voltage Detection Reset
Circuit
Figure 26.2-1 is the block diagram of the low-voltage detection reset circuit.
■ Block Diagram of Low-voltage Detection Reset Circuit
Figure 26.2-1 Block Diagram of Low-voltage Detection Reset Circuit
VCC
Reset signal
N-ch
Vref
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CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT
26.3 Pins of Low-voltage Detection Reset Circuit
26.3
MB95410H/470H Series
Pins of Low-voltage Detection Reset Circuit
This section describes the pins of the low-voltage detection reset circuit.
■ Pins of Low-voltage Detection Reset Circuit
● VCC pin
The low-voltage detection reset circuit monitors the voltage of this pin.
● VSS pin
This is the GND pin serving as the reference for voltage detection.
● RST pin
The low-voltage detection reset signal is output within the microcontroller and to this pin.
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CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT
26.4 Operation of Low-voltage Detection Reset Circuit
MB95410H/470H Series
26.4
Operation of Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit can generate a reset signal if the power
supply voltage drops below the low-voltage detection voltage.
■ Operation of Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit generates a reset signal if the power supply voltage falls
below the low-voltage detection voltage. Afterward, if the low-voltage detection reset circuit
detects the low-voltage detection reset release voltage, it outputs a reset signal lasting for the
oscillation stabilization wait time and then releases the reset.
For details of the electrical characteristics mentioned above, refer to the data sheet of the
MB95410H/470H Series.
Figure 26.4-1 Operation of Low-voltage Detection Reset
Vcc
Detection voltage/
reset release voltage
Operating voltage
lower limit
Reset signal
B
A
B
A
B
A
A: Delay
B: Oscillation stabilization wait time
■ Operation in Standby Mode
The low-voltage detection reset circuit keeps operating even in standby mode (stop mode, sleep
mode, subclock mode and watch mode).
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CHAPTER 26 LOW-VOLTAGE DETECTION RESET CIRCUIT
26.4 Operation of Low-voltage Detection Reset Circuit
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CHAPTER 27
CLOCK SUPERVISOR
COUNTER
This chapter describes the functions and
operations of the clock supervisor counter.
27.1 Overview of Clock Supervisor Counter
27.2 Configuration of Clock Supervisor Counter
27.3 Registers of Clock Supervisor Counter
27.4 Operations of Clock Supervisor Counter
27.5 Notes on Using Clock Supervisor Counter
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.1 Overview of Clock Supervisor Counter
27.1
MB95410H/470H Series
Overview of Clock Supervisor Counter
The clock supervisor counter can check the external clock frequency to detect
the abnormal state of the external clock.
■ Overview of Clock Supervisor Counter
The clock supervisor counter can check the external clock frequency to detect the abnormal
state of the external clock.
It counts up a built-in 8-bit counter according to the external clock input within a time-base
timer interval selected from eight options.
The count clock of this module can be selected from the main oscillation clock, the main PLL
clock and the suboscillation clock.
Note:
The clock supervisor counter must operate in main CR clock mode with the hardware
watchdog timer (running in standby mode).
Otherwise, it cannot detect the abnormal state of the external clock correctly and will
hang up if the external clock stops.
See "CHAPTER 12 HARDWARE/SOFTWARE WATCHDOG TIMER" for the hardware
watchdog timer (running in standby mode).
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.2 Configuration of Clock Supervisor Counter
MB95410H/470H Series
27.2
Configuration of Clock Supervisor Counter
The clock supervisor counter consists of the following blocks:
• Control circuit
• Clock Monitoring Control Register (CMCR)
• Clock Monitoring Data Register (CMDR)
• Time-base timer output selector
• Counter source clock selector
■ Block Diagram of Clock Supervisor Counter
Figure 27.2-1 is the block diagram of the clock supervisor counter.
Figure 27.2-1 Block Diagram of Clock Supervisor Counter
Edge detection
Time-base timer output
Time-base
Timer
Output
Selector
8-bit Counter
3
Main oscillation clock or
main PLL clock*
Suboscillation clock
Counter
Source
Clock
Selector
1st: counting starts
2nd: counting stops
CLK
Control Circuit
Counter enabled
Clock Monitoring Control Register (CMCR)
Clock Monitoring Data Register (CMDR)
Internal Bus
* : When the PLLC:PCS[1:0] bits are set to “00”, the main clock divided by 2 (FCH/2) is used as the count clock.
When the PLLC:PCS[1:0] bits are set to “01”, “10” or “11”, the main PLL clock is used as the count clock.
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.2 Configuration of Clock Supervisor Counter
MB95410H/470H Series
● Control circuit
This block controls the start and stop of the counter, the counter clock source, and the counter
enable period based on the settings of the clock monitoring control register (CMCR).
● Clock Monitoring Control Register (CMCR)
This register is used to select the counter source clock, select the counter enable period from
the eight different time-base timer intervals, start the counter and check whether the counter is
operating or not.
● Clock Monitoring Data Register (CMDR)
This register block is used to read the counter value after the counter stops. The software can
determine whether the external clock frequency is correct or not according to the contents of
this register.
● Time-base timer interval selector
This block is used to select the counter enable period from eight different time-base timer
intervals.
● Counter source clock selector
This block is used to select the counter source clock from the main oscillation clock, the main
PLL clock and the suboscillation clock.
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.3 Registers of Clock Supervisor Counter
MB95410H/470H Series
27.3
Registers of Clock Supervisor Counter
This section describes the registers of the clock supervisor counter.
■ Registers of Clock Supervisor Counter
Figure 27.3-1 shows the registers of the clock supervisor counter.
Figure 27.3-1 Clock Supervisor Counter Registers
Clock monitoring data register (CMDR)
Address
bit7
bit6
bit5
0FEAH
CMDR7 CMDR6 CMDR5
R/WX
R/WX
R/WX
bit4
CMDR4
R/WX
bit3
CMDR3
R/WX
bit2
CMDR2
R/WX
bit1
CMDR1
R/WX
bit0
CMDR0
R/WX
Clock monitoring control register (CMCR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0FE9H
Reserved CMCSEL TBTSEL2 TBTSEL1 TBTSEL0 CMCEN
R0/WX
R0/WX
R/W0
R/W
R/W
R/W
R/W
R/W
R/W
R/WX
R/W0
R0/WX
-
:
:
:
:
:
Initial value
00000000B
Initial value
00000000B
Readable/writable (The read value is the same as the write value.)
Read only (Readable. Writing a value to this bit has no effect on operation.)
The write value is "0". The read value is the same as the write value.
The read value is "0". Writing a value to this bit has no effect on operation.
Undefined bit
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.3 Registers of Clock Supervisor Counter
27.3.1
MB95410H/470H Series
Clock Monitoring Data Register (CMDR)
The clock monitoring data register (CMDR) is used to read the count value after
the clock supervisor counter stops. The software can determine whether the
external clock frequency is correct or not according to the content of this
register.
■ Clock Monitoring Data register (CMDR)
Figure 27.3-2 Clock Monitoring Data Register (CMDR)
Address
0FEAH
R/WX
bit7
CMDR7
R/WX
bit6
CMDR6
R/WX
bit5
CMDR5
R/WX
bit4
CMDR4
R/WX
bit3
CMDR3
R/WX
bit2
CMDR2
R/WX
bit1
CMDR1
R/WX
bit0
CMDR0
R/WX
Initial value
00000000B
: Read only (Readable. Writing a value to this bit has no effect on operation.)
The clock monitoring data register (CMDR) is used to read the counter value after the clock
supervisor counter stops.
• The counter value can be read from this clock monitoring data register (CMDR). The
software can check whether the external clock frequency is correct or not according to the
counter value read and the time-base timer interval selected.
Table 27.3-1 Functions of Bits in Clock Monitoring Data Register (CMDR)
Bit name
bit7
to
bit0
CMDR7 to CMDR0
Function
The CMDR register is a data register indicating the clock supervisor counter value after the
counter stops.
This register is cleared if one of the following events occurs:
• Reset
• The CMCEN bit is modified from "0" to "1" by the software.
• The CMCEN bit is modified from "1" to "0" by the software while the counter is running.
• After the external clock stops, the falling edge of the selected time-base timer clock is
detected twice (See Figure 27.5-2).
Note:
The value of this register is "0" as long as the counter is operating (CMCEN = 1).
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.3 Registers of Clock Supervisor Counter
MB95410H/470H Series
27.3.2
Clock Monitoring Control Register (CMCR)
The clock monitoring control register (CMCR) is used to select the counter
source clock, select the time-base timer interval as the counter enable period,
start the counter and check whether the counter is running or not.
■ Clock Monitoring Control register (CMCR)
Figure 27.3-3 Clock Monitoring Control Register (CMCR)
Address
0FE9H
bit7
R0/WX
bit6
R0/WX
bit5
Reserved
R/W0
bit4
CMCSEL
R/W
CMCEN
0
1
bit3
TBTSEL2
R/W
bit2
TBTSEL1
R/W
bit1
TBTSEL0
R/W
bit0
CMCEN
R/W
Initial value
00000000B
Counter enable bit
Disables the counter.
Enables the counter.
TBTSEL2
0
0
0
0
1
1
1
1
TBTSEL1
0
0
1
1
0
0
1
1
TBTSEL0
0
1
0
1
0
1
0
1
Time-base timer counter output select bits
23 × 1/FCRH
25 × 1/FCRH
27 × 1/FCRH
29 × 1/FCRH
211 × 1/FCRH
213 × 1/FCRH
215 × 1/FCRH
217 × 1/FCRH
CMCSEL
0
1
Counter clock select bit
Main oscillation clock or main PLL clock*
Suboscillation clock
Reserved
0
Always set this bit to “0”.
Reserved bit
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
Undefined bit
The read value is always “0”. Writing a value to this bit has no effect on operation.
R/W
R/W0
R0/WX
-
:
:
:
:
:
Readable/writable (The read value is the same as the write value.)
The write value is “0”. The read value is the same as the write value.
The read value is “0”. Writing a value to this bit has no effect on operation.
Undefined bit
Initial value
* : When the PLLC:PCS[1:0] bits are set to “00”, the main clock divided by 2 (FCH/2) is used as the count clock.
When the PLLC:PCS[1:0] bits are set to “01”, “10” or “11”, the main PLL clock is used as the count clock.
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.3 Registers of Clock Supervisor Counter
MB95410H/470H Series
Table 27.3-2 Functions of Bits in Clock Monitoring Control Register (CMCR)
Bit name
Function
bit7,
bit6
Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
bit5
Reserved bit
bit4
This bit selects the counter clock source.
CMCSEL:
Writing "0": Selects the main oscillation clock (PLLC:PCS[1:0] = 00) or the main PLL
Counter clock select bit
clock (PLLC:PCS[1:0] = 01, 10 or 11) as the source clock of the counter.
Writing "1": Selects the suboscillation clock as the source clock of the counter.
Always set this bit to "0".
These bits select the time-base timer interval.
The operation of the clock supervisor counter is enabled and disabled according to the timebase timer counter output selected by these bits.
The first rising edge of the interval selected enables the counter operation and the second
rising edge of the same output disables the counter operation.
TBTSEL2 TBTSEL1 TBTSEL0
bit3
to
bit1
bit0
TBTSEL2, TBTSEL1,
TBTSEL0:
Time-base timer
counter output select
bits
CMCEN:
Counter enable bit
Time-base timer counter output select bits
3
0
0
0
2 × 1/FCRH
0
0
1
25 × 1/FCRH
0
1
0
27 × 1/FCRH
0
1
1
29 × 1/FCRH
1
0
0
211 × 1/FCRH
1
0
1
213 × 1/FCRH
1
1
0
215 × 1/FCRH
1
1
1
217 × 1/FCRH
This bit enables and disables the clock supervisor counter.
Writing "0": Stops the counter and clears the CMDR register.
Writing "1": Enables the counter. The counter starts counting when detecting the rising
edge of the time-base timer interval. It stops counting when detecting the
second rising edge of the same interval.
This bit is automatically set to "0" when the counter stops.
Notes:
• Do not modify the CMCSEL bit when CMCEN = 1.
• Do not modify the TBTSEL[2:0] bits when CMCEN = 1.
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
27.4
Operations of Clock Supervisor Counter
This section describes the operations of the clock supervisor counter.
■ Clock Supervisor Counter
● Clock Supervisor Counter Operation 1
The clock supervisor counter is first enabled by the software (CMCEN = 1), and then the clock
supervisor counter operates with the time-base timer interval selected from eight options by the
TBTSEL[2:0] bits. Between two rising edges of the time-base timer interval selected, the
internal counter is clocked by the external clock.
The count clock of this module can be selected from the main oscillation clock, the main PLL
clock and the suboscillation clock.
Figure 27.4-1 Clock Supervisor Counter Operation
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
0
CMDR register
30
0
30
● Clock Supervisor Counter Operation 2
The CMDR register is cleared when the CMCEN bit changes from "0" to "1".
Figure 27.4-2 Clock Supervisor Counter Operation 2
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
CMDR register
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0
10
0
0
10
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
● Clock Supervisor Counter Operation 3
The counter stops counting if it reaches "255". It cannot count further.
Figure 27.4-3 Clock Supervisor Counter Operation 3
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
0
CMDR register
255
0
255
● Clock Supervisor Counter Operation 4
If the external clock selected stops, the counter stops counting. The software can then identify
that the external clock selected is in the abnormal state.
Figure 27.4-4 Clock Supervisor Counter Operation 4
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
0
CMDR register
0
● Clock Supervisor Counter Operation 5
The counter is cleared to "0" by the software if the CMCEN is set to "0" while the counter is
operating.
Figure 27.4-5 Clock Supervisor Counter Operation 5
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
Software setting
CMCEN
Internal counter
CMDR register
614
0
0
0
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
■ Table of Time-base Timer Intervals & Clock Supervisor Counter Values
Table 27.4-1 shows time-base timer intervals suitable for using different main CR clock
frequency to measure different external clocks.
Table 27.4-1 Table of Counter Values in Relation to TBTSEL Settings (1 / 2)
Main Main/SubMain MeasurCR
crystal
CR
ement
(FCRH) oscillation
error
error
[MHz]
[MHz]
0.03277
0.5
1
4
1
6
10
20
32.5
0.03277
0.5
1
4
8
6
10
20
32.5
TBTSEL2 - TBTSEL0
000B
001B
010B
011B
100B
101B
110B
111B
(23×1/FCRH) (25×1/FCRH) (27×1/FCRH) (29×1/FCRH) (211×1/FCRH) (213×1/FCRH) (215×1/FCRH) (217×1/FCRH)
+5%
-1
0
0
0
6
30
126
510
-5%
+1
1
1
3
9
36
142
566
2044
2261
+5%
-1
0
6
29
120
486
1949
7800
31206
-5%
+1
3
9
34
135
539
2156
8624
34493
+5%
-1
2
14
59
242
974
3899
15602
62414
-5%
+1
5
17
68
270
1078
4312
17247
68986
+5%
-1
14
59
242
974
3899
15602
62414
249659
-5%
+1
17
68
270
1078
4312
17247
68986
275942
+5%
-1
21
90
364
1461
5850
23404
93621
374490
-5%
+1
26
102
405
1617
6468
25870
103478
413912
+5%
-1
37
151
608
2437
9751
39008
156037
624151
-5%
+1
43
169
674
2695
10779
43116
172464
689853
+5%
-1
75
303
1218
4875
19503
78018
312075
1248303
-5%
+1
85
337
1348
5390
21558
86232
344927
1379706
+5%
-1
122
494
1979
7922
31694
126779
507122
2028494
-5%
+1
137
548
2190
8758
35032
140127
560506
2242022
+5%
-1
0
0
0
0
2
14
62
254
-5%
+1
1
1
1
2
5
18
71
283
+5%
-1
0
0
2
14
59
242
974
3899
-5%
+1
1
2
5
17
68
270
1078
4312
+5%
-1
0
0
6
29
120
486
1949
7800
-5%
+1
1
3
9
34
135
539
2156
8624
+5%
-1
0
6
29
120
486
1949
7800
31206
-5%
+1
3
9
34
135
539
2156
8624
34493
+5%
-1
1
10
44
181
730
2924
11701
46810
-5%
+1
4
13
51
203
809
3234
12935
51739
+5%
-1
3
18
75
303
1218
4875
19503
78018
-5%
+1
6
22
85
337
1348
5390
21558
86232
+5%
-1
8
37
151
608
2437
9751
39008
156037
-5%
+1
11
43
169
674
2695
10779
43116
172464
+5%
-1
14
60
246
989
3960
15846
63389
253560
-5%
+1
18
69
274
1095
4379
17516
70064
280253
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
Table 27.4-1 Table of Counter Values in Relation to TBTSEL Settings (2 / 2)
Main Main/SubMain MeasurCR
crystal
CR
ement
(FCRH) oscillation
error
error
[MHz]
[MHz]
0.03277
0.5
1
4
10
6
10
20
32.5
0.03277
0.5
1
4
12.5
6
10
20
32.5
TBTSEL2 - TBTSEL0
000B
001B
010B
011B
100B
101B
110B
111B
(23×1/FCRH) (25×1/FCRH) (27×1/FCRH) (29×1/FCRH) (211×1/FCRH) (213×1/FCRH) (215×1/FCRH) (217×1/FCRH)
+5%
-1
0
0
0
0
2
11
50
-5%
+1
1
1
1
1
4
15
57
203
227
+5%
-1
0
0
2
11
47
194
779
3119
-5%
+1
1
1
4
14
54
216
863
3450
+5%
-1
0
0
5
23
96
389
1559
6240
-5%
+1
1
2
7
27
108
432
1725
6899
+5%
-1
0
5
23
96
389
1559
6240
24965
-5%
+1
2
7
27
108
432
1725
6899
27595
+5%
-1
1
8
35
145
584
2339
9361
37448
-5%
+1
3
11
41
162
647
2587
10348
41392
+5%
-1
2
14
59
242
974
3899
15602
62414
-5%
+1
5
17
68
270
1078
4312
17247
68986
+5%
-1
6
29
120
486
1949
7800
31206
124829
-5%
+1
9
34
135
539
2156
8624
34493
137971
+5%
-1
11
48
197
791
3168
12677
50711
202848
-5%
+1
14
55
219
876
3504
14013
56051
224203
+5%
-1
0
0
0
0
1
9
39
162
-5%
+1
1
1
1
1
3
12
46
181
+5%
-1
0
0
1
8
38
155
623
2495
-5%
+1
1
1
3
11
44
173
690
2760
+5%
-1
0
0
3
18
77
311
1247
4992
-5%
+1
1
2
6
22
87
345
1380
5519
+5%
-1
0
3
18
77
311
1247
4992
19971
-5%
+1
2
6
22
87
345
1380
5519
22076
+5%
-1
0
6
28
116
467
1871
7488
29958
-5%
+1
3
9
33
130
518
2070
8279
33113
+5%
-1
2
11
47
194
779
3119
12482
49931
-5%
+1
4
14
54
216
863
3450
13798
55189
+5%
-1
5
23
96
389
1559
6240
24965
99863
-5%
+1
7
27
108
432
1725
6899
27595
110377
+5%
-1
8
38
157
632
2534
10141
40568
162278
-5%
+1
11
44
176
701
2803
11211
44841
179362
: Recommended setting
: The counter value becomes "0" or "255".
616
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
Table 27.4-1 is calculated by the following equation:
3
2 × 1/FCRH(TBTSEL=000)
5
2 × 1/FCRH(TBTSEL=001)
7
2 × 1/FCRH(TBTSEL=010)
9
2 × 1/FCRH(TBTSEL=011)
11
2 × 1/FCRH(TBTSEL=100)
13
2 × 1/FCRH(TBTSEL=101)
15
2 × 1/FCRH(TBTSEL=110)
17
2 × 1/FCRH(TBTSEL=111)
× Main oscillation/Suboscillation clock frequency
± 1 (Measurement error)
Counter value*1 =
2
*2
Selected time-base
timer interval
Within this period, the counter value in the above equation is
counted by the main oscillation/suboscillation clock.
*1 : Omit the decimal places of the counter value.
*2 : If the main PLL clock is selected as the count clock, this value becomes “1” (no division).
If the time-base timer interrupt is used to make the clock supervisor counter wait for the
oscillation stabilization time, please satisfy the following condition:
Time-base Timer Interval > Main oscillation/Suboscillation Stabilization Time × 1.05
e.g. FCH = 4 MHz, FCRH = 1 MHz, MWT[3:0] = 1111 (in WATR register)
14
Time-base Timer Interval >
(2 – 2 )
--------------------- × 1.05 ≈ 4.3 ms
6
4 × 10
TBC[3:0] = 0110 (213 × 1/FCRH)
Notes:
• See "11.1 Overview of Time-base Timer" for time-base timer interval settings.
• See "6.5 Oscillation Stabilization Wait Time Setting Register (WATR)" for main/
sub-oscillation stabilization time settings.
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.4 Operations of Clock Supervisor Counter
MB95410H/470H Series
■ Sample Operation Flow Chart of Clock Supervisor
Figure 27.4-6 Sample Operation Flow Chart of Clock Supervisor
Clock supervision starts
NO
Oscillation stabilization
wait time elapses
In main CR clock mode, wait for the elapse of the
specified main clock/subclock oscillation stabilization
wait time by using the time-base timer interrupt or
other methods.
YES
Read the main clock /
subclock oscillation
stabilization bit*
"0"
"1"
Set CMCSEL,
TBTSEL[2:0]
and CMCEN
"1"
Read CMCEN
"0"
NO
CMDR value =
estimate ?
YES
Change target external clock
(Normal oscillation)
Keep main CR clock mode
(The external clock is
oscillating at an abnormal
frequency.)
*: Main clock oscillation stabilization bit — STBC:MRDY
Subclock oscillation stabilization bit — SYCC:SRDY
618
Keep main CR clock mode
(If the oscillation stabilization wait
time has elapsed but the main
clock/subclock oscillation stabilization bit* is not set to “1”, that
means the external clock is dead
or the external clock frequency is
abnormal.)
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.5 Notes on Using Clock Supervisor Counter
MB95410H/470H Series
27.5
Notes on Using Clock Supervisor Counter
This section provides notes on using the clock supervisor counter.
■ Notes on Using Clock Supervisor Counter
● Restrictions
• The clock supervisor counter must operate in main CR clock mode with the hardware
watchdog timer (running in standby mode). Otherwise, it cannot detect the abnormal state
of the external clock correctly and will hang up if the external clock stops. See "CHAPTER
12 HARDWARE/SOFTWARE WATCHDOG TIMER" for the hardware watchdog timer
(running in standby mode).
• Use main CR clock mode only. DO NOT use any other clock mode.
• If the time-base timer stops, the internal counter stops working. DO NOT clear the timebase timer while the clock supervisor counter is counting with the external clock.
• Select a time-base timer interval that is sufficiently long for the clock supervisor counter to
operate. See Table 27.4-1 for time-base timer intervals.
• Read the CMDR register when CMCEN = 0. (The value of CMDR remains "0" while the
clock supervisor counter is operating (CMCEN = 1).)
• When using the clock supervisor counter, ensure that the machine clock cycle is shorter
than half the time-base timer interval selected. If the machine clock cycle is longer than half
the time-base timer interval selected, CMCEN may remain "1" even after the clock
supervisor counter stops.
Table 27.5-1 below shows the appropriate clock gear setting for each TBTSEL setting.
Table 27.5-1 Appropriate Clock Gear Setting for Respective TBTSEL
TBTSEL2 to TBTSEL0
000B
001B
010B to 111B
23 × 1/FCRH
25 × 1/FCRH
27 × 1/FCRH to 217 × 1/FCRH
00 (1 × 1/FCRH)
❍
❍
❍
01 (4 × 1/FCRH)
x
❍
❍
10 (8 × 1/FCRH)
x
❍
❍
11 (16 × 1/FCRH)
x
x
❍
DIV (clock gear setting)
❍: Recommended
x: Prohibited
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CHAPTER 27 CLOCK SUPERVISOR COUNTER
27.5 Notes on Using Clock Supervisor Counter
MB95410H/470H Series
● If the external clock stops while the clock supervisor counter is operating, and it restarts
after the second rising edge of the time-base timer interval selected, CMCEN is set to "0"
after the external clock restarts.
Figure 27.5-1 Clock Supervisor Counter Operation 1
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
0
CMDR register
5
6
0
6
● With the clock supervisor counter running, if the external clock stops, CMCEN is set to "0"
when a falling edge of the time-base timer interval selected is detected after the second
rising edge of the same interval. The counter is cleared at the same falling edge.
Figure 27.5-2 Clock Supervisor Counter Operation 2
Selected time-base
timer interval
Main oscillation clock/
Suboscillation clock
CMCEN
Internal counter
CMDR register
620
0
5
0
0
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
CHAPTER 28
LCD CONTROLLER
(MB95410H SERIES)
This chapter describes the functions and
operations of the LCD controller.
28.1 Overview of LCD Controller
28.2 Configuration of LCD Controller
28.3 Pins of LCD Controller
28.4 Registers of LCD Controller
28.5 LCD Controller Display RAM
28.6 Interrupts of LCD Controller
28.7 Operations of LCD Controller
28.8 Notes on Using LCD Controller
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CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.1 Overview of LCD Controller
28.1
MB95410H/470H Series
Overview of LCD Controller
The LCD controller has 2 modes: 8 COM mode and 4 COM mode.
In 8 COM mode, the LCD controller can use 36 bytes of display data memory
and controls an LCD display via 8 common outputs and 36 segment outputs. It
also has 2 different bias output options for driving an LCD panel.
In 4 COM mode, the LCD controller can use 20 bytes of display data memory
and controls an LCD display via 4 common outputs and 40 segment outputs. It
also has 3 different duty output options for driving an LCD panel.
■ Functions of LCD Controller
The LCD controller uses its segment and common outputs to display the contents of display
data memory (display RAM) directly on the LCD panel.
• It selects the 8 COM mode and the 4 COM mode through software.
• It has an LCD drive voltage divider resistor whose resistance value can be selected from
10 kΩ to 100 kΩ through software. An external divider resistor can also be used instead.
• In 8 COM mode, 8 common outputs (COM0 to COM7) and 36 segment outputs (SEG00 to
SEG35) are available
• In 4 COM mode, 4 common outputs (COM0 to COM3) and 40 segment outputs (SEG00 to
SEG39) are available.
• The display RAM size is 36 bytes (36 × 8 bits) in 8 COM mode and 20 bytes (40 × 4 bits) in
4 COM mode.
• It can use the main clock or the subclock as its operating clock.
• It has a blinking function, which is only available to certain pins.
• It can directly drive an LCD panel.
• In 8 COM mode, the bias can be selected from 1/3 or 1/4.
• In 4 COM mode, the duty can be selected from 1/2, 1/3 or 1/4 (governed by the bias
setting).
• The interrupt is in sync with the LCD module frame frequency.
Table 28.1-1 lists the bias-duty combinations available.
Table 28.1-1 Bias-duty Combinations
Duty
1/2 bias
1/3 bias
1/4 bias
1/2
❍
X
X
1/3
X
❍
X
1/4
X
❍
X
1/8, BLS8 = 0
X
❍
X
1/8, BLS8 = 1
X
X
❍
❍ : Recommended combination
X : Prohibited combination
622
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
MB95410H/470H Series
28.2
Configuration of LCD Controller
The LCD controller consists of the following blocks, which are divided
functionally into a controller section that generates the segment and common
signals based on the content of display RAM and a driver section that drives
the LCD.
Controller section
• LCDC control registers (LCDCC1, LCDCC2)
• LCDC enable registers (LCDCE1 to LCDCE7)
• LCDC blinking setting registers (LCDCB1, LCDCB2)
• Display RAM
• Clock selection
• Timing control
Driver section
• AC waveform generator circuit
• Common driver
• Segment driver
• Divider resistor
■ LCD Controller Block Diagrams
Figure 28.2-1 LCD Controller Block Diagram (8 COM Mode)
Main clock
Subclock
Clock
selection
Internal divider
resistor
Timing
control
AC waveform
generator circuit
Internal bus
LCDC control registers
(LCDCC1, LCDCC2)
LCDC enable registers
(LCDCE1 to LCDCE7)
LCDC blinking setting registers
(LCDCB1, LCDCB2)
Display RAM:
36 × 8 bits
(36 bytes)
Controller section
MN702-00005-2v0-E
Common
driver
COM0
to
COM7
Segment
driver
SEG00
to
SEG35
Driver section
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
MB95410H/470H Series
Figure 28.2-2 LCD Controller Block Diagram (4 COM Mode)
Main clock
Clock
selection
Subclock
Internal divider
resistor
Timing
control
AC waveform
generator circuit
Internal bus
LCDC control registers
(LCDCC1, LCDCC2)
LCDC enable registers
(LCDCE1 to LCDCE7)
LCDC blinking setting registers
(LCDCB1, LCDCB2)
Display RAM:
40 × 4 bits
(20 bytes)
Controller section
Common
driver
COM0
to
COM3
Segment
driver
SEG00
to
SEG39
Driver section
● LCDC control register 1 (LCDCC1)
This register is used to select the clock for generating the frame period, select the display
mode, select the frame period clock, and control the LCD driving power supply.
● LCDC control register 2 (LCDCC2)
This register is used to enable and disable interrupts, indicate interrupt status and set the
following parameters:
- Internal resistance value (10 kΩ or 100 kΩ)
- Bias to be used in 8 COM mode (1/3 or 1/4)
- Displaying data or a blank screen
- Inverted display
● LCDC enable registers 1 to 7 (LCDCE1 to LCDCE7)
These registers are used to control port inputs, blink interval, and pins.
● LCDC blinking setting register 1 (LCDCB1), LCDC blinking setting register 2 (LCDCB2)
These registers are used to turn on or off blinking.
● Display RAM
In 8 COM mode, 36 × 8 bits of RAM is available for generating segment output signals.
In 4 COM mode, 40 × 4 bits of RAM is available for generating segment output signals.
The content of the display RAM are read automatically in sync with the common signal
selection timing and are output from segment output pins.
When the display RAM is modified, the content of the VRAM will be output from segment
output pins.
624
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
● Clock selection
The frame frequency is generated based on the selection from the eight frequencies generated
from the two clocks.
● Timing control
The COM and SEG signals are controlled based on the frame frequency and register settings.
● AC waveform generator circuit
This block generates AC waveforms for driving the LCD from timing control signals.
● Common driver
This block is the driver of the LCD COM pins.
● Segment driver
This block is the driver of the LCD SEG pins.
● Divider resistor
This block is a resistor used to generate the LCD drive voltage. A divider resistor can be
connected to as an external component when a LCDC drive power supply pin (V0 to V4)
serves as a divider resistor connection pin.
■ LCD Controller Power Supply Voltage
The power supply voltage for the LCD driver is generated by internal divider resistors or by
connecting external divider resistors to the V0 to V4 pins.
■ Input Clock
The LCD controller uses the output clock of time-base timer or watch prescaler as the input
clock (operation clock).
MN702-00005-2v0-E
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CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
28.2.1
MB95410H/470H Series
Internal Divider Resistors for LCD Controller
The internal divider resistors generate power supply voltage for the LCD driver.
■ Internal Divider Resistors
Internal divider resistors are included. In addition, external divider resistors can be connected
to the LCDC drive power pins (V0 to V4).
The internal and external divider resistors are selected by the driving power control bit in the
LCDC control register 1 (LCDCC1:VSEL). Setting the VSEL bit to "1" energizes the internal
divider resistors. To use only the internal divider resistors without any external divider resistor,
set the VE3 bit in the LCDC enable register 1 (LCDCE1) to "1". (When internal split resistors are
used, the V4 pin cannot be used as general-purpose I/O ports.)
The LCD controller stops upon transition to main stop or watch mode (STBC:TMD = 1) while
operation in main stop and watch modes is disabled (LCDCC1:LCDEN = 0) with LCD
operation halted (LCDCC1:MS[2:0] = 000B).
Figure 28.2-3 shows an equivalent circuit with internal divider resistors used.
626
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
Figure 28.2-3 Equivalent Circuit with Internal Divider Resistors Used
VCC
V4
V4
90 kΩ
10 kΩ
V3
V3
Bias select signal
90 kΩ
10 kΩ
90 kΩ
10 kΩ
90 kΩ
10 kΩ
V2
V2
V1
V1
V0
V0
LCD enable
Internal resistance
select signal
N-ch
10 kΩ or 100 kΩ
select signal
V0 to V4: Respective voltages of V0 to V4 pins
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CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
MB95410H/470H Series
■ Use of Internal Divider Resistors and Brightness Control
There are two types of internal divider resistors: 10 kΩ and 100 kΩ. Figure 28.2-4 shows
examples of using the internal divider resistors.
If sufficient brightness cannot be achieved with the internal divider resistors in use, connect a
variable resistor (VR) externally (between the Vcc pin and the V4 pin) to adjust the V4
voltage. Figure 28.2-5 illustrates connecting a VR to the V4 pin to control brightness.
Figure 28.2-4 States with Internal Divider Resistors Used
VCC
VCC
VR
V4
10 kΩ
90 kΩ
90 kΩ
90 kΩ
V3
10 kΩ
V3
10 kΩ
90 kΩ
10 kΩ
90 kΩ
90 kΩ
V2
V2
10 kΩ
V2
10 kΩ
90 kΩ
10 kΩ
90 kΩ
90 kΩ
V1
V1
10 kΩ
V1
10 kΩ
90 kΩ
10 kΩ
90 kΩ
V0
LCD enable
On
1/4 bias internal connection with 100 kΩ internal resistors
90 kΩ
V0
1/3 bias internal connection with 100 kΩ internal resistors
1/2 bias internal connection with 100 kΩ internal resistors
VCC
VR
V4
VR
V4
10 kΩ
10 kΩ
90 kΩ
90 kΩ
V4
10 kΩ
90 kΩ
V3
V3
V3
10 kΩ
90 kΩ
10 kΩ
90 kΩ
90 kΩ
V2
V2
10 kΩ
V2
10 kΩ
90 kΩ
10 kΩ
90 kΩ
90 kΩ
V1
10 kΩ
V1
V1
10 kΩ
90 kΩ
10 kΩ
90 kΩ
V0
On
1/4 bias internal connection with 10 kΩ internal resistors
V0
On
VCC
VR
10 kΩ
LCD enable
On
VCC
628
V4
10 kΩ
V3
LCD enable
VR
V4
10 kΩ
LCD enable
VCC
VR
LCD enable
90 kΩ
V0
LCD enable
On
1/3 bias internal connection with 10 kΩ internal resistors
V0
On
1/2 bias internal connection with 10 kΩ internal resistors
FUJITSU SEMICONDUCTOR LIMITED
MN702-00005-2v0-E
MB95410H/470H Series
CHAPTER 28 LCD CONTROLLER (MB95410H SERIES)
28.2 Configuration of LCD Controller
Figure 28.2-5 Brightness Control by Connecting VR to V4 Pin
VCC
VR
V4
V4
R
V3
V3
R
V2
V2
R
V1
V1
R
V0
V0
LCD enable