MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register General Description Features The MM54C164/MM74C164 shift registers are a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. These 8-bit shift registers have gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. A high-level input enables the other input which will then determine the state of the flip-flop. Data is serially shifted in and out of the 8-bit register during the positive going transition of clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. All inputs are protected against electrostatic effects. Y Y Y Y Y 3V to 15V drive 2 LPTTL loads 0.45 VCC (typ.) 50 nW (typ.) 0.8 MHz (typ.) with 10V supply Applications Y Y Y Y Truth Table Supply voltage range Tenth power TTL compatible High noise immunity Low power Medium speed operation Data terminals Instrumentation Medical electronics Alarm systems Y Y Y Industrial electronics Remote metering Computers Connection Diagram Serial Inputs A and B Inputs tn Dual-In-Line Package Output tn a 1 A B QA 1 0 1 0 1 1 0 0 1 0 0 0 TL/F/5896 – 2 Top View Order Number MM54C164 or MM74C164 Block Diagram TL/F/5896 – 1 C1995 National Semiconductor Corporation TL/F/5896 RRD-B30M105/Printed in U. S. A. MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register February 1988 Absolute Maximum Ratings (Note 1) Voltage at Any Pin 18V Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range b 0.3V to VCC a 0.3V Operating Temperature Range MM54C164 MM74C164 b 65§ C to a 150§ C Storage Temperature Range Absolute Maximum VCC If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 3V to 15V 260§ C Lead Temperature (soldering, 10 sec.) DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V 3.5 8.0 VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e a 10 mA VCC e 10V, IO e a 10 mA IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V ICC Supply Current VCC e 15V V V 1.5 2.0 4.5 9.0 V V 0.005 b 1.0 V V 0.5 1.0 V V 1.0 mA b 0.005 0.05 mA 300 mA CMOS TO LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C VCC e 4.5V 74C VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C VCC e 4.5V 74C VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C VCC e 4.5V, IO e b360 mA 74C VCC e 4.75V, IO e b360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C VCC e 4.5V, IO e 360 mA 74C VCC e 4.75V, IO e 360 mA VCC b 1.5 VCC b 1.5 V V 0.8 0.8 2.4 2.4 V V V V 0.4 0.4 V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current VCC e 5V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 1.75 mA ISOURCE Output Source Current VCC e 10V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 8.0 mA ISINK Output Sink Current VCC e 5V, VIN(1) e 5V TA e 25§ C, VOUT e VCC 1.75 mA ISINK Output Sink Current VCC e 10V, VIN(1) e 10V TA e 25§ C, VOUT e VCC 8.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Typ Max Units tpd1 Symbol Propagation Delay Time to a Logical ‘‘0’’ or a Logical ‘‘1’’ from Clock to Q Parameter VCC e 5V VCC e 10V Conditions Min 230 90 310 120 ns ns tpd0 Propagation Delay Time to a Logical ‘‘0’’ from Clear to Q VCC e 5V VCC e 10V 280 110 380 150 ns ns tS Time Prior to Clock Pulse that Data Must be Present VCC e 5V VCC e 10V 200 80 110 30 ns ns tH Time After Clock Pulse that Data Must be Held VCC e 5V VCC e 10V 0 0 0 0 ns ns fMAX Maximum Clock Frequency VCC e 5V VCC e 10V 2.0 5.5 3 8 MHz MHz tW Minimum Clear Pulse Width VCC e 5V VCC e 10V tr, tf Maximum Clock Rise and Fall Time VCC e 5V VCC e 10V CIN Input Capacitance Any Input (Note 2) CPD Power Dissipation Capacitance (Note 3) 150 55 15 5 250 90 ns ns ms ms 5 pF 140 pF *AC Parameters are guaranteed by DC correlated testing. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90. Logic Waveforms TL/F/5896 – 3 3 Switching Time Waveforms CMOS to CMOS TTL to CMOS TL/F/5896 – 4 TL/F/5896 – 5 tr e tf e 20 ns AC Test Circuit TL/F/5896 – 6 Typical Applications 74C Compatibility Guaranteed Noise Margin as a Function of VCC TL/F/5896 – 7 TL/F/5896 – 8 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C164J or MM74C164J NS Package Number J14A 5 MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM54C164N or MM74C164N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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