A6A259: 8-Bit Addressable DMOS Power Driver

A6A259
8-Bit Addressable, DMOS Power Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 29, 2007
Recommended Substitutions:
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
8-BIT ADDRESSABLE
DMOS POWER DRIVER
PRELIMINARY INFORMATION
(Subject to change without notice)
March 24, 2003
A6A259KA (DIP)
20
OUT1
OUT3
2
19
OUT0
S1
3
18
S0 (LSB)
LOGIC
GROUND
4
VDD 17
LOGIC
SUPPLY
POWER
GROUND
5
POWER
GROUND
LATCHES
1
DECODER
OUT2
16
POWER
GROUND
6
15
POWER
GROUND
S2 (MSB)
7
14
CLEAR
ENABLE
8
13
DATA
OUT4
9
12
OUT7
OUT5
10
11
OUT6
EN
Dwg. PP-050-4
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................ 50 V
Output Drain Current,
Continuous, IO ...................... 350 mA*
Peak, IOM ........................... 1100 mA*†
Peak, IOM .................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical
charges.
Data Sheet
26186.121
6A259
The A6A259KA and A6A259KLB combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6A259KA/KLB
DMOS open-drain outputs are capable of sinking up to 500 mA.
The A6A259KA is furnished in a 20-pin dual in-line plastic package. The A6A259KLB is furnished in a 24-lead wide-body, smalloutline plastic batwing package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150
mA from all outputs continuously, to ambient temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 350 mA Output Current (all outputs simultaneously)
■ 1 Ω Typical rDS(on)
■ Internal Short-Circuit Protection
■ Low Power Consumption
■ Replacements for TPIC6A259N and TPIC6A259DW
Always order by complete part number:
Part Number
Package
RθJA
A6A259KA
20-pin DIP
55°C/W
A6A259KLB 24-lead SOIC 55°C/W
RθJC
25°C/W
—
RθJT
—
6°C/W
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
SUFFIX 'LB', R θJT = 6.0°C/W
1
24
OUT1
4
OUT3
2
23
OUT0
S1
3
22
S0 (LSB)
3
LOGIC
GROUND
4
VDD 21
LOGIC
SUPPLY
POWER
GROUND
5
20
POWER
GROUND
POWER
GROUND
6
19
POWER
GROUND
POWER
GROUND
7
18
POWER
GROUND
POWER
GROUND
8
17
POWER
GROUND
S2 (MSB)
9
16
CLEAR
ENABLE
10
15
DATA
OUT4
11
14
OUT7
OUT5
12
13
OUT6
SUFFIX 'A', R θJC = 25°C/W
2
1
R θJA = 55°C/W
0
50
25
75
100
TEMPERATURE IN ° C
125
150
LATCHES
OUT2
DECODER
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
A6A259KLB (SOIC)
5
EN
Dwg. GP-049-5
Dwg. PP-050-3A
VDD
OUT
IN
Dwg. EP-063-5
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
Inputs
CLEAR ENABLE DATA
H
H
H
L
L
L
L
L
H
L
L
H
L = Low Logic Level
2
H
L
X
H
L
X
LATCH SELECTION TABLE
Addressed
OUTPUT
Other
OUTPUTs
L
H
R
L
H
H
R
R
R
H
H
H
H = High Logic Level
X = Irrelevant
Function
Addressable
Latch
Memory
8-Line
Demultiplexer
Clear
R = Previous State
Select Inputs
Addressed
S2 (MSB) S1 S0 (LSB) OUTPUT
L
L
L
L
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
0
1
2
3
4
5
6
H
H
H
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2003 Allegro MicroSystems, Inc.
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
D
S0
(LSB)
OUT 0
C1
CLR
D
OUT 1
C1
CLR
S1
D
OUT 2
CLR
D
C1
CLR
S2
(MSB)
D
C1
CLR
LOGIC
SUPPLY
D
V DD
CURRENT LIMIT AND CHARGE PUMP
C1
OUT 3
OUT 4
OUT 5
C1
CLR
LOGIC
GROUND
D
OUT 6
C1
CLR
DATA
ENABLE
D
(ACTIVE LOW)
CLEAR
OUT 7
C1
CLR
POWER
GROUND
(ACTIVE LOW)
Dwg. FP-047-2
Power grounds must be connected externally to a single point.
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3
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic
Logic Supply Voltage
Output Breakdown
Voltage
Off-State Output
Current
Static Drain-Source
On-State Resistance
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VDD
Operating
4.5
5.0
5.5
V
V(BR)DSX
IO = 1 mA
50
—
—
V
IDSX
VO = 40 V
—
0.1
1.0
µA
VO = 40 V, TA = 125°C
—
0.2
5.0
µA
IO = 350 mA
—
1.0
1.5
Ω
IO = 350 mA, TA = 125°C
—
1.7
2.5
Ω
IF = 350 mA
—
1.0
—
V
rDS(on)
Source-to-Drain
Diode Voltage
VSD
Nominal Output
Current
IO(nom)
VDS(on) = 0.5 V, TA = 85°C
—
350
—
mA
Output Current
IO(chop)
IO at which chopping starts, TC = 25°C
0.6
0.8
1.1
A
IIH
VI = VDD = 5.5 V
—
—
1.0
µA
IIL
VI = 0, VDD = 5.5 V
—
—
-1.0
µA
tPLH
IO = 350 mA, CL = 30 pF
—
100
—
ns
tPHL
IO = 350 mA, CL = 30 pF
—
60
—
ns
Output Rise Time
tr
IO = 350 mA, CL = 30 pF
—
55
—
ns
Output Fall Time
tf
IO = 350 mA, CL = 30 pF
—
40
—
ns
IDD(off)
VDD = 5.5 V, Outputs OFF
—
0.75
1.0
mA
IDD(on)
VDD = 5.5 V, Outputs ON
—
2.0
3.0
mA
Logic Input Current
Prop. Delay Time
Supply Current
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤ 100 µs, duty cycle ≤ 2%.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
Four modes of operation are selectable by controlling the
CLEAR and ENABLE inputs as shown above.
ENABLE
DATA
In the addressable-latch mode, data at the DATA input is
written into the addressed transparent latch. The addressed
output inverts the data input with all other outputs remaining
in their previous states.
50%
t PLH
t PHL
90%
ADDRESSED
OUTPUT
10%
tr
tf
Dwg. WP-036
OUTPUT SWITCHING TIME
In the memory mode, all outputs remain in their previous
states and are unaffected by the DATA or address (Sn) inputs.
To prevent entering erroneus data in the latches, ENABLE
should be held HIGH while the address lines are changing.
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
ENABLE
50%
DATA
In the clear mode, all outputs are OFF and are unaffected
by the DATA or address (SN) inputs.
t h(D)
t su(D)
50%
t w(D)
Dwg. WP-037
DATA INPUT REQUIREMENTS
Data Active Time Before Enable
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
Given the appropriate inputs, when DATA is LOW for a
given address, the output is OFF; when DATA is HIGH, the
output is ON and can sink current.
LOGIC SYMBOL
S0
S1
S2
ENABLE
DATA
CLEAR
0
8M 0/7
2
G8
Z9
Z10
9,0D
10,0R
OUT 0
9,1D
10,1R
OUT 1
9,2D
10,2R
OUT 2
9,3D
10,3R
OUT 3
9,4D
10,4R
OUT 4
9,5D
10,5R
OUT 5
9,6D
10,6R
OUT 6
9,7D
10,7R
OUT 7
Dwg. FP-046-2
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5
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
TEST CIRCUITS
+15 V
1Ω
INPUT
210 mH
tav
IAS = 600 mA
IO
DUT
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066-2
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
A6A259KA
(DIP)
Terminal No.
A6A259KLB
(SOIC)
Terminal No.
Terminal Name
1
1
OUT2
Current-sinking, open-drain DMOS output, address 010.
2
2
OUT3
Current-sinking, open-drain DMOS output, address 011.
3
3
S1
4
4
LOGIC GROUND
5
5, 6
POWER GROUND Reference terminal for output voltage measurements
(OUT0-3).
6
7, 8
POWER GROUND Reference terminal for output voltage measurements
(OUT4-7).
7
9
S2
8
10
ENABLE
9
11
OUT4
Current-sinking, open-drain DMOS output, address 100.
10
12
OUT5
Current-sinking, open-drain DMOS output, address 101.
11
13
OUT6
Current-sinking, open-drain DMOS output, address 110.
12
14
OUT7
Current-sinking, open-drain DMOS output, address 111.
13
15
DATA
CMOS data input to the addressed output latch. When
enabled, the addressed output inverts the data input
(DATA = HIGH, OUTPUT = LOW).
14
16
CLEAR
Mode control input; see Function Table.
15
17, 18
POWER GROUND Reference terminal for output voltage measurements
(OUT4-7).
16
19, 20
POWER GROUND Reference terminal for output voltage measurements
(OUT0-3).
17
21
LOGIC SUPPLY
18
22
S0
19
23
OUT0
Current-sinking, open-drain DMOS output, address 000.
20
24
OUT1
Current-sinking, open-drain DMOS output, address 001.
Function
Binary-coded output-select input.
Reference terminal for input voltage measurements.
Binary-coded output-select input, most-significant bit.
Mode control input; see Function Table.
(VDD) The logic supply voltage (typically 5 V).
Binary-coded output-select input, least-significant bit.
NOTE —Power grounds must be connected together externally.
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7
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
A6A259KA (DIP)
Dimensions in Inches
(controlling dimensions)
20
0.014
0.008
11
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
1.060
0.980
10
0.005
BSC
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
20
0.355
0.204
11
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
26.92
24.89
10
BSC
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
NOTES:1.
2.
3.
4.
8
Dwg. MA-001-20 mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 18 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
A6A259KLB (SOIC)
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
3
0.6141
0.5985
0.050
BSC
0° TO 8°
NOTE 1
NOTE 3
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-25A in
Dimensions in Millimeters
(controlling dimensions)
24
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
3
15.60
15.20
1.27
BSC
0° TO 8°
NOTE 1
NOTE 3
2.65
2.35
0.10 MIN.
NOTES:1.
2.
3.
4.
Dwg. MA-008-25A mm
Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
Lead spacing tolerance is non-cumulative.
Exact body and lead configuration at vendor’s option within limits shown.
Supplied in standard sticks/tubes of 31 devices, or add “TR” to part number for tape and reel.
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9
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
10
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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