UCQ5810: BiMOS II 10-Bit Serial-Input, Latched Source Drivers with Active-DMOS Pull-Downs

Data Sheet
26182.25C
5810-F
BiMOS II 10-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS FOR -40°C TO +85°C OPERATION
UCQ5810AF
OUT 9
OUT 8
1
18
OUT 7
2
17
OUT 10
16
SERIAL
DATA OUT
OUT 6
3
LATCHES
CLOCK
4
GROUND
5
CLK
REGISTER
VBB 15
LOAD
SUPPLY
REGISTER
14
SERIAL
DATA IN
LATCHES
LOGIC
SUPPLY
6
VDD
STROBE
7
ST
OUT 5
OUT 4
BLNK 13
BLANKING
12
OUT 1
8
11
OUT 2
9
10
OUT 3
The UCQ5810AF and UCQ5810LWF combine a 10-bit CMOS shift
register and accompanying data latches, control circuitry, bipolar sourcing
outputs with DMOS active pull-downs. Designed primarily to drive vacuumfluorescent displays, the 60 V and -40 mA output ratings also allow these
devices to be used in many other peripheral power driver applications. The
UCQ5810AF/LWF feature reduced supply requirements (active DMOS pulldowns) and lower saturation voltages when compared with the original
UCQ5810A.
T
C
U
0
D
Y
1
L
O
8
N
6
R
P E O —A
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may
require appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCQ5811A (12 bits), UCQ5812AF/EPF (20 bits), and UCQ5818AF/EPF (32
bits).
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Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ..................... 15 V
Driver Supply Voltage, VBB .................... 60 V
Continuous Output Current Range,
IOUT .......................... -40 mA to +15 mA
Input Voltage Range,
VIN ........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD
(UCQ5810AF) ........................... 2.08 W*
(UCQ5810LWF) ........................ 1.33 W*
Operating Temperature Range,
TA .................................. -40°C to +85°C
Storage Temperature Range,
TS ................................ -55°C to +150°C
*Derate linearly to 0 W at +150°C.
m
o
c
e
R
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCQ5810AF (dual in-line package)
and UCQ5810LWF (small-outline IC package)
are electrically identical and share a common
terminal number assignment.
The UCQ5810AF/LWF output source drivers are npn Darlingtons
capable of sourcing up to 40 mA. The DMOS active pull-downs are capable
of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can
be disabled and the DMOS sink drivers turned on by the BLANKING input
high.
The UCQ5810AF is furnished in an 18-pin dual in-line plastic package.
The UCQ5810LWF is furnished in a wide-body, small-outline plastic package
(SOIC) with gull-wing leads. Copper lead frames, reduced supply current
requirements, and lower output saturation voltages allow all devices to source
25 mA from all outputs continuously, over the entire operating temperature
range.
FEATURES
■ High-Speed Source Drivers
■ 60 V Minimum
Output Breakdown
■ Improved Replacements
for TL4810B
■ Low Output Saturation Voltages
■ Low-Power CMOS Logic
and Latches
■ To 3.3 MHz Data Input Rate
■ Active DMOS Pull-Downs
Always order by complete part number, e.g., UCQ5810AF .
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCQ5810LWF
OUT 8
1
OUT 7
2
OUT 6
3
CLOCK
4
GROUND
5
FUNCTIONAL BLOCK DIAGRAM
18
17
OUT 10
16
SERIAL
DATA OUT
15
LOAD
SUPPLY
14
SERIAL
DATA IN
13
BLANKING
12
OUT 1
LATCHES
CLK
REGISTER
VBB
REGISTER
OUT 9
LOGIC
SUPPLY
V DD
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
SERIAL
DATA OUT
BLANKING
LATCHES
LOGIC
SUPPLY
6
VDD
STROBE
7
ST
OUT 5
8
11
OUT 2
OUT 4
9
10
OUT 3
BLNK
MOS
BIPOLAR
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
LOAD
SUPPLY
Dwg. FP-013-1
Dwg. PP-029-1
TYPICAL INPUT CIRCUIT
VDD
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
IN
2.5
2.0
SUFFIX 'A', R θJA = 60°C/W
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
1.5
V BB
1.0
SUFFIX 'LW', R
0.5
θJA
= 94°C/W
OUT N
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
Dwg. GP-018C
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1988, 2004 Allegro MicroSystems, Inc.
Dwg. No. A-14,219
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
ELECTRICAL CHARACTERISTICS over operating temperature range, VBB = 60 V unless otherwise noted.
Limits @ VDD = 5 V
Characteristic
Symbol
Output Leakage Current
Output Voltage
Output Pull-Down Current
Input Voltage
Input Current
Serial Data Output Voltage
Limits @ VDD = 12 V
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
ICEX
VOUT = 0 V, TA = +70°C
—
-5.0
-15
—
-5.0
-15
µA
VOUT(1)
IOUT = -25 mA
58
58.5
—
58
58.5
—
V
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
—
—
V
IOUT = 2 mA
—
—
—
—
1.0
1.5
V
VOUT = 5 V to VBB
2.0
3.5
—
—
—
—
mA
VOUT = 20 V to VBB
—
—
—
8.0
13
—
mA
VIN(1)
3.5
—
5.3
10.5
—
12.3
V
VIN(0)
-0.3
—
+0.8
-0.3
—
+0.8
V
IOUT(0)
IIN(1)
VIN = VDD
—
—
100
—
—
240
µA
IIN(0)
VIN = 0.8 V
—
-0.05
-0.5
—
-0.1
-1.0
µA
VOUT(1)
IOUT = -200 µA
4.5
4.7
—
11.7
11.8
—
V
VOUT(0)
IOUT = 200 µA
—
200
250
—
100
200
mV
3.3*
—
—
—
—
—
MHz
Maximum Clock Frequency
fclk
Supply Current
IDD(1)
All Outputs High
—
100
300
—
200
500
µA
IDD(0)
All Outputs Low
—
100
300
—
200
500
µA
IBB(1)
Outputs High, No Load
—
0.7
2.0
—
0.7
2.0
mA
IBB(0)
Outputs Low
—
10
100
—
10
100
µA
tPHL
CL = 30 pF, 50% to 50%
—
2000
—
—
1000
—
ns
tPLH
CL = 30 pF, 50% to 50%
—
1000
—
—
850
—
ns
Output Fall Time
tf
CL = 30 pF, 90% to 10%
—
1450
—
—
650
—
ns
Output Rise Time
tr
CL = 30 pF, 10% to 90%
—
650
—
—
700
—
ns
Blanking to Output Delay
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranted.
www.allegromicro.com
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
CLOCK
A
B
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
D
DATA IN
E
F
C
STROBE
BLANKING
G
OUTN
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
X = Irrelevant
X
P = Present State
X
...
X
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
L
L
... L
L
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCQ5810AF
Dimensions in Inches
(controlling dimensions)
0.014
0.008
10
18
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
0.920
0.880
9
BSC
0.005
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
18
0.355
0.204
10
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
23.37
22.35
9
BSC
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
NOTES: 1.
2.
3.
4.
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 21 devices.
www.allegromicro.com
Dwg. MA-001-18A mm
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCQ5810LWF
Dimensions in Inches
(for reference only)
18
10
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.4625
0.4469
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-18A in
Dimensions in Millimeters
(controlling dimensions)
18
10
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
11.75
11.35
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-18A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 41 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
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