Data Sheet 26183.10A 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS Designed primarily for use with high-voltage vacuum-fluorescent displays, the UCN5815A and UCN5815EP BiMOS II integrated circuits consist of eight NPN Darlington source drivers with output pull-down resistors, a CMOS latch for each driver, and common STROBE, BLANKING, and ENABLE functions. UCN5815A BiMOS II devices have considerably better data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will typically operate above 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs cause minimum loading and are compatible with standard CMOS and NMOS logic commonly found in microprocessor designs. TTL circuits may require the use of appropriate pull-up resistors. Dwg. No. A-10,987 T C U D O Y L R P ON The bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. All eight outputs can be activated simultaneously at ambient temperatures in excess of 75°C. To simplify printed wiring board layout, output connections are opposite the inputs. A minimum component display subsystem, requiring few or no discrete components, can be assembled using the UCN5815A/EP with the UCN5810AF/EPF/LWF, UCN5812AF/EPF, or UCN5818AF/EPF serial-to-parallel latched drivers. D E E C U N N RE I T E N F E O R C S OR I D F ABSOLUTE MAXIMUM RATINGS at +25°C Free-Air Temperature Output Voltage, VOUT . . . . . . . . . . . . . . 60 V Logic Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . 4.5 V to 15 V Load Supply Voltage Range, VBB . . . . . . . . . . . . . . . . . . 5.0 V to 60 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . -40 mA Package Power Dissipation, PD (UCN5815A) . . . . . . . . . . . . . . . 2.5 W* (UCN5815EP) . . . . . . . . . . . . . 2.27 W* Operating Temperature Range, TA . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . . -55°C to +150°C — * Derate linearly to 0 W at +150°C. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Suffix ‘A’ devices are furnished in a standard 22-pin plastic DIP; suffix ‘EP’ indicates a 28-lead PLCC. FEATURES ■ ■ ■ ■ ■ ■ 4.4 MHz Minimum Date-lnput Rate High-Voltage Source Outputs CMOS, NMOS, TTL Compatible Inputs Low-Power CMOS Latches Internal Pull-Down Resistors Wide Supply-Voltage Range Always order by complete part number: Part Number Package UCN5815A 22-Pin DIP UCN5815EP 28-Lead PLCC 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V, VDD = 5 V and 12 V (unless otherwise noted). Characteristic Symbol Test Conditions Min. Limits Max. Units — 1.0 V Output OFF Voltage VOUT Output ON Voltage VOUT IOUT = -25 mA, VBB = 60 V 57.5 — V Output Pull-Down Current IOUT VOUT = VBB 400 850 µA Output Leakage Current IOUT TA = 70°C — -15 µA Input Voltage VIN(1) VDD = 5.0 V 3.5 5.3 V VDD = 12 V 10.5 12.3 V -0.3 +0.8 V VDD = VIN = 5.0 V — 100 µA VDD = VIN = 12 V — 240 µA VIN(0) Input Current IIN(1) Input lmpedance ZIN VDD = 5.0 V 50 — kΩ Supply Current lBB All outputs ON, All outputs open — 10.5 mA All outputs OFF, All outputs open — 100 µA VDD = 5.0 V, All outputs OFF, All inputs = 0 V — 100 µA VDD = 12 V, All outputs OFF, All inputs = 0 V — 200 µA VDD = 5.0 V, One output ON, All inputs = 0 V — 1.0 mA VDD = 12 V, One output ON, All inputs = 0 V — 3.0 mA lDD NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin. TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER V DD V BB OUT IN 100 K Dwg. No. EP-010-4A 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 W Copyright © 1984, 1996, Allegro MicroSystems, Inc. Dwg. No. EP-021-3 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS UCN5815EP Dwg. No. A-10,991 TIMING CONDITIONS (VDD = 5 V, TA = +25°C, Logic Levels are VDD and Ground) Dwg. No. A-14,357 Information present at an input is transferred to its latch when the STROBE and ENABLE are high. The latches will continue to accept new data as long as both STROBE and ENABLE are held high. With either STROBE or ENABLE in the low state, no information can be loaded into the latches. When the BLANKING input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches. With the BLANKING input low, the outputs are controlled by the state of the latches. The timing conditions shown above guarantee a 4.4 MHz minimum data input rate with a 5 V supply. Typically, input rates above 5 MHz are permitted. With a 12 V supply, rates in excess of 10 MHz are possible. A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns D. Typical Time Between Strobe Activation and Output ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µs E. Typical Time Between Strobe Activation and Output OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns F. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns TRUTH TABLE INPUTS OUTN INN STROBE ENABLE BLANK T-1 T 0 1 X X X X X 1 1 X 0 0 X X 1 1 X X X 0 0 0 0 1 0 0 0 0 X X X 1 0 1 0 0 1 0 1 0 1 0 X = irrelevant T-1 = previous output state T = present output state 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS UCN5815A Dimensions in Inches (cvontrolling dimensions) 22 0.015 0.008 12 0.500 MAX 0.380 0.330 0.400 BSC 1 2 0.070 0.030 3 11 0.100 1.120 1.050 BSC 0.005 MIN 0.210 MAX 0.015 0.160 0.115 MIN 0.022 0.014 Dwg. MA-002-22 in Dimensions in Millimeters (for reference only) 22 0.381 0.204 12 12.70 MAX 9.65 8.39 10.16 BSC 1 2 0.070 0.030 3 2.54 28.44 26.67 BSC 11 0.13 MIN 5.33 MAX 0.39 4.06 2.93 MIN 0.558 0.356 Dwg. MA-002-22 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS UCN5815EP Dimensions in Inches (controlling dimensions 18 0.013 0.021 12 19 0.219 0.191 11 0.026 0.032 0.456 0.450 0.495 0.485 0.050 INDEX AREA BSC 0.219 0.191 25 5 26 0.020 28 1 4 0.456 0.450 0.495 0.485 MIN 0.165 0.180 Dwg. MA-005-28A in Dimensions in Millimeters (for reference only) 18 0.331 0.533 12 19 5.56 4.85 11 0.812 0.661 11.58 11.43 12.57 12.32 1.27 INDEX AREA BSC 5.56 4.85 25 5 26 0.51 MIN 4.57 4.20 28 1 4 11.582 11.430 12.57 12.32 Dwg. MA-005-28A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS BiMOS II (Series 5800) & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE Function Output Ratings * Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit -120 mA 350 mA 350 mA 350 mA 350 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 5895 5821 5822 5841 5842 1.6 A 50 V 5829 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) -25 mA 100 mA 100 mA 60 V 30 V 40 V 5818-F and 6818 5833 5832 9-Bit PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit 8-Bit -25 mA 350 mA 60 V 50 V‡ 5815 5801 SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver 1.25 A 450 mA 50 V‡ 30 V * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5804 6817