DS1720 01

RT1720
60V Hot Swap Controller with Fault Timer
General Description
The RT1720 is an over-voltage and over-current
protection circuit. It monitors a circuit’s input voltage
and current with its adjustable over-voltage and
over-current thresholds and drives an external
N-MOSFET switch to connect the input to the output
voltage only when it is safe. Its wide input voltage
range makes it useful for high-voltage applications and
in systems that experience large transient voltages and
currents, such as automotive, telecom, and industrial
The RT1720 features include, open-drain fault and
applications.

During over-voltage events, the RT1720 quickly
reduces the gate drive of the external MOSFET to
regulate the output voltage at the level chosen by its
external FB resistors. During over-current events, when
the load draws excessive current, the RT1720 reduces
the gate drive to regulate the output current at the level
set by its external current sense resistor. In both cases
the output voltage or current is linearly regulated,
thermally stressing the MOSFET load switch. However,
an externally-adjustable timer limits the duration of

power-good outputs, and a shutdown input.
The RT1720 is available in the MSOP-10 package.
Features







Wide Input Operation Range : 5V to 80V
Negative Input Voltage Rating to −60V
Adjustable Output Clamp Voltage
Adjustable Over-Current Protection
Programmable Timer for Fault Protection
Low Shut Down Current
Internal Charge Pump N-MOSFET Drive
Fast 80mA MOSFET Shut-off for Overvoltage
Fault Output Indication
Applications




Automotive/Avionic Surge Protection
Hot Swap/Live Insertion
High-Side Switch for Battery Powered Systems
Intrinsic Safety Applications
MOSFET stress, eventually signaling a fault and then
turning off the MOSFET. The RT1720 then periodically
restarts operation to test if the fault has cleared. The
timer protects the MOSFET while allowing the load
circuit to temporarily operate normally through voltage
and current surges, such as load dump in automobiles
or spinning up disk drives.
Simplified Application Circuit
RSNS
VIN
5V to 80V
R3
VCC
Q1
VOUT
VOUT_Max = 60V
COUT
SNS
SHDN
GATE
VOUT
RT1720
FB
FLT
TMR
CTMR
GND
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DS1720-01
November 2015
R2
PGOOD
FAULT
R1
POWER
GOOD
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RT1720
Ordering Information
Marking Information
RT1720
Package Type
F : MSOP-10
01= : Product Code
YMDNN : Date Code
01=YM
DNN
Lead Plating System
G : Green (Halogen Free and Pb Free)
Pin Configurations
Note :
(TOP VIEW)
Richtek products are :

RoHS compliant and compatible with the current
FB
VOUT
GATE
SNS
VCC
requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering
processes.
10
2
9
3
8
4
7
6
5
TMR
GND
PGOOD
FLT
SHDN
MSOP-10
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
FB
Voltage Regulator Feedback Input. Connect a resistive divider from output to FB to
GND to set the maximum output voltage and voltage regulation set-point.
2
VOUT
Output Voltage Connection. VOUT is the lower reference voltage for the GATE
charge pump.
3
GATE
N-MOSFET Gate Drive Output.
4
SNS
5
VCC
Positive Supply Voltage Input.
6
̅̅̅̅̅̅̅̅
SHDN
Shutdown Control Input.
7
̅̅̅̅̅̅̅
FLT
Open-Collector Fault Output.
8
PGOOD
Open-Collector Power Good Indicator.
9
GND
Ground.
Current Sense Input. Connect a sense resistor from VCC to SNS to monitor the
current through the external N-MOSFET.
Fault Timer Input. Connect a capacitor from TMR to GND to program the maximum
10
TMR
time the part is allowed to remain in voltage regulation or current regulation mode.
TMR capacitor with value greater than 0.47F is recommended.
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DS1720-01
November 2015
RT1720
Function Block Diagram
VCC SNS
+
-
+
-
Charge
Pump
+
-
50mV
VOUT
GATE
FB
1.25V
FLT
Control Logic
PGOOD
VCC
28.5μA
1.4V
+
SHDN
+
1.2V
-
GND
-
3.5μA
0.5V
+
TMR
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November 2015
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RT1720
Operation
The RT1720 is an over-voltage and over-current
protection regulator that drives an external N-MOSFET
load switch. If the input voltage rises above the voltage
set-point (set by the voltage divider at FB) the RT1720
linear-regulates the load voltage using the external
load switch MOSFET, until the adjustable fault timer
trips and turns the MOSFET off to prevent overheating.
If the load draws more than the current set-point (set by
the external sense resistor connected between SNS
and VCC) the IC controls the load switch MOSFET as a
current source to limit the output current, until the fault
timer trips and turns off the MOSFET. These functions
protect the load and system from faults and surges
while potentially allowing the load to operate through
short-term voltage or current overloads.
The RT1720 operates over a wide supply voltage
range of 5V to 80V and can withstand reverse supply
voltages up to 60V below ground without damage.
Whenever it is enabled and no fault is detected, its
internal charge pump generates a gate-source voltage
of about 12V, fully enhancing the load switch MOSFET
charged by a 25A pull-up current and at 1.2V the ̅̅̅̅̅̅̅
FLT
output goes low, signaling a fault. The load switch
MOSFET remains on until VTMR reaches 1.4V, giving
time for any system housekeeping to occur before the
MOSFET turns off.
If the fault condition ends or the MOSFET switch is
turned off (eliminating the fault), the capacitor at TMR is
slowly discharged by a 3.5A pull-down current. When
VTMR reaches 0.5V, GATE begins charging up and
turns on the load switch, restarting the load
automatically. The slower TMR discharge rate allows a
low duty factor of operation, to prevent overheating the
MOSFET or the load.
The RT1720 open-drain PGOOD output rises when the
load switch turns on fully and the MOSFET’s source
approaches its drain voltage. This output signal can be
used to enable downstream devices or to signal a
system that normal operation can begin.
The IC’s ̅̅̅̅̅̅̅̅̅
SHDN input disables all functions and
reduces the VCC quiescent current down to 7A.
to minimize dissipation and voltage loss. During a fault
condition, an external capacitor (at TMR) is slowly
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DS1720-01
November 2015
RT1720
Absolute Maximum Ratings
(Note 1)

VCC, SNS --------------------------------------------------------------------------------------------------------------- 60V to 90V

̅̅̅̅̅̅̅̅̅ -------------------------------------------------------------------------------------------------------------------- 0.3V to 45V
SHDN

̅̅̅̅̅̅̅̅̅
SHDN Input Current --------------------------------------------------------------------------------------------------- 1mA

VOUT--------------------------------------------------------------------------------------------------------------------- 0.3V to 65V

GATE ------------------------------------------------------------------------------------- 0.3V to VOUT + AMR (GATE to VOUT)

GATE to VOUT -------------------------------------------------------------------------------------------------------- (Note 5)

FB, TMR ----------------------------------------------------------------------------------------------------------------- 0.3V to 10V

̅̅̅̅̅̅̅, PGOOD ----------------------------------------------------------------------------------------------------------- 0.3V to 12V
FLT

TMR, FB, VOUT, GATE, PGOOD, FLT

Power Dissipation, PD @ TA = 25C
(Note 6) --------------------------------------------------------- 10mA
MSOP-10 ---------------------------------------------------------------------------------------------------------------- 0.27W

Package Thermal Resistance
(Note 2)
MSOP-10, JA ---------------------------------------------------------------------------------------------------------- 365C/W

Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------------------ 150C

Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility
(Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)

Supply Input Voltage, VCC ------------------------------------------------------------------------------------------ 5V to 80V

Output Voltage, VOUT ------------------------------------------------------------------------------------------------ 5V to 60V

Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C

Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
Electrical Characteristics
(VCC = 12V, TA = 25C, unless otherwise specified)
Parameter
Symbol
VCC Supply Current
ICC
Reverse Input Current
IR
GATE Output High Voltage
(Note 5)
VGATE
GATE Pull-Up Current
IGATE_UP
Test Conditions
̅̅̅̅̅̅̅̅̅ unconnected
SHDN
Min
Typ
Max
Unit
--
2.3
5
mA
--
7
25
A
--
0.3
1
mA
--
9
12
--
12
16
VGATE = 12V
15
40
60
VGATE = 48V, VCC = 48V
30
70
120
̅̅̅̅̅̅̅̅̅ = GND
SHDN
VSNS = VCC = 30V,
̅̅̅̅̅̅̅̅̅
SHDN unconnected
VCC = 5V ; (VGATE  VOUT)
80V ≥ VCC ≥ 8V ; (VGATE 
VOUT)
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November 2015
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A
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RT1720
Parameter
GATE Pull-Down Current
Symbol
IGATE_ON
Test Conditions
Min
Typ
Max
Over Voltage, VFB = 1.4V,
VGATE = 12V
55
80
--
--
3
--
55
80
--
Over Current, VCC  VSNS =
120mV, VGATE = 12V
̅̅̅̅̅̅̅̅̅ =
Shutdown Mode, SHDN
GND, VGATE = 12V
Unit
mA
FB Servo Voltage
VFB
VOUT = 12V
1.2
1.25
1.3
V
FB Input Current
IFB
VFB = 1.25V
--
0.3
1
A
Over Current Fault
Threshold
VSNS
(VCC VSNS)
VCC = 12V
45
50
55
VCC = 48V
43
48
53
SNS Input Current
ISNS
VSNS = VCC = 12V to 48V
--
120
--
A
̅̅̅̅̅, PGOOD Leakage
FLT
Current
ILEAK
VPGOOD = VFLT = 10V,
̅̅̅̅̅̅̅̅̅
SHDN = GND
--
--
2
A
TMR Pull-Up Current
ITMR_UP
VTMR = 1V, VFB = 1.5V, or
VSNS = 60mV
--
25
--
A
TMR Pull-Down Current
ITMR_DOWN
VTMR = 1V, VFB = 1V, or
VSNS = 0V
2.5
3.5
5
A
TMR Fault Threshold
Voltage
VTMR_F
FLT changes state
1.14
1.2
1.26
V
TMR GATE Off Threshold
VTMR_L
GATE turns off
--
1.4
--
V
TMR GATE On Threshold
VTMR_UL
GATE turns on
--
0.5
--
V
̅̅̅̅̅, PGOOD Output Low
FLT
Voltage
VOL
ISINK = 2mA
--
300
500
ISINK = 0.1mA
--
120
300
VOUT = VCC = 12V
--
200
500
A
VOUT Pin Input Current
IOUT
--
--
2
mA
VOUT High Threshold
VOUT
0.4
0.8
1.1
V
̅̅̅̅̅̅̅̅̅
SHDN
Input
Voltage
VOUT = VCC = 12V,
̅̅̅̅̅̅̅̅̅
SHDN = GND
VOUT = VCC VOUT ;
PGOOD from Low to High
mV
mV
Logic-High
VCC = 12V to 48V
2.5
--
--
V
Logic-Low
VCC = 12V to 48V
--
--
0.5
V
V̅̅̅̅̅̅̅̅̅
SHDN = 3V
--
0.4
--
A
̅̅̅̅̅̅̅̅̅ Input Current
SHDN
I̅̅̅̅̅̅̅̅̅
SHDN
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. GATE to VOUT voltage is internally generated and clamped with specification shown in the electrical characteristics
table. External driving at GATE pin is forbidden because it may damage the device.
Note 6. All currents into device pins are positive, all currents out of device pins are negative. All voltages are referenced to GND
unless otherwise specified.
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RT1720
Typical Application Circuit
RSNS
10m
VIN
R3
100k
Q1
VCC
COUT
1μF
SNS
SHDN
GATE
VOUT
R2
102k
RT1720
TMR
FB
CTMR
R1
4.99k
0.47μF
FAULT
VOUT
FLT
VCC
DC/DC
Converter
PGOOD
GND
SHDN GND
Figure 1. 4.5A, 27V Over-voltage Regulator
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RT1720
Typical Operating Characteristics
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RT1720
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RT1720
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RT1720
Application Information
The RT1720 over-voltage and over-current protection
controller directly drives an external N-MOSFET load
switch to limit the voltage and current delivered to a
load and to protect the load. If the supply voltage
surges or the load draws excessive current, the
RT1720 controls the MOSFET gate to regulate the
voltage or current, keeping both below their adjustable
while CTMR is slowly discharged. The discharge is
slower than the charge rate to reduce the overall duty
factor for faults that last multiple TMR cycles. Once
̅̅̅̅̅̅ is released and the MOSFET
VTMR reaches 0.5V, FLT
thresholds. If any fault condition continues long enough
to for the adjustable-length fault timer to time out, the
MOSFET is turned off for some time and then the
MOSFET automatically turns on again. MOSFET
turn-on is slow and controlled, to prevent surge
currents, making the circuit useful for soft-start and hot
insertion applications.
tFAULT =
turns on again in a controlled soft-start.
The duration of a fault before the MOSFET turns off is :
CTMR  1.4V
25μA
The interval between ̅̅̅̅̅̅
FLT asserting low and the
MOSFET turning off is given by :
t WARNING =
CTMR  1.4V - 1.2V 
25μA
The MOSFET cool down period is given by :
Fault Timer
The RT1720’s fault timer is activated during any
over-voltage or over-current event. During an event,
the capacitor at TMR (CTMR) is slowly charged. When
the voltage at TMR reaches 1.2V, the open-drain
̅̅̅̅̅̅
FLT output goes low and when VTMR reaches 1.4V the
MOSFET switch is turned off disconnecting the load.
The time delay while VTMR charges from 1.2V to 1.4V
gives system software an opportunity to perform any
required housekeeping functions. The fault timing is set
by the external capacitor at TMR.
During an over-voltage fault, the MOSFET load switch
is used to regulate the output voltage at the voltage
level set by the FB resistive divider. During an
over-current fault the current is regulated at the current
level set by the current sense resistor at SNS. In both
of these events, regulating the output voltage or current
causes power dissipation in the external MOSFET load
switch. The fault timer sets the maximum duration of
tCOOLOFF =
CTMR  1.4V - 0.5V 
3μA
Over-Voltage Protection
The RT1720’s adjustable over-voltage protection
function uses an external voltage divider at FB, from
the output voltage to GND, to set the protection
threshold voltage. When the voltage at FB exceeds
1.25V (typical), GATE is discharged sharply and the
MOSFET begins turning off. As the MOSFET turns off
and the voltage at FB drops, GATE begins charging up
again. In this way, GATE reaches an equilibrium point
and the output voltage is linear-regulated with FB at
1.25V.
During an over-voltage event, TMR begins charging
while the over-voltage remains and GATE continues to
linear-regulate the output voltage. Eventually, VTMR
̅̅̅̅̅̅ output goes low,
may reach 1.2V (where the FLT
the power dissipation stress. Select CTMR to keep the
MOSFET power dissipation acceptable for the selected
external MOSFET. If the MOSFET can withstand
continuous dissipation for any possible fault, you can
disable the timer by connecting TMR to ground.
signaling a fault) and then 1.4V (where GATE will turn
completely off). If VTMR does not reach 1.4V and the
input voltage drops (allowing GATE to turn on fully),
TMR will slowly discharge. The capacitor at TMR
determines how long an over-voltage event may last
without causing GATE to turn off and the output voltage
When the fault timer reaches 1.4V and turns off the
to collapse completely.
MOSFET, or if the fault ends before VTMR reaches
1.4V, TMR slowly discharges the capacitor (CTMR). If
the fault timer reaches 1.4V, the MOSFET load switch
is turned off to allow the switch and the load to cool
The system operates normally while TMR charges
during an over-voltage event but the excess input
voltage is dropped across the external MOSFET and
heat is dissipated. The capacitor at TMR should be
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RT1720
chosen carefully to allow the system to operate through
expected over-voltage events without interruption, but
to prevent prolonged excessive dissipation that might
The current limit is set by the following equation :
ILIM = 50mV
RSNS
damage the external MOSFET or load.
The OVP voltage is set by the following equation :

VOUT_OVP = 1.25V  1+ R2
R1

where R1 and R2 are the FB voltage divider from VOUT
to GND.
MOSEFT Selection
The N-MOSFET load switch is the critical component
for the protection circuit. Choosing an appropriate
device is not difficult but there are many important
requirements. The most important are :

Over-Current Protection

on-resistance (RDS(ON))
maximum current rating
maximum drain-source voltage
maximum gate-source voltage
power dissipation and safe operating area (SOA)
gate threshold (for lower VIN applications)
The RT1720’s adjustable over-current protection
function uses a current-sense resistor between SNS
and VCC to set the protection threshold voltage.

When the voltage between these two pins exceeds
50mV (typical), GATE is discharged and the MOSFET

begins turning off. As the MOSFET turns off and the
output voltage drops, the load current decreases and
that state, the voltage loss and power dissipation are a
simple matter of RDS(ON) and current. Choose a device
the current sense voltage drop below the threshold.
GATE begins charging up again and reaches an
equilibrium point regulating the load current at the
threshold.
that doesn’t drop more voltage than is acceptable
considering the minimum value of the intended input
voltage and the voltage requirements of the load, and
one that can handle the required continuous current.
Avoid logic-level MOSFETs with their low VGS
maximum ratings, or add a GATE-VOUT clamp to
During an over-current event, TMR begins charging
while the over-current remains and GATE continues to
regulate the load current. Eventually, VTMR will reach
̅̅̅̅̅̅ output goes low, signaling a fault)
1.2V (where the FLT
and then 1.4V (where GATE will turn completely off). If
VTMR does not reach 1.4V and the excessive load


For most of the time the MOSFET will be fully on. In
avoid damaging. The RT1720 GATE drive voltage may
be as high as 14V so standard-threshold MOSFETs
with 20V VGS ratings is recommended.
When the MOSFET is turned off (whether in shutdown
current decreases (allowing GATE to turn on fully),
TMR will slowly discharge. The capacitor at TMR
or in OVP or OCP) the full input voltage appears across
the MOSFET. Choose a MOSFET with a maximum
determines how long an over-current event may last
without causing GATE to turn off and the output voltage
drain-source voltage exceeding your maximum input
surge voltage.
to collapse completely.
During an over-voltage (OV) event, the MOSFET will
The system continues to operate somewhat normally
(with reduced output voltage) while TMR charges
during an over-current event but the voltage dropped
across the external MOSFET during the high load
current causes high dissipation in the external
MOSFET and possibly the load. The capacitor at TMR
linear regulate the output voltage delivered to the load.
According to the timing determined by the capacitor
connected at the TMR pin, the circuit will turn the load
on and off periodically until the over-voltage ends.
While linear-regulating, the MOSFET will dissipate
power and heat up. Since TMR charges around seven
should be chosen carefully to allow the system to
operate through expected over-current events without
interruption, but to prevent prolonged excessive
dissipation that might damage the external MOSFET or
load.
times the rate that it discharges, the MOSFET will
linear regulate with a duty cycle of about 12% during a
long continuous OV event.
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RT1720
If the OV event is shorter than the TMR charge timing
then examine the MOSFET’s safe operating area (SOA)
graph, using VIN – VOUT for MOSFET drain to source
use one of the longer timed areas of the SOA graph
(perhaps the DC area) but adjust the IOC_THRESHOLD
value by the 12% duty cycle of the MOSFET on periods
voltage and ILOAD(VOUT) for the drain current, to
determine if the over-voltage event will cause MOSFET
damage. It may be helpful to adjust CTMR to meet the
MOSFET’s SOA limits.
to determine if the MOSFET will work. For thermal
management, the MOSFET dissipation during long
over-current events is :
If the OV event lasts more than one TMR cycle then the
MOSFET will turn on and off, dissipating power each
time it is on and linear regulating and cooling down
when it is off. In this case, use one of the longer-timed
areas of the SOA graph but adjust the drain current
value by the 12% duty cycle of the MOSFET on periods
where DC is the duty cycle of current regulation,
typically about 12%.
to determine if the MOSFET will work. For thermal
management, the MOSFET dissipation during long
over-voltage events is :
PDMOSFET(OV) = DC   VIN - VOUT   IOC_THRESHOLD
Parallel MOSFETs
Select a single MOSFET for most applications. If the
RDS(ON) target is very low and difficult to achieve at the
necessary voltage rating, multiple devices may be used
in parallel. Parallel devices can decrease the voltage
drop in normal operation and reduce dissipation.
PDMOSFET(OV) = DC   VIN - VOUT   ILOAD(VOUT)
However, SOA requirements must generally be met by
a single device.
where DC is the duty cycle of linear regulation, typically
In OV and OC conditions, GATE will decrease until the
programmed output voltage or current is maintained. In
that state, the MOSFET with the lowest threshold will
carry more current than other parallel MOSFETs with
higher thresholds, perhaps dramatically more. It’s
generally best to assume that one device will be
subjected to the entire SOA stress.
about 12%.
During an over-current (OC) event the MOSFET will
regulate the output current delivered to the load and
the output voltage will collapse to whatever voltage is
needed to sustain the OC threshold current. According
to the timing determined by the capacitor connected at
the TMR pin, the circuit will turn the load on and off
periodically until the over-current event ends. While
regulating the load current, the MOSFET will dissipate
power and heat up. Unlike an OV event, the output
voltage and the MOSFET’s drain-source voltage may
not be easily predicted. If the output is shorted the
voltage may collapse nearly to zero, placing the entire
input voltage across the MOSFET. Further, this type of
event is likely to continue for long periods. If the output
voltage during the OC event is not easily determined,
use zero for VOUT.
For the rare OC event that is short compared to the
TMR timing, examine the MOSFET’s safe operating
area (SOA) graph, using VIN – VOUT for MOSFET drain
to source voltage and your IOC_THRESHOLD for drain
current, to determine if the over-current event will
cause MOSFET damage.
If the OC event lasts more than one TMR cycle then the
MOSFET will turn on and off, dissipating power each
time it is on and cooling down when it is off. In this case,
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS1720-01
November 2015
Shutdown
The RT1720 enters a low current (7A typical)
̅̅̅̅̅̅̅̅̅ pin
shutdown mode when the voltage at the SHDN
goes below its 0.5V logic-low level. In shutdown all
functions are turned off.
For automatic start-up, it’s recommended to connect
SHDN pin to
(1) A voltage between 3V and 45V through a 100k
resistor.
(2) A voltage higher than 45V through a resistor with
minimum value of the following formula,
RSHDN = [ VSHDN_max – 45V ] / 0.25mA
No external voltage clamp is needed since the pin
clamps the input voltage. If external board leakage is
kept below 1A, the pin can be left open and an
internal current source will pull the pin voltage to about
2.5V. ̅̅̅̅̅̅̅̅̅
SHDN may also be driven by a logic output to
turn the IC on and off.
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RT1720
̅̅̅̅̅̅
FLT Output
The RT1720 includes an open-drain fault output that
indicates the state of the TMR pin voltage. Typically,
̅̅̅̅̅̅ is externally pulled up to some positive voltage
FLT
(such as VIN or a system logic supply) through a
resistor such as 100k.
When an over-voltage or over-current condition occurs,
the TMR pin begins charging CTMR. When VTMR is less
than the fault threshold (1.2V typical) the ̅̅̅̅̅̅
FLT output
remains unconnected allowing the external resistor to
pull it high. When VTMR exceeds the threshold, the
̅̅̅̅̅̅
FLT output is internally pulled to GND, signaling that
VTMR is nearing the GATE latch threshold (1.4V typical)
where the external MOSFET is turned completely off.
When GATE turns off or the fault ends, the ̅̅̅̅̅̅
FLT output
remains low while GATE is off, until VTMR reaches the
GATE unlatch threshold (0.5V typical) and GATE turns
̅̅̅̅̅̅ output rises
the external MOSFET back on. The FLT
when TMR reaches the threshold, indicating that GATE
is beginning to turn on.
PGOOD Output
The RT1720’s includes an open-drain PGOOD output.
The PGOOD output’s state relates to the VOUT voltage
relative to VIN, rather than the absolute level of VOUT.
Since it is open drain, PGOOD only shows a voltage
level if it is externally pulled up to some positive voltage
(such as VIN, VOUT, or a system logic supply) through
a resistor such as 100k.
VIN, PGOOD rises when VOUT is within the VOUT
high threshold (VIN-1V typical). Once high, PGOOD
stays high even if GATE turns off and VOUT falls, until
VOUT discharges to about 2V (typical). Once low,
PGOOD only rises again when GATE turns on and
VOUT again approaches VIN. PGOOD is always high
when SHDN is low and the IC is in its low-power
shutdown state, unless PGOOD is pulled up to a
voltage (like VOUT) that turns off in shutdown. PGOOD
is not designed as a traditional power-good indicator. A
traditional power-good indicator usually has a fixed
threshold voltage and indicates if VOUT is above or
below that threshold. The RT1720’s PGOOD output is
intended to indicate to downstream load devices that
GATE has fully turned on the external MOSFET load
switch and full output current is available. Enabling the
load before GATE has fully turned on is poor practice
because the load current causes high dissipation in a
partially-enhanced MOSFET. Also, drawing a large
load current through the partially-on MOSFET might
cause the output voltage to collapse, possibly leaving
system components in an unreliable logic state.
PGOOD goes high (open-circuit) only when VOUT is
reaching VIN and the MOSFET switch is nearly fully on.
On MOSFET turn off (if SHDN falls or if there is a
voltage or current fault) PGOOD stays high, allowing
the load to operate as long as possible, until VOUT falls
to about 2V (typical). Once PGOOD falls, it only rises
again if the output voltage nears VIN.
When GATE begins charging and VOUT rises toward
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14
is a registered trademark of Richtek Technology Corporation.
DS1720-01
November 2015
RT1720
Application Design Example
Using the typical application circuit as a design
example with the following specifications :





Automotive Application
VIN = 8V to 14V DC with transients up to 80V.
Output Voltage : VOUT 16V
Current Limit (ILIM) : 10A
Overvoltage Duration : 25ms
Output Over-voltage Protection Setting :
To set the OVP threshold at 16V, choose R1 as 4.99k
(giving a very robust 250A divider current) and
calculate R2 according to the following equation :
R2 = R1
V
- 1 = 58.9k
 1.25V
During an over-voltage or over-current event, GATE
will regulate the output voltage or current while CTMR
charges. When the voltage on the timing capacitor
(VTMR) reaches the fault threshold ( VTMR_F , 1.2V
̅̅̅̅̅̅ will go low, signaling that GATE will turn
typical) FLT
off the external MOSFET soon. The “housekeeping”
timing from ̅̅̅̅̅̅
FLT low ( VTMR_F ) to GATE turn-off
(VTMR_L) is :
tHOUSEKEEPING =
CTMR   VTMR_L - VTMR_F 
iTMR_UP
tHOUSEKEEPING =
0.47μF  1.40V - 1.2V 
= 3.76ms
25μA
OVP
Select R2 as a standard 1% value of 59k or use 56k
and calculate the resulting threshold as :


VOVP = 1.25V  R2 + 1 = 15.3V
R1
In the event of a long fault, GATE will turn on an off
repeatedly. The on and off timings (tGATE_ON and
tGATE_OFF) are controlled by the TMR charge and
discharge currents (iTMR_UP and iTMR_DOWN) and the
voltage difference between the TMR latch and unlatch
thresholds (VTMR_L - VTMR_UL) :
Current Limit Setting :
Calculate the sense resistor, RSNS, according to the
following formula :
RSNS =
VSNS
= 50mV = 5mΩ
ILIM
10A
Calculate the power dissipation of RSNS to avoid
overheating the sense resistor :
PDRSNS  = ILIM2  RSNS = 1.2  (10A)2  5mΩ = 0.6W
Select a 1W sense resistor or consider a parallel
combination of lower-wattage resistors.
tGATE_ON =
CTMR   VTMR_L - VTMR_UL 
iTMR_UP
tGATE_ON =
0.47μF  1.40V - 0.5V 
= 16.9ms
25μA
tGATE_OFF =
CTMR   VTMR_L - VTMR_UL 
iTMR_DOWN
tGATE_OFF =
0.47μF  1.40V - 0.5V 
= 141ms
3μA
Over-Voltage/Over-Current Timer Setting :
Calculate the value of fault timing capacitor (CTMR)
using the typical TMR pull-up current and TMR latch
threshold with the following formula :
CTMR =
tLATCH  iTMR_UP
25ms  25μA
=
= 0.45μF
VTMR_L
1.4V
Select the standard value of 0.47F and calculate the
resulting fault timing:
tLATCH =
CTMR  VTMR_L
0.47μF  1.4V
=
= 26.3ms
iTMR_UP
25μA
Choose the MOSFET :
Select the Q1 MOSFET VDS rating, allowing for your
maximum input voltage and transients. Then select an
operating RDS(ON) to meet any voltage drop
specifications and your on-state dissipation allowance.
Finally, its package must be able to handle that
dissipation and control its operating temperature.
Most manufacturers list a maximum RDS(ON) at 25C
and provide a typical characteristics curve from which
values at other temperatures can be estimated. You
can also use the below equation to estimate maximum
RDS(ON) from the 25C specification :
RDS(ON)_MAX =  TJ(MAX) - 25C  0.5%/C
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS1720-01
November 2015
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15
RT1720
Given the 8V minimum input and the 10A output
current, the RDS(ON) must be very low to avoid dropping
a large percentage of the input voltage. To limit the
drop to 1% of 8V (80mV) requires an 8m maximum.
Therefore, the 25°C specification should be about 5m.
The package needs to dissipate about (10A)2 x 8m =
800mW into a hot automotive ambient temperature.
Something like the Vishay SQM120M10-3m8, with its
100V VDS rating, 6.4m maximum at 125°C, and its
40°C/W (on a copper PCB) D2Pak package should be
more than adequate.
Higher-Voltage Transients
If voltage transients above 80V are expected, there is
one possible approach (shown in Figure 3). The input
voltage can simply be clamped at less than 80V using a
Zener diode, transient voltage suppressor, or metal
oxide varistor. Noted that the voltage clamping device
D1 must be able to absorb the entire energy of the
input voltage transient.
VIN
Some applications have to withstand reverse input
Figure 2 shows one possible application. In normal
operation, GATE charges both MOSFET gates. In case
of reverse input voltage, Q3 turns on and pulls Q2’s
gate below ground and keeps its VGS near zero, while
GATE’s internal protection diode clamps its voltage at
ground, keeping Q1 off. The RT1720 IC’s VCC pin is
designed to withstand reverse voltage and needs no
additional protection.
RSNS
10mohm
VIN
Q2
Si4190DY
+24V Typical
-60V to +80V Transients
Q1
Si4190DY
VOUT
4.5A
Q3
2N3904
R5
100k
VCC
R5
100k
SNS
VCC
SHDN
GATE
VOUT
RT1720
R3
FB
GND
R4
Figure 3. Withstanding Higher-Voltage Transients
TMR Ratio Setting
The turn on time represents the time takes the circuit to
charge up the output capacitance and load. The turn on
time is a function of the type of control; current limit,
power limit, or dV/dt control for MOSFET. To reduce
heat dissipation of the MOSFET during OC/OV
protection, the lower ratio of tGATE_ON to tGATE_OFF can
be achieved by adding D1 and Q2 as shown in Figure 4
below.
RSNS
VOUT
Q1
C3
C2
R1
R2
GATE
0.1µF
VOUT
TMR
R3
102K
RT1720
VCC
SNS
SHDN
FB
R4
4.99K
FAULT
1µF
VIN
R7
100k
SNS
SHDN
VOUT
1µF
R6
100k
D1
1N4148
Q1
Si4190DY
D1
3.0SMCJ58A
Diodes Inc.
Reverse Input Voltage Blocking
voltages such as a battery connected backwards or
negative-voltage transients. Typically such applications
use a blocking diode in series with the input voltage. In
applications where the diode’s voltage drop or power
dissipation is unacceptable, back-to-back N-MOSFETs
may be an acceptable cost.
RSNS
10m
+24V Typical
+120V Transients
Q2
GATE
VOUT
TMR
D1
R3
RT1720
PGOOD
FLT
GND
FB
CTMR
R4
PGOOD
FLT
GND
Figure 2. Reverse-Voltage Application
Figure 4. Gate On and Gate Off Time Setting Design
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is a registered trademark of Richtek Technology Corporation.
DS1720-01
November 2015
RT1720
Thermal Considerations
operating ambient temperature for fixed TJ(MAX) and
Since this device dissipates little power in operation,
thermal resistance, JA. The derating curve in Figure 5
even the 270mW MSOP-10 package is unlikely to
overheat due to its own operation. Its 1mA supply
current, even with an 80V input voltage range, makes a
discussion of thermal resistance, package dissipation,
and thermal layout almost unnecessary.
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
0.4
However, carefully consider the placement of the
RT1720 in the overall layout with nearby components,
particularly for high-temperature applications (such as
automotive) and in conjunction with high-temperature
rated MOSFETs that can operate with junction
temperatures well above this IC’s 125°C maximum
recommended operating range. Do not allow the
combination
of
internal
dissipation,
ambient
temperature, and dissipation from surrounding
components (MOSFETs, sense resistors, DC/DC
converter components) to raise the IC’s junction
temperature above its 125°C maximum. The RT1720
includes a thermal shutdown state (typically activated
at 150°C) that pulls GATE low and turns off the external
MOSFET.
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
PD(MAX) = (TJ(MAX)  TA) / JA
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction to
ambient thermal resistance.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For MSOP-10 package, the thermal
resistance, JA, is 365C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
Four-Layer PCB
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Power Dissipation
Layout Considerations
The RT1720 has relatively simple layout requirements.
Place the VCC, VOUT, and TMR capacitors close to
their respective pins, to avoid noise issues.
Place FB voltage divider resistors close to their
respective pins to avoid threshold detection problems.
Don’t route these connections next to noisy traces such
as high-speed digital lines or DC/DC switching nodes.
Avoid current sensing errors by using Kelvin sensing in
the RSNS layout (Figure 6). Connect VCC and SNS to
RSNS avoiding any high current-carrying copper.
Connecting to the inside of RSNS is recommended.
Connect GND and the package’s backside pad (if any)
to the bypass and timing capacitor grounds and voltage
divider grounds with a wide solid copper ground area,
to avoid noise issues.
The recommended PCB layout guide lines are listed as
follows :

The current sense resistor RSNS is recommended
to achieve accurate current Kelvin sensing
connection.
dissipation at TA = 25C can be calculated by the
following formula :

PD(MAX) = (125C  25C) / (365C/W) = 0.27W for
MSOP-10 package
The input capacitors CIN must be placed as close
to the VCC pin as possible.

Connect the GND pin and exposed pad to a large
ground plane for maximum power dissipation and
noise reduction.
The maximum power dissipation depends on the
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November 2015
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RT1720
RSNS
CIN
PATH
POWER
VCC
SNS
GND
RT1720
Figure 6. Current Sense Resistor Kelvin Connection.
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is a registered trademark of Richtek Technology Corporation.
DS1720-01
November 2015
RT1720
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.810
1.100
0.032
0.043
A1
0.000
0.150
0.000
0.006
A2
0.750
0.950
0.030
0.037
b
0.170
0.270
0.007
0.011
D
2.900
3.100
0.114
0.122
e
0.500
0.020
E
4.800
5.000
0.189
0.197
E1
2.900
3.100
0.114
0.122
L
0.400
0.800
0.016
0.031
10-Lead MSOP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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November 2015
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