The following document contains information on Cypress products. AN07-00154-1E FR Family 32-BIT MICROCONTROLLER MB91F313 HDMI-CEC AN07-00154-1E Revision History Revision 1.0 Date Description March 7, 2008 Initial release 1 AN07-00154-1E All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Copyright© 2008 FUJITSU MICRELECTRONICS LIMITED all rights reserved 2 AN07-00154-1E Table of Contents Revision History ...................................................................................................................................1 Table of Contents ..................................................................................................................................3 1 Introduction...................................................................................................................................4 2 Outline of MB91F313...................................................................................................................5 3 Outline of reception function HDMI-CEC mounted on MB91F313 ............................................6 3.1 4 Operation of HDMI-CEC reception......................................................................................6 Input waveform into HDMI-CEC reception function ...................................................................7 4.1 HDMI-CEC format and its reception operation....................................................................7 5 Example of initialization flow of HDMI-CEC reception function................................................9 6 Example of HDMI-CEC circuit in MB91F313...........................................................................10 6.1 Configuration ......................................................................................................................10 6.2 Example of simple MB91F313 circuit................................................................................10 3 AN07-00154-1E 1 Introduction This document describes the usage of HDMI-CEC technology used with MB91F313, which begins being adopted in TV and AV devices. Up to now, analog signals have been used to send pictures and voices on signal lines to connect TVs and HD recorders. Generally, cables of the RCA terminal, S terminal, and D terminal have been used for picture transmission and cables of the RCA terminal for voice transmission. Since the analog signals to send pictures and voices are continuous voltage values, there has been the problem that they are subject to noise influences from the outside and inside. To solve the problem, HDMI technology has been developed for home-use electric apparatuses by arranging the personal computer’s DVI standard already supporting the digital video signal. In HDMI technology, a single cable can transfer pictures, voices, and device information. CEC is one function of the HDMI for device control, which has been defined in HDMI ver1.2a and was established in December, 2005. The function controls the relationship among each device mutually; for example, operation for multiple digital apparatuses can be integrated into one remote controller. This document is written for the purpose of smooth introduction of CEC function when using MB91F313. Note that this document is based on High-Definition Multimedia Interface Specification Version. 1.3a. *HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks and registered trademark of HDMI Licensing LLC. 4 AN07-00154-1E 2 Outline of MB91F313 MB91F313 has the HDMI-CEC reception function, allowing its hardware to receive CEC data without software intervention. Although data reception through software requires the pulse width measuring function such as PWC to process each bit, this function can make batch processing as one set of data since it can receive data in parallel, resulting in reduced loads of software processing. Sub-clock can be input to the HDMI-CEC reception circuit from the external. So, this sub-clock is entered regardless of the clock of CPU or peripheral function and the HDMI-CEC reception circuit can continuously operate even in the timer mode that stops the main clock. MB91F313 should receive the sub-clock. Therefore, In addition, if a transmission destination address is set to the address setting resister, an interrupt can occur only when MB91F313 receives a specified transmission destination address, which can greatly reduce power consumption in CEC reception standby state. For the specifications of power consumption, see the datasheet. Normal operation Main sleep Timer mode CPU Operates Stops Stops Peripheral function Operates Operates Stops HDMI-CEC function Operates Operates Operates Main clock Oscillates Oscillates Stops Sub-clock Oscillates Oscillates Oscillates Power consumption Normal Operation Mian Sleep Timer Mode 5 AN07-00154-1E 3 Outline of reception function HDMI-CEC mounted on MB91F313 HDMI-CEC reception function should be used only for reception. This macro has the circuit configuration below, which detects Low width between falling edge and rising edge, compares it with the setting value, and judges 0/1 of the received data. The hardware automatically compares the received address with the specified address, and if the addresses match, then the hardware sets the received data in the data storage register. Internal bus Count clock (1) Counter RCIN (3) Noise (4) Edge filter detection (5) Latch Overflow (2) Interrupt control register Start bit (6) Comparator ACK 0 Detection 1 Detection (8) Shifter Peripheral clock (10) Clock 32 KHz (9) Address setting register (11) Endian exchange Count clock (7) High width register selection and (12) Data storage register (13) Reception control division (14) Division setting register HDMI-CEC reception macro MB91F313 3.1 Operation of HDMI-CEC reception The signal entered from RCIN pin passes through the noise filter (3) in which noise is removed, and goes into the edge detection circuit (4). counter (1) and the latch circuit (5). Rising and falling signals are entered into the The counter (1) into which the clock selected by the clock selection and division circuit (10) enters, generates the overflow signal if it counts the 128 clock or the 256 clock. The signal entered from the latch circuit (5) into the comparator (6) is compared with the High width register (7). The High width register (7) has the time being set to detect the start bit, data “1”, and data “0”. The signal is judged by comparing with this time period. The signal generated from the comparator (6) goes into the shifter (8) and when 8-bit data are stored, they are compared with the address setting register (9). interrupt should occur. If they match, the The signal from the comparator above is also entered into the Endian-exchange circuit (11) and stored in the data storage register (12). 6 AN07-00154-1E 4 Input waveform into HDMI-CEC reception function 4.1 HDMI-CEC format and its reception operation CEC communication formats are roughly classified into the format for transmission start and format for reception. The 1st frame consists of the start bit, transmission source address, transmission destination address, EOM, and ACK and the 2nd frame consists of the transmission data, EOM, and ACK. 1st frame Start bit 2nd frame Transmission Transmission source address destination address Transmissionr data EOM ACK EOM ACK 2nd frame 1st frame Start bit Transmission source address Transmission destination address MSB EOM ACK Data EOM ACK LSB For data transmission, the format of the 1st frame is used to send the transmission source address and the transmission destination address and then the format of the 2nd frame is used to send arbitrary number of data set. Since HDMI-CEC reception function can detect the transmission destination address in the 1st frame, the device address setting register can be used so that it cannot be restored when it receives other than a specified value in it. Data of the 1st frame, the 2nd frame and later is stored as 8-bit parallel data in the data storage register. If overflow occurs after detecting the start bit, the counter overflow detection bit can be set to generate an interrupt. If the received data is normal, the reception side should return ACK for each frame to the source side. In addition, since the source uses EOM to notify the destination of the end of the data, EOM detection bit is used for confirmation. 7 AN07-00154-1E “1” and “0”of the start bit can be identified by using Low/High width of the pulse. Its cycle should be set by the start bit High width setting register, High width setting register A, and High width setting register B. In HDMI-CEC mode, since the input signal is inverted internally, High width comparison is applied to Low width. A value (ex. 3.48 ms) below the minimum value of 3.5 ms for the start bit Low width should be set in the start bit High width register. Since High width setting register A functions as a noise filter, a value (ex. 0.397 ms) below the minimum value of 0.4 ms for data “1” Low width should be set in the register A. Since High width setting register B is used for the threshold value for data “0” and “1”, a value (ex. 0.128 ms) above 0.8 ms and below 1.3 ms should be set in the register B. Data ”1” Start bit 4.5[ms] Data ”0” 2.4[ms] 2.4[ms] Typical: 3.7[ms] Typical: 0.6[ms] Typical: 1.5[ms] Max.: 3.9[ms] Max.: 0.8[ms] Max.: 1.7[ms] Min.: 3.5[ms] Min.: 0.4[ms] Min.: 1.3[ms] 8 AN07-00154-1E 5 Example of initialization flow of HDMI-CEC reception function Initialization function for HDMI-CEC reception function Starts initialization for HDMI-CEC reception. Interrupt function for HDMI-CEC reception Starts interrupt operation for HDMI-CEC reception. Sets MOD field of RCCR to HCMI-CEC mode. Overflow detected? Sets THSEL (sense selection) of RCCR to “1”. Overflow error handling Yes. OVF=1 No. OVF=0 Enables comparison between received address and device CEC data processing address in ADRCE (address comparison permission) of RCCR. - Obtaining received data from RCDT Sets the overflow time to 4 ms (128 clock: 32 KHz) in - Obtaining ST, ACK, EOM states OVFSEL bit of RCCR. Enables an interruption in STIE of RCST. End Enables an interruption in ACKIE of RCST. Enables an interruption in OVFIE of RCST. Set Low width of start bit to 3.48 ms (114 clock: 32.768 KHz) in RCSHW. Set noise removal width to 0.40 ms (13 clock: 32.768 KHz) in RCDAHW. Set threshold value of data “1” and “0” to 1.28 ms (42 clock: 32.768 KHz) in RCDBHW. Selects sub-clock in CKSEL bit in RCCKD. Enables operation with EN bit in RCCT. End 9 AN07-00154-1E 6 Example of HDMI-CEC circuit in MB91F313 6.1 Configuration HDMI-CEC reception function is used to receive CEC commands. In addition, PPG output having N-ch open/drain function is used to send CEC commands. As shown in the simple circuit example below, CEC input pins connect to CEC signal lines. 6.2 Example of simple MB91F313 circuit 3.3[V] CEC input/output 1.8[V] 27 KΩ MB91F313 2, 64, 92 pin VDDI 32 pin RCIN0 HDMI-CEC 54 pin PPG0 30, 40, 43, 44, 57, 90, 120 pin 3.3[V] VDDE 32.768KHz 59 pin X0A 58 pin INITX 10 KΩ 10 MΩ Dumping resistor Dumping resistor 80 pin TRSTX 60 pin X1A Reset Switch 62 pin X1 65 pin MD0 66 pin MD1 63 pin X0 67 pin MD2 16.5 MHz 1, 31, 41, 42, 61, 91 pin VSS * Select the dumping resistors and the capacitors for the oscillator based on the matching data of the used oscillator. The matching data is available from the manufacturer of the oscillator * An additional circuit should be required for on-board debugging and on-board flash writing. 10