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The following document contains information on Cypress products.
AN706-00053-1v0-E
32-BIT MICROCONTROLLER
FM3 family Application Note
The usage to control FRAM by I2C and SPI
ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
AN706-00053-1v0-E
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examples is presented solely for reference to examples of operations and uses of FUJITSU
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Copyright© 2013 FUJITSU SEMICONDUCTOR LIMITED all rights reserved
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Revision History
Rev
Date
Remark
1.0
Jul. 23, 2012
First Edition
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Table of Contents
Revision History...................................................................................................................... 2
Table of Contents.................................................................................................................... 3
Target products ....................................................................................................................... 5
1
Introduction...................................................................................................................... 8
2
References ...................................................................................................................... 9
3
FRAM ............................................................................................................................. 11
3.1
What is FRAM ......................................................................................................... 11
3.2
The Number of Rewrite Operations ........................................................................ 11
3.3
Application.............................................................................................................. 12
3.4
MB85RC64, MB85RC128 ...................................................................................... 13
3.4.1
Overview ......................................................................................................... 13
3.4.2
Samples .......................................................................................................... 15
3.5
4
5
3.5.1
Overview ......................................................................................................... 16
3.5.2
Samples .......................................................................................................... 18
Confirmed Operation Environment ............................................................................... 19
4.1
For MB85RC128 (I2C Control) ............................................................................... 19
4.2
For MB85RS256A (SPI control) ............................................................................. 20
Hardware ....................................................................................................................... 21
5.1
For MB85RC128 (I2C control)................................................................................ 21
5.1.1
Hardware Block .............................................................................................. 21
5.1.2
Function of the Microcontroller MB9AF132L Used in the I2C Control ............ 21
5.2
6
MB85RS64, MB85RS128A, and MB85RS256A ................................................... 16
For MB85RS256A (SPI control) ............................................................................. 22
5.2.1
Hardware Block .............................................................................................. 22
5.2.2
Functions of the Microcontroller MB9BF506R Used in the SPI Control ........ 22
Software ........................................................................................................................ 23
6.1
For MB85RC128 (I2C Control) ............................................................................... 23
6.1.1
Software Block ................................................................................................ 23
6.1.2
Setting ............................................................................................................. 24
6.1.2.1
Register Setting ....................................................................................... 24
6.1.2.2
MFS (I2C) Setting .................................................................................... 24
6.1.2.3
Interrupt Setting ....................................................................................... 25
6.1.3
API .................................................................................................................. 26
6.1.4
Operation Flow ............................................................................................... 28
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6.2
6.1.4.1
Initialization Function of the FRAM Driver............................................... 28
6.1.4.2
End Function of the FRAM Driver ........................................................... 28
6.1.4.3
Data Write Function to FRAM ................................................................. 29
6.1.4.4
Data Read Function from FRAM ............................................................. 30
For MB85RS256A (SPI Control) ............................................................................ 31
6.2.1
Software Block ................................................................................................ 31
6.2.2
Setting ............................................................................................................. 32
6.2.2.1
Register Setting ....................................................................................... 32
6.2.2.2
Setting MFS (SPI) ................................................................................... 33
6.2.2.3
Interrupt Setting ....................................................................................... 34
6.2.3
API .................................................................................................................. 35
6.2.4
Operation Flow ............................................................................................... 37
6.2.4.1
Initialization Function of the FRAM Driver............................................... 37
6.2.4.2
End Function of the FRAM Driver ........................................................... 38
6.2.4.3
Data Write Function for FRAM ................................................................ 39
6.2.4.4
Data Read Function from FRAM ............................................................. 41
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Target products
This application note is described about below products;
(TYPE0)
Series
Product Number (not included Package suffix）
MB9B500A
MB9BF504NA,MB9BF505NA,MB9BF506NA,
MB9BF504RA,MB9BF505RA,MB9BF506RA
MB9B500B
MB9BF504NB,MB9BF505NB,MB9BF506NB,
MB9BF504RB,MB9BF505RB,MB9BF506RB
MB9B400A
MB9BF404NA,MB9BF405NA,MB9BF406NA,
MB9BF404RA,MB9BF405RA,MB9BF406RA
MB9B300A
MB9BF304NA,MB9BF305NA,MB9BF306NA,
MB9BF304RA,MB9BF305RA,MB9BF306RA
MB9B300B
MB9BF304NB,MB9BF305NB,MB9BF306NB,
MB9BF304RB,MB9BF305RB,MB9BF306RB
MB9B100A
MB9BF102NA,MB9BF104NA,MB9BF105NA,MB9BF106NA,
MB9BF102RA,MB9BF104RA,MB9BF105RA,MB9BF106RA
(TYPE1)
Series
Product Number (not included Package suffix）
MB9A110A
MB9AF111LA,MB9AF112LA,MB9AF114LA
MB9AF111MA,MB9AF112MA,MB9AF114MA,MB9AF115MA,MB9AF116MA
MB9AF111NA,MB9AF112NA,MB9AF114NA,MB9AF115NA,MB9AF116NA
MB9A310A
MB9AF311LA,MB9AF312LA,MB9AF314LA
MB9AF311MA,MB9AF312MA,MB9AF314MA,MB9AF315MA,MB9AF316MA
MB9AF311NA,MB9AF312NA,MB9AF314NA,MB9AF315NA,MB9AF316NA
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(TYPE2)
Series
Product Number (not included Package suffix）
MB9B110T
MB9BF116S,MB9BF117S,MB9BF118S
MB9BF116T,MB9BF117T,MB9BF118T
MB9B210T
MB9BF216S,MB9BF217S,MB9BF218S
MB9BF216T,MB9BF217T,MB9BF218T
MB9B310T
MB9BF316S,MB9BF317S,MB9BF318S
MB9BF316T,MB9BF317T,MB9BF318T
MB9B410T
MB9BF416S,MB9BF417S,MB9BF418S
MB9BF416T,MB9BF417T,MB9BF418T
MB9B510T
MB9BF516S,MB9BF517S,MB9BF518S
MB9BF516T,MB9BF517T,MB9BF518T
MB9B610T
MB9BF616S,MB9BF617S,MB9BF618S
MB9BF616T,MB9BF617T,MB9BF618T
MB9BD10T
MB9BFD16S,MB9BFD17S,MB9BFD18S
MB9BFD16T,MB9BFD17T,MB9BFD18T
(TYPE3)
Series
Product Number (not included Package suffix）
MB9A130L
MB9AF131K,MB9AF132K
MB9AF131L,MB9AF132L
MB9A130LA
MB9AF131KA,MB9AF132KA
MB9AF131LA,MB9AF132LA
(TYPE4)
Series
Product Number (not included Package suffix）
MB9B110R
MB9BF112N,MB9BF114N,MB9BF115N,MB9BF116N
MB9BF112R,MB9BF114R,MB9BF115R,MB9BF116R
MB9B310R
MB9BF312N,MB9BF314N,MB9BF315N,MB9BF316N
MB9BF312R,MB9BF314R,MB9BF315R,MB9BF316R
MB9B410R
MB9BF412N,MB9BF414N,MB9BF415N,MB9BF416N
MB9BF412R,MB9BF414R,MB9BF415R,MB9BF416R
MB9B510R
MB9BF512N,MB9BF514N,MB9BF515N,MB9BF516N
MB9BF512R,MB9BF514R,MB9BF515R,MB9BF516R
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(TYPE5)
Series
Product Number (not included Package suffix）
MB9A110K
MB9AF111K,MB9AF112K
MB9A310K
MB9AF311K,MB9AF312K
(TYPE6)
Series
Product Number (not included Package suffix）
MB9AB40N
MB9AFB41L,MB9AFB42L,MB9AFB44L,MB9AFB41M,MB9AFB42M,
MB9AFB44M,MB9AFB41N,MB9AFB42N,MB9AFB44N
MB9AB40NA
MB9AFB41LA,MB9AFB42LA,MB9AFB44LA,MB9AFB41MA,MB9AFB42MA,
MB9AFB44MA,MB9AFB41NA,MB9AFB42NA,MB9AFB44NA
MB9AA40N
MB9AFA41L,MB9AFA42L,MB9AFA44L,MB9AFA41M,MB9AFA42M,
MB9AFA44M,MB9AFA41N,MB9AFA42N,MB9AFA44N
MB9AA40NA
MB9AFA41LA,MB9AFA42LA,MB9AFA44LA,MB9AFA41MA,MB9AFA42MA,
MB9AFA44MA,MB9AFA41NA,MB9AFA42NA,MB9AFA44NA
MB9A340N
MB9AF341L,MB9AF342L,MB9AF344L,MB9AF341M,MB9AF342M,
MB9AF344M,MB9AF341N,MB9AF342N,MB9AF344N
MB9A340NA
MB9AF341LA,MB9AF342LA,MB9AF344LA,MB9AF341MA,MB9AF342MA,
MB9AF344MA,MB9AF341NA,MB9AF342NA,MB9AF344NA
MB9A140N
MB9AF141L,MB9AF142L,MB9AF144L,MB9AF141M,MB9AF142M,
MB9AF144M,MB9AF141N,MB9AF142N,MB9AF144N
MB9A140NA
MB9AF141LA,MB9AF142LA,MB9AF144LA,MB9AF141MA,MB9AF142MA,
MB9AF144MA,MB9AF141NA,MB9AF142NA,MB9AF144NA
(TYPE7)
Series
Product Number (not included Package suffix）
MB9A130N
MB9AF131M,MB9AF132M
MB9AF131N,MB9AF132N
MB9AA30N
MB9AFA31M,MB9AFA32M
MB9AFA31N,MB9AFA32N
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1
Introduction
This application note explains the sample program that controls Fujitsu semiconductor
FRAM by I2C or SPI by using the multi-function serial interface (hereinafter called MFS) of
the Fujitsu semiconductor microcontroller FM3 family.
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2
References
[1] FRAM data sheet(I2C control)
MB85RC64
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘DS05-13109’.)
MB85RC128
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘DS05-13110’.)
[2] FRAM data sheet(SPI control)
MB85RS64
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘DS501-00012’.)
MB85RS128A
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘DS501-00008’.)
MB85RS256A
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘DS501-00007’.)
[3] 32-BIT MICROCONTROLLER FM3 PERIPHERAL MANUAL
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘MN706-00002’.)
[4] 32-BIT MICROCONTROLLER FM3 PERIPHERAL MANUAL Communication Macro Part
http://edevice.fujitsu.com/system/document/en/
(Please search by the Document Search of this URL using a keyword ‘MN706-00024’.)
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[5] Cortex-M3 r2p0 Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337h/DDI0337H_cortex_m3_r2p0_
trm.pdf
(Remark) Please see to this URL for FM3 family of Type0.
[6] Cortex-M3 r2p1 Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337i/DDI0337I_cortexm3_r2p1_trm
.pdf
(Remark) Please see to this URL for FM3 family of except Type0.
* These URLs may change without notice.
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3
FRAM
3.1
What is FRAM
FRAM (Ferroelectric Random Access Memory) is also known as FeRAM. It is a type of
memory that uses a ferroelectric film as a capacitor to store data.
FRAM has the characteristics of both ROM and RAM, and advantages in high speed
writing, high endurance, low power consumption, and tamper resistance.
Table 1 shows the comparison between FRAM and other memories.
Table 1 Comparison between FRAM and other memories
Memory type
Data
FRAM
EEPROM
FLASH
SRAM
Non-volatile
Non-volatile
Non-volatile
Volatile
Erase + write
Sector erase + Overwrite
rewrite Overwrite
method
write
Write cycle time
150ns
Endurance
*1
5ms
10μs
55ns
1012(1-trillion
106(1-million
105(100-thousand Unlimited
cycles) *2
cycles)
cycles)
*1 Specs of 256Kb stand-alone FRAM memory
*2 Total cycles of read and write operation (See “3.2The Number of Rewrite
Operations”)
The maximum cycles of the FRAM products
3.2
The Number of Rewrite Operations
FRAM is a memory that uses the polarization phenomenon of a ferroelectric substance.
It repeats the ferroelectric polarization inversion operation, fatigues, and reduces the
polarization amount. In the FRAM memory cell, polarization inversion occurs in the read
cycle as well as the write cycle. When “1” is read at the memory cell, the polarization
inversion occurs and “1” turns to “0.” Therefore, “1” is rewritten (in the case where “0” is
read, the polarization inversion does not occur). Thus, the warranty of the rewrite count
of FRAM is specified by the total of access counts in each memory cell, regardless of
the read/write cycle.
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3.3
Application
FRAMs corresponding to the sample program introduced in this document are shown in
Table 2.
Table 2 FRAM corresponding to the sample program
Model
MB85RC64
MB85RC128
MB85RS64
Communication
Communication
Write/Read
interface
speed
endurance
400kbps(MAX)
1012 cycles/byte
2
IC
2
IC
SPI
400kbps(MAX)
25Mbps(MAX)
Capacity (bit)
64K(8K x 8)
10
12
cycles/byte
128K(16K x 8)
10
10
cycles/byte
64K(8K x 8)
10
MB85RS128A
SPI
25Mbps(MAX)
10
cycles/byte
128K(16K x 8)
MB85RS256A
SPI
25Mbps(MAX)
1010 cycles/byte
256K(32K x 8)
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3.4
MB85RC64, MB85RC128
3.4.1
Overview
MB85RC64 and MB85RC128 are accessible from MCU by the 2-wire serial interface
(compatible with the world standard I2C BUS).
The pin assignment is shown in Figure 1, and the names and functions of pins are
shown in Table 3.
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Figure 1 Pin assignment of MB85RC64 and MB85RC128 (Top View)
Table 3 Names and functions of pins
Pin Name
Function
A0, A1, A2
Device address pin
When several devices are connected to the same data bus, this pin is used
to recognize each device. Each device needs to be set to a different logic.
VSS
Ground pin
SDA
Serial data input/output pin
SCL
Serial clock pin
The data are taken in by the rising edge of the clock and output by the
falling edge.
WP
Write-protected pin
In the case of “H” level, write process becomes disabled. In the case of “L”
level, rewrite of all memory areas is possible.
VDD
Power supply voltage pin
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The system structure example is shown in Figure 2.
VDD
SOT
SCK
SDA
SCL
SDA
SCL
SDA
SCL
MFS(I2C)
I2C
I2C
I2C
FM3
(Master)
FRAM
(Slave)
FRAM
(Slave)
FRAM
(Slave)
A2 A0 A0
0 0 0
A2 A0 A0
0 0 １
A2 A0 A0
0 1 0
Figure 2 System structure example
In addition, for details of FRAM I2C control, see the FRAM data sheet (I2C control) [1].
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3.4.2
Samples
FRAM used in the sample, setting, and command are shown in Table 4.
Table 4 FRAM used in the sample, setting, and command
Content
Remarks
FRAM
MB85RC128
128K bits (16K x 8 bits)
Baud rate
100kbps
Device address
“000”
WP pin
“L” fixed
Command
Byte Write
When the specified byte number is 1
byte
Page Write
When the specified byte number is 2
bytes or higher
Random Read
When the specified byte number is 1
byte
Sequential Read
When the specified byte number is 2
bytes or higher
For details of the command, see the FRAM data sheet (I2C control) [1].
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3.5
MB85RS64, MB85RS128A, and MB85RS256A
3.5.1
Overview
MB85RS64, MB85RS128A, and MB85RS256A are accessible from the MCU by the
serial peripheral interface (SPI).
The pin assignment is shown in Figure 3, and the name and function of pins are shown
in Table 5.
CS
SO
WP
GND
1
2
3
8
7
6
VDD
HOLD
SCK
4
5
SI
Figure 3 Pin assignment of MB85RS64, MB85RS128A, and MB85RS256A (Top View)
Table 5 Names and functions of pins
Pin
Function
Name
CS
Chip select pin
In the “H” level, the chip enters into the standby status, unless the chip
internal is not in the write status, and SO enters into the high impedance
status (hereinafter called High-Z). At this time, inputs of other pins are
ignored. In the “L” level, the chip enters into an active status.
SO
Serial data output pin
WP
Write protect pin
Pin to control writing in the status register.
GND
Ground pin
SI
Serial data input pin
SCK
Serial clock pin
SI is taken by synchronization with the SCK rising edge. SO is output by
synchronization with the SCK falling edge.
HOLD
Hold pin
It is used to pause the serial input/output without having the chip enter into
the standby status. In the “L” level, it enters into the hold operation, SO enters
into High-Z, and SCK and SI enter into “don’t care.” During the hold operation,
this pin has to be kept in the “L” level.
VDD
Power supply voltage pin
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For MB85RS64, MB85RS128A, and MB85RS256A, several chips can be connected by
using the MCU, to which the SPI port is attached. The system structure example is
shown in Figure 4.
SCK
MFS(SPI)
SO
SI
SO
SI
SCK
SO
FRAM
(Slave)
FM3
(Master)
CS
HOLD
SI
SCK
FRAM
(Slave)
CS
HOLD
CS1
CS2
GPIO
HOLD1
HOLD2
Figure 4 System structure example
In addition, for details of the SPI control for FRAM, see the FRAM data sheet (SPI
control) [2].
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3.5.2
Samples
The FRAM used in the sample, setting, and command are shown in Table 6.
Table 6 FRAM used in sample, setting, and command
Content
Remarks
FRAM
MB85RS256A
256K bits (32K x 8 bits)
Baud rate
2Mbps
The maximum of FRAM is 25 Mbps
Hold operation
Not used
Connect to GPIO, “H” fixed
Block protect
Not used
WP pin
“H” fixed
Command
WREN
Write-accept command
Used before writing starts
WRDI
Write-prohibit command
Used after writing ends
RDSR
Status register read command
After WREN is sent, used for WEL
check
WRSR
Status register write command
Set WPEN to 1 at initialization
Set WPEN to 0 at end
READ
Memory read command
Consecutive reading of specified byte
number
WRITE
Memory write command
Consecutive writing of specified byte
For details of the command, see the FRAM data sheet (SPI control) [2].
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4
Confirmed Operation Environment
4.1
For MB85RC128 (I2C Control)
The confirmed operation environment of the sample software for the MB85RC128 (I2C
control) is shown in Table 7.
Table 7 Confirmed operation environment of the sample software for the MB85RC128 (I2C
control)
Item
Content
Microcontroller used
MB9AF132L
Operating frequency
Core: 20 MHz
Peripheral: 10 MHz
Operating voltage
+3.3V
OS
Not used
Integrated
Development
Environment
Compile optimization
IAR
IAR Embedded Workbench for ARM 6.30.4
KEIL
MDK-Lite Version 4.22a
Yes (Even if this is set to “No,” the optimization process is
executed.)
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4.2
For MB85RS256A (SPI control)
The confirmed operation environment of the sample software for the MB85RS256A (SPI
control) is shown in Table 8.
Table 8 Confirmed operation environment of the sample software for the MB85RS256A (SPI
control)
Item
Content
Microcontroller used
MB9BF506R
Operating frequency
Core: 80 MHz
Peripheral: 40 MHz
Operating voltage
+3.3V
OS
Not used
Integrated
Development
Environment
Compile optimization
IAR
IAR Embedded Workbench for ARM 6.30.4
KEIL
MDK-Lite Version 4.22a
Yes (Even if this is set to “No,” the optimization process is
executed.)
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5
Hardware
For MB85RC128 (I2C control)
5.1
5.1.1
Hardware Block
The sample hardware block for MB85RC128 is shown in Figure 5.
3.3V
WP
3.3V
VDD
A0
A1
A2
SCL
SCK5_0
SDA
SOT5_0
MFS(I2C)
VSS
FRAM
MB85RC128
GND
Microcontroller
MB9AF132L
GND
Figure 5 Sample hardware block for MB85RC128
5.1.2
Function of the Microcontroller MB9AF132L Used in the I2C Control
Control by I2C is possible by connecting the microcontroller MB9AF132L and FRAM
MB85RC128 shown in Figure 5. In the I2C control, the MFS function mounted on the
microcontroller MB9AF132L is used. The functions of the microcontroller MB9AF132L
used in the I2C control are shown in Table 9.
Table 9 Functions of microcontroller MB9AF132L used in the I2C control
Peripheral
Description
Remarks
Ch.5
No transmission/reception FIFO
Function
MFS
(In MB9AF132L, no FIFO in all channels)
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5.2
For MB85RS256A (SPI control)
5.2.1
Hardware Block
The sample hardware block for MB85RS256A is shown in Figure 6.
3.3V
VDD
3.3V
HOLD
P08
CS
P64
WP
GND
SCK
SCK3_0
SO
SIN3_0
SI
SOT3_0
FRAM
MB85RS256A
GND
GPIO
MFS(SPI)
Microcontroller
MB9BF506R
GND
Figure 6 Sample Hardware block for MB85RS256A
5.2.2
Functions of the Microcontroller MB9BF506R Used in the SPI Control
Control by SPI is possible by connecting the microcontroller MB9BF506R and FRAM
MB85RS256A shown in Figure 6. For the SPI control, the MFS function and the GPIO
control mounted in the microcontroller MB9BF506R are used. The functions of the
microcontroller MB9BF506R used for the SPI control are shown in Table 10.
Table 10 Functions of microcontroller MB9BF506R used in the SPI control
Peripheral
Description
Remarks
MFS
Ch.3
With transmission/reception 16 byte FIFO
GPIO
P64
Output for CS pin control
Set to “L” when communication is executed by SPI
P08
Output for HOLD pin control
Always set to “H” output during the FRAM driver operation.
Functions
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6
Software
6.1
For MB85RC128 (I2C Control)
6.1.1
Software Block
The software block of the section related to the FRAM control in the sample is shown in
Figure 7 (including partial hardware block).
Software(microcontroller)
Application layer
Application
FRAM driver
Driver layer
I2C driver
MFS driver
Hardware(microcontroller)
MFS(I2C)
I2C(SCK,SDA)
Interface(I2C)
Hardware
Memory
(FRAM MB85RC128)
Register
Figure 7 Software block related to the FRAM control in the sample
Software blocks are shown in Table 11.
Table 11 Software blocks
Block
Content
MFS driver
Executes the channel control and the interrupt process function for
the sections that covers entirety of each driver (I2C, CSIO (*), SPI,
and UART) of Multi-Function Serial (MFS).
2
I C driver
Driver that operates MFS as I2C
FRAM driver
Driver that controls FRAM MB85RC128 by I2C
Application
Reads and writes the data by using the FRAM driver
(*)CSIO: Clock Synchronous Serial Interface
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6.1.2
Setting
6.1.2.1
Register Setting
The register setting to use the FM3 microcontroller (MB9AF132L) MFS Ch.5 as I 2C
for controlling MB85RC128 is shown in Table 12.
Table 12 Register setting to use MFS Ch.5 as I2C
Register
Name
Bit
Settin
g
Bit Name
Timing for
Overview
setting
Value
PFR6
1
“1” SOT5_0 is used (MFS Ch.5 is used as I2C)
PFR61
When
initialized
2
2
PFR62
“1” SCK5_0 is used (MFS Ch.5 is used as I C)
When
initialized
EPFR08 13,12
SOT5B
0b01 SOT5_0 is used for MFS-Ch.5-SOT pin
When
initialized
15,14
SCK5B
0b01 SCK5_0 is used for MFS-Ch.5-SCK pin
When
initialized
(*) For details of each register setting, see the “32-BIT MICROCONTROLLER FM3
PERIPHERAL MANUAL” [3].
6.1.2.2
MFS (I2C) Setting
The setting to the I2C driver when the MFS is used as I2C is shown in Table 13.
Table 13 Setting to the I2C driver
Item
Setting
Overview
Value
Baud rate
100000
100kbps
Slave address
0x50
Device address (A0, A1, and A2) setting is “000.”
1
Master operation
Operation mode
2
(*) For the I C operation of MFS, see the “32-BIT MICROCONTROLLER FM3
PERIPHERAL MANUAL Communication Macro Part” [4].
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6.1.2.3
Interrupt Setting
The exceptions and the interrupt factor vector that are input to NVIC when the MFS
ch.3 interrupt is used are shown in Table 14.
Table 14 MFS ch.3 interrupt vector
Exception and Interrupt Source
Vector No.
IRQ No.
Vector Offset
MFS ch.3 reception
28
12
0x70
MFS ch.3 transmission/status
29
13
0x74
(*)
(*) When MFS is used as I2C, the status interrupt occurs.
For the MFS interrupt, see the “32-BIT MICROCONTROLLER FM3 PERIPHERAL
MANUAL Communication Macro Part” [4].
○Setting of the interrupt set-enable register
To accept the MFS ch.3 interrupt, set the bits corresponding to IRQ No.28 and
No.29 of the interrupt set-enable register to “1.”
Table 15 Setting of interrupt set-enable register
Address: 0xE000E100：0bXX11XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value X X 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X is a discretional value (“0” or “1”)
(*1) For NVIC, see the “Cortex-M3 r2p1 Technical Reference Manual” [6]“CHAPTER
6 Nested Vectored Interrupt Controller”.
(*2) For the interrupt contents and interrupt numbers, see the “32-BIT
MICROCONTROLLER FM3 PERIPHERAL MANUAL” [3] “CHAPTER 7-4
INTERRUPT (C)” “3. Exception and Interrupt Factor Vector”.
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6.1.3
API
Function
int32_t Fram_Init(void)
Description
Initialization of the FRAM driver
Parameter
None
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
2
Initialize the I C driver of the channel (Ch.5) connected to FRAM and
establish the condition open to communication with FRAM.
Function
int32_t Fram_UnInit(void)
Description
Ending the FRAM driver
Parameter
None
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
2
The I C driver of the channel (Ch.5) connected to FRAM is ended, and
the FRAM driver ends.
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Function
int32_t Fram_Write(
uint16_t
u16WriteAddr,
uint8_t
*pu8WriteData,
uint16_t
u16Length
)
Description
Data writing to FRAM driver
Parameter
u16WriteAddr
Head address of FRAM to be accessed
pu8WriteData
Pointer to the write data storage source
u16Length
Write data length
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
Write the write data storage source data from the FRAM head address
for the write data length.
Write process completes when this function ends.
Function
int32_t Fram_Read(
uint16_t
u16ReadAddr,
uint8_t
*pu8ReadData,
uint16_t
u16Length
)
Description
Data read from the FRAM driver
Parameter
u16ReadAddr
Head address of FRAM to be accessed
pu8ReadData
Pointer to the read data storage destination
u16Length
Read data length
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
From the FRAM head address, read the data for the read data length
and write in the read data storage destination.
Read process completes when this function ends.
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6.1.4
Operation Flow
6.1.4.1
Initialization Function of the FRAM Driver
Initialize the I2C driver, and establish the condition open to access the FRAM
(Fram_Init).
Start
Set baud rate
Set FRAM slave address
Initialize I2C
End
Figure 8 Initialization function flow of the FRAM driver
6.1.4.2
End Function of the FRAM Driver
End the FRAM driver (Fram_UnInit).
Start
End I2C
End
Figure 9 End function flow of the FRAM driver
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6.1.4.3
Data Write Function to FRAM
Write data by accessing FRAM from I2C (Fram_Write).
Start
Set the initial value of the return value to error
Parameter check
Write data storage source pointer is other than NULL,
write data length is other than 0,
and the total of the head address of FRAM and write
data length is the FRAM final address or lower?
No
Yes
The write data length is other than 0?
No
Yes
Copy the write data storage source data to
the transmission buffer for the access data
length
Set the FRAM head address to the first 2
bytes of the transmission buffer in the order
of upper byte and lower byte
Add the access data length to the FRAM head
address
Set the write data length to the access data
length
Access data length >
capacity of the data section of the
transmission buffer
Add the access data length to the pointer of
the write data storage source
No
Subtract the access data length from the
write data length
Yes
Add address data length (2 bytes) to the
access data length
Set the capacity of the data section of the
transmission buffer to the access data length
I2C transmission
Set the result of I2C transmission to the
return value
No
The return value is error ?
Yes
Writing data to the FRAM memory
To transmit in the order of the address and the write
data, prepare the buffer for I2C transmission and then
transmit.
At that time, if the write data length is larger than the
capacity of the data section of the I2C transmission
buffer, execute the transmission by dividing into parts.
End
Figure 10 Data write function flow to FRAM
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6.1.4.4
Data Read Function from FRAM
Read the data by accessing from I2C to FRAM (Fram_Read).
Start
Set the initial value of the return value to an error
Parameter check
Read data storage destination pointer is other than NULL,
read data length is other than 0,
and the total of the head address of the FRAM and read
data length is the FRAM final address or lower?
Reading data from
the FRAM memory
Yes
Set the address data length (2 bytes) to the access
data length
Set the FRAM head address to the first 2 bytes of
the transmission buffer in the order of upper byte/
lower byte
I2C transmission
Set the result of I2C transmission to the return
value
Has the return value been success?
Yes
Set the read data length to the access data length
I2C receiption
Set the result of I2C reception to the return value
End
Figure 11 Data read function flow from FRAM
30
No
No
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6.2
For MB85RS256A (SPI Control)
6.2.1
Software Block
The software block of the section related to the FRAM control in the sample is shown in
Figure 12(including partial hardware block).
Software (Microcontroller)
Application layer
Application
FRAM driver
SPI driver
Driver layer
CSIO driver
MFS driver
Hardware(microcontroller)
GPIO
MFS(SPI)
GPIO(CS,HOLD)
SPI(SCK/SI/SO)
Interface(SPI)
Hardware
(FRAM MB85RS256A)
Memory
Register
Figure 12 Software block related to the FRAM control in the sample
Software blocks are shown in Table 16.
Table 16 Software blocks
Block
Content
MFS driver
Executes the channel control and the interrupt process function for
the sections that covers entirety of each driver (I2C, CSIO (*), SPI,
and UART) of Multi-Function Serial (MFS).
CSIO driver
Driver that operates MFS as CSIO
SPI driver
Driver that operates CSIO as SPI
For the chip select, the control by GPIO is separately mounted.
FRAM driver
Driver that controls FRAM MB85RS256A by SPI
Application
Executes data read and write processes by using the FRAM driver
(*)CSIO: Clock Synchronous Serial Interface
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6.2.2
Setting
6.2.2.1
Register Setting
The register setting to use the FM3 microcontroller (MB9BF506R) MFS Ch.3 as SPI
for controlling MB85RS256A is shown in Table 17.
Table 17 Register setting used for MFS Ch.3 to be used as SPI
Register
Name
PFR6
Bit
Set
Overview
Bit Name Value
Timing for setting
6
PFR66
“1” SIN3_0 is used (MFS Ch.3 is used as SPI) When initialized
7
PFR67
“1” SOT3_0 is used (MFS Ch.3 is used as SPI) When initialized
8
PFR68
“1” SCK3_0 is used (MFS Ch.3 is used as SPI) When initialized
EPFR07 23,22
SIN3S
0b00 SIN3_0 is used for MFS-Ch.3-SIN pin.
When initialized
25,24
SOT3B
0b01 SOT3_0 is used for MFS-Ch.3-SOT pin.
When initialized
27,26
SCK3B
0b01 SCK3_0 is used for MFS-Ch.3-SCK pin.
When initialized
DDR0
8
DDR08
“1” P08 pin (HOLD pin control) is set to output. When initialized
PDOR0
8
PDOR08
“1” P08 pin (HOLD pin control) is set to “H”.
When initialized
DDR6
4
DDR64
“1” P64 pin (CS pin control) is set to output.
When initialized
PDOR6
4
PDOR64
“1” P64 pin (CS pin control) is set to “H”.
When initialized
When SPI non
communication
“0” P64 pin (CS pin control) is set to “L”.
When
SPI
communication
(*) For details of each register setting, see the “32-BIT MICROCONTROLLER FM3
PERIPHERAL MANUAL” [3].
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6.2.2.2
Setting MFS (SPI)
The setting to the SPI driver when the MFS is used as SPI is shown in Table 18.
Table 18 Setting to the SPI driver
Item
Setting
Overview
Value
Baud rate
Mark polarity of the clock
2000000
1
2 Mbps, the maximum of FRAM is 25 Mbps
Low (SPI transfer (II)) during idling
Data output by the falling edge of the clock
Data acquisition by the rising edge of the clock
Operation mode
0
Master operation
Transfer direction
1
MSB first
(*) For the SPI operation of MFS, see the “32-BIT MICROCONTROLLER FM3
PERIPHERAL MANUAL Communication Macro Part” [4].
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6.2.2.3
Interrupt Setting
The exceptions and the interrupt factor vector that are input to NVIC when the MFS
ch.5 interrupt is used are shown in Table 19.
Table 19 MFS ch.5 interrupt vector
Exception
and
Vector No.
IRQ No.
Vector Offset
MFS ch.5 reception
33
17
0x84
MFS ch.5 transmission
34
18
0x88
Interrupt Source
(*)
(*) When MFS is used as SPI (CSIO), the status interrupt does not occur.
For the MFS interrupt, see the “32-BIT MICROCONTROLLER FM3 PERIPHERAL
MANUAL Communication Macro Part” [4].
○Setting of interrupt enable set-enable
To accept the MFS ch.5 interrupt, set the bits corresponding to IRQ No.33 and
No.34 of the interrupt set-enable register to “1.”
Table 20 Setting of interrupt set-enable register
Address: 0xE000E104: 0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11X
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 X
X is a discretional value (“0” or “1”)
(*1) For NVIC, see the “Cortex-M3 r2p0 Technical Reference Manual” [5] “CHAPTER
6: Nested Vectored Interrupt Controller”.
(*2) For the interrupt contents and interrupt numbers, see the “32-BIT
MICROCONTROLLER FM3 PERIPHERAL MANUAL” [3] “CHAPTER 7-2
INTERRUPT (A)” “3. Exception and Interrupt Factor Vector”.
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6.2.3
API
Function
int32_t Fram_Init(void)
Description
Initialization of the FRAM driver
Parameter
None
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
Initialize the SPI driver of the channel (Ch. 3) connected to FRAM and
establish the condition open to communication with FRAM.
The CS control pin and the HOLD control pin are set to “H” output.
In addition, by sending the WRSR command to FRAM, write enable latch
is set. In addition, for the WRSR command, see the FRAM data sheet
(SPI control) [2].
Function
int32_t Fram_UnInit(void)
Description
Ending the FRAM driver
Parameter
None
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
The write enable latch is cleared by sending the WRSR command to
FRAM. In addition, for the WRSR command, see the FRAM data sheet
(SPI control) [2].
In addition, the CS control pin and the HOLD control pin are changed to
the input, and the SPI driver of the channel (Ch.3) connected to FRAM is
ended, and the FRAM driver ends.
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Function
int32_t Fram_Write(
uint16_t
u16WriteAddr,
uint8_t
*pu8WriteData,
uint16_t
u16Length
)
Description
Data write to FRAM driver
Parameter
u16WriteAddr
FRAM head address to be accessed
pu8WriteData
Pointer to the write data storage source
u16Length
Write data length
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
Write the write data storage source data from the FRAM head address
for the write data length.
Write process completes when this function ends.
Function
int32_t Fram_Read(
uint16_t
u16ReadAddr,
uint8_t
*pu8ReadData,
uint16_t
u16Length
)
Description
Data read from the FRAM driver
Parameter
u16ReadAddr
FRAM head address to be accessed
pu8ReadData
Pointer to the read data storage destination
u16Length
Read data length
Return
MM_FRAM_OK
Normal end
value
MM_FRAM_ERR
Error
Explanation
From the FRAM head address, read the data for the read data length
and write in the read data storage destination.
Read process completes when this function ends.
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6.2.4
Operation Flow
6.2.4.1 Initialization Function of the FRAM Driver
Initialize the SPI driver and establish the condition open to access the FRAM
(Fram_Init).
In addition, set the CS control pin and the HOLD control pin to the “H” output. Use the
WRSR command to set the write enable latch.
Start
Set the baud rate and the polarity of IDLE
SPI initialization
Set the result of SPI initialization to the return value
No
The return value is success?
Yes
Set the CS control pin to outputting and then output "H"
FRAM initialization
By setting the WPEN bit of the
status register to "1," switching of
write protect by the WREN/WRDI
command becomes possible.
Set the HOLD control pin to outputing and then output "H"
Set the WRSR command to the head of the transmission
buffer
Set the WPEN set data to the second byte of the
transmission buffer
Set the CS control pin to "L"
Set 2 bytes to the transmission data length
SPI transmission
Set the result of SPI transmission to the return value
Set the CS control pin to "H"
No
The return value is error?
Yes
End the FRAM driver
(Fram_UnInit)
End
Figure 13 Initialization function flow of the FRAM driver
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6.2.4.2 End Function of the FRAM Driver
Initialize the SPI driver and establish the condition open to access the FRAM
(Fram_Init).
Set the CS control pin and the HOLD control pin to input, and clear the write enable
latch by using the WRSR command.
Start
FRAM end
By setting the WPEN bit of the
status register to "0," FRAM enters
into the protect status because the
WEL bit is "0" at this point.
Set the WRSR command to the head of the
transmission buffer
Set the WPEN clear data to the second byte of
the transmission buffer
Set the CS control pin to "L"
Set 2 bytes to the transmission data length
SPI transmission
Set the result of SPI transmission to the return
value
Set the CS control pin to "H"
No
The return value is success?
Yes
SPI end
Set the result of SPI end to the return value
No
The return value is success?
Yes
Set the CS control pin and the HOLD control pin
to input
End
Figure 14 End function flow of the FRAM driver
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6.2.4.3
Data Write Function for FRAM
Write data by accessing FRAM from SPI (Fram_Write).
Start
Set the initial value of the return value to error
Paramete check
Write data storage source pointer is other than NULL,
write data length is other than 0,
and the total of the head address of FRAM and write
data length is the FRAM final address or lower?
Releasing write-protect
By sending WREN
command, release the
write-protect
No
Waiting for the status to become writable
Wait for a specified period until the WEL
bit of the status register becomes "1"
(writable).
Yes
Counter lower than the WEL set
wait count?
Set the WREN command to the head of the
transmission buffer
Yes
Set the CS control pin to "L"
Set the RDSR command to the head of the
transmission buffer
Set 1 byte to the transmission data length
Set the CS control pin to "L"
SPI transmission
Set 1 byte to the transmission data length
Set the result of SPI transmission to the
return value
SPI transmission
Set 1 byte to the receiption data length
No
The return value is success?
SPI receiption
Yes
2
Set the return value to error
Set the CS control pin to "H"
Initialize the counter to 0
No
WEL bit of the
reception data is "1"?
Yes
Set the return value to success
1
Figure 15 Data write function flow to FRAM (1)
39
No
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1
Has the return value been success?
No
Yes
Set the WRITE command to the head of the
transmission buffer
Setting write-protect
By sending the WRDI command,
writing to FRAM is protected.
Set the FRAM head address to the 2nd and 3rd
byte of the transmission buffer in the order of
upper byte/lower byte
Set the WRDI command to the head of the
transmission buffer
Set the CS control pin to "L"
Set the CS control pin to "L"
Set the 3 bytes to the transmission data length
Set 1 byte to the transmission buffer length
SPI transmission
SPI transmission
Set the result of SPI transmission to the return
value
Has the return value been success?
No
Set the result of the SPI transmission to the
return value of the WRDI command transmission
(*2)
Yes
Set the CS control pin to "H"
Set the write data length to the transmission
data length
The return value
before this (*1) is success?
SPI transmission（write data）
Set the result of SPI transmission to the return
value (*1)
No
Yes
Set the return value of the WRDI command
transmission (*2) to the return value
Set the CS control pin to "H"
2
End
Writing data to the
FRAM memory
Figure 16 Data write function flow to FRAM (2)
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6.2.4.4
Data Read Function from FRAM
Read the data by accessing from SPI to FRAM (Fram_Read).
Start
Set the initial value of the return value to an error
Parameter check
Read data storage destination pointer is other than NULL,
read data length is other than 0,
and the total of the head address of the FRAM and read
data length is the FRAM final address or lower?
Reading data read
from the FRAM
memory
Yes
Set the READ command to the head of the
transmission buffer
Set the FRAM head address to the 2nd and 3rd byte of
the transmission buffer in the order of upper byte and
lower byte
Set the CS control pin to "L"
Set the 3 bytes to the transmission data length
SPI transmission
Set the result of SPI transmission to the return value
The return value is success?
No
Yes
Set the read data length to the receiption data length
SPI receiption
Set the result of SPI receiption to the return value
Set the CS control pin to "H"
End
Figure 17 Data read function flow from FRAM
41
No