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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300016-E-V10
FR FAMILY
32-BIT MICROCONTROLLER
MB88121, MB91460
INTERFACING MB91460 TO
MB88121
APPLICATION NOTE
Interfacing MB91460 TO MB88121
Revision History
Revision History
Date
2008-03-28
Issue
V1.0, MSt
First draft
This document contains 56 pages.
MCU-AN-300016-E-V10
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (eg. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer´s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
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4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
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the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300016-E-V10
Interfacing MB91460 TO MB88121
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 6
2 HARDWARE .................................................................................................................... 7
2.1
Power supply........................................................................................................... 7
2.2
Reset....................................................................................................................... 8
2.3
Clock connection ..................................................................................................... 8
2.4
2.5
2.6
2.3.1
MCU Clock ................................................................................................ 8
2.3.2
CC Clock ................................................................................................... 8
Operation Mode of MCU and CC............................................................................. 8
2.4.1
MCU operation mode................................................................................. 8
2.4.2
CC operation mode.................................................................................. 10
2.4.2.1
None multiplexed bus interface mode ...................................... 10
2.4.2.2
Multiplexed bus interface mode ............................................... 10
Bus interface connection ....................................................................................... 10
2.5.1
16-bit none multiplexed mode .................................................................. 11
2.5.2
16-bit multiplexed bus interface mode...................................................... 12
Interrupts............................................................................................................... 13
2.6.1
CC interrupt ............................................................................................. 13
2.7
DMA pins............................................................................................................... 13
2.8
Stop Watch pin...................................................................................................... 13
2.9
Debug pins ............................................................................................................ 14
3 SOFTWARE................................................................................................................... 15
3.1
Bus interface setup................................................................................................ 15
3.1.1
Simplified timing diagram of the MB88121B (none multiplexed access)... 15
3.1.2
Simplified timing diagram of MB88121B (multiplexed access) ................. 17
3.1.3
Configuration registers of the external bus interface ................................ 19
3.1.3.1
Area Select Register (ASR) .................................................... 19
3.1.3.2
Area Configuration Register (ACR) .......................................... 20
3.1.3.3
Area Wait Register (AWR) ....................................................... 22
3.1.3.4
Timing example of ordinary (non-multiplexed) bus ................... 24
3.1.3.5
Timing example of multiplexed bus .......................................... 25
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Contents
3.1.4
3.1.3.6
Settings of register ASR, AWR, ACR, CSER in file
start91460.asm ........................................................................ 26
3.1.3.7
Register CHER, IOWR, TCR, MCRA, MCRB and RCR ........... 27
Setup of Port function register (PFR) ....................................................... 28
3.1.4.1
3.1.5
External bus clock.................................................................................... 34
3.1.5.1
3.1.6
3.2
3.3
3.4
Port function register settings in start91460.asm...................... 30
Example setting in start91460.asm .......................................... 34
Initialisation sequence of MB88121 ......................................................... 35
Interrupts............................................................................................................... 36
3.2.1
MB88121 interrupt ................................................................................... 36
3.2.2
MCU external interrupt............................................................................. 37
3.2.2.1
External interrupt configuration registers.................................. 37
3.2.2.2
Port function Register (PFR) .................................................... 38
3.2.2.3
Interrupt vector table ................................................................ 40
DMA usage ........................................................................................................... 42
3.3.1
DMA register at MB88121........................................................................ 42
3.3.2
DMA at MB91460 .................................................................................... 42
3.3.3
DMA flow for Output buffer transfer ......................................................... 43
3.3.4
DMA flow for input buffer transfer ............................................................ 44
Debugging support ................................................................................................ 45
4 REFERENCE ................................................................................................................. 46
5 APPENDIX ..................................................................................................................... 47
5.1
Connection example using none-multiplexed Bus interface................................... 47
5.2
Connection example using multiplexed bus interface ............................................ 51
5.3
Tables ................................................................................................................... 55
5.4
Figures .................................................................................................................. 55
© Fujitsu Microelectronics Europe GmbH
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Interfacing MB91460 TO MB88121
Chapter 1 Introduction
1 Introduction
FUJITSU Microelectronics Europe GmbH offers a stand alone FlexRay Communication
Controller, MB88121 series, which supports parallel and serial connectivity to Host MCU.
The MB88121 series supports two parallel Bus interface modes, 16-bit none-multiplexed and
16-bit multiplexed mode, for the 32-bit MB91460 series. The following discusses Hardware
and Software requirement based on MB91F467D series.
Note:
Not all MB91460 devices support an external bus interface.
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Interfacing MB91460 TO MB88121
Chapter 2 Hardware
2 Hardware
This chapter discusses the Hardware related issues
Connection examples for 16-bit none-multiplexed and 16-bit multiplexed bus interface based
on MB91F467D and MB88121B are shown in chapter Appendix.
2.1
Power supply
MB91460 series has the ability to supply the GPIO (VDD5) and the external bus interface
(VDD35=3.3V) with different voltage level simultaneously. This is useful when using 3.3V
memory devices and 5V based components at Port functions.
Pin Nr
Name
Description
Range
26,52,208
VDD35
External bus voltage supply
3V—5.5V
78,104,130,156
VDD5
MCU voltage supply
3V—5.5V
Table 2-1 MB91F467D power supply pins
The MB88121 series is using single voltage supply. All pins having the same voltage level
which are supplied at Vcc pins. In case of using the interrupt functionality the interrupt pins of
MB88121 and the input pins (e.g. external interrupt) have same voltage level, if not level
conversion via level shifter is required. The same applies to the Reset pin when using one
reset connection for MCU and CC.
CC pin
MCU pin
MCU pin
VCC
VDD35
VDD5
3.3V
3.3V
5V
3.3V
3.3V
3.3V
5V
5V
5V
Changes if the interrupt function is used
Use additional level shifter for the interrupt line / Reset
(3.3V CC => 5V MCU)
\
Table 2-2 Relationship of the power supply
Note:
Be aware of the required voltage levels of all pins. Level conversion for interrupt /
reset pins might be required.
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Chapter 2 Hardware
2.2
Reset
The MCU (MB91F467D) and FlexRay CC (MB88121) support the Reset functionality via
external pin. Depending on Application both reset pin might be connected to an external
voltage supervisor chip, which controls the reset line or the MCU controls the reset pin of the
MB88121 via IO port. The example in this Application Note is using first mentioned
approach.
As MB88121 series is a single voltage supply series, care have to be taken in case the
MB91F467D series is using different voltage supply level at bus interface pins (Vdd35) and
other IO pins (Vdd). In this case ensure e.g. via level converter correct High level for
MB88121 series reset input pin.
2.3
Clock connection
Both devices require an external clock to generate the internal clock.
2.3.1 MCU Clock
For MB91460 series a 4 MHz external clock needs to be connected to X0 / X1 pins.
Via the internal PLL a clock of up to 10MHz is generated.
2.3.2 CC Clock
The MB88121 is requiring an internal clock of 80 MHz. This frequency is generated using a
PLL, supporting external clocks at pin X0 and X1.
4MHz, 5MHz, 8MHz or 10MHz crystal are supported.
2.4
Operation Mode of MCU and CC
Both devices need to be set to correct mode via mode pins.
2.4.1 MCU operation mode
The MD[2:0] pins of the MCU defines whether the reset vector is fetched from internal or
external area. In case the internal Flash memory shall be used the mode pins have to be set
to internal mode vector setting. During start-up phase of the MCU the bus interface settings
is configured via the bus interface registers.
The mode pins of MB91F467D should connect to GND directly so that the MCU operates in
the internal ROM external bus mode. The configuration of this mode is listed below.
Configuration
Mode pin
Description
Internal mode vector and reset vector
MD[2:0]=0
Table 2-3 Configuration of internal ROM external bus mode
The memory map of this operation mode is illustrated in the next page. The gray memory
area is not available. By default settings in file Start91460.asm chip select areas are set as
non-cacheable areas (register ICHCR). For the Flash memory 8KB pre-fetch buffer is
enabled (register FCHCR). For details about Flash memory and its instruction cache, please
refer to the chapter 11 ‘Memory Controller’ of MB91460 hardware Manual. Instruction cache
of external bus interface is declared in the chapter 12 ‘Instruction cache’.
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 2 Hardware
Figure 2-1 Memory map of internal ROM external bus mode
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Chapter 2 Hardware
2.4.2 CC operation mode
The mode pins MD[2:0] and MDE[2:0] select between different bus types. These pins can
directly connected to GND or Vcc.
2.4.2.1 None multiplexed bus interface mode
MD2 MD1
1
0
MD0
Mode
16bit parallel
communication
0
MDE2
MDE1
MDE0
0
0
0
0
0
1
1
0
0
1
1
0
Mode extension
Multiplexed
bus
FR460
Nonmultiplexed
bus
FR460
16FX
FR360
Table 2-4 Mode selection input of the communication controller
2.4.2.2 Multiplexed bus interface mode
MD2 MD1
1
0
MD0
0
Mode
16bit parallel
communication
MDE2
MDE1
MDE0
0
0
0
0
0
1
1
0
0
1
1
0
Mode extension
Multiplexed
bus
FR460
Nonmultiplexed
bus
FR460
16FX
FR360
Table 2-5 Mode selection input of the communication controller
2.5
Bus interface connection
Two modes are possible:
•
16-bit none multiplexed mode
•
16-bit multiplexed mode
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Interfacing MB91460 TO MB88121
Chapter 2 Hardware
2.5.1 16-bit none multiplexed mode
External bus interface: MB88121 pins in connection with MCU MB91F467D pins
CC pin Nr
Name
35
Function
MCU pin Nr
Name
A10
30
P06_2/A10
36
A9
29
P06_1/A9
37
A8
28
P06_0/A8
38
A7
25
P07_7/A7
39
A6
24
P07_6/A6
40
A5
23
P07_5/A5
41
A4
22
P07_4/A4
42
A3
21
P07_3/A3
43
A2
20
P07_2/A2
44
A1
19
P07_1/A1
45
A0
18
P07_0/A0
46
D15
17
P00_7/D31
47
D14
16
P00_6/D30
50
D13
15
P00_5/D29
51
D12
14
P00_4/D28
52
D11
13
P00_3/D27
53
D10
12
P00_2/D26
54
D9
11
P00_1/D25
55
D8
10
P00_0/D24
56
D7
9
P01_7/D23
57
D6
8
P01_6/D22
58
D5
7
P01_5/D21
59
D4
6
P01_4/D20
60
D3
5
P01_3/D19
61
D2
4
P01_2/D18
62
D1
3
P01_1/D17
63
D0
2
P01_0/D16
15
BCLK
Bus clock
65
P10_4/MCLKO
19
CS
Chip select
59
P09_3/CSX3
20
RD
Read enable
50
P08_4/RDX
21
WR
Write enable
64
P10_3/WEX
27
RDY
Ready signal
55
P08_7/RDY
Address bus
MCU=>CC
Data bus
MCU
CC
MCU=>CC
CC=>MCU
3
Table 2-6: 16-bit none multiplex bus interface pin assignment
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 Hardware
2.5.2 16-bit multiplexed bus interface mode
External bus interface: CC pins in connection with MCU pins
CC pin Nr
Name
53
Function
MCU pin Nr
Name
AD10
12
P00_2/D26
54
AD9
11
P00_1/D25
55
AD8
10
P00_0/D24
56
AD7
9
P01_7/D23
57
AD6
8
P01_6/D22
58
AD5
7
P01_5/D21
59
AD4
6
P01_4/D20
60
AD3
5
P01_3/D19
61
AD2
4
P01_2/D18
62
AD1
3
P01_1/D17
63
AD0
2
P01_0/D16
46
D15
17
P00_7/D31
47
D14
16
P00_6/D30
50
D13
15
P00_5/D29
51
D12
14
P00_4/D28
52
D11
13
P00_3/D27
15
BCLK
Bus clock
65
P10_4/MCLKO
19
CS
Chip select
59
P09_3/CSX3
20
RD
Read enable
50
P08_4/RDX
21
WR
Write enable
64
P10_3/WEX
22
AS
Address strobe
62
P10_1/ASX
27
RDY
Ready signal
55
P08_7/RDY
Address/data bus
MCU
CC
Data bus
MCU
CC
MCU=>CC
CC=>MCU
3
Table 2-7: 16-bit multiplexed bus interface pin assignment
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 2 Hardware
2.6
Interrupts
The MB88121 FlexRay CC is supporting also interrupt events. These events are available at
pins and can be connected to MCU external interrupt pins.
2.6.1 CC interrupt
Depending on used bus interface mode a different number of interrupt pins are available at
CC side.
CC pin
Interrupt type
INT0
E-Ray interrupt line0 (eray_int0)
INT1
E-Ray interrupt line1 (eray_int1)
INT2
E-Ray timer0 interrupt
INT3
E-Ray timer1 interrupt
INT4
Low voltage detection interrupt
Table 2-8 CC interrupt output by 16bit multiplexed mode
CC pin
Interrupt type
INT0
E-Ray interrupt line0 (eray_int0)
INT1
E-Ray interrupt line1 (eray_int1)
E-Ray timer0 interrupt
INT2
E-Ray timer1 interrupt
Low voltage detection interrupt
Table 2-9 CC interrupt output by 16bit non-multiplexed mode
2.7
DMA pins
The MB88121 is supporting DMA transfer from Host MCU. For this reason the DMA_Req pin
is available. This pin needs to be connected to a DMA request pin at MCU side. For
MB91F467D it is DREQ0 pin.
2.8
Stop Watch pin
The MB88121 supports the Stop Watch function. The function is similar to Input Capture
Unit, the time base is FlexRay global time. In case a external Signal, connected to Stop
Watch pin, is changing its Level the Macrotick value of FlexRay channel A and B is stored in
register and can be read out by host MCU.
This pin is an input pin. If the function is not used, a pull-up or pull-down resistor must be
connected to this pin.
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 Hardware
2.9
Debug pins
The MB88121 including debug pins, which help debugging during development phase.
CC debug pins
CC pin Nr
Name
Function
I/O type
7
SDS
Start of dynamic segment
OUT
8
CYCS0
Cycle 0 start
OUT
14
CYCS
Cycle start
OUT
23
MT
Macrotick start
OUT
38
MBSU_TX1
39
MBSU_RX1
44
MBSU_TX2
Message buffer status update port
OUT
45
MBSU_RX2
Configuration register
Debug support register
DBGS
Table 2-10: Debug pins on MB88121
The gray shaded pins are only available in 16-bit multiplexed mode.
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
3 Software
This chapter discusses the Software related issues
3.1
Bus interface setup
To access the MB88121 register in application these registers needs to be visible in the
MCU address range. For that reason the bus interface needs to be setup. All these settings
are available in start91460.asm file for MB91460 series MCU.
Following needs to be done:
•
Initialise Bus interface for required signal timing
•
Ensure Port function is set to Bus interface
•
Setup of Bus interface Clock (CLKT)
3.1.1 Simplified timing diagram of the MB88121B (none multiplexed access)
When using 16-bit none multiplexed mode The MB88121B requires following timing. This
timing need to be setup in the Bus interface register at MCU side.
Figure 3-1 MB88121 read operation (non-multiplexed)
© Fujitsu Microelectronics Europe GmbH
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Chapter 3 Software
Operation sequence:
1. The RD pin (signal RD ) becomes low level, the output data on pins D[15:0] is invalid.
2. After that the RDY pin becomes low level at the next rising edge of the clock signal
BCLK (pin BCLK), which causes the MCU to wait.
3. After several wait cycles the RDY pin becomes high level at the rising edge of the
BCLK pin and the valid data is output from the pins D[15:0].
4. When the RD pin becomes high level again, the read access is finished. Pins D[15:0]
become Hi-Z.
Figure 3-2 MB88121 Write operation (non-multiplexed)
Operation sequence:
1. The WR pin (signal WR ) becomes low level. At the next rising edge of the BCLK pin
the data on the pins D[15:0] is written to a temporary register and the RDY pin
becomes low level, which causes the MCU to wait.
2. The data in the temporary register is written to the addressed register. The RDY pin
becomes high level again.
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
3.1.2 Simplified timing diagram of MB88121B (multiplexed access)
Following timing needs to be setup in MB91460 series when using 16-bit multiplexed
access.
Figure 3-3 MB88121 read operation (multiplexed mode)
Operation sequence:
1. The address is latched by the rising edge of AS pin (signal AS ).
2. The RD pin (signal RD ) becomes low level, the output data on pins D[15:11] and
AD[10:0] is invalid.
3. After that the RDY pin becomes low level at the next rising edge of the clock signal
BCLK (pin BCLK), which causes the MCU to wait.
4. After several wait cycles the RDY pin becomes high level at the rising edge of the
BCLK pin and the valid data is output from the pins D[15:11] and AD[10:0].
5. When the RD pin becomes high level again, the read access is finished. Pins
D[15:11] and AD[10:0] become Hi-Z.
Note:
Details about RDY wait cycle and byte ordering are located in the
MB88121 data sheet.
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Chapter 3 Software
Figure 3-4 MB88121 write operation (multiplexed)
Operation sequence:
1. The address is latched by the rising edge of AS pin (signal AS ).
2. The WR pin (signal WR ) becomes low level. At the next rising edge of the BCLK pin
the data on the pins D[15:11] and AD[10:0] is written to a temporary register and the
RDY pin becomes low level, which causes the MCU to wait.
3. The data in the temporary register is written to the addressed register. The RDY pin
becomes high level again.
Note:
Details about RDY wait cycle and byte ordering are located in the
MB88121 data sheet.
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
3.1.3 Configuration registers of the external bus interface
The following table list the external bus interface register available in MB91F467D series.
Address
+0
+1
+2
+3
Area select register
Area configuration register
0x000640
ASR0
ACR0
0x000644
ASR1
ACR1
0x000648
ASR2
ACR2
0x00064C
ASR3
ACR3
0x000650
\
\
0x000654
\
\
0x000658
ASR6
ACR6
0x00065C
ASR7
ACR7
Area wait register
0x000660
AWR0
AWR1
0x000664
AWR2
AWR3
0x000668
\
\
0x00066C
AWR6
AWR7
Memory configuration register
0x000670
MCRA
MCRB
\
\
I/O wait register for DMA controller by fly-by transfer mode
0x000678
IOWR0
IOWR1
IOWR2
\
0x000680
Chip select enable
register CSER
Cache enable
register CHER
\
Timing control
register TCR
\
\
0x000684
Refresh control register RCR
Grey: not used for MB88121B
Table 3-1 External bus interface registers
3.1.3.1 Area Select Register (ASR)
Register ASR specifies the start address A[31:16] of each chip select area. For example if
start address is 0x00500000, value 0x0050 is assigned to register ASR. The size of each
area can be set in multiples of 64 KB.
In this example CS3 area is configured with start address 0x00500000.
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3.1.3.2 Area Configuration Register (ACR)
Function of register ACR is listed below. The register defines e.g. Data bus width, bus signal
usage, etc. A full description can be found in MB91460 series Hardware Manual.
The Grey entries are used in the example software.
Register ACRn
Function
Bit
Name
15:12
ASZ[3:0]
11:10
DBW[1:0]
Data bus width: 8/16/32 bit
9:8
BST[1:0]
Maximum burst size : 1/2/4/8
7
SREN
6
PFEN
5
WREN
4
LEND
3:0
TYP[3:0]
Size of the chip select area: 2
N
x 64KB with N
[0,15]
0
Sharing of chip select area disabled
1
Sharing of chip select area enabled
0
Disable pre-fetch
1
Enable pre-fetch
0
Write operation of the chip select area disabled
1
Write operation of the chip select area enabled
0
Big-endian byte ordering (CS0 supports only big-endian)
1
little-endian byte ordering
Access type of the chip select area
Grey: used for MB88121B
Table 3-2 Register ACR content
ASZ[3]
ASZ[2]
ASZ[1]
ASZ[0]
Area size
Valid bit of register ASR
0
0
0
0
64KB
ASR_A[31:16]
0
0
0
1
128KB
ASR_A[31:17]
0
0
1
0
256KB
ASR_A[31:18]
0
0
1
1
512KB
ASR_A[31:19]
0
1
0
0
1MB
ASR_A[31:20]
0
1
0
1
2MB
ASR_A[31:21]
0
1
1
0
4MB
ASR_A[31:22]
0
1
1
1
8MB
ASR_A[31:23]
1
0
0
0
16MB
ASR_A[31:24]
1
0
0
1
32MB
ASR_A[31:25]
1
0
1
0
64MB
ASR_A[31:26]
1
0
1
1
128MB
ASR_A[31:27]
1
1
0
0
256MB
ASR_A[31:28]
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ASZ[3]
ASZ[2]
ASZ[1]
ASZ[0]
Area size
Valid bit of register ASR
1
1
0
1
512MB
ASR_A[31:29]
1
1
1
0
1024MB
ASR_A[31:30]
1
1
1
1
2048MB
ASR_A[31]
Grey: used for MB88121B
Table 3-3 ASZ bits of register ACR
TYP[3]
TYP[2]
TYP[1]
TYP[0]
Access type
0
0
X
X
Normal access
0
1
X
X
Address/data multiplexed access
0
X
X
0
Disable WAIT insertion by the RDY pin
0
X
X
1
Enable WAIT insertion by the RDY pin
Use pins WRX[3:0]
0
X
0
X
( WR 0 , WR1 , WR 2 , WR3 )
as write strobe
0
X
1
X
Use pin WEX ( WE ) as write strobe
Grey: used for MB88121B
Table 3-4 TYP bits of register ACR for 16-bit none multiplexed mode
TYP[3]
TYP[2]
TYP[1]
TYP[0]
Access type
0
0
X
X
Normal access
0
1
X
X
Address/data multiplexed access
0
X
X
0
Disable WAIT insertion by the RDY pin
0
X
X
1
Enable WAIT insertion by the RDY pin
Use pins WRX[3:0]
0
X
0
X
( WR 0 , WR1 , WR 2 , WR3 )
as write strobe
0
X
1
X
Use pin WEX ( WE ) as write strobe
Table 3-5 TYP bits of register ACR for 16-bit multiplexed mode
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DBW1
DBW0
Data bus width
0
0
8bit
0
1
16bit
1
0
32bit
1
1
\
BST1
BST0
Maximum burst length
Single access (not burst access)
0
0
1
One access sequence starts with an assertion of
AS and
CS and ends with negation of CS .
0
1
2
1
0
4
1
1
8
Burst access
(transfer successive data items in one access sequence)
RDY input is ignored in burst access.
Grey: used for MB88121B
Table 3-6 DBW and BST bits of register ACR
3.1.3.3 Area Wait Register (AWR)
Function of register AWR is listed below. The register is used to configure the bus interface
timing to the demands using wait state insertion.
Grey entries are used in the example.
ACR_TYP[3:0]=00XX
Normal access (asynchronous SRAM, I/O, and single/page/burst-ROM/FLASH)
Precondition
ACR_TYP[3:0]=01XX
Address/data multiplexed access (8/16-bit bus width only)
AWR Bit
W[15:12]
W[11:8]
W[7:6]
W[5:4]
W03
Function
1-15
3 auto-wait cycles are inserted into every first access cycle
0
No auto-wait cycle inserted
1-15
3 auto-wait cycles are inserted into the in-page access cycle during burst
access (not used for MB88121B)
0
No auto-wait cycle inserted
1/2/3
3 idle cycles are inserted to prevent data collision on the data bus if a write
cycle follows a read cycle
0
No idle cycle inserted
1/2/3
3 write recovery cycles are inserted after write access.
During this time all chip select signals are negated and the data pins maintain
high impedance
0
No write recovery cycle inserted
0
pin WRX[3:0] and pin WEX are used as synchronous write enable output
1
pin WRX[3:0] and pin WEX are used as asynchronous write strobe output
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ACR_TYP[3:0]=00XX
Normal access (asynchronous SRAM, I/O, and single/page/burst-ROM/FLASH)
Precondition
ACR_TYP[3:0]=01XX
Address/data multiplexed access (8/16-bit bus width only)
AWR Bit
Function
0
W02
1
0
CS is asserted at the same time when AS is asserted
CS is asserted at the rising edge of the clock signal MCLK
Read/write strobe is asserted at the rising edge of the clock signal MCLK as
soon as
W01
1
0
W00
1
CS is asserted
Read/write strobe is asserted one cycle later after
CS is asserted
CS is negated after read/write strobe is negated
One cycle is inserted before
CS is negated after read/write strobe is negated
Grey: used for MB88121B
Table 3-7 Register AWR content
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3.1.3.4 Timing example of ordinary (non-multiplexed) bus
Using the settings above the timing should look like following figure:
An example under the condition ACR_TYP[3:0]=3 and AWR=0x2008 is shown below.
Figure 3-5 Timing example of the non-multiplexed mode
Note:
•
The basic access cycle includes two clock cycles
•
AS is asserted for one cycle in the bus access start cycle. The usage of pin ASX is
not necessary for MB88121B in the non-multiplexed mode.
•
AWR_W02=0, CS is asserted at the same time when AS is asserted.
•
RD and WR are asserted at the second cycle of the bus access. If AWR_W01=1,
assertion of RD and WR will be one cycle delayed after CS is asserted. Negation
occurs after the wait cycle is finished (register AWR bit W15-W12).
•
AWR_W00=0, CS is negated direct after the bus cycle ends ( RD / WR are negated).
•
For read access, data is read at the rising edge of the clock signal MCLK only when
the wait cycle is finished.
•
For write access, data output starts when WR is asserted.
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3.1.3.5 Timing example of multiplexed bus
An example with configuration ACR_TYP[3:0]=7 and AWR=0x0008 is shown below.
Figure 3-6 Timing example of the multiplexed bus mode
Note:
•
The basic access cycle includes 2 address output cycles and 1 data cycle.
•
In the address output cycles pin ASX (address strobe) is asserted.
•
Set one as the burst length (register ACR_BST[1:0]=0).
•
Like the ordinary bus register AWR[15:12], AWR[7:4], AWR[2:0] can be set.
•
Pin RDY (ACR_TYP0=1) is enabled for external wait insertion
•
Use pin WEX as the write strobe (ACR_TYP1=1)
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3.1.3.6 Settings of register ASR, AWR, ACR, CSER in file start91460.asm
Using the Fujitsu template projects, the bus interface settings are defined in the
start91460.asm file. Following shows the according settings in the file.
;===============================
; 4.9 External Bus Interface
;===============================
#set EXTBUS ON ;The external bus-interface is enabled
;=============================
; 4.9.1 Select Chip select
;=============================
#set CS3 ON ;Select CS3
#set ENACSX B'00001000 ;Enable CS3
;==============================================
; 4.9.2 Set memory addressing for Chip selects
;==============================================
#set AREASEL3 0x0050 ;Set start address for CS3
;=================================
; 4.9.3 Configure Chip select Area
;=================================
#set CONFIGCS3 B'0000010000100011 ;Configure CS3, ACR3
;========================================
; 4.9.4 Set Wait cycles for Chip selects
;========================================
#set WAITREG3 B'0011001111111000 ;CS3 Wait state, AWR3
;====================
; 6.6.6 Set CS3
;====================
#if CS3
LDI
#0x064C, R1
; area select register ASR3, ACR3
LDI
#(AREASEL3<<16)+CONFIGCS3, R0
; load settings
ST
R0, @R1
; set registers
LDI
#0x666, R1
; area wait register AWR3
LDI
#WAITREG3, R2
; wait settings
STH
R2, @R1
; set register
#endif
;=========================
; 6.6.16 Enable used CS
;=========================
LDI #0x0680, R3 ; Chip select enable register CSER
LDI #ENACSX, R2
ORB R2, @R3
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3.1.3.7 Register CHER, IOWR, TCR, MCRA, MCRB and RCR
Register CHER decides whether the data, read from the chip select area, is saved in the
built-in cache or not. For the communication controller the cache function is disabled through
register ICHCR. MCU accesses the communication controller directly without cache
intervention.
;===================================================
; 4.8 Enable/Disable I-CACHE
;===================================================
#set
C1024
1
; CACHE Size: 1024 BYTE
#set
C2048
2
; CACHE Size: 2048 BYTE
#set
C4096
3
; CACHE Size: 4096 BYTE
#set
CACHE
OFF
; I-CACHE is disabled
#set
CACHE_SIZE
C4096
; select size of CACHE
; This is a general CACHE-Enable. By the configuration of the external bus
; it is selected, which chip select area should be cached
;====================================
; 4.9.8 Enable CACHE for chip select
;====================================
; select which chip select area is used with Cache functionality
#set CHEENA B'11111111 ;enable cache for each CS
;
||||||||__ CHE0 bit, CS0 area
;
|||||||___ CHE1 bit, CS1 area
;
||||||____ CHE2 bit, CS2 area
;
|||||_____ CHE3 bit, CS3 area
;
||||______ CHE4 bit, CS4 area
;
|||_______ CHE5 bit, CS5 area
;
||________ CHE6 bit, CS6 area
;
|_________ CHE7 bit, CS7 area
;=======================================
; 6.6.14 Enable CACHE for selected CS
;=======================================
LDI
#0x0681, R3 ; cache enable register CHER
LDI
#CHEENA, R2
ORB
R2, @R3
;=========================================
; 6.7 I-cache ON/OFF
;=========================================
LDI #0x03E7, R1
; Cache control register ICHCR
LDI #0x06, R2
; disable cache
STB R2, @R1
;
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Note:
Not all MB91460 devices support Cache on external bus interface.
3.1.4 Setup of Port function register (PFR)
The Port function register defines which resource of the MCU is connected to the pin.
All the used pins of the external bus interface are listed below.
None-multiplexed mode:
•
Address line: A10 to A0
•
Data lines: D31 to D16
•
Control lines: RDY, MCLKO, CS 3 , RD , WE
Multiplexed mode:
•
Address/Data line: D31 to D16
•
Control lines: RDY, MCLKO, CS 3 , RD , WE , AS
MB91F467D provides maximal 26bit address-line and 32bit data-line for the external bus
interface. During the power-on or INITX reset MCU pins are going to Hi-Z (high impedance)
and the inputs are disabled to prevent the leakage by any floating pin. After release of reset
the IO-ports will be set to their initial function. The external bus function is active until any
user program overwrites the related port function register PFR.
I/O Port
P00 to P03
P04 to P07
P08 to P10
Other ports
Initial function
External bus (Data bus D0 to D31)
External bus (Address bus A0 to A31)
External bus (Control bus)
General purpose I/O
Table 3-8 Initial I/O port function
Memory address
0x000D80
0x000D84
0x000D88
+0
+1
+2
+3
PFR00
PFR01
PFR02
PFR03
11111111
11111111
11111111
11111111
PFR04
PFR05
PFR06
PFR07
------11
11111111
11111111
11111111
PFR08
PFR09
PFR10
\
11111111
11- -1111
-111111-
…
0x000DC8
\
\
EPFR10
- -00- - - -
\
Table 3-9 Port function registers (PFR/EPFR) and their initial values in memory
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Since the communication controller MB88121B has 11bit address-line and 16bit data-line,
the bus width is fixed.
•
16bit data bus, MCU pin D15 to D0 are not used (Big endian Byte ordering).
•
E-Ray registers are 16bit addressed from 0x0000 to 0x07FC. Each register is 32bit
long and begins at even address. Since the data bus is restricted to 16bit, the high
order 16bit data and low order 16bit data are distinguished by address bit A[1]. The
first five bits and the last bit of a 16bit address are always zero. The 11bit address
bus is shown below.
MCU port 0 and port 1 are assigned to data bus. MCU port 6 and port 7 are assigned to
address bus.
0
0
0
0
Always zero
0
X
X
X
X
X
X
Address A[10:2]
X
X
X
X
0
A[1] A[0]
Table 3-10 11bit address line
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3.1.4.1 Port function register settings in start91460.asm
Following find the settings required in the start91460.asm file to enable the corresponding
function at the pin.
;===============================================
; 4.9.9 Select External bus mode (Data lines)
;===============================================
#set PFUNC0 B'11111111 ;select data lines
;
||||||||__ D24 / P00_0
;
|||||||___ D25 / P00_1
;
||||||____ D26 / P00_2
;
|||||_____ D27 / P00_3
;
||||______ D28 / P00_4
;
|||_______ D29 / P00_5
;
||________ D30 / P00_6
;
|_________ D31 / P00_7
#set PFUNC1 B'11111111 ;select data lines
;
||||||||__ D16 / P01_0
;
|||||||___ D17 / P01_1
;
||||||____ D18 / P01_2
;
|||||_____ D19 / P01_3
;
||||______ D20 / P01_4
;
|||_______ D21 / P01_5
;
||________ D22 / P01_6
;
|_________ D23 / P01_7
;============================================================
; 6.6.12.1 set PFR00 Register. External bus mode (D[24-31])
;============================================================
LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)
LDI #PFUNC0, R0 ; load port settings
STB R0, @R1
; set register
;==========================================================
; 6.6.12.2 set PFR01 Register. External bus mode (D[16-23])
;==========================================================
LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)
LDI #PFUNC1, R0 ; load port settings
STB R0, @R1
; set register
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;===================================================
; 4.9.11 Select External bus mode (Control lines)
;===================================================
#set PFUNC8 B'10010000 ;select control signals
;
||||||||__ WRX0 / P08_0
;
|||||||___ WRX1 / P08_1
;
||||||____ WRX2 / P08_2
;
|||||_____ WRX3 / P08_3
;
||||______ RDX / P08_4
;
|||_______ BGRNTX / P08_5
;
||________ BRQ / P08_6
;
|_________ RDY / P08_7
#set PFUNC9 B'00001000 ;select control signals
;
||||||||__ CSX0 / P09_0
;
|||||||___ CSX1 / P09_1
;
||||||____ CSX2 / P09_2
;
|||||_____ CSX3 / P09_3
;
||||______ CSX4 / P09_4
;
|||_______ CSX5 / P09_5
;
||________ CSX6 / P09_6
;
|_________ CSX7 / P09_7
#set PFUNC10 B'00011000 ;select control signals
;
|||||||__ (SYSCLK or !SYSCLK) / P10_0
;
||||||___ ASX / P10_1
;
|||||____ BAAX / P10_2
;
||||_____ WEX / P10_3
;
|||______ (MCLKO or !MCLKO) / P10_4
;
||_______ (MCLKI or !MCLKI) / P10_5
;
|________ MCLKE / P10_6
#set EPFUNC10 B'00000000 ;select control signals
;
||
|__ 0:SYSCLK / 1:!SYSCLK
;
||______ 0:MCLKO / 1:!MCLKO
;
|_______ 0:MCLKI / 1:!MCLKI
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;==================================================================
; 6.6.12.9 set PFR08 Register. External bus mode (Control Signals)
;==================================================================
LDI #0x0D88, R1
; Port 8 Function Register, (PFR08)
LDI #PFUNC8, R0
; load port settings
STB R0, @R1
; set register
;====================================================================
; 6.6.12.10 set PFR09 Register. External bus mode (Control Signals)
;====================================================================
LDI #0x0D89, R1
; Port 9 Function Register, (PFR09)
LDI #PFUNC9, R0
; load port settings
STB R0, @R1
; set register
;===================================================================
; 6.6.12.11 set PFR10 Register. External bus mode (Control Signals)
;===================================================================
LDI #0x0D8A, R1
; Port 10 Function Register, (PFR10)
LDI #PFUNC10, R0
; load port settings
STB R0, @R1
; set register
;==================================================================
; .6.12.12 set EPFR10 Register. External bus mode (Control Signals)
;==================================================================
LDI #0x0DCA, R1
; Port 10 Extended Function Register, (EPFR10)
LDI #EPFUNC10, R0; load port settings
STB R0, @R1
; set register
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3.1.4.1.1 Multiplexed mode port function register setting
Using Multiplexed mode lower pin count is required because of Multiplexed addressdata bus usage. In Multiplexed mode ASX signal is required. Find the different port
function setting below:
;====================================================
; 4.9.10 Select External bus mode (Address lines)
;====================================================
#set PFUNC6 B'00000000 ;select address lines
;
||||||||__ A8 / P06_0
;
|||||||___ A9 / P06_1
;
||||||____ A10 / P06_2
;
|||||_____ A11 / P06_3
;
||||______ A12 / P06_4
;
|||_______ A13 / P06_5
;
||________ A14 / P06_6
;
|_________ A15 / P06_7
#set PFUNC7 B'00000000 ;select address lines
;
||||||||__ A0 / P07_0
;
|||||||___ A1 / P07_1
;
||||||____ A2 / P07_2
;
|||||_____ A3 / P07_3
;
||||______ A4 / P07_4
;
|||_______ A5 / P07_5
;
||________ A6 / P07_6
;
|_________ A7 / P07_7
#set PFUNC10 B'00011010 ;select control signals
;
|||||||__ (SYSCLK or !SYSCLK) / P10_0
;
||||||___ ASX / P10_1
;
|||||____ BAAX / P10_2
;
||||_____ WEX / P10_3
;
|||______ (MCLKO or !MCLKO) / P10_4
;
||_______ (MCLKI or !MCLKI) / P10_5
;
|________ MCLKE / P10_6
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3.1.5 External bus clock
To finalise the bus interface settings the external Bus clock needs to be setup. This clock is
output at MCLKO pin. The maximum bus clock frequency at MB88121 side is 33MHz.
Based on a 4MHz external oscillator and internal PLL circuitry the maximal core frequency of
MB91F467D (CLKB) can reach 96MHz. Accordingly the maximal external bus frequency
(CLKT) is 48MHz.
Register DIVR1 configures the clock used by the external bus interface (CLKT). The
example is using following setting:
•
CLKB = 64MHz (CPU frequency)
•
CLKT = CLKB/2 =32MHz
CLKB = [main oscillator * (PLLDIVM + 1) * ( PLLDIVN + 1 ) ] / [ (PLLDIVM + 1) * (DIVR0_B + 1) ]
= [ 4MHz * 2 * 16 ] / [ 2 * 1]
= 64 MHz
3.1.5.1 Example setting in start91460.asm
Following shows the setting required in start91460.asm file.
;==============================================
; 4.6 Clock Selection
;==============================================
; There exist 3 internal clock trees:
; CPU clock, peripheral clock and external bus clock
#set CLOCKSOURCE MAINPLLCLOCK ; select main clock with PLL
#set PLLx16
0x010F
#set PLLSPEED
PLLx16 ; CLKB = 64MHz
; PLLSPEED corresponds to the registers PLLDIVM and PLLDIVN at the
; address 0x48Ch and 0x48Dh.
#set DIV_G 0x0F ; register PLLDIVG at address 0x48Eh
#set MUL_G 0x0F ; register PLLMULG at address 0x48Fh
; PLL auto gear-up and auto gear-down
; recommendation settings for 64MHz
;========================================================
; 4.6.3 Select CPU and peripheral and External-bus clock
;========================================================
#set BASECLOCK_DIV2 0x01
; 1/2 CLKB
#set EXTBUSCLOCK BASECLOCK_DIV2
; external bus clock CLKT=32MHz.
;===============================================
; 6.5.5.2 Set External Bus interface clock
;===============================================
; register DIVR1 set the clock division ratio (relative to the base
; clock) for the clock used by the external bus interface (CLKT).
; Always write 0 to the lower 4 bits of DIVR1 register
LDI #0x0487, R2
; Set DIVR1
LDI #(EXTBUSCLOCK << 4), R3 ;
STB R3, @R2
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3.1.6 Initialisation sequence of MB88121
After the proper setup of the bus interface MB88121 is visual in the MCU address range
starting at 0x50.0000.
The MB88121 requires internal operation frequency of 80 MHz. This frequency is generated
via the internal PLL of the MB88121.
First access to MB88121 should setup the PLL. The PLL is set in the CLOCK CONTROL
REGISTER (CCNT) (Address 0x04 => 0x50.0004).
The example is using a 10 MHz crystal. The PLL must be setup to multiplication ratio x8
(PMUL[1:0]) to achieve the 80 MHz. The PLL must be enabled via PON bit. To supply the
FlexRay CC with clock the STOP bit needs to be set to ‘0’.
Other bits shall be set to ‘0’.
The stabilisation time of the PLL is 600us. After this time the MB88121 The PLL clock usage
can be selected via the CCNT.SEEL bit ( set to ‘1’).
The wait time can be assured using a reload timer of the MCU.
The MB88121 is operating with 80 MHz. It is now possible to initialise the MB88121 with the
FlexRay bus parameter settings.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. */
/* FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR */
/* ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES.
/*
*/
(C) Fujitsu Microelectronics Europe GmbH
#define CCNT ((uint32_t *)0x500004)
*/
/* address of CCNT ERAY Register */
void start_rldtmr_3 (void){
TMCSR3_TRG = 1;
/* start count operation */
}
/* setup of reload timer 3 */
TMCSR3_CNTE = 0;
/* stop reload Timer */
TMRLR3 = 600;
/* set reload value */
TMCSR3 = 0x0802;
/* set MB88121 Clock */
*CCNT = 0x0000000D;
/* enable PLL, PLLx8 */
start_rldtmr_3();
/* start wait time */
while (!TMCSR3_UF);
/* PLL stabilization wait time */
*CCNT = 0x0000000F;
/* switch to PLL clock */
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Interfacing MB91460 TO MB88121
Chapter 3 Software
3.2
Interrupts
Using interrupts of the MB88121 Communication Controller requires connection to
external interrupt pin. That requires also the setup of the external interrupt at MCU
beside the setup of the interrupt at MB88121 side.
3.2.1 MB88121 interrupt
Depending on used bus interface mode the MB88121 have different interrupt pins available.
CC pin
Interrupt type
INT0
E-Ray interrupt line0 (eray_int0)
INT1
E-Ray interrupt line1 (eray_int1)
INT2
E-Ray timer0 interrupt
INT3
E-Ray timer1 interrupt
INT4
Low voltage detection interrupt
Table 3-11 CC interrupt output by 16bit multiplexed mode
CC pin
Interrupt type
INT0
E-Ray interrupt line0 (eray_int0)
INT1
E-Ray interrupt line1 (eray_int1)
E-Ray timer0 interrupt
INT2
E-Ray timer1 interrupt
Low voltage detection interrupt
Table 3-12 CC interrupt output by 16bit non-multiplexed mode
After power-on / Reset these pins are set to output driving Low level. Interrupt requests are
indicated by High Level output at the pins.
To enable the output of the signals INT2 to INT 4 the INT (Interrupt register) at offset
address 0x0C (0x50.000C) must be used. The dedicated E-Ray timer interrupts are
indication a request just a few Macroticks, It is recommended to use rising edge detection for
the external interrupts.
The INT0 and INT1 pins are connected to the Eray_int0 and Eray_int1 interrupts. The
functions are configured with the E-Ray interrupt registers. In case of an interrupt request the
pins output High-level and remaining the level until the Interrupt Flag is clear in the
corresponding register.
Following interrupt registers are available:
•
Error Interrupt Register (EIR): indicates an error interrupt request
•
Status Interrupt Register (SIR): indicates a status interrupt request
•
Error Interrupt Line Select (EILS): Selects which error interrupt is output at which
eray_int (0 or 1) line.
•
Status Interrupt Line Select (SILS): Selects which status interrupt is output at which
eray_int (0 or 1) line.
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Interfacing MB91460 TO MB88121
Chapter 3 Software
•
Error Interrupt Enable Set / Reset (EIES, EIER): Enable / disable error interrupts
•
Status Interrupt Enable Set / Reset (SIES, SIER) : Enable / disable status interrupts
•
Interrupt Line Enable (ILE): Enable interrupt lines
3.2.2 MCU external interrupt
Following show the setup and usage of the external interrupt (rising edge) for MB88121
connection.
Following registers are relevant for external interrupt:
•
ELVR: interrupt request level register
•
EIRR: interrupt request register
•
ENIR: interrupt request enable register
•
DDR: data direction register
•
PFR: port function register
•
ICR: interrupt control register
3.2.2.1 External interrupt configuration registers
Register ELVR, EIRR and ENIR specify the external interrupt function. ELVR defines how to
detect interrupt request signal. EIRR shows if an external interrupt request is detected. ENIR
enables/disables interrupt request.
External interrupt 0-7
Bit value
register
address
7
6
5
4
3
2
1
0
EIRR0
0x30
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
ENIR0
0x31
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR0
0x32
0x33
External interrupt 8-14
Bit value
register
address
7
6
5
4
3
2
1
0
EIRR1
0x34
\
ER14
ER13
ER12
\
ER10
ER9
ER8
ENIR1
0x35
\
EN14
EN13
EN12
\
EN10
EN9
EN8
15
14
13
12
11
10
9
8
\
\
LB14
LA14
LB13
LA13
LB12
LA12
7
6
5
4
3
2
1
0
\
\
LB10
LA10
LB9
LA9
LB8
LA8
ELVR1
0x36
0x37
Table 3-13 EIRR, ENIR ELVR overview
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Chapter 3 Software
LBn
LAn
Description
0
0
Detect “L” level and generate an interrupt request
0
1
Detect “H” level and generate an interrupt request
1
0
Detect the rising-edge and generate an interrupt request
1
1
Detect the falling-edge and generate an interrupt request
Table 3-14 ELVR register
CC interrupt pins are high-level active. Therefore signal high-level or rising-edge should be
chosen for external interrupt detection.
ERn
Read register
Write register
0
No external interrupt
request present
Clear external interrupt request flag
1
External interrupt
request present
No effect
Table 3-15 EIRR register
ENn
Description
0
External interrupt request is disabled
1
External interrupt request is enabled
Table 3-16 ENIR register
3.2.2.2 Port function Register (PFR)
MB91F467D have altogether 14 external interrupt channels. User should choose three of
them for 16bit non-multiplexed mode.
The external interrupt function is assigned to MCU port22, port23 and port24. Each of them
has a 8bit port function register (PFR). The default value of register the PFR after reset is
zero, respectively all ports are general purpose input. To use the external interrupt function
only register PFR should be set to one.
Note:
All input pins are disabled by default. After pin configuration according
to its function it is necessary to enable the input pins globally:
PORTEN = 0x3;
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Interfacing MB91460 TO MB88121
Chapter 3 Software
MCU pin Nr
83
84
85
86
Port24
87
88
89
90
91
Port23
93
95
Pin function
P24_0
General purpose I/O
PFR24_0=0
DDR24_0=0/1
INT0
External interrupt 0
PFR24_0=1
DDR24_0=0
P24_1
General purpose I/O
PFR24_1=0
DDR24_1=0/1
INT1
External interrupt 1
PFR24_1=1
DDR24_1=0
P24_2
General purpose I/O
PFR24_2=0
DDR24_2=0/1
INT2
External interrupt 2
PFR24_2=1
DDR24_2=0
P24_3
General purpose I/O
PFR24_3=0
DDR24_3=0/1
INT3
External interrupt 3
PFR24_3=1
DDR24_3=0
P24_4
General purpose I/O
PFR24_4=0
DDR24_4=0/1
INT4
External interrupt 4
PFR24_4=1
DDR24_4=0
SDA2
Serial data pin for I2C 2
PFR24_4=1
DDR24_4=0/1
P24_5
General purpose I/O
PFR24_5=0
DDR24_5=0/1
INT5
External interrupt 5
PFR24_5=1
DDR24_5=0
SCL2
Serial clock pin for I2C 2
PFR24_5=1
DDR24_5=0/1
P24_6
General purpose I/O
PFR24_6=0
DDR24_6=0/1
INT6
External interrupt 6
PFR24_6=1
DDR24_6=0
SDA3
Serial data pin for I2C 3
PFR24_6=1
DDR24_4=0/1
P24_7
General purpose I/O
PFR24_7=0
DDR24_7=0/1
INT7
External interrupt 7
PFR24_7=1
DDR24_7=0
SCL3
Serial clock pin for I2C 3
PFR24_7=1
DDR24_7=0/1
P23_0
General purpose I/O
PFR23_0=0
DDR23_0=0/1
INT8
External interrupt 8
PFR23_0=1
DDR23_0=0
RX0
Reception input pin for CAN 0
PFR23_0=1
DDR23_0=0
P23_2
General purpose I/O
PFR23_2=0
DDR23_2=0/1
INT9
External interrupt 9
PFR23_2=1
DDR23_2=0
RX1
Reception input pin for CAN 1
PFR23_2=1
DDR23_2=0
P23_4
General purpose I/O
PFR23_4=0
DDR23_4=0/1
INT10
External interrupt 10
PFR23_4=1
DDR23_4=0
PFR23_4=1
DDR23_4=0
RX2
97
Port22
98
99
precondition
Reception input pin for CAN 2
P22_0
General purpose I/O
PFR22_0=0
DDR22_0=0/1
INT12
External interrupt 12
PFR22_0=1
DDR22_0=0
P22_2
General purpose I/O
PFR22_2=0
DDR22_2=0/1
INT13
External interrupt 13
PFR22_2=1
DDR22_2=0
P22_4
General purpose I/O
PFR22_4=0
DDR22_4=0/1
INT14
External interrupt 14
PFR22_4=1
DDR22_4=0
SDA0
Serial data pin for I2C 0
PFR22_4=1
DDR22_4=0/1
© Fujitsu Microelectronics Europe GmbH
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Interfacing MB91460 TO MB88121
Chapter 3 Software
Table 3-17 I/O port configuration for external interrupt
An initialization example of the external interrupt 5 is shown below.
void Init_extint_5 (void){
ENIR0_EN5 = 0;
/* disable extInt5 interrupt */
DDR24_D5 = 0;
/* port24.5 Data direction: input */
PFR24_D5 = 1;
/* set Port function of P24.5 to external Interrupt */
ELVR0_LB5 = 1;
/* rising edge detection */
ELVR0_LA5 = 0;
EIRR0_ER5 = 0;
/* clear interrupt request flag */
ENIR0_EN5 = 1;
/* enable extInt5 interrupt */
}
Before enabling the external interrupt request (ENn = 1) it is recommended to clear the
request flag of the external interrupt (ERn = 0) to avoid interrupts caused by previous trigger
(ERn is set independently of the setting of ENn).
3.2.2.3 Interrupt vector table
Register ICR defines the interrupt level. 16 priority levels are programmable. Level 16 has
the highest priority and level 31 disable the interrupt. The address of each interrupt service
routine is set in the interrupt vector. The vector address for each external interrupt is
calculated by adding the offset (listed in the following table) to the table base register value
(TBR). The TBR specifies the top of the interrupt vector table. Its initial value after a reset is
0x000FFC00.
External
interrupt
channel
Interrupt
number
(decimal)
0
16
1
17
2
18
3
19
4
20
5
21
6
22
7
23
8
24
9
25
10
26
reserved
27
12
28
13
29
MCU-AN-300016-E-V10
Interrupt level
Interrupt vector
Configuration
register
Register
address
ICR00
0x440
ICR01
0x441
ICR02
0x442
ICR03
0x443
ICR04
0x444
ICR05
0x445
ICR06
0x446
- 40 -
Offset
Default vector
address
0x3BC
0x000FFFBC
0x3B8
0x000FFFB8
0x3B4
0x000FFFB4
0x3B0
0x000FFFB0
0x3AC
0x000FFFAC
0x3A8
0x000FFFA8
0x3A4
0x000FFFA4
0x3A0
0x000FFFA0
0x39C
0x000FFF9C
0x398
0x000FFF98
0x394
0x000FFF94
0x390
0x000FFF90
0x38C
0x000FFF8C
0x388
0x000FFF88
© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
External
interrupt
channel
Interrupt
number
(decimal)
14
30
reserved
31
Interrupt level
Configuration
register
Register
address
ICR07
0x447
Interrupt vector
Offset
Default vector
address
0x384
0x000FFF84
0x380
0x000FFF80
Table 3-18 Interrupt vector table
A default interrupt vector table for MB91460 series is located in file vectors.c (provided in
the template project). An example for the external interrupt 5 is shown below.
void InitIrqLevels(void) /* interrupt level definition */
{
…
ICR02 = 28;
/* external Interrupt 5 */
…
}
…
__interrupt void ExtInt5_IRQHandler(void); /* interrupt service routine */
…
#pragma intvect ExtInt5_IRQHandler 21
/* interrupt vector definition */
…
Note:
After reset the external interrupt request is masked without reception (I flag of register CCR is zero).
User should set this flag to one in the application through interrupt mask disable function ‘__EI()’
© Fujitsu Microelectronics Europe GmbH
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Interfacing MB91460 TO MB88121
Chapter 3 Software
3.3
DMA usage
To fasten payload data access, the MB88121 supports DMA request for Input and Output
buffer transfer.
3.3.1 DMA register at MB88121
The lower 16-bit (Bit 15..0) of the CUS2 Register (Adr. 0x08 => 0x50.0008) are used to
control the DMA request feature of MB88121.
The DMAINV bit selects the Active Level (High or Low), the DMAOE bit select if DAM
request is output to a pin. The DMARE bit enables the interrupt request.
See also the Users Guide of MB88121 series.
3.3.2 DMA at MB91460
The MB91460 series DMA supports different transfer modes. In this example we are using
2-cycle transfer type: data is read from an address and then written to another address. The
Fly-by transfer type is suitable for DMA function between external I/O and external memory.
Therefore register IOWR is not used.
For further details see Hardware Manual of MB91460 series and Application note mcu-an300059-e-mb91460_dma.
Using the DMA following needs to be encountered:
The MB88121 is connected to the external transfer request pin “DREQ0” in our example. So
this DMA bus interface transfer needs to be setup.
Following settings have to be selected:
-
Source address
-
Destination address
-
Increment / decrement source / destination address
-
Data length
-
Number of data transmissions (data count)
-
DMA channel assignment
-
Transfer type
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
3.3.3 DMA flow for Output buffer transfer
Figure 3-7: Output buffer DMA flow
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300016-E-V10
Interfacing MB91460 TO MB88121
Chapter 3 Software
3.3.4 DMA flow for input buffer transfer
Figure 3-8 Input buffer DMA flow
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
3.4
Debugging support
The MB88121 offering also debug support at some pins.
CC debug pins
CC pin Nr
Name
Function
I/O type
7
SDS
Start of dynamic segment
OUT
8
CYCS0
Cycle 0 start
OUT
14
CYCS
Cycle start
OUT
23
MT
Macrotick start
OUT
38
MBSU_TX1
39
MBSU_RX1
44
MBSU_TX2
Message buffer status update port
OUT
45
MBSU_RX2
Configuration register
Debug support register
DBGS
Table 3-19: Debug pins on MB88121
The gray shaded pins are only available in 16-bit multiplexed mode.
After power on / reset these pins are set to output driving Low level.
The upper 16-bit (Bit 31..16) of CUS2 Register is called Debug support register (DBGS),
having the offset address 0x08 (0x50.0008) . Via these pins the output of the dedicated
debug signal is controlled.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300016-E-V10
Interfacing MB91460 TO MB88121
Chapter 4 Reference
4 Reference
•
Application note: mcu-an-300021-e-start91460 describing start91460.asm file
•
Application note: mcu-an-300033-e-mb91460_hw_setup
•
Application note: mcu-an-300055-e-mb91460_irq
•
Application note: mcu-an-300059-e-mb91460_dma
•
MB91F467D series Datasheet
•
Hardware Manual for MB91460 series
•
MB88121B series Datasheet
•
MB88121 series User’s Manual
•
Starter kit SK-91F467-FLEXRAY
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 5 Appendix
5 Appendix
5.1
Connection example using none-multiplexed Bus interface
A connection example of the non-multiplexed mode is summarized in the following table.
The gray entries show the differences between two parallel modes. All pins of the MB88121
communication controller (CC) are divided into 7 categories:
•
External bus interface: CC pins in connection with MCU pins
•
CC mode pins
•
CC debug pins
•
CC stop watch trigger pin
•
CC pins in connection with physical layer transceiver
•
CC power supply pins
•
CC external clock pin
Note:
1. The connection of the interrupt pins is application-specific. The table here shows only
an example.
2. The CC reset pin can be controlled by MCU reset pin or by an independent circuitry.
3. By default settings in file start91460.asm (see chapter 2.5) chip select area 3 is
configured. Other areas can also be used.
4. For the power supply it should be noticed that MB88121B is a single voltage supply
chip. All power supply pins should have the same supply voltage between 3.3V and
5V (see chapter 2.2).
© Fujitsu Microelectronics Europe GmbH
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Chapter 5 Appendix
External bus interface: MB88121 pins in connection with MCU MB91F467D pins
CC pin Nr
Name
35
Function
MCU pin Nr
Name
A10
30
P06_2/A10
36
A9
29
P06_1/A9
37
A8
28
P06_0/A8
38
A7
25
P07_7/A7
39
A6
24
P07_6/A6
40
A5
23
P07_5/A5
41
A4
22
P07_4/A4
42
A3
21
P07_3/A3
43
A2
20
P07_2/A2
44
A1
19
P07_1/A1
45
A0
18
P07_0/A0
CC pin Nr
Name
MCU pin Nr
Name
46
D15
17
P00_7/D31
47
D14
16
P00_6/D30
50
D13
15
P00_5/D29
51
D12
14
P00_4/D28
52
D11
13
P00_3/D27
53
D10
12
P00_2/D26
54
D9
11
P00_1/D25
55
D8
10
P00_0/D24
56
D7
9
P01_7/D23
57
D6
8
P01_6/D22
58
D5
7
P01_5/D21
59
D4
6
P01_4/D20
60
D3
5
P01_3/D19
61
D2
4
P01_2/D18
62
D1
3
P01_1/D17
63
D0
2
P01_0/D16
CC pin Nr
Name
MCU pin Nr
Name
10
INT0
83
P24_0/INT0
34
INT1
84
P24_1/INT1
22
INT2
85
P24_2/INT2
CC pin Nr
Name
MCU pin Nr
Name
6
RST
Reset
15
BCLK
Bus clock
65
P10_4/MCLKO
19
CS
Chip select
59
P09_3/CSX3
20
RD
Read enable
50
P08_4/RDX
Address bus
MCU=>CC
Function
Data bus
MCU
CC
Function
1
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CC interrupt output
CC=>MCU
Function
MCU=>CC
- 48 -
73
INITX
2
3
© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 5 Appendix
21
WR
Write enable
27
RDY
Ready signal
31
DMA_REQ
DMA request
CC=>MCU
64
P10_3/WEX
55
P08_7/RDY
189
P13_0/DREQ0
CC mode pins
CC pin Nr
Name
64
MD2
4
MD1
5
MD0
28
MDE2
29
MDE1
30
MDE0
Function
I/O type
Logic value
1
Mode selection
16bit parallel bus interface
0
0
IN
1
Extended mode
selection
Non-multiplexed mode
for MB91460
0
0
CC debug pins
CC pin Nr
Name
Function
7
SDS
Start of dynamic segment
8
CYCS0
Cycle 0 start
14
CYCS
Cycle start
23
MT
Macrotick start
I/O type
Configuration register
OUT
Debug support register
DBGS
CC stop watch trigger pin
CC pin Nr
Name
I/O type
Function
9
STPW
IN
After stop watch is triggered (rising or falling edge), register STPW1
captures actual cycle counter and macrotick value, register STPW2
captures slot counter values for channel A and B.
CC pins in connection with physical layer transceiver
CC pin Nr
Name
Function
I/O type
11
TXDA
Data transmission
OUT
12
TXENA
Channel transmission enable
OUT
13
RXDA
Data reception
IN
24
RXDB
Data reception
IN
25
TXENB
Channel transmission enable
OUT
26
TXDB
Data transmission
OUT
Channel A transceiver (U4)
Channel B transceiver (U10)
CC power pins
CC pin Nr
Name
Function
1,17,33,49
VSS
0V Ground
16, 32, 48
18
VCC
4
single power supply input between 3.3v and 5v
C
Power supply stabilization capacitor (W100nF)
CC external clock pin
CC pin Nr
Name
Function
2
X1
Oscillation output
3
X0
Oscillation input
4MHz, 5MHz,8MHz,10MHz
crystal or ceramic oscillator
Table 5-1 16bit non-multiplexed mode
© Fujitsu Microelectronics Europe GmbH
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Chapter 5 Appendix
Figure 5-1 Schematic view of the non-multiplexed mode
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 5 Appendix
5.2
Connection example using multiplexed bus interface
A connection example of the multiplexed mode is summarized in the following table. The
gray entries show the differences between two parallel modes. All pins of the communication
controller (CC) are divided into 7 categories:
•
External bus interface: CC pins in connection with MCU pins
•
CC mode pins
•
CC debug pins
•
CC stop watch trigger pin
•
CC pins in connection with physical layer transceiver
•
CC power supply pins
•
CC external clock pin
Note:
1. The connection of the interrupt pins is application-specific. The table here shows only
an example.
2. The CC reset pin can be controlled by MCU reset pin or by an independent circuitry.
3. By default settings in file start91460.asm (see chapter 3.5) chip select area 3 is
configured. Other areas can also be used.
4. For the power supply it should be noticed that MB88121B is a single voltage supply
chip. All power supply pins should have the same supply voltage between 3.3V and
5V (see chapter 3.2).
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Chapter 5 Appendix
External bus interface: CC pins in connection with MCU pins
CC pin Nr
Name
53
MCU pin Nr
Name
AD10
12
P00_2/D26
54
AD9
11
P00_1/D25
55
AD8
10
P00_0/D24
56
AD7
9
P01_7/D23
57
AD6
8
P01_6/D22
58
AD5
7
P01_5/D21
59
AD4
6
P01_4/D20
60
AD3
5
P01_3/D19
61
AD2
4
P01_2/D18
62
AD1
3
P01_1/D17
63
AD0
2
P01_0/D16
CC pin Nr
Name
MCU pin Nr
Name
46
D15
17
P00_7/D31
47
D14
16
P00_6/D30
50
D13
15
P00_5/D29
51
D12
14
P00_4/D28
52
D11
13
P00_3/D27
CC pin Nr
Name
MCU pin Nr
Name
83
P24_0/INT0
84
P24_1/INT1
85
P24_2/INT2
10
INT0
Function
Address/data bus
MCU
CC
Function
Data bus
MCU
CC
Function
1
34
INT1
35
INT2
36
INT3
86
P24_3/INT3
37
INT4
87
P24_4/INT4
CC pin Nr
Name
MCU pin Nr
Name
6
RST
Reset
73
15
BCLK
Bus clock
65
P10_4/MCLKO
19
CS
Chip select
59
P09_3/CSX3
20
RD
Read enable
50
P08_4/RDX
21
WR
Write enable
64
P10_3/WEX
22
AS
Address strobe
62
P10_1/ASX
27
RDY
Ready signal
55
P08_7/RDY
31
DMA_REQ
DMA request
189
P13_0/DREQ0
Interrupt output
CC=>MCU
Function
MCU=>CC
CC=>MCU
INITX
2
3
CC mode pins
CC pin Nr
Name
64
MD2
4
MD1
5
MD0
MCU-AN-300016-E-V10
Function
I/O type
IN
Mode selection
Logic value
1
0
16bit parallel bus interface
0
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© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 5 Appendix
28
MDE2
29
MDE1
30
MDE0
0
Extended mode
selection
0
Multiplexed mode
for MB91460
0
CC debug pins
CC pin Nr
Name
Function
I/O type
7
SDS
Start of dynamic segment
OUT
8
CYCS0
Cycle 0 start
OUT
14
CYCS
Cycle start
OUT
23
MT
Macrotick start
OUT
38
MBSU_TX1
39
MBSU_RX1
44
MBSU_TX2
Message buffer status update port
OUT
45
MBSU_RX2
Configuration register
Debug support register
DBGS
CC stop watch trigger pin
CC pin Nr
Name
I/O type
Function
9
STPW
IN
After stop watch is triggered (rising or falling edge), register STPW1
captures actual cycle counter and macrotick value, register STPW2
captures slot counter values for channel A and B.
CC pins in connection with physical layer transceiver
CC pin Nr
Name
Function
I/O type
11
TXDA
Data transmission
OUT
12
TXENA
Channel transmission enable
OUT
13
RXDA
Data reception
IN
24
RXDB
Data reception
IN
25
TXENB
Channel transmission enable
OUT
26
TXDB
Data transmission
OUT
Connection
Channel A transceiver
(U4)
Channel B transceiver
(U10)
CC power pins
CC pin Nr
Name
Function
1,17,33,49
VSS
0V Ground
16, 32, 48
18
VCC
4
Single power supply input between 3.3v and 5v
C
Power supply stabilization capacitor (W100nF)
CC external clock pin
CC pin Nr
Name
Function
2
X1
Oscillation output
3
X0
Oscillation input
4MHz, 5MHz,8MHz,10MHz
crystal or ceramic oscillator
Difference between two parallel modes: grey
Table 5-2 16bit multiplexed mode
© Fujitsu Microelectronics Europe GmbH
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Chapter 5 Appendix
Figure 5-2 Schematic view of the multiplexed mode
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Interfacing MB91460 TO MB88121
Chapter 5 Appendix
5.3
Tables
Table 2-1 MB91F467D power supply pins.............................................................................. 7
Table 2-2 Relationship of the power supply............................................................................ 7
Table 2-3 Configuration of internal ROM external bus mode.................................................. 8
Table 2-4 Mode selection input of the communication controller .......................................... 10
Table 2-5 Mode selection input of the communication controller .......................................... 10
Table 2-6: 16-bit none multiplex bus interface pin assignment ............................................. 11
Table 2-7: 16-bit multiplexed bus interface pin assignment .................................................. 12
Table 2-8 CC interrupt output by 16bit multiplexed mode..................................................... 13
Table 2-9 CC interrupt output by 16bit non-multiplexed mode.............................................. 13
Table 2-10: Debug pins on MB88121................................................................................... 14
Table 3-1 External bus interface registers ............................................................................ 19
Table 3-2 Register ACR content .......................................................................................... 20
Table 3-3 ASZ bits of register ACR ...................................................................................... 21
Table 3-4 TYP bits of register ACR for 16-bit none multiplexed mode.................................. 21
Table 3-20 TYP bits of register ACR for 16-bit multiplexed mode......................................... 21
Table 3-5 DBW and BST bits of register ACR ...................................................................... 22
Table 3-6 Register AWR content.......................................................................................... 23
Table 3-7 Initial I/O port function .......................................................................................... 28
Table 3-8 Port function registers (PFR/EPFR) and their initial values in memory ................. 28
Table 3-9 11bit address line ................................................................................................. 29
Table 2-8 CC interrupt output by 16bit multiplexed mode..................................................... 36
Table 2-9 CC interrupt output by 16bit non-multiplexed mode.............................................. 36
Table 3-10 EIRR, ENIR ELVR overview............................................................................... 37
Table 3-11 ELVR register..................................................................................................... 38
Table 3-12 EIRR register ..................................................................................................... 38
Table 3-13 ENIR register ..................................................................................................... 38
Table 3-14 I/O port configuration for external interrupt ......................................................... 40
Table 3-15 Interrupt vector table .......................................................................................... 41
Table 2-10: Debug pins on MB88121................................................................................... 45
Table 5-1 16bit non-multiplexed mode ................................................................................. 49
Table 5-2 16bit multiplexed mode ........................................................................................ 53
5.4
Figures
Figure 2-1 Memory map of internal ROM external bus mode ................................................. 9
Figure 3-1 MB88121 read operation (non-multiplexed) ........................................................ 15
Figure 3-2 MB88121 Write operation (non-multiplexed) ....................................................... 16
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Interfacing MB91460 TO MB88121
Chapter 5 Appendix
Figure 3-3 MB88121 read operation (multiplexed mode)...................................................... 17
Figure 3-4 MB88121 write operation (multiplexed) ............................................................... 18
Figure 3-5 Timing example of the non-multiplexed mode ..................................................... 24
Figure 3-6 Timing example of the multiplexed bus mode ..................................................... 25
Figure 3-7: Output buffer DMA flow...................................................................................... 43
Figure 3-8 Input buffer DMA flow ......................................................................................... 44
Figure 5-1 Schematic view of the non-multiplexed mode ..................................................... 50
Figure 5-2 Schematic view of the multiplexed mode ............................................................ 54
-- END --
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