The following document contains information on Cypress products. RECOMMENDATION FOR HARDWARE SETUP 32-BIT MICROCONTROLLER FR81S Family APPLICATION NOTE Publication Number ANxxx-xxxxx CONFIDENTIAL Revision 1.3 Issue Date January 06, 2014 A P P L I C A T I O N 2 CONFIDENTIAL N O T E ANxxx-xxxxx-1v0-E, January 06, 2014 A P P L I C A T I O N N O T E Target products This application note is described about FR81S products; , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 3 A P P L I C A T I O N N O T E Table of Contents 1 2 3 4 5 6 7 8 4 CONFIDENTIAL Introduction .............................................................................................................................................. 6 Minimal System........................................................................................................................................ 7 2.1 Schematic ....................................................................................................................................... 7 2.2 Serial Interface ............................................................................................................................... 7 2.3 Power supply .................................................................................................................................. 7 2.4 Analog Digital Converter Supply Pins ............................................................................................. 8 2.5 Analog Input Pins ........................................................................................................................... 8 2.6 Reset Pin (RSTX) ........................................................................................................................... 9 2.7 Non maskable Interrupt Pin (NMIX) ................................................................................................ 9 2.8 C-Pin .............................................................................................................................................. 9 2.9 Clock Source ................................................................................................................................ 10 2.10 Mode Pins .................................................................................................................................... 10 2.11 Not Connected Pins...................................................................................................................... 11 2.12 Debug Interface connection .......................................................................................................... 11 Layout and Electromagnetic Compatibility ......................................................................................... 13 3.1 General......................................................................................................................................... 13 3.2 Power supply Pins ........................................................................................................................ 13 3.3 Oscillator Pins............................................................................................................................... 14 3.4 Power Line Routing ...................................................................................................................... 14 3.5 Power Supply Decoupling ............................................................................................................ 15 3.6 Recommended Power Supply Circuit ........................................................................................... 16 3.7 Reset circuit .................................................................................................................................. 17 3.8 Quartz Crystal Placement and Signal Routing ............................................................................. 20 3.9 Test points .................................................................................................................................... 21 3.10 Other documents .......................................................................................................................... 22 Port Input / Unused Pins / Latch-up ..................................................................................................... 23 4.1 Port Input / Unused Pins ............................................................................................................... 23 4.2 Latch-up consideration (switch) .................................................................................................... 24 4.3 5V tolerant Input pins.................................................................................................................... 27 Flash Programming Connection .......................................................................................................... 28 5.1 Overview ...................................................................................................................................... 28 5.2 Serial programming via UART0 .................................................................................................... 28 5.3 Serial programming via MDI interface .......................................................................................... 30 5.4 Parallel programming interface ..................................................................................................... 31 5.5 Security function ........................................................................................................................... 32 Reset Behaviour of IO port pins ........................................................................................................... 33 Appendix ................................................................................................................................................ 34 7.1 References ................................................................................................................................... 34 MAJOR CHANGES IN THIS EDITION .................................................................................................... 35 mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Table of Figures Figure 2-1: Principle schematic for minimal requirements .......................................................................... 7 Figure 2-2 : Analog input circuit model ....................................................................................................... 8 Figure 2-3: Internal voltage regulator and C Pin. ...................................................................................... 10 Figure 2-4: How to connect debug system with programming connector .................................................. 11 Figure 3-1: Example of bad vs. good power line routing .......................................................................... 14 Figure 3-2: Example of PCB layer stack. .................................................................................................. 15 Figure 3-3: Power supply decoupling caps placement. ............................................................................ 15 Figure 3-4: Power supply decoupling on single-side assembled boards .................................................. 16 Figure 3-5: Power supply decoupling on double-side assembled boards................................................. 16 Figure 3-6: Principal Supply circuit ........................................................................................................ 17 Figure 3-7: Block diagram of reset extension circuit ................................................................................. 18 Figure 3-8: External reset timing .............................................................................................................. 18 Figure 3-9: Block diagram of reset extension circuit ................................................................................. 19 Figure 3-10: Principle oscillator circuit. ..................................................................................................... 20 Figure 3-11: Principal oscillator circuit and startup sequence ................................................................... 20 Figure 3-12: Layout example for crystal oscillator circuit .......................................................................... 21 Figure 3-13: Stray capacitance of PCB .................................................................................................... 21 Figure 3-14 : MONCLK internal clock select and prescaler. ..................................................................... 21 Figure 3-15: Supported output functions for test purposes ....................................................................... 22 Figure 4-1: Principal using of input circuit to avoid latch-up or leak current.............................................. 23 Figure 4-2: Usual configuration switch. .................................................................................................... 24 Figure 4-3: Usual configuration switch, equivalent circuit. ........................................................................ 24 Figure 4-4: Signal rise on switch closing (Point A).................................................................................... 25 Figure 4-5: Signal rise on switch closing (Point B). .................................................................................. 25 Figure 4-6: Equivalent circuit on switch closed. ........................................................................................ 25 Figure 4-7: Signal on the pin. ................................................................................................................... 26 Figure 4-8: Signal on the pin with a large capacity. .................................................................................. 26 Figure 4-9: Signal on the pin with a small capacity................................................................................... 26 Figure 4-10: Series resistor. ..................................................................................................................... 27 Figure 4-11: Reduction of the signal on the pin due to the series resistor. ............................................... 27 Figure 4-12: Standard IO Figure 4-13: 5V tolerant IO ............................................................. 27 Figure 5-1: Principle schematic for serial programming via Usart0 (with USB cable) ............................... 28 Figure 5-2: Principle schematic for serial programming via Usart0. ......................................................... 29 Figure 5-3: Snapshot of the FR program used for flash programming via Usart0. ................................... 29 Figure 5-4: Connection of the MB2100-01-E with the host computer and target board. ........................... 30 Figure 5-5: Picture of the MB2100-01-E. .................................................................................................. 30 Figure 5-6: Electronic components needed to protect the Debug I/F pin. ................................................. 31 Figure 5-7: Parallel programming with GALEP-5D ................................................................................... 31 Tables Table 2-1: Reference values ....................................................................................................................... 8 Table 2-2: RSTX and NMIX function........................................................................................................... 9 Table 2-3: Mode Pin Settings (x: does not care) ........................................................................................ 11 Table 2-4: SPEED-BOX general specifications ......................................................................................... 11 Table 3-1: Power Supply pins in use ........................................................................................................ 14 Table 3-2: Oscillator pins in use ............................................................................................................... 14 Table 3-3: External reset timing ................................................................................................................ 18 Table 6-1 : Power-On/RSTX reset state GPIO initial state ....................................................................... 33 , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 5 A P P L I C A T I O N N O T E 1 Introduction This application note describes how to set up a hardware environment for Spansion FR81S MCUs. As an example, the MB91F52x MCU is used. This design guide describes design restrictions and recommendations regarding signal wiring and the electrical power system of the MCU. For more details about the device features and its relevant settings, please refer to the FR81S Hardware Manual and its corresponding Datasheet for electrical characteristics. 6 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 2 Minimal System THIS CHAPTER GIVES AN EXAMPLE FOR A MINIMUM HARDWARE SYSTEM. 2.1 Schematic The following graphic shows a schematic of a minimum hardware system. Note that for other MCU families a different pinning is needed. PC connection MCU system 5V *2 100n AVcc AVRH AVss/AVRL 11 SOT0_0 T1IN 2 V+ 1 C1+ R1OUT 12 3 C1MAX232 4 C2+ Debug Connector SIN0_0 32.768kHz 100n 100n *1 DEBUGIF X0A 43R 12p RSTX MB91F52x 12p 2k RESET 1n X1A 10p 1 5 X1 C VSS 6 2K7 NMIX P006 MD0 MD1 2K7 4MHz T1OUT R1IN Vss 14 13 15 5V 5V X0 10p 2K7 8 R2IN 10 T2IN 33k 5 C26 V100n Vcc 10k 16 Vcc 100n 100k 100n 9 4u7 Figure 2-1: Principle schematic for minimal requirements *1 only needed for dual clock devices. *2 please refer to chapter Error! Reference source not found.. 2.2 Serial Interface The “PC connection” section is only needed, if no 5V external serial data lines for programming exist. The MAX232 is a standard level shifter, which converts the 5V levels of the MCU to 12V RS232V24 levels and vice versa. If you use a 3.3V system a MAX3232 is recommended. Please consider, that the internal charge pumps of the level shifter can produce noise on the +5 Volts line, which can influence the ADC, if AVCCn and AVRHn are directly (unfiltered) connected to it. 2.3 Power supply The power supply should be from 2.7 Volts to 5.5 Volts for normal usage. If a different supply voltage is used please refer to the corresponding data sheet. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 7 A P P L I C A T I O N N O T E 2.4 Analog Digital Converter Supply Pins The analog converter supply pins (AVCCn, AVRHn / AVRLn, AVSSn) should be connected even if the ADC of the MCU is not used. Please refer to our application note “mcu-an-300215-e-16fx_adc” for using the ADC and pin connection. 2.5 Analog Input Pins Because the ADC works with an internal sample capacitor (Cadc) you must be aware of the time needed to fully charge this capacitor to the corresponding analog signal source voltage level by the end of the sample time. When the external impedance is too high, the sampling period for analog voltages may not be sufficient. In this case, it is recommended to connect an external capacitor (Cext, approx. 0.1 μF) to the analog input pin. An input impedance maximum (Rext) 15k Ohm is recommended. So, an appropriate sample time has to be selected depending on the impedance Rext and the capacitance Cext. Please refer to Datasheet “A/D Converter” chapter for further information. MCU Analog Signal Source #1 Analog Signal Source #2 Analog Signal Source #n AN1 pin Analog SW (Closed during sample) Rext Cext Cpad AN2 pin Analog SW Rext Radc ADC Cpad Cext ANn pin Cadc Analog SW Rext Cext Cpad Figure 2-2 : Analog input circuit model Component Value AVcc Cadc 8.30 pF (Max) 4.5V… 5.5V Cadc 8.30 pF (Max) 3V… 3.6V Radc 1.9K (Max) 4.5V… 5.5V Radc 4.3K (Max) 3V… 3.6V Cpin 5pF..15pF Table 2-1: Reference values 8 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 2.6 Reset Pin (RSTX) To reset the MCU a switch connects this pin to Vss (Ground). There is internal 50k pull-up resistor, but for high noise requirements an external pull-up resistor with typical 10k is recommended. Additionally a capacitor has to be connected between Vss and the reset pin for debouncing the switch and for EMI protection. From experience a capacity of not more than 1 nF is recommended. This capacity covers the most common frequency protection in a wide range. Higher capacities and high impedance may cause latch-up effects together with an RSTX-Switch and low EMI protection. The reset level of RSTX pins depends on the logical level on NMIX pin. . Please refer to Hardware manual chapter 7 Reset. RSTX NMIX Function 1 1 0 1 0 1 0 0 Normal operation Non maskable interrupt External reset Reset (RST) Synchronous reset factor Irregular reset Initialize reset (INIT) Asynchronous reset factor (not guarantee that memory contents have not been destroyed by the reset) Table 2-2: RSTX and NMIX function 2.7 Non maskable Interrupt Pin (NMIX) The NMIX supports two several functions, (a) using as NMI input and (b) simultaneous assert of RSTX and NMIX pins to generate an irregular reset. There is internal 50k pull-up resistor, but for high noise requirements an external pull-up resistor with typical 10k is recommended. 2.8 C-Pin A 4.7 µF ceramic capacitor (dielectric X7R) must be connected very close to the C pin of the MCU. Furthermore an additional 100nF (dielectric X7R) for higher noise frequencies is recommended. Otherwise the MCU may not operate correct or will be damaged in worst case. Please refer to Datasheet chapter “Recommended operating conditions” for further information. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 9 A P P L I C A T I O N 5V GND Vcc GPIO GPIO Vcc GPIO Vss GPIO GND Vss GND CORE Internal 1.2V internal voltage regulator GPIO 5V OSC Vcc GPIO 5V GPIO GPIO Vss GPIO MCU N O T E C 4.7µF (ceramic X7R) Vss *1 GND GPIO GPIO Vcc 5V GPIO Note *1 : Vss pin closest to C pin Vss GND Figure 2-3: Internal voltage regulator and C Pin. 2.9 Clock Source A clock source must be provided to the MCU. Therefore crystals or external clock signals can be used. For external source pin X0 (X0A) is used whereby pin X1 (X1A) is not connected. There are MCU derivatives for dual clock and single clock devices, the sub clock can be enabled by software. If sub clock X0A pin is neither used as GPIO nor as clock input, the pin can be left open. If you want to use only CR clock then you need a MCU version with disabled CSV. Please also refer to the chapter “Handling the device” in the corresponding hardware manual for details. 2.10 Mode Pins The mode pins set the current operation mode for the MCU. For a minimal system only two modes are necessary: Flash-Asynchronous-Serial-Programming-Mode and Run Mode. In the case you use the Serial Programming Mode the MD-pins need pull-up/pull-down resistors (typically 2k7 resistors). In order to increase the protection against ESD and EMI effects the PCB tracks should be as short as possible. If the Serial Programming Mode is not used the MD-pins can be connected directly to Vcc or GND. Please refer to Datasheet chapter “Handling devices” for further information. The following settings are used for the both modes mentioned above: 10 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Mode P006 MD0 MD1 Serial Programming Mode 1 0 1 Run (Internal Vector Mode) x 1 0 Table 2-3: Mode Pin Settings (x: does not care) 2.11 Not Connected Pins In default state after power-on reset usually the GPIO pins are in high-z state. If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect at least a 2k resistor to each unused pins in pull-up or pull-down configuration. Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins. Concerning special use cases it is referred to chapter 4 for how to proceed with unused (not connected) pins. 2.12 Debug Interface connection Debugging is only supported by the 50 Ohm single-wire debug system, which is shared with mode pin „DEBUGIF‟. Concerning current limitation by an external resistor on programming tool side and maximum clamping current/structure at the „DEBUGIF‟ pin specified values must be taken out of data sheet. VCC MCU R2 ECU D2 Debug Connector DEBUGIF R1 D1 GND GND L2 L1 Figure 2-4: How to connect debug system with programming connector (R1= 43 R, R2 = 10 k, D1 e.g. HZM6.2Z4MFA-E, D2 schottky diode e.g. BAS40, Debug connector: SMA 50R connector for development target boards.) Item Specification MDI bus maximum communication speed 50Mbps (from MCU to SPEED-BOX) Does not depend on cable* length. (* cable between SPEED-BOX and ECU) MDI bus maximum communication speed Cable* length 2m or less : 25Mbps (from SPEED-BOX to MCU) Cable* length 5m or less : 12.5Mbps Cable* length 10m or less : 6.25Mbps (* cable between SPEED-BOX and ECU) L1 wiring length L2 wiring length As short as possible, keep less than 5 cm. Less than 15 cm. Table 2-4: SPEED-BOX general specifications , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 11 A P P L I C A T I O N N O T E Please check for detailed OCDS layout design rules of the MB2100-01-E (see chapter 5 ) and the chapter „On Chip Debugger: OCD‟ of the hardware manual. 12 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 3 Layout and Electromagnetic Compatibility THIS CHAPTER GIVES SOME TIPS FOR LAYOUT DESIGN 3.1 General To avoid ESD problems and noise emission of the system some rules for the layout design have to be observed. The most critical point is the C pin because this is the connection to the internal 1.2 V supply for the MCU core. Thus two decoupling capacitors have to be placed very near to this pin. Also the ground and Vcc routing has to be done carefully. Vcc lines should be routed in star shape. We recommend a Vss ground plane on the mounting side just under the MCU. For both Vcc and Vss only one connection to the rest of the circuit should be done, otherwise noise is carried-over from and to the MCU. This one connection should be used for power supply filtering (PI-Filter with ferrite). Decoupling capacitors (DeCaps) have to be placed as near as possible to the related pins. If they are placed too far away, their functionality becomes useless. If possible all decoupling capacitors should be placed on the same mounting side as the MCU; otherwise the DeCaps could be placed on bottom layer below the MCU. PI-Filter prevents EMI from radiating from power supply planes. Keep maximum distance between IN and OUT capacitor to avoid noise coupling at PI-Filter. If crystals are used, they have to be placed as near as possible to the X1(A) pins, output of the inverter. The feedback resistor of oscillator circuit (typ. 1Mohm) is already implemented internally. The evaluation of crystal/resonator and load capacitor must be tested by the related crystal vendor by crystal matching test. 3.2 Power supply Pins The following table shows the EMC critical pins and gives short information about how to connect them. Pin name Function VCC Dedicated power supply pins for IO buffer and crystal oscillator. VCC5* VCC3* VCCE* DVCC*, DVSS* *Only for MB91570/590 series. Dedicated power supply pins for IO buffer and crystal oscillator. *Only for MB91590 series. Power supply pins for 3V3 IO buffer. *Only for MB91570 series. Power supply pins for 3V3 IO buffer. *Only for MB91570/590 series. Power supply pins for high current output buffer pins. VSS Dedicated power supply (0V) pins. (IO buffer, MCU core and crystal oscillator) AVCCn Dedicated power supply pins for the AD-converter (unit n). AVRHn / AVRLn Dedicated positive/negative reference voltage pin for the AD-converter (unit n). AVSSn Dedicated power supply pin (0V) for the AD-converter (unit n). C Dedicated power supply pin for the internal power supply regulator (used to supply the MCU core). External capacitor connected to this pin is required. *Only for MB91590 series. C_1*, C_2*, C_3* Dedicated power supply pins for the internal power supply regulator (used to supply the MCU core). External capacitors connected to these pins are required. Please refer to datasheet “C Pin Connection Diagram” reference for further information. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 13 A P P L I C A T I O N N O T E Table 3-1: Power Supply pins in use 3.3 Oscillator Pins The following table shows the oscillator pins and gives short information about how to connect them. Pin name Function X0, X0A Oscillator input, if not used so shall be connected with pull-up or pull-down resistor (see please DS) *Only for devices with subclk. Oscillator output, the crystal and load capacitor must be connected with shortest distance and without X1*, X1A* any vias. If not used so shall be open Table 3-2: Oscillator pins in use 3.4 Power Line Routing In general the Vcc and Vss lines should not be routed in “chains”, but in “star shape”. For two layers board the Vss is recommended as ground plane which covers the chip package, and is connected in one point to Vss of the whole circuit to avoid a ground loop. Below is a principal example of a bad and a good power line routing: Figure 3-1: Example of bad vs. good power line routing For 4 and more layers PCB the Vcc and Vss should routed as a plane in the inner layers of PCB. Concerning the layer stack the several Vdd power supply planes should be not overlapped in parallel layers to avoid noise coupling. Recommendation for good EMC behaviour: 14 CONFIDENTIAL Use 4 layer or 6 layers PCB Use power supply planes (ground and power) in the inner-layer of PCB layer stack Reduce the distance between the power planes (low impedance) One or two decoupling capacitor close to each VCC pad/pair to adjacent VSS-pad/pair (route under). mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Use capacitor groups to match frequency behaviour of power supply decoupling. The decoupling capacitors can have values between 1nF and 10uF. Use ferrite filter for each power domain Split the used I/O signals in separate layer for low / high speed, and digital / analog signal types Below is an example for PCB layer stack: BAD crosstalk between different power supply planes high speed signals GND AVcc Vcc low speed signals GOOD separation of power supply planes for low EMC requirements high speed signals GND Avcc / Vcc low speed signals Figure 3-2: Example of PCB layer stack. 3.5 Power Supply Decoupling DeCaps for power supply have to be placed within the “current flow”. Otherwise they are senseless, because then their function become inoperable. The following graphic illustrates this: Figure 3-3: Power supply decoupling caps placement. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 15 A P P L I C A T I O N N O T E CB Usually the noise current should flows thought the soldering pad of decoupling capacitor C B. The following routing and placement for single-side assembled boards is recommended: VCC MCU VSS L1 (MCU) L2 (GND) L3 (VCC) L4 Figure 3-4: Power supply decoupling on single-side assembled boards The following routing and placement for multi layer PCB is recommended. Note that despite the capacitor is placed on the opposite side as the MCU, this solution is the best for high-density board assembly. CB VCC MCU VSS L1 (MCU) L2 (GND) L3 (VCC) L4 L4 L3 (VCC) L2 (GND) L1 (MCU) Figure 3-5: Power supply decoupling on double-side assembled boards 3.6 Recommended Power Supply Circuit To meet EMC requirements for the target board a noiseless supply is necessary. Therefore the supply should be filtered as shown in Figure 3-6: Principal Supply circuit. Switched IO pins like stepper motor controller or external bus interface can generate spikes on the supplies. These are difficult to filter using capacitors only. A series inductor (ferrite, e.g. WE742792022) is therefore recommended, as shown. 16 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E MCU Close to MCU pins Vcc C* 100nF X7R 5V GND GND L Vcc 100nF X7R 10uF 10uF GND GND C* GND GND 5V L AVcc GND R2* 10uF 10uF 100nF X7R GND C* GND *R2 (e.g. 10R) : Optional GND AVRH 100nF X7R *C (e.g. 1nF) : Optional C* GND GND AVSS VSS GND Figure 3-6: Principal Supply circuit 3.7 Reset circuit All hard reset events are extended by the hard reset extension circuit to guarantee the stabilization of the Low Voltage Detector (LVD) and complete reset of the device before program execution starts. The reset signal at RSTX pin goes through a noise filter to avoid any spike on the reset input. Please note there are two types of reset level (RST and INIT). , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 17 A P P L I C A T I O N N O T E Figure 3-7: Block diagram of reset extension circuit Please see also the datasheet, chapter “External reset timing” of related MCU series. Table 3-3: External reset timing Figure 3-8: External reset timing 18 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Figure 3-9: Block diagram of reset extension circuit , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 19 A P P L I C A T I O N N O T E 3.8 Quartz Crystal Placement and Signal Routing The feedback resistor (Rf) of the oscillator circuit is already inside of MCU device. The value of both load capacitors (C1, C2) should be determined with crystal matching test. The crystal matching test must be done by the crystal manufacturer based on the target board. As a result of crystal test maybe will be needed a damping resistor (Rd). MB91F52x X0 Inverter Vss C2 Rf 10p 4MHz C1 10p Rd 0R X1 Figure 3-10: Principle oscillator circuit. Figure 3-11: Principal oscillator circuit and startup sequence As you can see in Figure 3-12 the routing of these components is very important in order to reduce EMI effects. These components have to be placed on the same layer as the MCU. The connection of C1 and C2 to the Vss pin must be routed in a star way and so close as possible. The only vias should be placed to connect this ground star routing to the ground plane in other layer, never use vias to connect these components with the corresponding MCU pins. 20 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E DeCap CB on backside Vias to ground plane on inner layers Vias to Vcc plane on inner layers Vcc X1 X0 Vss CB Ground plane on inner layers Rd C1 C2 SMD Quartz Crystal Figure 3-12: Layout example for crystal oscillator circuit MB91F52x C3* X0 C1 Inverter C2 Rd 0R C4* CL Rf 4MHz X1 (C1 C3 ) (C2 C4 ) (C1 C3 ) (C2 C4 ) Equation 3-1 : CL calculation with stray capacitance of C3*,C4* : Stray capacitance of PCB PCB. Figure 3-13: Stray capacitance of PCB For a proper performance of the oscillator circuit it is necessary to match the load capacitors (C1, C2) with the crystal when the MCU, PCB or crystal are replaced for a different one. As a result of this matching test the value of CL is provided and then the calculation of C1 and C2 can be done using the Equation 3-1. 3.9 Test points The FR81S devices support several clock output functions for failure analysis in development, mass production or in the field. MONCLK out could be used e.g. for clock calibration of main or sub oscillator. Figure 3-14 : MONCLK internal clock select and prescaler. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 21 A P P L I C A T I O N N O T E Figure 3-15: Supported output functions for test purposes 3.10 Other documents For further detailed information please refer to the application notes on the web page 22 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 4 Port Input / Unused Pins / Latch-up HOW TO CONNECT INPUT PORT PINS AND HOW TO PROCEED WITH UNUSED PINS 4.1 Port Input / Unused Pins It is strongly recommended not to leave Input Pins unconnected. In this case those pins can enter a so-called floating state. This can cause a high ICC current, which is adverse to low power modes. Also damage of the MCU can happen. Use the internal pull-up/down resistors, if the port provides such function. If not, use external pull-up or pull-down resistors to define the input-level. If both solutions are not possible, set the Port Pin to Output. Never connect a potential divider with almost same resistor values. Figure 4-1: Principal using of input circuit to avoid latch-up or leak current Be careful with connection of input pins to other devices, which can go into High-Z states. Always use pull-up or pull-down resistors in this case. Outputs from external circuits should always be connected via a serial resistor to a MCU input pin. Debouncing and decoupling capacitors should always be chosen as smallest as possible. Please refer to chapter 4.2. All pins are set to input HiZ after its power-on default. Therefore set unused pins to input with internal pull-up/down resistor, or provide them with pull-up or pull-down resistors. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 23 A P P L I C A T I O N N O T E Do not connect any input ports directly to VCC or VSS (GND)! Always use pull up or down resistors (2k … 10k Ohms). If available it is possible to use the internal pull up or pull down resistors as well. Please note the value internal resistors can be 20k … 100k depends on the device and temperature. 4.2 Latch-up consideration (switch) Be careful with external switches to VCC or ground together with debouncing capacitors connected to port pins. A usual configuration is shown in the following schematic: Figure 4-2: Usual configuration switch. RPD is a pull-down resistor and CBD a debouncing capacitor. If the switch SW is open, a “0” is read from the port pin Pxy. If the switch is closed the input changes to “1”. From the physical aspect, it has to be considered, that the switch is often placed in distance to the MCU by cable, wire, or circuit path. The longer the circuit path is the higher will be its inductivity L X (and capacity CX). An equivalent circuit diagram looks like the following illustration: Figure 4-3: Usual configuration switch, equivalent circuit. 24 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E By closing the switch SW at time t0 the following voltage can be measured at point (A): Figure 4-4: Signal rise on switch closing (Point A). But at the port pin Pxy on point (B) the following voltage can be measured: Figure 4-5: Signal rise on switch closing (Point B). By closing the switch SW the circuit becomes a parallel oscillator with the wire-inductivity LX, the debouncing capacity CX and the damping RPD of the pull-down resistor (Assume the power supply to be ideal, i.e. it has no internal resistance): Figure 4-6: Equivalent circuit on switch closed. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 25 A P P L I C A T I O N N O T E Because RPD is often chosen high (> 50 K Ohms), its damping effect is weak. This (weakly) attenuated oscillator causes voltage overshoots on the port pin, drawn in red in the illustration below: Figure 4-7: Signal on the pin. These overshoots may cause an internal latch-up on the port pin, because the internal clamping diode connected to VDD becomes conductive. Similar is the effect, if the switch SW is opened. In this case there are under shoots on the port pin. The frequency of the oscillation can be calculated by fOSC 1 2 LX CDB Equation 4-1 : Oscillation frequency. The inductivity LX is the unknown value and depends on the PCB, its routing, and the wire lengths. There are two counter measurements to prevent from latch-up. One solution is to decrease the capacity of the debouncing capacitor. This increases the oscillation frequency, and the over-all energy of the overshoots is smaller. Figure 4-8: Signal on the pin with a large capacity. Figure 4-9: Signal on the pin with a small capacity This solution has two disadvantages: First the debouncing effect decreases and second, there is no guarantee, that the latch-up condition is eliminated. A better solution is to use a series resistor at the port pin like in the following schematic: 26 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Figure 4-10: Series resistor. The series resistor RS reduces the amplitude of the oscillation and decreases the voltage offset at first. The resistor must not be chosen too high, so that the port pin input voltage VP is within the positive CMOS/TTL/Automotive level. Figure 4-11: Reduction of the signal on the pin due to the series resistor. 4.3 5V tolerant Input pins In case of using of MCU on 3V level and peripherals on 5V level of power supply the ESD please note the influence of ESD clamping structure of usual GPIO pin. +3V MCU +3V +5V VCC VCC Peripheral +5V VCC VCC MCU Peripheral 5V tolerant input IN VSS IN OUT VSS Figure 4-12: Standard IO VSS OUT VSS Figure 4-13: 5V tolerant IO For 5V tolerant IO, the diode is not attached to the Pch side. It is a protection circuit in the parasitic bipolar and the diode to VSS. For the reason, clamp current cannot be specified in the DS for such kind of input pins. 5V tolerant inputs are e.g. for MB91F52x: P035, P041, P093, P122. Please see also the note *6 in the DS “ELECTRICAL CHARACTERISTICS – Maximum clamp current”. The current limitation with series resistor for + B signal is input is not possible for a 5V tolerant input. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 27 A P P L I C A T I O N N O T E 5 Flash Programming Connection THIS CHAPTER PROGRAMMING SHOWS WHICH CONNECTIONS ARE NEEDED FOR 5.1 Overview There are three different ways of programming the internal flash memory of this series. Serial programming via Uart0 Serial programming via MDI interface Parallel programming interface. 5.2 Serial programming via UART0 In order to program the internal memory flash of the MCU via Uart0, the only needed part is a cable to connect the PC with the MCU Usart0 module, to achieve that nowadays you can do it in different ways; using a regular serial cable if a DB9 serial connector is present in the computer or using a more modern USB cable (i.e. FTDI: TTL-232R http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm). With the USB cable the achieved baud rate is higher due to the higher speed of USB communication. 5V Vcc 100k AVcc AVRH Avss/AVRL SOT0 SIN0 TTL-232R X0A 32.768kHz USB 12p RSTX MB91F520 12p 2k RESET 1n X1A 5V X0 10p X1 C VSS 2K7 2K7 4MHz FTDI: TTL-232R 2K7 10p P006 MD0 MD1 4u7 Figure 5-1: Principle schematic for serial programming via Usart0 (with USB cable) To enable the serial programming using this method, you have to configure the Mode pins in an appropriate way (see Figure 5-1) according to the Table 2-3. The setting of the Mode pins can be done automatically by the programming system as you can see in the Figure 5-2, using only one signal connected to pin MD0, inverting MD1 and a pull-up resistor on the pin P006. 28 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N Flash Programming System N O T E ECU MCU R5 R4 R3 VCC SOT0_0 R11 SIN0_0 R6 R10 R7 Closed Serial Programming Mode Open User/Run Mode T1 P006 MD1 GND MD0 R8 RSTX R9 Reset GND GND GND C1 GND Figure 5-2: Principle schematic for serial programming via Usart0. The software used for flash programming of this MCU series is FR Spansion Serial Programmer tool. You can see a snapshot in the Figure 5-3. (Visit http://www.spansion.com/Support/microcontrollers/developmentenvironment/Pages/mcu-agreement.aspx for further information) Figure 5-3: Snapshot of the FR program used for flash programming via Usart0. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 29 A P P L I C A T I O N N O T E 5.3 Serial programming via MDI interface A suitable way of programming and debugging is the MDI interface using only one signal (pin Debug I/F) through the MB2100-01-E debugger. The MB2100-01-E debugger is connected to the host computer with an USB cable and to the target PCB with a single wire coaxial. OCDU is the device built-in debug support unit that provides the on-chip debug function in FR81. OCDU provides the basic debugger functions (CPU execution/break control, CPU register/memory/IO access), small-scale debug support functions (event, execution time measurement, trace, etc.), and security function. Figure 5-4: Connection of the MB2100-01-E with the host computer and target board. Figure 5-5: Picture of the MB2100-01-E. 30 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N ECU N O T E R2 VCC Debug Connector MCU D2 R1 DEBUGIF D1 GND GND Figure 5-6: Electronic components needed to protect the Debug I/F pin. (R1= 43 R, R2 = 10 k, D1 e.g. HZM6.2Z4MFA-E, D2 schottky diode e.g. BAS40, Debug connector: SMA 50R connector for development target boards.) 5.4 Parallel programming interface In case of using Flash security and unknown key or if the OCD interface function is disabled, the Flash may be erased only by the parallel programming mode. The parallel programming is supported by GALEP-5D: Figure 5-7: Parallel programming with GALEP-5D Further information about GALEP-5D can be found on the web page: http://www.conitec.net/english/galep5d.php , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 31 A P P L I C A T I O N N O T E 5.5 Security function This MCU series has a security function to impede improper access to the internal flash. To enable this function the user has to write in a specific flash memory location a password and a flash security code. From then security is turned on and access restrictions are imposed on subsequent accesses to flash memory. Once security has been turned on, the security is not turned off unless the entire flash memory area is erased (using serial or parallel programming method). To avoid not authorised access to memory during debugging the user is forced to enter the same password previously written in flash memory. Once authentication by password of on-chip debugger (OCD) is completed, you can read the content of flash memory from external by using OCD. The debug security area is allocated at 30 bytes of built-in flash start address +4 to +33. (For further information please go to the Hardware Manual of this series) 32 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 6 Reset Behaviour of IO port pins THIS CHAPTER SHOWS THE BEHAVIOUR OF IO-PORT DURING AND AFTER RESET During the power-on or RSTX reset state the GPIO port pins are going to HiZ and the inputs are disabled to prevent the leakage by any floating pin. After release of reset the IO-ports will be set to initial value (see also related DS of FR81S series) Pin Function Initial state Running X0/X1 Main oscillator X0A/X1A Sub oscillator Running Gpio port pins GPIO Input disabled HiZ Table 6-1 : Power-On/RSTX reset state GPIO initial state If some external bus pins should be used as GPIO than do not use any address or bus control lines as input, because these lines are driven as output high. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 33 A P P L I C A T I O N N O T E 7 Appendix 7.1 References Related documents for further information are listed in the table below: Ref. # Document file name Description 1 MB91520-MN705-00010-3v0-E.pdf FR81S MB91520 Series Hardware Manual 2 MB91F526L-DS705-00011-1v0-E.pdf FR Family FR81S, MB91520 Series datasheet 3 MB91590-MN705-00019-0v01-E.pdf FR81S MB91590 Series Hardware Manual 4 MB91590_DS705-00010-2v1-E.pdf FR Family FR81S, MB91590 Series datasheet 34 CONFIDENTIAL mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E 8 MAJOR CHANGES IN THIS EDITION Page / Section Chapter Change Results Revision 1.0 - - Initial release Revision 1.1 RSTX and NMIX input correction RSTX and NMIX input Revision 1.2 - - obsolete issue removed - New: 5V-tolerant IOs Revision 1.3 Ch. 4.3 , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 35 A P P L I C A T I O N N O T E MN706-00032-1v3-E Spansion Application Note FR81S Family 32-BIT MICROCONTROLLER HARDWARE SETUP January 2013 Rev. 1.3 Published: Edited: 36 CONFIDENTIAL Spansion Inc. Marketing Communications Dept. mcu-an-381008-e-v13-fr81s_hardware_setup, January 16, 2014 A P P L I C A T I O N N O T E Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. ® ® ® TM Copyright © 2013 Spansion Inc. All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse , TM ORNAND and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. , January 16, 2014, mcu-an-381008-e-v13-fr81s_hardware_setup CONFIDENTIAL 37