2559 Protected Quad Power Driver Last Time Buy This part is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Date of status change: November 1, 2010 Deadline for receipt of LAST TIME BUY orders: April 30, 2011 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 2559 Protected Quad Power Driver Features and Benefits Description ▪ 700 mA output current per channel ▪ Independent overcurrent protection for each driver ▪ Thermal protection for device and each driver ▪ Low output-saturation voltage ▪ Integral output flyback diodes ▪ TTL and 5 V CMOS-compatible inputs Providing improved output current limiting, the UDK, UDN, and UDQ2559B, EB, and LB quad power drivers combine AND logic gates and high-current bipolar outputs with complete output protection. Each of the four outputs sink 700 mA in the on state. The outputs have a minimum breakdown voltage (load dump) of 60 V and a sustaining voltage of 40 V. The inputs are compatible with TTL and 5 V CMOS logic systems. Packages: 16-pin DIP with exposed thermal tabs (B package) 28-pin PLCC (Package EB) Overcurrent protection for each channel has been designed into these devices and is activated at approximately 1 A. It protects each output from short circuits with supply voltages up to 25 V. When an output current trip point is reached, that output stage is driven linearly resulting in a reduced output current level. If an over-current or short-circuit condition continues, the thermal-limiting circuits will first sense the rise in junction temperature and then the rise in chip temperature, further decreasing the output current. Under worst-case conditions, these devices will tolerate short circuits on all outputs, simultaneously. These devices can be used to drive various loads including incandescent lamps (without warming or limiting resistors) or inductive loads such as relays, solenoids, or dc stepping motors. 16-pin SOICW with internally fused pins (LB package) The packages offer fused leads for enhanced thermal dissipation. Package B is a 16-pin power DIP with exposed tabs, EB is a 28-lead power PLCC, and LB is a 16-lead power wide-body SOIC for surface-mount applications. They are lead (Pb) free with 100% matte tin leadframe plating. Not to scale Functional Block Diagram (1 of 4 Channels) VCC K OUTN ENABLE INN Thermal Limit << 1Ω 29317.14L 2559 Protected Quad Power Driver Selection Guide Part Number Package Ambient Temperature (°C) Packing UDN2559B-T 16-pin DIP, exposed tabs 25 per tube UDN2559EBTR-T 28-lead PLCC 800 per reel UDQ2559LBTR-T 16-lead SOIC 1000 per reel UDK2559B-T 16-pin DIP, exposed tabs 25 per tube UDK2559EBTR-T 28-lead PLCC 800 per reel UDK2559LBTR-T 16-lead SOIC 1000 per reel –20 to 85 –40 to 85 –40 to 125 Absolute Maximum Ratings Characteristic Supply Voltage Input Voltage Range Output Voltage Overcurrent-Protected Output Voltage Output Current Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol Notes VCC Rating Units 7 V VIN, VEN 7 V VOUT 60 V 25 V 1.0 A Range K –40 to 125 ºC Range N –20 to 85 ºC Range Q –40 to 85 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC VOUT(P) IOUT TA Outputs are peak current limited at approximately 1.0 A per driver. See Circuit Description and Application section for further information. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 2559 Protected Quad Power Driver Pin-out Diagrams Package B Package LB OUT4 1 16 IN 4 K 2 15 IN3 OUT3 3 14 ENABLE GROUND 4 13 GROUND GROUND 5 12 GROUND OUT2 6 11 V CC K 7 10 OUT1 8 9 OUT 4 1 16 IN 4 K 2 15 IN 3 OUT 3 3 14 ENABLE GROUND 4 13 GROUND GROUND 5 12 GROUND OUT 2 6 11 V CC IN 2 K 7 10 IN 2 IN 1 OUT 1 8 9 IN 1 Dwg. PP-017-1 Dwg. PP-017-6 IN 1 IN 2 ENABLE 28 27 26 OUT1 2 NO CONNECTION K 3 1 OUT2 4 Package EB NC 25 6 24 7 23 8 22 9 21 10 20 11 19 GROUND GROUND VCC 13 14 15 16 17 18 K OUT 4 NO CONNECTION IN 4 IN 3 SUPPLY NC 12 GROUND 5 OUT 3 GROUND Dwg. PP-019-1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 2559 Protected Quad Power Driver Thermal Characteristics Characteristic Symbol Test Conditions* Value Units 2 Package Thermal Resistance RθJA Package B, 2-layer PCB with 0.5 in. exposed copper each side 43 ºC/W Package EB, 1-layer PCB with copper limited to solder pads 36 ºC/W Package LB, 1-layer PCB with copper limited to solder pads 90 ºC/W *Additional thermal information available on the Allegro website PD = (VOUT1 x IOUT1 x dc) + … + (VOUTn x IOUTn x dc) + (VCC x ICC) = (TJ - TA)/RJA Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Copyright © 1995, 2002 Allegro MicroSystems, Inc. 4 2559 Protected Quad Power Driver ELECTRICAL CHARACTERISTICS at TA = +25°C (prefix ‘UDN’) or over operating temperature range (prefix ‘UDK’ or ‘UDQ’), VCC = 4.75 V to 5.25 V Limits Characteristic Output Leakage Current Symbol ICEX Test Conditions Min. Typ. Max. Units VOUT = 50 V, VIN = 0.8 V, VEN = 2.0 V — <1.0 100 μA VOUT = 50 V, VIN = 2.0 V, VEN = 0.8 V — <1.0 100 μA Output Sustaining Voltage VOUT(SUS) IOUT = 100 mA, VIN = VEN = 0.8 V 40 — — V Output Saturation Voltage VOUT(SAT) All Devices, IOUT = 100 mA — — 300 mV All Devices, IOUT = 400 mA — — 500 mV B or EB package only, IOUT = 600 mA — — 700 mV — 1.0 — A Over-Current Trip Input Voltage Input Current Total Supply Current* Clamp Diode Forward Voltage Clamp Diode Leakage Current Turn-On Delay Thermal Limit ITRIP Logic 1 VIN(1) or VEN(1) 2.0 — — V Logic 0 VIN(0) or VEN(0) — — 0.8 V Logic 1 VIN(1) or VEN(1) = 2.0 V — — 40 μA Logic 0 VIN(0) or VEN(0) = 0.8 V — — -10 μA All Outputs ON, VIN = VEN = 2.0 V — — 80 mA All Outputs OFF — — 5.0 mA IF = 1.0 A — — 1.7 V IF = 1.5 A — — 2.1 V VR = 50 V, D1 + D2 or D3 + D4 — — 50 μA tPHL IOUT = 500 mA — — 20 μs tPLH IOUT = 500 mA — — 20 μs — 165 — °C ICC VF IR TJ Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified terminal. As used here, -100 is defined as greater than +10 (absolute magnitude convention) and the minimum is implicitly zero. * All inputs simultaneously, all other tests are performed with each input tested separately. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 2559 Protected Quad Power Driver TYPICAL OUTPUT CHARACTERISTIC CIRCUIT DESCRIPTION AND APPLICATION INCANDESCENT LAMP DRIVER High incandescent lamp turn-ON/in-rush currents can contribute to poor lamp reliability and destroy semiconductor lamp drivers. Warming or currentlimiting resistors protect both driver and lamp but use significant power either when the lamp is OFF or when the lamp is ON, respectively. Lamps with steady-state current ratings up to 700 mA can be driven by these devices without the need for warming (parallel) or current-limiting (series) resistors. When an incandescent lamp is initially turned ON, the cold filament is at minimum resistance and would normally allow a 10x to 12x in-rush current. With these drivers, during turn-ON, the high in-rush current is sensed by the internal low-value sense resistor. Drive current to the output stage is then diverted by the shunting transistor, and the load current is momentarily limited to approximately 1.0 A. During this short transition period, the output current is reduced to a value dependent on supply voltage and filament resistance. During lamp warmup, the filament resistance increases to its maximum value, the output stage goes into saturation and applies maximum rated voltage to the lamp. TYPICAL OUTPUT BEHAVIOR INDUCTIVE LOAD DRIVER Bifilar (unipolar) stepper motors, relays, or solenoids can be driven directly. The internal flyback diodes prevent damage to the output transistors by suppressing the high-voltage spikes that occur when turning OFF an inductive load. For rapid current decay (fast turn-OFF speeds), the use of Zener diodes will raise the flyback voltage and inprove performance. However, the peak voltage must not exceed the specified minimum sustaining voltage (VSUPPLY + VZ + VF VOUT(SUS)). FAULT CONDITIONS In the event of a shorted load, the load current will attempt to increase. As described above, the drive current to the affected output stage is reduced, causing the output stage to go linear, limiting the peak output current to approximately 1 A. As the power dissipation of that output stage increases, a thermal gradient sensing circuit will become operational, further decreasing the drive current to the affected output stage and reducing the output current to a value dependent on supply voltage and load resistance. Continuous or multiple overload conditions causing the chip temperature to reach approximately 165°C will result in an additional reduction in output current to maintain a safe level. If the fault condition is corrected, the output stage will return to its normal saturated condition. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 2559 Protected Quad Power Driver B Package, 16-pin DIP with internally fused pins 4, 5, 12, and 13 and external thermal tabs 19.05±0.25 16 +0.10 0.38 –0.05 +0.76 6.35 –0.25 +0.38 10.92 –0.25 7.62 A 1 2 5.33 MAX +0.51 3.30 –0.38 1.27 MIN 2.54 +0.25 1.52 –0.38 For Reference Only (reference JEDEC MS-001 BB) Dimensions in inches, metric dimensions (mm) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.46 ±0.12 EB Package, 28-pin PLCC with internally fused pins 5 through 11 and 19 through 25 12.45±0.13 11.51±0.08 2 1 0.51 28 A 12.45±0.13 5.21±0.36 11.51±0.08 5.21±0.36 0.51 MIN 0.74±0.08 +0.20 4.37 –0.18 28X 0.10 C 0.43±0.10 1.27 5.21±0.36 5.21±0.36 SEATING PLANE C For Reference Only (reference JEDEC MS-018 AB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 2559 Protected Quad Power Driver LB Package, 16-pin SOICW with internally fused pins 4 and 5, and 12 and 13 10.30±0.20 4° ±4 16 1.27 0.65 16 +0.07 0.27 –0.06 10.30±0.33 7.50±0.10 9.50 A +0.44 0.84 –0.43 2.25 1 2 1 2 0.25 B 16X SEATING PLANE 0.10 C 0.41 ±0.10 1.27 C PCB Layout Reference View SEATING PLANE GAUGE PLANE 2.65 MAX 0.20 ±0.10 For Reference Only Pins 4 and 5, and 12 and 13 internally fused Dimensions in millimeters (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-16M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©1995-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8