1.9 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16802-2E
32-bit Microcontroller
CMOS
FR60 MB91314A Series
MB91F314A
■ DESCRIPTION
The FR* family is a line of single-chip microcontrollers based on the 32-bit high-performance RISC CPU while
integrating a variety of I/O resources for embedded control applications which require high-performance, highspeed CPU processing.
MB91314A series contains multiple channels of data slicer and communication macros, best suited for embedded
applications such as TV control.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ FEATURES
1. FR CPU
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32-bit RISC, load/store architecture with a five-stage pipeline
Operating frequency 33 MHz [PLL used : Oscillation frequency 16.5 MHz : Doubled]
16-bit fixed length instructions (basic instructions), 1 instruction per cycle
Instruction set optimized for embedded applications : Memory-to-memory transfer, bit manipulation, barrel shift
instructions etc.
Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store
instructions
Register interlock functions : Facilitating coding in assemblers
On-chip multiplier supported at the instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt (PC, PS save) : 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
Instruction prefetch feature added by a 4-word queue in the CPU
Instruction set compatible with FR family
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
MB91314A Series
2. Simple External Bus interface
Capable of functioning 8-bit or 16-bit multiplex bus by setting with program
• Operating frequency : Max 16.5 MHz
• 8/16-bit data/address multiplex I/O
• Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
3. Internal Memory
MB91F314A : 512 Kbytes Flash, RAM 32 Kbytes
4. DMAC (DMA Controller)
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5 channels
Two forwarding factors (internal peripheral/software)
Addressing mode 20/24-bit address selection (increment/decrement/fixed)
Transfer modes (burst transfer/step transfer/block transfer)
Selectable transfer data size : 8, 16, or 32 bits
5. Bit Search Module (for REALOS)
Searches the location of the first bit of “1” or “0”, or first changing bit, from the MSB in a word
6. Reload Timer (Including 1 Channel for REALOS)
• 16-bit timer ch.6
• The internal clock is optional from 2/8/32 division
7. Multi function Serial Interface
• 11 channels
• Full duplex double buffer
• Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication,
clock synchronous communication (8.25 Mbps Max), I2C standard mode (100 kbps Max),
high-speed mode (400 kbps Max)
• Parity on/off selectable
• Baud rate generator per channel
• Abundant error detection functions are provided (parity, frame, and overrun)
• External clock can be used as transfer clock
• Ch.0 to ch.2 correspond to DMA transfer.
• Ch.0 to ch.2 have a pair of 16 bytes FIFO buffers for transmission and reception.
• I2C bridge feature (among channels 0, 1, and 2)
• SPI mode
8. Interrupt Controller
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A total of 24 external interrupt lines (external interrupt pins INT23 to INT0)
Interrupt from internal peripheral
Programmable 16 priority levels
Available for wakeup from STOP mode
(Continued)
2
DS07-16802-2E
MB91314A Series
9. A/D converter
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10-bit resolution, 10 channels
Successive approximation type : conversion time : About 8.0 µs
Conversion mode (Single-shot conversion mode, scan conversion mode)
Startup sources (software/external trigger)
10. PPG
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4 channels
16-bit down counter, 16-bit data register with cycle setting buffer
The internal clock is optional from 1/4/16/64 division
Support for automatic cycle setting by DMA transfer
Function for supporting remote control transmission
11. PWC
• 1 channel (1 input)
• 16-bit up counter
• Simple digital lowpass filter
12. Multi-function timer
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4 channels
Lowpass filter eliminating noise below a pre-set clock frequency
Capable of pulse width measurement using seven types of clock signals
Pin input event count function
Interval timer function using seven types of clock signals and external input clock
Internal HSYNC counter mode
13. Closed caption decoder feature
• 1 channel
• CC decoder function
• ID-1 (480i/480p) decoder function
14. Other interval timers
• Watch timer (32 kHz, Count up to 2 seconds)
• Watchdog timer
15. I/O port
Max 78 ports
(Continued)
DS07-16802-2E
3
MB91314A Series
(Continued)
16. Other features
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Internal oscillator circuit as a clock source
INIT is prepared as a reset terminal
Watchdog timer reset and software reset are available
Stop and sleep modes supported as low-power consumption modes
Gear function
• Built-in time base timer
• 5 V tolerant I/O (some pins)
• Package LQFP-120, 0.50 mm pitch, 16.0 mm × 16.0 mm
• CMOS technology (0.18µm)
• Power supply voltage 3.3 V ± 0.3 V, 1.8 V ± 0.15 V dual-power
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DS07-16802-2E
MB91314A Series
■ PIN ASSIGNMENT
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VDDE
P22/SCK0/SCL0 (I2C bridge)
P21/SOT0/SDA0 (I2C bridge)
P20/SIN0
P57/WR1
P56/WR0
P55/RD
P54/AS
P53/CS3/PPG3
P52/CS2/PPG2
P51/CS1/PPG1
P50/CS0/PPG0
P17/D15
P16/D14/SCK7/SCL7
P15/D13/SOT7/SDA7
P14/D12/SIN7
P13/D11/SCK6/SCL6
P12/D10/SOT6/SDA6
P11/D09/SIN6
P10/D08/SCK5/SCL5
P07/D07/SOT5/SDA5/INT15
P06/D06/SIN5/INT14
P05/D05/SCK4/SCL4/INT13
P04/D04/SOT4/SDA4/INT12
P03/D03/SIN4/INT11
P02/D02/SCK3/SCL3/INT10
P01/D01/SOT3/SDA3/INT9
P00/D00/SIN3/INT8
VDDI
VSS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VDDE
IBREAK
ICLK
ICS2
ICS1
ICS0
ICD3
ICD2
ICD1
ICD0
TRST
PC7/TRG1
PC6/TRG0
PC5/PPGB
PC4/PPGA
PC3
PC2/SCK9/SCL9
PC1/SOT9/SDA9
PC0/SIN9
PE7/SCK8/SCL8/INT7
PE6/SOT8/SDA8/INT6
PE5/SIN8/INT5
PE4/PPG3/INT4
MD2
MD1
MD0
VDDI
X0
X1
VSS
VSS
VDDC
VSSC
VIN
VCI
CPO
VDDP
VSSP
HSYNC
VDDE
VSS
AVSS
AVRH
AVCC
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
PE0/AN8/INT0
PE1/AN9/PPG0/INT1
PE2/PPG1/INT2/ATRG
PE3/PPG2/INT3
VDDE
INIT
X0A
X1A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
VDDI
P23/SIN1
P24/SOT1/SDA1 (I2C bridge)
P25/SCK1/SCL1 (I2C bridge)
P26/SIN2
P27/SOT2/SDA2 (I2C bridge)
P30/SCK2/SCL2 (I2C bridge)
P31/TOT0
P32/TOT1
P33/TOT2
P34/TIN0
P35/TIN1
P36/TIN2
P37/RIN
P40/TMO0/INT16
P41/TMO1/INT17
P42/TMO2/INT18
P43/TMO3/INT19
P44/TMI0/INT20
P45/TMI1/INT21/SIN10
P46/TMI2/INT22/SOT10/SDA10
P47/TMI3/INT23/SCK10/SCL10
P60/TOT3/TRG2
P61/TOT4/TRG3
P62/TOT5/RDY
P63/TIN3/CLK
P64/TIN4
P65/TIN5
VDDE
(FPT-120P-M21)
DS07-16802-2E
5
MB91314A Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O circuit type*
1
VSS
⎯
GND pin
2
VDDI
⎯
1.8 V power supply
3
P23
SIN1
D
P24
4
SOT1/SDA1
(I2C bridge)
6
SCK1/SCL1
(I2C bridge)
P26
SIN2
SOT2/SDA2
(I2C bridge)
D
9
10
11
12
13
14
15
SCK2/SCL2
(I2C bridge)
P31
TOT0
P32
TOT1
P33
TOT2
P34
TIN0
P35
TIN1
P36
TIN2
P37
RIN
TMO0
D
D
D
D
D
D
D
B
INT17
Multi function serial 2 serial data input pin
Multi function serial 2 serial data output pin
I2C data I/O pin
Multi function serial 2 serial communication clock I/O pin
I2C clock I/O pin
General-purpose I/O port
Output pin for reload timer
General-purpose I/O port
Output pin for reload timer
General-purpose I/O port
Output pin for reload timer
General-purpose I/O port
Event input pin for reload timer
General-purpose I/O port
Event input pin for reload timer
General-purpose I/O port
Event input pin for reload timer
General-purpose I/O port
PWC input pin
Multifunction timer output
External interrupt request input pin
P41
TMO1
General-purpose I/O port
General-purpose I/O port
INT16
17
Multi function serial 1 serial communication clock I/O pin
I2C clock I/O pin
General-purpose I/O port
L
P40
16
Multi function serial 1 serial data output pin
I2C data I/O pin
General-purpose I/O port
L
P30
8
Multi function serial 1 serial data input pin
General-purpose I/O port
L
P27
7
General-purpose I/O port
General-purpose I/O port
L
P25
5
Description
General-purpose I/O port
B
Multifunction timer output
External interrupt request input pin
(Continued)
6
DS07-16802-2E
MB91314A Series
Pin no.
Pin name
I/O circuit type*
P42
18
TMO2
General-purpose I/O port
B
INT18
TMO3
General-purpose I/O port
B
INT19
TMI0
General-purpose I/O port
B
INT20
TMI1
INT21
General-purpose I/O port
B
SIN10
22
General-purpose I/O port
TMI2
Multifunction timer input
B
General-purpose I/O port
TMI3
INT23
Multifunction timer input
B
P60
General-purpose I/O port
C
TRG2
General-purpose I/O port
C
TRG3
27
TOT5
General-purpose I/O port
C
Output pin for reload timer
RDY
External ready input pin
P63
General-purpose I/O port
TIN3
C
CLK
28
Output pin for reload timer
PPG trigger input
P62
26
Output pin for reload timer
PPG trigger input
P61
TOT4
External interrupt request input pin
Multi function serial 10 serial communication clock I/O pin
I2C clock I/O pin
SCK10/SCL10
TOT3
External interrupt request input pin
Multi function serial 10 serial data output pin
I2C data I/O pin
P47
25
External interrupt request input pin
Multi function serial 10 serial data input pin
SOT10/SDA10
24
Multifunction timer input
P46
INT22
23
Multifunction timer input
External interrupt request input pin
P45
21
Multifunction timer output
External interrupt request input pin
P44
20
Multifunction timer output
External interrupt request input pin
P43
19
Description
P64
TIN4
Event input pin for reload timer
External clock output pin
C
General-purpose I/O port
Event input pin for reload timer
(Continued)
DS07-16802-2E
7
MB91314A Series
Pin no.
29
Pin name
P65
TIN5
I/O circuit type*
C
Description
General-purpose I/O port
Event input pin for reload timer
30
VDDE
⎯
3.3 V power supply
31
VSS
⎯
GND pin
32
VDDC
⎯
Data slicer power supply
33
VSSC
⎯
Data slicer ground
34
VIN
N
Data slicer input
35
VCI
N
VCO control voltage input
36
CPO
N
Charge pump output
37
VDDP
⎯
Dot clock PLL power supply
38
VSSP
⎯
Dot clock PLL ground
39
HSYNC
M
Horizontal synchronous input
40
VDDE
⎯
3.3 V power supply
41
VSS
⎯
Ground pin
42
AVSS
⎯
Analog ground pin for A/D converter
43
AVRH
⎯
Analog reference power voltage input pin for A/D converter
44
AVCC
⎯
Analog power supply input pin for A/D converter
45
46
47
48
49
50
51
52
PD0
AN0
PD1
AN1
PD2
AN2
PD3
AN3
PD4
AN4
PD5
AN5
PD6
AN6
PD7
AN7
L
L
L
L
L
L
L
L
PE0
53
AN8
INT0
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
L
A/D converter analog input pin
External interrupt request input pin
(Continued)
8
DS07-16802-2E
MB91314A Series
Pin no.
Pin name
I/O circuit type*
PE1
AN9
54
PPG0
General-purpose I/O port
L
Output pin for PPG
External interrupt request input pin
PE2
General-purpose I/O port
INT2
B
ATRG
PPG2
Output pin for PPG
External interrupt request input pin
Trigger input pin for A/D converter
PE3
56
A/D converter analog input pin
INT1
PPG1
55
Description
General-purpose I/O port
B
INT3
Output pin for PPG
External interrupt request input pin
57
VDDE
⎯
3.3 V power supply
58
INIT
G
Initial reset pin
59
X0A
A
Sub clock input
60
X1A
A
Sub clock I/O
61
VSS
⎯
Ground pin
62
X1
A
Main clock I/O
63
X0
A
Main clock input
64
VDDI
⎯
1.8 V power supply
65
MD0
F
66
MD1
F
67
MD2
F
PE4
68
PPG3
69
70
71
General-purpose I/O port
B
Output pin for PPG
INT4
External interrupt request input pin
PE5
General-purpose I/O port
SIN8
B
Multi function serial 8 serial data input pin
INT5
External interrupt request input pin
PE6
General-purpose I/O port
SOT8/SDA8
B
Multi function serial 8 serial data output pin
I2C data I/O pin
INT6
External interrupt request input pin
PE7
General-purpose I/O port
SCK8/SCL8
B
INT7
72
Input pins for specifying the operating mode
PC0
SIN9
Multi function serial 8 serial communication clock I/O pin
I2C clock I/O pin
External interrupt request input pin
B
General-purpose I/O port
Multi function serial 9 serial data input pin
(Continued)
DS07-16802-2E
9
MB91314A Series
Pin no.
Pin name
I/O circuit type*
PC1
73
SOT9/SDA9
General-purpose I/O port
B
PC2
74
75
76
77
78
79
SCK9/SCL9
PC3
PC4
PPGA
PC5
PPGB
PC6
TRG0
PC7
TRG1
Description
Multi function serial 9 serial data output pin
I2C data I/O pin
General-purpose I/O port
B
Multi function serial 9 serial communication clock I/O pin
I2C clock I/O pin
B
General-purpose I/O port
B
B
B
B
General-purpose I/O port
Output pin for PPG
General-purpose I/O port
Output pin for PPG
General-purpose I/O port
PPG trigger input
General-purpose I/O port
PPG trigger input
80
TRST
G
81
ICD0
K
82
ICD1
K
83
ICD2
K
84
ICD3
K
85
ICS0
H
86
ICS1
H
87
ICS2
H
88
ICLK
H
Clock pin for development tool
89
IBREAK
I
Break pin for development tool
90
VDDE
⎯
3.3 V power supply
91
VSS
⎯
GND pin
92
VDDI
⎯
1.8 V power supply
P00
93
94
D00
SIN3
Reset pin for development tool
Data pin for development tool
Status pin for development tool
General-purpose I/O port
C
External address/ data bus I/O pin
Multi function serial 3 serial data input pin
INT8
External interrupt request input pin
P01
General-purpose I/O port
D01
External address/ data bus I/O pin
SOT3/SDA3
INT9
C
Multi function serial 3 serial data output pin
I2C data I/O pin
External interrupt request input pin
(Continued)
10
DS07-16802-2E
MB91314A Series
Pin no.
Pin name
I/O circuit type*
P02
General-purpose I/O port
D02
95
SCK3/SCL3
External address/ data bus I/O pin
C
INT10
D03
SIN4
General-purpose I/O port
C
INT11
97
General-purpose I/O port
D04
External address/ data bus I/O pin
C
P05
General-purpose I/O port
D05
External address/ data bus I/O pin
SCK4/SCL4
C
D06
SIN5
General-purpose I/O port
C
INT14
Multi function serial 5 serial data input pin
External interrupt request input pin
General-purpose I/O port
D07
External address/ data bus I/O pin
C
INT15
D08
General-purpose I/O port
C
External address/ data bus I/O pin
Multi function serial 5 serial communication clock I/O pin
I2C clock I/O pin
SCK5/SCL5
P11
D09
Multi function serial 5 serial data output pin
I2C data I/O pin
External interrupt request input pin
P10
General-purpose I/O port
C
External address/ data bus I/O pin
SIN6
Multi function serial 6 serial data input pin
P12
General-purpose I/O port
D10
103
External address/ data bus I/O pin
P07
SOT5/SDA5
102
Multi function serial 4 serial communication clock I/O pin
I2C clock I/O pin
External interrupt request input pin
P06
101
Multi function serial 4 serial data output pin
I2C data I/O pin
External interrupt request input pin
INT13
100
Multi function serial 4 serial data input pin
P04
SOT4/SDA4
99
External address/ data bus I/O pin
External interrupt request input pin
INT12
98
Multi function serial 3 serial communication clock I/O pin
I2C clock I/O pin
External interrupt request input pin
P03
96
Description
SOT6/SDA6
C
External address/ data bus I/O pin
Multi function serial 6 serial data output pin
I2C data I/O pin
(Continued)
DS07-16802-2E
11
MB91314A Series
Pin no.
Pin name
I/O circuit type*
P13
104
D11
General-purpose I/O port
C
P14
106
D12
General-purpose I/O port
C
Multi function serial 7 serial data input pin
P15
General-purpose I/O port
D13
C
D14
General-purpose I/O port
C
D15
C
P50
109
CS0
C
C
General-purpose I/O port
C
PPG2
CS3
General-purpose I/O port
C
PPG3
113
114
115
116
P54
AS
P55
RD
P56
WR0
P57
WR1
External chip select
Output pin for PPG
P53
112
External chip select
Output pin for PPG
P52
CS2
External chip select
General-purpose I/O port
PPG1
111
External address/ data bus I/O pin
Output pin for PPG
P51
CS1
General-purpose I/O port
General-purpose I/O port
PPG0
110
External address/ data bus I/O pin
Multi function serial 7 serial communication clock I/O pin
I2C clock I/O pin
SCK7/SCL7
P17
External address/ data bus I/O pin
Multi function serial 7 serial data output pin
I2C data I/O pin
P16
108
External address/ data bus I/O pin
SIN7
SOT7/SDA7
107
External address/ data bus I/O pin
Multi function serial 6 serial communication clock I/O pin
I2C clock I/O pin
SCK6/SCL6
105
Description
External chip select
Output pin for PPG
C
C
C
C
General-purpose I/O port
External address strobe output pin
General-purpose I/O port
External read strobe output pin
General-purpose I/O port
External data bus write strobe output pin
General-purpose I/O port
External data bus write strobe output pin
(Continued)
12
DS07-16802-2E
MB91314A Series
(Continued)
Pin no.
Pin name
P20
117
SIN0
I/O circuit type*
D
P21
118
SOT0/SDA0
(I2C bridge)
Description
General-purpose I/O port
Multi function serial 0 serial data input pin
General-purpose I/O port
D
P22
Multi function serial 0 serial data output pin
I2C data I/O pin
General-purpose I/O port
119
SCK0/SCL0
(I2C bridge)
D
Multi function serial 0 serial communication clock I/O pin
I2C clock I/O pin
120
VDDE
⎯
3.3 V power supply
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-16802-2E
13
MB91314A Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
Clock input
• Oscillation circuit
• Built-in feedback resistance
X0 pin − X1 pin : 1 MΩ
X0A pin − X1A pin : No
A
Standby control
P-ch
Digital output
Digital output
B
• CMOS level output
IOH = 4mA
• CMOS hysteresis input
VIH = 0.7 × VDDE
• With standby control
• 5 V tolerant
N-ch
Digital input
Standby control
P-ch
P-ch
Digital output
Digital output
C
• CMOS level output
IOH = 4 mA
• CMOS hysteresis input
VIH = 0.8 × VDDE
• With standby control
• With pull-up resistor (33 kΩ)
N-ch
Digital input
Standby control
(Continued)
14
DS07-16802-2E
MB91314A Series
Type
Circuit type
Remarks
P-ch
Digital output
Digital output
D
• CMOS level output
IOH = 4 mA
• CMOS hysteresis input
VIH = 0.8 × VDDE
• With standby control
• Without pull-up resistor
N-ch
Digital input
Standby control
• CMOS level input
• Without standby control
P-ch
F
N-ch
Digital input
P-ch
• CMOS hysteresis input
• With pull-up resistor
P-ch
G
N-ch
Digital input
• CMOS level output
P-ch
Digital output
H
Digital output
N-ch
(Continued)
DS07-16802-2E
15
MB91314A Series
Type
Circuit type
Remarks
• CMOS hysteresis input
• With pull-down resistor
• Without standby control
P-ch
I
N-ch
N-ch
Digital input
P-ch
Digital output
K
•
•
•
•
CMOS level output
CMOS level input
Without standby control
With pull-down resistor
Digital output
N-ch
N-ch
Digital input
P-ch
Digital output
• CMOS level output
CMOS hysteresis input
• With standby control
• Analog input with switch
Digital output
N-ch
L
Analog input
Control
Digital input
Standby control
(Continued)
16
DS07-16802-2E
MB91314A Series
(Continued)
Type
Circuit type
Remarks
• CMOS hysteresis input
• Without standby control
P-ch
M
N-ch
Digital input
• Analog pin
P-ch
N
N-ch
DS07-16802-2E
17
MB91314A Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VDDE or VDDI, or less than VSS is applied to input and
output pins or if an above-rating voltage is applied between VDDE or VDDI pins and VSS pin. A latch-up, if it
occurs, significantly increases the power supply current and may cause thermal destruction of an element. When
you use a CMOS IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
• About power supply pins
If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed
to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the
pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation,
prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current
rating. Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device
at the lowest impedance possible.
It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VDDE or VDDI and
VSS pin at circuit points close to the device as a bypass capacitor.
• About Crystal oscillator circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board
so that X0, X1, X0A and X1A pins the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground
are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• About Mode pins (MD0 to MD2)
These pins should be connected directly to VDDE or VSS pins. To prevent the device erroneously switching to
test mode due to noise, design the printed circuit board such that the distance between the mode pins and VDDE
or VSS pins is as short as possible and the connection impedance is low.
• Operation at start-up
Always use the INIT pin to perform a setting initialization reset (INIT) after turning on the power.
Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the stabilization wait
time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit (For
INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value).
• Source oscillation input at power on
When turning on the power, always input the clock for the duration of the oscillation stabilization delay time.
18
DS07-16802-2E
MB91314A Series
• Notes on the turning on/off VDDI pin (1.8 V internal power supply) and VDDE pin (3.3 V external pin power supply)
Do not apply only VDDE pin (external) voltage continuously (more than one minute) with VDDI pin (internal)
disconnected as it adversely affects the reliability of the LSI.
When VDDE pin (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal
state, for example, due to power supply noise.
Power on
VDD pin (internal) → Analog → VDDE pin (external) → signal
Power off
Signal → VDDE pin (external) → Analog → VDDI pin (internal)
When the power is turned on, the output pin may remain unstable until the internal power supply becomes stable.
• About the attention when the external clock is used
To use an external clock, in principle, supply the X1 (X1A) pin with a clock signal inverted in phase from the X0
(X0A) pin at the same time. However, in this case the stop mode (oscillator stop mode) must not be used. (This
is because the X1 (X1A) pin stops at “H” output in STOP mode.) At 12.5 MHz or less, the device can be used
only with the X0 (X0A) pin supplied with clock signals.
Using an External Clock (Normal Method)
X0, X0A
X1, X1A
MB91314A Series
The STOP mode (oscillation stop mode) cannot be used.
Using an External Clock (available at 12.5 MHz or less)
X0, X0A
Open
X1, X1A
MB91314A Series
Note : With respect to the X0 (X0A) signal, design X1 such that the delay is within 15 ns at 10 MHz.
• AVCC pin
The device has an internal A/D converter. A capacitor of approximately 0.1µF must be connected between the
AVCC pin and AVSS pin.
AVCC
0.1µF
MB91314A Series
DS07-16802-2E
AVSS
19
MB91314A Series
• Notes when the emulator is not used
To operate the evaluation MCU on the user system without connecting the emulator, treat each input pin on the
evaluation MCU connected to the emulator interface on the user system as shown below.
Emulator Interface Pin Treatment
Evaluation MCU pin name
Pin operation
TRST
Connected to the reset output circuit on the user system.
INIT
Connected to the reset output circuit on the user system.
Others
Open
• Note on operation with the PLL clock selected
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu Microelectronics will not guarantee results of operations if such failure
occurs.
20
DS07-16802-2E
MB91314A Series
■ RESTRICTIONS
1) Clock control block
Take the oscillation stabilization wait time during “L” level input to the INIT pin.
2) Bit Search Module
The bit search data register for 0-detection (BSD0), and bit search data register for 1-detection (BSD1), and
bit search data register for change point detection (BSDC) are only word-accessible.
3) I/O port
Ports are accessed only in bytes.
4) Low Power Consumption Mode
• To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the
timebase counter control register, TBCR) and be sure to use the following sequence:
(ldi
#value_of_standby, r0)
(ldi
#_STCR, r12)
stb
r0, @r12
// set STOP/SLEEP bit
ldub
@r12, r0
// Must read STCR
ldub
@r12, r0
// after reading, go into standby mode
nop
// Must insert NOP *5
nop
nop
nop
nop
• Please do not do the following when the monitor debugger is used.
• Setting of the break point to the above-mentioned instruction row.
• Execution of the step for the above-mentioned instruction row.
DS07-16802-2E
21
MB91314A Series
5) Notes on the PS register
Since some instructions write the information to PS register early time, the following exception operations may
cause a break to occur in an interrupt processing routine when using the debugger or the updating of the PS
flag. In either case, the processing is conducted properly again after return from an EIT, the operations before
and after the EIT are designed to perform as specified.
• The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S
instruction results in (a) acceptance of a user interrupt, (b) single-stepping, or (c) a break in response to a
data event or emulator menu:
(1) D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the D0/D1 flags are updated
back to the original value held before step (1).
• When a user interrupt source exists, executing either of the OR CCR, ST LIM and MOV Ri and PS instructions
to enable the interrupt results in the following operations:
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS registers are updated back to
the original value held before step (1).
6) Watchdog timer
The watchdog timer integrated in this model monitors the program to check that it delays a reset within a certain
period of time and, if the program runs out of control and fails to delay the reset, resets the CPU in place. Once
the watchdog timer is enabled, it keeps running until reset. As an exception, the watchdog timer delays the
reset automatically when a condition which stops program execution by the CPU develops. For those conditions
which correspond to this exception, refer to the function description of the watchdog timer in “HARDWARE MAN
UAL”. A watchdog reset may not be generated in the above situation caused by the system running out of
control. In that case, please reset (INIT) by external INIT terminal.
7) Notes on using the A/D converter
Although this series contains an A/D converter, do not apply a higher voltage to AVCC pin than to VDDE pin.
8) Software reset in synchronous mode
When using the software reset in synchronous mode, the following two conditions should be satisfied before
setting “0” to the SRST bit in STCR (standby control register) .
• Set the interrupt enable flag (I-Flag) to the interrupt disable (I-Flag = 0) .
• Do not use NMI.
22
DS07-16802-2E
MB91314A Series
■ BLOCK DIAGRAM
FR CPU CORE
32
Mask ROM
256 Kbytes/
Flash 512 Kbytes
32
Bit search
module
RAM
32 Kbytes
Bus converter
32 ↔ 16
adapter
DMAC
5 channels
Simple external bus I/F
8/16-bit
multiplex bus
Clock
control
Interrupt
controller
External
interrupt
Ports
DS07-16802-2E
Multi function
Serial interface
UART/SIO/I2C
11 channels
PWC
1 channel
A/D converter
10 channels
PPG
4 channels
Reload
timer
6 channels
Closed caption
decoder
1 channel
Multifunction
timer
4 channels
23
MB91314A Series
■ CPU AND CONTROL UNIT
Internal architecture
The FR family of CPUs is a line of high-performance cores providing advanced instructions for embedded
applications based on the RISC architecture.
1. Features
• RISC architecture adopted. Basic instructions : Executed at one instruction per cycle
• 32-bit architecture
General purpose registers : 32 bits × 16
• Four Gbytes of linear memory space
• Multiplier integrated
32-bit × 32-bit multiplication : 5 cycles
16-bit × 16-bit multiplication : 3 cycles
• Enhanced interrupt servicing
High-speed response (6 cycles)
Multi-level interrupt support
Level mask feature (16 levels)
• Enhanced I/O manipulation instructions
Memory-to-memory transfer instructions
Bit manipulation instructions
• High code efficiency
Basic instruction word length : 16 bits
• Lower-power consumption
Sleep mode/stop mode
Gear function
24
DS07-16802-2E
MB91314A Series
2. Internal architecture
The FR family of CPUs has a Harvard architecture in which the instruction bus and data bus are separated.
The 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the
CPU and peripheral resources.
The Harvard ↔ Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface
between the CPU and the bus controller.
FRex CPU
D-bus
I-bus
32
I address
External address
32
Harvard
I data
External data
D address
32
Data RAM
32-bit
16-bit
bus converter
24
D data
Princeton
bus
converter
16
32
Address
32
Data
32
16
R-bus
Peripheral resources
DS07-16802-2E
F-bus
Internal I/O
Bus converter
25
MB91314A Series
3. Programming model
• Programming model
32 bits
[Initial Value]
R0
XXXX XXXXH
R1
...
...
...
General
purpose
registers
26
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program status
PS
ILM
SCR
CCR
TBR
RP
System stack pointer
SSP
User stack pointer
USP
Multiply and divide result
register
...
R13
PC
Return pointer
...
...
R12
Program counter
Table base register
...
...
MDH
MDL
DS07-16802-2E
MB91314A Series
4. Register
• General purpose registers
32 bits
[Initial Value]
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general purpose registers. The registers are used as the accumulator and memory
access pointers for CPU operations.
Of these 16 registers, the registers listed below are intended for special applications, for which some instructions
are enhanced.
• R13 : Virtual accumulator (AC)
• R14 : Frame pointer (FP)
• R15 : Stack pointer (SP)
The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value).
• PS (Program Status)
This register holds the program status and is divided into the ILM, SCR, and CCR.
All of undefined bits are reserved bits. Reading these bits always returns 0. Writing to them has no effect.
bit 31
20
16
ILM
DS07-16802-2E
10
8 7
SCR
0
CCR
27
MB91314A Series
• CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
S
I
N
Z
V
C
[Initial Value]
--00XXXXB
S : Stack flag
• Cleared to 0 at a reset.
• Set the flag to 0 for execution of the RETI instruction.
I : Interrupt Enable flag
Cleared to 0 at a reset.
N : Negative flag
Initial state by reset is irregular.
Z : Zero flag
Initial state by reset is irregular.
V : Overflow flag
Initial state by reset is irregular.
C : Carrying flag
Initial state by reset is irregular.
• SCR (System Condition code Register)
bit 10
bit 9
bit 8
D1
D0
T
[Initial Value]
XX0B
D1, D0 : Flag for step division
Stores intermediate data for stepwise division operations.
T : Step trace trap flag
A flag specifying whether the step trace trap function is enabled or not.
• The emulator uses the step trace trap function. The function cannot be used by the user program when using
the emulator.
• ILM (Interrupt Level Mask Register)
bit 20
bit 19
bit 18
bit 17
bit 16
[Initial Value]
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.
Initialized to 15 (01111B) by a reset.
28
DS07-16802-2E
MB91314A Series
• PC (Program Counter)
bit 31
bit 0
[Initial Value]
XXXXXXXXH
The program counter contains the address of the instruction currently being executed.
The initial value after a reset is indeterminate.
• TBR (Table Base Register)
bit 31
bit 0
[Initial Value]
000FFC00H
The table base register contains the start address of the vector table used for servicing EIT events.
The initial value after a reset is 000FFC00H.
• RP (Return Pointer)
bit 31
bit 0
[Initial Value]
XXXXXXXXH
The return pointer contains the address to which to return from a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RET instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.
• SSP (System Stack Pointer)
bit 31
bit 0
[Initial Value]
00000000H
The SSP is the system stack pointer.
The SSP functions as R15 when the S flag is “0”.
The SSP can be explicitly specified.
The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event
occurs.
The initial value after a reset is 00000000H.
DS07-16802-2E
29
MB91314A Series
• USP (User Stack Pointer)
bit31
bit0
[Initial Value]
XXXXXXXXH
The USP is the user stack pointer.
The USP functions as R15 when the S flag is “1”.
The USP can be explicitly specified.
The initial value after a reset is indeterminate.
This pointer cannot be used by the RETI instruction.
• MDH, MDL (Multiply & Divide result register)
bit 31
bit 0
MDH
MDL
These registers hold the results of a multiplication or division. Each of them is 32-bit long.
The initial value after a reset is indeterminate.
30
DS07-16802-2E
MB91314A Series
■ MODE SETTINGS
The FR family sets the operation mode using mode pins (MD2, MD1, and MD0) and a mode register (MODR).
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Mode Pins
Mode name
Reset vector access area
MD2
MD1
MD0
0
0
0
Internal ROM mode vector
Internal
Note: Values other than those listed in the table are prohibited.
2. Mode Register (MODR)
• Detailed explanation of register
MODR
0007FDH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
1
WTH1
WTH0
[Initial Value]
XXXXXXXXB
Operation mode setting bits
Data written to the mode register by mode vector fetch is referred to as mode data.
When the mode register is set, the operation mode set in this register is used for operation.
The mode register is set when any reset source occurs.
Mode data cannot be written by the user program.
Note : Conventionally, the address (000007FFH) of the mode register for the FR family holds nothing.
The register can be updated in emulator mode. In this case, please use the instruction of the data transfer for
the 8-bit length.
Any 16/32-bit length transfer instruction cannot be used to write data to the mode register.
• Detailed explanation of mode data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
[Initial Value]
0
0
0
0
0
1
WTH1
WTH0
XXXXXXXXB
Operation mode setting bits
[bit 7 to bit 2] Reserved bits
Be sure to set these bits to “000001B”.
Setting the bits to any value other than “000001B” may result in an unpredictable operation.
DS07-16802-2E
31
MB91314A Series
[bit 1, bit 0] WTH1, WTH0 (bus width setting bits)
Used to set the bus width to be used in external bus mode.
When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area).
WTH1
WTH0
Function
Remarks
32
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
⎯
Setting disabled
1
1
Single chip mode
Single chip mode
DS07-16802-2E
MB91314A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU.
Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct area varies depending on the size of data to be accessed as follows:
→ Byte data access
: 000H to 0FFH
→ Half word data access : 000H to 1FFH
→ Word data access
: 000H to 3FFH
2. Memory Map
Single chip mode
Internal ROM
external bus mode
I/O
I/O
I/O
I/O
Access
disallowed
Internal RAM
32 Kbytes
Access
disallowed
Internal RAM
32 Kbytes
0000 0000H
0000 0400H
0001 0000H
0003 8000H
0004 0000H
Access
disallowed
Direct addressing area
Refer to “ ■ I/O Map”.
Access
disallowed
0005 0000H
0008 0000H
0010 0000H
0020 0000H
007F FFFFH
FFFF FFFFH
External area
Internal
Flash
512 Kbytes
Access
disallowed
Internal
Flash
512 Kbytes
Access
disallowed
External area
Access
disallowed
(MB91F314A)
DS07-16802-2E
33
MB91314A Series
■ I/O MAP
The following table shows the correspondence between the memory space area and each register of the
peripheral resource.
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
Port data
register
Read/Write attribute
Initial value after a reset
Register name (First-column register at address 4n; second-column register
at address 4n + 1)
Location of left-most register (When using word access, the register
in column 1 is in the MSB side of the data.
Note : The bit values in the register represent the following initial values:
• “1” : initial values“1”
• “0” : initial values“0”
• “X” : initial values“X”
• “-” : No physical register at this location
Access is barred with an undefined data access attribute.
34
DS07-16802-2E
MB91314A Series
Register
Address
0
1
2
3
000000H
PDR0 [R/W] B, H
XXXXXXXX
PDR1 [R/W] B, H
XXXXXXXX
PDR2 [R/W] B, H
XXXXXXXX
PDR3 [R/W] B, H
XXXXXXXX
000004H
PDR4 [R/W] B, H
XXXXXXXX
PDR5 [R/W] B, H
XXXXXXXX
PDR6 [R/W] B, H
--XXXXXX
⎯
PDRE [R/W] B, H
XXXXXXXX
⎯
PDRC [R/W] B, H
XXXXXXXX
PDRD [R/W] B, H
XXXXXXXX
000010H
to
00001CH
000020H
Port data register
⎯
000008H
00000CH
Block
⎯
ADCTH[R/W]
XXXXXX00
ADCTL[R/W]
00000X00
Reserved
ADCH[R/W]
00000000 00000000
000024H
ADAT0[R]
XXXXXX00 00000000
ADAT1[R]
XXXXXX00 00000000
000028H
ADAT2[R]
XXXXXX00 00000000
ADAT3[R]
XXXXXX00 00000000
00002CH
ADAT4[R]
XXXXXX00 00000000
ADAT5[R]
XXXXXX00 00000000
000030H
ADAT6[R]
XXXXXX00 00000000
ADAT7[R]
XXXXXX00 00000000
000034H
ADAT8[R]
XXXXXX00 00000000
ADAT9[R]
XXXXXX00 00000000
000038H
to
00003CH
⎯
10-bit A/D
converter
Reserved
000040H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
Ext. INT 0 to INT7
000044H
DICR [R/W]
00000000
HRCL [R, R/W]
0--11111
⎯
DLY / I-unit
000048H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
TMR0 [R]
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R, RW]
00000000 00000000
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
⎯
TMCSR1 [R, RW]
00000000 00000000
000054H
Reload timer 0
Reload timer 1
(Continued)
DS07-16802-2E
35
MB91314A Series
Address
Register
0
1
2
3
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R, RW]
00000000 00000000
000060H
000064H
SCR0/IBCR0
[R, R/W]
0--00000
SMR0 [W, R/W]
00000000
RDR0/TDR0 [R/W]
-------0 00000000
000068H
ISMK0 [R/W]
01111110
IBSA [R/W]
00000000
00006CH
FBYTE01 [R/W]
00000000
FBYTE00 [R/W]
00000000
000070H
SCR1/IBCR1
[R, R/W]
0--00000
SMR1 [W, R/W]
00000000
000074H
ISMK1 [R/W]
01111110
IBSA1 [R/W]
00000000
00007CH
FBYTE11 [R/W]
00000000
FBYTE10 [R/W]
00000000
000080H
SCR2/IBCR2
[R, R/W]
0--00000
SMR2 [W, R/W]
00000000
000084H
ISMK2 [R/W]
01111110
IBSA2 [R/W]
00000000
00008CH
FBYTE21 [R/W]
00000000
FBYTE20 [R/W]
00000000
000090H
SCR3/IBCR3
[R, R/W]
0--00000
SMR3 [W, R/W]
00000000
000094H
000098H
00009CH
BGR00 [R/W]
00000000
FCR01 [R/W]
00000000
FCR00 [R/W]
00000000
Multi function
Serial interface 0
FIFO0
SSR1 [R, R/W]
0-000011
ESCR1/IBSR1
[R/W]
--000000
BGR11 [R/W]
00000000
BGR10 [R/W]
00000000
FCR11 [R/W]
00000000
FCR10 [R/W]
00000000
Multi function
Serial interface 1
FIFO1
SSR2 [R, R/W]
0-000011
ESCR2/IBSR2
[R/W]
--000000
BGR21 [R/W]
00000000
BGR20 [R/W]
00000000
FCR21 [R/W]
00000000
FCR20 [R/W]
00000000
Multi function
Serial interface 2
⎯
RDR3/TDR3 [R/W]
-------0 00000000
ISMK3 [R/W]
01111110
BGR01 [R/W]
00000000
⎯
RDR2/TDR2 [R/W]
-------0 00000000
000088H
ESCR0/IBSR0
[R/W]
--000000
Reload timer 2
⎯
RDR1/TDR1 [R/W]
-------0 00000000
000078H
SSR0 [R, R/W]
0-000011
Block
IBSA3 [R/W]
00000000
SSR3 [R, R/W]
0-000011
ESCR3/IBSR3
[R/W]
--000000
BGR31 [R/W]
00000000
BGR30 [R/W]
00000000
Multi function
Serial interface 3
⎯
⎯
(Continued)
36
DS07-16802-2E
MB91314A Series
Register
Address
0000A0H
0
1
2
3
SCR4/IBCR4
[R, R/W]
0--00000
SMR4 [W, R/W]
00000000
SSR4 [R, R/W]
0-000011
ESCR4/IBSR4
[R/W]
--000000
BGR41 [R/W]
00000000
BGR40 [R/W]
00000000
RDR4/TDR4 [R/W]
-------0 00000000
0000A4H
0000A8H
ISMK4 [R/W]
01111110
IBSA4 [R/W]
00000000
SCR5/IBCR5
[R, R/W]
0--00000
⎯
SMR5 [W, R/W]
00000000
RDR5/TDR5 [R/W]
-------0 00000000
0000B4H
0000B8H
Multi function
Serial interface 4
⎯
0000ACH
0000B0H
Block
ISMK5 [R/W]
01111110
SSR5 [R, R/W]
0-000011
ESCR5/IBSR5
[R/W]
--000000
BGR51 [R/W]
00000000
BGR50 [R/W]
00000000
IBSA5 [R/W]
00000000
Multi function
Serial interface 5
⎯
⎯
0000BCH
0000C0H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
Ext. INT 8 to INT15
0000C4H
EIRR2 [R/W]
00000000
ENIR2 [R/W]
00000000
ELVR2 [R/W]
00000000 00000000
Ext. INT 16 to
INT23
0000C8H
to
0000CCH
0000D0H
⎯
PWCCL[R/W]
0000--00
PWCCH[R/W]
00-00000
PWCC2[R/W]
000-----
⎯
PWC
⎯
Reserved
PWCUD[R/W]
XXXXXXXX XXXXXXXX
0000DCH
0000E0H
to
0000ECH
0000F0H
⎯
PWCD[R]
XXXXXXXX XXXXXXXX
0000D4H
0000D8H
Reserved
⎯
⎯
T0LPCR [R/W]
-----000
0000F4H
T0CCR [R/W]
0-010000
T0DRR [R/W]
XXXXXXXX XXXXXXXX
Reserved
T0TCR [R/W]
00000000
T0R [R/W]
---00000
T0CRR [R/W]
XXXXXXXX XXXXXXXX
Multifunction timer
(Continued)
DS07-16802-2E
37
MB91314A Series
Address
0000F8H
0000FCH
000100H
000104H
000108H
Register
0
1
2
3
T1LPCR [R/W]
-----000
T1CCR [R/W]
0-000000
T1TCR [R/W]
00000000
T1R [R/W]
---00000
T1DRR [R/W]
XXXXXXXX XXXXXXXX
T2LPCR [R/W]
-----000
T1CRR [R/W]
XXXXXXXX XXXXXXXX
T2CCR [R/W]
0-000000
T2TCR [R/W]
00000000
T2DRR [R/W]
XXXXXXXX XXXXXXXX
T3LPCR [R/W]
-----000
T2R [R/W]
---00000
T2CRR [R/W]
XXXXXXXX XXXXXXXX
T3CCR [R/W]
0-000000
T3TCR [R/W]
00000000
T3DRR [R/W]
XXXXXXXX XXXXXXXX
T3CRR [R/W]
XXXXXXXX XXXXXXXX
000110H
TMODE [R/W]
-------- -----0--
⎯
⎯
000120H
PDUT0[W]
XXXXXXXX XXXXXXXX
000124H
PTMR0[R]
11111111 11111111
000128H
PDUT1[W]
XXXXXXXX XXXXXXXX
00012CH
PTMR1[R]
11111111 11111111
000130H
PDUT2[W]
XXXXXXXX XXXXXXXX
000134H
PTMR2[R]
11111111 11111111
000138H
PDUT3[W]
XXXXXXXX XXXXXXXX
00013CH
PTMR3[R]
11111111 11111111
000140H
to
000144H
Multifunction timer
T3R [R/W]
---00000
00010CH
000114H
to
00011CH
Block
Reserved
PCSR0[W]
XXXXXXXX XXXXXXXX
PCNH0[R/W]
00000000
PCNL0[R/W]
00000000
PCSR1[W]
XXXXXXXX XXXXXXXX
PCNH1[R/W]
00000000
PCNL1[R/W]
00000000
PCSR2[W]
XXXXXXXX XXXXXXXX
PCNH2[R/W]
00000000
PCNL2[R/W]
00000000
PCSR3[W]
XXXXXXXX XXXXXXXX
PCNH3[R/W]
00000000
PCNL3[R/W]
00000000
⎯
PPG0
PPG1
PPG2
PPG3
Reserved
000148H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
TMR3 [R]
XXXXXXXX XXXXXXXX
00014CH
⎯
TMCSR3 [R, RW]
00000000 00000000
Reload timer 3
(Continued)
38
DS07-16802-2E
MB91314A Series
Register
Address
0
1
2
3
000150H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
TMR4 [R]
XXXXXXXX XXXXXXXX
000154H
⎯
TMCSR4 [R, RW]
00000000 00000000
000158H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
TMR5 [R]
XXXXXXXX XXXXXXXX
⎯
TMCSR5 [R, RW]
00000000 00000000
00015CH
000160H
to
00019CH
⎯
PLLREG0[R/W] H
---00000 ---00000
PLLREG1[R/W] H
----0000 00000000
0001A4H
PLLREG2[R/W] H
-------- 0000--0-
PLLREG3[R/W] H
0000---- ----00-0
0001B0H
⎯
SCR6/IBCR6
[R, R/W]
0--00000
RDR6/TDR6 [R/W]
-------0 00000000
0001B4H
0001B8H
SMR6 [W, R/W]
00000000
ISMK6 [R/W]
01111110
SCR7/IBCR7
[R, R/W]
0--00000
RDR7/TDR7 [R/W]
-------0 00000000
ISMK7 [R/W]
01111110
ESCR6/IBSR6
[R/W]
--000000
BGR61 [R/W]
00000000
BGR60 [R/W]
00000000
Multi function
Serial
interface 6
SSR7 [R, R/W]
0-000011
ESCR7/IBSR7
[R/W]
--000000
BGR71 [R/W]
00000000
BGR70 [R/W]
00000000
IBSA7 [R/W]
00000000
Multi function
Serial
interface 7
⎯
⎯
SCR8/IBCR8
[R, R/W]
0--00000
SMR9 [W, R/W]
00000000
RDR8/TDR8 [R/W]
-------0 00000000
0001D4H
0001D8H
SSR6 [R, R/W]
0-000011
⎯
SMR7 [W, R/W]
00000000
0001CCH
0001D0H
PLL of high
multiplication
⎯
0001C4H
0001C8H
Reload timer 5
Reserved
IBSA6 [R/W]
00000000
0001BCH
0001C0H
Reload timer 4
Reserved
0001A0H
0001A8H
to
0001ACH
Block
ISMK8 [R/W]
01111110
0001DCH
IBSA8 [R/W]
00000000
SSR8 [R, R/W]
0-000011
ESCR8/IBSR8
[R/W]
--000000
BGR81 [R/W]
00000000
BGR80 [R/W]
00000000
Multi function
Serial
interface 8
⎯
⎯
(Continued)
DS07-16802-2E
39
MB91314A Series
Address
0001E0H
0001E4H
0001E8H
Register
0
1
2
3
SCR9/IBCR9
[R, R/W]
0--00000
SMR9 [W, R/W]
00000000
SSR9 [R, R/W]
0-000011
ESCR9/IBSR9
[R/W]
--000000
BGR91 [R/W]
00000000
BGR90 [R/W]
00000000
RDR9/TDR9 [R/W]
-------0 00000000
ISMK9 [R/W]
01111110
IBSA9 [R/W]
00000000
0001F4H
0001F8H
Multi function
Serial
interface 9
⎯
⎯
0001ECH
0001F0H
Block
SCRA/IBCRA
[R, R/W]
0--00000
SMRA [W, R/W]
00000000
RDRA/TDRA [R/W]
-------0 00000000
ISMKA [R/W]
01111110
IBSAA [R/W]
00000000
SSRA [R, R/W]
0-000011
ESCRA/IBSRA
[R/W]
--000000
BGRA1 [R/W]
00000000
BGRA0 [R/W]
00000000
Multi function
Serial
interface 10
⎯
0001FCH
⎯
000200H
DMACA0 [R/W]
00000000 00000000 00000000 00000000
000204H
DMACB0 [R/W]
00000000 00000000 00000000 00000000
000208H
DMACA1 [R/W]
00000000 00000000 00000000 00000000
00020CH
DMACB1 [R/W]
00000000 00000000 00000000 00000000
000210H
DMACA2 [R/W]
00000000 00000000 00000000 00000000
000214H
DMACB2 [R/W]
00000000 00000000 00000000 00000000
000218H
DMACA3 [R/W]
00000000 00000000 00000000 00000000
00021CH
DMACB3 [R/W]
00000000 00000000 00000000 00000000
000220H
DMACA4 [R/W]
00000000 00000000 00000000 00000000
000224H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000228H
to
00023CH
⎯
Reserved
000240H
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
DMAC
(Continued)
40
DS07-16802-2E
MB91314A Series
Register
Address
0
1
2
3
000244H
to
0003ECH
⎯
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Bit search
000400H
DDR0 [R/W] B, H
00000000
DDR1 [R/W] B, H
00000000
DDR2 [R/W] B, H
00000000
DDR3 [R/W] B, H
00000000
000404H
DDR4 [R/W] B, H
00000000
DDR5 [R/W] B, H
00000000
DDR6 [R/W] B, H
--000000
⎯
DDRE [R/W] B, H
00000000
⎯
00040CH
Data direction
register
⎯
000408H
DDRC [R/W] B, H
00000000
DDRD [R/W] B, H
00000000
000410H
⎯
000414H
to
00041CH
⎯
Reserved
000420H
PFR0 [R/W] B, H
00000000
PFR1 [R/W] B, H
00000000
PFR2 [R/W] B, H
00000000
PFR3 [R/W] B, H
00000000
000424H
PFR4 [R/W] B, H
00000000
PFR5 [R/W] B, H
00000000
PFR6 [R/W] B, H
--000000
⎯
PFRE [R/W] B, H
00000000
⎯
00042CH
Port function
register
⎯
000428H
PFRC [R/W] B, H
00000000
PFRD [R/W] B, H
00000000
000430H
⎯
000434H
to
00043CH
⎯
Block
Reserved
(Continued)
DS07-16802-2E
41
MB91314A Series
Address
Register
0
1
2
3
000440H
ICR00 [R, R/W]
---11111
ICR01 [R, R/W]
---11111
ICR02 [R, R/W]
---11111
ICR03 [R, R/W]
---11111
000444H
ICR04 [R, R/W]
---11111
ICR05 [R, R/W]
---11111
ICR06 [R, R/W]
---11111
ICR07 [R, R/W]
---11111
000448H
ICR08 [R, R/W]
---11111
ICR09 [R, R/W]
---11111
ICR10 [R, R/W]
---11111
ICR11 [R, R/W]
---11111
00044CH
ICR12 [R, R/W]
---11111
ICR13 [R, R/W]
---11111
ICR14 [R, R/W]
---11111
ICR15 [R, R/W]
---11111
000450H
ICR16 [R, R/W]
---11111
ICR17 [R, R/W]
---11111
ICR18 [R, R/W]
---11111
ICR19 [R, R/W]
---11111
000454H
ICR20 [R, R/W]
---11111
ICR21 [R, R/W]
---11111
ICR22 [R, R/W]
---11111
ICR23 [R, R/W]
---11111
000458H
ICR24 [R, R/W]
---11111
ICR25 [R, R/W]
---11111
ICR26 [R, R/W]
---11111
ICR27 [R, R/W]
---11111
00045CH
ICR28 [R, R/W]
---11111
ICR29 [R, R/W]
---11111
ICR30 [R, R/W]
---11111
ICR31 [R, R/W]
---11111
000460H
ICR32 [R, R/W]
---11111
ICR33 [R, R/W]
---11111
ICR34 [R, R/W]
---11111
ICR35 [R, R/W]
---11111
000464H
ICR36 [R, R/W]
---11111
ICR37 [R, R/W]
---11111
ICR38 [R, R/W]
---11111
ICR39 [R, R/W]
---11111
000468H
ICR40 [R, R/W]
---11111
ICR41 [R, R/W]
---11111
ICR42 [R, R/W]
---11111
ICR43 [R, R/W]
---11111
00046CH
ICR44 [R, R/W]
---11111
ICR45 [R, R/W]
---11111
ICR46 [R, R/W]
---11111
ICR47 [R, R/W]
---11111
000470H
to
00047CH
⎯
RSRR [R, R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXXX00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
OSCCR [R/W]
XXXXXXXX
⎯
⎯
Interrupt control
unit
Reserved
000480H
000488H
Block
Clock control
unit
00048CH
WPCR [R/W] B
00---000
⎯
Watch Timer
000490H
OSCR [R/W]
00000000
⎯
Main oscillation
stabilization
wait timer
000494H
to
0004FCH
⎯
Reserved
(Continued)
42
DS07-16802-2E
MB91314A Series
Register
Address
0
1
000500H
PCR0 [R/W] B, H
00000000
PCR1 [R/W] B, H
00000000
000504H
⎯
PCR5 [R/W] B, H
00000000
2
3
⎯
PCR6 [R/W] B, H
--000000
000508H
to
000510H
⎯
000514H
to
00051CH
⎯
⎯
Port Pull-up
control register
Reserved
000520H
EPFR0 [R/W] B, H EPFR1 [R/W] B, H EPFR2 [R/W] B, H
00000000
00000000
11111111
EPFR3 [R/W] B, H
11111111
000524H
EPFR4 [R/W] B, H EPFR5 [R/W] B, H EPFR6 [R/W] B, H
11111111
11111111
--001000
⎯
Extend
Port Control
Register
⎯
000528H
00052CH
Block
EPFRC [R/W] B, H EPFRD [R/W] B, H EPFRE [R/W] B, H
00000000
00000000
00000000
000530H
⎯
000534H
to
00056CH
⎯
000570H
ADER[R/W] H
00000000 00000000
⎯
NSF[R/W]
-----000 00000000
00057CH
to
00063CH
Special
Port Function
Register
Reserved
⎯
000574H
000578H
⎯
EXT/I2C/
A/D converter
Reserved
⎯
⎯
I2C noise filter
Reserved
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111XX00 00000000
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
T-Unit
(Continued)
DS07-16802-2E
43
MB91314A Series
Address
00064CH
Register
0
1
2
ASR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
to
00065CH
3
ACR3 [R/W]
XXXXXXXX XXXXXXXX
⎯
000660H
AWR0 [R/W] B, H, W
01111111 11111111
AWR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000668H
to
00067CH
000680H
T-Unit
⎯
CSER[R/W]B, H, W
00000001
⎯
000684H
⎯
000688H
to
0007F8H
⎯
0007FCH
Block
⎯
Unused
MODR [W]
XXXXXXXX
000800H
to
000AFCH
⎯
⎯
⎯
Unused
000B00H
ESTS0 [R/W] B
X0000000
ESTS1 [R/W] B
XXXXXXXX
ESTS2 [R] B
1XXXXXXX
⎯
000B04H
ECTL0 [R/W] B
0X000000
ECTL1 [R/W] B
00000000
ECTL2 [W] B
000X0000
ECTL3 [R/W] B
00X00X11
000B08H
ECNT0 [W] B
XXXXXXXX
ECNT1 [W] B
XXXXXXXX
EUSA [W] B
XXX00000
EDTC [W] B
0000XXXX
000B0CH
EWPT [R] H
00000000 00000000
ECTL4[R]([R/W])B ECTL5[R]([R/W])B
-0X00000
----000X
000B10H
EDTR0 [W] H
XXXXXXXX XXXXXXXX
EDTR1 [W] H
XXXXXXXX XXXXXXXX
DSU
(Continued)
44
DS07-16802-2E
MB91314A Series
Address
Register
0
1
2
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B64H
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
3
Block
DSU
(Continued)
DS07-16802-2E
45
MB91314A Series
(Continued)
Address
Register
0
1
2
000B68H
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000FFCH
⎯
001000H
DMASA0 [R/W]
00000000 00000000 00000000 00000000
001004H
DMADA0 [R/W]
00000000 00000000 00000000 00000000
001008H
DMASA1 [R/W]
00000000 00000000 00000000 00000000
00100CH
DMADA1 [R/W]
00000000 00000000 00000000 00000000
001010H
DMASA2 [R/W]
00000000 00000000 00000000 00000000
001014H
DMADA2 [R/W]
00000000 00000000 00000000 00000000
001018H
DMASA3 [R/W]
00000000 00000000 00000000 00000000
00101CH
DMADA3 [R/W]
00000000 00000000 00000000 00000000
001020H
DMASA4 [R/W]
00000000 00000000 00000000 00000000
001024H
DMADA4 [R/W]
00000000 00000000 00000000 00000000
001028H
to
006FFCH
⎯
Block
DSU
Reserved
DMAC
Reserved
007000H
FLCR[R/W]
01101000
⎯
007004H
FLWC[R/W]
00110011
⎯
46
3
Flash I/F
DS07-16802-2E
MB91314A Series
■ VECTOR TABLE
Interrupt source
Interrupt number
Decimal Hexadecimal
Interrupt
level
Offset
TBR default DMA
transfer
address
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
System reserved
10
0A
⎯
3D4H
000FFFD4H
⎯
System reserved
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
System reserved
15
0F
15 (FH) fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
⎯
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
⎯
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
⎯
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
⎯
Reload timer 1
25
19
ICR09
398H
000FFF98H
⎯
Reload timer 2
26
1A
ICR10
394H
000FFF94H
⎯
UART0 RX/I2C states
27
1B
ICR11
390H
000FFF90H
UART0 TX
28
1C
ICR12
38CH
000FFF8CH
UART1 RX/I C states
29
1D
ICR13
388H
000FFF88H
UART1 TX
30
1E
ICR14
384H
000FFF84H
UART2 RX/I2C states
31
1F
ICR15
380H
000FFF80H
UART2 TX
32
20
ICR16
37CH
000FFF7CH
33
21
ICR17
378H
000FFF78H
2
2
UART3 RX/TX/I C states
DMAC
STOP
factor
STOP
STOP
STOP
⎯
(Continued)
DS07-16802-2E
47
MB91314A Series
Interrupt source
Interrupt number
Decimal Hexadecimal
Interrupt
level
Offset
TBR default DMA
transfer
address
UART4 RX/TX/I2C states
34
22
ICR18
374H
000FFF74H
⎯
UART5 RX/TX/I2C states
35
23
ICR19
370H
000FFF70H
⎯
2
36
24
ICR20
36CH
000FFF6CH
⎯
2
UART7 RX/TX/I C states
37
25
ICR21
368H
000FFF68H
⎯
UART8 RX/TX/I2C states
38
26
ICR22
364H
000FFF64H
⎯
UART9 RX/TX/I2C states
39
27
ICR23
360H
000FFF60H
⎯
UART10 RX/TX/I C states
40
28
ICR24
35CH
000FFF5CH
⎯
A/D converter
41
29
ICR25
358H
000FFF58H
⎯
PPG0
42
2A
ICR26
354H
000FFF54H
PWC
43
2B
ICR27
350H
000FFF50H
⎯
CCD
44
2C
ICR28
34CH
000FFF4CH
⎯
Watch timer
45
2D
ICR29
348H
000FFF48H
⎯
Main oscillation wait
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer
47
2F
ICR31
340H
000FFF40H
⎯
Reload timer 3
48
30
ICR32
33CH
000FFF3CH
⎯
Reload timer 4
49
31
ICR33
338H
000FFF38H
⎯
Reload timer 5
50
32
ICR34
334H
000FFF34H
⎯
PPG1
51
33
ICR35
330H
000FFF30H
PPG2
52
34
ICR36
32CH
000FFF2CH
PPG3
53
35
ICR37
328H
000FFF28H
DMA0
54
36
ICR38
324H
000FFF24H
⎯
DMA1
55
37
ICR39
320H
000FFF20H
⎯
DMA2
56
38
ICR40
31CH
000FFF1CH
⎯
DMA3
57
39
ICR41
318H
000FFF18H
⎯
DMA4
58
3A
ICR42
314H
000FFF14H
⎯
External interrupt 8 to 15
59
3B
ICR43
310H
000FFF10H
⎯
External interrupt 16 to 23
60
3C
ICR44
30CH
000FFF0CH
⎯
Multi-function timer 0, 1
61
3D
ICR45
308H
000FFF08H
⎯
Multi-function timer 2, 3
62
3E
ICR46
304H
000FFF04H
⎯
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
⎯
System reserved
(Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved
(Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
UART6 RX/TX/I C states
2
DMAC
STOP
factor
(Continued)
48
DS07-16802-2E
MB91314A Series
(Continued)
Interrupt source
Interrupt number
Decimal Hexadecimal
Interrupt
level
Offset
TBR default DMA
transfer
address
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
DS07-16802-2E
DMAC
STOP
factor
49
MB91314A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage
Analog power supply voltage
Rating
Symbol
Unit
Min
Max
VDDE (3.3 V)
Vss − 0.5
Vss + 4.0
V
VDDI (1.8 V)
Vss − 0.3
Vss + 2.5
V
AVCC
Vss − 0.5
Vss + 4.0
V
Vss − 0.5
Vcc + 0.5
V
Vss − 0.5
Vss + 6.0
V
Input voltage
VI
Analog pin input voltage
VIA
Vss − 0.5
AVcc + 0.5
V
Output voltage
VO
Vss − 0.5
Vcc + 0.5
V
Tstg
− 40
+ 125
°C
Storage temperature
Remarks
5 V tolerant pin
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Parameter
Symbol
Value
Unit
Min
Max
Ta
− 10
+ 70
VDDE (3.3 V)
3.0
3.6
VDDI (1.8 V)
1.65
1.95
Analog power supply voltage
AVCC
3.0
VDDE
V
5 V tolerant pin input voltage
VI
⎯
VSS + 5.5
V
Operating temperature
Power supply voltage
°C
V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
50
DS07-16802-2E
MB91314A Series
3. DC Characteristics
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Pin name
Max
⎯
300
700
⎯
700
1000
⎯
100
120
⎯
70
100
⎯
60
80
⎯
60
90
⎯
400
1000
⎯
900
1300
⎯
160
600
⎯
40
80
⎯
900
4000
⎯
240
400
VDDE × 0.8
⎯
VDDE
V
PE2 to PE7, PC0 to PC7,
P40 to P47
VDDE × 0.7
⎯
VDDE
V
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P60 to P65,
PD0 to PD7, PE0, PE1,
HSYNC
VSS
⎯
VDDE × 0.2
V
VSS
⎯
VDDE × 0.3
V
⎯
⎯
ICC
⎯
⎯
ICCS
⎯
⎯
ICCL
⎯
⎯
⎯
ICCH
⎯
⎯
“L” level input
voltage
VIH
VIL
Unit
Typ
⎯
“H” level input
voltage
Value
Min
ICCT
Current
Consumption
(upper : 1.8 V
lower : 3.3 V)
Conditions
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P60 to P65,
PD0 to PD7, PE0, PE1
Watch mode
Ta = + 25 °C,
fclk = 32 kHz
During normal
operation
Ta = + 25 °C,
fcp = 33 MHz,
fcpp = 33 MHz
Main sleep mode
Ta = + 25 °C,
fcp = 33 MHz,
fcpp = 33 MHz
Sub RUN mode
Ta = + 25 °C,
fclk = 32 kHz
Main Stop mode
Ta = + 25 °C,
fclk = 0
Ta = + 70 °C,
fclk = 0
µA
mA
mA
µA
µA
µA
VDDE = 3.3 V
VDDE = 3.3 V
PE2 to PE7, PC0 to PC7,
P40 to P47
“H” level output
voltage
VOH
P00 to PE1
VDDE = 3.3 V,
IOH = − 4 mA
VDDE − 0.5
⎯
VDDE
V
“L” level output
voltage
VOL
P00 to PE1
VDDE = 3.3 V,
IOL = 4 mA
VSS
⎯
0.4
V
(Continued)
DS07-16802-2E
51
MB91314A Series
(Continued)
Parameter
Input leak current
(Ta = −10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V)
Symbol
IIL
Pin name
Other than
PD0 to PD7, PE0, PE1
Conditions
⎯
PD0 to PD7, PE0, PE1
I2C bus switch
connection
resistance
52
RBS
Between P21 and P24
Between P22 and P25
Between P24 and P27
Between P25 and P30
⎯
Value
Unit
Min
Typ
Max
−5
⎯
+5
µA
− 10
⎯
+ 10
µA
⎯
⎯
130
Ω
DS07-16802-2E
MB91314A Series
4. AC Characteristics
(1) Clock Timing
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Clock frequency
Sub clock frequency
Pin
name
Value
Conditions
Min
Max
Unit
Remarks
fC
X0, X1
⎯
10
16.5
33
PLL clock (self-oscillation
16.5 MHz doubled via
MHz
PLL : internal operation at
33 MHz max.)
fclk
X0A,
X1A
⎯
⎯
32.768
⎯
kHz
⎯
⎯
33
MHz CPU
⎯
⎯
33
MHz Peripheral
⎯
⎯
16.5
fCP
Internal operating
clock frequency
Typ
⎯
fCPP
⎯
fCPT
MHz External bus
(2) Clock Output Timing
(VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = −10 °C to + 70 °C)
Symbol
Pin
name
Cycle time
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
CLK
CLK ↓ → CLK ↑
tCLCL
CLK
Parameter
Value
Conditions
⎯
Unit Remarks
Min
Max
60.7
⎯
ns
*1
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*2
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*3
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : The following ratings are for the gear ratio set to × 1.
For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the
following equation.
(1/2 × 1/n) × tCYC − 10
*3 : The following rating are for the gear ratio set to × 1.
tCYC
tCHCL
CLK
VOH
tCLCL
VOH
VOL
(3) PLL Oscillation Stabilization Wait Time
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
PLL oscillation stabilization
wait time
tLOCK
DS07-16802-2E
Value
Min
Max
600
⎯
Unit
Remarks
µs
The length of time to wait for the PLL
oscillations to stabilize.
53
MB91314A Series
(4) Reset Input
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Pin
name
INIT input time
(at power-on)
INIT input time
(other than power-on)
INIT input time
(Stop recovery time)
tINTL
INIT
Value
Conditions
Unit
Min
Max
Oscillation stabilization delay time
of oscillator + tcp × 10
⎯
µs
tcp × 10
⎯
ns
Oscillation stabilization delay time
of oscillator + tcp × 10
⎯
µs
⎯
tINTL
INIT
54
0.2 VCC
DS07-16802-2E
MB91314A Series
(5) Multiplex Bus Access Read/Write Operation
(VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Pin name
CS0 to CS3 setup
tCSLCH
CLK
CS0 to CS3
D31 to D16
address setup time
→ CLK ↑
tASCH
CLK ↑→
D31 to D16
address hold time
tCHAX
D31 to D16
address setup time
→ AS ↑
tASASH
AS ↑→
D31 to D16
address hold time
tASHAX
WR0, WR1 delay time
tCHWL
WR0, WR1 delay time
tCHWH
CLK
WR0, WR1
WR0, WR1 minimum
pulse width
tWLWH
Data setup → WRx ↑
tDSWH
WRx ↑ → Data hold time
tWHDX
RD delay time
tCHRL
RD delay time
tCHRH
RD ↓ →
Valid data input time
tRLDV
Data setup
→ RD ↑ Time
tDSRH
RD ↑ → Data hold time
tRHDX
RD minimum pulse width
tRLRH
AS setup
tASLCH
AS hold
tASHCH
Conditions
Value
Unit
Remarks
Min
Max
3
⎯
ns
3
⎯
ns
3
tCYC / 2 + 6
ns
12
⎯
ns
*1
tCYC − 3
tCYC + 3
ns
*1
⎯
6
ns
⎯
6
ns
WR0, WR1
tCYC − 3
⎯
ns
WR0, WR1
D15 to D00
tCYC
⎯
ns
5
⎯
ns
CLK
RD
⎯
6
ns
⎯
6
ns
⎯
tCYC − 15
ns
15
⎯
ns
0
⎯
ns
RD
tCYC − 3
⎯
ns
CLK
AS
3
⎯
ns
3
⎯
ns
CLK
D31 to D16
(Address)
AS
D31 to D16
(Address)
RD
D15 to D00
⎯
*2
*1 : At CSx → RD/WRx setup extension = 1
*2 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
DS07-16802-2E
55
MB91314A Series
• At CSx → RD/WRx setup extension = 1
tCYC
BA1
BA2
BA1W
BA3
CLK
tASLCH
tASHCH
AS
tASASH
tASHAX
tCSLCH
CS0 to CS3
tASCH
D15 to D00
tCHAX
Address
Read data
tDSRH
tRHDX
tRLDV
RD
tRLRH
tCHRH
tCHRL
D15 to D00
Address
Write data
tDSWH
tWHDX
WR0, WR1
tWLWH
tCHWL
56
tCHWH
DS07-16802-2E
MB91314A Series
• At CSx → RD/WRx setup extension = 0
tCYC
BA1
BA2
BA3
CLK
AS
tASLCH
tASHCH
tCSLCH
CS0 to CS3
tASCH
D15 to D00
tCHAX
Address
Read data
tDSRH
tRHDX
tRLDV
RD
tRLRH
tCHRH
tCHRL
D15 to D00
Address
Write data
tDSWH
tWHDX
WR0, WR1
tWLWH
tCHWL
DS07-16802-2E
tCHWH
57
MB91314A Series
(6) Ready Input Timings
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Pin name
Conditions
RDY setup time →
CLK ↓
tRDYS
CLK, RDY
CLK ↓ → RDY hold time
tRDYH
CLK, RDY
Value
Unit
Min
Max
⎯
25
⎯
ns
⎯
0
⎯
ns
tCYC
CLK
VOH
VOH
VOL
VOL
tRDYS tRDYH
58
tRDYS tRDYH
VIH
RDY wait applied
VIL
RDY wait not applied
VIH
VIH
VIL
VIL
VIH
VIL
DS07-16802-2E
MB91314A Series
(7) UART timing
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
Conditions
Value
Unit
Min
Max
SCK0 to SCK10
4 tCYCP
⎯
ns
tSLOV
SCK0 to SCK10
SOT0 to SOT10
− 20
+ 20
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK10
SIN0 to SIN10
30
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK10
SIN0 to SIN10
20
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK10
2 tCYCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK10
2 tCYCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK10
SOT0 to SOT10
⎯
30
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK10
SIN0 to SIN10
20
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK10
SIN0 to SIN10
20
⎯
ns
Internal shift
clock operation
External shift
clock operation
Notes : • The above standards apply to the CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
DS07-16802-2E
59
MB91314A Series
• Internal shift clock mode
tSCYC
SCK0 to SCK10
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT10
tIVSH
tSHIX
VIH
VIL
SIN0 to SIN10
VIH
VIL
• External shift clock mode
tSLSH
SCK0 to SCK10
tSHSL
VOL
VOL
VOH
VOH
tSLOV
SOT0 to SOT10
VOH
VOL
tIVSH
SIN0 to SIN10
60
VIH
VIL
tSHIX
VIH
VIL
DS07-16802-2E
MB91314A Series
(8) Reload timer clock, PPG timer input, multi-function timer input timing, interrupt input timing
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Input pulse width
Symbol
tTIWH
tTIWL
Pin name
Conditions
TIN0 to TIN5
TRG0 to TRG3
TMI0 to TMI3
⎯
INT0 to INT23
⎯
Value
Unit
Min
Max
2 tCYCP
⎯
ns
3 tCYCP
⎯
ns
1.0
⎯
µs
Remarks
At stop
Note : tCYCP indicates the peripheral clock cycle time.
TIN0 to TIN5
TRG0 to TRG3
TMI0 to TMI3
INT0 to INT23
tTIWH
tTIWL
(9) Trigger Input Timing
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
A/D activation trigger input time
Symbol
Pin name
Conditions
tATRG
ATRG
⎯
Value
Min
Max
5 tCYCP
⎯
Unit
ns
Note : tCYCP indicates the peripheral clock cycle time.
tATRG
ATRG
DS07-16802-2E
61
MB91314A Series
(10) External circuit for data slicer
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Value
Symbol
Pin
name
Min
Typ
Max
Video signal input level
VVIN
VIN
1.0
⎯
1.5
Vp-p
VIN pin coupling capacitor
CVIN
VIN
⎯
⎯
0.1
µF
Ceramic capacitor with an
error of 10% exceeding
B-characteristics
Resistance for clamp
RCL
VIN
⎯
⎯
1
MΩ
Error 5%
VIN pin input resistance
RIN
VIN
⎯
⎯
0
Ω
Error 5%
VIN lowpass filter capacitor
C1
⎯
⎯
⎯
82
pF
Ceramic capacitor with an
error of 10% exceeding
B-characteristics
Power supply bypass capacitor
CBP
VDDC
VSSC
⎯
⎯
0.1
µF
Ceramic condenser
Video signal input buffer
resistance
R1
⎯
⎯
⎯
2.2
kΩ
Error 5%
Video signal level correction
resistance
R2
⎯
⎯
⎯
4.7
kΩ
Error 5%
Video signal level correction
resistance
R3
⎯
⎯
10
12
kΩ
Error 5%
Parameter
62
Unit
Remarks
DS07-16802-2E
MB91314A Series
External recommended circuit for data slicer
• Input composite video signals are DC-clamped.
3.3 V
VDDC
32
CBP
5V
VSSC
33
R1
RIN
VIN
CVIN
34
RCL
R2
2SB709A
equivalent
Composite video signals
(2Vp-p)
R3
C1
• Input composite video signals are not DC-clamped.
3.3 V
VDDC
32
Add this resistance
CBP
5V
VSSC
33
R1
RIN
VIN
10 kΩ
34
RCL
R2
2SB709A
equivalent
R3
DS07-16802-2E
(Error 5%)
CVIN
C1
Composite video signals
(2Vp-p)
63
MB91314A Series
(11) I2C timing
• At master mode operating
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol Conditions
Typical mode
High-speed
mode*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” period of SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” period of SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Bus free time between
“STOP condition” and
“START condition”
tBUS
4.7
⎯
1.3
⎯
µs
SCL ↓ → SDA output delay
time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
Repeated START condition
setup time SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Repeated START condition
hold time SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
SDA data input hold time
(vs. SCL ↓)
tHDDAT
2 × M*1
⎯
2 × M*1
⎯
µs
SDA data input setup time
(vs. SCL ↑)
tSUDAT
250
⎯
100*2
⎯
ns
64
R = 1 kΩ,
C = 50 pF*4
Remarks
The first clock
pulse is generated
after this.
DS07-16802-2E
MB91314A Series
• At slave mode operating
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Symbol Conditions
High-speed
mode*3
Typical mode
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” period of SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” period of SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
SCL ↓ → SDA output delay
time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
tBUS
4.7
⎯
1.3
⎯
µs
⎯
2 × M*1
⎯
µs
⎯
100*2
⎯
ns
Bus free time between
“STOP condition” and
“START condition”
SDA data input hold time
(vs. SCL ↓)
tHDDAT
SDA data input setup time
(vs. SCL↑)
tSUDAT
Repeated START condition setup time SCL ↑ →
SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Repeated START condition hold time SDA ↓ →
SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
2 × M*1
R = 1 kΩ,
C = 50 pF*4
250
Remarks
The first clock
pulse is generated
after this.
*1 : M = Resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT ≥ 250 ns”.
When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the
SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to 6 MHz or higher.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
DS07-16802-2E
65
MB91314A Series
5. Electrical Characteristics for the A/D Converter
(1)Electrical Characteristics
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C)
Parameter
Value
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error *1
⎯
⎯
± 5.5
LSB
Nonlinear error *1
⎯
⎯
± 3.5
LSB
Differential linear error *1
⎯
⎯
± 2.0
LSB
Zero transition voltage * 1
AVSS −
4.0 LSB
⎯
AVSS +
6.0 LSB
V
Full scale transition voltage*1
AVRH −
5.5 LSB
⎯
AVRH +
3.0 LSB
V
7.94*2
⎯
⎯
µs
Power supply current (analog + digital)
⎯
⎯
3
mA
Reference power supply current
(between AVRH and AVSS)
⎯
⎯
100
µA
Analog input capacitance
⎯
⎯
21
pF
Interchannel disparity
⎯
⎯
4
LSB
Conversion time
Remarks
AVcc = 3.3 V,
AVRH = 3.3 V (CPU sleep)
AVRH = 3.0 V,
AVSS = 0.0 V
*1 : Measured in the CPU sleep state
*2 : Depending on the clock cycle supplied to peripheral resources
Comparator
RIN
AN9 to AN0
Analog input pin
CIN
66
RIN = 5 kΩ
CIN = 21 pF
DS07-16802-2E
MB91314A Series
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB91314A
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
0
5
10
15
20
25
30
Minimum sampling time [µs]
DS07-16802-2E
35
MB91314A
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
67
MB91314A Series
(2) Definition of terms
Resolution
Linearity error
: Analog variation that is recognized by an A/D converter.
: The deviation between the actual conversion characteristics and a straight line
connecting the device's zero transition point (“0000000000” ←→ “0000000001”) and
full scale transition point (“1111111110” ←→ “1111111111”).
Differential linear error : Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value.
Total error
: This error indicates the difference between actual and ideal values, including the zero
transition error/full-scale transition error/linearity error
Linearity error
3FFH
Differential linearity error
Actual conversion characteristics
Actual conversion characteristics
(N + 1)H
3FEH
{1 LSB' (N − 1) + VOT}
VFST
(measurement value)
VNT
(measurement
value)
004H
003H
Digital output
Digital output
3FDH
Ideal characteristics
NH
V(N + 1)T
(measurement value)
(N − 1)H
Actual conversion
characteristics
002H
Ideal characteristics
001H
VNT
(measurement
value)
Actual conversion
characteristics
(N − 2)H
VOT (measurement value)
AVSS
AVRH
Analog input
AVSS
AVRH
Analog input
VNT − {1 LSB' × (N − 1) + VOT}
[LSB]
1 LSB'
V (N+1) T − VNT
Differential linear error in digital output N =
−1[LSB]
1 LSB'
VFST − VOT
[V]
1 LSB =
1022
Linear error in digital output N =
N
VOT
VFST
VNT
68
: A/D converter digital output value
: A voltage at which digital output transits from (000) H to (001) H
: A voltage at which digital output transits from (3FE) H to (3FF) H
: A voltage at which digital output transitions from (N−1) H to NH
DS07-16802-2E
MB91314A Series
Total error
3FFH
3FEH
1.5 LSB'
Actual conversion
characteristics
Digital output
3FDH
{1 LSB' (N - 1) + 0.5 LSB'}
004H
VNT
003H
(measurement
value)
002H
Actual conversion
characteristics
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
AVRH − AVSS
[V]
1024
VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
Total error of digital output N =
1 LSB'
1LSB' (ideal value) =
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N + 1) H to NH
VOT' (ideal value) = AVSS + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
6. Flash Memory Write/Erase Characteristics
(Ta = + 25 °C, VCC = 3.3 V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
⎯
0.5
2.0
s
Excludes internal programming
prior erasure.
Byte write time
⎯
6
100
µs
Excludes system-level overhead.
Chip write time
⎯
1.8
29.5
s
Excludes system-level overhead.
10000
⎯
⎯
cycle
Erase/write cycle
DS07-16802-2E
69
MB91314A Series
■ ORDERING INFORMATION
70
Part number
Package
MB91F314PMC-GE1
120-pin plastic LQFP
(FPT-120P-M21)
DS07-16802-2E
MB91314A Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
60
91
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
"A"
31
1
30
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
C
2002 FUJITSU LIMITED F120033S-c-4-4
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16802-2E
71
MB91314A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Changed the series name.
MB91314 series → MB91314A series
⎯
⎯
Deleted the part numbers.
MB91314A
14 to 17
36, 37
39, 40
36
42
58, 60
66
Change Results
■ I/O CIRCUIT TYPE
Changed the type of input level.
CMOS level hysteresis input → CMOS hysteresis input
■ I/O MAP
Changed the register name in “Multi function Serial interface”.
RDRn/TRDn → RDRn/TDRn (n=0 to 9, A)
■ I/O MAP
Address: 000060H
Changed the register name in “Multi function Serial interface”.
SCR0 → SCR0/IBCR0
ESCR0 → ESCR0/IBSR0
■ I/O MAP
Address: 000490H
Changed the register in “Main clock oscillation waits until
stable timer”.
OSCT → ⎯
■ ELECTRICAL CHARACTERISTICS
Changed the input level in the timing chart.
4. AC Characteristics
VOH → VIH
(6) Ready Input Timings
VOL → VIL
(7) UART timing
■ ELECTRICAL CHARACTERISTICS Changed the items of “Zero transition voltage” and
5. Electrical Characteristics for the A/D “Full-transition voltage”.
Converter
Unit : LSB → V
Value : value → AVSS ± value LSB
Value : AVRH ± value → AVRH ± value LSB
Changed the name of reference power supply current
AVRL → AVSS
The vertical lines marked in the left side of the page show the changes.
72
DS07-16802-2E
MB91314A Series
MEMO
DS07-16802-2E
73
MB91314A Series
MEMO
74
DS07-16802-2E
MB91314A Series
MEMO
DS07-16802-2E
75
MB91314A Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
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#05-08 New Tech Park 556741 Singapore
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http://www.fmal.fujitsu.com/
Europe
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http://emea.fujitsu.com/microelectronics/
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Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
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as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
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Edited: Sales Promotion Department
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