1.9 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16804-3E
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91210 Series
MB91F211B/213A/F213A/F218S/V210
■ DESCRIPTIONS
MB91210 series is Fujitsu Microelectronics's general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed real-time processing of consumer appliances. This
microcontroller uses FR60Lite as its CPU, compatible with other products in the FR* family.
This series incorporates a built-in UART with LIN function and CAN controller.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ FEATURES
• FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency : 40 MHz (Source oscillation is 4 MHz - PLL clock multiplier system)
• 16-bit fixed length instructions (basic instructions), one instruction per cycle
• Memory-memory transfer instructions, bit processing instructions, barrel shift instructions
- Instructions adapted for embedded applications
• Function entry/exit instructions, multiple-register load/store instructions
- Instructions supporting high-level language
• Register interlock function
- Easier assembler coding enabled
• Built-in multiplier supported at the instruction level
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction compatible with the FR family
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.2
MB91210 Series
• Internal ROM size & ROM type
• Mask ROM
: 544 Kbytes (MB91213A)
• Flash Memory
: 288 Kbytes (MB91F211B)
: 544 Kbytes (MB91F213A/F218S)
• Internal RAM size
: 24 Kbytes (MB91213A/F213A/F218S)
: 16 Kbytes (MB91F211B)
• DMA Controller
• Capable of simultaneous operation of up to 5 channels
• Two transfer sources (internal peripheral/software)
• Bit Search Module (for REALOS)
• Search for the position of the first bit that changes from “1” to “0” in one word, from the MSB
• UART with LIN function (7 channels)
• Asynchronous clock communication (start-stop synchronization), synchronous clock communication
• Synch-Break detection
• Dedicated built-in baud-rate generator for each channel
• SPI compliant (Mode 2 : clock synchronous communication mode)
• CAN Controller (3 channels)
• Maximum transfer rate : 1 Mbps
• 32 message buffer
• Timers
• 16-bit reload timer (3 channels)
Selectable internal clock from 2/8/32 divisions
• 16-bit free-run timer (4 channels)
• Output compare (8 channels)
• Input capture (8 channels)
• 8/16-bit PPG (16 channels/8 channels)
Selectable clock source from 1/2/16/64 division of peripheral clock
• Interrupt Controller
• Interrupts from internal peripherals
• Priority level can be set by software (16 levels)
• External Interrupt (16 channels)
• Selectable input from several pins
• Can be used as CAN WAKEUP
Noise filter is inserted to CAN WAKEUP (Typ 4 µs)
• A/D Converter (32 channels)
• 10-bit resolution
• Sequential comparison
Conversion time : 3 µs
• Conversion modes (single conversion mode and scan conversion mode)
• Activation trigger (software/external trigger/peripheral interrupt)
• Other Interval Timer/Counter
• 16-bit timebase timer/watchdog timer
(Continued)
2
DS07-16804-3E
MB91210 Series
(Continued)
• Other Features
• Has a built-in oscillation circuit as a clock source, and also can select PLL multiplier
• INITX is provided as a reset pin
• Additionally, a watchdog timer reset and software resets are provided
• Stop mode, sleep mode and real time clock mode supported as low-power consumption modes. Low-power
operation using 32 kHz CPU operation enabled
• Gear function
Clock can be generated from various combinations of PLL multiplier setting (1/2/4/8/10) and division setting
(1 to 16) for each clock
• Built-in timebase timer
• Package : LQFP-100, LQFP-144
• CMOS technology (0.18 µm)
• Power supply voltage : 3.5 V to 5.5 V
1.8 V is supplied to internal circuit from step-down circuit
• Comparison of Functions
MB91V210
MB91F211B
MB91F213A
Evaluation product
Flash memory
product
Flash
memory
product
BGA-420
LQFP-100
LQFP-144
External SRAM
288 Kbytes
544 Kbytes
4 Kbytes + 32 Kbytes
4 Kbytes + 12 Kbytes
4 Kbytes + 20 Kbytes
External interrupt
16 channels
16 channels
16 channels
DMA Controller
5 channels
5 channels
5 channels
External
sub-clock
Correspondence
Correspondence
Suspected
sub-clock
Non-correspondence
Correspondence
Non-correspondence
Yes
Yes
Yes
3 channels
(128 msg/ch)
1 channel (32 msg/ch)
3 channels (32 msg/ch)
UART with LIN
function
7 channels
4 channels
(LIN corresponding)
1 channel
(LIN non-corresponding)
7 channels
Reload Timer
3 channels
3 channels
3 channels
Free-run timer
4 channels
2 channels
4 channels
ICU
8 channels
4 channels
8 channels
OUT
8 channels
4 channels
8 channels
8/16bits PPG
8bits × 16 channels
(16bits × 8 channels)
8bits × 8 channels
(16bits × 4 channels)
8bits × 16 channels
(16bits × 8 channels)
A/D Converter
32 channels
16 channels
32 channels
Package
ROM/Flash size
RAM size
RTC
CAN Controller
DS07-16804-3E
MB91213A MB91F218S
Flash
memory
product
Mask ROM
product
Correspondence
Non-correspondence
3
MB91210 Series
■ PIN ASSIGNMENT
•MB91F211B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P44/IN0
P43
P42
P41
P40
P17/SCK4
P16/SOT4
P15/SIN4
VCC
VSS
P14/SCK3
P13/SOT3
P12/SIN3
P11/TOT1
P10/TIN1
P07/INT15R
P06/INT14R
P05/INT13R
P04/INT12R
P03/INT11R
P02/INT10R
P01/INT9R
P00/INT8R
X1A (P73)
X0A (P72)
(TOP VIEW)
UART RLT
INT
INT
OUT
CAN UART
LQFP-100
RLT UART UART
PPG
ICU
UART
FRT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(PPG)
RLT
ADC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
X1
X0
MD3
MD2
MD1
MD0
INITX
PD7/SCK1
PD6/SOT1
PD5/SIN1
PD4/SCK0
PD3/SOT0
PD2/SIN0
PD1/TOT0
PD0/TIN0/ATGX
VCC
VSS
PB7/INT7R
PB6/INT6R
PB5/INT5R
PB4/INT4R
PB3/INT3R
PB2/INT2R
PB1/INT1R
VCC
P82
P83
P84/TIN2
P85/TOT2
P90/AN0/PPG0R
P91/AN1/PPG2R
P92/AN2/PPG4R
P93/AN3/PPG6R
P94/AN4
P95/AN5
P96/AN6
P97/AN7
AVCC
AVSS/AVRL
AVRH
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
PA4/AN12
PA5/AN13
PA6/AN14
PA7/AN15
PB0/INT0R
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P45/IN1
P46/IN2
P47/IN3
P50/PPG1
P51/PPG3
P52/PPG5
P53/PPG7
P54
P55
P56
P57
P60
PE0/SIN2
PE1/SOT2
PE2/SCK2
P70/RX0/INT8
P71/TX0
P74/OUT0
P75/OUT1
P76/OUT2
P77/OUT3
P80/FRCK0
P81/FRCK1
C
VSS
(FPT-100P-M20)
4
DS07-16804-3E
VCC
P81/FRCK1
P82/FRCK2
P83/FRCK3
P84/TIN2
P85/TOT2
P90/AN0/PPG0R
P91/AN1/PPG2R
P92/AN2/PPG4R
P93/AN3/PPG6R
P94/AN4/PPG8R
P95/AN5/PPGAR
P96/AN6/PPGCR
P97/AN7/PPGER
PA0/AN8/SIN2R
PA1/AN9/SOT2R
PA2/AN10/SCK2R
PA3/AN11
PA4/AN12
PA5/AN13
PA6/AN14
PA7/AN15
AVCC
AVSS/AVRL
AVRH
PB0/AN16/INT0R
PB1/AN17/INT1R
PB2/AN18/INT2R
PB3/AN19/INT3R
PB4/AN20/INT4R
PB5/AN21/INT5R
PB6/AN22/ITN6R
PB7/AN23/INT7R
PC0/AN24
PC1/AN25
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
P37/INT15
P40/PPG9
P41/PPGB
P42/PPGD
P43/PPGF
P44/IN0
P45/IN1
P46/IN2
P47/IN3
P50/PPG1
P51/PPG3
P52/PPG5
P53/PPG7
P54/IN4
P55/IN5
P56/IN6
P57/IN7
P60/OUT6
P61/OUT7
P62
P63
VSS
VCC
P64
P70/RX0/INT8
P71/TX0
P72/RX1/INT9
P73/TX1
P74/OUT0
P75/OUT1
P76/OUT2
P77/OUT3
P80/FRCK0
C
VSS
DS07-16804-3E
OUT
FRT RLT
INT
PPG
ICU
PPG
PPG
LQFP-144
(PPG)
(UART)
RLT UART UARTUART
ICU
INT
ADC
FRT
CAN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
OUT
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS
P36/INT14
P35/INT13
P34/INT12
P33/INT11
P32/INT10
P31/TX2
P30/RX2/INT10C
P27/PPGE
P26/PPGC
P25/PPGA
P24/PPG8
P23/PPG6
P22/PPG4
P21/PPG2
P20/PPG0
P17/SCK4
P16/SOT4
P15/SIN4
P14/SCK3
P13/SOT3
P12/SIN3
P11/TOT1
P10/TIN1
P07/OUT5/INT15R
P06/OUT4/INT14R
P05/SCK6/INT13R
P04/SOT6/INT12R
P03/SIN6/INT11R
P02/SCK5/INT10R
P01/SOT5/INT9R
P00/SIN5/INT8R
VCC
VSS
X1A
X0A
MB91210 Series
•MB91213A/F213A/F218S
(TOP VIEW)
UART UART RLT OUT UART UART
(INT)
ADC
(INT)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
X1
X0
MD3
MD2
MD1
MD0
INITX
PF7/INT7
PF6/INT6
PF5/INT5
PF4/INT4
PF3/INT3
PF2/INT2
PF1/INT1
VCC
VSS
PF0/INT0
PE2/SCK2
PE1/SOT2
PE0/SIN2
PD7/SCK1
PD6/SOT1
PD5/SIN1
PD4/SCK0
PD3/SOT0
PD2/SIN0
PD1/TOT0
PD0/TIN0/ATGX
PC7/AN31
PC6/AN30
PC5/AN29
PC4/AN28
PC3/AN27
PC2/AN26
VCC
(FPT-144P-M08)
5
MB91210 Series
■ PIN DESCRIPTIONS
• Pin Functions
Pin no.
LQFP*
1
LQFP*
2
Pin name
Function
name
I/O circuit
type*3
Function
73
106
X0
X0
74
107
X1
X1
OA
OB
68
101
INITX
INITX
D
System reset input pin
72
105
MD3
MD3
E
Operation mode input pin
MD2 to MD0
C
Operation mode input pins
WA
WB
71 to 69
104 to 102 MD2 to MD0
76
109
X0A
X0A
77
110
X1A
X1A
P00
78
113
P00
SIN5*
A
P01
SOT5*5
A
P02
SCK5*5
A
P03
General purpose I/O port
5
SIN6*
A
INT11R
117
P04
SOT6*
General purpose I/O port
5
A
INT12R
118
P05
General purpose I/O port
SCK6*5
A
INT13R
119
P06
General purpose I/O port
OUT4*5
A
INT14R
120
P07
General purpose I/O port
5
OUT5*
A
INT15R
86
121
P10
P10
TIN1
OUT4 output
External interrupt 14 input (select with P36)
P07
85
UART6 clock I/O
External interrupt 13 input (select with P35)
P06
84
UART6 data output
External interrupt 12 input (select with P34)
P05
83
UART6 data input
External interrupt 11 input (select with P33)
P04
82
UART5 clock I/O
External interrupt 10 input (select with P32)
P03
116
UART5 data output
General purpose I/O port
INT10R
81
UART5 data input
External interrupt 9 input (select with P72)
P02
115
Sub-oscillation output pin
General purpose I/O port
INT9R
80
Sub-oscillation input pin
External interrupt 8 input (select with P70)
P01
114
Oscillator output pin
General purpose I/O port
5
INT8R
79
Oscillator input pin
OUT5 output
External interrupt 15 input (select with P37)
A
General purpose I/O port
External event input of reload timer 1
(Continued)
6
DS07-16804-3E
MB91210 Series
Pin no.
Pin name
LQFP*1
LQFP*2
87
122
P11
88
123
P12
89
124
P13
90
125
P14
93
126
P15
94
127
P16
95
128
P17
⎯
129
P20
⎯
130
P21
⎯
131
P22
⎯
132
P23
⎯
133
P24
⎯
134
P25
⎯
135
P26
⎯
136
P27
Function
name
P11
TOT1
P12
SIN3
P13
SOT3
P14
SCK3
P15
SIN4
P16
SOT4
P17
SCK4
P20
PPG0
P21
PPG2
P22
PPG4
P23
PPG6
P24
PPG8
P25
PPGA
P26
PPGC
P27
PPGE
I/O circuit
type*3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
P30
⎯
137
P30
RX2
138
P31
P31
TX2
General purpose I/O port
Reload timer 1 output
General purpose I/O port
UART3 data input
General purpose I/O port
UART3 data output
General purpose I/O port
UART3 clock I/O
General purpose I/O port
UART4 data input
General purpose I/O port
UART4 data output
General purpose I/O port
UART4 clock I/O
General purpose I/O port
PPG0 output
General purpose I/O port
PPG2 output
General purpose I/O port
PPG4 output
General purpose I/O port
PPG6 output
General purpose I/O port
PPG8 output
General purpose I/O port
PPGA output
General purpose I/O port
PPGC output
General purpose I/O port
PPGE output
General purpose I/O port
A
INT10C
⎯
Function
CAN2 input
External interrupt 10 input (select with P32)
A
General purpose I/O port
CAN2 output
(Continued)
DS07-16804-3E
7
MB91210 Series
Pin no.
Pin name
LQFP*1
LQFP*2
⎯
139
P32
⎯
140
P33
⎯
141
P34
⎯
142
P35
⎯
143
P36
⎯
2
P37
96
3
P40
97
4
P41
98
5
P42
99
6
P43
100
7
P44
1
8
P45
2
9
P46
3
10
P47
4
11
P50
5
12
P51
6
13
P52
Function
name
P32
A
INT10
P33
A
INT11
P34
A
INT12
P35
A
INT13
P36
A
INT14
P37
A
INT15
P40
PPG9*5
P41
5
PPGB*
P42
PPGD*5
P43
PPGF*
P44
IN0
P45
IN1
P46
IN2
P47
IN3
P50
PPG1
P51
PPG3
P52
PPG5
I/O circuit
type*3
5
A
A
A
A
A
A
A
A
A
A
A
Function
General purpose I/O port
External interrupt 10 input (select with P30)
General purpose I/O port
External interrupt 11 input (select with P03)
General purpose I/O port
External interrupt 12 input (select with P04)
General purpose I/O port
External interrupt 13 input (select with P05)
General purpose I/O port
External interrupt 14 input (select with P06)
General purpose I/O port
External interrupt 15 input (select with P07)
General purpose I/O port
PPG9 output
General purpose I/O port
PPGB output
General purpose I/O port
PPGD output
General purpose I/O port
PPGF output
General purpose I/O port
ICU0 input
General purpose I/O port
ICU1 input
General purpose I/O port
ICU2 input
General purpose I/O port
ICU3 input
General purpose I/O port
PPG1 output
General purpose I/O port
PPG3 output
General purpose I/O port
PPG5 output
(Continued)
8
DS07-16804-3E
MB91210 Series
Pin no.
LQFP*
1
LQFP*
2
Pin name
Function
name
P53
I/O circuit
type*3
General purpose I/O port
7
14
P53
8
15
P54
9
16
P55
10
17
P56
11
18
P57
12
19
P60
⎯
20
P61
⎯
21
P62
P62
A
General purpose I/O port
⎯
22
P63
P63
A
General purpose I/O port
⎯
25
P64
P64
A
General purpose I/O port
PPG7
P54
IN4*5
P55
IN5*
5
P56
IN6*
5
P57
IN7*5
P60
OUT6*5
P61
OUT7
A
Function
A
A
A
A
A
A
P70
16
26
P70
RX0
27
P71
P71
TX0
A
(76) *
28
P72
RX1
A
29
P73
18
30
P74
19
31
P75
20
32
P76
21
33
P77
P73
TX1
P74
OUT0
P75
OUT1
P76
OUT2
P77
OUT3
General purpose I/O port
ICU5 input
General purpose I/O port
ICU6 input
General purpose I/O port
ICU7 input
General purpose I/O port
OUT6 output
General purpose I/O port
OUT7 output
CAN0 input
General purpose I/O port
CAN0 output
General purpose I/O port
A
INT9
(77) *4
ICU4 input
External interrupt 8 input (select with P00)
P72
4
General purpose I/O port
General purpose I/O port
INT8
17
PPG7 output
CAN1 input
External interrupt 9 input (select with P01)
A
A
A
A
A
General purpose I/O port
CAN1 output
General purpose I/O port
OUT0 output
General purpose I/O port
OUT1 output
General purpose I/O port
OUT2 output
General purpose I/O port
OUT3 output
(Continued)
DS07-16804-3E
9
MB91210 Series
Pin no.
Pin name
LQFP*1
LQFP*2
22
34
P80
23
38
P81
27
39
P82
28
40
P83
29
41
P84
30
42
P85
Function
name
P80
I/O circuit
type*3
A
FRCK0
P81
A
FRCK1
P82
FRCK2*5
P83
5
FRCK3*
P84
A
A
A
TIN2
P85
A
TOT2
P90
31
43
P90
AN0
B
P91
AN1
B
P92
AN2
B
P93
AN3
B
P94
AN4
B
P95
P95
AN5
B
P96
Reload timer 2 output
A/D converter analog input
A/D converter analog input
A/D converter analog input
A/D converter analog input
AN6
PPGCR*5
A/D converter analog input
A/D converter analog input
PPGA output (select with P25)
P96
49
General purpose I/O port
General purpose I/O port
PPGAR*5
37
External event input of reload timer 2
PPG8 output (select with P24)
PPG8R*
48
General purpose I/O port
General purpose I/O port
5
36
External clock input of free-run timer 3
PPG6 output (select with P23)
P94
47
General purpose I/O port
General purpose I/O port
PPG6R
35
External clock input of free-run timer 2
PPG4 output (select with P22)
P93
46
General purpose I/O port
General purpose I/O port
PPG4R
34
External clock input of free-run timer 1
PPG2 output (select with P21)
P92
45
General purpose I/O port
General purpose I/O port
PPG2R
33
External clock input of free-run timer 0
PPG0 output (select with P20)
P91
44
General purpose I/O port
General purpose I/O port
PPG0R
32
Function
General purpose I/O port
B
A/D converter analog input
PPGC output (select with P26)
(Continued)
10
DS07-16804-3E
MB91210 Series
Pin no.
LQFP*1
LQFP*2
Pin name
Function
name
I/O circuit
type*3
P97
38
50
P97
General purpose I/O port
AN7
B
5
PA0
51
PA0
General purpose I/O port
AN8
B
SIN2R*5
52
PA1
General purpose I/O port
AN9
B
SOT2R*5
53
PA2
General purpose I/O port
AN10
B
5
SCK2R*
45
54
PA3
46
55
PA4
47
56
PA5
48
57
PA6
49
58
PA7
PA3
B
AN11
PA4
B
AN12
PA5
B
AN13
PA6
B
AN14
PA7
B
AN15
62
PB0
AN16*
B
PB1
AN17*
B
PB2
AN18*5
B
PB3
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
A/D converter analog input
AN19*5
INT3R
A/D converter analog input
A/D converter analog input
External interrupt 2 input (select with PF2)
PB3
65
General purpose I/O port
General purpose I/O port
INT2R
53
A/D converter analog input
External interrupt 1 input (select with PF1)
PB2
64
General purpose I/O port
General purpose I/O port
5
INT1R
52
A/D converter analog input
External interrupt 0 input (select with PF0)
PB1
63
General purpose I/O port
General purpose I/O port
5
INT0R
51
A/D converter analog input
UART2 clock I/O (select with PE2)
PB0
50
A/D converter analog input
UART2 data output (select with PE1)
PA2
44
A/D converter analog input
UART2 data input (select with PE0)
PA1
43
A/D converter analog input
PPGE output (select with P27)
PPGER*
42
Function
General purpose I/O port
B
A/D converter analog input
External interrupt 3 input (select with PF3)
(Continued)
DS07-16804-3E
11
MB91210 Series
Pin no.
LQFP*1
LQFP*2
Pin name
Function
name
I/O circuit
type*3
PB4
54
66
PB4
General purpose I/O port
AN20*5
B
INT4R
67
PB5
General purpose I/O port
5
AN21*
B
INT5R
68
PB6
General purpose I/O port
AN22*5
B
INT6R
69
PB7
General purpose I/O port
5
AN23*
B
INT7R
⎯
70
PC0
⎯
71
PC1
⎯
74
PC2
⎯
75
PC3
⎯
76
PC4
⎯
77
PC5
⎯
78
PC6
⎯
79
PC7
PC0
AN24
PC1
AN25
PC2
AN26
PC3
AN27
PC4
AN28
PC5
AN29
PC6
AN30
PC7
AN31
80
PD0
TIN0
B
B
B
B
B
B
B
B
81
PD1
62
82
PD2
PD1
TOT0
PD2
SIN0
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A/D converter analog input
General purpose I/O port
A
ATGX
61
A/D converter analog input
External interrupt 7 input (select with PF7)
PD0
60
A/D converter analog input
External interrupt 6 input (select with PF6)
PB7
57
A/D converter analog input
External interrupt 5 input (select with PF5)
PB6
56
A/D converter analog input
External interrupt 4 input (select with PF4)
PB5
55
Function
External event input of reload timer 0
A/D converter external trigger input
A
A
General purpose I/O port
Reload timer 0 output
General purpose I/O port
UART0 data input
(Continued)
12
DS07-16804-3E
MB91210 Series
Pin no.
Pin name
LQFP*1
LQFP*2
63
83
PD3
64
84
PD4
65
85
PD5
66
86
PD6
67
87
PD7
13
88
PE0
14
89
PE1
15
90
PE2
⎯
91
PF0
⎯
94
PF1
⎯
95
PF2
⎯
96
PF3
⎯
97
PF4
⎯
98
PF5
⎯
99
PF6
⎯
100
PF7
26, 59, 92
1, 24, 37,
73, 93, 112
VCC
Function
name
PD3
SOT0
PD4
SCK0
PD5
SIN1
PD6
SOT1
PD7
SCK1
PE0
SIN2
PE1
SOT2
PE2
SCK2
PF0
INT0
PF1
INT1
PF2
INT2
PF3
INT3
PF4
INT4
PF5
INT5
PF6
INT6
PF7
INT7
—
I/O circuit
type*3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
—
Function
General purpose I/O port
UART0 data output
General purpose I/O port
UART0 clock I/O
General purpose I/O port
UART1 data input
General purpose I/O port
UART1 data output
General purpose I/O port
UART1 clock I/O
General purpose I/O port
UART2 data input
General purpose I/O port
UART2 data output
General purpose I/O port
UART2 clock I/O
General purpose I/O port
External interrupt 0 input
General purpose I/O port
External interrupt 1 input
General purpose I/O port
External interrupt 2 input
General purpose I/O port
External interrupt 3 input
General purpose I/O port
External interrupt 4 input
General purpose I/O port
External interrupt 5 input
General purpose I/O port
External interrupt 6 input
General purpose I/O port
External interrupt 7 input
Power supply pins (5 V)
(Continued)
DS07-16804-3E
13
MB91210 Series
(Continued)
Pin no.
Pin name
Function
name
I/O circuit
type*3
23, 36, 72,
92, 108,
111, 144
VSS
—
—
Power supply pins (0 V)
24
35
C
—
—
Power stabilization capacitance pin
39
59
AVCC
—
—
Analog power supply pin
40
60
AVSS
—
—
Analog power supply pin
AVRL
—
—
Base power supply pin for A/D converter
41
61
AVRH
—
—
Base power supply pin for A/D converter
LQFP*1
LQFP*2
25, 58, 75,
91
Function
*1 : FPT-100P-M20
*2 : FPT-144P-M08
*3 : For information about the I/O circuit type, refer to “ ■ I/O CIRCUIT TYPE”.
*4 : MB91F211B can be selected by MD3 to MD0 of mode pins.
*5 : Only MB91213A/F213A/F218S
MD pin
76 pin
77 pin
0000
X0A
X1A
0011
P72
P73
Other than above
Setting prohibited
P72 and P73 function as general-purpose I/O ports only.
14
DS07-16804-3E
MB91210 Series
■ I/O CIRCUIT TYPE
Group
Circuit Type
A
Remarks
Pull-up control
P-ch
P-ch
Pout
Nout
N-ch
N-ch
• CMOS level output
• CMOS hysteresis input
(with standby-time input shutdown
function)
• Automotive input
(with standby-time input shutdown
function)
Pull-down control
CMOS Hysteresis
input
Automotive input
Standby control for
input control
B
Pull-up control
P-ch
P-ch
Pout
Nout
N-ch
N-ch
• CMOS level output
• CMOS hysteresis input
(with standby-time input shutdown
function)
• Automotive input
(with standby-time input shutdown
function)
• A/D analog input
Pull-down control
CMOS Hysteresis
input
Automotive input
Standby control for
input control
Analog input
(Continued)
DS07-16804-3E
15
MB91210 Series
(Continued)
Group
C
Circuit Type
Remarks
Mask ROM product
CMOS Hysteresis input
Flash memory product
N-ch
Mask ROM product
• CMOS hysteresis input
• MD 2 : Pull-down provided
Flash memory product
• High-voltage control signal for test
provided
• MD 2 : No pull-down provided
N-ch
Control signal
N-ch
N-ch
Mode input
N-ch
Diffused resistor
D
CMOS hysteresis input
Pull-up resistor
CMOS Hysteresis
input
E
CMOS hysteresis input
CMOS Hysteresis input
Pull-down resistor
OA
OB
X1
X0
WA
WB
X1A
X0A
16
Oscillation circuit
High speed oscillation feedback
resistance : approx. 1 MΩ
Xout
Standby control
signal
Xout
Oscillation circuit
Low speed oscillation feedback
resistance : approx. 20 MΩ (MB91213A/
F213A/F218S/V210)
approx. 10MΩ (MB91F211B)
Standby control
signal
DS07-16804-3E
MB91210 Series
■ HANDLING DEVICES
• Preventing latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input
and output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may
significantly increase the power supply current, and may cause thermal destruction of an element. When you
use a CMOS IC, be very careful not to exceed the maximum rating.
• Treatment of unused pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or
pull-down with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open.
When set to the input status, it should be handled in the same way as an input pin.
• Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
• About power supply pins
If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential
are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the
pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current
rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low
impedance.
Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC
and VSS pins near this device.
This device incorporates a regulator. When using the device with 5 V power supply, apply that power supply to
the VCC pin and always connect a 1 μF or greater capacitor to the C pin for the regulator.
• Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such
that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the
ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded
for use on the board. Caution must be taken especially when using a pin next to the X0.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.
In addition, a sub clock is required even when a dual clock product is used as a single clock product.
For MB91F218S input "L" level to X0A pin and open X1A pin.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
DS07-16804-3E
17
MB91210 Series
• Notes on using external clock
When an external clock is used, supply the opposite phase clock to X0/X1 pins, simultaneously. Note that input
only to X0 pin cannot be used. Also, when an external clock is used, do not use the STOP mode (oscillation
stop mode). (This is because the X1 pin stops at “H” output in the STOP mode.)
Example Application of External Clock (Normal)
X0
X1
MB91210 series
Note : STOP mode (oscillation stop mode) cannot be used.
• Handling of NC/OPEN pins
Always leave NC pins and OPEN pins open.
• Mode pins (MD0 to MD3)
These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to
test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS
pins is as short as possible and the connection impedance is now.
MD3 pin must be connected to VSS pin directly with a resistance of 0 Ω.
• Power-on
Upon power-on, INITX pin must have been set to “L” level.
• Source oscillation input upon power-on
Upon power-on, never fail to input the clock until the oscillation stabilization wait is cancelled.
• About Flash write
Note that Flash write/erase is not possible in the sub mode.
• Treatment of power supply pins on A/D converter
Connect to ensure “AVCC = VCC and AVSS = VSS” even if the A/D converter is not in use.
• Power-on sequence for power supply analog input of A/D converter
Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 31) after turning
on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before
turning off the digital power supply (VCC). In so doing, the power supply must be turn on and off so that AVRH
does not exceed AVCC. Even when using a pin shared with analog input as an input port, ensure that the input
voltage does not exceed AVCC (There is no problem in turning on or off the A/D converter (AVCC and AVRH) and
digital power supplies at the same time).
• Caution on operations during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the
microcontroller may continue to operate at the free-running frequency of the PLL’s internal self-oscillating oscillator circuit. Performance of this operation is not guaranteed.
18
DS07-16804-3E
MB91210 Series
■ BLOCK DIAGRAM
FR60Lite
CPU core
Bit search
D-bus RAM
Bus converter
Flash
DMA controller
F-bus RAM
RX0 to RX2
TX0 to TX2
CAN
32
16 adapter
X0, X1
X0A, X1A
MD0 to MD3
Clock
control
PORT I/F
PORT
INITX
Interrupt
controller
INT0 to INT15
(INT0R to INT15R)
INT10C
SIN0 to SIN6 (SIN2R)
SOT0 to SOT6 (SOT2R)
SCK0 to SCK6 (SCK2R)
Reload timer
TIN0 to TIN2
TOT0 to TOT2
Input capture
IN0 to IN7
Free-run timer
FRCK0 to FRCK3
External interrupt
UART
BRG for UART
Output compare
OUT0 to OUT7
Real-time clock
8/16 bits PPG
AN0 to AN31
ATGX
DS07-16804-3E
10 bits A/D
converter
PPG0 to PPGF
(PPG0R, 2R, 4R,
PPG6R, 8R, AR,
PPGCR, ER)
19
MB91210 Series
■ MEMORY SPACE
• Memory map
0000 0000H
MB91V210
MB91F211B
MB91213A
MB91F213A
MB91F218S
I/O
I/O
I/O
I/O
I/O
I/O
Access prohibit
Access prohibit
Access prohibit
Direct addressing
area
0000 0400H
0001 0000H
0002 0000H
0002 0100H
0002 0300H
0003 8000H
0003 B000H
0003 D000H
CAN
Access prohibit
F- bus RAM
CAN
CAN
Access prohibit
Access prohibit
F- bus RAM
F- bus RAM
D- bus RAM
D- bus RAM
0004 0000H
0004 1000H
D- bus RAM
Access prohibit
0005 0000H
Access prohibit
Access prohibit
0007 8000H
External SRAM
000B 8000H
Flash memory
Mask ROM/
Flash memory
0010 0000H
Access prohibit
20
Access prohibit
Access prohibit
DS07-16804-3E
MB91210 Series
■ MODE SETTINGS
In the FR family, the operating mode is set by the mode pins (MD3, 2, 1, 0) and the mode register (MODR).
• Mode pins
There are four mode pins (MD3 to MD0) to specify how to fetch the mode vector.
Settings other than these in the table are prohibited.
Mode pin
MD3 MD2 MD1 MD0
Mode name
Reset vector
access area
0
0
0
0
Internal ROM mode vector
Internal
0
0
0
1
External ROM mode vector
External
Remarks
Setting is prohibited in this device.
Note: In the FR family, the external mode vector fetch by a multiplex bus is not supported.
• Mode data
Data written to the mode register by a mode vector fetch is called mode data.
After an operating mode has been set in the mode register (MODR), the device operates in that operating mode.
The mode data is set by all reset sources. User programs cannot set data to the mode register.
Detailed description of mode data
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
ROM
WTH
WTH
Operation mode setting bits
[bit7 to bit3] Reserved bits
Always set the value to “00000B”.
Normal operation is not guaranteed when a value other than “00000B” is set.
[bit2] ROMA (Internal ROM enable bit)
This bit sets whether to enable F-bus ROM areas.
ROMA
Function
0
External ROM mode
Internal ROM area (50000H to FFFFFH) becomes the external area.
1
Internal ROM mode
F-bus ROM is enabled.
DS07-16804-3E
Remarks
21
MB91210 Series
[bit1, bit0] WTH1, WTH0 (Bus width specification bits)
These bits set the bus width specification in external bus mode.
In external bus mode, this value is set in the DBW0 bit of ACR0 (CS0 area).
WTH1
WTH0
Function
22
Remarks
0
0
8-bit bus width
Setup prohibited
0
1
16-bit bus width
Setup prohibited
1
0
—
Setup prohibited
1
1
Single-chip mode
Single-chip mode
DS07-16804-3E
MB91210 Series
■ I/O MAP
[How to read the map]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
Block
T-unit
Port data register
Read/Write attribute, Access unit
(B : byte, H : halfword, W : word)
Initial value after reset
Register name (First-column register at address 4n; second-column
register at 4n + 1, etc.)
Location of left-most register (When using word access, the register in
column 1 is in the MSB side of the data.)
Notes: Initial values of register bits are represented as follows :
• “1” : Initial value “1”
• “0” : Initial value “0”
• “X” : Initial value “undefined”
• “-” : No physical register present at this location.
Access by any undescribed data is prohibited.
DS07-16804-3E
23
MB91210 Series
Address
Register
Block
+0
+1
+2
+3
000000H
PDR0
(R/W) B, H, W
XXXXXXXX
PDR1
(R/W) B, H, W
XXXXXXXX
PDR2
(R/W) B, H, W
XXXXXXXX
PDR3
(R/W) B, H, W
XXXXXXXX
000004H
PDR4
(R/W) B, H, W
XXXXXXXX
PDR5
(R/W) B, H, W
XXXXXXXX
PDR6
(R/W) B, H, W
---XXXXX
PDR7
(R/W) B, H, W
XXXXXXXX
000008H
PDR8
(R/W) B, H, W
--XXXXXX
PDR9
(R/W) B, H, W
XXXXXXXX
PDRA
(R/W) B, H, W
XXXXXXXX
PDRB
(R/W) B, H, W
XXXXXXXX
00000CH
PDRC
(R/W) B, H, W
XXXXXXXX
PDRD
(R/W) B, H, W
XXXXXXXX
PDRE
(R/W) B, H, W
-----XXX
PDRF
(R/W) B, H, W
XXXXXXXX
000010H
to
00003CH
⎯
⎯
⎯
⎯
000040H
EIRR0
(R/W) B, H, W
00000000
ENIR0
(R/W) B, H, W
00000000
ELVR0
(R/W) B, H, W
00000000 00000000
External interrupt
(INT0 to INT7)
000044H
DICR
(R/W) B, H, W
-------0
HRCL
(R/W, R) B
0--11111
⎯
Delay interrupt
module/
Hold Request
000048H
00004CH
000050H
000054H
000058H
TMRLR0
(W) H, W
XXXXXXXX XXXXXXXX
⎯
⎯
TMRLR1
(W) H, W
XXXXXXXX XXXXXXXX
⎯
⎯
TMRLR2
(W) H, W
XXXXXXXX XXXXXXXX
TMR0
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR0
(R/W, R) B, H, W
----0000 00000000
TMR1
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR1
(R/W, R) B, H, W
----0000 00000000
TMR2
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR2
(R/W, R) B, H, W
----0000 00000000
00005CH
⎯
⎯
000060H
SCR0
(R/W, W) B, H, W
00000000
SMR0
(R/W, W) B, H, W
00000000
SSR0
(R/W, R) B, H, W
00001000
RDR0/TDR0
(R/W) B, H, W
00000000
000064H
ESCR0
(R/W) B, H, W
00000100
ECCR0
(R/W, R, W) B, H, W
000000XX
BGR10
(R/W) B, H, W
10000000
BGR00
(R/W) B, H, W
00000000
Port Data Register
Reserved
Reload timer 0
Reload timer 1
Reload timer 2
UART 0
(Continued)
24
DS07-16804-3E
MB91210 Series
Register
Address
+0
+1
+2
+3
000068H
SCR5
(R/W, W) B, H, W
00000000
SMR5
(R/W, W) B, H, W
00000000
SSR5
(R/W, R) B, H, W
00001000
RDR5/TDR5
(R/W) B, H, W
00000000
00006CH
ESCR5
(R/W) B, H, W
00000100
ECCR5
(R/W, R, W) B, H, W
000000XX
BGR15
(R/W) B, H, W
10000000
BGR05
(R/W) B, H, W
00000000
000070H
SCR6
(R/W, W) B, H, W
00000000
SMR6
(R/W, W) B, H, W
00000000
SSR6
(R/W, R) B, H, W
00001000
RDR6/TDR6
(R/W) B, H, W
00000000
000074H
ESCR6
(R/W) B, H, W
00000100
ECCR6
(R/W, R, W) B, H, W
000000XX
BGR16
(R/W) B, H, W
10000000
BGR06
(R/W) B, H, W
00000000
000078H
to
0000ACH
⎯
⎯
⎯
⎯
0000B0H
SCR1
(R/W, W) B, H, W
00000000
SMR1
(R/W, W) B, H, W
00000000
SSR1
(R/W, R) B, H, W
00001000
RDR1/TDR1
(R/W) B, H, W
00000000
0000B4H
ESCR1
(R/W) B, H, W
00000100
ECCR1
(R/W, R, W) B, H, W
000000XX
BGR11
(R/W) B, H, W
10000000
BGR01
(R/W) B, H, W
00000000
0000B8H
SCR2
(R/W, W) B, H, W
00000000
SMR2
(R/W, W) B, H, W
00000000
SSR2
(R/W, R) B, H, W
00001000
RDR2/TDR2
(R/W) B, H, W
00000000
0000BCH
ESCR2
(R/W) B, H, W
00000100
ECCR2
(R/W, R, W) B, H, W
000000XX
BGR12
(R/W) B, H, W
10000000
BGR02
(R/W)B, H, W
00000000
0000C0H
SCR3
(R/W, W) B, H, W
00000000
SMR3
(R/W, W) B, H, W
00000000
SSR3
(R/W, R) B, H, W
00001000
RDR3/TDR3
(R/W) B, H, W
00000000
0000C4H
ESCR3
(R/W) B, H, W
00000100
ECCR3
(R/W, R, W) B, H, W
000000XX
BGR13
(R/W) B, H, W
10000000
BGR03
(R/W) B, H, W
00000000
0000C8H
SCR4
(R/W, W) B, H, W
00000000
SMR4
(R/W, W) B, H, W
00000000
SSR4
(R/W, R) B, H, W
00001000
RDR4/TDR4
(R/W) B, H, W
00000000
0000CCH
ESCR4
(R/W) B, H, W
00000100
ECCR4
(R/W, R, W) B, H, W
000000XX
BGR14
(R/W) B, H, W
10000000
BGR04
(R/W) B, H, W
00000000
0000D0H
EIRR1
(R/W) B, H, W
00000000
ENIR1
(R/W) B, H, W
00000000
ELVR1
(R/W) B, H, W
00000000 00000000
Block
UART 5
UART 6
Reserved
UART 1
UART 2
UART 3
UART 4
External interrupt
(INT8 to INT15)
(Continued)
DS07-16804-3E
25
MB91210 Series
Address
Register
+0
+1
+2
+3
Block
0000D4H
TCDT0
(R/W) H, W
00000000 00000000
⎯
TCCS0
(R/W) B, H, W
00000000
Free-run Timer 0
0000D8H
TCDT1
(R/W) H, W
00000000 00000000
⎯
TCCS1
(R/W) B, H, W
00000000
Free-run Timer 1
0000DCH
TCDT2
(R/W) H, W
00000000 00000000
⎯
TCCS2
(R/W) B, H, W
00000000
Free-run Timer 2
0000E0H
TCDT3
(R/W) H, W
00000000 00000000
⎯
TCCS3
(R/W) B, H, W
00000000
Free-run Timer 3
0000E4H
IPCP1
(R) H, W
XXXXXXXX XXXXXXXX
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
⎯
⎯
IPCP3
(R) H, W
XXXXXXXX XXXXXXXX
⎯
⎯
IPCP5
(R) H, W
XXXXXXXX XXXXXXXX
⎯
⎯
IPCP7
(R) H, W
XXXXXXXX XXXXXXXX
IPCP0
(R) H, W
XXXXXXXX XXXXXXXX
⎯
ICS01
(R/W) B, H, W
00000000
IPCP2
(R) H, W
XXXXXXXX XXXXXXXX
⎯
ICS23
(R/W) B, H, W
00000000
IPCP4
(R) H, W
XXXXXXXX XXXXXXXX
⎯
ICS45
(R/W) B, H, W
00000000
IPCP6
(R) H, W
XXXXXXXX XXXXXXXX
000100H
⎯
⎯
⎯
ICS67
(R/W) B, H, W
00000000
000104H
⎯
⎯
⎯
⎯
Input Capture 0, 1
Input Capture 2, 3
Input Capture 4, 5
Input Capture 6, 7
Reserved
000108H
OCCP1
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP0
(R/W) H, W
XXXXXXXX XXXXXXXX
Output Compare
0, 1
00010CH
OCCP3
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP2
(R/W) H, W
XXXXXXXX XXXXXXXX
Output Compare
2, 3
(Continued)
26
DS07-16804-3E
MB91210 Series
Register
Address
+0
+1
+2
+3
Block
000110H
OCS23
(R/W) B, H, W
11101100 00001100
OCS01
(R/W) B, H, W
11101100 00001100
Output Compare
Cntl 0 to Cntl 3
000114H
OCCP5
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP4
(R/W) H, W
XXXXXXXX XXXXXXXX
Output Compare
4, 5
000118H
OCCP7
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP6
(R/W) H, W
XXXXXXXX XXXXXXXX
Output Compare
6, 7
00011CH
OCS67
(R/W) B, H, W
11101100 00001100
OCS45
(R/W) B, H, W
11101100 00001100
Output Compare
Cntl 4 to Cntl 7
000120H
to
000140H
⎯
⎯
000144H
⎯
WTDBL
(R/W) B
------00
000148H
⎯
WTBR2
(R/W) B
---XXXXX
WTBR1
(R/W) B
XXXXXXXX
WTBR0
(R/W) B
XXXXXXXX
00014CH
WTHR
(R/W) B, H
---XXXXX
WTMR
(R/W) B, H
--XXXXXX
WTSR
(R/W) B
--XXXXXX
⎯
ADERH
(R/W) B, H, W
00000000 00000000
000150H
⎯
⎯
WTCR
(R/W, R) B, H
00000000 000-00-0
ADCS1
(R/W) B, H, W
00000000
ADCS0
(R/W, R) B, H, W
00000000
ADCR1
(R) B, H, W
------XX
ADCR0
(R) B, H, W
XXXXXXXX
000158H
ADCT1
(R/W) B, H, W
00010000
ADCT0
(R/W) B, H, W
00101100
ADSCH
(R/W) B, H, W
---00000
ADECH
(R/W) B, H, W
---00000
00015CH
⎯
CUCR
(R/W, R) B, H, W
00000000
000160H
000164H
to
0001A4H
⎯
⎯
Real-time Clock
ADERL
(R/W) B, H, W
00000000 00000000
000154H
CUTR1
(R) B, H, W
00000000 00000000
Reserved
CUTD
(R/W) B, H, W
10000000 00000000
CUTR2
(R) B, H, W
00000000 00000000
⎯
⎯
A/D Converter
Sub Clock
Calibration unit
Reserved
(Continued)
DS07-16804-3E
27
MB91210 Series
Address
Register
+0
+1
+2
+3
0001A8H
CANPRE
(R/W, R) B, H, W
00000000
⎯
0001ACH
⎯
⎯
⎯
⎯
0001B0H
PRLH0
(R/W) B, H, W
XXXXXXXX
PRLL0
(R/W) B, H, W
XXXXXXXX
PRLH1
(R/W) B, H, W
XXXXXXXX
PRLL1
(R/W) B, H, W
XXXXXXXX
0001B4H
PRLH2
(R/W) B, H, W
XXXXXXXX
PRLL2
(R/W) B, H, W
XXXXXXXX
PRLH3
(R/W) B, H, W
XXXXXXXX
PRLL3
(R/W) B, H, W
XXXXXXXX
0001B8H
PPGC0
(R/W) B, H, W
0000000X
PPGC1
(R/W) B, H, W
0000000X
PPGC2
(R/W) B, H, W
0000000X
PPGC3
(R/W) B, H, W
0000000X
0001BCH
⎯
⎯
⎯
⎯
0001C0H
PRLH4
(R/W) B, H, W
XXXXXXXX
PRLL4
(R/W) B, H, W
XXXXXXXX
PRLH5
(R/W) B, H, W
XXXXXXXX
PRLL5
(R/W) B, H, W
XXXXXXXX
0001C4H
PRLH6
(R/W) B, H, W
XXXXXXXX
PRLL6
(R/W) B, H, W
XXXXXXXX
PRLH7
(R/W) B, H, W
XXXXXXXX
PRLL7
(R/W) B, H, W
XXXXXXXX
0001C8H
PPGC4
(R/W) B, H, W
0000000X
PPGC5
(R/W) B, H, W
0000000X
PPGC6
(R/W) B, H, W
0000000X
PPGC7
(R/W) B, H, W
0000000X
0001CCH
⎯
⎯
⎯
⎯
0001D0H
PRLH8
(R/W) B, H, W
XXXXXXXX
PRLL8
(R/W) B, H, W
XXXXXXXX
PRLH9
(R/W) B, H, W
XXXXXXXX
PRLL9
(R/W) B, H, W
XXXXXXXX
0001D4H
PRLHA
(R/W) B, H, W
XXXXXXXX
PRLLA
(R/W) B, H, W
XXXXXXXX
PRLHB
(R/W) B, H, W
XXXXXXXX
PRLLB
(R/W) B, H, W
XXXXXXXX
0001D8H
PPGC8
(R/W) B, H, W
0000000X
PPGC9
(R/W) B, H, W
0000000X
PPGCA
(R/W) B, H, W
0000000X
PPGCB
(R/W) B, H, W
0000000X
0001DCH
⎯
⎯
⎯
⎯
0001E0H
PRLHC
(R/W) B, H, W
XXXXXXXX
PRLLC
(R/W) B, H, W
XXXXXXXX
PRLHD
(R/W) B, H, W
XXXXXXXX
PRLLD
(R/W) B, H, W
XXXXXXXX
0001E4H
PRLHE
(R/W) B, H, W
XXXXXXXX
PRLLE
(R/W) B, H, W
XXXXXXXX
PRLHF
(R/W) B, H, W
XXXXXXXX
PRLLF
(R/W) B, H, W
XXXXXXXX
0001E8H
PPGCC
(R/W) B, H, W
0000000X
PPGCD
(R/W) B, H, W
0000000X
PPGCE
(R/W) B, H, W
0000000X
PPGCF
(R/W) B, H, W
0000000X
EISSR
(R/W) B, H, W
00000000 00000000
Block
Select CAN Clock
Prescaler/external
interrupt
Reserved
PPG 0 to PPG 3
Reserved
PPG 4 to PPG 7
Reserved
PPG 8 to PPG B
Reserved
PPG C to PPG F
(Continued)
28
DS07-16804-3E
MB91210 Series
Register
Address
Block
+0
+1
+2
+3
0001ECH
⎯
⎯
⎯
⎯
Reserved
0001F0H
TRG1
(R/W) B, H, W
00000000
TRG0
(R/W) B, H, W
00000000
REVC1
(R/W) B, H, W
00000000
REVC0
(R/W) B, H, W
00000000
PPG 0 to PPG F
AP/INV
0001F4H
to
0001FCH
⎯
⎯
⎯
⎯
Reserved
000200H
DMACA0
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
000204H
DMACB0
(R/W) B, H, W
00000000 00000000 00000000 00000000
000208H
DMACA1
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
00020CH
DMACB1
(R/W) B, H, W
00000000 00000000 00000000 00000000
000210H
DMACA2
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
000214H
DMACB2
(R/W) B, H, W
00000000 00000000 00000000 00000000
000218H
DMACA3
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
00021CH
DMACB3
(R/W) B, H, W
00000000 00000000 00000000 00000000
000220H
DMACA4
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
000224H
DMACB4
(R/W) B, H, W
00000000 00000000 00000000 00000000
000228H
to
00023CH
⎯
⎯
⎯
DMA Controller
⎯
Reserved
(Continued)
DS07-16804-3E
29
MB91210 Series
Address
Register
+0
+1
+3
DMACR
(R/W, R) B, H, W
00000000 00000000 00000000 00000000
000240H
000244H
to
0003ECH
+2
⎯
⎯
Block
DMA Controller
⎯
⎯
0003F0H
BSD0
(W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1
(R/W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC
(W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR
(R) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Bit Search Module
000400H
DDR0
(R/W) B, H, W
00000000
DDR1
(R/W) B, H, W
00000000
DDR2
(R/W) B, H, W
00000000
DDR3
(R/W) B, H, W
00000000
000404H
DDR4
(R/W) B, H, W
00000000
DDR5
(R/W) B, H, W
00000000
DDR6
(R/W) B, H, W
---00000
DDR7
(R/W) B, H, W
00000000
000408H
DDR8
(R/W) B, H, W
--000000
DDR9
(R/W) B, H, W
00000000
DDRA
(R/W) B, H, W
00000000
DDRB
(R/W) B, H, W
00000000
00040CH
DDRC
(R/W) B, H, W
00000000
DDRD
(R/W) B, H, W
00000000
DDRE
(R/W) B, H, W
-----000
DDRF
(R/W) B, H, W
00000000
000410H
to
00041CH
⎯
⎯
⎯
⎯
000420H
PFR0
(R/W) B, H, W
0000-00-
PFR1
(R/W) B, H, W
00-00-0-
PFR2
(R/W) B, H, W
00000000
PFR3
(R/W) B, H, W
------00
000424H
PFR4
(R/W) B, H, W
00000000
PFR5
(R/W) B, H, W
-0000000
PFR6
(R/W) B, H, W
------00
PFR7
(R/W) B, H, W
00000-0-
000428H
PFR8
(R/W) B, H, W
000-----
PFR9
(R/W) B, H, W
00000000
PFRA
(R/W) B, H, W
-----000
PFRB
(R/W) B, H, W
--------
00042CH
PFRC
(R/W) B, H, W
--------
PFRD
(R/W) B, H, W
00-00-0-
PFRE
(R/W) B, H, W
-----00-
PFRF
(R/W) B, H, W
--------
Data Direction
Register
Reserved
Port Function
Register
(Continued)
30
DS07-16804-3E
MB91210 Series
Register
Address
+0
+1
+2
+3
000430H
to
00043CH
⎯
⎯
⎯
⎯
000440H
ICR00
(R, R/W) B, H, W
---11111
ICR01
(R, R/W) B, H, W
---11111
ICR02
(R, R/W) B, H, W
---11111
ICR03
(R, R/W) B, H, W
---11111
000444H
ICR04
(R, R/W) B, H, W
---11111
ICR05
(R, R/W) B, H, W
---11111
ICR06
(R, R/W) B, H, W
---11111
ICR07
(R, R/W) B, H, W
---11111
000448H
ICR08
(R, R/W) B, H, W
---11111
ICR09
(R, R/W) B, H, W
---11111
ICR10
(R, R/W) B, H, W
---11111
ICR11
(R, R/W) B, H, W
---11111
00044CH
ICR12
(R, R/W) B, H, W
---11111
ICR13
(R, R/W) B, H, W
---11111
ICR14
(R, R/W) B, H, W
---11111
ICR15
(R, R/W) B, H, W
---11111
000450H
ICR16
(R, R/W) B, H, W
---11111
ICR17
(R, R/W) B, H, W
---11111
ICR18
(R, R/W) B, H, W
---11111
ICR19
(R, R/W) B, H, W
---11111
000454H
ICR20
(R, R/W) B, H, W
---11111
ICR21
(R, R/W) B, H, W
---11111
ICR22
(R, R/W) B, H, W
---11111
ICR23
(R, R/W) B, H, W
---11111
000458H
ICR24
(R, R/W) B, H, W
---11111
ICR25
(R, R/W) B, H, W
---11111
ICR26
(R, R/W) B, H, W
---11111
ICR27
(R, R/W) B, H, W
---11111
00045CH
ICR28
(R, R/W) B, H, W
---11111
ICR29
(R, R/W) B, H, W
---11111
ICR30
(R, R/W) B, H, W
---11111
ICR31
(R, R/W) B, H, W
---11111
000460H
ICR32
(R, R/W) B, H, W
---11111
ICR33
(R, R/W) B, H, W
---11111
ICR34
(R, R/W) B, H, W
---11111
ICR35
(R, R/W) B, H, W
---11111
000464H
ICR36
(R, R/W) B, H, W
---11111
ICR37
(R, R/W) B, H, W
---11111
ICR38
(R, R/W) B, H, W
---11111
ICR39
(R, R/W) B, H, W
---11111
000468H
ICR40
(R, R/W) B, H, W
---11111
ICR41
(R, R/W) B, H, W
---11111
ICR42
(R, R/W) B, H, W
---11111
ICR43
(R, R/W) B, H, W
---11111
00046CH
ICR44
(R, R/W) B, H, W
---11111
ICR45
(R, R/W) B, H, W
---11111
ICR46
(R, R/W) B, H, W
---11111
ICR47
(R, R/W) B, H, W
---11111
000470H
to
00047CH
⎯
⎯
⎯
⎯
Block
Reserved
Interrupt Control
Unit
Reserved
(Continued)
DS07-16804-3E
31
MB91210 Series
Address
Register
Block
+0
+1
+2
+3
000480H
RSRR
(R, R/W) B, H, W
X-***-00*2
STCR
(R/W) B, H, W
00110011
TBCR
(R/W, R) B, H, W
00XXXX11
CTBR
(W) B, H, W
XXXXXXXX
000484H
CLKR
(R/W) B, H, W
00000000
WPR
(W) B, H, W
XXXXXXXX
DIVR0
(R/W) B, H, W
00000011
DIVR1
(R/W) B, H, W
00000000
000488H
⎯
⎯
OSCCR
(R/W) B
XXXXXXX0
⎯
00048CH
⎯
⎯
⎯
⎯
Reserved
000490H
OSCR
(R/W, W) B
000XX000
⎯
⎯
⎯
Main Stabilization
Wait Timer
000494H
PLLC
(R/W, R) B, H, W
X1000101
⎯
⎯
⎯
PLL Controller
000498H
to
0004FCH
⎯
⎯
⎯
⎯
Reserved
000500H
PPER0
(R/W) B, H, W
00000000
PPER1
(R/W) B, H, W
00000000
PPER2
(R/W) B, H, W
00000000
PPER3
(R/W) B, H, W
00000000
000504H
PPER4
(R/W) B, H, W
00000000
PPER5
(R/W) B, H, W
00000000
PPER6
(R/W) B, H, W
---00000
PPER7
(R/W) B, H, W
00000000
000508H
PPER8
(R/W) B, H, W
--000000
PPER9
(R/W) B, H, W
00000000
PPERA
(R/W) B, H, W
00000000
PPERB
(R/W) B, H, W
00000000
00050CH
PPERC
(R/W) B, H, W
00000000
PPERD
(R/W) B, H, W
00000000
PPERE
(R/W) B, H, W
-----000
PPERF
(R/W) B, H, W
00000000
000510H
to
00051CH
⎯
⎯
⎯
⎯
Clock Control Unit
Port Pull-up/
Pull-down Enable
Register
Reserved
(Continued)
32
DS07-16804-3E
MB91210 Series
Register
Address
+0
+1
+2
+3
000520H
PPCR0
(R/W) B, H, W
11111111
PPCR1
(R/W) B, H, W
11111111
PPCR2
(R/W) B, H, W
11111111
PPCR3
(R/W) B, H, W
11111111
000524H
PPCR4
(R/W) B, H, W
11111111
PPCR5
(R/W) B, H, W
11111111
PPCR6
(R/W) B, H, W
---11111
PPCR7
(R/W) B, H, W
11111111
000528H
PPCR8
(R/W) B, H, W
--111111
PPCR9
(R/W) B, H, W
11111111
PPCRA
(R/W) B, H, W
11111111
PPCRB
(R/W) B, H, W
11111111
00052CH
PPCRC
(R/W) B, H, W
11111111
PPCRD
(R/W) B, H, W
11111111
PPCRE
(R/W) B, H, W
-----111
PPCRF
(R/W) B, H, W
11111111
000530H
to
00053CH
⎯
⎯
⎯
⎯
000540H
PILR0
(R/W) B, H, W
00000000
PILR1
(R/W) B, H, W
00000000
PILR2
(R/W) B, H, W
00000000
PILR3
(R/W) B, H, W
00000000
000544H
PILR4
(R/W) B, H, W
00000000
PILR5
(R/W) B, H, W
00000000
PILR6
(R/W) B, H, W
---00000
PILR7
(R/W) B, H, W
00000000
000548H
PILR8
(R/W) B, H, W
--000000
PILR9
(R/W) B, H, W
00000000
PILRA
(R/W) B, H, W
00000000
PILRB
(R/W) B, H, W
00000000
00054CH
PILRC
(R/W) B, H, W
00000000
PILRD
(R/W) B, H, W
00000000
PILRE
(R/W) B, H, W
-----000
PILRF
(R/W) B, H, W
00000000
000550H
to
00061CH
⎯
⎯
⎯
⎯
000620H
PIDR0
(R) B, H, W
XXXXXXXX
PIDR1
(R) B, H, W
XXXXXXXX
PIDR2
(R) B, H, W
XXXXXXXX
PIDR3
(R) B, H, W
XXXXXXXX
000624H
PIDR4
(R) B, H, W
XXXXXXXX
PIDR5
(R) B, H, W
XXXXXXXX
PIDR6
(R) B, H, W
---XXXXX
PIDR7
(R) B, H, W
XXXXXXXX
000628H
PIDR8
(R) B, H, W
--XXXXXX
PIDR9
(R) B, H, W
XXXXXXXX
PIDRA
(R) B, H, W
XXXXXXXX
PIDRB
(R) B, H, W
XXXXXXXX
00062CH
PIDRC
(R) B, H, W
XXXXXXXX
PIDRD
(R) B, H, W
XXXXXXXX
PIDRE
(R) B, H, W
-----XXX
PIDRF
(R) B, H, W
XXXXXXXX
000630H
to
000FFCH
⎯
⎯
⎯
⎯
Block
Port Pull-up/
Pull-down Control
Register
Reserved
Port Input Level
Select Register
Reserved
Input Data Direct
Read Register
Reserved
(Continued)
DS07-16804-3E
33
MB91210 Series
Address
Register
+0
+1
+2
001000H
DMASA0
(R/W) W
00000000 00000000 00000000 00000000
001004H
DMADA0
(R/W) W
00000000 00000000 00000000 00000000
001008H
DMASA1
(R/W) W
00000000 00000000 00000000 00000000
00100CH
DMADA1
(R/W) W
00000000 00000000 00000000 00000000
001010H
DMASA2
(R/W) W
00000000 00000000 00000000 00000000
001014H
DMADA2
(R/W) W
00000000 00000000 00000000 00000000
001018H
DMASA3
(R/W) W
00000000 00000000 00000000 00000000
00101CH
DMADA3
(R/W) W
00000000 00000000 00000000 00000000
001020H
DMASA4
(R/W) W
00000000 00000000 00000000 00000000
001024H
DMADA4
(R/W) W
00000000 00000000 00000000 00000000
+3
Block
DMA Controller
001028H
to
006FFCH
⎯
⎯
⎯
⎯
007000H
FLCR
(R/W, R) B, H, W
0000X101
⎯
⎯
⎯
007004H
FLWC
(R/W) B, H, W
01011011
⎯
⎯
⎯
007008H
to
01FFFCH
⎯
⎯
⎯
⎯
Reserved
Flash Interface
Reserved
(Continued)
34
DS07-16804-3E
MB91210 Series
Address
Register
+0
+1
+2
+3
020000H
CTRLR0
(R/W, R) B, H, W
00000000 00000001
STATR0
(R/W, R) B, H, W
00000000 00000000
020004H
ERRCNT0
(R) B, H, W
00000000 00000000
BTR0
(R/W, R) B, H, W
00100011 00000001
020008H
INTR0
(R) B, H, W
00000000 00000000
TESTR0
(R/W, R) B, H, W
00000000 r0000000*3
02000CH
BRPER0
(R, R/W) B, H, W
00000000 00000000
⎯
020010H
IF1CREQ0
(R/W, R) B, H, W
00000000 00000001
IF1CMSK0
(R/W, R) B, H, W
00000000 00000000
020014H
IF1MSK20
(R/W, R) B, H, W
11111111 11111111
IF1MSK10
(R/W) B, H, W
11111111 11111111
020018H
IF1ARB20
(R/W) B, H, W
00000000 00000000
IF1ARB10
(R/W) B, H, W
00000000 00000000
02001CH
IF1MCTR0
(R/W, R) B, H, W
00000000 00000000
020020H
IF1DTA10
(R/W) B, H, W
00000000 00000000
IF1DTA20
(R/W) B, H, W
00000000 00000000
020024H
IF1DTB10
(R/W) B, H, W
00000000 00000000
IF1DTB20
(R/W) B, H, W
00000000 00000000
020028H
to
02002CH
020030H
020034H
020038H
to
02003CH
⎯
⎯
⎯
⎯
⎯
⎯
IF1DTA10
(R/W) B, H, W
00000000 00000000
IF1DTB10
(R/W) B, H, W
00000000 00000000
IF1DTB20
(R/W) B, H, W
00000000 00000000
⎯
⎯
CAN Controller
0
⎯
IF1DTA20
(R/W) B, H, W
00000000 00000000
⎯
Block
⎯
Reserved
CAN Controller
0
Reserved
(Continued)
DS07-16804-3E
35
MB91210 Series
Address
Register
+0
+1
+2
+3
020040H
IF2CREQ0
(R/W, R) B, H, W
00000000 00000001
IF2CMSK0
(R/W, R) B, H, W
00000000 00000000
020044H
IF2MSK20
(R/W, R) B, H, W
11111111 11111111
IF2MSK10
(R/W) B, H, W
11111111 11111111
020048H
IF2ARB20
(R/W) B, H, W
00000000 00000000
IF2ARB10
(R/W) B, H, W
00000000 00000000
02004CH
IF2MCTR0
(R/W, R) B, H, W
00000000 00000000
020050H
IF2DTA10
(R/W) B, H, W
00000000 00000000
IF2DTA20
(R/W) B, H, W
00000000 00000000
020054H
IF2DTB10
(R/W) B, H, W
00000000 00000000
IF2DTB20
(R/W) B, H, W
00000000 00000000
020058H,
02005CH
020060H
020064H
020068H
to
02007CH
020080H
020084H
to
02008CH
020090H
020094H
to
02009CH
0200A0H
⎯
⎯
⎯
⎯
⎯
IF2DTA10
(R/W) B, H, W
00000000 00000000
IF2DTB20
(R/W) B, H, W
00000000 00000000
IF2DTB10
(R/W) B, H, W
00000000 00000000
⎯
TREQR20
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT20
(R) B, H, W
00000000 00000000
⎯
⎯
INTPND20
(R) B, H, W
00000000 00000000
⎯
⎯
TREQR10
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT10
(R) B, H, W
00000000 00000000
⎯
CAN Controller
0
⎯
IF2DTA20
(R/W) B, H, W
00000000 00000000
⎯
Block
⎯
INTPND10
(R) B, H, W
00000000 00000000
Reserved
CAN Controller
0
Reserved
CAN Controller
0
Reserved
CAN Controller
0
Reserved
CAN Controller
0
(Continued)
36
DS07-16804-3E
MB91210 Series
Address
0200A4H
to
0200ACH
0200B0H
0200B4H
to
0200FCH
Register
+0
+1
+2
+3
⎯
⎯
⎯
⎯
MSGVAL20
(R) B, H, W
00000000 00000000
⎯
⎯
MSGVAL10
(R) B, H, W
00000000 00000000
⎯
⎯
020100H
CTRLR1
(R/W, R) B, H, W
00000000 00000001
STATR1
(R/W, R) B, H, W
00000000 00000000
020104H
ERRCNT1
(R) B, H, W
00000000 00000000
BTR1
(R/W, R) B, H, W
00100011 00000001
020108H
INTR1
(R) B, H, W
00000000 00000000
TESTR1
(R/W, R) B, H, W
00000000 r0000000*3
02010CH
BRPER1
(R, R/W) B, H, W
00000000 00000000
⎯
020110H
IF1CREQ1
(R/W, R) B, H, W
00000000 00000001
IF1CMSK1
(R/W, R) B, H, W
00000000 00000000
020114H
IF1MSK21
(R/W, R) B, H, W
11111111 11111111
IF1MSK11
(R/W) B, H, W
11111111 11111111
020118H
IF1ARB21
(R/W) B, H, W
00000000 00000000
IF1ARB11
(R/W) B, H, W
00000000 00000000
02011CH
IF1MCTR1
(R/W, R) B, H, W
00000000 00000000
020120H
IF1DTA11
(R/W) B, H, W
00000000 00000000
IF1DTA21
(R/W) B, H, W
00000000 00000000
020124H
IF1DTB11
(R/W) B, H, W
00000000 00000000
IF1DTB21
(R/W) B, H, W
00000000 00000000
020128H,
02012CH
⎯
⎯
⎯
⎯
Block
Reserved
CAN Controller
0
Reserved
⎯
CAN Controller
1
⎯
⎯
Reserved
(Continued)
DS07-16804-3E
37
MB91210 Series
Address
020130H
020134H
020138H,
02013CH
Register
+0
+1
+2
+3
IF1DTA21
(R/W) B, H, W
00000000 00000000
IF1DTA11
(R/W) B, H, W
00000000 00000000
IF1DTB11
(R/W) B, H, W
00000000 00000000
IF1DTB21
(R/W) B, H, W
00000000 00000000
⎯
⎯
⎯
⎯
020140H
IF2CREQ1
(R/W, R) B, H, W
00000000 00000001
IF2CMSK1
(R/W, R) B, H, W
00000000 00000000
020144H
IF2MSK21
(R/W, R) B, H, W
11111111 11111111
IF2MSK11
(R/W) B, H, W
11111111 11111111
020148H
IF2ARB21
(R/W) B, H, W
00000000 00000000
IF2ARB11
(R/W) B, H, W
00000000 00000000
02014CH
IF2MCTR1
(R/W, R) B, H, W
00000000 00000000
020150H
IF2DTA11
(R/W) B, H, W
00000000 00000000
IF2DTA21
(R/W) B, H, W
00000000 00000000
020154H
IF2DTB11
(R/W) B, H, W
00000000 00000000
IF2DTB21
(R/W) B, H, W
00000000 00000000
020158H,
02015CH
⎯
⎯
⎯
⎯
⎯
IF2DTA21
(R/W) B, H, W
00000000 00000000
IF2DTA11
(R/W) B, H, W
00000000 00000000
020164H
IF2DTB21
(R/W) B, H, W
00000000 00000000
IF2DTB11
(R/W) B, H, W
00000000 00000000
⎯
⎯
⎯
CAN Controller
1
Reserved
CAN Controller
1
⎯
020160H
020168H
to
02017CH
Block
⎯
Reserved
CAN Controller
1
Reserved
(Continued)
38
DS07-16804-3E
MB91210 Series
Address
020180H
020184H
to
02018CH
020190H
020194H
to
02019CH
0201A0H
0201A4H
to
0201ACH
0201B0H
0200B4H
to
0200FCH
Register
+0
+1
TREQR21
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT21
(R) B, H, W
00000000 00000000
⎯
⎯
INTPND21
(R) B, H, W
00000000 00000000
⎯
⎯
MSGVAL21
(R) B, H, W
00000000 00000000
⎯
⎯
+2
+3
TREQR11
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT11
(R) B, H, W
00000000 00000000
⎯
⎯
INTPND11
(R) B, H, W
00000000 00000000
⎯
⎯
MSGVAL11
(R) B, H, W
00000000 00000000
⎯
⎯
020200H
CTRLR2
(R/W, R) B, H, W
00000000 00000001
STATR2
(R/W, R) B, H, W
00000000 00000000
020204H
ERRCNT2
(R) B, H, W
00000000 00000000
BTR2
(R/W, R) B, H, W
00100011 00000001
020208H
INTR2 (R) B, H, W
00000000 00000000
TESTR2
(R/W, R) B, H, W
00000000 r0000000*3
02020CH
BRPER2
(R, R/W) B, H, W
00000000 00000000
⎯
020210H
IF1CREQ2
(R/W, R) B, H, W
00000000 00000001
IF1CMSK2
(R/W, R) B, H, W
00000000 00000000
020214H
IF1MSK22
(R/W, R) B, H, W
11111111 11111111
IF1MSK12
(R/W) B, H, W
11111111 11111111
Block
CAN Controller
1
Reserved
CAN Controller
1
Reserved
CAN Controller
1
Reserved
CAN Controller
1
Reserved
CAN Controller
2
⎯
(Continued)
DS07-16804-3E
39
MB91210 Series
Address
Register
+0
+1
020218H
IF1ARB22
(R/W) B, H, W
00000000 00000000
02021CH
IF1MCTR2
(R/W, R) B, H, W
00000000 00000000
+2
+3
IF1ARB12
(R/W) B, H, W
00000000 00000000
⎯
⎯
020220H
IF1DTA12
(R/W) B, H, W
00000000 00000000
IF1DTA22
(R/W) B, H, W
00000000 00000000
020224H
IF1DTB12
(R/W) B, H, W
00000000 00000000
IF1DTB22
(R/W) B, H, W
00000000 00000000
020228H,
02022CH
020230H
020234H
020238H,
02023CH
⎯
⎯
⎯
⎯
IF1DTA22
(R/W) B, H, W
00000000 00000000
IF1DTA12
(R/W) B, H, W
00000000 00000000
IF1DTB22
(R/W) B, H, W
00000000 00000000
IF1DTB12
(R/W) B, H, W
00000000 00000000
⎯
⎯
Block
⎯
⎯
020240H
IF2CREQ2
(R/W, R) B, H, W
00000000 00000001
IF2CMSK2
(R/W, R) B, H, W
00000000 00000000
020244H
IF2MSK22
(R/W, R) B, H, W
11111111 11111111
IF2MSK12
(R/W) B, H, W
11111111 11111111
020248H
IF2ARB22
(R/W) B, H, W
00000000 00000000
IF2ARB12
(R/W) B, H, W
00000000 00000000
02024CH
IF2MCTR2
(R/W, R) B, H, W
00000000 00000000
020250H
IF2DTA12
(R/W) B, H, W
00000000 00000000
IF2DTA22
(R/W) B, H, W
00000000 00000000
020254H
IF2DTB12
(R/W) B, H, W
00000000 00000000
IF2DTB22
(R/W) B, H, W
00000000 00000000
⎯
CAN Controller
2
Reserved
CAN Controller
2
Reserved
CAN Controller
2
⎯
(Continued)
40
DS07-16804-3E
MB91210 Series
(Continued)
Address
020258H,
02025CH
020260H
020264H
020268H
to
02027CH
020280H
020284H
to
02028CH
020290H
020294H
to
02029CH
0202A0H
0202A4H
to
0202ACH
0202B0H
Register
+0
+1
+2
+3
⎯
⎯
⎯
⎯
IF2DTA22
(R/W) B, H, W
00000000 00000000
IF2DTA12
(R/W) B, H, W
00000000 00000000
IF2DTB22
(R/W) B, H, W
00000000 00000000
IF2DTB12
(R/W) B, H, W
00000000 00000000
⎯
⎯
TREQR22
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT22
(R) B, H, W
00000000 00000000
⎯
⎯
INTPND22
(R) B, H, W
00000000 00000000
⎯
⎯
MSGVAL22
(R) B, H, W
00000000 00000000
⎯
⎯
TREQR12
(R) B, H, W
00000000 00000000
⎯
⎯
NEWDT12
(R) B, H, W
00000000 00000000
⎯
⎯
INTPND12
(R) B, H, W
00000000 00000000
⎯
⎯
MSGVAL12
(R) B, H, W
00000000 00000000
Block
Reserved
CAN Controller
2
Reserved
CAN Controller
2
Reserved
CAN Controller
2
Reserved
CAN Controller
2
Reserved
CAN Controller
2
*1 : The lower 16 bits (DTC[15:0]) cannot be accessed in bytes.
*2 : It differs depending on the source.
*3 : As for bit7, the level of the RX pin is read.
DS07-16804-3E
41
MB91210 Series
■ INTERRUPT VECTOR
Interrupt number
Interrupt source
Decimal
Hexa- Interrupt level
decimal
Offset
TBR default address
Reset*
0
00
⎯
3FCH
000FFFFCH
Mode vector*
1
01
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
3ECH
000FFFECH
System reserved
5
05
⎯
3E8H
000FFFE8H
System reserved
6
06
⎯
3E4H
000FFFE4H
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
3D8H
000FFFD8H
System reserved
10
0A
⎯
3D4H
000FFFD4H
System reserved
11
0B
⎯
3D0H
000FFFD0H
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
NMI request (ICE)
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
NMI request
15
0F
15 (FH) Fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART 0 (Reception)
27
1B
ICR11
390H
000FFF90H
UART 0 (Transmission)
28
1C
ICR12
38CH
000FFF8CH
UART 1 (Reception)
29
1D
ICR13
388H
000FFF88H
UART 1 (Transmission)
30
1E
ICR14
384H
000FFF84H
UART 2 (Reception)
31
1F
ICR15
380H
000FFF80H
UART 2 (Transmission)
32
20
ICR16
37CH
000FFF7CH
(Continued)
42
DS07-16804-3E
MB91210 Series
Interrupt number
Interrupt source
HexaDecimal
decimal
Interrupt
level
Offset
TBR default address
CAN 0
33
21
ICR17
378H
000FFF78H
CAN 1
34
22
ICR18
374H
000FFF74H
UART 3/5 (Reception)
35
23
ICR19
370H
000FFF70H
UART 3/5 (Transmission)
36
24
ICR20
36CH
000FFF6CH
UART 4/6 (Reception)
37
25
ICR21
368H
000FFF68H
UART 4/6 (Transmission)
38
26
ICR22
364H
000FFF64H
A/D converter
39
27
ICR23
360H
000FFF60H
RTC/CAN 2
40
28
ICR24
35CH
000FFF5CH
ICU 0
41
29
ICR25
358H
000FFF58H
ICU 1
42
2A
ICR26
354H
000FFF54H
ICU 2/3
43
2B
ICR27
350H
000FFF50H
ICU 4/5/6/7
44
2C
ICR28
34CH
000FFF4CH
FRT 0/1/2/3
45
2D
ICR29
348H
000FFF48H
Main oscillation stabilization wait
timer
46
2E
ICR30
344H
000FFF44H
Time-base timer overflow
47
2F
ICR31
340H
000FFF40H
OUT 0/1/2/3
48
30
ICR32
33CH
000FFF3CH
OUT 4/5/6/7
49
31
ICR33
338H
000FFF38H
PPG 0
50
32
ICR34
334H
000FFF34H
PPG 1
51
33
ICR35
330H
000FFF30H
PPG 2/3
52
34
ICR36
32CH
000FFF2CH
PPG 4/5/6/7
53
35
ICR37
328H
000FFF28H
PPG 8/9/A/B
54
36
ICR38
324H
000FFF24H
PPG C/D/E/F
55
37
ICR39
320H
000FFF20H
External interrupt 8
56
38
ICR40
31CH
000FFF1CH
External interrupt 9
57
39
ICR41
318H
000FFF18H
External interrupt 10
58
3A
ICR42
314H
000FFF14H
External interrupt 11
59
3B
ICR43
310H
000FFF10H
External interrupt 12/13
60
3C
ICR44
30CH
000FFF0CH
External interrupt 14/15
61
3D
ICR45
308H
000FFF08H
DMA (End, Error)
62
3E
ICR46
304H
000FFF04H
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved
(Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
(Continued)
DS07-16804-3E
43
MB91210 Series
(Continued)
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default address
Decimal
Hexadecimal
System reserved
(Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
System reserved
66
42
⎯
2F4H
000FFEF4H
System reserved
67
43
⎯
2F0H
000FFEF0H
System reserved
68
44
⎯
2ECH
000FFEECH
System reserved
69
45
⎯
2E8H
000FFEE8H
System reserved
70
46
⎯
2E4H
000FFEE4H
System reserved
71
47
⎯
2E0H
000FFEE0H
System reserved
72
48
⎯
2DCH
000FFEDCH
System reserved
73
49
⎯
2D8H
000FFED8H
System reserved
74
4A
⎯
2D4H
000FFED4H
System reserved
75
4B
⎯
2D0H
000FFED0H
System reserved
76
4C
⎯
2CCH
000FFECCH
System reserved
77
4D
⎯
2C8H
000FFEC8H
System reserved
78
4E
⎯
2C4H
000FFEC4H
System reserved
79
4F
⎯
2C0H
000FFEC0H
Used in INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
* : Even though the TBR value is changed, fixed addresses, 000FFFFCH and 000FFFF8H, are always used for
the reset vector and the mode vector.
44
DS07-16804-3E
MB91210 Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
Indicates that the input function can be used.
• Output Hi-Z
Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving.
• Output maintained
Indicates the output in the output state existing immediately before this mode is established. If the device
enters this mode with an internal output peripheral operating or while serving as an output port, the output is
performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained.
When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
• Pull-down
Built-in pull-down resistor is valid.
DS07-16804-3E
45
MB91210 Series
Table of Pin Status in Each Mode
• Single chip mode
Pin name
Function name
INITX
INITX
X0
X0
X1
X1
X0A
X0A
X1A
X1A
MD0
MD0
MD1
MD1
MD2
MD2
MD3
MD3
P00
P00/SIN5/INT8R
P01
P01/SOT5/INT9R
P02
P02/SCK5/INT10R
P03
P03/SIN6/INT11R
P04
P04/SOT6/INT12R
P05
P05/SCK6/INT13R
P06
P06/OUT4/INT14R
P07
P07/OUT5/INT15R
P10
P10/TIN1
P11
P11/TOT1
P12
P12/SIN3
P13
P13/SOT3
P14
P14/SCK3
P15
P15/SIN4
P16
P16/SOT4
P17
P17/SCK4
Initial value
INITX = “L” INITX = “H”
Input
enabled
Input
enabled
In sleep state
In stop state
HIZ = 0
HIZ = 1
Input enabled
Input enabled
Pull-down
Pull-down
Input enabled
Input enabled
Input
enabled
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding
status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z
internal input held
P20 to P27/
P20 to P27 PPG0, 2, 4, 6, 8, A,
C, E
(Continued)
46
DS07-16804-3E
MB91210 Series
Pin name
Function name
Initial value
INITX = “L” INITX = “H”
In sleep state
In stop state
HIZ = 0
HIZ = 1
P30
P30/ (RX2) /
(INT10C)
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
P31
P31/ (TX2)
Output Hi-Z
internal input held
P32
P32/INT10
P33 to P37
P33 to P37/
INT11 to INT15
P40 to P43
P40 to P43/
PPG9, B, D, F
P44 to P47
P44 to P47/
IN0 to IN3
P50 to P53
P50 to P53/
PPG1, 3, 5, 7
P54
P54/IN4
P55
P55/IN5
P56
P56/IN6
P57
P57/IN7
P60
P60/OUT6
P61
P61/OUT7
P62
P62
P63
P63
P64
P64
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding
status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z
internal input held
P70
P70/RX0/INT8
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
P71
P71/TX0
Output Hi-Z
internal input held
(Continued)
DS07-16804-3E
47
MB91210 Series
Pin name
Function name
P72
P72/RX1/INT9
P73
P73/TX1
P74 to P77
P74 to P77/
OUT0 to OUT3
P80 to P83
P80 to P83/
FRCK0 to FRCK3
P84
P84/TIN2
P85
P85/TOT2
P90 to P97/PPG0R,
P90 to P97 2R, 4R, 6R, 8R, AR,
CR, ER/AN0 to AN7
PA0
PA0/SIN2R/AN8
PA1
PA1/SOT2R/AN9
PA2
PA2/SCK2R/AN10
PA3 to
PA7
PA3 to PA7/
AN11 to AN15
Initial value
INITX = “L” INITX = “H”
In sleep state
In stop state
HIZ = 0
HIZ = 1
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output Hi-Z
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding
status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z
internal input held
PB0 to
PB7
PB0 to PB7/
INT0R to INT7R/
AN16 to AN23
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
PC0 to
PC7
PC0 to PC7/
AN24 to AN31
Output Hi-Z
internal input held
(Continued)
48
DS07-16804-3E
MB91210 Series
(Continued)
Pin name
Function name
PD0
PD0/TIN0/ATGX
PD1
PD1/TOT0
PD2
PD2/SIN0
PD3
PD3/SOT0
PD4
PD4/SCK0
PD5
PD5/SIN1
PD6
PD6/SOT1
PD7
PD7/SCK1
PE0
PE0/SIN2
PE1
PE1/SOT2
PE2
PE2/SCK2
PF0 to PF7
DS07-16804-3E
PF0 to PF7/
INT0 to INT7
Initial value
INITX = “L” INITX = “H”
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
In sleep state
P:
Immediately
preceding
status held
F:
Normal
operation
performed
In stop state
HIZ = 0
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
HIZ = 1
Output Hi-Z
internal input held
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
49
MB91210 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
AVCC = VCC*1
AVRH
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
ICLAMP
− 2.0
+ 2.0
mA
*5
ΣICLAMP
—
20
mA
*5
IOL1
—
8
mA
IOLAV1
—
2
mA
ΣIOL1
—
64
mA
ΣIOLAV1
—
25
mA
IOH1
—
−8
mA
IOHAV1
—
−2
mA
ΣIOH1
—
− 64
mA
ΣIOHAV1
—
− 25
mA
Power consumption
PD
—
500
mW
Operating temperature
Ta
− 40
+ 105
°C
Storage temperature
Tstg
− 55
+ 150
°C
Power supply voltage
Maximum clamp current
Total maximum clamp current
“L” level maximum output current*
2
“L” level average output current*3
“L” level total maximum output current
4
“L” level total average output current*
“H” level maximum output current*
2
“H” level average output current*3
“H” level total maximum output current
4
“H” level total average output current*
Single-chip mode
*1: Caution must be taken that AVCC does not exceed VCC upon power-on and under other circumstances.
*2: The maximum output current defines the peak current value of each of the corresponding pins.
*3: The average output current defines the average value of the current (100 ms) which passes through each of
the corresponding pins. The average value represents a value calculated by multiplying the operating current
by the operating rate.
*4: The total average output current defines the average value of the current (100 ms) which passes through all the
corresponding pins. The average value represents a value calculated by multiplying the operating current by
the operating rate.
*5:
• Corresponding pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P64,
P70 to P77, P80 to P85, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC7, PD0 to PD7,
PE0 to PE2,PF0 to PF7
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal should always be applied a limiting resistor placed between the + B signal and the
microcontroller.
• The value of the limiting resistor should be set so that when the + B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input
potential can increase the potential at the VCC pin via a protection diode, possibly affecting other devices.
(Continued)
50
DS07-16804-3E
MB91210 Series
(Continued)
• Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through
the pin, possibly causing the microcontroller to operate imperfectly.
Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin,
possibly resulting in a power-supply voltage at which a power-on reset does not work.
• Be careful not to let the + B input pin open.
• Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input
pin cannot input + B.
• Recommended example circuit
• Input/output equivalent circuits
Protection diode
VCC
P-ch
Limiting resistor
+ B Input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-16804-3E
51
MB91210 Series
2. Recommended operation condition
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Value
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
3.5
5.5
V
Normal operation
VCC
3.0
5.5
V
RAM data retention at STOP operation
μF
Use a ceramic capacitor or a capacitor with
similar frequency characteristics.
Use a bypass capacitor for the VCC pin,
which has larger than CS.
°C
Single-chip mode
Smoothing capacitor*
CS
Operating temperature
Ta
1
(within tolerance ± 50%)
− 40
+ 105
* : For how to connect the smoothing capacitor CS, see the figure below.
• C Pin Connection Diagram
C
CS
VSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
52
DS07-16804-3E
MB91210 Series
3. DC Specifications
(Ta: Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
name
Condition
VIHS
—
VIHC
“H” level input
voltage
“L” level input
voltage
Value
Unit
Remarks
VCC + 0.3
V
CMOS automotive input
—
VCC + 0.3
V
CMOS Schmitt input
VCC − 0.3
—
VCC + 0.3
V
—
0.8 × VCC
—
VCC + 0.3
V
—
—
VSS − 0.3
—
0.5 × VCC
V
CMOS automotive input
VILC
—
—
VSS − 0.3
—
0.3 × VCC
V
CMOS Schmitt input
VILM
MD0
to
MD3
—
VSS − 0.3
—
VSS + 0.3
V
VILI
INITX
—
VSS − 0.3
—
0.2 × VCC
V
*1
—
40
60
mA
Normal operation *7
Ta = + 25 °C
—
2
3
mA
Ta = + 105 °C
—
2.6
4
mA
PLL stop operation
(2 MHz)
Min
Typ
Max
—
0.8 × VCC
—
—
—
0.7 × VCC
VIHM
MD0
to
MD3
—
VIHI
INITX
VILS
ICC
VCC
ICCS
VCC
*2
—
28
42
mA
SLEEP operation *7
ICCL
VCC
*3
—
150
300
µA
Sub-operation *7
ICCR32
VCC
*4
—
80
200
µA
32 kHz clock operation
ICCR4
VCC
*5
—
800
1200
µA
4 MHz clock operation
ICCH
VCC
*6
—
70
150
µA
STOP
Input leakage
current
IIL
—
⎯
−5
—
+5
µA
All input pins
Input capacity
CIN
—
⎯
—
5
15
pF
Pull-up
resistance
RUP
—
⎯
25
50
100
kΩ
All ports and INITX
Pull-down
resistance
RDOWN
—
⎯
25
50
100
kΩ
All ports, MD3, MD2*8
Output H voltage
VOH
⎯
IOH= − 2 mA
VCC − 0.5
—
—
V
All ports
Output L voltage
VOL
⎯
IOL=2 mA
—
—
0.4
V
All ports
Power supply
current
*1 : CLKB = 40 MHz, CLKP = 20 MHz, CLKT = 10 MHz, CANCLK = 10 MHz
*2 : Under *2, CPU stopped.
*3 : CLKB = CLKP = CLKT = CANCLK = 32 kHz, Ta = + 25 °C
*4 : CPU/peripheral circuit operation stopped, main oscillation stopped, 32 kHz clock operation, Ta = + 25 °C
*5 : CPU/peripheral circuit operation stopped, sub-oscillation stopped, 4 kHz clock operation, Ta = + 25 °C
*6 : CPU/peripheral circuit operation stopped, all oscillation circuits stopped, Ta = + 25 °C
*7 : The current consumption in normal operation/SLEEP mode, is the value at the maximum operation of the
peripheral circuit.
*8 : Only MB91213A
DS07-16804-3E
53
MB91210 Series
4. AC Specifications
(1) Clock timing
(Ta: Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Frequency of source
oscillation clock
Source oscillation
clock cycle time
Symbol Pin name Condition
FC
X0, X1
FCA
X0A, X1A
Value
Unit
Min
Typ
Max
—
4
16
MHz
—
32.768
100
kHz
—
32.768
—
Remarks
MB91213A/F213A/
F218S
kHz MB91F211B
tCYL
X0, X1
62.5
250
—
ns
tCYLL
X0A, X1A
10
30.5
—
μs
—
Input clock pulse width PWH, PWL
X0
30
—
—
ns
The duty ration
normally ranges from
40% to 60%.
Input clock rise/
fall time
tcr, tcf
X0
—
—
5
ns
When external clock
is used
Frequency of internal
clock operation
FCP
—
—
—
40
Internal operation
clock cycle time
tCP
—
25
—
—
—
When main clock
MHz and PLL clock is
used.
ns
When main clock
and PLL clock is
used.
t CYL
0.8 Vcc
X0
0.2 Vcc
PWH
54
tcf
PWL
tcr
DS07-16804-3E
MB91210 Series
• Operation guarantee range
Relation between internal operation clock frequency and power supply voltage
Power supply voltage VCC (V)
Recommended
operation range
5.5
4.0
3.5
PLL operation
guarantee range
2
8
20
40
Internal operation clock FCP (MHz)
Note : PLL operation stabilizing wait time should be set to 600 µs or more.
Relation between oscillation clock frequency and internal operation clock (example)
Source oscillation (4 MHz)
Source oscillation (5 MHz)
Divider
1/2
1/4
1/8
Divider
1/2
1/4
1/8
Multiplier
FCP
FCP
FCP
Multiplier
FCP
FCP
FCP
1
–
–
–
1
–
–
–
2
–
–
8 MHz
2
–
–
10 MHz
4
–
16 MHz
16 MHz
4
–
20 MHz
–
6
–
24 MHz
–
6
–
30 MHz
–
8
32 MHz
32 MHz
–
8
40 MHz
–
–
10
40 MHz
–
–
10
–
–
–
Source oscillation (10 MHz)
Source oscillation (16 MHz)
Divider
1/2
1/4
1/8
Divider
1/2
1/4
1/8
Multiplier
FCP
FCP
FCP
Multiplier
FCP
FCP
FCP
1
–
–
10 MHz
1
–
16 MHz
16 MHz
2
–
20 MHz
–
2
32 MHz
32 MHz
–
4
40 MHz
–
–
4
–
–
–
6
–
–
–
6
–
–
–
8
–
–
–
8
–
–
–
10
–
–
–
10
–
–
–
–: Prohibited
DS07-16804-3E
55
MB91210 Series
AC specifications are defined by the following measurement standard voltage values:
Input signal waveform
Output signal waveform
Hysteresis input pin
Output pin
0.7 Vcc
4.6 V
0.3 Vcc
0.4 V
Hysteresis input pin (Automotive)
0.8 Vcc
0.5 Vcc
Example oscillation circuit
X0
X1
R
C1
56
C2
DS07-16804-3E
MB91210 Series
(2) Reset input
(Ta: Recommended operating conditions; VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Parameter
Symbol Pin name Condition
INITX input
time
tINTL
INITX
—
Value
Unit
Min
Max
500
—
ns
217 × tCYL
—
ms
Remarks
Upon power-on and in
stop mode
tINTL
INITX
0.2 Vcc
0.2 Vcc
• In stop mode
tINTL
INITX
X0
0.2 Vcc
0.2 Vcc
90% of
amplitude
Internal
operation
clock
Oscillation time
of oscillator
Oscillation stabilization
wait time
Internal reset
DS07-16804-3E
Instruction executed
57
MB91210 Series
[External reset input specifications (INITX) and internal reset signal cancellation timing]
• When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the
internal reset signal to transmit all reset signals to the internal logic.
(Max 6.4 µs at 40 MHz)
• The following chart shows how to set the timing for instruction execution start (start of application operation)
after external reset input.
Time from external reset input to instruction start = Max 256 tcp + 61 tcp
• Timing Chart
INITX
Min
500 ns
Internal reset input timing
61 tcp
Internal reset
Max 256 tcp
Internal reset cancellation timing
58
DS07-16804-3E
MB91210 Series
(3) Power-on Conditions
(Ta : Recommended operating conditions; VSS = 0.0 V)
Value
Parameter
Symbol Pin name Condition
Unit
Remarks
30
ms
—
—
0.2
V
—
3.5
—
V
—
50
—
ms
Min
Max
tR
0.05
Power supply start voltage
VOFF
Power supply peak voltage
VON
Power supply cut-off time
tOFF
Power supply rising time
VCC
—
Due to repetitive
operation
tR
VCC
3.5V
0.2V
0.2V
0.2V
tOFF
(4) Power supply drop time, power supply voltages and external reset input to retain RAM data.
Satisfy the following reset input standard to retain the RAM data used in the single chip mode.
VCC(V)
Voltage drop time
External reset input standard (INITX)
3.5 V → 3.0 V dropped
Min 256 tcp
Min 256 tcp
Vcc
3.5 V
3.5 V
3.0 V
3.0 V
INITX
256 tcp
To retain RAM data, enter 256 tcp of INITX or more before dropping VCC to 3.0 V or lower.
DS07-16804-3E
59
MB91210 Series
(5) UART Timing
(Ta: Recommended operating conditions; VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT
delay time
tSLOV
SCK
SOT
Valid SIN → SCK ↑
tIVSH
SCK ↑ →
Valid SIN hold time
tSHIX
Serial clock “H” pulse
width
tSHSL
Serial clock “L” pulse
width
tSLSH
Condition
Output pin,
CL = 30 pF + 1 × TTL
SCK
SIN
Value
Unit
Min
Max
8 tCP
—
ns
− 80
+ 80
ns
100
—
ns
60
—
ns
4 tCP
—
ns
4 tCP
—
ns
—
2×
CLKP +
60
ns
60
—
ns
60
—
ns
Remarks
For internal
shift clock
mode
SCK
SCK ↓ → SOT
delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ →
Valid SIN hold time
tSHIX
SCK
SOT
Output pin,
CL = 30 pF + 1 × TTL
SCK
SIN
For external
shift clock
mode
Note: These are AC characteristics for CLK synchronous mode.
CL is a load capacitance connected to pins during testing.
60
DS07-16804-3E
MB91210 Series
• For internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
• For external shift clock mode
tSLSH
tSHSL
0.7 VCC
SCK
0.3 VCC
0.7 VCC
0.3 VCC
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
DS07-16804-3E
tSHIX
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
61
MB91210 Series
(6) Timer Input Timing
(Ta: Recommended operating conditions; VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Condition
tTIWH
tTIWL
TIN0 to TIN2
IN0 to IN7
—
Input pulse width
Value
Min
Max
4 tCP
—
Unit
ns
• Timer Input Timing
tTIWH
0.7 Vcc
TINx
INx
tTIWL
0.7 Vcc
0.3 Vcc
0.3 Vcc
(7) External Interrupt Timing
(Ta: Recommended operating conditions; VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Condition
Input pulse width
tINTH, tINTL
INT0 to INT15
Value
Unit
Min
Max
⎯
3 tCP
—
ns
STOP mode
1.0
—
μs
• External Interrupt Input Timing
tINTH
0.8 VCC
INTx
62
tINTL
0.8 VCC
0.5 VCC
0.5 VCC
DS07-16804-3E
MB91210 Series
5. Flash Memory Write/Erase Characteristics
Parameter
Condition
Value
Min
Typ
Max
Unit
Remarks
Sector erase time
—
—
0.9
3.6
s
Exclusive of internal write time
prior to erase
Word write time
—
—
23
370
µs
Exclusive of overhead time at
system level
Chip write time
—
—
6.2
102
s
Exclusive of overhead time at
system level
Erase/write cycle
⎯
10000
—
—
cycle
Average Ta= + 85 °C
20*
—
—
year
Data retention time
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C).
DS07-16804-3E
63
MB91210 Series
6. A/D Converter Electrical Characteristics
(Ta : Recommended operating conditions; VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Resolution
—
Total error
Value
Unit
Remarks
Min
Typ
Max
—
—
—
10
bit
—
—
—
—
± 3.0
LSB
Non-liner error
—
—
—
—
± 2.5
LSB
Differential linearity
error
—
—
—
—
± 1.9
LSB
Zero transition voltage
VOT
AN0 to AN31
AVSS −
1.5LSB
AVSS +
0.5LSB
AVSS +
2.5LSB
V
Full-scale transition
voltage
VFST
AN0 to AN31
AVRH −
3.5LSB
AVRH −
1.5LSB
AVRH +
0.5LSB
V
1.1
—
—
µs
VCC = AVCC =
4.5 V to 5.5 V*1
1.65
⎯
⎯
μs
VCC = AVCC =
3.5 V to 4.5 V*5
1.1
—
—
µs
VCC = AVCC =
4.5 V to 5.5 V*2
2.2
⎯
⎯
μs
VCC = AVCC =
3.5 V to 4.5 V*6
2.2
—
—
µs
VCC = AVCC =
4.5 V to 5.5 V*3
3.85
⎯
⎯
μs
VCC = AVCC =
3.5 V to 4.5 V*7
VAVSS ≤ VAIN ≤ VAVCC
Sampling time
Compare time
A/D conversion time
tSMP
tCMP
tCNV
—
—
—
1LSB =
(AVRH-AVSS)/1024
Analog port input
current
IAIN
AN0 to AN31
—
—
10
µA
Analog input voltage
VAIN
AN0 to AN31
0
—
AVRH
V
AVRH
AVRH
4.0
—
AVCC
V
—
2.4
4.7
mA
—
—
5
µA
*4
—
600
900
µA
VAVRH = 5.0 V
—
—
5
µA
*4
—
—
4
LSB
Standard voltage
IA
Power supply current
AVCC
IAH
Standard voltage
supply current
Variation between
channels
IR
AVRH
IRH
—
AN0 to AN31
*1 : When FCP is 40 MHz : tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP cycle = 2 Ch × 25 ns = 1.1 µs
*2 : When FCP is 40 MHz : tCMP = CKIN × 11 = CT × CLKP cycle × 11 = 4 h × 25 ns × 11 = 1.1 µs
*3 : This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 40 MHz.
(Continued)
64
DS07-16804-3E
MB91210 Series
(Continued)
*4: This defines the power supply current when the A/D converter is not in operation and the CPU is stopped
(at “VCC = AVCC = AVRH = 5.0 V”)
*5 : When FCP is 20 MHz : tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP cycle = 21h × 50 ns = 1.65 μs.
*6 : When FCP is 20 MHz : tCMP = CKIN × 11 = CT × CLKP cycle × 11 = 4 h × 50 ns × 11 = 2.2 μs.
*7 : This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 20 MHz.
Notes:
• As AVRH becomes smaller, the error becomes greater.
• Use the output impedance rS of the external circuit for analog input under the following conditions :
Output impedance rS of the external circuit = 4 kΩ (Max)
• If the output impedance of the external circuit is too high, the sampling time of the analog voltage may
not be sufficient.
• When placing a DC blocking capacitor between the external circuit and input pin, set the capacitance to
the value calculated by multiplying CSH by several thousands as a guideline in order to minimize the
impact from dividing voltage capacitance with CSH.
• Analog Input Equivalent Circuit
Circuit in microcontroller
rS
Input pin AN0
CSH
RSH
Comparator
Input pin AN7
VS
S/H circuit
Analog channel selector
<Recommended parameter values and tentative guideline for each element>
rS
4 kΩ or less
RSH = approx. 2.5 kΩ (5 V ± 10%)
CSH = approx. 8.5 pF
Note: These element parameters should be regarded as tentative values used only for design purposes.
DS07-16804-3E
65
MB91210 Series
■ TERM DEFINITIONS
Resolution
Level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, the analog voltage can be resolved into 210 = 1024.
Total error
Difference between actual and theoretical values, which is a total value derived from an offset error, gain error,
non-linearity error and noise.
Linearity error
Deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ←→ “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1110” ←→ “11 1111 1111”) compared with the actual conversion values obtained.
Differential linearity error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
66
DS07-16804-3E
MB91210 Series
• 10-bit A/D Converter- Conversion Characteristics
11 1111 1111B
11 1111 1110B
11 1111 1101B
11 1111 1100B
1LSB × N + V0T
00 0000 0011B
00 0000 0010B
00 0000 0001B
00 0000 0000B
V0T
VNT V (N+1)T
VFST
N = A/D converter digital output value.
V0T = AVss + 0.5LSB [V] (Theoretical value)
VFST = AVRH 1.5LSB [V] (Theoretical value)
VNT: Transition voltage of digital output from (N-1)H to NH
Linearity error=
Differential linearity error=
DS07-16804-3E
VNT − (1LSB × N + VOT)
1LSB
V(N + 1)T − VNT
1LSB
[LSB]
− 1 [LSB]
67
MB91210 Series
■ ORDERING INFORMATION
Part No.
Package
MB91F211BPMC-GSE1
100-pin plastic LQFP
(FPT-100P-M20)
MB91213APMC-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91F213APMC-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91F218SPMC-GTE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91V210PB-ESE1
420-pin plastic PBGA
(BGA-420P-M01)
68
DS07-16804-3E
MB91210 Series
■ PACKAGE DIMENSION
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-16804-3E
69
MB91210 Series
(Continued)
144-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7
C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
70
DS07-16804-3E
MB91210 Series
■ MAIN CHANGES IN THIS EDITION
Page
17
Section
Change Results
■ HANDLING DEVICES
Added the item of “• Serial Communication”
■ MODE SETTINGS
Corrected the figure of “Detailed description of mode data”
bit31, bit30, bit29, bit28, bit27, bit26, bit25, bit24 →
bit7, bit6, bit5bit4, bit3, bit2, bit1, bit0
21
The vertical lines marked in the left side of the page show the changes.
DS07-16804-3E
71
MB91210 Series
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