2.3 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16806-5E
32-bit Microcontroller
CMOS
FR60Lite MB91220 Series
MB91F223/F223S/F224/F224S/V220
■ OVERVIEW
MB91220 series is a line of single-chip microcontrollers based on a 32-bit high-performance RISC CPU and
integrating a variety of I/O resources for embedded control applications.
The MB91220 series is designed to be best suited for embedded applications which require high-speed and highperformance processing power in the CPU, such as DVD players, printers, TV sets, and the PDP control.The
MB91220 series is a line of CPUs in the FR60Lite implemented by FR* family.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.10
MB91220 Series
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with × 8 multiplier-PLL clock multiplier
system)
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : 1 instruction per cycle
• Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift
instructions etc.
• Instructions supported by C language : Function entry/exit instructions, multiple-register load/store instructions.
• Register interlock function : Easier assembler coding enabled
• Built-in multiplier supported at the instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC/PS save) : 6 cycles (16 priority levels)
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction set compatible with FR family
• Internal Peripheral Functions
• Internal ROM size & ROM type
Flash Memory
: 512 Kbytes (MB91F223/S) / 768 Kbytes (MB91F224/S)
• Internal RAM size : 16 Kbytes (MB91F223/S) / 24 Kbytes (MB91F224/S) / 64 Kbytes (MB91V220)
• General-purpose ports : up to 120 ports (including 4 input-only ports)
• 8/10-bit A/D converter (Sequential comparison type)
8/10-bit resolution : 24 channels
Conversion time : 3 μs (16/32 MHz)
Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is
achieved.
32 MHz : Source oscillation (4 MHz) with ×8 multiplier, divided by 1
16 MHz : Source oscillation with ×8 multiplier, divided by 2
• D/A converter (R-2R type)
8-bit resolution : 2 channels
• External interrupt : 8 channels
• Bit search module (for REALOS)
• LIN-UART (full duplex double buffer type) : 4 channels
Synchronous/asynchronous clock operations selectable
Sync-break detection
Dedicated built-in baud-rate generator
• I2C Bus interface : 2 channels
• Stepping motor controller (SMC) : 4 channels
10-bit PWM with 4 high-current outputs for each channel
• 8/16-bit PPG timer : 16 channels
• 16-bit reload timer : 3 channels
• 16-bit free-run timer : 2 channels (ICU/OCU linkage)
• 16-bit pulse width counter : 1 channel
• Input capture : 4 channels (free-run timers ch.0 and ch.1). ch.0 linked to PWC
• Output compare : 2 channels (free-run timer ch.0 )
• LCD controller : SEG0 to SEG31/COM0 to COM3 (shared with port)
• 16-bit timebase/watch dog timer
(Continued)
2
DS07-16806-5E
MB91220 Series
(Continued)
• Sound generator : 3 channels
• Real-time clock
• 32 kHz sub clock (not supported in devices with an S suffix in the part number)
• C-CAN : 2 channels
• Low power consumption modes : sleep mode, stop mode, watch mode
• Package : LQFP-144 (FPT-144P-M08)
• CMOS technology : 0.35 μm
• Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used))
DS07-16806-5E
3
MB91220 Series
■ PRODUCT LINEUP
ROM/Flash size
RAM size
MB91V220
MB91F223/S
MB91F224/S
External SRAM
512 Kbytes
768 Kbytes
64 Kbytes
16 Kbytes
24 Kbytes
External interrupt
8 channels
DMA Controller
5 channels
8 /10-bit A/D Converter
24 channels
D/A Converter
2 channels
LIN-UART
4 channels
2
IC
2 channels
Stepping Motor Controller
4 channels
8 /16-bit PPG Timer
16 channels
16-bit Reload Timer
3 channels
16-bit Free-Run Timer
2 channels
16-bit Pulse Width
Counter
1 channel
Input Capture Unit
4 channels
Output Compare Unit
2 channels
LCD Controller
4 COM, 32 SEG
Sound Generator
3 channels
Real Time Clock
Yes
32 kHz Sub Clock
Yes
On Chip Debug Support
Unit
C-CAN
Yes : MB91F224
No : MB91F224S
Addr 16 bits
Data 16 bits
External bus
Others
Yes : MB91F223
No : MB91F223S
Evaluation product
Flash memory
product
DSU4
⎯
2 channels
32-message buffer
Note : Embedded peripheral functions which are not listed are common functions.
4
DS07-16806-5E
MB91220 Series
■ PIN ASSIGNMENT
P21/SEG1/A01
P22/SEG2/A02
P23/SEG3/A03
P24/SEG4/A04
P25/SEG5/A05
P26/SEG6/A06
P27/SEG7/A07
P30/SEG8/A08
P31/SEG9/A09
P32/SEG10/A10
P33/SEG11/A11
P34/SEG12/A12
P35/SEG13/A13
P36/SEG14/A14
P37/SEG15/A15
X0A
X1A
VCC
VSS
VCC3C
P10/SEG16/D08
P11/SEG17/D09
P12/SEG18/D10
P13/SEG19/D11
P14/SEG20/D12
P15/SEG21/D13
P16/SEG22/D14
P17/SEG23/D15
P00/SEG24/D00
P01/SEG25/D01
P02/SEG26/D02
P03/SEG27/D03
P04/SEG28/D04
P05/SEG29/D05
P06/SEG30/D06
P07/SEG31/ATGX/D07
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
P20/SEG0/A00
PD7/COM3/PPG7H
PD6/COM2/PPG5H
PD5/COM1/PPG3H*
PD4/COM0/PPG1H*
PD3/IN3/V3
PD2/TIN2/IN2/V2
PD1/TIN1/IN1/V1
PD0/TIN0/IN0/PWC0/INT2/V0
P47/SYSCLK
P46/ASX
P57/OUT1/RDY
P56/OUT0/WR1X
P55/SCK5/WR0X
P54/SOT5/RDX
X0
X1
VSS
VCC
P53/SIN5/CK1/CS3X
P52/SCK4/CS2X
P51/SOT4/CS1X
P50/SIN4/CK0/CS0X
P45/SCK3
P44/SOT3
P43/SIN3/INT1
P42/SCK0
P41/SOT0
P40/SIN0/INT0
PG3/TOT2/PPG6H
PG2/TOT1/PPG4H
PG1/TOT0/PPG2H
P73/TX1
P72/INT7/RX1
P71/TX0
P70/INT6/RX0
(TOP VIEW)
1
2
108
107
3
106
4
5
105
104
6
7
103
102
8
101
9
10
100
99
11
98
12
13
14
97
96
95
15
94
16
93
17
18
92
91
LQFP-144
19
20
90
89
21
22
88
87
23
86
24
85
25
26
27
84
83
82
28
81
29
30
80
79
31
32
78
77
33
76
34
35
75
74
36
73
INITX
MD0
MD1
MD2
DVSS
DVCC
PE7/PPG15H/SCL1
PE6/PPG14H/SDA1
PE5/PPG13H/SCL0
PE4/PPG12H/SDA0
PE3/PWM2M2
PE2/PWM2P2
PE1/PWM1M2
PE0/PWM1P2
PA3/PWM2M3
PA2/PWM2P3
PA1/PWM1M3
PA0/PWM1P3
DVSS
DVCC
PF7/AN15
PF6/AN14
PF5/AN13
PF4/AN12
PF3/AN11
PF2/AN10
PF1/AN9
PF0/AN8
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AVSS/AVRL
AVRH
AVCC
P80/AN16
P81/AN17
P82/AN18
P83/AN19
P84/AN20
P85/AN21/INT3
P86/AN22/INT4
P87/AN23/INT5
P90/DA0
P91/DA1
P92/SGA0
P93/SGO0
P94/SGA1
P95/SGO1
P96/SGA2
P97/SGO2
DVSS
DVCC
PC3/PWM2M0
PC2/PWM2P0
PC1/PWM1M0
PC0/PWM1P0
PB7/PWM2M1
PB6/PWM2P1
PB5/PWM1M1
PB4/PWM1P1
PB3/PPG11H
PB2/PPG10H
PB1/PPG9H
PB0/PPG8H
DVSS
DVCC
PG0/PPG0H
(FPT-144P-M08)
*: For PD4 and PD5, the same pin function should be selected at PFRD/EPFRD registers.
When PD4 is used as the port function, PD5 should also be used as the port function.
When PD4 is used as the PPG function, PD5 should also be used as the PPG function.
When PD4 is used as the COM function, PD5 should also be used as the COM function.
DS07-16806-5E
5
MB91220 Series
■ PIN DESCRIPTIONS
Pin No.
Pin name
I/O
circuit
type*
129
X0
A
Main clock (oscillator) input.
128
X1
A
Main clock (oscillator) output.
16
X0A
B
Sub clock (oscillator) input.
17
X1A
B
Sub clock (oscillator) output.
108
INITX
C
External reset input
105
MD2
D
Mode pin 2. The setting on this pin determines the basic operation mode.
Connect it to VCC or VSS.
106
MD1
D
Mode pin 1. The setting on this pin determines the basic operation mode.
Connect it to VCC or VSS.
107
MD0
D
Mode pin 0. The setting on this pin determines the basic operation mode.
Connect it to VCC or VSS.
P00 to P06
29 to 35
SEG24 to SEG30
General-purpose I/O ports
G
D00 to D06
SEG31
ATGX
General-purpose I/O port
G
D07
SEG16 to SEG23
G
1 to 7
8 to 15
General-purpose I/O port
F
SEG output from LCDC
A00
External address bus bit00
P21 to P27
General-purpose I/O ports
SEG1 to SEG7
F
SEG outputs from LCDC
A01 to A07
External address bus bit01 to bit07
P30 to P37
General-purpose I/O ports
SEG8 to SEG15
F
A08 to A15
116
SEG outputs from LCDC
External data bus bit08 to bit15
P20
SEG0
External trigger input for A/D converter.
General-purpose I/O ports
D08 to D15
144
SEG output from LCDC
External data bus bit07
P10 to P17
21 to 28
SEG outputs from LCDC
External data bus bit00 to bit06
P07
36
Function
SEG outputs from LCDC
External address bus bit08 to bit15
P40
General-purpose I/O port: Valid when the data input specification is
prohibited on UART0.
SIN0
UART0 data input. Because this input is used as necessary while
UART0 is used for input operation, the port output needs to be disabled
except when it is used intentionally.
INT0
M
External interrupt input. Because this input is used as necessary while
the pertinent external interrupt is enabled, the port output needs to be
disabled except when it is used intentionally.
(Continued)
6
DS07-16806-5E
MB91220 Series
Pin No.
Pin name
I/O
circuit
type*
P41
117
I
SOT0
P42
118
I
SCK0
119
UART0 data output: Valid when the clock output specification is permitted
on UART0.
General-purpose I/O port: Valid when the clock output specification is
prohibited on UART0.
UART0 clock input/output: Valid when the clock output specification is
permitted on UART0.
General-purpose I/O port: Valid when the data input specification is
prohibited on LIN-UART1.
SIN3
UART1 data input. Because this input is used as necessary while UART1
is used for input operation, the port output needs to be disabled except
when it is used intentionally.
M
INT1
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled except when it is used intentionally.
P44
General-purpose I/O port: Valid when the data output specification on
UART1 is prohibited.
I
SOT3
P45
121
I
SCK3
P46
134
ASX
I
P47
122
General-purpose I/O port: Valid when the data output specification is
prohibited on UART0.
P43
120
135
Function
SYSCLK
LIN-UART1 data output: Valid when the data output specification is
permitted on LIN-UART1.
General-purpose I/O port: Valid when the clock output specification is
prohibited on LIN-UART1.
LIN-UART1 clock input/output: Valid when the clock output specification
is permitted on LIN-UART1.
General-purpose I/O port
Address strobe output: Valid when the address strobe output is permitted.
General-purpose I/O port
I
System clock output: Valid when the system clock output specification is
permitted. A clock with the same frequency as that external bus operation
frequency is output at this pin (Clock output stops at transition to the
STOP state).
P50
General-purpose I/O port : Valid when the data input specification is
prohibited on LIN-UART2.
SIN4
LIN-UART2 data input. Because this input is used as necessary while
LIN-UART2 is used for input operation, the port output needs to be
disabled except when it is used intentionally.
CK0
CS0X
M
External clock input for free-run timer 0
Chip select 0 output: Valid when the chip select 0 is permitted to output.
(Continued)
DS07-16806-5E
7
MB91220 Series
Pin No.
Pin name
I/O
circuit
type*
General-purpose I/O port: Valid when the data output specification is
prohibited on LIN-UART2.
P51
123
SOT4
I
General-purpose I/O port: Valid when clock output is prohibited on
LIN-UART2.
P52
SCK4
I
P53
General-purpose I/O port: Valid when the data input specification is
prohibited on LIN-UART3.
SIN5
LIN-UART3 data input. Because this input is used as necessary while LINUART3 is used for input operation, the port output needs to be disabled
except when it is used intentionally.
M
CK1
External clock input for free-run timer 1
Chip select 3 output: Valid when the output specification is permitted on
chip select 3.
CS3X
General-purpose I/O port: Valid when data output specification is
prohibited on LIN-UART3.
P54
130
131
SOT5
I
External bus read strobe output: Valid at the external bus mode.
P55
General-purpose I/O port: Valid when clock output is prohibited on
LIN-UART3.
SCK5
I
OUT0
General-purpose I/O port
I
P57
RDY
Output compare output
External bus write strobe output: Valid when the WR1X output is permitted
at the external bus mode.
WR1X
OUT1
LIN-UART3 clock input/output: Valid when the clock output specification is
permitted on LIN-UART3.
External bus write strobe output: Valid when the WR0X output is permitted
at the external bus mode.
P56
133
LIN-UART3 data output: Valid when the data output specification is
permitted on LIN-UART3.
RDX
WR0X
132
LIN-UART2 clock input/output: Valid when the clock output specification is
permitted on LIN-UART2.
Chip select 2 output: Valid when the output specification is permitted on
chip select 2.
CS2X
125
LIN-UART2 data output: Valid when the data output specification is
permitted on LIN-UART2.
Chip select 1 output: Valid when the output specification is permitted on
chip select 1.
CS1X
124
Function
General-purpose I/O port
J
Output compare output
External ready input: Valid when the external ready input specification is
permitted.
(Continued)
8
DS07-16806-5E
MB91220 Series
Pin No.
Pin name
I/O
circuit
type*
P60 to P67
73 to 80
E
AN0 to AN7
P70
109
INT6
P71
TX0
I
INT7
I
P73
TX1
I
I
E
AN16 to AN20
63
AN21
TX0 input pin for CAN0
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled
except when it is used intentionally.
General-purpose I/O port
TX1 output pin for CAN1
General-purpose I/O ports: Valid when analog input specification is
prohibited.
A/D converter analog inputs: Valid when the analog input is selected in the
ADER register.
General-purpose I/O port: Valid when analog input specification is
prohibited.
P85
64
General-purpose I/O port
RX1 input pin for CAN1
P80 to P84
69 to 65
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled
except when it is used intentionally.
General-purpose I/O port
RX1
112
A/D converter analog inputs: Valid when the analog input is selected in the
ADER register.
RX0 input pin for CAN0
P72
111
General-purpose I/O ports: Valid when analog input specification is
prohibited.
General-purpose I/O port
RX0
110
Function
E
A/D converter analog input: Valid when the analog input is selected in the
ADER register.
INT3
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled
except when it is used intentionally.
P86
General-purpose I/O port: Valid when analog input specification is
prohibited.
AN22
INT4
E
A/D converter analog input: Valid when the analog input is selected in the
ADER register.
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled
except when it is used intentionally.
(Continued)
DS07-16806-5E
9
MB91220 Series
Pin No.
Pin name
I/O
circuit
type*
General-purpose I/O port: Valid when analog input specification is
prohibited.
P87
62
AN23
E
60
59
58
57
56
55
54
91
92
93
94
P90
DA0
P91
DA1
P92
SGA0
P93
SGO0
P94
SGA1
P95
SGO1
P96
SGA2
P97
SGO2
PA0
PWM1P3
PA1
PWM1M3
PA2
PWM2P3
PA3
PWM2M3
L
L
I
I
I
I
I
I
H
H
H
H
PB0
40
PPG8H
PPG9H
General-purpose I/O port
D/A converter analog output
General-purpose I/O port
D/A converter analog output
General-purpose I/O port
Sound generator 0 output
General-purpose I/O port
Sound generator 0 output
General-purpose I/O port
Sound generator 1 output
General-purpose I/O port
Sound generator 1 output
General-purpose I/O port
Sound generator 2 output
General-purpose I/O port
Sound generator 2 output
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
I
PB1
41
A/D converter analog input: Valid when the analog input is selected in the
ADER register.
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled except when it is used intentionally.
INT5
61
Function
PPG timer 8 output: Valid when the output specification is permitted on
PPG timer 8.
General-purpose I/O port
I
PPG timer 9 output: Valid when the output specification is permitted on
PPG timer 9.
(Continued)
10
DS07-16806-5E
MB91220 Series
Pin No.
Pin name
I/O
circuit
type*
PB2
42
PPG10H
General-purpose I/O port
I
PB3
43
44
45
46
47
48
49
50
51
PPG11H
PB4
PWM1P1
PB5
PWM1M1
PB6
PWM2P1
PB7
PWM2M1
PC0
PWM1P0
PC1
PWM1M0
PC2
PWM2P0
PC3
PWM2M0
Function
PPG timer 10 output: Valid when the output specification is permitted on
PPG timer 10.
General-purpose I/O port
I
H
H
H
H
H
H
H
H
PPG timer 11 output: Valid when the output specification is permitted on
PPG timer 11.
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
General-purpose I/O port
Stepping motor controller PWM output pin
PD0
General-purpose I/O port
TIN0
External event input pin for reload timer 0
IN0
136
K
PWC0
INT2
V0
Trigger input for input capture 0: Valid when input capture trigger input is
permitted and an input port is specified. If this pin is selected for input capture
input, it is used as necessary for input. Therefore the port output needs to be
disabled except when it is used intentionally.
PWC0 pulse width counter 0 input: Valid when the PWC0 pulse width
counter 0 input is permitted.
External interrupt input. Because this input is used as necessary while the
pertinent external interrupt is enabled, the port output needs to be disabled
except when it is used intentionally.
LCD driver power supply input pin
(Continued)
DS07-16806-5E
11
MB91220 Series
Pin No.
137
Pin name
I/O
circuit
type*
PD1
General-purpose I/O port
TIN1
External event input pin for reload timer 1
IN1
K
V1
138
PD2
General-purpose I/O port
TIN2
External event input pin for reload timer 2
IN2
K
PD3
General-purpose I/O port
IN3
Trigger input for input capture 3: Valid when input capture trigger input is
permitted and an input port is specified. If this pin is selected for input
capture input, it is used as necessary for input. Therefore the port output
needs to be disabled except when it is used intentionally.
K
LCD driver power supply input pin
Power supply pin for the embedded ladder resistor.
PD4
COM0
General-purpose I/O port
F
PD5
COM1
General-purpose I/O port
F
PD6
COM2
General-purpose I/O port
F
PD7
COM3
General-purpose I/O port
F
PE0
PWM1P2
COM3 output from LCDC
PPG timer 7 output: Valid when the output specification is permitted on
PPG timer 7.
PPG7H
95
COM2 output from LCDC
PPG timer 5 output: Valid when the output specification is permitted on
PPG timer 5.
PPG5H
143
COM1 output from LCDC
PPG timer 3 output: Valid when the output specification is permitted on
PPG timer 3.
PPG3H
142
COM0 output from LCDC
PPG timer 1 output: Valid when the output specification is permitted on
PPG timer 1.
PPG1H
141
Trigger input for input capture 2: Valid when input capture trigger input is
permitted and an input port is specified. If this pin is selected for input
capture input, it is used as necessary for input. Therefore the port output
needs to be disabled except when it is used intentionally.
LCD driver power supply input pin
V3
140
Trigger input for input capture 1: Valid when input capture trigger input is
permitted and an input port is specified. If this pin is selected for input
capture input, it is used as necessary for input. Therefore the port output
needs to be disabled except when it is used intentionally.
LCD driver power supply input pin
V2
139
Function
H
General-purpose I/O port
Stepping motor controller PWM output pin
(Continued)
12
DS07-16806-5E
MB91220 Series
(Continued)
Pin No.
96
97
98
Pin name
PE1
PWM1M2
PE2
PWM2P2
PE3
PWM2M2
I/O
circuit
type*
H
H
H
PE4
99
PPG12H
N
N
N
N
PPG0H
TOT0
I
I
PPG6H
External timer output for reload timer 1
PPG timer 4 output: Valid when the output specification is permitted on
PPG timer 4.
PG3
TOT2
External timer output for reload timer 0
General-purpose I/O port
PPG4H
115
PPG timer 0 output: Valid when the output specification is permitted on
PPG timer 0.
PPG timer 2 output: Valid when the output specification is permitted on
PPG timer 2.
PG2
TOT1
A/D converter analog inputs: Valid when the analog input is selected in the
ADER register.
General-purpose I/O port
PPG2H
114
PPG timer 15 output: Valid when the output specification is permitted on
PPG timer 15.
General-purpose I/O port.
I
PG1
113
PPG timer 14 output: Valid when the output specification is permitted on
PPG timer 14.
General-purpose I/O ports: Valid when analog input is prohibited.
E
PG0
37
PPG timer 13 output: Valid when the output specification is permitted on
PPG timer 13.
I2C1 serial clock input/output pin
PF0 to PF7
AN8 to AN15
PPG timer 12 output: Valid when the output specification is permitted on
PPG timer 12.
General-purpose I/O port
SCL1
81 to 88
Stepping motor controller PWM output pin
I2C1 serial data input/output pin
PE7
PPG15H
General-purpose I/O port
General-purpose I/O port
SDA1
102
Stepping motor controller PWM output pin
I2C0 serial clock input/output pin
PE6
PPG14H
General-purpose I/O port
General-purpose I/O port
SCL0
101
Stepping motor controller PWM output pin
I2C0 serial data input/output pin
PE5
PPG13H
General-purpose I/O port
General-purpose I/O port
SDA0
100
Function
General-purpose I/O port
I
External timer output for reload timer 2
PPG timer 6 output: Valid when the output specification is permitted on
PPG timer 6.
* : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-16806-5E
13
MB91220 Series
[Power supply and GND pins]
Pin No.
Pin name
19, 127
VSS
GND pins. The potentials of these pins must be the same.
18, 126
VCC
Power supply pins. The potentials of these pins must be the same.
70
AVCC
Analog power supply pin for A/D converter
71
AVRH
Analog reference power supply pin for A/D converter
72
14
Function
AVSS/AVRL Analog GND or analog reference power supply pin for A/D converter
20
VCC3C
Capacitor coupling pin for internal regulator
38, 52, 89, 103
DVCC
Power supply pins for stepping motor controller
39, 53, 90, 104
DVSS
GND pins for stepping motor controller
DS07-16806-5E
MB91220 Series
■ I/O CIRCUIT TYPE
Group
Circuit Type
Remarks
A
Clock input
For high speed (source oscillation of
main clock)
• Oscillation circuit
• Feedback resistance X0 :
approx. 1 MΩ
Clock input
For low speed (source oscillation of
sub clock)
• Oscillation circuit
• Feedback resistance X0A :
approx. 7 MΩ
X1
X0
Standby control
B
X1A
X0A
Standby control
C
P-ch
• Hysteresis (CMOS level) input
• Pull-up resistor supported
Pull-up resistor value =
approx. 50 kΩ
• No standby control
P-ch
R
N-ch
R
CMOS hysteresis
input (CMOS level)
(Continued)
DS07-16806-5E
15
MB91220 Series
Group
Circuit Type
D
Remarks
Flash memory product
• Hysteresis input
• High-voltage control for Flash test
supported
N-ch
N-ch
Control
N-ch
N-ch
R
N-ch
Mode input
Diffused resistor
E
P-ch
Digital output
N-ch
Digital output
• CMOS output (4 mA)
• Hysteresis (Automotive level) input
(Standby control supported)
• Analog input
(Analog input is valid when the
corresponding ADER bit is set to 1.)
R
Hysteresis input
(Automotive level)
Standby control
Analog input
F
P-ch
Digital output
N-ch
Digital output
• CMOS output (4 mA)
• LCDC output
• Hysteresis (Automotive level) input
(Standby control provided)
R
R
LCDC output
Hysteresis input
(Automotive level)
Standby control
(Continued)
16
DS07-16806-5E
MB91220 Series
Group
Circuit Type
G
P-ch
Digital output
N-ch
Digital output
R
Remarks
• CMOS output (4 mA)
• LCDC output
• Hysteresis (Automotive level) input
(Standby control supported)
• Hysteresis (TTL level) input
(Standby control supported)
LCDC output
Hysteresis input
(Automotive level)
R
R
Hysteresis input
(TTL level)
Standby control
H
P-ch
Digital output
• CMOS output
High current output for PWM (30 mA)
• Hysteresis (Automotive level) input
(Standby control supported)
N-ch
Digital output
R
Hysteresis input
(Automotive level)
Standby control
I
P-ch
Digital output
• CMOS output (4 mA)
• Hysteresis (Automotive level) input
(Standby control supported)
N-ch
Digital output
R
Hysteresis input
(Automotive level)
Standby control
(Continued)
DS07-16806-5E
17
MB91220 Series
Group
Circuit Type
J
Remarks
• CMOS output (4 mA)
• Hysteresis (Automotive level) input
(Standby control supported)
• Hysteresis (TTL level) input
(Standby control supported)
P-ch
N-ch
R
Hysteresis input
(Automotive level)
Hysteresis input
(TTL level)
Standby control
R
K
Hysteresis (Automotive level) input
(Standby control supported)
P-ch
N-ch
R
Hysteresis input
(Automotive level)
Standby control
(Continued)
18
DS07-16806-5E
MB91220 Series
(Continued)
Group
Circuit Type
L
P-ch
Digital output
N-ch
Digital output
R
Remarks
• CMOS output (4 mA)
• D/A converter output
• Hysteresis (automotive level) input
(Standby control supported)
Analog output
R
Hysteresis input
(Automotive level)
Standby control
M
P-ch
Digital output
N-ch
Digital output
R
R
• CMOS output (4 mA)
• Hysteresis (automotive level) input
(Standby control supported)
• Hysteresis (CMOS level) input
(Standby control supported)
Hysteresis input
(Automotive Level)
Hysteresis input
(CMOS level)
Standby control
N
P-ch
N-ch
R
R
Digital output
(When I2C is used,
P-ch is intercepted.)
Digital output
• CMOS output (3 mA)
• Hysteresis (automotive level) input
(Standby control supported)
• Hysteresis (CMOS level) input
(Standby control supported)
Hysteresis input
(Automotive Level)
Hysteresis input
(CMOS level)
Standby control
DS07-16806-5E
19
MB91220 Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC or less than VSS is applied to input and output
pin, or if an above-rating voltage is applied between VCC and VSS pins. When latch-up occurs, it may significantly
increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS
IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave unused input pins open, as this may cause a malfunction. Handle by performing a pull-up or pulldown with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open.
When set to the input status, it should be handled in the same way as an input pin.
• Power supply pins
If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential
are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the
pins to the external power supply and ground lines to lower the electro-magnetic emission level, to prevent
abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output
current rating. Moreover, connect the current supply source to the VCC and VSS pins of this device via a low
impedance.
Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC
and VSS near this device.
This device incorporates a regulator. When using the device with 5 V power supply, apply that power supply to
the VCC pin and always connect the VCC3C pin to a capacitor with 1 μF or more for the purpose of regulator.
• Example of power supply connection
5V
5V
5V
VCC
DVCC
AVCC
AVRH
AVSS
VSS
DVSS
VCC3C
1 µF
GND
20
DS07-16806-5E
MB91220 Series
• Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such
that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the
ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded
for use on the board. Caution must be taken especially when using a pin next to the X0.
It is strongly recommended that the PC board artwork be designed such that the X0, X1, X0A and X1A pins are
surrounded by ground plane because stable operation can be expected with such a layout.
In addition, the X0A/X1A pins must be surrounded by ground plane even if the sub clock is disabled.
When using MB91F223S/F224S, connect the X0A pin to GND and leave the X1A pin open.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to
test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS
pin is as short as possible and the connection impedance is now.
• Operation at start-up
Always use the INITX pin to perform a setting initialization reset (INIT) after power-on. Immediately after poweron, hold the low level input to the INITX pin for the stabilization wait time required for the oscillator circuit, to take
the oscillation stabilization wait time for the oscillator circuit.
For INIT via the INITX pin, the oscillation stabilization wait time setting is initialized to the minimum value.
• Source oscillation input upon power-on
When power-on, always input the clock for the duration of the oscillation stabilization delay time.
• Treatment of power supply pins on A/D converter
Connect to ensure “AVCC = AVRH = VCC and AVSS = VSS” even if the A/D converter is not in use.
• Power-on sequence for power supply analog input of A/D converter
Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 23) after turning
on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before
turning off the digital power supply (VCC). AVR should not exceed AVCC when turning on and off. Even when
using a pin shared with analog input as an input port, ensure that the input voltage does not exceed AVCC.
• Handling power supply for high-current output buffer pin (DVCC, DVSS)
Always apply power to high-current output buffer pins (DVCC) after turning on the digital power supply (VCC).
In addition, turn off the power supply for the high-current output buffer pins before turning off the digital power
supply (VCC).
Apply the same power as for high-current output buffer pins even when using such pins as general-purpose
ports (There is no problem in turning on or off the power supply for the high-current output buffer pins and the
digital power supply at the same time).
Always use the GND pin (DVSS) for the high-current output buffer pin at the same potential as the digital GND
pin (VSS).
DS07-16806-5E
21
MB91220 Series
• Switching from main clock mode to sub clock mode or stop mode
Always stop the main clock after switching the main clock mode to the sub clock mode or stop mode. Also secure
the oscillation stabilization wait time when returning from the sub clock mode or stop mode to the main clock mode.
• Flash write
Note that Flash write is not possible in the sub mode.
• Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system.
For example, apply a checksum to detect an error. If an error is detected, retransmit the data.
22
DS07-16806-5E
MB91220 Series
■ BLOCK DIAGRAM
FR 60Lite
CPU Core
32
DSU*2
32
5 channels
DMAC
Bit search
Flash
768 Kbytes/
512 Kbytes
32
Bus
converter
RAM
64 Kbytes/
24 Kbytes/16 Kbytes
X0, X1
X0A, X1A*1
MD0 to MD2
INITX
16
32
adapter
Clock
control
16
Interrupt
controller
INT0 to INT7
8 channels
External interrupt
2 channels
C-CAN
PORT I/F
3 channels
Reload timer
1 channel
PWC timer
16 channels
PPG timer
IN0 to IN3
OUT0, OUT1
CK0, CK1
SGA0 to SGA2
SGO0 to SGO2
ATGX
AVCC, AVSS
AVRH
AN0 to AN23
SIN0,SIN3 to SIN5
SOT0,SOT3 to SOT5
SCK0,SCK3 to SCK5
4 channels
Input
capture
ICU2
ICU3
ICU0
ICU1
2 channels
Output compare
OCU0
OCU1
2 channels
Free-run timer
TIN0 to TIN2
TOT0 to TOT2
PWC0
PPG0H to PPG15H
CPU detect reset
4 channels
Stepper motor controller
24 channels
A/D converter
4 channels
LIN-UART
PORT
Real time clock
FRT0
FRT1
3 channels
Sound Generator
RX0, RX1
TX0, TX1
32SEG x 4COM
LCD controller
2 channels
I2C
2 channels
D/A converter
PWM1P0,PWM1P2
PWM1M0,PWM2P2
PWM2P0,PWM2M2
PWM2M0,PWM1M2
PWM1P1, PWM1P3
PWM1M1, PWM1M3
PWM2P1, PWM2P3
PWM2M1, PWM2M3
COM0 to COM3
SEG0 to SEG31
SDA0, SDA1
SCL0, SCL1
DA0, DA1
*1 : The devices with an S suffix in the part number does not support the sub-block.
*2 : DSU is built into the MB91V220 only.
DS07-16806-5E
23
MB91220 Series
■ MEMORY SPACE
• Memory space
The FR family has 4 Gbytes logical address space (232 addresses) linearly accessible to the CPU space.
• Direct addressing area
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during on instruction.
The direct area varies depending on the size of data to be accessed as follows.
→ Byte data access
: 000H to 0FFH
→ Halfword data access : 000H to 1FFH
→ Word data access
: 000H to 3FFH
24
DS07-16806-5E
MB91220 Series
■ MEMORY MAP
MB91V220
Single chip
mode
Internal ROM
External ROM
external bus mode
external bus mode
I/O
I/O
I/O
addressing area
I/O
I/O
I/O
Refer to “■ I/O MAP”.
Access prohibited
Access prohibited
Access prohibited
I/O (C-CAN)
I/O (C-CAN)
I/O (C-CAN)
0003 0000H
0004 0000H
Access prohibited
Access prohibited
Access prohibited
Internal RAM 64 KB
Internal RAM 64 KB
Internal RAM 64 KB
0005 0000H
Access prohibited
Access prohibited
Emulation
SRAM area
Emulation
SRAM area
Access prohibited
External area
0000 0000H
Direct
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
Access prohibited
0008 0000H
External area
0010 0000H
FFFF FFFFH
DS07-16806-5E
25
MB91220 Series
MB91F223/S
Single chip
mode
Internal ROM
External ROM
external bus mode
external bus mode
0000 0000H
Direct
I/O
I/O
I/O
addressing area
I/O
I/O
I/O
Refer to “■ I/O MAP”.
Access prohibited
Access prohibited
Access prohibited
I/O (C-CAN)
I/O (C-CAN)
I/O (C-CAN)
0003 C000H
0004 0000H
Access prohibited
Access prohibited
Access prohibited
Internal RAM 16 KB
Internal RAM 16 KB
Internal RAM 16 KB
0005 0000H
Access prohibited
Access prohibited
Flash memory
area
512 Kbytes
Flash memory
area
512 Kbytes
Access prohibited
External area
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
Access prohibited
0008 0000H
0010 0000H
External area
FFFF FFFFH
Note : Each mode is set depending on the mode vector fetch after INITX is negated. For mode settings, refer to
“■ MODE SETTINGS”.
26
DS07-16806-5E
MB91220 Series
MB91F224/S
Single chip
mode
Internal ROM
External ROM
external bus mode
external bus mode
I/O
I/O
I/O
addressing area
I/O
I/O
I/O
Refer to “■ I/O MAP”.
Access prohibited
Access prohibited
Access prohibited
I/O (C-CAN)
I/O (C-CAN)
I/O (C-CAN)
Access prohibited
Access prohibited
Access prohibited
Internal RAM 24 KB
Internal RAM 24 KB
Internal RAM 24 KB
Access prohibited
Access prohibited
Access prohibited
Flash memory
area
768 Kbytes
Flash memory
area
768 Kbytes
Access prohibited
External area
0000 0000H
Direct
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 A000H
0004 0000H
0005 0000H
External area
0011 0000H
FFFF FFFFH
Note : Each mode is set depending on the mode vector fetch after INITX is negated. For mode settings, refer to
“■ MODE SETTINGS”.
DS07-16806-5E
27
MB91220 Series
■ MODE SETTINGS
The FR family, sets the operation mode using mode pins (MD2 to MD0) and mode data.
• Mode pins
The mode pins (MD2 to MD0) specify how the mode vector fetch and reset vector fetch is performed.
Other settings than these in the table are prohibited.
Mode pin
Mode name
MD2
MD1
MD0
0
0
0
Reset vector access area
Internal ROM mode vector
Internal
• Mode data
Data written to the internal mode register (MODR) by mode vector fetch is called mode data.
After an operating mode has been set in the mode register the device operates in that operating mode.
The mode data is set by all reset sources. User programs cannot set data to the mode register.
Details of mode data
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
0
0
0
0
0
ROMA
WTH1
WTH2
Operating mode
setting bits
Bit 31 to bit 27 are reserved.
Always set the value to “00000B”. Otherwise, the operation is not guaranteed.
[bit26] ROMA (Internal ROM enabling bit)
This bit specifies whether to enable internal ROM area.
ROMA
Function
Remarks
0
External ROM mode
Internal F-bus RAM is enabled, and the internal
ROM area (80000H to 100000H) becomes an
external area.
1
Internal ROM mode
Internal ROM area is enabled.
[bit25, bit24] WTH1, WTH0 (bus width setting bits)
Specify the bus width for the external bus mode.
In the external bus mode, this value is set to DBW1 and DBW0 bits in ACR0 (CS0 area).
WTH1
WTH0
Function
28
0
0
8-bit bus width
0
1
16-bit bus width
1
0
⎯
1
1
Single chip mode
DS07-16806-5E
MB91220 Series
Note : Mode data set in the mode vector must be placed as byte data at 000FFFF8H.
Place the data in the most significant byte from bit 31 to bit 24 as the FR family uses the big endian system
for byte endian.
bit
Incorrect
Correct
24 23
16 15
8 7
0
000FFFF8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
000FFFFCH
DS07-16806-5E
31
Reset vector
29
MB91220 Series
■ I/O MAP
The following table shows the correspondence between the memory space area and each register of the peripheral resource.
[How to read the map]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
Block
T-unit
Port data register
Read/Write attribute, Access unit
(B : byte, H : halfword, W : word)
Initial value after reset
Register name (First-column register at address 4n; second-column
register at 4n + 1, etc.)
Location of left-most register (When using word access, the register in
column 1 is in the MSB side of the data.)
Note :
Initial values of register bits are represented as follows :
“ 1 ” : Initial value “1”
“ 0 ” : Initial value “0”
“ X ” : Initial value “undefined”
“-”
: No physical register present at this location
Access by any undescribed data access attribute is prohibited.
30
DS07-16806-5E
MB91220 Series
Register
Address
+0
+1
+2
+3
00000000H
PDR0[R/W] B,H
XXXXXXXX
PDR1[R/W] B,H
XXXXXXXX
PDR2[R/W] B,H
XXXXXXXX
PDR3[R/W] B,H
XXXXXXXX
00000004H
PDR4[R/W] B,H
XXXXXXXX
PDR5[R/W] B,H
XXXXXXXX
PDR6[R/W] B,H
XXXXXXXX
PDR7[R/W] B,H
----XXXX
00000008H
PDR8[R/W] B,H
XXXXXXXX
PDR9[R/W] B,H
XXXXXXXX
PDRA[R/W] B,H
----XXXX
PDRB[R/W] B,H
XXXXXXXX
0000000CH
PDRC[R/W] B,H
----XXXX
PDRD[R/W] B,H
0000XXXX
PDRE[R/W] B,H
XXXXXXXX
PDRF[R/W] B,H
XXXXXXXX
00000010H
PDRG[R/W] B,H
----XXXX
-
-
-
00000014H
to
0000003CH
-
Block
Port Data
Register
Reserved
00000040H
EIRR0 [R/W]
B,H,W
00000000
ENIR0 [R/W]
B,H,W
00000000
ELVR0 [R/W] B,H,W
00000000 00000000
External
Interrupt
00000044H
DICR [R/W] B,H,W
-------0
HRCL[R/W] B
0--11111
-
Delayed
Interrupt
00000048H
0000004CH
TMRLR0[W] H
XXXXXXXX XXXXXXXX
-
TMR0[R] H,W
XXXXXXXX XXXXXXXX
TMCSR0[R/W] B,H
----0000 00000000
Reserved
00000050H
TMRLR1[W] H
XXXXXXXX XXXXXXXX
TMR1[R] H,W
XXXXXXXX XXXXXXXX
00000054H
-
TMCSR1[R/W] B,H
----0000 00000000
00000058H
TMRLR2[W] H
XXXXXXXX XXXXXXXX
TMR2[R] H,W
XXXXXXXX XXXXXXXX
-
TMCSR2[R/W] B,H
----0000 00000000
0000005CH
00000060H
to
00000064H
00000068H
0000006CH
to
0000007CH
DACR1[R/W]
B, H, W
-------0
DACR0[R/W]
B, H, W
-------0
Reload Timer
1
Reload Timer
2
Reserved
DADR1[R/W]
B, H, W
XXXXXXXX
-
Reload Timer
0
DADR0[R/W]
B, H, W
XXXXXXXX
D/A converter
Reserved
(Continued)
DS07-16806-5E
31
MB91220 Series
Address
Register
+0
+1
+2
+3
00000080H
-
SGDBL0[R/W] B
-------0
00000084H
SGAR0[R/W]
B,H,W
00000000
SGFR0[R/W]
B,H,W
XXXXXXXX
00000088H
-
SGDBL1[R/W] B
-------0
0000008CH
SGAR1[R/W]
B,H,W
00000000
SGFR1[R/W]
B,H,W
XXXXXXXX
00000090H
-
SGDBL2[R/W] B
-------0
00000094H
SGAR2[R/W]
B,H,W
00000000
SGFR2[R/W]
B,H,W
XXXXXXXX
00000098H
LCDCMR[R/W]
B,H,W
----0000
-
0000009CH
VRAM0 [R/W]
B,H,W
00000000
VRAM1[R/W]
B,H,W
00000000
VRAM2 [R/W]
B,H,W
00000000
VRAM3 [R/W]
B,H,W
00000000
000000A0H
VRAM4 [R/W]
B,H,W
00000000
VRAM5 [R/W]
B,H,W
00000000
VRAM6 [R/W]
B,H,W
00000000
VRAM7 [R/W]
B,H,W
00000000
000000A4H
VRAM8 [R/W]
B,H,W
00000000
VRAM9 [R/W]
B,H,W
00000000
VRAM10[R/W]
B,H,W
00000000
VRAM11[R/W]
B,H,W
00000000
000000A8H
VRAM12[R/W]
B,H,W
00000000
VRAM13[R/W]
B,H,W
00000000
VRAM14[R/W]
B,H,W
00000000
VRAM15[R/W]
B,H,W
00000000
SGCR0[R/W] B,H,W
0-----00 00000000
SGTR0[R/W]
B,H,W
XXXXXXXX
SGDR0[R/W]
B,H,W
XXXXXXXX
SGCR1[R/W] B,H,W
0-----00 00000000
SGTR1[R/W]
B,H,W
XXXXXXXX
SGDR1[R/W]
B,H,W
XXXXXXXX
SGCR2[R/W, R] B,H,W
0-----00 00000000
SGTR2[R/W]
B,H,W
XXXXXXXX
SGDR2[R/W]
B,H,W
XXXXXXXX
-
000000B0H
SCR3 [R/W] B,H,W SMR3 [R/W] B,H,W SSR3 [R/W] B,H,W RDR3 [R/W] B,H,W
00000000
00000000
00001000
00000000
000000B8H
000000BCH
ESCR3[R/W]
B,H,W
00000X00
ECCR3[R/ W]
B,H,W
000000XX
Sound
Generator 0
Sound
Generator 1
Sound
Generator 2
LCR0 [R/W] B,H,W LCR1 [R/W] B,H,W
00010000
00000000
000000ACH
000000B4H
Block
LCD
Controller
Driver
Reserved
BGR13[R/W]
B,H,W
-0000000
BGR03[R/W]
B,H,W
00000000
LIN-UART1
SCR4 [R/W] B,H,W SMR4 [R/W] B,H,W SSR4 [R/W] B,H,W RDR4 [R/W] B,H,W
00000000
00000000
00001000
00000000
ESCR4[R/W]
B,H,W
00000X00
ECCR4[R/W]
B,H,W
000000XX
BGR14[R/W]
B,H,W
-0000000
BGR04[R/W]
B,H,W
00000000
LIN-UART2
(Continued)
32
DS07-16806-5E
MB91220 Series
Register
Address
000000C0H
+0
+2
+3
Block
SCR5 [R/W] B,H,W SMR5 [R/W] B,H,W SSR5 [R/W] B,H,W RDR5 [R/W] B,H,W
00000000
00000000
00001000
00000000
ESCR5[R/W]
B,H,W
00000X00
000000C4H
000000C8H
+1
ECCR5[R/W]
B,H,W
000000XX
BGR15[R/W]
B,H,W
-0000000
BGR05 [R/W]
B,H,W
00000000
LIN-UART3
SCR0 [R/W] B,H,W SMR0 [R/W] B,H,W SSR0 [R/W] B,H,W RDR0 [R/W] B,H,W
00000000
00000000
00001000
00000000
000000CCH
ESCR0[R/W]
B,H,W
00000X00
ECCR0[R/W]
B,H,W
000000XX
000000D0H
BGR10[R/W]
B,H,W
-0000000
BGR00[R/W]
B,H,W
00000000
-
LIN-UART0
Reserved
000000D4H
TCDT0 [R/W] H,W
00000000 00000000
-
TCCS0 [R/W]
B,H,W
00000000
16-bit
Free-Run
Timer 0
000000D8H
TCDT1 [R/W] H,W
00000000 00000000
-
TCCS1 [R/W]
B,H,W
00000000
16-bit
Free-Run
Timer 1
000000DCH
to
000000E0H
000000E4H
000000E8H
000000ECH
000000F0H
IPCP1 [R] H,W
XXXXXXXX XXXXXXXX
-
0000010CH
00000110H
00000114H
to
0000012CH
-
IPCP3 [R] H,W
XXXXXXXX XXXXXXXX
ICS01 [R/W] B,H,W
00000000
IPCP2 [R] H,W
XXXXXXXX XXXXXXXX
-
000000F4H
to
00000104H
00000108H
IPCP0 [R] H,W
XXXXXXXX XXXXXXXX
-
-
Reserved
-
ICS23 [R/W] B,H,W
00000000
OCCP1 [R/W] H,W
XXXXXXXX XXXXXXXX
-
16-bit ICU
0, 1
16-bit ICU
2, 3
Reserved
OCCP0 [R/W] H,W
XXXXXXXX XXXXXXXX
-
-
-
16-bit OCU
0, 1
OCS01 [R/W] B,H,W
---0--00 0000--00
-
-
Reserved
(Continued)
DS07-16806-5E
33
MB91220 Series
Address
Register
+0
+1
+2
+3
00000130H
PWCSR0[R/W] B,H,W
0000000X 00000000
PWCR0[R] H,W
00000000 00000000
00000134H
-
-
00000138H
PDIVR0[R/W]
B,H,W
-----000
-
0000013CH
to
00000140H
PWC
-
-
-
Reserved
00000144H
-
WTDBL [R/W] B
00000000
00000148H
-
WTBR1 [R/W] B
---XXXXX
WTBR2 [R/W] B
XXXXXXXX
WTBR3 [R/W] B
XXXXXXXX
0000014CH
WTHR [R/W] B,H
---00000
WTMR [R/W] B,H
--000000
WTSR [R/W] B
--000000
-
00000150H
ADERH[R/W] B,H,W
11111111 11111111
WTCR [R/W] B,H
00000000 000-0000
ADCS1[R/W]
B,H,W
00000000
ADCS0[R/W]
B,H,W
00000000
ADCR1[R] B,H,W
------XX
ADCR0[R] B,H,W
XXXXXXXX
00000158H
ADCT1[R/W]
B,H,W
00010000
ADCT0[R/W]
B,H,W
00101100
ADSCH[R/W]
B,H,W
---00000
ADECH[R/W]
B,H,W
---00000
0000015CH
CUCR[R/W] B,H,W
-------- ---0--00
CUTD[R/W] B,H,W
10000000 00000000
00000160H
CUTR1[R] B,H,W
-------- 00000000
CUTR2[R] B,H,W
00000000 00000000
00000164H
PWC20[R/W] H,W
------XX XXXXXXXX
PWC10[R/W] H,W
------XX XXXXXXXX
00000168H
-
PWC21[R/W] H,W
------XX XXXXXXXX
0000016CH
00000170H
-
PWC22[R/W] H,W
------XX XXXXXXXX
00000174H
00000178H
PWC1[R/W] B
-0000--0
-
PWC2[R/W] B
-0000--0
Real Time
Clock
ADERL[R/W] B,H,W
11111111 11111111
00000154H
PWC0[R/W] B
-0000--0
Block
PWS20[R/W]
B,H,W
-0000000
PWS10[R/W]
B,H,W
--000000
A/D converter
Clock
Calibrator
SMC0
PWC11[R/W] H,W
------XX XXXXXXXX
PWS21[R/W]
B,H,W
-0000000
PWS11[R/W]
B,H,W
--000000
SMC1
PWC12[R/W] H,W
------XX XXXXXXXX
PWS22[R/W]
B,H,W
-0000000
PWS12[R/W]
B,H,W
--000000
SMC2
(Continued)
34
DS07-16806-5E
MB91220 Series
Register
Address
+0
+1
+2
PWC23[R/W] H,W
------XX XXXXXXXX
0000017CH
00000180H
-
+3
PWC13[R/W] H,W
------XX XXXXXXXX
PWS23[R/W]
B,H,W
-0000000
PWC3[R/W] B
-0000--0
00000184H
to
000001A4H
PWS13[R/W]
B,H,W
--000000
CANPRE[R/W]
B,H,W
0---0000
000001A8H
Reserved
000001ACH
-
TRG0[R/W] B,H,W
00000000
-
-
-
REVC0[R/W]
B,H,W
00000000
PRLH0[R/W]B,H,W PRLL0[R/W]B,H,W PRLH1[R/W]B,H,W PRLL1[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001B8H
PRLH2[R/W]B,H,W PRLL2[R/W]B,H,W PRLH3[R/W]B,H,W PRLL3[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGC0[R/W]
B,H,W
0000000-
PPGC1[R/W]
B,H,W
00000---
CAN
Prescaler
Reserved
000001B4H
000001BCH
SMC3
Reserved
-
000001B0H
Block
PPGC2[R/W]
B,H,W
0000000-
PPGC3[R/W]
B,H,W
00000---
000001C0H
PRLH4[R/W]B,H,W PRLL4[R/W]B,H,W PRLH5[R/W]B,H,W PRLL5[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001C4H
PRLH6[R/W]B,H,W PRLL6[R/W]B,H,W PRLH7[R/W]B,H,W PRLL7[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001C8H
PPGC4[R/W]
B,H,W
0000000-
PPGC5[R/W]
B,H,W
00000---
PPGC6[R/W]
B,H,W
0000000-
PPGC7[R/W]
B,H,W
00000---
000001CCH
-
-
-
-
000001D0H
TRG1[R/W] B,H,W
00000000
-
REVC1[R/W]
B,H,W
00000000
-
000001D4H
PRLH8[R/W]B,H,W PRLL8[R/W]B,H,W PRLH9[R/W]B,H,W PRLL9[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001D8H
PRLHA[R/W]B,H,W PRLLA[R/W]B,H,W PRLHB[R/W]B,H,W PRLLB[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001DCH
PPGC8[R/W]
B,H,W
0000000-
PPGC9[R/W]
B,H,W
00000---
PPGCA[R/W]
B,H,W
0000000-
PPGCB[R/W]
B,H,W
00000---
000001E0H
PRLHC[R/W]
B,H,W
XXXXXXXX
PRLLC[R/W]B,H,W
XXXXXXXX
PRLHD[R/W]
B,H,W
XXXXXXXX
PRLLD[R/W]B,H,W
XXXXXXXX
PPG
ch.0 to ch.7
PPG
ch.8 to ch.15
(Continued)
DS07-16806-5E
35
MB91220 Series
Address
000001E4H
Register
+0
+1
+2
+3
PRLHE[R/W]B,H,W PRLLE[R/W]B,H,W PRLHF[R/W]B,H,W PRLLF[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000001E8H
PPGCC[R/W]
B,H,W
0000000-
PPGCD[R/W]
B,H,W
00000---
PPGCE[R/W]
B,H,W
0000000-
PPGCF[R/W]
B,H,W
00000---
000001ECH
-
-
-
-
000001F0H
to
000001FCH
-
00000200H
DMACA0[R/W] B,H,W *1
00000000 ----0000 00000000 00000000
00000204H
DMACB0[R/W] B,H,W
00000000 00000000 00000000 00000000
00000208H
DMACA1[R/W] B,H,W *1
00000000 ----0000 00000000 00000000
0000020CH
DMACB1[R/W] B,H,W
00000000 00000000 00000000 00000000
00000210H
DMACA2[R/W] B,H,W *1
00000000 ----0000 00000000 00000000
00000214H
DMACB2[R/W] B,H,W
00000000 00000000 00000000 00000000
00000218H
DMACA3[R/W] B,H,W *1
00000000 ----0000 00000000 00000000
0000021CH
DMACB3[R/W] B,H,W
00000000 00000000 00000000 00000000
00000220H
DMACA4[R/W] B,H,W *1
00000000 ----0000 00000000 00000000
00000224H
DMACB4[R/W] B,H,W
00000000 00000000 00000000 00000000
00000228H
to
0000023CH
Reserved
00000240H
00000244H
to
000003ECH
Block
DMACR[R/W] B
0--00000
XXXXXXXX
Reserved
XXXXXXXX
-
PPG1
DMAC
XXXXXXXX
Reserved
(Continued)
36
DS07-16806-5E
MB91220 Series
Register
Address
+0
+1
+2
+3
000003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00000400H
DDR0[R/W] B,H,W DDR1[R/W] B,H,W DDR2[R/W] B,H,W DDR3[R/W] B,H,W
00000000
00000000
00000000
00000000
00000404H
DDR4[R/W] B,H,W DDR5[R/W] B,H,W DDR6[R/W] B,H,W DDR7[R/W] B,H,W
00000000
00000000
00000000
----0000
00000408H
DDR8[R/W] B,H,W DDR9[R/W] B,H,W DDRA[R/W] B,H,W DDRB[R/W] B,H,W
00000000
00000000
----0000
00000000
0000040CH
DDRC[R/W] B,H,W DDRD[R/W] B,H,W DDRE[R/W] B,H,W DDRF[R/W] B,H,W
----0000
1111---00000000
00000000
00000410H
DDRG[R/W] B,H,W
----0000
-
00000414H
to
0000041CH
-
Bit Search
Data
Direction
Register
-
-
Reserved
00000420H
PFR0[R/W] B,H,W
00000000
PFR1[R/W] B,H,W
00000000
PFR2[R/W] B,H,W
00000000
PFR3[R/W] B,H,W
00000000
00000424H
PFR4[R/W] B,H,W
00000000
PFR5[R/W] B,H,W
00000000
Reserved
PFR7[R/W] B,H,W
----0000
00000428H
PFR8[R/W] B,H,W
00000000
PFR9[R/W] B,H,W
00000000
PFRA[R/W] B,H,W
----0000
0000042CH
PFRC[R/W] B,H,W PFRD[R/W] B,H,W PFRE[R/W] B,H,W
----0000
00000000
00000000
00000430H
PFRG[R/W] B,H,W
----0000
-
Block
-
PFRB[R/W] B,H,W Port Function
Register
00000000
PFRF[R/W] B,H,W
00000000
-
00000434H
to
0000043CH
-
00000440H
ICR00[R/W] B,H,W ICR01[R/W] B,H,W ICR02[R/W] B,H,W ICR03[R/W] B,H,W
---11111
---11111
---11111
---11111
00000444H
ICR04[R/W] B,H,W ICR05[R/W] B,H,W ICR06[R/W] B,H,W ICR07[R/W] B,H,W
---11111
---11111
---11111
---11111
00000448H
ICR08[R/W] B,H,W ICR09[R/W] B,H,W ICR10[R/W] B,H,W ICR11[R/W] B,H,W
---11111
---11111
---11111
---11111
0000044CH
ICR12[R/W] B,H,W ICR13[R/W] B,H,W ICR14[R/W] B,H,W ICR15[R/W] B,H,W
---11111
---11111
---11111
---11111
Reserved
Interrupt
Control Unit
(Continued)
DS07-16806-5E
37
MB91220 Series
Address
Register
+0
+1
+2
+3
00000450H
ICR16[R/W] B,H,W ICR17[R/W] B,H,W ICR18[R/W] B,H,W ICR19[R/W] B,H,W
---11111
---11111
---11111
---11111
00000454H
ICR20[R/W] B,H,W ICR21[R/W] B,H,W ICR22[R/W] B,H,W ICR23[R/W] B,H,W
---11111
---11111
---11111
---11111
00000458H
ICR24[R/W] B,H,W ICR25[R/W] B,H,W ICR26[R/W] B,H,W ICR27[R/W] B,H,W
---11111
---11111
---11111
---11111
0000045CH
ICR28[R/W] B,H,W ICR29[R/W] B,H,W ICR30[R/W] B,H,W ICR31[R/W] B,H,W
---11111
---11111
---11111
---11111
00000460H
ICR32[R/W] B,H,W ICR33[R/W] B,H,W ICR34[R/W] B,H,W ICR35[R/W] B,H,W
---11111
---11111
---11111
---11111
00000464H
ICR36[R/W] B,H,W ICR37[R/W] B,H,W ICR38[R/W] B,H,W ICR39[R/W] B,H,W
---11111
---11111
---11111
---11111
00000468H
ICR40[R/W] B,H,W ICR41[R/W] B,H,W ICR42[R/W] B,H,W ICR43[R/W] B,H,W
---11111
---11111
---11111
---11111
0000046CH
ICR44[R/W] B,H,W ICR45[R/W] B,H,W ICR46[R/W] B,H,W ICR47[R/W] B,H,W
---11111
---11111
---11111
---11111
00000470H
to
0000047CH
-
00000480H
00000484H
CLKR [W] B,H,W
00000000
WPR [R/W] B,H,W
XXXXXXXX
DIVR0 [R/W]
B,H,W
00000011
00000488H
-
-
OSCCR [R/W] B
00000000
00000490H
00000494H
to
000004ACH
CTBR [W] B,H,W
XXXXXXXX
DIVR1 [R/W]
B,H,W
00000000
-
Clock Control
Unit
Clock Control
Unit
Reserved
OSCR [R/W] B
00000001
Interrupt
Control Unit
Reserved
RSRR [R/W] B,H,W STCR [R/W] B,H,W TBCR [R/W] B,H,W
10000000
00110011
00XXXX11
0000048CH
Block
Reserved
-
Reserved
(Continued)
38
DS07-16806-5E
MB91220 Series
Register
Address
+0
+1
+2
+3
000004B0H
-
TRG2[R/W] B,H,W
00000000
-
REVC2[R/W]
B,H,W
00000000
000004B4H
PRLHG[R/W]
B,H,W
00000000
PRLLG[R/W]B,H,W
XXXXXXXX
PRLHH[R/W]
B,H,W
XXXXXXXX
PRLLH[R/W]B,H,W
XXXXXXXX
000004B8H
PRLHI[R/W]B,H,W
00000000
000004BCH
PPGCG[R/W]
B,H,W
0000000-
000004C0H
PRLLI[R/W]B,H,W PRLHJ[R/W]B,H,W PRLLJ[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGCH[R/W]
B,H,W
00000---
PPGCI[R/W]B,H,W PPGCJ[R/W]B,H,W
000000000000---
PPG
ch.16 to ch.23
PRLHK[R/W]B,H,W PRLLK[R/W]B,H,W PRLHL[R/W]B,H,W PRLLL[R/W]B,H,W
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
000004C4H
PRLHM[R/W]
B,H,W
00000000
PRLLM[R/W]B,H,W
XXXXXXXX
PRLHN[R/W]
B,H,W
XXXXXXXX
PRLLN[R/W]B,H,W
XXXXXXXX
000004C8H
PPGCK[R/W]
B,H,W
0000000-
PPGCL[R/W]
B,H,W
00000---
PPGCM[R/W]
B,H,W
0000000-
PPGCN[R/W]
B,H,W
00000---
REVC3[R/W]
B,H,W
00000000
-
000004CCH
-
000004D0H
TRG3[R/W] B,H,W
00000000
000004D4H
PRLHO[R/W]
B,H,W
00000000
PRLLO[R/W]B,H,W PRLHP[R/W]B,H,W PRLLP[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
000004D8H
PRLHQ[R/W]
B,H,W
00000000
PRLLQ[R/W]B,H,W
XXXXXXXX
PRLHR[R/W]
B,H,W
XXXXXXXX
PRLLR[R/W]B,H,W
XXXXXXXX
000004DCH
PPGCO[R/W]
B,H,W
0000000-
PPGCP[R/W]
B,H,W
00000---
PPGCQ[R/W]
B,H,W
0000000-
PPGCR[R/W]
B,H,W
00000---
000004E0H
Block
-
PPG
ch.24 to ch.31
PRLHS[R/W]B,H,W PRLLS[R/W]B,H,W PRLHT[R/W]B,H,W PRLLT[R/W]B,H,W
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
000004E4H
PRLHU[R/W]
B,H,W
00000000
000004E8H
PPGCS[R/W]
B,H,W
0000000-
000004ECH
PRLLU[R/W]B,H,W PRLHV[R/W]B,H,W PRLLV[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGCT[R/W]
B,H,W
00000---
PPGCU[R/W]
B,H,W
0000000-
PPGCV[R/W]
B,H,W
00000---
(Continued)
DS07-16806-5E
39
MB91220 Series
Address
Register
+0
+1
000004F0H
to
000004F8H
000004FCH
+2
+3
PSCR[W] B
00000000
-
00000500H
to
0000053CH
Reserved
-
-
PILR0[R/W] B
00000000
PILR1[R/W] B
00000000
Reserved
Reserved
00000544H
PILR4[R/W] B
00000000
PILR5[R/W] B
00000000
Reserved
-
PILRE[R/W] B
00000000
Reserved
0000054CH
-
-
00000550H
-
00000554H
to
0000055CH
-
00000560H
IBCR0[R/W] B,H,W
00000000
IBSR0[R] B,H,W
00000000
00000564H
ITMKH0[R/W]
B,H,W
00----11
ITMKL0[R/W]
B,H,W
11111111
00000568H
-
0000056CH
IBCR1[R/W] B,H,W
00000000
IBSR1[R] B,H,W
00000000
00000570H
ITMKH1[R/W]
B,H,W
00----11
ITMKL1[R/W]
B,H,W
11111111
00000574H
-
0000057CH
00000580H
to
000005FCH
ITBAH0[R/W]
B,H,W
------00
ITBAL0[R/W]
B,H,W
00000000
ISMK0[R/W] B,H,W ISBA0[R/W] B,H,W
01111111
-0000000
ITBAH1[R/W]
B,H,W
------00
ITBAL1[R/W]
B,H,W
00000000
ISMK1[R/W] B,H,W ISBA1[R/W] B,H,W
01111111
-0000000
IDAR1[R/W] B,H,W ICCR1[R/W] B,H,W
00000000
-0011111
LVRC[R/W] B,H,W
00011000
I2C1
Reserved
Reserved
Reserved
-
I2C0
Reserved
Reserved
Port Input
Level Select
Register
Reserved
IDAR0[R/W] B,H,W ICCR0[R/W] B,H,W
00000000
-0011111
00000578H
Port Input
Level Select
Register
Reserved
00000540H
00000548H
Block
Reserved
Detection of
CPU
operation
Reserved
(Continued)
40
DS07-16806-5E
MB91220 Series
Register
Address
+0
+1
+2
+3
00000600H
Reserved
Reserved
EPFR2[R/W]
B,H,W
00000000
EPFR3[R/W]
B,H,W
00000000
00000604H
EPFR4[R/W]
B,H,W
11111111
EPFR5[R/W]
B,H,W
00000000
-
EPFR7[R/W]
B,H,W
----0000
00000608H
EPFR8[R/W]
B,H,W
00000000
EPFR9[R/W]
B,H,W
00000000
-
-
0000060CH
-
EPFRD[R/W]
B,H,W
00000000
EPFRE[R/W]
B,H,W
00000000
EPFRF[R/W]
B,H,W
00000000
00000610H
EPFRG[R/W]
B,H,W
----0000
-
-
-
00000614H
to
0000063CH
ASR0 [R/W] B,H,W
00000000 00000000
ACR0 [R/W] B,H,W
00110*00 00000000
00000644H
ASR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B,H,W
XXXX0X00 00X0XXXX
00000648H
ASR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B,H,W
XXXX0X00 00X0XXXX
0000064CH
ASR3 [R/W] B,H,W
00000000 XXXXXXXX
ACR3 [R/W] B,H,W
01XX0X00 00X0XXXX
Reserved
T-unit
00000660H
AWR0 [R/W] B,H,W
01110000 01011011
AWR1 [R/W] B,H,W
XXXX0000 XX0X1XXX
00000664H
AWR2 [R/W] B,H,W
0XXX0000 XX0X1XXX
AWR3 [R/W] B,H,W
0XXX0000 0X0X1XXX
00000668H
to
0000067CH
00000680H
I/O
port
Reserved
00000640H
00000650H
to
0000065CH
Block
Reserved
CSER[R/W] B,H,W
00000001
-
00000684H
to
000007F8H
000007FCH
-
-
-
MODR *2
Reserved
-
-
(Continued)
DS07-16806-5E
41
MB91220 Series
Address
Register
+0
+1
00000800H
to
00000FFCH
+2
+3
Block
Reserved
00001000H
DMASA0[R/W] W
00000000 00000000 00000000 00000000
00001004H
DMADA0[R/W] W
00000000 00000000 00000000 00000000
00001008H
DMASA1[R/W] W
00000000 00000000 00000000 00000000
0000100CH
DMADA1[R/W] W
00000000 00000000 00000000 00000000
00001010H
DMASA2[R/W] W
00000000 00000000 00000000 00000000
00001014H
DMADA2[R/W] W
00000000 00000000 00000000 00000000
00001018H
DMASA3[R/W] W
00000000 00000000 00000000 00000000
0000101CH
DMADA3[R/W] W
00000000 00000000 00000000 00000000
00001020H
DMASA4[R/W] W
00000000 00000000 00000000 00000000
00001024H
DMADA4[R/W] W
00000000 00000000 00000000 00000000
00001028H
to
00006FFCH
DMAC
Reserved
00007000H
FLCR[R/W] B
01X0X000
-
-
-
00007004H
FLWC[R/W] B
00000011
-
-
-
Flash I/F
00007008H
to
0000FFFCH
Reserved
00020000H
CTRLR0 [R/W] B,H,W
00000000 00000001
STATR0 [R/W] B,H,W
00000000 00000000
00020004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0 [R/W] B,H,W
00100011 00000001
00020008H
INTR0 [R] B,H,W
00000000 00000000
TESTR0 [R/W] B,H,W
00000000 r0000000*
(r : indication the level on the CAN bus)
0002000CH
BRPER0 [R/W] B,H,W
00000000 00000000
Reserved
CAN0
(Continued)
42
DS07-16806-5E
MB91220 Series
Address
Register
+0
+1
+2
+3
00020010H
IF1CREQ0 [R/W] B,H,W
00000000 00000001
IF1CMSK0 [R/W] B,H,W
00000000 00000000
00020014H
IF1MSK20 [R/W] B,H,W
11111111 11111111
IF1MSK10 [R/W] B,H,W
11111111 11111111
00020018H
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1ARB10 [R/W] B,H,W
00000000 00000000
0002001CH
IF1MCTR0 [R/W] B,H,W
00000000 00000000
-
00020020H
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTA20 [R/W] B,H,W
00000000 00000000
00020024H
IF1DTB10 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W] B,H,W
00000000 00000000
00020028H
to
0002002CH
Block
Reserved
00020030H
IF1DTA20 [R/W] B,H,W
00000000 00000000
IF1DTA10 [R/W] B,H,W
00000000 00000000
00020034H
IF1DTB20 [R/W] B,H,W
00000000 00000000
IF1DTB10 [R/W] B,H,W
00000000 00000000
00020038H
to
0002003CH
CAN0
Reserved
00020040H
IF2CREQ0 [R/W] B,H,W
00000000 00000001
IF2CMSK0 [R/W] B,H,W
00000000 00000000
00020044H
IF2MSK20 [R/W] B,H,W
00000000 00000000
IF2MSK10 [R/W] B,H,W
00000000 00000000
00020048H
IF2ARB20 [R/W] B,H,W
00000000 00000000
IF2ARB10 [R/W] B,H,W
00000000 00000000
0002004CH
IF2MCTR0 [R/W] B,H,W
00000000 00000000
-
00020050H
IF2DTA10 [R/W] B,H,W
00000000 00000000
IF2DTA20 [R/W] B,H,W
00000000 00000000
00020054H
IF2DTB10 [R/W] B,H,W
00000000 00000000
IF2DTB20 [R/W] B,H,W
00000000 00000000
00020058H
to
0002005CH
Reserved
00020060H
IF2DTA20 [R/W] B,H,W
00000000 00000000
IF2DTA10 [R/W] B,H,W
00000000 00000000
00020064H
IF2DTB20 [R/W] B,H,W
00000000 00000000
IF2DTB10 [R/W] B,H,W
00000000 00000000
(Continued)
DS07-16806-5E
43
MB91220 Series
Address
Register
+0
+1
00020068H
to
0002007CH
00020080H
TREQR20 [R] B,H,W
00000000 00000000
TREQR10 [R] B,H,W
00000000 00000000
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
CAN0
Reserved
INTPEND20 [R] B,H,W
00000000 00000000
000200A4H
to
000200ACH
000200B0H
Block
Reserved
00020094H
to
0002009CH
000200A0H
+3
Reserved
00020084H
to
0002008CH
00020090H
+2
INTPEND10 [R] B,H,W
00000000 00000000
Reserved
MESVAL20 [R] B,H,W
00000000 00000000
000200B4H
to
000200BCH
MESVAL10 [R] B,H,W
00000000 00000000
Reserved
00020100H
CTRLR1 [R/W] B,H,W
00000000 00000001
STATR1 [R/W] B,H,W
00000000 00000000
00020104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1 [R/W] B,H,W
00100011 00000001
00020108H
INTR1 [R] B,H,W
00000000 00000000
TESTR1 [R/W] B,H,W
00000000 r0000000*
0002010CH
BRPER1 [R/W] B,H,W
00000000 00000000
Reserved
00020110H
IF1CREQ1 [R/W] B,H,W
00000000 00000001
IF1CMSK1 [R/W] B,H,W
00000000 00000000
00020114H
IF1MSK21 [R/W] B,H,W
11111111 11111111
IF1MSK11 [R/W] B,H,W
11111111 11111111
00020118H
IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1ARB11 [R/W] B,H,W
00000000 00000000
CAN1
(Continued)
44
DS07-16806-5E
MB91220 Series
Address
Register
+0
+1
+2
+3
0002011CH
IF1MCTR1 [R/W] B,H,W
00000000 00000000
-
00020120H
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTA21 [R/W] B,H,W
00000000 00000000
00020124H
IF1DTB11 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
00020128H
to
0002012CH
Reserved
00020130H
IF1DTA21 [R/W] B,H,W
00000000 00000000
IF1DTA11 [R/W] B,H,W
00000000 00000000
00020134H
IF1DTB21 [R/W] B,H,W
00000000 00000000
IF1DTB11 [R/W] B,H,W
00000000 00000000
00020138H
to
0002013CH
Reserved
00020140H
IF2CREQ1 [R/W] B,H,W
00000000 00000001
IF2CMSK1 [R/W] B,H,W
00000000 00000000
00020144H
IF2MSK21 [R/W] B,H,W
00000000 00000000
IF2MSK11 [R/W] B,H,W
00000000 00000000
00020148H
IF2ARB21 [R/W] B,H,W
00000000 00000000
IF2ARB11 [R/W] B,H,W
00000000 00000000
0002014CH
IF2MCTR1 [R/W] B,H,W
00000000 00000000
-
00020150H
IF2DTA11 [R/W] B,H,W
00000000 00000000
IF2DTA21 [R/W] B,H,W
00000000 00000000
00020154H
IF2DTB11 [R/W] B,H,W
00000000 00000000
IF2DTB21 [R/W] B,H,W
00000000 00000000
00020158H
to
0002015CH
CAN1
Reserved
00020160H
IF2DTA21 [R/W] B,H,W
00000000 00000000
IF2DTA11 [R/W] B,H,W
00000000 00000000
00020164H
IF2DTB21 [R/W] B,H,W
00000000 00000000
IF2DTB11 [R/W] B,H,W
00000000 00000000
00020168H
to
0002017CH
00020180H
Block
Reserved
TREQR21 [R] B,H,W
00000000 00000000
TREQR11 [R] B,H,W
00000000 00000000
(Continued)
DS07-16806-5E
45
MB91220 Series
(Continued)
Address
Register
+0
+1
00020184H
to
0002018CH
00020190H
NEWDT21 [B] B,H,W
00000000 00000000
000201B4H
to
000201BCH
Block
NEWDT11 [R] B,H,W
00000000 00000000
Reserved
INTPEND21 [R] B,H,W
00000000 00000000
000201A4H
to
000201ACH
000201B0H
+3
Reserved
00020194H
to
0002019CH
000201A0H
+2
INTPEND11 [R] B,H,W
00000000 00000000
CAN1
Reserved
MESVAL21 [R] B,H,W
00000000 00000000
MESVAL11 [R] B,H,W
00000000 00000000
Reserved
*1 : The lower 16 bits (DTC [15 : 0] ) of DMCA0 to DMCA4 cannot be accessed in bytes.
*2 : This register is set when the mode vector is fetched. Not user-accessible.
Notes : • Do not perform read modify write instructions to a register including write-on-bit.
• The data in the area reserved or - is undefined.
46
DS07-16806-5E
MB91220 Series
■ VECTOR TABLE
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
DMA
start
source
Decimal
Hexadecimal
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
System reserved
10
0A
⎯
3D4H
000FFFD4H
⎯
System reserved
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (ICE)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI instruction
15
0F
0FH
Fixed
3C0H
000FFFC0H
⎯
External interrupt 0/1/2/6/7
16
10
ICR00
3BCH
000FFFBCH
⎯
External interrupt 3
17
11
ICR01
3B8H
000FFFB8H
6
External interrupt 4
18
12
ICR02
3B4H
000FFFB4H
7
External interrupt 5
19
13
ICR03
3B0H
000FFFB0H
⎯
PPG0H/0L/8H/8L
20
14
ICR04
3ACH
000FFFACH
⎯
PPG2H/2L/9H/9L
21
15
ICR05
3A8H
000FFFA8H
⎯
PPG4H/4L/10H/10L
22
16
ICR06
3A4H
000FFFA4H
⎯
PPG6H/6L/11H/11L
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
LIN-UART0 (Reception)
27
1B
ICR11
390H
000FFF90H
⎯
LIN-UART0 (Transmission)
28
1C
ICR12
38CH
000FFF8CH
⎯
LIN-UART1 (Reception)
29
1D
ICR13
388H
000FFF88H
1
LIN-UART1 (Transmission)
30
1E
ICR14
384H
000FFF84H
4
LIN-UART2 (Reception)
31
1F
ICR15
380H
000FFF80H
2
LIN-UART2 (Transmission)
32
20
ICR16
37CH
000FFF7CH
5
LIN-UART3 (Reception)
33
21
ICR17
378H
000FFF78H
⎯
LIN-UART3 (Transmission)
34
22
ICR18
374H
000FFF74H
⎯
(Continued)
DS07-16806-5E
47
MB91220 Series
(Continued)
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
DMA
start
source
Decimal
Hexadecimal
35
23
ICR19
370H
000FFF70H
⎯
36
24
ICR20
36CH
000FFF6CH
⎯
PPG12H/12L/I C0
37
25
ICR21
368H
000FFF68H
⎯
PPG13H/13L
38
26
ICR22
364H
000FFF64H
⎯
PPG14H/14L/I C1
39
27
ICR23
360H
000FFF60H
⎯
PWC (Measurement completed)
40
28
ICR24
35CH
000FFF5CH
⎯
PWC (Overflow)
41
29
ICR25
358H
000FFF58H
⎯
DMAC
42
2A
ICR26
354H
000FFF54H
⎯
A/D converter
43
2B
ICR27
350H
000FFF50H
14
Real-time clock
44
2C
ICR28
34CH
000FFF4CH
⎯
PPG15H/15L
45
2D
ICR29
348H
000FFF48H
⎯
Main oscillation stabilization wait
timer
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
⎯
PPG1H/1L
48
30
ICR32
33CH
000FFF3CH
11
PPG3H/3L
49
31
ICR33
338H
000FFF38H
12
PPG5H/5L
50
32
ICR34
334H
000FFF34H
13
PPG7H/7L
51
33
ICR35
330H
000FFF30H
3
16-bit free-run timer 0
52
34
ICR36
32CH
000FFF2CH
⎯
16-bit free-run timer 1
53
35
ICR37
328H
000FFF28H
⎯
ICU0
54
36
ICR38
324H
000FFF24H
⎯
ICU1
55
37
ICR39
320H
000FFF20H
⎯
ICU2
56
38
ICR40
31CH
000FFF1CH
⎯
ICU3
57
39
ICR41
318H
000FFF18H
⎯
OCU0
58
3A
ICR42
314H
000FFF14H
⎯
OCU1
59
3B
ICR43
310H
000FFF10H
⎯
Sound generator 0
60
3C
ICR44
30CH
000FFF0CH
⎯
Sound generator 1
61
3D
ICR45
308H
000FFF08H
⎯
Sound generator 2
62
3E
ICR46
304H
000FFF04H
⎯
Delay interrupt
63
3F
ICR47
300H
000FFF00H
⎯
System reserved
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
to
79
42
to
4F
⎯
2F4H
to
2C0H
000FFEF4H
to
000FFEC0H
⎯
INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
CAN0
CAN1
2
2
48
DS07-16806-5E
MB91220 Series
■ TABLE OF PIN STATUS IN EACH MODE
• Single chip mode
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
INITX
INIT
Input permitted
Hi-Z or Input
permitted
X0
Main clock
"H" output or input
permitted
X1
X0A
Sub clock
Input
Input
Input
permitted permitted permitted
Hi-Z or input
permitted
"H" output or input
permitted
X1A
MD0
MD1
Mode
Input permitted
MD2
P00
SEG24
P01
SEG25
P02
SEG26
P03
SEG27
P04
SEG28
P05
SEG29
P06
SEG30
P07
SEG31/ATGX
P10
SEG16
P11
SEG17
P12
SEG18
P13
SEG19
P14
SEG20
P15
SEG21
P16
SEG22
P17
SEG23
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Previous Previous
Input
state held state held
permitted
Output
Hi-Z
Input
cut-off
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Previous Previous
Input
state held state held
permitted
Output
Hi-Z
Input
cut-off
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
(Continued)
DS07-16806-5E
49
MB91220 Series
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
P20
SEG0
P21
SEG1
P22
SEG2
P23
SEG3
P24
SEG4
P25
SEG5
P26
SEG6
P27
SEG7
P30
SEG8
P31
SEG9
P32
SEG10
P33
SEG11
P34
SEG12
P35
SEG13
P36
SEG14
P37
SEG15
P40
SIN0/INT0
P41
SOT0
P42
SCK0
P43
SIN3/INT1
P44
SOT3
P45
SCK3
P46
⎯
P47
⎯
P50
SIN4/CK0
P51
SOT4
P52
SCK4
P53
SIN5/CK1
P54
SOT5
P55
SCK5
P56
OUT0
P57
OUT1
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Previous Previous
Input
state held state held
permitted
Output
Hi-Z
Input
cut-off
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Previous Previous
Input
state held state held
permitted
Output
Hi-Z
Input
cut-off
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Input of external
interrupt is enabled
by setting PFR
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
(Continued)
50
DS07-16806-5E
MB91220 Series
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
P60
AN0
P61
AN1
P62
AN2
P63
AN3
P64
AN4
P65
AN5
P66
AN6
P67
AN7
P70
INT60/RX0
P71
TX0
P72
INT7/RX1
P73
TX1
P80
AN16
P81
AN17
P82
AN18
P83
AN19
P84
AN20
P85
AN21/INT3
P86
AN22/INT4
P87
AN23/INT5
P90
DA0
P91
DA1
P92
SGA0
P93
SGO0
P94
SGA1
P95
SGO1
P96
SGA2
P97
SGO2
PA0
PWM1P3
PA1
PWM1M3
PA2
PWM2P3
PA3
PWM2M3
Previous Previous
state held state held
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
Previous Previous
Input
permitted state held state held
permitted
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
Previous Previous
state held state held
Output
Hi-Z
Input
cut-off
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
Input of external
interrupt is enabled
by setting PFR
When DA is used,
output retention
(Continued)
DS07-16806-5E
51
MB91220 Series
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
PB0
PPG8H
PB1
PPG9H
PB2
PPG10H
PB3
PPG11H
PB4
PWM1P1
PB5
PWM1M1
PB6
PWM2P1
PB7
PWM2M1
PC0
PWM1P0
PC1
PWM1M0
PC2
PWM2P0
PC3
PWM2M0
PD0
TIN0/IN0/PWC0/INT2/V0
PD1
TIN1/IN1/V1
PD2
TIN2/IN2/V2
PD3
IN3/V3
PD4
COM0/PPG1H
PD5
COM1/PPG3H
PD6
COM2/PPG5H
PD7
COM3/PPG7H
PE0
PWM1P2
PE1
PWM1M2
PE2
PWM2P2
PE3
PWM2M2
PE4
PPG12H/SDA0
PE5
PPG13H/SCL0
PE6
PPG14H/SDA1
PE7
PPG15H/SCL1
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Input
Input
Previous
permitted permitted state held
Previous
state held
Output
Hi-Z
Input
cut-off
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
"L" output "L" output
Previous
Input
Input
state held
permitted permitted
Input of external
interrupt is enabled
by setting PFR
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
(Continued)
52
DS07-16806-5E
MB91220 Series
(Continued)
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
PF0
AN8
PF1
AN9
PF2
AN10
PF3
AN11
PF4
AN12
PF5
AN13
PF6
AN14
PF7
AN15
PG0
PPG0H
PG1
TOT0/PPG2H
PG2
TOT1/PPG4H
PG3
TOT2/PPG6H
DS07-16806-5E
Previous Previous
state held state held
Output
Hi-Z
Input
cut-off
Output
Output
Hi-Z
Previous Previous
Hi-Z
Input
state held state held
Input
permitted permitted
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
cut-off
53
MB91220 Series
• External bus mode (8-bit)
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
INITX
Input permitted
INIT
Hi-Z or Input
permitted
X0
Main clock
"H" output or input
permitted
X1
X0A
Sub clock
Input
Input
Input
permitted permitted permitted
Hi-Z or Input
permitted
"H" output or input
permitted
X1A
MD0
MD1
Input
permitted
Mode
MD2
P00
SEG24
P01
SEG25
P02
SEG26
P03
SEG27
P04
SEG28
P05
SEG29
P06
SEG30
P07
SEG31/ATGX
P10
D08
P11
D09
P12
D10
P13
D11
P14
D12
P15
D13
P16
D14
P17
D15
P20
A00
P21
A01
P22
A02
P23
A03
P24
A04
P25
A05
P26
A06
P27
A07
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Previous Previous
Input
state held state held
permitted
Output
Hi-Z
Input
cut-off
When LCD is used,
output operation or
output retention for
both SLEEP/STOP
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Hi-Z
Hi-Z
Output
Hi-Z
Input
cut-off
No port function
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Address
output
Address
output
Output
Hi-Z
Input
cut-off
No port function
(Continued)
54
DS07-16806-5E
MB91220 Series
(Continued)
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
Remarks
HIZ=0
HIZ=1
Address
output
Output
Hi-Z
Input
cut-off
No port function
Output
Hi-Z
Input
cut-off
Input of external
interrupt is enabled
by setting PFR
When external bus
signal is used, "H"
output/clock output
for SLEEP/STOP
(Hi-Z=0)
Output
Hi-Z
Input
cut-off
When external bus
signal is used, "H"
output for SLEEP/
STOP (Hi-Z=0)
State
P30
A08
P31
A09
P32
A10
P33
A11
P34
A12
P35
A13
P36
A14
P37
A15
P40
SIN0/INT0
P41
SOT0
P42
SCK0
P43
SIN3/INT1
P44
SOT3
P45
SCK3
P46
ASX
"H"
output
P47
SYSCLK
Clock
output
P50
SIN4/CK0/CS0X
P51
SOT4/CS1X
P52
SCK4/CS2X
P53
SIN5/CK1/CS3X
P54
SOT5/RDX
P55
SCK5/WR0X
P56
OUT0
P57
OUT1/RDY
P60
to
PG3
DS07-16806-5E
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
permitted
Address
output
Output
Hi-Z
Input
permitted Previous Previous
state held state held
Output
Hi-Z
Input
Previous Previous
permitted state held state held
Input
permitted
It is the same as the single chip mode.
55
MB91220 Series
• External bus mode (16-bit)
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
HIZ=0
HIZ=1
Remarks
State
INITX
Input permitted
INIT
X0
X1
Hi-Z or Input permitted
Main clock
X0A
X1A
Sub clock
"H" output or input
permitted
Input
permitted
Input
permitted
Input
permitted
Hi-Z or Input permitted
"H" output or input
permitted
MD0
MD1
Mode
Input permitted
MD2
P00
D00
P01
D01
P02
D02
P03
D03
P04
D04
P05
D05
P06
D06
P07
D07
P10
D08
P11
D09
P12
D10
P13
D11
P14
D12
P15
D13
P16
D14
P17
D15
P20
A00
P21
A01
P22
A02
P23
A03
P24
A04
P25
A05
P26
A06
P27
A07
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Hi-Z
Output
Hi-Z
Input
cut-off
No port function
Hi-Z
Hi-Z
Output
Hi-Z
Input
cut-off
No port function
Address
output
Address
output
Output
Hi-Z
Input
cut-off
No port function
Hi-Z
(Continued)
56
DS07-16806-5E
MB91220 Series
(Continued)
Initial value
Pin
Name
Function name
INITX=L
INITX=H
In
SLEEP
In STOP State
Remarks
HIZ=0
HIZ=1
Address
output
Output
Hi-Z
Input
cut-off
No port function
Output
Hi-Z
Input
cut-off
Input of external
interrupt is enabled
by setting PFR
When external bus
signal is used, "H"
output/clock output
for SLEEP/STOP
(Hi-Z=0)
Output
Hi-Z
Input
cut-off
When external bus
signal is used, "H"
output for SLEEP/
STOP (Hi-Z=0)
State
P30
A08
P31
A09
P32
A10
P33
A11
P34
A12
P35
A13
P36
A14
P37
A15
P40
SIN0/INT0
P41
SOT0
P42
SCK0
P43
SIN3/INT1
P44
SOT3
P45
SCK3
P46
ASX
"H"
output
P47
SYSCLK
Clock
output
P50
SIN4/CK0/CS0X
P51
SOT4/CS1X
P52
SCK4/CS2X
P53
SIN5/CK1/CS3X
P54
SOT5/RDX
P55
SCK5/WR0X
P56
OUT0/WR1X
P57
OUT1/RDY
P60
to
PG3
DS07-16806-5E
Output
Hi-Z
Input
cut-off
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
permitted
Output
Hi-Z
Input
permitted
Address
output
Output
Hi-Z
Input
permitted Previous Previous
state held state held
Output
Hi-Z
Input
Previous Previous
permitted state held state held
Input
permitted
It is the same as the single chip mode.
57
MB91220 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
AVCC = VCC*2
VAVRH
VSS − 0.3
VSS + 6.0
V
AVCC ≥ VAVRH
DVCC
VSS − 0.3
VSS + 6.0
V
DVCC = VCC*2
VI
VSS − 0.3
VCC + 0.3
V
*9
VO
VSS − 0.3
VCC + 0.3
V
*9
“L” level maximum output
current*3
IOL1
⎯
15
mA
*5
IOL2
⎯
40
mA
*6
“L” level average output
current*4
IOLAV1
⎯
4
mA
*5
IOLAV2
⎯
30
mA
*6
ΣIOL1
⎯
120
mA
*5
ΣIOL2
⎯
330
mA
*6
ΣIOLAV1
⎯
50
mA
*5
ΣIOLAV2
⎯
160
mA
*6
OH1 3
⎯
−15
mA
*5
IOH2*3
⎯
−40
mA
*6
IOHAV1*4
⎯
−4
mA
*5
OHAV2 4
*
⎯
−30
mA
*6
ΣIOH1
⎯
−120
mA
*5
ΣIOH2
Power supply voltage*1
Input voltage*1
Output voltage*
1
“L” level total maximum
output current
“L” level total average
output current
I
“H” level maximum output
current
“H” level average output
current
“H” level total maximum
output current
I
*
⎯
−330
mA
*6
OHAV1 7
⎯
−50
mA
*5
ΣIOHAV2*7
⎯
−160
mA
*6
Power consumption
PD
⎯
660
mW
Operating temperature
TA
−40
+105
°C
In single chip operation
0
+70
°C
In external bus operation
“H” level total average
output current
ΣI
*
Storage temperature
Tstg
−55
+150
°C
+B input standard
(Maximum clamp current)
ICLAMP
−2
+2
mA
+B input standard
(Total maximum clamp
current)
ΣICLAMP
−20
+20
mA
Except dedicated input pins, (PD3 to
PD0) and D/AC output pins (P91,
P90) *8
(Continued)
58
DS07-16806-5E
MB91220 Series
(Continued)
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : Note that AVCC and DVCC should not exceed VCC upon power-on and under other circumstances.
*3 : The maximum output current defines the peak current value of each of the corresponding pins.
*4 : The average output current defines the average value of the current (100 ms) which passes through each of
the corresponding pins. The average value represents a value calculated by multiplying the operating current
by the operating rate.
*5 : Output other than PA0 to PA3 pins, PB4 to PB7 pins, PC0 to PC3 pins, and PE0 to PE3 pins.
*6 : (PA0 to PA3, PE0 to PE3) + (PB4 to PB7, PC0 to PC3) .
The stepping motor controller pins are divided into two groups (8 pins each) and the value is calculated as the
total current per group.
*7 : The total average output current defines the average value of the current (100 ms) which passes through all
the corresponding pins. The average value represents a value calculated by multiplying the operating current
by the operating rate.
*8 : +B input standard defines the current value for each of the corresponding pins.
*9 : VI and VO should not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, when the +B input-enabled pin is used the ICLAMP rating supersedes the VI
rating.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended example circuit
MB91220 series
Protection diode
lIHH
+B Input (12 V to 16 V)
Current limiting resistor
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
DS07-16806-5E
59
MB91220 Series
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
Parameter
Power supply
voltage
Symbol
VCC
AVCC
DVCC
Smoothing
capacitor*3
CS
Operating
temperature
TA
Value
Unit
Remarks
Min
Max
4.5
5.5
V
Recommended guaranteed operating range
3.5
5.5
V
Guaranteed operating range*1
2.0
5.5
V
Guaranteed operating range for holding stop
operation status*2
(MB91F223/S, MB91F224/S)
μF
Use a ceramic capacitor or a capacitor with
similar frequency characteristics.
1
−40
+105
°C
In single chip operation
0
+70
°C
In external bus operation
*1 : Exclusive of A/D and D/A operation
*2 : Internal voltage held in RAM : 1.8 V (Min) /3.6 V (Max)
*3 : For how to connect the smoothing capacitor CS, refer to the diagram below.
• C Pin Connection Diagram
VCC3C
CS
VSS
DVSS
AVSS
< + B input (12 V to 16 V) conditions>
• Do not connect +B potential directly to a microcontroller pin.
• Always connect a resistor between the microcontroller pin and +B signal to limit the current.
lIHH = 2 mA per pin (Max) [In the steady state and transient state between power-on and power-off, etc.]
It can be connected to any general-purpose input port except the output pin for LCDC.
• The protection diode in the microcontroller turns the potential upon +B input between the limiting resistor and
microcontroller pin into “VCC + protection diode ON voltage”. Configure the circuit so that these are not
interfered and the potential is not exceeded.
60
DS07-16806-5E
MB91220 Series
3. DC Specifications
(TA : − 40 °C to + 105 °C ;Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V)
Parameter
“H” level
input
voltage
“L” level
input
voltage
Symbol
Pin name
Condition
VIHS
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, P70 to P73,
P80 to P87, P90 to P97,
PA0 to PA3, PB0 to PB7,
PC0 to PC3, PD0 to PD7,
PE0 to PE7, PF0 to PF7,
PG0 to PG3
VIH
VIHT
Value
Unit
Remarks
Min
Typ
Max
⎯
0.8 VCC
⎯
VCC + 0.3
V
Automotive level
input pins*1
P40, P43, P50, P53
PE4 to PE7
⎯
0.7 VCC
⎯
VCC + 0.3
V
CMOS input pins*2
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P57, P60 to P67,
PF0 to PF7
⎯
2.0
⎯
VCC + 0.3
V
TTL input pins*4
VIHM MD0 to MD2
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD pins*3
VIHX
X0, X1, X0A, X1A, INITX
⎯
0.8 VCC
⎯
⎯
V
VILS
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, P70 to P73,
P80 to P87, P90 to P97,
PA0 to PA3, PB0 to PB7,
PC0 to PC3, PD0 to PD7,
PE0 to PE7, PF0 to PF7,
PG0 to PG3
⎯
VSS − 0.3
⎯
0.5 VCC
V
Automotive level
input pins*1
VIL
P40, P43, P50, P53,
PE4 to PE7
⎯
VSS − 0.3
⎯
0.3 VCC
V
CMOS hysteresis
input pins*2
VILT
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P57, P60 to P67,
PF0 to PF7
⎯
VSS − 0.3
⎯
0.8
V
TTL input pins*4
VILM
MD0 to MD2
⎯
VSS − 0.3
⎯
Vss + 0.3
V
MD pins*3
VILX
X0, X1, X0A, X1A, INITX
⎯
⎯
⎯
0.2 VCC
V
(Continued)
DS07-16806-5E
61
MB91220 Series
(TA : − 40 °C to + 105 °C; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V)
Parameter Symbol Pin name
Condition
ICC
Operating
frequency :
FCP = 32 MHz
in main RUN
mode
Power
supply
current*5
Unit
Remarks
Min
Typ
Max
⎯
85
105
mA Under normal operation
⎯
102
126
mA
⎯
135
155
mA In Flash-Write mode
⎯
162
186
mA
⎯
40
70
mA
ICCS
Operating
frequency :
FCP = 32 MHz
in main sleep
mode
⎯
48
84
mA MB91F224/S (target value)
⎯
200
450
μA
main oscillation/PLL stops*6
ICCL
Operating
frequency :
FCP = 32 kHz,
TA = +25 °C
in sub RUN
mode
⎯
240
540
μA
main oscillation/PLL stops*6
MB91F224/S (target value)
⎯
180
400
μA
main oscillation/PLL stops*6
ICCLS
Operating
frequency :
FCP = 32 kHz,
TA = +25 °C,
Vcc = 5 V
in sub sleep
mode
⎯
216
480
μA
main oscillation/PLL stops*6
MB91F224/S (target value)
TA = +25 °C,
Vcc = 5 V
in stop mode
(oscillation
stopped)
⎯
10
150
μA
main clock/PLL/sub-oscillation halted*7
⎯
12
180
μA
main clock/PLL/sub-oscillation halted*7
MB91F224/S (target value)
TA = +25 °C,
Vcc = 5 V
in stop mode
(RTC in use*8)
⎯
330
500
μA
PLL/
sub-oscillation halted*7
⎯
396
600
μA
PLL/
sub-oscillation halted*7
MB91F224/S (target value)
⎯
40
180
μA
main oscillation/PLL stops*6
⎯
48
216
μA
main oscillation/PLL stops*6
MB91F224/S (target value)
−5
⎯
+5
μA
VCC
ICCH
ICTS4M
Sub clock
frequency =
32 kHz,
TA = +25 °C,
Vcc = 5 V
in stop mode
(Real Time Clock
Operation*8)
ICTS32K
Input leak
current
Value
IIL
All input
pins
VCC = DVCC =
AVCC = 5.5 V
VSS < VI < VCC
Under normal operation
MB91F224/S (target value)
In Flash-Write mode
MB91F224/S (target value)
(Continued)
62
DS07-16806-5E
MB91220 Series
(TA : − 40 °C to + 105 °C; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Condition
CIN1
Other than VCC,
VSS, DVCC, DVSS,
AVCC, AVSS,
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
Input
capacity 2
Pull-up
resistance
Value
Unit Remarks
Min
Typ
Max
⎯
⎯
5
15
pF
CIN2
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
⎯
⎯
15
45
pF
RUP
INITX
⎯
25
50
100
kΩ
VOH1
Other than
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
Vcc = 4.5 V
IOH = −4.0 mA
VCC − 0.5
⎯
⎯
V
VOH2
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
Vcc = 4.5 V
VCC − 0.5
IOH = −30.0 mA
⎯
⎯
V
VOL1
Other than
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
Vcc = 4.5 V
IOL = 4.0 mA
⎯
⎯
0.4
V
VOL2
PA0 to PA3,
PB4 to PB7,
PC0 to PC3,
PE0 to PE3
Vcc = 4.5 V
IOL = 30.0 mA
⎯
⎯
0.55
V
ΔVOH2
Vcc = 4.5 V
PWM1Pn,
IOH = 30.0 mA
PWM1Mn,
PWM2Pn,
Maximum
PWM2Mn, n = 0 to 3 deviation of VOH2
0
⎯
90
mV *9
High current output
Drive capacity
Phase-to-phase
deviation 2
ΔVOL2
Vcc = 4.5 V
PWM1Pn,
IOL = 30.0 mA
PWM1Mn,
PWM2Pn,
Maximum
PWM2Mn, n = 0 to 3 deviation of VOL2
0
⎯
90
mV *9
COM0 to COM3
Output impedance
RVCOM
COM0 to COM3
⎯
⎯
⎯
4.5
kΩ
SEG00 to SEG31
Output impedance
RVSEG
SEG0 to SEG31
⎯
⎯
⎯
30
kΩ
LCDC leak current
ILCDC
COM0 to COM3,
SEG0 to SEG31
TA = +25 °C
−0.5
⎯
+0.5
μA
Input
capacity 1
Output “H”
voltage 1
Output “H”
voltage 2
Output “L”
voltage 1
Output “L”
voltage 2
High current output
Drive capacity
Phase-to-phase
deviation 1
(Continued)
DS07-16806-5E
63
MB91220 Series
(Continued)
*1 : All input pins except X0, X1, X0A, X1A, MD0, MD1, MD2 and INITX pins
*2 : CMOS input can be switched by the SIN of the LIN-UART and I2C input pin and switched by the input level
selection register (PILR) .
*3 : MD0, MD1, MD2
*4 : TTL input can be selected by the external bus input pins and input pin only in the parallel writer mode. The
external bus input pins (P00 to P17 and P57) can be switched by the input level selection register (PILR) .
*5 : They represent current values used when supplying power to the external clock from pin X1.
*6 : Before switching from the main clock operation mode to the sub clock operation (operation in sub RUN, sub
SLEEP, and sub RTC) mode, set the main oscillation stop bit (OSCDS1) in the oscillation control register
(OSCCR) to "1" and the clock source to half of the source oscillation input, and then stop the PLL.
*7 : Before switching from the main clock operation mode to the stop mode, set the clock source to half of the
source oscillation input , stop the PLL, set the OSDC1 bit in the standby control register (STCR) to "1".
However, if using the main clock RTC operation , set the clock source to half of the source oscillation input,
stop the PLL, and then set each clock of the CPU clock (CLKB) , peripheral clock (CLKP) , and external
interface clock (CLKT) to the division ratio of 8 or more using the base clock divide setting registers 0 and 1
(DIVR0 and 1) before switching to the stop mode.
*8 : The real time clock can be operated only in the 4 MHz main clock oscillation or 32 kHz sub clock oscillation.
*9 : Defined by the maximum deviation of VOH2/VOL2 of each pin, when PWM1P0, PWM1M0, PWM2P0 and
PWM2M0 in ch.0 are simultaneously turned on. Other channels are applied in the same condition.
64
DS07-16806-5E
MB91220 Series
4. Flash Memory Write/Erase Characteristics
Parameter
Condition
Value
Min
Typ
Max
Unit
Remarks
Sector erase time
TA = +25 °C,
Vcc = 5.0 V
⎯
1
15
s
Exclusive of internal write time
prior to erase
Chip erase time
TA = +25 °C,
Vcc = 5.0 V
⎯
5
⎯
s
Exclusive of internal write time
prior to erase
Halfword write time
TA = +25 °C,
Vcc = 5.0 V
⎯
16
3600
μs
Exclusive of overhead time at
system level
Chip write time
TA = +25 °C,
Vcc = 5.0 V
⎯
2.1
⎯
s
Exclusive of overhead time at
system level
10000
⎯
⎯
cycle
10
⎯
⎯
year
Erase/write cycle
Flash memory data
retain time
⎯
TA = +85 °C
(average)
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into average temperature at + 85 °C) .
DS07-16806-5E
65
MB91220 Series
5. AC Specifications
(1) Clock timing
(TA : − 40 °C to + 105 °C; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
name
FC
Value
Condition
Unit
Remarks
Min
Typ
Max
X0, X1
⎯
4
⎯
MHz
Fca
X0A, X1A
⎯
32.768
⎯
kHz
Source oscillation clock
cycle time
tCYL
X0, X1
⎯
250
⎯
ns
Input clock pulse width
PWH,
PWL
X0
100
⎯
⎯
ns
The duty ratio
normally ranges
from 40% to 60%.
Input clock
rise/fall time
tcr,
tcf
X0
⎯
⎯
5
ns
When external clock is
used
Frequency of internal
operating clock
FCP
⎯
⎯
⎯
32
MHz
Internal operating
clock cycle time
tCP
⎯
⎯
31.25
⎯
⎯
ns
CAN PLL cycle jitter
(When locked)
tPJ
⎯
⎯
− 10
⎯
+ 10
ns
FCP = 32 MHz
(4 MHz, PLL multiplied
by 8)
External bus operating
clock cycle time
tCPT
⎯
⎯
125
⎯
1000
ns
TA : 0 °C to + 70 °C
Frequency of source
oscillation clock
⎯
⎯
• X0/X1 Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
66
tcf
PWL
tcr
DS07-16806-5E
MB91220 Series
• CAN PLL cycle jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
PLL output
t1
t2
tn-1
t3
tn
Ideal clock
Slow
Deviation
time
t3
t2
t1
tn-1
tn
Fast
• Operations
Oscillation should be performed as described below :
[Source oscillation] : X0/X1 : 4 MHz, PLL : multiplied by 8, Internal frequency : 32 MHz
: X0A/X1A : 32 kHz, PLL : no multiplication, Internal frequency : 32 kHz
Note that the PLL oscillation stabilization wait time should be set to 500 μs or more.
Sample oscillation circuit
X0
X1
R
C1
DS07-16806-5E
C2
67
MB91220 Series
AC specifications are defined by the following measurement standard voltage values :
• Input signal wave form
Automotive input pin
• Output signal wave form
Output pin
0.8 VCC
2.4 V
0.5 VCC
0.8 V
CMOS input pin
Output pin
0.7 VCC
0.3 VCC
C:50 pF
TTL input pin
2.0 V
0.8 V
68
DS07-16806-5E
MB91220 Series
(2) Reset input
(TA : − 40 °C to + 105 °C; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V)
Symbol
Parameter
INITX input time
Pin name
tINTL
Value
Condition
⎯
INITX
Unit
Remarks
Min
Max
500
⎯
ns
Under normal
operation
Oscillation time of
oscillator* +
10 tcp + 12 μs
⎯
ms
In stop mode
* : The oscillation time of the oscillator refers to the time when the amplitude has reached 90%. The oscillation time
of the crystal oscillator ranges from several ms to tens of ms. The oscillation time of the ceramic oscillator ranges
from several hundreds to several ms, while that of the external clock is 0 ms.
tINTL
INITX
0.2 VCC
0.2 VCC
• In stop mode
tINTL
INITX
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal
operation clock
10 tcp + 12 μs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Instruction executed
Internal reset
DS07-16806-5E
69
MB91220 Series
[External reset input specifications (INITX) and internal reset signal cancellation timing]
• When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the
internal reset signal to transmit all reset signals to the internal logic (Max 8 μs at 32 MHz) .
• The following chart shows how to set the timing for instruction execution start (start of application operation)
after external reset input.
Time from external reset input to instruction start = Max 256 tcp + 61 tcp
• Timing Chart
INITX
Min
Internal reset input timing
10 tcp
Internal reset
61 tcp
Max 256 tcp
Internal reset cancellation timing
[Pin state in external bus mode]
In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INITX = “0”) input.
Beside that, the value of the internal bus is to be output to each pin during the time between the internal reset
input and its cancellation.
• Timing Chart (Pin State for External Bus Mode : 1)
INITX
Min
10 tcp
Internal reset
61 tcp
Max 256 tcp
Pin state of
external bus
70
Hi-Z
Value immediately
before reset
Initial value at reset
DS07-16806-5E
MB91220 Series
It can be avoided by the following external reset input to continue Hi-Z.
• Timing Chart (Pin State for External Bus Mode : 2)
INITX
256 tcp
Internal reset
61 tcp
Max 256 tcp
Pin state of
external bus
DS07-16806-5E
Hi-Z
Initial value at reset
71
MB91220 Series
(3) Power-on Conditions
(TA : − 40 °C to + 105 °C; VSS = 0.0 V)
Parameter
Symbol Pin name
Condition
Value
Min
Max
Unit
Power supply rising
time
tR
0.05
30
ms
Power supply start
voltage
VOFF
⎯
0.2
V
Power supply peak
voltage
VON
3.5
⎯
V
Power supply cut-off
time
tOFF
50
⎯
ms
Remarks
⎯
VCC
Waiting time until
power-on
tR
3.5 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Power supply drop time, power supply voltages and external reset input to retain RAM data in MB91220 Satisfy
the following reset input standard to retain the RAM data used in the single chip mode.
Vcc (V)
Voltage drop time
External reset input standard (INITX)
dropped 4.0 V → 3.5 V
Vcc
Min 256 tcp
Min 256 tcp
4V
4V
3.5 V
3.5 V
INITX
256 tcp
To retain RAM data, enter 256 tcp of INITX or more before dropping VCC to 3.5 V or lower.
72
DS07-16806-5E
MB91220 Series
(4) Clock Output Timing
(VCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Cycle time
tCYC
SYSCLK
SYSCLK↑→SYSCLK↓
tCHCL
SYSCLK
SYSCLK↓→SYSCLK↑
tCLCH
SYSCLK
Value
Condition
⎯
Min
Max
tCPT
⎯
Unit
Remarks
ns
*1
tCYC / 2 − 10 tCYC / 2 + 10
ns
*2
tCYC / 2 − 10 tCYC / 2 + 10
ns
*3
tCYC
tCHCL
tCLCH
VOH
SYSCLK
VOH
VOL
*1 : tCYC is the frequency of one clock cycle including the gear cycle.
*2 : The rating is under the conditions of “gear cycle × 1”.
When the gear cycle is set to 1/2, 1/4 or 1/8, use the formula below by entering 1/2, 1/4 or 1/8 in “n” respectively.
( 1 / 2 × 1 / n ) × tCYC − 10
*3 : The rating is under the conditions of “gear cycle × 1”.
DS07-16806-5E
73
MB91220 Series
(5) Normal Bus Access : Read/Write Operation
(VCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
Pin name
tCSLCH
CS0X to CS3X setup
tCSDLCH
CS0X to CS3X hold
SYSCLK
CS0X to CS3X
Condition
Value
Unit
Min
Max
AWRxL :
W02 = 0
3
⎯
ns
AWRxL :
W02 = 0
−10
⎯
ns
3
tCYC / 2 + 25
ns
tCHCSH
tASCH
SYSCLK
A00 to A15
3
⎯
ns
tASWL
WR0X, WR1X
A00 to A15
3
⎯
ns
tASRL
RDX
A00 to A15
3
⎯
ns
tCHAX
SYSCLK
A00 to A15
3
tCYC / 2 + 25
ns
tWHAX
WR0X, WR1X
A00 to A15
3
⎯
ns
tRHAX
RDX
A00 to A15
3
⎯
ns
Valid address →
valid data input time
tAVDV
A00 to A15
D00 to D15
⎯
3 / 2 × tCYC −
45
ns
WR0X, WR1X ↓ delay
time
tCHWL
⎯
8
ns
WR0X, WR1X ↑delay time
tCHWH
⎯
8
ns
WR0X, WR1X minimum
pulse width
tWLWH
WR0X, WR1X
tCYC − 5
⎯
ns
Write data hold time
tWHDX
WR0X, WR1X,
D00 to D15
3
⎯
ns
Address setup
Address hold
RDX ↓ delay time
tCHRL
RDX ↑delay time
tCHRH
RDX ↓ →
valid data input time
tRLDV
Data setup → RDX ↑ time
tDSRH
RDX ↑ →
data hold time
tRHDX
RDX minimum pulse width
tRLRH
ASX setup
tASLCH
ASX hold
tCHASH
SYSCLK
WR0, WR1
⎯
⎯
8
ns
⎯
8
ns
⎯
tCYC − 30
ns
60
⎯
ns
0
⎯
ns
RDX
tCYC − 5
⎯
ns
SYSCLK
ASX
3
⎯
ns
3
tCYC / 2 + 25
ns
SYSCLK
RDX
RDX
D00 to D15
Remarks
*1, *2
*1
*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles)
to the rated value.
*2 : The rating is under the conditions of “gear cycle × 1”. When the gear cycle is set to 1/2 to 1/16, use the formula
below by entering 1/2 to 1/16 in “n” respectively.
Formula : 3/ (2n) × tCYC − 45
74
DS07-16806-5E
MB91220 Series
tCYC
VOH
VOH
VOH
VOH
SYSCLK
tASLCH
ASX
tCHASH
VOH
VOL
tCSLCH
tCSDLCH
CS0X to CS3X
tCHCSH
VOH
VOL
tASCH
A00 to A15
tCHAX
VOH
VOL
VOH
VOL
tCHRL
tCHRH
tRLRH
RDX
VOL
tRHAX
tASRL
tRLDV
tDSRH
tRHDX
tAVDV
D00 to D15
VOH
VOH
VOL
VOL
tCHWH
tCHWL
tWLWH
VOL
WR0X, WR1X
tASWL
VOH
tWHAX
tWHDX
D00 to D15
DS07-16806-5E
VOH
VOL
VOH
VOL
75
MB91220 Series
(6) Ready Input Timing
(VCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
Pin name
RDY setup time
→SYSCLK↓
tRDYS
SYSCLK
RDY
SYSCLK↑→
RDY hold time
tRDYH
SYSCLK
RDY
Value
Condition
Unit
Min
Max
52
⎯
ns
0
⎯
ns
⎯
tCYC
VoH
SYSCLK
VoL
tRDYS
With RDY
wait
Without RDY
wait
76
VoH
VoL
tRDYH
tRDYS
VoH
tRDYH
VoH
VoL
VoL
VoH
VoH
VoL
VoL
DS07-16806-5E
MB91220 Series
(7) UART Timing
(TA : − 40 °C to + 105 °C; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
tSCYC
SCK↓→
SOT delay time
tSLOV
Valid SIN→
SCK↑
tIVSH
SCK↑→
Valid SIN hold time
tSHIX
Serial clock
“H” pulse width
tSHSL
Serial clock
“L” pulse width
tSLSH
Serial clock
Cycle time
SCK↓→
SOT delay time
tSLOV
Valid SIN→
SCK↑
tIVSH
SCK↑→
Valid SIN hold time
tSHIX
Condition
Value
Unit
Min
Max
SCK0,
SCK3 to SCK5
8 tCP
⎯
ns
SCK0,
SCK3 to SCK5,
SOT0,
SOT3 to SOT5
− 80
+ 80
ns
100
⎯
ns
60
⎯
ns
4 tCP
⎯
ns
4 tCP
⎯
ns
⎯
150
ns
60
⎯
ns
60
⎯
ns
⎯
SCK0,
SCK3 to SCK5,
SIN0,
SIN3 to SIN5
SCK0,
SCK3 to SCK5
SCK0,
SCK3 to SCK5,
SOT0,
SOT3 to SOT5
SCK0,
SCK3 to SCK5,
SIN0,
SIN3 to SIN5
⎯
Remarks
In internal shift clock
mode, output pin;
CL = 80 pF+1 TTL
In internal shift clock
mode, output pin;
CL = 80 pF+1 TTL
Notes : • The above ratings are the values for clock synchronous mode.
• CL is a load capacitance connected to pins during testing.
DS07-16806-5E
77
MB91220 Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 Vcc
0.8 Vcc
0.5 Vcc
0.5 Vcc
• External Shift clock Mode
tSLSH
tSHSL
0.8 Vcc
SCK
0.5 Vcc
0.8 Vcc
0.5 Vcc
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
78
tSHIX
0.8 Vcc
0.8 Vcc
0.5 Vcc
0.5 Vcc
DS07-16806-5E
MB91220 Series
(8) Timer Input Timing
(TA : − 40 °C to + 105 °C; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Condition
tTIWH,
tTIWL
TIN0 to TIN2, PWC0
IN0 to IN3
⎯
Input pulse width
Value
Min
Max
4 tCP
⎯
Unit
ns
• Timer Input Timing
tTIWL
tTIWH
TIN0 to TIN2
IN0 to IN3
PWC0
0.8 Vcc
0.8 Vcc
0.5 Vcc
0.5 Vcc
(9) Trigger input Timing
(TA : − 40 °C to + 105 °C; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin name
Condition
Input pulse width
tTRGH,
tTRGL
INT0 to INT7,
ATGX, RX0, RX1
⎯
Value
Unit
Min
Max
5 tCP
⎯
ns
1
⎯
μs
Remarks
At STOP mode
• Timer input timing
tTRGH
INT0 to INT7
ATGX
0.8 Vcc
tTRGL
0.8 Vcc
0.5 Vcc
0.5 Vcc
RX0,RX1
DS07-16806-5E
79
MB91220 Series
6. A/D Converter Electrical Characteristics
(1) Electrical Characteristics
(TA : − 40 °C to + 105 °C; VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Symbol
Pin name
Resolution
⎯
Total error
Parameter
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Non-linearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential linearity
error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero transition voltage
VOT
AN0 to AN23
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
600
⎯
⎯
ns
AVCC ≥ 4.5 V*1
1200
⎯
⎯
ns
4.0 V ≤ AVCC < 4.5 V*2
990
⎯
⎯
ns
AVCC ≥ 4.5 V*1
1980
⎯
⎯
ns
4.0 V ≤ AVCC < 4.5 V*2
1 LSB =
(AVRH − AVSS) / 1024
Full-scale transition
voltage
VFST
AN0 to AN23
Sampling time
tSMP
⎯
Compare time
tCMP
⎯
A/D conversion time
tCNV
⎯
3
⎯
⎯
μs
tSMP + tCMP
Analog port input
current
IAIN
AN0 to AN23
⎯
⎯
10
μA
AVCC ≤ VAIN ≤ AVSS
Analog input voltage
VAIN
AN0 to AN23
0
⎯
AVRH
V
AVR +
AVRH
4.0
⎯
AVcc
V
⎯
2.4
4.7
mA
⎯
⎯
5
μA
*3
Standard voltage
Power supply
current
IA
IAH
AVCC
Standard voltage
supply current
IR
AVRH
⎯
500
900
μA
VAVRH = 5.0 V
IRH
AVRH
⎯
⎯
5
μA
*3
Variation between
channels
⎯
AN0 to AN23
⎯
⎯
5
LSB
*1 : Assume that the output impedance of the external analog signal is 2.74 kΩ or less. If the output impedance is
high, the sampling time is longer than the standard value (refer to note) . For actual use, set tCNV ≤ tSMP + tCMP.
*2 : Assume that the output impedance of the external analog signal is 0.7 kΩ or less. If the output impedance is
high, the sampling time is longer than the standard value (refer to note) . For actual use, set tCNV ≤ tSMP + tCMP.
*3 : This defines the power supply current when the A/D converter is not in operation and the CPU is stopped
(at VCC = AVCC = AVRH = 5.0 V) .
80
DS07-16806-5E
MB91220 Series
• External impedance and sampling time of analog inputs
The A/D converter is fitted with a sample and hold circuit. If the external impedance is so high that there is not
sufficient time for sampling, the internal sample and hold capacitor will not fully charge to the analog voltage,
and the precision of the A/D conversion will be adversely affected. Therefore, in order to satisfy the A/D conversion
precision specifications, either adjust the register values and operating frequency or reduce the external impedance so that the sampling time is greater than the minimum value as given by the relationship between external
impedance and minimum sampling time. If you are still unable to hold enough sampling time, connect a capacitor
of about 0.1 μF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
Note : The values are reference values.
DS07-16806-5E
R
C
3.95 kΩ (Max) 17 pF (Max)
81
MB91220 Series
• The relationship between the external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
[External impedance = 0 kΩ to 20 kΩ]
100
20
90
18
External impedance (kΩ)
External impedance (kΩ)
[External impedance = 0 kΩ to 100 kΩ]
80
70
60
50
40
30
20
10
0
0
5
10
16
14
12
10
8
6
4
2
0
0
15
Minimum sampling time (μs)
1
2
3
Minimum sampling time (μs)
• At 4.0 V ≤ AVCC < 4.5 V
[External impedance = 0 kΩ to 20 kΩ]
100
20
90
18
External impedance (kΩ)
External impedance (kΩ)
[External impedance = 0 kΩ to 100 kΩ]
80
70
60
50
40
30
20
10
0
0
5
10
Minimum sampling time (μs)
15
16
14
12
10
8
6
4
2
0
0
1
2
3
4
Minimum sampling time (μs)
• Measure against noise for reference power supply (AVRH pin)
It is recommended that a bypass capacitor of several μF be input to the reference power supply (AVRH) .
• About errors
|AVRH − AVSS| becomes smaller, values of relative errors grow larger.
• Others
When placing a DC blocking capacitor between the external circuit and input pin,set the capacitance value by
multiplying CSH and several thousands as a guideline in order to minimize the impact from dividing voltage
capacitance with CSH.
82
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• Analog Input Equivalent Circuit
Circuit in microcontroller
rs
Input pin
AN0
RSH
CSH
Comparator
Input pin
AN7
Vs
External circuit
S/H circuit
Analog channel selector
<Recommended parameter values for each element>
rS = 5 kΩ or less
RSH = approx. 2.5 kΩ
CSH = approx. 10 pF
Note : These element parameters should be regarded as tentative values used only for
design purposes. They do not guarantee the operation.
DS07-16806-5E
83
MB91220 Series
(2) Term Definitions
• Resolution
Level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, the analog voltage can be resolved into 210 = 1024.
• Total error
Difference between actual and theoretical values, which is a total value derived from an offset error, gain error,
non-linearity error and noise.
• Linearity error
Deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000”←→“00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1110”←→“11 1111 1111”) compared with the actual conversion values obtained.
• Differential linearity error
Deviation of input voltage, which is required for changing output code by1 LSB, from an ideal value.
Total error
3FFH
3FEH
0.5 LSB
Actual conversion
characteristics
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVSS
[V]
1024
Total error of digital output “N” =
1 LSB (Ideal value) =
[LSB]
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
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(Continued)
Linearity error
Differential linearity error
Ideal
characteristics
3FFH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FDH
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
Actual conversion
characteristics
003H
Digital output
3FEH
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002H
Ideal characteristics
Actual conversion
characteristics
N−2
001H
VOT (actual measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
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MB91220 Series
7. Electrical Characteristics for the D/A Converter
Parameter
Symbol
(TA : − 40 °C to + 105 °C; VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)
Value
Pin
Unit
Remarks
Min
Typ
Max
Resolution
⎯
⎯
⎯
⎯
8
bit
Differential linearity error
⎯
⎯
⎯
⎯
±3
LSB
⎯
⎯
⎯
0.45
⎯
μs
At load
capacitance 20 pF
⎯
⎯
⎯
2.00
⎯
μs
At load
capacitance 100 pF
Conversion time
Reference power supply
current
IDVR
AVCC
⎯
162
920
μA
TA = + 25 °C
IDVRS
AVCC
⎯
⎯
0.1
μA
At power down
Analog output impedance
⎯
⎯
2.0
3.0
3.9
kΩ
86
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■ ORDERING INFORMATION
Part number
Package
Remarks
MB91V220CR-ES
401-pin ceramic PGA
(PGA-401C-A02)
Evaluation product
MB91F223PFV-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
Sub clock support
MB91F223SPFV-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
Sub clock not yet support
MB91F224PFV-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
Sub clock support
MB91F224SPFV-GSE1
144-pin plastic LQFP
(FPT-144P-M08)
Sub clock not yet support
DS07-16806-5E
87
MB91220 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7
C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest Package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
88
DS07-16806-5E
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■ MAIN CHANGES IN THIS EDITION
Page
Section
■ PIN ASSIGNMENT
5
Change Results
Added the following footnote for pin number 140 and 141.
“*: For PD4 and PD5, the same pin function should be
selected at PFRD/EPFRD registers.
When PD4 is used as the port function, PD5 should also be
used as the port function.
When PD4 is used as the PPG function, PD5 should also be
used as the PPG function.
When PD4 is used as the COM function, PD5 should also be
used as the COM function.”
The vertical lines marked in the left side of the page show the changes.
DS07-16806-5E
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MB91220 Series
MEMO
90
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MEMO
DS07-16806-5E
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MB91220 Series
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Specifications are subject to change without notice. For further information please contact each office.
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