3.0 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16916-2E
32-bit Microcontrollers
CMOS
FR80 MB91665 Series
MB91F669/F668/V650
■ DESCRIPTION
The MB91665 series is a line of Fujitsu microcontrollers based on a 32-bit RISC CPU core that feature a variety
of peripheral functions for embedded applications that demand high-performance and high-speed CPU processing.
This series is based on the FR80* family CPU and is implemented as a single chip.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor Limited.
■ FEATURES
 FR80 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• General-purpose registers : 32-bit  16
• 16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle
• Instructions suitable for embedded applications
- Memory-to-memory transfer, bit processing, barrel shift instructions, etc.
- Instruction support for high level languages
Function entry and exit instructions, instructions for register multi-load and multi-store
- Bit search instruction
“1” detection, “0” detection, transition point detection
- Branch instructions with delay slots
Reduced overhead when processing branches
- Register interlock functions
Facilitate coding in assembly language
- Built-in multiplier/instruction-level support
- Signed 32-bit multiplication
: 5 cycles
- Signed 16-bit multiplication
: 3 cycles
- Interrupts (save PC and PS) : 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access to be executed simultaneously
- The prefetch function for instructions using the 4-word instruction queue in the CPU
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
MB91665 Series
• Instruction compatible with FR family CPU
- Additional bit search instructions
- No resource instructions and coprocessor instructions
• Maximum operating frequency
 CPU : 33 MHz
 Resources : 33 MHz
 External bus : 33 MHz
• External bus interface
 Operating frequency : Max 33 MHz
 MB91F669 (64 pins)
24 addresses, 8/16-bit data I/O (multiplex bus)
8 addresses, 8/16-bit data I/O (split bus)
 MB91F668 (48 pins)*
16 addresses, 8-bit data I/O (multiplex bus)
No address, 8-bit data I/O (split bus)
* There are no RDY, SYSCLK, WR1, CS1, CS2, and CS3
 24 address lines, 8- or 16-bit data I/O (separate busses or multiplexed bus)
 Programmable automatic wait cycle insertion for each area
• DMA controller (DMAC)
 4 channels
 Address space : 32 bits (4 Gbytes)
 Transfer modes : Block transfer/burst transfer/demand transfer
 Address update : Increment/decrement/fixed (increment/decrement step size of 1, 2, or 4)
 Transfer data length : Selectable from 8-bit, 16-bit, 32-bit
 Block size : 1 to 16
 Number of transfers : 1 to 65535
 Transfer requests
- Requests from software
- Interrupt requests from peripheral resources (interrupt requests are shared, including external interrupts)
 Reload functions : Reload can be specified on all channels
 Priority order : Fixed (ch.0  ch.1  ch.2  ch.3  ...) or round-robin
 Interrupt requests : Interrupts can be generated for transfer complete, transfer error, and transfer interrupted.
• Multifunction serial interface
 Operation mode is selectable from UART/CSIO/I2C for each channel
 UART
- Full-duplex double buffer
- Selectable parity on/off
- Built-in dedicated baud rate generator
- External clock can be used as a serial clock
- Error detection function for parity, frame and overrun errors
 CSIO
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function
 I2C
- Supports both standard mode (Max 100 kbps) and Fast mode (Max 400 kbps)
- Some channels are 5 V tolerant
(Continued)
2
DS07-16916-2E
MB91665 Series
• Interrupts
 Total of 16 external interrupts (some pins are 5 V tolerant)
 Interrupts from peripheral resources
 Programmable interrupt levels (16 levels)
 Can be used to return from stop mode, sleep mode
• A/D converter
 MB91F669 (64 pins): 12 channels, 1 unit
 MB91F668 (48 pins): 10 channels, 1 unit
 10-bit resolution
 Conversion time : approx. 1.2 s (PCLK  33 MHz)
 Priority conversion (2 levels)
 Conversion modes : Single-shot conversion mode, scan conversion mode
 Activation sources : Software, external trigger, base timer
 Built-in FIFO for storing conversion data (for scan conversion:16, for priority conversion:4)
• Base timer
 4 channels
 Operation mode is selectable from the followings for each channel
- 16/32-bit reload timer
- 16-bit PWM timer
- 16/32-bit PWC timer
- 16-bit PPG timer
 Cascading connection between 2 channels allows them to be used as one 32-bit timer
 Multiple channels can be started simultaneously
 Input/output select function
• 16-bit reload timer
 3 channels (including 1 channel for REALOS)
 Interval timer function
 Count clock select function (peripheral clock (PCLK) divided by 2 to 64)
• Compare timer
 32-bit input capture : 8 channels
 32-bit output compare : 8 channels
 32-bit free-run timer : 2 channels
• Other interval timers
 Up/down counter : 1 channel
 Watch counter : 1 channel
 Watchdog timer : 1 channel
(Continued)
DS07-16916-2E
3
MB91665 Series
(Continued)
• USB function / HOST
 1 channel
 USB2.0 Full-Speed supported
 The USB function and USB HOST are the switch types (USB I/O multiplexed)
 Support of DMA transfer
[USB Function]
 Support of up to four endpoints
- Endpoint 0 is provided for the fixed use of control transfers
- Bulk or interrupt transfer can be selected for endpoint 1 to 3
 Double buffer structure for endpoint 1 to 3
[USB HOST]
 Support control transfer, bulk transfer, interrupt transfer, and isochronous transfer
 Automatic detection of connection/disconnection of USB devices
 Automatic processing of a handshake packet for IN/OUT token processing
 Support of a maximum packet length of up to 256 bytes
 Support for a wakeup function
• Main timer
 1 channel
 Counts the oscillation stabilization wait time of the main clock (MCLK)
 Counts the oscillation stabilization wait time of the PLL clock (PLLCLK)
 Can be used as an interval timer while the main clock (MCLK) oscillations is stable
• Sub timer
 1 channel
 Counts the oscillation stabilization wait time of the sub clock (SBCLK)
 Can be used as an interval timer while the sub clock (SBCLK) oscillations is stable
• Clock generation
 Main clock (MCLK) oscillator
 Sub clock (SBCLK) oscillator
 PLL clock (PLLCLK) oscillator
• Low-power dissipation mode
 Stop mode
 Watch mode
 Sleep mode
 Doze mode
 Clock division function
• Other features
 I/O port
 INIT pin is provided as a reset pin
 Watchdog timer reset, software reset
 Delay interrupt
 Power supply
Single power supply (When USB not used: 2.7 V to 3.6 V, When USB used: 3.0 V to 3.6 V)
4
DS07-16916-2E
MB91665 Series
■ PRODUCT LINEUP
Part number
MB91F669
MB91F668
Parameter
Product type
Flash memory product
Built-in program memory
capacity
128 Kbytes (Flash)
Built-in RAM capacity
External bus
interface
16 Kbytes
multi
Address: 24 bits Data: 16/8 bits
Address: 16 bits Data: 8 bits
split
Address: 8 bits Data: 16/8 bits
No address Data: 8 bits
DMA controller (DMAC)
Base timer
4 channels
4 channels (Reload timer/ PWM/ PPG/ PWC modes can be switched)
Multifunction serial interface
4 channels (UART/ SPI/ I2C modes can be switched)
External interrupt
10-bit A/D converter
16
12 channels (1 unit)
16-bit reload timer
10 channels (1 unit)
3 channels
32-bit input capture: 8 channels
32-bit output compare: 8 channels
32-bit free-run timer: 2 channels
Compare timer
Up/Down counter
1 channel
Watch counter
1 channel
I/O port
50
USB function/HOST
34
1 channel (function/ host modes can be switched)
Main timer
1 channel
Sub timer
1 channel
Wild register
16 channels

Debug function
■ PACKAGES
Product name
MB91F669
MB91F668
Package

FPT-64P-M24
FPT-48P-M26

: Supported
Note: Refer to “■ PACKAGE DIMENSIONS” for detailed information on each package.
DS07-16916-2E
5
MB91665 Series
■ PIN ASSIGNMENT
 LQFP-64 (MB91F669)
P10/D08/SOUT2/INT0 (5V tolerance,OD)
P61/SYSCLK/TIOB1_1/SIN2_1
P60/RDY/TIOA1_1/SOUT2_1
P83/AN11/IN3_1
P82/AN10/IN2_1
P81/AN9/IN1_1/TMI1_1
P80/AN8/IN0_1/TMI0_1
P77/AN7/SCK0/TMI2/OUT7_1/INT23
P76/AN6/SIN0/TMI1/OUT6_1/INT22
P75/AN5/SOUT0/TMI0/OUT5_1/INT21
P74/AN4/TMO2/OUT4_1/INT20
P73/AN3/TMO1/OUT3_1/INT19
P72/AN2/TMO0/OUT2_1/INT18
P71/AN1/OUT1_1/INT17
P70/AN0/OUT0_1/INT16
AVcc
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
P11/D09/SIN2/INT1 (5V tolerance)
1
48
AVss
P12/D10/SCK2/INT2 (5V tolerance,OD)
2
47
P57/WR1/TIOB3_1/TMI2_1
P13/D11/INT3
3
46
P56/WR0/ZIN1_1/FRCK0/SCK6
P14/D12/AIN1/INT4/OUT4
4
45
P55/RD/BIN1_1/ADTRG0/SIN6
P15/D13/BIN1/INT5/OUT5
5
44
P54/AS/AIN1_1/SOUT6
P16/D14/ZIN1/INT6/OUT6
6
43
P53/CS3/FRCK1/TIOA3_1/SCK1_1
P17/D15/INT7/OUT7
7
42
P52/CS2/TIOB2_1/SIN1_1
PH3/INT3_1 (5V tolerance)
8
41
P51/CS1/TIOA2_1/SOUT1_1
Vcc
9
40
P50/CS0/TMO0_1
UDM
10
39
P07/D07/TIOB3/IN7
UDP
11
38
P06/D06/TIOA3/SCK1/IN6 (5V tolerance,OD)
Vss
12
37
P05/D05/TIOB2/SIN1/IN5 (5V tolerance)
P20/A00/TMO1_1/A16 (5V tolerance,OD)
13
36
P04/D04/TIOA2/SOUT1/IN4 (5V tolerance,OD)
P21/A01/TMO2_1/A17 (5V tolerance,OD)
14
35
P03/D03/TIOB1/IN3
P22/A02/TIOA0_1/A18 (5V tolerance,OD)
15
34
P02/D02/TIOA1/SCK0_1/IN2 (5V tolerance,OD)
P23/A03/TIOB0_1/A19 (5V tolerance)
16
33
Vcc
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P24/A04/OUT0/A20 (5V tolerance,OD)
P25/A05/OUT1/A21 (5V tolerance,OD)
P26/A06/OUT2/A22 (5V tolerance,OD)
P27/A07/OUT3/A23 (5V tolerance,OD)
PH2/SCK2_1/INT2_1 (5V tolerance)
P00/D00/TIOA0/SOUT0_1/IN0 (5V tolerance,OD)
P01/D01/TIOB0/SIN0_1/IN1
INIT
X0A/PK1
X1A/PK0
C
MD1
MD0
X0
X1
Vss
LQFP-64
* : Explanation of ( )
5 V tolerance: 5 V tolerant pin
OD: Open drain control pin
(FPT-64P-M24)
Note : The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the port number.
For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
6
DS07-16916-2E
MB91665 Series
 LQFP-48 (MB91F668)
P10/D08/SOUT2/INT0 (5V tolerance,OD)
P81/AN9/IN1_1/TMI1_1
P80/AN8/IN0_1/TMI0_1
P77/AN7/SCK0/TMI2/OUT7_1/INT23
P76/AN6/SIN0/TMI1/OUT6_1/INT22
P75/AN5/SOUT0/TMI0/OUT5_1/INT21
P74/AN4/TMO2/OUT4_1/INT20
P73/AN3/TMO1/OUT3_1/INT19
P72/AN2/TMO0/OUT2_1/INT18
P71/AN1/OUT1_1/INT17
P70/AN0/OUT0_1/INT16
AVcc
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
P11/D09/SIN2/INT1 (5V tolerance)
1
36
AVss
P12/D10/SCK2/INT2 (5V tolerance,OD)
2
35
P56/WR0/ZIN1_1/FRCK0/SCK6
P13/D11/INT3
3
34
P55/RD/BIN1_1/ADTRG0/SIN6
P14/D12/AIN1/INT4/OUT4
4
33
P54/AS/AIN1_1/SOUT6
P15/D13/BIN1/INT5/OUT5
5
32
P50/CS0/TMO0_1
P16/D14/ZIN1/INT6/OUT6
6
31
P07/D07/TIOB3/IN7
P17/D15/INT7/OUT7
7
30
P06/D06/TIOA3/SCK1/IN6 (5V tolerance,OD)
PH3/INT3_1 (5V tolerance)
8
29
P05/D05/TIOB2/SIN1/IN5 (5V tolerance)
Vcc
9
28
P04/D04/TIOA2/SOUT1/IN4 (5V tolerance,OD)
UDM
10
27
P03/D03/TIOB1/IN3
UDP
11
26
P02/D02/TIOA1/SCK0_1/IN2 (5V tolerance,OD)
Vss
12
25
Vcc
13
14
15
16
17
18
19
20
21
22
23
24
PH2/SCK2_1/INT2_1 (5V tolerance)
P00/D00/TIOA0/SOUT0_1/IN0 (5V tolerance,OD)
P01/D01/TIOB0/SIN0_1/IN1
INIT
X0A/PK1
X1A/PK0
C
MD1
MD0
X0
X1
Vss
LQFP-48
* : Explanation of ( )
5 V tolerance: 5 V tolerant pin
OD: Open drain control pin
(FPT-48P-M26)
Note : The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the port number.
For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
DS07-16916-2E
7
MB91665 Series
■ PIN DESCRIPTION
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the port number.
For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port
function register (EPFR) to select the pin
Pin Number
CMOS
I/O
CMOS
level
Circuit
Pin Name
Function
level
hysteresis
64 pin 48 pin
input
Type*1
input
P11
1
2
3
4
5
6
1
2
3
4
5
6
D09
General-purpose I/O port
Q*2


External bus interface data bus bit9
Multifunction serial interface ch.2 input pin

INT1
External interrupt request 1 input pin

P12
General-purpose I/O port

D10
External bus interface data bus bit10
SIN2

Multifunction serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL2 when it is used in an I2C (operation mode
4).

INT2
External interrupt request 2 input pin

P13
General-purpose I/O port

SCK2
(SCL2)
D11
*2
Q
B

External bus interface data bus bit11
INT3
External interrupt request 3 input pin

P14
General-purpose I/O port

D12
External bus interface data bus bit12

Up/Down counter ch.1 AIN input pin

INT4
External interrupt request 4 input pin

OUT4
32-bit output compare ch.4 output pin

P15
General-purpose I/O port

D13
External bus interface data bus bit13
AIN1
B

Up/Down counter ch.1 BIN input pin

INT5
External interrupt request 5 input pin

OUT5
32-bit output compare ch.5 output pin

P16
General-purpose I/O port

D14
External bus interface data bus bit14
BIN1
B

Up/Down counter ch.1 ZIN input pin

INT6
External interrupt request 6 input pin

OUT6
32-bit output compare ch.6 output pin

ZIN1
B

(Continued)
8
DS07-16916-2E
MB91665 Series
Pin Number
64 pin 48 pin
Pin Name
I/O
Circuit
Type*1
P17
7
7
D15
INT7
General-purpose I/O port
B
OUT7
PH3
Function
D*2
CMOS
CMOS
level
level
hysteresis
input
input


External bus interface data bus bit15
External interrupt request 7 input pin

32-bit output compare ch.7 output pin

General-purpose I/O port

External interrupt request 3 input pin (Port 1)

Power pin


8
8
9
9
VCC
10
10
UDM
USB
D pin of USB function/HOST


11
11
UDP
USB
D pin of USB function/HOST


12
12
VSS
GND pin


General-purpose I/O port

External bus interface address bus bit0

16-bit reload timer ch.1 output pin (Port 1)

A16
External bus interface address bus bit16

P21
General-purpose I/O port

External bus interface address bus bit1

16-bit reload timer ch.2 output pin (Port 1)

A17
External bus interface address bus bit17

P22
General-purpose I/O port

External bus interface address bus bit2

Base timer ch.0 TIOA pin (Port 1)

A18
External bus interface address bus bit18

P23
General-purpose I/O port

External bus interface address bus bit3

Base timer ch.0 TIOB pin (Port 1)

INT3_1


P20
13
14
15
16
17





A00
TMO1_1
A01
TMO2_1
A02
TIOA0_1
A03
TIOB0_1
Q*2
Q*2
Q*2
Q*2








A19
External bus interface address bus bit19
P24
General-purpose I/O port

External bus interface address bus bit4


32-bit output compare ch.0 output pin


External bus interface address bus bit20


A04
OUT0
A20
Q*2
(Continued)
DS07-16916-2E
9
MB91665 Series
Pin Number
64 pin 48 pin
Pin Name
I/O
Circuit
Type*1
General-purpose I/O port

External bus interface address bus bit5


32-bit output compare ch.1 output pin


A21
External bus interface address bus bit21


P26
General-purpose I/O port

External bus interface address bus bit6


32-bit output compare ch.2 output pin


A22
External bus interface address bus bit22


P27
General-purpose I/O port

External bus interface address bus bit7


32-bit output compare ch.3 output pin


A23
External bus interface address bus bit23


PH2
General-purpose I/O port

SCK2_1
(SCL2_1)
Multifunction serial interface ch.2 clock I/O pin
(Port 1).
This pin operates as SCK2_1 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SCL2_1 when it is used in an I2C (operation
mode 4).

INT2_1
External interrupt request 2 input pin (Port 1)

P00
General-purpose I/O port

D00
External bus interface data bus bit0
TIOA0
Base timer ch.0 TIOA pin


SOUT0_1
(SDA0_1)
Multifunction serial interface ch.0 output pin
(Port 1).
This pin operates as SOUT0_1 when it is used
in a UART/CSIO (operation modes 0 to 2) and
as SDA0_1 when it is used in an I2C (operation
mode 4).


IN0
32-bit input capture ch.0 input pin

P01
General-purpose I/O port

D01
External bus interface data bus bit1
P25
18
19
20
21
22
23



13
A05
OUT1
A06
OUT2
A07
OUT3
Q*2
Q*2
Q*2
D*2
Q*2
14
15
Function
CMOS
CMOS
level
level
hysteresis
input
input


Base timer ch.0 TIOB pin

SIN0_1
Multifunction serial interface ch.0 input pin
(Port 1)

IN1
32-bit input capture ch.1 input pin

TIOB0
B
(Continued)
10
DS07-16916-2E
MB91665 Series
Pin Number
Pin Name
64 pin 48 pin
24
16
25
17
26
18
27
19
28
20
INIT
PK1
X0A
PK0
X1A
C
MD1
I/O
Circuit
Type*1
Function
CMOS
CMOS
level
level
hysteresis
input
input
External reset input pin. A reset is valid when
INIT  L.
The I/O circuit type for the flash memory
products is P.

General-purpose I/O port

Sub clock (oscillation) input pin

General-purpose I/O port

Sub clock (oscillation) I/O pin



Power stabilization capacity pin


P
Mode 1 pin. Input must always be at the “L”
level.
The I/O circuit type for the flash memory
products is P.


P
I
I
29
21
MD0
P
Mode 0 pin.
The I/O circuit type for the flash memory
products is P.
During normal operation, MD0  L must be
input. During serial programming to flash
memory, MD0  H must be input.
30
22
X0
A
Main clock (oscillation) input pin

31
23
X1
A
Main clock (oscillation) I/O pin


32
24
VSS

GND pin


33
25
VCC

Power pin


P02
General-purpose I/O port

D02
External bus interface data bus bit2
TIOA1
Base timer ch.1 TIOA pin

SCK0_1
(SCL0_1)
Multifunction serial interface ch.0 clock I/O pin
(Port 1).
This pin operates as SCK0_1 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SCL0_1 when it is used in an I2C (operation
mode 4).

IN2
32-bit input capture ch.2 input pin

P03
General-purpose I/O port

34
35
Q*2
26
27
D03
TIOB1
IN3
B


External bus interface data bus bit3
Base timer ch.1 TIOB pin

32-bit input capture ch.3 input pin

(Continued)
DS07-16916-2E
11
MB91665 Series
Pin Number
64 pin 48 pin
36
Pin Name
I/O
Circuit
Type*1
General-purpose I/O port
D04
External bus interface data bus bit4
TIOA2
Base timer ch.2 TIOA pin

SOUT1
(SDA1)
Multifunction serial interface ch.1 output pin.
This pin operates as SOUT1 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SDA1 when it is used in an I2C (operation mode
4).

IN4
32-bit input capture ch.4 input pin

P05
General-purpose I/O port

Q*2
28
38
39
40
29
32


SIN1
Multifunction serial interface ch.1 input pin

IN5
32-bit input capture ch.5 input pin

P06
General-purpose I/O port

D06
External bus interface data bus bit6
TIOA3
Base timer ch.3 TIOA pin

SCK1
(SCL1)
Multifunction serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL1 when it is used in an I2C (operation mode
4).

IN6
32-bit input capture ch.6 input pin

P07
General-purpose I/O port

Q
*2
Q*2
D07
B


External bus interface data bus bit5
Base timer ch.2 TIOB pin
TIOB2
30
31

P04
D05
37
Function
CMOS
CMOS
level
level
hysteresis
input
input


External bus interface data bus bit7
Base timer ch.3 TIOB pin

IN7
32-bit input capture ch.7 input pin

P50
General-purpose I/O port

External bus interface chip select 0 output pin


16-bit reload timer ch.0 output pin (Port 1)


TIOB3
CS0
TMO0_1
C
(Continued)
12
DS07-16916-2E
MB91665 Series
Pin Number
64 pin 48 pin
41
Pin Name
I/O
Circuit
Type*1
P51
General-purpose I/O port

CS1
External bus interface chip select 1 output pin


TIOA2_1
Base timer ch.2 TIOA pin (Port 1)


SOUT1_1
(SDA1_1)
Multifunction serial interface ch.1 output pin
(Port 1).
This pin operates as SOUT1_1 when it is used
in a UART/CSIO (operation modes 0 to 2) and
as SDA1_1 when it is used in an I2C (operation
mode 4).

P52
General-purpose I/O port

External bus interface chip select 2 output pin

Base timer ch.2 TIOB pin (Port 1)

SIN1_1
Multifunction serial interface ch.1 input pin
(Port 1)

P53
General-purpose I/O port

CS3
External bus interface chip select 3 output pin

FRCK1
32-bit free-run timer ch.1 external clock input pin

Base timer ch.3 TIOA pin (Port 1)

SCK1_1
(SCL1_1)
Multifunction serial interface ch.1 clock I/O pin
(Port 1).
This pin operates as SCK1_1 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SCL1_1 when it is used in an I2C (operation
mode 4).

P54
General-purpose I/O port

AS
External bus interface address strobe output pin

AIN1_1
Up/Down counter ch.1 AIN input pin (Port 1)

SOUT6
(SDA6)
Multifunction serial interface ch.6 output pin.
This pin operates as SOUT6 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SDA6 when it is used in an I2C (operation mode
4).

P55
General-purpose I/O port

RD
External bus interface read strobe output pin

Up/Down counter ch.1 BIN input pin (Port 1)

ADTRG0
10-bit A/D converter external trigger input pin

SIN6
Multifunction serial interface ch.6 input pin


C
CS2
42

TIOB2_1
C
TIOA3_1
43
44
45

C
33
34
Function
CMOS
CMOS
level
level
hysteresis
input
input
C
BIN1_1
C




(Continued)
DS07-16916-2E
13
MB91665 Series
Pin Number
64 pin 48 pin
46
47
35

Pin Name
I/O
Circuit
Type*1
Function
CMOS
CMOS
level
level
hysteresis
input
input
P56
General-purpose I/O port

WR0
External bus interface write strobe 0 output pin

ZIN1_1
Up/Down counter ch.1 ZIN input pin (Port 1)

32-bit free-run timer ch.0 external clock input pin

SCK6
(SCL6)
Multifunction serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C (operation mode
4).

P57
General-purpose I/O port

External bus interface write strobe 1 output pin

Base timer ch.3 TIOB pin (Port 1)

16-bit reload timer ch.2 input pin (Port 1)

FRCK0
WR1
TIOB3_1
C
C
TMI2_1


48
36
AVSS

10-bit A/D converter GND pin


49
37
AVCC

10-bit A/D converter analog power pin


General-purpose I/O port

10-bit A/D converter ch.0 analog input pin


32-bit output compare ch.0 output pin (Port 1)


INT16
External interrupt request 16 input pin

P71
General-purpose I/O port

10-bit A/D converter ch.1 analog input pin


32-bit output compare ch.1 output pin (Port 1)


INT17
External interrupt request 17 input pin

P72
General-purpose I/O port

AN2
10-bit A/D converter ch.2 analog input pin


16-bit reload timer ch.0 output pin


OUT2_1
32-bit output compare ch.2 output pin (Port 1)


INT18
External interrupt request 18 input pin

P73
General-purpose I/O port

AN3
10-bit A/D converter ch.3 analog input pin


16-bit reload timer ch.1 output pin


OUT3_1
32-bit output compare ch.3 output pin (Port 1)


INT19
External interrupt request 19 input pin

P70
50
51
52
53
38
39
40
41
AN0
OUT0_1
AN1
OUT1_1
TMO0
TMO1
E
E
E
E
(Continued)
14
DS07-16916-2E
MB91665 Series
Pin Number
64 pin 48 pin
54
55
56
57
58
42
43
44
45
46
Pin Name
I/O
Circuit
Type*1
Function
CMOS
CMOS
level
level
hysteresis
input
input
P74
General-purpose I/O port

AN4
10-bit A/D converter ch.4 analog input pin


16-bit reload timer ch.2 output pin


OUT4_1
32-bit output compare ch.4 output pin (Port 1)


INT20
External interrupt request 20 input pin

P75
General-purpose I/O port

AN5
10-bit A/D converter ch.5 analog input pin


SOUT0
(SDA0)
Multifunction serial interface ch.0 output pin.
This pin operates as SOUT0 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SDA0 when it is used in an I2C (operation mode
4).


TMI0
16-bit reload timer ch.0 input pin

OUT5_1
32-bit output compare ch.5 output pin (Port 1)

INT21
External interrupt request 21 input pin

P76
General-purpose I/O port

AN6
10-bit A/D converter ch.6 analog input pin

Multifunction serial interface ch.0 input pin

16-bit reload timer ch.1 input pin

OUT6_1
32-bit output compare ch.6 output pin (Port 1)

INT22
External interrupt request 22 input pin

P77
General-purpose I/O port

AN7
10-bit A/D converter ch.7 analog input pin

SCK0
(SCL0)
Multifunction serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL0 when it is used in an I2C (operation mode
4).

TMI2
16-bit reload timer ch.2 input pin

OUT7_1
32-bit output compare ch.7 output pin (Port 1)

INT23
External interrupt request 23 input pin

P80
General-purpose I/O port

10-bit A/D converter ch.8 analog input pin

32-bit input capture ch.0 input pin (Port 1)

16-bit reload timer ch.0 input pin (Port 1)

TMO2
SIN0
TMI1
AN8
IN0_1
TMI0_1
E
E
E
E
E






(Continued)
DS07-16916-2E
15
MB91665 Series
(Continued)
Pin Number
64 pin 48 pin
Pin Name
I/O
Circuit
Type*1
General-purpose I/O port

10-bit A/D converter ch.9 analog input pin

32-bit input capture ch.1 input pin (Port 1)

TMI1_1
16-bit reload timer ch.1 input pin (Port 1)

P82
General-purpose I/O port

10-bit A/D converter ch.10 analog input pin

IN2_1
32-bit input capture ch.2 input pin (Port 1)

P83
General-purpose I/O port

10-bit A/D converter ch.11 analog input pin

IN3_1
32-bit input capture ch.3 input pin (Port 1)

P60
General-purpose I/O port

RDY
External bus interface ready input pin
TIOA1_1
Base timer ch.1 TIOA pin (Port 1)

SOUT2_1
(SDA2_1)
Multifunction serial interface ch.2 output pin
(Port 1).
This pin operates as SOUT2_1 when it is used
in a UART/CSIO (operation modes 0 to 2) and
as SDA2_1 when it is used in an I2C (operation
mode 4).

P61
General-purpose I/O port

SYSCLK
External bus interface bus clock output pin

Base timer ch.1 TIOB pin (Port 1)

SIN2_1
Multifunction serial interface ch.2 input pin
(Port 1)

P10
General-purpose I/O port

D08
External bus interface data bus bit8
SOUT2
(SDA2)
Multifunction serial interface ch.2 output pin.
This pin operates as SOUT2 when it is used in
a UART/CSIO (operation modes 0 to 2) and as
SDA2 when it is used in an I2C (operation mode
4).

External interrupt request 0 input pin

P81
59
60
61
62
63
64
47


AN9
IN1_1
AN10
AN11


48
Function
CMOS
CMOS
level
level
hysteresis
input
input
E
E
E
B
TIOB1_1
INT0
C
Q






*1 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
*2 : 5 V tolerant pin.
16
DS07-16916-2E
MB91665 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
• Oscillation feedback resistance
approx. 1 M
• With standby control
X0
Standby control
B
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up control
Digital input
Standby control
Digital input
Standby control
•
•
•
•
•
CMOS level output
CMOS level input
CMOS level hysteresis input
With pull-up control
With standby control
Notes: • CMOS level input when input data,
RDY pin of external bus interface.
Input other than above
situations,CMOS level hysteresis
input.
• When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
• When this pin is used as a N-ch open
drain control pin, the digital output
P-ch transistor is always off.
(Continued)
DS07-16916-2E
17
MB91665 Series
Type
Circuit
Remarks
C
•
•
•
•
P-ch
P-ch
Digital output
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up control
With standby control
Note: When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
R
Pull-up control
Digital input
Standby
control
D
P-ch
N-ch
Digital output
Digital output
•
•
•
•
CMOS level output
CMOS level hysteresis input
5 V tolerant input
With standby control
Note: When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
R
Digital input
Standby
control
(Continued)
18
DS07-16916-2E
MB91665 Series
Type
Circuit
Remarks
E
P-ch
P-ch
N-ch
R
Digital output
Digital output
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up control
With standby control
Note: When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
Pull-up control
Digital input
Standby control
Analog input
Input control
I
X1A
P-ch
Digital output
N-ch
Digital output
• Oscillation feedback resistance
approx.10 M
• CMOS level output
• CMOS level hysteresis input
• With standby control
R
Digital input
Standby
control
Clock input
R
Standby control
Digital input
P-ch
Standby
control
Digital output
N-ch
Digital output
X0A
(Continued)
DS07-16916-2E
19
MB91665 Series
(Continued)
Type
Circuit
Remarks
P
• Flash memory product only
• CMOS level hysteresis input
• High voltage control for testing Flash
memory
N-ch
N-ch
Control pin
N-ch
N-ch
N-ch
Mode input
R
Q
P-ch
N-ch
Digital output
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level input
CMOS level hysteresis input
5 V tolerant input
With standby control
Note: When this pin is used as a N-ch open
drain control pin, the digital output
P-ch transistor is always off.
Digital input
Standby control
Digital input
Standby control
USB
USB I/O pin
UDP(+) output
UDP(+)
UDP(+) input
Differential
UDM(-)
Differential input
UDM(-) input
UDM(-) output
Direction
20
DS07-16916-2E
MB91665 Series
■ HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected
by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes
precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your
FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales representative
beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such
overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause
large current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such
pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Code: DS00-00004-1Ea
DS07-16916-2E
21
MB91665 Series
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply
pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can
cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the
design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or
loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
 Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers,
office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely high
levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior
approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR’s recommended conditions. For
detailed information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board
and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process
usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature.
Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead
to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket
contacts and IC leads be verified before mounting.
22
DS07-16916-2E
MB91665 Series
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder reflow
method, and has established a ranking of mounting conditions for each product. Users are advised to mount
packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will
cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture
can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the
following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate
bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125 C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the
following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance
(on the level of 1 M).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
DS07-16916-2E
23
MB91665 Series
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation.
In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely
affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect
the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users
should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
24
DS07-16916-2E
MB91665 Series
■ HANDLING DEVICES
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the
device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally
to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at low impedance.
It is also advisable that a ceramic capacitor of approximately 0.1 F be connected as a bypass capacitor between
VCC and VSS near this device.
 Crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0,
X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the
device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0 and X1 pins are surrounded
by ground plane as this is expected to produce stable operation.
 Using an external clock
When using an external clock, the clock signal should be input to the X0 pin only and the X1 pin should be kept
open.
 Example of Using an External Clock
X0
Open
X1
MB91665 series
 C Pin
As MB91660 series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 F
to the C pin for use by the regulator.
C
MB91665 series
4.7 µF
VSS
GND
DS07-16916-2E
25
MB91665 Series
 Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pullup/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as
short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching
the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching
to test mode due to noise.
 Notes on power-on
• To ensure that the internal regulator and the oscillator have stabilized immediately after the power is turned
on, keep an “L” level input connected to the INIT pin for the duration of the regulator voltage stabilization wait
time + the oscillator start time of the oscillator + the main oscillator stabilization wait time.
• Turn power on/off in the following order
Turning on : VCC  AVCC  AVRH
Turning off : AVRH  AVCC  VCC
• Release the reset (INIT pin “L” level to “H” level) after the power supply has stabilized.
 Caution on operations during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency.
However, Fujitsu will not guarantee results of operations if such failure occurs.
26
DS07-16916-2E
MB91665 Series
■ BLOCK DIAGRAM
Step-down regulator
FR80
CPU
Built-in program
memory
Flash memory
Cross bar
switch
RAM
On-chip bus
DMAC
4 channels
Peripheral bus
bridge
Watchdog timer
Interrupt controller
Delay interrupt
Port
External interrupt
16 channels
16 -bit peripheral bus
Clock control
32 -bit peripheral bus
External bus I/F
USB function/
HOST
Clock generation
USB clock
generation
Watch counter
16 -bit reload timer
3 channels
32-bit free-run timer
2channels
Base timer
4 channels
Up/down counter
1 channel
32-bit output compare
8 channels
A/D converter
12/10 channels (1 unit)*
Port
32-bit input capture
8 channels
Multi-function serial interface
4 channels
*: MB91F669 (64 pins): 12 channels
MB91F668 (48 pins): 10 channels
Port
DS07-16916-2E
27
MB91665 Series
■ MEMORY SPACE
1. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
 Direct Addressing Areas
The following areas in the address space are used as I/O areas.
These areas are called direct addressing areas, and the address of an operand in these areas can be specified
directly within an instruction. The size of the directly addressable area depends on the length of the data being
accessed as follows.
 Byte data access
: 0000 0000H to 0000 00FFH
 Half word data access : 0000 0000H to 0000 01FFH
 Word data access
: 0000 0000H to 0000 03FFH
28
DS07-16916-2E
MB91665 Series
2. Memory Map
MB91F668/F669
Flash 128 Kbytes
RAM 16 Kbytes
0000 0000H
I/O area
(Direct addressing)
0000 0400H
I/O area
0001 0000H
Reserved
0003 C000H
Internal RAM area
16 Kbytes
0004 0000H
Reserved
000E 0000H
Flash area 128 Kbytes
0010 0000H
Reserved
0024 0000H
External bus area
FFFF FFFFH
Notes :  Small sector area is related to flash products only. Please refer to the Flash Memory section of the
Hardware Manual for more details.
 Do not access the reserved areas.
DS07-16916-2E
29
MB91665 Series
■ I/O MAP
[How to read the table]
Address
Register
0
0000 0000H
PDR0 [R/W] B, H
XXXXXXXX
0000 003CH
0000 0040H
1
2
Block
3
PDR1 [R/W] B, H PDR2 [R/W] B, H PDR3 [R/W] B, H
XXXXXXXX
XXXXXXXXXXX
XXXXXXXX
Port data
register
WDTCR0 [R/W]
B, H
- 0 - - 0000
WDTCPR0 [R/W]
B, H
00000000

Watchdog
timer
EIRR0 [R/W] B, H, W
000 0000
ENIR0 [R/W]
B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
External
interrupt
0 to 7
 : Reserved area
Initial value after reset
“1” : Initial value“1”
“0” : Initial value“0”
“X” : Initial value undefined
“ - ” : Reserved bit or undefined bit
Access unit
(B : byte, H : half word, W : word)
Read/write attribute
“R”
: Indicates that there is a read only bit.
“R/W” : Indicates that there is a read/write bit.
“W”
: Indicates that there is a write only bit.
Register name (column 1 of the register is at address 4n, column 2 is
at address 4 n  2...)
Leftmost register address (For word-length access, column 1 of the
register is the MSB of the data.)
Notes :  When performing a data access, the addresses should be as below.
- Word access : Address should be multiples of 4 (least significant 2 bits should be “00B”)
- Half word access : Address should be multiples of 2 (least significant bit should be “0B”)
- Byte access : 
 Do not access the reserved areas.
30
DS07-16916-2E
MB91665 Series
Registers
Address
+0
+1
+2
+3
0000 0000H
PDR0 [R/W] B,H
XXXXXXXX
PDR1 [R/W] B,H
XXXXXXXX
PDR2 [R/W] B,H
XXXXXXXX

0000 0004H

PDR5 [R/W] B,H
XXXXXXXX
PDR6 [R/W] B,H
XXXXXXXX
PDR7[R/W] B,H
XXXXXXXX
0000 0008H
PDR8 [R/W] B,H
XXXXXXXX


0000 000CH
0000 0010H

0000 0014H
PDRK [R/W] B
----XXXX
Block
PDRH [R/W] B,H
----XXXX

Port data
register

0000 0018H
to
0000 001CH

0000 0020H
to
0000 0038H

Reserved
0000 003CH
WDTCR0[R/W]
B,H
- 0- - 0000
WDTCPR0[R/W]
B,H
00000000

Watchdog
timer
0000 0040H
EIRR0[R/W]
B,H,W
00000000
ENIR0[R/W]
B,H,W
00000000
ELVR0[R/W] B,H,W
00000000 00000000
External
interrupt
0 to 7
0000 0044H
DICR [R/W] B
-------0

Delay
interrupt
0000 0048H
TMRLRA0 [R/W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
0000 004CH
TMRLRB0 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] H
- - 000000 - - 000000
0000 0050H
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMR1 [R] H
XXXXXXXX XXXXXXXX
0000 0054H
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] H
- - 000000 - - 000000
0000 0058H
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMR2 [R] H
XXXXXXXX XXXXXXXX
0000 005CH
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] H
- - 000000 - - 000000
16-bit
reload timer
ch.0
16-bit
reload timer
ch.1
16-bit
reload timer
ch.2
(Continued)
DS07-16916-2E
31
MB91665 Series
Address
0000 0060H
0000 0064H
0000 0068H
0000 006CH
Registers
+0
+1
+2
+3
SCR0[R/W]
IBCR0[R,R/W]
B,H,W*2
0 - - 00000
SMR0
[R/W] B,H,W
000 - 0000
SSR0
[R,R/W] B,H,W
0 - 000011
ESCR0[R/W]
IBSR0[R,R/W]
B,H,W*2
- 0000000
BGR10[R/W]H,W
00000000
BGR00[R/W]
H,W
00000000
SSR1
[R,R/W] B,H,W
0 - 000011
ESCR1[R/W]
IBSR1[R,R/W]
B,H,W*2
- 0000000
BGR11[R/W]
H,W
00000000
BGR01[R/W]
H,W
00000000
RDR0[R]/TDR0[W] B,H,W*1
- - - - - - - 0 00000000
SCR1[R/W]
IBCR1[R,R/W]
B,H,W*2
0 - - 00000
SMR1
[R/W] B,H,W
000 - 0000
RDR1[R]/TDR1[W] B,H,W*1
- - - - - - - 0 00000000
0000 0070H
ISMK1 [R/W]
B,H*2
--------
ISBA1 [R/W]
B,H*2
--------
0000 0074H
SCR2[R/W]
IBCR2[R,R/W]
B,H,W*2
0 - - 00000
SMR2
[R/W] B,H,W
000 - 0000
0000 0078H
0000 007CH
0000 00A4H
0000 00A8H
0000 00ACH
0000 00B0H
to
0000 00B8H
SSR2
[R,R/W] B,H,W
0 - 000011
ESCR2[R/W]
IBSR2 [R,R/W]
B,H,W*2
- 0000000
BGR12[R/W]
H,W
00000000
BGR02[R/W]
H,W
00000000
ISBA2 [R/W]
B,H*2
--------
0000 0080H
to
0000 00A0H
SMR6
[R/W] B,H,W
000 - 0000
RDR6[R]/TDR6[W] B,H,W*1
- - - - - - - 0 00000000
ISMK6 [R/W]
B,H*2
--------
Multi-function serial
interface
ch.1
Multi-function serial
interface
ch.2


SCR6[R/W]
IBCR6[R,R/W]
B,H,W*2
0 - - 00000
Multi-function serial
interface ch.0

RDR2[R]/TDR2[W] B,H,W*1
- - - - - - - 0 00000000
ISMK2 [R/W]
B,H*2
--------
Block
ISBA6 [R/W]
B,H*2
--------
Reserved
SSR6
[R,R/W] B,H,W
0 - 000011
ESCR6[R/W]
IBSR6[R,R/W]
B,H,W*2
- 0000000
BGR16 [R/W]
H,W
00000000
BGR06 [R/W]
H,W
00000000
Multi-function serial
interface
ch.6


Reserved
(Continued)
32
DS07-16916-2E
MB91665 Series
Registers
Address
0000 00BCH
+0
+1
ISMK0 [R/W]
B,H*2
--------
ISBA0 [R/W]
B,H*2
--------
0000 00C0H
to
0000 0110H
+2
+3
Multi-function serial
interface
ch.0


EIRR2[R/W]
B,H,W
00000000
0000 0114H
ENIR2[R/W]
B,H,W
00000000
0000 0118H
to
0000 011CH
Reserved
ELVR2[R/W] B,H,W
00000000 00000000

ADCR0[R/W] B,H
000- 0000
ADSR0[R,R/W]
B,H
00- - - 000

0000 0124H
SCCR0[R,R/W]
B,H
1000- 000
SFNS0[R/W] B,H
- - - - 0000
SCFD0[R] B,H
XXXXXXXX XX- XXXXX
0000 0128H

SCIS20[R/W] B
00000000
SCIS10[R/W] B,H SCIS00[R/W] B,H
00000000
00000000
0000 012CH
PCCR0[R,R/W]
B,H
1000- 000
PFNS0[R/W] B,H
- - - - - - 00
PCFD0[R] B,H
XXXXXXXX XXXXXXXX
0000 0130H
PCIS0[R/W] B
00000000

CMPD0[R/W] B,H
00000000
CMPCR0[R/W]
B,H
00000000
0000 0134H

ADSS20[R/W] B
00000000
ADSS10[R/W]
B,H
00000000
ADSS00[R/W]
B,H
00000000
0000 0138H
ADST00[R/W]
B,H
00100000
ADST10[R/W]
B,H
00100000
ADCT0[R/W] B
- - - - - 111


0000 0140H
BT0TMR[R]H
00000000 00000000
0000 0144H

0000 0148H
0000 014CH
External
interrupt
16 to 23
Reserved
0000 0120H
0000 013CH
Block
A/D
converter
Reserved
BT0TMCR[R/W] B,H
-0000000 00000000
BT0STC[R/W]B
0000-000

BT0PDUT/BT0PRLH/BT0DTBF
[R/W]H
XXXXXXXX XXXXXXXX
BT0PCSR/BT0PRLL[R/W]H
XXXXXXXX XXXXXXXX
Base timer ch.0

(Continued)
DS07-16916-2E
33
MB91665 Series
Address
Registers
+0
+1
0000 0150H
BT1TMR[R]H
00000000 00000000
0000 0154H

0000 0158H
BT1PDUT/BT1PRLH/BT1DTBF
[R/W]H
XXXXXXXX XXXXXXXX
Base timer ch.1

BT2TMR[R]H
00000000 00000000
0000 0164H

BT2TMCR [R/W] B,H
-0000000 00000000
BT2STC[R/W]B
0000-000

BT2PDUT/BT2PRLH/BT2DTBF
[R/W]H
XXXXXXXX XXXXXXXX
BT2PCSR/BT2PRLL[R/W]H
XXXXXXXX XXXXXXXX
Base timer ch.2

0000 016CH
0000 0170H
BT3TMR[R]H
00000000 00000000
0000 0174H

0000 017CH
Block

BT1PCSR/BT1PRLL[R/W]H
XXXXXXXX XXXXXXXX
0000 0160H
0000 0178H
+3
BT1TMCR[R/W] B,H
-0000000 00000000
BT1STC[R/W]B
0000-000
0000 015CH
0000 0168H
+2
BT3TMCR[R/W] B,H
-0000000 00000000
BT3STC[R/W]B
0000-000

BT3PDUT/BT3PRLH/BT3DTBF
[R/W]H
XXXXXXXX XXXXXXXX
BT3PCSR/BT3PRLL[R/W]H
XXXXXXXX XXXXXXXX
BTSEL0123
[R/W] B
00000000
Base timer ch.3

0000 0180H
to
0000 01A8H

Reserved
0000 01ACH
ADCHE [R/W] B,H,W
-------- 111111-- ----1111 11111111
A/D channel
enable
0000 01B0H
IRPR0H [R] B
000- - - - -
0000 01B4H

IRPR2L [R]
B,H,W
000- - - - -
0000 01B8H
IRPR4H [R]
B,H,W
0000- - - -
IRPR4L [R]
B,H,W
000000- -
0000 01BCH

IRPR3H [R]
B,H,W
0000- - - -
IRPR3L [R]
B,H,W
00000 - - -
Interrupt
request
batch read function


(Continued)
34
DS07-16916-2E
MB91665 Series
Registers
Address
+0
+1
0000 01C0H
to
0000 01CCH
0000 01D0H
+2
+3

RCRH1 [W] H,W
00000000
0000 01D4H
RCRL1 [W]
B,H,W
00000000
Reserved
UDCRH1 [R] H,W
00000000
UDCRL1 [R]
B,H,W
00000000

CSR1 [R,R/W] B
00000000
CCR1 [R,R/W] B,H
00000000 -0001000
0000 01D8H

0000 01DCH
to
0000 01FCH

0000 0200H
CPCLR0 [R/W] W
11111111 11111111 11111111 11111111
0000 0204H
TCDT0 [R/W] W
00000000 00000000 00000000 00000000
0000 0208H
TCCSH0 [R/W]
B,H
0- - - - - 00
TCCSL0 [R/W]
B,H
- 1- 00000
32-bit
Free-run timer ch.0

IPCP0 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0210H
IPCP1 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0214H
IPCP2 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0218H
IPCP3 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

ICS01 [R/W] B
00000000

IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0224H
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0228H
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 022CH
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

ICS45 [R/W] B
00000000

32-bit
Input capture
ch.0 to ch.3
ICS23 [R/W] B
00000000
0000 0220H
0000 0230H
Up/down counter
ch.1
Reserved
0000 020CH
0000 021CH
Block
32-bit
Input capture
ch.4 to ch.7
ICS67 [R/W] B
00000000
(Continued)
DS07-16916-2E
35
MB91665 Series
Address
Registers
+0
+1
+2
+3
0000 0234H
OCCP0 [R/W] W
00000000 00000000 00000000 00000000
0000 0238H
OCCP1 [R/W] W
00000000 00000000 00000000 00000000
0000 023CH
OCCP2 [R/W] W
00000000 00000000 00000000 00000000
0000 0240H
OCCP3 [R/W] W
00000000 00000000 00000000 00000000
0000 0244H
OCSH1 [R/W]
B,H,W
- - - 0- - 00
OCSL0 [R/W]
B,H,W
0000- - 00
OCSH3 [R/W]
B,H,W
- - - 0- - 00
OCCP4 [R/W] W
00000000 00000000 00000000 00000000
0000 024CH
OCCP5 [R/W] W
00000000 00000000 00000000 00000000
0000 0250H
OCCP6 [R/W] W
00000000 00000000 00000000 00000000
0000 0254H
OCCP7 [R/W] W
00000000 00000000 00000000 00000000
OCSH5 [R/W]
B,H,W
- - - 0- - 00
OCSL4 [R/W]
B,H,W
0000- - 00
0000 025CH
FRTSEL [R/W] B
- - - - - - 00
OCSH7 [R/W]
B,H,W
- - - 0- - 00
Free-run timer
selector

CPCLR1 [R/W] W
11111111 11111111 11111111 11111111
0000 0264H
TCDT1 [R/W] W
00000000 00000000 00000000 00000000
TCCSH1 [R/W]
B,H
0- - - - - 00
TCCSL1 [R/W]
B,H
- 1- 00000
0000 026CH
to
0000 031CH
0000 0320H
0000 0324H
to
0000 0334H
32-bit
Output
compare
ch.4 to ch.7
OCSL6 [R/W]
B,H,W
0000- - 00
0000 0260H
0000 0268H
32-bit
Output
compare
ch.0 to ch.3
OCSL2 [R/W]
B,H,W
0000- - 00
0000 0248H
0000 0258H
Block
32-bit
Free-run timer ch.1


FCTLR[R/W] H
- 0- - 1011 - - - - - - - -
Reserved


FSTR[R] B
-------1
Flash memory
control
Reserved
(Continued)
36
DS07-16916-2E
MB91665 Series
Address
0000 0338H
Registers
+0
+1
+2
+3
WREN[R/W] B,H
00000000 00000000

0000 033CH

0000 0340H
to
0000 037CH

0000 0380H
WRAR00[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 0384H
WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0388H
WRAR01[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 038CH
WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0390H
WRAR02[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 0394H
WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0398H
WRAR03[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 039CH
WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03A0H
WRAR04[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03A4H
WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03A8H
WRAR05[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03ACH
WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03B0H
WRAR06[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03B4H
WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03B8H
WRAR07[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03BCH
WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03C0H
WRAR08[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
Block
Wild register
Reserved
Wild register
(Continued)
DS07-16916-2E
37
MB91665 Series
Address
Registers
+0
+1
+2
+3
0000 03C4H
WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03C8H
WRAR09[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03CCH
WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03D0H
WRAR10[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03D4H
WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03D8H
WRAR11[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03DCH
WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03E0H
WRAR12[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03E4H
WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03E8H
WRAR13[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03ECH
WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03F0H
WRAR14[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03F4H
WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 03F8H
WRAR15[R/W] W
- - - - - - - - - - XXXXXX XXXXXXXX XXXXXX- -
0000 03FCH
WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild register
0000 0400H
DDR0 [R/W] B,H
00000000
DDR1 [R/W] B,H
00000000
DDR2 [R/W] B,H
00000000
DDR3 [R/W] B,H
00000000
0000 0404H
DDR4 [R/W] B,H
00000000
DDR5 [R/W] B,H
00000000
DDR6 [R/W] B,H
00000000
DDR7[R/W] B,H
00000000
0000 0408H
DDR8 [R/W] B
00000000

0000 040CH
0000 0410H
DDRA [R/W] B
00000000
Block

Data direction
register

DDRG [R/W] B,H DDRH [R/W] B,H
00000000
- - - - 0000

(Continued)
38
DS07-16916-2E
MB91665 Series
Registers
Address
+0
+1
+2
DDRK [R/W] B
- - - - 0000
0000 0414H
+3
Block

0000 0418H
to
0000 041CH
Data direction
register

0000 0420H
PCR0 [R/W] B,H
00000000
PCR1 [R/W] B,H
00000000
0000 0424H

PCR5 [R/W] B
00000000
0000 0428H
PCR8 [R/W] B,H
00000000

PCR6 [R/W] B,H
00000000
PCR7[R/W] B,H
00000000

0000 042CH
to
0000 043CH
Pull-up
control
register

0000 0440H
ICR00 [R,R/W]
B,H,W
- - - 11111
ICR01 [R,R/W]
B,H,W
- - - 11111
ICR02 [R,R/W]
B,H,W
- - - 11111
ICR03 [R,R/W]
B,H,W
- - - 11111
0000 0444H
ICR04 [R,R/W]
B,H,W
- - - 11111
ICR05 [R,R/W]
B,H,W
- - - 11111
ICR06 [R,R/W]
B,H,W
- - - 11111
ICR07 [R,R/W]
B,H,W
- - - 11111
0000 0448H
ICR08 [R,R/W]
B,H,W
- - - 11111
ICR09 [R,R/W]
B,H,W
- - - 11111
ICR10 [R,R/W]
B,H,W
- - - 11111
ICR11 [R,R/W]
B,H,W
- - - 11111
0000 044CH
ICR12 [R,R/W]
B,H,W
- - - 11111
ICR13 [R,R/W]
B,H,W
- - - 11111
ICR14 [R,R/W]
B,H,W
- - - 11111
ICR15 [R,R/W]
B,H,W
- - - 11111
0000 0450H
ICR16 [R,R/W]
B,H,W
- - - 11111
ICR17 [R,R/W]
B,H,W
- - - 11111
ICR18 [R,R/W]
B,H,W
- - - 11111
ICR19 [R,R/W]
B,H,W
- - - 11111
0000 0454H
ICR20 [R,R/W]
B,H,W
- - - 11111
ICR21 [R,R/W]
B,H,W
- - - 11111
ICR22 [R,R/W]
B,H,W
- - - 11111
ICR23 [R,R/W]
B,H,W
- - - 11111
0000 0458H
ICR24 [R,R/W]
B,H,W
- - - 11111
ICR25 [R,R/W]
B,H,W
- - - 11111
ICR26 [R,R/W]
B,H,W
- - - 11111
ICR27 [R,R/W]
B,H,W
- - - 11111
0000 045CH
ICR28 [R,R/W]
B,H,W
- - - 11111
ICR29 [R,R/W]
B,H,W
- - - 11111
ICR30 [R,R/W]
B,H,W
- - - 11111
ICR31 [R,R/W]
B,H,W
- - - 11111
Interrupt
control
(Continued)
DS07-16916-2E
39
MB91665 Series
Address
Registers
+0
+1
+2
+3
0000 0460H
ICR32 [R,R/W]
B,H,W
- - - 11111
ICR33 [R,R/W]
B,H,W
- - - 11111
ICR34 [R,R/W]
B,H,W
- - - 11111
ICR35 [R,R/W]
B,H,W
- - - 11111
0000 0464H
ICR36 [R,R/W]
B,H,W
- - - 11111
ICR37 [R,R/W]
B,H,W
- - - 11111
ICR38 [R,R/W]
B,H,W
- - - 11111
ICR39 [R,R/W]
B,H,W
- - - 11111
0000 0468H
ICR40 [R,R/W]
B,H,W
- - - 11111
ICR41 [R,R/W]
B,H,W
- - - 11111
ICR42 [R,R/W]
B,H,W
- - - 11111
ICR43 [R,R/W]
B,H,W
- - - 11111
0000 046CH
ICR44 [R,R/W]
B,H,W
- - - 11111
ICR45 [R,R/W]
B,H,W
- - - 11111
ICR46 [R,R/W]
B,H,W
- - - 11111
ICR47 [R,R/W]
B,H,W
- - - 11111
0000 0470H
to
0000 047CH
0000 0480H

RSTRR [R]
B,H,W
11-X- - - X*3
RSTCR [R/W]
B,H,W
000- - - - 0
0000 0488H
DIVR0 [R/W] B,H DIVR1 [R/W] B,H
000- - - - 0001- - - -
0000 0490H
STBCR [R/W]
B,H,W
0000- - 11
SLPRR [R/W]
B,H,W
00000000
DIVR2 [R/W] B
0011- - - -

IORR2 [R/W]
B,H,W
- 0000000
IORR3 [R/W]
B,H,W
- 0000000

0000 048CH
IORR0 [R/W]
B,H,W
- 0000000
IORR1 [R/W]
B,H,W
- 0000000
0000 0494H
to
0000 049CH

PFR0 [R/W] B,H
00000000
PFR1 [R/W] B,H
00000000
PFR2 [R/W] B,H
00000000
PFR3 [R/W] B,H
00000000
0000 04A4H
PFR4 [R/W] B,H
00000000
PFR5 [R/W] B,H
00000000
PFR6 [R/W] B,H
00- 00- 0-
PFR7[R/W] B,H
00000000
0000 04A8H
PFR8 [R/W] B
00000000

Clock division
control
Peripheral DMA
transmission
request control
PFRA [R/W] B
00-00000

Port function
register

0000 04ACH
0000 04B4H
Reset control/
Power consumption
control
Reserved
0000 04A0H
0000 04B0H
Interrupt
control
Reserved

0000 0484H
Block
PFRG [R/W] B,H
- 000- 000
PFRH [R/W] B,H
- - - - - 0- 0


(Continued)
40
DS07-16916-2E
MB91665 Series
Registers
Address
+0
+1
+2
+3
0000 04B8H
EPFR0 [R/W] B,H EPFR1 [R/W] B,H EPFR2 [R/W] B,H EPFR3 [R/W] B,H
- - 000000
- - 000000
- - 000000
- - 000000
0000 04BCH
EPFR4 [R/W] B,H EPFR5 [R/W] B,H EPFR6 [R/W] B,H EPFR7 [R/W] B,H
00000000
00000000
00000000
- - - 00000
0000 04C0H
EPFR8 [R/W] B,H EPFR9 [R/W] B,H
- - - 00000
- - - 00000
EPFR10 [R/W]
B,H
- - - 00000
EPFR11 [R/W]
B,H
- - - 00000
0000 04C4H
EPFR12 [R/W]
B,H
- - - 00000
EPFR13 [R/W]
B,H
- - - 00000
EPFR14 [R/W]
B,H
- - - 00000
EPFR15 [R/W]
B,H
- - - 00000
0000 04C8H
EPFR16 [R/W]
B,H
- - - 00000
EPFR17 [R/W]
B,H
- - - 00000
EPFR18 [R/W]
B,H
00000000
EPFR19 [R/W]
B,H
- - - - 0001
0000 04CCH
EPFR20 [R/W]
B,H
- - 000000
EPFR21 [R/W]
B,H
- - 000000
EPFR22 [R/W]
B,H
- - 000000
EPFR23 [R/W]
B,H
- - 000000
0000 04D0H
EPFR24 [R/W]
B,H
- - 000000
EPFR25 [R/W]
B,H
- - 000000
EPFR26 [R/W]
B,H
- - 000000
EPFR27 [R/W]
B,H
- - 000000
0000 04D4H
EPFR28 [R/W]
B,H
00000000
EPFR29 [R/W]
B,H
00000000
EPFR30 [R/W]
B,H
- - - - 0000
EPFR31 [R/W]
B,H
- 0000000
0000 04D8H
EPFR32 [R/W]
B,H
00000000
EPFR33 [R/W]
B,H
- - 000000
EPFR34 [R/W]
B,H
- 0000000
EPFR35 [R/W]
B,H
- - - - - - 00
0000 04DCH
NDE0 [R/W]
B,H
00000000
NDE1 [R/W]
B,H
00000000
EXBS [R/W]
B
-------0

0000 04E0H
to
0000 04ECH

Extended port
function
register
Reserved
0000 04F0H
ICSEL0[R/W]
B,H,W
- - - - - 000

ICSEL2[R/W]
B,H,W
- - - - - 000

0000 04F4H
ICSEL4[R/W]
B,H,W
- - - - - - 00

ICSEL6[R/W]
B,H,W
- - - - - - 00
ICSEL7[R/W]
B,H,W
-------0
0000 04F8H
ICSEL8[R/W]
B,H,W
- - - - - - 00
ICSEL9[R/W]
B,H,W
- - - - - 000
ICSEL10[R/W]
B,H,W
- - - - 0000

0000 04FCH
Block
DMA start
request clear select
function

(Continued)
DS07-16916-2E
41
MB91665 Series
Address
Registers
+0
+1
+2
+3
Block
0000 0500H

Reserved
0000 0504H
FRID [R] W
For the initial value, see the I/O Ports section of the Hardware Manual.
FR80ID
0000 0508H
to
0000 050CH

Reserved
0000 0510H
0000 0514H
CSELR [R/W]
B,H,W
001- - - 00
CMONR [R]
B,H,W
001- - - 00
PLLCR [R/W] B,H
- - 000000 11110000
0000 0518H
WCRD [R] B,H
- - 000000
0000 051CH
UCCR [R/W] B
- - - - - 001
MTMCR [R/W]
B,H,W
00001111
STMCR [R/W]
B,H,W
0000- 111
CSTBR [R/W] B
- 0000000

Clock
generation/
Main timer/
Sub timer

Clock counter
WCRL [R/W] B,H WCCR [R,R/W] B
- - 000000
00- - 0000

0000 0520H
to
0000 05FCH

0000 0600H
ASR0 [R/W] W
00000000 00000000 - - - - - - - - 1111- 001
0000 0604H
ASR1 [R/W] W
XXXXXXXX XXXXXXXX - - - - - - - - XXXX- XX0
0000 0608H
ASR2 [R/W] W
XXXXXXXX XXXXXXXX - - - - - - - - XXXX- XX0
0000 060CH
ASR3 [R/W] W
XXXXXXXX XXXXXXXX - - - - - - - - XXXX- XX0
0000 0610H
to
0000 063CH

0000 0640H
ACR0[R/W] W
- - - - - - - - - - - - - - - - - - - - - - - - 00- - 00- 0
0000 0644H
ACR1[R/W] W
- - - - - - - - - - - - - - - - - - - - - - - - XX- - XX- X
0000 0648H
ACR2[R/W] W
- - - - - - - - - - - - - - - - - - - - - - - - XX- - XX- X
0000 064CH
ACR3[R/W] W
- - - - - - - - - - - - - - - - - - - - - - - - XX- - XX- X
0000 0650H
to
0000 067CH

USB clock
generation
Reserved
External bus I/F
(Continued)
42
DS07-16916-2E
MB91665 Series
Address
Registers
+0
+1
+2
0000 0680H
AWR0 [R/W] W
- - - - 1111 00000000 11110000 00000- 0-
0000 0684H
AWR1 [R/W] W
- - - - XXXX XXXXXXXX XXXXXXXX XXXXX- X-
0000 0688H
AWR2 [R/W] W
- - - - XXXX XXXXXXXX XXXXXXXX XXXXX- X-
0000 068CH
AWR3 [R/W] W
- - - - XXXX XXXXXXXX XXXXXXXX XXXXX- X-
0000 0690H
to
0000 06BCH

0000 06C0H
to
0000 0BFCH

0000 0C00H
DCCR0 [R/W] W
0- - - - 000 - - 00- - 00 00000000 0- 000000
0000 0C04H
DCSR0 [R, R/W] H
0- - - - - - - - - - - - 000
0000 0C0CH
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C10H
DCCR1 [R/W] W
0- - - - 000 - - 00- - 00 00000000 0- 000000
DTCR1 [R/W] H
00000000 00000000
0000 0C18H
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C1CH
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C20H
DCCR2 [R/W] W
0- - - - 000 - - 00- - 00 00000000 0- 000000
0000 0C24H
DCSR2 [R, R/W] H
0- - - - - - - - - - - - 000
External bus I/F
DTCR0 [R/W] H
00000000 00000000
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCSR1 [R, R/W] H
0- - - - - - - - - - - - 000
Block
Reserved
0000 0C08H
0000 0C14H
+3
DMAC
DTCR2 [R/W] H
00000000 00000000
0000 0C28H
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C2CH
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C30H
DCCR3 [R/W] W
0- - - - 000 - - 00- - 00 00000000 0- 000000
(Continued)
DS07-16916-2E
43
MB91665 Series
Address
0000 0C34H
Registers
+0
+1
+2
DCSR3 [R, R/W] H
0- - - - - - - - - - - - 000
+3
DTCR3 [R/W] H
00000000 00000000
0000 0C38H
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000 0C3CH
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
0000 0C40H
to
0000 0DF0H

DILVR [R,R/W] B
- - - 11111

0000 0DF4H
0000 0DF8H
DMACR [R/W] W
0- - - - - - - - - - - - - - - 0- - - - - - - - - - - - - - -
0000 0DFCH
to
0000 20FCH

Reserved
0000 2100H
HCNT1[R/W] B,H HCNT0[R/W] B,H
- - - - - 001
00000000

0000 2104H
HERR[R/W] B,H
00000011
HIRQ[R/W] B,H
0- 000000

0000 2108H
HFCOMP[R/W]
B,H
00000000
HSTATE[R,R/W]
B,H
- - - 10010

HRTIMER1[R/W] HRTIMER0[R/W]
B,H
B,H
00000000
00000000

0000 210CH
Block
USB function/
HOST
0000 2110H
HADR[R/W] B,H
- 0000000
HRTIMER2[R/W]
B,H
- - - - - - 00

0000 2114H
HEOF1[R/W] B,H HEOF0[R/W] B,H
- - 000000
00000000

0000 2118H
HFRAME1[R/W]
B,H
- - - - - 000
HFRAME0[R/W]
B,H
00000000

0000 211CH

HTOKEN[R/W] B
00000000

(Continued)
44
DS07-16916-2E
MB91665 Series
Registers
Address
+0
+1
0000 2120H

UDCC[R/W] B
1010- - 00
0000 2124H
EP0C[R/W] H
- - - - - - 0- - 1000000

0000 2128H
EP1C[R/W] H
01100001 00000000

0000 212CH
EP2C[R/W] H
0110000- - 1000000

0000 2130H
EP3C[R/W] H
0110000- - 1000000

0000 2134H
to
0000 2138H
+2
+3
Block


TMSP[R] H
- - - - - 000 00000000
0000 213CH
UDCIE[R,R/W]
B,H
- - 000000
0000 2140H

UDCS[R/W] B,H
- - 000000

0000 2144H
EP0IS[R/W] H
10- - - 1- - - - - - - - - -

0000 2148H
EP00S[R,R/W] H
100- - 00- - XXXXXXX

0000 214CH
EP1S[R,R/W] H
100- 000X XXXXXXXX

0000 2150H
EP2S[R,R/W] H
100- 000- - XXXXXXX

0000 2154H
EP3S[R,R/W] H
100- 000- - XXXXXXX

0000 2158H
to
0000 215CH
USB function/
HOST

0000 2160H
EP0DTH [R/W]
B,H XXXXXXXX
EP0DTL [R/W]
B,H XXXXXXXX

0000 2164H
EP1DTH [R/W]
B,H XXXXXXXX
EP1DTL [R/W]
B,H XXXXXXXX

0000 2168H
EP2DTH [R/W]
B,H XXXXXXXX
EP2DTL [R/W]
B,H XXXXXXXX

0000 216CH
EP3DTH [R/W]
B,H XXXXXXXX
EP3DTL [R/W]
B,H XXXXXXXX

(Continued)
DS07-16916-2E
45
MB91665 Series
(Continued)
Address
Registers
+0
+1
+2
+3
Block
0000 2170H
to
0000 217CH

USB function/
HOST
0000 2180H
to
0000 21A0H

Reserved
0000 21A4H
DREQSEL [R/W]
B,H
00111011
USBSEL [R/W]
B,H
-------0
0000 21A8H
to
0000 FFFCH
USBEN [R/W] B
-------0


DMA transfer
request selector/
USB enable
Reserved
*1 : Byte access is available only when accessing the lower 8 bits within 9 bits.
*2 : The register of I2C can not be read immediate after reset.
*3 : Value just after reset by INIT pin.
Do not access the reserved areas.
46
DS07-16916-2E
MB91665 Series
■ VECTOR TABLE
Interrupt
Number
Dec.
Hex.
Interrupt level
setting
registers
Reset
0
00

3FCH
000F FFFCH
Reserved for system
1
01

3F8H
000F FFF8H
Reserved for system
2
02

3F4H
000F FFF4H
Reserved for system
3
03

3F0H
000F FFF0H
Reserved for system
4
04

3ECH
000F FFECH
Reserved for system
5
05

3E8H
000F FFE8H
Reserved for system
6
06

3E4H
000F FFE4H
Reserved for system
7
07

3E0H
000F FFE0H
Reserved for system
8
08

3DCH
000F FFDCH
INTE instruction
9
09

3D8H
000F FFD8H
Reserved for system
10
0A

3D4H
000F FFD4H
Reserved for system
11
0B

3D0H
000F FFD0H
Step trace trap
12
0C

3CCH
000F FFCCH
Reserved for system
13
0D

3C8H
000F FFC8H
Undefined instruction exception
14
0E

3C4H
000F FFC4H
15
0F
Always 15(FH)
3C0H
000F FFC0H
External interrupt request ch.0 to ch.7
16
10
ICR00
3BCH
000F FFBCH
Reserved
17
11
ICR01
3B8H
000F FFB8H
External interrupt request ch.16 to ch.23
18
12
ICR02
3B4H
000F FFB4H
Reserved
19
13
ICR03
3B0H
000F FFB0H
20
14
ICR04
3ACH
000F FFACH
Reception interrupt request from UART/CSIO/I C
ch.0
21
15
ICR05
3A8H
000F FFA8H
Transmission interrupt request from UART/CSIO/
I2C ch.0
Transmission bus idle interrupt request from
UART/CSIO ch.0
22
16
ICR06
3A4H
000F FFA4H
Reception interrupt request from UART/CSIO/I2C
ch.1
23
17
ICR07
3A0H
000F FFA0H
Transmission interrupt request from UART/CSIO/
I2C ch.1
Transmission bus idle interrupt request from
UART/CSIO ch.1
24
18
ICR08
39CH
000F FF9CH
Status interrupt request from I2C ch.1
25
19
ICR09
398H
000F FF98H
26
1A
ICR10
394H
000F FF94H
Interrupt Source (Peripheral Function)

16-bit reload timer ch.0 to ch.2
Offset
TBR Initial
address
2
2
Reception interrupt request from UART/CSIO/I C
ch.2
(Continued)
DS07-16916-2E
47
MB91665 Series
Interrupt
Number
Dec.
Hex.
Interrupt level
setting
registers
Transmission interrupt request from UART/CSIO/
I2C ch.2
Transmission bus idle interrupt request from
UART/CSIO ch.2
27
1B
ICR11
390H
000F FF90H
Status interrupt request from I2C ch.2
28
1C
ICR12
38CH
000F FF8CH
Reserved
29
1D
ICR13
388H
000F FF88H
Reserved
30
1E
ICR14
384H
000F FF84H
Reserved
31
1F
ICR15
380H
000F FF80H
Reserved
32
20
ICR16
37CH
000F FF7CH
Reserved
33
21
ICR17
378H
000F FF78H
34
22
ICR18
374H
000F FF74H
Reception interrupt request from UART/CSIO/I C
ch.6
35
23
ICR19
370H
000F FF70H
Transmission interrupt request from UART/CSIO/
I2C ch.6
Transmission bus idle interrupt request from
UART/CSIO ch.6
Status interrupt request from I2C ch.6
36
24
ICR20
36CH
000F FF6CH
32-bit input capture ch.4 to ch.7
37
25
ICR21
368H
000F FF68H
32-bit output compare ch.4 to ch.7
38
26
ICR22
364H
000F FF64H
Reserved
39
27
ICR23
360H
000F FF60H
16-bit up/down counter ch.0
40
28
ICR24
35CH
000F FF5CH
Main timer/sub timer/watch counter
41
29
ICR25
358H
000F FF58H
10-bit A/D converter
- Scanning conversion interrupt request
- Priority conversion interrupt request
- FIFO overrun interrupt request
- Conversion result comparison interrupt request
42
2A
ICR26
354H
000F FF54H
32-bit free-run timer ch.0, ch.1
43
2B
ICR27
350H
000F FF50H
32-bit input capture ch.0 to ch.3
44
2C
ICR28
34CH
000F FF4CH
32-bit output compare ch.0 to ch.3
45
2D
ICR29
348H
000F FF48H
Base timer ch.0
46
2E
ICR30
344H
000F FF44H
Base timer ch.1
47
2F
ICR31
340H
000F FF40H
Base timer ch.2
48
30
ICR32
33CH
000F FF3CH
Base timer ch.3
49
31
ICR33
338H
000F FF38H
Reserved
50
32
ICR34
334H
000F FF34H
Reserved
51
33
ICR35
330H
000F FF30H
Interrupt Source (Peripheral Function)
Reserved
Offset
TBR Initial
address
2
(Continued)
48
DS07-16916-2E
MB91665 Series
(Continued)
Interrupt
Number
Dec.
Hex.
Interrupt level
setting
registers
Reserved
52
34
ICR36
32CH
000F FF2CH
Reserved
53
35
ICR37
328H
000F FF28H
USB function (End point 1 to 3 for DRQ)
54
36
ICR38
324H
000F FF24H
USB function (End point 0 for DRQI, DRQO and
each status)/USB HOST (each status)
55
37
ICR39
320H
000F FF20H
Reserved
56
38
ICR40
31CH
000F FF1CH
DMA Controller (DMAC) ch.0
57
39
ICR41
318H
000F FF18H
DMA Controller (DMAC) ch.1
58
3A
ICR42
314H
000F FF14H
DMA Controller (DMAC) ch.2
59
3B
ICR43
310H
000F FF10H
DMA Controller (DMAC) ch.3
60
3C
ICR44
30CH
000F FF0CH
Reserved
61
3D
ICR45
308H
000F FF08H
System reserved
62
3E
ICR46
304H
000F FF04H
Delay interrupt
63
3F
ICR47
300H
000F FF00H
Reserved for system (used by REALOS)
64
40

2FCH
000F FEFCH
Reserved for system (used by REALOS)
65
41

2F8H
000F FEF8H
Used by the INT instruction
66
to
255
42
to
FF

2F4H
to
000H
000F FEF4H
to
000F FC00H
Interrupt Source (Peripheral Function)
DS07-16916-2E
Offset
TBR Initial
address
49
MB91665 Series
* : USB interrupt source
Interrupt Number
Decimal
Hexadecimal
54
36
55
37
USB interrupt source
USB function
(DRQ of End Point 1 to 3)
DRQ (End Point1 to 3)
USB function
DRQI, DRQO, SPK, SUSP,
(DRQI, DRQO of End Point 0 and each status) SOF, BRST, CONF, WKUP
USB HOST (Each status)
50
Details
DIRQ, URIRQ, RWKIRQ,
CNNIRQ, SOFIRQ, CMPIRQ
DS07-16916-2E
MB91665 Series
■ PIN STATUS IN EACH CPU STATE
• When INIT = “L”
This is the period when the INIT pin is the “L” level.
• When INIT = “H”
The status immediately after the INIT pin changes from the “L” level to the “H” level.
• SLVL1
This bit is a standby level setting bit in the standby mode control register (STBCR).
• Input enabled
Indicates that the input function can be used.
• Input disabled
Indicates that the input function cannot be used.
• Output Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
• Maintain previous state
Maintains the state that was being output immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
• Internal input fixed at “0”
The input gate connected to the pin is disconnected from the external input and internally connected to “0”.
• Input enabled when interrupt function selected and enabled
Inputs are allowed only when the pin is configured as an external interrupt request input pin and the external
interrupt request is enabled.
DS07-16916-2E
51
MB91665 Series
 List of pin status
During initialization
Pin
Name
Function Name
INIT
INIT

INIT  “L” INIT  “H”
Period
Period
Sleep
Mode
Standby Mode
SLVL1  0
SLVL1  1

Input
enabled
Input
enabled
X0
Input
enabled
Input
enabled
Hi-Z
or
Input
enabled
Hi-Z
or
Input
enabled
X1
X1
Input
enabled
Input
enabled
“H” output
or
Input
enabled
“H”output
or
Input
enabled
X0A
X0A
(When INIT input, see PK1.
When port selected,
input disabled)
Input
disabled
Input
disabled
Hi-Z
or
Input
enabled
Hi-Z
or
Input
enabled
X1A
X1A
(When INIT input, see PK0.
When port selected,
input disabled)
Input
disabled
Input
disabled
“H”output
or
Input
enabled
“H”output
or
Input
enabled
MD0
MD0
Input
enabled
Input
enabled
MD1
MD1
Input
enabled
Input
enabled
Input
enabled
Input
enabled
P00
P00/D00/TIOA0/SOUT0_1/IN0
P01
P01/D01/TIOB0/SIN0_1/IN1
P02
P02/D02/TIOA1/SCK0_1/IN2
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Maintain
previous
state
Output
Hi-Z/
Internal
input
fixed at “0”
X0
P03
P03/D03/TIOB1/IN3
P04
P04/D04/TIOA2/SOUT1/IN4
P05
P05/D05/TIOB2/SIN1/IN5
P06
P06/D06/TIOA3/SCK1/IN6
P07
P07/D07/TIOB3/IN7
P10
P10/D08/SOUT2/INT0
P11
P11/D09/SIN2/INT1
P12
P12/D10/SCK2/INT2
P13
P13/D11/INT3
P14
P14/D12/AIN1/INT4/OUT4
P15
P15/D13/BIN1/INT5/OUT5
P16
P16/D14//ZIN1/INT6/OUT6
P17
P17/D15/INT7/OUT7
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed at “0”
Input enabled
when interrupt
function
selected and
enabled
(Continued)
52
DS07-16916-2E
MB91665 Series
During initialization
Pin
Name
Function Name
P20
P20/A00/TMO1_1/A16
P21
P21/A01/TMO2_1/A17
P22
P22/A02/TIOA0_1/A18
P23
P23/A03/TIOB0_1/A19
P24
P24/A04/OUT0/A20
P25
P25/A05/OUT1/A21
P26
P26/A06/OUT2/A22
P27
P27/A07/OUT3/A23
P50
P50/CS0/TMO0_1
P51
P51/CS1/TIOA2_1/SOUT1_1
P52
P52/CS2/TIOB2_1/SIN1_1
P53
P53/CS3/FRCK1/TIOA3_1/
SCK_1
P54
P54/AS/SOUT6/AIN1_1
P55
P55/RD/SIN6/BIN1_1/ADTRG0
P56
P56/WR0/SCK6/ZIN1_1/FRCK0
P57
P57/WR1/TIOB3_1/TMI2_1
P60
P60/RDY/TIOA1_1/SOUT2_1
P61
P61/SYSCLK/TIOB1_1/SIN2_1
P70
P70/AN0/OUT0_1/INT16
P71
P71/AN1/OUT1_1/INT17
P72
P72/AN2/TMO0/OUT2_1/INT18
P73
P73/AN3/TMO1/OUT3_1/INT19
P74
P74/AN4/TMO2/OUT4_1/INT20
P75
P75/AN5/SOUT0/TMI0/OUT5_1/
INT21
P76
P76/AN6/SIN0/TMI1/OUT6_1/
INT22
P77
P77/AN7/SCK0/TMI2/OUT7_1/
INT23
INIT  “L” INIT  “H”
Period
Period
Standby Mode
Sleep
Mode
SLVL1  0
SLVL1  1
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed at “0”
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed at “0”
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed at “0”
Output
Hi-Z
Output
Hi-Z/
Input
disabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed
at “0”
Input enabled
when interrupt
function
selected and
enabled
(Continued)
DS07-16916-2E
53
MB91665 Series
(Continued)
During initialization
Pin
Name
Function Name
P80
P80/AN8/IN0_1/TMI0_1
P81
P81/AN9/IN1_1/TMI1_1
INIT  “L” INIT  “H”
Period
Period
Output
Hi-Z
P82
P82/AN10/IN2_1
P83
P83/AN11/IN3_1
PH2
54
SLVL1  0
SLVL1  1
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z/
Internal
input fixed
at “0”
Output Hi-Z/
Internal
input fixed at “0”
PH2/SCK2_1/INT2_1
PH3
PH3/INT3_1
PK0
PK0
PK1
PK1
UDP
UDP (USB)
UDM
Output
Hi-Z/
Input
disabled
Standby Mode
Sleep
Mode
UDM (USB)
Output
Hi-Z
Output
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Output
Hi-Z
Output
Hi-Z/
Internal input fixed at
“0”
Maintain
previous
state
Maintain
previous
state
Output Hi-Z/
Internal
input fixed at “0”
Output
Hi-Z
Output
Hi-Z/Input
enabled
Maintain
previous
state/Input
enabled
Maintain
previous
state
Maintain
previous state
Input enabled
when interrupt
function
selected and
enabled
DS07-16916-2E
MB91665 Series
 List of pin status (serial write mode)
Pin
name
Function
During
initialization
During
asynchronous
write operation
INIT  “L”
During synchronous
write operation
INIT  “H”
INIT
INIT



X0
X0
Input
enabled
Input
enabled
Input
enabled
X1
X1
Input
enabled
Input
enabled
Input
enabled
X0A
X0A
(When INIT input, see PK1.
When port selected,
input disabled)
Input
disabled
Input
disabled
Input
disabled
X1A
X1A
(When INIT input, see PK0.
When port selected,
input disabled)
Input
disabled
Input
disabled
Input
disabled
MD0
MD0
Input
enabled
Input
enabled
Input
enabled
MD1
MD1
Input
enabled
Input
enabled
Input
enabled
P00
P00/D00/TIOA0/SOUT0_1/IN0
P01
P01/D01/TIOB0/SIN0_1/IN1
P02
P02/D02/TIOA1/SCK0_1/IN2
P03
P03/D03/TIOB1/IN3
P04
P04/D04/TIOA2/SOUT1/IN4
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
P05
P05/D05/TIOB2/SIN1/IN5
P06
P06/D06/TIOA3/SCK1/IN6
P07
P07/D07/TIOB3/IN7
P10
P10/D08/SOUT2/INT0
P11
P11/D09/SIN2/INT1
P12
P12/D10/SCK2/INT2
P13
P13/D11/INT3
P14
P14/D12/AIN1/INT4/OUT4
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
P15
P15/D13/BIN1/INT5/OUT5
P16
P16/D14//ZIN1/INT6/OUT6
P17
P17/D15/INT7/OUT7
(Continued)
DS07-16916-2E
55
MB91665 Series
Pin
name
Function
During
initialization
During
asynchronous
write operation
INIT  “L”
P20
P20/A00/TMO1_1/A16
P21
P21/A01/TMO2_1/A17
P22
P22/A02/TIOA0_1/A18
P23
P23/A03/TIOB0_1/A19
P24
P24/A04/OUT0/A20
P25
P25/A05/OUT1/A21
P26
P26/A06/OUT2/A22
P27
P27/A07/OUT3/A23
P50
P50/CS0/TMO0_1
P51
P51/CS1/TIOA2_1/SOUT1_1
P52
P52/CS2/TIOB2_1/SIN1_1
P53
P53/CS3/FRCK1/TIOA3_1/
SCK_1
P54
P54/AS/SOUT6/AIN1_1
P55
P55/RD/SIN6/BIN1_1/ADTRG0
P56
P56/WR0/SCK6/ZIN1_1/FRCK0
P57
P57/WR1/TIOB3_1/TMI2_1
P60
P60/RDY/TIOA1_1/SOUT2_1
P61
P61/SYSCLK/TIOB1_1/SIN2_1
P70
P70/AN0/OUT0_1/INT16
P71
P71/AN1/OUT1_1/INT17
P72
P72/AN2/TMO0/OUT2_1/INT18
P73
P73/AN3/TMO1/OUT3_1/INT19
P74
P74/AN4/TMO2/OUT4_1/INT20
P75
P75/AN5/SOUT0/TMI0/OUT5_1/
INT21
P76
P76/AN6/SIN0/TMI1/OUT6_1/
INT22
P77
P77/AN7/SCK0/TMI2/OUT7_1/
INT23
P80
P80/AN8/IN0_1/TMI0_1
P81
P81/AN9/IN1_1/TMI1_1
P82
P82/AN10/IN2_1
P83
P83/AN11/IN3_1
During synchronous
write operation
INIT  “H”
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
Output Hi-Z
Output Hi-Z/
Input
disabled
Output Hi-Z/
Input
disabled
Output Hi-Z/
Input enabled
Output
Output
Output Hi-Z/
Input enabled
Output Hi-Z/
Input enabled
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Output Hi-Z/
Input
disabled
Output Hi-Z/
Input
disabled
Output Hi-Z
Output Hi-Z
(Continued)
56
DS07-16916-2E
MB91665 Series
(Continued)
Pin
name
Function
During
initialization
During
asynchronous
write operation
INIT  “L”
PH2
PH2/SCK2_1/INT2_1
PH3
PH3/INT3_1
PK0
PK0
PK1
PK1
UDP
UDP (USB)
UDM
DS07-16916-2E
UDM (USB)
During synchronous
write operation
INIT  “H”
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
Output Hi-Z
Output Hi-Z/
Input
enabled
Output Hi-Z/
Input
enabled
57
MB91665 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
1
Analog power supply voltage* , *
1
3
3
Analog reference voltage* , *
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current*4
Unit
Max
VCC
Vss  0.3
Vss  4.0
V
AVCC
Vss  0.3
Vss  4.0
V
AVRH
Vss  0.3
Vss  4.0
V
Vss  0.3
VCC + 0.3
(  4.0)
V
*7
Vss  0.3
Vss  6.0
V
5 V tolerant
Vss  0.5
VCC + 0.5
(  4.0)
V
USB I/O
Vss  0.3
Vss  4.0
V
Vss  0.3
Vcc  0.3
V
Vss  0.5
VCC + 0.5
(  4.0)
V
ICLAMP
4
4
mA
*8
|ICLAMP|

40
mA
*8

10
mA

43
mA

4
mA

15
mA
VIA
VO
IOL
“L” level average output current*5
IOLAV
“L” level total maximum
output current
IOL

100
mA
IOLAV

50
mA

 10
mA

 43
mA

4
mA

 15
mA
“L” level total average output current*6
“H” level maximum output current*4
IOH
“H” level average output current*5
IOHAV
“H” level total maximum output
current*6
IOH

 100
mA
IOHAV

 50
mA
Power consumption
PD

500
mW
Operating temperature
Ta
 40
 85
C
TSTG
 55
 125
C
“H” level total average output current
Storage temperature
Remarks
Min
VI
Analog pin input voltage*1
Rating
USB I/O
USB I/O
USB I/O
USB I/O
USB I/O
*1 : The parameter is based on VSS  AVSS  0.0 V.
*2 : VCC must not drop below VSS  0.3 V.
*3 : Be careful not to exceed VCC  0.3 V, for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output is the average current for a single pin over a period of 100 ms.
(Continued)
58
DS07-16916-2E
MB91665 Series
(Continued)
*6 : The total average output current is the average current for all pins over a period of 100 ms.
*7 : If the input current or the maximum input current are limited by some means with external components, the
ICLAMP rating supersedes the VI rating.
*8 :  Corresponding pins:P01, P03, P13 to P17,P50 to P57, P60, P61
 Use within recommended operating conditions.
 Use at DC voltage (current).
 The +B signal should always be applied by connecting a limiting resistor between the +B signal and the
microcontroller.
 The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the +B signal is input.
 Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
 Note that if the +B signal is input when the microcontroller is off (not fixed at 0V), since the power is supplied
through the pin, the microcontroller may operate incompletely.
 Do not leave +B input pins open.
 Sample recommended circuit
Input/output equivalent circuit
Protective diode
Vcc
Limiting ICLAMP
resistor
B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-16916-2E
59
MB91665 Series
2. Recommended Operating Conditions
(VSS  AVSS  0.0 V)
Parameter
Power supply voltage
Analog power supply voltage
Analog reference voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min
Max
2.7
3.6
V
Not using USB
3.0
3.6
V
Using USB
2.7
3.6
V
Not using USB
AVCC  VCC
3.0
3.6
V
Using USB
AVCC  VCC
AVRH
AVSS
AVCC
V
Ta
 40
 85
C
VCC
AVCC
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
60
DS07-16916-2E
MB91665 Series
3. DC Characteristics
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Pin name
Conditions
Value
Min

35
Max

VCC
45
Remarks
45
60
CPU : 32 MHz,
Peripheral :
mA
32 MHz,
Using USB*1, *3

10
20
Peripheral :
33 MHz,
mA
Not using
USB*1, *3

20
30
Peripheral :
mA 32 MHz
Using USB*1, *3
SLEEP
mode
ICCS
Unit
CPU : 33 MHz,
Peripheral :
mA 33 MHz,
Not using
USB*1, *3
Normal
operation
ICC
Power supply
current
Typ
ICCL
Sub
operation

100
300
A
CPU : 32 kHz,
Peripheral :
32 kHz*1, *2, *4
ICCT
Watch mode

70
200
A
*1, *2, *4
STOP mode

45
100
A
*1, *2
VIH
P00 to P07* ,
P10 to P17*6,
P22 to P27, P60*7
P72 to P77,
P80 to P83

VCC  0.7

Vcc 
0.3
V
VIL
P00 to P07*5,
P10 to P17*6,
P22 to P27, P60*7
P72 to P77,
P80 to P83

VSS  0.3

VCC  0.3
V
P00 to P07*8,
P10 to P17*9,
P50 to P57, P60*10,
P61, P70, P71,
P72 to P77,
P80 to P83,
PK0, PK1,
INIT, MD0, MD1

VCC  0.8

VCC  0.3
V
P20, P21, P22 to
P27,
PH2, PH3

VCC  0.8

VSS  5.5
V
ICCH
5
“H” level input
voltage
“L” level input
voltage
“H” level input
voltage
(hysteresis
input)
VIHS
5V
tolerant
(Continued)
DS07-16916-2E
61
MB91665 Series
(Continued)
Parameter
“L”level input
voltage
(hysteresis
input)
Symbol
Pin name
Conditions
VILS
P00 to P07*8,
P10 to P17*9,
P20, P21, P22 to P27,
P50 to P57, P60*10,
P61, P70, P71,
P72 to P77,
P80 to P83,
PH2, PH3,
PK0, PK1,
INIT, MD0, MD1

“H” level
output voltage
VOH
“L” level
output voltage
VOL
Input leak current
P00 to P07,
P10 to P17,
P20 to P27,
P50 to P57,
P60, P61,
P70 to P77,
P80 to P83,
PH2, PH3,
PK0, PK1
Value
Unit Remarks
Min
Typ
Max
Vss  0.3

VCC  0.2
V
VCC  3.0 V
IOH   4 VCC  0.5
mA

VCC
V
VCC  3.0 V
IOL  4 mA
VSS

0.4
V
5

5
A
Digital pin
 10

 10
A
Analog
pin
IIL


Pull-up
resistance
value
RPU
Pull-up pin

16.6
33
66
k
Input capacitance
CIN
Other than VCC, VSS,
AVCC, AVSS, AVRH


10
15
pF
*1 : When opened, all ports are fixed to output
*2 : Ta =  25 C and VCC = 3.3 V
*3 : X0 = 8.3 MHz, CPU clock = 33 MHz and X0A = when stopped
*4 : X0 = STOP and X0A = at 32 kHz
*5 : When using as D00 to D07 pin
*6 : When using as D08 to D15 pin
*7 : When using as RDY input
*8 : When using other than D00 to D07 pin
*9 : When using other than D08 to D15 pin
*10 : When using other than RDY input
62
DS07-16916-2E
MB91665 Series
 V-I characteristics
Conditions
Min : Process  Slow, Ta   85 C, VCC  2.7 V
Typ : Process  Typical, Ta   25 C, VCC  3.3 V
Max : Process  Fast, Ta   40 C, VCC  3.6 V
VOL - IOL
IOL [mA]
IOH [mA]
VOH - IOH
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
Typ
Max
Min
-0.5
-0.4
-0.3
-0.2
VOH-VCC [V]
DS07-16916-2E
-0.1
0
20
18
16
14
12
10
8
6
4
2
0
Typ
Max
Min
0
0.1
0.2
0.3
0.4
0.5
VOL [V]
63
MB91665 Series
4. AC Characteristics
(1) Main Clock (MCLK) Input Standard
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Input frequency
Input clock cycle
Symbol
Pin
name
Conditions
Value
Unit
Max

4
48
MHz
When crystal oscillator
is connected

4
48
MHz
When using external
clock

20.83
250
ns
When using external
clock
FCH
tCYLH
X0, X1
Remarks
Min
Input clock pulse width

PWH/tCYLH
PWL/tCYLH
45
55

When using external
clock
Input clock rise time
and fall time
tCF,
tCR


5
ns
When using external
clock
Internal operating
clock frequency
Internal operating
clock cycle time
64
FCS



33
MHz Source clock
FCC



33
MHz CPU clock
FCP



33
MHz Peripheral bus clock
FCT



33
MHz External bus clock
tCYCS


30

ns
Source clock
tCYCC


30

ns
CPU clock
tCYCP


30

ns
Peripheral bus clock
tCYCT


30

ns
External bus clock
DS07-16916-2E
MB91665 Series
 Operating guaranteed range (Not using USB)
Power supply voltage
Vcc (V)
• When the main clock is selected (DIVB=000)
3.6
3.3
3.0
2.7
2.4
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Internal operation clock Fcc (MHz)
• When the PLL clock is selected (DIVB=000)
Power supply voltage
Vcc (V)
3.6
3.3
3.0
2.7
2.4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Internal operation clock Fcc (MHz)
• When the sub clock is selected (FCL  32.768 kHz)
DIVB=111 DIVB=110 DIVB=101 DIVB=100 DIVB=011 DIVB=010 DIVB=001
DIVB=000
Power supply voltage
Vcc (V)
3.6
3.3
3.0
2.7
2.4
0
4
8
12
16
20
24
28
32
Internal operation clock Fcc (kHz)
DS07-16916-2E
65
MB91665 Series
 Example of configuration (Not using USB)
Internal operation clock
Fcc (MHz)
• When the main clock is selected (DIVB=000*1)
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
• When the PLL clock is selected (DIVB=000*1, PDS=0000*2)
PMS = 0111
PMS = 0110
PMS = 0101
PMS = 0100
PMS = 0011
PMS = 0010
PMS = 0001
34
Internal operation clock Fcc
(MHz)
32
ODS = 10
30
PMS = 0101
PMS = 0100
PMS = 0011
28
26
24
PMS = 0001
ODS = 11
22
PMS = 0010
20
18
16
14
12
10
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
• When the PLL clock is selected (DIVB=000*1, PDS=0001*2)
PMS=0111
PMS=0110
PMS=0101
PMS=0100
PMS=0011
PMS=0010
PMS=0001
Internal operation clock Fcc
(MHz)
34
32
ODS = 10
30
PMS=0101
PMS=0100
PMS=0011
28
26
24
ODS = 11
22
PMS=0001
PMS=0010
20
18
16
14
12
10
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
66
DS07-16916-2E
MB91665 Series
 Operating guaranteed range (at using USB)
• When the main clock is selected (DIVB  000*1)
Power supply voltage
Vcc (V)
3.6
3.3
3.0
2.7
2.4
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Internal operation clock Fcc (MHz)
• When the PLL clock is selected (DIVB  000*1, ODS  10*3, PMS  0111*4, PDS=0000*2, X0  4 MHz
or DIVB  000*1, ODS  10*3, PMS  0001*4, PDS  0010*2, X0  48 MHz)
Power supply voltage
Vcc (V)
3.6
3.3
3.0
2.7
2.4
0
4
8
12
16
20
24
28
32
Internal operation clock Fcc (MHz)
(Continued)
DS07-16916-2E
67
MB91665 Series
 Example of configuration (at using USB)
Internal operation clock
Fcc (MHz)
• When the main clock is selected (DIVB  000*1)
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
• When the PLL clock is selected (DIVB  000*1, ODS  10*3, PMS  0111*4, PDS  0000*2)
Internal operation clock
Fcc (MHz)
32
28
24
20
16
12
8
4
0
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
• When the PLL clock is selected (DIVB=000*1, ODS=10*3, PMS=0001*4, PDS=0010*2)
Internal operation clock
Fcc (MHz)
32
28
24
20
16
12
8
4
0
0
4
8
12
16
20
24
28
32
36
40
44
48
X0 input frequency (MHz)
(Continued)
68
DS07-16916-2E
MB91665 Series
(Continued)
*1: The values other than DIVB  000 are omitted.
*2: The values other than PDS  0000, 0001,0010 are omitted.
*3: The values other than ODS  10 are omitted.
*4: The values other than PMS  0001,0111 are omitted.
Note: DIVB: Base clock division configuration bit
ODS : PLL macro oscillation clock division rate select bit
PDS : PLL input clock division select bit
PMS : PLL clock multiple rate select bit
DS07-16916-2E
69
MB91665 Series
(2) Sub Clock (SBCLK) Input Standard
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Input frequency
Pin name Conditions
Value
Unit
Remarks

kHz
When crystal oscillator
is connected
32.768

kHz
When using external
clock

30.518

s
When using external
clock
Min
Typ
Max


32.768



FCL
X0A,
X1A
Input clock cycle
tCYLL
Input clock pulse
width

PWH / tCYLL
PWL / tCYLL
45

55
%
When using external
clock
Input clock rise
time and fall time
tCF,
tCR



200
ns
When using external
clock
<When external clock input>
tCYLH, tCYLL
X0
X0A
0.8 × VCC
0.8 × VCC
0.2 × VCC
PWH
0.2 × VCC
PWL
tCF
70
0.8 × VCC
tCR
DS07-16916-2E
MB91665 Series
(3) Conditions of PLL
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
PLL oscillation stabilization
wait time (LOCK UP time)
Value
Unit
Remarks

s
Time from when the PLL
starts operating until the
oscillation stabilizes

24
MHz
4

24
96

100
Min
Typ
Max
tLOCK
600

PLL input clock frequency
fPLLI
4
PLL multiple rate

fPLLO
PLL macro oscillation clock
frequency
multiplied
ODS  PMS
by
MHz
(4) Regulator Voltage Stabilization Wait Time
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Regulator voltage
stabilization wait time
Symbol
tREG
Value
Min
Max
50

Unit
Remarks
s
Time taken for the regulator
voltage to stabilize
Notes: • This is the time from when the external power supply stabilizes (after reaching 2.7 V) when USB is not used.
• This is the time from when the external power supply stabilizes (after reaching 3.0 V) when USB is used.
DS07-16916-2E
71
MB91665 Series
(5) Reset Input Standards
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Reset input time
(At power-on, main oscillation
stop mode)
Symbol Pin name
tINITX
Reset input rise time and fall
time
Unit
Min
Max
Oscillation time of
oscillator  10 tCYLH

ns
10 tCYLH

ns

10
ms

INIT
Reset input time
(At other times)
Value
Conditions
tINITXF,
tINITXR
Remarks
*
* : After the supply voltage has stabilized, it takes a further 50 s until the internal supply stabilizes. Hold the input
to the INIT pin during that period.
 At power-on
 When in stop mode
 When in sub mode and sub watch mode when the main oscillation is stopped.
tINITX
VIHS
VIHS
INIT
VILS
tINITXF
72
VILS
tINITXR
DS07-16916-2E
MB91665 Series
(6) Clock Output Timing
 tCHCL : tCLCH  1 : 1 (divided by 1, 2, 4, 6, 8)
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Cycle time
tCYC
SYSCLKSYSCLK
tCHCL
SYSCLKSYSCLK
tCLCH
Pin name
Conditions
SYSCLK*
FCT  FCC,
FCT  FCC/2
Value
Unit
Min
Max
tCYCT

ns
tCYC  2  5
tCYC  2  5
ns
tCYC  2  5
tCYC  2  5
ns
* : This pin is not existed in MB91F668.
Notes: • tCYC is a frequency of 1 clock cycle indicating gear ratio.
• When DIVT  000, be sure to set as DIVB  000.
 tCHCL : tCLCH  1 : 2 (divided by 3)
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Cycle time
tCYC
SYSCLKSYSCLK
tCHCL
SYSCLKSYSCLK
tCLCH
Pin name
Conditions
SYSCLK*
FCT  FCC,
FCT  FCC/2
Value
Unit
Min
Max
tCYCT

ns
1  3 tCYC  5
1  3 tCYC  5
ns
2  3 tCYC  5
2  3 tCYC  5
ns
* : This pin is not existed in MB91F668.
Note : tCYC is a frequency of 1 clock cycle indicating gear ratio.
 tCHCL : tCLCH  2 : 3 (divided by 5)
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Cycle time
tCYC
SYSCLKSYSCLK
tCHCL
SYSCLKSYSCLK
tCLCH
Pin name
Conditions
SYSCLK*
FCT  FCC,
FCT  FCC/2
Value
Unit
Min
Max
tCYCT

ns
2  5 tCYC  5
2  5 tCYC  5
ns
3  5 tCYC  5
3  5 tCYC  5
ns
* : This pin is not existed in MB91F668.
Note : tCYC is a frequency of 1 clock cycle indicating gear ratio.
DS07-16916-2E
73
MB91665 Series
 tCHCL : tCLCH  3 : 4 (divided by 7)
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Cycle time
tCYC
SYSCLKSYSCLK
tCHCL
SYSCLKSYSCLK
tCLCH
Pin name
Conditions
SYSCLK*
FCT  FCC,
FCT  FCC/2
Value
Unit
Min
Max
tCYCT

ns
3  7 tCYC  5
3  7 tCYC  5
ns
4  7 tCYC  5
4  7 tCYC  5
ns
* : This pin is not existed in MB91F668.
Note: tCYC is a frequency of 1 clock cycle indicating gear ratio.
tCYC
tCHCL
tCLCH
VOH
VOH
SYSCLK
VOL
74
DS07-16916-2E
MB91665 Series
(7) External Bus Access Read/Write Operation
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
Pin name
tCHASL
Conditions
Value
Unit Remarks
Min
Max
SYSCLK*2,
AS
0.6
10
ns
SYSCLK*2,
CS0 to CS3*2
0.6
10
ns
SYSCLK*2,
A23 to A00
0.6
10
ns
tCHRH
SYSCLK*2,
RD
0.6
10
ns
RD minimum pulse width
tRLRH
RD
tCYC  10

ns
Data setup  RD time
tDSRH
18

ns
RD data hold time
tRHDH
RD,
D15 to D00
0

ns
tCHWH
SYSCLK*2,
WR0, WR1*2
0.6
10
ns
WR0, WR1 minimum pulse
width
tWLWH
WR0, WR1*2
tCYC  10

ns
SYSCLK Data output time
tCHDV
0.6
15
ns
SYSCLK Data hold time
tCHDX
SYSCLK*2,
D15 to D00
0.6
15
ns
AS delay time
CS0 to CS3 delay time
Address delay time
RD delay time
WR0, WR1 delay time
tCHASH
tCHCSL
tCHCSH
tCHAV
tCHAX
tCHRL
tCHWL

*1
*1
*1 : When the bus timing is delayed by an automatic wait insertion or RDY input, add the time (tCYC  the number
of delay cycles added) to this rating.
*2 : This pin is not existed in MB91F668.
Note: When the external load capacitance C = 50 pF.
DS07-16916-2E
75
MB91665 Series
t2
t1
t3
tCYC
VOH
VOH
VOH
VOH
SYSCLK
tCHASL
tCHASH
VOH
AS
VOL
tCHCSH
tCHCSL
CS0 to CS3
VOH
VOL
tCHAX
tCHAV
VOH
VOH
A23 to A00
VOL
VOL
tCHRL
tCHRH
tRLRH
VOL
RD
VOH
tDSRH
tRHDH
VIH
D15 to D00
VIH
Read
VIL
tCHWL
VIL
tCHWH
tWLWH
WR0,WR1
VOL
VOH
VOH
VOH
D15 to D00
Write
VOL
VOL
tCHDV
76
tCHDX
DS07-16916-2E
MB91665 Series
(8) Multiplexed Bus Access Read/Write Operation
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
SYSCLK  D15 to D00
address delay time
tCHMAV,
tCHMAX
SYSCLK  D15 to D00
data delay time
tCHMDV
Pin name
SYSCLK*,
D15 to D00
(address)
Conditions
Value
Unit
Min
Max
0.6
15
ns
0.6
15
ns

*: This pin is not existed in MB91F668.
Notes: • The ratings not listed here are the same as the normal bus interface.
• When the external load capacitance C = 50 pF.
tCYC
SYSCLK
AS
tCHMAV
D15 to D00
DS07-16916-2E
Address
tCHMDV
tCHMAX
Write data
77
MB91665 Series
(9) Ready Input Timing (MB91F669 only)
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
RDY setup time  SYSCLK
SYSCLK RDY hold time
Symbol
Pin name
tRDYS
SYSCLK,
RDY
tRDYH
SYSCLK,
RDY
Value
Conditions
Unit
Min
Max
18

ns
0

ns

tCYC
VOH
SYSCLK
VOH
VOL
VOL
tRDYS tRDYH
tRDYS tRDYH
RDY
(wait applied)
VIH
VIL
RDY
(wait not applied)
VIH
VIH
VIL
78
VIH
VIL
VIL
DS07-16916-2E
MB91665 Series
(10) Base Timer Input Timing
 Timer input timing
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Input pulse width
Pin name
Conditions
Min
Max
tTIWH,
tTIWL
TIOAn/TIOBn
(When used as ECK, TIN)

2 tCYCP

tTIWH
ECK
VIHS
Parameter
Input pulse width
VILS
VILS
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Value
Symbol
Pin name
Conditions
Min
Max
tTRGH,
tTRGL
TIOAn/TIOBn
(When used as TGIN)

2 tCYCP

VIHS
DS07-16916-2E
ns
VIHS
tTRGH
TGIN
Unit
tTIWL
TIN
 Trigger Input Timing
Value
Symbol
Unit
ns
tTRGL
VIHS
VILS
VILS
79
MB91665 Series
(11) Synchronous serial (CSIO) timing
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
 Synchronous serial (SPI  0, SCINV  0)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKn
SCK   SOUT delay time
tSLOVI
SCKn,
SOUTn
Internal shift clock
operation
4tCYCP

ns
 30
 30
ns
57

ns
SIN  SCK  setup time
tIVSHI
SCKn,
SINn
SCK   SIN hold time
tSHIXI
SCKn,
SINn
0

ns
Serial clock “L” pulse width
tSLSH
SCKn
2tCYCP  10

ns
Serial clock “H” pulse width
tSHSL
SCKn
tCYCP  10

ns
SCK   SOUT delay time
tSLOVE
SCKn,
SOUTn

48
ns
SIN  SCK  setup time
tIVSHE
SCKn,
SINn
25

ns
SCK   SIN hold time
tSHIXE
SCKn,
SINn
20

ns
SCK fall time
tF
SCKn

5
ns
SCK rise time
tR
SCKn

5
ns
External shift clock
operation
Notes: • The above standards apply to CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
• When the external load capacitance C = 50 pF.
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
SOUT
VOL
tIVSHI
tSHIXI
VIHS
VIHS
VILS
VILS
SIN
MS bit  0
80
DS07-16916-2E
MB91665 Series
tSLSH
tSHSL
VIHS
SCK
tF
VIHS
VILS
VILS
VIHS
tR
tSLOVE
VOH
SOUT
VOL
tIVSHE
tSHIXE
VIHS
VIHS
VILS
VILS
SIN
MS bit  1
 Synchronous serial (SPI  0, SCINV  1)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK  SOUT delay time
Conditions
Value
Unit
Min
Max
SCKn
4tCYCP

ns
tSHOVI
SCKn,
SOUTn
 30
 30
ns
SIN  SCK  setup time
tIVSLI
SCKn,
SINn
57

ns
SCK   SIN hold time
tSLIXI
SCKn,
SINn
0

ns
Serial clock “L” pulse width
tSLSH
SCKn
2tCYCP  10

ns
Serial clock “H” pulse width
tSHSL
SCKn
tCYCP  10

ns
SCK   SOUT delay time
tSHOVE
SCKn,
SOUTn

48
ns
SIN  SCK  setup time
tIVSLE
SCKn,
SINn
25

ns
SCK   SIN hold time
tSLIXE
SCKn,
SINn
20

ns
SCK fall time
tF
SCKn

5
ns
SCK rise time
tR
SCKn

5
ns
Internal shift clock
operation
External shift clock
operation
Notes: • The above standards apply to CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
• When the external load capacitance C = 50 pF.
DS07-16916-2E
81
MB91665 Series
tSCYC
VOH
VOH
VOL
SCK
tSHOVI
VOH
SOUT
VOL
tIVSLI
SIN
tSLIXI
VIHS
VIHS
VILS
VILS
MS bit  0
tSHSL
VIHS
SCK
tSLSH
VIHS
VILS
VILS
VILS
tF
tR
tSHOVE
VOH
SOUT
VOL
tIVSLE
SIN
tSLIXE
VIHS
VIHS
VILS
VILS
MS bit  1
82
DS07-16916-2E
MB91665 Series
 Synchronous serial (SPI  1,SCINV  0)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK  SOUT delay time
Value
Conditions
Unit
Min
Max
SCKn
4tCYCP

ns
tSHOVI
SCKn,
SOUTn
 30
 30
ns
SIN  SCK  setup time
tIVSLI
SCKn,
SINn
57

ns
SCK   SIN hold time
tSLIXI
SCKn,
SINn
0

ns
SOUT  SCK  delay time
tSOVLI
SCKn,
SOUTn
2tCYCP  30

ns
Serial clock “L” pulse width
tSLSH
SCKn
2tCYCP  10

ns
Serial clock “H” pulse width
tSHSL
SCKn
tCYCP  10

ns
SCK   SOUT delay time
tSHOVE
SCKn,
SOUTn

48
ns
SIN  SCK  setup time
tIVSLE
SCKn,
SINn
25

ns
SCK   SIN hold time
tSLIXE
SCKn,
SINn
20

ns
SCK fall time
tF
SCKn

5
ns
SCK rise time
tR
SCKn

5
ns
Internal shift clock
operation
External shift clock
operation
Notes: • The above standards apply to CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
• When the external load capacitance C = 50 pF.
tSCYC
VOH
SCK
VOL
tSHOVI
VOL
tSOVLI
SOUT
VOH
VOL
VOH
VOL
tIVSLI
SIN
tSLIXI
VIHS
VILS
VIHS
VILS
MS bit  0
DS07-16916-2E
83
MB91665 Series
tSHSL
tSLSH
VIHS
SCK
VILS
tSHOVE
tR
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIHS
VILS
tF
*
SOUT
VIHS
VILS
tSLIXE
VIHS
VILS
VIHS
VILS
MS bit  1
* : Changes when writing to TDR register
 Synchronous serial (SPI  1, SCINV  1)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK   SOUT delay time
Conditions
Value
Unit
Min
Max
SCKn
4tCYCP

ns
tSLOVI
SCKn,
SOUTn
 30
 30
ns
SIN  SCK  setup time
tIVSHI
SCKn,
SINn
57

ns
SCK   SIN hold time
tSHIXI
SCKn,
SINn
0

ns
SOUT  SCK  delay time
tSOVHI
SCKn,
SOUTn
2tCYCP  30

ns
Serial clock “L” pulse width
tSLSH
SCKn
2tCYCP  10

ns
Serial clock “H” pulse width
tSHSL
SCKn
tCYCP  10

ns
SCK   SOUT delay time
tSLOVE
SCKn,
SOUTn

48
ns
SIN  SCK  setup time
tIVSHE
SCKn,
SINn
25

ns
SCK   SIN hold time
tSHIXE
SCKn,
SINn
20

ns
SCK fall time
tF
SCKn

5
ns
SCK rise time
tR
SCKn

5
ns
Internal shift clock
operation
External shift clock
operation
Notes: • The above standards apply to CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
• When the external load capacitance C = 50 pF.
84
DS07-16916-2E
MB91665 Series
tSCYC
VOH
SCK
VOH
VOL
tSLOVI
tSOVHI
VOH
VOL
VOH
VOL
SOUT
tIVSHI
tSHIXI
VIHS
VILS
SIN
VIHS
VILS
MS bit  0
tSHSL
tR
tSLSH
VIHS
SCK
VIHS
VILS
tSLOVE
VILS
VIHS
VILS
VOH
VOL
VOH
VOL
SOUT
tIVSHE
tSHIXE
VIHS
VILS
SIN
tF
VIHS
VILS
MS bit  1
 External clock (EXT  1) : asynchronous only
Parameter
Symbol
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
SCK fall time
tF
SCK rise time
tR
VIHS
VILS
DS07-16916-2E
CL  50 pF
tSHSL
tR
SCK
Conditions
Value
Max
tCYCP  10

ns
tCYCP  10

ns

5
ns

5
ns
tSLSH
VIHS
VILS
Unit
Min
tF
VIHS
VILS
85
MB91665 Series
(12) Free-run Timer Clock, Reload Timer Event Input, Up/down Counter Input, Input Capture Input, Interrupt
Input Timing
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Symbol
tTIWH,
tTIWL
Input pulse width
Value
Pin name
Conditions
Min
Max
FRCKn,
TMIn,
INn,
AINn,
BINn,
ZINn

2 tCYCP

ns
*1

3 tCYCP

ns
*1

1.0

s
*2
INTn
Unit
Remarks
*1 : tCYCP indicates peripheral clock cycle time, except when in stop mode, in main timer mode and in watch mode.
*2 : When in stop mode, in main timer mode, or in watch mode.
FRCKn
TMIn
INn
AINn
BINn
ZINn
INTn
tTIWH
tTIWL
VIHS
VILS
VIHS
VILS
(13) A/D Converter Trigger Input Timing
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Value
Parameter
Symbol
Pin name
Conditions
Min
Max
A/D converter trigger
input
tTADTGL,
tTADTGH
ADTRGn

2 tCYCP

Unit
ns
Remarks
*
* : tCYCP indicates peripheral clock cycle time.
tTADTGL
tTADTGH
ADTRGn
VIHS
VILS
86
VIHS
VILS
DS07-16916-2E
MB91665 Series
(14) I2C Timing
Parameter
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Symbol Pin name
Conditions
Typical mode
High-speed mode*3
Min
Max
Min
Max
Unit
fSCL
SCKn
(SCLn)
0
100
0
400
kHz
“(Repeated) START
condition” hold time
SDA   SCL 
tHDSTA
SOUTn
(SDAn) ,
SCKn
(SCLn)
4.0

0.6

s
SCL clock “L” width
tLOW
SCKn
(SCLn)
4.7

1.3

s
SCL clock “H” width
tHIGH
SCKn
(SCLn)
4.0

0.6

s
“Repeated START
condition” setup time
SCL  SDA 
tSUSTA
SCKn
(SCLn)
4.7

0.6

s
Data hold time
SCL   SDA  
tHDDAT
0
3.45*2
0
0.9*3
s
tSUDAT
SOUTn
(SDAn) ,
SCKn
(SCLn)
250

100

ns
“STOP condition” setup
time
SCL SDA
tSUSTO
SOUTn
(SDAn) ,
SCKn
(SCLn)
4.0

0.6

s
Bus free time between
“STOP condition” and
“START condition”
tBUF

4.7

1.3

s
Noise filter
tSP

2 tCYCP *4

2 tCYCP *4

ns
SCL clock frequency
Data setup time
SDA   SCL
CL  50 pF,
SOUTn R 
(SDAn) , (Vp/IOL) *1
SCKn
(SCLn)

*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least “L” period (tLOW) of device's SCL signal.
*3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of “tSUDAT  250 ns”.
*4 : tCYCP is the peripheral clock cycle time. To use I2C, set the peripheral bus clock at 8 MHz or more.
DS07-16916-2E
87
MB91665 Series
SDA
tSUSTA
tLOW
tSUDAT
tBUF
SCL
tHDSTA
88
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
DS07-16916-2E
MB91665 Series
5. Electrical Characteristics for the A/D Converter
Not using USB : (VCC  AVCC  2.7 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Using USB : (VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Value
Pin name
Min
Typ
Max
Unit
Remarks
Resolution



10
bit
Total error

5

5
LSB
Linearity error

 3.5

 3.5
LSB
Differential linearity error

3

3
LSB
Zero transition voltage
AN0 to AN11*4
 1.5
 0.5
4
LSB
Full transition voltage
AN0 to AN11*4
AVRH  4
Compare time

0.72*3


s
PCLK  33 MHz
Conversion time

1.2*1


s
PCLK  33 MHz


3.5
mA D/A stopped


11
A


0.6
mA AVRH  3.0 V


5
A


8.5
pF
Power supply current
(analog  digital)
AVCC
Reference power
supply current
(between AVRH and
AVSS)
AVRH
Analog input capacity

Interchannel disparity

Analog input voltage
Standard voltage
AN0 to AN11*
AVRH
AVRH  1.5 AVRH  0.5 LSB


4
LSB
4


10
A
4
AVSS

AVRH
V
AVSS

AVCC
V
Analog port input current AN0 to AN11*
AVCC  3.3 V,
AVRH  3.3 V
At power-down*2
At power-down*2
*1 : Depending on the clock cycle supplied to peripheral resources.
Ensure that it satisfies the value; PCLK cycle  more than 4 + the value calculated from (Equation 1).
The condition of the minimum conversion time is when PCLK  33 MHz, the value of sampling time: 0.424 s,
external impedance: 1.4 k or less and compare time: 0.72 s.
(Continued)
DS07-16916-2E
89
MB91665 Series
(Continued)
*2 : The current when the CPU is in stop mode and the A/D converter is not operating.
*3 : Compare time = {(CT  1)  10  4}  peripheral clock (PCLK) period. (CT indicates compare time setting bits.)
The condition of the minimum compare time is when CT  1 and PCLK  33 MHz.
*4 : There are no AN10 and AN11 in MB91F668.
Rext
AN0 to AN11
Analog input pin
Rin
Comparator
Analog
signal source
Cin
Rin
Cin
Approx. 5.3 k
Approx. 8.5 pF
The output impedance of the external circuit connected to the analog input affects the sampling time of the A/D
converter. Design the output impedance of the output circuit such that the required sampling time is less than the
value of TS calculated from the following equation.
(Equation 1) Ts  (Rin  Rext)  Cin  7
Ts
: Sampling time
Rin
: Input resistance of A/D  5.3 k
Cin
: Input capacitance of A/D  8.5 pF
Rext : Output impedance of external circuit
If the sampling time is set as 600 ns,
600 ns  (5.3 k  Rext)  8.5 pF  7
Rext  4.8 k
And the impedance of the external circuit therefore needs to be 4.8 k or less.
90
DS07-16916-2E
MB91665 Series
 Definition of 10-bit A/D Converter Terms
• Resolution
• Linearity error
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(00000000000000000001) and the full-scale transition point
(11111111101111111111) from the actual conversion characteristics.
• Differential linearity error : Deviation from the ideal value of the input voltage that is required to change the
output code by 1 LSB.
• Total error
: Difference between the actual value and the theoretical value. The total error includes
zero transition error, full-scale transition error, and linear error.
Linearity error
3FFH
Differential linearity error
Actual conversion
characteristics
Actual conversion
characteristics
(N + 1)H
3FEH
{1 LSB (N − 1) + V OT}
VFST
Ideal characteristics
(Actuallymeasured
value)
VNT
004H
(Actually-measured
value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
VOT
AVSS
Digital output
Digital output
3FDH
NH
(N − 1)H
VNT
(N − 2)H
(Actually-measured value)
Analog input
V(N+1)T
AVRH
(Actually-measured
value)
(Actually-measured
value)
Actual conversion characteristics
AVSS
AVRH
Analog input
VNT  {1 LSB  (N  1)  VOT}
[LSB]
1 LSB’
V (N1) T  VNT
 1 [LSB]
Differential linearity error of digital output N 
1 LSB
VFST  VOT
1 LSB 
1022
Linearity error of digital output N 
N
VOT
VFST
VNT
: A/D converter digital output value.
: Voltage at which the digital output changes from 000H to 001H.
: Voltage at which the digital output changes from 3FEH to 3FFH.
: Voltage at which the digital output changes from (N  1)H to NH.
(Continued)
DS07-16916-2E
91
MB91665 Series
(Continued)
Total error
3FFH
1.5 LSB'
3FEH
Actual conversion
characteristics
3FDH
Digital output
{1 LSB' (N − 1) + 0.5 LSB'}
004H
VNT
(Actually-measured value)
Actual conversion
characteristics
003H
002H
001H
Ideal
characteristics
0.5 LSB'
AVSS
Analog input
1 LSB' (Ideal value)
Total error of digital output N
AVRH
AVRH  AVSS
[V]
1024
VNT  {1 LSB'  (N  1)  0.5 LSB'}

1 LSB'

N : A/D converter digital output value.
VNT : Voltage at which the digital output changes from (N  1)H to NH.
VOT’ (Ideal value)  AVSS  0.5 LSB [V]
VFST’ (Ideal value)  AVRH  1.5 LSB [V]
92
DS07-16916-2E
MB91665 Series
6. USB Characteristics
(VCC  AVCC  3.0 V to 3.6 V, VSS  AVSS  0 V, Ta   40 C to  85 C)
Parameter
Input High level
voltage
Pin
name
Conditions
Value
Min
Max
Unit
Remarks
VIH

2.0
VCC  0.3
V
*1
VIL

VSS  0.3
0.8
V
*1
VDI

0.2

V
*2
VCM

0.8
2.5
V
*2
VOH
External
pull-down
resistance 
15 k
2.8
3.6
V
*3
VOL
External
pull-up
resistance 
1.5 k
0.0
0.3
V
*3
VCRS

1.3
2.0
V
*4
Rise time
tFR

4
20
nS
*5
Fall time
tFF

4
20
nS
*5
Rise/fall
time matching
tRFM

90
111.11

*5
Output impedance
ZDRV

28
44

Including
Rs  27 
Transceiver edge
rate control
capacitance
CEDGE


75
pF
*6
RS

25
30

Recommended
value:27 
Input Low level
voltage
Input
characteristics Differential input
sensitivity
Differential common
mode input voltage
Output High level
voltage
Output Low level
voltage
Output
characteristics Crossover voltage
Input
capacitance
Symbol
Series resistance
UDP,
UDM
*1 : The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max)  0.8 [V],
VIH (Min)  2.0 [V] (TTL input standard).
There are some hystereses to lower noise sensitivity.
(Continued)
DS07-16916-2E
93
MB91665 Series
*2 : Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 [mV] of differential input sensitivity when the differential data input is within 0.8 [V]
to 2.5 [V] to the local ground reference level.
Above voltage range is the common mode input voltage range.
Minimum differential input sensitivity [V]
1.0 [V]
0.2 [V]
0.8 [V]
2.5 [V]
Common mode input voltage [V]
*3 : The output drive capability of the driver is below 0.3 [V] at Low-State (VOL) (to 3.6 [V] and 1.5 k load), and
2.8 [V] or above (to the VSS and 15 k load) at High-State (VOH).
*4 : The cross voltage of the external differential output signal (D  /D  ) of USB I/O buffer is within 1.3 [V] to 2.0 [V].
D+
Max 2.0 [V]
VCRS standard range
Min 1.3 [V]
D-
*5 : Regarding tFR, tFF, tRFM
They indicate rise time (Trise) and fall time (Tfall) of the differential data signal.
They are defined by the time between 10 to 90 of the output signal voltage.
For full-speed buffer, tFR/tFF ratio is regulated as within 10 to minimize RFI emission.
Rise time
UDP
UDM
VCRS
90%
Fall time
90%
10%
10%
tFR
tFF
(Continued)
94
DS07-16916-2E
MB91665 Series
(Continued)
*6 : The place to connect transceiver edge rate control capacitance CEDGE
For this USB I/O, it is recommended to use CEDGE control capacitor.
For USB Max standard as 75 pF, please control the edge characteristic of output waveform by connecting 30 to
50 [pF] (recommended value : 47 [pF] =: 50[pF]) to D  and D  lines when implementing on the board.
RS = 27 Ω
+D
CEDGE
3-State
RS = 27 Ω
-D
CEDGE
Driver output impedance 3  to 19 
Rs serial resistance value 25  to 30 
Please apply 27  of serial resistance value as a recommended value.
DS07-16916-2E
95
MB91665 Series
7. Flash Memory Write/Erase Characteristics
(VCC  3.3 V, Ta   25 C)
Parameter
Value
Unit
Remarks
3.6
s
Excludes write time prior to internal erase
23
370
s
Not including system-level overhead time.

10.8
43.2
s
Excludes write time prior to internal erase
10000


cycle Average Ta   85 C
10*2


year
Min
Typ
Max
Sector erase time

0.9
Half word (16bits) write time

1
Chip erase time*
Erase/write cycles
Flash memory
data hold time
Average Ta   85 C
*1 : The chip erase time is the sector erase time multiplied across all sectors.
*2 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at  85 C) .
96
DS07-16916-2E
MB91665 Series
■ ORDERING INFORMATION
Part number
Package
MB91F669PMC
64-pin plastic LQFP
(FPT-64P-M24)
MB91F668PMC
48-pin plastic LQFP
(FPT-48P-M26)
DS07-16916-2E
97
MB91665 Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 mm × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0°~8°
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F48040S-c-2-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
98
DS07-16916-2E
MB91665 Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 mm × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
Details of "A" part
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
0.15(.006)
MAX
0.40(.016)
MAX
32
0.08(.003)
Details of "B" part
11.00(.433)
NOM.
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
"A"
64
LEAD No.
1
"B"
16
0.50(.020)
C
0~8°
17
0.20±0.05
(.008±.002)
0.08(.003)
M
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16916-2E
99
MB91665 Series
■ MAIN CHANGES IN THIS EDITION
Page
4
Section
■ FEATURES
Changed the explanation of “USB function / HOST”.
(Supports Full-Speed only  USB2.0 Full-Speed supported)
■ I/O MAP
Corrected “Initial value after reset”.
(ADCHE: -------- -------- ----1111 11111111
-------- 111111-- ----1111 11111111)"
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Changed “Value” for “Power supply current”.
34
61
Change Results
The vertical lines marked in the left side of the page show the changes.
100
DS07-16916-2E
MB91665 Series
MEMO
DS07-16916-2E
101
MB91665 Series
MEMO
102
DS07-16916-2E
MB91665 Series
MEMO
DS07-16916-2E
103
MB91665 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
Similar pages