3.4 MB

The following document contains information on Cypress products.
MB9A310A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF311LA/MA/NA, MB9AF312LA/MA/NA,
MB9AF314LA/MA/NA, MB9AF315MA/NA, MB9AF316MA/NA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A310A-DS706-00012
CONFIDENTIAL
Revision 3.0
Issue Date December 26, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9A310A-DS706-00012-3v0-E, December 26, 2014
CONFIDENTIAL
MB9A310A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF311LA/MA/NA, MB9AF312LA/MA/NA,
MB9AF314LA/MA/NA, MB9AF315MA/NA, MB9AF316MA/NA
Data Sheet (Full Production)
 DESCRIPTION
The MB9A310A Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9A310A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (USB,
UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE1 product categories in " FM3
Family PERIPHERAL MANUAL ".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9A310A-DS706-00012
Revision 3.0
Issue Date December 16, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 FEATURES
 32-bit ARM Cortex-M3 Core
 Processor version: r2p1
 Up to 40MHz Frequency Operation
 Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
 24-bit System timer (Sys Tick): System timer for OS task management
 On-chip Memories
[Flash memory]
 Up to 512 Kbyte
 Read cycle: 0wait-cycle
 Security function for code protection
[SRAM]
This Series contain a total of up to 32Kbyte on-chip SRAM. On-chip SRAM is composed of two
independent SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3
core. SRAM1 is connected to System bus.
 SRAM0: Up to 16 Kbytes
 SRAM1: Up to 16 Kbytes
 USB Interface
USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
 EndPoint 0 is control transfer
 EndPoint 1,2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
 EndPoint 3,4 and 5 can be selected Bulk-transfer, Interrupt-transfer
 EndPoint1-5 is comprised Double Buffer
EndPoint 0, 2 to 5:64 bytes
EndPoint 1: 256 bytes
[USB host]
 USB2.0 Full/Low speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer support
 USB Device connected/dis-connected automatically detect
 IN/OUT token handshake packet automatically
 Max 256-byte packet-length supported
 Wake-up function supported
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D a t a S h e e t
 Multi-function Serial Interface (Max 8channels)
 4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
 Operation mode is selectable from the followings for each channel.
 UART
 CSIO
 LIN
 I2C
[UART]
 Full-duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*
 Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AF311LA, F312LA and F314LA do not support Hardware Flow control
[CSIO]
 Full-duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detection function available
[LIN]
 LIN protocol Rev.2.1 supported
 Full-duplex double buffer
 Master/Slave mode supported
 LIN break field generation (can be changed 13-16bit length)
 LIN break delimiter generation (can be changed 1-4bit length)
 Various error detection functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard-mode (Max 100kbps) / Fast-mode (Max 400Kbps) supported
 External Bus Interface*







Supports SRAM, NOR Flash device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
* : MB9AF311LA, F312LA and F314LA do not support External Bus Interface
 DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.







8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32bit(4Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
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CONFIDENTIAL
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D a t a S h e e t
 A/D Converter (Max 16channels)
[12-bit A/D Converter]
 Successive Approximation type
 Built-in 3units*
 Conversion time: [email protected]
 Priority conversion available (priority at 2levels)
 Scanning conversion mode
 Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
* : MB9AF311LA, F312LA, F314LA built-in 2units
 Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.




16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
 Multi-function Timer (Max 2units)
The Multi-function timer is composed of the following blocks.






16-bit free-run timer × 3ch/unit
Input capture × 4ch/unit
Output compare × 6ch/unit
A/D activation compare × 3ch/unit
Waveform generator × 3ch/unit
16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor control.






PWM signal output function
DC chopper waveform output function
Dead timer function
Input capture function
A/D converter activate function
DTIF (Motor emergency stop) interrupt function
 Quadrature Position/Revolution Counter (QPRC) (Max 2units)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.




The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
 Dual Timer (32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each timer channel.
 Free-running
 Periodic (=Reload)
 One-shot
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D a t a S h e e t
 Watch Counter
The Watch counter is used for wake up from Low-Power Consumption mode.
 Interval timer: up to 64s(Max)@ Sub Clock : 32.768kHz
 Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a, "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except STOP mode.
 External Interrupt Controller Unit
 Up to 16 external interrupt input pins.
 Include one non-maskable interrupt (NMI) input pin.
 General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.





Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast General Purpose I/O Ports @ 100pin Package
Some ports are 5V tolerant I/O (MB9AF315MA/NA, MB9AF316MA/NA only)
Please see "PIN DESCRIPTION" to confirm the corresponding pins.
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
 Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
 Main Clock
: 4MHz to 48MHz
 Sub Clock
: 32.768kHz
 Built-in high-speed CR Clock : 4MHz
 Built-in low-speed CR Clock : 100kHz
 Main PLL Clock
[Resets]
 Reset requests from INITX pins
 Power-on reset
 Software reset
 Watchdog timers reset
 Low-voltage detector reset
 Clock supervisor reset
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CONFIDENTIAL
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 Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
 External clock failure (clock stop) is detected, reset is asserted.
 External frequency anomaly is detected, interrupt or reset is asserted.
 Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage
that has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
 SLEEP
 TIMER
 STOP
 Debug
 Serial Wire JTAG Debug Port (SWJ-DP)
 Embedded Trace Macrocells (ETM).*
*: MB9AF311LA/MA, F312LA/MA, F314LA/MA, F315MA and F316MA support only SWJ-DP.
 Power Supply
 Two Power Supplies
 VCC
= 2.7V to 5.5V: Correspond to the wide range voltage.
 USBVCC = 3.0V to 3.6V: for USB I/O power supply, when USB is used.
= 2.7V to 5.5V: when GPIO is used.
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CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 PRODUCT LINEUP
 Memory size
Product name
MB9AF311LA/MA/NA MB9AF312LA/MA/NA MB9AF314LA/MA/NA
On-chip Flash memory
On-chip SRAM
Product name
64Kbytes
16Kbytes
128Kbytes
16Kbytes
MB9AF315MA/NA
MB9AF316MA/NA
384Kbytes
32Kbytes
512Kbytes
32Kbytes
On-chip Flash memory
On-chip SRAM
256Kbytes
32Kbytes
 Function
Product name
MB9AF311LA
MB9AF312LA
MB9AF314LA
Pin count
64
CPU
Freq.
Power supply voltage range
USB2.0 interface (Function/Host)
DMAC
External Bus Interface
-
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
A/D
activation
3ch.
compare
Input
4ch.
capture
Free-run
MF3ch.
Timer timer
Output
6ch.
compare
Waveform
3ch.
generator
PPG
3ch.
QPRC
Dual Timer
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
MB9AF311NA
MB9AF312NA
MB9AF314NA
MB9AF315NA
MB9AF316NA
80
100
Cortex-M3
40MHz
2.7V to 5.5V
1ch.
8ch.
Addr:21-bit (Max)
Addr:25-bit (Max)
Data:8-bit
Data:8/16-bit
CS:4 (Max)
CS:8 (Max)
Support: SRAM, NOR Support: SRAM, NOR
Flash
Flash
8ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
8ch. (Max)
1 unit
2 units (Max)
2ch. (Max)
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
8pins (Max)+ NMI × 1 11pins (Max)+ NMI × 1 16pins (Max)+ NMI × 1
51pins (Max)
66pins (Max)
83pins (Max)
9ch. (2 units)
12ch. (3 units)
16ch. (3 units)
Yes
2ch.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
MB9AF311MA
MB9AF312MA
MB9AF314MA
MB9AF315MA
MB9AF316MA
7
D a t a S h e e t
Product name
MB9AF311LA
MB9AF312LA
MB9AF314LA
MB9AF311MA
MB9AF312MA
MB9AF314MA
MB9AF315MA
MB9AF316MA
MB9AF311NA
MB9AF312NA
MB9AF314NA
MB9AF315NA
MB9AF316NA
High-speed
4MHz
Built-in
CR
Low-speed
100kHz
Debug Function
SWJ-DP
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation
Characteristics" for accuracy of built-in CR.
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CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 PACKAGES
Package
MB9AF311LA
Product name
MB9AF312LA
MB9AF314LA
LQFP:FPT-64P-M38 (0.5mm pitch)
LQFP:FPT-64P-M39 (0.65mm pitch)
QFN:LCC-64P-M24 (0.5mm pitch)
LQFP:FPT-80P-M37 (0.5mm pitch)
LQFP:FPT-100P-M23 (0.5mm pitch)
QFP:FPT-100P-M06 (0.65mm pitch)
BGA:BGA-112P-M04 (0.8mm pitch)

*



-
MB9AF311MA
MB9AF312MA
MB9AF314MA
MB9AF315MA
MB9AF316MA

-
MB9AF311NA
MB9AF312NA
MB9AF314NA
MB9AF315NA
MB9AF316NA


*
: Supported
: MB9AF315NA, MB9AF316NA are planning
Note: Refer to "PACKAGE DIMENSIONS" for detailed information on each package.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
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D a t a S h e e t
 PIN ASSIGNMENT
 FPT-100P-M23
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1
P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1
P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
2
74
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
3
73
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
4
72
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
5
71
P23/SCK0_0/TIOA7_1/RTO00_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
6
70
P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
7
69
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
P56/INT08_2/DTTI1X_0/MADATA06_1
8
68
P1D/AN13/CTS4_1/IC03_1/MAD21_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
9
67
P1C/AN12/SCK4_1/IC02_1/MAD20_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
10
66
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
11
65
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
12
64
P19/AN09/SCK2_2/MAD17_1
P34/FRCK0_0/TIOB4_1/MADATA11_1
13
63
P18/AN08/SOT2_2/MAD16_1
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1
14
62
AVSS
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1
15
61
AVRH
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1
16
60
AVCC
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1
17
59
P17/AN07/SIN2_2/INT04_1/MAD15_1
P39/DTTI0X_0/ADTG_2
18
58
P16/AN06/SCK0_1/MAD14_1
P3A/RTO00_0/TIOA0_1
19
57
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3B/RTO01_0/TIOA1_1
20
56
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3C/RTO02_0/TIOA2_1
21
55
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3D/RTO03_0/TIOA3_1
22
54
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3E/RTO04_0/TIOA4_1
23
53
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3F/RTO05_0/TIOA5_1
24
52
P10/AN00
VSS
25
51
VCC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_1
P45/TIOA5_0/RTO15_1/MAD01_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 FPT-100P-M06
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
VCC
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1
P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1
P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
VSS
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P21/SIN0_0/INT06_1/BIN1_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
81
50
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
82
49
P23/SCK0_0/TIOA7_1/RTO00_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
83
48
P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
84
47
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
85
46
P1D/AN13/CTS4_1/IC03_1/MAD21_1
P56/INT08_2/DTTI1X_0/MADATA06_1
86
45
P1C/AN12/SCK4_1/IC02_1/MAD20_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
87
44
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
88
43
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
89
42
P19/AN09/SCK2_2/MAD17_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
90
41
P18/AN08/SOT2_2/MAD16_1
P34/FRCK0_0/TIOB4_1/MADATA11_1
91
40
AVSS
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1
92
39
AVRH
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1
93
38
AVCC
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1
94
37
P17/AN07/SIN2_2/INT04_1/MAD15_1
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1
95
36
P16/AN06/SCK0_1/MAD14_1
P39/DTTI0X_0/ADTG_2
96
35
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3A/RTO00_0/TIOA0_1
97
34
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3B/RTO01_0/TIOA1_1
98
33
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3C/RTO02_0/TIOA2_1
99
32
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3D/RTO03_0/TIOA3_1
100
31
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
28
VSS
30
27
PE3/X1
29
26
PE2/X0
VCC
25
P10/AN00
24
MD0
16
INITX
23
15
P47/X1A
PE0/MD1
14
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
13
P46/X0A
22
12
VSS
VCC
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
11
C
21
10
P45/TIOA5_0/RTO15_1/MAD01_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
9
P44/TIOA4_0/RTO14_1/MAD00_1
20
8
P43/TIOA3_0/RTO13_1/ADTG_7
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
7
P42/TIOA2_0/RTO12_1
19
6
P41/TIOA1_0/RTO11_1/INT13_1
18
5
P40/TIOA0_0/RTO10_1/INT12_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
4
VCC
17
3
VSS
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
2
P3F/RTO05_0/TIOA5_1
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
1
P3E/RTO04_0/TIOA4_1
QFP - 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
11
D a t a S h e e t
 FPT-80P-M37
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P07/ADTG_0/MCLKOUT_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
2
59
P21/SIN0_0/INT06_1/BIN1_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
3
58
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
4
57
P23/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
5
56
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
6
55
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
7
54
P19/AN09/SCK2_2/MAD17_1
P56/INT08_2/DTTI1X_0/MADATA06_1
8
53
P18/AN08/SOT2_2/MAD16_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
9
52
AVSS
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
10
51
AVRH
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
12
49
P17/AN07/SIN2_2/INT04_1/MAD15_1
P39/DTTI0X_0/ADTG_2
13
48
P16/AN06/SCK0_1/MAD14_1
P3A/RTO00_0/TIOA0_1
14
47
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3B/RTO01_0/TIOA1_1
15
46
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3C/RTO02_0/TIOA2_1
16
45
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3D/RTO03_0/TIOA3_1
17
44
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3E/RTO04_0/TIOA4_1
18
43
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3F/RTO05_0/TIOA5_1
19
42
P10/AN00
VSS
20
41
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/MAD00_1
P45/TIOA5_0/MAD01_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 FPT-64P-M38/M39
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3
P0F/NMIX/CROUT_1
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/SIN0_0/INT06_1
P50/INT00_0/AIN0_2/SIN3_1
2
47
P22/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
46
P23/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVSS
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1
10
39
P15/AN05/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1
12
37
P13/AN03/SCK1_1/IC01_2
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA4_1
14
35
P11/AN01/SIN1_1/INT02_1/FRCK0_2
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/AIN0_1
P4A/TIOB1_0/BIN0_1
P4B/TIOB2_0/ZIN0_1
P4C/TIOB3_0/SCK7_1/AIN1_2
P4D/TIOB4_0/SOT7_1/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
13
D a t a S h e e t
 BGA-112P-M04
1
2
3
4
5
6
7
8
9
10
11
A
VSS
UDP0
UDM0
USBVCC
P0E
P0B
P07
TMS/
SWDIO
TRSTX
VCC
VSS
B
VCC
VSS
P52
P61
P0F
P0C
P08
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0D
P09
P05
VSS
P20
P21
D
P53
P54
P55
VSS
P56
P63
P0A
VSS
P06
P23
AN15
E
P30
P31
P32
P33
Index
P22
AN14
AN12
AN11
F
P34
P35
P36
P39
AN13
AN10
AN09
AVRH
G
P37
P38
P3A
P3D
AN08
AN07
AN06
AVSS
H
P3B
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
J
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
PFBGA - 112
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 LCC-64P-M24
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3
P0F/NMIX/CROUT_1
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/SIN0_0/INT06_1
P50/INT00_0/AIN0_2/SIN3_1
2
47
P22/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
46
P23/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVSS
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1
10
39
P15/AN05/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1
12
37
P13/AN03/SCK1_1/IC01_2
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA4_1
14
35
P11/AN01/SIN1_1/INT02_1/FRCK0_2
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/AIN0_1
P4A/TIOB1_0/BIN0_1
P4B/TIOB2_0/ZIN0_1
P4C/TIOB3_0/SCK7_1/AIN1_2
P4D/TIOB4_0/SOT7_1/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
15
D a t a S h e e t
 LIST OF PIN FUNCTIONS
 List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
1
79
B1
1
LQFP-64
QFN-64
Pin name
1
VCC
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
(PPG10_0)
MADATA00_1
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
RTO11_0
(PPG10_0)
MADATA01_1
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
RTO12_0
(PPG12_0)
MADATA02_1
P53
SIN6_0
TIOA1_2
INT07_2
RTO13_0
(PPG12_0)
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
RTO14_0
(PPG14_0)
MADATA04_1
2
2
80
C1
2
-
3
3
81
C2
3
-
4
4
82
B3
4
-
5
83
D1
5
-
6
84
D2
6
-
16
CONFIDENTIAL
I/O circuit Pin state
type
type
-
E
H
E
H
E
H
E
H
E
I
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
7
85
D3
7
-
8
86
D5
8
-
9
87
E1
9
5
-
10
88
E2
10
6
-
11
89
E3
11
7
-
12
90
E4
12
8
13
91
F1
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
-
-
Pin name
P55
SCK6_0
(SCL6_0)
ADTG_1
RTO15_0
(PPG14_0)
MADATA05_1
P56
INT08_2
DTTI1X_0
MADATA06_1
P30
AIN0_0
TIOB0_1
INT03_2
MADATA07_1
P31
BIN0_0
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
MADATA08_1
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
MADATA09_1
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MADATA10_1
P34
FRCK0_0
TIOB4_1
MADATA11_1
I/O circuit Pin state
type
type
E
I
E
H
E
H
E
H
E
H
E
H
E
I
17
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
14
92
F2
-
-
15
93
F3
-
-
16
94
G1
-
-
17
95
G2
-
-
18
96
F4
13
9
19
97
G3
14
10
20
98
H1
15
11
21
99
H2
16
12
22
100
G4
17
13
-
-
B2
-
-
18
CONFIDENTIAL
Pin name
P35
IC03_0
TIOB5_1
INT08_1
MADATA12_1
P36
IC02_0
SIN5_2
INT09_1
MADATA13_1
P37
IC01_0
SOT5_2
(SDA5_2)
INT10_1
MADATA14_1
P38
IC00_0
SCK5_2
(SCL5_2)
INT11_1
MADATA15_1
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
TIOA0_1
P3B
RTO01_0
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
TIOA3_1
VSS
I/O circuit Pin state
type
type
E
H
E
H
E
H
E
H
E
I
G
I
G
I
G
I
G
I
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
23
1
H3
18
14
24
2
J2
19
15
25
26
3
4
L1
J1
20
-
16
-
27
5
J4
-
-
28
6
L5
-
-
29
7
K5
-
-
30
8
J5
-
-
31
9
H5
21
22
32
10
L6
-
-
-
K2
J3
H4
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
-
-
Pin name
P3E
RTO04_0
(PPG04_0)
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
P43
TIOA3_0
RTO13_1
(PPG12_1)
ADTG_7
P44
TIOA4_0
MAD00_1
RTO14_1
(PPG14_1)
P45
TIOA5_0
MAD01_1
RTO15_1
(PPG14_1)
VSS
VSS
VSS
I/O circuit Pin state
type
type
G
I
G
I
-
G
H
G
H
G
I
G
I
G
I
G
I
-
19
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
Pin name
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
MAD02_1
P49
TIOB0_0
AIN0_1
IC10_1
SOT3_2
(SDA3_2)
MAD03_1
P4A
TIOB1_0
BIN0_1
IC11_1
SCK3_2
(SCL3_2)
MAD04_1
P4B
TIOB2_0
ZIN0_1
IC12_1
MAD05_1
P4C
TIOB3_0
SCK7_1
(SCL7_1)
AIN1_2
IC13_1
MAD06_1
33
34
35
11
12
13
L2
L4
K1
23
24
25
17
18
36
14
L3
26
19
37
15
K3
27
20
38
16
K4
28
21
39
17
K6
29
-
22
40
18
J6
30
-
23
41
19
L7
31
-
24
42
20
K7
32
-
25
43
21
H6
33
-
20
CONFIDENTIAL
I/O circuit Pin state
type
type
D
M
D
N
B
C
E
H
E
I
E
I
E
I
E / I*
I
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
26
44
22
J7
34
-
45
23
K8
35
27
46
24
K9
36
28
47
25
L8
37
29
48
26
L9
38
30
49
27
L10
39
31
50
51
28
29
L11
K11
40
41
32
33
52
30
J11
42
34
53
31
J10
43
35
-
54
32
J8
44
-
-
K10
J9
-
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
36
-
Pin name
P4D
TIOB4_0
SOT7_1
(SDA7_1)
BIN1_2
FRCK1_1
MAD07_1
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MAD08_1
MD1
PE0
MD0
X0
PE2
X1
PE3
VSS
VCC
P10
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
MAD09_1
P12
AN02
SOT1_1
(SDA1_1)
IC00_2
MAD10_1
VSS
VSS
I/O circuit Pin state
type
type
E / I*
I
E / I*
I
C
P
J
D
A
A
A
B
-
F
K
F
L
F
K
-
21
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
55
33
H10
45
LQFP-64
QFN-64
37
38
56
34
H9
46
39
57
35
H7
47
-
58
36
G10
48
59
37
G9
49
60
61
62
38
39
40
H11
F11
G11
50
51
52
63
41
G8
53
-
40
41
42
43
44
-
64
42
F10
54
-
-
H8
-
22
CONFIDENTIAL
45
-
Pin name
P13
AN03
SCK1_1
(SCL1_1)
IC01_2
MAD11_1
P14
AN04
INT03_1
IC02_2
SIN0_1
MAD12_1
P15
AN05
IC03_2
SOT0_1
(SDA0_1)
MAD13_1
P16
AN06
SCK0_1
(SCL0_1)
MAD14_1
P17
AN07
SIN2_2
INT04_1
MAD15_1
AVCC
AVRH
AVSS
P18
AN08
SOT2_2
(SDA2_2)
MAD16_1
P19
AN09
SCK2_2
(SCL2_2)
MAD17_1
VSS
I/O circuit Pin state
type
type
F
K
F
L
F
K
F
K
F
L
-
F
K
F
K
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
65
43
F9
55
-
66
44
E11
56
-
67
45
E10
-
-
68
46
F8
-
-
69
47
E9
-
-
70
48
D11
-
-
-
-
B10
C9
-
-
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin name
P1A
AN10
SIN4_1
INT05_1
IC00_1
MAD18_1
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
MAD19_1
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
MAD20_1
P1D
AN13
CTS4_1
IC03_1
MAD21_1
P1E
AN14
RTS4_1
DTTI0X_1
MAD22_1
P1F
AN15
ADTG_5
FRCK0_1
MAD23_1
VSS
VSS
I/O circuit Pin state
type
type
F
L
F
K
F
K
F
K
F
K
F
K
-
23
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
57
71
49
50
46
D10
-
72
LQFP-64
QFN-64
E8
58
-
47
-
73
51
C11
59
48
-
74
52
C10
60
-
75
76
53
54
A11
A10
-
-
77
55
A9
61
49
-
78
56
B9
62
79
57
B11
63
50
51
-
80
58
A8
64
52
81
59
B8
65
53
82
60
C8
-
-
-
-
D8
-
-
24
CONFIDENTIAL
Pin name
P23
SCK0_0
(SCL0_0)
TIOA7_1
RTO00_1
(PPG00_1)
P22
SOT0_0
(SDA0_0)
TIOB7_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
CROUT_0
AIN1_1
MAD24_1
VSS
VCC
P00
TRSTX
MCSX7_1
P01
TCK
SWCLK
P02
TDI
MCSX6_1
P03
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
VSS
I/O circuit Pin state
type
type
E
I
E
I
E
H
E
H
E
E
E
E
E
E
E
E
E
E
E
F
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
83
61
D9
-
LQFP-64
QFN-64
-
66
84
62
A7
-
85
63
B7
-
-
86
64
C7
-
-
87
65
D7
67
54
-
55
88
66
A6
68
-
56
89
67
B6
69
-
-
-
D4
C3
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
-
-
Pin name
P06
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
MCSX4_1
P07
ADTG_0
MCLKOUT_1
TRACED2
SCK4_2
(SCL4_2)
P08
TRACED3
TIOA0_2
CTS4_2
MCSX3_1
P09
TRACECLK
TIOB0_2
RTS4_2
MCSX2_1
P0A
SIN4_0
INT00_2
FRCK1_0
MCSX1_1
P0B
SOT4_0
(SDA4_0)
TIOB6_1
IC10_0
MCSX0_1
P0C
SCK4_0
(SCL4_0)
TIOA6_1
IC11_0
MALE_1
VSS
VSS
I/O circuit Pin state
type
type
E
F
E
G
E
G
E
G
E / I*
H
E / I*
I
E / I*
I
-
25
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
LQFP-64
QFN-64
90
68
C6
70
-
91
69
A5
71
-
92
70
B5
72
57
93
71
D6
73
-
94
72
C5
74
58
-
95
73
B4
75
59
96
74
C4
76
97
75
A4
77
61
98
76
A3
78
62
99
77
A2
79
63
60
100
78
A1
80
64
*: 5V tolerant I/O on MB9AF315MA/NA, MB9AF316MA/NA.
26
CONFIDENTIAL
Pin name
P0D
RTS4_0
TIOA3_2
IC12_0
MDQM0_1
P0E
CTS4_0
TIOB3_2
IC13_0
MDQM1_1
P0F
NMIX
CROUT_1
P63
INT03_0
MWEX_1
P62
SCK5_0
(SCL5_0)
ADTG_3
MOEX_1
P61
SOT5_0
(SDA5_0)
TIOB2_2
UHCONX
P60
SIN5_0
TIOA2_2
INT15_1
MRDY_1
USBVCC
P80
UDM0
P81
UDP0
VSS
I/O circuit Pin state
type
type
E
I
E
I
E
J
E
H
E
I
E
I
E / I*
H
H
O
H
O
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Module
Pin name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base Timer
0
Base Timer
1
Base Timer
2
Function
A/D converter external trigger input
pin
A/D converter analog input pin
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
62
85
96
72
48
90
8
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
97
63
18
87
64
6
98
83
19
88
84
7
99
74
20
89
73
A7
D3
F4
C5
D11
E4
J5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
66
7
13
74
12
42
43
44
45
46
47
48
49
53
54
55
56
14
30
9
15
5
31
10
6
16
76
32
11
75
9
58
8
34
35
36
37
38
39
40
44
45
10
22
5
11
23
6
12
60
24
7
59
27
D a t a S h e e t
Module
Pin name
Base Timer
3
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
28
CONFIDENTIAL
Function
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
89
88
71
72
-
8
100
68
21
90
69
9
1
22
91
10
2
60
23
92
61
67
66
49
50
-
J5
G4
C6
H6
E4
A5
H5
H3
J7
F1
L6
J2
C8
K8
F2
D9
B6
A6
D10
E8
-
17
70
33
12
71
21
18
34
22
19
35
69
68
57
58
-
13
25
8
14
26
15
27
56
55
46
47
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Pin name
Debugger
SWCLK
External
Bus
Serial wire debug interface clock input
Serial wire debug interface data input /
SWDIO
output
SWO
Serial wire viewer output
TCK
J-TAG test clock input
TDI
J-TAG test data input
TDO
J-TAG debug data output
TMS
J-TAG test mode state input/output
TRACECLK Trace CLK output of ETM
TRACED0
TRACED1
Trace data output of ETM
TRACED2
TRACED3
TRSTX
J-TAG test reset Input
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
MAD12_1 External bus interface address bus
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Function
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
78
56
B9
62
50
80
58
A8
64
52
81
78
79
81
80
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
59
56
57
59
58
64
60
61
62
63
55
9
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
65
62
63
65
64
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
60
53
50
51
53
52
49
-
29
D a t a S h e e t
Module
Pin name
External
Bus
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
MOEX_1
MWEX_1
Function
External bus interface chip select
output pin
External bus interface byte mask
signal output
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
External bus interface data bus
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
Address Latch enable signal for
multiplex
MRDY_1
External RDY input signal
MCLKOUT_1 External bus clock output
MALE_1
30
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
63
61
70
71
-
94
72
C5
74
-
93
71
D6
73
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
4
5
6
7
8
9
10
11
12
-
-
89
67
B6
69
-
96
84
74
62
C4
A7
76
66
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Pin name
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
Function
External interrupt request 00
input pin
External interrupt request 01
input pin
External interrupt request 02
input pin
External interrupt request 03
input pin
External interrupt request 04
input pin
External interrupt request 05
input pin
External interrupt request 06
input pin
External interrupt request 07
input pin
External interrupt request 08
input pin
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
External interrupt request 15
input pin
Non-Maskable Interrupt input
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
2
67
3
4
43
73
46
9
12
49
10
60
55
11
59
35
2
54
3
4
35
38
5
8
40
6
7
48
27
5
83
D1
5
-
14
8
92
86
F2
D5
8
-
15
93
F3
-
-
16
94
G1
-
-
17
95
G2
-
-
27
5
J4
-
-
28
6
L5
-
-
39
17
K6
29
-
96
74
C4
76
60
92
70
B5
72
57
31
D a t a S h e e t
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
32
CONFIDENTIAL
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
60
59
58
57
49
50
51
52
53
54
55
56
57
34
35
36
37
38
39
40
44
45
48
47
46
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
9
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
5
6
7
8
9
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
3
4
60
59
58
62
63
28
30
31
33
D a t a S h e e t
Module
Pin name
Function
Multi
Function
Serial
0
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
Multifunction serial interface ch.0
input pin
Multifunction serial interface ch.0
output pin
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.0
clock I/O pin
This pin operates as SCK0 when it is
used in a CSIO (operation modes 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.1
input pin
Multifunction serial interface ch.1
output pin
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.1
clock I/O pin
This pin operates as SCK1 when it is
used in a CSIO (operation modes 2)
and as SCL1 when it is used in an I2C
(operation mode 4).
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multi
Function
Serial
1
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
34
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
73
56
51
34
C11
H9
59
46
48
-
72
50
E8
58
47
57
35
H7
47
-
71
49
D10
57
46
58
36
G10
48
-
53
31
J10
43
35
54
32
J8
44
36
55
33
H10
45
37
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Multi
Function
Serial
2
Pin name
SIN2_2
SOT2_2
(SDA2_2)
SCK2_2
(SCL2_2)
Multi
Function
Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function
Multifunction serial interface ch.2
input pin
Multifunction serial interface ch.2
output pin
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.2
clock I/O pin
This pin operates as SCK2 when it is
used in a CSIO (operation modes 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.3
input pin
Multifunction serial interface ch.3
output pin
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.3
clock I/O pin
This pin operates as SCK3 when it is
used in a CSIO (operation modes 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
59
37
G9
49
40
63
41
G8
53
44
64
42
F10
54
45
2
39
80
17
C1
K6
2
29
2
-
3
81
C2
3
3
40
18
J6
30
-
4
82
B3
4
4
41
19
L7
31
-
35
D a t a S h e e t
Module
Pin name
Multi
Function
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
SOT5_0
(SDA5_0)
Multi
Function
Serial
5
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_2
(SCL5_2)
36
CONFIDENTIAL
Function
Multifunction serial interface ch.4
input pin
Multifunction serial interface ch.4
output pin
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.4
clock I/O pin
This pin operates as SCK4 when it is
used in a CSIO (operation modes 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.4
RTS output pin
Multifunction serial interface ch.4
CTS input pin
Multifunction serial interface ch.5
input pin
Multifunction serial interface ch.5
output pin
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.5
clock I/O pin
This pin operates as SCK5 when it is
used in a CSIO (operation modes 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
87
65
82
65
43
60
D7
F9
C8
67
55
-
54
-
88
66
A6
68
55
66
44
E11
56
-
83
61
D9
-
-
89
67
B6
69
56
67
45
E10
-
-
84
62
A7
-
-
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
71
76
-
60
-
95
73
B4
75
59
16
94
G1
-
-
94
72
C5
74
58
17
95
G2
-
-
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Pin name
Function
Multi
Function
Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
Multifunction serial interface ch.6
input pin
Multifunction serial interface ch.6
output pin
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.6
clock I/O pin
This pin operates as SCK6 when it is
used in a CSIO (operation modes 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.7
input pin
Multifunction serial interface ch.7
output pin
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.7
clock I/O pin
This pin operates as SCK7 when it is
used in a CSIO (operation modes 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multi
Function
Serial
7
SIN7_1
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
5
12
83
90
D1
E4
5
12
8
6
84
D2
6
-
11
89
E3
11
7
7
85
D3
7
-
10
88
E2
10
6
45
23
K8
35
27
44
22
J7
34
26
43
21
H6
33
25
37
D a t a S h e e t
Module
Pin name
Function
Multi
Function
Timer
0
DTTI0X_0
Input signal of wave form generator to
control outputs RTO00 to RTO05 of
multi-function timer 0
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
38
CONFIDENTIAL
16-bit free-run timer ch.0 external
clock input pin
16-bit input capture input pin of
multi-function timer 0
ICxx describes channel number.
Wave form generator output of
multi-function timer 0
This pin operates as PPG00 when it is
used in PPG 0 output modes.
Wave form generator output of
multi-function timer 0
This pin operates as PPG00 when it is
used in PPG 0 output modes.
Wave form generator output of
multi-function timer 0
This pin operates as PPG02 when it is
used in PPG 0 output modes.
Wave form generator output of
multi-function timer 0
This pin operates as PPG02 when it is
used in PPG 0 output modes.
Wave form generator output of
multi-function timer 0
This pin operates as PPG04 when it is
used in PPG 0 output modes.
Wave form generator output of
multi-function timer 0
This pin operates as PPG04 when it is
used in PPG 0 output modes.
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
18
96
F4
13
9
69
47
E9
-
-
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
F1
D11
J10
G2
F9
J8
G1
E11
H10
F3
E10
H9
F2
F8
H7
43
55
44
56
45
46
47
35
36
37
38
39
19
97
G3
14
10
71
49
D10
-
-
20
98
H1
15
11
21
99
H2
16
12
22
100
G4
17
13
23
1
H3
18
14
24
2
J2
19
15
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
Pin name
Function
Multi
Function
Timer
1
DTTI1X_0
Input signal of wave form generator to
control outputs RTO10 to RTO15 of
multi-function timer 1
16-bit free-run timer ch.1 external
clock input pin
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
16-bit input capture input pin of
multi-function timer 1
ICxx describes channel number.
Wave form generator output of
multi-function timer 1
This pin operates as PPG10 when it is
used in PPG 1 output modes.
Wave form generator output of
multi-function timer 1
This pin operates as PPG10 when it is
used in PPG 1 output modes.
Wave form generator output of
multi-function timer 1
This pin operates as PPG12 when it is
used in PPG 1 output modes.
Wave form generator output of
multi-function timer 1
This pin operates as PPG12 when it is
used in PPG 1 output modes.
Wave form generator output of
multi-function timer 1
This pin operates as PPG14 when it is
used in PPG 1 output modes.
Wave form generator output of
multi-function timer 1
This pin operates as PPG14 when it is
used in PPG 1 output modes.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
8
86
D5
8
-
39
17
K6
29
-
87
44
88
40
89
41
90
42
91
43
65
22
66
18
67
19
68
20
69
21
D7
J7
A6
J6
B6
L7
C6
K7
A5
H6
67
34
68
30
69
31
70
32
71
33
-
2
80
C1
2
-
27
5
J4
-
-
3
81
C2
3
-
28
6
L5
-
-
4
82
B3
4
-
29
7
K5
-
-
5
83
D1
5
-
30
8
J5
-
-
6
84
D2
6
-
31
9
H5
21
-
7
85
D3
7
-
32
10
L6
22
-
39
D a t a S h e e t
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
UDM0
UDP0
UHCONX
Quadrature
Position/
Revolution
Counter
1
USB
40
CONFIDENTIAL
Function
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
USB Function / HOST D – pin
USB Function / HOST D + pin
USB external pull-up control pin
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
9
40
2
10
41
3
11
42
4
74
43
73
44
72
45
98
99
95
87
18
80
88
19
81
89
20
82
52
21
51
22
50
23
76
77
73
E1
J6
C1
E2
L7
C2
E3
K7
B3
C10
H6
C11
J7
E8
K8
A3
A2
B4
9
30
2
10
31
3
11
32
4
60
33
59
34
58
35
78
79
75
5
22
2
6
23
3
7
24
4
25
26
27
62
63
59
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Module
RESET
Pin name
INITX
Mode
MD0
MD1
POWER
GND
CLOCK
Analog
POWER
VCC
VCC
VCC
VCC
VCC
USBVCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Analog
GND
C pin
AVSS
C
Function
External Reset Input. A reset is valid
when INITX=L
Mode 0 pin
During normal operation, MD0=L
must be input. During serial
programming to flash memory,
MD0=H must be input.
Mode 1 pin
During serial programming to flash
memory, MD1=L must be input.
Power supply Pin
Power supply Pin
Power supply pin
Power supply pin
Power supply pin
3.3V Power supply port for USB I/O
GND Pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
A/D converter analog power supply
pin
A/D converter analog reference
voltage input pin
38
16
K4
28
21
47
25
L8
37
29
46
24
K9
36
28
1
26
35
51
76
97
25
34
50
75
100
48
36
49
37
74
92
79
4
13
29
54
75
3
12
28
53
78
26
14
27
15
52
70
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
L9
L3
L10
K3
C10
B5
1
25
41
77
20
24
40
80
38
26
39
27
60
72
1
18
33
61
16
32
64
30
19
31
20
57
60
38
H11
50
41
61
39
F11
51
42
A/D converter GND pin
62
40
G11
52
43
Power stabilization capacity pin
33
11
L2
23
17
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Pin No
LQFP- QFP- BGA- LQFP- LQFP100 100 112
80
64
QFN64
41
D a t a S h e e t
 I/O CIRCUIT TYPE
Type
Circuit
Remarks
 It is possible to select the
A
main oscillation / GPIO
function
Pull-up
resistor
P-ch
P-ch
When the main oscillation is
selected.
 Oscillation feedback resistor
: Approximately 1MΩ
 With Standby mode control
Digital output
X1
N-ch
R
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
Pull-up resistor control
 Pull-up resistor
: Approximately 50kΩ
Digital input
 IOH = -4mA, IOL = 4mA
Digital output
Standby mode control
Feedback
Clock input
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
 CMOS level hysteresis input
 Pull-up resistor
B
: Approximately 50kΩ
Pull-up resistor
Digital input
42
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Type
Circuit
C
Digital input
Remarks
 Open drain output
 CMOS level hysteresis input
Digital output
N-ch
 It is possible to select the sub
D
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
R
When the sub oscillation is
selected.
 Oscillation feedback resistor
: Approximately 5MΩ
 With Standby mode control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
Pull-up resistor control
: Approximately 50kΩ

I
OH = -4mA, IOL = 4mA
Digital input
Digital output
Standby mode control
Feedback
Clock input
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
43
D a t a S h e e t
Type
Circuit
Remarks





E
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
 IOH = -4mA, IOL = 4mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control







F
P-ch
R
P-ch
Digital output
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
 IOH = -4mA, IOL = 4mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
44
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Type
Circuit
Remarks





G
P-ch
P-ch
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
 IOH = -12mA, IOL = 12mA
 +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
 It is possible to select the
H
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP(+)output
EBP
USB full-speed, low-speed control
UDP(+)input
Differential
Differential input
EBM
USB IO / GPIO function.
When the USB IO is selected.
 Full-speed, Low-speed control
When the GPIO is selected.
 CMOS level output
 CMOS level hysteresis input
 With standby mode control
 IOH = -20.5mA, IOL = 18.5mA
USB/GPIO select
UDM(-)input
UDM(-)output
USB input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
45
D a t a S h e e t
Type
Circuit
Remarks






I
P-ch
Digital output
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
5V tolerant
With standby mode control
IOH = -4mA, IOL = 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode Input
46
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
47
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch
results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder
bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
48
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
49
D a t a S h e e t
3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
50
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 HANDLING DEVICES
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
 Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the
fluctuation is within the recommended operating conditions of the VCC power supply voltage.
As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation
in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not
exceed 10% of the VCC value in the recommended operating conditions, and the transient
fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching
the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located
as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Using an external clock
When using an external clock, the clock signal should be driven to the X0,X0A pin only and the X1,X1A
pin should be kept open.
 Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
 Handling when using Multi function serial pin as I2C pin
If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
51
D a t a S h e e t
 C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the
regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor
of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance
variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select
the capacitor that meets the specifications in the operating conditions to use by evaluating
the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is
as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : USBVCC → VCC
AVRH → AVCC → VCC
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
 Differences in features among the products with different memory sizes and between
Flash products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
52
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 BLOCK DIAGRAM
MB9AF311LA/MA/NA, F312LA/MA/NA, F314LA/MA/NA, F315MA/NA, F316MA/NA
TRSTX,TCK,
TDI,TMS
TDO
TRACED[3:0],
TRACECLK
SWJ-DP
ETM*1
TPIU*1
ROM
Table
SRAM0
8/16
Kbyte
Cortex-M3 Core I
@40 MHz(Max)
D
Multi-layer AHB (Max 40 MHz)
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40 MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
On-Chip
Flash
64/128/256/384/512
Kbyte
Flash I/F
Security
SRAM1
8/16
Kbyte
USB2.0
(Host/
Func)
PHY
USBVCC
UDP0/UDM0
UHCONX
DMAC
8ch
CSV
X0
X1
X0A
Main
Osc
Sub
Osc
PLL
CR
4MHz
AHB-AHB
Bridge
CLK
Source Clock
CR
100kHz
MAD[24:0]
CROUT
AVCC,
AVSS,AVRH
External Bus I/F*2
12-bit A/D Converter x 3
MADATA[15:0]
MCSX[7:0],
MOEX,MWEX,
MALE,
MRDY,
MCLKOUT,
MDQM[1:0]
Unit 0
AN[15:0]
Unit 1
ADTGx
Unit 2*2
USB Clock ctrl
AIN[1:0]
BIN[1:0]
QPRC
2ch.
ZIN[1:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
FRCK[1:0]
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
16-bit Input Capture
4ch.
16-bit Free-Run
Timer
3ch.
16-bit Output
Compare
6ch.
LVD Ctrl
AHB-APB Bridge : APB2 (Max 40 MHz)
TIOB[7:0]
Base Timer
16-bit 8ch. /
32-bit 4ch.
AHB-APB Bridge : APB1 (Max 40 MHz)
TIOA[7:0]
Multi-Function Timer x 2
Power-On
Reset
LVD
Regulator
C
IRQ-Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
MD[1:0]
MODE-Ctrl
GPIO
Waveform Generator
3ch.
16-bit PPG
3ch.
PLL
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to 7)
2
& HW flow control(ch.4)*
PIN-Function-Ctrl
P0[F:0],
P1[F:0],
.
.
.
Px[x:0]
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
*1: For the MB9AF311LA/MA, F312LA/MA, MB9AF314LA/MA, MB9AF315MA and MB9AF316MA, ETM
is not available.
*2: For the MB9AF311LA, F312LA and MB9AF314LA, the External Bus Interface and 12-bit A/D Converter
(unit 2) are not available. And the Multi-function Serial Interface does not support hardware flow control in
these products.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
53
D a t a S h e e t
 MEMORY SIZE
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
54
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 MEMORY MAP
 Memory Map(1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
Reserved
0x4003_B000
0x4003_A000
0x7000_0000
0x4003_9000
0x6000_0000
External Device
Area
0x4003_8000
0x4003_7000
Reserved
0x4003_6000
0x4003_5000
0x4400_0000
32Mbytes
Bit band alias
0x4200_0000
Peripherals
0x4000_0000
Reserved
0x2400_0000
Reserved
0x2008_0000
0x2000_0000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_8000
Reserved
0x0010_2000
Security/CR Trim
Watch Counter
CRC
MFS
Reserved
USB Clock Ctrl
LVD
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
A/DC
0x4002_6000
QPRC
0x4002_5000
Base Timer
PPG
0x4002_2000
0x4002_1000
0x4002_0000
Reserved
MFT Unit1
MFT Unit0
0x4001_6000
Flash
0x4001_5000
0x4001_3000
0x0000_0000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Reserved
0x4002_7000
SRAM1
SRAM0
0x1FF8_0000
0x0010_0000
0x4003_3000
0x4003_2000
0x4002_E000
32Mbytes
Bit band alias
0x2200_0000
See the next page
"nMemory Map
(2),(3)"
for the memory size
details.
0x4003_4000
DMAC
Reserved
USB ch.0
EXT-bus I/F
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
55
D a t a S h e e t
 Memory Map(2)
MB9AF316MA/NA
MB9AF315MA/NA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_4000
SRAM1
16Kbytes
0x2000_4000
SRAM1
16Kbytes
0x2000_0000
SRAM1
16Kbytes
0x2000_0000
SRAM0
16Kbytes
0x2000_0000
SRAM0
16Kbytes
0x1FFF_C000
SRAM0
16Kbytes
0x1FFF_C000
Reserved
0x1FFF_C000
Reserved
0x0010_2000
0x0010_0000
0x2008_0000
Reserved
0x2000_4000
0x0010_1000
MB9AF314LA/MA/NA
Reserved
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x0008_0000
Reserved
Reserved
0x0006_0000
SA10-13(64KBx4)
0x0000_0000
SA4-7(8KBx4)
0x0004_0000
SA10-11(64KBx2)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
SA8-9(48KBx2)
0x0000_0000
Flash 256Kbytes
SA8-9(48KBx2)
Flash 384Kbytes
Flash 512Kbytes
SA10-15(64KBx6)
SA4-7(8KBx4)
*: See "MB9A310/110 Series Flash programming Manual" for sector structure of Flash.
56
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 Memory Map(3)
MB9AF312LA/MA/NA
MB9AF311LA/MA/NA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
0x1FFF_E000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
Reserved
SA4-7(8KBx4)
0x0001_0000
SA8-9(16KBx2)
0x0000_0000
Flash 64Kbytes
SA8-9(48KBx2)
CR trimming
Security
Reserved
Flash 128Kbytes
0x0002_0000
0x0000_0000
SRAM1
8Kbytes
SRAM0
8Kbytes
SA4-7(8KBx4)
*: See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
57
D a t a S h e e t
 Peripheral Address Map
Start address
End address
0x4000_0000H
0x4000_0FFFH
0x4000_1000H
0x4001_0000H
0x4001_1000H
0x4001_2000H
0x4001_3000H
0x4001_5000H
0x4001_6000H
0x4002_0000H
0x4002_1000H
0x4002_2000H
0x4002_4000H
0x4002_5000H
0x4002_6000H
0x4002_7000H
0x4002_8000H
0x4002_E000H
0x4002_F000H
0x4003_0000H
0x4003_1000H
0x4003_2000H
0x4003_3000H
0x4003_4000H
0x4003_5000H
0x4003_6000H
0x4003_7000H
0x4003_8000H
0x4003_9000H
0x4003_A000H
0x4003_B000H
0x4003_F000H
0x4004_0000H
0x4005_0000H
0x4006_0000H
0x4006_1000H
0x4006_2000H
0x4006_3000H
0x4006_4000H
0x4000_FFFFH
0x4001_0FFFH
0x4001_1FFFH
0x4001_2FFFH
0x4001_4FFFH
0x4001_5FFFH
0x4001_FFFFH
0x4002_0FFFH
0x4002_1FFFH
0x4002_3FFFH
0x4002_4FFFH
0x4002_5FFFH
0x4002_6FFFH
0x4002_7FFFH
0x4002_DFFFH
0x4002_EFFFH
0x4002_FFFFH
0x4003_0FFFH
0x4003_1FFFH
0x4003_2FFFH
0x4003_3FFFH
0x4003_4FFFH
0x4003_5FFFH
0x4003_6FFFH
0x4003_7FFFH
0x4003_8FFFH
0x4003_9FFFH
0x4003_AFFFH
0x4003_EFFFH
0x4003_FFFFH
0x4004_FFFFH
0x4005_FFFFH
0x4006_0FFFH
0x4006_1FFFH
0x4006_2FFFH
0x4006_3FFFH
0x41FF_FFFFH
58
CONFIDENTIAL
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
Flash Memory I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt Controller
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
USB clock generator
Reserved
Multi-function serial
CRC
Watch Counter
Reserved
External bus interface
USB ch.0
Reserved
DMAC register
Reserved
Reserved
Reserved
Reserved
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
 INITX = 0
This is the period when the INITX pin is the "L" level.
 INITX = 1
This is the period when the INITX pin is the "H" level.
 SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
 SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
 Input enabled
Indicates that the input function can be used.
 Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
 Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
 Setting disabled
Indicates that the setting is disabled.
 Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
 Analog input is enabled
Indicates that the analog input is enabled.
 Trace output
Indicates that the trace function can be used.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
59
D a t a S h e e t
 LIST OF PIN STATUS
Power-on reset
or low voltage
detection state
Pin
status
type
Function group
Power supply
unstable
INITX input
state
Device internal
reset state
Power supply stable
Run mode or
sleep mode
state
Timer mode or STOP mode
state
Power supply
stable
Power supply stable
INITX=1
-
INITX=0
INITX=1
INITX=1
-
-
-
-
SPL=0
SPL=1
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Main crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Main crystal
oscillator output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enabled
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
INITX input pin
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
JTAG
selected
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
GPIO
selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Setting disabled
Setting
disabled
Setting
disabled
A
B
C
D
E
F
Trace selected
External interrupt
enabled selected
GPIO
selected, or resource
other than above
selected
60
CONFIDENTIAL
Trace output
Maintain
previous state
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Power-on reset
or low voltage
detection state
Pin
status
type
Function group
Power supply
unstable
Device internal
reset state
Power supply stable
Run mode or
sleep mode
state
Timer mode or STOP mode
state
Power supply
stable
Power supply stable
-
INITX=0
INITX=1
INITX=1
-
-
-
-
Setting disabled
Setting
disabled
Setting
disabled
GPIO
selected, or resource
other than above
selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO
selected, or resource
other than above
selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
GPIO selected,
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
NMIX selected
Setting disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
G
Trace selected
H
INITX input
state
INITX=1
SPL=0
Trace output
Maintain
previous state
Maintain
previous state
GPIO
selected, or resource
other than above
selected
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
I
J
SPL=1
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
61
D a t a S h e e t
Pin
status
type
Power-on reset
or low voltage
detection state
Function group
Power supply
unstable
Device internal
reset state
Power supply stable
Run mode or
sleep mode
state
Timer mode or STOP mode
state
Power supply
stable
Power supply stable
INITX=1
-
INITX=0
INITX=1
INITX=1
-
-
-
-
SPL=0
SPL=1
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO
selected, or resource
other than above
selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO
selected, or resource
other than above
selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Sub crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
K
L
INITX input
state
M
62
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Power-on reset
or low voltage
detection state
Pin
status
type
Function group
Power supply
unstable
INITX input
state
Device internal
reset state
Power supply stable
Run mode or
sleep mode
state
Timer mode or STOP mode
state
Power supply
stable
Power supply stable
-
INITX=0
INITX=1
INITX=1
-
-
-
-
SPL=0
INITX=1
SPL=1
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Sub crystal
oscillator output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enabled
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state/ Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Maintain
previous
state/ Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
GPIO selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Hi-Z at
transmission/
Input
enabled/
Internal input
fixed at "0" at
reception
N
O
P
USB I/O pin
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Hi-Z at
transmission/
Input
enabled/
Internal input
fixed at "0" at
reception
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/Input
enabled
*1 : Oscillation is stopped at sub timer mode, low speed CR timer mode, and stop mode.
*2 : Oscillation is stopped at stop mode.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
63
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
1.
Absolute Maximum Ratings
Parameter
1,
2
Power supply voltage* *
Power supply voltage (for USB) *1, *3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
Symbol
Min
Max
Unit
Remarks
Vss + 6.5
V
Vss + 6.5
V
Vss + 6.5
V
Vss + 6.5
V
Vcc + 0.5
Except for
Vss - 0.5
V
(≤ 6.5V)
USB pin
Input voltage*1
VI
USBVcc + 0.5
Vss - 0.5
V
USB pin
(≤ 6.5V)
Vss - 0.5
Vss + 6.5
V
5V tolerant
AVcc
+
0.5
Analog pin input voltage*1
VIA
Vss - 0.5
V
(≤ 6.5V)
Vcc + 0.5
Output voltage*1
VO
Vss - 0.5
V
(≤ 6.5V)
Clamp maximum current
ICLAMP
-2
+2
mA
*8
Clamp total maximum current
Σ[ICLAMP]
+20
mA
*8
10
mA
4mA type
"L" level maximum output current*5
IOL
20
mA
12mA type
39
mA
P80, P81
4
mA
4mA type
"L" level average output current*6
IOLAV
12
mA
12mA type
18.5
mA
P80, P81
"L" level total maximum output current
∑IOL
100
mA
"L" level total average output current*7
∑IOLAV
50
mA
- 10
mA
4mA type
"H" level maximum output current*5
IOH
- 20
mA
12mA type
- 39
mA
P80, P81
-4
mA
4mA type
6
"H" level average output current*
IOHAV
- 12
mA
12mA type
- 20.5
mA
P80, P81
"H" level total maximum output current
∑IOH
- 100
mA
"H" level total average output current*7
∑IOHAV
- 50
mA
Power consumption
PD
300
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1 : These parameters are based on the condition that Vss = AVss = 0.0V.
*2 : Vcc must not drop below Vss - 0.5V.
*3 : USBVcc must not drop below Vss - 0.5V.
*4 : Be careful not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*5 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*6 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*7 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
64
CONFIDENTIAL
Vcc
USBVcc
AVcc
AVRH
Rating
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss - 0.5
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
*8 :
・
・
・
・
・
・
・
・
See "LIST OF PIN FUNCTIONS" and "I/O CIRCUIT TYPE" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
65
D a t a S h e e t
2.
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Power supply voltage
Power supply voltage (3V
power supply) for USB
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
FPT-100P-M23
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
LCC-64P-M24
BGA-112P-M04
Symbol Conditions
Vcc
-
Value
Min
Max
2.7*4
Unit
AVcc
AVRH
-
2.7
2.7
5.5
3.6
(≤ Vcc)
5.5
(≤ Vcc)
5.5
AVcc
CS
-
1
10
μF
Ta
-
- 40
+ 105
°C
3.0
USBVcc
2.7
V
Remarks
*1
V
*2
V
V
AVcc = Vcc
For built-in
regulator*3
When
mounted on
- 40
+ 105
°C
four-layer
PCB
FPT-100P-M06
Ta
When
- 40
+ 105
°C Icc ≤ 35mA
mounted on
double-sided
- 40
+ 85
°C Icc > 35mA
single-layer
PCB
*1 : When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2 : When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3 : See " · C Pin" in "HANDLING DEVICES" for the connection of the smoothing capacitor.
*4 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
Operating
temperature
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
66
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
3. DC Characteristics
 Current rating
(Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol
RUN
mode
current
Pin
name
Icc
VCC
SLEEP
mode
current
Iccs
Conditions
CPU : 40MHz,
Peripheral : 40MHz,
Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*5
PLL
RUN mode CPU : 40MHz,
Peripheral : 40MHz,
Flash 3Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
*5
CPU/ Peripheral : 4MHz*2
High-speed
Flash 0Wait
CR
FRWTR.RWT = 00
RUN mode
FSYNDN.SD = 000
CPU/ Peripheral : 32kHz
Flash 0Wait
Sub
FRWTR.RWT = 00
RUN mode
FSYNDN.SD = 000
*6
CPU/ Peripheral : 100kHz
Low-speed
Flash 0Wait
CR
FRWTR.RWT = 00
RUN mode
FSYNDN.SD = 000
PLL
Peripheral : 40MHz
SLEEP mode *5
High-speed
CR
Peripheral : 4MHz*2
SLEEP mode
Sub
Peripheral : 32kHz
SLEEP mode *6
Low-speed
CR
Peripheral : 100kHz
SLEEP mode
Value
Unit Remarks
Typ*3 Max*4
32
41
mA
*1
21
28
mA
*1
3.9
7.7
mA
*1
0.15
3.2
mA
*1
0.2
3.3
mA
*1
10
15
mA
*1
1.2
4.4
mA
*1
0.1
3.1
mA
*1
0.1
3.1
mA
*1
*1 : When all ports are fixed.
*2 : When setting it to 4MHz by trimming.
*3 : Ta=+25°C, VCC=5.5V
*4 : Ta=+105°C, VCC=5.5V
*5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
67
D a t a S h e e t
(Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Pin
name
Parameter Symbol
Main
TIMER
mode
TIMER
mode
current
ICCT
VCC
STOP
mode
current
Value
Unit Remarks
Typ*2 Max*2
Conditions
Sub
TIMER
mode
ICCH
STOP mode
Ta = + 25°C,
When LVD is off
*3
Ta = + 105°C,
When LVD is off
*3
Ta = + 25°C,
When LVD is off
*4
Ta = + 105°C,
When LVD is off
*4
Ta = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
2.5
3
mA
*1
-
6
mA
*1
60
230
μA
*1
-
3.1
mA
*1
35
200
μA
*1
-
3
mA
*1
*1 : When all ports are fixed.
*2 : VCC=5.5V
*3 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
Conditions
At operation
for interrupt
Vcc = 5.5V
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Flash memory
write/erase
current
ICCFLASH
VCC
Conditions
At Write/Erase
Value
Typ
Max
Unit
11.4
mA
13.1
Remarks
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current
Reference power
supply current
68
CONFIDENTIAL
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
Value
Typ
Max
Unit
At 1unit
operation
0.57
0.72
mA
At stop
0.06
20
μA
At 1unit
operation
AVRH=5.5V
1.1
1.96
mA
At stop
0.06
4
μA
Conditions
Remarks
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol Pin name
"H" level
input
voltage
(hysteresis
input)
VIHS
"L" level input
voltage
(hysteresis
input)
VILS
"H" level
output voltage
"L" level
output voltage
Input leak
current
Pull-up
resistor
value
Input
capacitance
VOH
VOL
CMOS
hysteresis
input pin,
MD0,1
5V tolerant
I/O pin
CMOS
hysteresis
input pin,
MD0,1
Max
-
Vcc × 0.8
-
Vcc + 0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
Vss - 0.3
-
Vcc × 0.2
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.4
-
Vcc
V
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
-
-5
-
+5
μA
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
-
5
15
Vcc ≥ 4.5 V
IOH = - 4mA
4mA type
Vcc < 4.5 V
IOH = - 2mA
Vcc ≥ 4.5 V
IOH = - 12mA
12mA type
Vcc < 4.5 V
IOH = - 8mA
Vcc ≥ 4.5 V
IOH = - 20.5mA
P80, P81
Vcc < 4.5 V
IOH = - 13.0mA
Vcc ≥ 4.5 V
IOL = 4mA
4mA type
Vcc < 4.5 V
IOL = 2mA
Vcc ≥ 4.5 V
IOL = 12mA
12mA type
Vcc < 4.5 V
IOL = 8mA
Vcc ≥ 4.5 V
IOL = 18.5mA
P80, P81
Vcc < 4.5 V
IOL = 10.5mA
IIL
-
RPU
Pull-up pin
CIN
Other than
Vcc, Vss,
AVcc, AVss,
AVRH
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Min
Value
Typ
Conditions
Unit Remarks
kΩ
pF
69
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Pin
Symbol
Conditions
name
FCH
tCYLH
X0
X1
tCF
tCR
FCM
-
Value
Min
Max
Unit
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
PWH/tCYLH
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
-
-
40
MHz
MHz
MHz
ns
Remarks
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
When using external
clock
Master clock
Base clock
FCC
40
MHz
Internal operating
(HCLK/FCLK)
clock*1
FCP0
40
MHz APB0 bus clock*2
frequency
FCP1
40
MHz APB1 bus clock*2
FCP2
40
MHz APB2 bus clock*2
Base clock
25
ns
tCYCC
(HCLK/FCLK)
Internal operating
25
ns
APB0 bus clock*2
tCYCP0
clock*1
25
ns
APB1 bus clock*2
tCYCP1
cycle time
25
ns
APB2 bus clock*2
tCYCP2
*1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2 : For about each APB bus which each peripheral is connected to, see "BLOCK DIAGRAM" in this data
sheet.
X0
70
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
(2) Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input frequency
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Symbol
Conditions
name
Unit
FCL
X0A
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
(3) Built-in CR Oscillation Characteristics
 Built-in high-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRH
Min
Value
Typ
Max
Ta = + 25°C
3.96
4
4.04
Ta =
0°C to + 70°C
3.84
4
4.16
Conditions
Ta =
- 40°C to + 105°C
Ta =
- 40°C to + 105°C
Unit
Remarks
When trimming*1
MHz
3.8
4
4.2
3
4
5
When not trimming
Frequency
tCRWT
90
μs
*2
stability time
*1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2 : Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
 Built-in low-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
Conditions
FCRL
-
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
71
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input clock
of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time
(LOCK UP time)*1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
tLOCK
100
-
-
μs
fPLLI
fPLLO
FCLKPLL
4
13
200
-
-
16
75
300
40
MHz
multiple
MHz
MHz
USB clock frequency*3
FCLKSPLL
-
-
48
MHz
After the M frequency
division
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3 : For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family
PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the
input clock of the main PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time
tLOCK
100
μs
(LOCK UP time)*1
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiple rate
50
71
multiple
PLL macro oscillation clock frequency
fPLLO
190
300
MHz
Main PLL clock frequency*2
FCLKPLL
40
MHz
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
72
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
USB PLL connection
Main clock (CLKMO)
PLL input
clock
K
divider
PLL macro
oscillation clock
USB PLL
M
divider
USB
clock
N
divider
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
Pin
name
Value
Max
0
-
ms
1
-
ms
0.446
0.744
ms
Tr
Toff
Vcc
Tprt
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
RST Active
CPU Operation
Toff
Release
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions
・ VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "9. Low-Voltage Detection Characteristics"
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
73
D a t a S h e e t
(7) External Bus Timing
 External bus clock output Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
Vcc ≥ 4.5 V
40
MHz
Vcc < 4.5 V
32
MHz
MCLKOUT
Vcc
≥
4.5
V
25
ns
Minimum clock cycle
time
Vcc < 4.5 V
31.25
ns
Note: The external bus clock output is a divided clock of HCLK. For more information about setting of clock
divider, see "CHPATER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL"
When external bus clock is not output, this characteristic does not give any effect on external bus
operation.
Output frequency
tCYCLE
MCLKOUT
 External bus signal input/output Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Signal input characteristics
Signal output characteristics
74
CONFIDENTIAL
Symbol
Conditions
VIH
VIL
VOH
-
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Vcc ≥ 4.5V
MOEX
tOEW
MOEX
MCLK×n-3
Min pulse width
Vcc < 4.5V
Vcc ≥ 4.5V
-9
MCSX ↓→ Address
MCSX[7:0]
tCSL – AV
output delay time
MAD[24:0]
Vcc < 4.5V
-12
Vcc ≥ 4.5V
MOEX ↑ →
MOEX
tOEH - AX
0
Address hold time
MAD[24:0]
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×m-9
MCSX ↓→
tCSL - OEL
MOEX ↓ delay time
Vcc < 4.5V MCLK×m-12
MOEX
MCSX[7:0]
Vcc ≥ 4.5V
MOEX ↑ →
tOEH - CSH
0
MCSX ↑ time
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×m-9
MCSX ↓ →
MCSX
tCSL - RDQML
MDQM ↓ delay time
MDQM[1:0]
Vcc < 4.5V MCLK×m-12
Vcc ≥ 4.5V
20
Data set up →
MOEX
tDS - OE
MOEX ↑ time
MADATA[15:0]
Vcc < 4.5V
38
Vcc ≥ 4.5V
MOEX ↑ →
MOEX
tDH - OE
0
Data hold time
MADATA[15:0]
Vcc < 4.5V
Vcc ≥ 4.5V
MWEX
tWEW
MWEX
MCLK×n-3
Min pulse width
Vcc < 4.5V
Vcc ≥ 4.5V
MWEX ↑ → Address
MWEX
tWEH - AX
0
output delay time
MAD[24:0]
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×n-9
MCSX ↓ →
tCSL - WEL
MWEX ↓ delay time
Vcc < 4.5V MCLK×n-12
MWEX
MCSX[7:0]
Vcc ≥ 4.5V
MWEX ↑ →
tWEH - CSH
0
MCSX ↑ delay time
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×n-9
MCSX ↓ →
MCSX
tCSL-WDQML
MDQM ↓ delay time
MDQM[1:0]
Vcc < 4.5V MCLK×n-12
Vcc ≥ 4.5V
MCLK-9
MCSX ↓ →
MCSX
tCSL - DV
Data output time
MADATA[15:0]
Vcc < 4.5V
MCLK-12
Vcc ≥ 4.5V
MWEX ↑ →
MWEX
tWEH - DX
0
Data hold time
MADATA[15:0]
Vcc < 4.5V
Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16).
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Max
+9
+ 12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
75
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
76
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK
MAD[24:0]
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
tCSL
MCLK
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑→
Data hold time
MCLK
MADATA[15:0]
MCLK
MADATA[15:0]
tDS
tDH
tWEL
MCLK
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
MCLK
MDQM[1:0]
tDQMH
MCLK ↑ →
MCLK,
tODS
MADATA[15:0]
Data output time
MCLK ↑ →
MCLK
tOD
Data output time
MADATA[15:0]
Note: When the external load capacitance CL = 30pF.
Value
Min
Unit
Max
9
12
9
12
9
12
9
12
9
12
1
1
1
1
1
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
77
D a t a S h e e t
 Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Vcc ≥ 4.5V
Vcc < 4.5V
0
10
20
Vcc ≥ 4.5V
MCLK×n+0
MCLK×n+10
Vcc < 4.5V
MCLK×n+0
Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16).
MCLK×n+20
Multiplexed
Address delay time
tALE-CHMADV
Multiplexed
Address hold time
tCHMADH
MALE
MADATA[15:0]
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
78
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
MCLK
ALE
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
tCHMADV
Address delay time
MCLK
MADATA[15:0]
MCLK ↑ →
Multiplexed
tCHMADX
Data output time
Note: When the external load capacitance CL = 30pF.
Vcc ≥ 4.5V
Min
Value
Max
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
79
D a t a S h e e t
 External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
MCLK ↑
MRDY input
setup time
tRDYI
Pin name Conditions
MCLK
MRDY
Value
Min
Vcc ≥ 4.5V
19
Vcc < 4.5V
37
Max
-
Unit
Remarks
ns
 When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
 When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
80
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
(8) Base Timer Input Timing
 Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK,TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
 Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this
data sheet.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
81
D a t a S h e e t
(9) CSIO/UART Timing
 CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑→ SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tcycp
-
4tcycp
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tcycp 10
tcycp +
10
-
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
 The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30pF.
82
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
SIN
tSHIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
83
D a t a S h e e t
 CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tcycp
-
4tcycp
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tcycp 10
tcycp +
10
-
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
 The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30pF.
84
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
SIN
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
85
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK ↑→ SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
Vcc < 4.5V
Min
Max
SCKx
4tcycp
SCKx
- 30
SOTx
SCKx
50
SINx Master mode
SCKx
0
SINx
SCKx
2tcycp SOTx
30
2tcycp SCKx
10
tcycp +
SCKx
10
SCKx
SOTx
Slave mode
SCKx
10
SINx
SCKx
20
SINx
SCKx
SCKx
-
Vcc ≥ 4.5V
Min
Max
Unit
-
4tcycp
-
ns
+ 30
- 20
+ 20
ns
-
30
-
ns
-
0
-
ns
-
ns
-
ns
-
ns
-
2tcycp 30
2tcycp 10
tcycp +
10
50
-
30
ns
-
10
-
ns
-
20
-
ns
5
5
-
5
5
ns
ns
 The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30pF.
86
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
87
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Pin
Symbol
Conditions
name
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tcycp
-
4tcycp
-
ns
SCK ↓→ SOT delay time
tSLOVI
SCKx
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ →SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tcycp 30
2tcycp 10
tcycp +
10
-
2tcycp 30
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
 The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30pF.
88
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
tR
SCK
VIL
tSLSH
VIH
VIH
tF
VIL
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
 UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
CL = 30pF
tR
SCK
VIL
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Min
Max
tcycp + 10
tcycp + 10
-
5
5
tSHSL
VIH
VIL
ns
ns
ns
ns
tF
tSLSH
VIH
Unit Remarks
VIL
VIH
89
D a t a S h e e t
(10) External input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Pin name
Conditions
Value
Unit
Min
Max
ADTG
FRCKx
-
2tCYCP*
-
ns
-
2tCYCP*
-
ns
ICxx
Input pulse width
tINH
tINL
DTTIxX
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
generator
Except
2tCYCP + 100*
ns
Timer mode,
INTxx,
External interrupt
Stop mode
NMIX
NMI
Timer mode,
500
ns
Stop mode
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are
connected to, see "BLOCK DIAGRAM" in this data sheet.
90
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
BIN rise time from
PC_Mode2 or
tAUBU
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBUAD
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tADBD
AIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
tBDAU
BIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
2tCYCP *
ns
tBUAU
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tAUBD
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBDAD
BIN pin "L" level
PC_Mode3
BIN rise time from
PC_Mode2 or
tADBU
AIN pin "L" level
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC = "0"
ZIN pin "L" width
tZLL
QCR:CGSC = "0"
AIN/BIN rise and fall time
tZABE
QCR:CGSC = "1"
from determined ZIN level
Determined ZIN level from
tABEZ
QCR:CGSC = "1"
AIN/BIN rise and fall time
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK
DIAGRAM" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
tBLL
91
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
92
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
2
(12) I C timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Standard-mode Fast-mode
Min
Max
Min Max
Unit Remarks
SCL clock frequency
FSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓→ SCL ↓
SCLclock "L" width
tLOW
4.7
1.3
μs
SCLclock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START condition
setup time
tSUSTA
4.7
0.6
μs
CL = 30pF,
SCL ↑ → SDA ↓
R=
Data hold time
1
tHDDAT (Vp/IOL)*
0
3.45*2
0
0.9*3
μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
tBUF
4.7
1.3
μs
"START condition"
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
93
D a t a S h e e t
(13) ETM timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Data hold
TRACECLK
frequency
Symbol
Pin name
tETMH
TRACECLK
TRACED[3:0]
Conditions
Value
Unit
Min Max
Vcc ≥ 4.5V
2
9
Vcc < 4.5V
2
15
Vcc ≥ 4.5V
-
40
MHz
Vcc < 4.5V
-
32
MHz
Vcc ≥ 4.5V
25
-
ns
Vcc < 4.5V
31.25
-
ns
Remarks
ns
1/tTRACE
TRACECLK
TRACECLK
Clock cycle time
tTRACE
Note: When the external load capacitance CL = 30pF.
HCLK
TRACECLK
TRACED[3:0]
94
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
(14) JTAG timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
TMS, TDI setup time
tJTAGS
tJTAGH
TCK
TMS,TDI
TCK
TMS,TDI
tJTAGD
TCK
TDO
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
TMS, TDI hold time
TDO delay time
Vcc < 4.5V
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note: When the external load capacitance CL = 30pF.
TCK
TMS/TDI
TDO
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
95
D a t a S h e e t
5. 12-bit A/D Converter
 Electrical Characteristics for the A/D Converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter
Resolution
Integral
Nonlinearity
Differential
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Pin
Symbol
name
Min
Value
Typ
Max
Unit
-
-
-
-
12
bit
-
-
-
± 1.7
± 4.5
LSB
-
-
-
± 1.7
± 2.5
LSB
VZT
ANxx
-
±8
± 15
mV
VFST
ANxx
1.0*
1.2*1
*2
*2
-
-
μs
-
-
ns
-
50
-
2000
ns
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistor
RAIN
-
-
-
-
-
Ts
-
Compare clock cycle*3
Tcck
State transition time to
operation permission
Sampling time
AVRH = 2.7V to 5.5V
AVRH±8 AVRH±15 mV
1
Conversion time
Remarks
2
3.8
4
kΩ
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
Interchannel disparity
LSB
Analog port input
ANxx
5
μA
current
Analog input voltage
ANxx
AVSS
AVRH
V
Reference voltage
AVRH
2.7
AVCC
V
*1 : The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5V, HCLK=40MHz sampling time: 300ns, compare time: 700ns
AVcc < 4.5V, HCLK=40MHz sampling time: 500ns, compare time: 700ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at
Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this
data sheet.
*2 : A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3 : The compare time (Tc) is the value of (Equation 2)
96
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
Rext
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9
Ts
: Sampling time
RAIN : Input resistor of A/D = 2kΩ
4.5 ≤ AVCC ≤ 5.5
Input resistor of A/D = 3.8kΩ
2.7 ≤ AVCC < 4.5
CAIN : Input capacity of A/D = 12.9pF 2.7 ≤ AVCC ≤ 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc
Tcck
: Compare time
: Compare clock cycle
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
97
D a t a S h e e t
 Definition of 12-bit A/D Converter Terms
 Resolution
 Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion
characteristics.
 Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Ideal characteristics
0xN
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
98
CONFIDENTIAL
:
:
:
:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
6.
USB characteristics
(Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input
characteristics
Symbol
Pin
Conditions
name
Input High level voltage
VIH
-
Input Low level voltage
VIL
-
VDI
-
VCM
-
Differential input
sensitivity
Different common mode
range
Min
2.0
Vss 0.3
Value
Max
Unit Remarks
USBVcc + 0.3 V
*1
0.8
V
*1
0.2
-
V
*2
0.8
2.5
V
*2
External
pull-down
Output High level voltage
VOH
2.8
3.6
V *3
resistance
= 15kΩ
UDP0,
External
UDM0
pull-up
Output Low level voltage
VOL
0.0
0.3
V *3
resistance
Output
= 1.5kΩ
charact- Crossover voltage
VCRS
1.3
2.0
V *4
eristics Rising time
tFR
Full Speed
4
20
ns *5
Falling time
tFF
Full Speed
4
20
ns *5
Rise/fall time matching
tFRFM
Full Speed
90
111.11
% *5
Output impedance
ZDRV
Full Speed
28
44
Ω *6
Rising time
tLR
Low Speed
75
300
ns *7
Falling time
tLF
Low Speed
75
300
ns *7
Rise/fall time matching
tLRFM
Low Speed
80
125
% *7
*1 : The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hystereses to lower noise sensitivity.
Minimum differential input
sensitivity [V]
*2 : Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within
0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
December 16, 2014, MB9A310A-DS706-00012-3v0-E
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99
D a t a S h e e t
*3 : The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to the ground and 1.5 kΩ load) at High-State (VOH).
*4 : The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5 : They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
100
CONFIDENTIAL
Falling time
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
*6 : USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic
impedance(Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28Ωto 44Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7 : They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See "· Low-Speed Load (Compliance Load)" for conditions of external load.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
101
D a t a S h e e t
 Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
 Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
 Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
102
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
7.
Low-voltage detection characteristics
 Low-voltage detection reset
(Ta = - 40°C to + 105°C)
Parameter
Detected voltage
Released voltage
Symbol Conditions
VDL
VDH
-
Min
Value
Typ Max
2.25
2.30
2.45
2.50
Min
Value
Typ Max
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
 Interrupt of low-voltage detection
(Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Unit
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
2240 ×
tcycp *
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
* : tCYCP indicates the APB2 bus clock cycle time.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
103
D a t a S h e e t
8.
Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Large Sector
Small Sector
Value
Typ*
Max*
0.7
0.3
3.7
1.1
Unit
Remarks
Includes write time prior to
internal erase
Half word (16 bit)
Not including system-level
12
384
μs
write time
overhead time.
64K/128K/256KByte
5.2
23.6
s
Chip
Includes write time prior to
erase time
internal erase
384K/512KByte
8
38.4
s
* : The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
Sector erase time
s
(2) Erase/write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
1,000
20*
10,000
100,000
* : At average + 85C
104
CONFIDENTIAL
Remarks
10*
5*
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
9.
Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from
receiving the return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Value
Typ
Max*
tCYCC
Unit
ns
40
80
μs
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Low-speed CR TIMER mode
Ticnt
Remarks
* : The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : External interrupt is set to detecting fall edge.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
105
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
106
CONFIDENTIAL
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from
releasing reset to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Typ
Max*
308
444
μs
308
444
μs
428
684
μs
Sub TIMER mode
428
684
μs
STOP mode
428
684
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
* : The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Start
107
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
* : Internal resource reset
Notes:
108
CONFIDENTIAL
Start
is not included in return factor by the kind of Low-Power consumption mode.
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■ELECTRICAL CHARACTERISTICS" for the detail
on the time during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 ORDERING INFORMATION
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9AF311LAPMC1-G-JNE2
64Kbyte
16Kbyte
MB9AF312LAPMC1-G-JNE2
128Kbyte
16Kbyte
MB9AF314LAPMC1-G-JNE2
256Kbyte
32Kbyte
MB9AF311LAPMC-G-JNE2
64Kbyte
16Kbyte
MB9AF312LAPMC-G-JNE2
128Kbyte
16Kbyte
MB9AF314LAPMC-G-JNE2
256Kbyte
32Kbyte
MB9AF311LAQN-G-AVE2
64Kbyte
16Kbyte
MB9AF312LAQN-G-AVE2
128Kbyte
16Kbyte
MB9AF314LAQN-G-AVE2
256Kbyte
32Kbyte
MB9AF311MAPMC-G-JNE2
64Kbyte
16Kbyte
MB9AF312MAPMC-G-JNE2
128Kbyte
16Kbyte
MB9AF314MAPMC-G-JNE2
256Kbyte
32Kbyte
MB9AF315MAPMC-G-JNE2
384Kbyte
32Kbyte
MB9AF316MAPMC-G-JNE2
512Kbyte
32Kbyte
MB9AF311NAPMC-G-JNE2
64Kbyte
16Kbyte
MB9AF312NAPMC-G-JNE2
128Kbyte
16Kbyte
MB9AF314NAPMC-G-JNE2
256Kbyte
32Kbyte
MB9AF315NAPMC-G-JNE2
384Kbyte
32Kbyte
MB9AF316NAPMC-G-JNE2
512Kbyte
32Kbyte
MB9AF311NAPF-G-JNE1
64Kbyte
16Kbyte
MB9AF312NAPF-G-JNE1
128Kbyte
16Kbyte
MB9AF314NAPF-G-JNE1
256Kbyte
32Kbyte
MB9AF315NAPF-G-JNE1
384Kbyte
32Kbyte
MB9AF316NAPF-G-JNE1
512Kbyte
32Kbyte
MB9AF311NABGL-GE1
64Kbyte
16Kbyte
MB9AF312NABGL-GE1
128Kbyte
16Kbyte
MB9AF314NABGL-GE1
256Kbyte
32Kbyte
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Package
Packing
Plastic  LQFP
(0.5mm pitch),64-pin
(FPT-64P-M38)
Plastic  LQFP
(0.65mm pitch),64-pin
(FPT-64P-M39)
Plastic  QFN
(0.5mm pitch),64-pin
(LCC-64P-M24)
Plastic  LQFP
(0.5mm pitch),80-pin
(FPT-80P-M37)
Tray
Plastic  LQFP
(0.5mm pitch),100-pin
(FPT-100P-M23)
Plastic  QFP
(0.65mm pitch), 100-pin
(FPT-100P-M06)
Plastic  PFBGA
(0.8mm pitch),112-pin
(BGA-112P-M04)
109
D a t a S h e e t
 PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
0°~8°
0.50±0.20
(.020±.008)
26
"A"
1
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
110
CONFIDENTIAL
0.60±0.15
(.024±.006)
25
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
"A"
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
111
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551 ± .008)SQ
*12.00± 0.10(.472 ± .004)SQ
60
0.145± 0.055
(.006 ± .002)
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.05
(.004 ± .002)
(Stand off)
21
"A"
1
20
0.50(.020)
0.22± 0.05
(.009± .002)
C
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
112
CONFIDENTIAL
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145 ± 0.055
(.006 ± .002)
33
49
Details of "A" part
32
+0.20
0.08(.003)
1.50 –0.10
(Mounting height)
.059 +.008
–.004
0.25(.010)
0~8°
INDEX
64
17
1
0.22±0.05
(.009±.002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
0.10 ± 0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
113
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
49
32
+0.20
1.50 –0.10
+.008
.059 –.004
0.10(.004)
INDEX
64
16
0.65(.026)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
17
1
0.32±0.05
(.013±.002)
CONFIDENTIAL
0.10±0.10
(.004±.004)
0.25(.010)BSC
"A"
0.13(.005)
M
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
114
0~8˚
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
Ф 0.45 mm
Mounting height
1.45 mm Max.
Weight
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S B
0.80(.031)
REF
B
11
10
9
8
7
6
5
4
3
2
0.80(.031)
REF
A
10.00±0.10
(.394±.004)
1
L K J H G F
(INDEX AREA)
0.35±0.10
(.014±.004)
(Stand off)
0.20(.008) S A
1.25±0.20
(.049±.008)
(Seated height)
ED C B A
INDEX
112-Ф0.45±010
(112-Ф0.18±.004)
Ф0.08(.003) M S A B
S
0.10(.004) S
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
115
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Sealing method
Plastic mold
Mounting height
0.90 mm MAX
Weight
-
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.05 (.002) MAX
C
CONFIDENTIAL
0.40±0.05
(.016±.002)
(0.20 (.008))
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
116
0.50 (.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
 MAJOR CHANGES
Page
Section
Revision 1.0
Revision 2.0
-
-
-
PRODUCT LINEUP
Function Multi-function Serial
7
External Interrupts
34 to 37
SIGNAL DESCRIPTION
Multi-function Serial (ch.0 to ch.7)
I/O CIRCUIT TYPE
42, 43
51
54
69
71
72
79
88
HANDLING DEVICE
 Power supply pins
MEMORY SIZE
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1)Main Clock input Characteristics
(4-2) Operating Conditions of Main PLL 
(7) External Bus Timing
 External bus clock output Characteristics
(8) Base Timer Input Timing
 Trigger input timing
(10) External input timing 
5. 12-bit A/D Converter
(1) Electrical characteristics for the A/D
converter
94
Revision 2.1
Revision 3.0
FEATURES
2
USB Interface
FEATURES
3
External Bus Interface
9
PACKAGES
44, 46
I/O CIRCUIT TYPE
44, 45
I/O CIRCUIT TYPE
51
HANDLING DEVICES
HANDLING DEVICES
51
Crystal oscillator circuit
HANDLING DEVICES
52
C Pin
53
BLOCK DIAGRAM
December 16, 2014, MB9A310A-DS706-00012-3v0-E
CONFIDENTIAL
Change Results
Initial release
 Revised series name and part number:
MB9A310 Series → MB9A310A Series
MB9AF311L → MB9AF311LA
MB9AF312L → MB9AF312LA
MB9AF314L → MB9AF314LA
MB9AF311M → MB9AF311MA
MB9AF312M → MB9AF312MA
MB9AF314M → MB9AF314MA
MB9AF315M → MB9AF315MA
MB9AF316M → MB9AF316MA
MB9AF311N → MB9AF311NA
MB9AF312N → MB9AF312NA
MB9AF314N → MB9AF314NA
MB9AF315N → MB9AF315NA
MB9AF316N → MB9AF316NA
 Added the following package.
LCC-64P-M24
Added the following description.
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Corrected the following description.
7pins (Max) → 8pins (Max)
Corrected the description for function.
 Added "LIN pin"
 Deleted "UART pin"
 Corrected the following schematic for "TypeB".
CMOS level hysteresis input → Digital input
 Corrected the following schematic for "TypeC".
Control Pin → Digital output
Corrected the description.
Added "MEMORY SIZE ".
Added the items FCM to the Internal operating clock frequency.
Added the description.
Added the Note.
Corrected the footnote.
 Corrected the value of "Full-scale transition voltage".
Min: -20 → AVRH-20
Max: +20 → AVRH+20
 Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
 Corrected the value of "Reference voltage".
Min: AVSS → 2.7
Company name and layout design change
Added the description of PLL for USB
Added the description of Maximum area size
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Added the description of I2C to the type of E, F and I
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
117
D a t a S h e e t
Page
54
55
56, 57
Section
MEMORY SIZE
MEMORY MAP
· Memory map(1)
MEMORY MAP
· Memory map(2)(3)
64, 65
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
66
ELECTRICAL CHARACTERISTICS
2. Recommended Operation Conditions
67, 68
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current rating
71
72
73
75-77
82-89
96
105-108
109
110
118
CONFIDENTIAL
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1) Operating Conditions of Main and
USB PLL
(4-2) Operating Conditions of Main PLL
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(6) Power-on Reset Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) External Bus Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(8) CSIO/UART Timing
ELECTRICAL CHARACTERISTICS
5. 12bit A/D Converter
ELECTRICAL CHARACTERISTICS
9. Return Time from Low-Power
Consumption Mode
ORDERING INFORMATION
PACKAGE DIMENSIONS
Change Results
Changed to the following description
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
Modified the area of "Extarnal Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Added Frequency stability time at Built-in high-speed CR
· Added Main PLL clock frequency
· Added USB clock frequency
· Added the figure of Main PLL connection and USB PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Change to full part number
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
MB9A310A-DS706-00012-3v0-E, December 16, 2014
D a t a S h e e t
December 16, 2014, MB9A310A-DS706-00012-3v0-E
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D a t a S h e e t
120
CONFIDENTIAL
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2011-2014 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
122
CONFIDENTIAL
MB9A310A-DS706-00012-3v0-E, December 16, 2014