2.8 MB

The following document contains information on Cypress products.
MB9B100A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF102NA/RA, MB9BF104NA/RA, MB9BF105NA/RA,
MB9BF106NA/RA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B100A-DS706-00020
CONFIDENTIAL
Revision 2.0
Issue Date December 15, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
CONFIDENTIAL
MB9B100A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF102NA/RA, MB9BF104NA/RA, MB9BF105NA/RA,
MB9BF106NA/RA
Data Sheet (Full Production)
 DESCRIPTION
The MB9B100A Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9B100A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces
(UART,CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE0 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B100A-DS706-00020
Revision 3.0
Issue Date December 15, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 FEATURES
 32-bit ARM Cortex-M3 Core
・ Processor version: r2p0
・ Up to 80MHz Frequency Operation
・ Memory Protection Unit (MPU): improve the reliability of an embedded system
・ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・ 24-bit System timer (Sys Tick): System timer for OS task management
 On-chip Memories
[Flash memory]
・ Up to 512 Kbyte
・ Read cycle: [email protected] to 60MHz, 2wait-cycle* above
*: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle
・ Security function for code protection
[SRAM]
This series contain a total of up to 64Kbyte on-chip SRAM. This is composed of two independent
SRAM(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1
is connected to System bus.
・ SRAM0: Up to 32 Kbyte
・ SRAM1: Up to 32 Kbyte
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CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 Multi-function Serial Interface (Max. 8channels)
・ 4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・ Operation mode is selectable from the followings for each channel.
・ UART
・ CSIO
・ LIN
・ I 2C
[UART]
・ Full-duplex double buffer
・ Selection with or without parity supported
・ Built-in dedicated baud rate generator
・ External clock available as a serial clock
・ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・ Full-duplex double buffer
・ Built-in dedicated baud rate generator
・ Overrun error detect function available
[LIN]
・ LIN protocol Rev.2.1 supported
・ Full-duplex double buffer
・ Master/Slave mode supported
・ LIN break field generate (can be changed 13-16bit length)
・ LIN break delimiter generate (can be changed 1-4bit length)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
・ Standard-mode (Max.100kbps) / Fast-mode (Max.400Kbps) supported
 External Bus Interface
・ Supports SRAM, NOR& NAND Flash device
・ Up to 8 chip selects
・ 8/16-bit Data width
・ Up to 25-bit Address bit
・ Maximum area size : Up to 256 Mbytes
 DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・ 8 independently configured and operated channels
・ Transfer can be started by software or request from the built-in peripherals
・ Transfer address area: 32bit(4Gbyte)
・ Transfer mode: Block transfer/Burst transfer/Demand transfer
・ Transfer data type: byte/half-word/word
・ Transfer block count: 1 to 16
・ Number of transfers: 1 to 65536
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CONFIDENTIAL
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D a t a S h e e t
 A/D Converter (Max. 16channels)
[12-bit A/D Converter]
・ Successive Approximation Register type
・ Built-in 3unit
・ Conversion time: [email protected]
・ Priority conversion available (priority at 2levels)
・ Scanning conversion mode
・ Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
 Base Timer (Max. 8channels)
Operation mode is selectable from the followings for each channel.
・ 16-bit PWM timer
・ 16-bit PPG timer
・ 16/32-bit reload timer
・ 16/32-bit PWC timer
 Multi-function Timer (Max. 2units)
The Multi-function timer is composed of the following blocks.
・ 16-bit free-run timer × 3ch/unit
・ Input capture × 4ch/unit
・ Output compare × 6ch/unit
・ A/D activation compare × 3ch/unit
・ Waveform generator × 3ch/unit
・ 16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor control.
・ PWM signal output function
・ DC chopper waveform output function
・ Dead time function
・ Input capture function
・ A/D convertor activate function
・ DTIF (Motor emergency stop) interrupt function
 Quadrature Position/Revolution Counter (QPRC) (Max. 2units)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・ 16-bit position counter
・ 16-bit revolution counter
・ Two 16-bit compare registers
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CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 Dual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
 Watch Counter
The Watch counter is used for wake up from sleep mode.
・ Interval timer: up to 64s(Max.)@ Sub Clock : 32.768kHz
 Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore,”Hardware"
watchdog is active in any low-power consumption modes except STOP mode.
 External Interrupt Controller Unit
・ Up to 16 external vectors
・ Include one non-maskable interrupt(NMI)
 General Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
・ Capable of pull-up control per pin
・ Capable of reading pin level directly
・ Built-in the port relocate function
・ Up to 100 high-speed general-purpose I/O [email protected] Package
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
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CONFIDENTIAL
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D a t a S h e e t
 Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that are dynamically selectable.
・ Main Clock
・ Sub Clock
・ Built-in high-speed CR Clock
・ Built-in low-speed CR Clock
・ Main PLL Clock
: 4MHz to 48MHz
: 32.768kHz
: 4MHz
: 100kHz
[Resets]
・ Reset requests from INITX pins
・ Power-on reset
・ Software reset
・ Watchdog timers reset
・ Low-voltage detector reset
・ Clock supervisor reset
 Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
 Low Voltage Detector (LVD)
This series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has
been set, Low Voltage Detector generates an interrupt or reset.
・ LVD1: error reporting via interrupt
・ LVD2: auto-reset operation
 Low-Power Consumption Mode
Three low-power consumption modes supported.
・ SLEEP
・ TIMER
・ STOP
 Debug
・ Serial Wire JTAG Debug Port (SWJ-DP)
・ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
 Power Supply
・ VCC
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CONFIDENTIAL
= 2.7V to 5.5V: Correspond to the wide range voltage.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 PRODUCT LINEUP
 Memory size
Product device
MB9BF102NA/RA MB9BF104NA/RA MB9BF105NA/RA MB9BF106NA/RA
On-chip
Flash memory
On-chip SRAM
128Kbyte
256Kbyte
384Kbyte
512Kbyte
16Kbyte
32Kbyte
48Kbyte
64Kbyte
 Function
MB9BF102NA
MB9BF104NA
MB9BF105NA
MB9BF106NA
Product device
Pin count
100
120
Cortex-M3
80MHz
2.7V to 5.5V
8ch
CPU
Freq.
Power supply voltage range
DMAC
Addr:25bit (Max.)
Data:8/16 bit
CS:5(Max.)
Support: SRAM, NOR Flash
External Bus Interface
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
Addr:25bit (Max.)
Data:8/16 bit
CS:8(Max.)
Support: SRAM, NOR & NAND
Flash
8ch (Max.)
8ch (Max.)
(PWC/ Reload timer/PWM/PPG)
A/D activation compare
Input capture
MF- Free-run timer
Timer Output compare
Waveform generator
PPG
QPRC
Dual Timer
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12 bit A/D converter
CSV (Clock Super Visor)
MB9BF102RA
MB9BF104RA
MB9BF105RA
MB9BF106RA
3ch.
4ch.
3ch.
6ch.
3ch.
3ch.
2 units (Max.)
2ch (Max.)
1 unit
1 unit
Yes
1ch(SW) + 1ch(HW)
16pins (Max.)+ NMI × 1
80pins (Max.)
100pins (Max.)
16ch (3 units)
Yes
2ch
LVD (Low Voltage Detector)
High-speed
4MHz
Built-in CR
Low-speed
100kHz
Debug Function
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation
Characteristics" for accuracy of built-in CR.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
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D a t a S h e e t
 PACKAGES
Product name
Package
LQFP: FPT-100P-M23 (0.5mm pitch)
LQFP: FPT-120P-M37 (0.5mm pitch)
BGA:
BGA-112P-M04 (0.8mm pitch)
: Supported
MB9BF102NA
MB9BF104NA
MB9BF105NA
MB9BF106NA
MB9BF102RA
MB9BF104RA
MB9BF105RA
MB9BF106RA



-
Note : Refer to "PACKAGE DIMENSIONS" for detailed information on each package.
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CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 PIN ASSIGNMENT
 FPT-100P-M23
(TOP VIEW)
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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D a t a S h e e t
 FPT-120P-M37
(TOP VIEW)
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 BGA-112P-M04
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
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D a t a S h e e t
 LIST OF PIN FUNCTIONS
 List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin no.
LQFP-100 BGA-112 LQFP-120
12
CONFIDENTIAL
1
B1
1
2
C1
2
3
C2
3
4
B3
4
5
D1
5
6
D2
6
Pin name
VCC
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
(PPG10_0)
MDATA0
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
RTO11_0
(PPG10_0)
MDATA1
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
RTO12_0
(PPG12_0)
MDATA2
P53
SIN6_0
TIOA1_2
INT07_2
RTO13_0
(PPG12_0)
MDATA3
P54
SOT6_0
(SDA6_0)
TIOB1_2
RTO14_0
(PPG14_0)
MDATA4
I/O circuit
type
Pin state
type
-
E
H
E
H
E
H
E
H
E
I
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
I/O circuit
type
Pin state
type
E
I
E
H
9
MCSX7
P57
SOT1_0
(SDA1_0)
E
I
10
MNALE
P58
SCK1_0
(SCL1_0)
E
I
E
H
E
I
E
I
E
H
Pin name
P55
SCK6_0
(SCL6_0)
7
D3
7
ADTG_1
RTO15_0
(PPG14_0)
MDATA5
P56
SIN1_0
(120pin only)
8
D5
8
INT08_2
DTTI1X_0
-
-
-
-
MNCLE
P59
SIN7_0
-
-
-
-
-
-
11
12
13
INT09_2
MNWEX
P5A
SOT7_0
(SDA7_0)
MNREX
P5B
SCK7_0
(SCL7_0)
P30
AIN0_0
9
E1
14
TIOB0_1
INT03_2
MDATA6
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13
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
14
CONFIDENTIAL
10
E2
15
11
E3
16
12
E4
17
13
F1
18
14
F2
19
15
F3
20
16
G1
21
17
G2
22
Pin name
P31
BIN0_0
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
MDATA7
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
MDQM0
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MDQM1
P34
FRCK0_0
TIOB4_1
MAD24
P35
IC03_0
TIOB5_1
INT08_1
MAD23
P36
IC02_0
SIN5_2
INT09_1
MCSX3
P37
IC01_0
SOT5_2
(SDA5_2)
INT10_1
MCSX2
P38
IC00_0
SCK5_2
(SCL5_2)
INT11_1
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
I
E
H
E
H
E
H
E
H
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
18
F4
23
19
G3
24
-
B2
-
20
H1
25
21
H2
26
22
G4
27
23
H3
28
24
J2
29
25
26
L1
J1
30
31
27
J4
32
28
L5
33
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin name
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
TIOA0_1
VSS
P3B
RTO01_0
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
TIOA3_1
P3E
RTO04_0
(PPG04_0)
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
MAD22
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
MAD21
I/O circuit
type
Pin state
type
E
I
G
I
-
G
I
G
I
G
I
G
I
G
I
-
G
H
G
H
15
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
29
K5
34
30
J5
35
-
K2
J3
H4
-
31
H5
36
Pin name
P42
TIOA2_0
RTO12_1
(PPG12_1)
MAD20
P43
TIOA3_0
RTO13_1
(PPG12_1)
ADTG_7
MAD19
VSS
VSS
VSS
P44
TIOA4_0
RTO14_1
(PPG14_1)
I/O circuit
type
Pin state
type
G
I
G
I
-
G
I
G
I
MAD18
P45
TIOA5_0
32
L6
37
33
34
35
L2
L4
K1
38
39
40
36
L3
41
37
K3
42
38
K4
43
39
K6
44
RTO15_1
(PPG14_1)
MAD17
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
DTTI1X_1
INT14_1
D
M
D
N
B
C
E
H
E
I
SIN3_2
MAD16
P49
TIOB0_0
IC10_1
40
J6
45
AIN0_1
SOT3_2
(SDA3_2)
MAD15
16
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
Pin name
I/O circuit
type
Pin state
type
E
I
E
I
E
I
E
I
E
H
E
I
E
H
E
H
P4A
TIOB1_0
IC11_1
41
L7
46
BIN0_1
SCK3_2
(SCL3_2)
42
K7
47
43
H6
48
MAD14
P4B
TIOB2_0
IC12_1
ZIN0_1
MAD13
P4C
TIOB3_0
IC13_1
SCK7_1
(SCL7_1)
AIN1_2
MAD12
P4D
TIOB4_0
FRCK1_1
44
J7
49
SOT7_1
(SDA7_1)
BIN1_2
MAD11
P4E
TIOB5_0
INT06_2
45
K8
50
SIN7_1
ZIN1_2
-
-
51
-
-
52
MAD10
P70
TIOA4_2
P71
INT13_2
TIOB4_2
-
-
53
P72
SIN2_0
INT14_2
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D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
-
-
54
Pin name
P73
SOT2_0
(SDA2_0)
I/O circuit
type
Pin state
type
E
H
INT15_2
-
-
55
P74
SCK2_0
(SCL2_0)
E
I
46
K9
56
MD1
C
D
47
L8
57
MD0
C
D
48
L9
58
X0
A
A
49
L10
59
X1
A
B
50
L11
60
VSS
-
51
K11
61
VCC
-
52
J11
62
P10
AN00
F
K
F
L
P11
53
J10
63
AN01
SIN1_1
INT02_1
-
K10
-
VSS
-
-
J9
-
VSS
-
54
55
56
J8
H10
H9
64
65
66
P12
AN02
SOT1_1
(SDA1_1)
MAD09
P13
AN03
SCK1_1
(SCL1_1)
MAD08
P14
AN04
SIN0_1
F
K
F
K
F
L
F
K
INT03_1
57
H7
67
MCSX1
P15
AN05
SOT0_1
(SDA0_1)
MCSX0
18
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
58
59
G10
G9
68
69
Pin name
P16
AN06
SCK0_1
(SCL0_1)
MOEX
P17
AN07
SIN2_2
I/O circuit
type
Pin state
type
F
K
F
L
INT04_1
60
61
62
H11
F11
G11
70
71
72
63
G8
73
64
F10
74
65
F9
75
-
H8
-
66
E11
76
67
E10
77
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
MWEX
AVCC
AVRH
AVSS
P18
AN08
SOT2_2
(SDA2_2)
MDATA8
P19
AN09
SCK2_2
(SCL2_2)
MDATA9
P1A
AN10
SIN4_1
INT05_1
IC00_1
MDATA10
VSS
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
MDATA11
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
MDATA12
-
F
K
F
K
F
L
-
F
K
F
K
19
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
68
F8
78
69
E9
79
70
D11
80
-
-
81
-
-
82
-
-
83
-
-
84
-
B10
C9
-
-
-
85
Pin name
P1D
AN13
CTS4_1
IC03_1
MDATA13
P1E
AN14
RTS4_1
DTTI0X_1
MDATA14
P1F
AN15
ADTG_5
FRCK0_1
MDATA15
P28
ADTG_4
RTO05_1
(PPG04_1)
MCSX6
P27
INT02_2
RTO04_1
(PPG04_1)
MCSX5
P26
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
MCSX4
P25
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
VSS
VSS
P24
SIN2_1
INT01_2
I/O circuit
type
Pin state
type
F
K
F
K
F
K
E
I
E
H
E
I
E
I
-
E
H
RTO01_1
(PPG00_1)
20
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
Pin name
I/O circuit
type
Pin state
type
E
I
E
I
E
H
E
H
P23
SCK0_0
(SCL0_0)
71
D10
86
TIOA7_1
RTO00_1
(PPG00_1)
72
E8
87
P22
SOT0_0
(SDA0_0)
TIOB7_1
ZIN1_1
P21
SIN0_0
73
C11
88
INT06_1
BIN1_1
74
C10
89
75
76
A11
A10
90
91
77
A9
92
78
B9
93
79
B11
94
80
A8
95
81
B8
96
82
C8
97
-
D8
-
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
P20
INT05_0
CROUT
AIN1_1
VSS
VCC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
VSS
E
E
E
E
E
E
E
E
E
E
E
F
-
21
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
83
D9
98
Pin name
P06
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
I/O circuit
type
Pin state
type
E
F
E
G
E
G
E
G
E
H
E
I
E
I
E
I
INT01_1
84
A7
99
P07
TRACED2
ADTG_0
SCK4_2
(SCL4_2)
85
B7
100
P08
TRACED3
TIOA0_2
CTS4_2
86
C7
101
P09
TRACECLK
TIOB0_2
RTS4_2
P0A
SIN4_0
87
D7
102
INT00_2
FRCK1_0
MAD07
P0B
SOT4_0
(SDA4_0)
88
A6
103
TIOB6_1
IC10_0
22
CONFIDENTIAL
89
B6
104
90
C6
105
MAD06
P0C
SCK4_0
(SCL4_0)
TIOA6_1
IC11_0
MAD05
P0D
RTS4_0
TIOA3_2
IC12_0
MAD04
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
91
A5
106
-
D4
C3
-
92
B5
107
-
-
108
-
-
109
-
-
110
-
-
111
-
-
112
93
D6
-
-
94
C5
114
95
B4
115
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
113
Pin name
P0E
CTS4_0
TIOB3_2
IC13_0
MAD03
VSS
VSS
P0F
NMIX
MAD02
P68
SCK3_0
(SCL3_0)
TIOB7_2
INT12_2
P67
SOT3_0
(SDA3_0)
TIOA7_2
P66
SIN3_0
ADTG_8
INT11_2
P65
TIOB7_0
SCK5_1
(SCL5_1)
P64
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
P63
INT03_0
MAD01
SIN5_1
P62
SCK5_0
(SCL5_0)
ADTG_3
MAD00
P61
SOT5_0
(SDA5_0)
TIOB2_2
I/O circuit
type
Pin state
type
E
I
E
J
E
H
E
I
E
H
E
I
E
H
E
H
E
I
E
I
23
D a t a S h e e t
Pin no.
LQFP-100 BGA-112 LQFP-120
24
CONFIDENTIAL
96
C4
116
97
98
99
100
A4
A3
A2
A1
117
118
119
120
Pin name
P60
SIN5_0
TIOA2_2
INT15_1
VCC
P80
P81
VSS
I/O circuit
type
Pin state
type
E
H
H
H
O
O
-
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Module
Pin name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base Timer
0
Base Timer
1
Base Timer
2
Function
A/D converter external trigger input pin.
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin.
Base timer ch.0 TIOB pin.
Base timer ch.1 TIOA pin.
Base timer ch.1 TIOB pin.
Base timer ch.2 TIOA pin.
Base timer ch.2 TIOB pin.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
A7
D3
F4
C5
D11
E4
J5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
99
7
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
32
24
100
45
14
101
33
25
5
46
15
6
34
26
116
47
16
115
25
D a t a S h e e t
Module
Pin name
Base Timer
3
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
26
CONFIDENTIAL
Function
Base timer ch.3 TIOA pin.
Base timer ch.3 TIOB pin.
Base timer ch.4 TIOA pin.
Base timer ch.4 TIOB pin.
Base timer ch.5 TIOA pin.
Base timer ch.5 TIOB pin.
Base timer ch.6 TIOA pin.
Base timer ch.6 TIOB pin.
Base timer ch.7 TIOA pin.
Base timer ch.7 TIOB pin.
Pin No.
LQFP- BGA- LQFP100 112 120
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
89
88
71
72
-
J5
G4
C6
H6
E4
A5
H5
H3
J7
F1
L6
J2
C8
K8
F2
D9
B6
A6
D10
E8
-
35
27
105
48
17
106
36
28
51
49
18
52
37
29
97
50
19
98
104
103
112
86
109
111
87
108
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
Debugger
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00
MAD01
MAD02
MAD03
MAD04
MAD05
MAD06
MAD07
MAD08
MAD09
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
MAD16
MAD17
MAD18
MAD19
MAD20
MAD21
MAD22
MAD23
MAD24
MCSX0
MCSX1
MCSX2
MCSX3
MCSX4
MCSX5
MCSX6
MCSX7
External
Bus
Function
Serial wire debug interface clock input.
Serial wire debug interface data input / output.
Serial wire viewer output.
J-TAG test clock input.
J-TAG test data input.
J-TAG debug data output.
J-TAG test mode state input/output.
Trace CLK output of ETM.
Trace data output of ETM.
J-TAG test reset Input.
External bus interface address bus.
External bus interface chip select output pin.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
78
80
81
78
79
81
80
86
82
83
84
85
77
94
93
92
91
90
89
88
87
55
54
45
44
43
42
41
40
39
32
31
30
29
28
27
14
13
57
56
16
15
8
B9
A8
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
C5
D6
B5
A5
C6
B6
A6
D7
H10
J8
K8
J7
H6
K7
L7
J6
K6
L6
H5
J5
K5
L5
J4
F2
F1
H7
H9
G1
F3
D5
93
95
96
93
94
96
95
101
97
98
99
100
92
114
113
107
106
105
104
103
102
65
64
50
49
48
47
46
45
44
37
36
35
34
33
32
19
18
67
66
21
20
83
82
81
8
27
D a t a S h e e t
Module
Pin name
External
Bus
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
MDATA8
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
MDATA14
MDATA15
MDQM0
MDQM1
MNALE
MNCLE
MNREX
MNWEX
MOEX
MWEX
28
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
Function
External bus interface data bus.
External bus interface byte mask signal output.
External bus interface ALE signal to control NAND
Flash output pin.
External bus interface CLE signal to control NAND
Flash output pin.
External bus interface read enable signal to control
NAND Flash.
External bus interface write enable signal to control
NAND Flash.
External bus interface read enable signal for SRAM.
External bus interface write enable signal for SRAM.
2
3
4
5
6
7
9
10
63
64
65
66
67
68
69
70
11
12
C1
C2
B3
D1
D2
D3
E1
E2
G8
F10
F9
E11
E10
F8
E9
D11
E3
E4
2
3
4
5
6
7
14
15
73
74
75
76
77
78
79
80
16
17
-
-
9
-
-
10
-
-
12
-
-
11
58
59
G10
G9
68
69
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
Function
External interrupt request 00 input pin.
External interrupt request 01 input pin.
External interrupt request 02 input pin.
External interrupt request 03 input pin.
External interrupt request 04 input pin.
External interrupt request 05 input pin.
External interrupt request 06 input pin.
External interrupt request 07 input pin.
External interrupt request 08 input pin.
External interrupt request 09 input pin.
External interrupt request 10 input pin.
External interrupt request 11 input pin.
External interrupt request 12 input pin.
External interrupt request 13 input pin.
External interrupt request 14 input pin.
External interrupt request 15 input pin.
Non-Maskable Interrupt input.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
5
14
8
15
16
17
27
28
39
96
92
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
D1
F2
D5
F3
G1
G2
J4
L5
K6
C4
B5
2
97
102
3
98
85
4
63
82
113
66
14
17
69
15
89
75
16
88
50
5
19
8
20
11
21
112
22
110
32
108
33
52
44
53
116
54
107
29
D a t a S h e e t
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
30
CONFIDENTIAL
Function
General-purpose I/O port 0.
General-purpose I/O port 1.
General-purpose I/O port 2.
Pin No.
LQFP- BGA- LQFP100 112 120
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
-
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
-
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
88
87
86
85
84
83
82
81
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
Function
General-purpose I/O port 3.
General-purpose I/O port 4.
General-purpose I/O port 5.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
-
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
-
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
41
42
44
45
46
47
48
49
50
2
3
4
5
6
7
8
9
10
11
12
13
31
D a t a S h e e t
Module
Pin name
GPIO
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
SIN0_0
SIN0_1
Multi
Function
Serial
0
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
Multi
Function
Serial
1
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
32
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
Function
General-purpose I/O port 6.
General-purpose I/O port 7.
General-purpose I/O port 8.
Multifunction serial interface ch.0 input pin.
Multifunction serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL0
when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.1 input pin.
Multifunction serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL1
when it is used in an I2C (operation mode 4).
96
95
94
93
98
99
73
56
C4
B4
C5
D6
A3
A2
C11
H9
116
115
114
113
112
111
110
109
108
51
52
53
54
55
118
119
88
66
72
E8
87
57
H7
67
71
D10
86
58
G10
68
53
J10
8
63
-
-
9
54
J8
64
-
-
10
55
H10
65
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
Multi
Function
Serial
2
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multi
Function
Serial
3
Function
Multifunction serial interface ch.2 input pin.
Multifunction serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA2 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL2
when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.3 input pin.
Multifunction serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL3
when it is used in an I2C (operation mode 4).
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
59
G9
53
85
69
-
-
54
-
-
84
63
G8
73
-
-
55
-
-
83
64
F10
74
2
39
C1
K6
110
2
44
-
-
109
3
C2
3
40
J6
45
-
-
108
4
B3
4
41
L7
46
33
D a t a S h e e t
Module
Pin name
Multi
Function
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Multi
Function
Serial
5
34
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
Function
Multifunction serial interface ch.4 input pin.
Multifunction serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL4
when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.4 RTS output pin.
Multifunction serial interface ch.4 CTS input pin.
Multifunction serial interface ch.5 input pin.
Multifunction serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL5
when it is used in an I2C (operation mode 4).
87
65
82
D7
F9
C8
102
75
97
88
A6
103
66
E11
76
83
D9
98
89
B6
104
67
E10
77
84
A7
99
90
69
86
91
68
85
96
15
C6
E9
C7
A5
F8
B7
C4
F3
105
79
101
106
78
100
116
113
20
95
B4
115
-
-
112
16
G1
21
94
C5
114
-
-
111
17
G2
22
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
Multi
Function
Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SIN7_0
SIN7_1
Multi
Function
Serial
7
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
Function
Multifunction serial interface ch.6 input pin.
Multifunction serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL6
when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.7 input pin.
Multifunction serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode 4).
Multifunction serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as SCL7
when it is used in an I2C (operation mode 4).
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
5
12
D1
E4
5
17
6
D2
6
11
E3
16
7
D3
7
10
E2
15
45
K8
11
50
-
-
12
44
J7
49
-
-
13
43
H6
48
35
D a t a S h e e t
Module
Pin name
Multi
Function
Timer
0
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
IC00_0
IC00_1
IC01_0
IC01_1
IC02_0
IC02_1
IC03_0
IC03_1
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
36
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
Function
18
69
13
70
17
65
16
66
15
67
14
68
F4
E9
F1
D11
G2
F9
G1
E11
F3
E10
F2
F8
23
79
18
80
22
75
21
76
20
77
19
78
Wave form generator output of multi-function timer 0.
This pin operates as PPG00 when it is used in PPG 0
output modes.
19
G3
24
71
D10
86
Wave form generator output of multi-function timer 0.
This pin operates as PPG00 when it is used in PPG 0
output modes.
20
H1
25
-
-
85
Wave form generator output of multi-function timer 0.
This pin operates as PPG02 when it is used in PPG 0
output modes.
21
H2
26
-
-
84
Wave form generator output of multi-function timer 0.
This pin operates as PPG02 when it is used in PPG 0
output modes.
22
G4
27
-
-
83
Wave form generator output of multi-function timer 0.
This pin operates as PPG04 when it is used in PPG 0
output modes.
23
H3
28
-
-
82
Wave form generator output of multi-function timer 0.
This pin operates as PPG04 when it is used in PPG 0
output modes.
24
J2
29
-
-
81
Input signal controlling wave form generator outputs
RTO00 to RTO05 of multi-function timer 0.
16-bit free-run timer ch.0 external clock input pin.
16-bit input capture ch.0 input pin of multi-function
timer 0.
ICxx desicribes chanel number.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
Multi
Function
Timer
1
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Function
Input signal controlling wave form generator outputs
RTO10 to RTO15 of multi-function timer 1.
16-bit free-run timer ch.1 external clock input pin.
16-bit input capture ch.0 input pin of multi-function
timer 1.
ICxx desicribes chanel number.
Wave form generator output of multi-function timer 1.
This pin operates as PPG10 when it is used in PPG 1
output modes.
Wave form generator output of multi-function timer 1.
This pin operates as PPG10 when it is used in PPG 1
output modes.
Wave form generator output of multi-function timer 1.
This pin operates as PPG12 when it is used in PPG 1
output modes.
Wave form generator output of multi-function timer 1.
This pin operates as PPG12 when it is used in PPG 1
output modes.
Wave form generator output of multi-function timer 1.
This pin operates as PPG14 when it is used in PPG 1
output modes.
Wave form generator output of multi-function timer 1.
This pin operates as PPG14 when it is used in PPG 1
output modes.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
8
39
87
44
88
40
89
41
90
42
91
43
D5
K6
D7
J7
A6
J6
B6
L7
C6
K7
A5
H6
8
44
102
49
103
45
104
46
105
47
106
48
2
C1
2
27
J4
32
3
C2
3
28
L5
33
4
B3
4
29
K5
34
5
D1
5
30
J5
35
6
D2
6
31
H5
36
7
D3
7
32
L6
37
37
D a t a S h e e t
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
E1
14
40
J6
45
2
C1
2
10
E2
15
41
L7
46
BIN0_2
3
C2
3
ZIN0_0
11
E3
16
42
K7
47
AIN0_1
BIN0_0
QPRC ch.0 BIN input pin.
QPRC ch.0 ZIN input pin.
ZIN0_2
4
B3
4
AIN1_1
74
C10
89
43
H6
48
73
C11
88
44
J7
49
72
E8
87
45
K8
50
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
CONFIDENTIAL
QPRC ch.0 AIN input pin.
AIN0_2
ZIN0_1
38
Pin No.
LQFP- BGA- LQFP100 112 120
9
BIN0_1
Quadrature
Position/
Revolution
Counter
1
Function
QPRC ch.1 AIN input pin.
QPRC ch.1 BIN input pin.
QPRC ch.1 ZIN input pin.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Module
Pin name
Function
RESET
Mode
INITX
External Reset Input. A reset is valid when INITX=L.
Mode 0 pin.
During normal operation, MD0=L must be input.
During serial programming to flash memory, MD0=H
must be input.
Mode 1 pin. Input must always be at the "L" level.
MD0
POWER
GND
CLOCK
Analog
POWER
Analog
GND
C-pin
MD1
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT
AVCC
AVRH
AVSS
C
38
K4
43
47
L8
57
Main clock (oscillation) input pin.
Sub clock (oscillation) input pin.
Main clock (oscillation) I/O pin.
Sub clock (oscillation) I/O pin.
Built-in High-speed CR-osc clock output port.
A/D converter analog power pin.
A/D converter analog reference voltage input pin.
46
1
26
35
51
76
97
25
34
50
75
100
48
36
49
37
74
60
61
K9
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
L9
L3
L10
K3
C10
H11
F11
56
1
31
40
61
91
117
30
39
60
90
120
58
41
59
42
89
70
71
A/D converter GND pin.
62
G11
72
Power stabilization capacity pin.
33
L2
38
Power Pin.
GND Pin.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Pin No.
LQFP- BGA- LQFP100 112 120
39
D a t a S h e e t
 I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
・ Oscillation feedback resistor
: Approximately 1MΩ
・ With Standby mode control
X0
Standby mode control
・ CMOS level hysteresis input
・ pull-up resistor
: Approximately 50kΩ
B
Pull-up resistor
Digital input
・ CMOS level hysteresis input
C
Mode input
40
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Type
Circuit
Remarks
・ It is possible to select the sub
oscillation / GPIO function
D
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
R
When the sub oscillation is
selected.
・ Oscillation feedback resistor
: Approximately 20MΩ
・ With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
Pull-up resistor control ・ pull-up resistor
: Approximately 50kΩ
Digital input
・ IOH=-4mA, IOL=4mA
Digital output
Standby mode control
Feedback
Clock input
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
41
D a t a S h e e t
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ pull-up resistor
: Approximately 50kΩ
・ IOH=-4mA, IOL=4mA
・ When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
・ +B input is available
E
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
・ CMOS level output
・ CMOS level hysteresis input
・ With input control
・ Analog input
・ With pull-up resistor control
・ With standby mode control
・ pull-up resistor
: Approximately 50kΩ
・ IOH=-4mA, IOL=4mA
・ When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
・ +B input is available
F
P-ch
P-ch
N-ch
R
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
42
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Type
Circuit
Remarks
G
P-ch
P-ch
N-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ pull-up resistor
: Approximately 50kΩ
・ IOH=-12mA, IOL=12mA
・ +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
・ CMOS level output
・ CMOS level hysteresis input
・ With standby mode control
・ IOH=-25.3mA, IOL=19.7mA
H
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode Control
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
43
D a t a S h e e t
 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
・ Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
・ Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
・ Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
・ Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
44
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
・ Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
・ Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
・ Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
・ Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
・ Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
・ Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
・ Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
45
D a t a S h e e t
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
・ Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
・ Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
46
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
December 15, 2014, MB9B100A-DS706-00020-2v0-E
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47
D a t a S h e e t
 HANDLING DEVICES
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
 Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1,X1A pin
should be kept open.
・Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
 Handling when using Multi function serial pin as I2C pin
If it is using multi function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C
bus system with power OFF.
48
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
 Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that
the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS
pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as
for switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on : VCC  AVCC  AVRH
Turning off : AVRH  AVCC  VCC
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, restransmit the data.
 Differences in features among the products with different memory sizes and
between FLASH products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between FLASH products
and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
49
D a t a S h e e t
 BLOCK DIAGRAM
MB9BF102A/104A/105A/106A
TRSTX,TC
KTDI,TMS
TDO
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
SRAM0
8/16/24/32
Kbyte
Cortex-M3 Core I
@80MHz(Max.)
D
NVIC
Multi-layer AHB (Max.80MHz)
MPU
Sys
AHB-APB Bridge:
APB0(Max.40MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
On-Chip
Flash
128/256/384/
512Kbyte
Flash I/F
Security
SRAM1
8/16/24/32
Kbyte
DMAC
8ch.
CSV
X0
X1
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
Main
Osc
Sub
Osc
PLL
CR
4MHz
AHB-AHB
Bridge
CLK
Source Clock
CR
100kHz
MAD[24:0]
External Bus IF
12-bit A/D Converter
MDATA[15:0]
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE
MNWEX,
MNREX,
MDQM[1:0]
Unit 0
AN[15:0]
Unit 1
ADTG[8:0]
Unit 2
AIN[1:0]
BIN[1:0]
QPRC
2ch.
ZIN[1:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
FRCK[1:0]
16-bit Input Capture
4ch.
16-bit FreeRun Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
LVD Ctrl
AHB-APB Bridge : APB2 ( Max.40MHz)
TIOB[7:0]
Power On
Reset
Base Timer
16-bit 8ch.
/32-bit 4ch.
AHB-APB Bridge : APB1 (Max.40MHz)
TIOA[7:0]
LVD
Regulator
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
MD[1:0]
MODE-Ctrl
P0[F:0],
P1[F:0],
GPIO
PIN-Function-Ctrl
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi Function Timer x2
C
IRQ-Monitor
・
・
Px[x:0],
Multi-Function
Serial I/F
8ch.
(with FIFO ch.4~7)
*HW flow control(ch.4)
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
 MEMORY SIZE
See "  Memory size" in "PRODUCT LINEUP" to confirm the memory size.
50
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 MEMORY MAP
 Memory Map(1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0x4006_4000
Cortex-M3 Private
Peripherals
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
0xE010_0000
0xE000_0000
Reserved
Reserved
Reserved
DMAC
Reserved
0x4005_0000
Reserved
Reserved
0x4004_0000
0x4003_F000
Reserved
0x7000_0000
0x6000_0000
External Device
Area
Reserved
0x4400_0000
32Mbyte
Bit band alias
0x4200_0000
Peripherals
0x4000_0000
Reserved
0x2400_0000
32Mbyte
Bit band alias
0x2200_0000
0x2000_0000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
SRAM1
SRAM0
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x0010_2000
0x0010_0000
A/DC
QPRC
Base Timer
PPG
Reserved
0x1FF8_0000
Please refer to
the next page for
the memory size
details.
Watch Counter
CRC
MFS
Reserved
Reserved
LVD
Reserved
GPIO
Reserved
Int-Req. Read
EXTI
Reserved
CR Trim
Reserved
0x4002_8000
Reserved
0x2008_0000
EXT-bus I/F
Reserved
0x4002_2000
0x4002_1000
Security/CR Trim
0x4002_0000
Flash
0x4001_6000
0x4001_5000
MFT unit1
MFT unit0
Reserved
Dual Timer
Reserved
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Flash I/F
51
D a t a S h e e t
 Memory Map(2)
MB9BF106NA/RA
0x2008_0000
MB9BF105NA/RA
0x2008_0000
Reserved
MB9BF104NA/RA
0x2008_0000
Reserved
MB9BF102NA/RA
0x2008_0000
Reserved
Reserved
0x2000_8000
0x2000_6000
SRAM1
32kbyte
0x2000_4000
SRAM1
24kbyte
0x2000_0000
0x2000_0000
0x2000_0000
SRAM0
24kbyte
SRAM0
32Kbyte
0x1FFF_C000
0x2000_4000
SRAM1
16kbyte
0x2000_0000
SRAM0
16kbyte
0x1FFF_C000
SRAM1
8kbyte
SRAM0
8kbyte
0x1FFF_A000
0x1FFF_8000
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
Reserved
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
Reserved
Reserved
0x0008_0000
0x0006_0000
SA10-13(64KBx4)
SA4-7(8KBx4)
SA4-7(8KBx4)
0x0000_0000
SA10-11(64KBx2)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
0x0002_0000
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 128Kbyte
SA8-9(48KBx2)
0x0004_0000
Flash 256Kbyte
SA8-9(48KBx2)
Flash 384Kbyte
0x0000_0000
Flash 512Kbyte
SA10-15(64KBx6)
*: See "MB9B500/400/300/100/MB9A100 Series Flash programming Manual" for sector structure of Flash.
52
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low Voltage Detector
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4004_FFFF
Reserved
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
0x4006_2000
0x4006_2FFF
Reserved
0x4006_3000
0x4006_3FFF
Reserved
0x4006_4000
0x41FF_FFFF
Reserved
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
Flash Memory I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
Quadrature Position/Revolution Counter
Reserved
Reserved
53
D a t a S h e e t
 PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
・ INITX=0
This is the period when the INITX pin is the "L" level.
・ INITX=1
This is the period when the INITX pin is the "H" level.
・ SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
・ SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
・ Input enabled
Indicates that the input function can be used.
・ Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
・ Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
・ Setting disabled
Indicates that the setting is disabled.
・ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
・ Analog input is enabled
Indicates that the analog input is enabled.
・ Trace output
Indicates that the trace function can be used.
54
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 LIST OF PIN STATUS
Pin status type
Function group
Power-on reset
or low voltage
detection state
Power supply
unstable
-
INITX=0
-
INITX=1
-
Run mode or
sleep mode
state
Power supply
stable
INITX=1
-
INITX input
state
Device internal
reset state
Power supply stable
Timer mode or sleep mode
state
Power supply stable
INITX=1
SPL=0
SPL=1
A
Main crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
B
Main crystal
oscillator output
pin
H output/
Internal input
fixed at "0"/ or
Input enabled
H output/
Internal input
fixed at "0"
H output/
Internal input
fixed at "0"
Maintain
previous state/
H output at
oscillation
stop (*1)/
Internal input
fixed at "0"
Maintain
previous state/
H output at
oscillation
stop (*1)/
Internal input
fixed at "0"
Maintain
previous state/
H output at
oscillation
stop (*1)/
Internal input
fixed at "0"
C
INITX input pin
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
D
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
E
JTAG
selected
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
GPIO
selected
Setting disabled
Setting
disabled
Setting
disabled
Trace selected
Setting disabled
Setting
disabled
Setting
disabled
Hi-Z/
Input enabled
Hi-Z/
Input enabled
F
External interrupt
enabled selected
GPIO
selected, or other
than above resource
selected
Hi-Z
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Maintain
previous state
Trace output
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
55
D a t a S h e e t
Pin status type
G
Function group
Power-on reset
or low voltage
detection state
Power supply
unstable
-
INITX=0
-
INITX=1
-
Run mode or
sleep mode
state
Power supply
stable
INITX=1
Maintain
previous state
INITX input
state
Device internal
reset state
Power supply stable
Timer mode or sleep mode
state
Power supply stable
INITX=1
SPL=0
SPL=1
Maintain
previous state
Trace output
Trace selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO selected, or
other than above
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO selected, or
other than above
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
I
GPIO selected,
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
J
NMIX selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
GPIO selected, or
other than above
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
H
56
CONFIDENTIAL
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Pin status type
K
L
M
Function group
Power-on reset
or low voltage
detection state
Power supply
unstable
-
INITX=1
-
Device internal
reset state
Power supply stable
Timer mode or sleep mode
state
Power supply stable
INITX=1
SPL=0
SPL=1
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected, or
other than above
resource selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected, or
other than above
resource selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Sub crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
INITX=0
-
Run mode or
sleep mode
state
Power supply
stable
INITX=1
-
INITX input
state
57
D a t a S h e e t
Pin status type
Function group
Power-on reset
or low voltage
detection state
Power supply
unstable
-
N
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Sub crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Maintain
previous state/
Hi-Z at
oscillation stop
(*2)/
Internal input
fixed at "0"
Maintain
previous state/
Hi-Z at
oscillation stop
(*2)/
Internal input
fixed at "0"
GPIO selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous
state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
O
Run mode or
Device internal
sleep mode Timer mode or sleep mode state
reset state
state
Power
Power supply stable
Power supply stable
supply stable
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
INITX input
state
*1 : Oscillation is stopped at sub timer mode, Low speed CR timer mode, and stop mode.
*2 : Oscillation is stopped at stop mode.
58
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
1.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Min
Max
Vcc
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss - 0.5
Input voltage*1
VI
Vss - 0.5
Analog pin input voltage*1
VIA
Vss - 0.5
Output voltage*1
VO
Vss - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5V)
AVcc + 0.5
(≤ 6.5V)
Vcc + 0.5
(≤ 6.5V)
+2
+20
10
20
39
4
12
19.7
100
50
- 10
- 20
- 39
-4
- 12
- 25.3
- 100
- 50
800
+ 150
Power supply voltage*1,*2
Analog power supply voltage*1,*3
Analog reference voltage*1,*3
Clamp maximum current
Clamp total maximum current
"L" level maximum output current*4
"L" level average output current*5
"L" level total maximum output current
"L" level total average output current*6
"H" level maximum output current*4
"H" level average output current*5
Unit
Remarks
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
*7
*7
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"H" level total maximum output current
∑IOH
6
"H" level total average output current*
∑IOHAV
Power consumption
PD
Storage temperature
TSTG
- 55
*1 : These parameters are based on the condition that Vss = AVss = 0.0V.
*2 : Vcc must not drop below Vss - 0.5V.
*3 : Be careful not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
59
D a t a S h e e t
*7 :
・
・
・
・
・
・
・
・
See "LIST OF PIN FUNCTIONS" and "I/O CIRCUIT TYPE" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
60
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
2.
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Power supply voltage
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
Symbol Conditions
Value
Min
Max
Unit
Remarks
Vcc
AVcc
AVRH
-
2.7*2
2.7
2.7
5.5
5.5
AVcc
V
V
V
AVcc = Vcc
CS
-
1
10
μF
For built-in
regulator*1
When
mounted on
- 40
+ 85
C
four-layer
FPT-120P-M21
PCB
FPT-120P-M37
Operating
FPT-100P-M20
Ta
When
- 40
+ 85
C Icc  100mA
Temperature
FPT-100P-M23
mounted on
BGA-112P-M04
double-sided
- 40
+ 70
C Icc > 100mA
single-layer
PCB
*1 : See " · C Pin" in "HANDLING DEVICES" for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
61
D a t a S h e e t
3.
DC Characteristics
(1) Current rating
(Vcc = AVcc =2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40C to + 85C)
Parameter Symbol
RUN
mode
current
Pin
name
Icc
VCC
SLEEP
mode
current
Iccs
Value
Unit Remarks
Typ*3 Max*4
Conditions
CPU : 80MHz,
Peripheral : 40MHz,
FLASH 2Wait
FRWTR.RWT = 10
FSYNDN.SD = 000
CPU : 60MHz,
Peripheral : 30MHz,
FLASH 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
PLL
RUN mode CPU : 80MHz,
Peripheral : 40MHz,
FLASH 5Wait
FRWTR.RWT = 10
FSYNDN.SD = 011
CPU : 60MHz,
Peripheral : 30MHz,
FLASH 3Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
CPU/Peripheral : 4MHz*2
High-speed
FLASH 0Wait
CR
FRWTR.RWT = 00
RUN mode
FSYNDN.SD = 000
CPU/Peripheral : 32kHz
Sub
FLASH 0Wait
RUN mode FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/Peripheral : 100kHz
Low-speed
FLASH 0Wait
CR
FRWTR.RWT = 00
RUN mode
FSYNDN.SD = 000
PLL
Peripheral : 40MHz
SLEEP mode
High-speed
CR
Peripheral : 4MHz*2
SLEEP mode
Sub
Peripheral : 32kHz
SLEEP mode
Low-speed
CR
Peripheral : 100kHz
SLEEP mode
96
118
mA
*1, *5
76
94
mA
*1, *5
66
82
mA
*1, *5
52
65
mA
*1, *5
6.0
9.2
mA
*1
0.2
2.24
mA
*1, *6
0.3
2.36
mA
*1
43
54
mA
*1, *5
3.5
6.2
mA
*1
0.15
2.18
mA
*1, *6
0.22
2.27
mA
*1
*1:When all ports are fixed.
*2: When setting it to 4MHz by trimming.
*3: Ta=+25°C, VCC=3.3V
*4: Ta=+85°C, VCC=5.5V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
62
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(Vcc = AVcc =2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40C to + 85C)
Pin
name
Parameter Symbol
TIMER
mode
current
Ta = + 25C,
When LVD is off
Ta = + 85C,
When LVD is off
Ta = + 25C,
Sub
When LVD is off
TIMER
Ta = + 85C,
mode
When LVD is off
Ta = + 25C,
When LVD is off
STOP mode
Ta = + 85C,
When LVD is off
Main
TIMER
mode
ICCT
VCC
STOP
mode
current
Value
Unit Remarks
Typ*2 Max*3
Conditions
ICCH
2.4
2.5
mA
*1, *4
-
5.4
mA
*1, *4
110
300
μA
*1, *5
-
2.2
mA
*1, *5
50
200
μA
*1
-
2
mA
*1
*1:When all ports are fixed.
*2: VCC=3.3V
*3: VCC=5.5V
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Low-Voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
Conditions
At operation
for interrupt
Value
Typ
Max
2
10
Unit
μA
Remarks
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Flash memory
write/erase
current
ICCFLASH
VCC
Conditions
At Write/Erase
Value
Typ
Max
13
24
Unit
Remarks
mA
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Value
Typ
Max
Unit
At 1unit
operation
2.3
3.6
mA
At stop
0.1
2
μA
At 1unit
operation
AVRH=5.5V
2.2
3.0
mA
At stop
0.03
0.6
μA
Conditions
Remarks
63
D a t a S h e e t
(2) Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40C to + 85C)
Parameter Symbol Pin name
"H" level
input
voltage
(hysteresis
input)
"L" level input
voltage
(hysteresis
input)
"H" level
output voltage
"L" level
output voltage
Input leak
current
Pull-up
resistance
value
Input
capacitance
64
CONFIDENTIAL
Conditions
Min
Value
Typ Max
Unit
VIHS
CMOS
hysteresis
input pin,
MD0,1
-
Vcc
× 0.8
-
Vcc
+ 0.3
V
VILS
CMOS
hysteresis
input pin,
MD0,1
-
Vss
- 0.3
-
Vcc
× 0.2
V
Vcc
- 0.5
-
Vcc
V
Vcc
- 0.5
-
Vcc
V
Vcc
- 0.4
-
Vcc
V
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
-
-5
-
5
μA
Vcc  4.5 V
25
50
100
Vcc  4.5 V
30
80
200
-
-
5
15
VOH
VOL
Vcc  4.5 V
IOH = - 4mA
4mA type
Vcc < 4.5 V
IOH = - 2mA
Vcc  4.5 V
IOH = - 12mA
12mA type
Vcc  4.5 V
IOH = - 8mA
Vcc  4.5 V
IOH = - 25.3mA
P80, P81
Vcc < 4.5 V
IOH = - 13.4mA
Vcc  4.5 V
IOL = 4mA
4mA type
Vcc < 4.5 V
IOL = 2mA
Vcc  4.5 V
IOL = 12mA
12mA type
Vcc  4.5 V
IOL = 8mA
Vcc  4.5 V
IOL = 19.7mA
P80, P81
Vcc < 4.5 V
IOL = 11.9mA
IIL
-
RPU
Pull-up pin
CIN
Other than
Vcc, Vss,
AVcc, AVss,
AVRH
Remarks
kΩ
pF
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Pin
Conditions
name
Vcc  4.5V
Vcc  4.5V
Vcc  4.5V
Vcc  4.5V
Vcc  4.5V
Vcc  4.5V
PWH/tCYLH
PWL/tCYLH
Value
Min
Max
4
4
4
4
20.83
50
48
20
48
20
250
250
Unit
Remarks
When crystal oscillator
is connected
Input frequency
FCH
When using external
MHz
clock
X0
When using external
Input clock cycle
tCYLH
ns
X1
clock
Input clock pulse
When using external
45
55
%
width
clock
Input clock rise
tCF
When using external
5
ns
time and fall time
tCR
clock
FCM
80
MHz Master clock
Base clock
FCC
80
MHz
Internal operating
(HCLK/FCLK)
clock*1
FCP0
40
MHz APB0 bus clock*2
frequency
FCP1
40
MHz APB1 bus clock*2
FCP2
40
MHz APB2 bus clock*2
Base clock
tCYCC
12.5
ns
(HCLK/FCLK)
Internal operating
1
t
25
ns
APB0 bus clock*2
clock*
CYCP0
tCYCP1
25
ns
APB1 bus clock*2
cycle time
tCYCP2
25
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "BLOCK DIAGRAM" in this data
sheet.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
MHz
65
D a t a S h e e t
(2) Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Input frequency
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Conditions
name
Unit
FCL
X0A
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
(3) Built-in CR Oscillation Characteristics
· Built-in high-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Conditions
Ta = + 25C
Clock frequency
FCRH
Ta =
0C to + 70C
Ta =
- 40C to + 85C
Ta =
- 40C to + 85C
Min
Value
Typ
Max
3.92
4
4.08
3.84
4
4.16
3.8
4
4.2
3
4
5
Unit
Remarks
When trimming*1
MHz
When not trimming
Frequency
tCRWT
50
μs *2
stability time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
· Built-in low-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Clock frequency
66
CONFIDENTIAL
Symbol
Conditions
FCRL
-
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(4-1) Operating Conditions of Main PLL(In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time
tLOCK
100
μs
(LOCK UP time)*1
PLL input clock frequency
fPLLI
4
30
MHz
PLL multiple rate
4
30
multiple
PLL macro oscillation clock frequency
fPLLO
60
120
MHz
Main PLL clock frequency*2
FCLKPLL
80
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
(4-2) Operating Conditions of Main PLL(In the case of using built-in high speed CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time
tLOCK
100
μs
(LOCK UP time)*1
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiple rate
15
28
multiple
PLL macro oscillation clock frequency
fPLLO
57
120
MHz
Main PLL clock frequency*2
FCLKPLL
80
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency
has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
67
D a t a S h e e t
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
Pin
name
Value
Max
0
-
ms
1
-
ms
0.422
0.704
ms
Tr
Toff
Vcc
Tprt
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
CPU Operation
RST Active
Toff
Release
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions
・ VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "6. Low-Voltage Detection Characteristics"
68
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(7) External Bus Timing
· Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Pin name
MOEX
tOEW
MOEX
Min pulse width
MOEX
MOEX  
tOEL - AV
MAD24 to 00
Address delay time
MOEX
MOEX  
tOEH - AX
MAD24 to 00
Address delay time
MOEX  
MOEX
tOEL - CSL
MCSX
MCSX  delay time
MOEX  
MOEX
tOEH - CSH
MCSX
MCSX  delay time
Data set up
MOEX
tDS - OE
MDATA15 to 0
MOEX  time
MOEX  
MOEX
tDH - OE
MDATA15 to 0
Data hold time
MCSX  
MCSX
tCSL - WEL
MWEX
MWEX  delay time
MWEX  
MCSX
tWEH - CSH
MWEX
MCSX  delay time
Address 
MWEX
tAV - WEL
MAD24 to 00
MWEX  delay time
MWEX
MWEX  
tWEH - AX
MAD24
to 00
Address delay time
MWEX  
MWEX
t
MDQM  delay time WEL - DQML MDQM0 to 1
MWEX  
tWEH MWEX
MDQM0 to 1
MDQM  delay time
DQMH
MWEX
tWEW
MWEX
Min pulse width
MWEX
MWEX  
tWEL - DV
MDATA15 to 0
Data delay time
MWEX
MWEX  
tWEH - DX
MDATA15 to 0
Data delay time
Note: When the external load capacitance = 50pF.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Conditions
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Value
Min
Max
Unit Remarks
THCLK×1 - 3
-
ns
0
0
0
0
10
20
10
20
0
10
ns
0
10
ns
20
38
-
ns
0
-
ns
THCLK×1 - 5
THCLK×1 - 10
THCLK×1 - 5
THCLK×1 - 10
THCLK×1 - 5
THCLK×1 - 15
THCLK×1 - 5
THCLK×1 - 15
0
0
0
0
5
10
5
10
THCLK×1 - 3
-
-5
-15
THCLK×1 - 5
THCLK×1 - 15
5
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
69
D a t a S h e e t
SRAM read
tCYC
HCLK
VOH
VOH
tOEH-CSH
tOEL-CSL
MCSX0 to 7
VOH
VOL
tOEL-AV
tOEH-AX
VOH
VOL
MAD24 to 00
VOH
VOL
tOEW
MOEX
VOH
VOL
tDS-OE
VIH
MDATA15 to 0
tDH-OE
VIH
Read
VIL
VIL
SRAM write
tCYC
HCLK
tW EH-CSH
tCSL-W EL
MCSX0 to 7
VOH
VOL
tAV-W EL
MAD24 to 00
tW EH-AX
VOH
VOL
VOH
VOL
tW EH-DQMH
tW EL-DQML
MDQM0 to 1
VOH
VOL
tW EW
MWEX
VOL
VOH
tW EH-DX
tW EL-DV
MDATA15 to 0
VOH
VOL
70
CONFIDENTIAL
Write
VOH
VOL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
· NAND FLASH mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Pin name
MNREX
tNREW
MNREX
Min pulse width
Data set up
MNREX
tDS - NRE
MDATA15 to 0
 MNREX  tiime
MNREX
MNREX  
tDH - NRE
MDATA15 to 0
Data hold time
MNALE
MNALE  
t
MNWEX
MNWEX delay time ALEH - NWEL
MNALE
MNWEX  
tNWEH - ALEL
MNWEX
MNALE delay time
MNCLE
MNCLE  
t
MNWEX
MNWEX delay time CLEH - NWEL
MNWEX  
MNCLE
tNWEH - CLEL
MNWEX
MNCLE delay time
MNWEX
tNWEW
MNWEX
Min pulse width
MNWEX
MNWEX  
tNWEL - DV
MDATA15 to 0
Data delay time
MNWEX
MNWEX  
tNWEH - DX
MDATA15 to 0
Data delay time
Note: when the external load capacitance = 50pF.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Conditions
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Value
Min
Max
THCLK×1 - 3
-
20
38
0
0
THCLK×1 - 5
THCLK×1 - 15
THCLK×1 - 5
THCLK×1 - 15
THCLK×1 - 5
THCLK×1 - 15
THCLK×1 - 5
THCLK×1 - 15
-
THCLK×1 - 3
-
-5
-15
THCLK×1 - 5
THCLK×1 - 15
+5
+15
-
Unit Remarks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
71
D a t a S h e e t
NAND FLASH read
tCYC
HCLK
VOH
VOH
tNREW
MNREX
VOH
VOL
tDS-NRE
VIH
MDATA15 to 0
tDH-NRE
VIH
Read
VIL
VIL
NAND FLASH write
tCYC
HCLK
tNW EH-ALEL
tALEH-NW EL
VOH
VOL
MNALE
tNW EH-CLEL
tCLEH-NW EL
VOH
VOL
MNCLE
tNW EW
MNWEX
VOL
VOH
tNW EH-DX
tNW EL-DV
MDATA15 to 0
VOH
VOL
72
CONFIDENTIAL
Write
VOH
VOL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(8) Base Timer Input Timing
· Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK,TIN)
-
tTIWH
Min
Value
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
VIHS
VIHS
VILS
VILS
· Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
2tCYCP
-
Unit
Remarks
ns
tTRGL
tTRGH
VIHS
Value
Min
Max
VIHS
TGIN
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this
data sheet.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
73
D a t a S h e e t
(9) CSIO/UART Timing
· CSIO (SPI = 0, SCINV = 0)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Vcc ≥ 4.5V
Vcc  4.5V
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
SCK   SOT delay time
tSLOVI
SIN  SCK  setup time
tIVSHI
SCK   SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
Max
Min
Max
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
5
5
ns
ns
2tcycp 10
tcycp +
10
-
2tcycp 10
tcycp +
10
SCKx
50
SOTx
Slave mode
SCKx
tIVSHE
10
10
SIN  SCK  setup time
SINx
SCKx
tSHIXE
20
20
SCK   SIN hold time
SINx
SCK fall time
tF
SCKx
5
SCK rise time
tR
SCKx
5
Notes: · The above characteristics apply to CLK synchronous mode.
· tCYCP indicates the APB bus clock cycle time.
· About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
· These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
· When the external load capacitance = 50pF.
SCK   SOT delay time
74
CONFIDENTIAL
tSLOVE
Unit
Min
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
SIN
tSHIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
75
D a t a S h e e t
· CSIO (SPI = 0, SCINV = 1)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Vcc ≥ 4.5V
Vcc  4.5V
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
SCK   SOT delay time
tSHOVI
SIN  SCK  setup time
tIVSLI
SCK   SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
Max
Min
Max
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
5
5
ns
ns
2tcycp
- 10
tcycp +
10
-
2tcycp 10
tcycp +
10
SCKx
50
SOTx
Slave mode
SCKx
tIVSLE
10
10
SIN  SCK  setup time
SINx
SCKx
tSLIXE
20
20
SCK   SIN hold time
SINx
SCK fall time
tF
SCKx
5
SCK rise time
tR
SCKx
5
Notes: · The above characteristics apply to CLK synchronous mode.
· tCYCP indicates the APB bus clock cycle time.
· About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
· These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
· When the external load capacitance = 50pF.
SCK   SOT delay time
76
CONFIDENTIAL
tSHOVE
Unit
Min
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
SIN
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
77
D a t a S h e e t
· CSIO (SPI = 1, SCINV = 0)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Vcc ≥ 4.5V
Vcc  4.5V
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCKx
SCKx
SOTx
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
SCK   SOT delay time
tSHOVI
SIN  SCK  setup time
tIVSLI
SCK   SIN hold time
tSLIXI
SOT  SCK  delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
Max
Min
Max
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
5
5
ns
ns
2tcycp
- 30
2tcycp
- 10
tcycp +
10
-
2tcycp 30
2tcycp 10
tcycp +
10
SCKx
50
SOTx
Slave mode
SCKx
tIVSLE
10
10
SIN  SCK  setup time
SINx
SCKx
tSLIXE
20
20
SCK   SIN hold time
SINx
SCK fall time
tF
SCKx
5
SCK rise time
tR
SCKx
5
Notes: · The above characteristics apply to CLK synchronous mode.
· tCYCP indicates the APB bus clock cycle time.
· About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
· These characteristics only guarantees the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
· When the external load capacitance = 50pF.
SCK   SOT delay time
78
CONFIDENTIAL
tSHOVE
Unit
Min
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
79
D a t a S h e e t
· CSIO (SPI = 1, SCINV = 1)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Vcc ≥ 4.5V
Vcc  4.5V
Pin
Symbol
Conditions
name
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tcycp
-
4tcycp
-
ns
SCK   SOT delay time
tSLOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN  SCK  setup time
tIVSHI
50
-
30
-
ns
SCK  SIN hold time
tSHIXI
0
-
0
-
ns
SOT  SCK  delay time
tSOVHI
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
-
ns
30
ns
-
ns
-
ns
5
5
ns
ns
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
2tcycp
- 30
2tcycp
- 10
tcycp +
10
-
2tcycp 30
2tcycp 10
tcycp +
10
SCKx
50
SOTx
Slave mode
SCKx
tIVSHE
10
10
SIN  SCK  setup time
SINx
SCKx
tSHIXE
20
20
SCK   SIN hold time
SINx
SCK fall time
tF
SCKx
5
SCK rise time
tR
SCKx
5
Notes: · The above characteristics apply to CLK synchronous mode.
· tCYCP indicates the APB bus clock cycle time.
· About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
· These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
· When the external load capacitance = 50pF.
SCK   SOT delay time
80
CONFIDENTIAL
tSLOVE
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
tSHSL
tR
SCK
VIH
VIL
VIH
tF
tSHIXE
t IVSHE
VIH
VIL
VIH
VIL
SIN
VIH
t SLOVE
VOH
VOL
VOH
VOL
SOT
VIL
VIL
Slave mode
· UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol Conditions
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
tSLSH
tSHSL
tF
tR
CL = 50pF
Max
tcycp + 10
tcycp + 10
-
5
5
t
V IL
December 15, 2014, MB9B100A-DS706-00020-2v0-E
ns
ns
ns
ns
t
SHSL
SCK
Unit Remarks
tF
tR
CONFIDENTIAL
Min
V
IH
SLSH
V
IH
V IL
VIL
V
IH
81
D a t a S h e e t
(10) External input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter Symbol Pin name
Value
Unit
Min
Max
Conditions
ADTG
FRCKx
-
2tCYCP *
-
ns
-
2tCYCP *
-
ns
ICxx
Input pulse
width
tINH
tINL
DTTIxX
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
generator
Except
Timer mode,
2tCYCP + 100 *
ns
INTxx,
External interrupt
Stop mode
NMIX
NMI
Timer mode,
500
ns
Stop mode
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "BLOCK DIAGRAM" in this data sheet.
tINH
VILS
82
CONFIDENTIAL
tINL
VILS
VIHS
VIHS
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Value
Conditions
Min
Max
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
BIN rise time from
PC_Mode2 or
tAUBU
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBUAD
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tADBD
AIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
tBDAU
BIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
2tCYCP *
tBUAU
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tAUBD
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBDAD
BIN pin "L" level
PC_Mode3
BIN rise time from
PC_Mode2 or
tADBU
AIN pin "L" level
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rise and fall time
tZABE
QCR:CGSC="1"
from determined ZIN level
Determined ZIN level from
tABEZ
QCR:CGSC="1"
AIN/BIN rise and fall time
*: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature
Position/Revolution Counter is connected to, see "BLOCK DIAGRAM" in this data sheet.
Unit
ns
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
tBLL
83
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
84
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(12) I2C timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol
Conditions
Standard-mode
Min
Max
Fast-mode
Min
Max
Unit Remarks
SCL clock frequency
FSCL
0
100
0
400
kHz
(Repeated) START
condition hold time
tHDSTA
4.0
0.6
μs
SDA   SCL 
SCLclock "L" width
tLOW
4.7
1.3
μs
SCLclock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START
setup time
tSUSTA
4.7
0.6
μs
SCL   SDA 
CL = 50pF,
Data hold time
R = (Vp/IOL)*1
tHDDAT
0
3.45*2
0
0.9*3
μs
SCL   SDA  
Data setup time
tSUDAT
250
100
ns
SDA    SCL 
STOP condition setup
time
tSUSTO
4.0
0.6
μs
SCL   SDA 
Bus free time between
"STOP condition" and
tBUF
4.7
1.3
μs
"START condition"
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
85
D a t a S h e e t
(13) ETM timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Data hold
TRACECLK
Frequency
Pin name
Conditions
tETMH
TRACECLK
TRACED3 - 0
Vcc ≥ 4.5V
2
9
Vcc  4.5V
2
15
Vcc ≥ 4.5V
-
50
MHz
Vcc < 4.5V
-
32
MHz
Vcc ≥ 4.5V
20
-
ns
Vcc < 4.5V
31.25
-
ns
1/tTRACE
TRACECLK
TRACECLK
clock cycle time
Value
Unit
Min Max
Symbol
tTRACE
Remarks
ns
Note: When the external load capacitance = 50pF.
HCLK
TRACECLK
TRACED[3:0]
86
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(14) JTAG timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40C to + 85C)
Parameter
Symbol Pin name
TMS,TDI setup
time
tJTAGS
TMS,TDI hold time
tJTAGH
TCK
TMS,TDI
TCK
TMS,TDI
TCK
TDO
Note: When the external load capacitance = 50pF.
TDO delay time
tJTAGD
Conditions
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Vcc ≥ 4.5V
Vcc  4.5V
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
45
ns
Remarks
TCK
TMS/TDI
TDO
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
87
D a t a S h e e t
5.
12bit A/D Converter
· Electrical characteristics for the A/D converter.
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40C to + 85C)
Pin
Parameter
Symbol
name
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Min
VZT
ANxx
-
VFST
ANxx
-
Value
Typ
Max
±2
±2
±5
12
± 4.5
± 2.5
± 20
Unit
Remarks
bit
LSB
LSB
mV
AVRH = 2.7V to 5.5V
AVRH ± 10 AVRH ± 20 mV
1
1.0*
2.666*1
*2
*2
55.5
166.6*4
-
-
μs
-
10000
ns
-
-
-
2.5
μs
CAIN
-
-
-
14.5
pF
RAIN
-
-
-
Conversion time
-
-
Sampling time
Ts
-
Compare clock cycle *3
Tcck
-
State transition time to
operation permission
Tstt
Analog input capacity
Analog input resistance
0.93
2.04
4
ns
kΩ
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
Interchannel disparity
LSB
Analog port input
ANxx
5
μA
current
Analog input voltage
ANxx
AVSS
AVRH
V
Reference voltage
AVRH
2.7
AVCC
V
*1: The Conversion time is the value of sampling time(Ts) + compare time(Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5V, HCLK=72MHz
sampling time: 0.222μs
compare time: 0.778μs
AVcc < 4.5V, HCLK=54MHz
sampling time: 0.333μs
compare time: 2.333μs
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this
data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3: The Compare time (Tc) is the value of (Equation 2)
*4: When 12bit A/D converter is used at AVcc<4.5V, there is a limitation as follows.
Please set the HCLK frequency under 54MHz.
88
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
Rext
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistance of A/D = 0.93kΩ
4.5 ≤ AVCC ≤ 5.5
input resistance of A/D = 2.04kΩ
2.7 ≤ AVCC < 4.5
CAIN : input capacity of A/D = 14.5pF
2.7 ≤ AVCC ≤ 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Comrare clock cycle
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
89
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・ Resolution
・ Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
・ Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Ideal characteristics
0xN
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
90
CONFIDENTIAL
:
:
:
:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
6.
Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(Ta = - 40C to + 85C)
Parameter
Detected voltage
Released voltage
Symbol Conditions
VDL
VDH
-
Min
Value
Typ Max
2.20
2.30
2.40
2.50
2.60
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
(2) Interrupt of Low-Voltage Detection
(Ta = - 40C to + 85C)
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Min
Value
Typ Max
Unit
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
2040 ×
tcycp *
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
* : tCYCP indicates theAPB2 bus clock cycle time.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
91
D a t a S h e e t
7.
Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40C to + 85C)
Parameter
Sector erase
time
Large Sector
Value
Typ*
Max*
1.6
7.5
Unit
s
Small Sector
Half word (16 bit)
write time
0.4
2.1
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time.
Includes write time prior to internal
Chip erase time
16
76.8
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
25
400
μs
(2) Erase/write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
1,000
20 *
10,000
100,000
*: At average + 85C
92
CONFIDENTIAL
Remarks
10 *
5*
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
8.
Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Value
Typ
Max*
tCYCC
Unit
ns
33
100
μs
445
1061
μs
Sub TIMER mode
445
1061
μs
STOP mode
445
1061
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
93
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
94
CONFIDENTIAL
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
82
181
μs
82
181
μs
431
1003
μs
Sub TIMER mode
431
1003
μs
STOP mode
431
1003
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Start
95
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
96
CONFIDENTIAL
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■ELECTRICAL CHARACTERISTICS" for the detail
on the time during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 EXAMPLE OF CHARACTERISTIC
Power supply current (PLL run mode, PLL sleep mode)
Iccs sleep operation(PLL) temperature characteristics
Vcc:5.5V, Peripheral:40MHz
Icc normal operation(PLL) temperature characteristics
Vcc:5.5V, CPU:80MHz, Peripheral:40MHz,FLASH 2Wait
60
120
100
Power supply current [mA]
Power supply current [mA]
110
90
80
70
60
50
40
30
20
50
40
30
20
10
10
0
-40 -30 -20 -10
0
0
10
20
30
40
50
60
70
-40 -30 -20 -10
80
0
10
20
30
40
50
60
70
80
Temperature Ta[℃]
Temperature Ta[℃]
Power supply current (Sub run mode)
Icc normal operation(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, CPU/Peripheral:32KHz
Icc normal operation(sub oscillation) temperature
characteristics Vcc:5.5V, CPU/Peripheral:32KHz
1000
500
Power supply current [μ A] (log)
Power supply current [μ A]
450
400
350
300
250
200
150
100
100
10
50
1
0
-40 -30 -20 -10
0
10
20
30
40
Temperature Ta[℃]
50
60
70
-40 -30 -20 -10
80
0
10
20
30
40
50
60
70
80
70
80
Temperature Ta[℃]
Power supply current (Sub sleep mode)
Iccs sleep operation(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, Peripheral:32KHz
Iccs sleep operation(sub oscillation) temperature
characteristics Vcc:5.5V, Peripheral:32KHz
1000
500
Power supply current [μ A] (log)
Power supply current [μ A]
450
400
350
300
250
200
150
100
100
10
50
1
0
-40 -30 -20 -10
0
10
20
30
40
Temperature Ta[℃]
50
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
60
70
80
-40 -30 -20 -10
0
10
20
30
40
50
60
Temperature Ta[℃]
97
D a t a S h e e t
Power supply current (Sub timer mode)
ICCT timer mode(sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, LVD is Off
ICCT timer mode(sub oscillation) temperature characteristics
Vcc:5.5V, LVD is Off
1000
500
Power supply current [μ A] (log)
Power supply current [μ A]
450
400
350
300
250
200
150
100
100
10
50
0
-40 -30 -20 -10
1
0
10
20
30
40
Temperature Ta[℃]
50
60
70
-40 -30 -20 -10
80
0
10
20
30
40
50
60
70
80
70
80
Temperature Ta[℃]
Power supply current (Stop mode)
ICCH stop mode (sub oscillation) temperature
characteristics(semi-log) Vcc:5.5V, LVD is Off
ICCH stop mode (sub oscillation) temperature characteristics
Vcc:5.5V, LVD is Off
1000
500
Power supply current [μ A] (log)
Power supply current [μ A]
450
400
350
300
250
200
150
100
100
10
50
0
-40 -30 -20 -10
98
CONFIDENTIAL
1
0
10
20
30
40
Temperature Ta[℃]
50
60
70
80
-40 -30 -20 -10
0
10
20
30
40
50
60
Temperature Ta[℃]
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 ORDERING INFORMATION
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9BF102NAPMC-G-JNE2
128Kbyte
16Kbyte
MB9BF104NAPMC-G-JNE2
256Kbyte
32Kbyte
MB9BF105NAPMC-G-JNE2
384Kbyte
48Kbyte
MB9BF106NAPMC-G-JNE2
512Kbyte
64Kbyte
MB9BF102RAPMC-G-JNE2
128Kbyte
16Kbyte
MB9BF104RAPMC-G-JNE2
256Kbyte
32Kbyte
MB9BF105RAPMC-G-JNE2
384Kbyte
48Kbyte
MB9BF106RAPMC-G-JNE2
512Kbyte
64Kbyte
MB9BF102NABGL-G-YE1
128Kbyte
16Kbyte
MB9BF104NABGL-G-YE1
256Kbyte
32Kbyte
MB9BF105NABGL-G-YE1
384Kbyte
48Kbyte
MB9BF106NABGL-G-YE1
512Kbyte
64Kbyte
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Package
Packing
Plastic・LQFP
(0.5mm pitch),100-pin
(FPT-100P-M23)
Plastic・LQFP
(0.5mm pitch),120-pin
(FPT-120P-M37)
Tray
Plastic・PFBGA
(0.8mm pitch),112-pin
(BGA-112P-M04)
99
D a t a S h e e t
 PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
0°~8°
0.50±0.20
(.020±.008)
26
"A"
1
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
100
CONFIDENTIAL
0.60±0.15
(.024±.006)
25
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
120-pin plastic LQFP
(FPT-120P-M37)
120-pin plastic LQFP
(FPT-120P-M37)
Lead pitch
0.50 mm
Package width ×
package length
16.0 mm × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16 × 16-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 ± 0.20(.709 ± .008) SQ
* 16.00 ± 0.10(.630 ± .004) SQ
90
61
91
Details of "A" part
60
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60 ± 0.15
(.024 ± .006)
"A"
LEAD No.
1
30
0.50(.020)
C
0.22 ± 0.05
(.009 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
0.10 ± 0.05
(.004 ± .002)
(Stand off)
31
120
+0.05
0.145–0.03
( .006+.002
–.001 )
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
101
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
Ф 0.45 mm
Mounting height
1.45 mm Max.
Weight
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S B
0.80(.031)
REF
B
11
10
9
8
7
6
5
4
3
2
0.80(.031)
REF
A
10.00±0.10
(.394±.004)
1
L K J H G F
(INDEX AREA)
0.35±0.10
(.014±.004)
(Stand off)
0.20(.008) S A
1.25±0.20
(.049±.008)
(Seated height)
ED C B A
INDEX
112-Ф0.45±010
(112-Ф0.18±.004)
Ф0.08(.003) M S A B
S
0.10(.004) S
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
102
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
 MAJOR CHANGES
Page
Section
Revision 1.0
Revision 1.1
Revision 2.0
FEATURES
3
External Bus Interface
8
PACKAGES
LIST OF PIN FUNCTIONS
17
· List of pin numbers
LIST OF PIN FUNCTIONS
32-35
· List of pin functions
42
I/O CIRCUIT TYPE
42, 43
I/O CIRCUIT TYPE
48
HANDLING DEVICES
HANDLING DEVICES
48
Crystal oscillator circuit
HANDLING DEVICES
49
C Pin
50
BLOCK DIAGRAM
50
51
52
MEMORY SIZE
MEMORY MAP
· Memory map(1)
MEMORY MAP
· Memory map(2)
59, 60
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
61
ELECTRICAL CHARACTERISTICS
2. Recommended Operation Conditions
62, 63
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current rating
65
66
67
68
74-81
88
92
93-96
99
100
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Main Clock Input Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1)(4-2) Operating Conditions of Main PLL
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(6) Power-on Reset Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) CSIO/UART Timing
ELECTRICAL CHARACTERISTICS
5. 12bit A/D Converter
ELECTRICAL CHARACTERISTICS
7. Flash Memory Write/Erase Characteristics
ELECTRICAL CHARACTERISTICS
8. Return Time from Low-Power
Consumption Mode
ORDERING INFORMATION
PACKAGE DIMENSIONS
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
Change Results
Initial release
Company name and layout design change
Added the description of Maximum area size
Deleted the description of ES
Modified the Pin state type of P4E from I to H
Added LIN to the description of SOTxx
Added the description of I2C to the type of E and F
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
Changed to the following description
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
Modified the area of "Extarnal Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Added Master clock at Ingernal operating clock frequency
Added Frequency stability time at Built-in high-speed CR
· Added Main PLL clock frequency
· Added the figure of Main PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 4.5V
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Change to the erase time of include write time prior to internal erase
Added Return Time from Low-Power Consumption Mode
Change to full part number
Deleted FPT-100P-M20 and FPT-120P-M21
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D a t a S h e e t
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MB9B100A-DS706-00020-2v0-E, December 15, 2014
D a t a S h e e t
December 15, 2014, MB9B100A-DS706-00020-2v0-E
CONFIDENTIAL
105
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2011-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the
United States and other countries. Other names used are for informational purposes only and may be trademarks of their
respective owners.
106
CONFIDENTIAL
MB9B100A-DS706-00020-2v0-E, December 15, 2014