3.2 MB

The following document contains information on Cypress products.
MB9B520M Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF524K/L/M, MB9BF522K/L/M,
MB9BF521K/L/M
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B520M_DS706-00048
CONFIDENTIAL
Revision 3.0
Issue Date March 18, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
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consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
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disclaimer on the first page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B520M_DS706-00048-3v0-E, March 18, 2015
CONFIDENTIAL
MB9B520M Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF524K/L/M, MB9BF522K/L/M,
MB9BF521K/L/M
Data Sheet (Full Production)
 Description
The MB9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN,
UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B520M_DS706-00048
Revision 3.0
Issue Date March 18, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 Features
 32-bit ARM Cortex-M3 Core
 Processor version: r2p1
 Up to 72 MHz Frequency Operation
 Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
 24-bit System timer (Sys Tick): System timer for OS task management
 On-chip Memories
[Flash memory]
 Dual operation Flash memory
 Dual Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
 Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
 Work area: 32 Kbytes (lower bank)
 Read cycle: 0 wait-cycle
 Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
 SRAM0: Up to 16 Kbytes
 SRAM1: Up to 16 Kbytes
 USB Interface
The USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
 EndPoint 0 is control transfer
 EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
 EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
 EndPoint 1 to 5 are comprised of Double Buffers.
 The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5 : 64 bytes
- Endpoint 1 : 256 bytes
[USB host]
 USB2.0 Full/Low-speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer support
 USB Device connected/dis-connected automatic detection
 Automatic processing of the IN/OUT token handshake packet
 Max 256-byte packet-length supported
 Wake-up function supported
 CAN Interface
 Compatible with CAN Specification 2.0A/B
 Maximum transfer rate: 1 Mbps
 Built-in 32 message buffer
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CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Multi-function Serial Interface (Max eight channels)
 4 channels with 16 steps×9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)
 Operation mode is selectable from the followings for each channel.
 UART
 CSIO
 LIN
 I 2C
[UART]
 Full duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
 Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
 Full duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detection function available
[LIN]






LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit length)
LIN break delimiter generation (can be changed to 1 to 4-bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported
 DMA Controller (Eight channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.







8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
 A/D Converter (Max 26 channels)
[12-bit A/D Converter]
 Successive Approximation type
 Built-in 2units
 Conversion time: 0.8 μs @ 5 V
 Priority conversion available (priority at 2 levels)
 Scanning conversion mode
 Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
 D/A Converter (Max two channels)
 R-2R type
 10-bit resolution
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
3
D a t a S h e e t
 Base Timer (Max eight channels)
Operation mode is selectable from the followings for each channel.




16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
 General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover,
the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.





Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 65 high-speed general-purpose I/O [email protected] Package
Some ports are 5V tolerant.
See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins.
 Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
 Free-running
 Periodic (=Reload)
 One-shot
 Quadrature Position/Revolution Counter (QPRC) (Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.




The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
 Multi-function Timer
The Multi-function timer is composed of the following blocks.






16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
Output compare × 6ch./unit
A/D activation compare × 2ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.






PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
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CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
 The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
 Timer interrupt function after set time or each set time.
 Capable of rewriting the time with continuing the time count.
 Leap year automatic count is available.
 Watch Counter
The Watch counter is used for wake up from Sleep and Timer mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
 External Interrupt Controller Unit
 Up to 23 external interrupt input pins @ 80 pin Package
 Include one non-maskable interrupt (NMI) input pin
 Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby
RTC, Deep Standby Stop modes.
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
 Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).





Main Clock:
Sub Clock:
Built-in High-speed CR Clock:
Built-in Low-speed CR Clock:
Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
[Resets]
 Reset requests from INITX pin
 Power-on reset
 Software reset
 Watchdog timers reset
 Low-voltage detection reset
 Clock Super Visor reset
 Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
 If external clock failure (clock stop) is detected, reset is asserted.
 If external frequency anomaly is detected, interrupt or reset is asserted.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
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D a t a S h e e t
 Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low-Power Consumption Mode
Six low-power consumption modes supported.






Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of RAM and not)
Deep Standby Stop (selectable between keeping the value of RAM and not)
 Debug
Serial Wire JTAG Debug Port (SWJ-DP)
 Unique ID
Unique value of the device (41 bits) is set.
 Power Supply
Wide range voltage:
6
CONFIDENTIAL
VCC
USBVCC
= 2.7 V to 5.5 V
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Product Lineup
 Memory size
Product name
On-chip
Main area
Flash
Work area
memory
SRAM0
On-chip
SRAM1
SRAM
Total
MB9BF521K/L/M
64 Kbytes
MB9BF522K/L/M
128 Kbytes
MB9BF524K/L/M
256 Kbytes
32 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
 Function
MB9BF521K
MB9BF522K
MB9BF524K
Product name
Pin count
48
CPU
Freq.
Power supply voltage range
USB2.0 (Function/Host)
CAN
DMAC
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
4ch. (Max)
ch.0/1/3: FIFO
ch.5: No FIFO
(In ch.1/5, only UART
and LIN are
available.)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
2ch.
compare
Input capture
4ch.*
Free-run timer
3ch.
MFTimer Output compare
6ch.
Waveform
3ch.
generator
PPG
3ch.
QPRC
Dual Timer
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
MB9BF521L
MB9BF522L
MB9BF524L
64
Cortex-M3
72 MHz
2.7 V to 5.5 V
1ch. (Max)
1ch. (Max)
8ch.
MB9BF521M
MB9BF522M
MB9BF524M
80/96
8ch. (Max)
ch.0/1/3/4 FIFO
ch.2/5/6/7: No FIFO
(In ch.1, only UART and LIN are available.)
8ch. (Max)
1 unit
1ch.
14 pins (Max) +
NMI × 1
35 pins (Max)
14ch. (2 units)
2ch. (Max)
1 unit
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
19 pins (Max) +
23 pins (Max) +
NMI × 1
NMI × 1
50 pins (Max)
65 pins (Max)
23ch. (2 units)
26ch. (2 units)
2ch. (Max)
Yes
2ch.
4 MHz
100 kHz
SWJ-DP
Yes
7
D a t a S h e e t
*: The external input channel which can be used is shown as follws.
 ch.0 to ch.3 : MB9BF521M/F522M/F524M
 ch.0, ch.2, ch.3 : MB9BF521K/F522K/F524K, MB9BF521L/F522L/F524L
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See " Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
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CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Packages
Product name
Package
LQFP: FPT-48P-M49 (0.5 mm pitch)
QFN: LCC-48P-M73 (0.5 mm pitch)
LQFP: FPT-64P-M38 (0.5 mm pitch)
LQFP: FPT-64P-M39 (0.65 mm pitch)
QFN: LCC-64P-M24 (0.5 mm pitch)
LQFP: FPT-80P-M37 (0.5 mm pitch)
LQFP: FPT-80P-M40 (0.65 mm pitch)
BGA: BGA-96P-M07 (0.5 mm pitch)
MB9BF521K
MB9BF522K
MB9BF524K
MB9BF521L
MB9BF522L
MB9BF524L


-
-
-
-



-
MB9BF521M
MB9BF522M
MB9BF524M
-



: Supported
Note: See "Package Dimensions" for detailed information on each package.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
9
D a t a S h e e t
 Pin Assignment

FPT-80P-M37/M40
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P62/AN19/SCK5_0/ADTG_3
P63/INT03_0
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P0E/CTS4_0/TIOB3_2/INT21_0
P0D/RTS4_0/TIOA3_2/INT20_0
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
P0A/AN15/SIN4_0/INT00_2
P07/ADTG_0/INT23_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
P20/INT05_0/CROUT_0/AIN1_1
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
59
P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
58
P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
57
P23/AN12/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2
5
56
P1B/AN11/SOT4_1/INT20_2/IC01_1
P54/SOT6_0/TIOB1_2/INT18_1
6
55
P1A/AN10/SIN4_1/INT05_1/IC00_1
P55/SCK6_0/ADTG_1/INT19_1
7
54
P19/AN09/SCK2_2
P56/INT08_2
8
53
P18/AN08/SOT2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
9
52
AVRL
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
10
51
AVRH
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
12
49
P17/AN07/SIN2_2/INT04_1
P39/DTTI0X_0/INT06_0/ADTG_2
13
48
P16/AN06/SCK0_1/INT15_0
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
14
47
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
15
46
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
16
45
AVSS
P3D/RTO03_0/TIOA3_1
17
44
P12/AN02/SOT1_1/TX1_2/IC00_2
P3E/RTO04_0/TIOA4_1/INT19_2
18
43
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
19
42
P10/AN00
VSS
20
41
VCC
29
30
31
32
33
34
35
36
P48/SIN3_2/INT14_1
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
40
28
INITX
VSS
27
P47/X1A
39
26
P46/X0A
PE3/X1
25
VCC
38
24
VSS
37
23
C
MD0
22
P45/TIOA5_0/INT11_0
PE2/X0
21
P44/TIOA4_0/INT10_0
LQFP - 80
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t

FPT-64P-M38/M39
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P62/AN19/SCK5_0/ADTG_3
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
P0A/AN15/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
47
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
46
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVRL
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/INT06_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
10
39
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
12
37
AVSS
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/TX1_2/IC00_2
P3E/RTO04_0/TIOA4_1/INT19_2
14
35
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
11
D a t a S h e e t

LCC-64P-M24
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P62/AN19/SCK5_0/ADTG_3
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
P0A/AN15/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
47
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
46
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVRL
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/INT06_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
10
39
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
12
37
AVSS
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/TX1_2/IC00_2
P3E/RTO04_0/TIOA4_1/INT19_2
14
35
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t

FPT-48P-M49
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
33
AVRL
P39/DTTI0X_0/INT06_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/INT14_0/IC03_2
P3C/RTO02_0/TIOA2_1/INT18_2
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
AVSS
P3E/RTO04_0/TIOA4_1/INT19_2
10
27
P12/AN02/SOT1_1/TX1_2/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/INT20_1/DA0_0
P4A/TIOB1_0/INT21_1/DA1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 48
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
13
D a t a S h e e t

LCC-48P-M73
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
33
AVRL
P39/DTTI0X_0/INT06_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/INT14_0/IC03_2
P3C/RTO02_0/TIOA2_1/INT18_2
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
AVSS
P3E/RTO04_0/TIOA4_1/INT19_2
10
27
P12/AN02/SOT1_1/TX1_2/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/INT20_1/DA0_0
P4A/TIOB1_0/INT21_1/DA1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 48
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t

BGA-96P-M07
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
UDP0
UDM0
USBVCC
VSS
AN18
VSS
P07
TMS/
SWDIO
TRSTX
VSS
B
VCC
VSS
AN24
AN20
P63
P0D
AN17
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
AN22
AN23
VSS
AN21
AN19
P0E
AN16
AN15
VSS
P20
AN14
D
P53
P54
P55
Index
AN13
AN12
VSS
E
P56
AN25
AN26
AN11
AN10
AN09
F
VSS
VSS
VSS
AN08
AN07
AVRH
G
P32
P33
P39
AN06
AN05
AVRL
H
P3A
P3B
P3C
AN04
AVSS
AVCC
J
P3D
P3E
VSS
P3F
P48
P4A
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P45
P49
P4C
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P44
VSS
P4B
MD0
X0
X1
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
15
D a t a S h e e t
 List of Pin Functions
 List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
Pin Name
VCC
P50
INT00_0
AIN0_2
SIN3_1
AN22
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
AN23
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
AN24
P53
SIN6_0
TIOA1_2
INT07_2
P54
SOT6_0
(SDA6_0)
TIOB1_2
INT18_1
P55
SCK6_0
(SCL6_0)
ADTG_1
INT19_1
P56
INT08_2
P30
AIN0_0
TIOB0_1
INT03_2
AN25
1
B1
1
1
2
C1
2
2
3
C2
3
3
4
B3
4
4
5
D1
-
-
6
D2
-
-
7
D3
-
-
8
E1
-
-
9
E2
5
-
16
CONFIDENTIAL
I/O circuit
type
Pin state
type
-
F
N
F
N
F
N
E
L
E
L
E
L
E
L
F
N
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
10
E3
6
-
11
G1
7
-
12
G2
8
-
13
G3
9
5
14
H1
10
6
15
H2
11
7
16
H3
12
8
17
J1
13
9
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin Name
P31
BIN0_0
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
AN26
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
P39
DTTI0X_0
INT06_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
TIOA0_1
INT07_0
SUBOUT_2
RTCCO_2
P3B
RTO01_0
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
INT18_2
P3D
RTO03_0
(PPG02_0)
TIOA3_1
I/O circuit Pin state
type
type
F
N
E
L
E
L
E
L
G
L
G
K
G
L
G
K
17
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
18
J2
14
10
19
J4
15
11
20
L1
16
12
21
L5
-
-
22
K5
-
-
23
24
25
L2
L4
K1
17
18
13
14
26
L3
19
15
27
K3
20
16
28
K4
21
17
29
J5
-
-
18
30
K6
22
-
19
31
J6
23
-
18
CONFIDENTIAL
Pin Name
P3E
RTO04_0
(PPG04_0)
TIOA4_1
INT19_2
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
P44
TIOA4_0
INT10_0
P45
TIOA5_0
INT11_0
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
INT14_1
SIN3_2
P49
TIOB0_0
INT20_1
DA0_0
SOT3_2
(SDA3_2)
AIN0_1
P4A
TIOB1_0
INT21_1
DA1_0
SCK3_2
(SCL3_2)
BIN0_1
I/O circuit Pin state
type
type
G
L
G
K
G
L
G
L
-
D
F
D
G
B
C
E
L
L
L
L
L
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
32
L7
24
-
33
K7
25
-
34
J7
26
-
35
K8
27
-
36
K9
28
20
37
L8
29
21
38
L9
30
22
39
L10
31
23
40
41
L11
K11
32
33
24
-
42
J11
34
25
43
J10
35
26
44
J8
36
27
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin Name
P4B
TIOB2_0
INT22_1
IGTRG_0
ZIN0_1
P4C
TIOB3_0
SCK7_1
(SCL7_1)
INT12_0
AIN1_2
P4D
TIOB4_0
SOT7_1
(SDA7_1)
INT13_0
BIN1_2
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MD1
PE0
MD0
X0
PE2
X1
PE3
VSS
VCC
P10
AN00
P11
AN01
SIN1_1
INT02_1
RX1_2
FRCK0_2
WKUP1
P12
AN02
SOT1_1
(SDA1_1)
TX1_2
IC00_2
I/O circuit
type
Pin state
type
E
L
I*
L
I*
L
I*
L
C
E
K
D
A
A
A
B
-
F
M
F
N
F
M
19
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
Pin Name
AVSS
P14
AN04
INT03_1
IC02_2
SIN0_1
P15
AN05
IC03_2
SOT0_1
(SDA0_1)
INT14_0
P16
AN06
SCK0_1
(SCL0_1)
INT15_0
P17
AN07
SIN2_2
INT04_1
AVCC
AVRH
AVRL
P18
AN08
SOT2_2
(SDA2_2)
P19
AN09
SCK2_2
(SCL2_2)
P1A
AN10
SIN4_1
INT05_1
IC00_1
45
H10
37
28
46
H9
38
29
47
G10
39
30
48
G9
-
-
49
F10
40
-
50
51
52
H11
F11
G11
41
42
43
31
32
33
53
F9
44
-
54
E11
45
-
55
E10
-
-
20
CONFIDENTIAL
I/O circuit
type
Pin state
type
-
F
N
F
N
F
N
F
N
-
F
M
F
M
F
N
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
56
E9
-
-
57
D10
46
34
58
D9
47
35
-
-
59
C11
48
36
60
C10
-
-
61
A10
49
37
62
B9
50
38
63
B11
51
39
64
A9
52
40
65
B8
53
41
66
A8
-
-
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin Name
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
INT20_2
P23
SCK0_0
(SCL0_0)
TIOA7_1
AN12
P22
SOT0_0
(SDA0_0)
TIOB7_1
AN13
ZIN1_1
P21
SIN0_0
INT06_1
WKUP2
BIN1_1
AN14
P20
INT05_0
CROUT_0
AIN1_1
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P07
ADTG_0
INT23_1
I/O circuit
type
Pin state
type
F
N
F
M
F
M
F
N
E
N
E
J
E
J
E
J
E
J
E
J
E
L
21
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
67
C8
54
-
68
C7
55
-
69
B7
56
-
70
B6
-
-
71
C6
-
-
72
A6
57
42
73
B5
-
-
74
C5
58
-
75
B4
59
43
22
CONFIDENTIAL
Pin Name
P0A
SIN4_0
INT00_2
AN15
P0B
SOT4_0
(SDA4_0)
TIOB6_1
AN16
INT18_0
P0C
SCK4_0
(SCL4_0)
TIOA6_1
INT19_0
AN17
P0D
RTS4_0
TIOA3_2
INT20_0
P0E
CTS4_0
TIOB3_2
INT21_0
P0F
NMIX
SUBOUT_0
CROUT_1
RTCCO_0
WKUP0
AN18
P63
INT03_0
P62
SCK5_0
(SCL5_0)
ADTG_3
AN19
P61
SOT5_0
(SDA5_0)
TIOB2_2
UHCONX
DTTI0X_2
AN20
I/O circuit
type
Pin state
type
J*
N
J*
N
J*
N
E
L
E
L
F
I
E
L
F
M
F
M
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
LQFP-80
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
Pin Name
76
C4
60
44
77
A4
61
45
78
A3
62
46
79
A2
63
47
64
48
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
IGTRG_1
AN21
USBVCC
P80
UDM0
INT16_1
P81
UDP0
INT17_1
VSS
-
-
VSS
80
A1
A5, A7, A11,
B2, B10, C3,
C9, F1, F2,
F3, J3, J9, K2,
K10, L6
*: 5 V tolerant I/O
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
I/O circuit Pin state
type
type
J*
N
H
H
H
H
-
-
23
D a t a S h e e t
 List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin
function
ADC
24
CONFIDENTIAL
Pin name
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_6
AN00
AN01
AN02
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
66
A8
7
D3
A/D converter external trigger input pin
13
G3
9
5
74
C5
58
12
G2
8
42
J11
34
25
43
J10
35
26
44
J8
36
27
46
H9
38
29
47
G10
39
30
48
G9
49
F10
40
53
F9
44
54
E11
45
55
E10
56
E9
57
D10
46
34
58
D9
47
35
A/D converter analog input pin.
ANxx describes ADC ch.xx.
59
C11
48
36
67
C8
54
68
C7
55
69
B7
56
72
A6
57
42
74
C5
58
75
B4
59
43
76
C4
60
44
2
C1
2
2
3
C2
3
3
4
B3
4
4
9
E2
5
10
E3
6
-
Function description
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Pin
function
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
Debugger
Pin name
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOB4_0
TIOA5_0
TIOA5_1
TIOB5_0
TIOA6_1
TIOB6_1
TIOA7_1
TIOB7_1
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRSTX
Function description
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input
pin
Serial wire debug interface data input /
output pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
J-TAG test reset input pin
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
14
H1
10
6
30
K6
22
18
9
E2
5
15
H2
11
7
5
D1
31
J6
23
19
10
E3
6
6
D2
16
H3
12
8
76
C4
60
44
32
L7
24
11
G1
7
75
B4
59
43
17
J1
13
9
70
B6
33
K7
25
12
G2
8
71
C6
21
L5
18
J2
14
10
34
J7
26
22
K5
19
J4
15
11
35
K8
27
69
B7
56
68
C7
55
57
D10
46
34
58
D9
47
35
62
B9
50
38
64
A9
52
40
65
62
63
65
64
61
B8
B9
B11
B8
A9
A10
53
50
51
53
52
49
41
38
39
41
40
37
25
D a t a S h e e t
Pin
function
External
Interrupt
26
CONFIDENTIAL
Pin name
INT00_0
INT00_2
INT01_0
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_2
INT08_2
INT10_0
INT11_0
INT12_0
INT13_0
INT14_0
INT14_1
INT15_0
INT15_1
INT16_1
INT17_1
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
INT19_2
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
2
C1
2
2
External interrupt request 00 input pin
67
C8
54
External interrupt request 01 input pin
3
C2
3
3
4
B3
4
4
External interrupt request 02 input pin
43
J10
35
26
73
B5
External interrupt request 03 input pin
46
H9
38
29
9
E2
5
12
G2
8
External interrupt request 04 input pin
49
F10
40
10
E3
6
60
P20
External interrupt request 05 input pin
55
E10
11
G1
7
13
G3
9
5
External interrupt request 06 input pin
59
C11
48
36
35
K8
27
14
H1
10
6
External interrupt request 07 input pin
5
D1
External interrupt request 08 input pin
8
E1
External interrupt request 10 input pin
21
L5
External interrupt request 11 input pin
22
K5
External interrupt request 12 input pin
33
K7
25
External interrupt request 13 input pin
34
J7
26
47
G10
39
30
External interrupt request 14 input pin
29
J5
48
G9
External interrupt request 15 input pin
76
C4
60
44
External interrupt request 16 input pin
78
A3
62
46
External interrupt request 17 input pin
79
A2
63
47
68
C7
55
External interrupt request 18 input pin
6
D2
16
H3
12
8
59
C11
56
External interrupt request 19 input pin
7
D3
18
J2
14
10
Function description
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Pin
function
External
Interrupt
GPIO
Pin name
INT20_0
INT20_1
INT20_2
INT21_0
INT21_1
INT22_1
INT23_1
NMIX
P00
P01
P02
P03
P04
P07
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P14
P15
P16
P17
P18
P19
P1A
P1B
P20
P21
P22
P23
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
70
B6
External interrupt request 20 input pin
30
K6
22
18
56
E9
71
C6
External interrupt request 21 input pin
31
J6
23
19
External interrupt request 22 input pin
32
L7
24
External interrupt request 23 input pin
66
A8
Non-Maskable Interrupt input pin
72
A6
57
42
61
A10
49
37
62
B9
50
38
63
B11
51
39
64
A9
52
40
65
B8
53
41
66
A8
General-purpose I/O port 0
67
C8
54
68
C7
55
69
B7
56
70
B6
71
C6
72
A6
57
42
42
J11
34
25
43
J10
35
26
44
J8
36
27
46
H9
38
29
47
G10
39
30
General-purpose I/O port 1
48
G9
49
F10
40
53
F9
44
54
E11
45
55
E10
56
E9
60
C10
59
C11
48
36
General-purpose I/O port 2
58
D9
47
35
57
D10
46
34
Function description
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
27
D a t a S h e e t
Pin
function
GPIO
28
CONFIDENTIAL
Pin name
P30
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
9
E2
5
10
E3
6
11
G1
7
12
G2
8
13
G3
9
5
14
H1
10
6
15
H2
11
7
16
H3
12
8
17
J1
13
9
18
J2
14
10
19
J4
15
11
21
L5
22
K5
26
L3
19
15
27
K3
20
16
29
J5
30
K6
22
18
31
J6
23
19
32
L7
24
33
K7
25
34
J7
26
35
K8
27
2
C1
2
2
3
C2
3
3
4
B3
4
4
5
D1
6
D2
7
D3
8
E1
76
C4
60
44
75
B4
59
43
74
C5
58
73
B5
78
A3
62
46
79
A2
63
47
36
K9
28
20
38
L9
30
22
39
L10
31
23
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Pin
function
Multifunction
Serial
0
Pin name
Function description
SIN0_0
SIN0_1
Multi-function serial interface ch.0
input pin
Multi-function serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1
input pin
Multi-function serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/LIN (operation
modes 0,1,3) .
Multi-function serial interface ch.2
input pin
Multi-function serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.3
input pin
Multi-function serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
Multifunction
Serial
2
SIN1_1
SOT1_1
(SDA1_1)
SIN2_2
SOT2_2
(SDA2_2)
SCK2_2
(SCL2_2)
Multifunction
Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
59
C11
48
36
46
H9
38
29
58
D9
47
35
47
G10
39
30
57
D10
46
34
48
G9
-
-
43
J10
35
26
44
J8
36
27
49
F10
40
-
53
F9
44
-
54
E11
45
-
2
29
C1
J5
2
-
2
-
3
C2
3
3
30
K6
-
-
4
B3
4
4
31
J6
-
-
29
D a t a S h e e t
Pin
function
Multifunction
Serial
4
Pin name
Function description
SIN4_0
SIN4_1
Multi-function serial interface ch.4
input pin
Multi-function serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.4
RTS output pin
Multi-function serial interface ch.4
CTS input pin
Multi-function serial interface ch.5
input pin
Multi-function serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.6
input pin
Multi-function serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SCK4_0
(SCL4_0)
RTS4_0
CTS4_0
Multifunction
Serial
5
SIN5_0
SOT5_0
(SDA5_0)
SCK5_0
(SCL5_0)
Multifunction
Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
30
CONFIDENTIAL
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
67
C8
54
55
E10
68
C7
55
-
56
E9
-
-
69
B7
56
-
70
B6
-
-
71
C6
-
-
76
C4
60
44
75
B4
59
43
74
C5
58
-
5
12
D1
G2
8
-
6
D2
-
-
11
G1
7
-
7
D3
-
-
10
E3
6
-
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Pin
function
Multifunction
Serial
7
Pin name
SIN7_1
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
Multifunction
Timer
0
DTTI0X_0
DTTI0X_2
FRCK0_2
IC00_1
IC00_2
IC01_1
IC02_2
IC03_2
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
IGTRG_0
IGTRG_1
Function description
Multi-function serial interface ch.7
input pin
Multi-function serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
Multi-function timer 0.
16-bit free-run timer ch.0 external
clock input pin
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
PPG IGBT mode external trigger input
pin
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
35
K8
27
-
34
J7
26
-
33
K7
25
-
13
G3
9
5
75
B4
59
43
43
J10
35
26
55
44
56
46
47
E10
J8
E9
H9
G10
36
38
39
27
29
30
14
H1
10
6
15
H2
11
7
16
H3
12
8
17
J1
13
9
18
J2
14
10
19
J4
15
11
32
76
L7
C4
24
60
44
31
D a t a S h e e t
Pin function
Pin name
Quadrature
Position/
Revolution
Counter 0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
UDM0
UDP0
UHCONX
TX1_2
RX1_2
RTCCO_0
RTCCO_2
SUBOUT_0
SUBOUT_2
Quadrature
Position/
Revolution
Counter 1
USB
CAN
Real-time clock
Low-Power
Consumption
Mode
WKUP0
WKUP1
WKUP2
WKUP3
DAC
DA0
DA1
RESET
32
CONFIDENTIAL
INITX
Function description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
USB function/host D – pin
USB function/host D + pin
USB external pull-up control pin
CAN interface TX output pin
CAN interface RX input pin
0.5 seconds pulse output pin of
Real-time clock
Sub clock output pin
Deep standby mode return signal
input pin 0
Deep standby mode return signal
input pin 1
Deep standby mode return signal
input pin 2
Deep standby mode return signal
input pin 3
D/A converter ch.0 analog output
pin
D/A converter ch.1 analog output
pin
External Reset Input pin.
A reset is valid when INITX="L".
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
9
E2
5
30
K6
22
2
C1
2
2
10
E3
6
31
J6
23
3
C2
3
3
11
G1
7
32
L7
24
4
B3
4
4
60
C10
33
K7
25
59
C11
34
J7
26
58
D9
35
K8
27
78
A3
62
46
79
A2
63
47
75
B4
59
43
44
J8
36
27
43
J10
35
26
72
A6
57
42
14
H1
10
6
72
A6
57
42
14
H1
10
6
72
A6
57
42
43
J10
35
26
59
C11
48
36
76
C4
60
44
30
K6
22
18
31
J6
23
19
28
K4
21
17
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Pin
function
Pin name
Mode
MD0
MD1
POWER
GND
CLOCK
Analog
POWER
VCC
VCC
VCC
USBVCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Analog
GND
AVSS
AVRL
C pin
C
Function description
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash
memory, MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference
voltage input pin
A/D converter and D/A converter
GND pin
A/D converter analog reference
voltage input pin
Power supply stabilization capacity
pin
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Pin No
LQFP-64 LQFP-48
LQFP-80 BGA-96
QFN-64 QFN-48
37
L8
29
21
36
K9
28
20
1
25
41
77
20
24
40
80
38
26
39
27
60
72
B1
K1
K11
A4
F1
F2
F3
B2
L1
K2
J3
L6
L4
L11
K10
J9
B10
C9
D11
A11
A7
C3
A5
A1
L9
L3
L10
K3
C10
A6
1
18
33
61
16
32
64
30
19
31
20
57
1
14
45
12
24
48
22
15
23
16
42
50
H11
41
31
51
F11
42
32
45
H10
37
28
52
G11
43
33
23
L2
17
13
33
D a t a S h e e t
 I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
 Oscillation feedback resistor
: Approximately 1 MΩ
 With Standby mode control
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
 CMOS level hysteresis input
 Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
34
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Digital input
 Open drain output
 CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the sub oscillation is
selected.
 Oscillation feedback resistor
: Approximately 5 MΩ
 With Standby mode control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
35
D a t a S h e e t
Type
Circuit
Remarks





E
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control







F
P-ch
P-ch
N-ch
R
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
36
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Type
Circuit
Remarks





G
P-ch
P-ch
Digital output
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH= -12 mA, IOL= 12 mA
 +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
Differential
UDM0/P80
It is possible to select the USB
I/O / GPIO function.
When the USB I/O is selected.
 Full-speed, Low-speed control
When the GPIO is selected.
 CMOS level output
 CMOS level hysteresis input
 With standby mode control
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
37
D a t a S h e e t
Type
Circuit
Remarks






I
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
 Available to control PZR
registers.
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control








J
P-ch
P-ch
N-ch
R
Digital output
Digital output
Pull-up resistor control
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH= -4 mA, IOL= 4 mA
 Available to control PZR
registers.
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital input
Standby mode control
Analog input
Input control
K
CMOS level hysteresis input
Mode input
38
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Type
Circuit
L
P-ch
P-ch
Digital output
N-ch
Digital output
R
Remarks







CMOS level output
CMOS level hysteresis input
With input control
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode Control
Analog output
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
39
D a t a S h e e t
 Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
40
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
41
D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
42
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
43
D a t a S h e e t
 Handling Devices
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin, between AVRH
pin and AVRL pin near this device.
 Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
・ Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
・ Lead type
Load capacitance : Approximately 6 pF to 7 pF
44
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MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
•
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Set as
External clock
input
X1(PE3),
X1A (P47)
 Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
 C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
45
D a t a S h e e t
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : USBVCC → VCC
AVRH → AVCC → VCC
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
 Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
 Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant
I/O.
46
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Block Diagram
MB9BF521K/L/M, F522K/L/M, F524K/L/M
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8/16 Kbytes
SWJ-DP
ROM Table
Multi-layer AHB (Max 72MHz)
Cortex-M3 Core I
@72MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40MHz)
Dual-Timer
WatchDog Timer
(Software)
INITX
Clock Reset
Generator
WatchDog Timer
(Hardware)
SRAM1
8/16 Kbytes
On-Chip Flash
64+32 Kbytes/
128+32 Kbytes/
256+32 Kbytes
Flash I/F
Security
USB2.0 PHY
(Host/
Func)
USBVCC
UDP0/UDM0
UHCONX
DMAC
8ch.
CSV
CLK
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
X0A
X1A
CR
100kHz
CROUT
ADTGx
DAx
TIOAx
TIOBx
AINx
BINx
ZINx
Unit 0
CAN Prescaler
Unit 1
USB Clock Ctrl
10-bit D/A Converter
2units
LVD Ctrl
LVD
IRQ-Monitor
Regulator
Base Timer
16-bit 8ch./
32-bit 4ch.
QPRC
2ch.
A/D Activation
Compare 2ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
IGTRG_x
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer
AHB-APB Bridge : APB2 (Max 40MHz)
ANxx
TX1_2,
RX1_2
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40MHz)
AVCC,
AVSS,
AVRH,
AVRL
CAN
PLL
Power-On
Reset
C
CRC
Accelerator
RTCCO_x,
SUBOUT_x
Real-Time Colck
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MD0,
MD1
MODE-Ctrl
Deep Standby Ctrl
WKUPx
P0x,
P1x,
GPIO
PIN-Function-Ctrl
・
・
・
PFx
SCKx
Multi-Function Serial I/F
8ch.
(with FIFO ch.0/1/3/4)
HW flow control(ch.4)
SINx
SOTx
CTS4
RTS4
 Memory Size
See "  Memory size" in "Product Lineup" to confirm the memory size.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
47
D a t a S h e e t
 Memory Map
 Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_4000
0x4006_3000
0x4006_1000
0x4006_0000
Reserved
0x4005_0000
0x4004_0000
0x4003_C000
0x7000_0000
0x6000_0000
0x4003_B000
External DeviceArea
0x4003_A000
0x4003_9000
0x4003_8000
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0020_8000
0x0020_0000
0x0010_4000
See " • Memory Map (2)"
for the memory size
details.
0x0010_0000
0x4003_7000
0x4003_6000
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Security/CR Trim
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x0000_0000
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_0000
0x4000_1000
0x4000_0000
CONFIDENTIAL
DMAC
Reserved
USB ch.0
Reserved
RTC
Watch Counter
CRC
MFS
CAN Prescaler
USB Clock Ctrl
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
A/DC
QPRC
Base Timer
PPG
Reserved
0x4001_1000
48
Reserved
0x4002_1000
0x4002_0000
Flash(Main area)
CAN ch.1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Memory Map (2)
MB9BF524K/L/M
MB9BF522K/L/M
0x2008_0000
MB9BF521K/L/M
0x2008_0000
Reserved
0x2008_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
SRAM1
16Kbytes
0x2000_0000
0x2000_0000
SRAM0
16Kbytes
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x1FFF_C000
Reserved
Reserved
0x0020_0000
Reserved
0x0010_0000
0x0020_8000
0x0020_0000
Reserved
0x0010_4000
0x0010_2000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Flash(Work area)
32Kbytes
0x0020_8000
Flash(Work area)
32Kbytes
0x0020_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Flash(Work area)
32Kbytes
0x0020_8000
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
CR trimming
Security
Reserved
0x0004_0000
Reserved
SA11(64KB)
0x0002_0000
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
0x0001_0000
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
Flash(Main area)
64Kbytes
SA9(64KB)
Flash(Main area)
128Kbytes
SA9(64KB)
Flash(Main area)
256Kbytes
SA10(64KB)
Reserved
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
49
D a t a S h e e t
 Peripheral Address Map
Start address
End address
Bus
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
AHB
APB0
Peripherals
Flash Memory I/F register
Reserved
Software Watchdog timer
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
0x4002_8000
0x4002_8FFF
D/A Converter
0x4002_9000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Resister
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
CAN prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
CAN ch.1
0x4006_4000
0x41FF_FFFF
Reserved
50
CONFIDENTIAL
APB1
APB2
AHB
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
Deep standby mode Controller
USB clock generator
DMAC register
Reserved
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Pin Status in Each CPU State
The terms used for pin status have the following meanings.
 INITX=0
This is the period when the INITX pin is the "L" level.
 INITX=1
This is the period when the INITX pin is the "H" level.
 SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
 SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
 Input enabled
Indicates that the input function can be used.
 Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
 Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
 Setting disabled
Indicates that the setting is disabled.
 Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
 Analog input is enabled
Indicates that the analog input is enabled.
 Trace output
Indicates that the trace function can be used.
 GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
51
D a t a S h e e t
Pin status type
 List of Pin Status
A
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Power
supply
stable
INITX = 1
-
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator input
pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
B
CONFIDENTIAL
Hi-Z /
Internal
input fixed
at "0"
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When state/When
Hi-Z /
Hi-Z /
oscillation oscillation oscillation oscillation oscillation oscillation
Internal
Internal
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
at "0"
E
52
Maintain
previous
state
MB9B520M_DS706-00048-3v0-E, March 18, 2015
Pin status type
D a t a S h e e t
F
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
External interrupt
enabled selected
Setting
disabled
Maintain
previous
state
Power
supply
stable
INITX = 1
-
Input
enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/
Internal
input fixed
at "0"
GPIO
selected
Input
enabled
G
GPIO
selected
Hi-Z
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at "0"
at "0"
Setting
disabled
Hi-Z /
Input
enabled
Maintain
previous
state
Setting
disabled
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
H
USB I/O pin
Setting
disabled
Setting
disabled
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
Hi-Z /
Hi-Z /
Hi-Z/
Hi-Z/
Hi-Z/
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Setting
disabled
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Internal
Hi-Z /
input fixed
input
fixed
Internal
at "0"
at "0"
input fixed
at "0"
Hi-Z at
Hi-Z at
transtransmission/
mission/
Input
Input
enabled/
enabled/
Internal
Internal
input fixed input fixed
at "0" at
at "0" at
reception reception
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
53
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Analog input
selected
Hi-Z
NMIX selected
Setting
disabled
I
Resource other
than above
selected
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Resource selected
K
GPIO
selected
Analog output
selected
External interrupt
enabled selected
L
Resource other
than above
selected
Analog input
selected
54
CONFIDENTIAL
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
*3
Hi-Z
GPIO
selected
M
Power supply stable
Setting
disabled
J
GPIO
selected
Hi-Z
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
disabled
disabled
Hi-Z /
Input
enabled
GPIO
selected
JTAG
selected
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Hi-Z /
WKUP
input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
disabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
*4
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
MB9B520M_DS706-00048-3v0-E, March 18, 2015
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
Resource other
than above
selected
GPIO
selected
Analog input
selected
N
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Setting
disabled
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Setting
disabled
Maintain
previous
state
Timer mode,
RTC mode, or
STOP mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
previous
state
External interrupt
enabled selected
Resource other
than above
selected
Setting
disabled
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Setting
disabled
GPIO
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
Power
supply
stable
INITX = 1
-
GPIO
selected
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep
Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at "0" at RTC mode, Stop mode.
*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, Stop mode.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
 Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
VCC
USBVCC
AVCC
AVRH
Rating
Min
Max
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
1
Input voltage*
VI
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
Clamp maximum current
Clamp total maximum current
L level maximum output current*5
L level average output current*
6
IOLAV
L level total maximum output current
L level total average output current*7
H level maximum output current*
H level average output current*6
5
∑IOL
∑IOLAV
IOH
IOHAV
-
-
Unit
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
USBVCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
+20
10
20
mA
mA
mA
mA
39
mA
4
12
mA
mA
16.5
mA
100
50
- 10
- 20
mA
mA
mA
mA
- 39
mA
-4
- 12
mA
mA
- 18
mA
Remarks
V
V
V
V
V
Except for USB pin
V
USB pin
V
5 V tolerant
V
V
*8
*8
4 mA type
12 mA type
The pin doubled as
USB I/O
4 mA type
12 mA type
The pin doubled as
USB I/O
4 mA type
12 mA type
The pin doubled as
USB I/O
4 mA type
12 mA type
The pin doubled as
USB I/O
H level total maximum output current
∑IOH
- 100
mA
H level total average output current*7
∑IOHAV
- 50
mA
Power consumption
PD
300
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that V SS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*7: The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100 ms.
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MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
*8:
・
・
・
・
・
・
・
・
See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
2.
Recommended Operating Conditions
(VSS = AVSS = AVRL = 0.0V)
Parameter
Power supply voltage
Power supply voltage (3V power
supply) for USB
Analog power supply voltage
Symbol
Conditions
VCC
-
USBVCC
-
Min
Value
Max
2.7*4
3.0
2.7
5.5
3.6
(≤ VCC)
5.5
(≤ VCC)
5.5
AVCC
AVSS
10
+ 105
Unit
Remarks
V
*1
V
*2
AVCC
2.7
V
AVCC = VCC
AVRH
2.7
V
Analog reference voltage
AVRL
AVSS
V
Smoothing capacitor
CS
1
μF For Regulator*3
Operating temperature
TA
- 40
°C
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: See "  C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or
more, instruction execution and low voltage detection function by built-in High-speed CR(including Main
PLL is used) or bulit-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
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MB9B520M_DS706-00048-3v0-E, March 18, 2015
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3.
DC Characteristics
(1) Current Rating
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol
Conditions
Value
Unit Remarks
Typ Max
CPU : 72 MHz,
Peripheral : 36 MHz
32.5
41
mA
*1, *5
CPU:72 MHz,
Peripheral clock stops
NOP operation
18
23
mA
*1, *5
High-speed
CR
Run mode
CPU/ Peripheral : 4 MHz*2
2.5
3.4
mA
*1
Sub
Run mode
CPU/ Peripheral : 32 kHz
110
980
µA *1, *6
CPU/ Peripheral : 100 kHz
130
1030
µA *1
Peripheral : 36 MHz
22
28
mA *1, *5
Peripheral : 4 MHz*2
1.6
2.6
mA *1
Peripheral : 32 kHz
96
955
µA *1, *6
Peripheral : 100 kHz
115
975
µA *1
Pin
name
PLL
Run mode
Run
mode
current
ICC
VCC
Sleep
mode
current
ICCS
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Main
Timer mode
ICCT
Timer
mode
current
Sub
Timer mode
ICCT
RTC
mode
current
ICCR
Stop
mode
current
ICCH
Conditions
RTC mode
Stop mode
VCC
ICCRD
Deep Standby
RTC mode
Deep
Standby
mode
current
ICCHD
Deep Standby
Stop mode
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
Value
Unit Remarks
Typ*2 Max*2
4.1
4.8
mA *1, *4
-
5.4
mA *1, *4
17
66
μA *1, *5
-
835
μA *1, *5
15
61
μA *1, *5
-
680
μA *1, *5
14
53
μA *1
-
600
μA *1
2.2
11
μA *1, *3, *5
6.2
23
μA *1, *3, *5
155
μA *1, *3, *5
215
μA *1, *3, *5
1.6
9.6
μA *1, *3
5.6
22
μA *1, *3
150
μA *1, *3
210
μA *1, *3
-
-
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: RAM on/off setting is on-chip SRAM only.
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
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D a t a S h e e t
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Low-voltage
detection circuit
(LVD) power
supply current
Symbol
ICCLVD
Pin
name
Conditions
Value
Typ
Max
At operation
for reset
Vcc = 5.5 V
0.13
0.3
μA
At not detect
At operation
for interrupt
Vcc = 5.5 V
0.13
0.3
μA
At not detect
Unit
Remarks
VCC
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
Unit
9.5
mA
11.2
Remarks
*
*: The current at which to write or erase Flash memory, "ICCFLASH" is added to "ICC".
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
Value
Typ
Max
Unit
At 1unit
operation
0.69
0.90
mA
At stop
0.25
25.84
μA
At 1unit
operation
AVRH=5.5 V
1.1
1.97
mA
At stop
0.2
3.4
μA
Conditions
Remarks
· D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply
current*1
Symbol
Pin
name
IDDA*2
AVCC
IDSA
Conditions
At 1unit
operation
AVCC=3.3 V
At 1unit
operation
AVCC=5.0 V
At stop
Min
Value
Typ
Max
250
315
380
μA
380
475
580
μA
-
-
16
μA
Unit
Remarks
*1: No-load
*2: Generates the max current by the CODE about 0x200
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
(2) Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol Pin name
H level input
voltage
(hysteresis
input)
VIHS
L level input
voltage
(hysteresis
input)
VILS
H level
output voltage
L level
output voltage
Input leak
current
Pull-up
resistance
value
Input
capacitance
62
CONFIDENTIAL
VOH
VOL
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
Min
Value
Typ
Max
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC 0.4
-
USBVCC
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
Conditions
VCC ≥ 4.5 V,
IOH = - 4 mA
4 mA type
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
12 mA type
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
The pin
IOH = - 18.0 mA
doubled as
USBVCC < 4.5 V,
USB I/O
IOH = - 12.0 mA
VCC ≥ 4.5 V,
IOL = 4 mA
4 mA type
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
12 mA type
VCC < 4.5 V,
IOL = 8 mA
USBVCC ≥ 4.5 V,
The pin
IOL = 16.5 mA
doubled as
USBVCC < 4.5 V,
USB I/O
IOL = 10.5 mA
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH,
AVRL
Unit Remarks
kΩ
pF
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Symbol
Pin
Conditions
name
fCH
tCYLH
X0,
X1
tCF,
tCR
fCM
-
Value
Min
Max
Unit
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
PWH/tCYLH,
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
-
-
72
MHz
MHz
MHz
ns
Remarks
When crystal oscillator
is connected
When using external
Clock
When using external
Clock
When using external
Clock
When using external
Clock
Master clock
Base clock
fCC
72
MHz
(HCLK/FCLK)
Internal operating
clock frequency*1
fCP0
40
MHz APB0 bus clock*2
fCP1
40
MHz APB1 bus clock*2
fCP2
40
MHz APB2 bus clock*2
Base clock
tCYCC
13.8
ns
(HCLK/FCLK)
Internal operating
t
25
ns
APB0 bus clock*2
CYCP0
clock cycle time*1
tCYCP1
25
ns
APB1 bus clock*2
tCYCP2
25
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter:Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data
sheet.
X0
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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63
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
-
10
-
31.25
μs
Unit
1/ tCYLL
X0A,
X1A
Input clock cycle
Min
Value
Typ
Pin
Conditions
name
tCYLL
Input clock pulse
PWH/tCYLL,
45
55
%
width
PWL/tCYLL
* : See " Sub crystal oscillator" in "Handling Devices" for the crystal oscillator used.
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
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MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(3) Built-in CR Oscillation Characteristics
・ Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
fCRH
Min
Value
Typ
Max
TA = + 25°C
3.92
4
4.08
TA = 0°C to + 85°C
3.9
4
4.1
3.88
4
4.12
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
2.8
4
5.2
Conditions
TA = -40°C to +
105°C
TA = + 25°C
VCC ≤ 3.6 V
TA = - 20°C ~ + 85°C
VCC ≤ 3.6 V
TA = - 20°C ~ +
105°C
VCC ≤ 3.6 V
TA =
- 40°C to + 105°C
Unit
Remarks
When trimming*1
MHz
When not trimming
Frequency
tCRWT
30
μs *2
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
・ Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
Conditions
fCRL
-
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
65
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB clock frequency*3
Value
Min Typ Max
Unit
Remarks
μs
tLOCK
100
-
-
fPLLI
fPLLO
fCLKPLL
4
5
75
-
-
16
MHz
37 multiplier
150 MHz
72
MHz
fCLKSPLL
-
-
48
MHz
After the M frequency
division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3: For more information about USB clock, see "Chapter 2-2: USB Clock Generation" in "FM3 Family
PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock
of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*1
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiplication rate
19
35 multiplier
PLL macro oscillation clock frequency
fPLLO
72
150
MHz
Main PLL clock frequency*2
fCLKPLL
72
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
USB PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
66
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Reset input time
Symbol
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Power supply rising time
tVCCR
Power supply shut down time
Time until releasing
Power-on reset
tOFF
Pin
name
Value
Max
0
-
ms
1
-
ms
1.34
18.6
ms
VCC-
tPRT
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
tVCCR
tPRT
Internal reset
CPU Operation
Reset active
tOFF
Release
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions
・ VDH_minimum : Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset
See "8. Low-Voltage Detection Characteristics"
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
(7) Base Timer Input Timing
・ Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
・ Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data
sheet.
68
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MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(8) CSIO/UART Timing
・ CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
SIN
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
70
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
・ CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
tSHOVE
VOH
VOL
tIVSLE
SIN
VIL
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
72
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSOVLI
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
Master mode
tSLSH
VIH
SCK
SOT
VIL
VIL
tF
*
VOH
VOL
tR
tIVSLE
SIN
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
74
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
VCC < 4.5 V
Min
Max
VCC ≥ 4.5 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock L pulse width
tSLSH
SCKx
-
ns
Serial clock H pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
SCK
VIL
tF
tSHSL
VIH
VIH
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
・ UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
Symbol Conditions
tSLSH
tSHSL
tF
tR
CL = 30 pF
tR
SCK
76
CONFIDENTIAL
VIL
Max
tCYCP + 10
tCYCP + 10
-
5
5
tF
tSHSL
VIH
Min
VIH
VIL
Unit Remarks
ns
ns
ns
ns
tSLSH
VIL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(9) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
ADTG
-
2tCYCP*1
-
ns
ICxx
DTTIxX
INTxx,
NMIX
*2
*3
2tCYCP*1
2tCYCP + 100*1
500
-
ns
ns
ns
WKUPx
*4
500
-
ns
FRCKx
Input pulse width
tINH,
tINL
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Waveform generator
External interrupt
NMI
Deep standby wake
up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "Block Diagram" in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTL mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
(10) Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin H width
tAHL
AIN pin L width
tALL
BIN pin H width
tBHL
BIN pin L width
tBLL
BIN rising time from
PC_Mode2 or
tAUBU
AIN pin H level
PC_Mode3
AIN falling time from
PC_Mode2 or
tBUAD
BIN pin H level
PC_Mode3
BIN falling time from
PC_Mode2 or
tADBD
AIN pin L level
PC_Mode3
AIN rising time from
PC_Mode2 or
tBDAU
BIN pin L level
PC_Mode3
AIN rising time from
PC_Mode2 or
tBUAU
BIN pin H level
PC_Mode3
2tCYCP*
ns
BIN falling time from
PC_Mode2 or
tAUBD
AIN pin H level
PC_Mode3
AIN falling time from
PC_Mode2 or
tBDAD
BIN pin L level
PC_Mode3
BIN rising time from
PC_Mode2 or
tADBU
AIN pin L level
PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC=0
ZIN pin L width
tZLL
QCR:CGSC=0
AIN/BIN rising and falling
time from determined ZIN
tZABE
QCR:CGSC=1
level
Determined ZIN level from
AIN/BIN rising and falling
tABEZ
QCR:CGSC=1
time
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block
Diagram" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
78
CONFIDENTIAL
tBLL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
2
(11) I C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Standardmode
Min
Max
Fastmode
Unit Remarks
Min Max
SCL clock frequency
fSCL
0
100
0
400 kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓ → SCL ↓
SCL clock L width
tLOW
4.7
1.3
μs
SCL clock H width
tHIGH
4.0
0.6
μs
(Repeated) START condition
setup time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 30 pF,
R = (VP/IOL)*1
Data hold time
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
tBUF
4.7
1.3
μs
START condition
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4
ns
*1:R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2:The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3:A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4:tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
80
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(12) JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
VCC < 4.5 V
Note: When the external load capacitance CL = 30 pF.
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
TCK
TMS/TDI
TDO
March 18, 2015, MB9B520M_DS706-00048-3v0-E
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D a t a S h e e t
5.
12-bit A/D Converter
・Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Symbol
Pin
name
Min
Value
Typ
Max
VZT
ANxx
-
± 1.5
± 1.7
± 10
12
± 4.5
± 2.5
± 15
VFST
ANxx
-
Conversion time
-
-
Sampling time*2
tS
-
Compare clock cycle*3
tCCK
-
State transition time to
operation permission
tSTT
Analog input capacity
CAIN
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
AVRH ± 5 AVRH ± 15
0.8*1
1.0*1
0.24
0.3
40
50
-
-
-
-
-
Unit
bit
LSB
LSB
mV
Remarks
AVRH = 2.7 V
to 5.5 V
mV
-
μs
10
μs
1000
ns
-
1.0
μs
-
9.7
pF
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
1.7
AVCC ≥ 4.5 V
kΩ
2.4
AVCC < 4.5 V
Interchannel disparity
4
LSB
Analog port input current
ANxx
5
μA
Analog input voltage
ANxx
AVRL
AVRH
V
AVRH
2.7
AVCC
V
Reference voltage
AVRL
AVSS
AVSS
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=50 MHz sampling time: 240 ns, compare time: 560 ns
AVCC < 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family
PERIPHERAL MANUAL Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
For the number of the APB bus to which the A/D Converter is connected, see "Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Analog input resistor
82
CONFIDENTIAL
RAIN
-
-
-
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
REXT
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
RAIN:
CAIN:
REXT:
Sampling time
input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.7
input resistor of A/D = 1.6 kΩ at 4.5 V < AVCC < 5.5 V ch.8 to ch.15
input resistor of A/D = 1.7 kΩ at 4.5 V < AVCC < 5.5 V ch.16 to ch.26
input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.7
input resistor of A/D = 2.3 kΩ at 2.7 V < AVCC < 4.5 V ch.8 to ch.15
input resistor of A/D = 2.4 kΩ at 2.7 V < AVCC < 4.5 V ch.16 to ch.26
input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
tCCK:
Compare time
Compare clock cycle
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
83
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・ Resolution:
・ Integral Nonlinearity:
・ Differential Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVRL
Actual conversion characteristics
AVRH
AVRL
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
84
CONFIDENTIAL
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
6.
10-bit D/A Converter
 Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Resolution
Conversion time
Integral Nonlinearity*1
Differential
Nonlinearity*1,*2
Output Voltage offset
Symbol Pin name
tC20
tC100
INL
DNL
VOFF
DAx
Min
CONFIDENTIAL
Unit
0.47
2.37
- 4.0
0.58
2.90
-
10
0.69
3.43
+ 4.0
bit
μs
μs
LSB
- 0.9
-
+ 0.9
LSB
- 20.0
3.10
2.0
-
3.80
-
10.0
+ 5.4
4.50
70
mV
mV
kΩ
MΩ
ns
Analog output
RO
impedance
Output undefined period
tR
*1: No-load
*2: Generates the max current by the CODE about 0x200
March 18, 2015, MB9B520M_DS706-00048-3v0-E
Value
Typ Max
Remarks
Load 20 pF
Load 100 pF
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
85
D a t a S h e e t
7.
USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Input H level voltage
Input L level voltage
Input
charact- Differential input
eristics sensitivity
Different common mode
range
Pin
Conditions
name
Min
Value
Max
Unit Remarks
VIH
-
2.0
VIL
-
VSS - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
2.8
3.6
V
*3
0.0
0.3
V
*3
Output H level voltage
VOH
Output L level voltage
VOL
External
pull-down
resistor =
15 kΩ
External
UDP0,
pull-up
UDM0 resistor =
1.5 kΩ
Full-Speed
Full-Speed
USBVCC + 0.3 V
*1
Minimum differential input
sensitivity [V]
Output Crossover voltage
VCRS
1.3
2.0
V *4
charactRising time
tFR
4
20
ns *5
eristics
Falling time
tFF
4
20
ns *5
Rising/falling time
tFRFM
Full-Speed
90
111.11
% *5
matching
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rising time
tLR
Low-Speed
75
300
ns *7
Falling time
tLF
Low-Speed
75
300
ns *7
Rising/falling time
tLRFM
Low-Speed
80
125
% *7
matching
*1: The switching threshold voltage of the Single-End-Receiver of USB I/O buffer is set as within V IL
(Max) = 0.8V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is
within 0.8 V to 2.5 V to the local ground reference level.
The voltage range above is said to be the common mode input voltage range.
Common mode input voltage [V]
86
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to ground and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Falling time
87
D a t a S h e e t
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See "・Low-Speed Load (Compliance Load)" for conditions of the external load.
88
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
・Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
・Low-Speed Load (Downstream Port Load) - Reference 2
CL = 200pF to
600pF
CL = 200pF to
600pF
・Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
89
D a t a S h e e t
8.
Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Parameter
Symbol Conditions
SVHR*1=
00000
Min
Value
Typ Max
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
SVHR*1=
01010
LVD stabilization
wait time
tLVDW
-
-
-
8160 ×
tCYCP*2
μs
LVD detection delay
time
tLVDDL
-
-
-
200
μs
SVHR*1=
00001
SVHR*1=
00010
SVHR*1=
00011
SVHR*1=
00100
SVHR*1=
00101
SVHR*1=
00110
SVHR*1=
00111
SVHR*1=
01000
SVHR*1=
01001
2.25
2.45
2.65
2.30
2.50
2.70
2.39
2.60
2.81
Same as SVHR =
00000 value
2.48
2.70
2.92
Same as SVHR =
00000 value
2.58
2.80
3.02
Same as SVHR =
00000 value
2.76
3.00
3.24
Same as SVHR =
00000 value
2.94
3.20
3.46
Same as SVHR =
00000 value
3.31
3.60
3.89
Same as SVHR =
00000 value
3.40
3.70
4.00
Same as SVHR =
00000 value
3.68
4.00
4.32
Same as SVHR =
00000 value
3.77
4.10
4.43
Same as SVHR =
00000 value
3.86
4.20
4.54
Same as SVHR =
00000 value
Unit
Remarks
V
V
V
When voltage drops
When voltage rises
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
V
When voltage drops
V
When voltage rises
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by
Low-Voltage Detection Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
90
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Parameter
Symbol Conditions
Min
Value
Typ Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
tLVDW
-
-
-
8160 ×
tCYCP*
μs
LVD detection
delay time
tLVDDL
-
-
-
200
μs
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
91
D a t a S h e e t
9.
Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Sector erase
time
Large Sector
Value
Typ
Max
1.1
2.7
Unit
s
Small Sector
Half word (16-bit)
write time
0.3
0.9
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
6.8
18
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle
of erase/write.
16
310
μs
(2) Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
*: At average + 85C
92
CONFIDENTIAL
Remarks
10*
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
10. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Typ
Max*
Low-speed CR Timer mode
tICNT
Unit
40
80
μs
340
680
μs
680
860
μs
503
μs
583
503
μs
μs
RTC mode,
268
Stop mode
308
Deep Standby RTC mode
Deep Standby Stop mode
268
*: The maximum value depends on the accuracy of built-in CR.
Remarks
μs
tCYCC
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Sub Timer mode
Value
When RAM is off
When RAM is on
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
93
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
94
CONFIDENTIAL
・ The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in
"FM3 Family PERIPHERAL MANUAL".
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
tRCNT
Value
Unit
Typ
Max*
148
263
μs
148
263
μs
248
463
μs
312
496
μs
503
μs
583
503
μs
μs
RTC mode,
268
Stop mode
308
Deep Standby RTC mode
Deep Standby Stop mode
268
*: The maximum value depends on the accuracy of built-in CR.
Remarks
When RAM is off
When RAM is on
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Start
95
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in
"FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in Electrical Characteristics" for the detail on the time
during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the Main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
96
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Ordering Information
On-chip
Flash
memory
On-chip
SRAM
MB9BF521KQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522KQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524KQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521KPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522KPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524KPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521MPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521MPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Part number
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Package
Packing
Plastic・QFN
(0.5 mm pitch), 48-pin
(LCC-48P-M73)
Plastic・LQFP
(0.5 mm pitch), 48-pin
(FPT-48P-M49)
Plastic・QFN
(0.5 mm pitch), 64-pin
(LCC-64P-M24)
Plastic・LQFP
(0.5 mm pitch), 64-pin
(FPT-64P-M38)
Tray
Plastic・LQFP
(0.65 mm pitch), 64-pin
(FPT-64P-M39)
Plastic・LQFP
(0.5 mm pitch), 80-pin
(FPT-80P-M37)
Plastic・LQFP
(0.65 mm pitch), 80-pin
(FPT-80P-M40)
97
D a t a S h e e t
On-chip
Flash
memory
On-chip
SRAM
MB9BF521MBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Part number
98
CONFIDENTIAL
Package
Packing
Plastic・PFBGA
(0.5 mm pitch), 96-pin
(BGA-96P-M07)
Tray
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
 Package Dimensions
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551 ± .008)SQ
*12.00± 0.10(.472 ± .004)SQ
60
0.145± 0.055
(.006 ± .002)
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
–.004
.059 +.008
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.05
(.004 ± .002)
(Stand off)
21
"A"
1
20
0.50(.020)
0.22± 0.05
(.009± .002)
C
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
March 10, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
99
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
Details of "A" part
40
61
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
21
80
0.65(.026)
C
0.60±0.15
(.024±.006)
20
1
0.32±0.06
(.013±.002)
0.13(.005)
M
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
100
CONFIDENTIAL
0.10±0.05
(.004±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B520M_DS706-00048-3v0-E, March 10, 2015
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145 ± 0.055
(.006 ± .002)
33
49
Details of "A" part
32
0.08(.003)
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
INDEX
64
17
1
0.22±0.05
(.009±.002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
March 10, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
0.10 ± 0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
101
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
32
49
+0.20
1.50 –0.10
+.008
.059 –.004
0.10(.004)
INDEX
1
16
0.65(.026)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
17
64
0.32±0.05
(.013±.002)
CONFIDENTIAL
0.10±0.10
(.004±.004)
0.25(.010)BSC
"A"
0.13(.005)
M
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
102
0~8˚
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B520M_DS706-00048-3v0-E, March 10, 2015
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Sealing method
Plastic mold
Mounting height
0.90 mm MAX
Weight
-
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.05 (.002) MAX
C
CONFIDENTIAL
0.40±0.05
(.016±.002)
(0.20 (.008))
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
March 10, 2015, MB9B520M_DS706-00048-3v0-E
0.50 (.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
103
D a t a S h e e t
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
(FPT-48P-M49)
48-pin plastic LQFP
(FPT-48P-M49)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00 ± 0.20(.354 ± .008)SQ
*7.00± 0.10(.276 ± .004)SQ
36
0.145± 0.055
(.006 ± .002)
25
24
37
0.08(.003)
13
48
"A"
1
C
CONFIDENTIAL
0°~8°
0.10 ± 0.10
(.004 ± .004)
(Stand off)
12
0.22 ± 0.05
(.008 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2
104
+0.20
1.50 –0.10 (Mounting height)
+.008
.059 –.004
INDEX
0.50(.020)
Details of "A" part
0.25(.010)
M
0.60 ± 0.15
(.024 ± .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B520M_DS706-00048-3v0-E, March 10, 2015
D a t a S h e e t
48-pin plastic QFN
Lead pitch
0.5 mm
Package width ×
package length
7.00 mm × 7.00 mm
Sealing method
Plastic mold
Mounting height
0.90 mm MAX
Weight
–
(LCC-48P-M73)
48-pin plastic QFN
(LCC-48P-M73)
7.00±0.10
(.276±.004)
5.50±0.10
(.217±.004)
7.00±0.10
(.276±.004)
0.25±0.05
(.010±.002)
5.50±0.10
(.217±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.05 (.002) MAX
C
CONFIDENTIAL
0.40±0.05
(.016±.002)
(0.20(.008))
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC48-73Sc-2-1
March 10, 2015, MB9B520M_DS706-00048-3v0-E
0.50 (.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
105
D a t a S h e e t
96-pin plastic FBGA
Lead pitch
0.5 mm
Package width ×
package length
6.00 mm × 6.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.30 mm MAX
Weight
0.08 g
(BGA-96P-M07)
96-pin plastic FBGA
(BGA-96P-M07)
6.00±0.10(.236±.004)
5.00(.197)
REF
B
0.20(.008) S B
0.50
(.020)
TYP
11
10
9
8
A
7
5.00(.197)
REF
6.00±0.10
(.236±.004)
6
5
0.50(.020)
TYP
4
3
2
1
L
K
J
H G F E D C B A
(INDEX AREA)
INDEX
0.20(.008) S A
96-ø0.30±0.10
(96-ø.012±.004)
ø0.05(.002)
M
S A B
S
0.08(.003) S
C
2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1
106
CONFIDENTIAL
1.15±0.15
(Seated height)
(.045±.006)
0.25±0.10
(Stand off)
(.010±.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B520M_DS706-00048-3v0-E, March 10, 2015
D a t a S h e e t
 Major Changes
Page
Revision 1.0
2
3
6
7
16 to 18
33
39
Section
Change Results
-
FEATURES
• CAN Interface
• A/D Converter (Max 26channels)
• UniqueID
PRODUCT LINEUP
• Function
LIST OF PIN FUNCTIONS
• List of pin numbers
• List of pin functions
I/O CIRCUIT TYPE
BLOCK DIAGRAM
46
55
57
58, 59
62
63
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
3. DC Characteristics
(1) Current Rating
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
(4-2) Operating Conditions of Main PLL (In the
case of using built-in high-speed CR for input clock
of main PLL)
5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
79
82
87
6. 10-bit D/A Converter
8. Low-Voltage Detection Characteristics
9. MainFlash Memory Write/Erase Characteristics
88
Revision 1.1
Revision 2.0
FEATURES
• On-chip Memories [Flash memory]
• USB Interface [USB function]
3
• Multi-function Serial Interface [I C]
2
• General-Purpose I/O Port
• Multi-function Timer
7
PRODUCT LINEUP
• Function
8
21
LIST OF PIN FUNCTIONS
• List of pin numbers
24
29
31
• List of pin functions
37
I/O CIRCUIT TYPE
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
• Corrected the I/O circuit type.
• Corrected the Pin state type.
Corrected the Pin function.
Added the "Type: L".
Corrected the figure.
- TIOA: input → input/output
- TIOB: output → input
Revised the value of "TBD".
Revised the Condition of "Operating temperature".
• Revised the value of "TBD".
• Added "Flash memory write/erase current".
• Revised the Condition.
• Revised the footnote.
Revised the value of "TBD".
• Deleted "(Preliminary value)".
• Revised the conversion time.
Min: 1.0μs → 0.8μs
• Revised the value of "Compare clock cycle (AVCC ≥ 4.5V )".
Min: 50ns → 40ns
• Revised the footnote.
Deleted "(Preliminary value)".
Revised the value of "TBD".
• Revised the value of "TBD".
• Revised the value of "Sector erase time".
- Large Sector Typ: 1.065s → 1.1s
- Small Sector Typ: 0.606s → 0.3s
• Revised the value of "Chip erase time".
Typ: 9.11s → 6.8s
• Deleted "(targeted value)".
Company name and layout design change
2
4
Preliminary → Data Sheet
Corrected the following description.
CAN Interface (Max 2channels) → CAN Interface
Revised the conversion time: 1.0μs → 0.8μs
Added the "Unique ID".
Added the "Unique ID".
Revised the features of Dual operation Flash memory
Added the size of each endpoint.
Corrected the mode.
High speed mode → Fast mode
Revised the features of 5V tolerant I/O.
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
• Corrected the number of A/D activating compare channels.
3ch. → 2ch.
• Revised Built-in CR .
High-speed: 4MHz(± 2%) → 4MHz
Low-speed: 100kHz(Typ) → 100kHz
Revised the footnote.
Corrected the pin number of ZIN1_1.
Corrected the pin number of ADTG_2.
Corrected pin numbers of SIN0_1 and SOT0_1.
Corrected the pin number of DTTI0X_2.
Corrested the I/O circuit figure.
TYPE H : GPIO Digital input → GPIO Digital output
107
D a t a S h e e t
Page
Section
Change Results
44
HANDLING DEVICES
• Sub crystal oscillator
Added the descriptions.
47
BLOCK DIAGRAM
Corrected the figure.
-A/D Activation Compare: 3ch → 2ch
49
MEMORY MAP
• Memory Map (2)
Added the explanatory note.
54
55
PIN STATUS IN EACH CPU STATE
• List of Pin Status
58
ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
59
3. DC Characteristics
(1) Current Rating
63
64
66
4. AC Characteristics
(2) Sub clock input Characteristics
(3) Built-in CR Oscillation Characteristics
• Built-in High-speed CR
(6) Power-on Reset Timing
68
(8) CSIO Timing
70,72,74
79
81
(11) I2C Timing
5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
82
83
• Difinition of 12-bit A/D Converter Terms
84
6. 10-bit D/A Converter
• Electrical characteristics for the D/A converter
89
8. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
90
(2) Interrupt of Low-Voltage Detection
91
9. Flash Memory Write/Erase Characteristics
92
10. Return Time Low-Power Consumption Mode
Revision 3.0
Features
2
USB Interface
36, 37
I/O Circuit Type
Memory Map
49
· Memory map(2)
PIN STATUS IN EACH CPU STAE
54
· List of Pin Status
Electrical Characteristics
56, 57
1. Absolute Maximum Ratings
59-61
108
CONFIDENTIAL
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Added the pin function of selected Analog output about type L.
• Corrected the footnote.
Sub CR timer→ Low-speed CR tim
• Added the note and footnote.
• Corrected the value of Analog reference voltage “AVRH”.
Min.: AVss → 2.7
• Added notes and footnotes.
• Added the remarks of Icc.
• Added the frequency of main clock crystal oscillator in remarks.
Added the footnote.
• Added "Frequency stabilization time"
• Added notes and footnotes.
• Added "Timing until releaseing Power-on reset"
• Added the timing chart
• Corrected the title.
UART Timing → CSIO Timing
• Corrected the notefoot.
UART → Multi-function serial
Corrected the notefoot.
UART → Multi-function serial
• Revised the Condition.
• Revised the footnote.
• Changed the name of parameter.
•Non Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• Changed the Symbol. Of Zero transition voltage.
VoT → VZT
• Changed the pin name.
AN00 to AN26 → ANxx
• Corrected the value of V0T, VFST, Ts, Tstt, and reference voltage.
• Revides footnotes.
Change the figure.
AN00 to AN26 → ANxx
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• V0T → VZT
•Revised the remark of IDDA.
D/A operation → D/A 1unit operation
• Changed the name of parameter.
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• Corrected the condition and the value.
• Added the note and the footnote.
• Added “LVD detection delay time”.
• Corrected the condition and the value.
• Added “LVD detection delay time”.
Changed the title of Chapter.
Main Flash Memory Write/Erase Characteristics →
Flash Memory Write/Erase Characteristics
Added the Chapter “Return Time from Low-Power Consumption Mode”.
Added the description of PLL for USB
Added about +B input
Added the summary of Flash memory sector and the note
Changed the pin status of I-type
· Added the Clamp maximum current
· Added about +B input
· Changed the table format
· Added Main TIMER mode current
· Moved A/D Converter Current
· Moved D/A Converter Current
MB9B520M_DS706-00048-3v0-E, March 18, 2015
D a t a S h e e t
Page
66
69-76
77
82
97, 98
Section
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main and USB PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
Electrical Characteristics
4. AC Characteristics
(9) External Input Timing
Electrical Characteristics
5. 12bit A/D Converter
Ordering Information
March 18, 2015, MB9B520M_DS706-00048-3v0-E
CONFIDENTIAL
Change Results
· Added the figure of Main PLL connection and USB PLL connection
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
Added input pulse width of WKUPx pin
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 4.5V
Change to full part number
109
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered
trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes
only and may be trademarks of their respective owners.
110
CONFIDENTIAL
MB9B520M_DS706-00048-3v0-E, March 18, 2015