The following document contains information on Cypress products.
MB9B120J Series
®
32-bit ARM Cortex®-M3 based Microcontroller
MB9BF121J
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B120J_DS706-00053
CONFIDENTIAL
Revision 2.0
Issue Date March 31, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B120J_DS706-00053-2v0-E, March 31, 2015
CONFIDENTIAL
MB9B120J Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF121J
Data Sheet (Full Production)
Description
The MB9B120J Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE10 product categories in FM3
Family Peripheral Manual.
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B120J_DS706-00053
Revision 2.0
Issue Date March 31, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
64 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: 4 Kbytes
SRAM1: 4 Kbytes
Multi-function Serial Interface (Max four channels)
2 channels with 16steps×9-bit FIFO (ch.0/ch.1), 2 channels without FIFO (ch.2/ ch.5)
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I 2C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13-bit to 16-bit length)
LIN break delimiter generate (can be changed 1-bit to 4-bit length)
Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400kbps) supported
2
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D a t a S h e e t
DMA Controller (Four channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
4 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 8channels)
[12-bit A/D Converter]
Successive Approximation type
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Not included the function to activate A/D by external trigger input
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:
4steps)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover,
the port relocate function is built-in. It can set which I/O port the peripheral function can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 23 fast general-purpose I/O Ports@32pin Package
Some ports are 5V tolerant
See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
Quadrature Position/Revolution Counter (QPRC) (One channel)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
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CONFIDENTIAL
3
D a t a S h e e t
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 1ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
External Interrupt Controller Unit
Up to 7 external interrupt input pins@32 pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.
The "Hardware" watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except RTC, Stop modes.
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillator, and Main PLL).
Main Clock:
Sub Clock:
Built-in High-speed CR Clock:
Built-in Low-speed CR Clock:
Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-Voltage detection reset
Clock Super Visor reset
4
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is asserted.
If external frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Consumption Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Four low-power consumption modes supported.
Sleep
Timer
RTC
Stop
Debug
Serial Wire Debug Port (SW-DP)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage:
VCC=2.7 V to 5.5 V
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
5
D a t a S h e e t
Product Lineup
Memory size
Product name
MB9BF121J
On-chip Flash memory
SRAM0
On-chip
SRAM1
SRAM
Total
64 Kbytes
4 Kbytes
4 Kbytes
8 Kbytes
Function
Product name
Pin count
MB9BF121J
CPU
Freq.
Power supply voltage range
DMAC
Multi-function Serial Interface
(UART/CSIO/I2C)
32
Cortex-M3
72 MHz
2.7 V to 5.5 V
4ch.
4ch. (Max)
ch.0/ch.1: FIFO
ch.2/ch.5: No FIFO
Base Timer
8ch. (Max)
(PWC/Reload timer/PWM/PPG)
A/D activation
1ch.
compare
Input capture
4ch.
Free-run timer
3ch.
MF1 unit
Timer Output compare
6ch.
Waveform
3ch.
generator
PPG
3ch.
QPRC
1ch.
Dual Timer
1 unit
Real-Time Clock
1 unit
Watchdog timer
1ch. (SW) + 1ch. (HW)
External Interrupts
7 pins (Max) + NMI × 1
I/O ports
23 pins (Max)
12-bit A/D converter
8ch. (1 unit)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz
Built-in CR
Low-speed
100 kHz
Debug Function
SW-DP
Unique ID
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for
accuracy of built-in CR.
6
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Packages
Product name
Package
LQFP: FPT-32P-M30 (0.8 mm pitch)
QFN: LCC-32P-M73 (0.5 mm pitch)
MB9BF121J
: Supported
Note: See Package Dimensions for detailed information on each package.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
7
D a t a S h e e t
Pin Assignment
FPT-32P-M30
P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
P04/SWO
P03/SWDIO
P01/SWCLK
AVRH
AVRL
VSS
VCC
32
31
30
29
28
27
26
25
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0
1
24
P21/AN14/SIN0_0/INT06_1/BIN1_1
P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0
2
23
P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0
3
22
P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1
P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0
4
21
P15/AN05/SOT0_1/INT14_0/IC03_2
P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0
5
20
P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1
P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0
6
19
P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2
VCC
7
18
P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2
C
8
17
P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2
9
10
11
12
13
14
15
16
VSS
PE2/X0
PE3/X1
INITX
DTTI0X_0/INT07_1/P46/X0A
INT14_2/P47/X1A
MD0
PE0/MD1
LQFP - 32
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
8
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
LCC-32P-M73
P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
P04/SWO
P03/SWDIO
P01/SWCLK
AVRH
AVRL
VSS
VCC
32
31
30
29
28
27
26
25
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0
1
24 P21/AN14/SIN0_0/INT06_1/BIN1_1
P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0
2
23 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0
3
22 P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1
P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0
4
P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0
5
P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0
6
19 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2
VCC
7
18 P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2
C
8
17 P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2
21 P15/AN05/SOT0_1/INT14_0/IC03_2
QFN - 32
9
10
11
12
13
14
15
16
VSS
PE2/X0
PE3/X1
INITX
DTTI0X_0/INT07_1/P46/X0A
INT14_2/P47/X1A
MD0
PE0/MD1
20 P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
9
D a t a S h e e t
List of Pin Functions
・ List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin name
I/O circuit type
Pin state type
F
K
2
P3B
RTO01_0
(PPG00_0)
IC00_0
F
J
3
TIOA1_1
SOT2_0
(SDA2_0)
P3C
RTO02_0
(PPG02_0)
IC01_0
F
K
F
J
F
K
P3A
RTO00_0
(PPG00_0)
FRCK0_0
1
INT07_0
TIOA0_1
SCK2_0
(SCL2_0)
SUBOUT_2
RTCCO_2
INT18_2
TIOA2_1
SIN2_0
4
5
10
CONFIDENTIAL
P3D
RTO03_0
(PPG02_0)
IC02_0
TIOA3_1
SCK5_1
(SCL5_1)
AIN1_0
P3E
RTO04_0
(PPG04_0)
INT19_2
TIOA4_1
SOT5_1
(SDA5_1)
BIN1_0
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Pin No
Pin name
I/O circuit type
Pin state type
6
P3F
RTO05_0
(PPG04_0)
TIOA5_1
F
J
SIN5_1
ZIN1_0
7
VCC
-
-
8
C
-
-
9
VSS
-
-
A
A
A
B
B
C
D
F
D
G
H
D
C
E
G*
M
G*
L
10
11
12
PE2
X0
PE3
X1
INITX
P46
13
X0A
DTTI0X_0
INT07_1
P47
14
X1A
INT14_2
15
16
MD0
PE0
MD1
P11
AN01
17
SIN1_1
INT02_1
FRCK0_2
AIN1_2
P12
18
AN02
SOT1_1
(SDA1_1)
TIOA6_2
IC00_2
BIN1_2
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11
D a t a S h e e t
Pin No
Pin name
I/O circuit type
Pin state type
G*
L
G*
M
G*
M
G*
L
G*
L
G*
M
P13
19
AN03
SCK1_1
(SCL1_1)
SUBOUT_1
TIOB6_2
IC01_2
RTCCO_1
ZIN1_2
P14
AN04
SIN0_1
20
INT03_1
SCK0_1
(SCL0_1)
IC02_2
P15
21
AN05
SOT0_1
(SDA0_1)
INT14_0
IC03_2
P23
22
AN12
SCK0_0
(SCL0_0)
TIOA7_1
DTTI0X_1
AIN1_1
P22
23
AN13
SOT0_0
(SDA0_0)
TIOB7_1
ZIN1_1
P21
AN14
24
SIN0_0
INT06_1
BIN1_1
12
CONFIDENTIAL
25
VCC
-
-
26
VSS
-
-
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Pin No
Pin name
I/O circuit type
Pin state type
27
AVRL
-
-
28
AVRH
-
-
E
I
E
I
E
I
E
H
29
30
31
P01
SWCLK
P03
SWDIO
P04
SWO
P0F
NMIX
32
SUBOUT_0
CROUT_1
RTCCO_0
*: 5 V tolerant I/O
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
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D a t a S h e e t
・ List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin function
ADC
Pin name
Function description
Pin No
AN01
17
AN02
18
AN03
19
AN04
AN05
20
A/D converter analog input pin.
ANxx describes ADC ch.xx.
21
AN12
22
AN13
23
AN14
24
Base Timer 0
TIOA0_1
Base timer ch.0 TIOA pin
1
Base Timer 1
TIOA1_1
Base timer ch.1 TIOA pin
2
Base Timer 2
TIOA2_1
Base timer ch.2 TIOA pin
3
Base Timer 3
TIOA3_1
Base timer ch.3 TIOA pin
4
Base Timer 4
TIOA4_1
Base timer ch.4 TIOA pin
5
Base Timer 5
TIOA5_1
Base timer ch.5 TIOA pin
6
TIOA6_2
Base timer ch.6 TIOA pin
18
TIOB6_2
Base timer ch.6 TIOB pin
19
TIOA7_1
Base timer ch.7 TIOA pin
22
TIOB7_1
Base timer ch.7 TIOB pin
23
SWCLK
Serial wire debug interface clock input pin
29
SWDIO
Serial wire debug interface data input / output pin
30
Serial wire viewer output pin
31
INT02_1
External interrupt request 02 input pin
17
INT03_1
External interrupt request 03 input pin
20
INT06_1
External interrupt request 06 input pin
24
Base Timer 6
Base Timer 7
Debugger
SWO
INT07_0
External
Interrupt
INT07_1
INT14_0
INT14-2
CONFIDENTIAL
External interrupt request 14 input pin
1
13
21
14
INT18_2
External interrupt request 18 input pin
3
INT19_2
External interrupt request 19 input pin
5
Non-Maskable Interrupt input pin
32
NMIX
14
External interrupt request 07 input pin
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Pin function
Pin name
Function description
P01
P03
P04
29
General-purpose I/O port 0
P11
17
P12
18
General-purpose I/O port 1
20
P15
21
24
General-purpose I/O port 2
23
P23
22
P3A
1
P3B
2
P3C
P3D
General-purpose I/O port 3
P3E
3
4
5
P3F
6
P46
13
P47
General-purpose I/O port 4
PE0
PE2
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
14
16
General-purpose I/O port E
PE3
10
11
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA0
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO
(operation mode 2) and as SCL0 when it is used in an I 2C
(operation mode 4).
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO
(operation mode 2) and as SCL0 when it is used in an I 2C
(operation mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA1
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a CSIO
(operation mode 2) and as SCL1 when it is used in an I 2C
(operation mode 4).
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
19
P14
P22
Multi-function
Serial 1
31
32
P21
Multi-function
Serial 0
30
P0F
P13
GPIO
Pin No
24
20
23
21
22
20
17
18
19
15
D a t a S h e e t
Pin function
Pin name
SIN2_0
Multi-function
Serial 2
SOT2_0
(SDA2_0)
SCK2_0
(SCL2_0)
SIN5_1
Multi-function
Serial 5
SOT5_1
(SDA5_1)
SCK5_1
(SCL5_1)
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_2
Function description
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA2
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a CSIO
(operation mode 2) and as SCL2 when it is used in an I 2C
(operation mode 4).
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA5
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a CSIO
(operation mode 2) and as SCL5 when it is used in an I 2C
(operation mode 4).
3
Input signal of waveform generator to control outputs
RTO00 to RTO05 of Multi-function timer 0.
13
16-bit free-run timer ch.0 external clock input pin
6
5
4
22
1
17
IC00_2
18
3
16-bit input capture input pin of Multi-function timer 0.
ICxx describes channel number.
19
IC02_0
4
IC02_2
20
IC03_2
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
CONFIDENTIAL
1
2
IC01_2
16
2
IC00_0
IC01_0
Multi-function
Timer 0
Pin No
21
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
mode.
1
2
3
4
5
6
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Pin function
Pin name
Function description
AIN1_0
AIN1_1
Quadrature
Position/
Revolution
Counter
4
QPRC ch.1 AIN input pin
17
BIN1_0
5
BIN1_1
QPRC ch.1 BIN input pin
24
BIN1_2
18
ZIN1_0
6
QPRC ch.1 ZIN input pin
ZIN1_2
RTCCO_1
23
19
RTCCO_0
32
0.5 seconds pulse output pin of Real-time clock
19
RTCCO_2
1
SUBOUT_0
32
SUBOUT_1
Sub clock output pin
SUBOUT_2
RESET
22
AIN1_2
ZIN1_1
Real-time clock
Pin No
19
1
External Reset Input pin.
A reset is valid when INITX="L".
12
MD0
Mode 0 pin.
During normal operation, MD0="L" must be input. During
serial programming to Flash memory, MD0="H" must be
input.
15
MD1
Mode 1 pin.
During serial programming to Flash memory, MD1="L"
must be input.
16
VCC
Analog/Digital Power supply Pin
7
VCC
Analog/Digital Power supply Pin
25
VSS
Analog/Digital GND Pin
9
VSS
Analog/Digital GND Pin
26
X0
Main clock (oscillation) input pin
10
X0A
Sub clock (oscillation) input pin
13
X1
Main clock (oscillation) I/O pin
11
X1A
Sub clock (oscillation) I/O pin
14
Built-in High-speed CR-osc clock output port
32
AVRH
A/D converter analog reference voltage input pin
28
AVRL
A/D converter analog reference voltage input pin
27
Power supply stabilization capacity pin
8
INITX
Mode
POWER
GND
CLOCK
CROUT_1
Analog
POWER
Analog
GND
C pin
C
March 31, 2015, MB9B120J_DS706-00053-2v0-E
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17
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1 MΩ
With standby mode control
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
A
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
CMOS level hysteresis input
Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
B
18
CONFIDENTIAL
Digital input
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Type
Circuit
Remarks
Digital input
C
Open drain output
CMOS level hysteresis input
Digital output
N-ch
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5 MΩ
With standby mode control
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
D
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
19
D a t a S h e e t
Type
Circuit
Remarks
P-ch
E
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
+B input is available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
P-ch
P-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -12 mA, IOL= 12 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input is available
Digital output
F
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
20
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Type
Circuit
P-ch
Remarks
P-ch
N-ch
Digital output
Digital output
G
R
Pull-up resistor control
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Available to control of PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital input
Standby mode control
Analog input
Input control
CMOS level hysteresis input
H
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
Mode input
21
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include
attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
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MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
23
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
24
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
25
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVRH pin and AVRL pin near this
device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located
as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
・ Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
・ Lead type
Load capacitance : Approximately 6 pF to 7 pF
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CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
•
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Set as
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
2
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS
pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as
for switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
27
D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
Turning on : VCC → AVRH
Turning off : AVRH → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash
memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
28
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Block Diagram
MB9BF121J
SWCLK,
SWDIO
SWO
SRAM0
4 Kbyte
SW-DP
ROM Table
Multi-layer AHB (Max 72MHz)
Cortex-M3 Core I
@72MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40MHz)
Dual-Timer
WatchDog Timer
(Software)
INITX
Clock Reset
Generator
WatchDog Timer
(Hardware)
SRAM1
4 Kbyte
Flash I/F
On-Chip Flash
64 Kbyte
Security
DMAC
4ch.
CSV
CLK
X0A
X1A
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
CR
100kHz
CROUT
TIOAx
TIOBx
AINx
BINx
ZINx
Base Timer
16-bit 8ch./
32-bit 4ch.
QPRC
1ch.
A/D Activation
Compare 1ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
Power On
Reset
Unit 0
Waveform Generator
3ch.
16-bit PPG
3ch.
AHB-APB Bridge : APB2 (Max 40MHz)
ANxx
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40MHz)
AVRH,
AVRL
LVD Ctrl
LVD
IRQ-Monitor
Regulator
C
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
7-pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
GPIO
P0x,
P1x,
.
.
.
Pxx
Multi-function Serial I/F
4ch.
(with FIFO ch.0/ch.1)
Multi-function Timer
PIN-Function-Ctrl
SCKx
SINx
SOTx
Memory Size
See Memory size in Product Lineup to confirm the memory size.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
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29
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
Reserved
0x4003_C000
0x4003_B000
0x4003_9000
0x4003_8000
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_6000
0x4003_5000
Peripherals
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x4003_1000
0x4003_0000
32Mbytes
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0010_0008
See "Memory map(2)" for
the memory size details.
0x0010_0000
0x4002_7000
SRAM1
SRAM0
Reserved
0x4002_6000
0x4002_5000
0x4002_4000
Security/CR Trim
Reserved
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
A/DC
QPRC
Base Timer
PPG
Reserved
0x4002_0000
MFT unit0
Reserved
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
CONFIDENTIAL
MFS
0x4002_1000
Flash
30
RTC
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Memory Map (2)
MB9BF121J
0x2008_0000
Reserved
0x2000_1000
0x2000_0000
0x1FFF_F000
SRAM1
4Kbytes
SRAM0
4Kbytes
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
0x0000_FFF8
SA0-7 (8KBx8)
Flash 64Kbytes *
0x0000_0000
* : See "MB9A420L/120L/MB9B120J Series FLASH PROGRAMMING MANUAL" to confirm the detail of
Flash memory.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
31
D a t a S h e e t
Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
0x4003_5800
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_AFFF
Reserved
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
32
CONFIDENTIAL
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
Quadrature Position/Revolution Counter
Low-Voltage Detector
DMAC register
Reserved
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
33
D a t a S h e e t
Pin status type
List of Pin Status
Function
group
Power supply
unstable
GPIO selected
A
Power-on reset
or low-voltage
detection state
Main crystal
oscillator input
pin /
External main
clock input
selected
INITX
input state
Power supply stable
INITX = 0
-
Setting disabled Setting disabled
Input enabled
Device internal
Run mode or
reset state
SLEEP mode state
Input enabled
INITX = 1
Setting disabled
Input enabled
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
SPL = 1
Maintain previous Maintain previous Hi-Z / Internal
state
state
input fixed at "0"
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
External main
clock input
selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
Maintain previous Maintain previous Maintain previous
state / When
state / When
state / When
oscillation stops*1, oscillation stops*1, oscillation stops*1,
Hi-Z /
Hi-Z /
Hi-Z /
Internal input fixed Internal input fixed Internal input fixed
at 0
at 0
at 0
B
Main crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at 0
or Input enable
Hi-Z / Internal
input fixed at 0
Hi-Z / Internal
input fixed at 0
C
INITX input pin
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
D
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
E
GPIO selected
34
CONFIDENTIAL
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z /
Input enabled
MB9B120J_DS706-00053-2v0-E, March 31, 2015
Pin status type
D a t a S h e e t
F
Function
group
Power-on reset
or low-voltage
detection state
INITX
input state
Power supply
unstable
-
Device internal
Run mode or
reset state
SLEEP mode state
Power supply stable
INITX = 0
-
INITX = 1
-
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
SPL = 1
GPIO selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
External interrupt
enabled selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous Maintain previous
state
state
state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z / Internal
input fixed at 0
Input enabled
GPIO selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
External sub
clock input
selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
Maintain previous Maintain previous
state / When
state / When
Maintain previous
oscillation stops*2, oscillation stops*2,
state
Hi-Z / Internal Hi-Z / Internal input
input fixed at 0
fixed at 0
G
H
Sub crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at 0
or Input enable
Hi-Z / Internal
input fixed at 0
Hi-Z / Internal
input fixed at 0
NMIX selected
Setting disabled Setting disabled
Setting disabled
Resource other
than above
selected
Hi-Z
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Maintain previous
state
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
GPIO selected
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
35
Pin status type
D a t a S h e e t
Function
group
Power-on reset
or low-voltage
detection state
Power supply
unstable
Serial wire debug
selected
Hi-Z
INITX
input state
Device internal
Run mode or
reset state
SLEEP mode state
Power supply stable
INITX = 0
-
INITX = 1
-
Pull-up / Input
enabled
Pull-up / Input
enabled
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
SPL = 1
Maintain previous
state
Maintain previous Maintain previous
state
state
I
GPIO selected
Setting disabled Setting disabled
Hi-Z / Internal
input fixed at 0
Setting disabled
Resource selected
J
Hi-Z
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
GPIO selected
External interrupt
enabled selected
K
Resource other
than above
selected
Setting disabled Setting disabled
Hi-Z
Hi-Z /
Input enabled
Hi-Z
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Maintain previous
state
Setting disabled
Hi-Z /
Input enabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
GPIO selected
Analog input
selected
L
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input fixed Internal input fixed Internal input fixed Internal input fixed
at 0 /
at 0 /
at 0 /
at 0 /
Analog input
Analog input
Analog input
Analog input
enabled
enabled
enabled
enabled
Resource other
than above
selected
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
GPIO selected
36
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
Pin status type
D a t a S h e e t
Function
group
INITX
input state
Power supply
unstable
-
Analog input
selected
M
Power-on reset
or low-voltage
detection state
Hi-Z
Device internal
Run mode or
reset state
SLEEP mode state
Power supply stable
INITX = 0
-
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
INITX = 1
-
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input fixed Internal input fixed Internal input fixed Internal input fixed
at 0 /
at 0 /
at 0 /
at 0 /
Analog input
Analog input
Analog input
Analog input
enabled
enabled
enabled
enabled
External interrupt
enabled selected
Resource other
than above
selected
SPL = 1
Maintain previous
state
Setting disabled Setting disabled
Setting disabled
Maintain previous Maintain previous
state
state
Hi-Z / Internal
input fixed at 0
GPIO selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode.
*2: Oscillation is stopped at Stop mode.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
37
D a t a S h e e t
Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
Analog reference voltage*1, *3
Input voltage*1
Symbol
VCC
AVRH
VI
Rating
Min
Max
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
+20
10
20
4
12
100
50
- 10
- 20
-4
- 12
- 100
- 50
350
+ 150
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
Clamp maximum current
Clamp total maximum current
L level maximum output current*4
L level average output current*5
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
Unit
Remarks
V
V
V
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*7
*7
4 mA type
12 mA type
4 mA type
12 mA type
4 mA type
12 mA type
4 mA type
12 mA type
H level total maximum output current
∑IOH
H level total average output current*6
∑IOHAV
Power consumption
PD
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
38
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
*7:
・
・
・
・
・
・
・
・
See List of Pin Functions and I/O Circuit Type about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumption modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
VCC
Analog input
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
39
D a t a S h e e t
2.
Recommended Operating Conditions
(VSS = AVRL = 0.0V)
Parameter
Symbol
Conditions
Value
Min
Max
Unit
Remarks
2.7*2
5.5
V
2.7
VCC
V
Analog reference voltage
VSS
VSS
V
Smoothing capacitor
1
10
μF
For regulator*1
When
mounted on
- 40
+ 105
°C
four-layer
PCB
Operating
FPT-32P-M30,
TA
When
temperature LCC-32P-M19
mounted on
double-sided
- 40
+ 85
°C
single-layer
PCB
*1: See C Pin in Handling Devices for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or
more, instruction execution and low voltage detection function by built-in High-speed CR (including Main
PLL is used) or built-in Low-speed CR is possible to operate only.
Power supply voltage
VCC
AVRH
AVRL
CS
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under
any conditions other than these conditions may adversely affect reliability of device and could result in
device failure. No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other than listed
herein, please contact sales representatives beforehand.
40
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
3. DC Characteristics
(1) Current Rating
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
PLL
Run mode
Run
mode
current
ICC
VCC
Sleep
mode
current
ICCS
High-speed
CR
Run mode
Sub
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
CPU : 72 MHz,
Peripheral : 36 MHz
Instruction on Flash
CPU:72 MHz,
Peripheral : the clock stops
NOP operation
Instruction on Flash
CPU : 72 MHz,
Peripheral : 36 MHz
Instruction on RAM
Value
Unit Remarks
Typ Max
27
35
mA
*1, *5
18
22
mA
*1, *5
23
29
mA
*1
CPU/ Peripheral : 4 MHz*2
Instruction on Flash
2.2
3.1
mA
*1
CPU/ Peripheral : 32 kHz
Instruction on Flash
73
910
μA
*1, *6
CPU/ Peripheral : 100k Hz
Instruction on Flash
105
930
μA
*1
Peripheral : 36 MHz
17
20
mA
*1, *5
Peripheral : 4 MHz*2
1.3
2.2
mA
*1
Peripheral : 32 kHz
64
890
μA
*1, *6
Peripheral : 100 kHz
80
910
μA
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
41
D a t a S h e e t
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Main
Timer mode
ICCT
Timer
mode
current
Sub
Timer mode
ICCT
VCC
RTC
mode
current
ICCR
Stop
mode
current
ICCH
Value
Unit Remarks
Typ Max
Conditions
RTC mode
Stop mode
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
3.5
4.1
mA *1
-
4.6
mA *1
15
45
μA *1
-
740
μA *1
13
39
μA *1
-
580
μA *1
12
33
μA *1
-
550
μA *1
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
LVD current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Low-Voltage
detection
circuit (LVD)
power supply
current
Symbol
ICCLVD
Pin
name
Conditions
VCC
At operation
for reset
VCC = 5.5V
At operation
for interrupt
VCC = 5.5 V
Value
Typ
Max
Unit
Remarks
0.13
0.3
μA
At not detect
0.13
0.3
μA
At not detect
Flash memory current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Flash
memory
write/erase
current
Symbol
Pin
name
Conditions
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
Unit
9.5
mA
11.2
Remarks
A/D convertor current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply
current
Reference
power supply
current
42
CONFIDENTIAL
Symbol
Pin
name
Conditions
Value
Typ
Max
Unit
ICCAD
VCC
At operation
0.7
0.9
mA
1.1
1.97
mA
AVRH
At operation
AVRH=5.5 V
At stop
AVRH=5.5 V
0.1
1.7
μA
ICCAVRH
Remarks
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(2) Pin Characteristics
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter Symbol Pin name
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
VIHS
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
4 mA type
H level
output
voltage
VOH
12 mA type
4 mA type
L level
output
voltage
VOL
12 mA type
Input leak
current
IIL
-
Pull-up
resistance
value
RPU
Pull-up pin
Input
capacitance
CIN
Other than
VCC,
VSS,
AVRH,
AVRL
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
Min
Value
Typ
Max
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
Conditions
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
Unit Remarks
kΩ
pF
43
D a t a S h e e t
4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
4
4
48
20
Unit
Remarks
When crystal oscillator
is connected
Input frequency
fCH
When using external
4
48
MHz
Clock
X0,
When using external
Input clock cycle
tCYLH
20.83
250
ns
X1
Clock
Input clock pulse
PWH/tCYLH,
When using external
45
55
%
width
PWL/tCYLH
Clock
Input clock rise
tCF,
When using external
5
ns
time and fall time
tCR
Clock
fCM
72
MHz Master clock
Base clock
fCC
72
MHz
(HCLK/FCLK)
Internal operating
clock*1 frequency
fCP0
40
MHz APB0 bus clock*2
fCP1
40
MHz APB1 bus clock*2
fCP2
40
MHz APB2 bus clock*2
Base clock
tCYCC
13.8
ns
(HCLK/FCLK)
Internal operating
t
25
ns
APB0 bus clock*2
CYCP0
clock*1 cycle time
tCYCP1
25
ns
APB1 bus clock*2
tCYCP2
25
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
MHz
X0
44
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
-
10
-
31.25
μs
Unit
fCL
X0A,
X1A
Input clock cycle
Min
Pin
Conditions
name
tCYLL
Input clock pulse
PWH/tCYLL,
45
55
width
PWL/tCYLL
*: See Sub crystal oscillator in Handling Devices for the crystal oscillator used.
%
Remarks
When crystal
oscillator is
connected*
When using
external clock
When using
external clock
When using
external clock
X0A
March 31, 2015, MB9B120J_DS706-00053-2v0-E
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45
D a t a S h e e t
(3) Built-in CR Oscillation Characteristics
・
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
fCRH
Value
Min Typ Max
Conditions
TA = + 25°C,
3.6 V < VCC ≤ 5.5 V
TA =0°C to + 85°C,
3.6 V < VCC ≤ 5.5 V
TA = - 40°C to + 105°C,
3.6 V < VCC ≤ 5.5 V
TA = + 25°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 85°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 40°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 40°C to + 105°C
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
2.8
4
5.2
Unit
Remarks
When trimming*1
MHz
When not trimming
Frequency
tCRWT
30
μs
*2
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency
trimming/temperature trimming.
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR
clock as a source clock.
・
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
46
CONFIDENTIAL
Symbol
Conditions
fCRL
-
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(4-1) Operating Conditions of Main PLL
(In the case of using main clock for input of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait
tLOCK
100
μs
time*1 (LOCK UP time)
PLL input clock frequency
fPLLI
4
16
MHz
PLL multiple rate
5
37 multiple
PLL macro oscillation clock frequency
fPLLO
75
150 MHz
Main PLL clock frequency*2
fCLKPLL
72
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
(4-2) Operating Conditions of Main PLL
(In the case of using built-in High-speed CR for input clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait
tLOCK
100
μs
time*1 (LOCK UP time)
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiple rate
19
35 multiple
PLL macro oscillation clock frequency
fPLLO
72
150
MHz
Main PLL clock frequency*2
fCLKPLL
72
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
March 31, 2015, MB9B120J_DS706-00053-2v0-E
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47
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Power supply rising time
tVCCR
Power supply shut down time
Time until releasing
Power-on reset
tOFF
Pin
name
VCC
tPRT
Value
Unit
Min
Max
0
-
ms
1
-
ms
0.34
3.15
ms
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
tVCCR
tPRT
Internal reset
CPU Operation
Glossary
・ VCC_minimum
・ VDH_minimum
48
CONFIDENTIAL
Reset active
tOFF
Release
start
: Minimum VCC of recommended operating conditions.
: Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset.
See 6. Low-Voltage Detection Characteristics.
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(7) Base Timer Input Timing
Timer input timing
・
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
・
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see Block Diagram in this data sheet.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
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49
D a t a S h e e t
(8) CSIO/UART Timing
・
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to clock synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see ■Block Diagram in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
50
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
51
D a t a S h e e t
・
CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to clock synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see ■Block Diagram in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
52
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
53
D a t a S h e e t
・
CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to clock synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see ■Block Diagram in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
54
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSOVLI
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
Master mode
tSLSH
SCK
SOT
VIH
VIL
VIL
tF
*
VOH
VOL
tR
tIVSLE
SIN
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
55
D a t a S h e e t
・
CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
VCC < 4.5 V
Min
Max
VCC ≥ 4.5 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock L pulse width
tSLSH
SCKx
-
ns
Serial clock H pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to clock synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see ■Block Diagram in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
56
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
SCK
VIL
tF
tSHSL
VIH
VIH
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
・
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
CL = 30 pF
tR
SCK
VIL
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
Value
Symbol Conditions
Max
tCYCP + 10
tCYCP + 10
-
5
5
tF
tSHSL
VIH
Min
VIH
VIL
Unit Remarks
ns
ns
ns
ns
tSLSH
VIL
57
D a t a S h e e t
(9) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
FRCKx
Input pulse width
tINH,
tINL
Conditions
-
Value
Unit
Min
Max
2tCYCP*1
-
ns
ICxx
1
DTTIxX
-
2tCYCP*
-
ns
INTxx,
NMIX
*2
2tCYCP + 100*1
-
ns
*3
500
-
ns
Remarks
Free-run timer input
clock
Input capture
Wave form
generator
External interrupt,
NMI
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which, Multi-function Timer, External interrupt is connected to, see Block
Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTC mode, in Timer mode.
58
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(10) Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin H width
tAHL
AIN pin L width
tALL
BIN pin H width
tBHL
BIN pin L width
tBLL
Time from AIN pin H
PC_Mode2 or
tAUBU
level to BIN rise
PC_Mode3
Time from BIN pin H level
PC_Mode2 or
tBUAD
to AIN fall
PC_Mode3
Time from AIN pin L level
PC_Mode2 or
tADBD
to BIN fall
PC_Mode3
Time from BIN pin L level
PC_Mode2 or
tBDAU
to AIN rise
PC_Mode3
Time from BIN pin H level
PC_Mode2 or
tBUAU
to AIN rise
PC_Mode3
2tCYCP*
ns
Time from AIN pin H level
PC_Mode2 or
tAUBD
to BIN fall
PC_Mode3
Time from BIN pin L level
PC_Mode2 or
tBDAD
to AIN fall
PC_Mode3
Time from AIN pin L level
PC_Mode2 or
tADBU
to BIN rise
PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC=0
ZIN pin L width
tZLL
QCR:CGSC=0
Time from determined ZIN
level to AIN/BIN rise and
tZABE
QCR:CGSC=1
fall
Time from AIN/BIN rise
and fall time to determined
tABEZ
QCR:CGSC=1
ZIN level
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see Block
Diagram in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
tBLL
59
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
60
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(11) I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Standard-mode Fast-mode
Unit Remarks
Min
Max
Min Max
SCL clock frequency
fSCL
0
100
0
400 kHz
(Repeated) START condition
tHDSTA
4.0
0.6
μs
hold time SDA ↓ → SCL ↓
SCL clock L width
tLOW
4.7
1.3
μs
SCL clock H width
tHIGH
4.0
0.6
μs
(Repeated) Start condition
setup time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 30 pF,
Data hold time
R = (Vp/IOL)*1
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
Stop condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
Stop condition and
tBUF
4.7
1.3
μs
Start condition
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4 ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
61
D a t a S h e e t
(12) SWD Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol Pin name
Conditions
SWCLK,
SWDIO
SWCLK,
SWDIO hold time
tSWH
SWDIO
SWCLK,
SWDIO delay time
tSWD
SWDIO
Note: When the external load capacitance CL = 30 pF.
SWDIO setup time
tSWS
Value
Min
Max
Unit
-
15
-
ns
-
15
-
ns
-
-
45
ns
Remarks
SWCLK
SWDIO
(When input)
SWD
SWDIO
(When output)
62
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
5. 12-bit A/D Converter
・Electrical characteristics for the A/D converter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Resolution
Integral Nonlinearity
Differential
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Conversion time
Sampling time*2
Compare clock cycle*3
State transition time to
operation permission
Symbol Pin name
Min
Value
Typ
Max
Unit
-
-
-
± 3.0
12
± 4.5
bit
LSB
-
-
-
± 2.5
± 3.5
LSB
VZT
ANxx
-
± 15
± 20
mV
VFST
ANxx
-
tS
tCCK
-
1.0*1
0.3
50
-
10
1000
μs
μs
ns
tSTT
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
9.7
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
Analog port input leak
current
Analog input voltage
-
-
-
-
ANxx
-
AVRH ± 15 AVRH ± 20
Remarks
AVRH
= 2.7 V to
5.5 V
mV
-
1.5
2.2
4
LSB
-
5
μA
kΩ
VCC ≥ 4.5 V
VCC < 4.5 V
ANxx
AVRL
AVRH
V
AVRH
2.7
VCC
V
Reference voltage
AVRL
VSS
VSS
V
*1: Conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is when the value of sampling time: 300 ns, the value of
sampling time: 700 ns.
Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family
Peripheral Manual Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (tC) is the value of (Equation 2).
-
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
63
D a t a S h e e t
ANxx
Analog input pin
Analog signal
source
REXT
RAIN
Rin
Comparator
CAIN
Cin
(Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9
tS: Sampling time
RAIN: Input resistance of A/D = 1.5 kΩ at 4.5 V < VCC < 5.5 V
Input resistance of A/D = 2.2 kΩ at 2.7 V < VCC < 4.5 V
CAIN: Input capacity of A/D = 9.7 pF at 2.7 V < VCC < 5.5 V
REXT: Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC: Compare time
tCCK: Compare clock cycle
64
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・ Resolution:
・ Integral Nonlinearity:
・ Differential Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Differential Nonlinearity
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Ideal characteristics
VNT
Actual conversion characteristics
AVRH
AVRL
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
(Actually-measured
value)
(Actually-measured
value)
0x(N-2)
VZT (Actually-measured value)
AVRL
V(N+1)T
0x(N-1)
65
D a t a S h e e t
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Parameter
Value
Typ
Symbol
Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
SVHR*1 = 00000
LVD stabilization
wait time
tLVDW
-
-
-
8160 ×
tCYCP*2
μs
LVD detection
delay time
tLVDDL
-
-
-
200
μs
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
Min
Max
2.25
2.45
2.65
2.30
2.50
2.70
2.39
2.60
2.81
Same as SVHR = 0000 value
2.48
2.70
2.92
Same as SVHR = 0000 value
2.58
2.80
3.02
Same as SVHR = 0000 value
2.76
3.00
3.24
Same as SVHR = 0000 value
2.94
3.20
3.46
Same as SVHR = 0000 value
3.31
3.60
3.89
Same as SVHR = 0000 value
3.40
3.70
4.00
Same as SVHR = 0000 value
3.68
4.00
4.32
Same as SVHR = 0000 value
3.77
4.10
4.43
Same as SVHR = 0000 value
3.86
4.20
4.54
Same as SVHR = 0000 value
Unit
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low
voltage detection reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
66
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Parameter
Symbol Conditions
Detected voltage
VDL
SVHI = 00011
Released voltage
VDH
Detected voltage
VDL
SVHI = 00100
Released voltage
VDH
Detected voltage
VDL
SVHI = 00101
Released voltage
VDH
Detected voltage
VDL
SVHI = 00110
Released voltage
VDH
Detected voltage
VDL
SVHI = 00111
Released voltage
VDH
Detected voltage
VDL
SVHI = 01000
Released voltage
VDH
Detected voltage
VDL
SVHI = 01001
Released voltage
VDH
Detected voltage
VDL
SVHI = 01010
Released voltage
VDH
LVD stabilization
tLVDW
wait time
LVD detection
tLVDDL
delay time
*: tCYCP indicates the APB2 bus clock cycle time.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
Min
Value
Typ Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
-
-
-
-
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
8160 ×
tCYCP*
200
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
μs
67
D a t a S h e e t
7. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Value
Typ
Max
Unit
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
Half word (16-bit) write time
16
282
μs
time
Includes write time prior to internal
Chip erase time
2.4
5.6
s
erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of
erase/write.
Sector erase time
0.3
0.7
s
(2) Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
*: At average + 85C
68
CONFIDENTIAL
Remarks
10*
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
8. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Typ
Max*
tCYCC
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
Value
tICNT
Sub Timer mode
Unit
μs
43
83
μs
310
620
μs
534
724
μs
479
μs
RTC mode,
278
Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Remarks
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
69
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
70
CONFIDENTIAL
・ The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
tRCNT
Value
Unit
Typ
Max*
149
264
μs
149
264
μs
318
603
μs
308
583
μs
443
μs
RTC mode,
248
Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Remarks
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
Start
71
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
・ The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time
during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
72
CONFIDENTIAL
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
Ordering Information
Part number
Package
MB9BF121JPMC
Plastic・LQFP32 (0.8 mm pitch), 32 pin
(FPT-32P-M30)
MB9BF121JWQN
Plastic・QFN32 (0.5 mm pitch), 32 pin
(LCC-32P-M73)
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
73
D a t a S h e e t
Package Dimensions
32-pin plastic LQFP
Lead pitch
0.80 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm MAX
(FPT-32P-M30)
32-pin plastic LQFP
(FPT-32P-M30)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.05
* 7.00±0.10(.276±.004)SQ
24
0.13 –0.00
+.002
.005 –.000
17
16
25
0.10(.004)
Details of "A" part
1.60 MAX (Mounting height)
(.063) MAX
INDEX
0.25(.010)
9
32
0~7°
1
0.80(.031)
C
0.35
.014
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
74
CONFIDENTIAL
"A"
8
+0.08
–0.03
+.003
–.001
0.20(.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M73)
32-pin plastic QFN
(LCC-32P-M73)
5.00±0.10
(.197±.004)
3.20±0.10
(.068±.004)
0.25±0.05
(.010±.002)
INDEX AREA
5.00±0.10
(.197±.004)
3.20±0.10
(.068±.004)
0.75±0.05
(.030±.002)
(0.20)
((.008))
C
0.40±0.05
(.016±.002)
1PIN CORNER
C0.25(C.010)
0.02 +0.03
-0.02
(.0008 +.0012
-.0008 )
2013 FUJITSU SEMICONDUCTOR LIMITED HMbC32-73Sc-1-1
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
0.50(.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
75
D a t a S h e e t
Major Changes
Page
Section
Revision 0.1
Revision 1.0
2
FEATURES
4
FEATURES
-
Initial release
-
Preliminary → Data Sheet
Company name and layout design change
Revised I2C operation mode name
Revised Channel number of MFT A/D activation compare
・Revised channel number of MFT A/D activation compare
・Added notes of Built-in high speed CR accuracy
Corrected Package code
Corrected Package code
Corrected the remarks of type E and F
Revised Channel number of MFT A/D activation compare
6
PRODUCT LINEUP
7
9
20
29
PACKAGES
PIN ASSIGNMENT
I/O CIRCUIT TYPE
BLOCK DIAGRAM
ELECTRICAL CHARACTERISTICS
3.DC Characteristics (1) Current Rating
ELECTRICAL CHARACTERISTICS
3.AC Characteristics (6)Power-on Reset Timing
40,42
48
Change Results
Revised the values of “TBD”
Revised the values of “TBD”
61
ELECTRICAL CHARACTERISTICS
3.AC Characteristics (11) I2C Timing
・Revised I2C operation mode name
・Revised the value of noise filter
・Revised the notes explanation
62
ELECTRICAL CHARACTERISTICS
3.AC Characteristics (12) SWD Timing
Added the value of SWDIO delay time
63
ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter Electrical characteristics
68
ELECTRICAL CHARACTERISTICS
7. Flash Memory Write/Erase Characteristics
69,71
ELECTRICAL CHARACTERISTICS
8. Return Time from Low-Power Consumption
Mode
PACKAGE DIMENSIONS
75
Revision 2.0
20
I/O Circuit Type
Memory Map
31
· Memory map(2)
Electrical Characteristics
38, 39
1. Absolute Maximum Ratings
Electrical Characteristics
40
2. Recommended Operation Conditions
Electrical Characteristics
41, 42
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
47
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
48
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
50-57
4. AC Characteristics
(8) CSIO/UART Timing
Electrical Characteristics
63
5. 12bit A/D Converter
73
Ordering Information
76
CONFIDENTIAL
・Added the value of sampling time
・Revised the notes explanation
・Revised the value of Differential Nonlinearity +/-2.5LSB →+/-3.5LSB
・Deleted (Preliminary value) description
・Revised the values of “TBD”
・Revised the notes of Erase/write cycles and data hold time
・Deleted (target value) description
Revised the values of “TBD”
Corrected Package code
Added about +B input
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added about +B input
Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main Timer mode current
Added the figure of Main PLL connection
Changed the figure of timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
Changed notation of part number
MB9B120J_DS706-00053-2v0-E, March 31, 2015
D a t a S h e e t
March 31, 2015, MB9B120J_DS706-00053-2v0-E
CONFIDENTIAL
77
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
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MB9B120J_DS706-00053-2v0-E, March 31, 2015