The following document contains information on Cypress products.
MB9B520TA Series
®
32-bit ARM Cortex®-M3 based Microcontroller
MB9BF529SA/TA, MB9BF528SA/TA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B520TA_DS706-00060
CONFIDENTIAL
Revision 2.0
Issue Date January 30, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
CONFIDENTIAL
MB9B520TA Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF529SA/TA, MB9BF528SA/TA
Data Sheet (Full Production)
Description
The MB9B520TA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN,
UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE12 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B520TA_DS706-00060
Revision 2.0
Issue Date January 30, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 60 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Main area:
Up to 1.5Mbytes(1008Kbytes(ROM0) + 512Kbytes(ROM1) of Upper bank and 16Kbytes(ROM0)
of Lower bank.)
Work area
64 Kbytes(ROM1) of Lower bank
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 96 Kbytes
SRAM1: Up to 96 Kbytes
External Bus Interface
Supports SRAM, NOR NAND Flash memory device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
USB Interface
The USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each EndPoint is as follows.
EndPoint 0, 2 to 5:64 bytes
EndPoint 1: 256 bytes
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer support
USB Device connected/dis-connected automatic detection
Automatic processing of the IN/OUT token handshake packet
Max 256-byte packet-length supported
Wake-up function supported
2
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
CAN Interface
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Multi-function Serial Interface (Max 16channels)
16 channels with 16steps×9-bit FIFO
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I 2C
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit length)
LIN break delimiter generation (can be changed to 1 to 4-bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard - mode (Max 100kbps) / Fast - mode (Max 400kbps) supported
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 1.0μs @ 2.7V to 5.5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
3
D a t a S h e e t
D/A Converter (Max 2channels)
R-2R type
10-bit resolution
Base Timer (Max 16channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 154 high-speed general-purpose I/O Ports@176pin Package
Some ports are 5V tolerant.
See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins.
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
Quadrature Position/Revolution Counter (QPRC) (Max 2channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
HDMI-CEC/Remote Control Reception (Up to 2channels)
HDMI-CEC transmission
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
HDMI-CEC reception
Automatic ACK reply function available
Line error detection function available
Remote control reception
4 bytes reception buffer
Repeat code detection function available
4
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch
Input capture × 4ch
Output compare × 6ch
A/D activaion compare × 2ch
Waveform generator × 3ch
16-bit PPG timer × 3ch
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
Up to 32 external interrupt input pins @ 176pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby
RTC, Deep standby STOP modes.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
5
D a t a S h e e t
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock
Sub Clock
Built-in high-speed CR Clock
Built-in low-speed CR Clock
Main PLL Clock
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is asserted.
If external frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable between keeping the value of RAM and not)
Deep standby STOP (selectable between keeping the value of RAM and not)
Debug
・Serial Wire JTAG Debug Port (SWJ-DP)
・Embedded Trace Macrocell (ETM)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage : VCC
= 2.7V to 5.5V
: USBVCC = 3.0V to 3.6V (when USB is used)
= 2.7V to 5.5V (when GPIO is used)
6
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Product Lineup
Memory size
Product name
On-chip
Main area
Flash
Work area
memory
SRAM0
On-chip
SRAM1
SRAM
Total
MB9BF528SA/TA
1 Mbytes
MB9BF529SA/TA
1.5 Mbytes
64 Kbytes
80 Kbytes
80 Kbytes
160 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
192 Kbytes
MB9BF528SA
MB9BF529SA
MB9BF528TA
MB9BF529TA
Function
Product name
Pin count
CPU
Freq.
Power supply voltage range
USB2.0 (Function/Host)
CAN
DMAC
External Bus Interface
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
2ch.
compare
Input capture
4ch.
Free-run timer
3ch.
MFTimer Output compare
6ch.
Waveform
3ch.
generator
PPG
3ch.
QPRC
Dual Timer
HDMI-CEC/ Remote Control
Reception
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
144
176/192
Cortex-M3
60 MHz
2.7V to 5.5V
1ch.
1ch.
8ch.
Addr: 25 bit (Max)
R/Wdata : 8/16 bit (Max)
CS: 8 (Max)
SRAM , NOR Flash memory , NAND Flash memory
16ch. (Max) with 16steps×9-bit FIFO
16ch. (Max)
1 unit
1ch.(Max)
2ch. (Max)
1 unit
2ch. (Max)
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
32pins (Max) + NMI × 1
122pins (Max)
154pins (Max)
24ch. (2 units)
2ch. (Max)
Yes
2ch.
4 MHz
100 kHz
SWJ-DP / ETM
Yes
7
D a t a S h e e t
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See "Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
8
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Packages
Product name
Package
LQFP: FPT-144P-M08 (0.5mm pitch)
LQFP: FPT-176P-M07 (0.5mm pitch)
BGA: BGA-192P-M06 (0.8mm pitch)
MB9BF528SA
MB9BF529SA
-
MB9BF528TA
MB9BF529TA
-
: Supported
Note: See "Package Dimensions" for detailed information on each package.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
9
D a t a S h e e t
Pin Assignment
FPT-176P-M07
VSS
P81/UDP0
P80/UDM0
USBVCC
PF5/SCK6_2/IGTRG0_1/INT08_0/WKUP3/CEC1_0
PF4/SOT6_2/TIOB06_0/INT07_0
PF3/SIN6_2/TIOA06_0/INT06_0
P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0
P61/UHCONX/SOT5_0/TIOB02_2/MAD19_0
P62/ADTG_3/SCK5_0/MAD18_0
PD3/TIOB03_2/MAD17_0
PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0
PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0
PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0
PCF/CTS4_0/TIOB08_2/MAD13_0
PCE/RTS4_0/TIOB06_1/MAD12_0
PCD/MAD11_0
PCC/MAD10_0
PCB/MAD09_0
VSS
VCC
PCA/SCK15_0/MAD08_0
PC9/SOT15_0/MAD07_0
PC8/SIN15_0/MAD06_0
PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0
PC6/SCK14_0/TIOA14_0/MAD04_0
PC5/SOT14_0/TIOA10_2/MAD03_0
PC4/SIN14_0/TIOA08_2/CEC0_1/MAD02_0
PC3/TIOA06_1/MAD01_0
PC2/SCK13_0/MAD00_0
PC1/DA1_0/SOT13_0/MCSX4_0
PC0/DA0_0/SIN13_0/MCSX5_0
P95/TIOB13_0/INT27_0
P94/SCK5_1/TIOB12_0/INT26_0
P93/SOT5_1/TIOB11_0
P92/SIN5_1/TIOB10_0
P91/TIOB09_0/INT31_0
P90/TIOB08_0/INT30_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
VCC
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
(TOP VIEW)
VCC
1
132
VSS
PA0/SIN8_0/TIOA08_0/MAD21_0
2
131
VCC
PA1/SOT8_0/TIOA09_0/MAD22_0
3
130
P83/MCSX6_0
PA2/SCK8_0/TIOA10_0/MAD23_0
4
129
P82/MCSX7_0
PA3/SIN9_0/TIOA11_0/MAD24_0
5
128
PF6/NMIX/WKUP0
PA4/RX0_2/SOT9_0/TIOA12_0/INT03_0
6
127
P20/AIN1_1/INT05_0/CROUT_0
PA5/TX0_2/SCK9_0/TIOA13_0/INT10_2
7
126
P21/SIN0_0/BIN1_1/INT06_1
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
8
125
P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
9
124
P23/AN22/SCK0_0/RTO00_1/TIOA07_1
P07/TRACED2/ADTG_0/SCK4_2
10
123
P24/AN21/SIN2_1/RTO01_1/INT01_2
P08/TRACED3/CTS4_2/TIOA00_2
11
122
P25/AN20/SOT2_1/RTO02_1
P09/TRACECLK/RTS4_2/TIOB00_2
12
121
P26/AN19/SCK2_1/RTO03_1
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
13
120
P27/AN18/SCK12_0/RTO04_1/INT02_2
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
14
119
P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
15
118
P29/AN16/SIN12_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
16
117
AVRH
P54/SOT6_0/TIOB01_2/MALE_0
17
116
AVRL
P55/ADTG_1/SCK6_0/MRDY_0
18
115
AVSS
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
19
114
AVCC
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
113
PB7/TIOB12_1/INT23_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
112
PB6/SCK0_2/TIOA12_1/INT22_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
111
PB5/SOT0_2/TIOB11_1/INT21_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
110
PB4/SIN0_2/TIOA11_1/INT20_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
109
PB3/TIOB10_1/INT19_0
LQFP - 176
P5C/TIOA06_2/INT28_0
25
108
PB2/SCK7_2/TIOA10_1/INT18_0
P5D/TIOB06_2/INT29_0
26
107
PB1/SOT7_2/TIOB09_1/INT17_0
VSS
27
106
PB0/SIN7_2/TIOA09_1/INT16_0
P30/AIN0_0/TIOB00_1/INT03_2/WKUP4
28
105
P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
P31/SCK6_1/BIN0_0/TIOB01_1/INT04_2
29
104
P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_2
30
103
P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
P33/ADTG_6/SIN6_1/TIOB03_1/INT04_0
31
102
P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
P34/TX0_1/FRCK0_0/TIOB04_1
32
101
P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
P35/RX0_1/IC03_0/TIOB05_1/INT08_1
33
100
P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
34
99
P19/AN09/SCK2_2/INT22_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
35
98
P18/AN08/SOT2_2/INT21_1
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
P48/SIN3_2/INT14_1
P49/SOT3_2/AIN0_1/TIOB00_0
P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0
P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0
P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0
P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0
P4E/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0
P70/TX0_0/TIOA04_2/MADATA05_0
P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0
P72/SIN2_0/INT14_2/WKUP2/MADATA07_0
P73/SOT2_0/INT15_2/MADATA08_0
P74/SCK2_0/MADATA09_0
P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
P7B/TIOB07_0/INT10_0
P7C/TIOA07_0/INT11_0
P7D/TIOA14_1/INT12_0
P7E/TIOB14_1/INT24_0
P7F/TIOA15_1/INT25_0
PF0/SIN1_2/TIOB15_1/INT13_0/CEC0_0
PF1/SOT1_2/TIOA08_1/INT14_0
PF2/SCK1_2/TIOB08_1/INT15_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
INITX
VCC
56
89
P47/X1A
44
55
P10/AN00
VSS
P46/X0A
90
54
43
VCC
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P3F/RTO05_0/TIOA05_1
53
91
VSS
42
52
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA04_1
C
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
92
51
93
41
P45/SCK11_0/TIOA05_0
40
P3D/RTO03_0/TIOA03_1
50
P14/AN04/SIN0_1/IC02_2/INT03_1
P3C/RTO02_0/TIOA02_1
P44/SOT11_0/TIOA04_0
94
49
39
P43/ADTG_7/SIN11_0/TIOA03_0
P15/AN05/SOT0_1/IC03_2
P3B/RTO01_0/TIOA01_1
48
95
P42/SCK10_0/TIOA02_0/MCLKOUT_0
38
47
P16/AN06/SCK0_1/INT20_1
P3A/RTO00_0/TIOA00_1
46
P17/AN07/SIN2_2/INT04_1
96
45
97
37
P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0
36
P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0
P38/SCK5_2/IC00_0/INT11_1
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
FPT-144P-M08
VSS
P81/UDP0
P80/UDM0
USBVCC
PF5/IGTRG0_1/INT08_0/WKUP3/CEC1_0
P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0
P61/UHCONX/SOT5_0/TIOB02_2/MAD19_0
P62/ADTG_3/SCK5_0/MAD18_0
PD3/TIOB03_2/MAD17_0
PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0
PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0
PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0
PCF/CTS4_0/TIOB08_2/MAD13_0
PCE/RTS4_0/TIOB06_1/MAD12_0
PCD/MAD11_0
PCC/MAD10_0
PCB/MAD09_0
VSS
VCC
PCA/SCK15_0/MAD08_0
PC9/SOT15_0/MAD07_0
PC8/SIN15_0/MAD06_0
PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0
PC6/SCK14_0/TIOA14_0/MAD04_0
PC5/SOT14_0/TIOA10_2/MAD03_0
PC4/SIN14_0/TIOA08_2/CEC0_1/MAD02_0
PC3/TIOA06_1/MAD01_0
PC2/SCK13_0/MAD00_0
PC1/DA1_0/SOT13_0/MCSX4_0
PC0/DA0_0/SIN13_0/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
VCC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
(TOP VIEW)
VCC
1
108
VSS
PA0/SIN8_0/TIOA08_0/MAD21_0
2
107
VCC
PA1/SOT8_0/TIOA09_0/MAD22_0
3
106
P83/MCSX6_0
PA2/SCK8_0/TIOA10_0/MAD23_0
4
105
P82/MCSX7_0
PA3/SIN9_0/TIOA11_0/MAD24_0
5
104
PF6/NMIX/WKUP0
PA4/RX0_2/SOT9_0/TIOA12_0/INT03_0
6
103
P20/AIN1_1/INT05_0/CROUT_0
PA5/TX0_2/SCK9_0/TIOA13_0/INT10_2
7
102
P21/SIN0_0/BIN1_1/INT06_1
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
8
101
P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
9
100
P23/AN22/SCK0_0/RTO00_1/TIOA07_1
P07/TRACED2/ADTG_0/SCK4_2
10
99
P24/AN21/SIN2_1/RTO01_1/INT01_2
P08/TRACED3/CTS4_2/TIOA00_2
11
98
P25/AN20/SOT2_1/RTO02_1
P09/TRACECLK/RTS4_2/TIOB00_2
12
97
P26/AN19/SCK2_1/RTO03_1
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
13
96
P27/AN18/SCK12_0/RTO04_1/INT02_2
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
14
95
P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
15
94
P29/AN16/SIN12_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
16
93
AVRH
P54/SOT6_0/TIOB01_2/MALE_0
17
92
AVRL
P55/ADTG_1/SCK6_0/MRDY_0
18
91
AVSS
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
19
90
AVCC
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
89
P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
88
P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
87
P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
86
P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
85
P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
VSS
25
84
P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
26
83
P19/AN09/SCK2_2/INT22_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
27
82
P18/AN08/SOT2_2/INT21_1
P38/SCK5_2/IC00_0/INT11_1
28
81
P17/AN07/SIN2_2/INT04_1
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
29
80
P16/AN06/SCK0_1/INT20_1
P3A/RTO00_0/TIOA00_1
30
79
P15/AN05/SOT0_1/IC03_2
P3B/RTO01_0/TIOA01_1
31
78
P14/AN04/SIN0_1/IC02_2/INT03_1
P3C/RTO02_0/TIOA02_1
32
77
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3D/RTO03_0/TIOA03_1
33
76
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA04_1
34
75
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P3F/RTO05_0/TIOA05_1
35
74
P10/AN00
VSS
36
73
VCC
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0
P72/SIN2_0/INT14_2/WKUP2/MADATA07_0
P73/SOT2_0/INT15_2/MADATA08_0
P74/SCK2_0/MADATA09_0
P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
50
P48/SIN3_2/INT14_1
P70/TX0_0/TIOA04_2/MADATA05_0
49
INITX
P4E/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0
48
P47/X1A
55
47
P46/X0A
P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0
46
VCC
54
45
P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0
44
C
VSS
53
43
P45/SCK11_0/TIOA05_0
P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0
42
P44/SOT11_0/TIOA04_0
52
41
P43/ADTG_7/SIN11_0/TIOA03_0
51
40
P42/SCK10_0/TIOA02_0/MCLKOUT_0
P49/SOT3_2/AIN0_1/TIOB00_0
39
P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0
38
37
VCC
P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0
P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0
LQFP - 144
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
11
D a t a S h e e t
BGA-192P-M06
(TOP VIEW)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
UDP0
UDM0
USB
VCC
VSS
PCD
PCB
VSS
VCC
PC8
VSS
TCK
VCC
14
B
VSS
PA0
PF5
PF3
P61
PD1
PCA
PC1
P95
P92
TDO
TMS
TRSTX
VSS
C
VCC
PA1
PA2
PF4
P60
PD2
PCC
PC5
PC0
P93
P90
TDI
PF6
VCC
D
PA5
PA4
P05
P06
PA3
PD3
PCE
PC6
PC2
P94
P91
P21
P20
P83
E
VSS
P07
P08
P09
P50
P62
PCF
PC7
PC3
P25
P24
P23
P22
P82
F
P51
P52
P53
P54
P55
P56
PD0
PC9
PC4
P29
P28
P27
P26
AVRH
G
VSS
P57
P58
P59
P5A
P5B
VSS
VSS
PB7
PB6
PB5
PB4
PB3
AVRL
H
P5C
P5D
P30
P31
P32
P33
VSS
VSS
P1F
P1E
PB2
PB1
PB0
AVSS
J
VSS
P37
P36
P35
P34
P70
VSS
P76
P1D
P1C
P1B
P1A
P19
AVCC
K
P38
P39
P3A
P3B
P4A
P4E
VSS
P74
P7B
P7F
P18
P16
P15
P17
L
P3C
P3D
P3E
P43
P49
P4D
VSS
P73
P7A
P7E
P14
P13
P12
VSS
M
VSS
P3F
P42
P44
P48
P4C
VSS
P72
P79
PF0
PF2
P11
P10
VCC
N
VCC
P40
P41
P45
INITX
P4B
VSS
P71
P78
P7D
PF1
MD0
MD1
VSS
C
VSS
VCC
X0A
X1A
VSS
P75
P77
P7C
VSS
X0
X1
P
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
LQFP-176
1
Pin No
LQFP-144
1
BGA-192
C1
2
2
B2
3
3
C2
4
4
C3
5
5
D5
6
6
D2
7
7
D1
8
8
D3
9
9
D4
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin Name
VCC
PA0
SIN8_0
TIOA08_0
MAD21_0
PA1
SOT8_0
TIOA09_0
MAD22_0
PA2
SCK8_0
TIOA10_0
MAD23_0
PA3
SIN9_0
TIOA11_0
MAD24_0
PA4
RX0_2
SOT9_0
TIOA12_0
INT03_0
PA5
TX0_2
SCK9_0
TIOA13_0
INT10_2
P05
TRACED0
SIN4_2
TIOA05_2
INT00_1
P06
TRACED1
SOT4_2
TIOB05_2
INT01_1
I/O circuit
type
Pin state
type
-
I*
J
I*
J
I*
J
I*
J
I*
K
I*
K
E
Q
E
Q
13
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
10
10
E2
11
11
E3
12
12
E4
13
13
E5
14
14
F1
15
15
F2
14
CONFIDENTIAL
Pin Name
P07
TRACED2
ADTG_0
SCK4_2
P08
TRACED3
CTS4_2
TIOA00_2
P09
TRACECLK
RTS4_2
TIOB00_2
P50
SIN3_1
AIN0_2
INT00_0
MOEX_0
P51
SOT3_1
BIN0_2
INT01_0
MWEX_0
P52
SCK3_1
ZIN0_2
INT02_0
MDQM0_0
I/O circuit
type
Pin state
type
E
P
E
P
E
P
E
K
E
K
E
K
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
16
16
F3
17
17
F4
18
18
F5
19
19
F6
20
20
G2
21
21
G3
22
22
G4
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin Name
P53
SIN6_0
TIOA01_2
INT07_2
MDQM1_0
P54
SOT6_0
TIOB01_2
MALE_0
P55
ADTG_1
SCK6_0
MRDY_0
P56
SIN1_0
TIOA09_2
INT08_2
CEC1_1
MNALE_0
P57
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
TIOB11_2
INT09_2
MNREX_0
I/O circuit
type
Pin state
type
E
K
E
J
E
J
I*
S
I*
K
I*
K
E
K
15
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
23
23
G5
24
24
G6
25
-
H1
26
-
H2
27
25
A5
28
-
H3
29
-
H4
30
-
H5
31
-
H6
16
CONFIDENTIAL
Pin name
P5A
SOT7_0
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
TIOA06_2
INT28_0
P5D
TIOB06_2
INT29_0
VSS
P30
AIN0_0
TIOB00_1
INT03_2
WKUP4
P31
SCK6_1
BIN0_0
TIOB01_1
INT04_2
P32
SOT6_1
ZIN0_0
TIOB02_1
INT05_2
P33
ADTG_6
SIN6_1
TIOB03_1
INT04_0
I/O circuit
type
Pin state
type
E
K
E
K
E
K
E
K
-
E
U
E
K
E
K
E
K
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
32
-
J5
33
-
J4
34
26
J3
35
27
J2
36
28
K1
37
29
K2
38
30
K3
39
31
K4
40
32
L1
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
P34
TX0_1
FRCK0_0
TIOB04_1
P35
RX0_1
IC03_0
TIOB05_1
INT08_1
P36
SIN5_2
IC02_0
TIOA12_2
INT09_1
P37
SOT5_2
IC01_0
TIOB12_2
INT10_1
P38
SCK5_2
IC00_0
INT11_1
P39
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
P3A
RTO00_0
TIOA00_1
P3B
RTO01_0
TIOA01_1
P3C
RTO02_0
TIOA02_1
I/O circuit
type
Pin state
type
E
J
E
K
E
K
E
K
E
K
E
J
F
J
F
J
F
J
17
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
41
33
L2
42
34
L3
43
35
M2
44
45
36
37
A8
N1
46
38
N2
47
39
N3
48
40
M3
49
41
L4
50
42
M4
51
43
N4
52
53
54
44
45
46
P2
A11
P4
55
47
P5
56
48
P6
57
49
N5
58
50
M5
18
CONFIDENTIAL
Pin name
P3D
RTO03_0
TIOA03_1
P3E
RTO04_0
TIOA04_1
P3F
RTO05_0
TIOA05_1
VSS
VCC
P40
SIN10_0
TIOA00_0
INT12_1
MCSX2_0
P41
SOT10_0
TIOA01_0
INT13_1
MCSX3_0
P42
SCK10_0
TIOA02_0
MCLKOUT_0
P43
ADTG_7
SIN11_0
TIOA03_0
P44
SOT11_0
TIOA04_0
P45
SCK11_0
TIOA05_0
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
SIN3_2
INT14_1
I/O circuit
type
Pin state
type
F
J
F
J
F
J
-
E
K
E
K
E
J
I*
J
I*
J
I*
J
-
D
F
D
G
B
C
E
K
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
59
51
L5
60
52
K5
61
53
N6
62
54
M6
63
55
L6
64
56
K6
65
57
J6
66
58
N8
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
P49
SOT3_2
AIN0_1
TIOB00_0
P4A
SCK3_2
BIN0_1
TIOB01_0
MADATA00_0
P4B
IGTRG0_0
ZIN0_1
TIOB02_0
MADATA01_0
P4C
SCK7_1
AIN1_2
TIOB03_0
MADATA02_0
P4D
SOT7_1
BIN1_2
TIOB04_0
MADATA03_0
P4E
SIN7_1
ZIN1_2
TIOB05_0
INT06_2
MADATA04_0
P70
TX0_0
TIOA04_2
MADATA05_0
P71
RX0_0
TIOB04_2
INT13_2
MADATA06_0
I/O circuit
type
Pin state
type
E
J
E
J
E
J
E
J
E
J
E
K
E
J
E
K
19
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
67
59
M8
68
60
L8
69
61
K8
70
62
P8
71
63
J8
72
64
P9
73
65
N9
74
66
M9
-
-
M1
P3
20
CONFIDENTIAL
Pin name
P72
SIN2_0
INT14_2
WKUP2
MADATA07_0
P73
SOT2_0
INT15_2
MADATA08_0
P74
SCK2_0
MADATA09_0
P75
ADTG_8
SIN3_0
INT07_1
MADATA10_0
P76
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P78
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
VSS
I/O circuit
type
Pin state
type
E
U
E
K
E
J
E
K
E
K
E
K
E
J
E
K
-
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
75
67
L9
76
-
K9
77
-
P10
78
-
N10
79
-
L10
80
-
K10
81
-
M10
82
-
N11
83
-
M11
84
68
N13
85
69
N12
86
70
P12
87
71
P13
88
89
-
72
73
-
E1
M14
P7
N7
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
P7A
ZIN1_0
INT24_1
MADATA15_0
P7B
TIOB07_0
INT10_0
P7C
TIOA07_0
INT11_0
P7D
TIOA14_1
INT12_0
P7E
TIOB14_1
INT24_0
P7F
TIOA15_1
INT25_0
PF0
SIN1_2
TIOB15_1
INT13_0
CEC0_0
PF1
SOT1_2
TIOA08_1
INT14_0
PF2
SCK1_2
TIOB08_1
INT15_0
PE0
MD1
MD0
PE2
X0
PE3
X1
VSS
VCC
VSS
VSS
I/O circuit
type
Pin state
type
E
K
E
K
E
K
E
K
E
K
E
K
I*
S
I*
K
I*
K
C
E
J
D
A
A
A
B
-
21
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
90
74
M13
91
75
M12
92
76
L13
93
77
L12
94
78
L11
95
79
K13
96
80
K12
97
81
K14
-
-
M7
L7
K7
22
CONFIDENTIAL
Pin name
P10
AN00
P11
AN01
SIN1_1
FRCK0_2
INT02_1
WKUP1
P12
AN02
SOT1_1
IC00_2
P13
AN03
SCK1_1
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
SIN0_1
IC02_2
INT03_1
P15
AN05
SOT0_1
IC03_2
P16
AN06
SCK0_1
INT20_1
P17
AN07
SIN2_2
INT04_1
VSS
VSS
VSS
I/O circuit
type
Pin state
type
G
L
G
N
G
L
G
L
G
M
G
L
G
M
G
M
-
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
98
82
K11
99
83
J13
100
84
J12
101
85
J11
102
86
J10
103
87
J9
104
88
H10
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
P18
AN08
SOT2_2
INT21_1
P19
AN09
SCK2_2
INT22_1
P1A
AN10
SIN4_1
IC00_1
TIOA13_2
INT05_1
P1B
AN11
SOT4_1
IC01_1
TIOB13_2
INT25_1
P1C
AN12
SCK4_1
IC02_1
TIOA14_2
INT26_1
P1D
AN13
CTS4_1
IC03_1
TIOB14_2
INT27_1
P1E
AN14
RTS4_1
DTTI0X_1
TIOA15_2
INT28_1
I/O circuit
type
Pin state
type
G
M
G
M
G
M
G
M
G
M
G
M
G
M
23
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
105
89
H9
106
-
H13
107
-
H12
108
-
H11
109
-
G13
110
-
G12
111
-
G11
112
-
G10
113
-
G9
114
115
-
90
91
-
J14
H14
J7
P11
24
CONFIDENTIAL
Pin name
P1F
AN15
ADTG_5
FRCK0_1
TIOB15_2
INT29_1
PB0
SIN7_2
TIOA09_1
INT16_0
PB1
SOT7_2
TIOB09_1
INT17_0
PB2
SCK7_2
TIOA10_1
INT18_0
PB3
TIOB10_1
INT19_0
PB4
SIN0_2
TIOA11_1
INT20_0
PB5
SOT0_2
TIOB11_1
INT21_0
PB6
SCK0_2
TIOA12_1
INT22_0
PB7
TIOB12_1
INT23_0
AVCC
AVSS
VSS
VSS
I/O circuit
type
Pin state
type
G
M
E
K
E
K
E
K
E
K
E
K
E
K
E
K
E
K
-
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
116
117
Pin No
LQFP-144
92
93
BGA-192
G14
F14
118
94
F10
119
95
F11
120
96
F12
121
97
F13
122
98
E10
123
99
E11
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
AVRL
AVRH
P29
AN16
SIN12_0
P28
AN17
ADTG_4
SOT12_0
RTO05_1
INT09_0
P27
AN18
SCK12_0
RTO04_1
INT02_2
P26
AN19
SCK2_1
RTO03_1
P25
AN20
SOT2_1
RTO02_1
P24
AN21
SIN2_1
RTO01_1
INT01_2
I/O circuit
type
Pin state
type
-
G
L
G
M
G
M
G
L
G
L
G
M
25
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
124
100
E12
125
101
E13
126
102
D12
127
103
D13
128
104
C13
129
105
E14
130
106
D14
131
132
133
107
108
109
C14
G7
A13
134
110
B13
135
111
A12
136
112
C12
137
113
B12
138
114
B11
139
-
C11
-
-
N14
26
CONFIDENTIAL
Pin name
P23
AN22
SCK0_0
RTO00_1
TIOA07_1
P22
AN23
SOT0_0
ZIN1_1
TIOB07_1
P21
SIN0_0
BIN1_1
INT06_1
P20
AIN1_1
INT05_0
CROUT_0
PF6
NMIX
WKUP0
P82
MCSX7_0
P83
MCSX6_0
VCC
VSS
VCC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P90
TIOB08_0
INT30_0
VSS
I/O circuit
type
Pin state
type
G
L
G
L
E
K
E
K
I*
H
E
J
E
J
-
E
I
E
I
E
I
E
I
E
I
E
K
-
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
140
-
D11
141
-
B10
142
-
C10
143
-
D10
144
-
B9
145
115
C9
146
116
B8
147
117
D9
148
118
E9
149
119
F9
150
120
C8
-
-
L14
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
P91
TIOB09_0
INT31_0
P92
SIN5_1
TIOB10_0
P93
SOT5_1
TIOB11_0
P94
SCK5_1
TIOB12_0
INT26_0
P95
TIOB13_0
INT27_0
PC0
DA0_0
SIN13_0
MCSX5_0
PC1
DA1_0
SOT13_0
MCSX4_0
PC2
SCK13_0
MAD00_0
PC3
TIOA06_1
MAD01_0
PC4
SIN14_0
TIOA08_2
CEC0_1
MAD02_0
PC5
SOT14_0
TIOA10_2
MAD03_0
VSS
I/O circuit
type
Pin state
type
E
K
E
J
E
J
E
K
E
K
H
O
H
O
E
J
E
J
I*
R
I*
J
-
27
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
151
121
D8
152
122
E8
153
123
A10
154
124
F8
155
125
B7
156
157
126
127
A9
G8
158
128
A7
159
129
C7
160
130
A6
161
131
D7
162
132
E7
163
133
F7
164
134
B6
-
-
B14
H7
B1
G1
28
CONFIDENTIAL
Pin name
PC6
SCK14_0
TIOA14_0
MAD04_0
PC7
CROUT_1
RTCCO_0
SUBOUT_0
MAD05_0
PC8
SIN15_0
MAD06_0
PC9
SOT15_0
MAD07_0
PCA
SCK15_0
MAD08_0
VCC
VSS
PCB
MAD09_0
PCC
MAD10_0
PCD
MAD11_0
PCE
RTS4_0
TIOB06_1
MAD12_0
PCF
CTS4_0
TIOB08_2
MAD13_0
PD0
SCK4_0
TIOB10_2
INT30_1
MAD14_0
PD1
SOT4_0
TIOB14_0
INT31_1
MAD15_0
VSS
VSS
VSS
VSS
I/O circuit
type
Pin state
type
I*
J
E
J
E
J
E
J
E
J
-
E
J
E
J
E
J
E
J
E
J
E
K
E
K
-
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
165
135
C6
166
136
D6
167
137
E6
168
138
B5
169
139
C5
170
-
B4
171
-
C4
172
140
B3
173
141
A4
174
142
A3
175
143
A2
144
-
H8
J1
176
*
: 5V tolerant I/O
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin name
PD2
SIN4_0
TIOA03_2
INT00_2
MAD16_0
PD3
TIOB03_2
MAD17_0
P62
ADTG_3
SCK5_0
MAD18_0
P61
UHCONX
SOT5_0
TIOB02_2
MAD19_0
P60
SIN5_0
TIOA02_2
INT15_1
WKUP5
MAD20_0
PF3
SIN6_2
TIOA06_0
INT06_0
PF4
SOT6_2
TIOB06_0
INT07_0
PF5
IGTRG0_1
INT08_0
WKUP3
CEC1_0
SCK6_2
USBVCC
P80
UDM0
P81
UDP0
VSS
VSS
I/O circuit
type
Pin state
type
E
K
E
J
E
J
E
J
E
U
I*
K
I*
K
I*
T
K
V
K
V
-
29
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Pin
function
ADC
30
CONFIDENTIAL
Pin name
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
Pin No
Function description
LQFP-176 LQFP-144 BGA-192
A/D converter external trigger input
pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
10
18
37
167
119
105
31
49
70
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
118
119
120
121
122
123
124
125
10
18
29
137
95
89
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
100
101
E2
F5
K2
E6
F11
H9
H6
L4
P8
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
F10
F11
F12
F13
E10
E11
E12
E13
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
6
Pin name
TIOA00_0
TIOA00_1
TIOA00_2
TIOB00_0
TIOB00_1
TIOB00_2
TIOA01_0
TIOA01_1
TIOA01_2
TIOB01_0
TIOB01_1
TIOB01_2
TIOA02_0
TIOA02_1
TIOA02_2
TIOB02_0
TIOB02_1
TIOB02_2
TIOA03_0
TIOA03_1
TIOA03_2
TIOB03_0
TIOB03_1
TIOB03_2
TIOA04_0
TIOA04_1
TIOA04_2
TIOB04_0
TIOB04_1
TIOB04_2
TIOA05_0
TIOA05_1
TIOA05_2
TIOB05_0
TIOB05_1
TIOB05_2
TIOA06_0
TIOA06_1
TIOA06_2
TIOB06_0
TIOB06_1
TIOB06_2
Function description
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
46
38
11
59
28
12
47
39
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
64
33
9
170
148
25
171
161
26
38
30
11
51
12
39
31
16
52
17
40
32
139
53
138
41
33
135
54
136
42
34
57
55
58
43
35
8
56
9
118
131
-
N2
K3
E3
L5
H3
E4
N3
K4
F3
K5
H4
F4
M3
L1
C5
N6
H5
B5
L4
L2
C6
M6
H6
D6
M4
L3
J6
L6
J5
N8
N4
M2
D3
K6
J4
D4
B4
E9
H1
C4
D7
H2
31
D a t a S h e e t
Pin
function
Base Timer
7
Base Timer
8
Base Timer
9
Base Timer
10
Base Timer
11
Base Timer
12
Base Timer
13
32
CONFIDENTIAL
Pin name
TIOA07_0
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
TIOA08_1
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
Function description
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
Pin No
LQFP-176 LQFP-144 BGA-192
77
124
71
76
125
72
2
82
149
139
83
162
3
106
19
140
107
20
4
108
150
141
109
163
5
110
21
142
111
22
6
112
34
143
113
35
7
23
100
144
24
101
100
63
101
64
2
119
132
3
19
20
4
120
133
5
21
22
6
26
27
7
23
84
24
85
P10
E12
J8
K9
E13
P9
B2
N11
F9
C11
M11
E7
C2
H13
F6
D11
H12
G2
C3
H11
C8
B10
G13
F7
D5
G12
G3
C10
G11
G4
D2
G10
J3
D10
G9
J2
D1
G5
J12
B9
G6
J11
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Base Timer
14
Base Timer
15
Debugger
Pin name
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
Function description
Base timer ch.14 TIOA pin
Base timer ch.14 TIOB pin
Base timer ch.15 TIOA pin
Base timer ch.15 TIOB pin
Serial wire debug interface clock input
Serial wire debug interface data input /
output
Serial wire viewer output
J-TAG test clock input
J-TAG test data input
J-TAG debug data output
J-TAG test mode state input/output
Trace CLK output of ETM
Trace data output of ETM
J-TAG test reset Input
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
151
78
102
164
79
103
73
80
104
74
81
105
135
121
86
134
87
65
88
66
89
111
D8
N10
J10
B6
L10
J9
N9
K10
H10
M9
M10
H9
A12
137
113
B12
138
135
136
138
137
12
8
9
10
11
134
114
111
112
114
113
12
8
9
10
11
110
B11
A12
C12
B11
B12
E4
D3
D4
E2
E3
B13
33
D a t a S h e e t
Pin
function
External
Bus
Pin name
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
MOEX_0
MWEX_0
34
CONFIDENTIAL
Pin No
Function description
LQFP-176 LQFP-144 BGA-192
External bus interface address bus
External bus interface chip select
output pin
External bus interface byte mask
signal output
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
167
168
169
2
3
4
5
23
24
46
47
146
145
130
129
15
16
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
137
138
139
2
3
4
5
23
24
38
39
116
115
106
105
15
16
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
D6
E6
B5
C5
B2
C2
C3
D5
G5
G6
N2
N3
B8
C9
D14
E14
F2
F3
13
13
E5
14
14
F1
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Pin name
External
Bus
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MALE_0
MRDY_0
MCLKOUT_0
Function description
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable
signal to control NAND Flash
External bus interface write enable
signal to control NAND Flash
External bus interface data bus
(Address / data multiplex bus)
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY
input signal
External bus interface external clock
output
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
19
19
F6
20
20
G2
22
22
G4
21
21
G3
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
K5
N6
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
17
17
F4
18
18
F5
48
40
M3
35
D a t a S h e e t
Pin
function
External
Interrupt
36
CONFIDENTIAL
Pin name
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
Pin No
Function description
LQFP-176 LQFP-144 BGA-192
External interrupt request 00 input
pin
External interrupt request 01 input
pin
External interrupt request 02 input
pin
External interrupt request 03 input
pin
External interrupt request 04 input
pin
External interrupt request 05 input
pin
External interrupt request 06 input
pin
External interrupt request 07 input
pin
External interrupt request 08 input
pin
External interrupt request 09 input
pin
External interrupt request 10 input
pin
External interrupt request 11 input
pin
External interrupt request 12 input
pin
External interrupt request 13 input
pin
External interrupt request 14 input
pin
13
8
165
14
9
123
15
91
120
6
94
28
31
97
29
127
100
30
170
126
64
171
70
16
172
33
19
119
34
22
76
35
7
77
36
71
78
46
72
81
47
66
82
58
67
13
8
135
14
9
99
15
75
96
6
78
81
103
84
102
56
62
16
140
19
95
26
22
27
7
28
63
38
64
39
58
50
59
E5
D3
C6
F1
D4
E11
F2
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
D12
K6
C4
P8
F3
B3
J4
F6
F11
J3
G4
K9
J2
D1
P10
K1
J8
N10
N2
P9
M10
N3
N8
N11
M5
M8
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
External
Interrupt
Pin name
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
Function description
External interrupt request 15 input
pin
External interrupt request 16 input
pin
External interrupt request 17 input
pin
External interrupt request 18 input
pin
External interrupt request 19 input
pin
External interrupt request 20 input
pin
External interrupt request 21 input
pin
External interrupt request 22 input
pin
External interrupt request 23 input
pin
External interrupt request 24 input
pin
External interrupt request 25 input
pin
External interrupt request 26 input
pin
External interrupt request 27 input
pin
External interrupt request 28 input
pin
External interrupt request 29 input
pin
External interrupt request 30 input
pin
External interrupt request 31 input
pin
Non-Maskable Interrupt input
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
83
169
68
106
20
107
21
108
23
109
24
110
96
111
98
112
99
113
74
79
75
80
101
143
102
144
103
25
104
26
105
139
163
140
164
128
139
60
20
21
23
24
80
82
83
66
67
85
86
87
88
89
133
134
104
M11
C5
L8
H13
G2
H12
G3
H11
G5
G13
G6
G12
K12
G11
K11
G10
J13
G9
M9
L10
L9
K10
J11
D10
J10
B9
J9
H1
H10
H2
H9
C11
F7
D11
B6
C13
37
D a t a S h e e t
Pin
function
GPIO
38
CONFIDENTIAL
Pin name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
Function description
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Pin No
LQFP-176 LQFP-144 BGA-192
134
135
136
137
138
8
9
10
11
12
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
110
111
112
113
114
8
9
10
11
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
B13
A12
C12
B12
B11
D3
D4
E2
E3
E4
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
GPIO
Pin name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
Function description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
H3
H4
H5
H6
J5
J4
J3
J2
K1
K2
K3
K4
L1
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
K5
N6
M6
L6
K6
E5
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
G6
H1
H2
39
D a t a S h e e t
Pin
function
GPIO
40
CONFIDENTIAL
Pin name
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Function description
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port 9
General-purpose I/O port A
General-purpose I/O port B
Pin No
LQFP-176 LQFP-144 BGA-192
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
174
175
129
130
139
140
141
142
143
144
2
3
4
5
6
7
106
107
108
109
110
111
112
113
139
138
137
57
58
59
60
61
62
63
64
65
66
67
142
143
105
106
2
3
4
5
6
7
-
C5
B5
E6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
K9
P10
N10
L10
K10
A3
A2
E14
D14
C11
D11
B10
C10
D10
B9
B2
C2
C3
D5
D2
D1
H13
H12
H11
G13
G12
G11
G10
G9
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
GPIO
Pin name
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
Function description
General-purpose I/O port C
General-purpose I/O port D
General-purpose I/O port E
General-purpose I/O port F*
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No
LQFP-176 LQFP-144 BGA-192
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
86
87
81
82
83
170
171
172
128
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
70
71
140
104
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
D6
N13
P12
P13
M10
N11
M11
B4
C4
B3
C13
41
D a t a S h e e t
Pin
function
Multi
Function
Serial
0
Pin name
SIN0_0
SIN0_1
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SOT0_2
(SDA0_2)
Multi
Function
Serial
1
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SCK0_2
(SCL0_2)
SIN1_0
SIN1_1
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
42
CONFIDENTIAL
Pin No.
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.0
input pin
Multifunction serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA0 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL0 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.1
input pin
Multifunction serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA1 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL1 when it is
used in an I2C (operation mode 4).
126
94
110
102
78
-
D12
L11
G12
125
101
E13
95
79
K13
111
-
G11
124
100
E12
96
80
K12
112
-
G10
19
91
81
19
75
-
F6
M12
M10
20
20
G2
92
76
L13
82
-
N11
21
21
G3
93
77
L12
83
-
M11
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Multi
Function
Serial
2
Pin name
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
Multi
Function
Serial
3
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function description
Multifunction serial interface ch.2
input pin
Multifunction serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA2 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL2 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.3
input pin
Multifunction serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA3 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL3 when it is
used in an I2C (operation mode 4).
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No.
LQFP-176 LQFP-144 BGA-192
67
123
97
59
99
81
M8
E11
K14
68
60
L8
122
98
E10
98
82
K11
69
61
K8
121
97
F13
99
83
J13
70
13
58
62
13
50
P8
E5
M5
71
63
J8
14
14
F1
59
51
L5
72
64
P9
15
15
F2
60
52
K5
43
D a t a S h e e t
Pin
function
Multi
Function
Serial
4
Pin name
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
Multi
Function
Serial
5
44
CONFIDENTIAL
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
Pin No.
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.4
input pin
Multifunction serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA4 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL4 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.4
RTS output pin
Multifunction serial interface ch.4
CTS input pin
Multifunction serial interface ch.5
input pin
SOT5_2
(SDA5_2)
Multifunction serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA5 when it is used in an I2C
(operation mode 4).
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL5 when it is
used in an I2C (operation mode 4).
165
100
8
135
84
8
C6
J12
D3
164
134
B6
101
85
J11
9
9
D4
163
133
F7
102
86
J10
10
10
E2
161
104
12
162
103
11
169
141
34
131
88
12
132
87
11
139
26
D7
H10
E4
E7
J9
E3
C5
B10
J3
168
138
B5
142
-
C10
35
27
J2
167
137
E6
143
-
D10
36
28
K1
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Multi
Function
Serial
6
Pin name
SIN6_0
SIN6_1
SIN6_2
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SOT6_2
(SDA6_2)
Multi
Function
Serial
7
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
SIN7_0
SIN7_1
SIN7_2
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SOT7_2
(SDA7_2)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Function description
Multifunction serial interface ch.6
input pin
Multifunction serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA6 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL6 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.7
input pin
Multifunction serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA7 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL7 when it is
used in an I2C (operation mode 4).
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No.
LQFP-176 LQFP-144 BGA-192
16
31
170
16
-
F3
H6
B4
17
17
F4
30
-
H5
171
-
C4
18
18
F5
29
-
H4
172
-
B3
22
64
106
22
56
-
G4
K6
H13
23
23
G5
63
55
L6
107
-
H12
24
24
G6
62
54
M6
108
-
H11
45
D a t a S h e e t
Pin
function
Multi
Function
Serial
8
Pin name
SIN8_0
SOT8_0
(SDA8_0)
SCK8_0
(SCL8_0)
Multi
Function
Serial
9
SIN9_0
SOT9_0
(SDA9_0)
SCK9_0
(SCL9_0)
46
CONFIDENTIAL
Pin No.
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.8
input pin
Multifunction serial interface ch.6
output pin.
This pin operates as SOT8 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA8 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK8 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL8 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.9
input pin
Multifunction serial interface ch.9
output pin.
This pin operates as SOT9 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA9 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.9
clock I/O pin.
This pin operates as SCK9 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL9 when it is
used in an I2C (operation mode 4).
2
2
B2
3
3
C2
4
4
C3
5
5
D5
6
6
D2
7
7
D1
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Multi
Function
Serial
10
Pin name
SIN10_0
SOT10_0
(SDA10_0)
SCK10_0
(SCL10_0)
Multi
Function
Serial
11
SIN11_0
SOT11_0
(SDA11_0)
SCK11_0
(SCL11_0)
Function description
Multifunction serial interface ch.10
input pin
Multifunction serial interface ch.10
output pin.
This pin operates as SOT10 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA10 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.10
clock I/O pin.
This pin operates as SCK10 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL10 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.11
input pin
Multifunction serial interface ch.11
output pin.
This pin operates as SOT11 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA11 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.11
clock I/O pin.
This pin operates as SCK11 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL11 when it
is used in an I2C (operation mode 4).
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No.
LQFP-176 LQFP-144 BGA-192
46
38
N2
47
39
N3
48
40
M3
49
41
L4
50
42
M4
51
43
N4
47
D a t a S h e e t
Pin
function
Multi
Function
Serial
12
Pin name
SIN12_0
SOT12_0
(SDA12_0)
SCK12_0
(SCL12_0)
Multi
Function
Serial
13
SIN13_0
SOT13_0
(SDA13_0)
SCK13_0
(SCL13_0)
48
CONFIDENTIAL
Pin No.
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.12
input pin
Multifunction serial interface ch.12
output pin.
This pin operates as SOT12 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA12 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.12
clock I/O pin.
This pin operates as SCK12 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL12 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.13
input pin
Multifunction serial interface ch.13
output pin.
This pin operates as SOT13 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA13 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.13
clock I/O pin.
This pin operates as SCK13 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL13 when it
is used in an I2C (operation mode 4).
118
94
F10
119
95
F11
120
96
F12
145
115
C9
146
116
B8
147
117
D9
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Multi
Function
Serial
14
Pin name
SIN14_0
SOT14_0
(SDA14_0)
SCK14_0
(SCL14_0)
Multi
Function
Serial
15
SIN15_0
SOT15_0
(SDA15_0)
SCK15_0
(SCL15_0)
Function description
Multifunction serial interface ch.14
input pin
Multifunction serial interface ch.14
output pin.
This pin operates as SOT14 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA14 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.14
clock I/O pin.
This pin operates as SCK14 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL14 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.15
input pin
Multifunction serial interface ch.15
output pin.
This pin operates as SOT15 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA15 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.15
clock I/O pin.
This pin operates as SCK15 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL15 when it
is used in an I2C (operation mode 4).
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Pin No.
LQFP-176 LQFP-144 BGA-192
149
119
F9
150
120
C8
151
121
D8
153
123
A10
154
124
F8
155
125
B7
49
D a t a S h e e t
Pin
function
Multi
Function
Timer
0
50
CONFIDENTIAL
Pin name
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
IGTRG0_0
IGTRG0_1
Pin No
Function description
LQFP-176 LQFP-144 BGA-192
Input signal controlling wave form
generator outputs RTO00 to RTO05
of multi-function timer 0.
16-bit free-run timer ch.0 external
clock input pin
16-bit input capture ch.0 input pin of
multi-function timer 0.
ICxx describes channel number.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
PPG IGBT mode external trigger
input pin
37
29
K2
104
88
H10
32
105
91
36
100
92
35
101
93
34
102
94
33
103
95
89
75
28
84
76
27
85
77
26
86
78
87
79
J5
H9
M12
K1
J12
L13
J2
J11
L12
J3
J10
L11
J4
J9
K13
38
30
K3
124
100
E12
39
31
K4
123
99
E11
40
32
L1
122
98
E10
41
33
L2
121
97
F13
42
34
L3
120
96
F12
43
35
M2
119
95
F11
61
172
53
140
N6
B3
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Quadrature
Position/
Revolution
Counter
0
Pin name
AIN0_0
AIN0_1
L5
13
E5
BIN0_0
29
-
H4
60
52
K5
BIN0_2
14
14
F1
ZIN0_0
30
-
H5
61
53
N6
ZIN0_2
15
15
F2
AIN1_0
73
65
N9
AIN1_1
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
127
103
D13
AIN1_2
QPRC ch.1 AIN input pin
62
54
M6
BIN1_0
74
66
M9
126
102
D12
BIN1_2
63
55
L6
ZIN1_0
75
67
L9
125
101
E13
64
56
K6
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
ZIN1_2
UDM0
USB ch.0 function/host D – pin
174
142
A3
UDP0
USB ch.0 function/host D + pin
175
143
A2
UHCONX
USB ch.0
USB external pull-up control pin
168
138
B5
65
57
J6
TX0_0
TX0_1
32
-
J5
TX0_2
7
7
D1
RX0_0
66
58
N8
33
-
J4
RX0_1
Real-time
clock
CAN interface ch.0 TX output
CAN interface ch.0 RX output
RX0_2
6
6
D2
RTCCO_0
152
122
E8
93
77
L12
RTCCO_2
37
29
K2
SUBOUT_0
152
122
E8
93
77
L12
37
29
K2
RTCCO_1
SUBOUT_1
0.5 seconds pulse output pin of Realtime clock
Sub clock output pin
SUBOUT_2
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
H3
51
ZIN1_1
CAN
-
13
BIN1_1
USB
28
59
ZIN0_1
QPRC ch.0 AIN input pin
Pin No
LQFP-176 LQFP-144 BGA-192
AIN0_2
BIN0_1
Quadrature
Position/
Revolution
Counter
1
Function description
51
D a t a S h e e t
Pin
function
RESET
Pin name
INITX
Mode
MD0
MD1
Pin No
Function description
LQFP-176 LQFP-144 BGA-192
External Reset Input. A reset is valid
when INITX="L".
Mode 0 Pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
Mode 1 Pin.
During serial programming to Flash
memory, MD1="L" must be input.
POWER
VCC
USBVCC
Low-Power
Consumption
Mode
WKUP0
WKUP1
WKUP2
WKUP3
WKUP4
WKUP5
HDMICEC/
Remote
Control
Reception
DAC
52
CONFIDENTIAL
Power supply Pin
3.3V Power supply port for USB I/O
Deep standby mode return signal
input pin 0
Deep standby mode return signal
input pin 1
Deep standby mode return signal
input pin 2
Deep standby mode return signal
input pin 3
Deep standby mode return signal
input pin 4
Deep standby mode return signal
input pin 5
57
49
N5
85
69
N12
84
68
N13
1
45
54
89
131
1
37
46
73
107
C1
N1
P4
M14
C14
133
109
A13
156
173
126
A9
141
A4
128
104
C13
91
75
M12
67
59
M8
172
140
B3
28
-
H3
169
139
C5
CEC0_0
CEC0_1
HDMI-CEC/Remote Control
Reception ch.0 input/output pin
81
149
119
M10
F9
CEC1_0
HDMI-CEC/Remote Control
Reception ch.1 input/output pin
172
140
B3
19
145
146
19
115
116
F6
C9
B8
CEC1_1
DA0_0
DA1_0
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin
function
Pin name
Function description
GND
VSS
CLOCK
Analog
POWER
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Analog
GND
AVSS
AVRL
C pin
C
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
A/D converter, D/A converter analog
power pin
A/D converter analog reference
voltage input pin
A/D converter, D/A converter GND
pin
A/D converter analog reference
voltage input pin
Power supply stabilization capacity
pin
Pin No
LQFP-176 LQFP-144 BGA-192
27
44
53
88
132
157
176
86
55
87
56
127
152
25
36
45
72
108
127
144
70
47
71
48
103
122
A5
A8
A11
E1
G7
G8
H8
M1
P3
P7
N7
M7
L7
K7
J7
P11
N14
L14
B14
H7
B1
G1
J1
P12
P5
P13
P6
D13
E8
114
90
J14
117
93
F14
115
91
H14
116
92
G14
52
44
P2
* : 5V tolerant I/O
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
53
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1 MΩ
With Standby mode control
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
CMOS level hysteresis input
Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
54
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Digital input
Open drain output
CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5 MΩ
With Standby mode control
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
55
D a t a S h e e t
Type
Circuit
Remarks
E
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -12 mA, IOL= 12 mA
+B input available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
56
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Type
Circuit
Remarks
G
P-ch
Digital output
P-ch
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input available
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
H
P-ch
P-ch
Digital output
N-ch
Digital output
R
CMOS level output
CMOS level hysteresis input
With input control
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode Control
Analog output
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
57
D a t a S h e e t
Type
Circuit
Remarks
I
P-ch
P-ch
CMOS level output
CMOS level hysteresis input
5V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Available to control PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
K
It is possible to select the USB
I/O / GPIO function.
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
Differential
UDM0/P80
When the USB I/O is selected.
Full-speed, Low-speed control
When the GPIO is selected.
CMOS level output
CMOS level hysteresis input
With standby mode control
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
58
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
59
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
60
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
61
D a t a S h e e t
3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
62
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
・ Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
・ Lead type
Load capacitance : Approximately 6 pF to 7 pF
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
63
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
•
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Set as
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
64
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : USBVCC → VCC
AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the
wiring of GPIO, there is a possibility that the oscillation erroneously counts because oscillation wave has
noise with the change of GPIO. Keep as much distance as possible between both wirings and insert the
ground pattern between them in order to avoid this possibility.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
65
D a t a S h e e t
Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
ETM
TRACEDx,
TRACECLK
TPIU
ROM
Table
SRAM0
80/96 Kbytes
Multi-layer AHB (Max 60 MHz)
Cortex-M3 Core I
@60 MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 32 MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
SRAM1
80/96 Kbytes
Flash I/F
On-Chip Flash
1 Mbytes+64 Kbytes/
1.5 Mbytes+64 Kbytes
Security
USB2.0
PHY
(Host/
Func)
UDP0/UDM0
UHCONX
DMAC
8ch.
CSV
X0
X1
X0A
X1A
CROUT
AVCC,
AVSS,
AVRH
ANxx
Main
Osc
Sub
Osc
Source Clock
PLL
CR
4 MHz
AHB-AHB
Bridge
CLK
CR
100 kHz
Unit 1
AINx
BINx
ZINx
USB Clock Ctrl
Base Timer
16-bit 16ch./
32-bit 8ch.
LVD Ctrl
LVD
IRQ-Monitor
Regulator
QPRC
2ch.
A/D Activation Compare
2ch.
IC0x
FRCK0
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
PLL
Power-On
Reset
C
CRC Accelerator
Watch Counter
Deep Standby Ctrl
WKUPx
HDMI-CEC/
Remote Reciver Control
CEC0_x,
CEC1_x
Real-Time Clock
RTCCO,
SUBOUT
External Interrupt
Controller
32pin + NMI
INTx
NMIX
MD0,
MD1
P0x,
P1x,
MODE-Ctrl
DTTI0X
RTO0x
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT
10-bit D/Aconverter
2 Units
AHB-APB Bridge : APB2 (Max 32 MHz)
TIOBx
MADATAx
CAN Prescaler
AHB-APB Bridge : APB1 (Max 32 MHz)
TIOAx
TX0_x,
RX0_x
MADx
External Bus I/F
12-bit A/D Converter
Unit 0
ADTGx
DAx
CAN
1ch.
Waveform Generator
3ch.
GPIO
PIN-Function-Ctrl
.
.
.
PFx
IGTRGx
16-bit PPG
3ch.
Multi-function Timer × 1
Multi-function Serial I/F
16ch.
HW flow control(ch.4)
SCKx
SINx
SOTx
CTS4
RTS4
Memory Size
See " Memory size" in "Product Lineup" to confirm the memory size.
66
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
0x4005_0000
Reserved
0x4004_0000
0x4003_F000
0x4003_C000
0x7000_0000
0x6000_0000
0x4003_B000
External Device
Area
0x4003_A000
0x4003_9000
Reserved
0x4003_8000
0x4003_7000
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
0x2001_8000
0x2000_0000
0x1FFE_8000
0x0051_8000
See "Memory map(2)" for
the memory size details.
0x0050_8000
0x0040_4000
0x0040_0000
0x4003_6000
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Security/CR Trim
Flash(Main area)
0x0000_0000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Reserved
0x4002_1000
0x4002_0000
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
CAN ch.0
Reserved
DMAC
Reserved
USB ch.0
EXT-bus I/F
Reserved
RTC
Watch Counter
CRC
MFS
CAN Prescaler
USB Clock Ctrl
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
A/DC
QPRC
Base Timer
PPG
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
67
D a t a S h e e t
Memory Map (2)
MB9BF529SA/TA
MB9BF528SA/TA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2001_8000
0x2001_4000
SRAM1
80Kbytes
SRAM1
64Kbytes
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
SRAM1 16Kbytes*
SRAM0 16Kbytes*
0x2000_0000
0x1FFF_C000
SRAM1 16Kbytes*
SRAM0 16Kbytes*
SRAM0
64Kbytes
SRAM0
80Kbytes
0x1FFE_C000
0x1FFE_8000
Reserved
ROM1_SA0-7(8KBx8)
0x0050_8000
0x0051_8000
ROM1_SA0-7(8KBx8)
0x0050_8000
Reserved
Reserved
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_4000
CR trimming
Security
0x0018_0000
ROM1_SA8-15(8KBx8)
0x0040_2000
0x0040_0000
Flash
(Main area, ROM1)
512Kbytes
Reserved
0x0010_0000
CR trimming
Security
Reserved
0x0010_0000
ROM0_SA9-23(64KBx15)
0x0000_0000
ROM0_SA8(48KB)
ROM0_SA2-3(8KBx2)
Flash
(Main area, ROM0)
1Mbytes
ROM0_SA8(48KB)
ROM0_SA2-3(8KBx2)
Flash
(Main area, ROM0)
1Mbytes
ROM0_SA9-23(64KBx15)
0x0000_0000
Flash
(Work area, ROM1)
64Kbytes
0x0051_8000
Flash
(Work area, ROM1)
64Kbytes
Reserved
* : The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM
Retention Register (DSRAMR).
See "MB9B520T/420T/320T/120T Series Flash programming Manual" for sector structure of Flash.
68
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
AHB
APB0
Peripherals
Flash Memory I/F register
Reserved
Software Watchdog timer
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
0x4002_8000
0x4002_8FFF
D/A Converter
0x4002_9000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Resister
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
HDMI-CEC/Remote control Reception
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
CAN prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External bus interface
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x4006_1FFF
0x4006_2000
0x4006_2FFF
CAN ch.0
0x4006_3000
0x41FF_FFFF
Reserved
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
APB1
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
Deep standby mode Controller
APB2
AHB
USB clock generator
DMAC register
Reserved
69
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
70
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Pin status type
List of Pin Status
A
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Power
supply
stable
INITX = 1
-
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator input
pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
B
Hi-Z /
Internal
input fixed
at "0"
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When state/When
Hi-Z /
Hi-Z /
oscillation oscillation oscillation oscillation oscillation oscillation
Internal
Internal
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
at "0"
E
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Maintain
previous
state
71
Pin status type
D a t a S h e e t
F
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Power
supply
stable
INITX = 1
-
Input
enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/
Internal
input fixed
at "0"
GPIO
selected
Input
enabled
G
H
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at "0"
at "0"
I
GPIO
selected
72
CONFIDENTIAL
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
Hi-Z /
Hi-Z /
Hi-Z/
Hi-Z/
Hi-Z/
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Resource selected
J
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
External interrupt
enabled selected
K
Resource other
than above
selected
Hi-Z
GPIO
selected
Analog input
selected
Hi-Z
L
Resource other
than above
selected
GPIO
selected
Analog input
selected
M
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Timer mode,
RTC mode, or
STOP mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Internal
Hi-Z /
input fixed
Internal input fixed
at "0"
at "0"
input fixed
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
GPIO
selected
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Setting
disabled
Power
supply
stable
INITX = 1
-
GPIO
selected
Maintain
previous
state
External interrupt
enabled selected
Resource other
than above
selected
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
selected
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
73
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Analog input
selected
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
WKUP
enabled
Maintain
previous
state
N
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Analog output
selected
O
Resource other
than above
selected
Setting
disabled
Trace selected
P
Resource other
than above
selected
GPIO
selected
74
CONFIDENTIAL
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
*3
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Power
supply
stable
INITX = 1
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
selected
*4
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at "0"
input fixed
at "0"
at "0"
GPIO
selected
Trace
output
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at "0"
input fixed
at "0"
at "0"
GPIO
selected
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
STOP mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Maintain
previous
state
Q
Resource other
than above
selected
CEC
enabled
R
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
GPIO
selected
CEC
enabled
S
External interrupt
enabled selected
Resource other
than above
selected
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Hi-Z /
Input
enabled
Setting
disabled
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z
GPIO
selected
Maintain
previous
state
Setting
disabled
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Input
enabled
T
Setting
disabled
Setting
disabled
Maintain
previous
state
External interrupt
enabled selected
Resource other
than above
selected
GPIO
selected
Hi-Z
Hi-Z /
Input
enabled
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at "0"
input fixed
at "0"
at "0"
Maintain
previous
state
Setting
disabled
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
CEC
enabled
WKUP
enabled
Power
supply
stable
INITX = 1
-
Trace
output
Trace selected
Setting
disabled
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at "0"
input fixed
at "0"
at "0"
GPIO
selected
Maintain
previous
state
GPIO
selected
75
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
WKUP
enabled
U
Power-on
reset or
Device Run mode
INITX
low-voltage
internal or SLEEP
input state
detection
reset state mode state
state
Setting
disabled
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
GPIO
selected
V
Setting
disabled
Setting
disabled
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
USB I/O pin
Power supply stable
Maintain
previous
state
Maintain
previous
state
Deep standby
Return from
RTC mode or Deep
Deep
standby STOP mode
standby
state
mode state
Power supply stable
Setting
disabled
External interrupt
enabled selected
Resource other
than above
selected
Timer mode,
RTC mode, or
STOP mode state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at "0"
input fixed
at "0"
at "0"
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Hi-Z at
Hi-Z at
transtransmission/
mission/
Input
Input
enabled/
enabled/
Internal
Internal
input fixed input fixed
at "0" at
at "0" at
reception reception
Hi-Z /
Input
enabled
Power
supply
stable
INITX = 1
-
Hi-Z /
Input
enabled
GPIO
selected
GPIO
selected
Hi-Z /
Input
enabled
*1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep
standby RTC mode, and Deep standby STOP mode.
*2 : Oscillation is stopped at STOP mode and Deep standby STOP mode.
*3 : Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*4 : Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
76
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
Symbol
VCC
USBVCC
AVCC
AVRH
Rating
Min
Max
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
Clamp maximum current
Clamp total maximum current
"L" level maximum output current*5
"L" level average output current*6
"L" level total maximum output current
"L" level total average output current*7
"H" level maximum output current*5
"H" level average output current*6
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
USBVCC + 0.5
(≤ 6.5V)
VSS + 6.5
VSS + 3.63
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
+2
+20
10
20
39
4
12
16.5
100
50
- 10
- 20
- 39
-4
- 12
- 18
Unit
Remarks
V
V
V
V
V
Except for USB pin
V
USB pin
V
V
5V tolerant
5V tolerant*8
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*9
*9
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"H" level total maximum output
∑IOH
- 100
mA
current
7
"H" level total average output current*
∑IOHAV
- 50
mA
Power consumption
PD
390
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1 : These parameters are based on the condition that V SS = AVSS = 0V.
*2 : VCC must not drop below VSS - 0.5V.
*3 : USBVCC must not drop below VSS - 0.5V.
*4 : Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*6 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*7 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
*8: VCC = USBVCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0V
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
77
D a t a S h e e t
*9 :
・ See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
・ Use within recommended operating conditions.
・ Use at DC voltage (current) the +B input.
・ The +B signal should always be applied a limiting resistance placed between the +B signal
and the device.
・ The value of the limiting resistance should be set so that when the +B signal is applied the
input current to the device pin does not exceed rated values, either instantaneously or for
prolonged periods.
・ Note that when the device drive current is low, such as in the low-power consumpsion modes,
the +B input potential may pass through the protective diode and increase the potential at
the VCC and AVCC pin, and this may affect other devices.
・ Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the
power supply is provided from the pins, so that incomplete operation may result.
・ The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
78
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
2.
Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
VCC
-
Power supply voltage
Power supply voltage (3V power
supply) for USB
Analog power supply voltage
Analog reference voltage
Min
Value
Max
2.7*4
AVCC
AVRH
AVRL
-
2.7
2.7
AVSS
5.5
3.6
(≤ VCC)
5.5
(≤ VCC)
5.5
AVCC
AVSS
CS
-
1
10
3.0
USBVCC
2.7
Smoothing capacitor
Unit
Remarks
V
V
V
V
AVCC = VCC
μF
For built-in
Regulator*3
*1
V
*2
Operating temperature
Ta
- 40
+ 105
°C
*1 : When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2 : When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3 : See " C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*4 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
79
D a t a S h e e t
3.
DC Characteristics
(1) Current Rating
Symbol
Parameter (Pin
name)
Value
Conditions
Power
supply
current
ICCS
ICCH
37
mA
19
26
mA
CPU/ Peripheral : 4MHz*4
*3
3.1
6.4
mA
Sub
RUN mode
CPU/ Peripheral : 32kHz
*3,*6
170
2300
µA
Low-speed CR
RUN mode
CPU/ Peripheral : 100kHz
*3
210
2300
µA
PLL
SLEEP mode
High-speed CR
SLEEP mode
Sub
SLEEP mode
Low-speed CR
SLEEP mode
Peripheral : 30MHz
*3,*5
Peripheral : 4MHz*4
*3
Peripheral : 32kHz
*3,*6
Peripheral : 100kHz
*3
Ta = + 25°C
*3
Ta = + 105°C
*3
Ta = + 25°C
*3,*6
Ta = + 105°C
*3,*6
Ta = + 25°C
*3,*6
Ta = + 105°C
*3,*6
Ta = + 25°C
*3,*6
Ta = + 105°C
*3,*6
19
26
mA
2.1
5.1
mA
160
2200
µA
190
2200
µA
20
75
μA
-
1.3
mA
2.8
5.5
mA
-
6.5
mA
24
95
μA
-
1.7
mA
21
89
μA
-
1.7
mA
High-speed CR
RUN mode
STOP mode
Main
TIMER mode
ICCT
Sub
TIMER mode
ICCR
CPU : 60MHz,
Peripheral : 30MHz
*3,*5
CPU:60MHz,
Peripheral clock stops
*3,*5
Unit Remarks
29
PLL
RUN mode
ICC
Typ*1 Max*2
RTC mode
*1 : Ta=+25℃,VCC= 3.3V
*2 : Ta=+105℃,VCC=5.5V
*3 : When all ports are fixed.
*4 : When setting it to 4MHz by trimming.
*5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
80
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
Parameter
Symbol
(Pin
name)
ICCHD
Value
Conditions
Deep Standby
STOP mode
Power
supply
current
ICCRD
Deep Standby
RTC mode
Ta = + 25°C,
When RAM is off
*3
Ta = + 25°C,
When RAM is on(16KB)*4
*3
Ta = + 25°C,
When RAM is on(32KB) *4
*3
Ta = + 105°C,
When RAM is off
*3
Ta = + 105°C,
When RAM is on(16KB) *4
*3
Ta = + 105°C,
When RAM is on(32KB) *4
*3
Ta = + 25°C,
When RAM is off
*3,*5
Ta = + 25°C,
When RAM is on(16KB) *4
*3,*5
Ta = + 25°C,
When RAM is on(32KB) *4
*3,*5
Ta = + 105°C,
When RAM is off
*3,*5
Ta = + 105°C,
When RAM is on(16KB) *4
*3,*5
Ta = + 105°C,
When RAM is on(32KB) *4
*3,*5
Typ*1 Max*2
Unit Remarks
1.9
13
μA
4.8
17
μA
5.5
20
μA
300
μA
320
μA
330
μA
2.5
14
μA
5.4
18
μA
6.1
21
μA
305
μA
325
μA
335
μA
-
-
*1 : VCC=3.3V
*2 : VCC=5.5V
*3 : When all ports are fixed and LVD off.
*4 : For more information about RAM retention area, see "Memory Map (2)" in " Memory Map".
*5 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
81
D a t a S h e e t
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Low-Voltage
detection circuit
(LVD) power
supply current
Symbol
(Pin name)
ICCLVD
(VCC)
Conditions
Min
Value
Typ
Max
-
0.13
0.3
μA
For occurrence of
reset
-
0.13
0.3
μA
For occurrence of
interrupt
Unit
Remarks
At operation
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
(VCC)
Pin
name
Min
Value
Typ
Max
At ROM0
Write/Erase
-
9.9
11.8
mA
*1
At ROM1
Write/Erase
-
9.5
11.2
mA
*1
Conditions
Unit
Remarks
VCC
*1 : When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to
the Power supply current (ICC).
In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash
Memory Write/Erase current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current
(ICC).
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current
Reference
power supply
current
(AVRH)
Symbol
ICCAD
(VCC)
ICCAVRH
(VCC)
Pin
name
AVCC
AVRH
Min
Value
Typ
Max
At 1unit
operation
-
0.69
0.9
mA
At stop
-
0.6
35
μA
At 1unit
operation
AVRH=5.5V
-
1.1
1.97
mA
At stop
-
0.2
3.4
μA
Conditions
Unit
Remarks
D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current*1
Symbol
IDDA*2
(VCC)
IDSA
(VCC)
Pin
name
AVCC
Conditions
At 1unit
operation
AVCC=3.3V
At 1unit
operation
AVCC=5.0V
At stop
Min
Value
Typ
Max
250
315
380
μA
380
475
580
μA
-
-
30
μA
Unit
Remarks
*1 : No-load
*2 : Generates the max current by the CODE about 0x200
82
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(2) Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol Pin name
"H" level
input
voltage
(hysteresis
input)
VIHS
"L" level
input
voltage
(hysteresis
input)
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
4mA type
"H" level
output
voltage
VOH
12mA type
P80, P81
4mA type
"L" level
output
voltage
VOL
12mA type
P80, P81
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Min
Value
Typ
Max
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC 0.4
-
USBVCC
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
Conditions
VCC ≥ 4.5 V,
IOH = - 4mA
VCC < 4.5 V,
IOH = - 2mA
VCC ≥ 4.5 V,
IOH = - 12mA
VCC < 4.5 V,
IOH = - 8mA
USBVCC ≥ 4.5 V,
IOH = - 18.0 mA
USBVCC < 4.5 V,
IOH = - 12.0 mA
VCC ≥ 4.5 V,
IOL = 4mA
VCC < 4.5 V,
IOL = 2mA
VCC ≥ 4.5 V,
IOL = 12mA
VCC < 4.5 V,
IOL = 8mA
USBVCC ≥ 4.5 V,
IOL = 16.5mA
USBVCC < 4.5 V,
IOL = 10.5mA
Unit Remarks
83
D a t a S h e e t
Parameter Symbol Pin name
Input leak
current
IIL
CEC0_0,
CEC0_1,
CEC1_0,
CEC1_1
Pull-up
resistance
value
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH,
AVRL
Input
capacitance
84
CONFIDENTIAL
Min
Value
Typ
Max
VCC = USBVCC =
AVCC = AVRH =
VSS = AVSS =
AVRL = 0.0V
-5
-
+5
μA
-
-
+1.8
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
Conditions
Unit Remarks
kΩ
pF
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Symbol
Pin
Conditions
name
Value
Min
Max
Unit
VCC ≥ 4.5V
VCC < 4.5V
4
4
48
20
MHz
-
4
48
MHz
-
20.83
250
ns
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
tCF,
tCR
-
-
5
ns
-
-
60
MHz
FCH
tCYLH
FCM
X0,
X1
-
Remarks
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
When using external
clock
Master clock
Base clock
FCC
60
MHz
(HCLK/FCLK)
Internal operating
1
clock* frequency
FCP0
32
MHz APB0 bus clock*2
FCP1
32
MHz APB1 bus clock*2
FCP2
32
MHz APB2 bus clock*2
Base clock
tCYCC
16.7
ns
(HCLK/FCLK)
Internal operating
t
31.25
ns
APB0 bus clock*2
CYCP0
clock*1 cycle time
tCYCP1
31.25
ns
APB1 bus clock*2
tCYCP2
31.25
ns
APB2 bus clock*2
*1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2 : For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.
X0
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
85
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Min
Value
Typ
Max
Unit
Remarks
When crystal
oscillator is
connected*
Input frequency
1/ tCYLL
When using
32
100
kHz
X0A,
external clock
X1A
When using
Input clock cycle
tCYLL
10
31.25
μs
external clock
Input clock pulse
PWH/tCYLL,
When using
45
55
%
width
PWL/tCYLL
external clock
* : For more information about crystal oscillator, see "Sub crystal oscillator" in "Handling Devices".
-
-
32.768
-
kHz
X0A
86
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(3) Built-in CR Oscillation Characteristics
・ Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRH
Conditions
Min
Ta = + 25°C,
3.6V < VCC ≤ 5.5V
Ta = 0°C to + 85°C,
3.6V < VCC ≤ 5.5V
Ta = -40°C to + 105°C,
3.6V < VCC ≤ 5.5V
Ta = + 25°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 85°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = -40°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 40°C to + 105°C
Value
Unit
Typ Max
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
Remarks
When trimming*1
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
2.8
4
5.2
MHz
When not trimming
Frequency
tCRWT
30
μs *2
stability time
*1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2 : Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
・ Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
Conditions
FCRL
-
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
87
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
tLOCK
100
-
-
μs
FPLLI
FPLLO
FCLKPLL
4
5
75
-
-
16
37
150
60
MHz
multiplier
MHz
MHz
USB clock frequency*3
FCLKSPLL
-
-
48
MHz
After the M frequency
division
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3 : For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family
PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock
of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*1
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
FPLLI
3.8
4
4.2
MHz
PLL multiplication rate
19
35 multiplier
PLL macro oscillation clock frequency
FPLLO
72
150
MHz
Main PLL clock frequency*2
FCLKPLL
60
MHz
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
PLL input
clock
K
divider
USB PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
88
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
Pin
name
Value
Max
0
-
ms
1
-
ms
1.34
18.6
ms
Tr
Toff
VCC
Tprt
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
RST Active
CPU Operation
Toff
Release
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions
・ VDH_minimum : Minimum release voltage (when SVHR=00000) of Low-Voltage detection reset.
See "8. Low-Voltage Detection Characteristics"
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
89
D a t a S h e e t
(7) External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
VCC ≥ 4.5V
50
MHz
VCC < 4.5V
32
MHz
* : The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3
Family PERIPHERAL MANUAL".
When external bus clock is not output, this characteristics does not give any effect on external bus operation.
Output frequency
tCYCLE
MCLKOUT*
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Signal input characteristics
Signal output characteristics
90
CONFIDENTIAL
Symbol
Conditions
VIH
VIL
VOH
-
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5V
MOEX
tOEW
MOEX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
-9
MCSX ↓ → Address
MCSX[7:0],
tCSL – AV
output delay time
MAD[24:0]
VCC < 4.5V
-12
VCC ≥ 4.5V
MOEX ↑ →
MOEX,
tOEH - AX
0
Address hold time
MAD[24:0]
VCC < 4.5V
VCC ≥ 4.5V
MCLK×m-9
MCSX ↓ →
tCSL - OEL
MOEX ↓ delay time
VCC < 4.5V MCLK×m-12
MOEX,
MCSX[7:0]
VCC ≥ 4.5V
MOEX ↑ →
tOEH - CSH
0
MCSX ↑ time
VCC < 4.5V
VCC ≥ 4.5V
MCLK×m-9
MCSX ↓ →
MCSX,
tCSL - RDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V
20
Data set up →
MOEX,
tDS - OE
MOEX ↑ time
MADATA[15:0]
VCC < 4.5V
38
VCC ≥ 4.5V
MOEX ↑ →
MOEX,
tDH - OE
0
Data hold time
MADATA[15:0]
VCC < 4.5V
VCC ≥ 4.5V
MWEX
tWEW
MWEX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
MWEX ↑ → Address
MWEX,
tWEH - AX
0
output delay time
MAD[24:0]
VCC < 4.5V
VCC ≥ 4.5V
MCLK×n-9
MCSX ↓ →
tCSL - WEL
MWEX ↓ delay time
VCC < 4.5V
MCLK×n-12
MWEX,
MCSX[7:0]
VCC ≥ 4.5V
MWEX ↑ →
tWEH - CSH
0
MCSX ↑ delay time
VCC < 4.5V
VCC ≥ 4.5V
MCLK×n-9
MCSX ↓→
MCSX,
tCSL-WDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 4.5V
MCLK×n-12
VCC ≥ 4.5V
MCLK-9
MCSX ↓→
MCSX,
tCSL-DV
Data output time
MADATA[15:0]
VCC < 4.5V
MCLK-12
VCC ≥ 4.5V
MWEX ↑ →
MWEX,
tWEH - DX
0
Data hold time
MADATA[15:0]
VCC < 4.5V
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Max
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+12
ns
ns
ns
ns
ns
ns
91
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
92
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK,
MAD[24:0]
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
tCSL
MCLK,
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK,
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
tDS
tDH
tWEL
MCLK,
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
tDQMH
MCLK ↑ →
MCLK,
tODS
Data output time
MADATA[15:0]
MCLK ↑ →
MCLK,
tOD
Data hold time
MADATA[15:0]
Note: When the external load capacitance CL = 30 pF.
Value
Min
Max
1
12
1
1
1
1
Unit
ns
9
12
9
12
9
12
9
12
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
MAD[24:0]
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
93
D a t a S h e e t
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5V
Multiplexed
tALE-CHMADV
0
address delay time
VCC < 4.5V
MALE,
MADATA[15:0]
VCC ≥ 4.5V
MCLK×n+0
Multiplexed
tCHMADH
address hold time
VCC < 4.5V
MCLK×n+0
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Max
+10
+20
MCLK×n+12
MCLK×n+20
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
94
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
MCLK,
ALE
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
tCHMADV
Address delay time
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
tCHMADX
Data output time
Note: When the external load capacitance CL = 30 pF.
VCC ≥ 4.5V
Min
VCC < 4.5V
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
VCC < 4.5V
VCC ≥ 4.5V
Value
Max
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
95
D a t a S h e e t
NAND Flash Memory Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5V
MNREX
tNREW
MNREX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
20
Data setup →
MNREX,
tDS – NRE
MNREX↑time
MADATA[15:0] VCC < 4.5V
38
VCC ≥ 4.5V
MNREX↑→
MNREX,
tDH – NRE
0
Data hold time
MADATA[15:0] VCC < 4.5V
VCC ≥ 4.5V MCLK×m-9
MNALE↑→
MNALE,
tALEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V MCLK×m-9
MNALE↓→
MNALE,
tALEL - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V MCLK×m-9
MNCLE↑→
MNCLE,
tCLEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V
MNWEX↑→
MNCLE,
tNWEH - CLEL
0
MNCLE delay time
MNWEX
VCC < 4.5V
VCC ≥ 4.5V
MNWEX
tNWEW
MNWEX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
-9
MNWEX↓→
MNWEX,
tNWEL – DV
Data output time
MADATA[15:0] VCC < 4.5V
-12
VCC ≥ 4.5V
MNWEX↑→
MNWEX,
tNWEH – DX
0
Data hold time
MADATA[15:0] VCC < 4.5V
Note: When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
96
CONFIDENTIAL
Max
Unit
-
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
+9
+12
MCLK×m+11
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
NAND Flash Memory Read
MCLK
MNREX
MADATA[15:0]
Read
NAND Flash Memory Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Write
97
D a t a S h e e t
NAND Flash Memory Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
98
CONFIDENTIAL
Write
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
MCLK ↑
MRDY input
setup time
Symbol
tRDYI
Pin name Conditions
MCLK,
MRDY
Value
Min
VCC ≥ 4.5V
19
VCC < 4.5V
37
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
·· · ·· ·
2 cycles
Extended
MOEX
MWEX
tRDYI
MRDY
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
0.5×VCC
99
D a t a S h e e t
(8) Base Timer Input Timing
・ Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
・ Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data
sheet.
100
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(9) CSIO/UART Timing
・ CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC ≥ 4.5V
Min
Max
Unit
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
・ About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30pF.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
VCC < 4.5V
Min
Max
101
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
SIN
tSHIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
102
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・ CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
・ About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
VCC ≥ 4.5V
Min
Max
Pin
Conditions
name
103
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
SIN
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
SIN
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
104
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
VCC < 4.5V
Min
Max
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
Unit
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
・ About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
VCC ≥ 4.5V
Min
Max
Pin
Conditions
name
105
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
* : Changes when writing to TDR register
106
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
・ About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance CL = 30 pF.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
107
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
tSHSL
tR
SCK
VIH
VIL
VIH
tF
tSHIXE
t IVSHE
VIH
VIL
VIH
VIL
SIN
VIH
t SLOVE
VOH
VOL
VOH
VOL
SOT
VIL
VIL
Slave mode
・ UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
CL = 30pF
Max
tCYCP + 10
tCYCP + 10
-
5
5
t
V IL
Unit Remarks
ns
ns
ns
ns
t
SHSL
SCK
CONFIDENTIAL
Min
tF
tR
108
Value
Symbol Conditions
V
IH
SLSH
V
IH
V IL
VIL
V
IH
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(10) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
ADTG
FRCKx
Input pulse width
tINH,
tINL
ICxx
DTTIxX
INTxx
WKUPx
-
2tCYCP*1
-
ns
*2
*3
2tCYCP*1
2tCYCP + 100*1
500
-
ns
ns
ns
*4
500
-
ns
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Waveform generator
External interrupt,
NMI
Deep standby wake
up
*1 : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "Block Diagram" in this data sheet.
*2 : When in RUN mode, in SLEEP mode.
*3 : When in STOP mode, in TIMER mode.
*4 : When in Deep standby RTC mode, in Deep standby STOP mode.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
109
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
Time from AIN pin "H"
PC_Mode2 or
tAUBU
level to BIN rise
PC_Mode3
Time from BIN pin "H"
PC_Mode2 or
tBUAD
level to AIN fall
PC_Mode3
Time from AIN pin "L"
PC_Mode2 or
tADBD
level to BIN fall
PC_Mode3
Time from BIN pin "L"
PC_Mode2 or
tBDAU
level to AIN rise
PC_Mode3
Time from BIN pin "H"
PC_Mode2 or
tBUAU
level to AIN rise
PC_Mode3
2tCYCP*
ns
Time from AIN pin "H"
PC_Mode2 or
tAUBD
level to BIN fall
PC_Mode3
Time from BIN pin "L"
PC_Mode2 or
tBDAD
level to AIN fall
PC_Mode3
Time from AIN pin "L"
PC_Mode2 or
tADBU
level to BIN rise
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
Time from determined ZIN
level to AIN/BIN rise and
tZABE
QCR:CGSC="1"
fall
Time from AIN/BIN rise
and fall time to determined
tABEZ
QCR:CGSC="1"
ZIN level
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block
Diagram" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
110
CONFIDENTIAL
tBLL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
111
D a t a S h e e t
2
(12) I C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Standard-mode Fast-mode
Unit Remarks
Min
Max
Min Max
SCL clock frequency
FSCL
0
100
0
400 kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓ → SCL ↓
SCLclock "L" width
tLOW
4.7
1.3
μs
SCLclock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START condition
setup time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 30 pF,
R = (Vp/IOL)*1
Data hold time
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
tBUF
4.7
1.3
μs
"START condition"
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4 ns
*1 : R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
112
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
(13) ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Data hold
TRACECLK
frequency
Pin name
Conditions
tETMH
TRACECLK,
TRACED[3:0]
VCC ≥ 4.5V
2
10
VCC < 4.5V
2
15
VCC ≥ 4.5V
-
40
MHz
VCC < 4.5V
-
20
MHz
VCC ≥ 4.5V
25
-
ns
VCC < 4.5V
50
-
ns
1/ tTRACE
TRACECLK
TRACECLK
clock cycle
Value
Unit
Min Max
Symbol
tTRACE
Remarks
ns
Note: When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
113
D a t a S h e e t
(14) JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
VCC < 4.5V
Note: When the external load capacitance CL = 30 pF.
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
TCK
TMS/TDI
TDO
114
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
5.
12-bit A/D Converter
・Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Max
± 1.5
± 2.2
±6
12
± 4.5
± 2.5
± 15
Symbol
Pin
name
Min
VZT
ANxx
-
VFST
ANxx
-
-
-
1.0*1
-
-
μs
Ts
-
0.3
-
10
μs
Compare clock cycle*
State transition time to
operation permission
Tcck
-
50
-
1000
ns
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
9.5
pF
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Conversion time
Sampling time*2
3
AVRH ± 5 AVRH ± 15
Unit
bit
LSB
LSB
mV
Remarks
AVRH = 2.7V
to 5.5V
mV
1.62
AVCC ≥ 4.5V
kΩ
2.35
AVCC < 4.5V
Interchannel disparity
4
LSB
Analog port input current
ANxx
5
μA
Analog input voltage
ANxx
AVRL
AVRH
V
AVRH
2.7
AVCC
V
Reference voltage
AVRL
AVSS
AVSS
V
*1 : The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of
compare time:700ns (AVCC ≥ 4.5V).
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data
sheet.
*2 : A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3 : The compare time (Tc) is the value of (Equation 2).
Analog input resistor
RAIN
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
-
-
-
115
D a t a S h e e t
Rext
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistor of A/D = 1.62 kΩ ch.0 to ch.7
at 4.5V < AVCC < 5.5V
input resistor of A/D = 1.58 kΩ ch.8 to ch.15
at 4.5V < AVCC < 5.5V
input resistor of A/D = 1.56 kΩ ch.16 to ch.23 at 4.5V < AVCC < 5.5V
input resistor of A/D = 2.35 kΩ ch.0 to ch.7
at 2.7V < AVCC < 4.5V
input resistor of A/D = 2.3 kΩ
ch.8 to ch.15
at 2.7V < AVCC < 4.5V
input resistor of A/D = 2.25 kΩ ch.16 to ch.23 at 2.7V < AVCC < 4.5V
CAIN : input capacity of A/D = 9.5pF at 2.7V < AVCC < 5.5V
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
116
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・ Resolution
・ Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
・ Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVRL
Actual conversion characteristics
AVRH
AVRL
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
:
:
:
:
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
AVRH
Analog input
117
D a t a S h e e t
6.
10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Parameter
Resolution
Conversion time
Integral Nonlinearity*1
Differential
Nonlinearity*1,*2
Output Voltage offset
Analog output
impedance
Output undefined period
Symbol Pin name
tc20
tc100
INL
DNL
VOFF
RO
tR
DAx
Min
Value
Typ Max
Unit
0.47
2.37
- 4.0
0.58
2.90
-
10
0.69
3.43
+ 4.0
bit
μs
μs
LSB
- 0.9
-
+ 0.9
LSB
- 20.0
3.10
2.0
-
3.80
-
10.0
+ 5.4
4.50
70
mV
mV
kΩ
MΩ
ns
Remarks
Load 20pF
Load 100pF
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
*1 : No-load
*2 : Generates the max current by the CODE about 0x200
118
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
7.
USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Input
characteristics
Symbol
Pin
Conditions
name
Min
Value
Max
Unit Remarks
Input "H" level voltage
VIH
-
2.0
Input "L" level voltage
Differential input
sensitivity
Different common mode
range
VIL
-
VSS - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
2.8
3.6
V
*3
0.0
0.3
V
*3
Output "H" level voltage
VOH
Output "L" level voltage
VOL
Output
characteristics
External
pull-down
resistor =
15kΩ
External
UDP0,
pull-up
UDM0 resistor =
1.5kΩ
Full-Speed
Full-Speed
USBVCC + 0.3 V
*1
Minimum differential input
sensitivity [V]
Crossover voltage
VCRS
1.3
2.0
V *4
Rising time
tFR
4
20
ns *5
Falling time
tFF
4
20
ns *5
Rising/falling time
tFRFM
Full-Speed
90
111.11
% *5
matching
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rising time
tLR
Low-Speed
75
300
ns *7
Falling time
tLF
Low-Speed
75
300
ns *7
Rising/falling time
tLRFM
Low-Speed
80
125
% *7
matching
*1 : The switching threshold voltage of the Single-End-Receiver of USB I/O buffer is set as within V IL
(Max) = 0.8V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2 : Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is
within 0.8 V to 2.5 V to the local ground reference level.
The voltage range above is said to be the common mode input voltage range.
Common mode input voltage [V]
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
119
D a t a S h e e t
*3 : The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to ground and 15 kΩ load) at High-State (VOH).
*4 : The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5 : They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
120
CONFIDENTIAL
Falling time
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
*6 : USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7 : They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See "・Low-Speed Load (Compliance Load)" for conditions of the external load.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
121
D a t a S h e e t
・Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
・Low-Speed Load (Downstream Port Load) - Reference 2
CL = 200pF to
600pF
CL = 200pF to
600pF
・Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
122
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
8.
Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(Ta = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Detected voltage
VDL
SVHR*1 = 00000
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
SVHR*1 = 00001
Min
Value
Typ
Unit
Max
2.25
2.45
2.65
V
2.30
2.50
2.70
V
2.39
2.60
2.81
V
Same as SVHR = 00000 value
SVHR*1 = 00010
2.48
2.70
2.92
Same as SVHR = 00000 value
SVHR*1 = 00011
2.58
2.80
3.02
Same as SVHR = 00000 value
SVHR*1 = 00100
2.76
3.00
3.24
Same as SVHR = 00000 value
SVHR*1 = 00101
2.94
3.20
3.46
Same as SVHR = 00000 value
SVHR*1 = 00110
3.31
3.60
3.89
Same as SVHR = 00000 value
SVHR*1 = 00111
3.40
3.70
4.00
Same as SVHR = 00000 value
SVHR*1 = 01000
3.68
4.00
4.32
Same as SVHR = 00000 value
SVHR*1 = 01001
3.77
4.10
4.43
Same as SVHR = 00000 value
SVHR*1 = 01010
3.86
4.20
4.54
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
Released voltage
VDH
Same as SVHR = 00000 value
V
LVD
6432 ×
stabilization wait
TLVDW
μs
tCYCP*2
time
LVD detection
TLVDDL
200
μs
delay time
*1 : The SVHR bit of Low-voltage Detection Voltage Control Register (LVD_CTL) is initialized to “00000” by
low-voltage detection reset.
*2 : tCYCP indicates the APB2 bus clock cycle time.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
123
D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(Ta = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
-
LVD detection
TLVDDL
delay time
* : tCYCP indicates the APB2 bus clock cycle time.
124
CONFIDENTIAL
Min
Value
Typ
Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
6432 ×
tCYCP*
μs
-
-
200
μs
Unit
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
9.
Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Sector erase
time
Large Sector
Value
Typ
Max
1.1
2.7
Unit
s
Small Sector
0.3
0.9
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
31
79
s
erase
* : The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle
of erase/write.
Half word (16-bit) write time
20
317
μs
(2)Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
* : At average + 85C
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Remarks
10*
125
D a t a S h e e t
10. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Typ
Max*
tCYCC
Low-speed CR TIMER mode
Sub TIMER mode
Value
Ticnt
RTC mode,
STOP mode
Deep Standby RTC mode,
Deep Standby STOP mode
Unit
Remarks
ns
43
83
μs
310
620
μs
534
724
μs
278
479
μs
298
543
μs
When RAM is off
288
523
μs
When RAM is on
* : The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : External interrupt is set to detecting fall edge.
126
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
127
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
149
264
μs
149
264
μs
318
603
μs
308
583
μs
RTC/STOP mode
248
443
μs
Deep Standby RTC mode,
Deep Standby STOP mode
298
543
μs
When RAM is off
288
523
μs
When RAM is on
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
Trcnt
* : The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
128
CONFIDENTIAL
Start
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■Electrical Characteristics" for the detailon the time
during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
129
D a t a S h e e t
Ordering Information
On-chip
Flash
memory
On-chip
SRAM
MB9BF528SAPMC-GE1
Main: 1 Mbyte
Work: 64 Kbyte
160 Kbyte
MB9BF529SAPMC-GE1
Main: 1.5 Mbyte
Work: 64 Kbyte
192 Kbyte
MB9BF528TAPMC-GE1
Main: 1 Mbyte
Work: 64 Kbyte
160 Kbyte
MB9BF529TAPMC-GE1
Main: 1.5 Mbyte
Work: 64 Kbyte
192 Kbyte
MB9BF528TABGL-GE1
Main: 1 Mbyte
Work: 64 Kbyte
160 Kbyte
MB9BF529TABGL-GE1
Main: 1.5 Mbyte
Work: 64 Kbyte
192 Kbyte
Part number
130
CONFIDENTIAL
Package
Packing
Plastic・LQFP,
144-pin (0.5mm pitch)
(FPT-144P-M08)
Plastic・LQFP,
176-pin (0.5mm pitch)
(FPT-176P-M07)
Tray
Plastic・FBGA,
192-pin (0.8mm pitch)
(BGA-192P-M06)
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Package Dimensions
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.5 0
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
132
0.145±0.055
(.006±.002)
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
LEAD No.
45
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
0.08(.003)
"A"
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
131
D a t a S h e e t
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20 g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
132
CONFIDENTIAL
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B520TA_DS706-00060-2v0-E, January 30, 2014
D a t a S h e e t
192-ball plastic FBGA
Ball pitch
0.80 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.45 mm Max.
Weight
0.34 g
(BGA-192P-M06)
192-ball plastic FBGA
(BGA-192P-M06)
10.40(.409)REF
12.00±0.10(.472±.004)
0.20(.008) S B
B
0.80(.031)
REF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
12.00±0.10
(.472±.004)
(INDEX AREA)
10.40(.409)
REF
0.20(.008) S A
0.35±0.10
(.014±.004)
(Stand off)
1.25±0.20
(.049±.008)
(Seated height)
P N M L K J H G F E D C B A
INDEX
192-ø0.45±0.10
(192-ø.018±.004)
ø0.08(.003)
M
S A B
S
0.10(.004) S
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED B192006S-c-1-3
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
133
D a t a S h e e t
Major Changes
Page
Revision 0.1
Revision 0.2
Revision 1.0
2
4
5
8
64
66
67
77
79
80 - 82
Section
-
Initial release
-
Company name and layout design change
FEATURES
External Bus Interface
FEATURES
A/D Converter
FEATURES
Multi-function Timer
PRODUCT LINEUP
Function
HANDLING DEVICES
Power supply pins
BLOCK DIAGRAM
MEMORY MAP
Memory Map(1)
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
3.DC Characteristics
(1) Current Rating
84
(2) Pin Characteristics
89
4. AC Characteristics
(6) Power-on Reset Timing
108
(9) CSIO Timing
Synchronous serial (SPI=1, SCINV=1)
External clock (EXT=1):asynchronous only
115
125
126
128
Change Results
5.12-bit A/D Converter
・Electrical characteristics for the A/D
converter
9. Electrical characteristics for the A/D
converter
(1) Write / Erase time
10. Return Time from Low-Power
Consumption Mode
(1) Return Factor: Interrupt/WKUP
Return Count Time
(2) Return Factor: Reset
Return Count Time
Preliminary → Full Production
Added the descriptions as follows
Maximum area size : Up to 256 Mbytes
Corrected conversion time
Corrected the channel count of "A/D activation compare"
Added the footnote
Added the description
Corrected the figure
Corrected the Address of “External Device Area”
Added the Item of “Input Voltage”
Added the footnote
Corrected the Condition
Corrected the Value
Corrected the Remarks
Added the footnote
Added the Item of “Inputleak current”
Revised the values of “Time until releasing Power-on reset”
Corrected the figure
Corrected the Glossary
Corrected the figure of “MS bit=1”
Corrected the figure
Corrected the Pins name
AN00 - AN23 → ANxx
Corrected the Min Vale of “Conversion time”
Corrected the Min Vale of “Sampling time”
Corrected the Min Value of “Compare clock cycle”
Corrected the “State Transitontime to operation permission”
Corrected the footnote
Revised the values of “TBD”
Revised the values of “TBD”
Revised the values of “TBD”
Revision 2.0
-
-
-
-
2
42 to 49
56, 57
68
77, 78
80, 81
134
CONFIDENTIAL
Features
USB Interface
List of Pin Functions
· List of pin functions
I/O Circuit Type
Memory Map
· Memory map(2)
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Changed the series name.
MB9B520T Series -> MB9B520TA Series
Changed the product name as follows.
MB9BF528SA, MB9BF529SA, MB9BF528TA, MB9BF529TA
Added the description of PLL for USB
Added LIN to the description of SOTxx
Added about +B input
Added the summary of Flash memory sector
· Added the Clamp maximum current
· Added about +B input
· Changed the expression of condition
· Added Main TIMER mode current
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
Page
88
101 to 108
115
130
Section
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main and USB
PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Ordering Information
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
Change Results
· Added the figure of Main PLL connection and USB PLL connection
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
Change to full part number
135
D a t a S h e e t
136
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015
D a t a S h e e t
January 30, 2015, MB9B520TA_DS706-00060-2v0-E
CONFIDENTIAL
137
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2015 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
138
CONFIDENTIAL
MB9B520TA_DS706-00060-2v0-E, January 30, 2015