The following document contains information on Cypress products. Although the document is marked with the name “Spansion”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes ® NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC ® programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense ® capacitive touch-sensing controllers, and Wireless BLE Bluetooth Low-Energy and USB connectivity solutions, Cypress is committed to providing its customers worldwide with consistent innovation, bestin-class support and exceptional system value. MB9A130LB Series ® 32-bit ARM Cortex®-M3 based Microcontroller MB9AF131KB/LB, MB9AF132KB/LB Data Sheet (Full Production) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number MB9A130LB-DS706-00066 CONFIDENTIAL Revision 2.0 Issue Date June 9, 2015 D a t a S h e e t Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 CONFIDENTIAL MB9A130LB Series 32-bit ARM® Cortex®-M3 based Microcontroller MB9AF131KB/LB, MB9AF132KB/LB Data Sheet (Full Production) Description The MB9A130LB Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power consumption mode and competitive cost. The MB9A130LB Series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE3 product categories in FM3 Family Peripheral Manual. Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. Publication Number MB9A130LB-DS706-00066 Revision 2.0 Issue Date June 9, 2015 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 20MHz Operation Frequency Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Up to 128 Kbytes Read cycle: 0 wait-cycle Security function for code protection [SRAM] This series contains 8 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core. SRAM1: 8 Kbytes Multi-function Serial Interface (Max 8channels) Operation mode is selectable from the followings for each channel. UART CSIO I2C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available 2 [I C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported A/D Converter (Max 8channels) [12-bit A/D Converter] Successive Approximation type Conversion time: Min. 1.0 μs Priority conversion available (priority at 2 levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) 2 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Base Timer (Max 8channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 52 fast general purpose I/O Ports@64 pin Package Some pins are 5V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer × 3ch. Input capture × 4ch. Output compare × 6ch. A/D activation compare × 1ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. External Interrupt Controller Unit Up to 8 external interrupt input pins Include one non-maskable interrupt (NMI) input pin June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 3 D a t a S h e e t Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. Hardware watchdog timer is clocked by built-in Low-speed CR oscillator. Therefore, Hardware watchdog is active in any low power consumption mode except RTC and Stop and Deep Standby RTC and Deep Standby Stop modes. Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL) that are dynamically selectable. Main Clock: Sub Clock: Built-in High-speed CR Clock: Built-in Low-speed CR Clock: Main PLL Clock 4 MHz to 20 MHz 32.768 kHz 4 MHz 100 kHz [Resets] Reset requests from INITX pin Power on reset Software reset Watchdog timers reset Low voltage detector reset Clock supervisor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has been set, Low Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low Power Consumption Mode Six low power consumption modes supported. Sleep Timer RTC Stop Deep Standby RTC Deep Standby Stop Back up register is 16 bytes. 4 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Debug Serial Wire JTAG Debug Port (SWJ-DP) Power Supply Wide range voltage : VCC = 1.8 V to 5.5 V June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 5 D a t a S h e e t Product Lineup Memory size Product name On-chip Flash On-chip SRAM SRAM1 MB9AF131KB/LB MB9AF132KB/LB 64 Kbytes 8 Kbytes 128 Kbytes 8 Kbytes MB9AF131KB MB9AF132KB MB9AF131LB MB9AF132LB Function Product name Pin count CPU Freq. Power supply voltage range MF Serial Interface (UART/CSIO/I2C) Base Timer (PWC/ Reload timer/PWM/PPG) A/D activation 1ch. compare Input capture 4ch. Free-run timer 3ch. MFTimer Output compare 6ch. Waveform 3ch. generator PPG 3ch. Real-time clock Watchdog timer External Interrupts general purpose I/O ports 12-bit A/D converter CSV (Clock Super Visor) LVD (Low Voltage Detector) High-speed Built-in CR Low-speed Debug Function 48 64 Cortex-M3 20 MHz 1.8 V to 5.5 V 4ch. (Max) (CSIO and I2C is Max 3ch.) 8ch. (Max) 8ch. (Max) 1 unit (Max) 1 unit 1ch. (SW) + 1ch. (HW) 6 pins (Max) + NMI × 1 8 pins (Max) + NMI × 1 37 pins (Max) 52 pins (Max) 6ch. (1 unit) 8ch. (1 unit) Yes 2ch. 4 MHz 100 kHz SWJ-DP Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for accuracy of built-in CR. 6 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Packages Product name Package LQFP: QFN: LQFP: LQFP: QFN: FPT-48P-M49 (0.5mm pitch) LCC-48P-M73 FPT-64P-M38 (0.5mm pitch) FPT-64P-M39 (0.65mm pitch) LCC-64P-M24 MB9AF131KB MB9AF132KB - MB9AF131LB MB9AF132LB : Supported Note : See Package Dimensions for detailed information on each package. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 7 D a t a S h e e t Pin Assignment FPT-48P-M49 VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 31 AVCC P3B / TIOA1_1 / RTO01_0 7 30 P15 / AN05 / IC03_2 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 12 25 P10 / AN00 14 15 16 17 18 19 20 21 22 23 24 P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS 13 C VCC P46 / X0A LQFP - 48 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 8 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t LCC-48P-M73 37 P00 / TRSTX 38 P01 / TCK / SWCLK 39 P02 / TDI 40 P03 / TMS / SWDIO 41 P04 / TDO / SWO 42 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 43 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 44 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 45 P80 46 P81 47 P82 48 VSS (TOP VIEW) VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 P3B / TIOA1_1 / RTO01_0 7 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 31 AVCC QFN - 48 30 P15 / AN05 / IC03_2 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 24 PE3 / X1 23 PE2 / X0 22 MD0 21 PE0 / MD1 20 P4A / TIOB1_0 19 P49 / TIOB0_0 18 INITX 17 P47 / X1A 16 P46 / X0A 15 C 13 25 P10 / AN00 VCC 14 VSS 12 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 9 D a t a S h e e t FPT-64P-M38/M39 VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 P4B / TIOB2_0 P4C / SCK7_1 / TIOB3_0 P4D / SOT7_1 / TIOB4_0 P4E / SIN7_1 / TIOB5_0 / INT06_2 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS 17 C VCC P46 / X0A LQFP - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 10 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t LCC-64P-M24 49 P00 / TRSTX 50 P01 / TCK / SWCLK 51 P02 / TDI 52 P03 / TMS / SWDIO 53 P04 / TDO / SWO 54 P0A / SIN4_0 / INT00_2 55 P0B / SOT4_0 / TIOB6_1 56 P0C / SCK4_0 / TIOA6_1 57 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 58 P62 / SCK5_0 / ADTG_3 59 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 60 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 61 P80 62 P81 63 P82 64 VSS (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 P39 / DTTI0X_0 / ADTG_2 9 41 AVCC QFN - 64 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 32 PE3 / X1 31 PE2 / X0 30 MD0 29 PE0 / MD1 28 P4E / SIN7_1 / TIOB5_0 / INT06_2 27 P4D / SOT7_1 / TIOB4_0 26 P4C / SCK7_1 / TIOB3_0 25 P4B / TIOB2_0 24 P4A / TIOB1_0 23 P49 / TIOB0_0 22 INITX 21 P47 / X1A 20 P46 / X0A 19 C 17 33 VCC VCC 18 VSS 16 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 11 D a t a S h e e t List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Pin name 1 1 2 2 3 3 4 4 5 - 6 - 7 - 8 - 9 5 10 6 VCC P50 INT00_0 SIN3_1 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) P30 TIOB0_1 INT03_2 P31 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 P32 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 P39 DTTI0X_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 12 CONFIDENTIAL I/O circuit type Pin state type - G F G F G F E F E F E F E F E H E H MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 11 7 12 8 13 9 14 10 15 11 16 17 18 12 13 14 19 15 20 16 21 17 22 18 23 19 24 - June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Pin name P3B RTO01_0 (PPG00_0) TIOA1_1 P3C RTO02_0 (PPG02_0) TIOA2_1 P3D RTO03_0 (PPG02_0) TIOA3_1 P3E RTO04_0 (PPG04_0) TIOA4_1 P3F RTO05_0 (PPG04_0) TIOA5_1 VSS C VCC P46 X0A P47 X1A INITX P49 TIOB0_0 P4A TIOB1_0 P4B TIOB2_0 I/O circuit type Pin state type E H E H E H E H E H D M D N B C E H E H E H 13 D a t a S h e e t Pin No LQFP-64 QFN-64 14 CONFIDENTIAL LQFP-48 QFN-48 25 - 26 - 27 - 28 20 29 21 30 22 31 23 32 33 24 - 34 25 35 26 36 27 37 28 Pin name P4C TIOB3_0 SCK7_1 (SCL7_1) P4D TIOB4_0 SOT7_1 (SDA7_1) P4E TIOB5_0 INT06_2 SIN7_1 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 P11 AN01 SIN1_1 INT02_1 FRCK0_2 IC02_0 WKUP1 P12 AN02 SOT1_1 (SDA1_1) IC00_2 P13 AN03 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 I/O circuit type Pin state type E H E H E F C P H D A A A B - F J F L F J F J MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 38 29 39 30 40 - 41 42 43 31 32 33 44 - 45 - 46 34 47 35 48 36 49 37 50 38 51 39 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Pin name P14 AN04 INT03_1 IC02_2 P15 AN05 IC03_2 P17 AN07 SIN2_2 INT04_1 AVCC AVRH AVSS P18 AN08 SOT2_2 (SDA2_2) P19 SCK2_2 (SCL2_2) P23 SCK0_0 (SCL0_0) TIOA7_1 P22 SOT0_0 (SDA0_0) TIOB7_1 P21 SIN0_0 INT06_1 WKUP2 P00 TRSTX P01 TCK SWCLK P02 TDI I/O circuit type Pin state type F K F J F K - F J E H G H G H G G E E E E E E 15 D a t a S h e e t Pin No LQFP-64 QFN-64 16 CONFIDENTIAL LQFP-48 QFN-48 52 40 53 41 54 - 55 - 56 - 57 42 58 - 59 43 60 44 61 62 63 64 45 46 47 48 Pin name P03 TMS SWDIO P04 TDO SWO P0A SIN4_0 INT00_2 P0B SOT4_0 (SDA4_0) TIOB6_1 P0C SCK4_0 (SCL4_0) TIOA6_1 P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P62 SCK5_0 (SCL5_0) ADTG_3 P61 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 P60 SIN5_0 TIOA2_2 INT15_1 IC00_0 WKUP3 P80 P81 P82 VSS I/O circuit type Pin state type E E E E E F E H E H E I I H I H I G G G G O O O - MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin function Pin name ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger ADTG_2 ADTG_3 ADTG_6 AN00 AN01 AN02 AN03 AN04 AN05 AN07 AN08 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_1 TIOB4_0 TIOA5_1 TIOB5_0 TIOA6_1 TIOB6_1 TIOA7_1 TIOB7_1 SWCLK SWDIO SWO TRSTX TCK TDI TMS TDO Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin J-TAG reset Input pin J-TAG test clock input pin J-TAG test data input pin J-TAG test mode state input/output pin J-TAG debug data output pin June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL LQFP-64 QFN-64 9 58 8 34 35 36 37 38 39 40 44 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 56 55 46 47 50 52 53 49 50 51 52 53 LQFP-48 QFN-48 5 25 26 27 28 29 30 6 18 7 19 8 44 43 9 10 11 34 35 38 40 41 37 38 39 40 41 17 D a t a S h e e t Pin No Pin function Pin name External Interrupt GPIO 18 CONFIDENTIAL INT00_0 INT00_2 INT01_0 INT02_0 INT02_1 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_2 INT06_1 INT06_2 INIT15_1 NMIX P00 P01 P02 P03 P04 P0A P0B P0C P0F P10 P11 P12 P13 P14 P15 P17 P18 P19 P21 P22 P23 Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 LQFP-64 QFN-64 2 54 3 4 35 38 5 8 40 6 7 48 27 60 57 49 50 51 52 53 54 55 56 57 34 35 36 37 38 39 40 44 45 48 47 46 LQFP-48 QFN-48 2 3 4 26 29 36 44 42 37 38 39 40 41 42 25 26 27 28 29 30 36 35 34 MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin No Pin function Pin name GPIO P30 P31 P32 P33 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P4B P4C P4D P4E P50 P51 P52 P60 P61 P62 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL LQFP-64 QFN-64 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 61 62 63 28 30 31 LQFP-48 QFN-48 5 6 7 8 9 10 11 15 16 18 19 2 3 4 44 43 45 46 47 20 22 23 19 D a t a S h e e t Pin No Pin function Pin name Multifunction Serial 0 Multifunction Serial 1 Multifunction Serial 2 20 CONFIDENTIAL Function description LQFP-64 QFN-64 LQFP-48 QFN-48 Multi-function serial interface ch.0 input pin 48 36 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 47 35 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 46 34 Multi-function serial interface ch.1 input pin 35 26 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 36 27 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 37 28 Multi-function serial interface ch.2 input pin 40 - SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 44 - SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 45 - SIN0_0 SIN1_1 SIN2_2 MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin No Pin function Pin name Multifunction Serial 3 Multifunction Serial 4 LQFP-64 QFN-64 2 LQFP-48 QFN-48 2 SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 3 3 SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 4 Multi-function serial interface ch.4 input pin 54 - Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 55 - 56 - 60 44 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 59 43 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 58 - SIN3_1 SIN4_0 SOT4_0 (SDA4_0) SCK4_0 (SCL4_0) Multifunction Serial 5 Function description SIN5_0 Multi-function serial interface ch.3 input pin Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 input pin June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 21 D a t a S h e e t Pin No Pin function Pin name Multifunction Serial 6 Multifunction Serial 7 22 CONFIDENTIAL Function description LQFP-64 QFN-64 8 LQFP-48 QFN-48 - SOT6_1 (SDA6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). 7 - SCK6_1 (SCL6_1) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 6 - Multi-function serial interface ch.7 input pin 27 - SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 26 - SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 25 - SIN6_1 SIN7_1 Multi-function serial interface ch.6 input pin MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin No Pin function Pin name Function description Multifunction Timer 0 DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 16-bit free-run timer ch.0 external clock input pin DTTI0X_2 FRCK0_2 IC00_0 IC00_2 IC01_2 IC02_0 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Real-time clock Low Power Consumption Mode RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 WKUP0 WKUP1 WKUP2 WKUP3 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep stand-by mode return signal input pin 0 Deep stand-by mode return signal input pin 1 Deep stand-by mode return signal input pin 2 Deep stand-by mode return signal input pin 3 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL LQFP-64 QFN-64 9 LQFP-48 QFN-48 5 59 43 35 26 60 36 37 35 38 39 44 27 28 26 29 30 10 6 11 7 12 8 13 9 14 10 15 11 57 37 10 57 37 10 57 35 48 60 42 28 6 42 28 6 42 26 36 44 23 D a t a S h e e t Pin No Pin function Reset Pin name INITX Mode MD0 MD1 Function description LQFP-64 QFN-64 LQFP-48 QFN-48 21 17 29 21 28 20 1 18 33 16 32 64 30 19 31 20 57 41 1 14 12 24 48 22 15 23 16 42 31 42 32 A/D converter GND pin 43 33 Power stabilization capacity pin 17 13 External Reset Input pin. A reset is valid when INITX = L. Mode 0 pin. During normal operation, MD0 = L must be input During serial programming to flash memory, MD0 = H must be input. Mode 1 pin. During normal operation, input is not needed During serial programming to flash memory, MD1 = L must be input. Power VCC Power supply pin VSS GND pin GND Clock ADC Power ADC GND C pin 24 CONFIDENTIAL X0 X0A X1 X1A CROUT_1 AVCC AVRH AVSS C Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in High-speed CR-osc clock output port A/D converter analog power pin A/D converter analog reference voltage input pin MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function. Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R Pull-up resistor control When the main oscillation is selected. Oscillation feedback resistor : Approximately 1 MΩ With Standby control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Digital input Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control CMOS level hysteresis input Pull-up resistor : Approximately 50 kΩ B Pull-up resistor Digital input June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 25 D a t a S h e e t Type Circuit Remarks Open drain output CMOS level hysteresis input C Digital input Digital output N-ch D It is possible to select the sub oscillation / GPIO function Pull-up When the sub oscillation is selected. Oscillation feedback resistor : Approximately 5 MΩ With Standby control resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control Digital input When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control 26 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Type Circuit Remarks E P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output Pch transistor is always off Digital output R Pull-up resistor control Digital input Standby mode Control F P-ch P-ch N-ch R Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output Pch transistor is always off Pull-up resistor control Digital input Standby mode Control Analog input Input control June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 27 D a t a S h e e t Type Circuit Remarks G P-ch N-ch CMOS level output CMOS level hysteresis input With standby control 5 V tolerant input IOH = -4 mA, IOL = 4 mA Available to control of PZR registers. Only P22, P23, P51, P52 When this pin is used as an I2C pin, the digital output Pch transistor is always off Digital output Digital output R Digital input Standby mode control H CMOS level hysteresis input Mode input I P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With standby control IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output Pch transistor is always off Digital output R Digital input Standby mode control 28 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 29 D a t a S h e e t Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. 30 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 31 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf 32 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pins. Example of Using an External Clock Device X0/PE2 (X0A/P46) Can be used as general-purpose I/O ports. X1/PE3 (X1A/P47) Set as general-purpose I/O ports. Handling when using Multi-function serial pin as I2C pin If it is using the Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 33 D a t a S h e e t C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7uF would be recommended for this series. C Device CS VSS GND Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. 34 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Block Diagram MB9AF131/132 TRSTX,TCK, TDI,TMS TDO ROM Table SWJ-DP Cortex-M3 Core I @20MHz(Max) D Multi-layer AHB (Max 20MHz) Sys AHB-APB Bridge: APB0 (Max 20MHz) NVIC Flash I/F Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) Security On-Chip Flash 64/128Kbytes SRAM1 8Kbytes CSV CLK X0 X1 X0A X1A Main Osc Sub Osc PLL Source Clock CR 4MHz CR 100kHz CROUT AVCC, AVSS,AVRH ANxx Deep Standby Ctrl WKUPx 12-bit A/D Converter Unit 0 ADTG_x A/D Activation Compare 1ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x LVD Ctrl AHB-APB Bridge : APB2 (Max 20MHz) TIOBx Power On Reset Base Timer 16-bit 8ch. / 32-bit 4ch. AHB-APB Bridge : APB1 (Max 20MHz) TIOAx C IRQ-Monitor RTCCO SUBOUT Real-Time Clock External Interrupt Controller 8-pin + NMI INTxx NMIX MD1, MD0 MODE-Ctrl GPIO Waveform Generator 3ch. 16-bit PPG 3ch. LVD Regulator Multi-Function Serial I/F 8ch. PIN-Function-Ctrl P0x, P1x, . . Pxx SCKx SINx SOTx Multi-Function Timer ×1 Memory Size See Memory size in Product Lineup to confirm the memory size. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 35 D a t a S h e e t Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved Reserved 0x4003_C000 0x4003_B000 0x4003_9000 0x4003_8000 0x4400_0000 0x4200_0000 0x4000_0000 32Mbytes Bit band alias Peripherals Reserved 0x2400_0000 0x2200_0000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 SRAM1 Reserved See "Memory map(2)" for the memory size details. 0x0010_0008 0x0010_0000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 RTC Reserved MFS Reserved LVD/DS mode Reserved GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved A/DC Reserved Base Timer PPG Reserved Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 Flash Reserved 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 SW WDT HW WDT Clock/Reset Reserved 0x4000_1000 0x4000_0000 36 CONFIDENTIAL Flash I/F MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Memory Map (2) MB9AF132KB/LB MB9AF131KB/LB 0x2008_0000 0x2008_0000 Reserved Reserved 0x2000_2000 0x2000_0000 0x2000_2000 SRAM1 8 Kbytes 0x2000_0000 Reserved Reserved 0x0010_0008 0x0010_0004 0x0010_0000 SRAM1 8 Kbytes 0x0010_0008 CR trimming Security 0x0010_0004 0x0010_0000 CR trimming Security Reserved Reserved SA2 (60 KB) 0x0000_0000 SA1 (4 KB) 0x0001_0000 SA2 (60 KB) 0x0000_0000 Flash 64 Kbytes SA3 (64 KB) Flash 128 Kbytes 0x0002_0000 SA1 (4 KB) *: See MB9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 37 D a t a S h e e t Peripheral Address Map Start address End address Bus 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_50FF Low Voltage Detector 0x4003_5100 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface AHB APB0 APB1 APB2 Peripherals Flash I/F register Reserved Software Watchdog timer Reserved Base Timer Reserved Deep stand-by mode Controller Reserved 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF Reserved 0x4006_1000 0x4006_1FFF 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved 38 CONFIDENTIAL AHB Reserved MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX = 0 This is the period when the INITX pin is the L level. INITX = 1 This is the period when the INITX pin is the H level. SPL = 0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 0. SPL = 1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Trace output Indicates that the trace function can be used. GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 39 D a t a S h e e t Pin status type List of Pin Status Function group Main crystal oscillator input pin A External main clock input selected GPIO selected B C Power-on reset or Device Run mode INITX input low voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Input enabled Setting disabled Setting disabled Hi-Z / Main crystal Internal oscillator input fixed output pin at 0 Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Input enabled Setting disabled Setting disabled Input enabled Maintain previous state Maintain previous state Timer mode, RTC mode, or Stop mode state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable INITX = 1 - Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Input enabled Input enabled Input enabled Input enabled Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stop*1, output maintain previous state / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Input enabled Hi-Z / Input enabled / When oscillation stop*1, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous state / state / state / state / state / state / Hi-Z / When When When When When When Internal oscillation oscillation oscillation oscillation oscillation oscillation input fixed stop*1, Hi-Z stop*1, Hi-Z stop*1, Hi-Z stop*1, Hi-Z stop*1, Hi-Z stop*1, Hi-Z at 0 output / output / output / output / output / output / Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed at 0 at 0 at 0 at 0 at 0 at "0" GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled 40 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 Pin status type D a t a S h e e t D Function group Power-on reset or Device Run mode INITX input low voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - F INITX = 1 SPL = 0 SPL = 1 Input enabled Input enabled Input enabled JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain previous state Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 WKUP enabled Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Resource other than above selected Hi-Z GPIO selected Resource selected H INITX = 1 SPL = 0 SPL = 1 Input enabled GPIO selected G Power supply stable Input enabled Maintain previous state GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Mode input pin E Input enabled Timer mode, RTC mode, or Stop mode state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state WKUP input enabled GPIO selected Maintain previous state Input enabled Maintain previous state GPIO selected Maintain previous state Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Power supply stable INITX = 1 - GPIO selected GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state 41 Pin status type D a t a S h e e t Function group NMIX selected I Resource other than above selected Power-on reset or Device Run mode INITX input low voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Setting disabled Hi-Z GPIO selected Analog input selected J Resource other than above selected Hi-Z Setting disabled K Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state GPIO selected 42 CONFIDENTIAL Hi-Z / Internal input fixed at 0 Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Resource other than above selected Maintain previous state Setting disabled Setting disabled Setting disabled Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Setting disabled GPIO selected Analog input selected Timer mode, RTC mode, or Stop mode state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled Power supply stable INITX = 1 - GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Maintain previous state MB9A130LB_DS706-00066-2v0-E, June 9, 2015 Pin status type D a t a S h e e t Function group Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 WKUP enabled Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled External interrupt enabled selected Maintain previous state Resource other than above selected Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 / Analog input enabled Power supply stable Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Hi-Z / Internal input fixed at 0 / Analog input enabled Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Timer mode, RTC mode, or Stop mode state Hi-Z / Internal input fixed at 0 / Analog input enabled Analog input selected L Power-on reset or Device Run mode INITX input low voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Sub crystal oscillator input pin External sub clock input selected Input enabled Setting disabled Input enabled Setting disabled Input enabled Setting disabled Input enabled Maintain previous state M GPIO selected Setting disabled Setting disabled June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Setting disabled Maintain previous state Input enabled Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Input enabled Hi-Z / Input enabled / When oscillation stop*2, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Input enabled Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Maintain previous state Input enabled Input enabled Maintain Hi-Z / Input previous enabled / state / When When oscillation Return from stop*2, Deep Hi-Z / Stand-by Internal STOP mode, input fixed GPIO at 0 selected Hi-Z / Internal input fixed at 0 Maintain previous state 43 Pin status type D a t a S h e e t Function group Timer mode, RTC mode, or Stop mode state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Power supply stable INITX = 1 - Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO/ Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled Maintain previous state Hi-Z / Input enabled Maintain previous state N O Power-on reset or Device Run mode INITX input low voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - P *1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. 44 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Electrical Characteristics 1. Absolute Maximum Ratings Parameter 1, 2 Power supply voltage* * Analog power supply voltage*1,*3 Analog reference voltage*1,*3 Symbol VCC AVCC AVRH Rating Min Max Unit Remarks VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS + 6.5 V VSS + 6.5 V VSS + 6.5 V VCC + 0.5 VSS - 0.5 V (≤ 6.5 V) Input voltage*1 VI VSS - 0.5 VSS + 6.5 V 5V tolerant AVCC + 0.5 1 Analog pin input voltage* VIA VSS - 0.5 V (≤ 6.5 V) VCC + 0.5 Output voltage*1 VO VSS - 0.5 V (≤ 6.5 V) 4 L level maximum output current* IOL 10 mA L level average output current*5 IOLAV 4 mA L level total maximum output current ∑IOL 60 mA 6 L level total average output current* ∑IOLAV 30 mA H level maximum output current*4 IOH -10 mA H level average output current*5 IOHAV -4 mA H level total maximum output current ∑IOH -60 mA H level total average output current*6 ∑IOHAV -30 mA Power consumption PD 400 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. <WARNING> Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 45 D a t a S h e e t 2. Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Power supply voltage Analog power supply voltage VCC AVCC - Analog reference voltage AVRH - CS TA Smoothing capacitor Operating Temperature FPT-48P-M49, LCC-48P-M73, FPT-64P-M38, FPT-64P-M39, LCC-64P-M24 Value Unit Min Max 1.8 1.8 2.7 AVCC 5.5 5.5 AVCC AVCC V V V - 1 10 μF - - 40 + 85 °C Remarks AVCC = VCC AVCC ≥ 2.7 V AVCC < 2.7 V For built-in Regulator * *: See C Pin in Handling Devices for the connection of the smoothing capacitor. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 46 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 3. DC Characteristics (1) Current Rating (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions PLL Run mode High-speed CR Run mode ICC Power supply current VCC Sub Run mode Low-speed CR Run mode ICCS PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU: 20 MHz, Peripheral: clock stopped, NOP operation CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 Value Unit Remarks Typ*3 Max*4 20 25 mA *1, *5 10 15 mA *1, *5 4.5 5 mA *1 0.25 0.35 mA *1, *6 0.3 0.45 mA *1 Peripheral: 20 MHz 9 13 mA *1, *5 Peripheral: 4 MHz*2 2 2.5 mA *1 Peripheral: 32 kHz 0.1 0.2 mA *1, *6 Peripheral: 100 kHz 0.2 0.35 mA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 47 D a t a S h e e t Parameter Symbol Pin name Conditions Main Timer mode ICCT Sub Timer mode ICCR Power supply current RTC mode VCC ICCH ICCRD ICCHD Stop mode Deep Standby RTC mode Deep Standby Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off Value Unit Remarks Typ*2 Max*3 1 3.6 mA *1, *4 1.7 3.9 mA *1, *4 8.5 70 μA *1, *5 18 170 μA *1, *5 1.8 7.5 μA *1, *5 7 62 μA *1, *5 0.7 7 μA *1 6 60 μA *1 1.6 3 μA *1, *5 3.6 14.5 μA *1, *5 0.5 2.5 μA *1 2.5 12.5 μA *1 *1: When all ports are fixed. *2: VCC=3.3 V *3: VCC=5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) 48 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t ・ Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Low-voltage detection circuit (LVD) power supply current ICCLVD Value Typ* Max Pin name Conditions VCC For occurrence of reset or for occurrence of interrupt in normal mode operation For occurrence of reset and for occurrence of interrupt in normal mode operation For occurrence of interrupt in low-power mode operation 10 20 Unit Remarks μA When not detected 14 30 μA 0.3 2 μA When not detected *: When VCC=3.3 V ・ Flash Memory Current (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Flash memory write/erase current ICCFLASH VCC Conditions At Write/Erase Value Typ Max Unit 10.8 mA 11.9 Remarks ・ A/D Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Power supply current Reference power supply current Symbol Pin name ICCAD AVCC ICCAVRH AVRH June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Conditions At 1unit operation At stop At 1unit operation AVRH=5.5 V At stop Value Typ Max Unit 1.4 2.5 mA 0.1 0.35 μA 0.8 1.5 mA 0.1 0.3 μA Remarks 49 D a t a S h e e t (2) Pin Characteristics (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name H level input voltage (hysteresis input) L level input voltage (hysteresis input) VIHS VILS MD0, MD1, PE0, PE2, PE3, P46, P47, INITX P21, P22, P23, P50, P51, P52, P80, P81, P82 CMOS hysteresis input pins other than the above MD0, MD1, PE0, PE2, PE3, P46, P47, INITX CMOS hysteresis input pins other than the above H level output voltage VOH L level output voltage VOL Pxx IIL - RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Input leak current Pull-up resistance value Input capacitance 50 CONFIDENTIAL Pxx Conditions Min Value Typ Max Unit - VCC × 0.8 - VCC + 0.3 V - VCC× 0.7 - VSS + 5.5 V - VCC × 0.7 - VCC + 0.3 V - VSS 0.3 - VCC× 0.2 V - VSS 0.3 - VCC× 0.3 V - VCC - VCC VCC ≥ 4.5 V IOH = - 4 mA VCC < 4.5 V IOH = - 1 mA VCC ≥ 4.5 V IOL = 4 mA VCC < 4.5 V IOL = 2 mA VCC 0.5 VCC 0.5 VSS - 0.4 V - -5 - +5 μA VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 40 100 400 - - 5 15 Remarks 5V tolerant V kΩ pF MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 4. AC Characteristics (1) Main Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Input frequency fCH Input clock cycle tCYLH Input clock pulse width Input clock rise time and fall time Internal operating clock*1 frequency Internal operating clock*1 cycle time Value Min Max Unit VCC ≥ 2.0 V VCC < 2.0 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH 4 4 4 4 50 62.5 20 4 20 16 250 250 MHz MHz MHz MHz ns ns 45 55 % - - 5 ns Pin Conditions name X0, X1 tCF, tCR Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock fCM - - - 20 MHz Master clock fCC - - - 20 MHz Base clock (HCLK/FCLK) fCP0 - - - 20 MHz APB0 bus clock*2 fCP1 - - - 20 MHz APB1 bus clock*2 fCP2 - - - 20 MHz APB2 bus clock*2 tCYCC - - 50 - ns Base clock (HCLK/FCLK) tCYCP0 - - 50 - ns APB0 bus clock*2 tCYCP1 - - 50 - ns APB1 bus clock*2 tCYCP2 - - 50 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 51 D a t a S h e e t (2) Sub Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input frequency Symbol Min Value Typ Max - - 32.768 - kHz - 32 - 100 kHz Pin Conditions name Unit fCL X0A, X1A Input clock cycle tCYLL - 10 - 31.25 μs Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock X0A (3) Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol TA = + 25°C TA = - 40°C to + 85°C TA = - 40°C to + 85°C TA = + 25°C TA = - 40°C to + 85°C TA = - 40°C to + 85°C VCC ≥ 2.2 V Clock frequency Value Unit Min Typ Max Conditions fCRH VCC < 2.2 V 3.92 4 4.08 3.8 4 4.2 2.3 - 7.03 3.4 4 4.6 3.16 4 4.84 2.3 - 7.03 Remarks When trimming*1 MHz When not trimming When trimming*1 MHz When not trimming Frequency tCRWT 10 μs *2 stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Clock frequency 52 CONFIDENTIAL Symbol Conditions fCRL - Min Value Typ Max 50 100 150 Unit Remarks kHz MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 μs (LOCK UP time) PLL input clock frequency fPLLI 4 20 MHz PLL multiplication rate 1 5 multiplier PLL macro oscillation clock frequency fPLLO 10 20 MHz Main PLL clock frequency*2 fCLKPLL 20 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. (4-2) Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 μs (LOCK UP time) PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate 3 4 multiplier PLL macro oscillation clock frequency fPLLO 11.4 16.8 MHz Main PLL clock frequency*2 fCLKPLL 16.8 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 53 D a t a S h e e t (5) Reset Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Reset input time tINITX Pin Conditions name INITX - Value Unit Min Max 500 - ns 1.5 - ms 1.5 - ms Remarks When RTC mode or Stop mode When Deep Standby mode (6) Power-on Reset Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Power supply rising time Power supply shut down time Reset release voltage Reset detection voltage Time until releasing Power-on reset Reset detection delay time Symbol Pin name dV/dt Min Value Typ Max 0.1 - - V/ms Unit Remarks tOFF 1 - - ms VDETH 1.44 1.60 1.76 V When voltage rises 1.39 1.55 1.71 V When voltage drops tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs VDETL VCC VDETH VDETL VCC dV 0.2V dt 0.2V tOFF tPRT Internal reset CPU Operation 54 CONFIDENTIAL Reset active tOFFD Release Reset active start MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t (7) Base Timer Input Timing Timer input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input pulse width Symbol Pin name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK,TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK TIN VIHS VIHS VILS VILS Trigger input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 55 D a t a S h e e t (8) CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Serial clock cycle time SCK ↓ → SOT delay time SIN → SCK ↑ setup time SCK ↑ → SIN hold time Serial clock L pulse width Serial clock H pulse width SCK ↓ → SOT delay time SIN → SCK ↑ setup time SCK ↑ → SIN hold time SCK falling time SCK rising time *1 When PZR=0. *2 When PZR=1. Notes: CONFIDENTIAL tSCYC tSLOVI tIVSHI tSHIXI SCKx SCKx, SOTx Master mode SCKx, SINx SCKx, SINx tSLSH SCKx tSHSL SCKx tSLOVE tIVSHE tSHIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 2.7 V 2.7 V ≤ VCC < 4.5 V Min Max Min Max 4tCYCP - 4tCYCP -40 +40 75 0 2tCYCP - 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - 75 - 50 - 30*1 40*2 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. 56 Pin Symbol Conditions name About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK VIH VIH VIL tR SOT tSLSH tF VIL VIL tSHOVE VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 57 D a t a S h e e t CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Serial clock cycle time SCK ↑ → SOT delay time SIN → SCK ↓ setup time SCK ↓ → SIN hold time Serial clock L pulse width Serial clock H pulse width SCK ↑ → SOT delay time SIN → SCK ↓ setup time SCK ↓ → SIN hold time SCK falling time SCK rising time *1 When PZR=0. *2 When PZR=1. Notes: CONFIDENTIAL tSCYC tSHOVI tIVSLI tSLIXI VCC < 2.7 V Min Max SCKx 4tCYCP - 4tCYCP -40 +40 75 0 SCKx, SOTx Master mode SCKx, SINx SCKx, SINx tSLSH SCKx tSHSL SCKx tSHOVE tIVSLE tSLIXE tF tR 2.7 V ≤ VCC < 4.5 V Min Max Pin Conditions name SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP - 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - 75 - 50 - 30*1 40*2 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. 58 Symbol About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK VIH VIH VIL tR SOT tSLSH tF VIL VIL tSHOVE VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 59 D a t a S h e e t CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Serial clock cycle time SCK ↑ → SOT delay time SIN → SCK ↓ setup time SCK ↓ → SIN hold time SOT → SCK ↓ delay time Serial clock L pulse width Serial clock H pulse width SCK ↑ → SOT delay time SIN → SCK ↓ setup time SCK ↓ → SIN hold time SCK falling time SCK rising time *1 When PZR=0. *2 When PZR=1. Notes: CONFIDENTIAL tSCYC tSHOVI tIVSLI tSLIXI tSOVLI VCC < 2.7 V Min Max SCKx 4tCYCP - 4tCYCP -40 +40 75 0 SCKx, SOTx SCKx, Master mode SINx SCKx, SINx SCKx, SOTx tSLSH SCKx tSHSL SCKx tSHOVE tIVSLE tSLIXE tF tR 2.7 V ≤ VCC < 4.5 V Min Max Pin Conditions name SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - ns - 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 - 75 - 50 - 30*1 40*2 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. 60 Symbol About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t tSCYC VOH SCK VOL tSOVLI SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL Master mode tSLSH VIH SCK SOT VIL VIL tF * VOH VOL tR tIVSLE SIN tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 61 D a t a S h e e t CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin Conditions name VCC < 2.7 V Min Max 2.7 V ≤ VCC < 4.5 V Min Max VCC ≥ 4.5 V Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns 75 - 50 - 30 - ns 0 - 0 - 0 - ns - ns - ns - ns SIN → SCK ↑ setup time SCK ↑ → SIN hold time SOT → SCK ↑ delay time Serial clock L pulse width Serial clock H pulse width SCK ↓ → SOT delay time SIN → SCK ↑ setup time SCK ↑ → SIN hold time SCK falling time SCK rising time *1 When PZR=0. *2 When PZR=1. Notes: CONFIDENTIAL tSHIXI tSOVHI SCKx, Master mode SINx SCKx, SINx SCKx, SOTx tSLSH SCKx tSHSL SCKx tSLOVE tIVSHE tSHIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 30 2tCYCP - 10 tCYCP + 10 - 75 - 50 - 30*1 40*2 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. 62 tIVSHI About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL Master mode tR SCK tF tSHSL VIH VIH VIL tSLSH VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR CL = 50 pF Min Max tCYCP + 10 tCYCP + 10 - 5 5 Unit Remarks ns ns ns ns tF tR t t SHSL SCK V IL June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Value Symbol Conditions V IH SLSH V IH V IL VIL V IH 63 D a t a S h e e t (9) External Input Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max ADTG - 2tCYCP*1 - ns ICxx DTTIxX INTxx, NMIX *2 *3 2tCYCP*1 2tCYCP + 100*1 500 - ns ns ns WKUPx *4 500 - ns FRCKx Input pulse width tINH, tINL Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform generator External interrupt NMI Deep Standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which A/D converter, Multi-function Timer, External interrupt, Deep Standby mode Controller is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode. 64 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 2 (10) I C Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Standard-mode Symbol Conditions Min Max Fast-mode Unit Remarks Min Max SCL clock frequency fSCL 0 100 0 400 kHz (Repeated) START condition hold time tHDSTA 4.0 0.6 μs SDA ↓ → SCL ↓ SCL clock L width tLOW 4.7 1.3 μs SCL clock H width tHIGH 4.0 0.6 μs (Repeated) START condition setup time tSUSTA 4.7 0.6 μs CL = 50 pF, SCL ↑ → SDA ↓ R= Data hold time 1 tHDDAT (VP/IOL)* 0 3.45*2 0 0.9*3 μs SCL ↓ → SDA ↓ ↑ Data setup time tSUDAT 250 100 ns SDA ↓ ↑ → SCL ↑ STOP condition setup time tSUSTO 4.0 0.6 μs SCL ↑ → SDA ↑ Bus free time between STOP condition and tBUF 4.7 1.3 μs START condition Noise filter tSP 2 tCYCP*4 2 tCYCP*4 ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 65 D a t a S h e e t (11) JTAG Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V tJTAGH VCC < 4.5 V VCC ≥ 4.5 V TCK, TDO delay time tJTAGD 2.7 V ≤ VCC < 4.5 V TDO VCC < 2.7 V Note: When the external load capacitance CL = 50 pF. TMS,TDI setup time TMS,TDI hold time tJTAGS TCK, TMS,TDI TCK, TMS,TDI Value Min Max Unit 15 - ns 15 - ns - 30 45 60 ns Remarks TCK TMS/TDI TDO 66 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 5. 12-bit A/D Converter Electrical characteristics for the A/D converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Symbol Pin name - - Integral Nonlinearity INL - Differential Nonlinearity DNL - Zero transition voltage Full-scale transition voltage VZT VFST ANxx ANxx Conversion time*1 - - Sampling time*2 tS - tCCK - Parameter Resolution Compare clock cycle*3 Min Value Typ Max Unit 1.0 4.0 0.3 1.2 50 200 - 12 ± 3.0 ± 5.0 ± 1.9 ± 2.9 ± 20 AVRH ± 20 bit LSB LSB LSB LSB mV mV - - μs - 10 μs - 1000 ns Period of operation enable state transitions Analog input capacity tSTT - - - 1 μs CAIN - - - pF Analog input resistor RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 15 0.9 1.6 4.0 4 LSB - ANxx - - 0.3 μA - ANxx kΩ Remarks AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 4.5 V 2.7 V ≤ AVCC < 4.5 V AVCC < 2.7 V AVSS AVRH V 2.7 AVCC ≥ 2.7 V Reference voltage AVRH AVCC V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 67 D a t a S h e e t ANxx Analog input pin Analog signal source Rext Comparator RAIN CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: RAIN: CAIN: REXT: Sampling time Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: tCCK: 68 CONFIDENTIAL Compare time Compare clock cycle MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Definition of 12-bit A/D Converter Terms Resolution: Integral Nonlinearity: Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Actual conversion characteristics Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVSS Actual conversion characteristics AVRH AVSS Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL AVRH Analog input 69 D a t a S h e e t 6. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Parameter Symbol Detected voltage Released voltage Detected voltage Released voltage VDLR VDHR VDLR VDHR LVD stabilization wait time tLVDRW Conditions SVHR = 0001 SVHR = 0100 - Detection delay time tLVDRD dV/dt ≥ -4mV/µs *: tCYCP indicates the APB2 bus clock cycle time. 70 CONFIDENTIAL Min Value Typ Max 1.43 1.53 1.80 1.90 1.53 1.63 1.93 2.03 - Unit Remarks 1.63 1.73 2.06 2.16 V V V V When voltage drops When voltage rises When voltage drops When voltage rises - 633 × tCYCP * μs - 60 μs MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t (2) Interrupt of Low-voltage Detection Normal mode (TA = - 40°C to + 85°C) Parameter Symbol Conditions Min Value Typ Max 1.87 1.97 1.96 2.06 2.05 2.15 2.15 2.25 2.24 2.34 2.33 2.43 2.43 2.53 2.61 2.71 2.80 2.90 2.99 3.09 3.36 3.46 3.45 3.55 3.73 3.83 3.83 3.93 3.92 4.02 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 2.13 2.23 2.24 2.34 2.35 2.45 2.45 2.55 2.56 2.66 2.67 2.77 2.77 2.87 2.99 3.09 3.20 3.30 3.41 3.51 3.84 3.94 3.95 4.05 4.27 4.37 4.37 4.47 4.48 4.58 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI LVD stabilization wait time tLVDIW - - - 633 × tCYCP* μs Detection delay time tLVDID dV/dt ≥ -4mV/µs - - 60 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 71 D a t a S h e e t Low power mode (TA = - 40°C to + 85°C) Parameter Symbol Conditions Min Value Typ Max 1.80 1.90 1.89 1.99 1.98 2.08 2.07 2.17 2.16 2.26 2.25 2.35 2.34 2.44 2.52 2.62 2.70 2.80 2.88 2.98 3.24 3.34 3.33 3.43 3.60 3.70 3.69 3.79 3.78 3.88 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 2.20 2.30 2.31 2.41 2.42 2.52 2.53 2.63 2.64 2.74 2.75 2.85 2.86 2.96 3.08 3.18 3.30 3.40 3.52 3.62 3.96 4.06 4.07 4.17 4.40 4.50 4.51 4.61 4.62 4.72 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL LVD stabilization wait time tLVDILW - - - 8039 × tCYCP * μs Detection delay time tLVDILD dV/dt ≥ -0.4mV/μs - - 800 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. 72 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 7. Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 2.0V to 5.5V, TA = - 40°C to + 85°C) Parameter Large Sector Sector erase time Small Sector Half word (16-bit) write time Value Typ* Max* 1.6 0.4 7.5 2.1 Unit Remarks Includes write time prior to internal erase Not including system-level overhead 25 400 μs time. Includes write time prior to internal Chip erase time 4 19.2 s erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. s (2) Write cycles and data hold time Erase/write cycles (cycle) 1,000 10,000 100,000 *: At average + 85C June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL Data hold time (year) Remarks 20* 10* 5* 73 D a t a S h e e t 8. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Max* Low-speed CR Timer mode tICNT Unit 40 80 μs 630 1260 μs 630 1260 μs 2100 μs 2127 μs RTC mode, 1083 Stop mode Deep Standby RTC mode 1099 Deep Standby Stop mode *: The maximum value depends on the accuracy of built-in CR. Remarks μs tCYCC Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Sub Timer mode Value Typ Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. 74 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 75 D a t a S h e e t (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Typ Max* 359 647 μs 359 647 μs 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs 2127 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Deep Standby RTC mode 1099 Deep Standby Stop mode *: The maximum value depends on the accuracy of built-in CR. Remarks Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation 76 CONFIDENTIAL Start MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. The internal resource reset means the watchdog reset and the CSV reset. June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 77 D a t a S h e e t Ordering Information On-chip Flash memory On-chip SRAM MB9AF131KBPMC-G-SNE2 64 Kbyte 8 Kbyte MB9AF132KBPMC-G-SNE2 128 Kbyte 8 Kbyte MB9AF131KBQN-G-AVE2 64 Kbyte 8 Kbyte MB9AF132KBQN-G-AVE2 128 Kbyte 8 Kbyte MB9AF131LBPMC1-G-SNE2 64 Kbyte 8 Kbyte MB9AF132LBPMC1-G-SNE2 128 Kbyte 8 Kbyte MB9AF131LBPMC-G-SNE2 64 Kbyte 8 Kbyte MB9AF132LBPMC-G-SNE2 128 Kbyte 8 Kbyte MB9AF131LBQN-G-AVE2 64 Kbyte 8 Kbyte MB9AF132LBQN-G-AVE2 128 Kbyte 8 Kbyte Part number 78 CONFIDENTIAL Package Packing Plastic LQFP (0.5mm pitch), 48-pin (FPT-48P-M49) Plastic QFN (0.5mm pitch), 48-pin (LCC-48P-M73) Plastic LQFP (0.5mm pitch), 64-pin (FPT-64P-M38) Tray Plastic LQFP (0.65mm pitch), 64-pin (FPT-64P-M39) Plastic QFN (0.5mm pitch), 64-pin (LCC-64P-M24) MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t Package Dimensions 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00 ± 0.20(.354 ± .008)SQ *7.00± 0.10(.276 ± .004)SQ 36 0.145± 0.055 (.006 ± .002) 25 37 24 0.08(.003) 48 13 "A" 1 C 0°~8° 0.10 ± 0.10 (.004 ± .004) (Stand off) 12 0.22 ± 0.05 (.008 ± .002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 INDEX 0.50(.020) Details of "A" part 0.25(.010) M 0.60 ± 0.15 (.024 ± .006) Dimensions in mm (inches). Note: The values in parentheses are reference values. 79 D a t a S h e e t 48-pin plastic QFN Lead pitch 0.5 mm Package width × package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight – (LCC-48P-M73) 48-pin plastic QFN (LCC-48P-M73) 7.00±0.10 (.276±.004) 5.50±0.10 (.217±.004) 7.00±0.10 (.276±.004) 0.25±0.05 (.010±.002) 5.50±0.10 (.217±.004) INDEX AREA 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) 0.05 (.002) MAX C CONFIDENTIAL 0.40±0.05 (.016±.002) (0.20(.008)) 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC48-73Sc-2-1 80 0.50 (.020) (TYP) Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145 ± 0.055 (.006 ± .002) 33 49 Details of "A" part 32 0.08(.003) +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° INDEX 64 17 1 0.22±0.05 (.009±.002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 81 D a t a S h e e t 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-64P-M39) 64-pin plastic LQFP (FPT-64P-M39) Note 1) Pins width and pins thickness include plating thickness. 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.006±.002) 33 Details of "A" part 32 49 +0.20 1.50 –0.10 +.008 .059 –.004 0.10(.004) INDEX 1 16 0.65(.026) C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 17 64 0.32±0.05 (.013±.002) CONFIDENTIAL 0.10±0.10 (.004±.004) 0.25(.010)BSC "A" 0.13(.005) M 2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2 82 0~8˚ Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t 64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight - (LCC-64P-M24) 64-pin plastic QFN (LCC-64P-M24) 9.00 ± 0.10 (.354 ±. 004) 6.00 ± 0.10 (.236 ±. 004) 9.00 ± 0.10 (.354 ±. 004) 0.25 ± 0.05 (.010 ±. 002) 6.00 ± 0.10 (.236 ±. 004) INDEX AREA 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85 ± 0.05 (.033 ±. 002) 0.05 (.002) MAX C 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1 June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 0.50 (.020) (TYP) 0.40 ± 0.05 (.016 ±. 002) (0.20 (.008)) Dimensions in mm (inches). Note: The values in parentheses are reference values. 83 D a t a S h e e t Major Changes Page Section Revision 1.0 Revision 2.0 Features 2 · On-chip Memories 33 Handling Devices Handling Devices 33 Crystal oscillator circuit Memory Map 37 · Memory map(2) 47 - 49 53 54 56 - 63 67 70 73 74 - 77 78 84 CONFIDENTIAL Electrical Characteristics 3. DC Characteristics (1) Current rating Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing Electrical Characteristics 5. 12bit A/D Converter Electrical Characteristics 7. Low-voltage Detection Characteristics Electrical Characteristics 8. Flash Memory Write/Erase Characteristics Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Ordering Information Change Results Initial release Changed the description of on-chip SRAM Added "· Stabilizing power supply voltage" Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." Added the summary of Flash memory sector · Changed the table format · Added Timer mode current · Added Flash Memory Current · Moved A/D Converter Current · Added the figure of Main PLL connection · Changed the figure of timing · Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVCC < 2.7 V Deleted the figure Change to the erase time of include write time prior to internal erase Added Return Time from Low-Power Consumption Mode Changed notation of part number MB9A130LB_DS706-00066-2v0-E, June 9, 2015 D a t a S h e e t June 9, 2015, MB9A130LB_DS706-00066-2v0-E CONFIDENTIAL 85 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2014-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 86 CONFIDENTIAL MB9A130LB_DS706-00066-2v0-E, June 9, 2015