7.9MB

MB9DF126
MB9DF126B
MB9DF126 Series Data Sheet
Cortex R4 Family
Cypress Cortex R4 Family
CMOS
MB9DF126 Series
MB9DF126, MB9DF126B
DESCRIPTION
MB9DF126 series is based on Cypress’s advanced ARM architecture (32-bit with instruction pipeline for RISClike performance). Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 128MHz operation frequency from an external resonator.
Note: ARM, Cortex, Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries.
Note: APIX ® is a registered mark of INOVA Semiconductors GmbH.
TM
Cypress Semiconductor Corporation
Document Number: DS707-00002-4v1-E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 4, 2015
MB9DF126
MB9DF126B
■ REVISION HISTORY
Version
Date
Remark
0.01
2010-08-12
Initial draft
0.02
2010-08-24
Updated according to latest short spec
0.03
2011-01-27
Updated Overview, Memory Map, Package and Pin Assignment, Interrupt/
DMA chapter with relavent information. Removed Recommended settings
chapter.
0.04
2011-02-01
Updated Electrical characteristics chapter and modfied the document footer.
0.05
2011-02-04
Updated Block diagram with CRC, Overview, Table 2-1, Table 3-2, Table
4-1, Table 4-3, Table 6-1, Table 6-3, Figure 6-3, Table 6-4, Table 6-5, Table
6-9, Table 6-11, Table 6-14, Figure 6-8.
Renamed Pnn_m to Pi_jj.
0.06
2011-02-15
Updated Document code.
Updated Figure 3-2, Table 3-1, and Section 3.3.2
0.07
2011-03-10
Updated QFP-296 diagram, QFP-296 Package pinout table, Pin circuit type
of QFP-296, I/O circuit types.
1.00
2011-03-18
Updated IO_MAP.
1.01
2011-03-31
Updated Table 6-5 with PLL information and modified Table2-2.
1.02
2011-04-06
Updated Section I/O Pins and their functions and I/O Pin Types.
1.03
2011-05-04
Added RICFG information in Section 3.2.2. Added Procudures chapter. Renamed EEFLASH in Memory and Config(MEMORY_CONFIG)AHB Bus
Memory Map
1.04
2011-05-13
Renamed APIX power supply pins in QFP-296 Package diagram and QFP296 Package pinout table.
1.05
2011-05-27
Added Section Master ID.
1.06
2012-05-04
Added Input Level Description and Drive Strenght Information. Corrected
IO circuit diagrams, ID value and reference supply in DC characrteristics.
Added current consumption values
1.07
2012-07-02
Added handling devices, ordering information, flash programming times.
1.08
2012-07-10
Added RC Oscillator Frequency, modified Characteristics to match evaluation results. DMA channel registers limited to 8.
2.0
2012-08-21
No longer preliminary revision
2.1
2012-12-13
Trademark note added, Support note removed, package information updated, std version for Warning, back cover changed, boundary scan chapter
updated, new HSSPI timing, ADC reference values
Document Number: DS707-00002-4v1-E
Page ii
MB9DF126
MB9DF126B
Version
2.2
Date
2013-02-08
Remark
Corrected TC-Flash ID in table 2-14: List of Module ID
Updated IO circuit type JTAGO and SDIN/SDOUT/RREF in table 3-3
Changed item name of table 4-3 Modules with DMA
Corrected reset value of PPC_PCFGR040 ~ PPC_PCFGR123 in table 5-6
memory layout for the PERI0_RBUS registers
Updated pin, condition, value and remarks of DC characteristics in table 6-3
Extended 7.1 Boundary Scan chapter.
Updated 8.4 Power on sequence
Added 8.5 Pin State while Power-On-Reset
Added MB9DF126BPMC-GSE2 to 9.Ordering Information
2.3
2013-06-19
Specified APIX leakage current of ICCPSS in table 6-3
Changed condition of ICCPSS for PD2 and PD3 in table 6-3
2.4
2013-06-28
Corrected condition of ICCPSS for PD2 and PD3 in table 6-3 back to
version 2v1
3.0
2013-07-01
Added figure 3-2: Package Dimensions QFP-296
Corrected order information in chapter 9. by updating partnumber for QFP296 variant and removing unnecessary "*1" marks from part number
4.0
2014-01-31
corrected number of MPU channels from 8 to 12, corrected name of
QFP176 package pin 127 from VSS5 to VSS, extented remark for PD1 run
mode current, removed precondition from flash program/erase cycle and
data retention time, corrected HTM trace sources with ID2, corrected partnumber for QFP-296
4.1
2015-10-28
Updated electrical specifications per PCN: 2901.
DC Characteristics, Power supply current in PSS mode
DC Characteristics, Power supply current in Timer mode
In addition, updated document from Fujitsu look and feel to Cypress.
Cosmetic changes only.
Document Number: DS707-00002-4v1-E
Page iii
MB9DF126
MB9DF126B
TABLE OF CONTENTS
1 Overview
1.1 Block diagram
1.2 Power Domains
2 Feature list
2.1
2.2
2.3
2.4
2.5
2.6
Overview
Features
Memory Map
Resource distribution for non-modulated clock
Lock/unlock values for protection units
ID-Values for Module Identification Registers
3 Package and Pin Assignment
3.1 Package
3.1.1 QFP-296 Package
3.1.2 QFP-176 Package
3.1.3 IO Circuit Types
3.2 I/O Pins and their functions
3.2.1 Port Pin Multiplexing table
3.2.2 Resource input source table
3.2.2.1
RICFG0_ADC
3.2.2.2
RICFG0
3.2.2.3
RICFG1
3.2.2.4
RICFG3
3.2.2.5
RICFG4
3.2.2.6
RICFG7
3.2.2.7
RICFG8
4 Interrupt / DMA
4.1
4.2
4.3
4.4
4.5
Interrupt table
NMI
DMA Overview
PPU
Master ID
5 I/O map
6 Electrical characteristics
6.1
6.2
6.3
6.4
Absolute Maximum Ratings
Recommended operating conditions
DC Characteristics
AC Characteristics
Document Number: DS707-00002-4v1-E
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87
88
95
96
97
342
342
346
347
356
Page iii
MB9DF126
MB9DF126B
6.4.1 Source Clock timing
6.4.2 Internal Clock timing
6.4.3 External Reset timing
6.4.4 External Input timing
6.4.5 Slew Rate High Current Outputs
6.4.6 USART timing
6.4.7 I2C timing
6.4.8 HSSPI timing
6.4.9 SPI timing
6.4.10 External Bus Interface timing
6.5 Analog Digital Converter
6.6 FLASH memory program/erase characteristics
6.7 RC Oscillator Frequency
7 Procedures
7.1 Boundary scan
7.2 Flash Parallel Programming
7.2.1 Memory Map
7.2.1.1
Address Space & Memory Cell Select Address Assignment
7.2.1.2
LIMITATION ON MB9DF126 DEVICE
7.2.1.3
Input Data Table
7.2.2 Flash macro selection and address mapping in FPP
7.2.3 Flash Power On Sequence
7.3 Debug and Trace
8 Handling Devices
8.1 Preventing Latch-up
8.2 Handling of unused input pins
8.3 Power supply pins
8.4 Power on sequence
8.5 Pin State while Power-On-Reset
8.6 Crystal oscillator circuit
8.7 Notes on using external clock
8.7.1 Opposite phase clock supply: Oscillation Mode
8.7.2 Single phase clock supply
8.7.3 Single phase clock supply: Fast Clock Input Mode
8.8 Unused sub clock signal
9 Ordering Information
Document Number: DS707-00002-4v1-E
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359
360
361
362
365
367
370
375
382
386
387
389
389
392
399
399
400
400
402
404
407
411
411
411
411
411
412
413
413
413
414
414
414
415
Page iv
SYSC_CKOT
SYSC_CKOTX
SYSC
Power Control
IRQ Control
TPU
PERI3_eRBUS
PPU
GPIO
(141 pins)
UDC
(1 ch)
RLT
(10 ch)
Peripheral Bus
Bridge 3
CLK_HPM_PD2
CLK_CFG_PD1
CLK_PERI3_PD2
Memories
CRC
GPIO0_00o˘GPIO0_52o
GPIO0_62o,GPIO0_63o
GPIO1_00o˘GPIO1_59o
GPIO2_00o˘GPIO2_25o
GPIO0_00i˘... GPIO0_52i
GPIO0_62i,GPIO0_63i
GPIO1_00i˘...GPIO1_59i
GPIO2_00i˘... GPIO2_25i
TCMRAM
128K
A−Shell 0
A−Shell 1
Remote
Handler
I2S
(2 ch)
SPI
(3 ch)
DMA
(8 ch)
USART6_SCKi
USART6_SIN
USART6_SCKo
USART6_SOT
APIX PHY
R
SDOUTM/SDOUTP
SDINM/SDINP
ARH0_AIC0_UPCLK
ARH0_AIC0_UPDATA0
ARH0_AIC0_UPDATA1
PPG_ETRG0˘.. PPG_ETRG3
ARH0−AIC0_TDA0
PPGA
ARH0−AIC0_TDA1
PPGB
ARH0−AIC1_TDA0
ARH0−AIC1_TDA1
ARH0−AIC0_dbg_out_0, ARH0−AIC1_dbg_out_0
ARH0−AIC0_dbg_out_1, ARH0−AIC1_dbg_out_1
16−bit PPG
(8 ch)
I/O Timer
(4 ch)
FRT 16/17/18/19
ICU 18/19
OCU 16/17
USART
(1 ch)
CANn_RX
CANn_TX
SG
(1 ch)
CLK_HPM_PD2
CLK_SYS_PD3
D−Cache
8K
I−Cache
8K
PPG_ETRG0˘.. PPG_ETRG3
PPGn_PPGA
PPGn_PPGB
SMCn_M1
SMCn_P1
SMCn_M2
SMCn_P2
SMC
(6 ch)
USART0_SCKi
USART0_SIN
USART0_SCKo
USART0_SOT
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
I2C0_SCLi
I2C0_SDAi
I2C0_SCLo
I2C0_SDAo
16−bit PPG
(16 ch)
X0
X1
MODE
X0A
X1A
RSTX
AVDD5
AVSS5
AVRH
ADC0_AN0..... ADC0_AN31
ADC0_EDGI
CSV/CLK−out
PLL’s
Oscillators
Clock group
I2C
(1 ch)
USART
(1 ch)
I/O Timer
(4 ch)
FRT 0/1/2/3
ICU 2/3
OCU 0/1
(50 ch)
10−bit ADC
Peripheral Bus
Bridge 0
PERI5_AHB BUS
MPU
12 ch
Cortex R4
DBG0_CTL
DBG0_CLK
DBG0_TRACE0.... DBG0_TRACE7
Peripheral Bus
Bridge 1
CAN
(3 ch)
SG_SGA
SG_SGO
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
AIC0_dbg−select
ARH0−AIC0_RCK
ARH0_AIC0_RDA0
ARH0_AIC0_RDA1
ARH0_AIC0_TCKI
I2Sn_SDo
I2Sn_WSo
I2Sn_SCKo
I2Sn_ECLK
I2Sn_SCKi
I2Sn_SDi
I2Sn_WSi
SPIn_CLKo
SPIn_DATA[0]o˘. SPIn_DATA[3]o
SPIn_SSo
SPIn_SSO[1]˘. SPIn_SSO[3]
SPIn_CLKi
SPIn_DATA0i˘. SPIn_DATA3i
SPIn_SSi
CLK_HPM_PD2
Trace
CLK_TRACE_PD2
On−chip
Debug
CLK_DBG_PD2
CLK_DMA_PD2
High Performance Matrix (HPM)
EBI
EBI0_MDATA00o...EBI0_MDATA15o
EBI0_MAD00...EBI0_MAD23
EBI0_MDQM0, EBI0_MDQM1
EBI0_MWEX
EBI0_MOEX
EBI0_MCLK
EBI0_MCASX
EBI0_MRASX
EBI0_MDWEX
EBI0_MCKE
EBI0_MNALE
EBI0_MNCLE
EBI0_MNWEX
EBI0_MNREX
EBI0_MCSX0...EBI0_MCSX3
EBI0_MCSX8
DMA0_DEOP_ACK0, DMA0_DEOP_ACK1
DMA0_DREQ0, DMA0_DREQ1
DMA0_DSTP0, DMA0_DSTP1
DMA0_DREQ_ACK0, DMA0_DREQ_ACK1
DMA0_DSTP_ACK0, DMA0_DSTP_ACK1
DMA0_DEOP0, DMA0_DEOP1
SRAM
64K
CLK_HPM_PD2
TCFlash
2M
CLK_MEM_E_PD3
CLK_HPM_PD2
ECC
Peripheral Bus
Bridge 4
BootROM
8K
RetRAM
16K
CLK_CFG_PD4
CLK_MEM_E_PD3
EEFlash
64K option
UDC0_AIN0, UDC0_AIN1
UDC0_BIN0, UDC0_BIN1
UDC0_ZIN0, UDC0_ZIN1
UDC0_UDOT0
UDC0_UDOT1
RLTn_TIN
RLTn_TOUT
Memory
Map
HS−SPI
(1 ch)
RTC_WOT
RTC
Watchdog
EIC0_NMI
EIC
PERI4_SLAVE AHB BUS
NMI
CLK_PERI4_PD2
EBI0_MDATA00i......EBI0_MDATA15i
EBI0_RDY
PERI1_RBUS
EIC0_INT00.... EIC0_INT31
CLK_PERI1_PD2
Document Number: DS707-00002-4v1-E
PERI0_RBUS
1.1
CLK_PERI0_PD2
Controlgroup
MB9DF126
MB9DF126B
1 Overview
Block diagram
Page 1
MB9DF126
MB9DF126B
1.2
Power Domains
Power
Domain
Modules
PD1
Clockgroup (Osc, PLL, CSV), Controlgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ
Control, Power Control)
PD2
Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG,
CAN, USART, FRT, ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, ARH, APIX, I2S), On-Chip Debug, Trace, SRAM, CRC
PD3
Cortex R4, MPU, I-Cache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI,
EBI
PD4
RetRAM
Document Number: DS707-00002-4v1-E
Page 2
MB9DF126
MB9DF126B
2 Feature list
2.1
Overview
Feature
MB9DF126 / QFP-176
MB9DF126 / QFP-296
Max. Core frequency
128 MHz
128 MHz
DMA
8 channels
8 channels
TCFlash
2 MB
2 MB
EEFlash
64 KB
64 KB
AXI RAM (with ECC)
64 KB
64 KB
TCM RAM (with ECC)
128 KB
128 KB
RetRAM
16 KB
16 KB
Core has 4-way-associative cache
I/D each 8KB
I/D each 8KB
Boot-ROM
8 KB
8 KB
IRQ Ctrl
256
256
RTC (with auto calibration)
1 channel
1 channel
Source clock timer
4
4
RLT (Reload Timer) (32 bit)
10 channels
10 channels
FRT
8 channels
8 channels
ICU
8 channels
8 channels
OCU
8 channels
8 channels
PPG
24 channels
24 channels
SG (Sound Generator)
1 channel
1 channel
UDC (UpDown Counter)
2 channels
2 channels
CAN
3 channels
3 channels
USART (LIN-USART)
2 channels
2 channels
SPI
3 channels
3 channels
I2C
1 channel
1 channel
I2S
2 channels
2 channels
ARH (Automotive Remote Handler)
2 ch annels (1 channel physical)
2 ch annels (1 channel physical)
Quad - SPI
1 channel
1 channel
External bus
24-bit address/16-bit data
24-bit address/16-bit data
EIC (External Interrupts)
32 channels
32 channels
NMI (intern / extern)
32/1
32/1
SMC
6 channels
6 channels
ADC (10-bit)
50 channels
(including 24 channels shared
with SMC)
50 channels
(including 24 channels shared with
SMC)
CRC
1 channel
1 channel
Package
QFP-176
QFP-296
Document Number: DS707-00002-4v1-E
Page 3
MB9DF126
MB9DF126B
2.2
Features
Table 2-1: Feature
Feature
Technology
Description
• 90nm CMOS with embedded flash
•
•
•
•
•
Processor Subsystem
Debug and Trace
Clocks
Clock Supervisor
Resets
•
•
•
Cortex R4 CPU core
32-bit ARM architecture, dual-issue superscalar eight stage pipeline
ARMv7 and Thumb-2 instruction set compliant
Memory Protection Unit (MPU) with 12 regions
Two Tightly Coupled Memory (TCM) ports. 64-bit AXI slave port for access to
TCMs
64-bit AXI master port
Vectored Interrupt Controller (VIC) port for faster interrupt processing
Single error correction, double error detection (SECDED) Error Correction Coding (ECC) for memory error detection and correction
Instruction cache: 8KB 4-way set-associative
Data cache: 8KB 4-way set-associative
Up to 8 break-points and 8 watchpoints
•
•
•
•
ARM Coresight technology
Standard 5-pin JTAG interface
4-bit, 8-bit, 16-bit, and 32-bit trace data width supported depending on package
Secure entry supported for debugger
•
•
•
•
•
•
•
•
External main clock of 4MHz (up to 8MHz under evaluation)
External sub clock (typical 32.768 kHz)
Embedded RC oscillator (typical 8/12 MHz, configurable)
Embedded Slow RC oscillator (typical 100 kHz)
On-chip Phase Locked Loop (PLL) clock multiplier for main clock, Spread Spectrum Clock Generation (SSCG)
• Stabilization timers for all source clocks
• Clock supervision for all source clocks and PLL outputs
• Reset generation for out-of-bound clock frequencies on input source clocks, or
PLL output clocks
•
•
•
•
•
•
•
Power on Reset (PoR)
External Reset
Software triggered hard reset
Clock supervision resets
Watchdog
Low Voltage Detection reset
Software reset
Document Number: DS707-00002-4v1-E
Page 4
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
Description
Watchdog Timer
• 32-bit counter
• Supports selection of four clock sources (Main clock, Sub clock, RC clock or Slow
RC clock)
• Support for window watchdog functionality
• Reset or NMI generation support on watchdog errors
• Support for preemptive warning interrupt before watchdog reset or NMI generation
• Additional safety provision through three times redundancy and error correction
logic for important configuration bits
• Option to halt watchdog counter in case of core reaching break-point
DMA
Interrupts
External Interrupts
Timing Protection
•
•
•
•
•
•
•
64-bit AHB Master Interface
32-bit AHB Slave Interface
Block, burst and demand transfer modes
Fixed and incremental addressing for source as well as destination
132 clients
8 channels to handle independent data flows
Fixed priority, dynamic priority, and round robin arbitration
•
•
•
•
•
•
Interrupt Request (IRQ) and Fast Interrupt Request (FIQ) capability
NMI sources can generate FIQ
Supports 32 Non Maskable Interrupt (NMI) source for FIQ generation
Supports 512 Normal Interrupt sources for IRQ generation
Supports request for low power mode entry
Programmable 32-level priority controller for normal IRQ sources. Also, supports
programmable priority level masking
• Programmable 16-level priority controller for NMI interrupt sources
• Software interrupt generation
• Privileged mode support for restricted access
•
•
•
•
•
•
•
Up to 32 pins can be used as external interrupts
Optional 25ns (typical) noise filters on all lines
DMA support
NMI support
Five polarity support (‘H’, ‘L’, rising edge, falling edge, and, any edge)
Event capture support for all 32 external interrupt pins
Software enabled monitoring of external events, with sampling frequency of
500Hz to 16MHz
• Up to eight identical 24-bit timers for execution time protection, locking time protection, inter-arrival time protection or deadline protection
• Normal and overflow mode support
• Global linear prescaler (1 to 64) to scale down clock frequency
• Additional, individual timer prescaler to support 4 different software programmable frequencies (1, 1/2, 1/4, and 1/16 )
• Start, stop, and continue options per timer controllable by software
Document Number: DS707-00002-4v1-E
Page 5
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
Description
Memory Protection
• Memory protection unit for all bus masters
• AXI interface support
• 8 programmable memory regions, and one background region which covers entire 4GB address space
• Unauthorized access generates NMI
Peripheral Protection
• Protection to all peripherals and General Purpose IOs (GPIO)
• Individual protection setting for up to 512 peripherals, and 512 GPIO channels
• DMA access support for faster register configuration
CAN
USART/LIN
•
•
•
•
•
•
•
•
• Programmable LIN or USART function
• Full-duplex support
• Clock synchronous (start-stop synchronization and start-stop-bit option),and
Clock asynchronous (using start-, stop-bits) transfer modes
• Dedicated baud rate generator. Mechanism for automatic baud rate adjust available in LIN mode
• Support for data length of 7-bits (not in synchronous or LIN mode) and 8-bits
• Support for signal modes Non-Return to Zero (NRZ) and Non-Return to Zero
Inverted (NRZI)
• Reception error detection for framing, overrun, parity, checksum, sync field timeout, and frame-ID (only in LIN mode) errors
• Interrupt capability for transmission, reception, and errors
• DMA support
•
•
•
•
I2C
•
•
•
•
Stepper Motor Control
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 Mbps
64 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled automatic retransmission mode for time triggered CAN applications
Programmable loop-back mode for self-test operation
Master/slave transmitting and receiving functions
7-bit addressing as master and slave
10-bit addressing as master and slave
Acknowledge disable option upon slave address reception (master-only operation)
Address mirroring to give interface several slave addresses
Up to 400 kbps transfer rate
Optional noise filters for SDA and SCL
Interrupt capability on transmission and bus error events
• PWM duty cycle programmable from 0% to 100%
• Programmable setting to select ‘L’, ‘H’, ‘PWM’ and ‘HighZ’ output
• High current output pins
Document Number: DS707-00002-4v1-E
Page 6
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
A/D Converter
Description
•
•
•
•
•
•
•
•
•
50 channels
Conversion time: 1us per channel
RC type Successive Approximation (SAR) with sample and hold circuit
10-bit or 8-bit resolution
Program selection analog input from 32 channels
Single conversion, continuous conversion, and scan conversion options
Interrupt capability
DMA support
4 range comparator channels for comparing conversion output with thresholds
I2S
• Programmable master/slave operations
• Supports transmission only, reception only and simultaneous transmission/reception operations
• Support for 1 sub frame and 2 sub frame constructions
• Up to 32 channels supported in each sub frame
• Support for individual configuration of channel number, channel length, word
length in each sub frame
• Word length support from 7-bits to 32-bits
• Programmable frequency, polarity, and phase of frame synchronous signal
• Programmable sampling point of received data (center or at the end of received
data)
• Support for frequency division from 1 to 126 in multiples of 2
• DMA support
• Interrupt capability
Sound Generator
• Produces sound/melody with varying frequency and amplitude
• Square wave sound output with frequency of 100Hz – 6kHz (resolution 20Hz)
• Programmable Pulse Width Modulated (PWM) cycle width of 255 or 511 clocks.
PWM duty cycle programmable from 0% to 100%
• Two 2-bit prescaler with programmable clock division of 1, 1/2, 1/3, and 1/4
• Automatic linear or exponential amplitude increment or decrement
• Start, stop, resume functionality
• DMA support
• Automatic sound output stop when amplitude becomes 0
Up Down Counter
• Format: 32-bit or 2 times 16-bit
• Three count modes (timer mode, up/down count mode, and phase difference
count mode) supported
• Multiply by 2 or multiply by 4 in phase difference count mode
• Count source can be internal clock or external trigger
• Counting range: any value between 0 and 232-1 can be set
• 4 interrupt options (Compare-match interrupt, Underflow interrupt, Overflow interrupt, and Count direction change interrupt)
Document Number: DS707-00002-4v1-E
Page 7
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
Description
•
•
•
•
•
•
•
Reload Timers
32-bit reload counter
External and Internal clock/event source
Trigger signal programmable as rising/falling edge or both
Gated count function
One-shot or reload counter mode
Counter state can be made visible at external pin
Prescaler with six different settings for the internal clock and two settings for the
external clock
• Several Reload Timers can be cascaded to form a longer Reload Timer
• DMA support
Free Running Timers
• Signals an interrupt on overflow, match with Compare registers, zero-detection,
or match with Compare Clear Register
• Option to mask zero detection, compare clear match interrupt, or both to allow
for interrupt generation only after multiple events
• Programmable timer period up to 1 s
• Support for 11 counter clocks. Prescaler with 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512, and 1/1024 of peripheral clock frequency
• DMA support
Input Capture Units
•
•
•
•
•
Consists of 2 independent input channels
16-bit wide capture registers per channel
Signals an interrupt upon external event
Rising edge, falling edge or rising & falling edge sensitive
DMA support
Output Compare
Units
•
•
•
•
•
Consists of 2 independent channels
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal
Interrupt capability
Programmable Pulse
Generator
•
•
•
•
16-bit down counter, cycle and duty setting registers
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock
and Reload timer underflow as clock input
• Can be triggered by software or reload timer
•
•
•
•
Real Time Clock
•
•
•
•
Can be clocked from main clock, sub clock or RC clock
Automatic calibration support even when device is in low power state
Interrupt capability on half-second, 1 second, 1 minute, 1 hour, and 1 day duration
Additional capability for interrupt generation on calibration failure detection and
calibration done event
Auto calibration of Sub clock or RC clock with respect to Main clock
Separate clock selector for calibration
Configurable calibration duration
Auto/manual trigger for calibration
Document Number: DS707-00002-4v1-E
Page 8
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
Description
Internal MemoriesTCMRAM
• 128 KB
• 64-bit interface
• Single error correction, double error detection (SECDED) ECC support
Internal MemoriesSystem RAM
•
•
•
•
64-bit AXI interface
64 KB
Single error correction, double error detection (SECDED) ECC support
Parallel read/write capability for 2 different banks
Internal MemoriesRetention RAM
•
•
•
•
16 KB
4 banks
32-bit AHB
Low leakage RAMs for low power consumption
Tightly Coupled Flash
Memory
EEPROM Emulation
Flash Memory
Quad SPI
Error Collection
Low Voltage Detect
• 2 MB
• Parallel Programming support
• Mapped to TCM address space as well as Cacheable address space through
AXI interface
• Single error correction, double error detection (SECDED) ECC support
• TCM address space supports only read access
• Cacheable AXI address space supports write and read access
• Detection of hang-up 1 state
• 32 large sectors of 64KB each
• 16 small sectors of 8KB each
• Sector-wise access protection for write and read accesses
•
•
•
•
•
•
•
•
64 KB
Parallel Programming support
Single error correction, double error detection (SECDED) ECC support
Support for sector erase
EEPROM emulation mode support
Support for mirroring of memory in 3 diverse memory-mapped regions
8 sectors of 8KB each
Sector-wise access protection for write and read accesses
• Supports legacy as well as the dual-bit and quad-bit modes of SPI operation
• Supports up to four slave devices in master mode
• Programmable transfer rate, active-level of slave-select signal, polarity, and
phase of the serial clock per slave select
• Support for memory mapped operation of external serial flash and serial SRAM
devices in command sequencer mode
• Additional direct mode support for standard SPI operation through FIFO interface
• Error collection on all peripherals
• Optional Non-Maskable Interrupt (NMI) generation capability
• Low voltage detection for 5V, 3.3V, and 1.2V
• Programmable thresholds
• Reset generation capability on low voltage events
Document Number: DS707-00002-4v1-E
Page 9
MB9DF126
MB9DF126B
Table 2-1: Feature (Continued)
Feature
Description
I/O Ports
•
•
•
•
All functional pins can be used as GPIO
Programmable analog or digital functionality selection
Programmable input levels (Automotive, CMOS, and TTL)
Programmable pull-up/pull-down and output drive
EBI
•
•
•
•
Endianess configuration support for all SRAM interfaces based on chip select
PPU Protection for EBI Configuration register range
Only 32-bit write access support supported by EBI Configuration registers
Lock/Unlock register for write protection for EBI Configuration registers
APIX
•
•
•
•
Support 500, 250, 125 Mbps pixel data transmission
Support 62.5, 41.67, 31.25, 20.83 Mbps side band data reception
Support loop back test mode (BIST logic)
Monitoring PLL lock detection over Osc clock glitches
ARH
• PPU protection for register access
• Debug support for RAM
• Registers accesses based on Lock status ARHn_RHCTRL:LST bit, ARHn_TST:TM bit, on transaction buffer state, and on tx_config from Remote Handler
• Arbitration between S/W read and A-Shell write over the event buffer
CRC
•
•
•
•
•
•
•
•
Packages
Programmable 8, 16, 24 or 32 bit input data width
Programmable polynomial value (Polynomial degree from 2 to 32)
Programmable initial seed value
Programmable final checksum XOR value
Interrupt and DMA client interface
Configurable input/output bit reflection and byte swapping
Supports PPU
Supports block/multiple data transfers (more than 32-bit)
• QFP-296 (evaluation variant with additional trace pins)
• QFP-176 (series variant)
Note: EEPROM (Electronically Erasable and Programmable Read-Only Memory)
Document Number: DS707-00002-4v1-E
Page 10
MB9DF126
MB9DF126B
2.3
Memory Map
Table 2-2: Memory Map
FFFF2000
FFFF0000
FFFEF000
B0D01000
B0D00000
B0C00000
B0B00000
B0A00000
B0900000
B0800000
B0700000
B0600000
B0500000
B0400000
B0200000
B0180000
B0080000
B0000000
90000000
80000000
28000000
20000000
10000000
06000000
05FE0000
05A00000
05800000
05020000
05000000
04800000
04000000
01A10000
01A00000
01800000
017E0000
01200000
01000000
00FE0000
00A00000
00800000
00020000
00000000
Document Number: DS707-00002-4v1-E
Reserved
BOOTROM
EXCFG
Reserved
SYSTEM_RAM_CONFIG
PERI5_AHB
PERI4_SLAVE
PERI3_ERBUS
Reserved
PERI1_RBUS
PERI0_RBUS
MCU_CONFIG
DEBUG_BUS
MEMORY_CONFIG
Reserved
EBI
Reserved
HSSPI0
Reserved
HSSPI0_MEMORY
Reserved
EBI_MEMORY1
EBI_MEMORY0
Reserved
AXI_SLAVE_CORE0_TCM_FLASH_SMALL_SECTORS
Reserved
AXI_SLAVE_CORE0_TCM_FLASH_LARGE_SECTORS
Reserved
AXI_SLAVE_CORE0_TCM_RAM
AXI_SLAVE_CORE0_DCACHE
AXI_SLAVE_CORE0_ICACHE
Reserved
SYSTEM_RAM
Reserved
AXI_FLASH_MEMORY_SMALL_SECTORS
Reserved
AXI_FLASH_MEMORY_LARGE_SECTORS
TCM_FLASH_SMALL_SECTORS
Reserved
TCM_FLASH_LARGE_SECTORS
Reserved
TCM_RAM
Page 11
MB9DF126
MB9DF126B
Table 2-3: PERI0_RBUS Memory Map
B07FFC00
B07FA800
B07F8000
B07F0400
B07F0000
B07EC000
B07E8000
B075A000
B074C000
B074BC00
B0748C00
B0748800
B0748400
B0748000
B0747C00
B073BC00
B073B800
B073B400
B073B000
B073AC00
B073A800
B073A400
B073A000
B0739C00
B0739800
B0739400
B0739000
B0738C00
B0738800
B0738400
B0738000
B0732000
B0731800
B0731400
B0731000
B0730C00
B0730800
B0730400
B0730000
B0729800
B0728000
B0720C00
B0720000
B071C000
B0718400
B0718000
B0714000
B0710C00
B0710800
B0710400
B0708C00
B0708800
B0708400
B0708000
B0700400
B0700000
Document Number: DS707-00002-4v1-E
BSU0
Reserved
RICFG0
Reserved
BECU0
Reserved
PPC
Reserved
PPGGLC0
Reserved
PPGGRP3
PPGGRP2
PPGGRP1
PPGGRP0
Reserved
PPG15
PPG14
PPG13
PPG12
PPG11
PPG10
PPG9
PPG8
PPG7
PPG6
PPG5
PPG4
PPG3
PPG2
PPG1
PPG0
Reserved
SMCTG0
SMC5
SMC4
SMC3
SMC2
SMC1
SMC0
Reserved
USART0
Reserved
I2C0
Reserved
OCU1
OCU0
Reserved
ICU3
ICU2
Reserved
FRT3
FRT2
FRT1
FRT0
Reserved
ADC0
Page 12
MB9DF126
MB9DF126B
Table 2-4: PERI1_RBUS Memory Map
Document Number: DS707-00002-4v1-E
B08FFC00
BSU1
B08FB000
Reserved
B08F8000
RICFG1
B08F0000
BECU1
B0868000
Reserved
B085C000
PPGGLC1
B085BC00
Reserved
B0858400
PPGGRP17
B0858000
PPGGRP16
B0857C00
Reserved
B0849C00
PPG71
B0849800
PPG70
B0849400
PPG69
B0849000
PPG68
B0848C00
PPG67
B0848800
PPG66
B0848400
PPG65
B0848000
PPG64
B0842000
Reserved
B0838000
USART6
B0830C00
Reserved
B0828400
OCU17
B0828000
OCU16
B0824000
Reserved
B0820C00
ICU19
B0820800
ICU18
B0820400
Reserved
B0818C00
FRT19
B0818800
FRT18
B0818400
FRT17
B0818000
FRT16
B0810400
Reserved
B0808800
CAN2
B0808400
CAN1
B0808000
CAN0
B0800400
Reserved
B0800000
SG0
Page 13
MB9DF126
MB9DF126B
Table 2-5: PERI3_eRBUS Memory Map
Document Number: DS707-00002-4v1-E
B0AFFC00
BSU3
B0AF9400
Reserved
B0AF8000
RICFG3
B0AF0000
BECU3
B0A28000
Reserved
B0A20000
UDC0
B0A18000
Reserved
B0A12400
RLT9
B0A12000
RLT8
B0A11C00
RLT7
B0A11800
RLT6
B0A11400
RLT5
B0A11000
RLT4
B0A10C00
RLT3
B0A10800
RLT2
B0A10400
RLT1
B0A10000
RLT0
B0A09000
Reserved
B0A08000
GPIO
B0A00400
Reserved
B0A00000
PPU0
Page 14
MB9DF126
MB9DF126B
Table 2-6: PERI4_SLAVE AHB Bus Memory Map
Document Number: DS707-00002-4v1-E
B0BFFC00
BSU4
B0BFA400
Reserved
B0BF8000
RICFG4
B0B40400
Reserved
B0B40000
ARH0
B0B3B000
Reserved
B0B38800
SPI2
B0B38400
SPI1
B0B38000
SPI0
B0B30800
Reserved
B0B30000
CRC0
B0B29000
Reserved
B0B20400
I2S1
B0B20000
I2S0
B0B00000
Reserved
Page 15
MB9DF126
MB9DF126B
Table 2-7: PERI5_AHB Bus Memory Map
B0CFFC00
BSU5
B0CFF800
Reserved
B0C08000
MPUXDMA0
B0C04000
Reserved
B0C00000
DMA0
B0800000
PERI1_RBUS
B0700000
PERI0_RBUS
Table 2-8: Memory and Config (MEMORY_CONFIG)AHB Bus Memory Map
B04C0000
B0480000
B0440000
B0420400
B0418000
B0412400
B0412000
B0411400
B0411000
B0410400
B0410000
B040B400
B0408000
B0401000
B0400000
Document Number: DS707-00002-4v1-E
EEFLASH_NOECC_MIR
EEFLASH_TABLE_MIR
EEFLASH_ECC_MIR
Reserved
BSU6
Reserved
EEFCFG
Reserved
TCFCFG
Reserved
TRCFG
Reserved
TPU0
Reserved
IRQ0
Page 16
MB9DF126
MB9DF126B
Table 2-9: MCU_CONFIG AHB Bus Memory Map
B06FFC00
BSU7
B06F9400
Reserved
B06F8000
RICFG7
B0648000
Reserved
B063B000
RETRAMBANK3
B063A000
RETRAMBANK2
B0639000
RETRAMBANK1
B0638000
RETRAMBANK0
B0630000
Reserved
B0628000
EICU0
B0620400
Reserved
B0620000
EIC0
B0618400
Reserved
B0618000
RTC
B0610400
Reserved
B0610000
RRCFG
B0608400
Reserved
B0608000
WDG
B0601000
Reserved
B0600000
SYSC
Table 2-10: HSSPI0 Memory Map
B007FC00
BSU8
B0078400
Reserved
B0078000
RICFG8
B0000000
HSSPI0
Table 2-11: EBI Memory Map
Document Number: DS707-00002-4v1-E
B01FFC00
BSU10
B0180080
Reserved
B0180000
EBI
Page 17
MB9DF126
MB9DF126B
2.4
Resource distribution for non-modulated clock
Some of the resources are available with modulated and non-modulated clock. Find below the distribution:
Table 2-12: Resource distribution for non-modulated clock
2.5
Module
Non-modulated
Modulation possible
CAN
3
-
SG
1
-
ICU/OCU/FRT
4
4
PPG
8
16
USART/LIN
1
1
I2C
1
-
SMC
-
6
Lock/unlock values for protection units
For various protection and system relevant units, registers must be unlocked before configuring and can be locked
for protection. For the details about functionality, see the FCR4 Hardware Manual.
Table 2-13: Lock/unlock values for FCR4 protection module instances.
Module
Unlock value
Lock value
TPU0
ACC5A110
B10CACC5
PPU0
ACC5BB01
BB0B10C1
MPUXDMA0
ACCABB56
112ABB56
TRCFG
ACC55ECC
5ECCB10C
EXCFG
ACC5B007
B007ECF6
IRQ0
17ACC911
17B10C11
RRCFG
ACC5DECC
DECCB10C
SCCFG
5ECACCE5
A135331A
SRCFG
5ECC551F
551FB10C
ARH0
A86ACCE5
A86AB10C
ETH0
E18ACCE5
E18B10CC
TCFCFG
CF61F1A5
EEFCFG
CF6DF1A5
WDG
EDACCE55
SYSC
5CACCE55
EBI
EB1410CE
Document Number: DS707-00002-4v1-E
10CE0EB1
Page 18
MB9DF126
MB9DF126B
2.6
ID-Values for Module Identification Registers
For several peripheral and system related modules, the hardware contains Module Identification Registers that
hold read-only values which contain information about the module number, the version and possible patches.
Table 2-14: List of Module ID
Module
ID-Register
ID Value
System Controller
SYSC_SYSIDR
0x00020101
Security Checker
SCCFG_MODID
0x00020200
SRAM Interface
SRCFG_MID
0x00040200
TC-Flash Interface
TCFCFG_FMIDR
0x000E0102
EE-Flash Interface
EEFCFG_MIR
0x00090200
Interrupt Controller 0
IRQ0_MID
0x000B0100
DMA Controller 0
DMA0_ID
0x00010102
Timing Protection Unit 0
TPU0_MID
0x00050200
Memory Protection Unit for AXI
MPUXDMA0_MID
0x000D0100
Bus Error Collection Unit 0
BECU0_MIDH / BECU0_MIDL
0x0008 / 0x0100
Bus Error Collection Unit 1
BECU1_MIDH / BECU1_MIDL
0x0008 / 0x0100
Bus Error Collection Unit 3
BECU3_MIDH / BECU3_MIDL
0x0008 / 0x0100
High Speed SPI Interface 0
HSSPI0_MID
0x00060200
SPI Interface 0
SPI0_MID
0x00070200
SPI Interface 1
SPI1_MID
0x00070200
SPI Interface 2
SPI2_MID
0x00070200
Inter IC Sound 0
I2S0_MIDREG
0x000A0200
Inter IC Sound 1
I2S1_MIDREG
0x000A0200
Automotive Remote Handler 0
ARH0_MID
0x000C0200
Document Number: DS707-00002-4v1-E
Page 19
MB9DF126
MB9DF126B
3
Package and Pin Assignment
3.1
Package
The same die will be used for two packages.
A QFP-176 package is used for MB9DF126. The package code is FPT-176P-M07.
Also an optional QFP-296 package with trace pins is shown in Section 3.1.1. The package code is FPT-296P-M04.
3.1.1
QFP-296 Package
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
NB
NB
NB
NB
NB
NB
VDP5
VDP5
RSTX
NB
MODE
X1A
NB
X0A
NB
VSS
X0
X1
XTAL0
XTAL1
VSSA
MOSC_BOPT
VDE5_OSC (5V)
NB
VSSA
VDDA (1.2V)
VSSA
VDEA_VCO (3.3V)
RREF
VDEA (3.3V)
SDOUTP
NB
VSSA
SDOUTM
VDEA (3.3V)
SDINM
SDINP
VSSA
NB
NB
NB
NB
VDP3
VDP3
VSS
VSS
P1_29
P1_28
P1_27
P1_26
P3_32
P3_31
P3_30
P3_29
P3_28
P3_27
P3_26
P3_25
VSS
VSS
VDP3
VDP3
P3_24
P3_23
P3_22
VSS
VSS
VDD
VDD
NB
NB
NB
NB
NB
Figure 3-1: QFP-296 Package
VDP5 / 3V−5V−IO
VDP5 / 3V−5V−IO
APIX / analog
VDP3 / 3V−IO
1 VDP5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
QFP296
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
analog
DVCC / 3V−5V−IO
VDP3 / 3V−IO
DBG0_TRACE15
DBG0_TRACE14
P3_21
P3_20
DBG0_TRACE13
VSS
VDP3
P3_19
DBG0_TRACE12
P3_18
P3_17
DBG0_TRACE11
DBG0_TRACE10
P3_16
P3_15
P3_14
DBG0_TRACE9
DBG0_TRACE8
P3_13
VSS
VSS
VDP3
VDP3
P3_42
P3_41
DBG0_TRACE7
P3_40
P3_39
DBG0_TRACE6
P3_38
DBG0_TRACE5
P3_37
VSS
VDP3
P3_36
P3_35
P3_34
P3_33
P1_25
P1_24
DBG0_TRACECTL
DBG0_TRACECLK
VDP3
VDP3
VSS
VSS
P3_12
P3_11
P3_10
P3_09
P3_08
P3_07
VSS
VDP3
P3_06
P3_05
P3_04
P3_03
DBG0_TRACE4
P3_02
P3_01
DBG0_TRACE3
DBG0_TRACE2
VSS
VSS
VDP3
VDP3
P3_00
P1_33
P1_32
DBG0_TRACE1
P1_31
P1_30
DBG0_TRACE0
NB
NB
AVSS5
AVRH5
AVDD5
NB
DVCC
DVCC
DVSS
DVSS
P1_00
P1_01
NB
P1_02
NB
NB
NB
P1_03
P1_04
P1_05
P1_06
P1_07
DVSS
DVSS
DVCC
DVCC
P1_08
P1_09
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
NB
NB
DVSS
DVSS
DVCC
DVCC
P1_16
P1_17
P1_18
P1_19
P1_20
NB
NB
P1_21
P1_22
P1_23
DVSS
DVSS
DVCC
DVCC
NB
NB
NB
NB
NB
NB
NB
VDP3
VDP3
VSS
VSS
P1_34
P1_35
P1_36
P1_37
P1_38
VDD
VDD
VSS
VSS
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
VDP3 / 3V−IO
NB
VSS
VSS
VDD
VDD
VSS
VSS
P0_40
P0_41
NB
P0_42
P0_43
P0_44
NB
NB
NB
NB
NB
NB
NB
NB
NB
P0_45
P0_46
P0_47
P0_48
P0_49
NB
NB
P0_50
P0_51
P0_62
P0_63
P2_32
NB
P2_33
VDP5
VDP5
VSS
VSS
P2_34
P2_35
P2_36
P2_37
P2_38
P2_39
NB
NB
NB
NB
NB
NB
P2_40
P2_41
P2_42
P2_43
P2_44
P2_45
P2_46
P2_47
VSS
VSS
VDP5
VDP5
JTAG_TDO
JTAG_TDI
JTAG_TCK
VSS
VSS
VDD
VDD
JTAG_TMS
JTAG_NTRST
NB
Document Number: DS707-00002-4v1-E
Page 17
MB9DF126
MB9DF126B
Table 3-1: QFP-296 Package pinout
Pin No
Pin Name
IO-Type
1
NB
NA
2
NB
NA
3
AVSS5
supply
4
AVRH5
supply
5
AVDD5
supply
6
NB
NA
7
DVCC
supply
8
DVCC
supply
9
DVSS
supply
10
DVSS
supply
11
P1_00
SMC
12
P1_01
SMC
13
NB
NA
14
P1_02
SMC
15
NB
NA
16
NB
NA
17
NB
NA
18
P1_03
SMC
19
P1_04
SMC
20
P1_05
SMC
21
P1_06
SMC
22
P1_07
SMC
23
DVSS
supply
24
DVSS
supply
25
DVCC
supply
26
DVCC
supply
27
P1_08
SMC
28
P1_09
SMC
29
P1_10
SMC
30
P1_11
SMC
31
P1_12
SMC
32
P1_13
SMC
33
P1_14
SMC
34
P1_15
SMC
35
NB
NA
36
NB
NA
37
DVSS
supply
38
DVSS
supply
39
DVCC
supply
40
DVCC
supply
41
P1_16
SMC
Document Number: DS707-00002-4v1-E
Page 18
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
42
P1_17
SMC
43
P1_18
SMC
44
P1_19
SMC
45
P1_20
SMC
46
NB
NA
47
NB
NA
48
P1_21
SMC
49
P1_22
SMC
50
P1_23
SMC
51
DVSS
supply
52
DVSS
supply
53
DVCC
supply
54
DVCC
supply
55
NB
NA
56
NB
NA
57
NB
NA
58
NB
NA
59
NB
NA
60
NB
NA
61
NB
NA
62
VDP3
supply
63
VDP3
supply
64
VSS
supply
65
VSS
supply
66
P1_34
BIDI33
67
P1_35
BIDI33
68
P1_36
BIDI33
69
P1_37
BIDI33
70
P1_38
BIDI33
71
VDD
supply
72
VDD
supply
73
VSS
supply
74
VSS
supply
75
DBG0_TRACE0
BIDI33
76
P1_30
BIDI33
77
P1_31
BIDI33
78
DBG0_TRACE1
BIDI33
79
P1_32
BIDI33
80
P1_33
BIDI33
81
P3_00
BIDI33
82
VDP3
supply
83
VDP3
supply
Document Number: DS707-00002-4v1-E
Page 19
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
84
VSS
supply
85
VSS
supply
86
DBG0_TRACE2
BIDI33
87
DBG0_TRACE3
BIDI33
88
P3_01
BIDI33
89
P3_02
BIDI33
90
DBG0_TRACE4
BIDI33
91
P3_03
BIDI33
92
P3_04
BIDI33
93
P3_05
BIDI33
94
P3_06
BIDI33
95
VDP3
supply
96
VSS
supply
97
P3_07
BIDI33
98
P3_08
BIDI33
99
P3_09
BIDI33
100
P3_10
BIDI33
101
P3_11
BIDI33
102
P3_12
BIDI33
103
VSS
supply
104
VSS
supply
105
VDP3
supply
106
VDP3
supply
107
DBG0_TRACECLK
BIDI33
108
DBG0_TRACECTL
BIDI33
109
P1_24
BIDI33
110
P1_25
BIDI33
111
P3_33
BIDI33
112
P3_34
BIDI33
113
P3_35
BIDI33
114
P3_36
BIDI33
115
VDP3
supply
116
VSS
supply
117
P3_37
BIDI33
118
DBG0_TRACE5
BIDI33
119
P3_38
BIDI33
120
DBG0_TRACE6
BIDI33
121
P3_39
BIDI33
122
P3_40
BIDI33
123
DBG0_TRACE7
BIDI33
124
P3_41
BIDI33
125
P3_42
BIDI33
Document Number: DS707-00002-4v1-E
Page 20
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
126
VDP3
supply
127
VDP3
supply
128
VSS
supply
129
VSS
supply
130
P3_13
BIDI33
131
DBG0_TRACE8
BIDI33
132
DBG0_TRACE9
BIDI33
133
P3_14
BIDI33
134
P3_15
BIDI33
135
P3_16
BIDI33
136
DBG0_TRACE10
BIDI33
137
DBG0_TRACE11
BIDI33
138
P3_17
BIDI33
139
P3_18
BIDI33
140
DBG0_TRACE12
BIDI33
141
P3_19
BIDI33
142
VDP3
supply
143
VSS
supply
144
DBG0_TRACE13
BIDI33
145
P3_20
BIDI33
146
P3_21
BIDI33
147
DBG0_TRACE14
BIDI33
148
DBG0_TRACE15
BIDI33
149
NB
NA
150
NB
NA
151
NB
NA
152
NB
NA
153
NB
NA
154
VDD
supply
155
VDD
supply
156
VSS
supply
157
VSS
supply
158
P3_22
BIDI33
159
P3_23
BIDI33
160
P3_24
BIDI33
161
VDP3
supply
162
VDP3
supply
163
VSS
supply
164
VSS
supply
165
P3_25
BIDI33
166
P3_26
BIDI33
167
P3_27
BIDI33
Document Number: DS707-00002-4v1-E
Page 21
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
168
P3_28
BIDI33
169
P3_29
BIDI33
170
P3_30
BIDI33
171
P3_31
BIDI33
172
P3_32
BIDI33
173
P1_26
BIDI33
174
P1_27
BIDI33
175
P1_28
BIDI33
176
P1_29
BIDI33
177
VSS
supply
178
VSS
supply
179
VDP3
supply
180
VDP3
supply
181
NB
NA
182
NB
NA
183
NB
NA
184
NB
NA
185
VSSA
supply
186
SDINP
SDIN
187
SDINM
SDIN
188
VDEA (3.3V)
supply
189
SDOUTM
SDOUT
190
VSSA
supply
191
NB
NA
192
SDOUTP
SDOUT
193
VDEA (3.3V)
supply
194
RREF
RREF
195
VDEA_VCO (3.3V)
supply
196
VSSA
supply
197
VDDA(1.2V)
supply
198
VSSA
supply
199
NB
NA
200
VDE5_OSC (5V)
supply
201
MOSC_BOPT
MODE
202
VSSA
supply
203
XTAL1
204
XTAL0
205
X1
206
X0
MAINOSC
(20MHz)
MAINOSC
(20MHz)
MAINOSC
(4MHz)
MAINOSC
(4MHz)
207
VSS
supply
208
NB
NA
209
X0A
SUBOSC
Document Number: DS707-00002-4v1-E
Page 22
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
210
NB
NA
211
X1A
SUBOSC
212
MODE
MODE
213
NB
NA
214
RSTX
MODE
215
VDP5
supply
216
VDP5
supply
217
NB
NA
218
NB
NA
219
NB
NA
220
NB
NA
221
NB
NA
222
NB
NA
223
NB
NA
224
VSS
supply
225
VSS
supply
226
VDD
supply
227
VDD
supply
228
VSS
supply
229
VSS
supply
230
P0_40
BIDI50
231
P0_41
BIDI50
232
NB
NA
233
P0_42
BIDI50
234
P0_43
BIDI50
235
P0_44
BIDI50
236
NB
NA
237
NB
NA
238
NB
NA
239
NB
NA
240
NB
NA
241
NB
NA
242
NB
NA
243
NB
NA
244
NB
NA
245
P0_45
BIDI50
246
P0_46
BIDI50
247
P0_47
BIDI50
248
P0_48
BIDI50
249
P0_49
BIDI50
250
NB
NA
251
NB
NA
Document Number: DS707-00002-4v1-E
Page 23
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
252
P0_50
BIDI50
253
P0_51
BIDI50
254
P0_62
I2C
255
P0_63
I2C
256
P2_32
BIDI50
257
NB
NA
258
P2_33
BIDI50
259
VDP5
supply
260
VDP5
supply
261
VSS
supply
262
VSS
supply
263
P2_34
BIDI50
264
P2_35
BIDI50
265
P2_36
BIDI50
266
P2_37
BIDI50
267
P2_38
BIDI50
268
P2_39
BIDI50
269
NB
NA
270
NB
NA
271
NB
NA
272
NB
NA
273
NB
NA
274
NB
NA
275
P2_40
BIDI50
276
P2_41
BIDI50
277
P2_42
BIDI50
278
P2_43
BIDI50
279
P2_44
BIDI50
280
P2_45
BIDI50
281
P2_46
BIDI50
282
P2_47
BIDI50
283
VSS
supply
284
VSS
supply
285
VDP5
supply
286
VDP5
supply
287
JTAG_TDO
JTAGO
288
JTAG_TDI
JTAGIUP
289
JTAG_TCK
JTAGIUP
290
VSS
supply
291
VSS
supply
292
VDD
supply
293
VDD
supply
Document Number: DS707-00002-4v1-E
Page 24
MB9DF126
MB9DF126B
Pin No
Pin Name
IO-Type
294
JTAG_TMS
JTAGIUP
295
JTAG_NTRST
JTAGIDN
296
NB
NA
Figure 3-2: Package Dimensions QFP-296
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)3730
SLQSODVWLF4)3
)3730
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PP
3DFNDJHZLGWK SDFNDJHOHQJWK
PP
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6HDOLQJPHWKRG
3ODVWLFPROG
0RXQWLQJKHLJKW
PP0$;
:HLJKW
J
7KHUPDO
UHVLVWDQFH
/RZWKHUPDOUHVLVWDQFHW\SH
&RGH
5HIHUHQFH
3)4)3 1RWH 7KHVHGLPHQVLRQVGRQRWLQFOXGHUHVLQSURWUXVLRQ
1RWH 3LQVZLGWKDQGSLQVWKLFNQHVVLQFOXGHSODWLQJWKLFNQHVV
1RWH 3LQVZLGWKGRQRWLQFOXGHWLHEDUFXWWLQJUHPDLQGHU
““64
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'HWDLOVRI$SDUW
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0RXQWLQJKHLJKW
,1'(;
)8-,7686(0,&21'8&725/,0,7(')6F
&
7K
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W
W
I WKL G
W
EM
WW
K
Document Number: DS707-00002-4v1-E
LWK
W
0
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ƒaƒ
$
/($'1R
±
±
6WDQGRII
“
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'LPHQVLRQVLQPPLQFKHV
1RWH7KHYDOXHVLQSDUHQWKHVHVDUHUHIHUHQFHYDOXHV
WL
Page 25
MB9DF126
MB9DF126B
3.1.2
QFP-176 Package
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDP5
RSTX
MODE
X1A
X0A
VSS
XTAL0
XTAL1
VSSA
VDE5_OSC (5V)
VSSA
VDDA(1.2V)
VSSA
VDEA_VCO (3.3V
RREF
VDEA (3.3V)
SDOUTP
VSSA
SDOUTM
VDEA (3.3V)
SDINM
SDINP
VSSA
VDP3
VSS
P1_29
P1_28
P1_27
P1_26
P3_32
P3_31
P3_30
P3_29
P3_28
P3_27
P3_26
P3_25
VSS
VDP3
P3_24
P3_23
P3_22
VSS
VDD
Figure 3-3: QFP-176 Package
VDP5 / 3V−5V−IO
VDP5
APIX / analog
VDP3 / 3V−IO
QFP176
VDP5
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VDP3 / 3V−IO
VSS
VDD
VSS
P0_40
P0_41
P0_42
P0_43
P0_44
P0_45
P0_46
P0_47
P0_48
P0_49
P0_50
P0_51
P0_62
P0_63
P2_32
P2_33
VDP5
VSS
P2_34
P2_35
P2_36
P2_37
P2_38
P2_39
P2_40
P2_41
P2_42
P2_43
P2_44
P2_45
P2_46
P2_47
VSS
VDP5
JTAG_TDO
JTAG_TDI
JTAG_TCK
VSS
VDD
JTAG_TMS
JTAG_NTRST
DVCC / 3V−5V−IO
VDP3 / 3V−IO
P3_21
P3_20
P3_19
P3_18
P3_17
P3_16
P3_15
P3_14
P3_13
VSS
VDP3
P3_42
P3_41
P3_40
P3_39
P3_38
P3_37
P3_36
P3_35
P3_34
P3_33
P1_25
P1_24
VDP3
VSS
P3_12
P3_11
P3_10
P3_09
P3_08
P3_07
P3_06
P3_05
P3_04
P3_03
P3_02
P3_01
VSS
VDP3
P3_00
P1_33
P1_32
P1_31
P1_30
AVSS5
AVRH5
AVDD5
DVCC
DVSS
P1_00
P1_01
P1_02
P1_03
P1_04
P1_05
P1_06
P1_07
DVSS
DVCC
P1_08
P1_09
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
DVSS
DVCC
P1_16
P1_17
P1_18
P1_19
P1_20
P1_21
P1_22
P1_23
DVSS
DVCC
VDP3
VSS
P1_34
P1_35
P1_36
P1_37
P1_38
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
analog
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
Document Number: DS707-00002-4v1-E
Page 26
MB9DF126
MB9DF126B
Table 3-2: QFP-176 Package pinout
Pin No
Document Number: DS707-00002-4v1-E
Pin Name
IO_Type
1
AVSS5
supply
2
AVRH5
supply
3
AVDD5
supply
4
DVCC
supply
5
DVSS
supply
6
P1_00
SMC
7
P1_01
SMC
8
P1_02
SMC
9
P1_03
SMC
10
P1_04
SMC
11
P1_05
SMC
12
P1_06
SMC
13
P1_07
SMC
14
DVSS
supply
15
DVCC
supply
16
P1_08
SMC
17
P1_09
SMC
18
P1_10
SMC
19
P1_11
SMC
20
P1_12
SMC
21
P1_13
SMC
22
P1_14
SMC
23
P1_15
SMC
24
DVSS
supply
25
DVCC
supply
26
P1_16
SMC
27
P1_17
SMC
28
P1_18
SMC
29
P1_19
SMC
30
P1_20
SMC
31
P1_21
SMC
32
P1_22
SMC
33
P1_23
SMC
34
DVSS
supply
35
DVCC
supply
36
VDP3
supply
37
VSS
supply
38
P1_34
BIDI33
39
P1_35
BIDI33
40
P1_36
BIDI33
41
P1_37
BIDI33
Page 27
MB9DF126
MB9DF126B
Document Number: DS707-00002-4v1-E
Pin No
Pin Name
IO_Type
42
P1_38
BIDI33
43
VDD
supply
44
VSS
supply
45
P1_30
BIDI33
46
P1_31
BIDI33
47
P1_32
BIDI33
48
P1_33
BIDI33
49
P3_00
BIDI33
50
VDP3
supply
51
VSS
supply
52
P3_01
BIDI33
53
P3_02
BIDI33
54
P3_03
BIDI33
55
P3_04
BIDI33
56
P3_05
BIDI33
57
P3_06
BIDI33
58
P3_07
BIDI33
59
P3_08
BIDI33
60
P3_09
BIDI33
61
P3_10
BIDI33
62
P3_11
BIDI33
63
P3_12
BIDI33
64
VSS
supply
65
VDP3
supply
66
P1_24
BIDI33
67
P1_25
BIDI33
68
P3_33
BIDI33
69
P3_34
BIDI33
70
P3_35
BIDI33
71
P3_36
BIDI33
72
P3_37
BIDI33
73
P3_38
BIDI33
74
P3_39
BIDI33
75
P3_40
BIDI33
76
P3_41
BIDI33
77
P3_42
BIDI33
78
VDP3
supply
79
VSS
supply
80
P3_13
BIDI33
81
P3_14
BIDI33
82
P3_15
BIDI33
83
P3_16
BIDI33
Page 28
MB9DF126
MB9DF126B
Pin No
Pin Name
IO_Type
84
P3_17
BIDI33
85
P3_18
BIDI33
86
P3_19
BIDI33
87
P3_20
BIDI33
88
P3_21
BIDI33
89
VDD
supply
90
VSS
supply
91
P3_22
BIDI33
92
P3_23
BIDI33
93
P3_24
BIDI33
94
VDP3
supply
95
VSS
supply
96
P3_25
BIDI33
97
P3_26
BIDI33
98
P3_27
BIDI33
99
P3_28
BIDI33
100
P3_29
BIDI33
101
P3_30
BIDI33
102
P3_31
BIDI33
103
P3_32
BIDI33
104
P1_26
BIDI33
105
P1_27
BIDI33
106
P1_28
BIDI33
107
P1_29
BIDI33
108
VSS
supply
109
VDP3
supply
110
VSSA
supply
111
SDINP
SDIN
112
SDINM
SDIN
113
VDEA (3.3V)
supply
114
SDOUTM
SDOUT
115
VSSA
supply
116
SDOUTP
SDOUT
117
VDEA (3.3V)
supply
118
RREF
RREF
119
VDEA_VCO (3.3V)
supply
120
VSSA
supply
121
VDDA(1.2V)
supply
122
VSSA
supply
123
VDE5_OSC (5V)
supply
124
VSSA
supply
XTAL1
MAINOSC
(20MHz)
125
Document Number: DS707-00002-4v1-E
Page 29
MB9DF126
MB9DF126B
Document Number: DS707-00002-4v1-E
Pin No
Pin Name
IO_Type
126
XTAL0
MAINOSC
(20MHz)
127
VSS
supply
128
X0A
SUBOSC
129
X1A
SUBOSC
130
MODE
MODE
131
RSTX
MODE
132
VDP5
supply
133
VSS
supply
134
VDD
supply
135
VSS
supply
136
P0_40
BIDI50
137
P0_41
BIDI50
138
P0_42
BIDI50
139
P0_43
BIDI50
140
P0_44
BIDI50
141
P0_45
BIDI50
142
P0_46
BIDI50
143
P0_47
BIDI50
144
P0_48
BIDI50
145
P0_49
BIDI50
146
P0_50
BIDI50
147
P0_51
BIDI50
148
P0_62
I2C
149
P0_63
I2C
150
P2_32
BIDI50
151
P2_33
BIDI50
152
VDP5
supply
153
VSS
supply
154
P2_34
BIDI50
155
P2_35
BIDI50
156
P2_36
BIDI50
157
P2_37
BIDI50
158
P2_38
BIDI50
159
P2_39
BIDI50
160
P2_40
BIDI50
161
P2_41
BIDI50
162
P2_42
BIDI50
163
P2_43
BIDI50
164
P2_44
BIDI50
165
P2_45
BIDI50
166
P2_46
BIDI50
167
P2_47
BIDI50
Page 30
MB9DF126
MB9DF126B
Pin No
Document Number: DS707-00002-4v1-E
Pin Name
IO_Type
168
VSS
supply
169
VDP5
supply
170
JTAG_TDO
JTAGO
171
JTAG_TDI
JTAGIUP
172
JTAG_TCK
JTAGIUP
173
VSS
supply
174
VDD
supply
175
JTAG_TMS
JTAGIUP
176
JTAG_NTRST
JTAGIDN
Page 31
MB9DF126
MB9DF126B
Figure 3-4: Package Dimensions QFP-176
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
88
133
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
Document Number: DS707-00002-4v1-E
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 32
MB9DF126
MB9DF126B
3.1.3
IO Circuit Types
Table 3-3: IO Circuit Type
Type
Circuit
Remarks
High-speed oscillation circuit:
X1
MAINOSC
(20MHz
or 4MHz)
0
R
Xout
1
• Programmable between oscillation mode
(external crystal or resonator connected to X0/
X1pins, resp. XTAL0/XTAL1 pins) and Fast external Clock Input (FCI) mode (external clock
connected to X0 pin, resp. XTAL0 pin.
• Input frequency:
20MHz type
FCI
X0
4 MHz type
FCI or osc disable
• Low-speed oscillation circuit
X1A
SUBOSC
Xout
R
X0A
osc disable
• TTL level input pin
• Pull-down resistor value: approx. 50 k
R
JTAGIDN
Hysteresis
inputs
Pull−down
Resistor
• TTL level input pin
• Pull-up resistor value: approx. 50 k
JTAGIUP
Pull−up
Resistor
R
Document Number: DS707-00002-4v1-E
Hysteresis
inputs
Page 33
MB9DF126
MB9DF126B
Table 3-3: IO Circuit Type (Continued)
Type
Circuit
Remarks
• CMOS level output
• Output Driving strength is fixed:
Pout
JTAGO
IOL
IOH
+1 mA
-1 mA
Nout
ANE
AVRH5
• A/D converter ref+ (AVRH5) power supply
input pin with protection circuit
• Flash devices do not have a protection circuit
against VDP5 for pins AVRH5
AVR
ANE
• Hysteresis input pin
MODE
R
Document Number: DS707-00002-4v1-E
Hysteresis
input
Page 34
MB9DF126
MB9DF126B
Table 3-3: IO Circuit Type (Continued)
Type
Circuit
Remarks
• CMOS level output (programmable)
Pull−up control
ODR[1:0]
IOL
IOH
00
+1 mA
-1 mA
01
+2 mA
-2 mA
10
+5 mA
-5 mA
11
+2 mA
-2 mA
Pout
Nout
Pull−down control
R
BIDI50
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
CMOS input
Analog input
• Hysteresis input with input shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• CMOS input with input shutdown function
PIL[1:0]
Input buffer
Levels
00
Hysteresis
20% / 80%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
20% / 80%
• Programmable pull-up and pull-down resistor; 50 k approx.
• Analog input
• CMOS level output
Pull−up control
ODR[1:0]
IOL
IOH
-
+12 mA
-12 mA
Pout
Nout
BIDI33
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
Document Number: DS707-00002-4v1-E
• Hysteresis input with input shutdown function
• TTL input with input shutdown function
PIL[1:0]
Input buffer
Levels
00
Hysteresis
20% / 80%
10
TTL
0.8 V / 2 V
Hysteresis input
TTL input
• Programmable pull-up and pull-down resistor: 33 k approx.
Page 35
MB9DF126
MB9DF126B
Table 3-3: IO Circuit Type (Continued)
Type
Circuit
Remarks
• CMOS level output (programmable)
Pull−up control
ODR[1:0]
IOL
IOH
00
+1 mA
-1 mA
01
+2 mA
-2 mA
10
+30 mA
-30 mA
11
+5 mA
-5 mA
Pout
Nout
Pull−down control
R
Standby control
for input shutdown
SMC
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
• Hysteresis input with input shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• CMOS input with input shutdown function
PIL[1:0]
Input buffer
Levels
00
Hysteresis
20% / 80%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
20% / 80%
CMOS input
• Programmable pull-up resistor and pull
down resistor: 50 k approx.
Document Number: DS707-00002-4v1-E
Page 36
MB9DF126
MB9DF126B
Table 3-3: IO Circuit Type (Continued)
Type
Circuit
Remarks
• CMOS level output (programmable)
Pull−up control
Pout
I2C_enable
Nout
ODR[1:0]
I2C_enable
IOL
IOH
00
0
+1 mA
-1 mA
01
0
+2 mA
-2 mA
10
0
+5 mA
-5 mA
11
0
+2 mA
-2 mA
*
1
+3 mA
(Pseudo Open
Drain)*1
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Automotive input
I2C
Standby control
for input shutdown
Standby control
for input shutdown
TTL input
CMOS input
• Hysteresis input with input shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• CMOS input with input shutdown function
• I2C_enable is high, when the corresponding
PCFGRxxx_POF value is set to I2C function
and the I2C interface module is enabled.
Note: *1: For Pseudo Open Drain output logic
value “1”, Push/Pull CMOS driver is
switched to HIZ state.
PIL[1:0]
Input buffer
Levels
00
Hysteresis
30% / 70%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
30% / 70%
• Programmable pull-up resistor and pulldown resistor: 50 k approx.
VDEA (3.3V)
SDIN /
SDOUT /
RREF
Document Number: DS707-00002-4v1-E
Analog Line
• Analog terminal
• Type SDIN: Analog input pin with ESD protection
• Type SDOUT: Analog output line with ESD
protection
• Type RREF: Analog output line with ESD
protection
Page 37
MB9DF126
MB9DF126B
3.2
I/O Pins and their functions
IO Pin configuration needs to be done by writing into Port Pin Multiplexing registers and Resource Input Configuration registers which are described in Section 3.2.1 and Section 3.2.2 respectively. The access to the PPC_PCFGRiij registers must be enabled before starting IO Pin configuration by setting the corresponding bit of the GPIO_
PPERn, where n denotes the port number to which the GPIO_PPERn belongs.
Note:
The corresponding GPIO_PPERn register bit must be set for both Port Pin Multiplexing and Resource input sourceMultiplexing registers. GPIO_PPERn can only be written in priviledged mode and each byte can be written only
once. In priviledged mode, access to the PPC registers must be enabled on the PPU channel PPCPRIV (see chapter 4.4).
3.2.1
Port Pin Multiplexing table
Table 3-4: Port Pin Multiplexing table
Register
(offset)
PPC_PCFGR040
(0x0050)
PPC_PCFGR041
(0x0052)
PPC_PCFGR042
(0x0054)
PPC_PCFGR043
(0x0056)
PPC_PCFGR044
(0x0058)
Port
P0_40
P0_41
P0_42
P0_43
P0_44
Resource functional output
POF=0
GPIO0_40
GPIO0_41
GPIO0_42
GPIO0_43
GPIO0_44
POF=1
SPI2_SS
SPI2_DATA1
SPI2_DATA0
SPI2_CLK
SPI0_SS
Document Number: DS707-00002-4v1-E
POF=2
POF=3
PPG64_
PPGB
RTC_WOT
SYSC_
CKOT
SYSC_CKOTX
WDG_OBSERVE
SPI2_SSO2
POF=4
USART6_
SCK
USART6_
SOT
CAN0_TX
SPI2_DATA2
PPG65_
PPGB
PPG66_
PPGB
PPG67_
PPGB
PPG68_
PPGB
POF=5
OCU16_
OTD0_G
POF=6
ARH0_
AIC0_TDA1
OCU16_
OTD1_G
OCU17_
OTD0_G
RLT2_TOT
OCU17_
OTD1_G
OCU0_
OTD0_G
RLT3_TOT
POF=7
Possible Resource Function
Input
PPG8_
PPGA
GPIO0_40,
EIC0_INT05,
EIC0_INT12,
EIC0_INT11,
SPI2_SS,
USART6_SIN,
USART0_SIN,
FRT0_FRCK, RLT5_
TIN, ADC0_AN15
PPG9_
PPGA
GPIO0_41,
EIC0_INT15,
SPI2_DATA1,
USART6_SCK,
USART0_SCK,
FRT1_FRCK, RLT6TIN,
ARH0_AIC0_TCKI,
ICU2_IN0,
ICU18_IN1,
ADC0_AN16
PPG10_
PPGA
GPIO0_42,
EIC0_INT08,
EIC0_INT10,
EIC0_INT11,
SPI2_DATA0,
CAN0_RX,
CAN2_RX,
FRT2_FRCK,
ARH0_AIC0_RCK,
ICU2_IN1,
ICU19_IN0,
USART0_SIN,
ADC0_AN17
PPG11_
PPGA
GPIO0_43,
EIC0_INT09,
SPI2_CLK,
CAN1_RX,
FRT3_FRCK,
RLT2_TIN,
ARH0_AIC0_RDA1,
ADC0_AN18
PPG12_
PPGA
GPIO0_44,
EIC0_INT03,
SPI2_DATA2,
SPI0_SS,
FRT16_FRCK,
ARH0_AIC0_RDA0,
UDC0_AIN0,
ADC0_AN19
Page 38
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR045
(0x005A)
PPC_PCFGR046
(0x005C)
PPC_PCFGR047
(0x005E)
PPC_PCFGR048
(0x0060)
PPC_PCFGR049
(0x0062)
PPC_PCFGR050
(0x0064)
Port
P0_45
P0_46
P0_47
P0_48
P0_49
P0_50
Resource functional output
POF=0
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
POF=1
SPI0_DATA1
SPI0_DATA0
SPI0_CLK
SPI1_SS
SPI1_DATA1
POF=2
SPI2_SSO3
SPI2_SSO1
UDC0_
UDOT0
SPI0_SSO2
SPI0_SSO1
SPI1_DATA0
SPI0_SSO3
UDC0_
UDOT1
POF=3
SPI2_DATA3
USART0_
SCK
USART0_
SOT
SPI0_DATA2
CAN1_TX
POF=4
PPG69_
PPGB
PPG70_
PPGB
PPG71_
PPGB
PPG0_
PPGB
PPG1_
PPGB
POF=5
OCU0_
OTD1_G
OCU1_
OTD0_G
POF=6
ARH0_
AIC0_TDA0
ARH0_
AIC1_TDA1
OCU1_
OTD1_G
OCU0_
OTD0
OCU0_
OTD1
RLT4_TOT
RLT0_TOT
POF=7
Possible Resource Function
Input
PPG13_
PPGA
GPIO0_45, EIC0_
INT11, EIC0_INT12,
FRT16_FRCK,
FRT18_FRCK,
SPI2_DATA3, SPI0_
DATA1, USART0_
SIN, USART6_SIN,
FRT17_FRCK,
RLT3_TIN, FRT19_
FRCK, UDC0_BIN0,
ADC0_AN20
PPG14_
PPGA
GPIO0_46, EIC0_
INT16, SPI0_DATA0,
USART0_SCK, USART6_SCK, FRT18_
FRCK, RLT4_TIN,
UDC0_ZIN0, ICU18_
IN0, ADC0_AN21
PPG15_
PPGA
GPIO0_47, FRT0_
FRCK, FRT1_FRCK,
FRT2_FRCK, EIC0_
INT17, FRT3_FRCK,
SPI0_CLK, FRT16_
FRCK, FRT17_
FRCK, FRT19_
FRCK, RLT0_TIN,
FRT18_FRCK,
ARH0_AIC1_TCKI,
EIC0_INT12, ICU18_
IN1, USART6_SIN,
ADC0_AN22
PPG64_
PPGA
GPIO0_48, EIC0_
INT04, EIC0_INT09,
EIC0_INT08, SPI0_
DATA2, SPI1_SS,
CAN1_RX, CAN0_
RX, ICU2_IN0,
ARH0_AIC1_RCK,
UDC0_AIN1, ADC0_
AN23
PPG65_
PPGA
GPIO0_49, EIC0_
INT10, SPI1_DATA1,
CAN2_RX, ICU2_
IN1, ARH0_AIC1_
RDA1, UDC0_BIN1,
ADC0_AN24
SPI0_DATA3
PPG2_
PPGB
OCU1_
OTD0
RLT1_TOT
PPG66_
PPGA
GPIO0_50, EIC0_
INT10, EIC0_INT09,
SPI0_DATA3, SPI1_
DATA0, CAN2_RX,
CAN1_RX, ICU3_
IN0, ARH0_AIC1_
RDA0, UDC0_ZIN1,
ADC0_AN25
CAN2_TX
PPG3_
PPGB
OCU1_
OTD1
ARH0_
AIC1_TDA0
PPG67_
PPGA
GPIO0_51, EIC0_
INT08, SPI1_CLK,
CAN0_RX, ICU3_
IN1, RLT1_TIN,
ADC0_EDGI
PPC_PCFGR051
(0x0066)
P0_51
GPIO0_51
SPI1_CLK
PPC_PCFGR062
(0x007C)
P0_62
GPIO0_62
I2C0_SCL
GPIO0_62, EIC0_
INT24, I2C0_SCL
PPC_PCFGR063
(0x007E)
P0_63
GPIO0_63
I2C0_SDA
GPIO0_63, EIC0_
INT00, I2C0_SDA
PPC_PCFGR100
(0x0080)
P1_00
GPIO1_00
SMC0_M2
Document Number: DS707-00002-4v1-E
ARH0_
AIC0_DNCLK
PPG64_
PPGB
PPG0_
PPGA
GPIO1_00, CAN0_
RX, EIC0_INT08,
EIC0_INT25, ARH0_
AIC0_TCKI, ADC0_
AN26
Page 39
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR101
(0x0082)
PPC_PCFGR102
(0x0084)
Port
P1_01
P1_02
Resource functional output
POF=0
GPIO1_01
GPIO1_02
POF=1
POF=2
POF=3
POF=4
PPG65_
PPGB
SMC0_P2
POF=5
POF=6
CAN0_TX
PPG66_
PPGB
SMC0_M1
POF=7
Possible Resource Function
Input
PPG1_
PPGA
GPIO1_01,
EIC0_INT26,
ARH0_AIC0_UPCLK,
ARH0_AIC0_RCK,
ADC0_AN26
PPG2_
PPGA
GPIO1_02,
EIC0_INT13,
CAN1_RX,
EIC0_INT09,
ARH0_AIC0_UPDATA1,
ARH0_AIC0_RDA1,
ADC0_AN26
PPG3_
PPGA
GPIO1_03,
EIC0_INT27,
ARH0_AIC0_UPDATA0,
ARH0_AIC0_RDA0,
ADC0_AN26
PPC_PCFGR103
(0x0086)
P1_03
GPIO1_03
SMC0_P1
PPC_PCFGR104
(0x0088)
P1_04
GPIO1_04
SMC1_M2
ARH0_
AIC0_DNDATA1
ARH0_
AIC0_TDA1
PPG68_
PPGB
PPG4_
PPGA
GPIO1_04,
EIC0_INT28,
ADC0_AN27
PPC_PCFGR105
(0x008A)
P1_05
GPIO1_05
SMC1_P2
ARH0_
AIC0_DNDATA0
ARH0_
AIC0_TDA0
PPG69_
PPGB
PPG5_
PPGA
GPIO1_05,
EIC0_INT29,
ADC0_AN27
PPC_PCFGR106
(0x008C)
P1_06
GPIO1_06
SMC1_M1
ARH0_
AIC1_DNDATA1
ARH0_
AIC1_TDA1
PPG70_
PPGB
PPG6_
PPGA
GPIO1_06,
EIC0_INT30,
ADC0_AN27
PPC_PCFGR107
(0x008E)
P1_07
GPIO1_07
SMC1_P1
ARH0_
AIC1_DNDATA0
ARH0_
AIC1_TDA0
PPG71_
PPGB
PPG7_
PPGA
GPIO1_07,
EIC0_INT31,
ADC0_AN27
PPG8_
PPGA
GPIO1_08,
USART0_SIN,
RLT3_TIN,
EIC0_INT00,
SPI0_SS,
ADC0_AN28,
EIC0_INT03,
EIC0_INT11
PPG9_
PPGA
GPIO1_09,
USART0_SCK,
RLT4_TIN,
EIC0_INT01,
SPI0_DATA1,
ICU2_IN1,
ADC0_AN28
PPG10_
PPGA
GPIO1_10,
EIC0_INT02,
ARH0_AIC0_dbg_
select,
SPI0_DATA0,
ICU2_IN0,
ADC0_AN28
PPG11_
PPGA
GPIO1_11,
EIC0_INT03,
SPI0_CLK,
RLT0_TIN,
ADC0_AN28
PPG12_
PPGA
GPIO1_12,
USART6_SIN,
RLT5_TIN,
EIC0_INT04,
SPI1_SS,
ADC0_AN29,
EIC0_INT12
PPC_PCFGR108
(0x0090)
PPC_PCFGR109
(0x0092)
PPC_PCFGR110
(0x0094)
PPC_PCFGR111
(0x0096)
PPC_PCFGR112
(0x0098)
P1_08
P1_09
P1_10
P1_11
P1_12
GPIO1_08
GPIO1_09
GPIO1_10
GPIO1_11
GPIO1_12
SMC2_M2
SMC2_P2
PPG67_
PPGB
ARH0_
AIC0_dbg_
out_0
ARH0_
AIC0_dbg_
out_1
PPG0_
PPGB
PPG1_
PPGB
SMC2_M1
PPG2_
PPGB
SMC2_P1
PPG3_
PPGB
SMC3_M2
Document Number: DS707-00002-4v1-E
ARH0_
AIC1_dbg_
out_0
PPG4_
PPGB
CAN1_TX
SPI0_SS
SPI0_DATA1
SPI0_DATA0
SPI0_CLK
SPI1_SS
USART0_
SCK
USART0_
SOT
Page 40
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR113
(0x009A)
PPC_PCFGR114
(0x009C)
PPC_PCFGR115
(0x009E)
Port
P1_13
P1_14
P1_15
Resource functional output
POF=0
GPIO1_13
GPIO1_14
GPIO1_15
POF=1
SMC3_P1
PPG7_
PPGB
SMC4_M2
PPC_PCFGR117
(0x00A2)
P1_17
GPIO1_17
SMC4_P2
SMC4_M1
SPI2_DATA1
SPI1_SSO1
PPG65_
PPGA
GPIO1_17,
EIC0_INT14,
SPI2_DATA1,
ADC0_AN30
SG0_SGA
DMA0_
DREQ_
ACK1
PPG10_
PPGB
SPI2_DATA0
SPI1_SSO3
PPG66_
PPGA
GPIO1_18,
EIC0_INT15,
SPI2_DATA0,
ICU18_IN0,
ADC0_AN30
PPG11_
PPGB
PPG67_
PPGA
GPIO1_19,
EIC0_INT16,
SPI2_CLK,
ICU19_IN1,
RLT2_TIN,
ADC0_AN30
PPG12_
PPGB
PPG68_
PPGA
GPIO1_20,
EIC0_INT17,
ARH0_AIC1_TCKI,
ADC0_AN31
PPG69_
PPGA
GPIO1_21,
EIC0_INT18,
ARH0_AIC1_UPCLK,
DMA0_DREQ1,
ARH0_AIC1_RCK,
ADC0_AN31
PPG70_
PPGA
GPIO1_22,
EIC0_INT19,
ARH0_AIC1_UPDATA1,
DMA0_DSTP1,
ARH0_AIC1_RDA1,
ADC0_AN31
PPG71_
PPGA
GPIO1_23,
EIC0_INT20,
ARH0_AIC1_UPDATA0,
DMA0_DEOP_
ACK1,
ARH0_AIC1_RDA0,
ADC0_AN31
P1_20
GPIO1_20
SMC5_M2
ARH0_
AIC1_DNCLK
DMA0_
DEOP1
PPC_PCFGR123
(0x00AE)
P1_23
GPIO1_23
SMC5_M1
SMC5_P1
Document Number: DS707-00002-4v1-E
GPIO1_15,
EIC0_INT07,
SPI1_CLK,
RLT1_TIN,
ADC0_AN29
PPG9_
PPGB
PPC_PCFGR120
(0x00A8)
GPIO1_22
PPG15_
PPGA
CAN2_TX
SG0_SGO
P1_22
SPI1_CLK
PPG14_
PPGA
GPIO1_14,
EIC0_INT06,
ARH0_AIC1_dbg_
select,
SPI1_DATA0,
ICU19_IN1,
ADC0_AN29
PPG64_
PPGA
SMC4_P1
PPC_PCFGR122
(0x00AC)
USART6_
SOT
PPG13_
PPGA
GPIO1_13,
USART6_SCK,
RLT6_TIN,
EIC0_INT05,
SPI1_DATA1,
ICU18_IN0,
ADC0_AN29
SPI1_SSO2
GPIO1_19
SMC5_P2
SPI1_DATA0
USART6_
SCK
POF=7
SPI2_SS
P1_19
GPIO1_21
SPI1_DATA1
POF=6
PPG8_
PPGB
DMA0_
DSTP_
ACK1
P1_21
POF=5
GPIO1_16,
CAN2_RX,
EIC0_INT10,
EIC0_INT13,
SPI2_SS,
ADC0_AN30,
EIC0_INT05
PPC_PCFGR119
(0x00A6)
PPC_PCFGR121
(0x00AA)
PPG5_
PPGB
PPG6_
PPGB
GPIO1_16
GPIO1_18
POF=4
SMC3_M1
P1_16
P1_18
POF=3
ARH0_
AIC1_dbg_
out_1
SMC3_P2
PPC_PCFGR116
(0x00A0)
PPC_PCFGR118
(0x00A4)
POF=2
Possible Resource Function
Input
PPG13_
PPGB
PPG14_
PPGB
PPG15_
PPGB
SPI2_CLK
Page 41
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR124
(0x00B0)
PPC_PCFGR125
(0x00B2)
PPC_PCFGR126
(0x00B4)
Port
P1_24
P1_25
P1_26
Resource functional output
POF=0
GPIO1_24
GPIO1_25
GPIO1_26
POF=1
POF=2
DBG0_
TRACE6
DMA0_
DREQ_
ACK0
DBG0_
TRACE7
DMA0_
DSTP_
ACK0
DBG0_
TRACE0
DMA0_
DEOP0
POF=3
ARH0_
AIC1_DNCLK
I2S1_SD
I2S1_WS
POF=4
PPG5_
PPGB
PPG6_
PPGB
PPG7_
PPGB
POF=5
OCU16_
OTD1
OCU17_
OTD0
POF=6
EBI0_
MAD13
EBI0_
MAD14
OCU17_
OTD1
POF=7
Possible Resource Function
Input
PPG69_
PPGA
GPIO1_24,
EIC0_INT19,
I2S0_ECLK,
I2S1_ECLK,
ARH0_AIC1_TCKI,
ICU18_IN1
PPG70_
PPGA
GPIO1_25,
EIC0_INT20,
I2S1_SD,
ARH0_AIC1_RCK,
ICU19_IN0,
ARH0_AIC1_UPCLK
PPG71_
PPGA
GPIO1_26,
EIC0_INT07,
I2S1_WS,
ARH0_AIC1_RDA1,
ICU19_IN1,
ARH0_AIC1_UPDATA1
GPIO1_27,
EIC0_INT21,
DMA0_DREQ0,
I2S1_SCK,
ARH0_AIC1_RDA0,
ARH0_AIC1_UPDATA0
PPC_PCFGR127
(0x00B6)
P1_27
GPIO1_27
DBG0_
TRACE1
PPC_PCFGR128
(0x00B8)
P1_28
GPIO1_28
DBG0_CTL
ARH0_
AIC1_TDA1
ARH0_
AIC1_DNDATA1
RLT3_TOT
GPIO1_28,
EIC0_INT22,
DMA0_DSTP0
PPC_PCFGR129 (0x00- P1_29
BA)
GPIO1_29
DBG0_CLK
ARH0_
AIC1_TDA0
ARH0_
AIC1_DNDATA0
RLT4_TOT
GPIO1_29,
EIC0_INT23,
DMA0_DEOP_ACK0
PPC_PCFGR130
(0x00BC)
P1_30
I2S1_SCK
GPIO1_30
HSSPI0_
SSO3
OCU0_
OTD0
OCU0_
OTD1
DBG0_
TRACE2
EBI0_
MAD15
GPIO1_30,
EIC0_INT11,
PPG_ETRG2,
USART0_SIN,
RLT3_TIN,
ADC0_EDGI
USART0_
SCK
DBG0_
TRACE3
EBI0_
MAD16
GPIO1_31,
EIC0_INT24,
USART0_SCK,
ICU3_IN1,
RLT4_TIN
PPC_PCFGR131
(0x00BE)
P1_31
GPIO1_31
HSSPI0_
SSO2
PPC_PCFGR132
(0x00C0)
P1_32
GPIO1_32
HSSPI0_
SSO1
OCU1_
OTD0
USART0_
SOT
DBG0_
TRACE4
EBI0_
MAD17
GPIO1_32,
EIC0_INT25,
ICU3_IN0
PPC_PCFGR133
(0x00C2)
P1_33
GPIO1_33
HSSPI0_
SS
OCU1_
OTD1
CAN0_TX
DBG0_
TRACE5
EBI0_
MAD18
GPIO1_33,
EIC0_INT01,
HSSPI0_SS
GPIO1_34
HSSPI0_
DATA3
EBI0_
MAD19
GPIO1_34,
EIC0_INT08,
HSSPI0_DATA3,
CAN0_RX,
UDC0_AIN0
GPIO1_35
HSSPI0_
DATA2
EBI0_
MAD20
GPIO1_35,
EIC0_INT26,
HSSPI0_DATA2,
ICU2_IN0,
UDC0_BIN0
EBI0_
MAD21
GPIO1_36,
EIC0_INT09,
HSSPI0_DATA1,
CAN1_RX,
ICU2_IN1,
UDC0_ZIN0
PPC_PCFGR134
(0x00C4)
PPC_PCFGR135
(0x00C6)
PPC_PCFGR136
(0x00C8)
P1_34
P1_35
P1_36
GPIO1_36
HSSPI0_
DATA1
Document Number: DS707-00002-4v1-E
CAN1_TX
ARH0_
AIC0_dbg_
out_0
ARH0_
AIC0_dbg_
out_1
Page 42
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
Port
PPC_PCFGR137 (0x00- P1_37
CA)
PPC_PCFGR138
(0x00CC)
PPC_PCFGR232
(0x0140)
PPC_PCFGR233
(0x0142)
PPC_PCFGR234
(0x0144)
PPC_PCFGR235
(0x0146)
PPC_PCFGR236
(0x0148)
P1_38
P2_32
P2_33
P2_34
P2_35
P2_36
Resource functional output
POF=0
POF=1
GPIO1_37
HSSPI0_
DATA0
GPIO1_38
HSSPI0_
CLK
GPIO2_32
GPIO2_33
GPIO2_34
GPIO2_35
GPIO2_36
SPI2_SS
SPI2_DATA1
SPI2_DATA0
SPI2_CLK
SPI1_SS
Document Number: DS707-00002-4v1-E
POF=2
UDC0_
UDOT0
UDC0_
UDOT0
I2S0_SD
POF=3
POF=5
CAN2_TX
SPI1_DATA2
SPI1_DATA3
PPG8_
PPGB
PPG9_
PPGB
PPG10_
PPGB
I2S0_WS
PPG11_
PPGB
I2S0_SCK
UDC0_
UDOT1
POF=4
ARH0_
AIC0_TDA1
PPG12_
PPGB
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
OCU16_
OTD0
POF=6
POF=7
Possible Resource Function
Input
RLT5_TOT
EBI0_
MAD22
GPIO1_37,
EIC0_INT13,
HSSPI0_DATA0,
ARH0_AIC0_dbg_
select,
ICU3_IN0
RLT6_TOT
EBI0_
MAD23
GPIO1_38,
EIC0_INT10,
HSSPI0_CLK,
CAN2_RX,
ICU3_IN1
PPG0_
PPGA
GPIO2_32,
I2S0_ECLK,
I2S1_ECLK,
SPI1_DATA2,
ARH0_AIC0_RCK,
SPI2_SS,
SPI0_SS,
ICU2_IN0,
ARH0_AIC0_UPCLK,
EIC0_INT05,
EIC0_INT03,
ADC0_EDGI
PPG1_
PPGA
GPIO2_33,
I2S0_SD,
I2S1_SD,
SPI1_DATA3,
UDC0_AIN0,
ARH0_AIC0_RDA1,
SPI2_DATA1,
SPI0_DATA1,
ICU2_IN1,
ARH0_AIC0_UPDATA1,
EIC0_INT26,
ADC0_AN0
PPG2_
PPGA
GPIO2_34,
I2S0_WS,
I2S1_WS,
UDC0_BIN0,
ARH0_AIC0_RDA0,
SPI2_DATA0,
SPI0_DATA0,
ICU3_IN0,
ARH0_AIC0_UPDATA0,
EIC0_INT06,
EIC0_INT07,
ADC0_AN1
PPG3_
PPGA
GPIO2_35,
I2S0_SCK,
I2S1_SCK,
UDC0_ZIN0,
ARH0_AIC0_TCKI,
SPI2_CLK,
SPI0_CLK,
RLT2_TIN,
ICU3_IN1,
EIC0_INT29,
ADC0_AN2
PPG4_
PPGA
GPIO2_36,
I2S1_ECLK,
I2S0_ECLK,
SPI1_SS,
SPI2_SS,
RLT9_TIN,
ICU18_IN0,
EIC0_INT04,
EIC0_INT05,
ADC0_AN3
RLT9_TOT
RLT8_TOT
RLT7_TOT
ARH0_
AIC0_DNCLK
ARH0_
AIC0_DNDATA1
Page 43
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR237
(0x014A)
PPC_PCFGR238
(0x014C)
PPC_PCFGR239
(0x014E)
PPC_PCFGR240
(0x0150)
PPC_PCFGR241
(0x0152)
PPC_PCFGR242
(0x0154)
Port
P2_37
P2_38
P2_39
P2_40
P2_41
P2_42
Resource functional output
POF=0
GPIO2_37
GPIO2_38
GPIO2_39
GPIO2_40
GPIO2_41
GPIO2_42
POF=1
SPI1_DATA1
SPI1_DATA0
SPI1_CLK
SPI0_SS
SPI0_DATA1
SPI0_DATA0
Document Number: DS707-00002-4v1-E
POF=2
I2S1_SD
POF=3
ARH0_
AIC0_TDA0
PPG13_
PPGB
PPG14_
PPGB
I2S1_WS
PPG15_
PPGB
I2S1_SCK
PPG64_
PPGB
CAN0_TX
PPG65_
PPGB
I2S0_SD
I2S0_WS
POF=4
SG0_SGA
PPG66_
PPGB
POF=5
OCU16_
OTD1
POF=6
ARH0_
AIC0_DNDATA0
OCU17_
OTD0
OCU17_
OTD1
OCU0_
OTD1_I
OCU0_
OTD0_I
OCU0_
OTD1_GI
RLT8_TOT
RLT9_TOT
POF=7
Possible Resource Function
Input
PPG5_
PPGA
GPIO2_37,
I2S1_SD,
I2S0_SD,
UDC0_AIN1,
SPI1_DATA1,
SPI2_DATA1,
RLT8_TIN,
ICU18_IN1,
EIC0_INT30,
ADC0_AN4
PPG6_
PPGA
GPIO2_38,
I2S1_WS,
I2S0_WS,
PPG_ETRG0,
UDC0_BIN1,
SPI1_DATA0,
SPI2_DATA0,
RLT7_TIN,
ICU19_IN0,
EIC0_INT06,
EIC0_INT07,
ADC0_AN5
PPG7_
PPGA
GPIO2_39,
I2S1_SCK,
I2S0_SCK,
PPG_ETRG1,
UDC0_ZIN1,
SPI1_CLK,
SPI2_CLK,
RLT1_TIN,
ICU19_IN1,
EIC0_INT31,
ADC0_AN6
PPG8_
PPGA
GPIO2_40,
I2S0_ECLK,
CAN2_RX,
ARH0_AIC1_RCK,
SPI0_SS,
SPI1_SS, ICU2_IN0,
FRT16_FRCK,
ARH0_AIC1_UPCLK,
EIC0_INT03,
EIC0_INT04, EIC0_
INT10,
ADC0_AN7
PPG9_
PPGA
GPIO2_41,
I2S0_SD,
CAN0_RX,
CAN1_RX,
ARH0_AIC1_RDA1,
SPI0_DATA1,
SPI1_DATA1,
RLT8_TIN,
ICU2_IN1,
FRT17_FRCK,
ARH0_AIC1_UPDATA1,
EIC0_INT08,
EIC0_INT09,
ADC0_AN8
PPG10_
PPGA
GPIO2_42,
I2S0_WS,
ARH0_AIC1_RDA0,
SPI0_DATA0,
SPI1_DATA0,
RLT9_TIN,
ICU3_IN0,
FRT18_FRCK,
ARH0_AIC1_UPDATA0,
EIC0_INT06,
ADC0_AN9
Page 44
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR243
(0x0156)
PPC_PCFGR244
(0x0158)
PPC_PCFGR245
(0x015A)
PPC_PCFGR246
(0x015C)
PPC_PCFGR247
(0x015E)
PPC_PCFGR300
(0x0180)
PPC_PCFGR301
(0x0182)
Port
P2_43
P2_44
P2_45
P2_46
P2_47
P3_00
P3_01
Resource functional output
POF=0
GPIO2_43
GPIO2_44
GPIO2_45
POF=1
SPI0_CLK
ARH0_
AIC1_DNDATA1
ARH0_
AIC1_DNDATA0
GPIO2_46
GPIO2_47
I2S0_SCK
CAN1_TX
I2S1_SD
I2S1_WS
CAN2_TX
I2S1_SCK
OCU16_
OTD0
GPIO3_00
GPIO3_01
POF=2
USART6_
SCK
Document Number: DS707-00002-4v1-E
OCU16_
OTD1
POF=3
SG0_SGO
ARH0_
AIC1_TDA1
ARH0_
AIC1_TDA0
SG0_SGA
SG0_SGO
POF=4
PPG67_
PPGB
PPG68_
PPGB
PPG69_
PPGB
PPG70_
PPGB
PPG71_
PPGB
POF=5
OCU0_
OTD0_GI
OCU16_
OTD1_I
POF=6
ARH0_
AIC1_DNCLK
RLT7_TOT
OCU16_
OTD0_I
OCU16_
OTD1_GI
OCU16_
OTD0_GI
RLT5_TOT
RLT6_TOT
POF=7
Possible Resource Function
Input
PPG11_
PPGA
GPIO2_43,
I2S0_SCK,
EIC0_NMI,
ARH0_AIC1_TCKI,
SPI0_CLK,
SPI1_CLK,
RLT0_TIN,
ICU3_IN1,
FRT19_FRCK,
ADC0_AN10
PPG12_
PPGA
GPIO2_44,
I2S1_ECLK,
CAN0_RX,
ICU18_IN0,
FRT0_FRCK,
EIC0_INT08,
ADC0_AN11
PPG13_
PPGA
GPIO2_45,
I2S1_SD,
CAN1_RX,
CAN2_RX,
FRT0_FRCK,
RLT7_TIN,
ICU18_IN1,
FRT1_FRCK,
FRT2_FRCK,
FRT3_FRCK,
EIC0_INT09,
EIC0_INT10,
ADC0_AN12
PPG14_
PPGA
GPIO2_46,
I2S1_WS,
CAN2_RX,
CAN0_RX,
ICU19_IN0,
FRT2_FRCK,
EIC0_INT07,
EIC0_INT10,
EIC0_INT08,
ADC0_AN13
PPG15_
PPGA
GPIO2_47,
I2S1_SCK,
FRT2_FRCK,
CAN1_RX,
FRT16_FRCK,
FRT17_FRCK,
FRT18_FRCK,
ICU19_IN1,
FRT3_FRCK,
FRT19_FRCK,
FRT0_FRCK,
FRT1_FRCK,
EIC0_INT09,
ADC0_AN14
EBI0_
MAD00
GPIO3_00,
EIC0_INT12,
EIC0_INT11,
USART6_SIN,
RLT5_TIN,
USART0_SIN
EBI0_
MAD01
GPIO3_01,
EIC0_INT27,
PPG_ETRG3,
USART6_SCK,
ICU3_IN1,
RLT6_TIN,
ADC0_EDGI,
USART0_SCK
Page 45
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
Port
Resource functional output
POF=0
POF=1
POF=2
USART6_
SOT
OCU17_
OTD0
PPC_PCFGR302
(0x0184)
P3_02
GPIO3_02
PPC_PCFGR303
(0x0186)
P3_03
GPIO3_03
PPC_PCFGR304
(0x0188)
PPC_PCFGR305
(0x018A)
PPC_PCFGR306
(0x018C)
P3_04
P3_05
P3_06
OCU17_
OTD1
GPIO3_06
PPG6_
PPGA
PPG7_
PPGA
GPIO3_04
GPIO3_05
POF=3
USART0_
SOT
POF=5
PPG70_
PPGB
POF=6
POF=7
RLT3_TOT
EBI0_
MAD02
GPIO3_02,
EIC0_INT11,
EIC0_INT28,
ICU3_IN0,
USART0_SIN
RLT4_TOT
EBI0_
MAD03
GPIO3_03,
EIC0_INT02
EBI0_
MAD04
GPIO3_04,
EIC0_INT11,
EIC0_INT12,
USART0_SIN,
ICU18_IN0,
RLT3_TIN,
UDC0_AIN1,
USART6_SIN
EBI0_
MAD05
GPIO3_05,
EIC0_INT29,
USART0_SCK,
ICU18_IN1,
RLT4_TIN,
UDC0_BIN1,
USART6_SCK
EBI0_
MAD06
GPIO3_06,
EIC0_INT12,
EIC0_INT30,
ICU19_IN0,
UDC0_ZIN1,
USART6_SIN
PPG71_
PPGB
PPG0_
PPGB
ARH0_
AIC1_dbg_
out_0
PPG9_
PPGA
PPG1_
PPGB
ARH0_
AIC1_dbg_
out_1
PPG10_
PPGA
PPG2_
PPGB
EBI0_
MAD07
GPIO3_07,
EIC0_INT31,
ARH0_AIC1_dbg_
select,
ICU19_IN1
PPG11_
PPGA
PPG3_
PPGB
EBI0_
MAD08
GPIO3_08,
EIC0_INT00
PPG8_
PPGA
USART0_
SCK
POF=4
Possible Resource Function
Input
PPC_PCFGR307
(0x018E)
P3_07
GPIO3_07
PPC_PCFGR308
(0x0190)
P3_08
GPIO3_08
SPI0_SSO3
PPC_PCFGR309
(0x0192)
P3_09
GPIO3_09
SPI2_SS
OCU0_
OTD1_I
PPG12_
PPGA
PPG4_
PPGB
EBI0_
MAD09
GPIO3_09,
SPI2_SS,
EIC0_INT05
PPC_PCFGR310
(0x0194)
P3_10
GPIO3_10
SPI2_DATA1
OCU0_
OTD0_I
PPG13_
PPGA
PPG5_
PPGB
EBI0_
MAD10
GPIO3_10,
EIC0_INT02,
SPI2_DATA1
PPC_PCFGR311
(0x0196)
P3_11
GPIO3_11
SPI2_DATA0
OCU0_
OTD1_GI
PPG14_
PPGA
PPG6_
PPGB
EBI0_
MAD11
GPIO3_11,
EIC0_INT14,
SPI2_DATA0
PPC_PCFGR312
(0x0198)
P3_12
GPIO3_12
SPI2_CLK
OCU0_
OTD0_GI
PPG15_
PPGA
PPG7_
PPGB
EBI0_
MAD12
GPIO3_12,
EIC0_INT15,
SPI2_CLK,
RLT2_TIN
PPC_PCFGR313
(0x019A)
P3_13
GPIO3_13
SPI2_DATA2
UDC0_
UDOT0
PPG64_
PPGA
PPG8_
PPGB
EBI0_
MCSX0
GPIO3_13,
EIC0_INT16,
SPI2_DATA2,
ICU2_IN0
GPIO3_14
SPI2_DATA3
PPG65_
PPGA
PPG9_
PPGB
EBI0_
MCSX1
GPIO3_14,
EIC0_INT17,
SPI2_DATA3,
ICU2_IN1,
UDC0_AIN0
EBI0_
MCSX2
GPIO3_15,
EIC0_INT18,
ICU3_IN0,
ARH0_AIC1_RCK,
UDC0_BIN0,
ARH0_AIC1_UPCLK
PPC_PCFGR314
(0x019C)
PPC_PCFGR315
(0x019E)
P3_14
P3_15
GPIO3_15
UDC0_
UDOT1
SPI0_SSO1
Document Number: DS707-00002-4v1-E
PPG66_
PPGA
PPG10_
PPGB
EBI0_
MCSX8
EBI0_MDQM1
Page 46
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR316
(0x01A0)
PPC_PCFGR317
(0x01A2)
PPC_PCFGR318
(0x01A4)
PPC_PCFGR319
(0x01A6)
Port
P3_16
P3_17
P3_18
P3_19
Resource functional output
POF=0
GPIO3_16
GPIO3_17
GPIO3_18
GPIO3_19
POF=1
POF=2
PPG67_
PPGA
SPI0_SSO2
SPI2_SSO2
POF=3
UDC0_
UDOT1
PPG68_
PPGA
PPG69_
PPGA
SPI2_SSO1
SPI1_DATA2
PPG70_
PPGA
POF=4
POF=5
POF=6
PPG11_
PPGB
POF=7
EBI0_
MCSX3
Possible Resource Function
Input
GPIO3_16,
EIC0_INT19,
ICU3_IN1,
ARH0_AIC1_RDA1,
UDC0_ZIN0,
ARH0_AIC1_UPDATA1
GPIO3_17,
EBI0_MDATA00,
EIC0_INT20,
EBI0_MDAICU18_IN0,
TA00
ARH0_AIC1_RDA0,
ARH0_AIC1_UPDATA0
PPG12_
PPGB
PPG13_
PPGB
ARH0_
AIC1_DNCLK
PPG14_
PPGB
ARH0_
AIC1_TDA1
ARH0_
AIC1_DNDATA1
ARH0_
AIC1_TDA0
ARH0_
AIC1_DNDATA0
EBI0_MDATA01
GPIO3_18,
EBI0_MDATA01,
EIC0_INT21,
ICU18_IN1,
ARH0_AIC1_TCKI,
UDC0_AIN1
EBI0_MDATA02
GPIO3_19,
EBI0_MDATA02,
EIC0_INT22,
SPI1_DATA2, I
CU19_IN0,
UDC0_BIN1
EBI0_MDATA03
GPIO3_20,
EBI0_MDATA03,
EIC0_INT23,
SPI1_DATA3,
ICU19_IN1,
UDC0_ZIN1
PPC_PCFGR320
(0x01A8)
P3_20
GPIO3_20
SPI1_DATA3
PPC_PCFGR321
(0x01AA)
P3_21
GPIO3_21
SPI1_SS
OCU17_
OTD0
EBI0_MDATA04
GPIO3_21,
EBI0_MDATA04,
SPI1_SS,
EIC0_INT04
PPC_PCFGR322
(0x01AC)
P3_22
GPIO3_22
SPI1_DATA1
OCU17_
OTD1
EBI0_MDATA05
GPIO3_22,
EBI0_MDATA05,
EIC0_INT20,
SPI1_DATA1
PPC_PCFGR323
(0x01AE)
P3_23
GPIO3_23
SPI1_DATA0
EBI0_MDATA06
GPIO3_23,
EBI0_MDATA06,
EIC0_INT21,
SPI1_DATA0
EBI0_MDATA07
GPIO3_24,
EBI0_MDATA07,
EIC0_INT22,
SPI1_CLK,
RLT1_TIN
EBI0_MDATA08
GPIO3_25,
EBI0_MDATA08,
SPI0_SS,
ARH0_AIC0_RCK,
ARH0_AIC0_UPCLK,
EIC0_INT03
PPC_PCFGR324
(0x01B0)
PPC_PCFGR325
(0x01B2)
PPC_PCFGR326
(0x01B4)
PPC_PCFGR327
(0x01B6)
P3_24
P3_25
P3_26
P3_27
GPIO3_24
GPIO3_25
GPIO3_26
GPIO3_27
PPG71_
PPGA
PPG15_
PPGB
RLT0_TOT
SPI1_CLK
SPI0_SS
SPI0_DATA1
SPI0_DATA0
Document Number: DS707-00002-4v1-E
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
PPG64_
PPGB
PPG65_
PPGB
PPG66_
PPGB
PPG0_
PPGA
RLT1_TOT
PPG1_
PPGA
GPIO3_26,
EBI0_MDATA09,
EIC0_INT24,
EBI0_MDARLT2_TOT
SPI0_DATA1,
TA09
ARH0_AIC0_RDA1,
ARH0_AIC0_UPDATA1
PPG2_
PPGA
GPIO3_27,
EBI0_MDATA10,
EIC0_INT25,
EBI0_MDARLT5_TOT
SPI0_DATA0,
TA10
ARH0_AIC0_RDA0,
ARH0_AIC0_UPDATA0
Page 47
MB9DF126
MB9DF126B
Table 3-4: Port Pin Multiplexing table (Continued)
Register
(offset)
PPC_PCFGR328
(0x01B8)
Port
Resource functional output
POF=0
POF=1
POF=2
POF=3
POF=4
POF=5
POF=6
POF=7
Possible Resource Function
Input
ARH0_
AIC0_DNCLK
EBI0_MDATA11
GPIO3_28,
EBI0_MDATA11,
EIC0_INT26,
SPI0_CLK,
ARH0_AIC0_TCKI,
RLT0_TIN
P3_28
GPIO3_28
SPI0_CLK
OCU1_
OTD1
PPG67_
PPGB
PPG3_
PPGA
PPC_PCFGR329 (0x01- P3_29
BA)
GPIO3_29
SPI0_DATA2
OCU16_
OTD0
PPG68_
PPGB
PPG4_
PPGA
ARH0_
AIC0_TDA1
ARH0_
AIC0_DNDATA1
EBI0_MDATA12
GPIO3_29,
EBI0_MDATA12,
EIC0_INT27,
SPI0_DATA2
OCU16_
OTD1
PPG69_
PPGB
PPG5_
PPGA
ARH0_
AIC0_TDA0
ARH0_
AIC0_DNDATA0
EBI0_MDATA13
GPIO3_30,
EBI0_MDATA13,
EIC0_INT28,
SPI0_DATA3,
RLT5_TIN
PPC_PCFGR330
(0x01BC)
P3_30
GPIO3_30
SPI0_DATA3
PPC_PCFGR331
(0x01BE)
P3_31
GPIO3_31
SPI1_SSO1
OCU1_
OTD1_I
SG0_SGO
EBI0_MDATA14
GPIO3_31,
EBI0_MDATA14,
EIC0_INT27,
ICU19_IN0
PPC_PCFGR332
(0x01C0)
P3_32
GPIO3_32
SPI1_SSO2
OCU1_
OTD0_I
SG0_SGA
EBI0_MDATA15
GPIO3_32,
EBI0_MDATA15,
EIC0_INT28,
ICU19_IN1
PPC_PCFGR333
(0x01C2)
P3_33
GPIO3_33
OCU1_
OTD1_GI
UDC0_
UDOT0
EBI0_
MAD18
EBI0_
MNALE
EBI0_
MCASX
GPIO3_33,
I2S0_ECLK,
EIC0_INT01
PPC_PCFGR334
(0x01C4)
P3_34
GPIO3_34
OCU1_
OTD0_GI
I2S0_SD
EBI0_
MAD19
EBI0_MNCLE
EBI0_
MRASX
GPIO3_34,
I2S0_SD,
EIC0_INT14,
UDC0_AIN0
PPC_PCFGR335
(0x01C6)
P3_35
GPIO3_35
OCU16_
OTD1_I
I2S0_WS
EBI0_
MAD20
EBI0_MNWEX
EBI0_
MDWEX
GPIO3_35,
I2S0_WS,
UDC0_BIN0,
EIC0_INT06
PPC_PCFGR336
(0x01C8)
P3_36
GPIO3_36
OCU16_
OTD0_I
I2S0_SCK
EBI0_
MAD21
EBI0_MNREX
EBI0_
MCKE
GPIO3_36,
I2S0_SCK,
EIC0_INT18,
UDC0_ZIN0
PPC_PCFGR337 (0x01- P3_37
CA)
GPIO3_37
OCU16_
OTD1_GI
UDC0_
UDOT1
EBI0_
MAD18
EBI0_
MCASX
EBI0_MDQM0
GPIO3_37,
I2S1_ECLK,
EIC0_INT19
PPC_PCFGR338
(0x01CC)
P3_38
GPIO3_38
OCU16_
OTD0_GI
I2S1_SD
EBI0_
MAD19
EBI0_
MRASX
EBI0_MDQM1
GPIO3_38,
I2S1_SD,
EIC0_INT23,
UDC0_AIN1
PPC_PCFGR339
(0x01CE)
P3_39
GPIO3_39
OCU17_
OTD1_I
I2S1_WS
EBI0_
MAD20
EBI0_
MDWEX
EBI0_
MWEX
GPIO3_39,
I2S1_WS,
UDC0_BIN1,
EIC0_INT07
PPC_PCFGR340
(0x01D0)
P3_40
GPIO3_40
OCU17_
OTD0_I
I2S1_SCK
EBI0_
MAD21
EBI0_
MCKE
EBI0_
MOEX
GPIO3_40,
I2S1_SCK,
EIC0_INT29,
UDC0_ZIN1
PPC_PCFGR341
(0x01D2)
P3_41
GPIO3_41
SPI1_SSO3
OCU17_
OTD1_GI
EBI0_
MCLK
GPIO3_41,
EIC0_INT30,
ADC0_EDGI
PPC_PCFGR342
(0x01D4)
P3_42
GPIO3_42
SPI2_SSO3
OCU17_
OTD0_GI
Document Number: DS707-00002-4v1-E
EBI0_
MAD22
EBI0_MDQM0
GPIO3_42,
EBI0_RDY,
EIC0_INT31
Page 48
MB9DF126
MB9DF126B
3.2.2
Resource input source table
3.2.2.1
RICFG0_ADC
Table 3-5: Resource input source table for ADC configurations
Register
(offset)
Resource
input
ADC0EDGIL
ADC0EDGI
(0x000C)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PORTPIN
OCU
-
-
-
-
-
-
Ports selected
by ADC0EDGI_
PORTSEL register.
All the signals that are
enabled by
the
ADC0EDGIOCUn registers ANDed
together.
If they are
not enabled,
they are
masked to
'1'.
reserved
reserved
reserved
reserved
reserved
reserved
PORT-SEL[3:0]
-
-
-
-
-
-
0010: P1_30 is
selected
0100: P0_51 is
selected
0101: P2_32 is
selected
0110: P3_01 is
selected 0111:
P3_41 is selected
reserved
reserved
reserved
reserved
reserved
reserved
ADC0_EDGI
ADC0EDGIH
ADC0EDGIOCU0L
ADC0EDGIOCU0
(0x000E)
Source for resource input
Register
Field
ADC0_EDGI
OCU00
OCU01
OCU10
OCU11
-
-
-
-
0: OCU0_OTD0
is disabled
1: OCU0_OTD0
is enabled
0: OCU0_
OTD1 is disabled
1: OCU0_
OTD1 is enabled
0: OCU1_
OTD0 is disabled
1: OCU1_
OTD0 is enabled
0: OCU1_
OTD1 is disabled
1: OCU1_
OTD1 is enabled
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC0EDGIOCU1
(0x0010)
ADC0_EDGI
-
ADC0EDGIOCU2
(0x0012)
ADC0_EDGI
-
ADC0EDGIOCU3
(0x0014)
ADC0_EDGI
-
Document Number: DS707-00002-4v1-E
Page 49
MB9DF126
MB9DF126B
Table 3-5: Resource input source table for ADC configurations
Register
(offset)
Resource
input
ADC0EDGIOCU4L
ADC0EDGIOCU4
(0x0016)
Source for resource input
Register
Field
ADC0_EDGI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
OCU160
OCU161
OCU170
OCU171
-
-
-
-
0: OCU16_
OTD0 is disabled
1: OCU16_
OTD0 is enabled
0: OCU16_
OTD1 is disabled
1: OCU16_
OTD1 is enabled
0: OCU17_
OTD0 is disabled
1: OCU17_
OTD0 is enabled
0: OCU17_
OTD1 is disabled
1: OCU17_
OTD1 is enabled
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT
PPGL
PPGH
-
-
-
-
-
UFSET output
of RLT that is
selected by
RICFGRADC0_
TIMIRLT bits
[3:0]
ADTRGH
and ADTRGL signals of
PPG0 to
PPG63
ORed together
ADTRGH
and ADTRGL signals of
PPG64 to
PPG127
ORed together
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT
-
-
-
-
0000: RLT0_
UFSET
0001: RLT1_
UFSET
...
1001: RLT9_
UFSET
1010 - 1111:
clipped to GND
(reserved in
spec)
-
-
-
-
-
ADC0EDGIOCU5
(0x0018)
ADC0_EDGI
-
ADC0EDGIOCU6
(0x001A)
ADC0_EDGI
-
ADC0EDGIOCU7
(0x001C)
ADC0_EDGI
-
ADC0TIMIL
ADC0TIMI
(0x001E)
ADC0_TIMI
-
ADC0TIMIRL
TL
ADC0TIMIRLT
(0x0020)
ADC0_TIMI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ZPDEN
ADC0ZPDEN*1
(0x003E)
ADC0_ZPD
ADC0ZPDEN
0: ZPD disable
1: ZPD enable
,-,-,-,-,-,-,-,-,-,-
Note:
*1: The ADC0ZPDEN register is write-only-once protected.
Document Number: DS707-00002-4v1-E
Page 50
MB9DF126
MB9DF126B
3.2.2.2
RICFG0
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_00
P1_01
P1_02
P1_03
P1_00 /
P1_01
P1_01 /
P1_00
P1_02 /
P1_03
P1_03 /
P1_02
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_05 /
P1_04
P1_06 /
P1_07
P1_07 /
P1_06
RESSEL
ADC0AN26
(0x0000)
ADC0_AN26
PORTSEL
RESSEL
ADC0AN27
(0x0002)
ADC0_AN27
P1_04
P1_05
P1_06
P1_07
P1_04 /
P1_05
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_08
P1_09
P1_10
P1_11
P1_08 / P1_
09
P1_09 / P1_
08
P1_10 / P1_
11
P1_11 / P1_
10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_12
P1_13
P1_14
P1_15
P1_12 (20)/
P1_13 (21)
P1_13 (21)/
P1_12 (20)
P1_14 (22)/
P1_15 (23)
P1_15 (23)/
P1_14 (22)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_16
P1_17
P1_18
P1_19
P1_16 /
P1_17
P1_17 /
P1_16
P1_18 /
P1_19
P1_19 /
P1_18
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_20
P1_21
P1_22
P1_23
P1_20 /
P1_21
P1_21 /
P1_20
P1_22 /
P1_23
P1_23 /
P1_22
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT3_TOT
RLT0_TOT
PPG10_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_40
P0_47
P2_44
P2_45
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
RESSEL
ADC0AN28
(0x0004)
ADC0_AN28
PORTSEL
RESSEL
ADC0AN29
(0x0006)
ADC0_AN29
PORTSEL
RESSEL
ADC0AN30
(0x0008)
ADC0_AN30
PORTSEL
RESSEL
ADC0AN31
(0x000A)
ADC0_AN31
PORTSEL
RESSEL
FRT0TEXT
(0x0400)
FRT0_TEXT
PORTSEL
Port Sel
RLT2_TOT
RLT3_TOT
RLT1_TOT
PPG11_
PPGB
-
-
-
-
-
-
-
-
reserved
reserved
P0_41
P0_47
P2_45
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL
FRT1TEXT
(0x0420)
FRT1_TEXT
PORTSEL
Document Number: DS707-00002-4v1-E
Page 51
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port Sel
RLT2_TOT
RLT3_TOT
RLT4_TOT
PPG12_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_42
P0_47
P2_45
P2_46
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT3_TOT
RLT5_TOT
PPG13_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P0_43
P0_47
P2_45
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
P0_48
P1_35
reserved
P0_41
P1_10
P2_32
P2_40
P3_13
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
P0_49
P1_36
reserved
P0_42
P1_09
P2_33
P2_41
P3_14
reserved
reserved
reserved
FRT2
FRT0
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
FRT2TEXT
(0x0440)
FRT2_TEXT
PORTSEL
RESSEL
FRT3TEXT
(0x0460)
FRT3_TEXT
PORTSEL
RESSEL
ICU2IN0
(0x0840)
ICU2_IN0
PORTSEL
RESSEL
ICU2IN1
(0x0842)
ICU2_IN1
PORTSEL
ICU2FRTSEL
(0x0844)
ICU2_FRTSEL
RESSEL
PORTSEL
RESSEL
ICU3IN0
(0x0860)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P0_50
P1_37
reserved
P1_32
P2_34
P2_42
P3_02
P3_15
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P0_51
P1_38
reserved
P1_31
P2_35
P2_43
P3_01
P3_16
reserved
reserved
reserved
reserved
FRT3
FRT1
ICU2_
TOUT0[15:0]
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT0_TOT
PPG5_
PPGA
PPG6_
PPGA
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU3_IN0
PORTSEL
RESSEL
ICU3IN1
(0x0862)
ICU3_IN1
PORTSEL
ICU3FRTSEL
(0x0864)
ICU3_FRTSEL
RESSEL
PORTSEL
OCU0OTD0
GATE
(0x0C00)
OCU0_
OTD0 Gate
RESSEL
PORTSEL
OCU0OTD0
GM (0x0C02)
OCU0_
OTD0 GateMode
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 52
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
OCU0OTD1
GATE
(0x0C04)
Resource
Input
OCU0_
OTD1 Gate
RESSEL[
3:0]/
PORTSE
L[3:0]
OCU0_
OTD1 GateMode
OCU1_
CMP0EXT
RESSEL
PORTSEL
OCU1FRTSEL
(0x0C22)
OCU1_FRTSEL
OCU1_
OTD0 Gate
OCU1_
OTD0 GateMode
OCU1_
OTD1 Gate
OCU1_
OTD1 GateMode
5
6
7
8
9
10
11
12
13
14
15
RLT4_TOT
RLT1_TOT
PPG5_
PPGA
PPG7_
PPGA
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCU1_
MTRG
OCU0_
CMP0OUT
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FRT1
FRT0
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT2_TOT
PPG5_
PPGA
PPG8_
PPGA
OCU0_
OTD0
OCU0_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT3_TOT
PPG5_
PPGA
PPG9_
PPGA
OCU0_
OTD0
OCU0_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_41
P0_46
P1_31
reserved
P1_09
P3_01
P3_05
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_40
P0_45
P1_30
reserved
P0_42
P1_08
P3_00
P3_02
P3_04
reserved
reserved
reserved
reserved
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
OCU1OTD1
GM
(0x0C2A)
4
RESSEL
PORTSEL
OCU1OTD1
GATE
(0x0C28)
3
RESSEL
PORTSEL
OCU1OTD0
GM (0x0C26)
2
RESSEL
PORTSEL
OCU1OTD0
GATE
(0x0C24)
1
RESSEL
PORTSEL
OCU1CMP0
EXT
(0x0C20)
0
RESSEL
PORTSEL
OCU0OTD1
GM (0x0C06)
Source for resource input
RESSEL
PORTSEL
RESSEL
USART0SCKI (0x1400)
USART0_
SCKI
PORTSEL
RESSEL
USART0SIN
(0x1402)
USART0_
SIN
PORTSEL
PPG0PPGA
GATE
(0x1C00)
PPG0_
PPGA Gate
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 53
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG0PPGA
GM (0x1C02)
Resource
Input
PPG0_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG0_
PPGB Gate
PPG0_
PPGB GateMode
PPG1_
PPGA Gate
PPG1_
PPGA GateMode
PPG1_
PPGB Gate
PPG1_
PPGB GateMode
PPG2_
PPGA Gate
PPG2_
PPGA GateMode
PPG2_
PPGB Gate
PPG2_
PPGB GateMode
PPG3_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG3PPGA
GATE
(0x1C60)
9
RESSEL
PORTSEL
PPG2PPGBGM (0x1C46)
8
RESSEL
PORTSEL
PPG2PPGBGATE
(0x1C44)
7
RESSEL
PORTSEL
PPG2PPGA
GM (0x1C42)
6
RESSEL
PORTSEL
PPG2PPGA
GATE
(0x1C40)
5
RESSEL
PORTSEL
PPG1PPGBGM (0x1C26)
4
RESSEL
PORTSEL
PPG1PPGBGATE
(0x1C24)
3
RESSEL
PORTSEL
PPG1PPGA
GM (0x1C22)
2
RESSEL
PORTSEL
PPG1PPGA
GATE
(0x1C20)
1
RESSEL
PORTSEL
PPG0PPGBGM (0x1C06)
0
RESSEL
PORTSEL
PPG0PPGBGATE
(0x1C04)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 54
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG3PPGA
GM (0x1C62)
Resource
Input
PPG3_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG3_
PPGB Gate
PPG3_
PPGB GateMode
PPG4_
PPGA Gate
PPG4_
PPGA GateMode
PPG4_
PPGB Gate
PPG4_
PPGB GateMode
PPG5_
PPGA Gate
PPG5_
PPGA GateMode
PPG5_
PPGB Gate
PPG5_
PPGB GateMode
PPG6_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG6PPGA
GATE
(0x1CC0)
9
RESSEL
PORTSEL
PPG5PPGBGM (0x1CA6)
8
RESSEL
PORTSEL
PPG5PPGBGATE (0x1CA4)
7
RESSEL
PORTSEL
PPG5PPGA
GM (0x1CA2)
6
RESSEL
PORTSEL
PPG5PPGA
GATE (0x1CA0)
5
RESSEL
PORTSEL
PPG4PPGBGM (0x1C86)
4
RESSEL
PORTSEL
PPG4PPGBGATE
(0x1C84)
3
RESSEL
PORTSEL
PPG4PPGA
GM (0x1C82)
2
RESSEL
PORTSEL
PPG4PPGA
GATE
(0x1C80)
1
RESSEL
PORTSEL
PPG3PPGBGM (0x1C66)
0
RESSEL
PORTSEL
PPG3PPGBGATE
(0x1C64)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 55
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG6PPGA
GM
(0x1CC2)
Resource
Input
PPG6_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG6_
PPGB Gate
PPG6_
PPGB GateMode
PPG7_
PPGA Gate
PPG7_
PPGA GateMode
PPG7_
PPGB Gate
PPG7_
PPGB GateMode
PPG8_
PPGA Gate
PPG8_
PPGA GateMode
PPG8_
PPGB Gate
PPG8_
PPGB GateMode
PPG9_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG9PPGA
GATE
(0x1D20)
9
RESSEL
PORTSEL
PPG8PPGBGM (0x1D06)
8
RESSEL
PORTSEL
PPG8PPGBGATE
(0x1D04)
7
RESSEL
PORTSEL
PPG8PPGA
GM (0x1D02)
6
RESSEL
PORTSEL
PPG8PPGA
GATE
(0x1D00)
5
RESSEL
PORTSEL
PPG7PPGBGM
(0x1CE6)
4
RESSEL
PORTSEL
PPG7PPGBGATE
(0x1CE4)
3
RESSEL
PORTSEL
PPG7PPGA
GM
(0x1CE2)
2
RESSEL
PORTSEL
PPG7PPGA
GATE
(0x1CE0)
1
RESSEL
PORTSEL
PPG6PPGBGM
(0x1CC6)
0
RESSEL
PORTSEL
PPG6PPGBGATE
(0x1CC4)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 56
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG9PPGA
GM (0x1D22)
Resource
Input
PPG9_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG9_
PPGB Gate
PPG9_
PPGB GateMode
PPG10_
PPGA Gate
PPG10_
PPGA GateMode
PPG10_
PPGB Gate
PPG10_
PPGB GateMode
PPG11_
PPGA Gate
PPG11_
PPGA GateMode
PPG11_
PPGB Gate
PPG11_
PPGB GateMode
PPG12_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG12PPG
AGATE
(0x1D80)
9
RESSEL
PORTSEL
PPG11PPGBGM
(0x1D66)
8
RESSEL
PORTSEL
PPG11PPGBGATE
(0x1D64)
7
RESSEL
PORTSEL
PPG11PPG
AGM
(0x1D62)
6
RESSEL
PORTSEL
PPG11PPG
AGATE
(0x1D60)
5
RESSEL
PORTSEL
PPG10PPGBGM
(0x1D46)
4
RESSEL
PORTSEL
PPG10PPGBGATE
(0x1D44)
3
RESSEL
PORTSEL
PPG10PPG
AGM
(0x1D42)
2
RESSEL
PORTSEL
PPG10PPG
AGATE
(0x1D40)
1
RESSEL
PORTSEL
PPG9PPGBGM (0x1D26)
0
RESSEL
PORTSEL
PPG9PPGBGATE
(0x1D24)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 57
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG12PPG
AGM
(0x1D82)
Resource
Input
PPG12_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG12_
PPGB Gate
PPG12_
PPGB GateMode
PPG13_
PPGA Gate
PPG13_
PPGA GateMode
PPG13_
PPGB Gate
PPG13_
PPGB GateMode
PPG14_
PPGA Gate
PPG14_
PPGA GateMode
PPG14_
PPGB Gate
PPG14_
PPGB GateMode
PPG15_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG15PPG
AGATE
(0x1DE0)
9
RESSEL
PORTSEL
PPG14PPGBGM
(0x1DC6)
8
RESSEL
PORTSEL
PPG14PPGBGATE
(0x1DC4)
7
RESSEL
PORTSEL
PPG14PPG
AGM
(0x1DC2)
6
RESSEL
PORTSEL
PPG14PPG
AGATE
(0x1DC0)
5
RESSEL
PORTSEL
PPG13PPGBGM (0x1DA6)
4
RESSEL
PORTSEL
PPG13PPGBGATE (0x1DA4)
3
RESSEL
PORTSEL
PPG13PPG
AGM (0x1DA2)
2
RESSEL
PORTSEL
PPG13PPG
AGATE (0x1DA0)
1
RESSEL
PORTSEL
PPG12PPGBGM
(0x1D86)
0
RESSEL
PORTSEL
PPG12PPGBGATE
(0x1D84)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 58
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPG15PPG
AGM
(0x1DE2)
Resource
Input
PPG15_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG15_
PPGB Gate
PPG15_
PPGB GateMode
PPGGRP0_
ETRG0
PPGGRP0_
ETRG1
PPGGRP0_
ETRG2
PPGGRP0_
ETRG3
PPGGRP1ETRG
0 (0x2420)
PPGGRP0_
RLTTRG1
PPGGRP1_
ETRG1
PPGGRP1_
ETRG2
9
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
P1_30
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
P1_30
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPGGRP1ETRG
2 (0x2424)
8
RESSEL
PORTSEL
PPGGRP1ETRG
1 (0x2422)
7
RESSEL
PORTSEL
PPGGRP1_
ETRG0
6
RESSEL
PORTSEL
PPGGRP0RLTTRG1
(0x2408)
5
RESSEL
PORTSEL
PPGGRP0ETRG
3 (0x2406)
4
RESSEL
PORTSEL
PPGGRP0ETRG
2 (0x2404)
3
RESSEL
PORTSEL
PPGGRP0ETRG
1 (0x2402)
2
RESSEL
PORTSEL
PPGGRP0ETRG
0 (0x2400)
1
RESSEL
PORTSEL
PPG15PPGBGM
(0x1DE6)
0
RESSEL
PORTSEL
PPG15PPGBGATE
(0x1DE4)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 59
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPGGRP1ETRG
3 (0x2426)
Resource
Input
PPGGRP1_
ETRG3
RESSEL[
3:0]/
PORTSE
L[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
PORTSEL
P-
-
-
-
-
-
-
-
RESSEL
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPGGRP1RLTTRG1
(0x2428)
PPGGRP2ETRG
0 (0x2440)
PPGGRP1_
RLTTRG1
RESSEL
PORTSEL
PPGGRP2_
ETRG0
RESSEL
PORTSEL
PPGGRP2ETRG
1 (0x2442)
PPGGRP2ETRG
2 (0x2444)
PPGGRP2_
ETRG1
RESSEL
PPGGRP2_
ETRG2
PORTSEL
PPGGRP2ETRG
3 (0x2446)
PPGGRP2_
ETRG3
PPGGRP3ETRG
0 (0x2460)
PPGGRP2_
RLTTRG1
PPGGRP3_
ETRG1
PPGGRP3_
ETRG2
PPGGRP3_
ETRG3
-
-
-
-
Port Sel
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
P-
-
-
-
-
-
-
-
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
P1_30
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPGGRP3ETRG
3 (0x2466)
OCU17_
OTD0
RESSEL
PORTSEL
PPGGRP3ETRG
2 (0x2464)
OCU16_
OTD1
RESSEL
PORTSEL
PPGGRP3ETRG
1 (0x2462)
OCU16_
OTD0
RESSEL
PORTSEL
PPGGRP3_
ETRG0
P1_30
RESSEL
PORTSEL
PPGGRP2RLTTRG1
(0x2448)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 60
MB9DF126
MB9DF126B
Table 3-6: Resource input source table (RICFG0)
Register
(offset)
PPGGRP3RLTTRG1
(0x2468)
Resource
Input
PPGGRP3_
RLTTRG1
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 61
MB9DF126
MB9DF126B
3.2.2.3
RICFG1
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
PPGGRP16ETR
G0 (0x0000)
Resource
Input
PPGGRP16_
ETRG0
RESSEL[
3:0]/
PORTSE
L[3:0]
PPGGRP16_
ETRG1
PPGGRP16_
ETRG2
PPGGRP16_
ETRG3
PPGGRP17ETR
G0 (0x0020)
PPGGRP16_
RLTTRG1
PPGGRP17ETR
G2 (0x0024)
PPGGRP17_
ETRG1
PPGGRP17_
RLTTRG1
8
9
10
11
12
13
14
15
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD0
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU0_
OTD1
OCU1_
OTD0
OCU1_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
PORTSEL
-
-
-
-
-
-
-
-
RESSEL
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port Sel
OCU16_
OTD0
OCU16_
OTD1
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
RESSEL
PORTSEL
PPGGRP17RLTTRG1
(0x0028)
7
OCU0_
OTD0
PPGGRP17_
ETRG2
PPGGRP17_
ETRG3
6
-
PORTSEL
PPGGRP17ETR
G3 (0x0026)
5
RESSEL
PORTSEL
PPGGRP17ETR
G1 (0x0022)
4
RESSEL
PORTSEL
PPGGRP17_
ETRG0
3
RESSEL
PORTSEL
PPGGRP16RLTTRG1
(0x0008)
2
RESSEL
PORTSEL
PPGGRP16ETR
G3 (0x0006)
1
RESSEL
PORTSEL
PPGGRP16ETR
G2 (0x0004)
0
RESSEL
PORTSEL
PPGGRP16ETR
G1 (0x0002)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 62
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CAN0_RX
CAN0_RX
&CAN0_TX
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_42
P0_48
P0_51
P1_34
P1_00
P2_41
P2_44
P2_46
reserved
reserved
reserved
reserved
reserved
CAN1_RX
CAN1_RX
&CAN1_TX
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_43
P0_48
P0_50
P1_36
P1_02
P2_41
P2_45
P2_47
reserved
reserved
reserved
reserved
reserved
CAN2_RX
CAN2_RX
&CAN2_TX
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL
CAN0RX
(0x0400)
CAN0_RX
PORTSEL
RESSEL
CAN1RX
(0x0420)
CAN1_RX
PORTSEL
RESSEL
CAN2RX
(0x0440)
CAN2_RX
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_42
P0_49
P0_50
P1_38
P1_16
P2_40
P2_45
P2_46
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT3_TOT
RLT6_TOT
PPG64_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P0_44
P0_45
P0_47
P2_40
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT3_TOT
RLT7_TOT
PPG65_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P0_45
P0_47
P2_41
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
RESSEL
FRT16TEXT
(0x0C00)
FRT16_
TEXT
PORTSEL
RESSEL
FRT17TEXT
(0x0C20)
FRT17_
TEXT
PORTSEL
Port Sel
RLT2_TOT
RLT3_TOT
RLT8_TOT
PPG66_
PPGB
-
-
-
-
-
-
-
-
reserved
reserved
P0_45
P0_46
P0_47
P2_42
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT3_TOT
RLT9_TOT
PPG67_
PPGB
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P0_45
P0_47
P2_43
P2_47
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
RESSEL
FRT18TEXT
(0x0C40)
FRT18_
TEXT
PORTSEL
RESSEL
FRT19TEXT
(0x0C60)
FRT19_
TEXT
PORTSEL
RESSEL
ICU18IN0
(0x1040)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
P0_46
P1_13
P1_18
P2_36
P2_44
P3_04
P3_17
reserved
reserved
ICU18_IN0
PORTSEL
Document Number: DS707-00002-4v1-E
Page 63
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P1_24
reserved
reserved
P0_41
P0_47
P2_37
P2_45
P3_05
P3_18
reserved
reserved
reserved
FRT18
FRT16
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P1_25
reserved
reserved
P0_42
P2_38
P2_46
P3_06
P3_19
P3_31
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P1_26
reserved
reserved
P1_14
P1_19
P2_39
P2_47
P3_07
P3_20
P3_32
reserved
reserved
FRT19
FRT17
ICU18_
TOUT0[15:0]
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT5_TOT
PPG64_
PPGB
PPG65_
PPGB
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
RESSEL
ICU18IN1
(0x1042)
ICU18_IN1
PORTSEL
ICU18FRTSEL
(0x1044)
ICU18_FRTSEL
RESSEL
PORTSEL
RESSEL
ICU19IN0
(0x1060)
ICU19_IN0
PORTSEL
RESSEL
ICU19IN1
(0x1062)
ICU19_IN1
PORTSEL
ICU19FRTSEL
(0x1064)
ICU19_FRTSEL
RESSEL
PORTSEL
OCU16OTD
0GATE
(0x1400)
OCU16_
OTD0 Gate
RESSEL
PORTSEL
OCU16OTD
0GM
(0x1402)
OCU16_
OTD0 GateMode
OCU16_
OTD1 Gate
OCU16_
OTD1 GateMode
OCU17_
CMP0EXT
RESSEL
PORTSEL
OCU17FRTSEL
(0x1422)
OCU17_
FRTSEL
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT6_TOT
PPG64_
PPGB
PPG66_
PPGB
OCU17_
OTD0
OCU17_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCU17_
MTRG
OCU16_
CMP0OUT
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FRT17
FRT16
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
OCU17CMP
0EXT
(0x1420)
reserved
RESSEL
PORTSEL
OCU16OTD
1GM
(0x1406)
Sync
RESSEL
PORTSEL
OCU16OTD
1GATE
(0x1404)
Async
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 64
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
OCU17OTD
0GATE
(0x1424)
Resource
Input
OCU17_
OTD0 Gate
RESSEL[
3:0]/
PORTSE
L[3:0]
OCU17_
OTD0 GateMode
OCU17_
OTD1 Gate
OCU17_
OTD1 GateMode
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RLT4_TOT
RLT7_TOT
PPG64_
PPGB
PPG67_
PPGB
OCU16_
OTD0
OCU16_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RLT4_TOT
RLT8_TOT
PPG64_
PPGB
PPG68_
PPGB
OCU16_
OTD0
OCU16_
OTD1
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_41
P0_46
reserved
P1_13
P3_01
P3_05
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_40
P0_45
reserved
P0_47
P1_12
P3_00
P3_04
P3_06
reserved
reserved
reserved
reserved
reserved
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
OCU17OTD
1GM
(0x142A)
1
RESSEL
PORTSEL
OCU17OTD
1GATE
(0x1428)
0
RESSEL
PORTSEL
OCU17OTD
0GM
(0x1426)
Source for resource input
RESSEL
PORTSEL
RESSEL
USART6SCKI (0x1C00)
USART6_
SCKI
PORTSEL
RESSEL
USART6SIN
(0x1C02)
USART6_
SIN
PORTSEL
PPG64PPG
AGATE
(0x2400)
PPG64_
PPGA Gate
RESSEL
PORTSEL
PPG64PPG
AGM
(0x2402)
PPG64_
PPGA GateMode
RESSEL
PORTSEL
PPG64PPGBGATE
(0x2404)
PPG64_
PPGB Gate
RESSEL
PORTSEL
PPG64PPGBGM
(0x2406)
PPG64_
PPGB GateMode
PPG65_
PPGA Gate
-
-
-
-
-
-
-
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG65PPG
AGATE
(0x2420)
Async
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 65
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
PPG65PPG
AGM
(0x2422)
Resource
Input
PPG65_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG65_
PPGB Gate
PPG65_
PPGB GateMode
PPG66_
PPGA Gate
PPG66_
PPGA GateMode
PPG66_
PPGB Gate
PPG66_
PPGB GateMode
PPG67_
PPGA Gate
PPG67_
PPGA GateMode
PPG67_
PPGB Gate
PPG67_
PPGB GateMode
PPG68_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG68PPG
AGATE
(0x2480)
9
RESSEL
PORTSEL
PPG67PPGBGM
(0x2466)
8
RESSEL
PORTSEL
PPG67PPGBGATE
(0x2464)
7
RESSEL
PORTSEL
PPG67PPG
AGM
(0x2462)
6
RESSEL
PORTSEL
PPG67PPG
AGATE
(0x2460)
5
RESSEL
PORTSEL
PPG66PPGBGM
(0x2446)
4
RESSEL
PORTSEL
PPG66PPGBGATE
(0x2444)
3
RESSEL
PORTSEL
PPG66PPG
AGM
(0x2442)
2
RESSEL
PORTSEL
PPG66PPG
AGATE
(0x2440)
1
RESSEL
PORTSEL
PPG65PPGBGM
(0x2426)
0
RESSEL
PORTSEL
PPG65PPGBGATE
(0x2424)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 66
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
PPG68PPG
AGM
(0x2482)
Resource
Input
PPG68_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG68_
PPGB Gate
PPG68_
PPGB GateMode
PPG69_
PPGA Gate
PPG69_
PPGA GateMode
PPG69_
PPGB Gate
PPG69_
PPGB GateMode
PPG70_
PPGA Gate
PPG70_
PPGA GateMode
PPG70_
PPGB Gate
PPG70_
PPGB GateMode
PPG71_
PPGA Gate
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG71PPG
AGATE
(0x24E0)
9
RESSEL
PORTSEL
PPG70PPGBGM
(0x24C6)
8
RESSEL
PORTSEL
PPG70PPGBGATE
(0x24C4)
7
RESSEL
PORTSEL
PPG70PPG
AGM
(0x24C2)
6
RESSEL
PORTSEL
PPG70PPG
AGATE
(0x24C0)
5
RESSEL
PORTSEL
PPG69PPGBGM
(0x24A6)
4
RESSEL
PORTSEL
PPG69PPGBGATE
(0x24A4)
3
RESSEL
PORTSEL
PPG69PPG
AGM
(0x24A2)
2
RESSEL
PORTSEL
PPG69PPG
AGATE
(0x24A0)
1
RESSEL
PORTSEL
PPG68PPGBGM
(0x2486)
0
RESSEL
PORTSEL
PPG68PPGBGATE
(0x2484)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 67
MB9DF126
MB9DF126B
Table 3-7: Resource input source table (RICFG1)
Register
(offset)
PPG71PPG
AGM
(0x24E2)
Resource
Input
PPG71_
PPGA GateMode
RESSEL[
3:0]/
PORTSE
L[3:0]
PPG71_
PPGB Gate
PPG71_
PPGB GateMode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Async
Sync
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
PPG71PPGBGM
(0x24E6)
0
RESSEL
PORTSEL
PPG71PPGBGATE
(0x24E4)
Source for resource input
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 68
MB9DF126
MB9DF126B
3.2.2.4
RICFG3
Table 3-8: Resource input source table (RICFG3)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port Sel
RLT9_TOT
RLT9_UFSET
RLT1_TOT
PPG0_
PPGA
MCLKDIV4
RCCLKDIV4
reserved
-
-
-
-
-
-
-
-
reserved
P0_47
reserved
P1_11
P2_43
P3_28
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT0_TOT
RLT0_UFSET
RLT2_TOT
PPG1_
PPGA
MCLKDIV4
RCCLKDIV4
reserved
-
-
-
-
-
-
-
-
reserved
P0_51
reserved
P1_15
P2_39
P3_24
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT1_TOT
RLT1_UFSET
RLT3_TOT
PPG2_
PPGA
MCLKDIV4
RCCLKDIV4
reserved
-
-
-
-
-
-
-
-
reserved
P0_43
reserved
P1_19
P2_35
P3_12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT2_UFSET
RLT4_TOT
PPG3_
PPGA
MCLKDIV4
RCCLKDIV4
reserved
-
-
-
-
-
-
-
-
reserved
P0_45
P1_30
reserved
P1_08
P3_04
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT3_TOT
RLT3_UFSET
RLT5_TOT
PPG4_
PPGA
USART0_
SOT
USART6_
SOT
reserved
RESSEL
RLT0TIN
(0x0800)
RLT0_TIN
PORTSEL
RESSEL
RLT1TIN
(0x0820)
RLT1_TIN
PORTSEL
RESSEL
RLT2TIN
(0x0840)
RLT2_TIN
PORTSEL
RESSEL
RLT3TIN
(0x0860)
RLT3_TIN
PORTSEL
RESSEL
RLT4TIN
(0x0880)
RLT4_TIN
-
-
-
-
-
-
-
-
reserved
P0_46
P1_31
reserved
P1_09
P3_05
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT4_TOT
RLT4_UFSET
RLT6_TOT
PPG5_
PPGA
USART0_
SOT
USART6_
SOT
reserved
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
RLT5TIN
(0x08A0)
RLT5_TIN
reserved
P0_40
reserved
reserved
P1_12
P3_00
P3_30
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT5_TOT
RLT5_UFSET
RLT7_TOT
PPG6_
PPGA
UDC0_
UDOT0
UDC0_
UDOT1
reserved
-
-
-
-
-
-
-
-
reserved
P0_41
reserved
P1_13
P3_01
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT6_TOT
RLT6_UFSET
RLT8_TOT
PPG7_
PPGA
UDC0_
UDOT0
UDC0_
UDOT1
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_38
P2_45
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
RESSEL
RLT6TIN
(0x08C0)
RLT6_TIN
PORTSEL
RESSEL
RLT7TIN
(0x08E0)
RLT7_TIN
PORTSEL
Document Number: DS707-00002-4v1-E
Page 69
MB9DF126
MB9DF126B
Table 3-8: Resource input source table (RICFG3)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port Sel
RLT7_TOT
RLT7_UFSET
RLT9_TOT
PPG8_
PPGA
UDC0_
UDOT0
UDC0_
UDOT1
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_37
P2_41
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT8_TOT
RLT8_UFSET
RLT0_TOT
PPG9_
PPGA
UDC0_
UDOT0
UDC0_
UDOT1
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_36
P2_42
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT0_TOT
RLT3_TOT
RLT7_TOT
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P1_34
reserved
P0_44
P2_33
P3_14
P3_34
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT1_TOT
RLT4_TOT
RLT7_TOT
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P0_48
P2_37
P3_04
P3_18
P3_38
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT1_TOT
RLT4_TOT
RLT8_TOT
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
P1_35
reserved
P0_45
P2_34
P3_15
P3_35
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT5_TOT
RLT8_TOT
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P0_49
P2_38
P3_05
P3_19
P3_39
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT2_TOT
RLT5_TOT
RLT9_TOT
PPG0_
PPGA
PPG1_
PPGA
PPG2_
PPGA
PPG3_
PPGA
RESSEL
RLT8TIN
(0x0900)
RLT8_TIN
PORTSEL
RESSEL
RLT9TIN
(0x0920)
RLT9_TIN
PORTSEL
RESSEL
UDC0AIN0
(0x1000)
UDC0_AIN0
PORTSEL
RESSEL
UDC0AIN1
(0x1004)
UDC0_AIN1
PORTSEL
RESSEL
UDC0BIN0
(0x1008)
UDC0_BIN0
PORTSEL
RESSEL
UDC0BIN1
(0x100C)
UDC0_BIN1
PORTSEL
RESSEL
UDC0ZIN0
(0x1010)
UDC0_ZIN0
-
-
-
-
-
-
-
-
reserved
reserved
P1_36
reserved
P0_46
P2_35
P3_16
P3_36
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG0_
PPGA
PPG1_
PPGA
PPG2_
PPGA
PPG3_
PPGA
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
P0_50
P2_39
P3_06
P3_20
P3_40
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
RESSEL
UDC0ZIN1
(0x1014)
UDC0_ZIN1
PORTSEL
Document Number: DS707-00002-4v1-E
Page 70
MB9DF126
MB9DF126B
3.2.2.5
RICFG4
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port Sel
SPECIAL0_
CLK_PERI1
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_24
P2_32
P2_36
P2_40
P3_33
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
RESSEL
I2S0ECLK
(0x1000)
I2S0_ECLK
PORTSEL
RESSEL
I2S0SCKI
(0x1004)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_35
P2_39
P2_43
P3_36
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_33
P2_37
P2_41
P3_34
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
I2S0_SCKI
PORTSEL
RESSEL
I2S0SDI
(0x1008)
I2S0_SDI
PORTSEL
RESSEL
I2S0WSI
(0x100C)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P2_34
P2_38
P2_42
P3_35
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port Sel
SPECIAL0_
CLK_PERI1
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_24
P2_32
P2_36
P2_44
P3_37
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_27
P2_35
P2_39
P2_47
P3_40
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_25
P2_33
P2_37
P2_45
P3_38
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_26
P2_34
P2_38
P2_46
P3_39
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
I2S0_WSI
PORTSEL
RESSEL
I2S1ECLK
(0x1020)
I2S1_ECLK
PORTSEL
RESSEL
I2S1SCKI
(0x1024)
I2S1_SCKI
PORTSEL
RESSEL
I2S1SDI
(0x1028)
I2S1_SDI
PORTSEL
RESSEL
I2S1WSI
(0x102C)
I2S1_WSI
PORTSEL
Document Number: DS707-00002-4v1-E
Page 71
MB9DF126
MB9DF126B
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_47
P1_11
P2_35
P2_43
P3_28
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_46
P1_10
P2_34
P2_42
P3_27
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_45
P1_09
P2_33
P2_41
P3_26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P0_48
P3_29
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
SPI0CLKI
(0x1C00)
SPI0_CLKI
PORTSEL
RESSEL
SPI0DATA0I
(0x1C04)
SPI0_DATA0I
PORTSEL
RESSEL
SPI0DATA1I
(0x1C08)
SPI0_DATA1I
PORTSEL
RESSEL
SPI0DATA2I
(0x1C0C)
SPI0_DATA2I
PORTSEL
RESSEL
SPI0DATA3I
(0x1C10)
SPI0_DATA3I
reserved
P0_50
P3_30
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RLT0_TOT
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG64_
PPGB
OCU16_
OTD0
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_44
P1_08
P2_32
P2_40
P3_25
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_51
P1_15
P2_39
P2_43
P3_24
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_50
P1_14
P2_38
P2_42
P3_23
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
SPI0MSTAR
T (0x1C14)
SPI0_
MSTART
RESSEL
PORTSEL
RESSEL
SPI0SSI
(0x1C18)
SPI0_SSI
PORTSEL
RESSEL
SPI1CLKI
(0x1C20)
SPI1_CLKI
PORTSEL
RESSEL
SPI1DATA0I
(0x1C24)
SPI1_DATA0I
PORTSEL
Document Number: DS707-00002-4v1-E
Page 72
MB9DF126
MB9DF126B
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_49
P1_13
P2_37
P2_41
P3_22
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P2_32
P3_19
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
SPI1DATA1I
(0x1C28)
SPI1_DATA1I
PORTSEL
RESSEL
SPI1DATA2I
(0x1C2C)
SPI1_DATA2I
PORTSEL
RESSEL
SPI1DATA3I
(0x1C30)
SPI1_DATA3I
reserved
reserved
P2_33
P3_20
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RLT0_TOT
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG64_
PPGB
OCU16_
OTD0
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_48
P1_12
P2_36
P2_40
P3_21
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_43
P1_19
P2_35
P2_39
P3_12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_42
P1_18
P2_34
P2_38
P3_11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_41
P1_17
P2_33
P2_37
P3_10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P0_44
P3_13
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
SPI1MSTAR
T (0x1C34)
SPI1_
MSTART
RESSEL
PORTSEL
RESSEL
SPI1SSI
(0x1C38)
SPI1_SSI
PORTSEL
RESSEL
SPI2CLKI
(0x1C40)
SPI2_CLKI
PORTSEL
RESSEL
SPI2DATA0I
(0x1C44)
SPI2_DATA0I
PORTSEL
RESSEL
SPI2DATA1I
(0x1C48)
SPI2_DATA1I
PORTSEL
RESSEL
SPI2DATA2I
(0x1C4C)
SPI2_DATA2I
PORTSEL
Document Number: DS707-00002-4v1-E
Page 73
MB9DF126
MB9DF126B
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
SPI2DATA3I
(0x1C50)
SPI2_DATA3I
reserved
P0_45
P3_14
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RLT0_TOT
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG64_
PPGB
OCU16_
OTD0
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_40
P1_16
P2_32
P2_36
P3_09
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_42
P1_01
P2_32
P3_25
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_44
P1_03
P2_34
P3_27
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_43
P1_02
P2_33
P3_26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_41
P1_00
P2_35
P3_28
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_01
P2_32
P3_25
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_03
P2_34
P3_27
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
SPI2MSTAR
T (0x1C54)
SPI2_
MSTART
RESSEL
PORTSEL
RESSEL
SPI2SSI
(0x1C58)
SPI2SSI
PORTSEL
RESSEL
ARH0AIC0RCK
(0x2000)
ARH0_
AIC0RCK
PORTSEL
RESSEL
ARH0AIC0RDA0
(0x2004)
ARH0_
AIC0RDA0
PORTSEL
RESSEL
ARH0AIC0RDA1
(0x2008)
ARH0_
AIC0RDA1
PORTSEL
RESSEL
ARH0AIC0TCKI
(0x200C)
ARH0_
AIC0TCKI
PORTSEL
RESSEL
ARH0AIC0UPCLK
(0x2010)
ARH0_
AIC0UPCLK
PORTSEL
ARH0AIC0UPDATA0
(0x2014)
RESSEL
ARH0_
AIC0UPDATA0
PORTSEL
Document Number: DS707-00002-4v1-E
Page 74
MB9DF126
MB9DF126B
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
ARH0AIC0UPDATA1
(0x2018)
ARH0AIC0DBGSELECT
(0x201C)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
ARH0_
AIC0UPDATA1
P1_02
P2_33
P3_26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_37
P1_10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
ARH0_
AIC0DBGSE
LECT
PORTSEL
RESSEL
ARH0AIC1RCK
(0x2020)
ARH0_
AIC1RCK
P1_25
reserved
P0_48
P1_21
P2_40
P3_15
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_27
reserved
P0_50
P1_23
P2_42
P3_17
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
ARH0AIC1RDA0
(0x2024)
ARH0_
AIC1RDA0
PORTSEL
RESSEL
ARH0AIC1RDA1
(0x2028)
ARH0_
AIC1RDA1
P1_26
reserved
P0_49
P1_22
P2_41
P3_16
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_24
reserved
P0_47
P1_20
P2_43
P3_18
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
ARH0AIC1TCKI
(0x202C)
ARH0_
AIC1TCKI
PORTSEL
RESSEL
ARH0AIC1UPCLK
(0x2030)
ARH0_
AIC1UPCLK
P1_21
P1_25
P2_40
P3_15
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_23
P1_27
P2_42
P3_17
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
ARH0AIC1UPDATA0
(0x2034)
ARH0AIC1UPDATA1
(0x2038)
RESSEL
ARH0_
AIC1UPDATA0
PORTSEL
RESSEL
ARH0_
AIC1UPDATA1
P1_22
P1_26
P2_41
P3_16
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
Document Number: DS707-00002-4v1-E
Page 75
MB9DF126
MB9DF126B
Table 3-9: Resource input source table (RICFG4)
Register
(offset)
ARH0AIC1DBGSELECT
(0x203C)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
ARH0_
AIC1DBGSE
LECT
reserved
P1_14
P3_07
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
Document Number: DS707-00002-4v1-E
Page 76
MB9DF126
MB9DF126B
3.2.2.6
RICFG7
Table 3-10: Resource input source table (RICFG7)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P0_38
P1_30
P1_39
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_63
P1_08
P3_08
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P1_33
reserved
P1_09
P3_33
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_10
P3_03
P3_10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_44
P1_11
P1_08
P2_32
P2_40
P3_25
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_48
P1_12
P2_36
P2_40
P3_21
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P0_40
P1_13
P1_16
P2_32
P2_36
P3_09
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_14
P2_34
P2_38
P2_42
P3_35
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_26
P1_15
P2_34
P2_38
P2_46
P3_39
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL
GFX0DCLKI
(0x0000)
GFX0_DCLKI
PORTSEL
RESSEL
EIC0INT00
(0x1000)
EIC0_INT00
PORTSEL
RESSEL
EIC0INT01
(0x1004)
EIC0_INT01
PORTSEL
RESSEL
EIC0INT02
(0x1008)
EIC0_INT02
PORTSEL
RESSEL
EIC0INT03
(0x100C)
EIC0_INT03
PORTSEL
RESSEL
EIC0INT04
(0x1010)
EIC0_INT04
PORTSEL
RESSEL
EIC0INT05
(0x1014)
EIC0_INT05
PORTSEL
RESSEL
EIC0INT06
(0x1018)
EIC0_INT06
PORTSEL
RESSEL
EIC0INT07
(0x101C)
EIC0_INT07
PORTSEL
Document Number: DS707-00002-4v1-E
Page 77
MB9DF126
MB9DF126B
Table 3-10: Resource input source table (RICFG7)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_42
P0_48
P0_51
P1_34
P1_00
P2_41
P2_44
P2_46
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_43
P0_48
P0_50
P1_36
P1_02
P2_41
P2_45
P2_47
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_42
P0_49
P0_50
P1_38
P1_16
P2_40
P2_45
P2_46
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_40
P0_45
P1_30
reserved
P0_42
P1_08
P3_00
P3_02
P3_04
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P0_40
P0_45
reserved
P0_47
P1_12
P3_00
P3_04
P3_06
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P1_37
P1_02
P1_16
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_17
reserved
P3_11
P3_34
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P0_41
reserved
P1_18
reserved
P3_12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
EIC0INT08
(0x1020)
EIC0_INT08
PORTSEL
RESSEL
EIC0INT09
(0x1024)
EIC0_INT09
PORTSEL
RESSEL
EIC0INT10
(0x1028)
EIC0_INT10
PORTSEL
RESSEL
EIC0INT11
(0x102C)
EIC0_INT11
PORTSEL
RESSEL
EIC0INT12
(0x1030)
EIC0_INT12
PORTSEL
RESSEL
EIC0INT13
(0x1034)
EIC0_INT13
PORTSEL
RESSEL
EIC0INT14
(0x1038)
EIC0_INT14
PORTSEL
RESSEL
EIC0INT15
(0x103C)
EIC0_INT15
PORTSEL
RESSEL
EIC0INT16
(0x1040)
EIC0_INT16
reserved
P0_46
reserved
P1_19
reserved
P3_13
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
Document Number: DS707-00002-4v1-E
Page 78
MB9DF126
MB9DF126B
Table 3-10: Resource input source table (RICFG7)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
EIC0INT17
(0x1044)
EIC0_INT17
reserved
P0_47
reserved
P1_20
reserved
P3_14
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
P1_21
reserved
P3_15
P3_36
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT18
(0x1048)
EIC0_INT18
PORTSEL
RESSEL
EIC0INT19
(0x104C)
EIC0_INT19
reserved
P1_24
reserved
P1_22
reserved
P3_16
P3_37
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P1_25
reserved
P1_23
reserved
P3_17
P3_22
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT20
(0x1050)
EIC0_INT20
PORTSEL
RESSEL
EIC0INT21
(0x1054)
EIC0_INT21
reserved
P1_27
reserved
reserved
reserved
P3_18
P3_23
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P1_28
reserved
reserved
reserved
P3_19
P3_24
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT22
(0x1058)
EIC0_INT22
PORTSEL
RESSEL
EIC0INT23
(0x105C)
EIC0_INT23
reserved
P1_29
reserved
reserved
reserved
P3_20
P3_38
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
P1_31
P0_62
reserved
reserved
P3_26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT24
(0x1060)
EIC0_INT24
PORTSEL
RESSEL
EIC0INT25
(0x1064)
EIC0_INT25
reserved
P1_32
P1_00
reserved
reserved
P3_27
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
Document Number: DS707-00002-4v1-E
Page 79
MB9DF126
MB9DF126B
Table 3-10: Resource input source table (RICFG7)
Register
(offset)
Resource
Input
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
EIC0INT26
(0x1068)
EIC0_INT26
reserved
P1_35
P1_01
reserved
reserved
P2_33
P3_28
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_03
reserved
reserved
P3_01
P3_29
P3_31
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT27
(0x106C)
EIC0_INT27
PORTSEL
RESSEL
EIC0INT28
(0x1070)
EIC0_INT28
reserved
reserved
P1_04
reserved
reserved
P3_02
P3_30
P3_32
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_05
reserved
P2_35
P3_05
P3_40
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL
RESSEL
EIC0INT29
(0x1074)
EIC0_INT29
PORTSEL
RESSEL
EIC0INT30
(0x1078)
EIC0_INT30
reserved
reserved
P1_06
reserved
P2_37
P3_06
P3_41
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
P1_07
reserved
P2_39
P3_07
P3_42
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
P2_23 *1
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL
RESSEL
EIC0INT31
(0x107C)
EIC0_INT31
PORTSEL
RESSEL
EIC0NMI
(0x1080)
EIC0_NMI
PORTSEL
Note:
*1: If this bit is set to “1”, the port is used for External NMI. The input receiver is enabled irrespective of
Port register settings and the output driver is disabled irrespective of assigned ressources.
Document Number: DS707-00002-4v1-E
Page 80
MB9DF126
MB9DF126B
3.2.2.7
RICFG8
Table 3-11: Resource input source table (RICFG8)
Register
(offset)
HSSPI0MSTART
(0x0000)
Resource
Input
HSSPI0_
MSTART
RESSEL[
3:0]/
PORTSE
L[3:0]
Source for resource input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RLT0_TOT
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG64_
PPGB
OCU16_
OTD0
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESSEL
PORTSEL
Document Number: DS707-00002-4v1-E
Page 81
MB9DF126
MB9DF126B
4
Interrupt / DMA
This section shows the allocation of interrupt and interrupt vector/interrupt register.
4.1
Interrupt table
Table 4-1: Interrupt Table
Interrupt
Line No
Interrupt Name
Interrupt Description
0
SYSCIRQ
Status Interrupt from System Controller (SYSC_SYSSTSR:RUNDN is set when current RUN Profile was
successfully applied)
1
WDGIRQ
Watchdog pre-warning Interrupt
(WDG_INT:IRQ_FLAG is set when watchdog error condition
is detected (missing or wrong WDG clearing procedure))
13
ARH0IRQ0
APIX Remote Handler IRQ0
(Event IRQ ARH0_EVIRQC:EVIRQ, Event Buffer fifo Level
ARH0_EVIRQC:LVIRQ, Event Buffer fifo overflow ARH0_EVIRQC:OFLIRQ, AShell fatal error ARH0_CHCTRL0~1:FATIRQ, watchdog timer (TX)
ARH0_CHWDGCTL0~1:WDTXIRQ0~3 and (RX)
ARH0_CHWDGCTL0~1:WDRXIRQ0~3)
14
ARH0IRQ1
APIX Remote Handler IRQ1
(Transaction Buffer Interrupt ARH0_TBCTRL00~15:TBIRQ)
30
ADC0IRQ
ADC0 Conversion End Interrupt
(ADC0_CS1:INT signals end of conversion for current channel (this flag is mirrored in ADC0_CS3:INT))
31
ADC0IRQ2
ADC0 Scan End Interrupt
(ADC0_CS3:INT2 is set when the current scan over selected
channels has finished)
32
ADC0IRQR
ADC0 Range Comparator Interrupt
(ADC0_RCOINT10~32:RCOINT[15:0] are set when corresponding ADC result is outside selected range (check
ADC0_RCOOF10~32:RCOOF[15:0] and the selected mode
ADC0_RCOIRS10~32:RCOIRS[15:0] for interrupt cause)
33
ADC0IRQP
ADC0 Pulse Detection Interrupt
(ADC0_PCZF10~32:CTPZF[15:0] are set when corresponding pulse counter becomes zero)
34
RRCFGIRQERR
Retention RAM Single Bit Error
(RRCFG_CSR:CEIF is set when a correctable error occurred
during any read access to Retention RAM)
Document Number: DS707-00002-4v1-E
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
35
SRCFGIRQERR
System RAM Single Bit Error
(SRCFG_ERRFLG:SECFLG is set when a correctable error
occurred during any read access to SRAM)
TCCFGIRQ
Instruction Flash Write Completion Interrupt (TCFCFG_FSTATn:RDYINT is set on the rising edge of TCFCFG_FSTATn:RDY flag
Instruction Flash Hang Interrupt
(TCFCFG_FSTATn:HANGINT is set when a hang condition
occurs in Instruction Flash)
Instruction Flash Single Bit Error
(TCFCFG_FSECIR:SECINT is set when a correctable error
occurred during any read access to Instruction Flash)
37
EECFGIRQERR
Data Flash Error Interrupt
(EEFCFG_SR:ERRINT is set if the write command sequencer is disabled in ongoing operation or if any write error occurs
during ongoing transfer)
Data Flash Hang Interrupt
(EEFCFG_SR:HANGINT is set when a hang condition occurs in Data Flash)
38
IRQ0IRQERR
IUNIT Vector RAM Single Bit Error
(IRQ0_EEI:EEIS is set when a correctable error occurred
during any read access to Interrupt Controller RAM)
41
EECFGIRQ
Data Flash Write Completion Interrupt
(EEFCFG_SR:RDYINT is set on the rising edge of EEFCFG_SR:RDY flag)
Data Flash Single Bit Error
(EEFCFG_SECIR:SECINT is set when a correctable error
occurred during any read access to Data Flash)
42
EICU0IRQ
External Interrupt Capture Unit 0 Interrupt (EICU0_CNFGR:DATAVALID is set when 256 samples have been taken
at the selected external interrupt input pin)
43
HSSPI0IRQRX
HSSPI0 Receive Interrupt
(check HSSPI0_RXF:[6:0] for detailed RX interrupt cause)
44
HSSPI0IRQTX
HSSPI0 Transmit Interrupt
(check HSSPI0_TXF:[6:0] for detailed TX interrupt cause)
49
SPI0IRQRX
SPI0 Receive Interrupt
(check SPI0_RXF:[6:0] for detailed RX interrupt cause)
50
SPI0IRQTX
SPI0 Transmit Interrupt
(check SPI0_TXF:[6:0] for detailed TX interrupt cause)
52
SPI1IRQRX
36
Document Number: DS707-00002-4v1-E
SPI1 Receive Interrupt
(check SPI1_RXF:[6:0] for detailed RX interrupt cause)
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
53
SPI1IRQTX
SPI1 Transmit Interrupt
(check SPI1_TXF:[6:0] for detailed TX interrupt cause)
55
SPI2IRQRX
SPI2 Receive Interrupt (check SPI2_RXF:[6:0] for detailed
RX interrupt cause)
56
SPI2IRQTX
SSPI2 Transmit Interrupt (check SPI2_TXF:[6:0] for detailed
TX interrupt cause)
CAN0IRQ
CAN0 Interrupt
(this interrupt is called depending on CTRLR0:EIE,
CTRLR0:SIE and the corresponding transmit/receive interrupt enable flags in the message objects TXE/RXE)
CAN1IRQ
CAN1 Interrupt
(this interrupt is called depending on CTRLR1:EIE,
CTRLR1:SIE and the corresponding transmit/receive interrupt enable flags in the message objects TXE/RXE)
63
CAN2IRQ
CAN2 Interrupt
(this interrupt is called depending on CTRLR2:EIE,
CTRLR2:SIE and the corresponding transmit/receive interrupt enable flags in the message objects TXE/RXE)
69
EIC0IRQ0
External Interrupt 0
(EIC0_EIRR:ER0 is set when an interrupt condition is detected at the corresponding input pin)
70
EIC0IRQ1
External Interrupt 1
(EIC0_EIRR:ER1 is set when an interrupt condition is detected at the corresponding input pin)
71
EIC0IRQ2
External Interrupt 2
(EIC0_EIRR:ER2 is set when an interrupt condition is detected at the corresponding input pin)
72
EIC0IRQ3
External Interrupt 3
(EIC0_EIRR:ER3 is set when an interrupt condition is detected at the corresponding input pin)
73
EIC0IRQ4
External Interrupt 4
(EIC0_EIRR:ER4 is set when an interrupt condition is detected at the corresponding input pin)
74
EIC0IRQ5
External Interrupt 5
(EIC0_EIRR:ER5 is set when an interrupt condition is detected at the corresponding input pin)
75
EIC0IRQ6
External Interrupt 6
(EIC0_EIRR:ER6 is set when an interrupt condition is detected at the corresponding input pin)
61
62
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
76
EIC0IRQ7
External Interrupt 7
(EIC0_EIRR:ER7 is set when an interrupt condition is detected at the corresponding input pin)
77
EIC0IRQ8
External Interrupt 8
(EIC0_EIRR:ER8 is set when an interrupt condition is detected at the corresponding input pin)
78
EIC0IRQ9
External Interrupt 9
(EIC0_EIRR:ER9 is set when an interrupt condition is detected at the corresponding input pin)
79
EIC0IRQ10
External Interrupt 10
(EIC0_EIRR:ER10 is set when an interrupt condition is detected at the corresponding input pin)
80
EIC0IRQ11
External Interrupt 11
(EIC0_EIRR:ER11 is set when an interrupt condition is detected at the corresponding input pin)
81
EIC0IRQ12
External Interrupt 12
(EIC0_EIRR:ER12 is set when an interrupt condition is detected at the corresponding input pin)
82
EIC0IRQ13
External Interrupt 13
(EIC0_EIRR:ER13 is set when an interrupt condition is detected at the corresponding input pin)
83
EIC0IRQ14
External Interrupt 14
(EIC0_EIRR:ER14 is set when an interrupt condition is detected at the corresponding input pin)
84
EIC0IRQ15
External Interrupt 15
(EIC0_EIRR:ER15 is set when an interrupt condition is detected at the corresponding input pin)
85
EIC0IRQ16
External Interrupt 16
(EIC0_EIRR:ER16 is set when an interrupt condition is detected at the corresponding input pin)
86
EIC0IRQ17
External Interrupt 17
(EIC0_EIRR:ER17 is set when an interrupt condition is detected at the corresponding input pin)
87
EIC0IRQ18
External Interrupt 18
(EIC0_EIRR:ER18 is set when an interrupt condition is detected at the corresponding input pin)
88
EIC0IRQ19
External Interrupt 19
(EIC0_EIRR:ER19 is set when an interrupt condition is detected at the corresponding input pin)
Document Number: DS707-00002-4v1-E
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
89
EIC0IRQ20
External Interrupt 20
(EIC0_EIRR:ER20 is set when an interrupt condition is detected at the corresponding input pin)
90
EIC0IRQ21
External Interrupt 21
(EIC0_EIRR:ER21 is set when an interrupt condition is detected at the corresponding input pin)
91
EIC0IRQ22
External Interrupt 22
(EIC0_EIRR:ER22 is set when an interrupt condition is detected at the corresponding input pin)
92
EIC0IRQ23
External Interrupt 23
(EIC0_EIRR:ER23 is set when an interrupt condition is detected at the corresponding input pin)
93
EIC0IRQ24
External Interrupt 24
(EIC0_EIRR:ER24 is set when an interrupt condition is detected at the corresponding input pin)
94
EIC0IRQ25
External Interrupt 25
(EIC0_EIRR:ER25 is set when an interrupt condition is detected at the corresponding input pin)
95
EIC0IRQ26
External Interrupt 26
(EIC0_EIRR:ER26 is set when an interrupt condition is detected at the corresponding input pin)
96
EIC0IRQ27
External Interrupt 27
(EIC0_EIRR:ER27 is set when an interrupt condition is detected at the corresponding input pin)
97
EIC0IRQ28
External Interrupt 28
(EIC0_EIRR:ER28 is set when an interrupt condition is detected at the corresponding input pin)
98
EIC0IRQ29
External Interrupt 29
(EIC0_EIRR:ER29 is set when an interrupt condition is detected at the corresponding input pin)
99
EIC0IRQ30
External Interrupt 30
(EIC0_EIRR:ER30 is set when an interrupt condition is detected at the corresponding input pin)
100
EIC0IRQ31
External Interrupt 31
(EIC0_EIRR:ER31 is set when an interrupt condition is detected at the corresponding input pin)
101
RTCIRQ
Real Time Clock Interrupt
(check RTC_WINS:[6:0] for detailed Real Time Clock interrupt cause)
Document Number: DS707-00002-4v1-E
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
102
SG0IRQ
Sound Generator 0 Interrupt
(SG0_CR1:ZAINT (zero amplitude interrupt),
SG0_CR1:TCINT (tone pulse count interrupt),
SG0_CR1:AMINT (amplitude match interrupt))
104
FRT0IRQ
Free Running Timer 0 Interrupt
(FRT0_TCCS:IVF (compare clear match/counter overflow),
FRT0_ETCCS:IRQZF (counter zero detection))
105
FRT1IRQ
Free Running Timer 1 Interrupt
(FRT1_TCCS:IVF (compare clear match/counter overflow),
FRT1_ETCCS:IRQZF (counter zero detection))
106
FRT2IRQ
Free Running Timer 2 Interrupt
(FRT2_TCCS:IVF (compare clear match/counter overflow),
FRT2_ETCCS:IRQZF (counter zero detection))
107
FRT3IRQ
Free Running Timer 3 Interrupt
(FRT3_TCCS:IVF (compare clear match/counter overflow),
FRT3_ETCCS:IRQZF (counter zero detection)
112
FRT16IRQ
Free Running Timer 16 Interrupt
(FRT16_TCCS:IVF (compare clear match/counter overflow),
FRT16_ETCCS:IRQZF (counter zero detection))
113
FRT17IRQ
Free Running Timer 17 Interrupt
(FRT17_TCCS:IVF (compare clear match/counter overflow),
FRT17_ETCCS:IRQZF (counter zero detection))
114
FRT18IRQ
Free Running Timer 18 Interrupt
(FRT0_TCCS:IVF (compare clear match/counter overflow),
FRT18_ETCCS:IRQZF (counter zero detection))
115
FRT19IRQ
Free Running Timer 19 Interrupt
(FRT19_TCCS:IVF (compare clear match/counter overflow),
FRT19_ETCCS:IRQZF (counter zero detection))
124
ICU2IRQ0
Input Capture Unit 2 channel 0 Interrupt (ICU2_ICEICS01:IDSE0)
125
ICU2IRQ1
Input Capture Unit 2 channel 1 Interrupt (ICU2_ICEICS01:IDSE1)
126
ICU3IRQ0
Input Capture Unit 3 channel 0 Interrupt (ICU3_ICEICS01:IDSE0)
127
ICU3IRQ1
Input Capture Unit 3 channel 1 Interrupt (ICU3_ICEICS01:IDSE1)
132
ICU18IRQ0
Input Capture Unit 18 channel 0 Interrupt (ICU18_ICEICS01:IDSE0)
133
ICU18IRQ1
Input Capture Unit 18 channel 1 Interrupt (ICU18_ICEICS01:IDSE1)
Document Number: DS707-00002-4v1-E
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
134
ICU19IRQ0
Input Capture Unit 19 channel 0 Interrupt (ICU19_ICEICS01:IDSE0)
135
ICU19IRQ1
Input Capture Unit 19 channel 1 Interrupt (ICU19_ICEICS01:IDSE1)
136
OCU0IRQ0
Output Compare Unit 1 channel 0 Interrupt
(OCU0_OSR01:ICP0)
137
OCU0IRQ1
Output Compare Unit 0 channel 1 Interrupt
(OCU0_OSR01:ICP1)
138
OCU1IRQ0
Output Compare Unit 1 channel 0 Interrupt
(OCU1_OSR01:ICP0)
139
OCU1IRQ1
Output Compare Unit 1 channel 1 Interrupt
(OCU1_OSR01:ICP1)
144
OCU16IRQ0
Output Compare Unit 16 channel 0 Interrupt
(OCU16_OSR01:ICP0)
145
OCU16IRQ1
Output Compare Unit 16 channel 1 Interrupt
(OCU16_OSR01:ICP1)
146
OCU17IRQ0
Output Compare Unit 17 channel 0 Interrupt
(OCU17_OSR01:ICP0)
147
OCU17IRQ1
Output Compare Unit 17 channel 1 Interrupt
(OCU17_OSR01:ICP1)
USART0IRQRX
LIN USART 0 Receive Interrupt
(UART0_SSR:RDF (receive data full), USART0_ESR:RXHRI (automatic reception of LIN header completed))
USART0IRQTX
LIN USART 0 Transmit Interrupt
(UART0_SSR:TDRE (transmission data empty), USART0_ECCR:RBI = 1 and USART0_ECCR:TBI = 1 and USART0_ECCR:BIE = 1 (bus idle interrupt),
USART0_ESR:LBSOF (transmitted last bit in synchronous/
asynchronous mode), USART0_ESR:TXHRI (automatic
transmission of LIN header completed))
USART0IRQERR
LIN USART 0 Error Interrupt
(USART0_SSR:PE (parity error), USART0_SSR:ORE (overrun error), USART0_SSR:FRE (framing error), USART0_CSCR:CRCERR (error found in checksum validation),
USART0_ESR:SYNFE (sync field detection timeout), USART0_ESR:BUSERR (bus error occurred), USART0_ESR:PEFRD (parity error in received frame ID))
152
153
154
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
USART6IRQRX
LIN USART 6 Receive Interrupt
(UART6_SSR:RDF (receive data full), USART6_ESR:RXHRI (automatic reception of LIN header completed))
USART6IRQTX
LIN USART 6 Transmit Interrupt
(UART0_SSR:TDRE (transmission data empty), USART6_ECCR:RBI = 1 and USART6_ECCR:TBI = 1 and USART6_ECCR:BIE = 1 (bus idle interrupt),
USART0_ESR:LBSOF (transmitted last bit in synchronous/
asynchronous mode), USART0_ESR:TXHRI (automatic
transmission of LIN header completed))
160
USART6IRQERR
LIN USART 6 Error Interrupt
(USART0_SSR:PE (parity error), USART6_SSR:ORE (overrun error), USART6_SSR:FRE (framing error), USART6_CSCR:CRCERR (error found in checksum validation),
USART0_ESR:SYNFE (sync field detection timeout), USART0_ESR:BUSERR (bus error occurred), USART0_ESR:PEFRD (parity error in received frame ID))
164
DMA0IRQD0
DMA0 Completion Interrupt for channels 0 + 8*n (DMACDIRQ1:DIRQ[24, 16, 8, 0] and DMACDIRQ2:DIRQ[56, 48,
40, 32])
165
DMA0IRQD1
DMA0 Completion Interrupt for channels 1 + 8*n (DMACDIRQ1:DIRQ[25, 17, 9, 1] and DMACDIRQ2:DIRQ[57, 49,
41, 33])
166
DMA0IRQD2
DMA0 Completion Interrupt for channels 2 + 8*n (DMACDIRQ1:DIRQ[26, 18, 10, 2] and DMACDIRQ2:DIRQ[58,50,
42, 34])
167
DMA0IRQD3
DMA0 Completion Interrupt for channels 3 + 8*n (DMACDIRQ1:DIRQ[27, 19, 11, 3] and DMACDIRQ2:DIRQ[59, 51,
43, 35])
168
DMA0IRQD4
DMA0 Completion Interrupt for channels 4 + 8*n (DMACDIRQ1:DIRQ[28, 20, 12, 4] and DMACDIRQ2:DIRQ[60, 52,
44, 36])
169
DMA0IRQD5
DMA0 Completion Interrupt for channels 5 + 8*n (DMACDIRQ1:DIRQ[29, 21, 13, 5] and DMACDIRQ2:DIRQ[61, 53,
45, 37])
170
DMA0IRQD6
DMA0 Completion Interrupt for channels 6 + 8*n (DMACDIRQ1:DIRQ[30, 22, 14, 6] and DMACDIRQ2:DIRQ[62, 54,
46, 38])
171
DMA0IRQD7
DMA0 Completion Interrupt for channels 7 + 8*n (DMACDIRQ1:DIRQ[31, 23, 15, 7] and DMACDIRQ2:DIRQ[63, 55,
47, 39])
158
159
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
172
DMA0IRQERR
DMA0 Error Interrupt
(DMACEDIRQ1:EDIRQ[31:0] and
DMACEDIRQ2:EDIRQ[63:32])
173
MSCTIRQ
Main Source Clock Timer Interrupt (SYSC_MAINSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
174
SSCTIRQ
Sub Source Clock Timer Interrupt (SYSC_SUBSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
175
RCSCTIRQ
RC Source Clock Timer Interrupt (SYSC_RCSCTSTATR:INTF is set when counter matches or is greater than the corresponding compare register)
176
SRCSCTIRQ
Slow RC Source Clock Timer Interrupt (SYSC_SRCSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
177
CORE0IRQ
CORTEX R4 Performance Monitor Interrupt
178
RLT0IRQ
Reload Timer 0 Interrupt
(RLT0_TMCSR:UF is set when reload timer counter underflows)
179
RLT1IRQ
Reload Timer 1 Interrupt
(RLT1_TMCSR:UF is set when reload timer counter underflows)
180
RLT2IRQ
Reload Timer 2 Interrupt
(RLT2_TMCSR:UF is set when reload timer counter underflows)
181
RLT3IRQ
Reload Timer 3 Interrupt
(RLT3_TMCSR:UF is set when reload timer counter underflows)
182
RLT4IRQ
Reload Timer 4 Interrupt
(RLT4_TMCSR:UF is set when reload timer counter underflows)
183
RLT5IRQ
Reload Timer 5 Interrupt
(RLT5_TMCSR:UF is set when reload timer counter underflows)
184
RLT6IRQ
Reload Timer 6 Interrupt
(RLT6_TMCSR:UF is set when reload timer counter underflows)
185
RLT7IRQ
Reload Timer 7 Interrupt
(RLT7_TMCSR:UF is set when reload timer counter underflows)
Document Number: DS707-00002-4v1-E
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
Interrupt Name
Interrupt Description
186
RLT8IRQ
Reload Timer 8 Interrupt
(RLT8_TMCSR:UF is set when reload timer counter underflows)
187
RLT9IRQ
Reload Timer 9 Interrupt
(RLT9_TMCSR:UF is set when reload timer counter underflows)
194
UDC0IRQ0
Up/Down Counter 0 channel 0 Interrupt
(UDN0_CS0:OVFF (overflow), UDFF (underflow), CMPF
(compare match))
195
UDC0IRQ1
Up/Down Counter 0 channel 1 Interrupt
(UDN0_CS1:OVFF (overflow), UDFF (underflow), CMPF
(compare match))
198
I2S0IRQ
I2S0 Interrupt
(check I2S0_STATUS:[31:24], [19], [17:16] for detailed interrupt cause)
199
I2S1IRQ
I2S1 Interrupt
(check I2S1_STATUS:[31:24], [19], [17:16] for detailed interrupt cause)
I2C0IRQ
I2C0 Interrupt
(I2C0_IBCSR_INT (masked by I2C0_IBCSR_INTE) set after
end of 1 byte data transfer or reception including acknowledge bit (bus master, addressed as slave, GCA received, Arbitration lost),
I2C0_IBCSR_BER (masked by I2C0_IBCSR_BEIE) indicates bus error (Start- or Stop-Condition detected at wrong
places))
203
I2C0IRQERR
I2C0 Error Interrupt
(I2C0_IBCSR_BER (masked by I2C0_IEIER_BEREIE) indicates bus error (Start- or Stop-Condition detected at wrong
places), I2C0_IBCSR_AL (masked by I2C0_IEIER_ALEIE)
indicates arbitration lost)
206
CRC0IRQ
CRC0 Interrupt
(CRC0_CFG:CIRQ set after checksum is calculated and
available in register)
PPG0IRQ
Programmable Pulse Generator 0 Interrupt
(PPG0_PCN:IRQF set depending on PPG0_PCN:IRS[2:0],
PPG0_EPCN1:TRIG set when PWM output generation is
started, PPG0_EPCN2:[7:0] see detailed description in docu)
Programmable Pulse Generator 0 Interrupt
PPG1IRQ
Programmable Pulse Generator 1 Interrupt
(PPG1_PCN:IRQF set depending on PPG1_PCN:IRS[2:0],
PPG1_EPCN1:TRIG set when PWM output generation is
started, PPG1_EPCN2:[7:0] see detailed description in docu)
202
208
209
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
210
211
212
213
214
215
216
217
218
219
Interrupt Name
Interrupt Description
PPG2IRQ
Programmable Pulse Generator 2 Interrupt
(PPG2_PCN:IRQF set depending on PPG2_PCN:IRS[2:0],
PP2_EPCN1:TRIG set when PWM output generation is started, PPG2_EPCN2:[7:0] see detailed description in docu)
PPG3IRQ
Programmable Pulse Generator 3 Interrupt
(PPG3_PCN:IRQF set depending on PPG3_PCN:IRS[2:0],
PPG0_EPCN1:TRIG set when PWM output generation is
started, PPG3_EPCN2:[7:0] see detailed description in docu)
PPG4IRQ
Programmable Pulse Generator 4 Interrupt
(PPG4_PCN:IRQF set depending on PPG4_PCN:IRS[2:0],
PPG4_EPCN1:TRIG set when PWM output generation is
started, PPG4_EPCN2:[7:0] see detailed description in docu)
PPG5IRQ
Programmable Pulse Generator 5 Interrupt
(PPG5_PCN:IRQF set depending on PPG5_PCN:IRS[2:0],
PPG5_EPCN1:TRIG set when PWM output generation is
started, PPG5_EPCN2:[7:0] see detailed description in docu)
PPG6IRQ
Programmable Pulse Generator 6 Interrupt
(PPG6_PCN:IRQF set depending on PPG6_PCN:IRS[2:0],
PPG6_EPCN1:TRIG set when PWM output generation is
started, PPG6_EPCN2:[7:0] see detailed description in docu)
PPG7IRQ
Programmable Pulse Generator 7 Interrupt
(PPG7_PCN:IRQF set depending on PPG7_PCN:IRS[2:0],
PPG7_EPCN1:TRIG set when PWM output generation is
started, PPG7_EPCN2:[7:0] see detailed description in docu)
PPG8IRQ
Programmable Pulse Generator 8 Interrupt
(PPG8_PCN:IRQF set depending on PPG8_PCN:IRS[2:0],
PPG8_EPCN1:TRIG set when PWM output generation is
started, PPG8_EPCN2:[7:0] see detailed description in docu)
PPG9IRQ
Programmable Pulse Generator 9 Interrupt
(PPG9_PCN:IRQF set depending on PPG9_PCN:IRS[2:0],
PPG9_EPCN1:TRIG set when PWM output generation is
started, PPG9_EPCN2:[7:0] see detailed description in docu)
PPG10IRQ
Programmable Pulse Generator 10 Interrupt
(PPG10_PCN:IRQF set depending on
PPG10_PCN:IRS[2:0], PPG10_EPCN1:TRIG set when
PWM output generation is started, PPG10_EPCN2:[7:0] see
detailed description in docu)
PPG11IRQ
Programmable Pulse Generator 11 Interrupt
(PPG11_PCN:IRQF set depending on
PPG11_PCN:IRS[2:0], PPG11_EPCN1:TRIG set when
PWM output generation is started, PPG11_EPCN2:[7:0] see
detailed description in docu)
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
220
221
222
223
232
233
234
235
Interrupt Name
Interrupt Description
PPG12IRQ
Programmable Pulse Generator 12 Interrupt
(PPG12_PCN:IRQF set depending on
PPG12_PCN:IRS[2:0], PPG12_EPCN1:TRIG set when
PWM output generation is started, PPG12_EPCN2:[7:0] see
detailed description in docu)
PPG13IRQ
Programmable Pulse Generator 13 Interrupt
(PPG13_PCN:IRQF set depending on
PPG13_PCN:IRS[2:0], PPG13_EPCN1:TRIG set when
PWM output generation is started, PPG13_EPCN2:[7:0] see
detailed description in docu)
PPG14IRQ
Programmable Pulse Generator 14 Interrupt
(PPG14_PCN:IRQF set depending on
PPG14_PCN:IRS[2:0], PPG14_EPCN1:TRIG set when
PWM output generation is started, PPG14_EPCN2:[7:0] see
detailed description in docu)
PPG15IRQ
Programmable Pulse Generator 15 Interrupt
(PPG15_PCN:IRQF set depending on
PPG15_PCN:IRS[2:0], PPG15_EPCN1:TRIG set when
PWM output generation is started, PPG15_EPCN2:[7:0] see
detailed description in docu)
PPG64IRQ
Programmable Pulse Generator 64 Interrupt
(PPG64_PCN:IRQF set depending on
PPG64_PCN:IRS[2:0], PPG64_EPCN1:TRIG set when
PWM output generation is started, PPG64_EPCN2:[7:0] see
detailed description in docu)
PPG65IRQ
Programmable Pulse Generator 65 Interrupt
(PPG65_PCN:IRQF set depending on
PPG65_PCN:IRS[2:0], PPG65_EPCN1:TRIG set when
PWM output generation is started, PPG65_EPCN2:[7:0] see
detailed description in docu)
PPG66IRQ
Programmable Pulse Generator 66 Interrupt
(PPG66_PCN:IRQF set depending on
PPG66_PCN:IRS[2:0], PPG66_EPCN1:TRIG set when
PWM output generation is started, PPG66_EPCN2:[7:0] see
detailed description in docu)
PPG67IRQ
Programmable Pulse Generator 67 Interrupt
(PPG67_PCN:IRQF set depending on
PPG67_PCN:IRS[2:0], PPG67_EPCN1:TRIG set when
PWM output generation is started, PPG67_EPCN2:[7:0] see
detailed description in docu)
Document Number: DS707-00002-4v1-E
Page 85
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Table 4-1: Interrupt Table (Continued)
Interrupt
Line No
236
237
238
239
Interrupt Name
Interrupt Description
PPG68IRQ
Programmable Pulse Generator 68 Interrupt
(PPG68_PCN:IRQF set depending on
PPG68_PCN:IRS[2:0], PPG68_EPCN1:TRIG set when
PWM output generation is started, PPG68_EPCN2:[7:0] see
detailed description in docu)
PPG69IRQ
Programmable Pulse Generator 69 Interrupt
(PPG69_PCN:IRQF set depending on
PPG69_PCN:IRS[2:0], PPG69_EPCN1:TRIG set when
PWM output generation is started, PPG69_EPCN2:[7:0] see
detailed description in docu)
PPG70IRQ
Programmable Pulse Generator 70 Interrupt
(PPG70_PCN:IRQF set depending on
PPG70_PCN:IRS[2:0], PPG70_EPCN1:TRIG set when
PWM output generation is started, PPG70_EPCN2:[7:0] see
detailed description in docu)
PPG71IRQ
Programmable Pulse Generator 71 Interrupt
(PPG71_PCN:IRQF set depending on
PPG71_PCN:IRS[2:0], PPG71_EPCN1:TRIG set when
PWM output generation is started, PPG71_EPCN2:[7:0] see
detailed description in docu)
Document Number: DS707-00002-4v1-E
Page 86
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4.2
NMI
Table 4-2: List of NMI
NMI Number
Source
0
EIC0NMI
1
SYSCNMILVD
Low Voltage Detect NMI (check SYSC_SYSERRR:LVD12IF,
SYSC_SYSERRR:LVD33IF, SYSC_SYSERRR:LVD50IF for detailed
NMI cause)
2
SYSCNMIERR
System Controller Error NMI (check SYSC_SYSERRR:RUNERRIF,
SYSC_SYSERRR:RUNWKERRIF,
SYSC_SYSERRR:PSSERRIF,
SYSC_SYSERRR:TRGERRIF,
SYSC_SYSERRR:RUNTRGEIF,
SYSC_SYSERRR:MOMISSIF,
SYSC_SYSERRR:SOMISSIF,
SYSC_SYSERRR:MPMISSIF,
SYSC_SYSERRR:SPMISSIF,
SYSC_SYSERRR:GPMISSIF,
SYSC_SYSERRR:PSSENEIF for detailed NMI cause)
3
WDGNMI
Watchdog NMI (WDG_INT:NMI_FLAG is set on Watchdog error condition if WDG_INT:NMI_EN is '1')
4
TPU0NMI
Timing Protection Unit NMI (check TPU0TIR:IR[7:0] bits for detailed
NMI cause)
Note: The Timing Protection Unit NMI is maskable within the TPU but
non-maskable on system level.
5
MPUXDMA0NMI
MPU DMA0 Access Violation NMI (MPUXDMA0_CTRL0:NMI is set
when a memory protection violation by DMA0 is detected)
9
IRQ0NMIERR
IRQ Double Error NMI (IRQ0_EEI:EENS bit is set when a double bit
error is detected in the IRQ0 Interrupt Vector RAM)
11
BECU0NMI
BECU0 Access Violation NMI (BECU0_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 0 bus)
12
BECU1NMI
BECU1 Access Violation NMI (BECU1_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 1 bus)
13
BECU3NMI
BECU3 Access Violation NMI (BECU3_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 3 bus)
Document Number: DS707-00002-4v1-E
Description
External Pin NMI (EIC0_NMIR:NMIINT)
Page 87
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4.3
DMA Overview
Table 4-3: Modules with DMA
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
0
EXTDMA0
External DMA Request 0 (external pin DMA0_DREQ0)
1
EXTDMA1
External DMA Request 1 (external pin DMA0_DREQ0)
8
EIC0DMA0
External Interrupt 0 DMA Request (EIC0_DRFR:DRF0)
9
EIC0DMA1
External Interrupt 1 DMA Request (EIC0_DRFR:DRF1)
10
EIC0DMA2
External Interrupt 2 DMA Request (EIC0_DRFR:DRF2)
11
EIC0DMA3
External Interrupt 3 DMA Request (EIC0_DRFR:DRF3)
12
EIC0DMA4
External Interrupt 4 DMA Request (EIC0_DRFR:DRF4)
13
EIC0DMA5
External Interrupt 5 DMA Request (EIC0_DRFR:DRF5)
14
EIC0DMA6
External Interrupt 6 DMA Request (EIC0_DRFR:DRF6)
15
EIC0DMA7
External Interrupt 7 DMA Request (EIC0_DRFR:DRF7)
16
EIC0DMA8
External Interrupt 8 DMA Request (EIC0_DRFR:DRF8)
17
EIC0DMA9
External Interrupt 9 DMA Request (EIC0_DRFR:DRF9)
18
EIC0DMA10
External Interrupt 10 DMA Request (EIC0_DRFR:DRF10)
19
EIC0DMA11
External Interrupt 11 DMA Request (EIC0_DRFR:DRF11)
20
EIC0DMA12
External Interrupt 12 DMA Request (EIC0_DRFR:DRF12)
21
EIC0DMA13
External Interrupt 13 DMA Request (EIC0_DRFR:DRF13)
22
EIC0DMA14
External Interrupt 14 DMA Request (EIC0_DRFR:DRF14)
23
EIC0DMA15
External Interrupt 15 DMA Request (EIC0_DRFR:DRF15)
24
EIC0DMA16
External Interrupt 16 DMA Request(EIC0_DRFR:DRF16)
25
EIC0DMA17
External Interrupt 17 DMA Request (EIC0_DRFR:DRF17)
26
EIC0DMA18
External Interrupt 18 DMA Request (EIC0_DRFR:DRF18)
27
EIC0DMA19
External Interrupt 19 DMA Request (EIC0_DRFR:DRF19)
28
EIC0DMA20
External Interrupt 20 DMA Request (EIC0_DRFR:DRF20)
29
EIC0DMA21
External Interrupt 21 DMA Request (EIC0_DRFR:DRF21)
30
EIC0DMA22
External Interrupt 22 DMA Request (EIC0_DRFR:DRF22)
31
EIC0DMA23
External Interrupt 23 DMA Request (EIC0_DRFR:DRF23)
32
EIC0DMA24
External Interrupt 24 DMA Request (EIC0_DRFR:DRF24)
33
EIC0DMA25
External Interrupt 25 DMA Request (EIC0_DRFR:DRF25)
Document Number: DS707-00002-4v1-E
Page 88
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MB9DF126B
Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
34
EIC0DMA26
External Interrupt 26 DMA Request (EIC0_DRFR:DRF26)
35
EIC0DMA27
External Interrupt 27 DMA Request (EIC0_DRFR:DRF27)
36
EIC0DMA28
External Interrupt 28 DMA Request (EIC0_DRFR:DRF28)
37
EIC0DMA29
External Interrupt 29 DMA Request (EIC0_DRFR:DRF29)
38
EIC0DMA30
External Interrupt 30 DMA Request (EIC0_DRFR:DRF30)
39
EIC0DMA31
External Interrupt 31 DMA Request (EIC0_DRFR:DRF31)
40
SG0DMA
Sound Generator 0 DMA Request
(SG0_CR1:AMINT* (amplitude match flag)
SG0_CR1:TCINT* (tone pulse count match flag)
SG0_CR1:ZAINT* (zero amplitude flag))
44
HSSPI0DMARX
HSSPI0 Receive DMA Request
(HSSPI0_RXF:RFMTS*
(RX FIFO fill level more than threshold))
45
HSSPI0DMAT
HSSPI0 Transmit DMA Request
(HSSPI0_TXF:TFLETS*
(TX FIFO fill level less or equal to threshold))
48
FRT0DMA
Free Running Timer 0 DMA Request
(FRT0_TCCS:IVF* (compare clear flag);
FRT0_ETCCS:IRQZF* (zero detect flag))
49
FRT1DMA
FFree Running Timer 1 DMA Request
(FRT1_TCCS:IVF* (compare clear flag);
FRT1_ETCCS:IRQZF* (zero detect flag))
50
FRT2DMA
Free Running Timer 2 DMA Request
(FRT2_TCCS:IVF* (compare clear flag);
FRT2_ETCCS:IRQZF* (zero detect flag))
51
FRT3DMA
Free Running Timer 3 DMA Request
(FRT3_TCCS:IVF* (compare clear flag);
FRT3_ETCCS:IRQZF* (zero detect flag))
64
FRT16DMA
Free Running Timer 16 DMA Request
(FRT16_TCCS:IVF* (compare clear flag);
FRT16_ETCCS:IRQZF* (zero detect flag))
65
FRT17DMA
Free Running Timer 17 DMA Request
(FRT17_TCCS:IVF* (compare clear flag);
FRT17_ETCCS:IRQZF* (zero detect flag))
66
FRT18DMA
Free Running Timer 18 DMA Request
(FRT18_TCCS:IVF* (compare clear flag);
FRT18_ETCCS:IRQZF* (zero detect flag))
Document Number: DS707-00002-4v1-E
Page 89
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MB9DF126B
Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
67
FRT19DMA
Free Running Timer 19 DMA Request
(FRT19_TCCS:IVF* (compare clear flag);
FRT19_ETCCS:IRQZF* (zero detect flag))
84
ICU2DMA0
Input Capture Unit 2 channel 0 DMA Request (ICU2_ICEICS01:ICP0*)
85
ICU2DMA1
Input Capture Unit 2 channel 1 DMA Request (ICU2_ICEICS01:ICP1*)
86
ICU3DMA0
Input Capture Unit 3 channel 0 DMA Request (ICU2_ICEICS01:ICP0*)
87
ICU3DMA1
Input Capture Unit 3 channel 1 DMA Request (ICU2_ICEICS01:ICP1*)
116
ICU18DMA0
Input Capture Unit 18 channel 0 DMA Request (ICU18_ICEICS01:ICP0*)
117
ICU18DMA1
Input Capture Unit 18 channel 1 DMA Request (ICU18_ICEICS01:ICP1*)
118
ICU19DMA0
Input Capture Unit 19 channel 0 DMA Request (ICU19_ICEICS01:ICP0*)
119
ICU19DMA1
Input Capture Unit 19 channel 1 DMA Request (ICU19_ICEICS01:ICP1*)
144
OCU0DMA0
Output Compare Unit 0 channel 0 DMA Request
(OCU0_OSR01:ICP0*)
145
OCU0DMA1
Output Compare Unit 0 channel 1 DMA Request
(OCU0_OSR01:ICP1*)
146
OCU1DMA0
Output Compare Unit 1 channel 0 DMA Request
(OCU1_OSR01:ICP0*)
147
OCU1DMA1
Output Compare Unit 1 channel 1 DMA Request
(OCU1_OSR01:ICP1*)
176
OCU16DMA0
Output Compare Unit 16 channel 0 DMA Request
(OCU16_OSR01:ICP0*)
177
OCU16DMA1
Output Compare Unit 16 channel 1 DMA Request
(OCU16_OSR01:ICP1*)
178
OCU17DMA0
Output Compare Unit 17 channel 0 DMA Request
(OCU17_OSR01:ICP0*)
179
OCU17DMA1
Output Compare Unit 17 channel 1 DMA Request
(OCU17_OSR01:ICP1*)
208
USART0DMARX
LIN USART 0 Receive DMA Request
(USART0_SSR:RDRF* (RX data full flag))
Document Number: DS707-00002-4v1-E
Page 90
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MB9DF126B
Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
209
USART0DMATX
LIN USART 0 Transmit DMA Request
(USART0_SSR:TDRE* (TX data empty flag))
220
USART6DMARX
LIN USART 6 Receive DMA Request
(USART6_SSR:RDRF* (RX data full flag))
221
USART6DMATX
LIN USART 6 Transmit DMA Request
(USART6_SSR:TDRE* (TX data empty flag))
232
I2C0DMARX
I2C0 Receive DMA Request (I2C0_IBCSR:INT*)
233
I2C0DMATX
I2C0 Transmit DMA Request (I2C0_IBCSR:INT*)
244
PPG0DMA
Programmable Pulse Generator 0 DMA Request
(PPG0_PCN:IRQF*)
245
PPG1DMA
Programmable Pulse Generator 1 DMA Request
(PPG1_PCN:IRQF*)
246
PPG2DMA
Programmable Pulse Generator 2 DMA Request
(PPG2_PCN:IRQF*)
247
PPG3DMA
Programmable Pulse Generator 3 DMA Request
(PPG3_PCN:IRQF*)
248
PPG4DMA
Programmable Pulse Generator 4 DMA Request
(PPG4_PCN:IRQF*)
249
PPG5DMA
Programmable Pulse Generator 5 DMA Request
(PPG5_PCN:IRQF*)
250
PPG6DMA
Programmable Pulse Generator 6 DMA Request
(PPG6_PCN:IRQF*)
251
PPG7DMA
Programmable Pulse Generator 7 DMA Request
(PPG7_PCN:IRQF*)
252
PPG8DMA
Programmable Pulse Generator 8 DMA Request
(PPG8_PCN:IRQF*)
253
PPG9DMA
Programmable Pulse Generator 9 DMA Request
(PPG9_PCN:IRQF*)
254
PPG10DMA
Programmable Pulse Generator 10 DMA Request
(PPG10_PCN:IRQF*)
255
PPG11DMA
Programmable Pulse Generator 11 DMA Request
(PPG11_PCN:IRQF*)
256
PPG12DMA
Programmable Pulse Generator 12 DMA Request
(PPG12_PCN:IRQF*)
257
PPG13DMA
Programmable Pulse Generator 13 DMA Request
(PPG13_PCN:IRQF*)
Document Number: DS707-00002-4v1-E
Page 91
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MB9DF126B
Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
258
PPG14DMA
Programmable Pulse Generator 14 DMA Request
(PPG14_PCN:IRQF*)
259
PPG15DMA
Programmable Pulse Generator 15 DMA Request
(PPG15_PCN:IRQF*)
308
PPG64DMA
Programmable Pulse Generator 64 DMA Request
(PPG64_PCN:IRQF*)
309
PPG65DMA
Programmable Pulse Generator 65 DMA Request
(PPG65_PCN:IRQF*)
310
PPG66DMA
Programmable Pulse Generator 66 DMA Request
(PPG66_PCN:IRQF*)
311
PPG67DMA
Programmable Pulse Generator 67 DMA Request
(PPG67_PCN:IRQF*)
312
PPG68DMA
Programmable Pulse Generator68 DMA Request
(PPG68_PCN:IRQF*)
313
PPG69DMA
Programmable Pulse Generator 69 DMA Request
(PPG69_PCN:IRQF*)
314
PPG70DMA
Programmable Pulse Generator 70 DMA Request
(PPG70_PCN:IRQF*)
315
PPG71DMA
Programmable Pulse Generator 71 DMA Request
(PPG71_PCN:IRQF*)
372
ADC0DMA
ADC0 Conversion End DMA Request
(ADC0_CS1:INT* (end of conversion flag))
373
ADC0DMA2
ADC0 Scan End DMA Request
(ADC0_CS3:INT2* (end of scan flag))
376
RLT0DMA
Reload Timer 0 DMA Request
(RTL0_TMCSR:UF* (underflow flag))
377
RLT1DMA
Reload Timer 1 DMA Request
(RTL1_TMCSR:UF* (underflow flag))
378
RLT2DMA
Reload Timer 2 DMA Request
(RTL2_TMCSR:UF* (underflow flag))
379
RLT3DMA
Reload Timer 3 DMA Request
(RTL3_TMCSR:UF* (underflow flag))
380
RLT4DMA
Reload Timer 4 DMA Request
(RTL4_TMCSR:UF* (underflow flag))
381
RLT5DMA
Reload Timer 5 DMA Request
(RTL5_TMCSR:UF* (underflow flag))
Document Number: DS707-00002-4v1-E
Page 92
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Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
382
RLT6DMA
Reload Timer 6 DMA Request
(RTL6_TMCSR:UF* (underflow flag))
383
RLT7DMA
Reload Timer 7 DMA Request
(RTL7_TMCSR:UF* (underflow flag))
384
RLT8DMA
Reload Timer 8 DMA Request
(RTL8_TMCSR:UF* (underflow flag))
385
RLT9DMA
Reload Timer 9 DMA Request
(RTL9_TMCSR:UF* (underflow flag))
408
I2S0DMARX
I2S0 Receive DMA Request
(I2S0_STATUS:RXFI* (receive FIFO full))
409
I2S0DMATX
I2S0 Transmit DMA Request
(I2S0_STATUS:TXFI* (transmit FIFO empty))
410
I2S1DMARX
I2S0 Receive DMA Request
(I2S1_STATUS:RXFI* (receive FIFO full))
411
I2S1DMATX
I2S0 Transmit DMA Request
(I2S1_STATUS:TXFI* (transmit FIFO empty))
424
CRC0DMA
CRC0 DMA Request (CRC0_CFG:CIRQ* (CRC calculated flag))
426
SPI0DMARX
SPI0 Receive DMA Request
(SPI0_RXF:RFMTS* (RX FIFO fill level more than threshold))
427
SPI0DMATX
SPI0 Transmit DMA Request
(SPI0_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
428
SPI1DMARX
SPI1 Receive DMA Request
(SPI1_RXF:RFMTS* (RX FIFO fill level more than threshold))
429
SPI1DMATX
SPI1 Transmit DMA Request
(SPI1_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
430
SPI2DMARX
SPI2 Receive DMA Request
(SPI2_RXF:RFMTS* (RX FIFO fill level more than threshold))
431
SPI2DMATX
SPI2 Transmit DMA Request
(SPI2_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
450
EEFLASHDMA
EE Flash DMA Request (EEFCFG_WSR:ST[1:0])
451
ARH0DMA0
Remote Handler DMA Request 0 (ARH0_TBCTRL0:TBIRQ*)
452
ARH0DMA1
Remote Handler DMA Request 1 (ARH0_TBCTRL1:TBIRQ*)
453
ARH0DMA2
Remote Handler DMA Request 2 (ARH0_TBCTRL2:TBIRQ*)
454
ARH0DMA3
Remote Handler DMA Request 3 (ARH0_TBCTRL3:TBIRQ*)
455
ARH0DMA4
Remote Handler DMA Request 4 (ARH0_TBCTRL4:TBIRQ*)
Document Number: DS707-00002-4v1-E
Page 93
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Table 4-3: Modules with DMA (Continued)
DMA Client
(Interface)
DMA Client
(Interface) Name
DMA Client (Interface) Description
456
ARH0DMA5
Remote Handler DMA Request 5 (ARH0_TBCTRL5:TBIRQ*)
457
ARH0DMA6
Remote Handler DMA Request 6 (ARH0_TBCTRL6:TBIRQ*)
458
ARH0DMA7
Remote Handler DMA Request 7 (ARH0_TBCTRL7:TBIRQ*)
459
ARH0DMA8
Remote Handler DMA Request 8 (ARH0_TBCTRL8:TBIRQ*)
460
ARH0DMA9
Remote Handler DMA Request 9 (ARH0_TBCTRL9:TBIRQ*)
461
ARH0DMA10
Remote Handler DMA Request 10 (ARH0_TBCTRL10:TBIRQ*)
462
ARH0DMA11
Remote Handler DMA Request 11 (ARH0_TBCTRL11:TBIRQ*)
463
ARH0DMA12
Remote Handler DMA Request 12 (ARH0_TBCTRL12:TBIRQ*)
464
ARH0DMA13
Remote Handler DMA Request 13 (ARH0_TBCTRL13:TBIRQ*)
465
ARH0DMA14
Remote Handler DMA Request 14 (ARH0_TBCTRL14:TBIRQ*)
466
ARH0DMA15
Remote Handler DMA Request 15 (ARH0_TBCTRL15:TBIRQ*)
467
PPUDMA
PPU DMA Request
(DMA is triggered by sucessful PPU UNLOCK (PPU0_UNLOCK)
indicated by PPU0_ST:LST = 0)
Document Number: DS707-00002-4v1-E
Page 94
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MB9DF126B
4.4
PPU
Table 4-4: List of PPU channels
-
-
SMC0
SMC1
-
ADC0
SPI0
SPI1
-
RLT0 USART0
FRT0
RLT1
-
-
FRT1
-
OCU0
-
-
PPCUSER
OCU1
-
PPGGRP0
PPCPRIV
-
PPG0
PPGGRP1
-
PPG64
PPG1
-
PPG65
-
-
-
0
-
-
-
SMC2
SMC3
-
SPI2
-
RLT2
RLT3
FRT3
FRT2
ICU2
ICU3
-
DBG0
WDG
PPGGRP3
PPGGRP2
PPG2
PPG3
-
PPG66
-
PPG67
-
-
SMC4
SMC5
-
ARH0
-
-
RLT4
RLT5
-
-
-
MSCT
SSCT
-
PPG4
PPG5
-
PPG68
-
PPG69
-
-
SMCTG0
-
-
-
RLT6 USART6
RLT7
-
-
-
RCSCT
SRCSCT
-
PPG6
PPG7
-
PPG70
-
PPG71
-
-
-
-
I2C0
-
-
RLT8
RLT9
-
-
-
-
-
PPG8
PPG9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG10
PPG11
-
-
-
-
PPG12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG13
PPG14
-
-
-
-
-
-
SG0
-
I2S0
HSSPI0
-
CAN0
-
-
FRT16
-
-
OCU16
-
-
PPGGRP16
-
PPG15
-
-
-
-
-
-
-
I2S1
-
CAN1
CAN2
-
FRT17
-
ICU18 FRT18
-
OCU17
-
-
PPGGRP17
-
-
-
-
-
PPU0_PA15
PPU0_PR15
-
-
-
-
-
-
-
-
-
-
ICU19 FRT19
-
-
-
-
-
PPU0_PA14
PPU0_PR14
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
3
-
-
-
-
-
UDC0
-
-
-
-
-
-
-
CRC0
-
-
-
4
-
-
5
-
-
-
-
-
-
-
-
-
-
-
-
-
EICU0
-
-
-
6
-
-
7
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC
-
-
-
8
-
-
-
-
-
-
-
-
-
-
-
-
PPGGLC0
EEFCFG
-
-
EBI
-
9
-
PPU0_PA13
PPU0_PR13
-
PPU0_PA12
PPU0_PR12
-
PPU0_PA11
PPU0_PR11
-
PPU0_PA10
PPU0_PR10
-
PPU0_PA9
PPU0_PR9
-
PPU0_PA8
PPU0_PR8
-
PPU0_PA7
PPU0_PR7
-
PPU0_PA6
PPU0_PR6
-
PPU0_PA5
PPU0_PR5
PPGGLC1
PPU0_PA4
PPU0_PR4
-
PPU0_PA3
PPU0_PR3
-
PPU0_PA2
PPU0_PR2
-
PPU0_PA1
PPU0_PR1
-
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PPU0_PA0
PPU0_PR0
Note:
In general, a PPU channel controls the access in user mode to the corresponding peripheral.
However, there are a few exceptions:
— PPCPRIV controls the access to PPC in privileged mode
— PPCUSER controls the access to PPC in user mode
— MSCT, SSCT, RCSCT and SRCSCT control the access to the source clock timers within the System
Controller, i.e. the registers SYSC_MSCT*, SYSC_SSCT*, SYSC_RCSCT* and SYSC_SRCSCT, after
the corresponding source clock stabilization time has elapsed
Document Number: DS707-00002-4v1-E
Page 95
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MB9DF126B
— WDG controls the write access in user mode to the Watchdog trigger registers, so WDG has no read
attribute
— Read attribute for DBG0 is always enabled. Even privilege mode access for DBG0 needs PPU to be
enabled.
4.5
Master ID
Table 4-5: List of Master IDs used on MB9DF126 device
Master name
Master ID (USER signal values)
CPU_S0
0x04
DMA_SI
0x08
DAP_AHB
0x01
Document Number: DS707-00002-4v1-E
Page 96
MB9DF126
MB9DF126B
5 I/O map
Table 5-1 Memory layout of HSSPI0 registers
Offset
+3
+2
+1
0xB0000000
HSSPI0_MCTRL
00000000 00000000 00000000 00000000
0xB0000004
HSSPI0_PCC0
00000000 00000001 00000000 00000000
0xB0000008
HSSPI0_PCC1
00000000 00000001 00000000 00000000
0xB000000C
HSSPI0_PCC2
00000000 00000001 00000000 00000000
0xB0000010
HSSPI0_PCC3
00000000 00000001 00000000 00000000
0xB0000014
HSSPI0_TXF
00000000 00000000 00000000 00000000
0xB0000018
HSSPI0_TXE
00000000 00000000 00000000 00000000
0xB000001C
HSSPI0_TXC
00000000 00000000 00000000 00000000
0xB0000020
HSSPI0_RXF
00000000 00000000 00000000 00000000
0xB0000024
HSSPI0_RXE
00000000 00000000 00000000 00000000
0xB0000028
HSSPI0_RXC
00000000 00000000 00000000 00000000
0xB000002C
HSSPI0_FAULTF
00000000 00000000 00000000 00000000
0xB0000030
HSSPI0_FAULTC
00000000 00000000 00000000 00000000
0xB0000034
Document Number: DS707-00002-4v1-E
read0
00000000 00000000
HSSPI0_DMDMAEN
00000000
+0
HSSPI0_DMCFG
00000001
Page 97
MB9DF126
MB9DF126B
Table 5-1 Memory layout of HSSPI0 registers (Continued)
Offset
+3
+2
+1
+0
0xB0000038
HSSPI0_DMTRP
00000000
HSSPI0_DMPSEL
00000000
HSSPI0_DMSTOP
00000000
HSSPI0_DMSTART
00000000
0xB000003C
0xB0000040
0xB0000044
HSSPI0_DMBCS
00000000 00000000
HSSPI0_DMBCC
00000000 00000000
HSSPI0_DMSTATUS
00000000 00000000 00000000 00000000
read0
00000000 00000000
HSSPI0_RXBITCNT
00000000
0xB0000048
HSSPI0_RXSHIFT
00000000 00000000 00000000 00000000
0xB000004C
HSSPI0_FIFOCFG
00000000 00000000 00000000 01110111
0xB0000050
HSSPI0_TXFIFO0
00000000 00000000 00000000 00000000
0xB0000054
HSSPI0_TXFIFO1
00000000 00000000 00000000 00000000
0xB0000058
HSSPI0_TXFIFO2
00000000 00000000 00000000 00000000
0xB000005C
HSSPI0_TXFIFO3
00000000 00000000 00000000 00000000
0xB0000060
HSSPI0_TXFIFO4
00000000 00000000 00000000 00000000
0xB0000064
HSSPI0_TXFIFO5
00000000 00000000 00000000 00000000
0xB0000068
HSSPI0_TXFIFO6
00000000 00000000 00000000 00000000
0xB000006C
HSSPI0_TXFIFO7
00000000 00000000 00000000 00000000
0xB0000070
HSSPI0_TXFIFO8
00000000 00000000 00000000 00000000
0xB0000074
HSSPI0_TXFIFO9
00000000 00000000 00000000 00000000
0xB0000078
HSSPI0_TXFIFO10
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
HSSPI0_TXBITCNT
00000000
Page 98
MB9DF126
MB9DF126B
Table 5-1 Memory layout of HSSPI0 registers (Continued)
Offset
+3
+2
+1
0xB000007C
HSSPI0_TXFIFO11
00000000 00000000 00000000 00000000
0xB0000080
HSSPI0_TXFIFO12
00000000 00000000 00000000 00000000
0xB0000084
HSSPI0_TXFIFO13
00000000 00000000 00000000 00000000
0xB0000088
HSSPI0_TXFIFO14
00000000 00000000 00000000 00000000
0xB000008C
HSSPI0_TXFIFO15
00000000 00000000 00000000 00000000
0xB0000090
HSSPI0_RXFIFO0
00000000 00000000 00000000 00000000
0xB0000094
HSSPI0_RXFIFO1
00000000 00000000 00000000 00000000
0xB0000098
HSSPI0_RXFIFO2
00000000 00000000 00000000 00000000
0xB000009C
HSSPI0_RXFIFO3
00000000 00000000 00000000 00000000
0xB00000A0
HSSPI0_RXFIFO4
00000000 00000000 00000000 00000000
0xB00000A4
HSSPI0_RXFIFO5
00000000 00000000 00000000 00000000
0xB00000A8
HSSPI0_RXFIFO6
00000000 00000000 00000000 00000000
0xB00000AC
HSSPI0_RXFIFO7
00000000 00000000 00000000 00000000
0xB00000B0
HSSPI0_RXFIFO8
00000000 00000000 00000000 00000000
0xB00000B4
HSSPI0_RXFIFO9
00000000 00000000 00000000 00000000
0xB00000B8
HSSPI0_RXFIFO10
00000000 00000000 00000000 00000000
0xB00000BC
HSSPI0_RXFIFO11
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 99
MB9DF126
MB9DF126B
Table 5-1 Memory layout of HSSPI0 registers (Continued)
Offset
+3
+2
+1
+0
0xB00000C0
HSSPI0_RXFIFO12
00000000 00000000 00000000 00000000
0xB00000C4
HSSPI0_RXFIFO13
00000000 00000000 00000000 00000000
0xB00000C8
HSSPI0_RXFIFO14
00000000 00000000 00000000 00000000
0xB00000CC
HSSPI0_RXFIFO15
00000000 00000000 00000000 00000000
0xB00000D0
HSSPI0_CSCFG
00000000 00000000 00000000 00000000
0xB00000D4
HSSPI0_CSITIME
00000000 00000000 11111111 11111111
0xB00000D8
HSSPI0_CSAEXT
00000000 00000000 00000000 00000000
0xB00000DC
HSSPI0_RDCSDC1
00000000 00000000
HSSPI0_RDCSDC0
00000000 00000000
0xB00000E0
HSSPI0_RDCSDC3
00000000 00000000
HSSPI0_RDCSDC2
00000000 00000000
0xB00000E4
HSSPI0_RDCSDC5
00000000 00000000
HSSPI0_RDCSDC4
00000000 00000000
0xB00000E8
HSSPI0_RDCSDC7
00000000 00000000
HSSPI0_RDCSDC6
00000000 00000000
0xB00000EC
HSSPI0_WRCSDC1
00000000 00000000
HSSPI0_WRCSDC0
00000000 00000000
0xB00000F0
HSSPI0_WRCSDC3
00000000 00000000
HSSPI0_WRCSDC2
00000000 00000000
0xB00000F4
HSSPI0_WRCSDC5
00000000 00000000
HSSPI0_WRCSDC4
00000000 00000000
0xB00000F8
HSSPI0_WRCSDC7
00000000 00000000
HSSPI0_WRCSDC6
00000000 00000000
0xB00000FC
HSSPI0_MID
00000000 00000000 00000000 00000001
0xB0000100B0077FFC
reserved
00000000 00000000 00000000 0000000X
Document Number: DS707-00002-4v1-E
Page 100
MB9DF126
MB9DF126B
Table 5-1 Memory layout of HSSPI0 registers (Continued)
Offset
+3
0xB0078000
+2
read0
00000000 00000000
+1
RICFG8_HSSPI0MSTART
00000000 00000000
0xB0078004B007FC00
reserved
00000000 00000000 00000000 0000000X
0xB007FC04
BSU8_BTST
00000000 00000000 00000000 00000000
0xB007FC08B007FC0C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB007FC10
BSU8_PEN0
00000000 00000000 00000000 00000000
0xB007FC14B007FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 101
MB9DF126
MB9DF126B
Table 5-2 Memory layout of EBI registers
Offset
+3
+2
+1
0xB0180000
EBI_UNLOCK
00000000 00000000 00000000 00000000
0xB0180004
EBI_LSTSR
00000000 00000000 00000000 00000000
0xB0180008
EBI_SFMR0
00000000 00000000 00000000 00000000
0xB018000C
EBI_SFMR1
00000000 00000000 00000000 00000000
0xB0180010
EBI_SFMR2
00000000 00000000 00000000 00000000
0xB0180014
EBI_SFMR3
00000000 00000000 00000000 00000000
0xB0180018
EBI_SFMR4
00000000 00000000 00000000 00000000
0xB018001C
EBI_SFMR5
00000000 00000000 00000000 00000000
0xB0180020
EBI_SFMR6
00000000 00000000 00000000 00000000
0xB0180024
EBI_SFMR7
00000000 00000000 00000000 00000000
0xB0180028
EBI_SFACCR0
00000101 01011111 11110000 00001111
0xB018002C
EBI_SFACCR1
00000101 01011111 11110000 00001111
0xB0180030
EBI_SFACCR2
00000101 01011111 11110000 00001111
0xB0180034
EBI_SFACCR3
00000101 01011111 11110000 00001111
0xB0180038
EBI_SFACCR4
00000101 01011111 11110000 00001111
Document Number: DS707-00002-4v1-E
+0
Page 102
MB9DF126
MB9DF126B
Table 5-2 Memory layout of EBI registers (Continued)
Offset
+3
+2
+1
0xB018003C
EBI_SFACCR5
00000101 01011111 11110000 00001111
0xB0180040
EBI_SFACCR6
00000101 01011111 11110000 00001111
0xB0180044
EBI_SFACCR7
00000101 01011111 11110000 00001111
0xB0180048
EBI_SFADDCR0
00000000 00001111 00000000 00000000
0xB018004C
EBI_SFADDCR1
00000000 00001111 00000000 00010000
0xB0180050
EBI_SFADDCR2
00000000 00001111 00000000 00100000
0xB0180054
EBI_SFADDCR3
00000000 00001111 00000000 00110000
0xB0180058
EBI_SFADDCR4
00000000 00001111 00000000 01000000
0xB018005C
EBI_SFADDCR5
00000000 00001111 00000000 01010000
0xB0180060
EBI_SFADDCR6
00000000 00001111 00000000 01100000
0xB0180064
EBI_SFADDCR7
00000000 00001111 00000000 01110000
0xB0180068
EBI_SDMODCR
00000000 00000000 00010011 00000000
0xB018006C
EBI_SDRCR
00000000 00000000 00000000 00101000
0xB0180070
EBI_SDPCR
00000000 00000000 00000000 00000000
0xB0180074
EBI_SDTCR
00000000 01000010 00010001 01000001
0xB0180078
EBI_SDCOMDR
00000000 00000000 00000000 00000000
0xB018007C
EBI_ERRR
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 103
MB9DF126
MB9DF126B
Table 5-2 Memory layout of EBI registers (Continued)
Offset
+3
+2
+1
0xB0180080 0xB01FFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB01FFC04
BSU10_BTST
00000000 00000000 00000000 00000000
0xB01FFC08 0xB01FFC0C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB01FFC10
BSU10_PEN0
00000000 00000000 00000000 00000000
0xB01FFC14 0xB01FFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 104
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400000
IRQ0_NMIST
00000000 00000000 00001111 00100000
IRQ0_NMIVAS
00000000 00000000 00000000 00000000
0xB0400008
IRQ0_IRQST
00000000 00011111 00000010 00000000
IRQ0_IRQVAS
00000000 00000000 00000000 00000000
0xB0400010
IRQ0_NMIVA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400018
IRQ0_NMIVA3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400020
IRQ0_NMIVA5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA4
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400028
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400030
IRQ0_NMIVA9
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400038
IRQ0_NMIVA11
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400040
IRQ0_NMIVA13
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA12
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400048 0xB0400088
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400090
IRQ0_IRQVA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400098
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000A8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 105
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04000B8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000C0
IRQ0_IRQVA13
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000C8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA14
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04000D0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000D8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000E0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000E8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000F0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400100
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400108
IRQ0_IRQVA31
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA30
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400110
IRQ0_IRQVA33
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA32
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400118
IRQ0_IRQVA35
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA34
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400120
IRQ0_IRQVA37
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA36
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400128
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA38
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400130
IRQ0_IRQVA41
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400138
IRQ0_IRQVA43
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA42
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
Document Number: DS707-00002-4v1-E
Page 106
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400140
IRQ0_IRQVA45
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA44
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400148
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400150
IRQ0_IRQVA49
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400158
IRQ0_IRQVA51
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA50
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400160
IRQ0_IRQVA53
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA52
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400168
IRQ0_IRQVA55
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA54
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400170
IRQ0_IRQVA57
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA56
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400178
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400180
IRQ0_IRQVA61
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400188
IRQ0_IRQVA63
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA62
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400190
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400198
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04001A0
IRQ0_IRQVA69
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04001A8
IRQ0_IRQVA71
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA70
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001B0
IRQ0_IRQVA73
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA72
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001B8
IRQ0_IRQVA75
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA74
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001C0
IRQ0_IRQVA77
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA76
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
Document Number: DS707-00002-4v1-E
Page 107
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04001C8
IRQ0_IRQVA79
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA78
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001D0
IRQ0_IRQVA81
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA80
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001D8
IRQ0_IRQVA83
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA82
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001E0
IRQ0_IRQVA85
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA84
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001E8
IRQ0_IRQVA87
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA86
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001F0
IRQ0_IRQVA89
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA88
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001F8
IRQ0_IRQVA91
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA90
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400200
IRQ0_IRQVA93
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA92
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400208
IRQ0_IRQVA95
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA94
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400210
IRQ0_IRQVA97
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA96
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400218
IRQ0_IRQVA99
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA98
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400220
IRQ0_IRQVA101
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA100
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400228
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
IRQ0_IRQVA102
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400230
IRQ0_IRQVA105
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA104
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400238
IRQ0_IRQVA107
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA106
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400240
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400248
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 108
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400250
IRQ0_IRQVA113
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA112
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400258
IRQ0_IRQVA115
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA114
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400260
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400268
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400270
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400278
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400280
IRQ0_IRQVA125
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA124
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400288
IRQ0_IRQVA127
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA126
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400290
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400298
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002A0
IRQ0_IRQVA133
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA132
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002A8
IRQ0_IRQVA135
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA134
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002B0
IRQ0_IRQVA137
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA136
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002B8
IRQ0_IRQVA139
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA138
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002C8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002D0
IRQ0_IRQVA145
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA144
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
Document Number: DS707-00002-4v1-E
Page 109
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04002D8
IRQ0_IRQVA147
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA146
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002E0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002E8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002F0
IRQ0_IRQVA153
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA152
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA154
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400300
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400308
IRQ0_IRQVA159
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA158
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400310
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA160
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400318
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400320
IRQ0_IRQVA165
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA164
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400328
IRQ0_IRQVA167
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA166
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400330
IRQ0_IRQVA169
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA168
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400338
IRQ0_IRQVA171
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA170
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400340
IRQ0_IRQVA173
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA172
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400348
IRQ0_IRQVA175
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA174
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400350
IRQ0_IRQVA177
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA176
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400358
IRQ0_IRQVA179
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA178
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
Document Number: DS707-00002-4v1-E
Page 110
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400360
IRQ0_IRQVA181
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA180
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400368
IRQ0_IRQVA183
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA182
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400370
IRQ0_IRQVA185
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA184
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400378
IRQ0_IRQVA187
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA186
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400380
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400388
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400390
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400398
IRQ0_IRQVA195
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA194
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003A8
IRQ0_IRQVA199
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA198
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003B8
IRQ0_IRQVA203
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA202
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003C8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA206
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003D0
IRQ0_IRQVA209
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA208
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003D8
IRQ0_IRQVA211
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA210
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003E0
IRQ0_IRQVA213
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA212
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
Document Number: DS707-00002-4v1-E
Page 111
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04003E8
IRQ0_IRQVA215
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA214
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003F0
IRQ0_IRQVA217
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA216
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003F8
IRQ0_IRQVA219
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA218
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400400
IRQ0_IRQVA221
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA220
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400408
IRQ0_IRQVA223
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA222
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400410
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400418
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400420
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400428
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400430
IRQ0_IRQVA233
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA232
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400438
IRQ0_IRQVA235
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA234
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400440
IRQ0_IRQVA237
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA236
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400448
IRQ0_IRQVA239
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA238
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400450 0xB0400888
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400890
IRQ0_NMIPL1
00000000 00000000 00001111 00001111
IRQ0_NMIPL0
00001111 00001111 00001111 00000000
0xB0400898
IRQ0_NMIPL3
00000000 00000000 00001111 00001111
IRQ0_NMIPL2
00001111 00000000 00001111 00000000
0xB04008A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 112
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04008A8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL0
00000000 00000000 00011111 00011111
0xB04008B8
IRQ0_IRQPL3
00000000 00011111 00011111 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008C8
IRQ0_IRQPL7
00011111 00011111 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008D0
IRQ0_IRQPL9
00000000 00011111 00011111 00011111
IRQ0_IRQPL8
00011111 00011111 00011111 00011111
0xB04008D8
IRQ0_IRQPL11
00000000 00000000 00011111 00011111
IRQ0_IRQPL10
00011111 00011111 00011111 00000000
0xB04008E0
IRQ0_IRQPL13
00011111 00011111 00011111 00011111
IRQ0_IRQPL12
00011111 00011111 00011111 00000000
0xB04008E8
IRQ0_IRQPL15
00011111 00011111 00011111 00000000
IRQ0_IRQPL14
00000000 00000000 00011111 00011111
0xB04008F0
IRQ0_IRQPL17
00011111 00011111 00011111 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008F8
IRQ0_IRQPL19
00011111 00011111 00011111 00011111
IRQ0_IRQPL18
00011111 00011111 00011111 00011111
0xB0400900
IRQ0_IRQPL21
00011111 00011111 00011111 00011111
IRQ0_IRQPL20
00011111 00011111 00011111 00011111
0xB0400908
IRQ0_IRQPL23
00011111 00011111 00011111 00011111
IRQ0_IRQPL22
00011111 00011111 00011111 00011111
0xB0400910
IRQ0_IRQPL25
00000000 00011111 00011111 00011111
IRQ0_IRQPL24
00011111 00011111 00011111 00011111
0xB0400918
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL26
00011111 00011111 00011111 00011111
0xB0400920
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL28
00011111 00011111 00011111 00011111
0xB0400928
IRQ0_IRQPL31
00011111 00011111 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 113
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400930
IRQ0_IRQPL33
00011111 00011111 00011111 00011111
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400938
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL34
00011111 00011111 00011111 00011111
0xB0400940
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL36
00011111 00011111 00011111 00011111
0xB0400948
IRQ0_IRQPL39
00011111 00011111 00000000 00000000
IRQ0_IRQPL38
00000000 00011111 00011111 00011111
0xB0400950
IRQ0_IRQPL41
00011111 00011111 00011111 00011111
IRQ0_IRQPL40
00000000 00000000 00000000 00011111
0xB0400958
IRQ0_IRQPL43
00011111 00011111 00011111 00011111
IRQ0_IRQPL42
00011111 00011111 00011111 00011111
0xB0400960
IRQ0_IRQPL45
00011111 00011111 00011111 00011111
IRQ0_IRQPL44
00011111 00011111 00011111 00011111
0xB0400968
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL46
00011111 00011111 00011111 00011111
0xB0400970
IRQ0_IRQPL49
00011111 00011111 00000000 00000000
IRQ0_IRQPL48
00011111 00011111 00000000 00000000
0xB0400978
IRQ0_IRQPL51
00000000 00011111 00000000 00000000
IRQ0_IRQPL50
00011111 00011111 00000000 00000000
0xB0400980
IRQ0_IRQPL53
00011111 00011111 00011111 00011111
IRQ0_IRQPL52
00011111 00011111 00011111 00011111
0xB0400988
IRQ0_IRQPL55
00011111 00011111 00011111 00011111
IRQ0_IRQPL54
00011111 00011111 00011111 00011111
0xB0400990
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400998
IRQ0_IRQPL59
00011111 00011111 00011111 00011111
IRQ0_IRQPL58
00011111 00011111 00011111 00011111
0xB04009A0 0xB0400AA8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AB0
IRQ0_NMIR
00000000 00000000 00000000 00000000
IRQ0_NMIS
00000000 00000000 00000000 00000000
0xB0400AB8
read0
00000000 00000000 00000000 00000000
IRQ0_NMISIS
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 114
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400AC0
IRQ0_IRQS1
00000000 00000000 00000000 00000000
IRQ0_IRQS0
00000000 00000000 00000000 00000000
0xB0400AC8
IRQ0_IRQS3
00000000 00000000 00000000 00000000
IRQ0_IRQS2
00000000 00000000 00000000 00000000
0xB0400AD0
IRQ0_IRQS5
00000000 00000000 00000000 00000000
IRQ0_IRQS4
00000000 00000000 00000000 00000000
0xB0400AD8
IRQ0_IRQS7
00000000 00000000 00000000 00000000
IRQ0_IRQS6
00000000 00000000 00000000 00000000
0xB0400AE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AF0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B00
IRQ0_IRQR1
00000000 00000000 00000000 00000000
IRQ0_IRQR0
00000000 00000000 00000000 00000000
0xB0400B08
IRQ0_IRQR3
00000000 00000000 00000000 00000000
IRQ0_IRQR2
00000000 00000000 00000000 00000000
0xB0400B10
IRQ0_IRQR5
00000000 00000000 00000000 00000000
IRQ0_IRQR4
00000000 00000000 00000000 00000000
0xB0400B18
IRQ0_IRQR7
00000000 00000000 00000000 00000000
IRQ0_IRQR6
00000000 00000000 00000000 00000000
0xB0400B20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B30
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B38
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B40
IRQ0_IRQSIS1
00000000 00000000 00000000 00000000
IRQ0_IRQSIS0
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 115
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400B48
IRQ0_IRQSIS3
00000000 00000000 00000000 00000000
IRQ0_IRQSIS2
00000000 00000000 00000000 00000000
0xB0400B50
IRQ0_IRQSIS5
00000000 00000000 00000000 00000000
IRQ0_IRQSIS4
00000000 00000000 00000000 00000000
0xB0400B58
IRQ0_IRQSIS7
00000000 00000000 00000000 00000000
IRQ0_IRQSIS6
00000000 00000000 00000000 00000000
0xB0400B60
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B68
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B70
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B80
IRQ0_IRQCES1
00000000 00000000 00000000 00000000
IRQ0_IRQCES0
00000000 00000000 00000000 00000000
0xB0400B88
IRQ0_IRQCES3
00000000 00000000 00000000 00000000
IRQ0_IRQCES2
00000000 00000000 00000000 00000000
0xB0400B90
IRQ0_IRQCES5
00000000 00000000 00000000 00000000
IRQ0_IRQCES4
00000000 00000000 00000000 00000000
0xB0400B98
IRQ0_IRQCES7
00000000 00000000 00000000 00000000
IRQ0_IRQCES6
00000000 00000000 00000000 00000000
0xB0400BA0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BA8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BB0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BB8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BC0
IRQ0_IRQCEC1
00000000 00000000 00000000 00000000
IRQ0_IRQCEC0
00000000 00000000 00000000 00000000
0xB0400BC8
IRQ0_IRQCEC3
00000000 00000000 00000000 00000000
IRQ0_IRQCEC2
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 116
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400BD0
IRQ0_IRQCEC5
00000000 00000000 00000000 00000000
IRQ0_IRQCEC4
00000000 00000000 00000000 00000000
0xB0400BD8
IRQ0_IRQCEC7
00000000 00000000 00000000 00000000
IRQ0_IRQCEC6
00000000 00000000 00000000 00000000
0xB0400BE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BF0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C00
IRQ0_IRQCE1
00000000 00000000 00000000 00000000
IRQ0_IRQCE0
00000000 00000000 00000000 00000000
0xB0400C08
IRQ0_IRQCE3
00000000 00000000 00000000 00000000
IRQ0_IRQCE2
00000000 00000000 00000000 00000000
0xB0400C10
IRQ0_IRQCE5
00000000 00000000 00000000 00000000
IRQ0_IRQCE4
00000000 00000000 00000000 00000000
0xB0400C18
IRQ0_IRQCE7
00000000 00000000 00000000 00000000
IRQ0_IRQCE6
00000000 00000000 00000000 00000000
0xB0400C20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C30
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C38
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C40
IRQ0_NMIHS
00000000 00000000 00000000 00000000
IRQ0_NMIHC
00000000 00000000 00000000 00000000
0xB0400C48
read0
00000000 00000000 00000000 00000000
IRQ0_IRQHC
00000000 00000000 00000000 00000000
0xB0400C50
IRQ0_IRQHS1
00000000 00000000 00000000 00000000
IRQ0_IRQHS0
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 117
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400C58
IRQ0_IRQHS3
00000000 00000000 00000000 00000000
IRQ0_IRQHS2
00000000 00000000 00000000 00000000
0xB0400C60
IRQ0_IRQHS5
00000000 00000000 00000000 00000000
IRQ0_IRQHS4
00000000 00000000 00000000 00000000
0xB0400C68
IRQ0_IRQHS7
00000000 00000000 00000000 00000000
IRQ0_IRQHS6
00000000 00000000 00000000 00000000
0xB0400C70
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C80
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C88
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C90
read0
00000000 00000000 00000000 00000000
IRQ0_IRQPLM
00000000 00000000 00000000 00100000
0xB0400C98
read0
00000000 00000000 00000000 00000000
IRQ0_CSR
00000000 00000001 00000000 00000000
0xB0400CA0
read0
00000000 00000000 00000000 00000000
IRQ0_NESTL
00000000 00000000 00000000 00000000
0xB0400CA8
IRQ0_NMIPS
00000000 00000000 00000000 00000000
IRQ0_NMIRS
00000000 00000000 00000000 00000000
0xB0400CB0
IRQ0_IRQRS1
00000000 00000000 00000000 00000000
IRQ0_IRQRS0
00000000 00000000 00000000 00000000
0xB0400CB8
IRQ0_IRQRS3
00000000 00000000 00000000 00000000
IRQ0_IRQRS2
00000000 00000000 00000000 00000000
0xB0400CC0
IRQ0_IRQRS5
00000000 00000000 00000000 00000000
IRQ0_IRQRS4
00000000 00000000 00000000 00000000
0xB0400CC8
IRQ0_IRQRS7
00000000 00000000 00000000 00000000
IRQ0_IRQRS6
00000000 00000000 00000000 00000000
0xB0400CD0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CD8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 118
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400CE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CF0
IRQ0_IRQPS1
00000000 00000000 00000000 00000000
IRQ0_IRQPS0
00000000 00000000 00000000 00000000
0xB0400CF8
IRQ0_IRQPS3
00000000 00000000 00000000 00000000
IRQ0_IRQPS2
00000000 00000000 00000000 00000000
0xB0400D00
IRQ0_IRQPS5
00000000 00000000 00000000 00000000
IRQ0_IRQPS4
00000000 00000000 00000000 00000000
0xB0400D08
IRQ0_IRQPS7
00000000 00000000 00000000 00000000
IRQ0_IRQPS6
00000000 00000000 00000000 00000000
0xB0400D10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D30
read0
00000000 00000000 00000000 00000000
IRQ0_UNLOCK
00000000 00000000 00000000 00000000
0xB0400D38
read0
00000000 00000000 00000000 00000000
IRQ0_MID
00000000 00000000 00000000 00000000
0xB0400D40
IRQ0_EAN
00000000 00000000 00000000 00000000
IRQ0_EEI
00000000 00000000 00000000 00000000
0xB0400D48
IRQ0_EEB0
00000000 00000000 00000000 00000000
IRQ0_ET
00000000 00000000 00000000 00000000
0xB0400D50
IRQ0_EEB2
00000000 00000000 00000000 00000000
IRQ0_EEB1
00000000 00000000 00000000 00000000
0xB0400D58B0407FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0408000
TPU0_LST
00000000 00000000 00000000 00000001
Document Number: DS707-00002-4v1-E
TPU0_UNLOCK
00000000 00000000 00000000 00000000
Page 119
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0408008
TPU0_TIR
00000000 00000000 00000000 00000000
TPU0_CFG
00000000 00000000 00000000 00000000
0xB0408010
TPU0_TIE
00000000 00000000 00000000 00000000
TPU0_TST
00000000 00000000 00000000 00000000
0xB0408018
read0
00000000 00000000 00000000 00000000
TPU0_MID
00000000 00000000 00000000 00000000
0xB0408020B0408028
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0408030
TPU0_TCN01
00000000 00000000 00000000 00000000
TPU0_TCN00
00000000 00000000 00000000 00000000
0xB0408038
TPU0_TCN03
00000000 00000000 00000000 00000000
TPU0_TCN02
00000000 00000000 00000000 00000000
0xB0408040
TPU0_TCN05
00000000 00000000 00000000 00000000
TPU0_TCN04
00000000 00000000 00000000 00000000
0xB0408048
TPU0_TCN07
00000000 00000000 00000000 00000000
TPU0_TCN06
00000000 00000000 00000000 00000000
0xB0408050
TPU0_TCN11
00000000 00000000 00000000 00000000
TPU0_TCN10
00000000 00000000 00000000 00000000
0xB0408058
TPU0_TCN13
00000000 00000000 00000000 00000000
TPU0_TCN12
00000000 00000000 00000000 00000000
0xB0408060
TPU0_TCN15
00000000 00000000 00000000 00000000
TPU0_TCN14
00000000 00000000 00000000 00000000
0xB0408068
TPU0_TCN17
00000000 00000000 00000000 00000000
TPU0_TCN16
00000000 00000000 00000000 00000000
0xB0408070
TPU0_TCC1
00000000 00000000 00000000 00000000
TPU0_TCC0
00000000 00000000 00000000 00000000
0xB0408078
TPU0_TCC3
00000000 00000000 00000000 00000000
TPU0_TCC2
00000000 00000000 00000000 00000000
0xB0408080
TPU0_TCC5
00000000 00000000 00000000 00000000
TPU0_TCC4
00000000 00000000 00000000 00000000
0xB0408088
TPU0_TCC7
00000000 00000000 00000000 00000000
TPU0_TCC6
00000000 00000000 00000000 00000000
0xB0408090B040FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 120
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0410000
TRCFG_TCMCFG1
00000000 00000000 00000000 00000000
TRCFG_TCMCFG0
00000011 00000000 00000001 00000000
0xB0410008
read0
00000000 00000000 00000000 00000000
TRCFG_TCMUNLOCK
00000000 00000000 00000000 00000000
0xB0410010B0410FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411000
reserved
00000000 00000000 00000000 00000000
TCFCFG_FCPROTKEY
00000000 00000000 00000000 00000000
0xB0411008
reserved
00000000 00000000 00000000 00000000
TCFCFG_FCFGR
00000000 00000000 00000000 00000001
0xB0411010
reserved
00000000 00000000 00000000 00000000
TCFCFG_FECCCTRL
00000000 00000000 00000000 00000000
0xB0411018
TCFCFG_FECCEIR
00000000 00000000 00000000 00000000
TCFCFG_FDATEIR
00000000 00000000 00000000 00000000
0xB0411020
TCFCFG_FICTRL1
00000000 00000000 00000000 00000000
TCFCFG_FICTRL0
00000000 00000000 00000000 00000000
0xB0411028
TCFCFG_FICTRL3
00000000 00000000 00000000 00000000
TCFCFG_FICTRL2
00000000 00000000 00000000 00000000
0xB0411030
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0411038
TCFCFG_FSTAT1
00000000 00000000 00000000 00000000
TCFCFG_FSTAT0
00000000 00000000 00000000 00000000
0xB0411040
TCFCFG_FSTAT3
00000000 00000000 00000000 00000000
TCFCFG_FSTAT2
00000000 00000000 00000000 00000000
0xB0411048
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0411050
TCFCFG_FECCEAR
00000000 00000000 00000000 00000000
TCFCFG_FSECIR
00000000 00000000 00000000 00000000
0xB0411058
reserved
00000000 00000000 00000000 00000000
TCFCFG_FMIDR
00000000 00000000 00000000 00000000
0xB0411060
TCFCFG_FCAMHR0
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411068
TCFCFG_FCAMHR1
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 121
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0411070
TCFCFG_FCAMHR2
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411078
TCFCFG_FCAMHR3
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411080B0411FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412000
reserved
00000000 00000000 00000000 00000000
EEFCFG_CPR
00000000 00000000 00000000 00000000
0xB0412008
EEFCFG_ECR
00000000 00000000 00000000 00000000
EEFCFG_CR
00000000 00000000 00000000 00000011
0xB0412010
EEFCFG_WSR
00000000 00000000 00000000 00000000
EEFCFG_WCR
00000000 00000000 00000000 00000000
0xB0412018
EEFCFG_EEIR
00000000 00000000 00000000 00000000
EEFCFG_DBEIR
00000000 00000000 00000000 00000000
0xB0412020
EEFCFG_ICR
00000000 00000000 00000000 00000000
EEFCFG_WMER
00000000 00000000 00000000 00000000
0xB0412028
EEFCFG_SECIR
00000000 00000000 00000000 00000000
EEFCFG_SR
00000000 00000000 00000000 00000000
0xB0412030
EEFCFG_MIR
00000000 00000000 00000000 00000000
EEFCFG_EEAR
00000000 00000000 00000000 00000000
0xB0412038
read0
00000000 00000000 00000000 00000000
EEFCFG_EMENR
00000000 00000000 00000000 00000000
0xB0412040
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412048
EEFCFG_FCAMHR
00000000 00000000 000XXXXX XXXXXXXX
EEFCFG_FCAMLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412058B0417FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0418000
BSU6_BTST
00000000 00000000 00000000 00000000
0xB0418008B0418010
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0418018
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN2
00000000 00000000 00000001 00000000
Page 122
MB9DF126
MB9DF126B
Table 5-3 Memory layout of MEMORY_CONFIG registers (Continued)
Offset
0xB0418020
0xB0418028B0418038
0xB0418040
0xB0418048B0418058
0xB0418060
0xB0418068B04FFFF8
+7
+6
+5
+4
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
+2
+1
+0
BSU6_PEN4
00000000 00000000 00000000 00000001
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN12
00000000 00000000 00000000 00000001
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN20
00000000 00000000 00000000 00000001
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 123
MB9DF126
MB9DF126B
Table 5-4 Memory layout for DEBUG_BUS registers
Offset
+3
+2
+1
0xB0500000B050DFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050E000
MCFG_DTAR
000XXX0X 000000XX 00000000 00000000
0xB050E004
MCFG_TSR
00000000 00000000 00000000 00111011
0xB050E008B050F11C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F120
SCCFG_TCFPUSRKEY0
00000000 00000000 00000000 00000000
0xB050F124
SCCFG_TCFPUSRKEY1
00000000 00000000 00000000 00000000
0xB050F128
SCCFG_TCFPUSRKEY2
00000000 00000000 00000000 00000000
0xB050F12C
SCCFG_TCFPUSRKEY3
00000000 00000000 00000000 00000000
0xB050F130
SCCFG_EEFPUSRKEY0
00000000 00000000 00000000 00000000
0xB050F134
SCCFG_EEFPUSRKEY1
00000000 00000000 00000000 00000000
0xB050F138
SCCFG_EEFPUSRKEY2
00000000 00000000 00000000 00000000
0xB050F13C
SCCFG_EEFPUSRKEY3
00000000 00000000 00000000 00000000
0xB050F140B050F16C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F170
SCCFG_CTRL
00000000 00000000 00000000 00000000
0xB050F174
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 124
MB9DF126
MB9DF126B
Table 5-4 Memory layout for DEBUG_BUS registers
Offset
+3
+2
+1
0xB050F178
SCCFG_STAT0
00000000 00000000 00000000 00000000
0xB050F17C
SCCFG_STAT1
00000001 0000000X 00000000 00111111
0xB050F180
SCCFG_STAT2
00000000 00000000 00000000 00000101
0xB050F184B050F18C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F190
SCCFG_SECKEY0
00000000 00000000 00000000 00000000
0xB050F194
SCCFG_SECKEY1
00000000 00000000 00000000 00000000
0xB050F198
SCCFG_SECKEY2
00000000 00000000 00000000 00000000
0xB050F19C
SCCFG_SECKEY3
00000000 00000000 00000000 00000000
0xB050F1A0
SCCFG_MODID
00000000 00000000 00000000 00000000
0xB050F1A4
SCCFG_UNLCK
00000000 00000000 00000000 00000000
0xB050F1A8
SCCFG_GPREG0
00000000 00000000 00000000 00000000
0xB050F1AC
SCCFG_GPREG1
00000000 00000000 00000000 00000000
0xB050F1B0B05FFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 125
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers
Offset
+3
+2
+1
+0
0xB0600000
SYSC_PROTKEYR
00000000 00000000 00000000 00000000
0xB0600004B060007C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600080
SYSC_RUNCKSRER
00000000 00001110
SYSC_RUNPDCFGR
00000000 00001111
0xB0600084
SYSC_RUNCKSELR
00100011 00000000 00000000 00000000
0xB0600088
SYSC_RUNCKER
01110001 00111111 00001101 11110001
0xB060008C
SYSC_RUNCKDIVR0
00000000 00000000 00000000 00000000
0xB0600090
SYSC_RUNCKDIVR1
00000000 00000000 00000000 00000000
0xB0600094
SYSC_RUNCKDIVR2
00000000 00000000 00000000 00000000
0xB0600098
SYSC_RUNPLLCNTR
00000000 00001101 00000001 00000000
0xB060009C
SYSC_RUNSSCGCNTR0
00000001 00001101 00000001 00000000
0xB06000A0
SYSC_RUNSSCGCNTR1
00000000 00000000 00000000 00101001
0xB06000A4
SYSC_RUNGFXCNTR0
00000001 00001101 00000000 00000000
0xB06000A8
SYSC_RUNGFXCNTR1
00000000 00000000 00000000 00101001
0xB06000AC
SYSC_RUNLVDCFGR
00000000 00001011 00001110 00001111
0xB06000B0
Document Number: DS707-00002-4v1-E
SYSC_TRGRUNCNTR
00000000 00000000
SYSC_RUNCSVCFGR
00000000 00000000
Page 126
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
0xB06000B4B06000FC
0xB0600100
+2
+1
+0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_PSSCKSRER
00000000 00001110
SYSC_PSSPDCFGR
00000000 00001111
0xB0600104
SYSC_PSSCKSELR
00100011 00000000 00000000 00000000
0xB0600108
SYSC_PSSCKER
01110001 00111110 00001101 11110001
0xB060010C
SYSC_PSSCKDIVR0
00000000 00000000 00000000 00000000
0xB0600110
SYSC_PSSCKDIVR1
00000000 00000000 00000000 00000000
0xB0600114
SYSC_PSSCKDIVR2
00000000 00000000 00000000 00000000
0xB0600118
SYSC_PSSPLLCNTR
00000000 00001101 00000001 00000000
0xB060011C
SYSC_PSSSSCGCNTR0
00000001 00001101 00000001 00000000
0xB0600120
SYSC_PSSSSCGCNTR1
00000000 00000000 00000000 00101001
0xB0600124
SYSC_PSSGFXCNTR0
00000001 00001101 00000000 00000000
0xB0600128
SYSC_PSSGFXCNTR1
00000000 00000000 00000000 00101001
0xB060012C
SYSC_PSSLVDCFGR
00000000 00001011 00001110 00001111
0xB0600130
0xB0600134B060017C
0xB0600180
0xB0600184
Document Number: DS707-00002-4v1-E
SYSC_PSSENR
00000000 00000000
SYSC_PSSCSVCFGR
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_APPCKSRER
00000000 00001110
SYSC_APPPDCFGR
00000000 00001111
SYSC_APPCKSELR
00100011 00000000 00000000 00000000
Page 127
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
+0
0xB0600188
SYSC_APPCKER
01110001 00111111 00001101 11110001
0xB060018C
SYSC_APPCKDIVR0
00000000 00000000 00000000 00000000
0xB0600190
SYSC_APPCKDIVR1
00000000 00000000 00000000 00000000
0xB0600194
SYSC_APPCKDIVR2
00000000 00000000 00000000 00000000
0xB0600198
SYSC_APPPLLCNTR
00000000 00001101 00000001 00000000
0xB060019C
SYSC_APPSSCGCNTR0
00000001 00001101 00000001 00000000
0xB06001A0
SYSC_APPSSCGCNTR1
00000000 00000000 00000000 00101001
0xB06001A4
SYSC_APPGFXCNTR0
00000001 00001101 00000000 00000000
0xB06001A8
SYSC_APPGFXCNTR1
00000000 00000000 00000000 00101001
0xB06001AC
SYSC_APPLVDCFGR
00000000 00001011 00001110 00001111
0xB06001B0
0xB06001B4B06001FC
0xB0600200
reserved
XXXXXXXX XXXXXXXX
SYSC_APPCSVCFGR
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_CKSRESTSR
00000000 00001110
SYSC_PDSTSR
00000000 00001111
0xB0600204
SYSC_CKSELSTSR
00100011 00000000 00000000 00000000
0xB0600208
SYSC_CKESTSR
01110001 00111111 00001101 11110001
0xB060020C
SYSC_CKDIVSTSR0
00000000 00000000 00000000 00000000
0xB0600210
SYSC_CKDIVSTSR1
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 128
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0600214
SYSC_CKDIVSTSR2
00000000 00000000 00000000 00000000
0xB0600218
SYSC_PLLSTSR
00000000 00001101 00000001 00000000
0xB060021C
SYSC_SSCGSTSR0
00000001 00001101 00000001 00000000
0xB0600220
SYSC_SSCGSTSR1
00000000 00000000 00000000 00101001
0xB0600224
SYSC_GFXSTSR0
00000001 00001101 00000000 00000000
0xB0600228
SYSC_GFXSTSR1
00000000 00000000 00000000 00101001
0xB060022C
SYSC_LVDCFGSTSR
00000000 00101011 00101110 00101111
0xB0600230
reserved
XXXXXXXX XXXXXXXX
SYSC_CSVCFGSTSR
00000000 00000000
0xB0600234B060027C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600280
SYSC_SYSIDR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600284
SYSC_SYSSTSR
00000000 00000000 00000100 00000000
0xB0600288
SYSC_SYSINTER
00000000 00000000 00000000 00000000
0xB060028C
SYSC_SYSICLR
00000000 00000000 00000000 00000000
0xB0600290
SYSC_SYSERRR
00000000 00000000 00000000 00000000
0xB0600294
SYSC_SYSERRICLR
00000000 00000000 00000000 00000000
0xB0600298B06002FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600300
SYSC_CSVMOCFGR
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 129
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0600304
SYSC_CSVSOCFGR
00000000 00000000 00000000 00000000
0xB0600308
SYSC_CSVMPCFGR
00000000 00000000 00000000 00000000
0xB060030C
SYSC_CSVSPCFGR
00000000 00000000 00000000 00000000
0xB0600310
SYSC_CSVGPCFGR
00000000 00000000 00000000 00000000
0xB0600314
SYSC_CSVTESTR
00000000 00000000 00000000 00000000
0xB0600318B060037C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600380
SYSC_RSTCNTR
00000000 00000000 00000000 00000000
0xB0600384
SYSC_RSTCAUSEUR
00011110 00000000 00000000 00000001
0xB0600388
SYSC_RSTCAUSEBT
X0011110 00000000 00000000 00000001
0xB060038CB06003FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600400
SYSC_SRCSCTTRG
00000000 00000000 00000000 00000000
0xB0600404
SYSC_SRCSCTCNTR
00000000 00000000 00000000 00000000
0xB0600408
SYSC_SRCSCTCPR
00000000 00000110 00000000 00000001
0xB060040C
SYSC_SRCSCTSTATR
00000000 00000000 00000000 00000000
0xB0600410
SYSC_SRCSCTINTER
00000000 00000000 00000000 00000000
0xB0600414
SYSC_SRCSCTICLR
00000000 00000000 00000000 00000000
0xB0600418B060047C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 130
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0600480
SYSC_RCSCTTRG
00000000 00000000 00000000 00000000
0xB0600484
SYSC_RCSCTCNTR
00000000 00000000 00000000 00000000
0xB0600488
SYSC_RCSCTCPR
00000000 00000110 00000000 00011110
0xB060048C
SYSC_RCSCTSTATR
00000000 00000000 00000000 00000000
0xB0600490
SYSC_RCSCTINTER
00000000 00000000 00000000 00000000
0xB0600494
SYSC_RCSCTICLR
00000000 00000000 00000000 00000000
0xB0600498B06004FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600500
SYSC_MAINSCTTRG
00000000 00000000 00000000 00000000
0xB0600504
SYSC_MAINSCTCNTR
00000000 00000000 00000000 00000000
0xB0600508
SYSC_MAINSCTCPR
00000000 00000110 00010000 00000000
0xB060050C
SYSC_MAINSCTSTATR
00000000 00000000 00000000 00000000
0xB0600510
SYSC_MAINSCTINTER
00000000 00000000 00000000 00000000
0xB0600514
SYSC_MAINSCTICLR
00000000 00000000 00000000 00000000
0xB0600518B060057C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600580
SYSC_SUBSCTTRG
00000000 00000000 00000000 00000000
0xB0600584
SYSC_SUBSCTCNTR
00000000 00000000 00000000 00000000
0xB0600588
SYSC_SUBSCTCPR
00000000 00000110 00000100 00000000
Document Number: DS707-00002-4v1-E
+0
Page 131
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB060058C
SYSC_SUBSCTSTATR
00000000 00000000 00000000 00000000
0xB0600590
SYSC_SUBSCTINTER
00000000 00000000 00000000 00000000
0xB0600594
SYSC_SUBSCTICLR
00000000 00000000 00000000 00000000
0xB0600598B06005FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600600
SYSC_CKOTCFGR
00000000 00000000 00000000 00000111
0xB0600604B060067C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600680
SYSC_SPCCFGR
00000000 000000X0 00000000 00000000
0xB0600684
SYSC_RCCFGR
00000000 00000000 00000001 11111111
0xB0600688
SYSC_TESTR0
00000000 00000000 00000000 00000000
0xB060068C
SYSC_TESTR1
00000000 00000000 00000000 00000000
0xB0600690
SYSC_TESTR2
00000000 00000000 00000000 00000000
0xB0600694B06006FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600700
SYSC_JTAGDETECT
00000000 00000000 00000000 00000000
0xB0600704
SYSC_JTAGCNFG
00000000 00000000 00000000 00000001
0xB0600708
SYSC_JTAGWAKEUP
00000000 00000000 00000000 00000001
0xB060070CB0607FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0608000
WDG_PROT
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 132
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0608004
reserved
00000000 00000000 00000000 00000000
0xB0608008
WDG_CNT
00000000 00000000 00000000 00000000
0xB060800C
WDG_RSTCAUSE
00000000 00000000 00000000 000XXXXX
0xB0608010
WDG_TRG0
00000000 00000000 00000000 00000000
0xB0608014
reserved
00000000 00000000 00000000 00000000
0xB0608018
WDG_TRG1
00000000 00000000 00000000 00000000
0xB060801C
reserved
00000000 00000000 00000000 00000000
0xB0608020
WDG_INT
00000000 00000000 00000000 00000000
0xB0608024
WDG_INTCLR
00000000 00000000 00000000 00000000
0xB0608028
reserved
00000000 00000000 00000000 00000000
0xB060802C
WDG_TRG0CFG
00000000 00000000 00000000 00000000
0xB0608030
WDG_TRG1CFG
00000000 00000000 00000000 00000000
0xB0608034
WDG_RUNLL
00000000 00000000 00000000 00000000
0xB0608038
WDG_RUNUL
00000001 00000000 00000000 00000000
0xB060803C
WDG_PSSLL
00000000 00000000 00000000 00000000
0xB0608040
WDG_PSSUL
10000000 00000000 00000000 00000000
0xB0608044
WDG_RSTDLY
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 133
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0608048
WDG_CFG
00000000 00000000 00000000 00000011
0xB060804CB060FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0610000
RRCFG_UNLOCKR
00000000 00000000 00000000 00000000
0xB0610004
RRCFG_CSR
00001111 00000000 00000010 00000000
0xB0610008
RRCFG_EAN
00000000 00000000 00000000 00000000
0xB061000C
RRCFG_ERRMSKR0
00000000 00000000 00000000 00000000
0xB0610010
RRCFG_ERRMSKR1
00000000 00000000 00000000 00000000
0xB0610014
RRCFG_ECCEN
00000000 00000000 00000000 00000001
0xB0610018B0617FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0618000
RTC_WTCR
00000000 00000000 00000000 00000000
0xB0618004
RTC_WTSR
00000000 00000000 00000000 00000000
0xB0618008
RTC_WINS
00000000 00000000 00000000 00000000
0xB061800C
RTC_WINE
00000000 00000000 00000000 00000000
0xB0618010
RTC_WINC
00000000 00000000 00000000 00000000
0xB0618014
RTC_WTBR
00000000 00000000 00000000 00000000
0xB0618018
RTC_WRT
00000000 00000000 00000000 00000000
0xB061801C
RTC_CNTCAL
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 134
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0618020
RTC_CNTPCAL
00000000 00000000 00000000 00000000
0xB0618024
RTC_DURMW
00000000 00000000 00000000 00000000
0xB0618028
RTC_CALTRG
00000000 00000000 00000000 00000000
0xB061802C
RTC_DEBUG
00000000 00000000 00000000 00000000
0xB0618030B061FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0620000
EIC0_ENIR
00000000 00000000 00000000 00000000
0xB0620004
EIC0_ENISR
00000000 00000000 00000000 00000000
0xB0620008
EIC0_ENICR
00000000 00000000 00000000 00000000
0xB062000C
EIC0_EIRR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0620010
EIC0_EIRCR
00000000 00000000 00000000 00000000
0xB0620014
EIC0_NFER
00000000 00000000 00000000 00000000
0xB0620018
EIC0_NFESR
00000000 00000000 00000000 00000000
0xB062001C
EIC0_NFECR
00000000 00000000 00000000 00000000
0xB0620020
EIC0_ELVR0
00000000 00000000 00000000 00000000
0xB0620024
EIC0_ELVR1
00000000 00000000 00000000 00000000
0xB0620028
EIC0_ELVR2
00000000 00000000 00000000 00000000
0xB062002C
EIC0_ELVR3
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 135
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB0620030
EIC0_NMIR
00000000 00000000 00000000 00000000
0xB0620034
EIC0_DRER
00000000 00000000 00000000 00000000
0xB0620038
EIC0_DRESR
00000000 00000000 00000000 00000000
0xB062003C
EIC0_DRECR
00000000 00000000 00000000 00000000
0xB0620040
EIC0_DRFR
00000000 00000000 00000000 00000000
0xB0620044B0627FFC
reserved
00000000 00000000 00000000 0000000X
0xB0628000
EICU0_CNFGR
00000000 00000000 00000000 00000000
0xB0628004
EICU0_IRENR
00000000 00000000 00000000 00000000
0xB0628008
EICU0_SPLR0
00000000 00000000 00000000 00000000
0xB062800C
EICU0_SPLR1
00000000 00000000 00000000 00000000
0xB0628010
EICU0_SPLR2
00000000 00000000 00000000 00000000
0xB0628014
EICU0_SPLR3
00000000 00000000 00000000 00000000
0xB0628018
EICU0_SPLR4
00000000 00000000 00000000 00000000
0xB062801C
EICU0_SPLR5
00000000 00000000 00000000 00000000
0xB0628020
EICU0_SPLR6
00000000 00000000 00000000 00000000
0xB0628024
EICU0_SPLR7
00000000 00000000 00000000 00000000
0xB0628028B06F8FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 136
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
+0
0xB06F9000
read0
00000000 00000000
RICFG7_EIC0INT00
00000000 00000000
0xB06F9004
read0
00000000 00000000
RICFG7_EIC0INT01
00000000 00000000
0xB06F9008
read0
00000000 00000000
RICFG7_EIC0INT02
00000000 00000000
0xB06F900C
read0
00000000 00000000
RICFG7_EIC0INT03
00000000 00000000
0xB06F9010
read0
00000000 00000000
RICFG7_EIC0INT04
00000000 00000000
0xB06F9014
read0
00000000 00000000
RICFG7_EIC0INT05
00000000 00000000
0xB06F9018
read0
00000000 00000000
RICFG7_EIC0INT06
00000000 00000000
0xB06F901C
read0
00000000 00000000
RICFG7_EIC0INT07
00000000 00000000
0xB06F9020
read0
00000000 00000000
RICFG7_EIC0INT08
00000000 00000000
0xB06F9024
read0
00000000 00000000
RICFG7_EIC0INT09
00000000 00000000
0xB06F9028
read0
00000000 00000000
RICFG7_EIC0INT10
00000000 00000000
0xB06F902C
read0
00000000 00000000
RICFG7_EIC0INT11
00000000 00000000
0xB06F9030
read0
00000000 00000000
RICFG7_EIC0INT12
00000000 00000000
0xB06F9034
read0
00000000 00000000
RICFG7_EIC0INT13
00000000 00000000
0xB06F9038
read0
00000000 00000000
RICFG7_EIC0INT14
00000000 00000000
0xB06F903C
read0
00000000 00000000
RICFG7_EIC0INT15
00000000 00000000
0xB06F9040
read0
00000000 00000000
RICFG7_EIC0INT16
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 137
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
+0
0xB06F9044
read0
00000000 00000000
RICFG7_EIC0INT17
00000000 00000000
0xB06F9048
read0
00000000 00000000
RICFG7_EIC0INT18
00000000 00000000
0xB06F904C
read0
00000000 00000000
RICFG7_EIC0INT19
00000000 00000000
0xB06F9050
read0
00000000 00000000
RICFG7_EIC0INT20
00000000 00000000
0xB06F9054
read0
00000000 00000000
RICFG7_EIC0INT21
00000000 00000000
0xB06F9058
read0
00000000 00000000
RICFG7_EIC0INT22
00000000 00000000
0xB06F905C
read0
00000000 00000000
RICFG7_EIC0INT23
00000000 00000000
0xB06F9060
read0
00000000 00000000
RICFG7_EIC0INT24
00000000 00000000
0xB06F9064
read0
00000000 00000000
RICFG7_EIC0INT25
00000000 00000000
0xB06F9068
read0
00000000 00000000
RICFG7_EIC0INT26
00000000 00000000
0xB06F906C
read0
00000000 00000000
RICFG7_EIC0INT27
00000000 00000000
0xB06F9070
read0
00000000 00000000
RICFG7_EIC0INT28
00000000 00000000
0xB06F9074
read0
00000000 00000000
RICFG7_EIC0INT29
00000000 00000000
0xB06F9078
read0
00000000 00000000
RICFG7_EIC0INT30
00000000 00000000
0xB06F907C
read0
00000000 00000000
RICFG7_EIC0INT31
00000000 00000000
0xB06F9080
read0
00000000 00000000
RICFG7_EIC0NMI
00000000 00000000
0xB06F9084B06FFC00
Document Number: DS707-00002-4v1-E
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Page 138
MB9DF126
MB9DF126B
Table 5-5 Memory layout of MCU_CONFIG registers (Continued)
Offset
+3
+2
+1
0xB06FFC04
BSU7_BTST
00000000 00000000 00000000 00000000
0xB06FFC08B06FFC18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC1C
BSU7_PEN3
00000000 00000000 00000000 00000000
0xB06FFC20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC24
BSU7_PEN5
00000000 00000000 00000000 00000000
0xB06FFC28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC2C
BSU7_PEN7
00000000 00000000 00000000 00000000
0xB06FFC30
BSU7_PEN8
00000000 00000000 00000000 00000000
0xB06FFC34B06FFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 139
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers
Offset
+1
+0
0xB0700000
ADC0_ER32
00000000 00000000
0xB0700002
ADC0_ER10
00000000 00000000
0xB0700004
ADC0_CS1
00000000
ADC0_CS0
00000000
0xB0700006
ADC0_CS3
00000000
ADC0_CS2
00000000
0xB0700008
ADC0_CSS1
00000000
reserved
XXXXXXXX
0xB070000A
ADC0_CSC1
00000000
reserved
XXXXXXXX
0xB070000C
ADC0_CSS3
00000000
reserved
XXXXXXXX
0xB070000E
ADC0_CSC3
00000000
reserved
XXXXXXXX
0xB0700010
ADC0_CR
000000XX XXXXXXXX
0xB0700012
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700014
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700016
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700018
ADC0_CD0
000000XX XXXXXXXX
0xB070001A
ADC0_CD1
000000XX XXXXXXXX
0xB070001C
ADC0_CD2
000000XX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 140
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB070001E
ADC0_CD3
000000XX XXXXXXXX
0xB0700020
ADC0_CD4
000000XX XXXXXXXX
0xB0700022
ADC0_CD5
000000XX XXXXXXXX
0xB0700024
ADC0_CD6
000000XX XXXXXXXX
0xB0700026
ADC0_CD7
000000XX XXXXXXXX
0xB0700028
ADC0_CD8
000000XX XXXXXXXX
0xB070002A
ADC0_CD9
000000XX XXXXXXXX
0xB070002C
ADC0_CD10
000000XX XXXXXXXX
0xB070002E
ADC0_CD11
000000XX XXXXXXXX
0xB0700030
ADC0_CD12
000000XX XXXXXXXX
0xB0700032
ADC0_CD13
000000XX XXXXXXXX
0xB0700034
ADC0_CD14
000000XX XXXXXXXX
0xB0700036
ADC0_CD15
000000XX XXXXXXXX
0xB0700038
ADC0_CD16
000000XX XXXXXXXX
0xB070003A
ADC0_CD17
000000XX XXXXXXXX
0xB070003C
ADC0_CD18
000000XX XXXXXXXX
0xB070003E
ADC0_CD19
000000XX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 141
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0700040
ADC0_CD20
000000XX XXXXXXXX
0xB0700042
ADC0_CD21
000000XX XXXXXXXX
0xB0700044
ADC0_CD22
000000XX XXXXXXXX
0xB0700046
ADC0_CD23
000000XX XXXXXXXX
0xB0700048
ADC0_CD24
000000XX XXXXXXXX
0xB070004A
ADC0_CD25
000000XX XXXXXXXX
0xB070004C
ADC0_CD26
000000XX XXXXXXXX
0xB070004E
ADC0_CD27
000000XX XXXXXXXX
0xB0700050
ADC0_CD28
000000XX XXXXXXXX
0xB0700052
ADC0_CD29
000000XX XXXXXXXX
0xB0700054
ADC0_CD30
000000XX XXXXXXXX
0xB0700056
ADC0_CD31
000000XX XXXXXXXX
0xB0700058
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB070005A
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB070005C
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB070005E
0xB0700060
Document Number: DS707-00002-4v1-E
ADC0_CT
00010000 00101100
ADC0_ECH
00000000
ADC0_SCH
00000000
Page 142
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0700062
reserved
XXXXXXXX
ADC0_MAR
00000000
0xB0700064
reserved
XXXXXXXX
ADC0_MACR
00000000
0xB0700066
reserved
XXXXXXXX
ADC0_MASR
00000000
0xB0700068
ADC0_RCOH0
11111111
ADC0_RCOL0
00000000
0xB070006A
ADC0_RCOH1
11111111
ADC0_RCOL1
00000000
0xB070006C
ADC0_RCOH2
11111111
ADC0_RCOL2
00000000
0xB070006E
ADC0_RCOH3
11111111
ADC0_RCOL3
00000000
0xB0700070
ADC0_CC1
00000000
ADC0_CC0
00000000
0xB0700072
ADC0_CC3
00000000
ADC0_CC2
00000000
0xB0700074
ADC0_CC5
00000000
ADC0_CC4
00000000
0xB0700076
ADC0_CC7
00000000
ADC0_CC6
00000000
0xB0700078
ADC0_CC9
00000000
ADC0_CC8
00000000
0xB070007A
ADC0_CC11
00000000
ADC0_CC10
00000000
0xB070007C
ADC0_CC13
00000000
ADC0_CC12
00000000
0xB070007E
ADC0_CC15
00000000
ADC0_CC14
00000000
0xB0700080
ADC0_RCOIRS32
00000000 00000000
0xB0700082
ADC0_RCOIRS10
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 143
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0700084
ADC0_RCOOF32
00000000 00000000
0xB0700086
ADC0_RCOOF10
00000000 00000000
0xB0700088
ADC0_RCOINT32
00000000 00000000
0xB070008A
ADC0_RCOINT10
00000000 00000000
0xB070008C
ADC0_RCOINTC32
00000000 00000000
0xB070008E
ADC0_RCOINTC10
00000000 00000000
0xB0700090
ADC0_PCTNRL0
00000000
ADC0_PCTPRL0
00000000
0xB0700092
ADC0_PCTNCT0
00000000
ADC0_PCTPCT0
00000000
0xB0700094
ADC0_PCTNRL1
00000000
ADC0_PCTPRL1
00000000
0xB0700096
ADC0_PCTNCT1
00000000
ADC0_PCTPCT1
00000000
0xB0700098
ADC0_PCTNRL2
00000000
ADC0_PCTPRL2
00000000
0xB070009A
ADC0_PCTNCT2
00000000
ADC0_PCTPCT2
00000000
0xB070009C
ADC0_PCTNRL3
00000000
ADC0_PCTPRL3
00000000
0xB070009E
ADC0_PCTNCT3
00000000
ADC0_PCTPCT3
00000000
0xB07000A0
ADC0_PCTNRL4
00000000
ADC0_PCTPRL4
00000000
0xB07000A2
ADC0_PCTNCT4
00000000
ADC0_PCTPCT4
00000000
0xB07000A4
ADC0_PCTNRL5
00000000
ADC0_PCTPRL5
00000000
Document Number: DS707-00002-4v1-E
Page 144
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07000A6
ADC0_PCTNCT5
00000000
ADC0_PCTPCT5
00000000
0xB07000A8
ADC0_PCTNRL6
00000000
ADC0_PCTPRL6
00000000
0xB07000AA
ADC0_PCTNCT6
00000000
ADC0_PCTPCT6
00000000
0xB07000AC
ADC0_PCTNRL7
00000000
ADC0_PCTPRL7
00000000
0xB07000AE
ADC0_PCTNCT7
00000000
ADC0_PCTPCT7
00000000
0xB07000B0
ADC0_PCTNRL8
00000000
ADC0_PCTPRL8
00000000
0xB07000B2
ADC0_PCTNCT8
00000000
ADC0_PCTPCT8
00000000
0xB07000B4
ADC0_PCTNRL9
00000000
ADC0_PCTPRL9
00000000
0xB07000B6
ADC0_PCTNCT9
00000000
ADC0_PCTPCT9
00000000
0xB07000B8
ADC0_PCTNRL10
00000000
ADC0_PCTPRL10
00000000
0xB07000BA
ADC0_PCTNCT10
00000000
ADC0_PCTPCT10
00000000
0xB07000BC
ADC0_PCTNRL11
00000000
ADC0_PCTPRL11
00000000
0xB07000BE
ADC0_PCTNCT11
00000000
ADC0_PCTPCT11
00000000
0xB07000C0
ADC0_PCTNRL12
00000000
ADC0_PCTPRL12
00000000
0xB07000C2
ADC0_PCTNCT12
00000000
ADC0_PCTPCT12
00000000
0xB07000C4
ADC0_PCTNRL13
00000000
ADC0_PCTPRL13
00000000
0xB07000C6
ADC0_PCTNCT13
00000000
ADC0_PCTPCT13
00000000
Document Number: DS707-00002-4v1-E
Page 145
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07000C8
ADC0_PCTNRL14
00000000
ADC0_PCTPRL14
00000000
0xB07000CA
ADC0_PCTNCT14
00000000
ADC0_PCTPCT14
00000000
0xB07000CC
ADC0_PCTNRL15
00000000
ADC0_PCTPRL15
00000000
0xB07000CE
ADC0_PCTNCT15
00000000
ADC0_PCTPCT15
00000000
0xB07000D0
ADC0_PCTNRL16
00000000
ADC0_PCTPRL16
00000000
0xB07000D2
ADC0_PCTNCT16
00000000
ADC0_PCTPCT16
00000000
0xB07000D4
ADC0_PCTNRL17
00000000
ADC0_PCTPRL17
00000000
0xB07000D6
ADC0_PCTNCT17
00000000
ADC0_PCTPCT17
00000000
0xB07000D8
ADC0_PCTNRL18
00000000
ADC0_PCTPRL18
00000000
0xB07000DA
ADC0_PCTNCT18
00000000
ADC0_PCTPCT18
00000000
0xB07000DC
ADC0_PCTNRL19
00000000
ADC0_PCTPRL19
00000000
0xB07000DE
ADC0_PCTNCT19
00000000
ADC0_PCTPCT19
00000000
0xB07000E0
ADC0_PCTNRL20
00000000
ADC0_PCTPRL20
00000000
0xB07000E2
ADC0_PCTNCT20
00000000
ADC0_PCTPCT20
00000000
0xB07000E4
ADC0_PCTNRL21
00000000
ADC0_PCTPRL21
00000000
0xB07000E6
ADC0_PCTNCT21
00000000
ADC0_PCTPCT21
00000000
0xB07000E8
ADC0_PCTNRL22
00000000
ADC0_PCTPRL22
00000000
Document Number: DS707-00002-4v1-E
Page 146
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07000EA
ADC0_PCTNCT22
00000000
ADC0_PCTPCT22
00000000
0xB07000EC
ADC0_PCTNRL23
00000000
ADC0_PCTPRL23
00000000
0xB07000EE
ADC0_PCTNCT23
00000000
ADC0_PCTPCT23
00000000
0xB07000F0
ADC0_PCTNRL24
00000000
ADC0_PCTPRL24
00000000
0xB07000F2
ADC0_PCTNCT24
00000000
ADC0_PCTPCT24
00000000
0xB07000F4
ADC0_PCTNRL25
00000000
ADC0_PCTPRL25
00000000
0xB07000F6
ADC0_PCTNCT25
00000000
ADC0_PCTPCT25
00000000
0xB07000F8
ADC0_PCTNRL26
00000000
ADC0_PCTPRL26
00000000
0xB07000FA
ADC0_PCTNCT26
00000000
ADC0_PCTPCT26
00000000
0xB07000FC
ADC0_PCTNRL27
00000000
ADC0_PCTPRL27
00000000
0xB07000FE
ADC0_PCTNCT27
00000000
ADC0_PCTPCT27
00000000
0xB0700100
ADC0_PCTNRL28
00000000
ADC0_PCTPRL28
00000000
0xB0700102
ADC0_PCTNCT28
00000000
ADC0_PCTPCT28
00000000
0xB0700104
ADC0_PCTNRL29
00000000
ADC0_PCTPRL29
00000000
0xB0700106
ADC0_PCTNCT29
00000000
ADC0_PCTPCT29
00000000
0xB0700108
ADC0_PCTNRL30
00000000
ADC0_PCTPRL30
00000000
0xB070010A
ADC0_PCTNCT30
00000000
ADC0_PCTPCT30
00000000
Document Number: DS707-00002-4v1-E
Page 147
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB070010C
ADC0_PCTNRL31
00000000
ADC0_PCTPRL31
00000000
0xB070010E
ADC0_PCTNCT31
00000000
ADC0_PCTPCT31
00000000
0xB0700110
ADC0_PCZF10
00000000 00000000
0xB0700112
ADC0_PCZF32
00000000 00000000
0xB0700114
ADC0_PCZFC10
00000000 00000000
0xB0700116
ADC0_PCZFC32
00000000 00000000
0xB0700118
ADC0_PCIE10
00000000 00000000
0xB070011A
ADC0_PCIE32
00000000 00000000
0xB070011C
ADC0_PCIES10
00000000 00000000
0xB070011E
ADC0_PCIES32
00000000 00000000
0xB0700120
ADC0_PCIEC10
00000000 00000000
0xB0700122
ADC0_PCIEC32
00000000 00000000
0xB0700124B0707FFE
reserved
XXXXXXXX XXXXXXXX
0xB0708000
FRT0_TCDT
00000000 00000000
0xB0708002
FRT0_CPCLRB
11111111 11111111
0xB0708004
FRT0_CPCLR
11111111 11111111
0xB0708006
FRT0_TCCS
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 148
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0708008
FRT0_TSTPTCLK
01000000 00000000
0xB070800A
FRT0_ETCCS
00000000 00000000
0xB070800C
FRT0_CIMSZIMS
00000000 00000000
0xB070800E
reserved
XXXXXXXX
FRT0_DMACFG
00000000
0xB0708010B07083FE
reserved
XXXXXXXX XXXXXXXX
0xB0708400
FRT1_TCDT
00000000 00000000
0xB0708402
FRT1_CPCLRB
11111111 11111111
0xB0708404
FRT1_CPCLR
11111111 11111111
0xB0708406
FRT1_TCCS
00000000 00000000
0xB0708408
FRT1_TSTPTCLK
01000000 00000000
0xB070840A
FRT1_ETCCS
00000000 00000000
0xB070840C
FRT1_CIMSZIMS
00000000 00000000
0xB070840E
reserved
XXXXXXXX
FRT1_DMACFG
00000000
0xB0708410B07087FE
reserved
XXXXXXXX XXXXXXXX
0xB0708800
FRT2_TCDT
00000000 00000000
0xB0708802
FRT2_CPCLRB
11111111 11111111
0xB0708804
FRT2_CPCLR
11111111 11111111
Document Number: DS707-00002-4v1-E
Page 149
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0708806
FRT2_TCCS
00000000 00000000
0xB0708808
FRT2_TSTPTCLK
01000000 00000000
0xB070880A
FRT2_ETCCS
00000000 00000000
0xB070880C
FRT2_CIMSZIMS
00000000 00000000
0xB070880E
reserved
XXXXXXXX
FRT2_DMACFG
00000000
0xB0708810B0708BFE
reserved
XXXXXXXX XXXXXXXX
0xB0708C00
FRT3_TCDT
00000000 00000000
0xB0708C02
FRT3_CPCLRB
11111111 11111111
0xB0708C04
FRT3_CPCLR
11111111 11111111
0xB0708C06
FRT3_TCCS
00000000 00000000
0xB0708C08
FRT3_TSTPTCLK
01000000 00000000
0xB0708C0A
FRT3_ETCCS
00000000 00000000
0xB0708C0C
FRT3_CIMSZIMS
00000000 00000000
0xB0708C0E
reserved
XXXXXXXX
FRT3_DMACFG
00000000
0xB0708C10B07107FE
reserved
XXXXXXXX XXXXXXXX
0xB0710800
ICU2_IPC0
00000000 00000000
0xB0710802
ICU2_IPC1
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 150
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0710804
ICU2_ICC01
00000000 00000000
0xB0710806
ICU2_ICEICS01
00000000 00000000
0xB0710808
ICU2_DEBUG01
00000000
ICU2_DMACFG01
00000000
0xB071080AB0710BFE
reserved
XXXXXXXX XXXXXXXX
0xB0710C00
ICU3_IPC0
00000000 00000000
0xB0710C02
ICU3_IPC1
00000000 00000000
0xB0710C04
ICU3_ICC01
00000000 00000000
0xB0710C06
ICU3_ICEICS01
00000000 00000000
0xB0710C08
ICU3_DEBUG01
00000000
ICU3_DMACFG01
00000000
0xB0710C0AB0717FFE
reserved
XXXXXXXX XXXXXXXX
0xB0718000
OCU0_OCCP0
00000000 00000000
0xB0718002
OCU0_OCCP1
00000000 00000000
0xB0718004
OCU0_OCCPB0
00000000 00000000
0xB0718006
OCU0_OCCPB1
00000000 00000000
0xB0718008
OCU0_OCCPBD0
00000000 00000000
0xB071800A
OCU0_OCCPBD1
00000000 00000000
0xB071800C
OCU0_OCS01
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 151
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB071800E
OCU0_OCSC01
00000000 00000000
0xB0718010
OCU0_OCSS01
00000000 00000000
0xB0718012
reserved
XXXXXXXX
OCU0_OSR01
00000000
0xB0718014
reserved
XXXXXXXX
OCU0_OSCR01
00000000
0xB0718016
OCU0_EOCS01
00000000 00000000
0xB0718018
OCU0_EOCSSH01
00000000
reserved
XXXXXXXX
0xB071801A
OCU0_EOCSCH01
00000000
reserved
XXXXXXXX
0xB071801C
OCU0_DEBUG01
00000000
OCU0_DMACFG01
00000000
0xB071801E
OCU0_OCMCR01
00000000
reserved
XXXXXXXX
0xB0718020B07183FE
reserved
XXXXXXXX XXXXXXXX
0xB0718400
OCU1_OCCP0
00000000 00000000
0xB0718402
OCU1_OCCP1
00000000 00000000
0xB0718404
OCU1_OCCPB0
00000000 00000000
0xB0718406
OCU1_OCCPB1
00000000 00000000
0xB0718408
OCU1_OCCPBD0
00000000 00000000
0xB071840A
OCU1_OCCPBD1
00000000 00000000
0xB071840C
OCU1_OCS01
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 152
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB071840E
OCU1_OCSC01
00000000 00000000
0xB0718410
OCU1_OCSS01
00000000 00000000
0xB0718412
reserved
XXXXXXXX
OCU1_OSR01
00000000
0xB0718414
reserved
XXXXXXXX
OCU1_OSCR01
00000000
0xB0718416
OCU1_EOCS01
00000000 00000000
0xB0718418
OCU1_EOCSSH01
00000000
reserved
XXXXXXXX
0xB071841A
OCU1_EOCSCH01
00000000
reserved
XXXXXXXX
0xB071841C
OCU1_DEBUG01
00000000
OCU1_DMACFG01
00000000
0xB071841E
OCU1_OCMCR01
00000000
reserved
XXXXXXXX
0xB0718420B071FFFE
reserved
XXXXXXXX XXXXXXXX
0xB0720000
I2C0_IBCSR
00000000 00000000
0xB0720002
I2C0_ITBA
00000000 00000000
0xB0720004
I2C0_ITMK
00XXXX11 11111111
0xB0720006
I2C0_ISBMA
01111111 00000000
0xB0720008
reserved
XXXXXXXX
I2C0_IODAR
00000000
0xB072000A
reserved
XXXXXXXX
I2C0_ICCR
00111111
0xB072000C
I2C0_ICDIDAR
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 153
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB072000E
I2C0_IEICR
00000000 00000000
0xB0720010
I2C0_DDMACFG
00000000 00000000
0xB0720012
0xB0720014B0727FFE
reserved
XXXXXXXX
I2C0_IEIER
00000000
reserved
XXXXXXXX XXXXXXXX
0xB0728000
USART0_SCR
00000000
USART0_SMR
00000000
0xB0728002
USART0_SCSR
00000000
USART0_SMSR
00000000
0xB0728004
USART0_SCCR
00000000
reserved
XXXXXXXX
0xB0728006
USART0_SSR
00001000
USART0_TDR
00000000
0xB0728008
USART0_SSSR
00000000
USART0_RDR
00000000
0xB072800A
USART0_SSCR
00000000
reserved
XXXXXXXX
0xB072800C
USART0_ESCR
00000100
USART0_ECCR
000000XX
0xB072800E
USART0_ESCSR
00000000
USART0_ECCSR
00000000
0xB0728010
USART0_ESCCR
00000000
USART0_ECCCR
00000000
0xB0728012
USART0_EIER
00000000
USART0_ESIR
000010X0
0xB0728014
USART0_EIESR
00000000
USART0_ESISR
00000000
0xB0728016
USART0_EIECR
00000000
USART0_ESICR
00000000
0xB0728018
USART0_EFERH
00000000
USART0_EFERL
00000000
Document Number: DS707-00002-4v1-E
Page 154
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB072801A
USART0_TFCR
00000000
USART0_RFCR
00000000
0xB072801C
USART0_TFCSR
00000000
USART0_RFCSR
00000000
0xB072801E
USART0_TFCCR
00000000
USART0_RFCCR
00000000
0xB0728020
USART0_TFSR
00000000
USART0_RFSR
00000000
0xB0728022
USART0_ESR
00000000
USART0_CSCR
00000000
0xB0728024
reserved
XXXXXXXX
USART0_CSCSR
00000000
0xB0728026
USART0_ESCLR
00000000
USART0_CSCCR
00000000
0xB0728028
USART0_BGRLM
00000000
USART0_BGRLL
00000000
0xB072802A
reserved
XXXXXXXX
USART0_BGRLH
00000000
0xB072802C
USART0_BGRM
00000000
USART0_BGRL
00000000
0xB072802E
reserved
XXXXXXXX
USART0_BGRH
00000000
0xB0728030
USART0_SRXDR
00000000
USART0_STXDR
00000000
0xB0728032
USART0_SRXDSR
00000000
USART0_STXDSR
00000000
0xB0728034
USART0_SRXDCR
00000000
USART0_STXDCR
00000000
0xB0728036
read0
00000000
read0
00000000
0xB0728038
reserved
XXXXXXXX
read0
00000000
0xB072803A
reserved
XXXXXXXX
USART0_FIDR
00000000
Document Number: DS707-00002-4v1-E
Page 155
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB072803C
reserved
XXXXXXXX
USART0_DEBUG
00000000
0xB072803EB072FFFE
reserved
XXXXXXXX XXXXXXXX
0xB0730000
reserved
XXXXXXXX
SMC0_PWC
00000000
0xB0730002
reserved
XXXXXXXX
SMC0_PWCS
00000000
0xB0730004
reserved
XXXXXXXX
SMC0_PWCC
00000000
0xB0730006
SMC0_PWC1
000000XX XXXXXXXX
0xB0730008
SMC0_PWC2
000000XX XXXXXXXX
0xB073000A
SMC0_PWS
00000000 00000000
0xB073000C
SMC0_PWSS
00000000 XXXXXXXX
0xB073000E
reserved
XXXXXXXX
SMC0_PTRGDL
00000000
0xB0730010
reserved
XXXXXXXX
SMC0_DEBUG
00000000
0xB0730012B07303FE
reserved
XXXXXXXX XXXXXXXX
0xB0730400
reserved
XXXXXXXX
SMC1_PWC
00000000
0xB0730402
reserved
XXXXXXXX
SMC1_PWCS
00000000
0xB0730404
reserved
XXXXXXXX
SMC1_PWCC
00000000
0xB0730406
SMC1_PWC1
000000XX XXXXXXXX
0xB0730408
SMC1_PWC2
000000XX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 156
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073040A
SMC1_PWS
00000000 00000000
0xB073040C
SMC1_PWSS
00000000 XXXXXXXX
0xB073040E
reserved
XXXXXXXX
SMC1_PTRGDL
00000000
0xB0730410
reserved
XXXXXXXX
SMC1_DEBUG
00000000
0xB0730412B07307FE
reserved
XXXXXXXX XXXXXXXX
0xB0730800
reserved
XXXXXXXX
SMC2_PWC
00000000
0xB0730802
reserved
XXXXXXXX
SMC2_PWCS
00000000
0xB0730804
reserved
XXXXXXXX
SMC2_PWCC
00000000
0xB0730806
SMC2_PWC1
000000XX XXXXXXXX
0xB0730808
SMC2_PWC2
000000XX XXXXXXXX
0xB073080A
SMC2_PWS
00000000 00000000
0xB073080C
SMC2_PWSS
00000000 XXXXXXXX
0xB073080E
reserved
XXXXXXXX
SMC2_PTRGDL
00000000
0xB0730810
reserved
XXXXXXXX
SMC2_DEBUG
00000000
0xB0730812B0730BFE
reserved
XXXXXXXX XXXXXXXX
0xB0730C00
reserved
XXXXXXXX
SMC3_PWC
00000000
0xB0730C02
reserved
XXXXXXXX
SMC3_PWCS
00000000
Document Number: DS707-00002-4v1-E
Page 157
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0730C04
reserved
XXXXXXXX
SMC3_PWCC
00000000
0xB0730C06
SMC3_PWC1
000000XX XXXXXXXX
0xB0730C08
SMC3_PWC2
000000XX XXXXXXXX
0xB0730C0A
SMC3_PWS
00000000 00000000
0xB0730C0C
SMC3_PWSS
00000000 XXXXXXXX
0xB0730C0E
reserved
XXXXXXXX
SMC3_PTRGDL
00000000
0xB0730C10
reserved
XXXXXXXX
SMC3_DEBUG
00000000
0xB0730C12B0730FFE
reserved
XXXXXXXX XXXXXXXX
0xB0731000
reserved
XXXXXXXX
SMC4_PWC
00000000
0xB0731002
reserved
XXXXXXXX
SMC4_PWCS
00000000
0xB0731004
reserved
XXXXXXXX
SMC4_PWCC
00000000
0xB0731006
SMC4_PWC1
000000XX XXXXXXXX
0xB0731008
SMC4_PWC2
000000XX XXXXXXXX
0xB073100A
SMC4_PWS
00000000 00000000
0xB073100C
SMC4_PWSS
00000000 XXXXXXXX
0xB073100E
reserved
XXXXXXXX
SMC4_PTRGDL
00000000
0xB0731010
reserved
XXXXXXXX
SMC4_DEBUG
00000000
Document Number: DS707-00002-4v1-E
Page 158
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
0xB0731012B07313FE
+1
+0
reserved
XXXXXXXX XXXXXXXX
0xB0731400
reserved
XXXXXXXX
SMC5_PWC
00000000
0xB0731402
reserved
XXXXXXXX
SMC5_PWCS
00000000
0xB0731404
reserved
XXXXXXXX
SMC5_PWCC
00000000
0xB0731406
SMC5_PWC1
000000XX XXXXXXXX
0xB0731408
SMC5_PWC2
000000XX XXXXXXXX
0xB073140A
SMC5_PWS
00000000 00000000
0xB073140C
SMC5_PWSS
00000000 XXXXXXXX
0xB073140E
reserved
XXXXXXXX
SMC5_PTRGDL
00000000
0xB0731410
reserved
XXXXXXXX
SMC5_DEBUG
00000000
0xB0731412B07317FE
reserved
XXXXXXXX XXXXXXXX
0xB0731800
SMCTG0_PTRGS
00000000 00000000
0xB0731802
reserved
XXXXXXXX
SMCTG0_PTRG
00000000
0xB0731804B0737FFE
reserved
XXXXXXXX XXXXXXXX
0xB0738000
PPG0_PCN
00000000 00000000
0xB0738002
PPG0_SWTRIG
00000000
PPG0_IRQCLR
00000000
0xB0738004
PPG0_CNTEN
00000000
PPG0_OE
00000000
Document Number: DS707-00002-4v1-E
Page 159
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0738006
PPG0_RMPCFG
00000000
PPG0_OPTMSK
00000000
0xB0738008
PPG0_TRIGCLR
00000000
PPG0_STRD
00000000
0xB073800A
PPG0_EPCN1
00000000 00000000
0xB073800C
PPG0_EPCN2
00000000 00000000
0xB073800E
PPG0_GCN3
00000000
PPG0_GCN1
00000000
0xB0738010
PPG0_GCN5
00000000
PPG0_GCN4
00000110
0xB0738012
PPG0_PCSR
XXXXXXXX XXXXXXXX
0xB0738014
PPG0_PDUT
XXXXXXXX XXXXXXXX
0xB0738016
PPG0_PTMR
11111111 11111111
0xB0738018
PPG0_PSDR
00000000 00000000
0xB073801A
PPG0_PTPC
00000000 00000000
0xB073801C
PPG0_PEDR
00000000 00000000
0xB073801E
PPG0_DEBUG
00000000
PPG0_DMACFG
00000000
0xB0738020B07383FE
reserved
XXXXXXXX XXXXXXXX
0xB0738400
PPG1_PCN
00000000 00000000
0xB0738402
PPG1_SWTRIG
00000000
PPG1_IRQCLR
00000000
0xB0738404
PPG1_CNTEN
00000000
PPG1_OE
00000000
Document Number: DS707-00002-4v1-E
Page 160
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0738406
PPG1_RMPCFG
00000000
PPG1_OPTMSK
00000000
0xB0738408
PPG1_TRIGCLR
00000000
PPG1_STRD
00000000
0xB073840A
PPG1_EPCN1
00000000 00000000
0xB073840C
PPG1_EPCN2
00000000 00000000
0xB073840E
PPG1_GCN3
00000000
PPG1_GCN1
00000000
0xB0738410
PPG1_GCN5
00000000
PPG1_GCN4
00000110
0xB0738412
PPG1_PCSR
XXXXXXXX XXXXXXXX
0xB0738414
PPG1_PDUT
XXXXXXXX XXXXXXXX
0xB0738416
PPG1_PTMR
11111111 11111111
0xB0738418
PPG1_PSDR
00000000 00000000
0xB073841A
PPG1_PTPC
00000000 00000000
0xB073841C
PPG1_PEDR
00000000 00000000
0xB073841E
PPG1_DEBUG
00000000
PPG1_DMACFG
00000000
0xB0738420B07387FE
reserved
XXXXXXXX XXXXXXXX
0xB0738800
PPG2_PCN
00000000 00000000
0xB0738802
PPG2_SWTRIG
00000000
PPG2_IRQCLR
00000000
0xB0738804
PPG2_CNTEN
00000000
PPG2_OE
00000000
Document Number: DS707-00002-4v1-E
Page 161
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0738806
PPG2_RMPCFG
00000000
PPG2_OPTMSK
00000000
0xB0738808
PPG2_TRIGCLR
00000000
PPG2_STRD
00000000
0xB073880A
PPG2_EPCN1
00000000 00000000
0xB073880C
PPG2_EPCN2
00000000 00000000
0xB073880E
PPG2_GCN3
00000000
PPG2_GCN1
00000000
0xB0738810
PPG2_GCN5
00000000
PPG2_GCN4
00000110
0xB0738812
PPG2_PCSR
XXXXXXXX XXXXXXXX
0xB0738814
PPG2_PDUT
XXXXXXXX XXXXXXXX
0xB0738816
PPG2_PTMR
11111111 11111111
0xB0738818
PPG2_PSDR
00000000 00000000
0xB073881A
PPG2_PTPC
00000000 00000000
0xB073881C
PPG2_PEDR
00000000 00000000
0xB073881E
PPG2_DEBUG
00000000
PPG2_DMACFG
00000000
0xB0738820B0738BFE
reserved
XXXXXXXX XXXXXXXX
0xB0738C00
PPG3_PCN
00000000 00000000
0xB0738C02
PPG3_SWTRIG
00000000
PPG3_IRQCLR
00000000
0xB0738C04
PPG3_CNTEN
00000000
PPG3_OE
00000000
Document Number: DS707-00002-4v1-E
Page 162
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0738C06
PPG3_RMPCFG
00000000
PPG3_OPTMSK
00000000
0xB0738C08
PPG3_TRIGCLR
00000000
PPG3_STRD
00000000
0xB0738C0A
PPG3_EPCN1
00000000 00000000
0xB0738C0C
PPG3_EPCN2
00000000 00000000
0xB0738C0E
PPG3_GCN3
00000000
PPG3_GCN1
00000000
0xB0738C10
PPG3_GCN5
00000000
PPG3_GCN4
00000110
0xB0738C12
PPG3_PCSR
XXXXXXXX XXXXXXXX
0xB0738C14
PPG3_PDUT
XXXXXXXX XXXXXXXX
0xB0738C16
PPG3_PTMR
11111111 11111111
0xB0738C18
PPG3_PSDR
00000000 00000000
0xB0738C1A
PPG3_PTPC
00000000 00000000
0xB0738C1C
PPG3_PEDR
00000000 00000000
0xB0738C1E
PPG3_DEBUG
00000000
PPG3_DMACFG
00000000
0xB0738C20B0738FFE
reserved
XXXXXXXX XXXXXXXX
0xB0739000
PPG4_PCN
00000000 00000000
0xB0739002
PPG4_SWTRIG
00000000
PPG4_IRQCLR
00000000
0xB0739004
PPG4_CNTEN
00000000
PPG4_OE
00000000
Document Number: DS707-00002-4v1-E
Page 163
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0739006
PPG4_RMPCFG
00000000
PPG4_OPTMSK
00000000
0xB0739008
PPG4_TRIGCLR
00000000
PPG4_STRD
00000000
0xB073900A
PPG4_EPCN1
00000000 00000000
0xB073900C
PPG4_EPCN2
00000000 00000000
0xB073900E
PPG4_GCN3
00000000
PPG4_GCN1
00000000
0xB0739010
PPG4_GCN5
00000000
PPG4_GCN4
00000110
0xB0739012
PPG4_PCSR
XXXXXXXX XXXXXXXX
0xB0739014
PPG4_PDUT
XXXXXXXX XXXXXXXX
0xB0739016
PPG4_PTMR
11111111 11111111
0xB0739018
PPG4_PSDR
00000000 00000000
0xB073901A
PPG4_PTPC
00000000 00000000
0xB073901C
PPG4_PEDR
00000000 00000000
0xB073901E
PPG4_DEBUG
00000000
PPG4_DMACFG
00000000
0xB0739020B07393FE
reserved
XXXXXXXX XXXXXXXX
0xB0739400
PPG5_PCN
00000000 00000000
0xB0739402
PPG5_SWTRIG
00000000
PPG5_IRQCLR
00000000
0xB0739404
PPG5_CNTEN
00000000
PPG5_OE
00000000
Document Number: DS707-00002-4v1-E
Page 164
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0739406
PPG5_RMPCFG
00000000
PPG5_OPTMSK
00000000
0xB0739408
PPG5_TRIGCLR
00000000
PPG5_STRD
00000000
0xB073940A
PPG5_EPCN1
00000000 00000000
0xB073940C
PPG5_EPCN2
00000000 00000000
0xB073940E
PPG5_GCN3
00000000
PPG5_GCN1
00000000
0xB0739410
PPG5_GCN5
00000000
PPG5_GCN4
00000110
0xB0739412
PPG5_PCSR
XXXXXXXX XXXXXXXX
0xB0739414
PPG5_PDUT
XXXXXXXX XXXXXXXX
0xB0739416
PPG5_PTMR
11111111 11111111
0xB0739418
PPG5_PSDR
00000000 00000000
0xB073941A
PPG5_PTPC
00000000 00000000
0xB073941C
PPG5_PEDR
00000000 00000000
0xB073941E
PPG5_DEBUG
00000000
PPG5_DMACFG
00000000
0xB0739420B07397FE
reserved
XXXXXXXX XXXXXXXX
0xB0739800
PPG6_PCN
00000000 00000000
0xB0739802
PPG6_SWTRIG
00000000
PPG6_IRQCLR
00000000
0xB0739804
PPG6_CNTEN
00000000
PPG6_OE
00000000
Document Number: DS707-00002-4v1-E
Page 165
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0739806
PPG6_RMPCFG
00000000
PPG6_OPTMSK
00000000
0xB0739808
PPG6_TRIGCLR
00000000
PPG6_STRD
00000000
0xB073980A
PPG6_EPCN1
00000000 00000000
0xB073980C
PPG6_EPCN2
00000000 00000000
0xB073980E
PPG6_GCN3
00000000
PPG6_GCN1
00000000
0xB0739810
PPG6_GCN5
00000000
PPG6_GCN4
00000110
0xB0739812
PPG6_PCSR
XXXXXXXX XXXXXXXX
0xB0739814
PPG6_PDUT
XXXXXXXX XXXXXXXX
0xB0739816
PPG6_PTMR
11111111 11111111
0xB0739818
PPG6_PSDR
00000000 00000000
0xB073981A
PPG6_PTPC
00000000 00000000
0xB073981C
PPG6_PEDR
00000000 00000000
0xB073981E
PPG6_DEBUG
00000000
PPG6_DMACFG
00000000
0xB0739820B0739BFE
reserved
XXXXXXXX XXXXXXXX
0xB0739C00
PPG7_PCN
00000000 00000000
0xB0739C02
PPG7_SWTRIG
00000000
PPG7_IRQCLR
00000000
0xB0739C04
PPG7_CNTEN
00000000
PPG7_OE
00000000
Document Number: DS707-00002-4v1-E
Page 166
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB0739C06
PPG7_RMPCFG
00000000
PPG7_OPTMSK
00000000
0xB0739C08
PPG7_TRIGCLR
00000000
PPG7_STRD
00000000
0xB0739C0A
PPG7_EPCN1
00000000 00000000
0xB0739C0C
PPG7_EPCN2
00000000 00000000
0xB0739C0E
PPG7_GCN3
00000000
PPG7_GCN1
00000000
0xB0739C10
PPG7_GCN5
00000000
PPG7_GCN4
00000110
0xB0739C12
PPG7_PCSR
XXXXXXXX XXXXXXXX
0xB0739C14
PPG7_PDUT
XXXXXXXX XXXXXXXX
0xB0739C16
PPG7_PTMR
11111111 11111111
0xB0739C18
PPG7_PSDR
00000000 00000000
0xB0739C1A
PPG7_PTPC
00000000 00000000
0xB0739C1C
PPG7_PEDR
00000000 00000000
0xB0739C1E
PPG7_DEBUG
00000000
PPG7_DMACFG
00000000
0xB0739C20B0739FFE
reserved
XXXXXXXX XXXXXXXX
0xB073A000
PPG8_PCN
00000000 00000000
0xB073A002
PPG8_SWTRIG
00000000
PPG8_IRQCLR
00000000
0xB073A004
PPG8_CNTEN
00000000
PPG8_OE
00000000
Document Number: DS707-00002-4v1-E
Page 167
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073A006
PPG8_RMPCFG
00000000
PPG8_OPTMSK
00000000
0xB073A008
PPG8_TRIGCLR
00000000
PPG8_STRD
00000000
0xB073A00A
PPG8_EPCN1
00000000 00000000
0xB073A00C
PPG8_EPCN2
00000000 00000000
0xB073A00E
PPG8_GCN3
00000000
PPG8_GCN1
00000000
0xB073A010
PPG8_GCN5
00000000
PPG8_GCN4
00000110
0xB073A012
PPG8_PCSR
XXXXXXXX XXXXXXXX
0xB073A014
PPG8_PDUT
XXXXXXXX XXXXXXXX
0xB073A016
PPG8_PTMR
11111111 11111111
0xB073A018
PPG8_PSDR
00000000 00000000
0xB073A01A
PPG8_PTPC
00000000 00000000
0xB073A01C
PPG8_PEDR
00000000 00000000
0xB073A01E
PPG8_DEBUG
00000000
PPG8_DMACFG
00000000
0xB073A020B073A3FE
reserved
XXXXXXXX XXXXXXXX
0xB073A400
PPG9_PCN
00000000 00000000
0xB073A402
PPG9_SWTRIG
00000000
PPG9_IRQCLR
00000000
0xB073A404
PPG9_CNTEN
00000000
PPG9_OE
00000000
Document Number: DS707-00002-4v1-E
Page 168
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073A406
PPG9_RMPCFG
00000000
PPG9_OPTMSK
00000000
0xB073A408
PPG9_TRIGCLR
00000000
PPG9_STRD
00000000
0xB073A40A
PPG9_EPCN1
00000000 00000000
0xB073A40C
PPG9_EPCN2
00000000 00000000
0xB073A40E
PPG9_GCN3
00000000
PPG9_GCN1
00000000
0xB073A410
PPG9_GCN5
00000000
PPG9_GCN4
00000110
0xB073A412
PPG9_PCSR
XXXXXXXX XXXXXXXX
0xB073A414
PPG9_PDUT
XXXXXXXX XXXXXXXX
0xB073A416
PPG9_PTMR
11111111 11111111
0xB073A418
PPG9_PSDR
00000000 00000000
0xB073A41A
PPG9_PTPC
00000000 00000000
0xB073A41C
PPG9_PEDR
00000000 00000000
0xB073A41E
PPG9_DEBUG
00000000
PPG9_DMACFG
00000000
0xB073A420B073A7FE
reserved
XXXXXXXX XXXXXXXX
0xB073A800
PPG10_PCN
00000000 00000000
0xB073A802
PPG10_SWTRIG
00000000
PPG10_IRQCLR
00000000
0xB073A804
PPG10_CNTEN
00000000
PPG10_OE
00000000
Document Number: DS707-00002-4v1-E
Page 169
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073A806
PPG10_RMPCFG
00000000
PPG10_OPTMSK
00000000
0xB073A808
PPG10_TRIGCLR
00000000
PPG10_STRD
00000000
0xB073A80A
PPG10_EPCN1
00000000 00000000
0xB073A80C
PPG10_EPCN2
00000000 00000000
0xB073A80E
PPG10_GCN3
00000000
PPG10_GCN1
00000000
0xB073A810
PPG10_GCN5
00000000
PPG10_GCN4
00000110
0xB073A812
PPG10_PCSR
XXXXXXXX XXXXXXXX
0xB073A814
PPG10_PDUT
XXXXXXXX XXXXXXXX
0xB073A816
PPG10_PTMR
11111111 11111111
0xB073A818
PPG10_PSDR
00000000 00000000
0xB073A81A
PPG10_PTPC
00000000 00000000
0xB073A81C
PPG10_PEDR
00000000 00000000
0xB073A81E
PPG10_DEBUG
00000000
PPG10_DMACFG
00000000
0xB073A820B073ABFE
reserved
XXXXXXXX XXXXXXXX
0xB073AC00
PPG11_PCN
00000000 00000000
0xB073AC02
PPG11_SWTRIG
00000000
PPG11_IRQCLR
00000000
0xB073AC04
PPG11_CNTEN
00000000
PPG11_OE
00000000
Document Number: DS707-00002-4v1-E
Page 170
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073AC06
PPG11_RMPCFG
00000000
PPG11_OPTMSK
00000000
0xB073AC08
PPG11_TRIGCLR
00000000
PPG11_STRD
00000000
0xB073AC0A
PPG11_EPCN1
00000000 00000000
0xB073AC0C
PPG11_EPCN2
00000000 00000000
0xB073AC0E
PPG11_GCN3
00000000
PPG11_GCN1
00000000
0xB073AC10
PPG11_GCN5
00000000
PPG11_GCN4
00000110
0xB073AC12
PPG11_PCSR
XXXXXXXX XXXXXXXX
0xB073AC14
PPG11_PDUT
XXXXXXXX XXXXXXXX
0xB073AC16
PPG11_PTMR
11111111 11111111
0xB073AC18
PPG11_PSDR
00000000 00000000
0xB073AC1A
PPG11_PTPC
00000000 00000000
0xB073AC1C
PPG11_PEDR
00000000 00000000
0xB073AC1E
PPG11_DEBUG
00000000
PPG11_DMACFG
00000000
0xB073AC20B073AFFE
reserved
XXXXXXXX XXXXXXXX
0xB073B000
PPG12_PCN
00000000 00000000
0xB073B002
PPG12_SWTRIG
00000000
PPG12_IRQCLR
00000000
0xB073B004
PPG12_CNTEN
00000000
PPG12_OE
00000000
Document Number: DS707-00002-4v1-E
Page 171
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073B006
PPG12_RMPCFG
00000000
PPG12_OPTMSK
00000000
0xB073B008
PPG12_TRIGCLR
00000000
PPG12_STRD
00000000
0xB073B00A
PPG12_EPCN1
00000000 00000000
0xB073B00C
PPG12_EPCN2
00000000 00000000
0xB073B00E
PPG12_GCN3
00000000
PPG12_GCN1
00000000
0xB073B010
PPG12_GCN5
00000000
PPG12_GCN4
00000110
0xB073B012
PPG12_PCSR
XXXXXXXX XXXXXXXX
0xB073B014
PPG12_PDUT
XXXXXXXX XXXXXXXX
0xB073B016
PPG12_PTMR
11111111 11111111
0xB073B018
PPG12_PSDR
00000000 00000000
0xB073B01A
PPG12_PTPC
00000000 00000000
0xB073B01C
PPG12_PEDR
00000000 00000000
0xB073B01E
PPG12_DEBUG
00000000
PPG12_DMACFG
00000000
0xB073B020B073B3FE
reserved
XXXXXXXX XXXXXXXX
0xB073B400
PPG13_PCN
00000000 00000000
0xB073B402
PPG13_SWTRIG
00000000
PPG13_IRQCLR
00000000
0xB073B404
PPG13_CNTEN
00000000
PPG13_OE
00000000
Document Number: DS707-00002-4v1-E
Page 172
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073B406
PPG13_RMPCFG
00000000
PPG13_OPTMSK
00000000
0xB073B408
PPG13_TRIGCLR
00000000
PPG13_STRD
00000000
0xB073B40A
PPG13_EPCN1
00000000 00000000
0xB073B40C
PPG13_EPCN2
00000000 00000000
0xB073B40E
PPG13_GCN3
00000000
PPG13_GCN1
00000000
0xB073B410
PPG13_GCN5
00000000
PPG13_GCN4
00000110
0xB073B412
PPG13_PCSR
XXXXXXXX XXXXXXXX
0xB073B414
PPG13_PDUT
XXXXXXXX XXXXXXXX
0xB073B416
PPG13_PTMR
11111111 11111111
0xB073B418
PPG13_PSDR
00000000 00000000
0xB073B41A
PPG13_PTPC
00000000 00000000
0xB073B41C
PPG13_PEDR
00000000 00000000
0xB073B41E
PPG13_DEBUG
00000000
PPG13_DMACFG
00000000
0xB073B420B073B7FE
reserved
XXXXXXXX XXXXXXXX
0xB073B800
PPG14_PCN
00000000 00000000
0xB073B802
PPG14_SWTRIG
00000000
PPG14_IRQCLR
00000000
0xB073B804
PPG14_CNTEN
00000000
PPG14_OE
00000000
Document Number: DS707-00002-4v1-E
Page 173
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073B806
PPG14_RMPCFG
00000000
PPG14_OPTMSK
00000000
0xB073B808
PPG14_TRIGCLR
00000000
PPG14_STRD
00000000
0xB073B80A
PPG14_EPCN1
00000000 00000000
0xB073B80C
PPG14_EPCN2
00000000 00000000
0xB073B80E
PPG14_GCN3
00000000
PPG14_GCN1
00000000
0xB073B810
PPG14_GCN5
00000000
PPG14_GCN4
00000110
0xB073B812
PPG14_PCSR
XXXXXXXX XXXXXXXX
0xB073B814
PPG14_PDUT
XXXXXXXX XXXXXXXX
0xB073B816
PPG14_PTMR
11111111 11111111
0xB073B818
PPG14_PSDR
00000000 00000000
0xB073B81A
PPG14_PTPC
00000000 00000000
0xB073B81C
PPG14_PEDR
00000000 00000000
0xB073B81E
PPG14_DEBUG
00000000
PPG14_DMACFG
00000000
0xB073B820B073BBFE
reserved
XXXXXXXX XXXXXXXX
0xB073BC00
PPG15_PCN
00000000 00000000
0xB073BC02
PPG15_SWTRIG
00000000
PPG15_IRQCLR
00000000
0xB073BC04
PPG15_CNTEN
00000000
PPG15_OE
00000000
Document Number: DS707-00002-4v1-E
Page 174
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB073BC06
PPG15_RMPCFG
00000000
PPG15_OPTMSK
00000000
0xB073BC08
PPG15_TRIGCLR
00000000
PPG15_STRD
00000000
0xB073BC0A
PPG15_EPCN1
00000000 00000000
0xB073BC0C
PPG15_EPCN2
00000000 00000000
0xB073BC0E
PPG15_GCN3
00000000
PPG15_GCN1
00000000
0xB073BC10
PPG15_GCN5
00000000
PPG15_GCN4
00000110
0xB073BC12
PPG15_PCSR
XXXXXXXX XXXXXXXX
0xB073BC14
PPG15_PDUT
XXXXXXXX XXXXXXXX
0xB073BC16
PPG15_PTMR
11111111 11111111
0xB073BC18
PPG15_PSDR
00000000 00000000
0xB073BC1A
PPG15_PTPC
00000000 00000000
0xB073BC1C
PPG15_PEDR
00000000 00000000
0xB073BC1E
0xB073BC20B0747FFE
0xB0748000
0xB0748002B07483FE
0xB0748400
Document Number: DS707-00002-4v1-E
PPG15_DEBUG
00000000
PPG15_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP0_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP1_GCTRL
00000000
Page 175
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
0xB0748402B07487FE
0xB0748800
0xB0748802B0748BFE
0xB0748C00
0xB0748C02B074BFFE
0xB074C000
+1
+0
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP2_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP3_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGLC0_GCNR
00000000
0xB074C002B07E804E
reserved
XXXXXXXX XXXXXXXX
0xB07E8050
PPC_PCFGR040
0XX00100 00000000
0xB07E8052
PPC_PCFGR041
0XX00100 00000000
0xB07E8054
PPC_PCFGR042
0XX00100 00000000
0xB07E8056
PPC_PCFGR043
0XX00100 00000000
0xB07E8058
PPC_PCFGR044
0XX00100 00000000
0xB07E805A
PPC_PCFGR045
0XX00100 00000000
0xB07E805C
PPC_PCFGR046
0XX00100 00000000
0xB07E805E
PPC_PCFGR047
0XX00100 00000000
0xB07E8060
PPC_PCFGR048
0XX00100 00000000
0xB07E8062
PPC_PCFGR049
0XX00100 00000000
Document Number: DS707-00002-4v1-E
Page 176
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E8064
PPC_PCFGR050
0XX00100 00000000
0xB07E8066
PPC_PCFGR051
0XX00100 00000000
0xB07E8068 - 0xB07E807A
reserved
XXXXXXXX XXXXXXXX
0xB07E807C
PPC_PCFGR062
0XX00100 00000000
0xB07E807E
PPC_PCFGR063
0XX00100 00000000
0xB07E8080
PPC_PCFGR100
0XX00100 00000000
0xB07E8082
PPC_PCFGR101
0XX00100 00000000
0xB07E8084
PPC_PCFGR102
0XX00100 00000000
0xB07E8086
PPC_PCFGR103
0XX00100 00000000
0xB07E8088
PPC_PCFGR104
0XX00100 00000000
0xB07E808A
PPC_PCFGR105
0XX00100 00000000
0xB07E808C
PPC_PCFGR106
0XX00100 00000000
0xB07E808E
PPC_PCFGR107
0XX00100 00000000
0xB07E8090
PPC_PCFGR108
0XX0100 00000000
0xB07E8092
PPC_PCFGR109
0XX00100 00000000
0xB07E8094
PPC_PCFGR110
0XX00100 00000000
0xB07E8096
PPC_PCFGR111
0XX00100 00000000
Document Number: DS707-00002-4v1-E
Page 177
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E8098
PPC_PCFGR112
0XX00100 00000000
0xB07E809A
PPC_PCFGR113
0XX00100 00000000
0xB07E809C
PPC_PCFGR114
0XX00100 00000000
0xB07E809E
PPC_PCFGR115
0XX00100 00000000
0xB07E80A0
PPC_PCFGR116
0XX00100 00000000
0xB07E80A2
PPC_PCFGR117
0XX00100 00000000
0xB07E80A4
PPC_PCFGR118
0XX00100 00000000
0xB07E80A6
PPC_PCFGR119
0XX00100 00000000
0xB07E80A8
PPC_PCFGR120
0XX00100 00000000
0xB07E80AA
PPC_PCFGR121
0XX00100 00000000
0xB07E80AC
PPC_PCFGR122
0XX00100 00000000
0xB07E80AE
PPC_PCFGR123
0XX00100 00000000
0xB07E80B0
PPC_PCFGR124
0XX00000 00000000
0xB07E80B2
PPC_PCFGR125
0XX00000 00000000
0xB07E80B4
PPC_PCFGR126
0XX00000 00000000
0xB07E80B6
PPC_PCFGR127
0XX00000 00000000
0xB07E80B8
PPC_PCFGR128
0XX00000 00000000
Document Number: DS707-00002-4v1-E
Page 178
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E80BA
PPC_PCFGR129
0XX00000 00000000
0xB07E80BC
PPC_PCFGR130
0XX00000 00000000
0xB07E80BE
PPC_PCFGR131
0XX00000 00000000
0xB07E80C0
PPC_PCFGR132
0XX00000 00000000
0xB07E80C2
PPC_PCFGR133
0XX00000 00000000
0xB07E80C4
PPC_PCFGR134
0XX00000 00000000
0xB07E80C6
PPC_PCFGR135
0XX00000 00000000
0xB07E80C8
PPC_PCFGR136
0XX00000 00000000
0xB07E80CA
PPC_PCFGR137
0XX00000 00000000
0xB07E80CC
PPC_PCFGR138
0XX00000 00000000
0xB07E80CE - 0xB07E813E
reserved
XXXXXXXX XXXXXXXX
0xB07E8140
PPC_PCFGR232
0XX00000 00000000
0xB07E8142
PPC_PCFGR233
0XX00000 00000000
0xB07E8144
PPC_PCFGR234
0XX00000 00000000
0xB07E8146
PPC_PCFGR235
0XX00000 00000000
0xB07E8148
PPC_PCFGR236
0XX00000 00000000
0xB07E814A
PPC_PCFGR237
0XX00000 00000000
Document Number: DS707-00002-4v1-E
Page 179
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E814C
PPC_PCFGR238
0XX00000 00000000
0xB07E814E
PPC_PCFGR239
0XX00000 00000000
0xB07E8150
PPC_PCFGR240
0XX00000 00000000
0xB07E8152
PPC_PCFGR241
0XX00000 00000000
0xB07E8154
PPC_PCFGR242
0XX00000 00000000
0xB07E8156
PPC_PCFGR243
0XX00000 00000000
0xB07E8158
PPC_PCFGR244
0XX00000 00000000
0xB07E815A
PPC_PCFGR245
0XX00000 00000000
0xB07E815C
PPC_PCFGR246
0XX00000 00000000
0xB07E815E
PPC_PCFGR247
0XX00000 00000000
0xB07E8160 - 0xB07E817E
reserved
XXXXXXXX XXXXXXXX
0xB07E8180
PPC_PCFGR300
0XX00000 00000000
0xB07E8182
PPC_PCFGR301
0XX00000 00000000
0xB07E8184
PPC_PCFGR302
0XX00000 00000000
0xB07E8186
PPC_PCFGR303
0XX00000 00000000
0xB07E8188
PPC_PCFGR304
0XX00000 00000000
0xB07E818A
PPC_PCFGR305
0XX00000 00000000
Document Number: DS707-00002-4v1-E
Page 180
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E818C
PPC_PCFGR306
0XX00000 00000000
0xB07E818E
PPC_PCFGR307
0XX00000 00000000
0xB07E8190
PPC_PCFGR308
0XX00000 00000000
0xB07E8192
PPC_PCFGR309
0XX00000 00000000
0xB07E8194
PPC_PCFGR310
0XX00000 00000000
0xB07E8196
PPC_PCFGR311
0XX00000 00000000
0xB07E8198
PPC_PCFGR312
0XX00000 00000000
0xB07E819A
PPC_PCFGR313
0XX00000 00000000
0xB07E819C
PPC_PCFGR314
0XX00000 00000000
0xB07E819E
PPC_PCFGR315
0XX00000 00000000
0xB07E81A0
PPC_PCFGR316
0XX00000 00000000
0xB07E81A2
PPC_PCFGR317
0XX00000 00000000
0xB07E81A4
PPC_PCFGR318
0XX00000 00000000
0xB07E81A6
PPC_PCFGR319
0XX00000 00000000
0xB07E81A8
PPC_PCFGR320
0XX00000 00000000
0xB07E81AA
PPC_PCFGR321
0XX00000 00000000
0xB07E81AC
PPC_PCFGR322
0XX00000 00000000
Document Number: DS707-00002-4v1-E
Page 181
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E81AE
PPC_PCFGR323
0XX00000 00000000
0xB07E81B0
PPC_PCFGR324
0XX00000 00000000
0xB07E81B2
PPC_PCFGR325
0XX00000 00000000
0xB07E81B4
PPC_PCFGR326
0XX00000 00000000
0xB07E81B6
PPC_PCFGR327
0XX00000 00000000
0xB07E81B8
PPC_PCFGR328
0XX00000 00000000
0xB07E81BA
PPC_PCFGR329
0XX00000 00000000
0xB07E81BC
PPC_PCFGR330
0XX00000 00000000
0xB07E81BE
PPC_PCFGR331
0XX00000 00000000
0xB07E81C0
PPC_PCFGR332
0XX00000 00000000
0xB07E81C2
PPC_PCFGR333
0XX00000 00000000
0xB07E81C4
PPC_PCFGR334
0XX00000 00000000
0xB07E81C6
PPC_PCFGR335
0XX00000 00000000
0xB07E81C8
PPC_PCFGR336
0XX00000 00000000
0xB07E81CA
PPC_PCFGR337
0XX00000 00000000
0xB07E81CC
PPC_PCFGR338
0XX00000 00000000
0xB07E81CE
PPC_PCFGR339
0XX00000 00000000
Document Number: DS707-00002-4v1-E
Page 182
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07E81D0
PPC_PCFGR340
0XX00000 00000000
0xB07E81D2
PPC_PCFGR341
0XX00000 00000000
0xB07E81D4
PPC_PCFGR342
0XX00000 00000000
0xB07E81D6B07EFFFE
reserved
XXXXXXXX XXXXXXXX
0xB07F0000
BECU0_CTRL
00000000 00000000
0xB07F0002
BECU0_CTRH
00000000 00000000
0xB07F0004
BECU0_ADDRL
00000000 00000000
0xB07F0006
BECU0_ADDRH
00000000 00000000
0xB07F0008
BECU0_DATALL
00000000 00000000
0xB07F000A
BECU0_DATALH
00000000 00000000
0xB07F000C
BECU0_DATAHL
00000000 00000000
0xB07F000E
BECU0_DATAHH
00000000 00000000
0xB07F0010
BECU0_MASTERID
00000000 00000000
0xB07F0012
BECU0_MIDL
XXXXXXXX XXXXXXXX
0xB07F0014
BECU0_MIDH
XXXXXXXX XXXXXXXX
0xB07F0016
reserved
00000000 00000000
0xB07F0018
BECU0_NMIEN
XXXXXXXX 00000001
Document Number: DS707-00002-4v1-E
Page 183
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F001AB07F7FFE
reserved
XXXXXXXX XXXXXXXX
0xB07F8000
RICFG0_ADC0AN26
00000000 XXXXXXXX
0xB07F8002
RICFG0_ADC0AN27
00000000 XXXXXXXX
0xB07F8004
RICFG0_ADC0AN28
00000000 XXXXXXXX
0xB07F8006
RICFG0_ADC0AN29
00000000 XXXXXXXX
0xB07F8008
RICFG0_ADC0AN30
00000000 XXXXXXXX
0xB07F800A
RICFG0_ADC0AN31
00000000 XXXXXXXX
0xB07F800C
RICFG0_ADC0EDGI
00000000 00000000
0xB07F800E
RICFG0_ADC0EDGIOCU0
XXXXXXXX 00000000
0xB07F8010B07F8014
reserved
XXXXXXXX XXXXXXXX
0xB07F8016
RICFG0_ADC0EDGIOCU4
XXXXXXXX 00000000
0xB07F8018B07F801C
reserved
XXXXXXXX XXXXXXXX
0xB07F801E
RICFG0_ADC0TIMI
XXXXXXXX 00000000
0xB07F8020
RICFG0_ADC0TIMIRLT
XXXXXXXX 00000000
0xB07F8022B07F803C
reserved
XXXXXXXX XXXXXXXX
0xB07F803E
RICFG0_ADC0ZPDEN
XXXXXXXX 00000000
0xB07F8040B07F83FE
reserved
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 184
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F8400
RICFG0_FRT0TEXT
00000000 00000000
0xB07F8402B07F841E
reserved
XXXXXXXX 00000000
0xB07F8420
RICFG0_FRT1TEXT
00000000 00000000
0xB07F8422B07F843E
reserved
XXXXXXXX 00000000
0xB07F8440
RICFG0_FRT2TEXT
00000000 00000000
0xB07F8442B07F845E
reserved
XXXXXXXX 00000000
0xB07F8460
RICFG0_FRT3TEXT
00000000 00000000
0xB07F8462B07F883E
reserved
XXXXXXXX 00000000
0xB07F8840
RICFG0_ICU2IN0
00000000 XXXXXXXX
0xB07F8842
RICFG0_ICU2IN1
00000000 XXXXXXXX
0xB07F8844
RICFG0_ICU2FRTSEL
XXXXXXXX 00000000
0xB07F8846B07F885E
reserved
XXXXXXXX 00000000
0xB07F8860
RICFG0_ICU3IN0
00000000 XXXXXXXX
0xB07F8862
RICFG0_ICU3IN1
00000000 XXXXXXXX
0xB07F8864
RICFG0_ICU3FRTSEL
XXXXXXXX 00000000
0xB07F8866B07F8BFE
reserved
XXXXXXXX 00000000
0xB07F8C00
RICFG0_OCU0OTD0GATE
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 185
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F8C02
RICFG0_OCU0OTD0GM
XXXXXXXX 00000000
0xB07F8C04
RICFG0_OCU0OTD1GATE
XXXXXXXX 00000000
0xB07F8C06
RICFG0_OCU0OTD1GM
XXXXXXXX 00000000
0xB07F8C08B07F8C1E
reserved
XXXXXXXX 00000000
0xB07F8C20
RICFG0_OCU1CMP0EXT
XXXXXXXX 00000000
0xB07F8C22
RICFG0_OCU1FRTSEL
XXXXXXXX 00000000
0xB07F8C24
RICFG0_OCU1OTD0GATE
XXXXXXXX 00000000
0xB07F8C26
RICFG0_OCU1OTD0GM
XXXXXXXX 00000000
0xB07F8C28
RICFG0_OCU1OTD1GATE
XXXXXXXX 00000000
0xB07F8C2A
RICFG0_OCU1OTD1GM
XXXXXXXX 00000000
0xB07F8C2CB07F93FE
reserved
XXXXXXXX XXXXXXXX
0xB07F9400
RICFG0_USART0SCKI
00000000 XXXXXXXX
0xB07F9402
RICFG0_USART0SIN
00000000 XXXXXXXX
0xB07F9404B07F9BFE
reserved
XXXXXXXX XXXXXXXX
0xB07F9C00
RICFG0_PPG0PPGAGATE
XXXXXXXX 00000000
0xB07F9C02
RICFG0_PPG0PPGAGM
XXXXXXXX 00000000
0xB07F9C04
RICFG0_PPG0PPGBGATE
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 186
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F9C06
RICFG0_PPG0PPGBGM
XXXXXXXX 00000000
0xB07F9C08B07F9C1E
reserved
XXXXXXXX 00000000
0xB07F9C20
RICFG0_PPG1PPGAGATE
XXXXXXXX 00000000
0xB07F9C22
RICFG0_PPG1PPGAGM
XXXXXXXX 00000000
0xB07F9C24
RICFG0_PPG1PPGBGATE
XXXXXXXX 00000000
0xB07F9C26
RICFG0_PPG1PPGBGM
XXXXXXXX 00000000
0xB07F9C28B07F9C3E
reserved
XXXXXXXX XXXXXXXX
0xB07F9C40
RICFG0_PPG2PPGAGATE
XXXXXXXX 00000000
0xB07F9C42
RICFG0_PPG2PPGAGM
XXXXXXXX 00000000
0xB07F9C44
RICFG0_PPG2PPGBGATE
XXXXXXXX 00000000
0xB07F9C46
RICFG0_PPG2PPGBGM
XXXXXXXX 00000000
0xB07F9C48B07F9C5E
reserved
XXXXXXXX XXXXXXXX
0xB07F9C60
RICFG0_PPG3PPGAGATE
XXXXXXXX 00000000
0xB07F9C62
RICFG0_PPG3PPGAGM
XXXXXXXX 00000000
0xB07F9C64
RICFG0_PPG3PPGBGATE
XXXXXXXX 00000000
0xB07F9C66
RICFG0_PPG3PPGBGM
XXXXXXXX 00000000
0xB07F9C68B07F9C7E
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 187
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F9C80
RICFG0_PPG4PPGAGATE
XXXXXXXX 00000000
0xB07F9C82
RICFG0_PPG4PPGAGM
XXXXXXXX 00000000
0xB07F9C84
RICFG0_PPG4PPGBGATE
XXXXXXXX 00000000
0xB07F9C86
RICFG0_PPG4PPGBGM
XXXXXXXX 00000000
0xB07F9C88B07F9C9E
reserved
XXXXXXXX XXXXXXXX
0xB07F9CA0
RICFG0_PPG5PPGAGATE
XXXXXXXX 00000000
0xB07F9CA2
RICFG0_PPG5PPGAGM
XXXXXXXX 00000000
0xB07F9CA4
RICFG0_PPG5PPGBGATE
XXXXXXXX 00000000
0xB07F9CA6
RICFG0_PPG5PPGBGM
XXXXXXXX 00000000
0xB07F9CA8B07F9CBE
reserved
XXXXXXXX XXXXXXXX
0xB07F9CC0
RICFG0_PPG6PPGAGATE
XXXXXXXX 00000000
0xB07F9CC2
RICFG0_PPG6PPGAGM
XXXXXXXX 00000000
0xB07F9CC4
RICFG0_PPG6PPGBGATE
XXXXXXXX 00000000
0xB07F9CC6
RICFG0_PPG6PPGBGM
XXXXXXXX 00000000
0xB07F9CC8B07F9CDE
reserved
XXXXXXXX XXXXXXXX
0xB07F9CE0
RICFG0_PPG7PPGAGATE
XXXXXXXX 00000000
0xB07F9CE2
RICFG0_PPG7PPGAGM
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 188
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F9CE4
RICFG0_PPG7PPGBGATE
XXXXXXXX 00000000
0xB07F9CE6
RICFG0_PPG7PPGBGM
XXXXXXXX 00000000
0xB07F9CE8B07F9CFE
reserved
XXXXXXXX XXXXXXXX
0xB07F9D00
RICFG0_PPG8PPGAGATE
XXXXXXXX 00000000
0xB07F9D02
RICFG0_PPG8PPGAGM
XXXXXXXX 00000000
0xB07F9D04
RICFG0_PPG8PPGBGATE
XXXXXXXX 00000000
0xB07F9D06
RICFG0_PPG8PPGBGM
XXXXXXXX 00000000
0xB07F9D08B07F9D1E
reserved
XXXXXXXX XXXXXXXX
0xB07F9D20
RICFG0_PPG9PPGAGATE
XXXXXXXX 00000000
0xB07F9D22
RICFG0_PPG9PPGAGM
XXXXXXXX 00000000
0xB07F9D24
RICFG0_PPG9PPGBGATE
XXXXXXXX 00000000
0xB07F9D26
RICFG0_PPG9PPGBGM
XXXXXXXX 00000000
0xB07F9D28B07F9D3E
reserved
XXXXXXXX XXXXXXXX
0xB07F9D40
RICFG0_PPG10PPGAGATE
XXXXXXXX 00000000
0xB07F9D42
RICFG0_PPG10PPGAGM
XXXXXXXX 00000000
0xB07F9D44
RICFG0_PPG10PPGBGATE
XXXXXXXX 00000000
0xB07F9D46
RICFG0_PPG10PPGBGM
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 189
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F9D48B07F9D5E
reserved
XXXXXXXX XXXXXXXX
0xB07F9D60
RICFG0_PPG11PPGAGATE
XXXXXXXX 00000000
0xB07F9D62
RICFG0_PPG11PPGAGM
XXXXXXXX 00000000
0xB07F9D64
RICFG0_PPG11PPGBGATE
XXXXXXXX 00000000
0xB07F9D66
RICFG0_PPG11PPGBGM
XXXXXXXX 00000000
0xB07F9D68B07F9D7E
reserved
XXXXXXXX XXXXXXXX
0xB07F9D80
RICFG0_PPG12PPGAGATE
XXXXXXXX 00000000
0xB07F9D82
RICFG0_PPG12PPGAGM
XXXXXXXX 00000000
0xB07F9D84
RICFG0_PPG12PPGBGATE
XXXXXXXX 00000000
0xB07F9D86
RICFG0_PPG12PPGBGM
XXXXXXXX 00000000
0xB07F9D88B07F9D9E
reserved
XXXXXXXX XXXXXXXX
0xB07F9DA0
RICFG0_PPG13PPGAGATE
XXXXXXXX 00000000
0xB07F9DA2
RICFG0_PPG13PPGAGM
XXXXXXXX 00000000
0xB07F9DA4
RICFG0_PPG13PPGBGATE
XXXXXXXX 00000000
0xB07F9DA6
RICFG0_PPG13PPGBGM
XXXXXXXX 00000000
0xB07F9DA8B07F9DBE
reserved
XXXXXXXX XXXXXXXX
0xB07F9DC0
RICFG0_PPG14PPGAGATE
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 190
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07F9DC2
RICFG0_PPG14PPGAGM
XXXXXXXX 00000000
0xB07F9DC4
RICFG0_PPG14PPGBGATE
XXXXXXXX 00000000
0xB07F9DC6
RICFG0_PPG14PPGBGM
XXXXXXXX 00000000
0xB07F9DC8B07F9DDE
reserved
XXXXXXXX XXXXXXXX
0xB07F9DE0
RICFG0_PPG15PPGAGATE
XXXXXXXX 00000000
0xB07F9DE2
RICFG0_PPG15PPGAGM
XXXXXXXX 00000000
0xB07F9DE4
RICFG0_PPG15PPGBGATE
XXXXXXXX 00000000
0xB07F9DE6
RICFG0_PPG15PPGBGM
XXXXXXXX 00000000
0xB07F9DE8B07FA3FE
reserved
XXXXXXXX XXXXXXXX
0xB07FA400
RICFG0_PPGGRP0ETRG0
XXXXXXXX 00000000
0xB07FA402
RICFG0_PPGGRP0ETRG1
XXXXXXXX 00000000
0xB07FA404
RICFG0_PPGGRP0ETRG2
XXXXXXXX 00000000
0xB07FA406
RICFG0_PPGGRP0ETRG3
XXXXXXXX 00000000
0xB07FA408
RICFG0_PPGGRP0RLTTRG1
XXXXXXXX 00000000
0xB07FA40AB07FA41E
reserved
XXXXXXXX XXXXXXXX
0xB07FA420
RICFG0_PPGGRP1ETRG0
XXXXXXXX 00000000
0xB07FA422
RICFG0_PPGGRP1ETRG1
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 191
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07FA424
RICFG0_PPGGRP1ETRG2
XXXXXXXX 00000000
0xB07FA426
RICFG0_PPGGRP1ETRG3
XXXXXXXX 00000000
0xB07FA428
RICFG0_PPGGRP1RLTTRG1
XXXXXXXX 00000000
0xB07FA42AB07FA43E
reserved
XXXXXXXX XXXXXXXX
0xB07FA440
RICFG0_PPGGRP2ETRG0
XXXXXXXX 00000000
0xB07FA442
RICFG0_PPGGRP2ETRG1
XXXXXXXX 00000000
0xB07FA444
RICFG0_PPGGRP2ETRG2
XXXXXXXX 00000000
0xB07FA446
RICFG0_PPGGRP2ETRG3
XXXXXXXX 00000000
0xB07FA448
RICFG0_PPGGRP2RLTTRG1
XXXXXXXX 00000000
0xB07FA44AB07FA45E
reserved
XXXXXXXX XXXXXXXX
0xB07FA460
RICFG0_PPGGRP3ETRG0
XXXXXXXX 00000000
0xB07FA462
RICFG0_PPGGRP3ETRG1
XXXXXXXX 00000000
0xB07FA464
RICFG0_PPGGRP3ETRG2
XXXXXXXX 00000000
0xB07FA466
RICFG0_PPGGRP3ETRG3
XXXXXXXX 00000000
0xB07FA468
RICFG0_PPGGRP3RLTTRG1
XXXXXXXX 00000000
0xB07FA46AB07FC002
reserved
XXXXXXXX XXXXXXXX
0xB07FC004
BSU0_BTSTL
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 192
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07FC006
BSU0_BTSTH
00000000 00000000
0xB07FC008B07FC00E
reserved
XXXXXXXX XXXXXXXX
0xB07FC010
BSU0_PEN0L
XXXXXXXX 00000000
0xB07FC012
reserved
XXXXXXXX XXXXXXXX
0xB07FC014
BSU0_PEN1L
00000000 00000000
0xB07FC016
reserved
XXXXXXXX XXXXXXXX
0xB07FC018
BSU0_PEN2L
00000000 00000000
0xB07FC01A
reserved
XXXXXXXX XXXXXXXX
0xB07FC01C
BSU0_PEN3L
00000000 00000000
0xB07FC01E
reserved
XXXXXXXX XXXXXXXX
0xB07FC020
BSU0_PEN4L
XXXXXXXX 00000000
0xB07FC022
reserved
XXXXXXXX XXXXXXXX
0xB07FC024
BSU0_PEN5L
XXXXXXXX 00000000
0xB07FC026
reserved
XXXXXXXX XXXXXXXX
0xB07FC028
BSU0_PEN6L
XXXXXXXX 00000000
0xB07FC02A
reserved
XXXXXXXX XXXXXXXX
0xB07FC02C
BSU0_PEN7L
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 193
MB9DF126
MB9DF126B
Table 5-6 Memory layout for the PERI0_RBUS registers (Continued)
Offset
+1
+0
0xB07FC02E
BSU0_PEN7H
00000000 00000000
0xB07FC030
BSU0_PEN8L
00000000 00000000
0xB07FC032
BSU0_PEN8H
00000000 00000000
0xB07FC034
BSU0_PEN9L
00000000 00000000
0xB07FC036
BSU0_PEN9H
XXXXXXXX 00000000
0xB07FC038B07FC03A
reserved
XXXXXXXX XXXXXXXX
0xB07FC03C
BSU0_PEN11L
XXXXXXXX 00000000
0xB07FC03EB07FFFFE
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 194
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers
Offset
0xB0800000
0xB0800002
+1
+0
SG0_CR0
00000000 00000000
reserved
XXXXXXXX
0xB0800004
SG0_ECRL
00000000 00000000
0xB0800006
SG0_FRL
00000000 00000000
0xB0800008
SG0_ARL
00000000 00000000
0xB080000A
SG0_AR
00000000 00000000
0xB080000C
SG0_TARL
00000000 00000000
0xB080000E
SG0_TCRLIDRL
00000000 00000000
0xB0800010
reserved
XXXXXXXX
SG0_CR1
00000000
SG0_NRL
00000000
0xB0800012
SG0_DER
00000000 00000000
0xB0800014
SG0_DMAR
00000000 00000000
0xB0800016B0807FFE
reserved
XXXXXXXX XXXXXXXX
0xB0808000
CAN0_CTRLR
XXXXXXXX 000X0001
0xB0808002
CAN0_STATR
XXXXXXXX 00000000
0xB0808004
CAN0_ERRCNT
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 195
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808006
CAN0_BTR
X0100011 00000001
0xB0808008
CAN0_INTR
00000000 00000000
0xB080800A
CAN0_TESTR
XXXXXXXX 000000XX
0xB080800C
CAN0_BRPER
XXXXXXXX XXXX0000
0xB080800E
reserved
XXXXXXXX XXXXXXXX
0xB0808010
CAN0_IF1CREQ
0XXXXXXX 00000001
0xB0808012
CAN0_IF1CMSK
XXXXXXXX 00000000
0xB0808014
CAN0_IF1MSK1
11111111 11111111
0xB0808016
CAN0_IF1MSK2
11X11111 11111111
0xB0808018
CAN0_IF1ARB1
00000000 00000000
0xB080801A
CAN0_IF1ARB2
00000000 00000000
0xB080801C
CAN0_IF1MCTR
00000000 0XXX0000
0xB080801E
reserved
XXXXXXXX XXXXXXXX
0xB0808020
CAN0_IF1DTA1
00000000 00000000
0xB0808022
CAN0_IF1DTA2
00000000 00000000
0xB0808024
CAN0_IF1DTB1
00000000 00000000
0xB0808026
CAN0_IF1DTB2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 196
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808028B080803E
reserved
XXXXXXXX XXXXXXXX
0xB0808040
CAN0_IF2CREQ
0XXXXXXX 00000001
0xB0808042
CAN0_IF2CMSK
XXXXXXXX 00000000
0xB0808044
CAN0_IF2MSK1
11111111 11111111
0xB0808046
CAN0_IF2MSK2
11X11111 11111111
0xB0808048
CAN0_IF2ARB1
00000000 00000000
0xB080804A
CAN0_IF2ARB2
00000000 00000000
0xB080804C
CAN0_IF2MCTR
00000000 00000000
0xB080804E
reserved
XXXXXXXX XXXXXXXX
0xB0808050
CAN0_IF2DTA1
00000000 00000000
0xB0808052
CAN0_IF2DTA2
00000000 00000000
0xB0808054
CAN0_IF2DTB1
00000000 00000000
0xB0808056
CAN0_IF2DTB2
00000000 00000000
0xB0808058B080807E
reserved
XXXXXXXX XXXXXXXX
0xB0808080
CAN0_TREQR1
00000000 00000000
0xB0808082
CAN0_TREQR2
00000000 00000000
0xB0808084
CAN0_TREQR3
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 197
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808086
CAN0_TREQR4
00000000 00000000
0xB0808088B080808E
reserved
XXXXXXXX XXXXXXXX
0xB0808090
CAN0_NEWDT1
00000000 00000000
0xB0808092
CAN0_NEWDT2
00000000 00000000
0xB0808094
CAN0_NEWDT3
00000000 00000000
0xB0808096
CAN0_NEWDT4
00000000 00000000
0xB0808098B080809E
reserved
XXXXXXXX XXXXXXXX
0xB08080A0
CAN0_INTPND1
00000000 00000000
0xB08080A2
CAN0_INTPND2
00000000 00000000
0xB08080A4
CAN0_INTPND3
00000000 00000000
0xB08080A6
CAN0_INTPND4
00000000 00000000
0xB08080A8B08080AE
reserved
XXXXXXXX XXXXXXXX
0xB08080B0
CAN0_MSGVAL1
00000000 00000000
0xB08080B2
CAN0_MSGVAL2
00000000 00000000
0xB08080B4
CAN0_MSGVAL3
00000000 00000000
0xB08080B6
CAN0_MSGVAL4
00000000 00000000
0xB08080B8B08080CC
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 198
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08080CE
reserved
00000000
CAN0_COER
XXXXXXX0
0xB08080D0
CAN0_DEBUG
XXXXXXXX 00000000
0xB08080D2B08083FE
reserved
XXXXXXXX XXXXXXXX
0xB0808400
CAN1_CTRLR
XXXXXXXX 000X0001
0xB0808402
CAN1_STATR
XXXXXXXX 00000000
0xB0808404
CAN1_ERRCNT
00000000 00000000
0xB0808406
CAN1_BTR
X0100011 00000001
0xB0808408
CAN1_INTR
00000000 00000000
0xB080840A
CAN1_TESTR
XXXXXXXX 000000XX
0xB080840C
CAN1_BRPER
XXXXXXXX XXXX0000
0xB080840E
reserved
XXXXXXXX XXXXXXXX
0xB0808410
CAN1_IF1CREQ
0XXXXXXX 00000001
0xB0808412
CAN1_IF1CMSK
XXXXXXXX 00000000
0xB0808414
CAN1_IF1MSK1
11111111 11111111
0xB0808416
CAN1_IF1MSK2
11X11111 11111111
0xB0808418
CAN1_IF1ARB1
00000000 00000000
0xB080841A
CAN1_IF1ARB2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 199
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB080841C
CAN1_IF1MCTR
00000000 0XXX0000
0xB080841E
reserved
00000000 00000000
0xB0808420
CAN1_IF1DTA1
00000000 00000000
0xB0808422
CAN1_IF1DTA2
00000000 00000000
0xB0808424
CAN1_IF1DTB1
00000000 00000000
0xB0808426
CAN1_IF1DTB2
00000000 00000000
0xB0808428B080843E
reserved
XXXXXXXX XXXXXXXX
0xB0808440
CAN1_IF2CREQ
0XXXXXXX 00000001
0xB0808442
CAN1_IF2CMSK
XXXXXXXX 00000000
0xB0808444
CAN1_IF2MSK1
11111111 11111111
0xB0808446
CAN1_IF2MSK2
11X11111 11111111
0xB0808448
CAN1_IF2ARB1
00000000 00000000
0xB080844A
CAN1_IF2ARB2
00000000 00000000
0xB080844C
CAN1_IF2MCTR
00000000 00000000
0xB080844E
reserved
XXXXXXXX XXXXXXXX
0xB0808450
CAN1_IF2DTA1
00000000 00000000
0xB0808452
CAN1_IF2DTA2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 200
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808454
CAN1_IF2DTB1
00000000 00000000
0xB0808456
CAN1_IF2DTB2
00000000 00000000
0xB0808458B080847E
reserved
XXXXXXXX XXXXXXXX
0xB0808480
CAN1_TREQR1
00000000 00000000
0xB0808482
CAN1_TREQR2
00000000 00000000
0xB0808484
CAN1_TREQR3
00000000 00000000
0xB0808486
CAN1_TREQR4
00000000 00000000
0xB0808488B080848E
reserved
XXXXXXXX XXXXXXXX
0xB0808490
CAN1_NEWDT1
00000000 00000000
0xB0808492
CAN1_NEWDT2
00000000 00000000
0xB0808494
CAN1_NEWDT3
00000000 00000000
0xB0808496
CAN1_NEWDT4
00000000 00000000
0xB0808498B080849E
reserved
XXXXXXXX XXXXXXXX
0xB08084A0
CAN1_INTPND1
00000000 00000000
0xB08084A2
CAN1_INTPND2
00000000 00000000
0xB08084A4
CAN1_INTPND3
00000000 00000000
0xB08084A6
CAN1_INTPND4
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 201
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08084A8B08084AE
reserved
XXXXXXXX XXXXXXXX
0xB08084B0
CAN1_MSGVAL1
00000000 00000000
0xB08084B2
CAN1_MSGVAL2
00000000 00000000
0xB08084B4
CAN1_MSGVAL3
00000000 00000000
0xB08084B6
CAN1_MSGVAL4
00000000 00000000
0xB08084B8B08084CC
reserved
XXXXXXXX XXXXXXXX
0xB08084CE
reserved
00000000
CAN1_COER
XXXXXXX0
0xB08084D0
CAN1_DEBUG
XXXXXXXX 00000000
0xB08084D2B08087FE
reserved
XXXXXXXX XXXXXXXX
0xB0808800
CAN2_CTRLR
XXXXXXXX 000X0001
0xB0808802
CAN2_STATR
XXXXXXXX 00000000
0xB0808804
CAN2_ERRCNT
00000000 00000000
0xB0808806
CAN2_BTR
X0100011 00000001
0xB0808808
CAN2_INTR
00000000 00000000
0xB080880A
CAN2_TESTR
XXXXXXXX 000000XX
0xB080880C
CAN2_BRPER
XXXXXXXX XXXX0000
0xB080880E
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 202
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808810
CAN2_IF1CREQ
0XXXXXXX 00000001
0xB0808812
CAN2_IF1CMSK
XXXXXXXX 00000000
0xB0808814
CAN2_IF1MSK1
11111111 11111111
0xB0808816
CAN2_IF1MSK2
11X11111 11111111
0xB0808818
CAN2_IF1ARB1
00000000 00000000
0xB080881A
CAN2_IF1ARB2
00000000 00000000
0xB080881C
CAN2_IF1MCTR
00000000 0XXX0000
0xB080881E
reserved
XXXXXXXX XXXXXXXX
0xB0808820
CAN2_IF1DTA1
00000000 00000000
0xB0808822
CAN2_IF1DTA2
00000000 00000000
0xB0808824
CAN2_IF1DTB1
00000000 00000000
0xB0808826
CAN2_IF1DTB2
00000000 00000000
0xB0808828B080883E
reserved
XXXXXXXX XXXXXXXX
0xB0808840
CAN2_IF2CREQ
0XXXXXXX 00000001
0xB0808842
CAN2_IF2CMSK
XXXXXXXX 00000000
0xB0808844
CAN2_IF2MSK1
11111111 11111111
0xB0808846
CAN2_IF2MSK2
11X11111 11111111
Document Number: DS707-00002-4v1-E
Page 203
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808848
CAN2_IF2ARB1
00000000 00000000
0xB080884A
CAN2_IF2ARB2
00000000 00000000
0xB080884C
CAN2_IF2MCTR
00000000 00000000
0xB080884E
reserved
XXXXXXXX XXXXXXXX
0xB0808850
CAN2_IF2DTA1
00000000 00000000
0xB0808852
CAN2_IF2DTA2
00000000 00000000
0xB0808854
CAN2_IF2DTB1
00000000 00000000
0xB0808856
CAN2_IF2DTB2
00000000 00000000
0xB0808858B080887E
reserved
XXXXXXXX XXXXXXXX
0xB0808880
CAN2_TREQR1
00000000 00000000
0xB0808882
CAN2_TREQR2
00000000 00000000
0xB0808884
CAN2_TREQR3
00000000 00000000
0xB0808886
CAN2_TREQR4
00000000 00000000
0xB0808888B080888E
reserved
XXXXXXXX XXXXXXXX
0xB0808890
CAN2_NEWDT1
00000000 00000000
0xB0808892
CAN2_NEWDT2
00000000 00000000
0xB0808894
CAN2_NEWDT3
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 204
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0808896
CAN2_NEWDT4
00000000 00000000
0xB0808898B080889E
reserved
XXXXXXXX XXXXXXXX
0xB08088A0
CAN2_INTPND1
00000000 00000000
0xB08088A2
CAN2_INTPND2
00000000 00000000
0xB08088A4
CAN2_INTPND3
00000000 00000000
0xB08088A6
CAN2_INTPND4
00000000 00000000
0xB08088A8B08088AE
reserved
XXXXXXXX XXXXXXXX
0xB08088B0
CAN2_MSGVAL1
00000000 00000000
0xB08088B2
CAN2_MSGVAL2
00000000 00000000
0xB08088B4
CAN2_MSGVAL3
00000000 00000000
0xB08088B6
CAN2_MSGVAL4
00000000 00000000
0xB08088B8B08088CC
reserved
XXXXXXXX XXXXXXXX
0xB08088CE
CAN2_COER
XXXXXXX0
reserved
00000000
0xB08088D0
CAN2_DEBUG
XXXXXXXX 00000000
0xB08088D2B0817FFE
reserved
XXXXXXXX XXXXXXXX
0xB0818000
FRT16_TCDT
00000000 00000000
0xB0818002
FRT16_CPCLRB
11111111 11111111
Document Number: DS707-00002-4v1-E
Page 205
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0818004
FRT16_CPCLR
11111111 11111111
0xB0818006
FRT16_TCCS
00000000 00000000
0xB0818008
FRT16_TSTPTCLK
01000000 00000000
0xB081800A
FRT16_ETCCS
00000000 00000000
0xB081800C
FRT16_CIMSZIMS
00000000 00000000
0xB081800E
reserved
XXXXXXXX
FRT16_DMACFG
00000000
0xB0818010B08183FE
reserved
XXXXXXXX XXXXXXXX
0xB0818400
FRT17_TCDT
00000000 00000000
0xB0818402
FRT17_CPCLRB
11111111 11111111
0xB0818404
FRT17_CPCLR
11111111 11111111
0xB0818406
FRT17_TCCS
00000000 00000000
0xB0818408
FRT17_TSTPTCLK
01000000 00000000
0xB081840A
FRT17_ETCCS
00000000 00000000
0xB081840C
FRT17_CIMSZIMS
00000000 00000000
0xB081840E
reserved
XXXXXXXX
FRT17_DMACFG
00000000
0xB0818410B08187FE
reserved
XXXXXXXX XXXXXXXX
0xB0818800
FRT18_TCDT
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 206
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0818802
FRT18_CPCLRB
11111111 11111111
0xB0818804
FRT18_CPCLR
11111111 11111111
0xB0818806
FRT18_TCCS
00000000 00000000
0xB0818808
FRT18_TSTPTCLK
01000000 00000000
0xB081880A
FRT18_ETCCS
00000000 00000000
0xB081880C
FRT18_CIMSZIMS
00000000 00000000
0xB081880E
reserved
XXXXXXXX
FRT18_DMACFG
00000000
0xB0818810B0818BFE
reserved
XXXXXXXX XXXXXXXX
0xB0818C00
FRT19_TCDT
00000000 00000000
0xB0818C02
FRT19_CPCLRB
11111111 11111111
0xB0818C04
FRT19_CPCLR
11111111 11111111
0xB0818C06
FRT19_TCCS
00000000 00000000
0xB0818C08
FRT19_TSTPTCLK
01000000 00000000
0xB0818C0A
FRT19_ETCCS
00000000 00000000
0xB0818C0C
FRT19_CIMSZIMS
00000000 00000000
0xB0818C0E
0xB0818C10B08207FE
Document Number: DS707-00002-4v1-E
reserved
XXXXXXXX
FRT19_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
Page 207
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0820800
ICU18_IPC0
00000000 00000000
0xB0820802
ICU18_IPC1
00000000 00000000
0xB0820804
ICU18_ICC01
00000000 00000000
0xB0820806
ICU18_ICEICS01
00000000 00000000
0xB0820808
ICU18_DEBUG01
00000000
ICU18_DMACFG01
00000000
0xB082080AB0820BFE
reserved
XXXXXXXX XXXXXXXX
0xB0820C00
ICU19_IPC0
00000000 00000000
0xB0820C02
ICU19_IPC1
00000000 00000000
0xB0820C04
ICU19_ICC01
00000000 00000000
0xB0820C06
ICU19_ICEICS01
00000000 00000000
0xB0820C08
ICU19_DEBUG01
00000000
ICU19_DMACFG01
00000000
0xB0820C0AB0827FFE
reserved
XXXXXXXX XXXXXXXX
0xB0828000
OCU16_OCCP0
00000000 00000000
0xB0828002
OCU16_OCCP1
00000000 00000000
0xB0828004
OCU16_OCCPB0
00000000 00000000
0xB0828006
OCU16_OCCPB1
00000000 00000000
0xB0828008
OCU16_OCCPBD0
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 208
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB082800A
OCU16_OCCPBD1
00000000 00000000
0xB082800C
OCU16_OCS01
00000000 00000000
0xB082800E
OCU16_OCSC01
00000000 00000000
0xB0828010
OCU16_OCSS01
00000000 00000000
0xB0828012
reserved
XXXXXXXX
OCU16_OSR01
00000000
0xB0828014
reserved
XXXXXXXX
OCU16_OSCR01
00000000
0xB0828016
OCU16_EOCS01
00000000 00000000
0xB0828018
OCU16_EOCSSH01
00000000
reserved
XXXXXXXX
0xB082801A
OCU16_EOCSCH01
00000000
reserved
XXXXXXXX
0xB082801C
OCU16_DEBUG01
00000000
OCU16_DMACFG01
00000000
0xB082801E
OCU16_OCMCR01
00000000
reserved
XXXXXXXX
0xB0828020B08283FE
reserved
XXXXXXXX XXXXXXXX
0xB0828400
OCU17_OCCP0
00000000 00000000
0xB0828402
OCU17_OCCP1
00000000 00000000
0xB0828404
OCU17_OCCPB0
00000000 00000000
0xB0828406
OCU17_OCCPB1
00000000 00000000
0xB0828408
OCU17_OCCPBD0
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 209
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB082840A
OCU17_OCCPBD1
00000000 00000000
0xB082840C
OCU17_OCS01
00000000 00000000
0xB082840E
OCU17_OCSC01
00000000 00000000
0xB0828410
OCU17_OCSS01
00000000 00000000
0xB0828412
reserved
XXXXXXXX
OCU17_OSR01
00000000
0xB0828414
reserved
XXXXXXXX
OCU17_OSCR01
00000000
0xB0828416
OCU17_EOCS01
00000000 00000000
0xB0828418
OCU17_EOCSSH01
00000000
reserved
XXXXXXXX
0xB082841A
OCU17_EOCSCH01
00000000
reserved
XXXXXXXX
0xB082841C
OCU17_DEBUG01
00000000
OCU17_DMACFG01
00000000
0xB082841E
OCU17_OCMCR01
00000000
reserved
XXXXXXXX
0xB0828420B0837FFE
reserved
XXXXXXXX XXXXXXXX
0xB0838000
USART6_SCR
00000000
USART6_SMR
00000000
0xB0838002
USART6_SCSR
00000000
USART6_SMSR
00000000
0xB0838004
USART6_SCCR
00000000
reserved
XXXXXXXX
0xB0838006
USART6_SSR
00001000
USART6_TDR
00000000
0xB0838008
USART6_SSSR
00000000
USART6_RDR
00000000
Document Number: DS707-00002-4v1-E
Page 210
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB083800A
USART6_SSCR
00000000
reserved
XXXXXXXX
0xB083800C
USART6_ESCR
00000100
USART6_ECCR
000000XX
0xB083800E
USART6_ESCSR
00000000
USART6_ECCSR
00000000
0xB0838010
USART6_ESCCR
00000000
USART6_ECCCR
00000000
0xB0838012
USART6_EIER
00000000
USART6_ESIR
000010X0
0xB0838014
USART6_EIESR
00000000
USART6_ESISR
00000000
0xB0838016
USART6_EIECR
00000000
USART6_ESICR
00000000
0xB0838018
USART6_EFERH
00000000
USART6_EFERL
00000000
0xB083801A
USART6_TFCR
00000000
USART6_RFCR
00000000
0xB083801C
USART6_TFCSR
00000000
USART6_RFCSR
00000000
0xB083801E
USART6_TFCCR
00000000
USART6_RFCCR
00000000
0xB0838020
USART6_TFSR
00000000
USART6_RFSR
00000000
0xB0838022
USART6_ESR
00000000
USART6_CSCR
00000000
0xB0838024
reserved
XXXXXXXX
USART6_CSCSR
00000000
0xB0838026
USART6_ESCLR
00000000
USART6_CSCCR
00000000
0xB0838028
USART6_BGRLM
00000000
USART6_BGRLL
00000000
0xB083802A
reserved
XXXXXXXX
USART6_BGRLH
00000000
Document Number: DS707-00002-4v1-E
Page 211
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB083802C
USART6_BGRM
00000000
USART6_BGRL
00000000
0xB083802E
reserved
XXXXXXXX
USART6_BGRH
00000000
0xB0838030
USART6_SRXDR
00000000
USART6_STXDR
00000000
0xB0838032
USART6_SRXDSR
00000000
USART6_STXDSR
00000000
0xB0838034
USART6_SRXDCR
00000000
USART6_STXDCR
00000000
0xB0838036
read0
00000000
read0
00000000
0xB0838038
reserved
XXXXXXXX
read0
00000000
0xB083803A
reserved
XXXXXXXX
USART6_FIDR
00000000
0xB083803C
reserved
XXXXXXXX
USART6_DEBUG
00000000
0xB083803EB0847FFE
reserved
XXXXXXXX XXXXXXXX
0xB0848000
PPG64_PCN
00000000 00000000
0xB0848002
PPG64_SWTRIG
00000000
PPG64_IRQCLR
00000000
0xB0848004
PPG64_CNTEN
00000000
PPG64_OE
00000000
0xB0848006
PPG64_RMPCFG
00000000
PPG64_OPTMSK
00000000
0xB0848008
PPG64_TRIGCLR
00000000
PPG64_STRD
00000000
0xB084800A
PPG64_EPCN1
00000000 00000000
0xB084800C
PPG64_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 212
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084800E
PPG64_GCN3
00000000
PPG64_GCN1
00000000
0xB0848010
PPG64_GCN5
00000000
PPG64_GCN4
00000110
0xB0848012
PPG64_PCSR
XXXXXXXX XXXXXXXX
0xB0848014
PPG64_PDUT
XXXXXXXX XXXXXXXX
0xB0848016
PPG64_PTMR
11111111 11111111
0xB0848018
PPG64_PSDR
00000000 00000000
0xB084801A
PPG64_PTPC
00000000 00000000
0xB084801C
PPG64_PEDR
00000000 00000000
0xB084801E
PPG64_DEBUG
00000000
PPG64_DMACFG
00000000
0xB0848020B08483FE
reserved
XXXXXXXX XXXXXXXX
0xB0848400
PPG65_PCN
00000000 00000000
0xB0848402
PPG65_SWTRIG
00000000
PPG65_IRQCLR
00000000
0xB0848404
PPG65_CNTEN
00000000
PPG65_OE
00000000
0xB0848406
PPG65_RMPCFG
00000000
PPG65_OPTMSK
00000000
0xB0848408
PPG65_TRIGCLR
00000000
PPG65_STRD
00000000
0xB084840A
PPG65_EPCN1
00000000 00000000
0xB084840C
PPG65_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 213
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084840E
PPG65_GCN3
00000000
PPG65_GCN1
00000000
0xB0848410
PPG65_GCN5
00000000
PPG65_GCN4
00000110
0xB0848412
PPG65_PCSR
XXXXXXXX XXXXXXXX
0xB0848414
PPG65_PDUT
XXXXXXXX XXXXXXXX
0xB0848416
PPG65_PTMR
11111111 11111111
0xB0848418
PPG65_PSDR
00000000 00000000
0xB084841A
PPG65_PTPC
00000000 00000000
0xB084841C
PPG65_PEDR
00000000 00000000
0xB084841E
PPG65_DEBUG
00000000
PPG65_DMACFG
00000000
0xB0848420B08487FE
reserved
XXXXXXXX XXXXXXXX
0xB0848800
PPG66_PCN
00000000 00000000
0xB0848802
PPG66_SWTRIG
00000000
PPG66_IRQCLR
00000000
0xB0848804
PPG66_CNTEN
00000000
PPG66_OE
00000000
0xB0848806
PPG66_RMPCFG
00000000
PPG66_OPTMSK
00000000
0xB0848808
PPG66_TRIGCLR
00000000
PPG66_STRD
00000000
0xB084880A
PPG66_EPCN1
00000000 00000000
0xB084880C
PPG66_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 214
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084880E
PPG66_GCN3
00000000
PPG66_GCN1
00000000
0xB0848810
PPG66_GCN5
00000000
PPG66_GCN4
00000110
0xB0848812
PPG66_PCSR
XXXXXXXX XXXXXXXX
0xB0848814
PPG66_PDUT
XXXXXXXX XXXXXXXX
0xB0848816
PPG66_PTMR
11111111 11111111
0xB0848818
PPG66_PSDR
00000000 00000000
0xB084881A
PPG66_PTPC
00000000 00000000
0xB084881C
PPG66_PEDR
00000000 00000000
0xB084881E
PPG66_DEBUG
00000000
PPG66_DMACFG
00000000
0xB0848820B0848BFE
reserved
XXXXXXXX XXXXXXXX
0xB0848C00
PPG67_PCN
00000000 00000000
0xB0848C02
PPG67_SWTRIG
00000000
PPG67_IRQCLR
00000000
0xB0848C04
PPG67_CNTEN
00000000
PPG67_OE
00000000
0xB0848C06
PPG67_RMPCFG
00000000
PPG67_OPTMSK
00000000
0xB0848C08
PPG67_TRIGCLR
00000000
PPG67_STRD
00000000
0xB0848C0A
PPG67_EPCN1
00000000 00000000
0xB0848C0C
PPG67_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 215
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0848C0E
PPG67_GCN3
00000000
PPG67_GCN1
00000000
0xB0848C10
PPG67_GCN5
00000000
PPG67_GCN4
00000110
0xB0848C12
PPG67_PCSR
XXXXXXXX XXXXXXXX
0xB0848C14
PPG67_PDUT
XXXXXXXX XXXXXXXX
0xB0848C16
PPG67_PTMR
11111111 11111111
0xB0848C18
PPG67_PSDR
00000000 00000000
0xB0848C1A
PPG67_PTPC
00000000 00000000
0xB0848C1C
PPG67_PEDR
00000000 00000000
0xB0848C1E
PPG67_DEBUG
00000000
PPG67_DMACFG
00000000
0xB0848C20B0848FFE
reserved
XXXXXXXX XXXXXXXX
0xB0849000
PPG68_PCN
00000000 00000000
0xB0849002
PPG68_SWTRIG
00000000
PPG68_IRQCLR
00000000
0xB0849004
PPG68_CNTEN
00000000
PPG68_OE
00000000
0xB0849006
PPG68_RMPCFG
00000000
PPG68_OPTMSK
00000000
0xB0849008
PPG68_TRIGCLR
00000000
PPG68_STRD
00000000
0xB084900A
PPG68_EPCN1
00000000 00000000
0xB084900C
PPG68_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 216
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084900E
PPG68_GCN3
00000000
PPG68_GCN1
00000000
0xB0849010
PPG68_GCN5
00000000
PPG68_GCN4
00000110
0xB0849012
PPG68_PCSR
XXXXXXXX XXXXXXXX
0xB0849014
PPG68_PDUT
XXXXXXXX XXXXXXXX
0xB0849016
PPG68_PTMR
11111111 11111111
0xB0849018
PPG68_PSDR
00000000 00000000
0xB084901A
PPG68_PTPC
00000000 00000000
0xB084901C
PPG68_PEDR
00000000 00000000
0xB084901E
PPG68_DEBUG
00000000
PPG68_DMACFG
00000000
0xB0849020B08493FE
reserved
XXXXXXXX XXXXXXXX
0xB0849400
PPG69_PCN
00000000 00000000
0xB0849402
PPG69_SWTRIG
00000000
PPG69_IRQCLR
00000000
0xB0849404
PPG69_CNTEN
00000000
PPG69_OE
00000000
0xB0849406
PPG69_RMPCFG
00000000
PPG69_OPTMSK
00000000
0xB0849408
PPG69_TRIGCLR
00000000
PPG69_STRD
00000000
0xB084940A
PPG69_EPCN1
00000000 00000000
0xB084940C
PPG69_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 217
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084940E
PPG69_GCN3
00000000
PPG69_GCN1
00000000
0xB0849410
PPG69_GCN5
00000000
PPG69_GCN4
00000110
0xB0849412
PPG69_PCSR
XXXXXXXX XXXXXXXX
0xB0849414
PPG69_PDUT
XXXXXXXX XXXXXXXX
0xB0849416
PPG69_PTMR
11111111 11111111
0xB0849418
PPG69_PSDR
00000000 00000000
0xB084941A
PPG69_PTPC
00000000 00000000
0xB084941C
PPG69_PEDR
00000000 00000000
0xB084941E
PPG69_DEBUG
00000000
PPG69_DMACFG
00000000
0xB0849420B08497FE
reserved
XXXXXXXX XXXXXXXX
0xB0849800
PPG70_PCN
00000000 00000000
0xB0849802
PPG70_SWTRIG
00000000
PPG70_IRQCLR
00000000
0xB0849804
PPG70_CNTEN
00000000
PPG70_OE
00000000
0xB0849806
PPG70_RMPCFG
00000000
PPG70_OPTMSK
00000000
0xB0849808
PPG70_TRIGCLR
00000000
PPG70_STRD
00000000
0xB084980A
PPG70_EPCN1
00000000 00000000
0xB084980C
PPG70_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 218
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB084980E
PPG70_GCN3
00000000
PPG70_GCN1
00000000
0xB0849810
PPG70_GCN5
00000000
PPG70_GCN4
00000110
0xB0849812
PPG70_PCSR
XXXXXXXX XXXXXXXX
0xB0849814
PPG70_PDUT
XXXXXXXX XXXXXXXX
0xB0849816
PPG70_PTMR
11111111 11111111
0xB0849818
PPG70_PSDR
00000000 00000000
0xB084981A
PPG70_PTPC
00000000 00000000
0xB084981C
PPG70_PEDR
00000000 00000000
0xB084981E
PPG70_DEBUG
00000000
PPG70_DMACFG
00000000
0xB0849820B0849BFE
reserved
XXXXXXXX XXXXXXXX
0xB0849C00
PPG71_PCN
00000000 00000000
0xB0849C02
PPG71_SWTRIG
00000000
PPG71_IRQCLR
00000000
0xB0849C04
PPG71_CNTEN
00000000
PPG71_OE
00000000
0xB0849C06
PPG71_RMPCFG
00000000
PPG71_OPTMSK
00000000
0xB0849C08
PPG71_TRIGCLR
00000000
PPG71_STRD
00000000
0xB0849C0A
PPG71_EPCN1
00000000 00000000
0xB0849C0C
PPG71_EPCN2
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 219
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB0849C0E
PPG71_GCN3
00000000
PPG71_GCN1
00000000
0xB0849C10
PPG71_GCN5
00000000
PPG71_GCN4
00000110
0xB0849C12
PPG71_PCSR
XXXXXXXX XXXXXXXX
0xB0849C14
PPG71_PDUT
XXXXXXXX XXXXXXXX
0xB0849C16
PPG71_PTMR
11111111 11111111
0xB0849C18
PPG71_PSDR
00000000 00000000
0xB0849C1A
PPG71_PTPC
00000000 00000000
0xB0849C1C
PPG71_PEDR
00000000 00000000
0xB0849C1E
0xB0849C20B0857FFE
0xB0858000
0xB0858002B08583FE
0xB0858400
0xB0858402B085BFFE
0xB085C000
PPG71_DEBUG
00000000
PPG71_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP16_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP17_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGLC1_GCNR
00000000
0xB085C002B08EFFFE
reserved
XXXXXXXX XXXXXXXX
0xB08F0000
BECU1_CTRL
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 220
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08F0002
BECU1_CTRH
00000000 00000000
0xB08F0004
BECU1_ADDRL
00000000 00000000
0xB08F0006
BECU1_ADDRH
00000000 00000000
0xB08F0008
BECU1_DATALL
00000000 00000000
0xB08F000A
BECU1_DATALH
00000000 00000000
0xB08F000C
BECU1_DATAHL
00000000 00000000
0xB08F000E
BECU1_DATAHH
00000000 00000000
0xB08F0010
BECU1_MASTERID
00000000 00000000
0xB08F0012
BECU1_MIDL
XXXXXXXX XXXXXXXX
0xB08F0014
BECU1_MIDH
XXXXXXXX XXXXXXXX
0xB08F0016
reserved
00000000 00000000
0xB08F0018
BECU1_NMIEN
XXXXXXXX 00000001
0xB08F001AB08F83FE
reserved
XXXXXXXX XXXXXXXX
0xB08F8400
RICFG1_CAN0RX
00000000 00000000
0xB08F8402B08F841E
reserved
XXXXXXXX 00000000
0xB08F8420
RICFG1_CAN1RX
00000000 00000000
0xB08F8422B08F843E
reserved
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 221
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08F8440
RICFG1_CAN2RX
00000000 00000000
0xB08F8442B08F8BFE
reserved
XXXXXXXX 00000000
0xB08F8C00
RICFG1_FRT16TEXT
00000000 00000000
0xB08F8C02B08F8C1E
reserved
XXXXXXXX 00000000
0xB08F8C20
RICFG1_FRT17TEXT
00000000 00000000
0xB08F8C22B08F8C3E
reserved
XXXXXXXX 00000000
0xB08F8C40
RICFG1_FRT18TEXT
00000000 00000000
0xB08F8C42B08F8C5E
reserved
XXXXXXXX 00000000
0xB08F8C60
RICFG1_FRT19TEXT
00000000 00000000
0xB08F8C62B08F903E
reserved
XXXXXXXX 00000000
0xB08F9040
RICFG1_ICU18IN0
00000000 XXXXXXXX
0xB08F9042
RICFG1_ICU18IN1
00000000 XXXXXXXX
0xB08F9044
RICFG1_ICU18FRTSEL
XXXXXXXX 00000000
0xB08F9046B08F905E
reserved
XXXXXXXX 00000000
0xB08F9060
RICFG1_ICU19IN0
00000000 XXXXXXXX
0xB08F9062
RICFG1_ICU19IN1
00000000 XXXXXXXX
0xB08F9064
RICFG1_ICU19FRTSEL
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 222
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08F9066B08F93FE
reserved
XXXXXXXX 00000000
0xB08F9400
RICFG1_OCU16OTD0GATE
XXXXXXXX 00000000
0xB08F9402
RICFG1_OCU16OTD0GM
XXXXXXXX 00000000
0xB08F9404
RICFG1_OCU16OTD1GATE
XXXXXXXX 00000000
0xB08F9406
RICFG1_OCU16OTD1GM
XXXXXXXX 00000000
0xB08F9408B08F941E
reserved
XXXXXXXX 00000000
0xB08F9420
RICFG1_OCU17CMP0EXT
XXXXXXXX 00000000
0xB08F9422
RICFG1_OCU17FRTSEL
XXXXXXXX 00000000
0xB08F9424
RICFG1_OCU17OTD0GATE
XXXXXXXX 00000000
0xB08F9426
RICFG1_OCU17OTD0GM
XXXXXXXX 00000000
0xB08F9428
RICFG1_OCU17OTD1GATE
XXXXXXXX 00000000
0xB08F942A
RICFG1_OCU17OTD1GM
XXXXXXXX 00000000
0xB08F942CB08F9BFE
reserved
XXXXXXXX 00000000
0xB08F9C00
RICFG1_USART6SCKI
00000000 XXXXXXXX
0xB08F9C02
RICFG1_USART6SIN
00000000 XXXXXXXX
0xB08F9C04B08FA3FE
reserved
XXXXXXXX 00000000
0xB08FA400
RICFG1_PPG64PPGAGATE
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 223
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08FA402
RICFG1_PPG64PPGAGM
XXXXXXXX 00000000
0xB08FA404
RICFG1_PPG64PPGBGATE
XXXXXXXX 00000000
0xB08FA406
RICFG1_PPG64PPGBGM
XXXXXXXX 00000000
0xB08FA408B08FA41E
reserved
XXXXXXXX 00000000
0xB08FA420
RICFG1_PPG65PPGAGATE
XXXXXXXX 00000000
0xB08FA422
RICFG1_PPG65PPGAGM
XXXXXXXX 00000000
0xB08FA424
RICFG1_PPG65PPGBGATE
XXXXXXXX 00000000
0xB08FA426
RICFG1_PPG65PPGBGM
XXXXXXXX 00000000
0xB08FA428B08FA43E
reserved
XXXXXXXX 00000000
0xB08FA440
RICFG1_PPG66PPGAGATE
XXXXXXXX 00000000
0xB08FA442
RICFG1_PPG66PPGAGM
XXXXXXXX 00000000
0xB08FA444
RICFG1_PPG66PPGBGATE
XXXXXXXX 00000000
0xB08FA446
RICFG1_PPG66PPGBGM
XXXXXXXX 00000000
0xB08FA448B08FA45E
reserved
XXXXXXXX 00000000
0xB08FA460
RICFG1_PPG67PPGAGATE
XXXXXXXX 00000000
0xB08FA462
RICFG1_PPG67PPGAGM
XXXXXXXX 00000000
0xB08FA464
RICFG1_PPG67PPGBGATE
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 224
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08FA466
RICFG1_PPG67PPGBGM
XXXXXXXX 00000000
0xB08FA468B08FA47E
reserved
XXXXXXXX 00000000
0xB08FA480
RICFG1_PPG68PPGAGATE
XXXXXXXX 00000000
0xB08FA482
RICFG1_PPG68PPGAGM
XXXXXXXX 00000000
0xB08FA484
RICFG1_PPG68PPGBGATE
XXXXXXXX 00000000
0xB08FA486
RICFG1_PPG68PPGBGM
XXXXXXXX 00000000
0xB08FA488B08FA49E
reserved
XXXXXXXX 00000000
0xB08FA4A0
RICFG1_PPG69PPGAGATE
XXXXXXXX 00000000
0xB08FA4A2
RICFG1_PPG69PPGAGM
XXXXXXXX 00000000
0xB08FA4A4
RICFG1_PPG69PPGBGATE
XXXXXXXX 00000000
0xB08FA4A6
RICFG1_PPG69PPGBGM
XXXXXXXX 00000000
0xB08FA4A8B08FA4BE
reserved
XXXXXXXX 00000000
0xB08FA4C0
RICFG1_PPG70PPGAGATE
XXXXXXXX 00000000
0xB08FA4C2
RICFG1_PPG70PPGAGM
XXXXXXXX 00000000
0xB08FA4C4
RICFG1_PPG70PPGBGATE
XXXXXXXX 00000000
0xB08FA4C6
RICFG1_PPG70PPGBGM
XXXXXXXX 00000000
0xB08FA4C8B08FA4DE
reserved
XXXXXXXX 00000000
Document Number: DS707-00002-4v1-E
Page 225
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08FA4E0
RICFG1_PPG71PPGAGATE
XXXXXXXX 00000000
0xB08FA4E2
RICFG1_PPG71PPGAGM
XXXXXXXX 00000000
0xB08FA4E4
RICFG1_PPG71PPGBGATE
XXXXXXXX 00000000
0xB08FA4E6
RICFG1_PPG71PPGBGM
XXXXXXXX 00000000
0xB08FA4E8B08FABFE
reserved
XXXXXXXX 00000000
0xB08FAC00
RICFG1_PPGGRP16ETRG0
XXXXXXXX 00000000
0xB08FAC02
RICFG1_PPGGRP16ETRG1
XXXXXXXX 00000000
0xB08FAC04
RICFG1_PPGGRP16ETRG2
XXXXXXXX 00000000
0xB08FAC06
RICFG1_PPGGRP16ETRG3
XXXXXXXX 00000000
0xB08FAC08
RICFG1_PPGGRP16RLTTRG1
XXXXXXXX 00000000
0xB08FAC0AB08FAC1E
reserved
XXXXXXXX XXXXXXXX
0xB08FAC20
RICFG1_PPGGRP17ETRG0
XXXXXXXX 00000000
0xB08FAC22
RICFG1_PPGGRP17ETRG1
XXXXXXXX 00000000
0xB08FAC24
RICFG1_PPGGRP17ETRG2
XXXXXXXX 00000000
0xB08FAC26
RICFG1_PPGGRP17ETRG3
XXXXXXXX 00000000
0xB08FAC28
RICFG1_PPGGRP17RLTTRG1
XXXXXXXX 00000000
0xB08FAC2AB08FFC02
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 226
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08FFC04
BSU1_BTSTL
00000000 00000000
0xB08FFC06
BSU1_BTSTH
00000000 00000000
0xB08FFC08B08FFC0E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC10
BSU1_PEN0L
XXXXXXXX 00000000
0xB08FFC12
reserved
XXXXXXXX XXXXXXXX
0xB08FFC14
BSU1_PEN1L
XXXXXXXX 00000000
0xB08FFC16
reserved
XXXXXXXX XXXXXXXX
0xB08FFC18
BSU1_PEN2L
XXXXXXXX 00000000
0xB08FFC1A
reserved
XXXXXXXX XXXXXXXX
0xB08FFC1C
BSU1_PEN3L
00000000 00000000
0xB08FFC1E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC20
BSU1_PEN4L
00000000 00000000
0xB08FFC22
reserved
XXXXXXXX XXXXXXXX
0xB08FFC24
BSU1_PEN5L
00000000 00000000
0xB08FFC26
reserved
XXXXXXXX XXXXXXXX
0xB08FFC28
BSU1_PEN6L
XXXXXXXX 00000000
0xB08FFC2A
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 227
MB9DF126
MB9DF126B
Table 5-7 Memory layout of PERI1_RBUS registers (Continued)
Offset
+1
+0
0xB08FFC2C
BSU1_PEN7L
XXXXXXXX 00000000
0xB08FFC2E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC30
BSU1_PEN8L
XXXXXXXX 00000000
0xB08FFC32
reserved
XXXXXXXX XXXXXXXX
0xB08FFC34
BSU1_PEN9L
00000000 00000000
0xB08FFC36
BSU1_PEN9H
00000000 00000000
0xB08FFC38
BSU1_PEN10L
00000000 00000000
0xB08FFC3A
BSU1_PEN10H
00000000 00000000
0xB08FFC3C
BSU1_PEN11L
00000000 00000000
0xB08FFC3E
BSU1_PEN11H
XXXXXXXX 00000000
0xB08FFC40B09FFFFE
reserved
XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 228
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A00000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00008
PPU0_PRS3
00000000 00000000 00000000 00000000
PPU0_PRS2
00000000 00000000 00000000 00000000
0xB0A00010
PPU0_PRS5
00000000 00000000 00000000 00000000
PPU0_PRS4
00000000 00000000 00000000 00000000
0xB0A00018
PPU0_PRS7
00000000 00000000 00000000 00000000
PPU0_PRS6
00000000 00000000 00000000 00000000
0xB0A00020
PPU0_PRS9
00000000 00000000 00000000 00000000
PPU0_PRS8
00000000 00000000 00000000 00000000
0xB0A00028
PPU0_PRS11
00000000 00000000 00000000 00000000
PPU0_PRS10
00000000 00000000 00000000 00000000
0xB0A00030
PPU0_PRS13
00000000 00000000 00000000 00000000
PPU0_PRS12
00000000 00000000 00000000 00000000
0xB0A00038B0A00040
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00048
PPU0_PAS3
00000000 00000000 00000000 00000000
PPU0_PAS2
00000000 00000000 00000000 00000000
0xB0A00050
PPU0_PAS5
00000000 00000000 00000000 00000000
PPU0_PAS4
00000000 00000000 00000000 00000000
0xB0A00058
PPU0_PAS7
00000000 00000000 00000000 00000000
PPU0_PAS6
00000000 00000000 00000000 00000000
0xB0A00060
PPU0_PAS9
00000000 00000000 00000000 00000000
PPU0_PAS8
00000000 00000000 00000000 00000000
0xB0A00068
PPU0_PAS11
00000000 00000000 00000000 00000000
PPU0_PAS10
00000000 00000000 00000000 00000000
0xB0A00070
PPU0_PAS13
00000000 00000000 00000000 00000000
PPU0_PAS12
00000000 00000000 00000000 00000000
0xB0A00078
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 229
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A00080
PPU0_GAS1
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00088
PPU0_GAS3
00000000 00000000 00000000 00000000
PPU0_GAS2
00000000 00000000 00000000 00000000
0xB0A00090
PPU0_GAS5
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00098
PPU0_GAS7
00000000 00000000 00000000 00000000
PPU0_GAS6
00000000 00000000 00000000 00000000
0xB0A000A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000A8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000B8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000C8
PPU0_PRC3
00000000 00000000 00000000 00000000
PPU0_PRC2
00000000 00000000 00000000 00000000
0xB0A000D0
PPU0_PRC5
00000000 00000000 00000000 00000000
PPU0_PRC4
00000000 00000000 00000000 00000000
0xB0A000D8
PPU0_PRC7
00000000 00000000 00000000 00000000
PPU0_PRC6
00000000 00000000 00000000 00000000
0xB0A000E0
PPU0_PRC9
00000000 00000000 00000000 00000000
PPU0_PRC8
00000000 00000000 00000000 00000000
0xB0A000E8
PPU0_PRC11
00000000 00000000 00000000 00000000
PPU0_PRC10
00000000 00000000 00000000 00000000
0xB0A000F0
PPU0_PRC13
00000000 00000000 00000000 00000000
PPU0_PRC12
00000000 00000000 00000000 00000000
0xB0A000F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00100
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 230
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A00108
PPU0_PAC3
00000000 00000000 00000000 00000000
PPU0_PAC2
00000000 00000000 00000000 00000000
0xB0A00110
PPU0_PAC5
00000000 00000000 00000000 00000000
PPU0_PAC4
00000000 00000000 00000000 00000000
0xB0A00118
PPU0_PAC7
00000000 00000000 00000000 00000000
PPU0_PAC6
00000000 00000000 00000000 00000000
0xB0A00120
PPU0_PAC9
00000000 00000000 00000000 00000000
PPU0_PAC8
00000000 00000000 00000000 00000000
0xB0A00128
PPU0_PAC11
00000000 00000000 00000000 00000000
PPU0_PAC10
00000000 00000000 00000000 00000000
0xB0A00130
PPU0_PAC13
00000000 00000000 00000000 00000000
PPU0_PAC12
00000000 00000000 00000000 00000000
0xB0A00138
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00140
PPU0_GAC1
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00148
PPU0_GAC3
00000000 00000000 00000000 00000000
PPU0_GAC2
00000000 00000000 00000000 00000000
0xB0A00150
PPU0_GAC5
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00158
PPU0_GAC7
00000000 00000000 00000000 00000000
PPU0_GAC6
00000000 00000000 00000000 00000000
0xB0A00160
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00168
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00170
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00178
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00180
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00188
PPU0_PR3
00000000 00000000 00000000 00000000
PPU0_PR2
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 231
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A00190
PPU0_PR5
00000000 00000000 00000000 00000000
PPU0_PR4
00000000 00000000 00000000 00000000
0xB0A00198
PPU0_PR7
00000000 00000000 00000000 00000000
PPU0_PR6
00000000 00000000 00000000 00000000
0xB0A001A0
PPU0_PR9
00000000 00000000 00000000 00000000
PPU0_PR8
00000000 00000000 00000000 00000000
0xB0A001A8
PPU0_PR11
00000000 00000000 00000000 00000000
PPU0_PR10
00000000 00000000 00000000 00000000
0xB0A001B0
PPU0_PR13
00000000 00000000 00000000 00000000
PPU0_PR12
00000000 00000000 00000000 00000000
0xB0A001B8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A001C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A001C8
PPU0_PA3
00000000 00000000 00000000 00000000
PPU0_PA2
00000000 00000000 00000000 00000000
0xB0A001D0
PPU0_PA5
00000000 00000000 00000000 00000000
PPU0_PA4
00000000 00000000 00000000 00000000
0xB0A001D8
PPU0_PA7
00000000 00000000 00000000 00000000
PPU0_PA6
00000000 00000000 00000000 00000000
0xB0A001E0
PPU0_PA9
00000000 00000000 00000000 00000000
PPU0_PA8
00000000 00000000 00000000 00000000
0xB0A001E8
PPU0_PA11
00000000 00000000 00000000 00000000
PPU0_PA10
00000000 00000000 00000000 00000000
0xB0A001F0
PPU0_PA13
00000000 00000000 00000000 00000000
PPU0_PA12
00000000 00000000 00000000 00000000
0xB0A001F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00200
PPU0_GA1
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00208
PPU0_GA3
00000000 00000000 00000000 00000000
PPU0_GA2
00000000 00000000 00000000 00000000
0xB0A00210
PPU0_GA5
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 232
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A00218
PPU0_GA7
00000000 00000000 00000000 00000000
PPU0_GA6
00000000 00000000 00000000 00000000
0xB0A00220
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00228
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00230
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00238
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00240
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PPU0_UNLOCK
00000000 00000000 00000000 00000000
0xB0A00248
PPU0_CTR
XXXXXXXX 00000001 00000000 00000000
PPU0_ST
XXXXXXXX XXXXXXXX 00000001 00000001
0xB0A00250B0A07FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08000
GPIO_POSR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08008
GPIO_POCR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08010
GPIO_DDSR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08018
GPIO_DDCR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08020
GPIO_POSR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08028
GPIO_POCR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08030
GPIO_DDSR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08038
GPIO_DDCR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08040
GPIO_POSR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 233
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
0xB0A08048
GPIO_POCR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08050
GPIO_DDSR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08058
GPIO_DDCR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08060
GPIO_POSR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08068
GPIO_POCR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08070
GPIO_DDSR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08078
GPIO_DDCR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08080
GPIO_POSR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08088
GPIO_POCR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08090
GPIO_DDSR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08098
GPIO_DDCR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080A0
GPIO_POSR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080A8
GPIO_POCR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080B0
GPIO_DDSR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080B8
GPIO_DDCR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080C0
GPIO_POSR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080C8
GPIO_POCR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 234
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A080D0
GPIO_DDSR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080D8
GPIO_DDCR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080E0
GPIO_POSR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080E8
GPIO_POCR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080F0
GPIO_DDSR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A080F8
GPIO_DDCR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08100B0A081F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08200
GPIO_PODR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08208
GPIO_DDR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08210
GPIO_PODR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08218
GPIO_DDR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08220
GPIO_PODR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08228
GPIO_DDR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08230
GPIO_PODR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08238
GPIO_DDR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08240
GPIO_PODR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08248
GPIO_DDR4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 235
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A08250
GPIO_PODR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08258
GPIO_DDR5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08260
GPIO_PODR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08268
GPIO_DDR6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08270
GPIO_PODR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08278
GPIO_DDR7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08280B0A082F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08300
GPIO_PIDR0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08308
GPIO_PIDR1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08310
GPIO_PIDR2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08318
GPIO_PIDR3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08320
GPIO_PIDR4
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08328
GPIO_PIDR5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08330
GPIO_PIDR6
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08338
GPIO_PIDR7
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08340B0A08378
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08380
GPIO_PPER0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 236
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
0xB0A08388
GPIO_PPER1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08390
GPIO_PPER2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08398
GPIO_PPER3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083A0
GPIO_PPER4
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083A8
GPIO_PPER5
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083B0
GPIO_PPER6
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083B8
GPIO_PPER7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083C0B0A0FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000X
+0
0xB0A10000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_TMCSR
00000000 00000000 00000000 00000000
0xB0A10010
RLT0_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10018B0A103F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_TMCSR
00000000 00000000 00000000 00000000
0xB0A10410
RLT1_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10418B0A107F8
0xB0A10800
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000X
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
RLT2_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
Page 237
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0A10808
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT2_TMCSR
00000000 00000000 00000000 00000000
0xB0A10810
RLT2_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT2_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10818B0A10BF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000X
0xB0A10C00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10C08
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_TMCSR
00000000 00000000 00000000 00000000
0xB0A10C10
RLT3_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10C18B0A10FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_TMCSR
00000000 00000000 00000000 00000000
0xB0A11010
RLT4_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11018B0A113F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_TMCSR
00000000 00000000 00000000 00000000
0xB0A11410
RLT5_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11418B0A117F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11800
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT6_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11808
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT6_TMCSR
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 238
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
0xB0A11810
0xB0A11818B0A11BF8
+7
+6
+5
+4
RLT6_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
+2
+1
+0
RLT6_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11C00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11C08
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_TMCSR
00000000 00000000 00000000 00000000
0xB0A11C10
RLT7_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11C18B0A11FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A12008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_TMCSR
00000000 00000000 00000000 00000000
0xB0A12010
RLT8_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12018B0A123F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A12408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_TMCSR
00000000 00000000 00000000 00000000
0xB0A12410
RLT9_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12418B0A1FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A20000
UDC0_ECC1
XXXXXXXX 00000000
UDC0_CC1
00000000 00000000
UDC0_ECC0
XXXXXXXX 00000000
UDC0_CC0
00000000 00000000
0xB0A20008
UDC0_TGL1
00000000 00000000
UDC0_TGL0
00000000 00000000
UDC0_CS1
00000000 00000000
UDC0_CS0
00000000 00000000
0xB0A20010
UDC0_RC
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
UDC0_CR
00000000 00000000 00000000 00000000
Page 239
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
0xB0A20018
0xB0A20020B0AEFFF8
+7
+6
+5
+4
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
+2
reserved
XXXXXXXX XXXXXXXX
+1
+0
UDC0_DBG
XXXXXXXX 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AF0000
BECU3_ADDRH
00000000 00000000
BECU3_ADDRL
00000000 00000000
BECU3_CTRH
00000000 00000000
BECU3_CTRL
00000000 00000000
0xB0AF0008
BECU3_DATAHH
00000000 00000000
BECU3_DATAHL
00000000 00000000
BECU3_DATALH
00000000 00000000
BECU3_DATALL
00000000 00000000
0xB0AF0010
reserved
00000000 00000000
BECU3_MIDH
XXXXXXXX XXXXXXXX
BECU3_MIDL
XXXXXXXX XXXXXXXX
BECU3_MASTERID
00000000 00000000
0xB0AF0018
reserved
00000000 00000000
reserved
00000000 00000000
reserved
00000000 00000000
BECU3_NMIEN
XXXXXXXX 00000001
0xB0AF0020B0AF87F8
0xB0AF8800
0xB0AF8808B0AF8818
0xB0AF8820
0xB0AF8828B0AF8838
0xB0AF8840
0xB0AF8848B0AF8858
0xB0AF8860
0xB0AF8868B0AF8878
0xB0AF8880
0xB0AF8888B0AF8898
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000X
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT0TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT1TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT2TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT3TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT4TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 240
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
0xB0AF88A0
0xB0AF88A8B0AF88B8
0xB0AF88C0
0xB0AF88C8B0AF88D8
0xB0AF88E0
0xB0AF88E8B0AF88F8
0xB0AF8900
0xB0AF8908B0AF8918
0xB0AF8920
0xB0AF8928B0AF8FF8
+7
+6
reserved
XXXXXXXX XXXXXXXX
+5
+4
reserved
XXXXXXXX XXXXXXXX
+3
+2
reserved
XXXXXXXX XXXXXXXX
+1
+0
RICFG3_RLT5TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT6TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT7TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT8TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT9TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AF9000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0AIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0AIN0
00000000 00000000
0xB0AF9008
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0BIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0BIN0
00000000 00000000
0xB0AF9010
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0ZIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0ZIN0
00000000 00000000
0xB0AF9018B0AFFBF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AFFC00
BSU3_BTST
00000000 00000000 00000000 00000000
0xB0AFFC08B0AFFC10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AFFC18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU3_PEN2
00000000 00000000 00000000 00000000
Page 241
MB9DF126
MB9DF126B
Table 5-8 Memory layout of the PERI3_ERBUS registers (Continued)
Offset
0xB0AFFC20
0xB0AFFC28B0AFFFF8
+7
+6
+5
+4
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
+2
+1
+0
BSU3_PEN4
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 242
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers
Offset
+3
+2
+1
0xB0B00000 0xB0B1FFFFF
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B20000
I2S0_RXFDAT0
00000000 00000000 00000000 00000000
0xB0B20004
I2S0_RXFDAT1
00000000 00000000 00000000 00000000
0xB0B20008
I2S0_RXFDAT2
00000000 00000000 00000000 00000000
0xB0B2000C
I2S0_RXFDAT3
00000000 00000000 00000000 00000000
0xB0B20010
I2S0_RXFDAT4
00000000 00000000 00000000 00000000
0xB0B20014
I2S0_RXFDAT5
00000000 00000000 00000000 00000000
0xB0B20018
I2S0_RXFDAT6
00000000 00000000 00000000 00000000
0xB0B2001C
I2S0_RXFDAT7
00000000 00000000 00000000 00000000
0xB0B20020
I2S0_RXFDAT8
00000000 00000000 00000000 00000000
0xB0B20024
I2S0_RXFDAT9
00000000 00000000 00000000 00000000
0xB0B20028
I2S0_RXFDAT10
00000000 00000000 00000000 00000000
0xB0B2002C
I2S0_RXFDAT11
00000000 00000000 00000000 00000000
0xB0B20030
I2S0_RXFDAT12
00000000 00000000 00000000 00000000
0xB0B20034
I2S0_RXFDAT13
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 243
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B20038
I2S0_RXFDAT14
00000000 00000000 00000000 00000000
0xB0B2003C
I2S0_RXFDAT15
00000000 00000000 00000000 00000000
0xB0B20040
I2S0_TXFDAT0
00000000 00000000 00000000 00000000
0xB0B20044
I2S0_TXFDAT1
00000000 00000000 00000000 00000000
0xB0B20048
I2S0_TXFDAT2
00000000 00000000 00000000 00000000
0xB0B2004C
I2S0_TXFDAT3
00000000 00000000 00000000 00000000
0xB0B20050
I2S0_TXFDAT4
00000000 00000000 00000000 00000000
0xB0B20054
I2S0_TXFDAT5
00000000 00000000 00000000 00000000
0xB0B20058
I2S0_TXFDAT6
00000000 00000000 00000000 00000000
0xB0B2005C
I2S0_TXFDAT7
00000000 00000000 00000000 00000000
0xB0B20060
I2S0_TXFDAT8
00000000 00000000 00000000 00000000
0xB0B20064
I2S0_TXFDAT9
00000000 00000000 00000000 00000000
0xB0B20068
I2S0_TXFDAT10
00000000 00000000 00000000 00000000
0xB0B2006C
I2S0_TXFDAT11
00000000 00000000 00000000 00000000
0xB0B20070
I2S0_TXFDAT12
00000000 00000000 00000000 00000000
0xB0B20074
I2S0_TXFDAT13
00000000 00000000 00000000 00000000
0xB0B20078
I2S0_TXFDAT14
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 244
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B2007C
I2S0_TXFDAT15
00000000 00000000 00000000 00000000
0xB0B20080
I2S0_CNTREG
00000000 00000000 00000000 01100000
0xB0B20084
I2S0_MCR0REG
00000000 00000000 00000000 00000000
0xB0B20088
I2S0_MCR1REG
00000000 00000000 00000000 00000000
0xB0B2008C
I2S0_MCR2REG
00000000 00000000 00000000 00000000
0xB0B20090
I2S0_OPRREG
00000000 00000000 00000000 00000000
0xB0B20094
I2S0_SRST
00000000 00000000 00000000 00000000
0xB0B20098
I2S0_INTCNT
01111111 00111111 00000000 00000000
0xB0B2009C
I2S0_STATUS
00000000 00000000 00000000 00000000
0xB0B200A0
I2S0_DMAACT
00000000 00000000 00000000 00000000
0xB0B200A4
I2S0_DEBUG
00000000 00000000 00000000 00000000
0xB0B200A8
I2S0_MIDREG
00000000 00000000 00000000 00000000
0xB0B200ACB0B203FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B20400
I2S1_RXFDAT0
00000000 00000000 00000000 00000000
0xB0B20404
I2S1_RXFDAT1
00000000 00000000 00000000 00000000
0xB0B20408
I2S1_RXFDAT2
00000000 00000000 00000000 00000000
0xB0B2040C
I2S1_RXFDAT3
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 245
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B20410
I2S1_RXFDAT4
00000000 00000000 00000000 00000000
0xB0B20414
I2S1_RXFDAT5
00000000 00000000 00000000 00000000
0xB0B20418
I2S1_RXFDAT6
00000000 00000000 00000000 00000000
0xB0B2041C
I2S1_RXFDAT7
00000000 00000000 00000000 00000000
0xB0B20420
I2S1_RXFDAT8
00000000 00000000 00000000 00000000
0xB0B20424
I2S1_RXFDAT9
00000000 00000000 00000000 00000000
0xB0B20428
I2S1_RXFDAT10
00000000 00000000 00000000 00000000
0xB0B2042C
I2S1_RXFDAT11
00000000 00000000 00000000 00000000
0xB0B20430
I2S1_RXFDAT12
00000000 00000000 00000000 00000000
0xB0B20434
I2S1_RXFDAT13
00000000 00000000 00000000 00000000
0xB0B20438
I2S1_RXFDAT14
00000000 00000000 00000000 00000000
0xB0B2043C
I2S1_RXFDAT15
00000000 00000000 00000000 00000000
0xB0B20440
I2S1_TXFDAT0
00000000 00000000 00000000 00000000
0xB0B20444
I2S1_TXFDAT1
00000000 00000000 00000000 00000000
0xB0B20448
I2S1_TXFDAT2
00000000 00000000 00000000 00000000
0xB0B2044C
I2S1_TXFDAT3
00000000 00000000 00000000 00000000
0xB0B20450
I2S1_TXFDAT4
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 246
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B20454
I2S1_TXFDAT5
00000000 00000000 00000000 00000000
0xB0B20458
I2S1_TXFDAT6
00000000 00000000 00000000 00000000
0xB0B2045C
I2S1_TXFDAT7
00000000 00000000 00000000 00000000
0xB0B20460
I2S1_TXFDAT8
00000000 00000000 00000000 00000000
0xB0B20464
I2S1_TXFDAT9
00000000 00000000 00000000 00000000
0xB0B20468
I2S1_TXFDAT10
00000000 00000000 00000000 00000000
0xB0B2046C
I2S1_TXFDAT11
00000000 00000000 00000000 00000000
0xB0B20470
I2S1_TXFDAT12
00000000 00000000 00000000 00000000
0xB0B20474
I2S1_TXFDAT13
00000000 00000000 00000000 00000000
0xB0B20478
I2S1_TXFDAT14
00000000 00000000 00000000 00000000
0xB0B2047C
I2S1_TXFDAT15
00000000 00000000 00000000 00000000
0xB0B20480
I2S1_CNTREG
00000000 00000000 00000000 01100000
0xB0B20484
I2S1_MCR0REG
00000000 00000000 00000000 00000000
0xB0B20488
I2S1_MCR1REG
00000000 00000000 00000000 00000000
0xB0B2048C
I2S1_MCR2REG
00000000 00000000 00000000 00000000
0xB0B20490
I2S1_OPRREG
00000000 00000000 00000000 00000000
0xB0B20494
I2S1_SRST
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 247
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B20498
I2S1_INTCNT
01111111 00111111 00000000 00000000
0xB0B2049C
I2S1_STATUS
00000000 00000000 00000000 00000000
0xB0B204A0
I2S1_DMAACT
00000000 00000000 00000000 00000000
0xB0B204A4
I2S1_DEBUG
00000000 00000000 00000000 00000000
0xB0B204A8
I2S1_MIDREG
00000000 00000000 00000000 00000000
0xB0B204ACB0B2FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B30000
CRC0_POLY
00000100 11000001 00011101 10110111
0xB0B30004
CRC0_SEED
11111111 11111111 11111111 11111111
0xB0B30008
CRC0_FXOR
11111111 11111111 11111111 11111111
0xB0B3000C
CRC0_CFG
00000000 11100000 00000000 00000000
0xB0B30010
CRC0_WR
00000000 00000000 00000000 00000000
0xB0B30014
CRC0_RD
00000000 00000000 00000000 00000000
0xB0B30018B0B37FFC
reserved
00000000 00000000 00000000 0000000X
0xB0B38000
SPI0_MCTRL
00000000 00000000 00000000 00000000
0xB0B38004
SPI0_PCC0
00000000 00000001 00000000 00000000
0xB0B38008
SPI0_PCC1
00000000 00000001 00000000 00000000
0xB0B3800C
SPI0_PCC2
00000000 00000001 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 248
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0B38010
SPI0_PCC3
00000000 00000001 00000000 00000000
0xB0B38014
SPI0_TXF
00000000 00000000 00000000 00000000
0xB0B38018
SPI0_TXE
00000000 00000000 00000000 00000000
0xB0B3801C
SPI0_TXC
00000000 00000000 00000000 00000000
0xB0B38020
SPI0_RXF
00000000 00000000 00000000 00000000
0xB0B38024
SPI0_RXE
00000000 00000000 00000000 00000000
0xB0B38028
SPI0_RXC
00000000 00000000 00000000 00000000
0xB0B3802C
SPI0_FAULTF
00000000 00000000 00000000 00000000
0xB0B38030
SPI0_FAULTC
00000000 00000000 00000000 00000000
read0
00000000 00000000
0xB0B38034
0xB0B38038
SPI0_DMTRP
00000000
0xB0B3803C
0xB0B38040
0xB0B38044
SPI0_DMPSEL
00000000
SPI0_DMBCS
00000000 00000000
SPI0_DMDMAEN
00000000
SPI0_DMCFG
00000001
SPI0_DMSTOP
00000000
SPI0_DMSTART
00000000
SPI0_DMBCC
00000000 00000000
SPI0_DMSTATUS
00000000 00000000 00000000 00000000
read0
00000000 00000000
SPI0_RXBITCNT
00000000
0xB0B38048
SPI0_RXSHIFT
00000000 00000000 00000000 00000000
0xB0B3804C
SPI0_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38050
SPI0_TXFIFO0
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
SPI0_TXBITCNT
00000000
Page 249
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B38054
SPI0_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38058
SPI0_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3805C
SPI0_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38060
SPI0_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38064
SPI0_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38068
SPI0_TXFIFO6
00000000 00000000 00000000 00000000
0xB0B3806C
SPI0_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38070
SPI0_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38074
SPI0_TXFIFO9
00000000 00000000 00000000 00000000
0xB0B38078
SPI0_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3807C
SPI0_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38080
SPI0_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38084
SPI0_TXFIFO13
00000000 00000000 00000000 00000000
0xB0B38088
SPI0_TXFIFO14
00000000 00000000 00000000 00000000
0xB0B3808C
SPI0_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38090
SPI0_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38094
SPI0_RXFIFO1
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 250
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B38098
SPI0_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3809C
SPI0_RXFIFO3
00000000 00000000 00000000 00000000
0xB0B380A0
SPI0_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B380A4
SPI0_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B380A8
SPI0_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B380AC
SPI0_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B380B0
SPI0_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B380B4
SPI0_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B380B8
SPI0_RXFIFO10
00000000 00000000 00000000 00000000
0xB0B380BC
SPI0_RXFIFO11
00000000 00000000 00000000 00000000
0xB0B380C0
SPI0_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B380C4
SPI0_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B380C8
SPI0_RXFIFO14
00000000 00000000 00000000 00000000
0xB0B380CC
SPI0_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B380D0B0B380F8
reserved
00000000 00000000 00000000 00000000
0xB0B380FC
SPI0_MID
00000000 00000000 00000000 00000001
0xB0B38100B0B383FC
reserved
00000000 00000000 00000000 0000000X
Document Number: DS707-00002-4v1-E
+0
Page 251
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0B38400
SPI1_MCTRL
00000000 00000000 00000000 00000000
0xB0B38404
SPI1_PCC0
00000000 00000001 00000000 00000000
0xB0B38408
SPI1_PCC1
00000000 00000001 00000000 00000000
0xB0B3840C
SPI1_PCC2
00000000 00000001 00000000 00000000
0xB0B38410
SPI1_PCC3
00000000 00000001 00000000 00000000
0xB0B38414
SPI1_TXF
00000000 00000000 00000000 00000000
0xB0B38418
SPI1_TXE
00000000 00000000 00000000 00000000
0xB0B3841C
SPI1_TXC
00000000 00000000 00000000 00000000
0xB0B38420
SPI1_RXF
00000000 00000000 00000000 00000000
0xB0B38424
SPI1_RXE
00000000 00000000 00000000 00000000
0xB0B38428
SPI1_RXC
00000000 00000000 00000000 00000000
0xB0B3842C
SPI1_FAULTF
00000000 00000000 00000000 00000000
0xB0B38430
SPI1_FAULTC
00000000 00000000 00000000 00000000
read0
00000000 00000000
0xB0B38434
0xB0B38438
SPI1_DMTRP
00000000
0xB0B3843C
0xB0B38440
Document Number: DS707-00002-4v1-E
SPI1_DMPSEL
00000000
SPI1_DMBCS
00000000 00000000
SPI1_DMDMAEN
00000000
SPI1_DMCFG
00000001
SPI1_DMSTOP
00000000
SPI1_DMSTART
00000000
SPI1_DMBCC
00000000 00000000
SPI1_DMSTATUS
00000000 00000000 00000000 00000000
Page 252
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
0xB0B38444
+2
read0
00000000 00000000
+1
+0
SPI1_RXBITCNT
00000000
SPI1_TXBITCNT
00000000
0xB0B38448
SPI1_RXSHIFT
00000000 00000000 00000000 00000000
0xB0B3844C
SPI1_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38450
SPI1_TXFIFO0
00000000 00000000 00000000 00000000
0xB0B38454
SPI1_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38458
SPI1_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3845C
SPI1_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38460
SPI1_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38464
SPI1_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38468
SPI1_TXFIFO6
00000000 00000000 00000000 00000000
0xB0B3846C
SPI1_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38470
SPI1_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38474
SPI1_TXFIFO9
00000000 00000000 00000000 00000000
0xB0B38478
SPI1_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3847C
SPI1_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38480
SPI1_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38484
SPI1_TXFIFO13
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 253
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B38488
SPI1_TXFIFO14
00000000 00000000 00000000 00000000
0xB0B3848C
SPI1_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38490
SPI1_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38494
SPI1_RXFIFO1
00000000 00000000 00000000 00000000
0xB0B38498
SPI1_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3849C
SPI1_RXFIFO3
00000000 00000000 00000000 00000000
0xB0B384A0
SPI1_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B384A4
SPI1_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B384A8
SPI1_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B384AC
SPI1_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B384B0
SPI1_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B384B4
SPI1_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B384B8
SPI1_RXFIFO10
00000000 00000000 00000000 00000000
0xB0B384BC
SPI1_RXFIFO11
00000000 00000000 00000000 00000000
0xB0B384C0
SPI1_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B384C4
SPI1_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B384C8
SPI1_RXFIFO14
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 254
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B384CC
SPI1_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B384D0B0B384F8
reserved
00000000 00000000 00000000 00000000
0xB0B384FC
SPI1_MID
00000000 00000000 00000000 00000001
0xB0B38500B0B387FC
reserved
00000000 00000000 00000000 0000000X
0xB0B38800
SPI2_MCTRL
00000000 00000000 00000000 00000000
0xB0B38804
SPI2_PCC0
00000000 00000001 00000000 00000000
0xB0B38808
SPI2_PCC1
00000000 00000001 00000000 00000000
0xB0B3880C
SPI2_PCC2
00000000 00000001 00000000 00000000
0xB0B38810
SPI2_PCC3
00000000 00000001 00000000 00000000
0xB0B38814
SPI2_TXF
00000000 00000000 00000000 00000000
0xB0B38818
SPI2_TXE
00000000 00000000 00000000 00000000
0xB0B3881C
SPI2_TXC
00000000 00000000 00000000 00000000
0xB0B38820
SPI2_RXF
00000000 00000000 00000000 00000000
0xB0B38824
SPI2_RXE
00000000 00000000 00000000 00000000
0xB0B38828
SPI2_RXC
00000000 00000000 00000000 00000000
0xB0B3882C
SPI2_FAULTF
00000000 00000000 00000000 00000000
0xB0B38830
SPI2_FAULTC
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 255
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
read0
00000000 00000000
0xB0B38834
0xB0B38838
+2
SPI2_DMTRP
00000000
0xB0B3883C
0xB0B38840
0xB0B38844
SPI2_DMPSEL
00000000
SPI2_DMBCS
00000000 00000000
+1
+0
SPI2_DMDMAEN
00000000
SPI2_DMCFG
00000001
SPI2_DMSTOP
00000000
SPI2_DMSTART
00000000
SPI2_DMBCC
00000000 00000000
SPI2_DMSTATUS
00000000 00000000 00000000 00000000
read0
00000000 00000000
SPI2_RXBITCNT
00000000
0xB0B38848
SPI2_RXSHIFT
00000000 00000000 00000000 00000000
0xB0B3884C
SPI2_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38850
SPI2_TXFIFO0
00000000 00000000 00000000 00000000
0xB0B38854
SPI2_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38858
SPI2_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3885C
SPI2_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38860
SPI2_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38864
SPI2_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38868
SPI2_TXFIFO6
00000000 00000000 00000000 00000000
0xB0B3886C
SPI2_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38870
SPI2_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38874
SPI2_TXFIFO9
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
SPI2_TXBITCNT
00000000
Page 256
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B38878
SPI2_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3887C
SPI2_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38880
SPI2_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38884
SPI2_TXFIFO13
00000000 00000000 00000000 00000000
0xB0B38888
SPI2_TXFIFO14
00000000 00000000 00000000 00000000
0xB0B3888C
SPI2_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38890
SPI2_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38894
SPI2_RXFIFO1
00000000 00000000 00000000 00000000
0xB0B38898
SPI2_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3889C
SPI2_RXFIFO3
00000000 00000000 00000000 00000000
0xB0B388A0
SPI2_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B388A4
SPI2_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B388A8
SPI2_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B388AC
SPI2_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B388B0
SPI2_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B388B4
SPI2_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B388B8
SPI2_RXFIFO10
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 257
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B388BC
SPI2_RXFIFO11
00000000 00000000 00000000 00000000
0xB0B388C0
SPI2_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B388C4
SPI2_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B388C8
SPI2_RXFIFO14
00000000 00000000 00000000 00000000
0xB0B388CC
SPI2_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B388D0B0B388F8
reserved
00000000 00000000 00000000 00000000
0xB0B388FC
SPI2_MID
00000000 00000000 00000000 00000001
0xB0B38900B0B3FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B40000
ARH0_RHCTRL
00000000 00000000 00000000 00000001
0xB0B40004
ARH0_CHCTRL0
00001111 00000000 00000000 00000000
0xB0B40008
ARH0_CHSTAT0
00000000 00000000 00000000 00000000
0xB0B4000C
ARH0_CHWDGCTL0
00000000 00000000 00000000 00000000
0xB0B40010
ARH0_CHWDGCNT0
00000000 00000000 XXXXXXXX XXXXXXXX
0xB0B40014
ARH0_CHCTRL1
00000111 00000000 00000000 00000000
0xB0B40018
ARH0_CHSTAT1
00000000 00000000 00000000 00000000
0xB0B4001C
ARH0_CHWDGCTL1
00000000 00000000 00000000 00000000
0xB0B40020
ARH0_CHWDGCNT1
00000000 00000000 XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 258
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B40024
ARH0_TBCTRL0
00000000 00000000 00000000 00000000
0xB0B40028
ARH0_TBCTRL1
00000000 00000000 00000000 00000000
0xB0B4002C
ARH0_TBCTRL2
00000000 00000000 00000000 00000000
0xB0B40030
ARH0_TBCTRL3
00000000 00000000 00000000 00000000
0xB0B40034
ARH0_TBCTRL4
00000000 00000000 00000000 00000000
0xB0B40038
ARH0_TBCTRL5
00000000 00000000 00000000 00000000
0xB0B4003C
ARH0_TBCTRL6
00000000 00000000 00000000 00000000
0xB0B40040
ARH0_TBCTRL7
00000000 00000000 00000000 00000000
0xB0B40044
ARH0_TBCTRL8
00000000 00000000 00000000 00000000
0xB0B40048
ARH0_TBCTRL9
00000000 00000000 00000000 00000000
0xB0B4004C
ARH0_TBCTRL10
00000000 00000000 00000000 00000000
0xB0B40050
ARH0_TBCTRL11
00000000 00000000 00000000 00000000
0xB0B40054
ARH0_TBCTRL12
00000000 00000000 00000000 00000000
0xB0B40058
ARH0_TBCTRL13
00000000 00000000 00000000 00000000
0xB0B4005C
ARH0_TBCTRL14
00000000 00000000 00000000 00000000
0xB0B40060
ARH0_TBCTRL15
00000000 00000000 00000000 00000000
0xB0B40064
Document Number: DS707-00002-4v1-E
ARH0_TBIRQ
00000000 00000000
ARH0_TBIDX0
00000000
+0
ARH0_TBIDX1
00000000
Page 259
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0B40068
ARH0_TFCTRL0
00000000
ARH0_TFIDX0
00000000
ARH0_TFCTRL1
00000000
ARH0_TFIDX1
00000000
0xB0B4006C
ARH0_TFCTRL2
00000000
ARH0_TFIDX2
00000000
ARH0_TFCTRL3
00000000
ARH0_TFIDX3
00000000
0xB0B40070
ARH0_TFCTRL4
00000000
ARH0_TFIDX4
00000000
ARH0_TFCTRL5
00000000
ARH0_TFIDX5
00000000
0xB0B40074
ARH0_TFCTRL6
00000000
ARH0_TFIDX6
00000000
ARH0_TFCTRL7
00000000
ARH0_TFIDX7
00000000
0xB0B40078
ARH0_TFCTRL8
00000000
ARH0_TFIDX8
00000000
ARH0_TFCTRL9
00000000
ARH0_TFIDX9
00000000
0xB0B4007C
ARH0_TFCTRL10
00000000
ARH0_TFIDX10
00000000
ARH0_TFCTRL11
00000000
ARH0_TFIDX11
00000000
0xB0B40080
ARH0_TFCTRL12
00000000
ARH0_TFIDX12
00000000
ARH0_TFCTRL13
00000000
ARH0_TFIDX13
00000000
0xB0B40084
ARH0_TFCTRL14
00000000
ARH0_TFIDX14
00000000
ARH0_TFCTRL15
00000000
ARH0_TFIDX15
00000000
0xB0B40088
ARH0_TFADDR0
00000000 00000000 00000000 00000000
0xB0B4008C
ARH0_TFADDR1
00000000 00000000 00000000 00000000
0xB0B40090
ARH0_TFADDR2
00000000 00000000 00000000 00000000
0xB0B40094
ARH0_TFADDR3
00000000 00000000 00000000 00000000
0xB0B40098
ARH0_TFADDR4
00000000 00000000 00000000 00000000
0xB0B4009C
ARH0_TFADDR5
00000000 00000000 00000000 00000000
0xB0B400A0
ARH0_TFADDR6
00000000 00000000 00000000 00000000
0xB0B400A4
ARH0_TFADDR7
00000000 00000000 00000000 00000000
0xB0B400A8
ARH0_TFADDR8
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
Page 260
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B400AC
ARH0_TFADDR9
00000000 00000000 00000000 00000000
0xB0B400B0
ARH0_TFADDR10
00000000 00000000 00000000 00000000
0xB0B400B4
ARH0_TFADDR11
00000000 00000000 00000000 00000000
0xB0B400B8
ARH0_TFADDR12
00000000 00000000 00000000 00000000
0xB0B400BC
ARH0_TFADDR13
00000000 00000000 00000000 00000000
0xB0B400C0
ARH0_TFADDR14
00000000 00000000 00000000 00000000
0xB0B400C4
ARH0_TFADDR15
00000000 00000000 00000000 00000000
0xB0B400C8
ARH0_TFDATA0
00000000 00000000 00000000 00000000
0xB0B400CC
ARH0_TFDATA1
00000000 00000000 00000000 00000000
0xB0B400D0
ARH0_TFDATA2
00000000 00000000 00000000 00000000
0xB0B400D4
ARH0_TFDATA3
00000000 00000000 00000000 00000000
0xB0B400D8
ARH0_TFDATA4
00000000 00000000 00000000 00000000
0xB0B400DC
ARH0_TFDATA5
00000000 00000000 00000000 00000000
0xB0B400E0
ARH0_TFDATA6
00000000 00000000 00000000 00000000
0xB0B400E4
ARH0_TFDATA7
00000000 00000000 00000000 00000000
0xB0B400E8
ARH0_TFDATA8
00000000 00000000 00000000 00000000
0xB0B400EC
ARH0_TFDATA9
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 261
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0B400F0
ARH0_TFDATA10
00000000 00000000 00000000 00000000
0xB0B400F4
ARH0_TFDATA11
00000000 00000000 00000000 00000000
0xB0B400F8
ARH0_TFDATA12
00000000 00000000 00000000 00000000
0xB0B400FC
ARH0_TFDATA13
00000000 00000000 00000000 00000000
0xB0B40100
ARH0_TFDATA14
00000000 00000000 00000000 00000000
0xB0B40104
ARH0_TFDATA15
00000000 00000000 00000000 00000000
0xB0B40108
ARH0_EVCTRL
00000000 00000000 00000000 10000000
0xB0B4010C
ARH0_EVIRQC
00000000 00000000 00000000 00000000
0xB0B40110
ARH0_EVBUF0
0000000X XXXXXXXX 00000000 00000000
0xB0B40114
ARH0_EVBUF1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B40118
ARH0_APCFG00
0000X000 00110000 00000000 10010000
0xB0B4011C
ARH0_APCFG01
11110000 00000000 00000000 01001000
0xB0B40120
ARH0_APCFG02
0000001X 00000010 01000000 00000000
0xB0B40124
ARH0_APCFG03
00100110 10100100 10011010 00000000
0xB0B40128
ARH0_APCFG10
00000000 0011000000000000 10010000
0xB0B4012C
ARH0_APCFG11
111100XX 00000000 00000000 0100100X
0xB0B40130
ARH0_APCFG12
00000010 00000010 01000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 262
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0B40134
ARH0_APCFG13
00100110 10100100 10011010 00000000
0xB0B40138
ARH0_TST
00000000 00000000 00000000 00000000
0xB0B4013C
ARH0_UNLOCK
00000000 00000000 00000000 00000000
0xB0B40140
ARH0_MID
00000000 00000000 00000000 00000000
0xB0B40144
ARH0_APCFG04
00000000 00000000 00000000 00000000
0xB0B40148
ARH0_APCFG14
00000000 00000000 00000000 00000000
0xB0B4014C
ARH0_EVAL0
00000000 00000000 00000000 00000000
0xB0B40150
ARH0_EVAL1
00000000 00000000 00000000 00000000
0xB0B40154
ARH0_EVAL2
00000000 00000000 00000000 00001010
0xB0B40158
ARH0_EVAL3
00000000 00000000 00000000 00000000
0xB0B4015C
ARH0_EVAL4
00000000 00000000 00000000 00001100
0xB0B40160
ARH0_EVAL5
00000000 00000000 00000000 00000000
0xB0B40164
ARH0_EVAL6
00000000 00000000 00000000 00000000
0xB0B40168
ARH0_EVAL7
00000000 00000000 00000000 00000000
0xB0B4016CB0BF8FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0BF9000
read0
00000000 00000000
RICFG4_I2S0ECLK
00000000 00000000
0xB0BF9004
read0
00000000 00000000
RICFG4_I2S0SCKI
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 263
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0BF9008
read0
00000000 00000000
RICFG4_I2S0SDI
00000000 00000000
0xB0BF900C
read0
00000000 00000000
RICFG4_I2S0WSI
00000000 00000000
0xB0BF9010B0BF901C
reserved
00000000 00000000 00000000 00000000
0xB0BF9020
read0
00000000 00000000
RICFG4_I2S1ECLK
00000000 00000000
0xB0BF9024
read0
00000000 00000000
RICFG4_I2S1SCKI
00000000 00000000
0xB0BF9028
read0
00000000 00000000
RICFG4_I2S1SDI
00000000 00000000
0xB0BF902C
read0
00000000 00000000
RICFG4_I2S1WSI
00000000 00000000
0xB0BF9030B0BF9BFC
reserved
00000000 00000000 00000000 00000000
0xB0BF9C00
read0
00000000 00000000
RICFG4_SPI0CLKI
00000000 00000000
0xB0BF9C04
read0
00000000 00000000
RICFG4_SPI0DATA0I
00000000 00000000
0xB0BF9C08
read0
00000000 00000000
RICFG4_SPI0DATA1I
00000000 00000000
0xB0BF9C0C
read0
00000000 00000000
RICFG4_SPI0DATA2I
00000000 00000000
0xB0BF9C10
read0
00000000 00000000
RICFG4_SPI0DATA3I
00000000 00000000
0xB0BF9C14
read0
00000000 00000000
RICFG4_SPI0MSTART
00000000 00000000
0xB0BF9C18
read0
00000000 00000000
RICFG4_SPI0SSI
00000000 00000000
0xB0BF9C1C
0xB0BF9C20
Document Number: DS707-00002-4v1-E
reserved
00000000 00000000 00000000 00000000
read0
00000000 00000000
RICFG4_SPI1CLKI
00000000 00000000
Page 264
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0BF9C24
read0
00000000 00000000
RICFG4_SPI1DATA0I
00000000 00000000
0xB0BF9C28
read0
00000000 00000000
RICFG4_SPI1DATA1I
00000000 00000000
0xB0BF9C2C
read0
00000000 00000000
RICFG4_SPI1DATA2I
00000000 00000000
0xB0BF9C30
read0
00000000 00000000
RICFG4_SPI1DATA3I
00000000 00000000
0xB0BF9C34
read0
00000000 00000000
RICFG4_SPI1MSTART
00000000 00000000
0xB0BF9C38
read0
00000000 00000000
RICFG4_SPI1SSI
00000000 00000000
0xB0BF9C3C
reserved
00000000 00000000 00000000 00000000
0xB0BF9C40
read0
00000000 00000000
RICFG4_SPI2CLKI
00000000 00000000
0xB0BF9C44
read0
00000000 00000000
RICFG4_SPI2DATA0I
00000000 00000000
0xB0BF9C48
read0
00000000 00000000
RICFG4_SPI2DATA1I
00000000 00000000
0xB0BF9C4C
read0
00000000 00000000
RICFG4_SPI2DATA2I
00000000 00000000
0xB0BF9C50
read0
00000000 00000000
RICFG4_SPI2DATA3I
00000000 00000000
0xB0BF9C54
read0
00000000 00000000
RICFG4_SPI2MSTART
00000000 00000000
0xB0BF9C58
read0
00000000 00000000
RICFG4_SPI2SSI
00000000 00000000
0xB0BF9C5CB0BF9FFC
reserved
00000000 00000000 00000000 00000000
0xB0BFA000
read0
00000000 00000000
RICFG4_ARH0AIC0RCK
00000000 00000000
0xB0BFA004
read0
00000000 00000000
RICFG4_ARH0AIC0RDA0
00000000 00000000
Document Number: DS707-00002-4v1-E
Page 265
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
+0
0xB0BFA008
read0
00000000 00000000
RICFG4_ARH0AIC0RDA1
00000000 00000000
0xB0BFA00C
read0
00000000 00000000
RICFG4_ARH0AIC0TCKI
00000000 00000000
0xB0BFA010
read0
00000000 00000000
RICFG4_ARH0AIC0UPCLK
00000000 00000000
0xB0BFA014
read0
00000000 00000000
RICFG4_ARH0AIC0UPDATA0
00000000 00000000
0xB0BFA018
read0
00000000 00000000
RICFG4_ARH0AIC0UPDATA1
00000000 00000000
0xB0BFA01C
read0
00000000 00000000
RICFG4_ARH0AIC0DBGSELECT
00000000 00000000
0xB0BFA020
read0
00000000 00000000
RICFG4_ARH0AIC1RCK
00000000 00000000
0xB0BFA024
read0
00000000 00000000
RICFG4_ARH0AIC1RDA0
00000000 00000000
0xB0BFA028
read0
00000000 00000000
RICFG4_ARH0AIC1RDA1
00000000 00000000
0xB0BFA02C
read0
00000000 00000000
RICFG4_ARH0AIC1TCKI
00000000 00000000
0xB0BFA030
read0
00000000 00000000
RICFG4_ARH0AIC1UPCLK
00000000 00000000
0xB0BFA034
read0
00000000 00000000
RICFG4_ARH0AIC1UPDATA0
00000000 00000000
0xB0BFA038
read0
00000000 00000000
RICFG4_ARH0AIC1UPDATA1
00000000 00000000
0xB0BFA03C
read0
00000000 00000000
RICFG4_ARH0AIC1DBGSELECT
00000000 00000000
0xB0BFA040B0BFFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0BFFC04
BSU4_BTST
00000000 00000000 00000000 00000000
0xB0BFFC08B0BFFC10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 266
MB9DF126
MB9DF126B
Table 5-9 Memory layout of the PERI4_SLAVE registers (Continued)
Offset
+3
+2
+1
0xB0BFFC14
BSU4_PEN1
00000000 00000000 00000000 00000000
0xB0BFFC18
BSU4_PEN2
00000000 00000000 00000000 00000000
0xB0BFFC1C
BSU4_PEN3
00000000 00000000 00000000 00000000
0xB0BFFC20
BSU4_PEN4
00000000 00000000 00000000 00000000
0xB0BFFC24
BSU4_PEN5
00000000 00000000 00000000 00000000
0xB0BFFC28
BSU4_PEN6
00000000 00000000 00000000 00000000
0xB0BFFC2C
BSU4_PEN7
00000000 00000000 00000000 00000000
0xB0BFFC30
BSU4_PEN8
00000000 00000000 00000000 00000000
0xB0BFFC34B0BFFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 267
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers
Offset
+3
+2
+1
0xB0C00000
DMA0_A0
00000000 00001111 00000000 00000000
0xB0C00004
DMA0_B0
00000000 00000000 00110011 01111111
0xB0C00008
DMA0_SA0
00000000 00000000 00000000 00000000
0xB0C0000C
DMA0_DA0
00000000 00000000 00000000 00000000
0xB0C00010
DMA0_C0
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00014
DMA0_D0
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00018
DMA0_SASHDW0
00000000 00000000 00000000 00000000
0xB0C0001C
DMA0_DASHDW0
00000000 00000000 00000000 00000000
0xB0C00020B0C0003C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00040
DMA0_A1
00000000 00001111 00000000 00000000
0xB0C00044
DMA0_B1
00000000 00000000 00110011 01111111
0xB0C00048
DMA0_SA1
00000000 00000000 00000000 00000000
0xB0C0004C
DMA0_DA1
00000000 00000000 00000000 00000000
0xB0C00050
DMA0_C1
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00054
DMA0_D1
00000000 XXXXXXXX 00000000 XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 268
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00058
DMA0_SASHDW1
00000000 00000000 00000000 00000000
0xB0C0005C
DMA0_DASHDW1
00000000 00000000 00000000 00000000
0xB0C00060B0C0007C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00080
DMA0_A2
00000000 00001111 00000000 00000000
0xB0C00084
DMA0_B2
00000000 00000000 00110011 01111111
0xB0C00088
DMA0_SA2
00000000 00000000 00000000 00000000
0xB0C0008C
DMA0_DA2
00000000 00000000 00000000 00000000
0xB0C00090
DMA0_C2
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00094
DMA0_D2
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00098
DMA0_SASHDW2
00000000 00000000 00000000 00000000
0xB0C0009C
DMA0_DASHDW2
00000000 00000000 00000000 00000000
0xB0C000A0B0C000BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C000C0
DMA0_A3
00000000 00001111 00000000 00000000
0xB0C000C4
DMA0_B3
00000000 00000000 00110011 01111111
0xB0C000C8
DMA0_SA3
00000000 00000000 00000000 00000000
0xB0C000CC
DMA0_DA3
00000000 00000000 00000000 00000000
0xB0C000D0
DMA0_C3
XXXXXXXX XXXXXXXX 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 269
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C000D4
DMA0_D3
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C000D8
DMA0_SASHDW3
00000000 00000000 00000000 00000000
0xB0C000DC
DMA0_DASHDW3
00000000 00000000 00000000 00000000
0xB0C000E0B0C000FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00100
DMA0_A4
00000000 00001111 00000000 00000000
0xB0C00104
DMA0_B4
00000000 00000000 00110011 01111111
0xB0C00108
DMA0_SA4
00000000 00000000 00000000 00000000
0xB0C0010C
DMA0_DA4
00000000 00000000 00000000 00000000
0xB0C00110
DMA0_C4
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00114
DMA0_D4
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00118
DMA0_SASHDW4
00000000 00000000 00000000 00000000
0xB0C0011C
DMA0_DASHDW4
00000000 00000000 00000000 00000000
0xB0C00120B0C0013C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00140
DMA0_A5
00000000 00001111 00000000 00000000
0xB0C00144
DMA0_B5
00000000 00000000 00110011 01111111
0xB0C00148
DMA0_SA5
00000000 00000000 00000000 00000000
0xB0C0014C
DMA0_DA5
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 270
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00150
DMA0_C5
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00154
DMA0_D5
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00158
DMA0_SASHDW5
00000000 00000000 00000000 00000000
0xB0C0015C
DMA0_DASHDW5
00000000 00000000 00000000 00000000
0xB0C00160B0C0017C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00180
DMA0_A6
00000000 00001111 00000000 00000000
0xB0C00184
DMA0_B6
00000000 00000000 00110011 01111111
0xB0C00188
DMA0_SA6
00000000 00000000 00000000 00000000
0xB0C0018C
DMA0_DA6
00000000 00000000 00000000 00000000
0xB0C00190
DMA0_C6
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00194
DMA0_D6
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00198
DMA0_SASHDW6
00000000 00000000 00000000 00000000
0xB0C0019C
DMA0_DASHDW6
00000000 00000000 00000000 00000000
0xB0C001A0B0C001BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C001C0
DMA0_A7
00000000 00001111 00000000 00000000
0xB0C001C4
DMA0_B7
00000000 00000000 00110011 01111111
0xB0C001C8
DMA0_SA7
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 271
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C001CC
DMA0_DA7
00000000 00000000 00000000 00000000
0xB0C001D0
DMA0_C7
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C001D4
DMA0_D7
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C001D8
DMA0_SASHDW7
00000000 00000000 00000000 00000000
0xB0C001DC
DMA0_DASHDW7
00000000 00000000 00000000 00000000
0xB0C001E0B0C001FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00200
DMA0_A8
00000000 00001111 00000000 00000000
0xB0C00204
DMA0_B8
00000000 00000000 00110011 01111111
0xB0C00208
DMA0_SA8
00000000 00000000 00000000 00000000
0xB0C0020C
DMA0_DA8
00000000 00000000 00000000 00000000
0xB0C00210
DMA0_C8
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00214
DMA0_D8
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00218
DMA0_SASHDW8
00000000 00000000 00000000 00000000
0xB0C0021C
DMA0_DASHDW8
00000000 00000000 00000000 00000000
0xB0C00220B0C0023C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00240
DMA0_A9
00000000 00001111 00000000 00000000
0xB0C00244
DMA0_B9
00000000 00000000 00110011 01111111
Document Number: DS707-00002-4v1-E
+0
Page 272
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00248
DMA0_SA9
00000000 00000000 00000000 00000000
0xB0C0024C
DMA0_DA9
00000000 00000000 00000000 00000000
0xB0C00250
DMA0_C9
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00254
DMA0_D9
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00258
DMA0_SASHDW9
00000000 00000000 00000000 00000000
0xB0C0025C
DMA0_DASHDW9
00000000 00000000 00000000 00000000
0xB0C00260B0C0027C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00280
DMA0_A10
00000000 00001111 00000000 00000000
0xB0C00284
DMA0_B10
00000000 00000000 00110011 01111111
0xB0C00288
DMA0_SA10
00000000 00000000 00000000 00000000
0xB0C0028C
DMA0_DA10
00000000 00000000 00000000 00000000
0xB0C00290
DMA0_C10
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00294
DMA0_D10
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00298
DMA0_SASHDW10
00000000 00000000 00000000 00000000
0xB0C0029C
DMA0_DASHDW10
00000000 00000000 00000000 00000000
0xB0C002A0B0C002BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C002C0
DMA0_A11
00000000 00001111 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 273
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C002C4
DMA0_B11
00000000 00000000 00110011 01111111
0xB0C002C8
DMA0_SA11
00000000 00000000 00000000 00000000
0xB0C002CC
DMA0_DA11
00000000 00000000 00000000 00000000
0xB0C002D0
DMA0_C11
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C002D4
DMA0_D11
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C002D8
DMA0_SASHDW11
00000000 00000000 00000000 00000000
0xB0C002DC
DMA0_DASHDW11
00000000 00000000 00000000 00000000
0xB0C002E0B0C002FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00300
DMA0_A12
00000000 00001111 00000000 00000000
0xB0C00304
DMA0_B12
00000000 00000000 00110011 01111111
0xB0C00308
DMA0_SA12
00000000 00000000 00000000 00000000
0xB0C0030C
DMA0_DA12
00000000 00000000 00000000 00000000
0xB0C00310
DMA0_C12
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00314
DMA0_D12
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00318
DMA0_SASHDW12
00000000 00000000 00000000 00000000
0xB0C0031C
DMA0_DASHDW12
00000000 00000000 00000000 00000000
0xB0C00320B0C0033C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 274
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00340
DMA0_A13
00000000 00001111 00000000 00000000
0xB0C00344
DMA0_B13
00000000 00000000 00110011 01111111
0xB0C00348
DMA0_SA13
00000000 00000000 00000000 00000000
0xB0C0034C
DMA0_DA13
00000000 00000000 00000000 00000000
0xB0C00350
DMA0_C13
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00354
DMA0_D13
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00358
DMA0_SASHDW13
00000000 00000000 00000000 00000000
0xB0C0035C
DMA0_DASHDW13
00000000 00000000 00000000 00000000
0xB0C00360B0C0037C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00380
DMA0_A14
00000000 00001111 00000000 00000000
0xB0C00384
DMA0_B14
00000000 00000000 00110011 01111111
0xB0C00388
DMA0_SA14
00000000 00000000 00000000 00000000
0xB0C0038C
DMA0_DA14
00000000 00000000 00000000 00000000
0xB0C00390
DMA0_C14
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00394
DMA0_D14
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00398
DMA0_SASHDW14
00000000 00000000 00000000 00000000
0xB0C0039C
DMA0_DASHDW14
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 275
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C003A0B0C003BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C003C0
DMA0_A15
00000000 00001111 00000000 00000000
0xB0C003C4
DMA0_B15
00000000 00000000 00110011 01111111
0xB0C003C8
DMA0_SA15
00000000 00000000 00000000 00000000
0xB0C003CC
DMA0_DA15
00000000 00000000 00000000 00000000
0xB0C003D0
DMA0_C15
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C003D4
DMA0_D15
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C003D8
DMA0_SASHDW15
00000000 00000000 00000000 00000000
0xB0C003DC
DMA0_DASHDW15
00000000 00000000 00000000 00000000
0xB0C003E0B0C003FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00400
DMA0_A16
00000000 00001111 00000000 00000000
0xB0C00404
DMA0_B16
00000000 00000000 00110011 01111111
0xB0C00408
DMA0_SA16
00000000 00000000 00000000 00000000
0xB0C0040C
DMA0_DA16
00000000 00000000 00000000 00000000
0xB0C00410
DMA0_C16
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00414
DMA0_D16
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00418
DMA0_SASHDW16
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 276
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0041C
DMA0_DASHDW16
00000000 00000000 00000000 00000000
0xB0C00420B0C0043C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00440
DMA0_A17
00000000 00001111 00000000 00000000
0xB0C00444
DMA0_B17
00000000 00000000 00110011 01111111
0xB0C00448
DMA0_SA17
00000000 00000000 00000000 00000000
0xB0C0044C
DMA0_DA17
00000000 00000000 00000000 00000000
0xB0C00450
DMA0_C17
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00454
DMA0_D17
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00458
DMA0_SASHDW17
00000000 00000000 00000000 00000000
0xB0C0045C
DMA0_DASHDW17
00000000 00000000 00000000 00000000
0xB0C00460B0C0047C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00480
DMA0_A18
00000000 00001111 00000000 00000000
0xB0C00484
DMA0_B18
00000000 00000000 00110011 01111111
0xB0C00488
DMA0_SA18
00000000 00000000 00000000 00000000
0xB0C0048C
DMA0_DA18
00000000 00000000 00000000 00000000
0xB0C00490
DMA0_C18
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00494
DMA0_D18
00000000 XXXXXXXX 00000000 XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 277
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00498
DMA0_SASHDW18
00000000 00000000 00000000 00000000
0xB0C0049C
DMA0_DASHDW18
00000000 00000000 00000000 00000000
0xB0C004A0B0C004BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C004C0
DMA0_A19
00000000 00001111 00000000 00000000
0xB0C004C4
DMA0_B19
00000000 00000000 00110011 01111111
0xB0C004C8
DMA0_SA19
00000000 00000000 00000000 00000000
0xB0C004CC
DMA0_DA19
00000000 00000000 00000000 00000000
0xB0C004D0
DMA0_C19
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C004D4
DMA0_D19
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C004D8
DMA0_SASHDW19
00000000 00000000 00000000 00000000
0xB0C004DC
DMA0_DASHDW19
00000000 00000000 00000000 00000000
0xB0C004E0B0C004FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00500
DMA0_A20
00000000 00001111 00000000 00000000
0xB0C00504
DMA0_B20
00000000 00000000 00110011 01111111
0xB0C00508
DMA0_SA20
00000000 00000000 00000000 00000000
0xB0C0050C
DMA0_DA20
00000000 00000000 00000000 00000000
0xB0C00510
DMA0_C20
XXXXXXXX XXXXXXXX 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 278
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00514
DMA0_D20
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00518
DMA0_SASHDW20
00000000 00000000 00000000 00000000
0xB0C0051C
DMA0_DASHDW20
00000000 00000000 00000000 00000000
0xB0C00520B0C0053C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00540
DMA0_A21
00000000 00001111 00000000 00000000
0xB0C00544
DMA0_B21
00000000 00000000 00110011 01111111
0xB0C00548
DMA0_SA21
00000000 00000000 00000000 00000000
0xB0C0054C
DMA0_DA21
00000000 00000000 00000000 00000000
0xB0C00550
DMA0_C21
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00554
DMA0_D21
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00558
DMA0_SASHDW21
00000000 00000000 00000000 00000000
0xB0C0055C
DMA0_DASHDW21
00000000 00000000 00000000 00000000
0xB0C00560B0C0057C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00580
DMA0_A22
00000000 00001111 00000000 00000000
0xB0C00584
DMA0_B22
00000000 00000000 00110011 01111111
0xB0C00588
DMA0_SA22
00000000 00000000 00000000 00000000
0xB0C0058C
DMA0_DA22
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 279
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00590
DMA0_C22
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00594
DMA0_D22
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00598
DMA0_SASHDW22
00000000 00000000 00000000 00000000
0xB0C0059C
DMA0_DASHDW22
00000000 00000000 00000000 00000000
0xB0C005A0B0C005BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C005C0
DMA0_A23
00000000 00001111 00000000 00000000
0xB0C005C4
DMA0_B23
00000000 00000000 00110011 01111111
0xB0C005C8
DMA0_SA23
00000000 00000000 00000000 00000000
0xB0C005CC
DMA0_DA23
00000000 00000000 00000000 00000000
0xB0C005D0
DMA0_C23
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C005D4
DMA0_D23
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C005D8
DMA0_SASHDW23
00000000 00000000 00000000 00000000
0xB0C005DC
DMA0_DASHDW23
00000000 00000000 00000000 00000000
0xB0C005E0B0C005FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00600
DMA0_A24
00000000 00001111 00000000 00000000
0xB0C00604
DMA0_B24
00000000 00000000 00110011 01111111
0xB0C00608
DMA0_SA24
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 280
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0060C
DMA0_DA24
00000000 00000000 00000000 00000000
0xB0C00610
DMA0_C24
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00614
DMA0_D24
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00618
DMA0_SASHDW24
00000000 00000000 00000000 00000000
0xB0C0061C
DMA0_DASHDW24
00000000 00000000 00000000 00000000
0xB0C00620B0C0063C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00640
DMA0_A25
00000000 00001111 00000000 00000000
0xB0C00644
DMA0_B25
00000000 00000000 00110011 01111111
0xB0C00648
DMA0_SA25
00000000 00000000 00000000 00000000
0xB0C0064C
DMA0_DA25
00000000 00000000 00000000 00000000
0xB0C00650
DMA0_C25
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00654
DMA0_D25
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00658
DMA0_SASHDW25
00000000 00000000 00000000 00000000
0xB0C0065C
DMA0_DASHDW25
00000000 00000000 00000000 00000000
0xB0C00660B0C0067C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00680
DMA0_A26
00000000 00001111 00000000 00000000
0xB0C00684
DMA0_B26
00000000 00000000 00110011 01111111
Document Number: DS707-00002-4v1-E
+0
Page 281
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00688
DMA0_SA26
00000000 00000000 00000000 00000000
0xB0C0068C
DMA0_DA26
00000000 00000000 00000000 00000000
0xB0C00690
DMA0_C26
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00694
DMA0_D26
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00698
DMA0_SASHDW26
00000000 00000000 00000000 00000000
0xB0C0069C
DMA0_DASHDW26
00000000 00000000 00000000 00000000
0xB0C006A0B0C006BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C006C0
DMA0_A27
00000000 00001111 00000000 00000000
0xB0C006C4
DMA0_B27
00000000 00000000 00110011 01111111
0xB0C006C8
DMA0_SA27
00000000 00000000 00000000 00000000
0xB0C006CC
DMA0_DA27
00000000 00000000 00000000 00000000
0xB0C006D0
DMA0_C27
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C006D4
DMA0_D27
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C006D8
DMA0_SASHDW27
00000000 00000000 00000000 00000000
0xB0C006DC
DMA0_DASHDW27
00000000 00000000 00000000 00000000
0xB0C006E0B0C006FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00700
DMA0_A28
00000000 00001111 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 282
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00704
DMA0_B28
00000000 00000000 00110011 01111111
0xB0C00708
DMA0_SA28
00000000 00000000 00000000 00000000
0xB0C0070C
DMA0_DA28
00000000 00000000 00000000 00000000
0xB0C00710
DMA0_C28
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00714
DMA0_D28
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00718
DMA0_SASHDW28
00000000 00000000 00000000 00000000
0xB0C0071C
DMA0_DASHDW28
00000000 00000000 00000000 00000000
0xB0C00720B0C0073C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00740
DMA0_A29
00000000 00001111 00000000 00000000
0xB0C00744
DMA0_B29
00000000 00000000 00110011 01111111
0xB0C00748
DMA0_SA29
00000000 00000000 00000000 00000000
0xB0C0074C
DMA0_DA29
00000000 00000000 00000000 00000000
0xB0C00750
DMA0_C29
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00754
DMA0_D29
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00758
DMA0_SASHDW29
00000000 00000000 00000000 00000000
0xB0C0075C
DMA0_DASHDW29
00000000 00000000 00000000 00000000
0xB0C00760B0C0077C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 283
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00780
DMA0_A30
00000000 00001111 00000000 00000000
0xB0C00784
DMA0_B30
00000000 00000000 00110011 01111111
0xB0C00788
DMA0_SA30
00000000 00000000 00000000 00000000
0xB0C0078C
DMA0_DA30
00000000 00000000 00000000 00000000
0xB0C00790
DMA0_C30
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00794
DMA0_D30
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00798
DMA0_SASHDW30
00000000 00000000 00000000 00000000
0xB0C0079C
DMA0_DASHDW30
00000000 00000000 00000000 00000000
0xB0C007A0B0C007BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C007C0
DMA0_A31
00000000 00001111 00000000 00000000
0xB0C007C4
DMA0_B31
00000000 00000000 00110011 01111111
0xB0C007C8
DMA0_SA31
00000000 00000000 00000000 00000000
0xB0C007CC
DMA0_DA31
00000000 00000000 00000000 00000000
0xB0C007D0
DMA0_C31
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C007D4
DMA0_D31
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C007D8
DMA0_SASHDW31
00000000 00000000 00000000 00000000
0xB0C007DC
DMA0_DASHDW31
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 284
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C007E0B0C007FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00800
DMA0_A32
00000000 00001111 00000000 00000000
0xB0C00804
DMA0_B32
00000000 00000000 00110011 01111111
0xB0C00808
DMA0_SA32
00000000 00000000 00000000 00000000
0xB0C0080C
DMA0_DA32
00000000 00000000 00000000 00000000
0xB0C00810
DMA0_C32
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00814
DMA0_D32
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00818
DMA0_SASHDW32
00000000 00000000 00000000 00000000
0xB0C0081C
DMA0_DASHDW32
00000000 00000000 00000000 00000000
0xB0C00820B0C0083C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00840
DMA0_A33
00000000 00001111 00000000 00000000
0xB0C00844
DMA0_B33
00000000 00000000 00110011 01111111
0xB0C00848
DMA0_SA33
00000000 00000000 00000000 00000000
0xB0C0084C
DMA0_DA33
00000000 00000000 00000000 00000000
0xB0C00850
DMA0_C33
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00854
DMA0_D33
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00858
DMA0_SASHDW33
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 285
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0085C
DMA0_DASHDW33
00000000 00000000 00000000 00000000
0xB0C00860B0C0087C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00880
DMA0_A34
00000000 00001111 00000000 00000000
0xB0C00884
DMA0_B34
00000000 00000000 00110011 01111111
0xB0C00888
DMA0_SA34
00000000 00000000 00000000 00000000
0xB0C0088C
DMA0_DA34
00000000 00000000 00000000 00000000
0xB0C00890
DMA0_C34
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00894
DMA0_D34
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00898
DMA0_SASHDW34
00000000 00000000 00000000 00000000
0xB0C0089C
DMA0_DASHDW34
00000000 00000000 00000000 00000000
0xB0C008A0B0C008BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C008C0
DMA0_A35
00000000 00001111 00000000 00000000
0xB0C008C4
DMA0_B35
00000000 00000000 00110011 01111111
0xB0C008C8
DMA0_SA35
00000000 00000000 00000000 00000000
0xB0C008CC
DMA0_DA35
00000000 00000000 00000000 00000000
0xB0C008D0
DMA0_C35
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C008D4
DMA0_D35
00000000 XXXXXXXX 00000000 XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 286
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C008D8
DMA0_SASHDW35
00000000 00000000 00000000 00000000
0xB0C008DC
DMA0_DASHDW35
00000000 00000000 00000000 00000000
0xB0C008E0B0C008FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00900
DMA0_A36
00000000 00001111 00000000 00000000
0xB0C00904
DMA0_B36
00000000 00000000 00110011 01111111
0xB0C00908
DMA0_SA36
00000000 00000000 00000000 00000000
0xB0C0090C
DMA0_DA36
00000000 00000000 00000000 00000000
0xB0C00910
DMA0_C36
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00914
DMA0_D36
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00918
DMA0_SASHDW36
00000000 00000000 00000000 00000000
0xB0C0091C
DMA0_DASHDW36
00000000 00000000 00000000 00000000
0xB0C00920B0C0093C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00940
DMA0_A37
00000000 00001111 00000000 00000000
0xB0C00944
DMA0_B37
00000000 00000000 00110011 01111111
0xB0C00948
DMA0_SA37
00000000 00000000 00000000 00000000
0xB0C0094C
DMA0_DA37
00000000 00000000 00000000 00000000
0xB0C00950
DMA0_C37
XXXXXXXX XXXXXXXX 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 287
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00954
DMA0_D37
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00958
DMA0_SASHDW37
00000000 00000000 00000000 00000000
0xB0C0095C
DMA0_DASHDW37
00000000 00000000 00000000 00000000
0xB0C00960B0C0097C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00980
DMA0_A38
00000000 00001111 00000000 00000000
0xB0C00984
DMA0_B38
00000000 00000000 00110011 01111111
0xB0C00988
DMA0_SA38
00000000 00000000 00000000 00000000
0xB0C0098C
DMA0_DA38
00000000 00000000 00000000 00000000
0xB0C00990
DMA0_C38
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00994
DMA0_D38
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00998
DMA0_SASHDW38
00000000 00000000 00000000 00000000
0xB0C0099C
DMA0_DASHDW38
00000000 00000000 00000000 00000000
0xB0C009A0B0C009BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C009C0
DMA0_A39
00000000 00001111 00000000 00000000
0xB0C009C4
DMA0_B39
00000000 00000000 00110011 01111111
0xB0C009C8
DMA0_SA39
00000000 00000000 00000000 00000000
0xB0C009CC
DMA0_DA39
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 288
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C009D0
DMA0_C39
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C009D4
DMA0_D39
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C009D8
DMA0_SASHDW39
00000000 00000000 00000000 00000000
0xB0C009DC
DMA0_DASHDW39
00000000 00000000 00000000 00000000
0xB0C009E0B0C009FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00A00
DMA0_A40
00000000 00001111 00000000 00000000
0xB0C00A04
DMA0_B40
00000000 00000000 00110011 01111111
0xB0C00A08
DMA0_SA40
00000000 00000000 00000000 00000000
0xB0C00A0C
DMA0_DA40
00000000 00000000 00000000 00000000
0xB0C00A10
DMA0_C40
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A14
DMA0_D40
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A18
DMA0_SASHDW40
00000000 00000000 00000000 00000000
0xB0C00A1C
DMA0_DASHDW40
00000000 00000000 00000000 00000000
0xB0C00A20B0C00A3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00A40
DMA0_A41
00000000 00001111 00000000 00000000
0xB0C00A44
DMA0_B41
00000000 00000000 00110011 01111111
0xB0C00A48
DMA0_SA41
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 289
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00A4C
DMA0_DA41
00000000 00000000 00000000 00000000
0xB0C00A50
DMA0_C41
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A54
DMA0_D41
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A58
DMA0_SASHDW41
00000000 00000000 00000000 00000000
0xB0C00A5C
DMA0_DASHDW41
00000000 00000000 00000000 00000000
0xB0C00A60B0C00A7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00A80
DMA0_A42
00000000 00001111 00000000 00000000
0xB0C00A84
DMA0_B42
00000000 00000000 00110011 01111111
0xB0C00A88
DMA0_SA42
00000000 00000000 00000000 00000000
0xB0C00A8C
DMA0_DA42
00000000 00000000 00000000 00000000
0xB0C00A90
DMA0_C42
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A94
DMA0_D42
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A98
DMA0_SASHDW42
00000000 00000000 00000000 00000000
0xB0C00A9C
DMA0_DASHDW42
00000000 00000000 00000000 00000000
0xB0C00AA0B0C00ABC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00AC0
DMA0_A43
00000000 00001111 00000000 00000000
0xB0C00AC4
DMA0_B43
00000000 00000000 00110011 01111111
Document Number: DS707-00002-4v1-E
+0
Page 290
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00AC8
DMA0_SA43
00000000 00000000 00000000 00000000
0xB0C00ACC
DMA0_DA43
00000000 00000000 00000000 00000000
0xB0C00AD0
DMA0_C43
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00AD4
DMA0_D43
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00AD8
DMA0_SASHDW43
00000000 00000000 00000000 00000000
0xB0C00ADC
DMA0_DASHDW43
00000000 00000000 00000000 00000000
0xB0C00AE0B0C00AFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B00
DMA0_A44
00000000 00001111 00000000 00000000
0xB0C00B04
DMA0_B44
00000000 00000000 00110011 01111111
0xB0C00B08
DMA0_SA44
00000000 00000000 00000000 00000000
0xB0C00B0C
DMA0_DA44
00000000 00000000 00000000 00000000
0xB0C00B10
DMA0_C44
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B14
DMA0_D44
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00B18
DMA0_SASHDW44
00000000 00000000 00000000 00000000
0xB0C00B1C
DMA0_DASHDW44
00000000 00000000 00000000 00000000
0xB0C00B20B0C00B3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B40
DMA0_A45
00000000 00001111 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 291
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00B44
DMA0_B45
00000000 00000000 00110011 01111111
0xB0C00B48
DMA0_SA45
00000000 00000000 00000000 00000000
0xB0C00B4C
DMA0_DA45
00000000 00000000 00000000 00000000
0xB0C00B50
DMA0_C45
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B54
DMA0_D45
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00B58
DMA0_SASHDW45
00000000 00000000 00000000 00000000
0xB0C00B5C
DMA0_DASHDW45
00000000 00000000 00000000 00000000
0xB0C00B60B0C00B7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B80
DMA0_A46
00000000 00001111 00000000 00000000
0xB0C00B84
DMA0_B46
00000000 00000000 00110011 01111111
0xB0C00B88
DMA0_SA46
00000000 00000000 00000000 00000000
0xB0C00B8C
DMA0_DA46
00000000 00000000 00000000 00000000
0xB0C00B90
DMA0_C46
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B94
DMA0_D46
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00B98
DMA0_SASHDW46
00000000 00000000 00000000 00000000
0xB0C00B9C
DMA0_DASHDW46
00000000 00000000 00000000 00000000
0xB0C00BA0B0C00BBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 292
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00BC0
DMA0_A47
00000000 00001111 00000000 00000000
0xB0C00BC4
DMA0_B47
00000000 00000000 00110011 01111111
0xB0C00BC8
DMA0_SA47
00000000 00000000 00000000 00000000
0xB0C00BCC
DMA0_DA47
00000000 00000000 00000000 00000000
0xB0C00BD0
DMA0_C47
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00BD4
DMA0_D47
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00BD8
DMA0_SASHDW47
00000000 00000000 00000000 00000000
0xB0C00BDC
DMA0_DASHDW47
00000000 00000000 00000000 00000000
0xB0C00BE0B0C00BFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00C00
DMA0_A48
00000000 00001111 00000000 00000000
0xB0C00C04
DMA0_B48
00000000 00000000 00110011 01111111
0xB0C00C08
DMA0_SA48
00000000 00000000 00000000 00000000
0xB0C00C0C
DMA0_DA48
00000000 00000000 00000000 00000000
0xB0C00C10
DMA0_C48
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C14
DMA0_D48
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C18
DMA0_SASHDW48
00000000 00000000 00000000 00000000
0xB0C00C1C
DMA0_DASHDW48
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 293
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00C20B0C00C3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00C40
DMA0_A49
00000000 00001111 00000000 00000000
0xB0C00C44
DMA0_B49
00000000 00000000 00110011 01111111
0xB0C00C48
DMA0_SA49
00000000 00000000 00000000 00000000
0xB0C00C4C
DMA0_DA49
00000000 00000000 00000000 00000000
0xB0C00C50
DMA0_C49
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C54
DMA0_D49
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C58
DMA0_SASHDW49
00000000 00000000 00000000 00000000
0xB0C00C5C
DMA0_DASHDW49
00000000 00000000 00000000 00000000
0xB0C00C60B0C00C7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00C80
DMA0_A50
00000000 00001111 00000000 00000000
0xB0C00C84
DMA0_B50
00000000 00000000 00110011 01111111
0xB0C00C88
DMA0_SA50
00000000 00000000 00000000 00000000
0xB0C00C8C
DMA0_DA50
00000000 00000000 00000000 00000000
0xB0C00C90
DMA0_C50
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C94
DMA0_D50
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C98
DMA0_SASHDW50
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 294
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00C9C
DMA0_DASHDW50
00000000 00000000 00000000 00000000
0xB0C00CA0B0C00CBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00CC0
DMA0_A51
00000000 00001111 00000000 00000000
0xB0C00CC4
DMA0_B51
00000000 00000000 00110011 01111111
0xB0C00CC8
DMA0_SA51
00000000 00000000 00000000 00000000
0xB0C00CCC
DMA0_DA51
00000000 00000000 00000000 00000000
0xB0C00CD0
DMA0_C51
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00CD4
DMA0_D51
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00CD8
DMA0_SASHDW51
00000000 00000000 00000000 00000000
0xB0C00CDC
DMA0_DASHDW51
00000000 00000000 00000000 00000000
0xB0C00CE0B0C00CFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D00
DMA0_A52
00000000 00001111 00000000 00000000
0xB0C00D04
DMA0_B52
00000000 00000000 00110011 01111111
0xB0C00D08
DMA0_SA52
00000000 00000000 00000000 00000000
0xB0C00D0C
DMA0_DA52
00000000 00000000 00000000 00000000
0xB0C00D10
DMA0_C52
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00D14
DMA0_D52
00000000 XXXXXXXX 00000000 XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 295
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00D18
DMA0_SASHDW52
00000000 00000000 00000000 00000000
0xB0C00D1C
DMA0_DASHDW52
00000000 00000000 00000000 00000000
0xB0C00D20B0C00D3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D40
DMA0_A53
00000000 00001111 00000000 00000000
0xB0C00D44
DMA0_B53
00000000 00000000 00110011 01111111
0xB0C00D48
DMA0_SA53
00000000 00000000 00000000 00000000
0xB0C00D4C
DMA0_DA53
00000000 00000000 00000000 00000000
0xB0C00D50
DMA0_C53
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00D54
DMA0_D53
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00D58
DMA0_SASHDW53
00000000 00000000 00000000 00000000
0xB0C00D5C
DMA0_DASHDW53
00000000 00000000 00000000 00000000
0xB0C00D60B0C00D7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D80
DMA0_A54
00000000 00001111 00000000 00000000
0xB0C00D84
DMA0_B54
00000000 00000000 00110011 01111111
0xB0C00D88
DMA0_SA54
00000000 00000000 00000000 00000000
0xB0C00D8C
DMA0_DA54
00000000 00000000 00000000 00000000
0xB0C00D90
DMA0_C54
XXXXXXXX XXXXXXXX 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 296
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00D94
DMA0_D54
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00D98
DMA0_SASHDW54
00000000 00000000 00000000 00000000
0xB0C00D9C
DMA0_DASHDW54
00000000 00000000 00000000 00000000
0xB0C00DA0B0C00DBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00DC0
DMA0_A55
00000000 00001111 00000000 00000000
0xB0C00DC4
DMA0_B55
00000000 00000000 00110011 01111111
0xB0C00DC8
DMA0_SA55
00000000 00000000 00000000 00000000
0xB0C00DCC
DMA0_DA55
00000000 00000000 00000000 00000000
0xB0C00DD0
DMA0_C55
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00DD4
DMA0_D55
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00DD8
DMA0_SASHDW55
00000000 00000000 00000000 00000000
0xB0C00DDC
DMA0_DASHDW55
00000000 00000000 00000000 00000000
0xB0C00DE0B0C00DFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00E00
DMA0_A56
00000000 00001111 00000000 00000000
0xB0C00E04
DMA0_B56
00000000 00000000 00110011 01111111
0xB0C00E08
DMA0_SA56
00000000 00000000 00000000 00000000
0xB0C00E0C
DMA0_DA56
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 297
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00E10
DMA0_C56
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E14
DMA0_D56
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E18
DMA0_SASHDW56
00000000 00000000 00000000 00000000
0xB0C00E1C
DMA0_DASHDW56
00000000 00000000 00000000 00000000
0xB0C00E20B0C00E3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00E40
DMA0_A57
00000000 00001111 00000000 00000000
0xB0C00E44
DMA0_B57
00000000 00000000 00110011 01111111
0xB0C00E48
DMA0_SA57
00000000 00000000 00000000 00000000
0xB0C00E4C
DMA0_DA57
00000000 00000000 00000000 00000000
0xB0C00E50
DMA0_C57
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E54
DMA0_D57
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E58
DMA0_SASHDW57
00000000 00000000 00000000 00000000
0xB0C00E5C
DMA0_DASHDW57
00000000 00000000 00000000 00000000
0xB0C00E60B0C00E7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00E80
DMA0_A58
00000000 00001111 00000000 00000000
0xB0C00E84
DMA0_B58
00000000 00000000 00110011 01111111
0xB0C00E88
DMA0_SA58
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 298
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00E8C
DMA0_DA58
00000000 00000000 00000000 00000000
0xB0C00E90
DMA0_C58
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E94
DMA0_D58
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E98
DMA0_SASHDW58
00000000 00000000 00000000 00000000
0xB0C00E9C
DMA0_DASHDW58
00000000 00000000 00000000 00000000
0xB0C00EA0B0C00EBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00EC0
DMA0_A59
00000000 00001111 00000000 00000000
0xB0C00EC4
DMA0_B59
00000000 00000000 00110011 01111111
0xB0C00EC8
DMA0_SA59
00000000 00000000 00000000 00000000
0xB0C00ECC
DMA0_DA59
00000000 00000000 00000000 00000000
0xB0C00ED0
DMA0_C59
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00ED4
DMA0_D59
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00ED8
DMA0_SASHDW59
00000000 00000000 00000000 00000000
0xB0C00EDC
DMA0_DASHDW59
00000000 00000000 00000000 00000000
0xB0C00EE0B0C00EFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F00
DMA0_A60
00000000 00001111 00000000 00000000
0xB0C00F04
DMA0_B60
00000000 00000000 00110011 01111111
Document Number: DS707-00002-4v1-E
+0
Page 299
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00F08
DMA0_SA60
00000000 00000000 00000000 00000000
0xB0C00F0C
DMA0_DA60
00000000 00000000 00000000 00000000
0xB0C00F10
DMA0_C60
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F14
DMA0_D60
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00F18
DMA0_SASHDW60
00000000 00000000 00000000 00000000
0xB0C00F1C
DMA0_DASHDW60
00000000 00000000 00000000 00000000
0xB0C00F20B0C00F3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F40
DMA0_A61
00000000 00001111 00000000 00000000
0xB0C00F44
DMA0_B61
00000000 00000000 00110011 01111111
0xB0C00F48
DMA0_SA61
00000000 00000000 00000000 00000000
0xB0C00F4C
DMA0_DA61
00000000 00000000 00000000 00000000
0xB0C00F50
DMA0_C61
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F54
DMA0_D61
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00F58
DMA0_SASHDW61
00000000 00000000 00000000 00000000
0xB0C00F5C
DMA0_DASHDW61
00000000 00000000 00000000 00000000
0xB0C00F60B0C00F7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F80
DMA0_A62
00000000 00001111 00000000 00000000
Document Number: DS707-00002-4v1-E
+0
Page 300
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C00F84
DMA0_B62
00000000 00000000 00110011 01111111
0xB0C00F88
DMA0_SA62
00000000 00000000 00000000 00000000
0xB0C00F8C
DMA0_DA62
00000000 00000000 00000000 00000000
0xB0C00F90
DMA0_C62
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F94
DMA0_D62
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00F98
DMA0_SASHDW62
00000000 00000000 00000000 00000000
0xB0C00F9C
DMA0_DASHDW62
00000000 00000000 00000000 00000000
0xB0C00FA0B0C00FBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00FC0
DMA0_A63
00000000 00001111 00000000 00000000
0xB0C00FC4
DMA0_B63
00000000 00000000 00110011 01111111
0xB0C00FC8
DMA0_SA63
00000000 00000000 00000000 00000000
0xB0C00FCC
DMA0_DA63
00000000 00000000 00000000 00000000
0xB0C00FD0
DMA0_C63
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00FD4
DMA0_D63
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00FD8
DMA0_SASHDW63
00000000 00000000 00000000 00000000
0xB0C00FDC
DMA0_DASHDW63
00000000 00000000 00000000 00000000
0xB0C00FE0B0C00FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 301
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C01000
DMA0_R
01000000 XXXXXXXX XXXXXXXX 00000001
0xB0C01004
DMA0_DIRQ1
00000000 00000000 00000000 00000000
0xB0C01008
DMA0_DIRQ2
00000000 00000000 00000000 00000000
0xB0C0100C
DMA0_EDIRQ1
00000000 00000000 00000000 00000000
0xB0C01010
DMA0_EDIRQ2
00000000 00000000 00000000 00000000
0xB0C01014
DMA0_ID
00000000 00000000 00000000 00000000
0xB0C01018B0C01FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02000
DMA0_CMECIC0
00000000 00000000 XXXXXXXX 00000000
0xB0C02004
DMA0_CMECIC1
00000000 00000000 XXXXXXXX 00000000
0xB0C02008
DMA0_CMECIC2
00000000 00000000 XXXXXXXX 00000000
0xB0C0200C
DMA0_CMECIC3
00000000 00000000 XXXXXXXX 00000000
0xB0C02010
DMA0_CMECIC4
00000000 00000000 XXXXXXXX 00000000
0xB0C02014
DMA0_CMECIC5
00000000 00000000 XXXXXXXX 00000000
0xB0C02018
DMA0_CMECIC6
00000000 00000000 XXXXXXXX 00000000
0xB0C0201C
DMA0_CMECIC7
00000000 00000000 XXXXXXXX 00000000
0xB0C02020
DMA0_CMICIC0
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02024
DMA0_CMICIC1
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 302
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02028
DMA0_CMICIC2
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0202C
DMA0_CMICIC3
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02030
DMA0_CMICIC4
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02034
DMA0_CMICIC5
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02038
DMA0_CMICIC6
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0203C
DMA0_CMICIC7
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02040
DMA0_CMICIC8
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02044
DMA0_CMICIC9
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02048
DMA0_CMICIC10
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0204C
DMA0_CMICIC11
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02050
DMA0_CMICIC12
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02054
DMA0_CMICIC13
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02058
DMA0_CMICIC14
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0205C
DMA0_CMICIC15
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02060
DMA0_CMICIC16
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02064
DMA0_CMICIC17
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02068
DMA0_CMICIC18
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 303
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0206C
DMA0_CMICIC19
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02070
DMA0_CMICIC20
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02074
DMA0_CMICIC21
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02078
DMA0_CMICIC22
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0207C
DMA0_CMICIC23
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02080
DMA0_CMICIC24
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02084
DMA0_CMICIC25
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02088
DMA0_CMICIC26
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0208C
DMA0_CMICIC27
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02090
DMA0_CMICIC28
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02094
DMA0_CMICIC29
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02098
DMA0_CMICIC30
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0209C
DMA0_CMICIC31
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A0
DMA0_CMICIC32
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A4
DMA0_CMICIC33
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A8
DMA0_CMICIC34
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020AC
DMA0_CMICIC35
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 304
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C020B0
DMA0_CMICIC36
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020B4
DMA0_CMICIC37
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020B8
DMA0_CMICIC38
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020BC
DMA0_CMICIC39
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C0
DMA0_CMICIC40
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C4
DMA0_CMICIC41
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C8
DMA0_CMICIC42
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020CC
DMA0_CMICIC43
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D0
DMA0_CMICIC44
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D4
DMA0_CMICIC45
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D8
DMA0_CMICIC46
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020DC
DMA0_CMICIC47
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E0
DMA0_CMICIC48
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E4
DMA0_CMICIC49
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E8
DMA0_CMICIC50
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020EC
DMA0_CMICIC51
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020F0
DMA0_CMICIC52
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 305
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C020F4
DMA0_CMICIC53
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020F8
DMA0_CMICIC54
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020FC
DMA0_CMICIC55
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02100
DMA0_CMICIC56
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02104
DMA0_CMICIC57
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02108
DMA0_CMICIC58
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0210C
DMA0_CMICIC59
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02110
DMA0_CMICIC60
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02114
DMA0_CMICIC61
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02118
DMA0_CMICIC62
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0211C
DMA0_CMICIC63
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02120
DMA0_CMICIC64
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02124
DMA0_CMICIC65
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02128
DMA0_CMICIC66
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0212C
DMA0_CMICIC67
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02130
DMA0_CMICIC68
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02134
DMA0_CMICIC69
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 306
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02138
DMA0_CMICIC70
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0213C
DMA0_CMICIC71
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02140
DMA0_CMICIC72
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02144
DMA0_CMICIC73
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02148
DMA0_CMICIC74
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0214C
DMA0_CMICIC75
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02150
DMA0_CMICIC76
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02154
DMA0_CMICIC77
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02158
DMA0_CMICIC78
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0215C
DMA0_CMICIC79
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02160
DMA0_CMICIC80
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02164
DMA0_CMICIC81
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02168
DMA0_CMICIC82
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0216C
DMA0_CMICIC83
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02170
DMA0_CMICIC84
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02174
DMA0_CMICIC85
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02178
DMA0_CMICIC86
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 307
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0217C
DMA0_CMICIC87
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02180
DMA0_CMICIC88
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02184
DMA0_CMICIC89
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02188
DMA0_CMICIC90
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0218C
DMA0_CMICIC91
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02190
DMA0_CMICIC92
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02194
DMA0_CMICIC93
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02198
DMA0_CMICIC94
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0219C
DMA0_CMICIC95
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A0
DMA0_CMICIC96
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A4
DMA0_CMICIC97
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A8
DMA0_CMICIC98
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021AC
DMA0_CMICIC99
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021B0
DMA0_CMICIC100
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021B4
DMA0_CMICIC101
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021B8
DMA0_CMICIC102
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021BC
DMA0_CMICIC103
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 308
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C021C0
DMA0_CMICIC104
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021C4
DMA0_CMICIC105
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021C8
DMA0_CMICIC106
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021CC
DMA0_CMICIC107
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D0
DMA0_CMICIC108
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D4
DMA0_CMICIC109
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D8
DMA0_CMICIC110
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021DC
DMA0_CMICIC111
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E0
DMA0_CMICIC112
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E4
DMA0_CMICIC113
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E8
DMA0_CMICIC114
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021EC
DMA0_CMICIC115
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F0
DMA0_CMICIC116
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F4
DMA0_CMICIC117
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F8
DMA0_CMICIC118
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021FC
DMA0_CMICIC119
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02200
DMA0_CMICIC120
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 309
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02204
DMA0_CMICIC121
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02208
DMA0_CMICIC122
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0220C
DMA0_CMICIC123
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02210
DMA0_CMICIC124
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02214
DMA0_CMICIC125
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02218
DMA0_CMICIC126
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0221C
DMA0_CMICIC127
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02220
DMA0_CMICIC128
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02224
DMA0_CMICIC129
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02228
DMA0_CMICIC130
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0222C
DMA0_CMICIC131
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02230
DMA0_CMICIC132
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02234
DMA0_CMICIC133
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02238
DMA0_CMICIC134
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0223C
DMA0_CMICIC135
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02240
DMA0_CMICIC136
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02244
DMA0_CMICIC137
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 310
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02248
DMA0_CMICIC138
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0224C
DMA0_CMICIC139
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02250
DMA0_CMICIC140
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02254
DMA0_CMICIC141
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02258
DMA0_CMICIC142
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0225C
DMA0_CMICIC143
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02260
DMA0_CMICIC144
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02264
DMA0_CMICIC145
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02268
DMA0_CMICIC146
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0226C
DMA0_CMICIC147
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02270
DMA0_CMICIC148
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02274
DMA0_CMICIC149
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02278
DMA0_CMICIC150
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0227C
DMA0_CMICIC151
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02280
DMA0_CMICIC152
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02284
DMA0_CMICIC153
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02288
DMA0_CMICIC154
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 311
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0228C
DMA0_CMICIC155
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02290
DMA0_CMICIC156
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02294
DMA0_CMICIC157
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02298
DMA0_CMICIC158
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0229C
DMA0_CMICIC159
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A0
DMA0_CMICIC160
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A4
DMA0_CMICIC161
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A8
DMA0_CMICIC162
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022AC
DMA0_CMICIC163
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022B0
DMA0_CMICIC164
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022B4
DMA0_CMICIC165
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022B8
DMA0_CMICIC166
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022BC
DMA0_CMICIC167
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C0
DMA0_CMICIC168
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C4
DMA0_CMICIC169
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C8
DMA0_CMICIC170
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022CC
DMA0_CMICIC171
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 312
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C022D0
DMA0_CMICIC172
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022D4
DMA0_CMICIC173
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022D8
DMA0_CMICIC174
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022DC
DMA0_CMICIC175
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E0
DMA0_CMICIC176
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E4
DMA0_CMICIC177
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E8
DMA0_CMICIC178
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022EC
DMA0_CMICIC179
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F0
DMA0_CMICIC180
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F4
DMA0_CMICIC181
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F8
DMA0_CMICIC182
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022FC
DMA0_CMICIC183
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02300
DMA0_CMICIC184
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02304
DMA0_CMICIC185
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02308
DMA0_CMICIC186
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0230C
DMA0_CMICIC187
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02310
DMA0_CMICIC188
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 313
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02314
DMA0_CMICIC189
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02318
DMA0_CMICIC190
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0231C
DMA0_CMICIC191
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02320
DMA0_CMICIC192
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02324
DMA0_CMICIC193
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02328
DMA0_CMICIC194
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0232C
DMA0_CMICIC195
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02330
DMA0_CMICIC196
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02334
DMA0_CMICIC197
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02338
DMA0_CMICIC198
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0233C
DMA0_CMICIC199
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02340
DMA0_CMICIC200
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02344
DMA0_CMICIC201
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02348
DMA0_CMICIC202
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0234C
DMA0_CMICIC203
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02350
DMA0_CMICIC204
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02354
DMA0_CMICIC205
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 314
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02358
DMA0_CMICIC206
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0235C
DMA0_CMICIC207
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02360
DMA0_CMICIC208
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02364
DMA0_CMICIC209
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02368
DMA0_CMICIC210
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0236C
DMA0_CMICIC211
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02370
DMA0_CMICIC212
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02374
DMA0_CMICIC213
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02378
DMA0_CMICIC214
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0237C
DMA0_CMICIC215
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02380
DMA0_CMICIC216
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02384
DMA0_CMICIC217
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02388
DMA0_CMICIC218
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0238C
DMA0_CMICIC219
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02390
DMA0_CMICIC220
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02394
DMA0_CMICIC221
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02398
DMA0_CMICIC222
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 315
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0239C
DMA0_CMICIC223
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A0
DMA0_CMICIC224
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A4
DMA0_CMICIC225
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A8
DMA0_CMICIC226
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023AC
DMA0_CMICIC227
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023B0
DMA0_CMICIC228
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023B4
DMA0_CMICIC229
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023B8
DMA0_CMICIC230
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023BC
DMA0_CMICIC231
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C0
DMA0_CMICIC232
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C4
DMA0_CMICIC233
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C8
DMA0_CMICIC234
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023CC
DMA0_CMICIC235
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D0
DMA0_CMICIC236
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D4
DMA0_CMICIC237
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D8
DMA0_CMICIC238
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023DC
DMA0_CMICIC239
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 316
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C023E0
DMA0_CMICIC240
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023E4
DMA0_CMICIC241
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023E8
DMA0_CMICIC242
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023EC
DMA0_CMICIC243
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F0
DMA0_CMICIC244
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F4
DMA0_CMICIC245
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F8
DMA0_CMICIC246
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023FC
DMA0_CMICIC247
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02400
DMA0_CMICIC248
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02404
DMA0_CMICIC249
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02408
DMA0_CMICIC250
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0240C
DMA0_CMICIC251
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02410
DMA0_CMICIC252
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02414
DMA0_CMICIC253
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02418
DMA0_CMICIC254
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0241C
DMA0_CMICIC255
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02420
DMA0_CMICIC256
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 317
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02424
DMA0_CMICIC257
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02428
DMA0_CMICIC258
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0242C
DMA0_CMICIC259
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02430
DMA0_CMICIC260
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02434
DMA0_CMICIC261
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02438
DMA0_CMICIC262
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0243C
DMA0_CMICIC263
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02440
DMA0_CMICIC264
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02444
DMA0_CMICIC265
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02448
DMA0_CMICIC266
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0244C
DMA0_CMICIC267
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02450
DMA0_CMICIC268
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02454
DMA0_CMICIC269
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02458
DMA0_CMICIC270
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0245C
DMA0_CMICIC271
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02460
DMA0_CMICIC272
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02464
DMA0_CMICIC273
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 318
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02468
DMA0_CMICIC274
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0246C
DMA0_CMICIC275
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02470
DMA0_CMICIC276
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02474
DMA0_CMICIC277
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02478
DMA0_CMICIC278
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0247C
DMA0_CMICIC279
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02480
DMA0_CMICIC280
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02484
DMA0_CMICIC281
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02488
DMA0_CMICIC282
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0248C
DMA0_CMICIC283
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02490
DMA0_CMICIC284
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02494
DMA0_CMICIC285
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02498
DMA0_CMICIC286
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0249C
DMA0_CMICIC287
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A0
DMA0_CMICIC288
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A4
DMA0_CMICIC289
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A8
DMA0_CMICIC290
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 319
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C024AC
DMA0_CMICIC291
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B0
DMA0_CMICIC292
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B4
DMA0_CMICIC293
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B8
DMA0_CMICIC294
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024BC
DMA0_CMICIC295
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C0
DMA0_CMICIC296
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C4
DMA0_CMICIC297
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C8
DMA0_CMICIC298
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024CC
DMA0_CMICIC299
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D0
DMA0_CMICIC300
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D4
DMA0_CMICIC301
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D8
DMA0_CMICIC302
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024DC
DMA0_CMICIC303
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E0
DMA0_CMICIC304
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E4
DMA0_CMICIC305
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E8
DMA0_CMICIC306
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024EC
DMA0_CMICIC307
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 320
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C024F0
DMA0_CMICIC308
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024F4
DMA0_CMICIC309
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024F8
DMA0_CMICIC310
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024FC
DMA0_CMICIC311
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02500
DMA0_CMICIC312
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02504
DMA0_CMICIC313
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02508
DMA0_CMICIC314
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0250C
DMA0_CMICIC315
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02510
DMA0_CMICIC316
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02514
DMA0_CMICIC317
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02518
DMA0_CMICIC318
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0251C
DMA0_CMICIC319
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02520
DMA0_CMICIC320
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02524
DMA0_CMICIC321
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02528
DMA0_CMICIC322
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0252C
DMA0_CMICIC323
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02530
DMA0_CMICIC324
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 321
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02534
DMA0_CMICIC325
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02538
DMA0_CMICIC326
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0253C
DMA0_CMICIC327
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02540
DMA0_CMICIC328
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02544
DMA0_CMICIC329
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02548
DMA0_CMICIC330
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0254C
DMA0_CMICIC331
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02550
DMA0_CMICIC332
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02554
DMA0_CMICIC333
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02558
DMA0_CMICIC334
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0255C
DMA0_CMICIC335
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02560
DMA0_CMICIC336
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02564
DMA0_CMICIC337
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02568
DMA0_CMICIC338
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0256C
DMA0_CMICIC339
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02570
DMA0_CMICIC340
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02574
DMA0_CMICIC341
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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Page 322
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02578
DMA0_CMICIC342
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0257C
DMA0_CMICIC343
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02580
DMA0_CMICIC344
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02584
DMA0_CMICIC345
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02588
DMA0_CMICIC346
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0258C
DMA0_CMICIC347
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02590
DMA0_CMICIC348
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02594
DMA0_CMICIC349
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02598
DMA0_CMICIC350
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0259C
DMA0_CMICIC351
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025A0
DMA0_CMICIC352
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025A4
DMA0_CMICIC353
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025A8
DMA0_CMICIC354
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025AC
DMA0_CMICIC355
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B0
DMA0_CMICIC356
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B4
DMA0_CMICIC357
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B8
DMA0_CMICIC358
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 323
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C025BC
DMA0_CMICIC359
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C0
DMA0_CMICIC360
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C4
DMA0_CMICIC361
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C8
DMA0_CMICIC362
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025CC
DMA0_CMICIC363
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D0
DMA0_CMICIC364
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D4
DMA0_CMICIC365
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D8
DMA0_CMICIC366
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025DC
DMA0_CMICIC367
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E0
DMA0_CMICIC368
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E4
DMA0_CMICIC369
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E8
DMA0_CMICIC370
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025EC
DMA0_CMICIC371
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F0
DMA0_CMICIC372
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F4
DMA0_CMICIC373
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F8
DMA0_CMICIC374
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025FC
DMA0_CMICIC375
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 324
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02600
DMA0_CMICIC376
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02604
DMA0_CMICIC377
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02608
DMA0_CMICIC378
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0260C
DMA0_CMICIC379
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02610
DMA0_CMICIC380
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02614
DMA0_CMICIC381
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02618
DMA0_CMICIC382
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0261C
DMA0_CMICIC383
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02620
DMA0_CMICIC384
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02624
DMA0_CMICIC385
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02628
DMA0_CMICIC386
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0262C
DMA0_CMICIC387
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02630
DMA0_CMICIC388
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02634
DMA0_CMICIC389
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02638
DMA0_CMICIC390
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0263C
DMA0_CMICIC391
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02640
DMA0_CMICIC392
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 325
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02644
DMA0_CMICIC393
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02648
DMA0_CMICIC394
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0264C
DMA0_CMICIC395
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02650
DMA0_CMICIC396
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02654
DMA0_CMICIC397
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02658
DMA0_CMICIC398
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0265C
DMA0_CMICIC399
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02660
DMA0_CMICIC400
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02664
DMA0_CMICIC401
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02668
DMA0_CMICIC402
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0266C
DMA0_CMICIC403
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02670
DMA0_CMICIC404
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02674
DMA0_CMICIC405
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02678
DMA0_CMICIC406
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0267C
DMA0_CMICIC407
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02680
DMA0_CMICIC408
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02684
DMA0_CMICIC409
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 326
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02688
DMA0_CMICIC410
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0268C
DMA0_CMICIC411
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02690
DMA0_CMICIC412
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02694
DMA0_CMICIC413
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02698
DMA0_CMICIC414
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0269C
DMA0_CMICIC415
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026A0
DMA0_CMICIC416
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026A4
DMA0_CMICIC417
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026A8
DMA0_CMICIC418
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026AC
DMA0_CMICIC419
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B0
DMA0_CMICIC420
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B4
DMA0_CMICIC421
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B8
DMA0_CMICIC422
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026BC
DMA0_CMICIC423
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C0
DMA0_CMICIC424
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C4
DMA0_CMICIC425
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C8
DMA0_CMICIC426
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 327
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C026CC
DMA0_CMICIC427
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D0
DMA0_CMICIC428
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D4
DMA0_CMICIC429
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D8
DMA0_CMICIC430
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026DC
DMA0_CMICIC431
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E0
DMA0_CMICIC432
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E4
DMA0_CMICIC433
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E8
DMA0_CMICIC434
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026EC
DMA0_CMICIC435
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026F0
DMA0_CMICIC436
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026F4
DMA0_CMICIC437
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026F8
DMA0_CMICIC438
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026FC
DMA0_CMICIC439
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02700
DMA0_CMICIC440
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02704
DMA0_CMICIC441
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02708
DMA0_CMICIC442
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0270C
DMA0_CMICIC443
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
+0
Page 328
MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02710
DMA0_CMICIC444
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02714
DMA0_CMICIC445
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02718
DMA0_CMICIC446
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0271C
DMA0_CMICIC447
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02720
DMA0_CMICIC448
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02724
DMA0_CMICIC449
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02728
DMA0_CMICIC450
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0272C
DMA0_CMICIC451
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02730
DMA0_CMICIC452
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02734
DMA0_CMICIC453
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02738
DMA0_CMICIC454
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0273C
DMA0_CMICIC455
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02740
DMA0_CMICIC456
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02744
DMA0_CMICIC457
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02748
DMA0_CMICIC458
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0274C
DMA0_CMICIC459
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02750
DMA0_CMICIC460
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02754
DMA0_CMICIC461
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02758
DMA0_CMICIC462
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0275C
DMA0_CMICIC463
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02760
DMA0_CMICIC464
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02764
DMA0_CMICIC465
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02768
DMA0_CMICIC466
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0276C
DMA0_CMICIC467
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02770
DMA0_CMICIC468
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02774
DMA0_CMICIC469
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02778
DMA0_CMICIC470
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0277C
DMA0_CMICIC471
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02780
DMA0_CMICIC472
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02784
DMA0_CMICIC473
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02788
DMA0_CMICIC474
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0278C
DMA0_CMICIC475
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02790
DMA0_CMICIC476
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02794
DMA0_CMICIC477
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02798
DMA0_CMICIC478
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0279C
DMA0_CMICIC479
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027A0
DMA0_CMICIC480
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027A4
DMA0_CMICIC481
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027A8
DMA0_CMICIC482
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027AC
DMA0_CMICIC483
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B0
DMA0_CMICIC484
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B4
DMA0_CMICIC485
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B8
DMA0_CMICIC486
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027BC
DMA0_CMICIC487
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C0
DMA0_CMICIC488
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C4
DMA0_CMICIC489
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C8
DMA0_CMICIC490
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027CC
DMA0_CMICIC491
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D0
DMA0_CMICIC492
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D4
DMA0_CMICIC493
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D8
DMA0_CMICIC494
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C027DC
DMA0_CMICIC495
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E0
DMA0_CMICIC496
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E4
DMA0_CMICIC497
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E8
DMA0_CMICIC498
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027EC
DMA0_CMICIC499
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027F0
DMA0_CMICIC500
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027F4
DMA0_CMICIC501
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027F8
DMA0_CMICIC502
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027FC
DMA0_CMICIC503
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02800
DMA0_CMCHIC0
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02804
DMA0_CMCHIC1
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02808
DMA0_CMCHIC2
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0280C
DMA0_CMCHIC3
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02810
DMA0_CMCHIC4
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02814
DMA0_CMCHIC5
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02818
DMA0_CMCHIC6
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0281C
DMA0_CMCHIC7
XXXXXXXX XXXXXXXX 00000000 00000010
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02820
DMA0_CMCHIC8
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02824
DMA0_CMCHIC9
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02828
DMA0_CMCHIC10
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0282C
DMA0_CMCHIC11
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02830
DMA0_CMCHIC12
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02834
DMA0_CMCHIC13
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02838
DMA0_CMCHIC14
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0283C
DMA0_CMCHIC15
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02840
DMA0_CMCHIC16
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02844
DMA0_CMCHIC17
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02848
DMA0_CMCHIC18
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0284C
DMA0_CMCHIC19
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02850
DMA0_CMCHIC20
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02854
DMA0_CMCHIC21
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02858
DMA0_CMCHIC22
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0285C
DMA0_CMCHIC23
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02860
DMA0_CMCHIC24
XXXXXXXX XXXXXXXX 00000000 00000010
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C02864
DMA0_CMCHIC25
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02868
DMA0_CMCHIC26
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0286C
DMA0_CMCHIC27
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02870
DMA0_CMCHIC28
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02874
DMA0_CMCHIC29
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02878
DMA0_CMCHIC30
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0287C
DMA0_CMCHIC31
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02880
DMA0_CMCHIC32
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02884
DMA0_CMCHIC33
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02888
DMA0_CMCHIC34
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0288C
DMA0_CMCHIC35
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02890
DMA0_CMCHIC36
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02894
DMA0_CMCHIC37
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02898
DMA0_CMCHIC38
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0289C
DMA0_CMCHIC39
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028A0
DMA0_CMCHIC40
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028A4
DMA0_CMCHIC41
XXXXXXXX XXXXXXXX 00000000 00000010
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C028A8
DMA0_CMCHIC42
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028AC
DMA0_CMCHIC43
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B0
DMA0_CMCHIC44
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B4
DMA0_CMCHIC45
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B8
DMA0_CMCHIC46
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028BC
DMA0_CMCHIC47
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C0
DMA0_CMCHIC48
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C4
DMA0_CMCHIC49
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C8
DMA0_CMCHIC50
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028CC
DMA0_CMCHIC51
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D0
DMA0_CMCHIC52
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D4
DMA0_CMCHIC53
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D8
DMA0_CMCHIC54
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028DC
DMA0_CMCHIC55
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E0
DMA0_CMCHIC56
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E4
DMA0_CMCHIC57
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E8
DMA0_CMCHIC58
XXXXXXXX XXXXXXXX 00000000 00000010
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C028EC
DMA0_CMCHIC59
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028F0
DMA0_CMCHIC60
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028F4
DMA0_CMCHIC61
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028F8
DMA0_CMCHIC62
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028FC
DMA0_CMCHIC63
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02900B0C07FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08000
MPUXDMA0_CTRL0
00000000 00000000 00000001 00000000
0xB0C08004
MPUXDMA0_NMIEN
XXXXXXXX XXXXXXXX XXXXXXXX 00000001
0xB0C08008
MPUXDMA0_WERRC
XXXXXXXX XXXXXXXX 00000XXX XXXXXXX0
0xB0C0800C
MPUXDMA0_WERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08010
MPUXDMA0_RERRC
XXXXXXXX XXXXXXXX 00000XXX XXXXXXX0
0xB0C08014
MPUXDMA0_RERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08018
MPUXDMA0_CTRL1
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C0801C
MPUXDMA0_SADDR1
00000000 00000000 00000000 00000000
0xB0C08020
MPUXDMA0_EADDR1
00000000 00000000 00000000 01111111
0xB0C08024
MPUXDMA0_CTRL2
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08028
MPUXDMA0_SADDR2
00000000 00000000 00000000 00000000
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C0802C
MPUXDMA0_EADDR2
00000000 00000000 00000000 01111111
0xB0C08030
MPUXDMA0_CTRL3
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08034
MPUXDMA0_SADDR3
00000000 00000000 00000000 00000000
0xB0C08038
MPUXDMA0_EADDR3
00000000 00000000 00000000 01111111
0xB0C0803C
MPUXDMA0_CTRL4
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08040
MPUXDMA0_SADDR4
00000000 00000000 00000000 00000000
0xB0C08044
MPUXDMA0_EADDR4
00000000 00000000 00000000 01111111
0xB0C08048
MPUXDMA0_CTRL5
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C0804C
MPUXDMA0_SADDR5
00000000 00000000 00000000 00000000
0xB0C08050
MPUXDMA0_EADDR5
00000000 00000000 00000000 01111111
0xB0C08054
MPUXDMA0_CTRL6
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08058
MPUXDMA0_SADDR6
00000000 00000000 00000000 00000000
0xB0C0805C
MPUXDMA0_EADDR6
00000000 00000000 00000000 01111111
0xB0C08060
MPUXDMA0_CTRL7
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08064
MPUXDMA0_SADDR7
00000000 00000000 00000000 00000000
0xB0C08068
MPUXDMA0_EADDR7
00000000 00000000 00000000 01111111
0xB0C0806C
MPUXDMA0_CTRL8
XXXXXXXX XXXXXXXX 00000000 00000000
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-10 Memory layout for the PERI5_AHB registers (Continued)
Offset
+3
+2
+1
0xB0C08070
MPUXDMA0_SADDR8
00000000 00000000 00000000 00000000
0xB0C08074
MPUXDMA0_EADDR8
00000000 00000000 00000000 01111111
0xB0C08078
MPUXDMA0_UNLOCK
00000000 00000000 00000000 00000000
0xB0C0807C
MPUXDMA0_MID
00000000 00000000 00000000 00000000
0xB0C08080B0CFFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0CFFC04
BSU5_BTST
00000000 00000000 00000000 00000000
0xB0CFFC08B0CFFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-11 Memory layout of SYSTEM_RAM_CONFIG registers
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0D00000
SRCFG_CFG1
00000000 00000000 00000000 00000000
SRCFG_CFG0
00000011 00000011 00000001 00000000
0xB0D00008
SRCFG_KEY
00000000 00000000 00000000 00000000
SRCFG_CFG2
00000000 00000000 00000000 00000000
0xB0D00010
SRCFG_INTE
00000000 00000000 00000000 00000000
SRCFG_ERRFLG
00000000 00000000 00000000 00000000
0xB0D00018
read0
00000000 00000000 00000000 00000000
SRCFG_ECCE
00000000 00000000 00000000 00000001
0xB0D00020
SRCFG_MID
00000000 00000000 00000000 00000000
SRCFG_ERRADR
00000000 00000000 00000000 00000000
0xB0D00028B0D00FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
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MB9DF126
MB9DF126B
Table 5-12 Memory map of EXCFG registers
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xFFFEF000 0xFFFEFF50
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFF58
read0
00000000 00000000 00000000 00000000
EXCFG_UNLOCK
00000000 00000000 00000000 00000000
0xFFFEFF58
read0
00000000 00000000 00000000 00000000
EXCFG_CNFG
00000000 00000000 00000000 00000000
0xFFFEFF60 0xFFFEFF78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFF80
EXCFG_UNDEFINACT
11111111 11111111 00000000 00100100
read0
00000000 00000000 00000000 00000000
0xFFFEFF88
EXCFG_PABORTINACT
11111111 11111111 00000000 00101100
EXCFG_SYCINACT
11111111 11111111 00000000 00101000
0xFFFEFF90
read0
00000000 00000000 00000000 00000000
EXCFG_DABORTINACT
11111111 11111111 00000000 00110000
0xFFFEFF98
read0
00000000 00000000 00000000 00000000
EXCFG_IRQINACT
11111111 11111111 00000000 00111000
0xFFFEFFA0 0xFFFEFFB8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFFC0
EXCFG_UNDEFACT
11111111 11111111 00000000 00100100
read0
00000000 00000000 00000000 00000000
0xFFFEFFC8
EXCFG_PABORTACT
11111111 11111111 00000000 00101100
EXCFG_SYCACT
11111111 11111111 00000000 00101000
0xFFFEFFD0
read0
00000000 00000000 00000000 00000000
EXCFG_DABORTACT
11111111 11111111 00000000 00110000
0xFFFEFFD8
read0
00000000 00000000 00000000 00000000
EXCFG_IRQACT
11111111 11111111 00000000 00111000
0xFFFEFFE0 0xFFFEFFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: DS707-00002-4v1-E
Page 340
MB9DF126
MB9DF126B
Note:
—
SYSC_SPCCFGR:FASTON register bit is reserved and should be always written as ’0’, since this
device does not support "Fast Power domain control" feature.
— SCCFG_STAT1:EEFCEEN and SCCFG_STAT1:TCFCEEN register bits are read-1 (write has no impact
and read always returns ’1’) in this device.
—
SCCFG_STAT1:FPPEN and SCCFG_STAT1:SCMEN register bits are read-0 (write has no impact and
read always returns ’0’) in this device.
Document Number: DS707-00002-4v1-E
Page 341
MB9DF126
MB9DF126B
6 Electrical characteristics
6.1
Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Table 6-1: Absolute Maximum Ratings
Parameter
Power supply voltage
AD Converter voltage references
Symbol
Rating
Unit
Remarks
Min
Max
VDP5
VSS - 0.3
VSS + 6.0
V
VDP3
VSS - 0.3
VSS + 4.0
V
VDD
VSS - 0.3
VSS + 1.8
V
AVDD5
AVSS5 - 0.3
AVSS5 + 6.0
V
VDE5
VSS - 0.3
VSS + 6.0
V
VDEA
VSS - 0.3
VSS + 4.0
V
VDDA
VSS - 0.3
VSS + 1.8
V
AVRH5
AVSS5 - 0.3
AVSS5 + 6.0
V
AVDD5 AVRH5, AVRH5 AVSS5
See *4 VDP5 = AVDD5 = DVCC
when ZPD functionality is
used
SMC Power supply
DVCC
DVSS - 0.3
DVSS + 6.0
V
Analog input voltage
VIA
AVSS5 - 0.3
AVDD5 + 0.3
V
VSS - 0.3
VDP5 + 0.3
V
VSS - 0.3
VDP3 + 0.3
V
DVSS - 0.3
DVCC + 0.3
V
VSS - 0.3
VDP5 + 0.3
V
VSS - 0.3
VDP3 + 0.3
V
DVSS - 0.3
DVCC + 0.3
V
Input voltage
VI
Output voltage
VO
VDP5 = AVDD5 *1
VI - DVCC,VDP5 + 0.3V *2
VO - DVCC,VDP5 + 0.3V *2
Maximum Clamp Current
ICLAMP
-4
+4
mA
Applicable to general purpose I/O pins *3
Total Maximum Clamp Current
|ICLAMP|
-
20
mA
Applicable to general purpose I/O pins *3
Document Number: DS707-00002-4v1-E
Page 342
MB9DF126
MB9DF126B
Table 6-1: Absolute Maximum Ratings (Continued)
Parameter
Symbol
Unit
Remarks
2
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
4
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOL5
-
10
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOLI2C
-
6
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOLHSIO
-
24
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOLSMC
-
40
mA
SMC outputs(SMC) with driving strength set to 30mA
IOLVDP5
-
100
mA
-
IOLVDP3
-
100
mA
-
IOLDVCC
-
360
mA
-
IOLAV1
-
1
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
IOLAV2
-
2
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOLAV5
-
5
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOLAVI2C
-
3
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOLAVHSIO
-
12
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOLAVSMC
-
30
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOLAVDP5
-
50
mA
-
IOLAVDP3
-
50
mA
-
IOLADVCC
-
230
mA
-
“L” level maximum output
current
“L” level maximum overall
output current
“L” level average output current
“L” level average overall output current
Rating
Document Number: DS707-00002-4v1-E
Min
Max
IOL1
-
IOL2
Page 343
MB9DF126
MB9DF126B
Table 6-1: Absolute Maximum Ratings (Continued)
Parameter
Symbol
Rating
Unit
Remarks
-2
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
-4
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOH5
-
-10
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOHI2C
-
-6
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOHHSIO
-
-24
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOHSMC
-
-40
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOHVDP5
-
-100
mA
-
IOHVDP3
-
-100
mA
-
IOHDVCC
-
-360
mA
-
IOHAV1
-
-1
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
IOHAV2
-
-2
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOHAV5
-
-5
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOHAVI2C
-
-3
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOHAVHSIO
-
-12
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOHAVSMC
-
-30
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOHAVDP5
-
-50
mA
-
IOHAVDP3
-
-50
mA
-
IOHADVCC
-
-230
mA
-
Power consumption
PTOT
-
2000
mW
-
Operating ambient temperature
TA
-40
105
°C
-
“H” level maximum output
current
“H” level maximum overall
output current
“H” level average output current
“H” level average overall output current
Document Number: DS707-00002-4v1-E
Min
Max
IOH1
-
IOH2
Page 344
MB9DF126
MB9DF126B
Table 6-1: Absolute Maximum Ratings (Continued)
Parameter
Symbol
Storage temperature
TSTG
Rating
Min
Max
-55
150
Unit
Remarks
°C
-
NOTES:
*1: AVDD5 and VDP5 must be set to the same voltage. It is required that AVDD5 does not exceed VDP5 and that the
voltage at the analog inputs does not exceed AVDD5 neither when the power is switched on.
*2: VI and VO should not exceed VDP5 + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating. Input/output voltages of standard ports depend on VDP5.
*3:
•
•
•
•
•
•
•
•
•
•
Applicable to all general purpose I/O pins (Pi_jj)
Use within recommended operating conditions.
Use at DC voltage (current).
+B signals are input signals that exceed the VDP5 / VDP3 / DVcc voltage.
The +B signals should always be applied a limiting resistance placed between the +B signal and the microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VDP5 pin, and this may affect
other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply
is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low
voltage reset in internal vector mode).
Sample recommended circuits:
Protection Diode
Vcc
P−ch
+B input (0V to 16V)
Limiting
resistance
N−ch
R
*4: DVCC, AVDD5 and VDP5 must be set to the same voltage during zero point detection (ZPD) on any of the SMC
ports. If zero point detection is not required on any of the SMC ports, then DVCC can have any value with-in absolute
rating, provided switches are disabled by RICFG0_ADC0ZPDEN:ZPDEN register. Note, for ZPD, conversion time
will be more and accuracy of measurement will be low.
Document Number: DS707-00002-4v1-E
Page 345
MB9DF126
MB9DF126B
6.2
Recommended operating conditions
Table 6-2: Recommended operating conditions
Parameter
Symbol
5V power supply voltage
Value
Unit
Remarks
Min
Typ
Max
VDP5
3.0
3.3/5.0
5.5
V
3.3V power supply voltage
VDP3
3.0
3.3
3.6
V
1.2V power supply voltage
VDD
1.1
1.2
1.3
V
Analog 5V power supply voltage
VDE5
3.0
3.3/5.0
5.5
V
Analog 3.3V power supply voltage
VDEA
3.0
3.3
3.6
V
Analog 1.2V power supply voltage
VDDA
1.1
1.2
1.3
V
DVCC
4.5
5.0
5.5
V
If used as SMC
DVCC
3.0
3.3/5.0
5.5
V
If used as GPIO
Analog power supply voltage
AVDD5
3.0
3.3/5.0
5.5
V
AD Converter voltage reference
AVRH5
AVDD5 - 0.5
-
AVDD5
V
Operation ambient temparature
TOP
-40
-
105
°C
SMC power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Document Number: DS707-00002-4v1-E
Page 346
MB9DF126
MB9DF126B
6.3
DC Characteristics
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
VIH
Port
inputs
Pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
VIH
XTAL0
Value
Unit
Remarks
VDP5
V
4.5V  VDP5  5.5V
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.8 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.8 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
2.0
-
VDP5
V
4.5V  VDP5  5.5V
2.0
-
VDP5
V
3.0V  VDP5  3.6V
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
Min
Typ
Max
0.8 x VDP5
-
0.8 x VDP5
20 MHz Oscillator
0.8 x VDP5
Input “H“ voltage
0.8 x VDP5
VIH
X0
-
4 MHz Oscillator
0.8 x VDP5
0.8 x VDP5
VIH
X0A
-
32 KHz Oscillator
0.8 x VDP5
VIHXDF
VIHXOS
VIHR
VIHM
VIHHSIO
X0,
XTAL0
External clock
in"Fast Clock Input
mode"
0.7 x VDP5
X0,X1,
X0A,X1A
External clock in
"oscillation mode"
0.8 x VDP5
MODE/RSTX
Hysteresis
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
RSTX
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
MODE/RSTX
Hysteresis
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
MODE
-
0.7 x VDP5
-
0.8 x VDP5
BIDI33
Hysteresis
0.8 x VDP3
VDP3
V
3.0V  VDP3  3.6V
BIDI33
TTL
2
VDP3
V
3.0V  VDP3  3.6V
pi_jj
Document Number: DS707-00002-4v1-E
Page 347
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
VIL
Port inputs
pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
VIL
XTAL0
Value
Unit
Remarks
0.2 x VDP5
V
4.5V  VDP5  5.5V
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.2 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.5 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.8
V
4.5V  VDP5  5.5V
VSS
-
0.8
V
3.0V  VDP5  3.6V
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
0.3 x VDP5
V
4.5V  VDP5  5.5V
0.3 x VDP5
V
3.0V  VDP5  3.6V
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
Min
Typ
Max
VSS
-
VSS
20 MHz Oscillator
VSS
Input “L“ voltage
VSS
VIL
X0
-
4 MHz Oscillator
VSS
VSS
VIL
X0A
-
32 KHz Oscillator
VSS
VILX0F
VILX0S
VILR
VILM
VILHSIO
X0,
XTAL0
External clock
in"Fast Clock Input
mode"
VSS
X0,X1
X0A,X1A
External clock in
"oscillation mode"
VSS
MODE/RSTX
Hysteresis
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
RSTX
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
MODE/RSTX
Hysteresis
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
BIDI33
Hysteresis
VSS
-
0.2 x VDP3
V
3.0V  VDP3  3.6V
BIDI33
TTL
VSS
-
0.8
V
3.0V  VDP3  3.6V
MODE
-
VSS
-
VSS
pi_jj
Document Number: DS707-00002-4v1-E
Page 348
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
Port
inputs
pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
XTAL0
Value
Unit
Remarks
-
V
4.5V  VDP5  5.5V
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
0.35
-
-
V
4.5V  VDP5  5.5V
0.35
-
-
V
3.0V  VDP5  3.6V
0.1
-
-
V
4.5V  VDP5  5.5V
0.1
-
-
V
3.0V  VDP5  3.6V
-
-
-
V
4.5V  VDP5  5.5V
-
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
-
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
-
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
-
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
V
3.0V  VDP5  3.6V
Min
Typ
Max
-
-
-
20 MHz Oscillator
0.05 x VDP5
Hysteresis
VHYS
0.05 x VDP5
X0
-
4 MHz Oscillator
0.05 x VDP5
0.05 x VDP5
X0A
-
32 KHz Oscillator
0.05 x VDP5
X0,
XTAL0
External clock
in"Fast Clock
Input mode"
0.05 x VDP5
X0,X1,
X0A,X1A
External clock in
"oscillation mode"
0.05 x VDP5
MODE/RSTX
Hysteresis
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
RSTX
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
MODE/RSTX
Hysteresis
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
BIDI33
Hysteresis
0.05 x VDP3
-
-
V
3.0V  VDP3  3.6V
BIDI33
TTL
0.1
-
-
V
3.0V  VDP3  3.6V
MODE
-
0.05 x VDP5
-
0.05 x VDP5
pi_jj
Document Number: DS707-00002-4v1-E
Page 349
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Output “H“
voltage
Output “L“
voltage
Symbol
Pin
VOH1
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH2
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH5
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH3
I2 C
outputs
(VDP5)
VOHSMC
SMC
outputs
(DVCC)
VOH3X
32 KHz
oscillator
outputs
(VDP5)
VOH4X
4 MHz oscillator
outputs
(VDP5)
VOH2X
20 MHz
oscillator
outputs
(VDP5)
VOH12
BIDI33
outputs
(VDP3)
VOL1
BIDI50 /
SMC / I2C
outputs
(VDP5)
Document Number: DS707-00002-4v1-E
Condition
Value
Unit
Remarks
-
V
Driving strength
set to 1mA
-
-
V
Driving strength
set to 2mA
VDP5 - 0.5
-
-
V
Driving strength
set to 5mA
-
-
-
V
Pseudo Open
Drain (HIZ for logic
value “1” )
DVCC - 0.5
-
DVCC
V
Driving strength
set to 30mA
VDP5 - 1.3
-
VDP5
V
VDP5 - 0.9
-
VDP5
V
VDP5 - 0.5
-
VDP5
V
VDP3 - 0.5
-
VDP3
V
VSS
-
0.4
Min
Typ
Max
VDP5 - 0.5
-
VDP5 - 0.5
4.5V  VDP5  5.5V
IOH = -1mA
3.0V  VDP5  3.6V
IOH = -0.8mA
4.5V  VDP5  5.5V
IOH = -2mA
3.0V  VDP5  3.6V
IOH = -1.5mA
4.5V  VDP5  5.5V
IOH = -5mA
3.0V  VDP5  3.6V
IOH = -3mA
4.5V  VDP5  5.5V
3.0V  VDP5  3.6V
4.5V  DVCC  5.5V
IOH = -30mA
3.0V  DVCC  3.6V
IOH = -20mA
4.5V  VDP5  5.5V
IOH = -20A
3.0V  VDP5  3.6V
IOH = -11A
4.5V  VDP5  5.5V
IOH = -200A
3.0V  VDP5  3.6V
IOH = -115A
4.5V  VDP5  5.5V
IOH = -1.3mA
3.0V  VDP5  3.6V
IOH = -0.7mA
3.0V  VDP3  3.6V
IOH = -11mA
4.5V  VDP5  5.5V
IOL = +1mA
3.0V  VDP5  3.6V
IOL = +0.8mA
Driving strength
set to 11mA
Driving strength
set to 1mA
Page 350
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Symbol
Pin
VOL2
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOL5
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOL3
I2C
outputs
(VDP5)
VOLSMC
SMC
outputs
DVCC)
VOL3X
32 KHz
oscillator
outputs
(VDP5)
VOL3X
4 MHz oscillator
outputs
(VDP5)
VOL4X
20 MHz
oscillator
outputs
(VDP5)
VOL12
Normal
outputs
(VDP3)
Output “L“
voltage
Input leak
current
pi_jj
(GPIO)
Condition
Value
Unit
Remarks
0.4
V
Driving strength
set to 2mA
-
0.4
V
Driving strength
set to 5mA
VSS
-
0.4
V
Driving strength
set to 3mA
DVSS
-
0.5
V
Driving strength
set to 30mA
VSS
-
1.2
V
VSS
-
1.2
V
VSS
-
0.5
V
3.0V  VDP3  3.6V
IOL = +11mA
VSS
-
0.4
V
Driving strength
set to 11mA
-
-1
-
+1
A
TA = 25°C
-
-3
-
+3
A
TA = 105°C
-
-1
-
+1
A
TA = 25°C
-
-3
-
+3
A
TA = 105°C
Min
Typ
Max
VSS
-
VSS
4.5V  VDP5  5.5V
IOL = +2mA
3.0V  VDP5  3.6V
IOL = +1.5mA
4.5V  VDP5  5.5V
IOL = +5mA
3.0V  VDP5  3.6V
IOL = +3mA
4.5V  VDP5  5.5V
IOL = +3mA
3.0V  VDP5  3.6V
IOL = +1.7mA
4.5V  DVCC  5.5V
IOH = -30mA
3.0V  DVCC  3.6V
IOH = -20mA
4.5V  VDP5  5.5V
IOH = +20A
3.0V  VDP5  3.6V
IOH = +11A
4.5V  VDP5  5.5V
IOH = +200A
3.0V  VDP5  3.6V
IOH = +115A
4.5V  VDP5  5.5V
IOH = -1.3mA
3.0V  VDP5  3.6V
IOH = -0.7mA
IIL
pi_jj
(ANIN)
Document Number: DS707-00002-4v1-E
Page 351
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
15
A
i = number of IO
= 30 GPIO (in
VDP5 IO domain)
-
30
A
i = number of IO
= 58 GPIO (in
VDP3 IO domain)
-
-
15
A
i = number of IO
= 24 GPIO (in
DVCC IO domain)
-
25
50
100
k
4.5V  VDP5  5.5V
-
25
50
200
k
3.0V  VDP5  3.6V
-
15
33
80
k
3.0V  VDP3  3.6V
-
25
50
100
k
4.5V  VDP5  5.5V
-
25
50
200
k
3.0V  VDP5  3.6V
-
15
33
80
k
3.0V  VDP3  3.6V
-
-
30
80
A
Operational
-
0.008
5
A
Standby
-
-
1.7
2.4
mA
Operational @
20MHz
load = 10pF
-
-
1.0
1.6
mA
Operational @
4MHz
load = 10pF
-
-
-
5
A
Standby
-
-
10
25
A
Operational
-
-
-
3
A
Standby
-
-
2
6
A
Operational
-
-
-
0.1
A
Standby
Min
Typ
Max
-
-
-
VDP5 VIN  VSS
AVDD5 VIN  AVSS5
pi_jj
(GPIO,
ANIN)
(1 to n) [max (|ILHi|,|ILLi|)]
ILH: leakage at high level
input
ILL: leakage at low level
input
VDP3 VIN  VSS
Total input
leakage current
(1 to n) [max(|ILHi|,|ILLi|)]
IIL
pi_jj
(GPIO)
ILH: leakage at high level
input
ILL: leakage at low level
input
DVCC  VIN  VSS
(1 to n) [max(|ILHi|,|ILLi|)]
pi_jj
(GPIO)
ILH: leakage at high level
input
ILL: leakage at low level
input
Pull-up
resistance
RUP
pi_jj
(BIDI50/
SMC/I2C)
pi_jj (BIDI33)
Pull-down
resistance
RDN
pi_jj (BIDI50/
SMC/I2C)
pi_jj (BIDI33)
Low voltage
detection current
Main oscillator
current
(XTAL0/1)
ILYDETI
IMOSCR
IMOSCS
Sub oscillator
current (32 kHz)
Slow RC oscillator current
(100kHz)
(VDP5)
(VDP5)
(VDP5)
ISOSCR
(VDP5)
ISOSCS
IRCS
(VDD)
Document Number: DS707-00002-4v1-E
Page 352
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (Continued)
Parameter
Fast RCO
current (8 MHz)
Fast RCO
current (12 MHz)
Input
capacitance
Symbol
IRFC8
IRFC12
CIN
Pin
Condition
(VDD)
Value
Unit
Remarks
11
A
Operational
(average with
trimming)
305
700
A
Operational
(average with
trimming)
-
0.01
3
A
Standby
-
-
0.003
3
A
Standby
(VDD)
-
-
11
16
A
Operational
(average with
trimming)
(VDP5)
-
-
416
1050
A
Operational
(average with
trimming)
(VDD)
-
-
0.01
3
A
Standby
(VDP5)
-
-
0.003
3
A
Standby
-
-
-
5
15
pF
Other than supply
pins
Min
Typ
Max
-
-
7
(VDP5)
-
-
(VDD)
-
(VDP5)
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-4: DC characteristics
Parameter
Symbol
Pin
(VDD)
Power supply
current in RUN
mode
(VDD)
ICCRUN
(VDD)
(VDD)
Document Number: DS707-00002-4v1-E
Condition
RUN mode current
of PD1
RUN mode current
of PD2
RUN mode current
of PD3
RUN mode current
of PD4
Value
Unit
Temp
Remarks
25°C
with all clocks at max
frequency, Includes
leakage of respective PD
Includes VDDA current for APIX AIC
Mode
Typ
Max
-
16.6
-
17.4
105°C
-
58
25°C
-
80
105°C
-
139
25°C
-
170
105°C
-
1
25°C
-
2
mA
mA
mA
mA
105°C
with all clocks at max
frequency, Includes
leakage of respective PD
with all clocks at max
frequency, Includes
leakage of respective PD
with all clocks at max
frequency, Includes
leakage of respective PD
Page 353
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-4: DC characteristics (Continued)
Parameter
Symbol
Pin
Condition
(VDD)
Leakage current of
PD1
(VDD)
Power supply
current in PSS
mode
ICCPSS
(VDD)
(VDD)
(VDDA)
ICCTMAIN
ICCTRCH
(VDD)
(VDD)
Power supply
current in Timer
mode
ICCTRCL
ICCTSUB
TCFLASH
Read current
(64 MHz)
ICCTCFLASHRD
TCFLASH
Program/Erase
current
ICCTCFLASHPE
TCFLASH
Sleep current
ICCTCFLASHSB
EEFLASH
Read current
ICCEEFLASHRD
EEFLASH
Program/Erase
current
ICCEEFLASHPE
EEFLASH
Sleep current
ICCEEFLASHSB
(VDD)
(VDD)
Leakage current of
PD2 (excluding
PD3)
Leakage current of
PD3
Value
Typ
Max
-
0.075
Unit
mA
-
0.7
-
2
16
-
2
mA
-
22.8
Leakage current of
PD4
-
0.015
-
0.5
Leakage current of
APIX
-
0.05
mA
mA
-
0.25
Main Timer mode
with CLKMC =
20MHz
-
0.6
-
2.3
RC Timer mode
with CLKRC =
12MHz
-
0.6
-
2.3
Main Timer mode
with CLKSRC =
100kHz
-
0.52
-
2.2
Sub Timer mode
with CLKSC =
32kHz
-
0.52
25°C
105°C
105°C
25°C
105°C
25°C
105°C
25°C
105°C
25°C
mA
105°C
25°C
mA
105°C
25°C
mA
105°C
25°C
mA
105°C
-
2.2
(VDD)
-
32.9
mA
105°C
(VDP5)
-
21
mA
105°C
-
1.8
mA
105°C
-
11.3
mA
105°C
(VDD)
-
412
A
105°C
(VDP5)
-
11
A
105°C
(VDD)
-
28.1
mA
105°C
(VDP5)
-
21
mA
105°C
-
1.8
mA
105°C
-
11.3
mA
105°C
(VDD)
-
236
A
105°C
(VDP5)
-
11
A
105°C
(VDD)
(VDP5)
(VDD)
(VDP5)
Document Number: DS707-00002-4v1-E
Current for one
Instruction Flash
module
Current for one
Data Flash module
Remarks
PCN: 2901
25°C
mA
-
Temp
-
-
PCN: 2901
applies only to
MB9DF126B
with PD2, PD3, PD4,
switched off
PCN: 2901
with PD2, PD3, PD4,
switched off
PCN: 2901
with PD2, PD3, PD4,
switched off
PCN: 2901
with PD2, PD3, PD4,
switched off
PCN: 2901
Only applicable if
PD3 is ON
Only applicable if
PD3 is ON
Page 354
MB9DF126
MB9DF126B
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-4: DC characteristics (Continued)
Parameter
Symbol
Pin
Condition
Power
consumption
POP
-
-
Document Number: DS707-00002-4v1-E
Value
Typ
Max
Unit
-
1250
mW
Temp
Remarks
-
Page 355
MB9DF126
MB9DF126B
6.4
6.4.1
AC Characteristics
Source Clock timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-5: Source Clock timing
Parameter
Oscillator
Clock frequency
Oscillator
Clock frequency
Oscillator
Clock frequency
Slow Clock
frequency
Symbol
fc
fFCI
fCL
fCRS
Fast RCO
clock
frequency
fCRF
Fast RCO
clock
stability
fPRCF
Pin
Value
Unit
Remarks
20
MHz
When using a crystal oscillator, PLL off
20
MHz
When using an opposite phase external
clock, PLL off
Min
Typ
Max
-
-
-
-
4
-
20
MHz
When using a crystal oscillator or opposite phase external clock, PLL on.
PLL input clock divider (PLLDIVL) must
be greater than 1 since PLL does not support input clock freq more than 16MHz.
Please also see limitation for fPLLVCO input
frequency
0
-
62.5
MHz
When using a single phase external clock
in “Fast Clock Input mode”, PLL off
XTAL0
XTAL1
4
-
62.5
MHz
When using a single phase external clock
in “Fast Clock Input mode”, PLL on
PLL input clock divider (PLLDIVL) must
be greater than 1 since PLL does not support input clock freq more than 16MHz.
32
32.768
100
kHz
When using an oscillation circuit
0
-
100
kHz
When using a opposite phase external
clock
X0A
0
-
50
kHz
When using a single phase external clock
-
50
100
150
kHz
When using slow frequency of RC oscillator
6.3
7.9
10.1
MHz
When using fast frequency of RC oscillator (8MHz mode) and SYSC_RCCFGR:TRM[7:0] = “0x7F”
9.3
11.6
14.6
MHz
When using fast frequency of RC oscillator (12MHz mode) and SYSC_RCCFGR:TRM[7:0] = “0x7F”
-2
-
+2
%
TA = 0..70C
-6
-
+6
%
TA = -40..105C
XTAL0
X0A,
X1A
-
Document Number: DS707-00002-4v1-E
Page 356
MB9DF126
MB9DF126B
Table 6-5: Source Clock timing
Parameter
PLL Clock
frequency
Symbol
fCLKVCO
Value
Pin
Min
-
200
Typ
-
Max
400
Unit
Remarks
MHz
Permitted VCO output frequency of PLL
(CLKVCO)
Please also see limitation for fPLLVCO input
frequency
PLL input
frequency
(after DIVL)
fPLLVCO
-
4
-
16
MHz
Input frequency of PLL after PLLDIVL divider.
PLL input clock divider (PLLDIVL) must
be greater than 1, if the frequency at the
Clock input exceeds 16MHz
PLL Phase
jitter
TPSKEW
-
-5
-
±5
ns
For CLKMC (PLL input clock) - 4 MHz, jitter coming from external oscillator, crystal
or resonator is not yet recovered
Input clock
pulse width
PWH, PWL
XTAL0
XTAL1
8
-
-
ns
Duty ratio is about 30% to 70%
Input clock
pulse width
PWHL,
PWLL
X0A,
X1A
5
-
-
s
Figure 6-1: Source Clock timing
t CYL
V IH
XTAL0
V IL
P WH
P WL
t CYLL
V IH
X0A
V IL
P WHL
Document Number: DS707-00002-4v1-E
P WLL
Page 357
MB9DF126
MB9DF126B
6.4.2
Internal Clock timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-6: Internal Clock timing
Parameter
Symbol
Min
Max
Unit
CLK_SYS_PD3
fCLK_SYS_PD3
0
128
MHz
CLK_DBG_PD2
fCLK_DBG_PD2
0
128
MHz
CLK_DBG_PD3
fCLK_DBG_PD3
0
128
MHz
CLK_TRACE_PD2
fCLK_TRACE_PD2
0
128
MHz
CLK_TRACE_PD3
fCLK_TRACE_PD3
0
128
MHz
CLK_HPM_PD2
fCLK_HPM_PD2
0
128
MHz
CLK_HPM_PD3
fCLK_HPM_PD3
0
128
MHz
CLK_CFG_PD4
fCLK_CFG_PD4
0
64
MHz
CLK_DMA_PD2
fCLK_DMA_PD2
0
128
MHz
CLK_MEM_I_PD3
fCLK_MEM_I_PD3
0
128
MHz
CLK_EXTBUS_PD3
fCLK_EXTBUS_PD3
0
64
MHz
CLK_MEM_E_PD3
fCLK_MEM_E_PD3
0
128
MHz
CLK_CFG_PD1
fCLK_CFG_PD1
0
64
MHz
CLK_PERI4_PD2
fCLK_PERI4_PD2
0
128
MHz
CLK_PERI0_PD2
fCLK_PERI0_PD2
0
64
MHz
CLK_PERI1_PD2
fCLK_PERI1_PD2
0
32
MHz
CLK_PERI3_PD2
fCLK_PERI3_PD2
0
64
MHz
CLK_SPI_PD3
fCLK_SPI_PD3
0
128
MHz
CKOT, CKOTX
fCKOT, fCKOTX
0
128
MHz
Document Number: DS707-00002-4v1-E
Remarks
internal clock, set
clock divider >4
for output
Page 358
MB9DF126
MB9DF126B
6.4.3
External Reset timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-7: External Reset timing
Value
Parameter
Symbol
Pin
Reset input time
tRSTL
RSTX
Min
Typ
Max
500
-
-
Unit
Remarks
ns
Figure 6-2: External Reset timing
t RSTL
RSTX
0.2VDP5
Document Number: DS707-00002-4v1-E
0.2VDP5
Page 359
MB9DF126
MB9DF126B
6.4.4
External Input timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-8: External Input timing
Parameter
Symbol
Pin
Value
Condition
EIC0_INTk
NMI
Input pulse
width
tINH
tINL
Min
Max
200
-
Unit
ns
Used Pin input
function
External Interrupt
NMI
Pi_jj
General purpose
IO
RLTn_TIN
Reload Timer
PPG_ETRGx
PPG Trigger input
--
ADCn_EDGI
AD Converter
Trigger
2tCLK_PER + tNF
(*1 *2)
FRTn_FRCK
ns
Free Running
Timer external
clock
ICUn_INm
Input Capture
UDCn_AIN,
UDCn_BIN,
UDCn_ZIN
Up/Down Counter
Note:*1 tCLK_PER is the period of the corresponding peripheral clock.
Note:*2 tNF is 200ns, if noise filter is enabled and 0ns, if noise filter is bypassed.
Figure 6-3: External Input timing
External Pin input
VIH
VIH
VIL
tINH
Document Number: DS707-00002-4v1-E
VIL
t INL
Page 360
MB9DF126
MB9DF126B
6.4.5
Slew Rate High Current Outputs
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-9: Slew Rate High Current Outputs
Value
Parameter
Symbol
Pin
Condition
Output rise/
fall time
tR30
tF30
I/O circuit
type SMC
Output driving
strength set to
“30mA”
Min
Max
15 @
CLOAD=0pF
-
Unit
Remarks
ns
Figure 6-4: Slew Rate High Current Output timing
Slew rate output timing
VH
VH = 0.9 x DVCC
VL = 0.1 x DVCC
VH
VL
VL
t R30
Document Number: DS707-00002-4v1-E
t F30
Page 361
MB9DF126
MB9DF126B
6.4.6
USART timing
Note: The values given below are for an I/O drive strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must be increased by 10ns.
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = 0V, IOdrive = 5mA, CL = 50pF)
Table 6-10: USART timing
Parameter
Symbol
Pin
Serial clock
cycle time
tSCYCI
SCK SOT
delay time
Condition
VDP5 = 4.5V to 5.5V
VDP5 = 3.0V to 4.5V
Unit
Min
Max
Min
Max
SCK
4*tCLK_PERI0_PD2
-
4*tCLK_PERI0_PD2
-
ns
tSLOVI
SCK,
SOT
-20
+20
-30
+30
ns
SOT SCK
delay time
tOVSHI
SCK,
SOT
N*tCLK_PERI0_PD
*1
2 – 20
-
N*tCLK_PERI0_PD2
– 30 *1
-
ns
Valid SIN
SCK
tIVSHI
SCK,
SIN
tCLK_PERI0_PD2
+ 45
-
tCLK_PERI0_PD2
+ 55
-
ns
SCK Valid
SIN hold
time
tSHIXI
SCK,
SIN
0
-
0
-
ns
Serial clock
“L” pulse
width
tSLBHE
SCK
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
Serial clock
“H” pulse
width
tSHSLE
SCK
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
SCK SOT
delay time
tSLOVE
SCK,
SOT
-
2
tCLK_DBG_PD2
+45
-
2
tCLK_DBG_PD2
+45
ns
Valid SIN
SCK
tIVSHE
SCK,
SIN
-
ns
SCK Valid
SIN hold
time
tSHIXE
SCK,
SIN
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
SCK fall
time
tFE
SCK
-
20
-
20
ns
SCK rise
time
tRE
SCK
-
20
-
20
ns
Document Number: DS707-00002-4v1-E
Internal
Shift Clock
Mode
External
Shift Clock
Mode
tCLK_PERI0_PD2/2
+ 10
-
tCLK_PERI0_PD2/2
+ 10
Page 362
MB9DF126
MB9DF126B
Notes:
AC characteristics in CLK synchronized mode.
CL is the load capacity value of pins when testing.
Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
tCLK_PERI0_PD2 is the cycle time of the clock (CLK_PERI0_PD2), Unit: ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLK_PERI0_PD2, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLK_PERI0_PD2, then N = k+1, where k is an integer > 1
Examples:
Document Number: DS707-00002-4v1-E
tSCYCI
N
4*tCLK_PERI0_PD2
2
5*tCLK_PERI0_PD2, 6*tCLK_PERI0_PD2
3
7*tCLK_PERI0_PD2, 8*tCLK_PERI0_PD2
4
….
….
Page 363
MB9DF126
MB9DF126B
Figure 6-5: USART timing
t SCYCI
0.8*VDP5
SCK for
ESCR:SCES =0
SCK for
ESCR:SCES = 1
0.2*VDP5
0.2*VDP5
0.8*VDP5
0.8*VDP5
t SLOVI
0.2*VDP5
t OVSHI
0.8*VDP5
SOT
0.2*VDP5
t IVSHI
SIN
t SHIXI
V IH
V IH
V IL
V IL
Internal Shift Clock Mode
t SLSHE
t SHSLE
V IH
SCK for
ESCR:SCES =0
V IL
SOT
t SLOVE
V IL
t RE
0.8*VDP5
0.2*VDP5
t IVSHE
SIN
V IL
V IH
V IL
t FE
V IH
V IL
V IH
SCK for
ESCR:SCES = 1
V IH
t SHIXE
V IH
V IH
V IL
V IL
External Shift Clock Mode
Document Number: DS707-00002-4v1-E
Page 364
MB9DF126
MB9DF126B
6.4.7
I2C timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 4.5V to 5.5V*4
DVCC = 4.5V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-11: I2C Timing
Parameter
Symbol
SCL clock frequency
Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDASCL
tHDSTA
4.0
-
0.6
-
s
“L” width of the SCL clock
tLOW
4.7
-
1.3
-
s
“H” width of the SCL clock
tHIGH
4.0
-
0.6
-
s
Set-up time for a repeated START
condition
SCLSDA
tSUSTA
4.7
-
0.6
-
s
Data hold time
SCLSDA
tHDDAT
0
3.45
0
0.9
s
Data set-up time
SDA---SCL¦¦-
tSUDAT
250
-
100
-
ns
Set-up time for STOP condition
SCL--SDA-
tSUSTO
4
-
0.6
-
s
Bus free time between a STOP
and START condition
tBUS
4.7
-
1.3
-
s
Output fall time from 0.7*VDP5 to
0.3*VDP5 with a bus capacitance
from 10pF to 400pF
tof
20 +
0.1*Cb *2
250
20 +
0.1*Cb *2
250
ns
Capacitive load for each bus line
Cb
-
400
-
50
pF
Pulse width of spikes which will be
suppressed by input noise filter
tSP
n/a
n/a
0
1tCLK_PERI0_PD2 *3
ns
*1: For use at over 100 kHz, set the CLK_PERI0_PD2 to at least 6 MHz.
*2: Cb = capacitance of one bus line in pF.
*3: tCLK_PERI0_PD2 is the cycle time of the peripheral clock CLK_PERI0_PD2
*4: I2C spec only guaranteed at VDP5 = 4.5V to 5.5V.
Document Number: DS707-00002-4v1-E
Page 365
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MB9DF126B
Figure 6-6: I2C timing
SDA
t LOW
t SUDAT
t BUS
t HDSTA
SCL
t HDSTA
t HDDAT
t HIGH
Document Number: DS707-00002-4v1-E
t SUSTA
t SUSTO
Page 366
MB9DF126
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6.4.8
HSSPI timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-12: HSSPI Interface timing (Master Mode,)
Parameter
Symbol
HSSPI clock frequency
Value
Units
Typ
Max
-
-
64
MHz
13.4
-
-
ns
no clock retiming
5.6
-
-
ns
with clock retiming
0
-
-
ns
no clock retiming
1.5
-
-
ns
with clock retiming
Input setup time
(HSSPIn_DATAi)
TIS,DATA
Input hold time
(HSSPIn_DATAi)
TIH,DATA
Output delay time
(HSSPIn_DATAo)
TOD,DATA
-
-
3.8
ns
Output hold time
(HSSPIn_DATAo)
TOH,DATA
5
-
-
ns
Output delay time
(HSSPIn_SSELo)
TOD,SSEL
-
-
5.05
ns
Output hold time
(HSSPIn_SSELo)
TOH,SSEL
0
-
-
ns
Document Number: DS707-00002-4v1-E
Remarks
Min
Page 367
MB9DF126
MB9DF126B
Figure 6-7: HSSPI Interface timing
HSSPIn_CLK
T IS,DATA T IH,DATA
HSSPIn_DATAi
T IS,SSEL T IH,SSEL
HSSPIn_SSELi
TOD,DATA
T OH,DATA
TOD,SSEL
T OH,SSEL
HSSPIn_DATAo
HSSPIn_SSELo
Table 6-13: HSSPI Interface timing (Slave Mode)
Parameter
Symbol
HSSPI clock frequency
Value
Units
Min
Typ
Max
-
-
25
MHz
Input setup time
(HSSPIn_DATAi)
TIS,DATA
5
-
-
ns
Input hold time
(HSSPIn_DATAi)
TIH,DATA
0
-
-
ns
Input setup time
(HSSPIn_SSELi)
TIS,SSEL
8.2
-
-
ns
Input hold time
(HSSPIn_SSELi)
TIH,SSEL
2
-
-
ns
Output delay time
(HSSPIn_DATAo)
TOD,DATA
-
-
15.5
ns
Document Number: DS707-00002-4v1-E
Remarks
Page 368
MB9DF126
MB9DF126B
Table 6-13: HSSPI Interface timing (Slave Mode)
Parameter
Symbol
Output hold time
(HSSPIn_DATAo)
TOH,DATA
Document Number: DS707-00002-4v1-E
Value
Min
Typ
Max
0
-
-
Units
Remarks
ns
Page 369
MB9DF126
MB9DF126B
6.4.9
SPI timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
For each SPI module, several combinations of I/O pins can be chosen for each SPI signal. The timing depends on
the actual combination and is given below as separate values for each possible type of I/O-cell. When I/O/cells of
different types are mixed, the worst case table, called “OVERALL SPI Interface timing” must be used.
In Master Mode, using the clock retiming function improves the setup and hold times for input data.
The usable maximum clock frequency depends on the transmission mode (Master to Slave / Slave to Master, using
clock-retiming or not). An example for caculation is given below each table.
Table 6-14: OVERALL SPI Interface timing
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
23.9
-
8.0
-
7.9
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-4.3 *1
-
5.4
-
5.3
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
8.9
-
8.9
-
26.9
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-5.7 *1
-
-5.7 *1
-
4.0
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
8.4
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
4.9
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
8.0
-
8.0
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
-5.7 *1
-
-5.7 *1
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
29.7
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
14.3
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
Document Number: DS707-00002-4v1-E
Page 370
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Table 6-15: SPI Interface timing for all cells of type BIDI33
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
16.5
-
4.8
-
4.2
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-4.3 *1
-
1.3
-
0.9
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
7.7
-
7.7
-
21.4
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-2.1 *1
-
-2.1 *1
-
4.0
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
4.4
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
0.7
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
4.0
-
4.0
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
1.2
-
1.2
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
42
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
19
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
Document Number: DS707-00002-4v1-E
Page 371
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Table 6-16: SPI Interface timing for all cells of type BIDI50
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
23.9
-
5.8
-
5.7
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-6.4 *1
-
3.2
-
3.1
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
7.2
-
7.2
-
25.8
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-2.5 *1
-
-2.5 *1
-
6.6
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
6.5
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
2.5
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
6.2
-
6.2
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
0.9
-
0.9
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
38.7
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
15.8
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
Document Number: DS707-00002-4v1-E
Page 372
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MB9DF126B
Table 6-17: SPI Interface timing for all cells of type SMC
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
21.2
-
4.7
-
4.6
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-6.1 *1
-
3.2
-
3.1
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
6.1
-
6.1
-
26.1
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-0.7 *1
-
-0.7 *1
-
6.5
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
5.5
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
1.5
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
4.6
-
4.6
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
1.8
-
1.8
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
46.7
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
16.2
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
Document Number: DS707-00002-4v1-E
Page 373
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MB9DF126B
Figure 6-8: SPI Interface timing
SPIn_CLK
T IS,DATA T IH,DATA
SPIn_DATAi
T IS,SSEL T IH,SSEL
SPIn_SSELi
TOD,DATA
T OH,DATA
TOD,SSEL
T OH,SSEL
SPIn_DATAo
SPIn_SSELo
Document Number: DS707-00002-4v1-E
Page 374
MB9DF126
MB9DF126B
6.4.10
External Bus Interface timing
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 4.5V to 5.5V
DVCC = 4.5V to 5.5V, VSS = AVSS5 = DVSS = 0V, CLoad = 20 pF)
•
General Timing
Table 6-18: General Timing Parameters
Parameter
Pin names
Tcso
EBI0_MCLK,
EBI0_MCSX0 ~
EBI0_MCSX7
7
ns
Tao
EBI0_MCLK, EBI0_MAD[23:0]
11
ns
Tdo
EBI0_MCLK,
EBI0_MDATA[31:0]
9
ns
Tdoz
EBI0_MCLK,
EBI0_MDATA[31:0]
10
ns
MCSX0~MCSX7
Address delay time
Data output delay time
Data output HiZ time
Document Number: DS707-00002-4v1-E
Value
Symbol
Min
Max
Unit
Note
Page 375
MB9DF126
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•
SRAM Read Timing
Table 6-19: SRAM Read Timing Parameters
Parameter
SRAM data setup time
SRAM data hold time
MOEX delay time
Value
Symbol
Pin names
Tdsr
EBI0_MOEX,
EBI0_MDATA[31:0]
15
ns
Tdhr
EBI0_MOEX,
EBI0_MDATA[31:0]
0
ns
Trdo
EBI0_MCLK,
EBI0_MOEX
Min
Max
8
Unit
Note
ns
Figure 6-9: SRAM Read Timing
Tcyc
EBI0_MCLK
Tcso
EBI0_MCSX0...EBI0_MCSX7
Tao
EBI0_MAD [23:0]
Trdo
EBI0_MOEX
Tdsr
Tdhr
EBI0_MDATA[31:0]
Document Number: DS707-00002-4v1-E
Page 376
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•
SRAM Write Timing
Table 6-20: SRAM Write Timing Parameters
Parameter
SRAM WE delay time
MDQM[3:0] delay time
Value
Symbol
Pin names
Tweo
EBI0_MCLK,
EBI0_MWEX
7
ns
Twro
EBI0_MCLK,
EBI0_MDQM[3:0]
7
ns
Min
Max
Unit
Note
Figure 6-10: SRAM Write Timing
Tcyc
EBI0_MCLK
Tcso
EBI0_MCSX0...EBI0_MCSX7
Tao
EBI0_MAD [23:0]
Tweo
EBI0_MWEX
EBI0_MDQM[3:0]
Twro
Tdo
Tdoz
EBI0_MDATA[31:0]
Document Number: DS707-00002-4v1-E
Page 377
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•
SDRAM Access Timing
Table 6-21: SDRAM Access Timing Parameters
Parameter
SDRAM CS delay time
SDRAM RAS delay time
SDRAM CAS delay time
SDRAM WE delay time
SDRAM CKE delay time
SDRAM data setup time
SDRAM data hold time
Document Number: DS707-00002-4v1-E
Value
Symbol
Pin names
Tmcs
EBI0_MCLK,
EBI0_MCSX0
7
ns
Tras
EBI0_MCLK,
EBI0_MRASX
6
ns
Tcas
EBI0_MCLK,
EBI0_MCASX
6.5
ns
Tmwe
EBI0_MCLK,
EBI0_MDWEX
7
ns
Tcke
EBI0_MCLK,
EBI0_MCKE
7.5
ns
Tdssd
EBI0_MCLK,
EBI0_MDATA[31:0]
8.5
ns
Tdhsd
EBI0_MCLK,
EBI0_MDATA[31:0]
0
ns
Min
Max
Unit
Note
Page 378
MB9DF126
MB9DF126B
Figure 6-11: SDRAM Access Timing
Tcyc
EBI0_MCLK
Tmcs
EBI0_MCSX0...EBI0_MCSX7
Tras
EBI0_MRASX
Tcas
EBI0_MCASX
Tmwe
EBI0_MDWEX
Twro
EBI0_MDQM[3:0]
Tcke
EBI0_MCKE
Tdssd
Tdhsd
EBI0_MDATA[31:0]
Tdo
Tdoz
EBI0_MDATA [31:0]
Document Number: DS707-00002-4v1-E
Page 379
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•
NAND Flash Read Timing
Table 6-22: NAND Flash Read Timing Parameters
Parameter
NAND Read Enable delay time
NAND data setup time
NAND data hold time
Value
Symbol
Pin names
Treno
EBI0_MCLK,
EBI0_MNREX
Tdsn
EBI0_MCLK,
EBI0_MDATA[31:0]
14.5
ns
Tdhn
EBI0_MCLK,
EBI0_MDATA[31:0]
0
ns
Min
Max
7.5
Unit
Note
ns
Figure 6-12: NAND Flash Read Timing
Tcyc
EBI0_MCLK
Treno
EBI0_MNREX
Tdsn
Tdhn
EBI0_MDATA[31:0]
•
NAND Flash Write Timing
Table 6-23: NAND Flash Write Timing Parameters
Value
Parameter
Symbol
Pin names
NAND Address Latch Enable
delay time
Taleo
EBI0_MCLK,
EBI0_MNALE
6
ns
NAND Command Latch Enable
delay time
Tcleo
EBI0_MCLK,
EBI0_MNCLE
4.5
ns
Tweno
EBI0_MCLK,
EBI0_MNWEX
6.5
ns
NAND Write Enable delay time
Document Number: DS707-00002-4v1-E
Min
Max
Unit
Note
Page 380
MB9DF126
MB9DF126B
Figure 6-13: NAND Flash Write Timing
Tcyc
EBI0_MCLK
Taleo
EBI0_MNALE
Tcleo
EBI0_MNCLE
Tweno
EBI0_MNWEX
Tdo
Tdoz
EBI0_MDATA[31:0]
Document Number: DS707-00002-4v1-E
Page 381
MB9DF126
MB9DF126B
6.5
Analog Digital Converter
(TA = -40°C to 105°C, 3.0V - AVRH5, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V,
VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-24: Analog Digital Converter
Parameter
Symbol
Pin
Resolution
-
Total error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
10
bit
-
-
-3
-
+3
LSB
Nonlinearity
error
-
-
-2.5
-
+2.5
LSB
Differential
nonlinearity
error
-
-
-1.9
-
+1.9
LSB
Full scale
transition
voltage
VFST
ANi
Typ
- 20
AVRH5 - 1.5
LSB
Typ
+ 20
mV
between 1022 and
1023
Zero Transition
Voltage
VZT
ANi
Typ
- 20
AVSS5 + 0.5
LSB
Typ
+ 20
mV
between 0 and 1
Conversion
Rate
TS
353
-
1186
KS/s
646.8
-
-
ns
Fclk=17MHz,
Tclk=58.8ns * 11
clocks
ns
AVDD5 =
4.5V...5.5V,
Fclk=4MHz,
Tclk=250ns * 11
clocks
Comparison
Time
Analog input
leakage
current (during
conversion)
pi_jj(A
NIN)
TCOMP
IAIN
-
2750
-
-
-
1837
ns
AVDD5 =
3.0V...4.5V,
Fclk=6MHz,
Tclk=167ns * 11
clocks
-1
-
+1
A
TA  25C,
AVSS5 < VI < AVDD5,
AVRH5
-3
-
+3
A
TA  105C,
AVSS5 < VI < AVDD5,
AVRH5
ANn
Document Number: DS707-00002-4v1-E
Page 382
MB9DF126
MB9DF126B
Table 6-24: Analog Digital Converter
Parameter
Symbol
Pin
Analog input
voltage range
VAIN
Reference
voltage range
Power supply
current
Reference
voltage current
Offset between
input channels
Value
Unit
Remarks
Min
Typ
Max
ANn
AVSS5
-
AVRH5
V
AVRH5
AVRH5
AVDD5 - 0.5
-
AVDD5
V
IA
AVDD5
-
2
3.4
mA
A/D Converter active
-
-
6
A
25°C,
A/D Converter not
operated
-
-
11
A
105°C,
A/D Converter not
operated
IAH
AVDD5
IR
AVRH5
-
0.6
1
mA
A/D Converter active
IRH
AVRH5
-
-
0.6
A
A/D Converter not
operated
-
ANn
-
-
4
LSB
Note:The accuracy gets worse as |AVRH5 | becomes smaller.
Minimum Sampling Time
The minimum sampling time can be calculated from the following formula:
For pins ADC0_AN0..25:
Tsamp = 7.63 x [ Rext x ( Cext + CIN ) + ( Rext + RADC ) x CADC ]
For Pins ADC0_AN26..31:
Tsamp = 7.63 x [ Rext x ( Cext + CIN ) + ( Rext + RADC1 ) x CADC1 + (Rext + RADC1 + RADC ) x CADC ]
Please see the Hardware Manual for an explanation and the reference model for above formulas. The following
values are reference values for calculation.
Table 6-25: Reference values for A/D Converter sampling time calculation (*1)
Symbol
Explanation
Rext
Value
Unit
External driving impedance
-
-
Cext
Capacitance of PCB at A/D Converter input
-
-
CIN
Capacitance of the MCU input pin
16
pF
Document Number: DS707-00002-4v1-E
Condition
Page 383
MB9DF126
MB9DF126B
Symbol
Explanation
RADC
Resitances within MCU for ADC and internal nets
RADC1
Condition
Value
Unit
4.5V <= AVDD5 <= 5.5V
2.4
kOhm
3.0V <= AVDD5 < 4.5V
4.9
kOhm
Resitances within MCU for analog switch and inter- 4.5V <= AVDD5 <= 5.5V
nal nets
3.0V <= AVDD5 < 4.5V
1.8
kOhm
4.3
kOhm
CADC
Sampling Capacitance of ADC and internal nets
18
pF
CADC1
Capacitance within MCU for analog switch and internal nets
3
pF
Note: (*1) The values given in this table are intended as reference values for calculation of the sampling time for
A/D Converter. These values are not guaranteed.
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (00 0000 0000 <--> 00 0000 0001) and fullscale transition line (11 1111 1110 <--> 11 1111 1111) and actual conversion characteristics.
Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an
ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
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Total error
3FF
1.5 LSB
3FE
Actual conversion
characteristics
3FD
Digital output
{1 LSB X (N−1) + 0.5 LSB}
004
V NT
(Actually−measured value)
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5 LSB
AVRH
0
Analog input
Total error of digital output "N" =
1 LSB = (Ideal value)
V NT − {1 LSB X (N−1) + 0.5 LSB}
AVRH
1024
1 LSB
[LSB]
[V]
N : A/D converter digital output value
V OT (Ideal value) = 0 + 0.5 LSB [V]
V FST (Ideal value) = AVRH − 1.5LB [V]
V NT : A voltage at which digital output transition from (N−1) to N.
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6.6
FLASH memory program/erase characteristics
(TA = -40°C to 105°C, VDD = VDDA = 1.1V to 1.3V, VDP3 = VDEA = 3.0V to 3.6V, VDP5 = AVDD5 = VDE5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-26: Program/erase time for TCFLASH and EEFLASH
Value
Parameter
Sector Erase Time
Macro Erase Time
Unit
Min
Typ*1
Max
Small Sector
-
0.3
1.1
s
Large Sector
-
0.7
3.7
s
TCFLASH
-
13.6
68
s
EEFLASH
-
2.4
8.8
s
-
12
384
s
Word Programming Time
Remarks
The internal programming
time before the erase procedure starts is included.
Note:
*1: Typical definition: TA=25°C / VDD=1.2V / Program/Erase cycle = Immediately after shipment.
Table 6-27: Program/Erase cycle and Data Retention time*2
Program/Erase cycle at
each sector
Data Retention time
Min Value
Unit
Min Value
Unit
1000
cycles
20
years
10000
cycles
10
years
100000
cycles
5
years
Note:
*2: These values were converted from the technology qualification using Arrhenius equation to translate high temperature measurements into normalized values at + 85°C.
Table 6-28: Execution Time Limit
Parameter
Value
Unit
1.3
ms
TCFLASH
187.2
s
EEFLASH
63
s
7.8
s
Program Execution Time limit*3
Macro Erase Execution Time limit
Sector Erase Execution Time limit*4
Note:
*3: This is the time it takes for the macro to detect a Hang up 1 error when 1 is to be programmed to a memory cell
whose memory value is either 0 or X.
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*4: See the Hardware Manual for an explanation about Flash Timing Limit Exceeded Flags. The time during Sector Erase Suspend (period from Suspend Command Write Cycle to Resume Command Write Cycle) is not
included.
6.7
RC Oscillator Frequency
This chapter provides reference values for the RC Configuration Register (SYSC_RCCFGR) settings. The corresponding oscillator is commoly referred to as the “12 MHz RC Oscillator”, because its typical frequency at the central setting is about 12 MHz, with the SYSC_RCCFGR:SFREQ bit set to “1”.
When the SYSC_RCCFGR:SFREQ bit is set to “0”, the central setting corresponds to about 8 MHz.
The default value of SYSC_RCCFGR:SFREQ is “1” and the default value of SYSC_RCCFGR:TRM[7:0] is “0xFF”,
so the default frequency setting is 16.9 MHz (typical value).
Figure 6-14: RC Oscillator frequency at SYSC_RCCFGR:SFREQ = 0
MHz
RC Oscillator frequency
14.7
11.6
10.1
9.3
7.9
6.3
5.2
4.1
3.3
0x00
0x7F
0xFF
SYSC_RCCFGR:TRM[7:0] setting
Note: The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are
listed in Table 6-5 on page 356.
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Figure 6-15: RC Oscillator frequency at SYSC_RCCFGR:SFREQ = 1
MHz
21.3
RC Oscillator frequency
16.9
14.6
13.4
11.6
9.3
7.7
6.1
4.9
0x00
0x7F
0xFF
SYSC_RCCFGR:TRM[7:0] setting
Note: The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are
listed in Table 6-5 on page 356.
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7 Procedures
7.1
Boundary scan
Boundary scan is supported using standard IEEE 1149.1 JTAG interface. A 5-pin JTAG connection is available on
QFP-176 (production variant), as well as QFP-296 (bond-out variant). Instruction register supported is 6-bits wide,
and the standard instructions listed In Table 7-1 are supported. Any other value of instruction register is reserved,
and should not be entered. Entering reserved values can result in indeterminate operation.
Boundary scan mode may be entered by setting pins MODE = “1” and MD[0] = “0”.
Table 7-1: Supported Instructions
Instruction Code
(in binary)
Instruction
Accessible Data Register
‘000000’
EXTEST
Boundary scan chain
‘000001’
SAMPLE
Boundary scan chain
PRELOAD
Boundary scan chain
‘000011’
IDCODE
Device ID code register
For MB9DF126, IDCODE is
32-bits long, and is
0x0F147009
‘000100’
USERCODE
Device user code register
For MB9DF126, USERCODE is 32-bits long, and is
0xC4AA140B
‘000101’
HIGHZ
Boundary scan chain
‘000110’
CLAMP
Boundary scan chain
‘000010’
‘010001’
IO_CNTRL
IO Control register
‘111111’
BYPASS
Bypass register
Document Number: DS707-00002-4v1-E
Remarks
Command must be followed
by 16bit data value:
0x04pp,
where pp is a pin control setting from table 7-2
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Table 7-2: IO Control (IO_CNTRL) register
IO_CNTRL
reserved
reserved
reserved
DCPDN
DCPUP
OUTDR[1]
OUTDR[0]
PITILS[1]
PITILS[0]
R0W0
R0W0
RW
RW
RW
RW
RW
RW
0
R0W0
1
I2C
2
RW
3
SEL
4
RW
5
reserved
6
R0W0
7
reserved
8
R0W0
9
reserved
10
R0W0
11
reserved
12
R0W0
13
reserved
14
R0W0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-3: IO Control (IO_CNTRL) register bits
Bit Position
Bit FieldName
[15:11]
reserved
Reserved. Always write 0 to these bits.
[10]
SEL
Selection of DCPDN, DCPUP, OUTDR and PITILS
"0": IO_CNTRL[5:0] are disabled. Input buffers are disabled.
"1": IO_CNTRL[5:0] will control IO pads
[9]
I2C
Extends IO_CNTRL[3:2], but for I2C IO cell only (see below)
"0” : set I2C cell to value selected by IO_CNTRL[3:2]
"1" : set I2C cell to "pseudo open drain"
[8:6]
reserved
Reserved. Always write 0 to these bits.
[5]
DCPDN
Control all pull-down resistors of the IOs
Valid if bit [10] is "1"
"0” : All pull-downs are disabled
"1” : All pull-downs are enabled
[4]
DCPUP
Control all pull-up resistors of the IOs
Valid if bit [10] is "1"
"0” : All pull-uos are disabled
"1” : All pull-ups are enabled
Document Number: DS707-00002-4v1-E
Bit Description
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Table 7-3: IO Control (IO_CNTRL) register bits
Bit Position
Bit FieldName
[3:2]
OUTDR
Bit Description
Output driver strength
Valid if bit 10 is "1"
Bit selection depends on IO cell type (see chapter “IO Circuit Types”
on page 33)
OUTDR[1:0]
BIDI50
BIDI33
SMC
I2C
“00”
1mA±
12mA
1mA
1mA
“01”
5mA
12mA
30mA
5mA
“10”
2mA
12mA
2mA
2mA
“11”
2mA
12mA
5mA
2mA
-
-
-
pseudo
open drain
x + bit[9] = “1”
[1:0]
PITILS
Pin Input Test Input Level Select
Valid if bit 10 is "1"
"00”: Hysteresis
"01”: Automotive
"10”: TTL
"11”: CMOS
Note: When Bit[10] = “0”, all input buffers are disabled in Boundary Scan mode. Then, input of data via external
pins to the BSR (Boundary Scan Register) is impossible. Therefore, the minimum setting to allow input to
the BSR is 0x0400.
Procedure for Configuration for Port Input
1. MODE clipped to ’1’ and MD[0] clipped to ’0’.
2. release JTAG_NRST and RSTX.
3. JTAG-Instruction IO_CNTRL (010001)
4. set IO_CNTRL-reg 10th bit: (e.g. 0000010000000000)
5. JTAG-Instruction SAMPLE. -> Port Input
The serial chain starts with the I/O closest to JTAG_TDI pin, and ends with the I/O closest to the JTAG_TDO pin.
Details may be obtained from BSDL files released per package.
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7.2
Flash Parallel Programming
Flash Parallel Programming (FPP) mode is supported to allow for quick programming/erase of embedded flashes.
In this mode program or erase of flash is done using a flash memory programmer directly via external pins. Flash
programming is done either in 8-bit or 16-bit mode through the command sequence. Refer Section 4 of Tightly Coupled Flash Chapter of HWM for details of Flash program/erase command sequence. Flash addressing in this mode
is direct physical addressing, with higher order bits used for flash macro selection.
In MB9DF126 device, there are 2 flash macros of 1MB+64KB size each, and 1 flash macro of 64KB. Details about
flash macro sectoring are shown in Table 7-4
Table 7-4: Flash sector information
Flash Macro
Macro size
Small Sectors Large sectors
(8KB/sector) (64KB/sector)
TCFLASH macro 0
1MB + 64KB
8
16
TCFLASH macro 1
1MB + 64KB
8
16
EEFLASH macro
64KB
8
Not Available
Details about mapping of flash pins to external pins are presented in Table 7-5.
Table 7-5: Flash pin mapping to external pins
External Pin External Pin
External Pin
Number
Number
Name
(QFP-296)
(QFP-176)
Flash macro pin
Function
Flash select signal. Refer Table 7-10 for
additional details regarding use of DFSEL.
93
160
P3_24
DFSEL
126
204
XTAL0
FCLK
Flash clock
130
212
MODE
MODE
Mode pin to enter test mode (MODE = ‘1’)
131
214
RSTX
RSTX
Device Reset pin
103
172
P3_32
SMD[0]
Set to ‘1’ when entering FPP mode.
104
173
P1_26
SMD[1]
Set to ‘1’ when entering FPP mode.
105
174
P1_27
MD[2]
Set to ‘1’ when entering FPP mode.
106
175
P1_28
MD[1]
Set to ‘1’ when entering FPP mode.
107
176
P1_29
MD[0]
Set to ‘1’ when entering FPP mode.
External flash reset pin
98
167
P3_27
FRSTX
‘0’ : Reset
‘1’ : Normal operation
99
168
P3_28
FRSTRX
External power enable to flash macro at
5V
‘0’ : Reset
‘1’ : Normal operation
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Table 7-5: Flash pin mapping to external pins
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-296)
Flash macro pin
Function
Flash macro enable
6
11
P1_00
CEX
‘0’ : Macro recognizes read/write commands
‘1’ : Neither read operation nor write operation is executed
Write enable
146
252
P0_50
WEX
‘0’ : Macro recognizes write commands
‘1’ : Macro recognizes read commands
Byte access enable
147
253
P0_51
BYTEX
‘0’ : 8-bit write mode
‘1’ : 16-bit write mode
Direction control signal for shared pins
like data and ECC data
‘0’ : Shared data/ECC data pins are in
output mode
68
111
P3_33
OEX
‘1’ : Shared data/ECC data pins are in input mode
limitation applies for read (output) data
(they appear as logical ORed of all
FLASHs)
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Table 7-5: Flash pin mapping to external pins
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-296)
Flash macro pin
7
12
P1_01
FA[00]
8
14
P1_02
FA[01]
9
18
P1_03
FA[02]
10
19
P1_04
FA[03]
11
20
P1_05
FA[04]
12
21
P1_06
FA[05]
13
22
P1_07
FA[06]
16
27
P1_08
FA[07]
17
28
P1_09
FA[08]
18
29
P1_10
FA[09]
19
30
P1_11
FA[10]
20
31
P1_12
FA[11]
21
32
P1_13
FA[12]
22
33
P1_14
FA[13]
23
34
P1_15
FA[14]
26
41
P1_16
FA[15]
27
42
P1_17
FA[16]
28
43
P1_18
FA[17]
29
44
P1_19
FA[18]
30
45
P1_20
FA[19]
31
48
P1_21
FA[20]
32
49
P1_22
FA[21]
33
50
P1_23
FA[22]
Document Number: DS707-00002-4v1-E
Function
Flash address. Refer Table 7-10 for additional details regarding use of FA[21].
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Table 7-5: Flash pin mapping to external pins
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-296)
Flash macro pin
150
256
P2_32
DIN[00]/DOR[00]
151
258
P2_33
DIN[01]/DOR[01]
154
263
P2_34
DIN[02]/DOR[02]
155
264
P2_35
DIN[03]/DOR[03]
156
265
P2_36
DIN[04]/DOR[04]
157
266
P2_37
DIN[05]/DOR[05]
158
267
P2_38
DIN[06]/DOR[06]
159
268
P2_39
DIN[07]/DOR[07]
160
275
P2_40
DIN[08]/DOR[08]
161
276
P2_41
DIN[09]/DOR[09]
162
277
P2_42
DIN[10]/DOR[10]
163
278
P2_43
DIN[11]/DOR[11]
164
279
P2_44
DIN[12]/DOR[12]
165
280
P2_45
DIN[13]/DOR[13]
166
281
P2_46
DIN[14]/DOR[14]
167
282
P2_47
DIN[15]/DOR[15]
136
230
P0_40
EDIN[00]/EDOR[00]
137
231
P0_41
EDIN[01]/EDOR[01]
138
233
P0_42
EDIN[02]/EDOR[02]
139
234
P0_43
EDIN[03]/EDOR[03]
140
235
P0_44
EDIN[04]/EDOR[04]
141
245
P0_45
EDIN[05]/EDOR[05]
142
246
P0_46
EDIN[06]/EDOR[06]
Function
Shared data input/output
Refer Section 7.2.1.2 / 7.2.1.3
Shared ECC data input/output
Refer Section 7.2.1.2 / 7.2.1.3
ECC write access enable
70
113
P3_35
ECCA
‘0’ : ECC write disable
‘1’ : ECC write enable
Internal voltage ready/busy flag at 5V
144
248
P0_48
RDYR
‘0’ : Busy
‘1’ : Ready
FLASH internal state at PPROGRAM,
ERASE and power on
0: busy
145
249
P0_49
RDY
1: ready
Output behaves as open drain (needs
pull-up) to support programming multiple
devicves at once.
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Table 7-5: Flash pin mapping to external pins
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-296)
Flash macro pin
Function
64-bit read enable
69
112
P3_34
RD64
0 : 32-bit read mode
1 : 64-bit read mode
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Timing requirements for flash signals are provided in Figure 7-1:“Flash timing parameters” and Table 7-6:“Flash
timing requirements”.
Figure 7-1: Flash timing parameters
RDYR /
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Table 7-6: Flash timing requirements
Parameter
Symbol
Cycle Time
Value
Unit
tCY
min
100
ns
Clock High Time
tCWH
min
25
ns
Clock Low Time
tCWL
min
25
ns
CEX setup
tSCE
min
20
ns
CEX hold
tHCE
min
20
ns
WEX setup
tSWE
min
20
ns
WEX hold
tHWE
min
20
ns
RD64 setup
tSRD
min
20
ns
RD64 hold
tHRD
min
20
ns
BYTEX setup
tSBW
min
20
ns
BYTEX hold
tHBW
min
20
ns
ECCA setup
tSEC
min
20
ns
ECCA hold
tHEC
min
20
ns
OEX setup
tSOE
min
20
ns
OEX hold
tHOE
min
20
ns
DFSEL setup
tSDF
min
20
ns
DFSEL hold
tHDF
min
20
ns
FA setup
tSA
min
20
ns
FA hold
tHA
min
20
ns
DIN/EDIN setup
tSI
min
20
ns
DIN/EDIN hold
tHI
min
20
ns
RDY output delay
tACY
min
80
ns
DOR/EDOR
put delay
tACC
min
80
ns
tHD
min
5
ns
out-
DOR/EDOR hold
Note:
•
Input Data should change at falling edge of XTAL0 clock.
•
Output data should be sampled at next rising edge of XTAL0 clock.
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7.2.1
Memory Map
This flash memory consists of 16 sectors of 64k byte (large sector) and 8 sectors of 8k byte (small sector).
A large sector is composed of 16k word, and a small sector is composed of 2k word. 1word data width is 39bit
(regular bit: 32bit + ECC parity bit: 7bit) for both large sector and small sector.
7.2.1.1
Address Space & Memory Cell Select Address Assignment
The select address assignment is listed below. The assignment in the large sector and that in the small sector differ.
When the small sector (FA[20]=0) is selected, no matter what the values (1/0) of FA[19:16] are, the memory cell
to be used is determined according to the values of FA[15:0].
■ Large Sector (0x100000 ~ 0x1FFFFF)
Table 7-7: Large Sector (0x100000 ~ 0x1FFFFF)
• In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to the
corresponding pin. For the correspondence between data output pins and data input pins, see Section 7.2.1.2
and Section 7.2.1.3. Please note the limitation in section 7.2.1.2.
8bit program mode (BYTEX=0) : Ignore none of FA[20:0] and input 8bit selected in FA[20:0].
16bit program mode (BYTEX=1) : Ignore FA[0] and input 16bit.
•
FPP mode can only output 8 or 16 bit.
•
RD64 should always be kept 0.
•
BYTEX=0: DQ[7:0] is used
•
BYTEX=1: DQ[15:0] is used
■ Small Sector (0x0*0000 ~ 0x0*FFFF)
Table 7-8: Small Sector (0x0*0000 ~ 0x0*FFFF)
The left asterisk mark in the value indicates a given value (except an indeterminate value).
• When small sector is selected (FA[20]=0), input a given value (1/0) to FA[19:16] pins.
• In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to the
corresponding pin. For the correspondence between data output pins and data input pins, see Section 7.2.1.2
and Section 7.2.1.3. Please note the limitation in section 7.2.1.2.
8bit program mode (BYTEX=0) : Ignore none of FA[20,15:0] and input 8bit selected in FA[20,15:0].
16bit program mode (BYTEX=1) : Ignore FA[0] and input 16bit.
•
FPP mode can only output 8 or 16 bit.
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•
RD64 should always be kept 0.
•
BYTEX=0: DQ[7:0] is used
•
BYTEX=1: DQ[15:0] is used
7.2.1.2
LIMITATION ON MB9DF126 DEVICE
MB9DF126 device has the following limitation:
Reading works only, when both other FLASHs are programmed with all-0 (output data of 3 FLASHs is logically
ORed). Therefore, reading of FLASH is not supported.
•
Programming/erasing FLASH can be done by checking RDY, verifying of read data is not possible
•
It is recommended to choose a JTAG programmer
7.2.1.3
Input Data Table
In 8bit program mode, the data of the different input pins based on the FA[0] values is programmed as
shown in the Table 7-9:.
When ECCA=1 is input at the program data input, the data is written to ECC parity bit as well as Regular bit. When
ECCA=0 is input at the program data input, the data is written only to Regular bit. In this case, EDIN[6:0] input value
is "don’t care," and regardless of the value, no value is written to ECC parity bit. In the case of erase operation,
regardless of input values to ECCA, both Regular bit and ECC parity bit are erased together.
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Table 7-9: Correspondence Table of Data Input and Memory Cell Bit in Program Bit Modes
• "Any" a value of either 1 or 0.
• FA[#] indicates the lowest bit of sector-selected address, i.e. FA[16] when the large sector is selected
(FA[n]=1), and FA[13] when the small sector is selected (FA[n]=0). When programming, in both 8bit mode
and 16bit mode, program/erase operation is executed per one sector specified by the selected addresses.
• Program Data Input means the 4th write cycle of a program command in the normal operation state and the
2nd write cycle of a program command in the Unlock-bypass state.
• Command Data Input means the write cycles in the write command sequence other than those
mentioned above in which program data is input.
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7.2.2
Flash macro selection and address mapping in FPP
Individual flash macros can be accessed using the address decoding scheme as mentioned in Table 7-10.
Table 7-10: Flash macro selection
DFSEL
FA[21]
Flash Macro selection
0
0
TCFLASH macro 0
0
1
TCFLASH macro 1
1
X
EEFLASH macro
However, device level memory map differs from actual physical address to flash macro. Hence, it is expected that
the flash parallel programmer must translate CPU mode addressing to actual physical address to flash. Hence,
CPU execution code must be located at physical addresses that are mapped to the CPU mode addresses.
Translation of CPU mode address to actual physical address differs based on whether small or large sectors are
accessed. Address translation for small sectors of TCFLASH macro 0 and 1 is as shown in Table 7-11.
Table 7-11: TCFlash small sectors address translation
Flash Address Bit
CPU Address Bit
FA[21]
0
FA[20]
0
FA[19]
0
FA[18]
0
FA[17]
0
FA[16]
0
FA[15]
ADDR[15]
FA[14]
ADDR[14]
FA[13]
ADDR[02]
FA[12]
ADDR[13]
FA[11]
ADDR[12]
FA[10]
ADDR[11]
FA[09]
ADDR[10]
FA[08]
ADDR[09]
FA[07]
ADDR[08]
FA[06]
ADDR[07]
FA[05]
ADDR[06]
FA[04]
ADDR[05]
FA[03]
ADDR[04]
FA[02]
ADDR[03]
FA[01]
ADDR[01]
FA[00]
ADDR[00]
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Note:
Small sectors are interleaved (even and odd sectors). Even numbered sectors provide lower 4 byte and odd numbered sectors provide upper 4 byte of a 64 bit FLASH line.
Address translation for large sectors of TCFlash is shown in Table 7-12.
Table 7-12: TCFlash large sectors address translation
Flash Address Bit
CPU Address Bit
FA[21]
ADDR[03]
FA[20]
1
FA[19]
ADDR[20]
FA[18]
ADDR[19]
FA[17]
ADDR[18]
FA[16]
ADDR[02]
FA[15]
ADDR[17]
FA[14]
ADDR[16]
FA[13]
ADDR[15]
FA[12]
ADDR[14]
FA[11]
ADDR[13]
FA[10]
ADDR[12]
FA[09]
ADDR[11]
FA[08]
ADDR[10]
FA[07]
ADDR[09]
FA[06]
ADDR[08]
FA[05]
ADDR[07]
FA[04]
ADDR[06]
FA[03]
ADDR[05]
FA[02]
ADDR[04]
FA[01]
ADDR[01]
FA[00]
ADDR[00]
Note
•
Large sectors of TCFLASH are 4-times interleaved for best read performance (see also HW/Manual fig. 9.3-2
TCFLASH sector/address mapping - CPU mode).
•
Large sectors are interleaved (even and odd numbered sectors). Even numbered sectores provide lower 4 byte
and odd numbered sectors provide upper 4 byte of a 64 bit FLASH line.
•
Address space is interleaved between TCFLASH0 and TCFLASH1. TCFLASH0 keeps lower 8 byte and TCFLASH1 keeps upper 8 byte of a 128 bit FLASH line (2 FLASHs are read in parallel).
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EEFlash macro small sectors address translation is as shown in Table 7-13.
Table 7-13: EEFlash small sectors address translation
7.2.3
Flash Address Bit
CPU Address Bit
FA[15]
ADDR[15]
FA[14]
ADDR[14]
FA[13]
ADDR[13]
FA[12]
ADDR[12]
FA[11]
ADDR[11]
FA[10]
ADDR[10]
FA[09]
ADDR[09]
FA[08]
ADDR[08]
FA[07]
ADDR[07]
FA[06]
ADDR[06]
FA[05]
ADDR[05]
FA[04]
ADDR[04]
FA[03]
ADDR[03]
FA[02]
ADDR[02]
FA[01]
ADDR[01]
FA[00]
ADDR[00]
Flash Power On Sequence
Prior to entering flash parallel programming mode, the sequence mentioned below must be followed:
1. Apply following constant pin setting: MODE = 1 and MD[2:0] = 111. The pins for MD[2:0] have
pull-up, thus can be left open.
2. Assert RSTX = 0 and JTAG_nTRST = 0. The pin JTAG_nTRST has pull-down, so it will be
kept in reset by the device if it is left open. Asserting FRSTX = 0 and FRSTRX = 0 is optional. This
is done internally at device startup.
3. Ramp up the power supply (please refer to device specific datasheet for power supply
sequence) and wait till all power suppliess (VDP5, VDP3 & VDD) are stable
4.
Wait for at least 500ns after all power supplies are stable.
5.
De-assert RSTX= 1, also deassert FRSTX = 1 and FRSTRX = 1 if those were asserted before.
6. Wait until Flash Parallel Programming mode is entered by the bootROM program (boot time).
Wait time should be >=2.5 ms after RSTX release. Note that the wait time is necessary because
RDY pin is High-Z before FPP mode is entered. Looking at RDY (which has pull-up) alone would
cause mis-interpretation before that time is elapsed.
7. Flash access is possible after RDY pin goes to “1” . Clock supply is needed for monitoring
RDY.
RDY pin is pseudo open drain and thus needs a pull-up resistor. That makes it possible to program multiple devices
at once by using wired-AND of the RDY outputs, to detect when slowest device becomes ready.
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Failure to follow the above sequence can result in indeterminate behavior. Once the above sequence is completed,
flash parallel programming mode may be entered.
Flash parallel programming mode standard usage:
Entering FPP by releasing RSTX while keeping
•
MODE = ‘1’
•
MD[1] = ‘1’ , MD[0] = ‘1’
•
SMD[2] = ‘1’ , SMD[1] = ‘1’ , SMD[0] = ‘1’
Furthermore, Flash parallel programming mode may be entered using 2 options:
1.
Setting MCFG_DTAR:FPPREQ
2.
Setting MCFG_TSR:MD= ’XXX111’, and MCFG_TSR:SMD= ’11111’
Once flash parallel mode is requested, the bit SYSC_MCR:FPPEN is set, which enables entry to FPP mode. However, it must be noted that FPP access must also be enabled in Security Description Record (SDR) (see HWM).
The external programmer must also take care to program ECC bits for flash data contents. This also applies to
flash erase, where bit flipping (XOR with 0x73) is to be performed to handle ECC checking for erased flash.
Figure 7-2: Power On Sequence
VDP5
tRP
RSTX
VDD
XTAL0 / FCLK
tHCE
CEX
WEX,FA[n:0],ECCA
RD64,RD32,BYTEX
DIN[15:0],EDIN[6:0]
valid
tREGRDYR
tARYR
RDYR
RDY
tARY
tREGRDY
tACY
DQ[15:0],EDQ[6:0]
Recommendation: FRSTX = FRSTRX = ’1’
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Table 7-14: Timing parameters related to Power ON Sequence
Parameter
Symbol
Hardware Reset(FRSTX=0) period
Value
Unit
Min
Max
tRP
440
-
ns
Hardware Reset(RSTX=0) period
tRP
500
-
ns
FRSTRX fall to RDYR fall access
tARYR
-
80
ns
FRSTX fall to RDY reset
tARY
-
80
ns
FRSTRX rise to RDYR rise access
tREGRDYR
-
80
ns
FRSTRX rise to RDY rise access
tREGRDY
-
80
ns
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7.3
Debug and Trace
A standard 5-pin JTAG interface is supported for debug and trace. Conventional debug (core halted, and invasive)
as well as trace debug (core not halted and non-invasive) are supported. The procedures for debug and trace are
based on ARM Coresight technology. The features for debug are:
•
Secure mode entry for debugger
•
Up to 8 breakpoints, or 8 watchpoints
Tracing support is provided on both packages as shown below:
•
QFP-176: 4-bit, 8-bit trace data shared with resources.
•
QFP-296: 4-bit, 8-bit, 16-bit, and 32-bit trace data
Trace port to pin mapping in QFP-176 and QFP-296 packages is shown in Table 7-15.
Table 7-15: Trace port to external pin mapping
External
Pin
Number
(QFP-176)
External
Pin
Number
(QFP-296)
External Pin
Name
Trace Port
-
108
TRACECTL
CTL
-
107
TRACECLK
CLK
-
75
TRACE[00]
TRACE[00]
-
78
TRACE[01]
TRACE[01]
-
86
TRACE[02]
TRACE[02]
-
87
TRACE[03]
TRACE[03]
-
90
TRACE[04]
TRACE[04]
-
118
TRACE[05]
TRACE[05]
-
120
TRACE[06]
TRACE[06]
-
123
TRACE[07]
TRACE[07]
-
131
TRACE[8]
TRACE[08]
-
132
TRACE[9]
TRACE[09]
-
136
TRACE[10]
TRACE[10]
-
137
TRACE[11]
TRACE[11]
-
140
TRACE[12]
TRACE[12]
-
144
TRACE[13]
TRACE[13]
-
147
TRACE[14]
TRACE[14]
-
148
TRACE[15]
TRACE[15]
Package QFP-176 has no dedicated trace pins. Please see the Port Pin Multiplexing table in Chapter 3.2.1 for relevant pins and the corresponding settings for their activation.
In general, additional information regarding debug and trace methodology can be obtained from Coresight TRM
provided by ARM Limited. However, an additional characteristic is the support of security feature to prevent unau-
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thorized access through the debug port. At the time of initiating the debugger access, it depends on the security
configuration of the device, whether it is necessary to transmit a security key. The security key can only be transmitted once after reset. If a wrong key is entered, further accesses are disabled, and the only method to regain
access is through application of external reset.
In the device, trace support is provided for the following components/busses:
1.
Embedded Trace Macro (ETM) and Instrumentation Trace Macro (ITM) for processor core
2.
2 independent AHB bus trace macro (HTM) for up to 8 busses. Refer Table 7-16 for details
Further, Cross Trigger Interface (CTI) macros are included to support cross triggering among all the above macros.
Table 7-16: HTM trace sources
Bus
Width (bits)
Source ID
DMA master
64
1
PERI4 master
32
2
MEMORY_CONFIG slave
64
3
MCU_CONFIG slave
32
4
PERI5 slave
32
5
PERI3 slave
64
6
PERI4 slave
32
7
HSSPI slave
32
8
EBI slave
32
9
Power domain on/off status information can be obtained through debug port by accessing register on memory
mapped address 0xB0509400. This provides an easy method to obtain information on current state of power domains, without the need to access device level internal registers. Refer Table 7-17 for details.
Table 7-17: Power domain status information for debugger
Bit Number
31:3
Function
Reserved
PD4 on/off status
2
‘0’ : Power domain is off
‘1’ : Power domain is on
PD3 on/off status
1
‘0’ : Power domain is off
‘1’ : Power domain is on
PD2 on/off status
0
‘0’ : Power domain is off
‘1’ : Power domain is on
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In the QFP-296 pin package, trace data width settings are configurable on the non-shared pins through register at
memory mapped address 0xB0509404. This is highlighted in Table 7-18.
Table 7-18: Trace width setting on QFP-296 package
Bit Number
31:7
Function
Reserved
6
’1’ : Trace clock (CLK) is driven on pin
5
’1’ : Trace control (CTL) is driven on pin
4
’1’ : bits 31 to 16 of trace data are driven on pins
3
’1’ : bits 15 to 8 of trace data are driven on pins
2
’1’ : bits 7 to 4 of trace data are driven on pins
1
’1’ : bits 3 to 2 of trace data are driven on pins
0
’1’ : bits 1 to 0 of trace data are driven on pins
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8 Handling Devices
8.1
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD, VDP3 or VDP5) or less than (VSS) is applied to an input
or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device.
Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
8.2
Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to
pull-up or pull-down resistor (2K to 10K) or enable internal pullup or pulldown resistors (PUE/PDE) before the
input enable (PIE) is activated by software. The pins of circuit type MODE can be connected to VSS or VDP5 directly.
8.3
Power supply pins
In FCR4 series, devices including multiple power supply pins and ground pins are designed as follows: pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the
power supply pins and ground pins must be externally connected to the power supply and ground respectively in
order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to
follow the total output current ratings. Furthermore, the power supply pins and ground pins of the FCR4 series must
be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between
power supply pin and ground pin near this device.
If DVCC is not set to the same voltage level as AVDD5, the ZPD functionality of SMC pins cannot be used.
8.4
Power on sequence
At any time, the difference between the power supply pins belonging to the same voltage level must not exceed
0.5V. This especially applies to the power on sequence. Otherwise, the risk of latchup will increase. Figure 8-1
shows the power on sequence and the groups of power supply that might be used, depending on the actual application.
Furthermore, VDP5 supply must be switched on before any other power supply or at least at the same time. The
following conditions must be fulfilled at any moment:
1. The voltage of VDP5 must be higher or equal than the voltage on VDE5, AVDD5 and AVRH5.
2. For MB9DF126, MB9DF126B the voltage of VDP3 must be higher or equal than the voltage on VDD and VDDA. In
particular, VDP3 must not be switched off for saving power.
3. The supply voltage for MODE and RSTX pins must reach the minimum operational value before switching on
core voltage suppy.
4. APIX module, which is supplied by VDEA, must be able to receive a reset signal from the core domain, so the
corresponding power supply must be within the operational range while the reset occurs.
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Figure 8-1: Power on sequence
V
5.5V
5V
AVRH5 = AVDD5 = DVCC = VDP5 = VDE5
0.5V
3.6V
3.3V
VDEA / VDP3
3.0V
VDP5
0.5V
1.3V
1.2V
VDDA = VDD
1.1V
0.5V
t
RSTX pin
Internal RSTX
undefined
APIX RSTX
undefined
MODE pin
internal MODE
8.5
undefined
Pin State while Power-On-Reset
The following table shows the state of output/bidirectional pins during Power-On-Reset. For subsequent reset or
power saving states, the pin state can be programmed according to the possibilities listed in HWM. Before software
execution is started, however, the user must pay attention to the listed behavior.
Table 8-1: Pin state during active Power-On-Reset
Document Number: DS707-00002-4v1-E
Pin type
Reset state
JTAGO
HIZ
BIDI50
HIZ
BIDI33
HIZ
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Table 8-1: Pin state during active Power-On-Reset
8.6
Pin type
Reset state
SMC
HIZ
I2C
HIZ
SDOUT
HIZ
Crystal oscillator circuit
Noise in proximity to the XTAL0/X0/X0A and XTAL1/X1/X1A pins can cause the device to operate abnormally.
Printed circuit boards should be designed so that the XTAL0/X0/X0A and XTAL1/X1/X1A pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the XTAL0/X0/X0A and XTAL1/X1/
X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the related characteristics of the crystal and this device.
8.7
8.7.1
Notes on using external clock
Opposite phase clock supply: Oscillation Mode
When using the external clock, it is possible to simultaneously supply the XTAL0/X0/X0A and XTAL1/X1/X1A pins.
In the described combination XTAL0/X0/X0A should be supplied with a clock signal which has the opposite phase
to the XTAL1/X1/X1A pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is
because the XTAL1/X1/X1A pin stops at ”H” output in STOP mode).
With opposite phase supply at XTAL0/X0 and XTAL1/X1, a frequency up to 16 MHz is possible.
Figure 8-2: Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
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8.7.2
Single phase clock supply
For lower frequencies, up to 4 MHz, it is possible to supply a single phase clock at XTAL0/X0.
Figure 8-3: Example of using single phase supply
X0 (X0A)
X1 (X1A)
8.7.3
Single phase clock supply: Fast Clock Input Mode
When a high frequency clock needs to be fed, it is possible to directly supply a single phase clock at XTAL0/X0.
For this mode:
• SYSC_SPCCFGR:FCIMEN bit must be set to “1”.
• the input clock must have 50% duty cycle.
Figure 8-4: Example of using Fast Clock Input Mode
X0
X1
8.8
Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
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9 Ordering Information
Part number
Package
Remarks
MB9DF126PMC-GSE2
176-pin plastic LQFP
FPT-176-M07
Lead-free package
MB9DF126BPMC-GSE2
176-pin plastic LQFP
FPT-176-M07
Lead-free package
MB9DF126PFFS-ESE2
296-pin plastic LQFP
FPT-296P-M04
Trace variant
Lead-free package
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Revised November 4, 2015
Page 415
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