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The following document contains information on Cypress products.
S6J3110 Series
32-bit Microcontroller
Spansion® TraveoTM Family
S6J311AHAA / S6J3119HAA / S6J3118HAA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S6J311A_DS708-00004
CONFIDENTIAL
Revision 1.0
Issue Date January 16, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered
may occur."
Questions regarding these document designations may be directed to your local sales office.
2
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
S6J3110 Series
32-bit Microcontroller
Spansion® TraveoTM Family
S6J311AHAA / S6J3119HAA / S6J3118HAA
Data Sheet (Full Production)
1. Description
This section provides an overview of the S6J3110 series.
®
The S6J3110 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM
Cortex-R5 CPU as a CPU.
Note:
−
®
ARM, Cortex , Thumb are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number S6J311A_DS708-00004
Revision 1.0
Issue Date January 16, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems
the products to have been in sufficient production volume such that subsequent versions of this document are not expected to
change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Table of Contents
1.
Description.......................................................................................................................................... 3
2.
Features .............................................................................................................................................. 5
2.1
Cortex-R5 Core ........................................................................................................................ 5
2.2
Peripheral Functions ................................................................................................................ 6
3.
Product Lineup ................................................................................................................................... 9
4.
Pin Assignment ................................................................................................................................ 11
5.
Pin Description ................................................................................................................................. 12
6.
I/O Circuit Types ............................................................................................................................... 22
7.
Handling Precautions ...................................................................................................................... 25
7.1
Precautions for Product Design.............................................................................................. 25
7.2
Precautions for Package Mounting ........................................................................................ 27
7.3
Precautions for Use Environment........................................................................................... 29
8.
Handling Devices ............................................................................................................................. 30
9.
Block Diagram .................................................................................................................................. 33
10. Memory Map ..................................................................................................................................... 34
11. Pin Status in CPU Status ................................................................................................................. 39
12. Electrical Characteristics................................................................................................................. 42
12.1 Absolute Maximum Ratings.................................................................................................... 42
12.2 Recommended Operating Conditions .................................................................................... 44
12.3 DC Characteristics ................................................................................................................. 45
12.4 AC Characteristics ................................................................................................................. 53
12.4.1 Source Clock Timing .................................................................................................. 53
12.4.2 Internal Clock Timing ................................................................................................. 55
12.4.3 Reset Input................................................................................................................. 59
12.4.4 Power-on Conditions .................................................................................................. 60
12.4.5 Multi-function Serial.................................................................................................... 61
12.5 Timer Input Timing ................................................................................................................. 81
12.6 Trigger Input Timing ............................................................................................................... 82
12.7 NMI Input Timing .................................................................................................................... 83
12.8 Low-Voltage Detection (External Low-Voltage Detection) ...................................................... 84
12.9 Low-Voltage Detection (Internal Low-Voltage Detection) ....................................................... 85
12.10 Low-Voltage Detection (1.2 V Power Supply Low-Voltage Detection) ................................... 85
12.11 A/D Converter ........................................................................................................................ 86
12.11.1
Electrical Characteristics .................................................................................. 86
12.11.2
Notes on Using A/D Converters ....................................................................... 88
12.11.3
Definition of terms ............................................................................................ 89
12.12 Flash Memory ........................................................................................................................ 91
13. Ordering Information ....................................................................................................................... 92
14. Part Number Option ......................................................................................................................... 92
15. Package Dimensions ....................................................................................................................... 93
16. Major Changes.................................................................................................................................. 94
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
2. Features
This section explains the features of the S6J3110 series.
2.1
Cortex-R5 Core
This section explains the Cortex-R5 CPU core.
− ARM® Cortex®-R5
− 32-bit ARM architecture
−
2-instruction issuance super scalar
−
8-stage pipeline
− ARMv7/Thumb®-2 instruction set
− MPU (memory protection) equipped
−
16-area support
− ECC support for the TCM ports
1-bit error correction and 2-bit error detection (SEC-DED)
− TCM ports
2 TCM ports
−
ATCM port
−
BTCM port (B0TCM, B1TCM)
− Caches
−
Instruction cache 16 KB
−
Data cache 16 KB
− VIC port
Low latency interrupt
− AXI master interface
64-bit AXI interface (instruction/data access)
32-bit AXI interface (I/O access)
− AXI slave interface
64-bit AXI interface (TCM port access)
− ETM-R5 trace
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CONFIDENTIAL
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2.2
Peripheral Functions
This section explains peripheral functions.
− Clock generation
−
Main clock oscillation (4 MHz)
−
No sub clock oscillation
−
CR oscillation (100 kHz)
−
CR oscillation (4 MHz)
− Built-in flash memory size
−
Program: 1024 K + 64 KB (S6J311AHAA) / 768 K + 64 KB (S6J3119HAA) / 512 K + 64 KB
(S6J3118HAA)
−
Work: 48 KB (S6J311AHAA) / 48 KB (S6J3119HAA) / 48 KB (S6J3118HAA)
− Built-in RAM size
−
TCRAM 64 KB (S6J311AHAA) / 48 KB (S6J3119HAA) / 32 KB (S6J3118HAA)
−
System SRAM 16 KB (S6J311AHAA) / 16 KB (S6J3119HAA) / 16 KB (S6J3118HAA)
−
Backup RAM 8 KB (S6J311AHAA) / Backup RAM 8 KB (S6J3119HAA) / Backup RAM 8 KB
(S6J3118HAA)
− General-purpose ports: 116 channels (S6J311AHAA) / 116 channels (S6J3119HAA) / 116 channels
(S6J3118HAA)
− DMA controller
−
Up to 16 channels can be activated simultaneously.
− A/D converter (successive approximation type)
−
12-bit resolution, 2 units mounted: Max 56 channels (25 channels + 31 channels)
(S6J311AHAA) / Max 56 channels (25 channels + 31 channels) (S6J3119HAA) / Max 56
channels (25 channels + 31 channels) (S6J3118HAA)
− External interrupt input: 16 channels
−
Level ("H"/"L") and edge (rising/falling) can be detected.
− Multi-function serial (transmission and reception FIFOs mounted) :Max 4 channels (S6J311AHAA)
/ Max 4 channels (S6J3119HAA) / Max 4 channels (S6J3118HAA)
<UART (asynchronous serial interface) >
−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Parity check can be enabled/disabled.
−
Built-in dedicated baud rate generator
−
An external clock can be used as a transfer clock.
−
Parity, frame, overrun error detection functions are available.
−
DMA transfer is supported.
<CSIO (synchronous serial interface) >
−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Support for SPI. Both master and slave roles are supported. Data length in bits can be set to a
value from 5 to 16 or one of the values of 20, 24, and 32.
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CONFIDENTIAL
−
Built-in dedicated baud rate generator (master operation)
−
External clock input is enabled (slave operation).
−
Overrun error detection function is available.
−
DMA transfer is supported.
−
Serial chip select SPI function
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
<LIN-UART (asynchronous serial interface for LIN) >
−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Support for LIN protocol revision 2.1
−
Both master and slave roles are supported.
−
Framing error and overrun error detection
−
LIN Synch break generation and detection, LIN Synch Delimiter generation
−
Built-in dedicated baud rate generator
−
The external clock can be adjusted by the reload counter.
DMA transfer is supported.
− CAN controller: CAN-FD Max 1 channel
−
CAN transfer speed :Max 5Mbps
−
CAN Clock :Max 40MHz
−
192 message buffers/channel (reception message buffer size)
− Base timer: Max 30 channels
−
16bit Timer.
−
It is selectable by 4 functions of the PWM/PPG/PWC/Reload Timer.
−
2-channel cascade connection enables operation as a 32-bit timer.(PWC and Reload Timer)
− Free-run timer: Max 6 channels
−
32bit Timer.
−
Main clock oscillation and CR oscillation are available.
−
Free-run timer output can work in combination with an input capture and an output compare.
− Input capture: Max 12 channels
−
32bit Timer.
− Output compare: Max 12 channels
−
32bit Timer.
− Real time clock (RTC) (day/hour/minute/second)
−
Main clock oscillation or CR oscillation (100 kHz) can be selected as an operation clock.
− Calibration: Real time clock (RTC) driven by the CR clock
−
Correction can be done by configuring the prescaler of the real time clock based on the ratio
between the main clock and the CR clock.
− Clock supervisor
−
Abnormality (such as damaged crystal) of the main clock oscillation (4 MHz) can be monitored.
−
The clock can switch to the CR clock when an abnormality is detected.
−
PLL abnormality can be detected.
− CRC generation
−
Fixed-length CRC
−
CCITT CRC16 generator polynomial: 0x1021
−
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
− Watchdog timer
−
Hardware watchdog
−
Software watchdog
− NMI
− I/O relocation
−
Peripheral function pin locations can be changed.
− Low-power consumption control
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D a t a S h e e t
−
Standby function
−
Power-off function
− Power-on reset
− Low-voltage detection reset
− Security
−
Flash security
−
Interface security (JTAG + test port)
−
SHE
−
Unique device ID
− Package: LEU144 (S6J311xHAA)
− CMOS 55 nm technology
− Power supply
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CONFIDENTIAL
−
5 V single power supply
−
The voltage step-down circuit generates internal 1.2 V from 5 V.
−
5 V power supply is used for I/O.
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
3. Product Lineup
The following table lists the product lineup of the S6J3110 series.
Table 3-1 Memory Size
Flash
RAM
Program
S6J311AHAA
S6J3119HAA
S6J3118HAA
1024K bytes
768K bytes
512K bytes
+
+
+
Small sector (8 KB x 8)
Small sector (8 KB x 8)
Small sector (8 KB x 8)
Work
48K bytes
48K bytes
48K bytes
TCRAM
64K bytes
48K bytes
32K bytes
System SRAM
16K bytes
16K bytes
16K bytes
Backup RAM
8K bytes
8K bytes
8K bytes
Table 3-2 Product Lineup
S6J311xHAA
CPU core
CMOS 55 nm technology
Package
Main clock
Built-in CR oscillator
Maximum CPU operating frequency
Watchdog timer
Coretex-R5
55 nm
LEU144
4 MHz
100 kHz
4 MHz
96 MHz
1 channel (hardware)
1 channel (software)
Clock supervisor
YES
External power supply, low-voltage detection reset
YES
Internal power supply, low-voltage detection reset
YES
NMI request
YES
External interrupt
16 channels
DMA controller
16 channels
CAN-FD
Multi-function serial
1 channel
(192 msg buffers/ch)
4 channels
12-bit (2 units)
A/D converter
Unit 0 x 25 channels
Unit 1 x 31 channels
Free-run timer
6 channels
Input capture
12 channels
Output compare
12 channels
Base timer (16-bit)
30 channels
Real time clock (RTC)
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
1 channel
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D a t a S h e e t
S6J311xHAA
CR clock calibration
YES
CRC generation
YES
Low-power consumption mode
SHE
General-purpose port GPIO
Standby function
Power-off function
YES
116 channels
Power supply
5 V + 5% to 10%
Operation assurance temperature (TA)
-40 °C to +125 °C
On-chip debugger (JTAG)
10
CONFIDENTIAL
YES
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
4. Pin Assignment
The following figures show the pin assignment of the S6J3110 series.
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VCC
P421/SIN2_1/TRACECTL
P420/SCK2_1/TRACECLK
P418/INT14_0/SCS22_0
P417/INT15_1/TIOA23_1
P416/IN5_0/TIOA22_1
P414/SCS21_0
P413/INT14_1/SCS20_0
P411/INT13_1/SCK2_0/TRACEDATA7
P409/SOT2_0/TIOA24_1/TRACEDATA6
P408/INT12_0/SIN2_0/TRACEDATA5
P407/TRACEDATA4
P406/TRACEDATA3
P405/INT11_0/IN4_0/TRACEDATA2
P404/IN3_0/TRACEDATA1
P403/IN2_0/TRACEDATA0
P402/INT2_0/IN1_0
P401/IN0_0
C
VSS
VCC
RSTX
P400
P331
VSS
X1
X0
MD
P330
P327
TCK
TMS
TDI/P324
TDO/P323
TRST/P322
VCC
Figure 4-1 Pin Assignment for S6J311xHAA
VSS
P000/SOT2_1
P001/SCS20_1
P003/SCS22_1
P005/SIN3_0/IN6_0
P006/SOT3_0/IN7_0
P007/SCK3_0/IN8_0
P008/SCS30_0/IN9_0/TIOA0_0
P009/INT0_1/IN10_0/TIOA1_0
P010/IN11_0/TIOA2_0
P012/OUT5_0/TIOA3_0
P013/OUT6_0/TIOA4_0
P015/OUT7_0/TIOA5_0
P016/OUT8_0/TIOA6_0
P017/OUT9_0/TIOA7_0
P018/OUT10_0/TIOA8_0
P019/TEXT0_0/OUT11_0/TIOB0_0
P020/SOT0_0/TEXT1_0/TIOB1_0
P021/SCK0_0/TIOB2_0
P022/INT3_0/SIN0_0/TIOB3_0
P023/SCS0_0/TIOB4_0
P024/TIOB5_0
P027/INT1_1/TEXT0_1/TIOB6_0/TIOA4_1
P028/INT4_0/SIN1_0/OUT0_1/TIOB7_0
P029/AN0/SOT1_0/OUT1_1
P030/OUT2_1
P031/AN1/SCS1_0/OUT3_1
P100/AN2/SCK1_0/OUT4_1
P101/AN3/OUT5_1
P103/AN5/OUT6_1
P105/OUT7_1/TIOA9_0
P106/OUT8_1
P107/INT2_1/OUT9_1/TIOA10_0
P108/INT3_1/AN6/OUT10_1/TIOA11_0
P109/OUT11_1/TIOA12_0
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
●
TOP VIEW
LEU144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
P321
VSS
VCC
P317/INT11_1/AN62/TIOA9_1
P315/AN61/IN5_1/TIOA8_1
P314/AN60/IN4_1/TIOA7_1
P313/INT10_1/AN59/IN3_1
P312/AN58/IN2_1
P309/AN57/IN1_1/TIOA29_1
P308/AN56/IN0_1/TIOA28_1
P307/INT1_0/AN55/RX0_0
P306/AN54/TX0_0
NMIX
P305/AN53/TEXT5_0/TIOA29_0
P304/AN52/TEXT4_0/TIOA20_1
P302/AN51/TIOA19_1
P301/AN50/OUT4_0/TIOA18_1
P300/AN49/OUT3_0/TIOA28_0
P231/AN48/OUT2_0/TIOA27_0
P230/AN47/OUT1_0/TIOA26_0
P229/INT8_0/AN46/RX0_1/OUT0_0/TIOA25_0
P228/AN45/TX0_1/TIOA24_0
P227/AN44/TIOA23_0
AVCC1
AVRH1
AVSS1/AVRL1
P226/AN43/IN11_2/TIOA17_1
P225/INT0_0/AN42/RX0_2/IN10_2
P224/AN41/TX0_2/IN9_2
P223/AN40/IN8_2
P222/INT7_0/AN39/IN7_2
P220/AN38/IN6_2
P219/AN37/TEXT3_0
P218/AN36/TEXT2_0
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P215/INT9_1/IN5_2/TIOA16_1
P214/IN4_2/TIOA15_1
P213/INT8_1/IN3_2/TIOA14_1
P212/AN35/IN2_2/TIOA13_1
P211/AN34/IN1_2/TIOA22_0
P210/INT6_0/AN33/IN0_2/TIOA21_0
P209/AN32/TIOA20_0
P208/AN31/TIOA19_0
P207/INT7_1/AN30/TEXT5_1
P206/AN29/TEXT4_1
P205/AN28/TEXT3_1
P204/AN27/IN11_1
P203/IN10_1
P202/INT6_1/IN9_1
P131/AN24/IN8_1
P130/INT5_0/AN23/IN7_1
P129/AN22/IN6_1
P128/AN21/TEXT2_1
P127/AN20/TEXT1_1
P126/AN19
P123/AN18/TIOA12_1
P122/AN17/TIOA11_1
P120/AN15
P119/AN14
P118/INT5_1/AN13
P117/INT4_1/AN12
P115
AVSS0/AVRL0
AVRH0
AVCC0
P114/AN10/TIOA6_1
P113/TIOA5_1
P112/AN9/TIOA13_0
C
VSS
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
11
D a t a S h e e t
5. Pin Description
This section provides a list of the pin functions of the S6J3110 series
Table 5-1 S6J311xHAA Pin Functions
Pin No.
S6J311xHAA
2
3
4
5
6
7
8
9
10
11
12
13
14
12
CONFIDENTIAL
I/O
Pin Name
Polarity
Circuit
Function
Type
P000
-
SOT2_1
-
P001
-
SCS20_1
-
P003
-
SCS22_1
-
P005
-
IN6_0
-
SIN3_0
-
Multi-function serial ch.3 serial data input pin (0)
P006
-
General-purpose I/O port
IN7_0
-
SOT3_0
-
Multi-function serial ch.3 serial data output pin (0)
P007
-
General-purpose I/O port
IN8_0
-
SCK3_0
-
Multi-function serial ch.3 clock I/O pin (0)
P008
-
General-purpose I/O port
IN9_0
-
SCS30_0
-
TIOA0_0
-
Base timer ch.0 TIOA output pin (0)
P009
-
General-purpose I/O port
IN10_0
-
TIOA1_0
-
INT0_1
-
INT0 external interrupt input pin (1)
P010
-
General-purpose I/O port
IN11_0
-
TIOA2_0
-
P012
-
TIOA3_0
-
OUT5_0
-
P013
-
TIOA4_0
-
OUT6_0
-
P015
-
TIOA5_0
-
OUT7_0
-
P016
-
TIOA6_0
-
OUT8_0
-
P
P
P
General-purpose I/O port
Multi-function serial ch.2 serial data output pin (1)
General-purpose I/O port
Multi-function serial ch.2 serial chip select 0 I/O pin (1)
General-purpose I/O port
Multi-function serial ch.2 serial chip select 2 output pin (1)
General-purpose I/O port
P
P
P
P
P
P
Input capture ch.6 input pin (0)
Input capture ch.7 input pin (0)
Input capture ch.8 input pin (0)
Input capture ch.9 input pin (0)
Multi-function serial ch.3 serial chip select 0 I/O pin (0)
Input capture ch.10 input pin (0)
Base timer ch.1 TIOA I/O pin (0)
Input capture ch.11 input pin (0)
Base timer ch.2 TIOA output pin (0)
General-purpose I/O port
P
Base timer ch.3 TIOA I/O pin (0)
Output compare ch.5 output pin (0)
General-purpose I/O port
P
Base timer ch.4 TIOA output pin (0)
Output compare ch.6 output pin (0)
General-purpose I/O port
P
Base timer ch.5 TIOA I/O pin (0)
Output compare ch.7 output pin (0)
General-purpose I/O port
P
Base timer ch.6 TIOA output pin (0)
Output compare ch.8 output pin (0)
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Pin No.
S6J311xHAA
15
16
17
18
19
20
21
22
23
24
25
26
I/O
Pin Name
Polarity
Function
Type
P017
-
TIOA7_0
-
OUT9_0
-
Output compare ch.9 output pin (0)
P018
-
General-purpose I/O port
TIOA8_0
-
OUT10_0
-
Output compare ch.10 output pin (0)
P019
-
General-purpose I/O port
OUT11_0
-
TIOB0_0
-
TEXT0_0
-
Free-run timer 0 clock input pin (0)
P020
-
General-purpose I/O port
General-purpose I/O port
P
P
P
Base timer ch.7 TIOA I/O pin (0)
Base timer ch.8 TIOA output pin (0)
Output compare ch.11 output pin (0)
Base timer ch.0 TIOB input pin (0)
SOT0_0
-
TIOB1_0
-
TEXT1_0
-
P021
-
SCK0_0
-
TIOB2_0
-
P022
-
General-purpose I/O port
SIN0_0
-
Multi-function serial ch.0 serial data input pin (0)
TIOB3_0
-
INT3_0
-
INT3 external interrupt input pin (0)
P023
-
General-purpose I/O port
SCS0_0
-
TIOB4_0
-
P024
-
TIOB5_0
-
P027
-
General-purpose I/O port
TIOA4_1
-
Base timer ch.4 TIOA output pin (1)
TIOB6_0
-
INT1_1
-
INT1 external interrupt input pin (1)
TEXT0_1
-
Free-run timer 0 clock input pin (1)
P028
-
General-purpose I/O port
SIN1_0
-
TIOB7_0
-
INT4_0
-
INT4 external interrupt input pin (0)
OUT0_1
-
Output compare ch.0 output pin (1)
P029
-
General-purpose I/O port
SOT1_0
-
AN0
-
OUT1_1
-
P030
-
OUT2_1
-
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Circuit
P
Multi-function serial ch.0 serial data output pin (0)
Base timer ch.1 TIOB input pin (0)
Free-run timer 1 clock input pin (0)
General-purpose I/O port
P
Multi-function serial ch.0 clock I/O pin (0)
Base timer ch.2 TIOB input pin (0)
P
P
Base timer ch.3 TIOB input pin (0)
Multi-function serial ch.0 serial chip select I/O pin (0)
Base timer ch.4 TIOB input pin (0)
P
P
General-purpose I/O port
Base timer ch.5 TIOB input pin (0)
Base timer ch.6 TIOB input pin (0)
Multi-function serial ch.1 serial data input pin (0)
P
A
Base timer ch.7 TIOB input pin (0)
Multi-function serial ch.1 serial data output pin (0)
ADC analog 0 input pin
Output compare ch.1 output pin (1)
P
General-purpose I/O port
Output compare ch.2 output pin (1)
13
D a t a S h e e t
Pin No.
S6J311xHAA
27
28
29
30
31
32
33
34
35
39
40
41
45
46
14
CONFIDENTIAL
I/O
Pin Name
Polarity
Circuit
Function
Type
P031
-
General-purpose I/O port
SCS1_0
-
AN1
-
OUT3_1
-
P100
-
General-purpose I/O port
SCK1_0
-
Multi-function serial ch.1 clock I/O pin (0)
AN2
-
OUT4_1
-
Output compare ch.4 output pin (1)
P101
-
General-purpose I/O port
AN3
-
OUT5_1
-
P103
-
AN5
-
OUT6_1
-
P105
-
TIOA9_0
-
OUT7_1
-
P106
-
OUT8_1
-
P107
-
TIOA10_0
-
INT2_1
-
OUT9_1
-
P108
-
General-purpose I/O port
AN6
-
ADC analog 6 input pin
TIOA11_0
-
INT3_1
-
INT3 external interrupt input pin (1)
OUT10_1
-
Output compare ch.10 output pin (1)
P109
-
General-purpose I/O port
TIOA12_0
-
OUT11_1
-
Output compare ch.11 output pin (1)
P112
-
General-purpose I/O port
AN9
-
TIOA13_0
-
P113
-
TIOA5_1
-
P114
-
AN10
-
TIOA6_1
-
P115
-
P117
-
AN12
-
INT4_1
-
A
Multi-function serial ch.1 serial chip select I/O pin (0)
ADC analog 1 input pin
Output compare ch.3 output pin (1)
A
A
ADC analog 2 input pin
ADC analog 3 input pin
Output compare ch.5 output pin (1)
General-purpose I/O port
A
ADC analog 5 input pin
Output compare ch.6 output pin (1)
General-purpose I/O port
P
Base timer ch.9 TIOA I/O pin (0)
Output compare ch.7 output pin (1)
P
General-purpose I/O port
Output compare ch.8 output pin (1)
General-purpose I/O port
P
Base timer ch.10 TIOA output pin (0)
INT2 external interrupt input pin (1)
Output compare ch.9 output pin (1)
A
P
A
Base timer ch.11 TIOA I/O pin (0)
Base timer ch.12 TIOA output pin (0)
ADC analog 9 input pin
Base timer ch.13 TIOA I/O pin (0)
P
General-purpose I/O port
Base timer ch.5 TIOA I/O pin (1)
General-purpose I/O port
A
ADC analog 10 input pin
Base timer ch.6 TIOA output pin (1)
P
General-purpose I/O port
A
ADC analog 12 input pin
General-purpose I/O port
INT4 external interrupt input pin (1)
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Pin No.
S6J311xHAA
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
I/O
Pin Name
Polarity
Function
Type
P118
-
AN13
-
INT5_1
-
P119
-
AN14
-
P120
-
AN15
-
P122
-
General-purpose I/O port
A
ADC analog 13 input pin
INT5 external interrupt input pin (1)
A
A
General-purpose I/O port
ADC analog 14 input pin
General-purpose I/O port
ADC analog 15 input pin
General-purpose I/O port
AN17
-
TIOA11_1
-
Base timer ch.11 TIOA I/O pin (1)
P123
-
General-purpose I/O port
A
A
ADC analog 17 input pin
AN18
-
TIOA12_1
-
P126
-
AN19
-
P127
-
AN20
-
TEXT1_1
-
Free-run timer 1 clock input pin (1)
P128
-
General-purpose I/O port
AN21
-
TEXT2_1
-
P129
-
IN6_1
-
AN22
-
P130
-
General-purpose I/O port
IN7_1
-
Input capture ch.7 input pin (1)
AN23
-
INT5_0
-
INT5 external interrupt input pin (0)
P131
-
General-purpose I/O port
IN8_1
-
AN24
-
ADC analog 24 input pin
P202
-
General-purpose I/O port
IN9_1
-
INT6_1
-
P203
-
IN10_1
-
P204
-
IN11_1
-
AN27
-
P205
-
AN28
-
TEXT3_1
-
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Circuit
ADC analog 18 input pin
Base timer ch.12 TIOA output pin (1)
A
General-purpose I/O port
ADC analog 19 input pin
General-purpose I/O port
A
A
ADC analog 20 input pin
ADC analog 21 input pin
Free-run timer 2 clock input pin (1)
General-purpose I/O port
A
Input capture ch.6 input pin (1)
ADC analog 22 input pin
A
A
P
ADC analog 23 input pin
Input capture ch.8 input pin (1)
Input capture ch.9 input pin (1)
INT6 external interrupt input pin (1)
P
General-purpose I/O port
Input capture ch.10 input pin (1)
General-purpose I/O port
A
Input capture ch.11 input pin (1)
ADC analog 27 input pin
General-purpose I/O port
A
ADC analog 28 input pin
Free-run timer 3 clock input pin (1)
15
D a t a S h e e t
Pin No.
S6J311xHAA
62
63
64
65
66
67
68
69
70
71
74
75
16
CONFIDENTIAL
I/O
Pin Name
Polarity
Circuit
Function
Type
P206
-
General-purpose I/O port
AN29
-
TEXT4_1
-
A
ADC analog 29 input pin
Free-run timer 4 clock input pin (1)
P207
-
General-purpose I/O port
AN30
-
INT7_1
-
TEXT5_1
-
P208
-
AN31
-
TIOA19_0
-
Base timer ch.19 TIOA I/O pin (0)
P209
-
General-purpose I/O port
A
ADC analog 30 input pin
INT7 external interrupt input pin (1)
Free-run timer 5 clock input pin (1)
General-purpose I/O port
A
A
ADC analog 31 input pin
AN32
-
TIOA20_0
-
ADC analog 32 input pin
Base timer ch.20 TIOA output pin (0)
P210
-
General-purpose I/O port
IN0_2
-
AN33
-
TIOA21_0
-
Base timer ch.21 TIOA I/O pin (0)
INT6_0
-
INT6 external interrupt input pin (0)
P211
-
General-purpose I/O port
IN1_2
-
AN34
-
TIOA22_0
-
Base timer ch.22 TIOA output pin (0)
P212
-
General-purpose I/O port
IN2_2
-
AN35
-
TIOA13_1
-
P213
-
General-purpose I/O port
IN3_2
-
Input capture ch.3 input pin (2)
TIOA14_1
-
INT8_1
-
INT8 external interrupt input pin (1)
P214
-
General-purpose I/O port
IN4_2
-
TIOA15_1
-
Base timer ch.15 TIOA I/O pin (1)
P215
-
General-purpose I/O port
IN5_2
-
TIOA16_1
-
INT9_1
-
INT9 external interrupt input pin (1)
P218
-
General-purpose I/O port
Input capture ch.0 input pin (2)
A
A
A
ADC analog 33 input pin
Input capture ch.1 input pin (2)
ADC analog 34 input pin
Input capture ch.2 input pin (2)
ADC analog 35 input pin
Base timer ch.13 TIOA I/O pin (1)
P
P
P
A
Base timer ch.14 TIOA output pin (1)
Input capture ch.4 input pin (2)
Input capture ch.5 input pin (2)
Base timer ch.16 TIOA output pin (1)
AN36
-
TEXT2_0
-
Free-run timer 2 clock input pin (0)
P219
-
General-purpose I/O port
AN37
-
TEXT3_0
-
A
ADC analog 36 input pin
ADC analog 37 input pin
Free-run timer 3 clock input pin (0)
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Pin No.
S6J311xHAA
76
77
78
79
80
81
85
86
87
88
89
I/O
Pin Name
Polarity
Function
Type
P220
-
IN6_2
-
AN38
-
ADC analog 38 input pin
P222
-
General-purpose I/O port
IN7_2
-
AN39
-
INT7_0
-
P223
-
IN8_2
-
AN40
-
ADC analog 40 input pin
P224
-
General-purpose I/O port
IN9_2
-
TX0_2
-
AN41
-
P225
-
General-purpose I/O port
IN10_2
-
Input capture ch.10 input pin (2)
RX0_2
-
AN42
-
ADC analog 42 input pin
INT0_0
-
INT0 external interrupt input pin (0)
P226
-
General-purpose I/O port
IN11_2
-
Input capture ch.11 input pin (2)
AN43
-
TIOA17_1
-
P227
-
AN44
-
TIOA23_0
-
P228
-
General-purpose I/O port
TX0_1
-
CAN transmission data 0 output pin (1)
AN45
-
TIOA24_0
-
Base timer ch.24 TIOA output pin (0)
P229
-
General-purpose I/O port
RX0_1
-
CAN reception data 0 input pin (1)
AN46
-
TIOA25_0
-
INT8_0
-
INT8 external interrupt input pin (0)
OUT0_0
-
Output compare ch.0 output pin (0)
P230
-
General-purpose I/O port
General-purpose I/O port
A
A
Input capture ch.6 input pin (2)
Input capture ch.7 input pin (2)
ADC analog 39 input pin
INT7 external interrupt input pin (0)
General-purpose I/O port
A
A
Input capture ch.8 input pin (2)
Input capture ch.9 input pin (2)
CAN transmission data 0 output pin (2)
ADC analog 41 input pin
A
A
CAN reception data 0 input pin (2)
ADC analog 43 input pin
Base timer ch.17 TIOA I/O pin (1)
General-purpose I/O port
A
ADC analog 44 input pin
Base timer ch.23 TIOA I/O pin (0)
A
A
ADC analog 45 input pin
ADC analog 46 input pin
Base timer ch.25 TIOA I/O pin (0)
AN47
-
TIOA26_0
-
OUT1_0
-
Output compare ch.1 output pin (0)
P231
-
General-purpose I/O port
AN48
-
TIOA27_0
-
OUT2_0
-
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Circuit
A
A
ADC analog 47 input pin
Base timer ch.26 TIOA output pin (0)
ADC analog 48 input pin
Base timer ch.27 TIOA I/O pin (0)
Output compare ch.2 output pin (0)
17
D a t a S h e e t
Pin No.
S6J311xHAA
90
91
92
93
94
95
96
97
98
99
100
101
18
CONFIDENTIAL
I/O
Pin Name
Polarity
Circuit
Function
Type
P300
-
General-purpose I/O port
AN49
-
TIOA28_0
-
OUT3_0
-
P301
-
General-purpose I/O port
AN50
-
ADC analog 50 input pin
TIOA18_1
-
OUT4_0
-
Output compare ch.4 output pin (0)
P302
-
General-purpose I/O port
AN51
-
TIOA19_1
-
P304
-
General-purpose I/O port
AN52
-
ADC analog 52 input pin
TIOA20_1
-
TEXT4_0
-
Free-run timer 4 clock input pin (0)
P305
-
General-purpose I/O port
A
ADC analog 49 input pin
Base timer ch.28 TIOA output pin (0)
Output compare ch.3 output pin (0)
A
A
Base timer ch.18 TIOA output pin (1)
ADC analog 51 input pin
Base timer ch.19 TIOA I/O pin (1)
A
Base timer ch.20 TIOA output pin (1)
AN53
-
TIOA29_0
-
TEXT5_0
-
NMIX
N
P306
-
TX0_0
-
AN54
-
ADC analog 54 input pin
P307
-
General-purpose I/O port
RX0_0
-
AN55
-
INT1_0
-
INT1 external interrupt input pin (0)
P308
-
General-purpose I/O port
IN0_1
-
AN56
-
TIOA28_1
-
P309
-
General-purpose I/O port
IN1_1
-
Input capture ch.1 input pin (1)
AN57
-
A
ADC analog 53 input pin
Base timer ch.29 TIOA I/O pin (0)
Free-run timer 5 clock input pin (0)
F
Non-maskable interrupt input pin
General-purpose I/O port
A
A
A
CAN transmission data 0 output pin (0)
CAN reception data 0 input pin (0)
ADC analog 55 input pin
Input capture ch.0 input pin (1)
ADC analog 56 input pin
Base timer ch.28 TIOA output pin (1)
A
ADC analog 57 input pin
TIOA29_1
-
Base timer ch.29 TIOA I/O pin (1)
P312
-
General-purpose I/O port
IN2_1
-
AN58
-
ADC analog 58 input pin
P313
-
General-purpose I/O port
IN3_1
-
AN59
-
INT10_1
-
A
A
Input capture ch.2 input pin (1)
Input capture ch.3 input pin (1)
ADC analog 59 input pin
INT10 external interrupt input pin (1)
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Pin No.
S6J311xHAA
I/O
Pin Name
Polarity
Circuit
Function
Type
P314
-
IN4_1
-
AN60
-
TIOA7_1
-
P315
-
General-purpose I/O port
IN5_1
-
Input capture ch.5 input pin (1)
AN61
-
TIOA8_1
-
Base timer ch.8 TIOA output pin (1)
P317
-
General-purpose I/O port
AN62
-
TIOA9_1
-
INT11_1
-
P321
-
TRST
N
P322
-
TDO
-
P323
-
TDI
-
P324
-
113
TMS
-
E
JTAG test mode state input pin
114
TCK
-
E
JTAG test clock input pin
115
P327
-
P
General-purpose I/O port
116
P330
-
P
General-purpose I/O port
117
MD
-
C
Mode pin
118
X0
-
G
Main clock oscillation input pin
119
X1
-
G
Main clock oscillation output pin
121
P331
-
P
General-purpose I/O port
122
P400
-
P
General-purpose I/O port
123
RSTX
N
F
External reset input pin
P401
-
IN0_0
-
P402
-
IN1_0
-
INT2_0
-
INT2 external interrupt input pin (0)
P403
-
General-purpose I/O port
IN2_0
-
TRACEDATA0
-
Trace data 0 output pin
P404
-
General-purpose I/O port
IN3_0
-
TRACEDATA1
-
102
103
104
107
110
111
112
127
128
129
130
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
General-purpose I/O port
A
Input capture ch.4 input pin (1)
ADC analog 60 input pin
Base timer ch.7 TIOA I/O pin (1)
A
A
ADC analog 61 input pin
ADC analog 62 input pin
Base timer ch.9 TIOA I/O pin (1)
INT11 external interrupt input pin (1)
D
J
I
D
Q
General-purpose output port
JTAG test reset input pin
General-purpose output port
JTAG test data output pin
General-purpose output port
JTAG test data input pin
General-purpose output port
General-purpose I/O port
Input capture ch.0 input pin (0)
General-purpose I/O port
Q
Q
Q
Input capture ch.1 input pin (0)
Input capture ch.2 input pin (0)
Input capture ch.3 input pin (0)
Trace data 1 output pin
19
D a t a S h e e t
Pin No.
S6J311xHAA
I/O
Pin Name
Polarity
Circuit
Function
Type
P405
-
IN4_0
-
INT11_0
-
TRACEDATA2
-
P406
-
TRACEDATA3
-
P407
-
TRACEDATA4
-
P408
-
General-purpose I/O port
SIN2_0
-
Multi-function serial ch.2 serial data input pin (0)
INT12_0
-
TRACEDATA5
-
Trace data 5 output pin
P409
-
General-purpose I/O port
SOT2_0
-
TIOA24_1
-
TRACEDATA6
-
Trace data 6 output pin
P411
-
General-purpose I/O port
SCK2_0
-
INT13_1
-
TRACEDATA7
-
P413
-
SCS20_0
-
INT14_1
-
P414
-
SCS21_0
-
P416
-
IN5_0
-
TIOA22_1
-
Base timer ch.22 TIOA output pin (1)
P417
-
General-purpose I/O port
TIOA23_1
-
INT15_1
-
INT15 external interrupt input pin (1)
P418
-
General-purpose I/O port
SCS22_0
-
INT14_0
-
INT14 external interrupt input pin (0)
P420
-
General-purpose I/O port
SCK2_1
-
TRACECLK
-
Trace clock
P421
-
General-purpose I/O port
SIN2_1
-
TRACECTL
-
42
AVCC0
-
-
Analog power supply pin for AD converter unit 0
84
AVCC1
-
-
Analog power supply pin for AD converter unit 1
43
AVRH0
-
-
Upper-limit reference voltage pin for AD converter unit 0
131
132
133
134
135
136
137
138
139
140
141
142
143
20
CONFIDENTIAL
General-purpose I/O port
Q
Input capture ch.4 input pin (0)
INT11 external interrupt input pin (0)
Trace data 2 output pin
Q
Q
Q
Q
Q
General-purpose I/O port
Trace data 3 output pin
General-purpose I/O port
Trace data 4 output pin
INT12 external interrupt input pin (0)
Multi-function serial ch.2 serial data output pin (0)
Base timer ch.24 TIOA output pin (1)
Multi-function serial ch.2 clock I/O pin (0)
INT13 external interrupt input pin (1)
Trace data 7 output pin
General-purpose I/O port
Q
Multi-function serial ch.2 serial chip select 0 I/O pin (0)
INT14 external interrupt input pin (1)
Q
General-purpose I/O port
Multi-function serial ch.2 serial chip select 1 output pin (0)
General-purpose I/O port
Q
Q
Q
Q
Q
Input capture ch.5 input pin (0)
Base timer ch.23 TIOA I/O pin (1)
Multi-function serial ch.2 serial chip select 2 output pin (0)
Multi-function serial ch.2 clock I/O pin (1)
Multi-function serial ch.2 serial data input pin (1)
Trace control
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Pin No.
S6J311xHAA
83
44
82
38
126
I/O
Pin Name
Polarity
Circuit
Function
Type
AVRH1
-
-
AVSS0
-
AVRL0
-
AVSS1
-
AVRL1
-
C
-
-
External capacity connection output pin
VCC
-
-
Power supply pin
VSS
-
-
-
Upper-limit reference voltage pin for AD converter unit 1
GND pin for AD converter unit 0
Lower-limit reference voltage pin for AD converter unit 0
GND pin for AD converter unit 1
Lower-limit reference voltage pin for AD converter unit 1
36
72
105
109
124
144
1
37
73
106
GND
108
120
125
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
21
D a t a S h e e t
6. I/O Circuit Types
This section explains I/O circuit types.
Type
A
Circuit
Overview
Pull-up control
Digital output
Digital output
Pull-down control
− General-purpose I/O port with analog input
− Output of 1 mA or 2 mA selectable
− 50 kΩ with pull-up resistor control
− 50 kΩ with pull-down resistor control
− CMOS hysteresis input
CMOS input
PSS control
Analog input
B
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
Analog input
C
− General-purpose I/O port with analog input
− Output of 1 mA or 2 mA selectable
− 50 kΩ with pull-up resistor control
− 50 kΩ with pull-down resistor control
− Automotive/CMOS hysteresis input selectable
− Mode input
− CMOS hysteresis input
Mode
input
Control
D
− JTAG
Pull-up control
Digital output
Digital output
− General-purpose output port
− Output of 2 mA
− 50 kΩ with pull-up resistor control
− TTL input
TTL input
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Type
Circuit
Overview
E
− JTAG
Pull-up control
− 50 kΩ with pull-up resistor control
− TTL input
TTL input
F
− CMOS hysteresis input
− 50 kΩ with pull-up resistor
CMOS-hys input
G
Input
− Main oscillation I/O
Standby
control
I
− JTAG
− Output of 2 mA
Digital output
Digital output
J
− JTAG
Digital output
Digital output
Pull-down control
− General-purpose output port
− Output of 2 mA
− 50 kΩ with pull-down resistor control
− TTL input
TTL input
P
Pull-up control
Digital output
Digital output
Pull-down control
− General-purpose I/O port
− Output of 1 mA or 2 mA selectable
− 50 kΩ with pull-up resistor control
− 50 kΩ with pull-down resistor control
− CMOS hysteresis input
CMOS input
PSS control
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
Type
Q
Circuit
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
24
CONFIDENTIAL
Overview
− General-purpose I/O port
− Output of 1 mA or 2 mA selectable
− 50 kΩ with pull-up resistor control
− 50 kΩ with pull-down resistor control
− Automotive/CMOS hysteresis input selectable
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
7. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
7.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not
exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the
data sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to
power supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to
cause deterioration within the device, and in extreme cases leads to permanent damage of
the device. Try to prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large
capacitance can cause large current flows. Such conditions if present for extended periods
of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of
operation. Such pins should be connected through an appropriate resistance to a power
supply pin or ground pin.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate.
When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor
structures) may be formed, causing large current levels in excess of several hundred mA to flow
continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This
should include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and
standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment,
personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy
controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are
requested to consult with sales representatives before such use. The company will not be responsible for
damages arising from such use without prior approval.
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
7.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion’s recommended conditions. For
detailed information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute
ratings for storage temperature. Mounting processes should conform to Spansion recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces
can lead to contact deterioration after long periods. For this reason it is recommended that the surface
treatment of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore
leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin
pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to
solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages
in accordance with Spansion ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental
conditions will cause absorption of moisture. During mounting, the application of heat to a package that
has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages
to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the
product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity,
and at temperatures between 5 ˚C and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their
aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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27
D a t a S h e e t
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the
Spansion recommended conditions for baking.
Condition: 125 ˚C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must
take the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through
high resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures
to minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed
board assemblies.
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
7.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit
boards. If high humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause
abnormal operation. In such cases, use anti-static measures or processing to prevent
discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that
will adversely affect the device. If you use devices in such conditions, consider ways to
prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic
radiation. Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near
combustible substances. If devices begin to smoke or burn, there is danger of the release of
toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
January 16, 2015, S6J311A_DS708-00004-1v0-E
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29
D a t a S h e e t
8. Handling Devices
For Latch-up Prevention
The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an
input or output pin is higher than VCC or lower than VSS; or the voltage applied between a VCC pin and
a VSS pin exceeds the rating. A latch-up causes a rapid increase in the power supply current, possibly
resulting in thermal damage to an element. When using the device, take sufficient care not to exceed
the maximum rating.
Also be careful that analog power supplies (AVCC0, AVCC1, AVRH0, and AVRH1) and analog inputs
do not exceed the digital power supply (VCC) at the analog system power-on and power-off times.
The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and
analog supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1), or turn on the digital supply voltage
(VCC) and then the analog supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1).
About Handling Unused Pins
Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take
measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kiloohms
or higher.
If there are any unused input/output pins, set them to the output state and then open them, or set them
to the input state and handle them in the same way as input pins.
About Power Supply Pins
If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that
should be at the same potential are connected to each other inside the device to prevent malfunctions
such as latch-up. However, to reduce unwanted emissions, prevent malfunctions of strobe signals
caused by an increase of the ground level, and observe standards on total output current, be sure to
connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS
power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS
systems, the device does not operate normally even within the guaranteed operating range.
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Figure 8-1 Pin Assignment
In addition, consider connecting with low impedance from the power supply source to the VCC and
VSS of this device.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of
C pin is recommended to use as a bypass capacitor between the VCC pin and the VSS pin.
About the Crystal Oscillation Circuit
Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a
way that the X0 and X1 pins, the crystal oscillator (or ceramic resonator), and a bypass capacitor to
ground are located very close to the device.
We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground.
About the Mode Pin (MD)
Use mode pin MD by directly connecting it to a VCC or VSS pin. To prevent noise from causing the
device to accidentally enter test mode, reduce the pattern length between each mode pin and a VCC
or VSS pin on the printed circuit board, and connect them with low impedance.
About the Power-on Time
To prevent the internal built-in voltage step-down circuit from malfunctioning, secure a voltage rise time
of 50 µs (between 0.2 V and 2.7 V) or longer at the power-on time.
Point to Note during PLL Clock Operation
While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue
operating with the free running frequency of the internal self-oscillator circuit. This operation is outside
of the guaranteed range.
Power Supply Pin Processing of an A/D Converter
Even when no A/D converter is used, establish a connection such that AVCC=AVRH=VCC and
AVSS/AVRL=VSS.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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31
D a t a S h e e t
Points to Note about Using External Clocks
External clocks are not supported.
External direct clock input cannot be used.
Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter
Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC,
AVRH, and AVRL) and analog inputs (AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to
AN24, and AN27 to AN62) of an A/D converter.
At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn
off the digital power supply (VCC). Perform these power-on and power-off operations without AVRH
exceeding AVCC. Even when using a pin shared with an analog input as an input port, do not allow the
input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital supply voltage
simultaneously is not a problem.)
About C Pin Processing
This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin (pin
126 in S6J311xHAA specifications) for internal stabilization of the device. For the standard values, see
"Recommended operating conditions" in the latest data sheet.
Precautions on Designing a Mounting Substrate
Measures against heat generation from the package must be taken for the mounting substrate to
observe the absolute maximum rating (operating temperature). Design a mounting substrate with 4 or
more layers. Connect the back of the package stage and the substrate pad with solder paste. Arrange
thermal via holes on the substrate pad. For detailed information about mount conditions, contact your
sales representative.
Notes on Writing to a Register Containing a Status Flag
In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a
function, it is important to take care not to accidentally clear the status flag.
Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then
set the control bit to the desired value.
Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit
instructions have only 1-bit access). In such cases, byte, half-word, or word access is used to write to
the control bits and a status flag simultaneously. However, at this time, be careful not to accidentally
clear bits other than the intended ones (the status flag bit in this case).
Note: Bit instructions take this point into account for registers that support bit-band units, so it does not
need to be a concern. You need to take care when using bit instructions for registers that do not
support bit-band units.
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
9. Block Diagram
This section provides block diagrams of the S6J3110 series.
Figure 9-1 S6J311xHAA Block Diagram
Trace I/F(8Pin)
Debug I/F (JTAG/SWD)
Power Domain 2
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
Bus Config Group
From/To PPU-SLAVEs
- Bus Performance Counters
- Misc Register Module
DAP
CLK_DBG
CLK_LLPBM2
Security
APB-M
PPU Master
APB-S
AHB-M
CLK_HPM
Debug APB
CLK_HPM
Trace Group
CLK_CPU
CLK_DBG
ATB
CLK_ATB
Core Group (1-Core)
Power Domain 3
Security
Checker
ETB (Trace Buffer)
16KB
CLK_TRC
From/To
CommonPERI#2
From/To
CommonPERI#2
AHB2APB
(Priviledge
Protection)
APB-32
CLK_LLPBM2
Debug APB
TCFLASH #0
1MB/768KB/521KB + 64KB
+
EEFlash #0
48KB
WorkFlash
TCF
AHB-64
AHB-64
(Reg & Data) (Reg)
AHB-64
CLK_MEMC
AXI-64
CLK_SHE
CLK_SHE
TCF
AXI-64
(data)
CLK_MEMC
CLK_FCLK
CLK_SHE
CLK_CPU
Flash Group
SHE Group
AHB-32
From/To
Memory Config Grp.
ETMTM
#0
TCF
ATCM #0
TCRAM #0
(2bank)
64KB
(32KB×2)/
48KB
(24KB×2)/
32KB
(16KB×2)
AXI-64
CPU #0
B0TCM
- DMAC 16.ch
- ReloadTimer 4ch
CLK_DMA
MPU
#0
AXI-64
CLK_CPU
D$
#0
I$
#0
16KB
16KB
CLK_HPM
LLPP
AXI32-M AHB32
AXI-M AXI-S
CLK_CPU
DMAC Complex #0
CortexTM -R5F
B1TCM
#0
ATCM
#0
AHB-64
CLK_MEMC
From/To
Memory Config Grp.
Procceser
AXI-64
CLK_CPU
AXI-32
CLK_CPU
From/To CommonPERI#2
DMAC Config
AHB-32
CLK_CPU
AHB-32
CLK_HPM2
AHB-64
CLK_HPM
AHB-32
CLK_HPM2
High Performance Matrix (HPM)
AXI-64
CLK_HPM
System SRAM
16KB
AHB-32
AXI-64
AHB-32
CLK_HPM
CLK_SYSC1
EAM
CLK_MEMC
CLK_HPM
AHB-32
CLK_CPU
AHB-64
CLK_HPM
From/To
Flash Group
BBU
BBU
AHB-32
CLK_LLPBM
Low Latency Peripheral Bus Matrix (LLPBM)
AHB-32
CLK_LLPBM
AHB-32
BBU
BBU
CLK_SYSC0H
Power Domain 6_0
System
Controller(SYSC)
(CLK_CAN)
CLK_LCP
BootROM
16KB
SW-Watchdog
CSV(for PLL)
Timing
Protection
SYSC1
Fast-CR
Slow-CR
PLL0
SSCG PLL0
CLK_MEMC
State manage
LVD
CLK_CAN
C
Peripheral
Bus Bridge
RAM
CRC
4ch
#0 TCRAM
(Config)
Peripheral
Bus Bridge
CLK_LLPBM2
P
Bus Config
Group
(Config)
GPIO
32Bit FRT
6ch
DMAC
Complex #0
(Config)
32Bit ICU
12ch
PPU Master
(Cnofig)
32Bit OCU
12ch
Memory & Config Group
CLK_MEMC
Power Domain 3
P
M.F.S
4ch
Wakeup
Request #0
Peripheral
Bus Bridge
CLK_HPM
CLK_LCP0A
Base Timer
30ch
RAM
PONR
CSV
CAN-FD
1ch
IRC #0
512 Vectors
Power manage
Source Clock
Timer
CLK_LCP0A
(TPU) #0
CLK_SYSC1
Clock manage
EICU 16ch
Backup RAM 4KB
(8+5 bit width RAM x 4)
Power CLK_RAM1H
Domain 4_1
CAN prescaler
Backup RAM 4KB
(8+5 bit width RAM x 4)
Power CLK_RAM0H
Domain 4_0
Reset manage
CLK_LLPBM
CLK_LLPBM
Flash Group I/F
Clock divide
and distribution
CLK_COMH
ECC-ed RAM I/F
State manage (2)
From/To
Core-Group
AHB-32
CLK_LLPBM
BBU
Common PERI #0
Group
12Bit A/DC
Unit0×25ch
Common PERI #1
Group
Common PERI #2
Group
Wakeup-detect
RTC
12Bit A/DC
Unit1×31ch
Clock Calibration
H/W Watchdog
EXT-IRQ
16ch
Common PERI #0
Group
Power Domain 1 (Always on)
NMI
MCU Config Group
Power Domain 1
(Always on)
January 16, 2015, S6J311A_DS708-00004-1v0-E
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33
D a t a S h e e t
10. Memory Map
This section explains the memory map.
Figure 10-1 Memory Map
Address
START
END
group
0x0000_0000
0x0000_7FFF
0x0000_8000
0x0000_BFFF
0x0000_C000
0x0000_FFFF
S6J311AHAA
S6J3119HAA
part
part
part
TCRAM
TCRAM
TCRAM
(Main 64KByte)
(Main 48KByte)
(Main 32KByte)
S6J3118HAA
Reserved
Reserved
Reserved
0x0001_0000
0x007F_FFFF
Reserved
Reserved
Reserved
0x0080_0000
0x008F_FFFF
Reserved
Reserved
Reserved
TCM_FLASH
TCM_FLASH
TCM_FLASH
(Small Sector 8KByte×8)
(Small Sector 8KByte×8)
(Small Sector 8KByte×8)
TCM_FLASH
TCM_FLASH
TCM_FLASH
(Code 1MByte)
(Code 768KByte)
(Code 512KByte)
Reserved
Reserved
0x009F_0000
0x009F_FFFF
0x00A0_0000
0x00A7_FFFF
0x00A8_0000
0x00AB_FFFF
0x00AC_0000
0x00AF_FFFF
Reserved
Internal area for CR5
Complex
0x00B0_0000
0x00DF_FFFF
0x00E0_0000
0x0100_0000
0x00FF_FFFF
Reserved
Reserved
Reserved
Reserved
0x018F_FFFF
Reserved
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
0x019F_FFFF
(Small Sector 8KByte×8 *Mirror)
(Small Sector 8KByte×8 *Mirror)
(Small Sector 8KByte×8 *Mirror)
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
0x01A7_FFFF
(Code 1MByte *Mirror)
(Code 768KByte *Mirror)
(Code 512KByte *Mirror)
Reserved
Reserved
0x019F_0000
0x01A0_0000
0x01A8_0000
0x01AB_FFFF
0x01AC_0000
0x01AF_FFFF
Reserved
Reserved
Reserved
0x01B0_0000
0x01DF_FFFF
0x01E0_0000
Reserved
Reserved
0x01FF_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYSTEM SRAM
SYSTEM SRAM
SYSTEM SRAM
0x0200_3FFF
(16KByte)
(16KByte)
(16KByte)
0x0200_4000
0x0203_FFFF
Reserved
Reserved
Reserved
0x0204_0000
0x027F_FFFF
Reserved
Reserved
Reserved
0x0280_0000
0x0280_002F
Exclusive Access Memory
Exclusive Access Memory
Exclusive Access Memory
0x0280_0030
0x03FF_FFFF
Reserved
Reserved
Reserved
0x0400_0000
0x05FF_FFFF
AXI_SLAVE_CORE0
AXI_SLAVE_CORE0
AXI_SLAVE_CORE0
Reserved
Reserved
Reserved
0x0200_0000
0x0600_0000
0x0DFF_FFFF
0x0E00_0000
WORK_FLASH
WORK_FLASH
WORK_FLASH
0x0E00_BFFF
(48KByte mirror area 1)
(48KByte mirror area 1)
(48KByte mirror area 1)
0x0E00_C000
0x0E01_BFFF
Reserved
Reserved
Reserved
0x0E01_C000
0x0E0F_FFFF
Reserved
Reserved
Reserved
0x0E10_0000
0x0E1F_FFFF
0x0E20_0000
Shared Flash and memory
area
Reserved
Reserved
Reserved
WORK_FLASH
WORK_FLASH
WORK_FLASH
(48KByte mirror area 3)
0x0E20_BFFF
(48KByte mirror area 3)
(48KByte mirror area 3)
0x0E20_C000
0x0E21_BFFF
Reserved
Reserved
0x0E21_C000
0x0E2F_FFFF
Reserved
Reserved
Reserved
WORK_FLASH
WORK_FLASH
WORK_FLASH
(48KByte mirror area 4)
0x0E30_0000
Reserved
0x0E30_BFFF
(48KByte mirror area 4)
(48KByte mirror area 4)
0x0E30_C000
0x0E31_BFFF
Reserved
Reserved
Reserved
0x0E31_C000
0x0E3F_FFFF
Reserved
Reserved
Reserved
0x0E40_0000
Reserved
Reserved
Reserved
Backup RAM
Backup RAM
Backup RAM
0x0E80_1FFF
0x0E7F_FFFF
8KByte
8KByte
8KByte
0x0E80_2000
0x0E80_FFFF
Reserved
Reserved
Reserved
0x0E81_0000
0x0E87_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0E80_0000
0x0E88_0000
0x0FFF_FFFF
0x1000_0000
Reserved
0xAFFF_FFFF
0xB000_0000
0xB483_FFFF
Peri_area
Peri_area
Peri_area
0xB484_0000
0xB484_FFFF
APPS#5
APPS#5
APPS#5
Peri_area
Peri_area
Peri_area
Reserved
Reserved
Reserved
Reserved
ERRCFG
ERRCFG
ERRCFG
ERRCFG
BootROM
BootROM
BootROM
Reserved
Reserved
Reserved
0xB485_0000
Peri area
0xB7FF_FFFF
0xB800_0000
0xFFFE_DFFF
34
CONFIDENTIAL
0xFFFE_E000
0xFFFE_FFFF
0xFFFF_0000
0xFFFF_3FFF
0xFFFF_4000
0xFFFF_FFFF
BootROM
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Only the CPU core can access 0000_0000 ~ 01FF_FFFF. Bus masters other than the CPU core
cannot access the region.
Internal area of CR5 complex (0000_0000 ~ 01FF_FFFF) is mapped to AXI_SLAVE_CORE0. All bus
masters can access to internal area of CR5 complex via AXI_SLAVE_CORE0.
In each of the following memory area combinations, the areas are physically the same memory area.
1. TCM FLASH (0x00A0_0000 -) and AXI FLASH MEMORY (0x01A0_0000 -)
2. TCM FLASH Small Sector (0x009F_0000 -) and AXI FLASH MEMORY Small Sector
(0x019F_0000 -)
3. WORKFLASH (0x0E00_0000 -), WORKFLASH (0x0E20_0000 -), and WORKFLASH
(0x0E30_0000 -)
− The differences between the TCM FLASH and AXI FLASH include the following.
Function
High-speed Access Using Dedicated Bus
Write and Erase
TCM FLASH
AXI FLASH
Applicable
Not applicable
Not applicable
Applicable
(Read-only)
Read
Applicable
Applicable
− The differences between WORKFLASH areas include the following.
Area
Function
WORKFLASH Area 1
Used in write operation (with ECC)
WORKFLASH Area 3
Used in write operation (without ECC)
WORKFLASH Area 4
Used in read operation
− Terms are as follows.
Term
Description
TCM RAM
Main RAM
TCM FLASH
Program FLASH (TCM area)
AXI FLASH
Program FLASH (AXI area)
This is physically the same as the TCM FLASH.
SYSTEM RAM
System RAM
AXI SLAVE CORE
AXI CPU control area
WORKFLASH
FLASH for work
BACKUP RAM
Backup RAM
Peri area
Entire area for peripheral functions
APPS#5
Part of area for peripheral functions
ERRCFG
Error configuration area
BootROM
ROM for reset boot
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
35
D a t a S h e e t
S6J311xHAA Peripheral Map
START
Address
B000_0000
B010_8000
B010_8100
B030_0000
B030_8000
B040_0000
B040_8000
B041_0000
B041_1000
B041_2000
B041_2100
B050_0000
B060_0000
B060_0080
B060_0100
B060_0180
B060_0200
B060_0280
B060_0300
B060_0380
B060_0400
B060_0480
B060_0500
B060_0600
B060_0680
B060_0700
B060_0800
B060_C000
B061_0000
B061_8000
B062_0000
B064_0000
B066_0000
B068_0000
B068_8000
B068_8400
B068_8800
B068_8C00
B069_0000
B070_0000
B080_0000
B100_0000
B110_0000
B120_0000
B200_0000
B210_0000
B470_0000
B470_4000
B471_0000
B471_1000
B471_4000
B471_5000
B471_8000
B471_8400
B471_8800
B471_8C00
B471_9000
B473_8000
B474_0000
B474_8000
B475_0000
B475_8000
B478_FC00
B479_0000
36
CONFIDENTIAL
END
Address
B010_7FFF
B010_80FF
B02F_FFFF
B030_7FFF
B03F_FFFF
B040_7FFF
B040_FFFF
B041_0FFF
B041_1FFF
B041_20FF
B04F_FFFF
B05F_FFFF
B060_007F
B060_00FF
B060_017F
B060_01FF
B060_027F
B060_02FF
B060_037F
B060_03FF
B060_047F
B060_04FF
B060_05FF
B060_067F
B060_06FF
B060_07FF
B060_BFFF
B060_FFFF
B061_7FFF
B061_FFFF
B063_FFFF
B065_FFFF
B067_FFFF
B068_7FFF
B068_83FF
B068_87FF
B068_8BFF
B068_FFFF
B06F_FFFF
B07F_FFFF
B0FF_FFFF
B10F_FFFF
B11F_FFFF
B1FF_FFFF
B20F_FFFF
B46F_FFFF
B470_3FFF
B470_FFFF
B471_0FFF
B471_3FFF
B471_4FFF
B471_7FFF
B471_83FF
B471_87FF
B471_8BFF
B471_8FFF
B473_7FFF
B473_FFFF
B474_7FFF
B474_FFFF
B475_7FFF
B478_FBFF
B478_FFFF
B47F_FFFF
Group
SystemSRAM
SYSC1
SYSC1
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
Bit RMW alias
Bit RMW alias
Bit RMW alias
SHE
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
Function
Reserved
SystemSRAM registers
Reserved
System Controller #1
SWDT
IRC0
TPU0
TCRAM Control Status Register
TCFlash Control Status Register
WFlash Control Status Register
Reserved
Reserved
Protection register area
RUN profile register area
PSS profile register area
APP profile register area
STS profile register area
System register area
CSV
RESET
SCT(Fast CR)
SCT(Slow CR)
SCT(Main clock)
Clock System
Special register area
Debug register area
Mode
HWDT
Reserved
RTC
EIC
Reserved
Reserved
BURAMIF
EICU
CR_Calibration
IRQ all
CAN Prescaler
Reserved
Reserved
Bit RMW alias for MCU config Gr (Covers B060_0000 -- B06F_FFFF)
Bit RMW alias for SYSC1 (Covers B030_0000 -- B031_FFFF)
Bit RMW alias for MEMC (Covers B040_0000 -- B041_FFFF)
Reserved
SHE configuration registers
Reserved
DMAC #0 registers
Reserved
MPU for DMAC#0
Reserved
DMA Complex #0 registers (Additional registers, RLTs)
Reserved
CRC#0
CRC#1
CRC#2
CRC#3
Reserved
GPIO
PPC
RIC
PPU
Reserved
Reserved
Reserved
PPU No
21
19
16
17
18
34
33
35
32
37
38
42
43
63
64
66
68
70
71
72
73
74
75
76
-
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
START
Address
B480_0000
B480_0400
B480_0800
B480_0C00
B480_1000
B480_8000
B480_8400
B480_8800
B480_8C00
B480_9000
B480_9400
B480_9800
B480_9C00
B480_A000
B480_A400
B480_A800
B480_AC00
B480_B000
B482_0000
B482_0400
B482_0800
B482_0C00
B482_1000
B482_1400
B482_1800
B482_8000
B482_8400
B482_8800
B482_8C00
B482_9000
B482_9400
B482_9800
B483_0000
B483_0400
B483_0800
B483_0C00
B483_1000
B483_1400
B483_1800
B483_FC00
B484_0000
B485_0000
B48A_0000
B48B_1000
B48B_FC00
B48C_0000
B490_0000
B491_0000
B4C0_0000
B500_0000
B600_0000
B700_0000
B780_0000
B7C0_0000
B800_0000
FFFE_E000
FFFE_FC00
END
Address
B480_03FF
B480_07FF
B480_0BFF
B480_0FFF
B480_7FFF
B480_83FF
B480_87FF
B480_8BFF
B480_8FFF
B480_93FF
B480_97FF
B480_9BFF
B480_9FFF
B480_A3FF
B480_A7FF
B480_ABFF
B480_AFFF
B481_FFFF
B482_03FF
B482_07FF
B482_0BFF
B482_0FFF
B482_13FF
B482_17FF
B482_7FFF
B482_83FF
B482_87FF
B482_8BFF
B482_8FFF
B482_93FF
B482_97FF
B482_FFFF
B483_03FF
B483_07FF
B483_0BFF
B483_0FFF
B483_13FF
B483_17FF
B483_FBFF
B483_FFFF
B484_FFFF
B489_FFFF
B48B_0FFF
B48B_FBFF
B48B_FFFF
B48F_FFFF
B490_FFFF
B4BF_FFFF
B4FF_FFFF
B5FF_FFFF
B6FF_FFFF
B77F_FFFF
B7BF_FFFF
B7FF_FFFF
FFFE_DFFF
FFFE_FBFC
FFFE_FFFF
Group
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
APPS #5
CommonPERI #0
Bit RMW alias
Bit RMW alias
Bit RMW alias
Error Config
Error Config
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Function
M.F.Serial ch.0
M.F.Serial ch.1
M.F.Serial ch.2
M.F.Serial ch.3
Reserved
BaseTimer ch.0
BaseTimer ch.1
BaseTimer ch.2
BaseTimer ch.3
BaseTimer ch.4
BaseTimer ch.5
BaseTimer ch.6
BaseTimer ch.7
BaseTimer ch.8
BaseTimer ch.9
BaseTimer ch.10
BaseTimer ch.11
Reserved
FRT ch.0
FRT ch.1
FRT ch.2
FRT ch.3
FRT ch.4
FRT ch.5
Reserved
ICU ch.0 / ch.1
ICU ch.2 / ch.3
ICU ch.4 / ch.5
ICU ch.6 / ch.7
ICU ch.8 / ch.9
ICU ch.10 / ch.11
Reserved
OCU ch.0 / ch.1
OCU ch.2 / ch.3
OCU ch.4 / ch.5
OCU ch.6 / ch.7
OCU ch.8 / ch.9
OCU ch.10 / ch.11
Reserved
Reserved
APPS#5 area
Reserved
Reserved
Reserved
Reserved
Reserved
CAN_FD ch.0
Reserved
Bit RMW alias for CPERI#0(Covers B490_0000 -- B497_FFFF)
Reserved
Reserved
Bit RMW alias for CPERI#2 (Covers B470_0000 -- B47F_FFFF)
Bit RMW alias for CPERI#0 (Covers B480_0000 -- B487_FFFF)
Reserved
Reserved
IRC
BootROM I/F
PPU No
176
177
178
179
88
89
90
91
92
93
94
95
96
97
98
99
208
209
210
211
212
213
224
225
226
227
228
229
240
241
242
243
244
245
256
20
37
D a t a S h e e t
- APPS#5 area
START
Address
B484_0000
B484_3800
B484_3C00
B484_4000
B484_4400
B484_4800
B484_4C00
B484_5000
B484_5400
B484_5800
B484_5C00
B484_6000
B484_6400
B484_6800
B484_6C00
B484_7000
B484_7400
B484_7800
B484_7C00
B484_8000
B484_8400
B484_8800
B484_8C00
38
CONFIDENTIAL
END
Address
B484_37FF
B484_3BFF
B484_3FFF
B484_43FF
B484_47FF
B484_4BFF
B484_4FFF
B484_53FF
B484_57FF
B484_5BFF
B484_5FFF
B484_63FF
B484_67FF
B484_6BFF
B484_6FFF
B484_73FF
B484_77FF
B484_7BFF
B484_7FFF
B484_83FF
B484_87FF
B484_8BFF
B484_FFFF
Group
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
Function
Reserved
BaseTimer ch.12
BaseTimer ch.13
BaseTimer ch.14
BaseTimer ch.15
BaseTimer ch.16
BaseTimer ch.17
BaseTimer ch.18
BaseTimer ch.19
BaseTimer ch.20
BaseTimer ch.21
BaseTimer ch.22
BaseTimer ch.23
BaseTimer ch.24
BaseTimer ch.25
BaseTimer ch.26
BaseTimer ch.27
BaseTimer ch.28
BaseTimer ch.29
A/D unit0
A/D unit1
A/D analog input control
Reserved
PPU No
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
-
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
11. Pin Status in CPU Status
Table 11-1 Pin State Table (1/2)
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Timer mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Stop mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
Sleep mode
CPU Sleep mode
Internal Reset Factor
*2
After internal reset
issuance (Before GPORT
setting)
External Reset
Factor 3
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
After external
factor
releasing
Internal reset
issuance in
progress
External Reset Factor 2
External factor
generation in
progress
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
GPORTEN
Control
After external
factor
releasing
Internal reset
issuance in
progress
Pin Name
Internal reset
issuance in
progress
Pin No.
External
factor
generation in
progress
Before internal
reset issuance
External Reset Factor 1
2
3
4
5
6
7
8
P000/SOT2_1
P001/SCS20_1
P003/SCS22_1
P005/SIN3_0/IN6_0
P006/SOT3_0/IN7_0
P007/SCK3_0/IN8_0
P008/SCS30_0/IN9_0/TIOA0_0
Hi-Z/Input
blocked
Hi-Z/Input
blocked
9
P009/INT0_1/IN10_0/TIOA1_0
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
10
11
12
13
14
15
16
17
P010/IN11_0/TIOA2_0
P012/OUT5_0/TIOA3_0
P013/OUT6_0/TIOA4_0
P015/OUT7_0/TIOA5_0
P016/OUT8_0/TIOA6_0
P017/OUT9_0/TIOA7_0
P018/OUT10_0/TIOA8_0
P019/TEXT0_0/OUT11_0/TIOB0_0
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
18 P020/SOT0_0/TEXT1_0/TIOB1_0
19 P021/SCK0_0/TIOB2_0
20 P022/INT3_0/SIN0_0/TIOB3_0
21 P023/SCS0_0/TIOB4_0
22 P024/TIOB5_0
23 P027/INT1_1/TEXT0_1/TIOB6_0/TIOA4_1
24 P028/INT4_0/SIN1_0/OUT0_1/TIOB7_0
25
26
27
28
29
30
31
32
33
P029/AN0/SOT1_0/OUT1_1
P030/OUT2_1
P031/AN1/SCS1_0/OUT3_1
P100/AN2/SCK1_0/OUT4_1
P101/AN3/OUT5_1
P103/AN5/OUT6_1
P105/OUT7_1/TIOA9_0
P106/OUT8_1
P107/INT2_1/OUT9_1/TIOA10_0
34 P108/INT3_1/AN6/OUT10_1/TIOA11_0
35
39
40
41
45
46
P109/OUT11_1/TIOA12_0
P112/AN9/TIOA13_0
P113/TIOA5_1
P114/AN10/TIOA6_1
P115
P117/INT4_1/AN12
With control
Hi-Z/Input blocked
Hi-Z/
Hi-Z/Input
Last
blocked
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Status
Last state
immediately
retained
before the
shutdown retaine
Last state
retained
*3
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
P119/AN14
P120/AN15
P122/AN17/TIOA11_1
P123/AN18/TIOA12_1
P126/AN19
P127/AN20/TEXT1_1
P128/AN21/TEXT2_1
P129/AN22/IN6_1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
56 P130/INT5_0/AN23/IN7_1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
47 P118/INT5_1/AN13
48
49
50
51
52
53
54
55
57 P131/AN24/IN8_1
58 P202/INT6_1/IN9_1
59
60
61
62
P203/IN10_1
P204/AN27/IN11_1
P205/AN28/TEXT3_1
P206/AN29/TEXT4_1
63 P207/INT7_1/AN30/TEXT5_1
64 P208/AN31/TIOA19_0
65 P209/AN32/TIOA20_0
66 P210/INT6_0/AN33/IN0_2/TIOA21_0
67 P211/AN34/IN1_2/TIOA22_0
68 P212/AN35/IN2_2/TIOA13_1
69 P213/INT8_1/IN3_2/TIOA14_1
70 P214/IN4_2/TIOA15_1
71 P215/INT9_1/IN5_2/TIOA16_1
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
39
D a t a S h e e t
Table 11-2 Pin State Table (2/2)
74 P218/AN36/TEXT2_0
75 P219/AN37/TEXT3_0
76 P220/AN38/IN6_2
78 P223/AN40/IN8_2
79 P224/AN41/TX0_2/IN9_2
With control
Hi-Z/Input blocked
Hi-Z/
Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Status
immediately
Last state
before the
retained
shutdown retaine
Hi-Z/Input
blocked
Last state
retained
*3
-
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
96 P306/AN54/TX0_0
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
With control
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
Hi-Z/Input blocked
status
blocked
retained
Status
immediately
Last state
before the
retained
shutdown retaine
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
*1
104 P317/INT11_1/AN62/TIOA9_1
Pull-up
(Last
state
retained
*5)
Pull-up
(Last state
retained
*3
*5)
Pull-up
(Hi-Z
*5)
Pull-up
(Last state
retained
*3
*5)
Pull-up
(Hi-Z
*5)
Input enabled
(Status
immediately
before the
shutdown retaine
*5)
Input
enabled
(Last
state
retained
*5)
Input enabled
(Last state
retained
*3
*5)
Input enabled
(Hi-Z/Input
blocked
*5)
Input enabled
(Last state
retained
*3
*5)
Input enabled
(Hi-Z/Input
blocked
*5)
Input enabled
Input
enabled
Input enabled
-
Input enabled
-
Input enabled
-
Input enabled
-
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
-
With control
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
-
Input enabled
Input enabled
Input enabled
Input enabled
115 P327
With control
116 P330
-
121 P331
122 P400
Status
immediately
Last state
before the
retained
shutdown retaine
Status
immediately
Last state
before the
retained
shutdown retaine
Input enabled
Input enabled
127 P401/IN0_0
Input enabled
Last state
retained
*3
Last state
retained
*3
129 P403/IN2_0/TRACEDATA0
130 P404/IN3_0/TRACEDATA1
131 P405/INT11_0/IN4_0/TRACEDATA2
132 P406/TRACEDATA3
133 P407/TRACEDATA4
135 P409/SOT2_0/TIOA24_1/TRACEDATA6
136 P411/INT13_1/SCK2_0/TRACEDATA7
137 P413/INT14_1/SCS20_0
138 P414/SCS21_0
139 P416/IN5_0/TIOA22_1
With control
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Status
immediately
Last state
before the
retained
shutdown retaine
Hi-Z/Input
blocked
Last state
retained
*3
Input enabled
Last state
retained
*3
Hi-Z/Input
blocked
Input enabled
-
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
128 P402/INT2_0/IN1_0
134 P408/INT12_0/SIN2_0/TRACEDATA5
Hi-Z/Input
blocked
*1
Pull-up
(Status
immediately
before the
shutdown retaine
*5)
Pull-up
113 TMS
114 TCK
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
112 TDI/P324
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
*1
Pull-up
-
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
107 P321
123 RSTX
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
102 P314/AN60/IN4_1/TIOA7_1
103 P315/AN61/IN5_1/TIOA8_1
117 MD
118 X0
119 X1
Hi-Z/Input
blocked
*1
Last state
retained
*3
Hi-Z/Input
blocked
*1
101 P313/INT10_1/AN59/IN3_1
110 TRST/P322
111 TDO/P323
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
97 P307/INT1_0/AN55/RX0_0
98 P308/AN56/IN0_1/TIOA28_1
99 P309/AN57/IN1_1/TIOA29_1
100 P312/AN58/IN2_1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
87 P229/INT8_0/AN46/RX0_1/OUT0_0/TIOA25_0
P230/AN47/OUT1_0/TIOA26_0
P231/AN48/OUT2_0/TIOA27_0
P300/AN49/OUT3_0/TIOA28_0
P301/AN50/OUT4_0/TIOA18_1
P302/AN51/TIOA19_1
P304/AN52/TEXT4_0/TIOA20_1
P305/AN53/TEXT5_0/TIOA29_0
NMIX
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
80 P225/INT0_0/AN42/RX0_2/IN10_2
88
89
90
91
92
93
94
95
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Hi-Z/Input
blocked
77 P222/INT7_0/AN39/IN7_2
81 P226/AN43/IN11_2/TIOA17_1
85 P227/AN44/TIOA23_0
86 P228/AN45/TX0_1/TIOA24_0
Timer mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Stop mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
Sleep mode
CPU Sleep mode
Internal Reset Factor
*2
After internal reset
issuance (Before GPORT
setting)
External Reset
Factor 3
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
After external
factor
releasing
Internal reset
issuance in
progress
External Reset Factor 2
External factor
generation in
progress
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
Internal reset
issuance in
progress
GPORTEN
Control
Internal reset
issuance in
progress
Pin No.
Pin Name
After external
factor
releasing
Before internal
reset issuance
External Reset Factor 1
External
factor
generation in
progress
Last state
retained
*3
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
141 P418/INT14_0/SCS22_0
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
142 P420/SCK2_1/TRACECLK
143 P421/SIN2_1/TRACECTL
Hi-Z/Input
blocked
Hi-Z/Input
blocked
140 P417/INT15_1/TIOA23_1
40
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
*1: Input disable is not valid when external interrupts are enabled.
*2: Recovery from standby (power off) becomes a factor.
*3: The pin state from the time that HOLDIO_PD2 was set (SYSC0_SPECFGR.HOLDIO_PD2=1) is retained. If
power-off has not occurred and HOLDIO_PD2 has not been set (SYSC0_SPECFGR.HOLDIO_PD2=0), the last
state is retained.
*4: To power off power domains 2 and 3, be sure to set HOLDIO_PD2 (SYSC0_SPECFGR.HOLDIO_PD2=1).
*5: The pin state when the PORT function is enabled is shown.
-External Reset Factor 1
Power-on reset (PONR)
RAM retention low-voltage detection reset (RVD)
Internal power supply low-voltage detection reset (LVDL1R)
RSTX pin + MD pin simultaneous assert reset (INITX)
-External Reset Factor 2
RSTX pin input reset (RSTX)
-External Reset Factor 3
Hardware watchdog reset (HWDR)
Software watchdog reset (SWDR)
PLL clock supervisor reset (CSVPRn)
SSCG clock supervisor reset (CSVSRn)
Profile error reset (PRFERR)
Software trigger hard reset (SHRST)
Software reset (SRST)
-Internal Reset Factor
Standby transition reset/ Power domain reset
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
41
D a t a S h e e t
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
*1, *2
Analog supply voltage
*1
Analog reference voltage
*1
Rating
Unit
Remarks
Min
Max
VCC
VSS-0.3
VSS+6.0
V
AVCC
VSS-0.3
VSS+6.0
V
AVCC=VCC
AVRH
VSS-0.3
VSS+6.0
V
AVRH≤AVCC
Input voltage
VI
VSS-0.3
VCC+0.3
V
Analog pin input voltage*1
VIA
VSS-0.3
VCC+0.3
V
VO
VSS-0.3
VCC+0.3
V
Maximum clamp current
|ICLAMP |
-
4
mA
Total maximum clamp current
Σ|ICLAMP |
-
20
mA
*7
IOL1
-
3.5
mA
When setting is 1 mA*6
IOL2
-
7
mA
When setting is 2 mA
IOLAV1
-
1
mA
When setting is 1 mA*6
*1
Output voltage
"L"-level maximum output current*3
"L"-level average output current*4
*7
IOLAV2
-
2
mA
When setting is 2 mA
ΣIOL
-
40
mA
*6
IOH1
-
-3.5
mA
When setting is 1 mA*6
IOH2
-
-7
mA
When setting is 2 mA
IOHAV1
-
-1
mA
When setting is 1 mA*6
IOHAV2
-
-2
mA
When setting is 2 mA
ΣIOH
-
-40
mA
*6
Power consumption
PD
-
1300
mW
Operating temperature
TA
-40
+125
°C
Tstg
-55
+150
°C
"L"-level total output current*5
"H"-level maximum output current*3
"H"-level average output current*4
"H"-level total output current*5
Storage temperature
S6J311xHAA*8
*1: These parameters are based on the condition that VSS=AVSS=0.0V.
*2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed
VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: The maximum output current is defined as the value of the peak current flowing through any one of
the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of
the corresponding pins for a 10 ms period. The average value is the operation current X the operation
ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding
pins.
*6: Corresponding pins: general-purpose ports
42
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
*7: Corresponding pins: All general-purpose ports and analog input pins
−
Use the device within the recommended operating conditions.
−
Use the device with direct voltage (current).
−
The + B signal should always be applied by connecting a limiting resistor between the + B
signal and the microcontroller.
−
The value of the limiting resistor should be set so that the current input to the microcontroller
pin does not exceed rated values at any time regardless of instantaneously or constantly when
the + B signal is input.
−
Note that when the microcontroller drive current is low, such as in the low-power consumption
modes, the + B input potential can increase the potential at the VCC pin via a protective diode,
possibly affecting other devices.
−
Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the
power is supplied through the pin, the microcontroller may operate incompletely.
−
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the
power-on reset may not function in the power supply voltage.
−
Do not leave + B input pins open.
*8: It is standard when four-layer substrate is used.
Example of a recommended circuit
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed
any of these ratings.
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
43
D a t a S h e e t
12.2 Recommended Operating Conditions
(VSS=AVSS=0.0 V)
Parameter
Supply voltage
Symbol
Value
Min
Max
Unit
VCC
4.5
5.25
V
AVCC
4.5
5.25
V
VCC
3.5
5.25
V
AVCC
3.5
5.25
V
Remarks
Recommended operation assurance range
Operation assurance range
Tolerance of up to ±40%, 126pin
Use a ceramic capacitor or a capacitor that has the
Smoothing capacitor*
CS1
4.7
µF
similar frequency characteristics.
Use a capacitor with a capacitance greater than CS as
the smoothing capacitor on the VCC pin.
Operating temperature
TA
-40
+125
°C
S6J311xHAA
*: For the connections of smoothing capacitor CS1, see the following diagram.
· C pin connection diagram
C(126pin)
CS1
VSS
VSS
C(38pin)
open
AVSS
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device
and could result in device failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on
this data sheet. If you are considering application under any conditions other than listed herein, please
contact sales representatives beforehand.
44
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
12.3 DC Characteristics
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0.7×VCC
-
VCC+0.3
V
0.8×VCC
-
VCC+0.3
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
VIH1
"H" level
P122 to P123,
CMOS
P126 to P131,
Schmitt
P202 to P215,
input level
P218 to P220,
P222 to P231,
P300 to P302,
selected
P304 to P309,
input voltage
P312 to P315, P317,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P401 to P409, P411,
VIH2
P413 to P414,
P416 to P418,
P420 to P421
input level
selected
VIH4
RSTX, NMIX
-
0.7×VCC
-
VCC+0.3
V
VIH5
MD
-
0.7×VCC
-
VCC+0.3
V
2.3
-
VCC+0.3
V
VIH6
TRST, TCK, TDI,
TMS
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
Automotive
TTL input
level
45
D a t a S h e e t
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
VSS-0.3
-
0.3×VCC
V
VSS-0.3
-
0.5×VCC
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
VIL1
"L" level
CMOS
P126 to P131,
Schmitt
P202 to P215,
input level
P218 to P220,
P222 to P231,
P300 to P302,
selected
P304 to P309,
input voltage
P312 to P315, P317,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P401 to P409, P411,
VIL2
P413 to P414,
P416 to P418,
P420 to P421
CONFIDENTIAL
input level
selected
VIL4
RSTX, NMIX
-
VSS-0.3
-
0.3×VCC
V
VIL5
MD
-
VSS-0.3
-
0.3×VCC
V
VSS-0.3
-
0.8
V
VIL6
46
Automotive
TRST, TCK, TDI,
TMS
TTL input
level
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Min
Typ
Max
VCC-0.5
-
VCC
Unit
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"H" level
output
voltage
P126 to P131,
VOH1
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
VCC=4.5 V
IOH=-2.0 mA
V
P304 to P309,
P312 to P315, P317,
P321 to P324,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
47
D a t a S h e e t
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
VCC-0.5
-
VCC
V
0
-
0.4
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"H" level
output
P126 to P131,
VOH2
voltage
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
VCC=4.5 V
IOH=-1.0 mA
P304 to P309,
P312 to P315, P317,
P321 to P324,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"L" level
output
voltage
P126 to P131,
VOL1
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
VCC=4.5 V
IOL=2.0 mA
P304 to P309,
P312 to P315, P317,
P321 to P324,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
48
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Parameter
Symbol
Pin Name
Conditions
Value
Min
Typ
Max
0
-
0.4
Unit
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"L" level
output
voltage
P126 to P131,
VOL2
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
VCC=4.5 V
IOL=1.0 mA
V
P304 to P309,
P312 to P315, P317,
P321 to P324,
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
49
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Input leakage
current
Symbol
Pin Name
IIL
All input pins
RUP1
RSTX, NMIX
Conditions
VCC=AVCC=5.25 V
VSS < VI < VCC
-
Value
Unit
Min
Typ
Max
-5
-
+5
µA
25
-
100
kΩ
25
-
100
kΩ
25
-
100
kΩ
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
Pull-up
RUP2
resistor
P126 to P131,
Pull-up resistor
P202 to P215,
selected
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315, P317
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
RUP3
50
CONFIDENTIAL
P321, TDI(P324),
TMS, TCK
-
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
25
-
100
kΩ
-
25
-
100
kΩ
-
-
5
15
pF
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
Pull-down
RDOWN1
resistor
P126 to P131,
Pull-down resistor
P202 to P215,
selected
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315, P317
P327, P330 to P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
RDOWN2
TRST(P322)
Pins other than
Input
capacitance
CIN
VCC, VSS,
AVCC0, AVCC1,
AVSS0, AVSS1
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
51
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin
Name
Conditions
supply
Max
-
80
175
mA
Operating at 96MHz
-
100
200
mA
Operating at 96MHz
CPU Sleep
-
65
150
mA
Operating at 96 MHz
Timer mode
-
480
1450
µA
Stop mode
-
480
1450
µA
-
40
100
µA
-
40
100
µA
Flash
ICCS5
current
ICCT5
S6J311xH
ICCH5
AA
ICCT52
ICCH52
VCC
Remarks
Typ
write/erase
Power
Unit
Min
Normal operation
ICC5
Value
Timer mode
(Shutdown)
Stop mode
(Shutdown)
TA=25°C
Slow-CR source Oscillation
TA=25°C
TA=25°C
Slow-CR source Oscillation
TA=25°C
Refer to Hardware manual "APPENDIX State transition" for Internal clock frequency setting / Setting of the power domain /
Regulator setting.
52
CONFIDENTIAL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
12.4 AC Characteristics
12.4.1
Source Clock Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Source oscillation clock
frequency
Source oscillation clock
cycle time
CAN PLL jitter
(during lock)
Built-in slow-CR
oscillation frequency
Built-in fast-CR
oscillation frequency
PLL input clock
frequency
PLL macro oscillation
clock frequency
SSCG-PLL input clock
frequency
SSCG-PLL macro
oscillation clock
frequency
Value
Pin
Cond
Name
itions
Min
Typ
Max
FC
X0, X1
-
-
4
-
MHz
tCYL
X0, X1
-
-
250
-
ns
tPJ
-
-
-10
-
+10
ns
FCRS
-
-
50
100
150
kHz
FCRF
-
-
2.4
4
6.0
MHz
FPLLI
-
-
-
4
-
MHz
FPLLO
-
-
400
-
576
MHz
FSSCGPLLI
-
-
-
4
-
MHz
FSSCGPLLO
-
-
400
-
576
MHz
Symbol
Unit
Remarks
*
*: The maximum/minimum values have been standardized with the main clock and PLL clock in use.
−
X0 and X1 clock timing
tCYL
X0
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D a t a S h e e t
−
CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
t1
t2
t3
tn-1
tn
Ideal clock
Slow
PLL output
t1
t2
t3
tn-1
tn
Fast
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D a t a S h e e t
12.4.2
Parameter
Internal Clock Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Symbol
Pin Name
Conditions
S6J311xHAA Value
Min
Internal
Clock
Frequency
Typ
Max
Unit
Remarks
FCLK_CPU
-
-
-
-
96
MHz
CLK_CPU
FCLK_FCLK
-
-
-
-
48
MHz
CLK_FCLK
FCLK_ATB
-
-
-
-
48
MHz
CLK_ATB
FCLK_DBG
-
-
-
-
48
MHz
CLK_DBG
FCLK_HPM
-
-
-
-
24
MHz
CLK_HPM
FCLK_HPM2
-
-
-
-
12
MHz
CLK_HPM2
FCLK_DMA
-
-
-
-
24
MHz
CLK_DMA
FCLK_MEMC
-
-
-
-
24
MHz
CLK_MEMC
FCLK_EXTBUS
-
-
-
-
24
MHz
CLK_EXTBUS
FCLK_SYSC1
-
-
-
-
24
MHz
CLK_SYSC1
FCLK_HAPP0A0
-
-
-
-
24
MHz
CLK_HAPP0A0
FCLK_HAPP0A1
-
-
-
-
24
MHz
CLK_HAPP0A1
FCLK_HAPP1B0
-
-
-
-
24
MHz
CLK_HAPP1B0
FCLK_HAPP1B1
-
-
-
-
24
MHz
CLK_HAPP1B1
FCLK_LLPBM
-
-
-
-
96
MHz
CLK_LLPBM
FCLK_LLPBM2
-
-
-
-
48
MHz
CLK_LLPBM2
FCLK_LCP
-
-
-
-
48
MHz
CLK_LCP
FCLK_LCP0
-
-
-
-
24
MHz
CLK_LCP0
FCLK_LCP0A
-
-
-
-
24
MHz
CLK_LCP0A
FCLK_LCP1
-
-
-
-
24
MHz
CLK_LCP1
FCLK_LCP1A
-
-
-
-
24
MHz
CLK_LCP1A
FCLK_LAPP0
-
-
-
-
24
MHz
CLK_LAPP0
FCLK_LAPP0A
-
-
-
-
24
MHz
CLK_LAPP0A
FCLK_LAPP1
-
-
-
-
24
MHz
CLK_LAPP1
FCLK_LAPP1A
-
-
-
-
24
MHz
CLK_LAPP1A
FCLK_TRC
-
-
-
-
48
MHz
CLK_TRC
FCLK_HSSPI
-
-
-
-
24
MHz
CLK_HSSPI
FCLK_SYSC0H
-
-
-
-
24
MHz
CLK_SYSC0H
FCLK_COMH
-
-
-
-
24
MHz
CLK_COMH
FCLK_RAM0H
-
-
-
-
24
MHz
CLK_RAM0H
FCLK_RAM1H
-
-
-
-
24
MHz
CLK_RAM1H
FCLK_SYSC0P
-
-
-
-
24
MHz
CLK_SYSC0P
FCLK_COMP
-
-
-
-
24
MHz
CLK_COMP
FCANFD_CCLK
-
-
-
-
40
MHz
CANFD_CCLK
tCLK_CPU
-
-
10.4
-
-
ns
CLK_CPU
tCLK_FLASH
-
-
20.8
-
-
ns
CLK_FCLK
Internal
tCLK_ATB
-
-
20.8
-
-
ns
CLK_ATB
Clock Cycle
tCLK_DBG
-
-
20.8
-
-
ns
CLK_DBG
Time
tCLK_HPM
-
-
41.6
-
-
ns
CLK_HPM
tCLK_HPM2
-
-
83.3
-
-
ns
CLK_HPM2
tCLK_DMA
-
-
41.6
-
-
ns
CLK_DMA
January 16, 2015, S6J311A_DS708-00004-1v0-E
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55
D a t a S h e e t
Parameter
Symbol
Pin Name
Conditions
S6J311xHAA Value
Min
Typ
Max
Unit
Remarks
tCLK_MEMC
-
-
41.6
-
-
ns
CLK_MEMC
tCLK_EXTBUS
-
-
41.6
-
-
ns
CLK_EXTBUS
tCLK_SYSC1
-
-
41.6
-
-
ns
CLK_SYSC1
tCLK_HAPP0A0
-
-
41.6
-
-
ns
CLK_HAPP0A0
tCLK_HAPP0A1
-
-
41.6
-
-
ns
CLK_HAPP0A1
tCLK_HAPP1B0
-
-
41.6
-
-
ns
CLK_HAPP1B0
tCLK_HAPP1B1
-
-
41.6
-
-
ns
CLK_HAPP1B1
tCLK_LLPBM
-
-
10.4
-
-
ns
CLK_LLPBM
tCLK_LLPBM2
-
-
20.8
-
-
ns
CLK_LLPBM2
tCLK_LCP
-
-
20.8
-
-
ns
CLK_LCP
tCLK_LCP0
-
-
41.6
-
-
ns
CLK_LCP0
tCLK_LCP0A
-
-
41.6
-
-
ns
CLK_LCP0A
Internal
tCLK_LCP1
-
-
41.6
-
-
ns
CLK_LCP1
Clock Cycle
tCLK_LCP1A
-
-
41.6
-
-
ns
CLK_LCP1A
Time
tCLK_LAPP0
-
-
41.6
-
-
ns
CLK_LAPP0
tCLK_LAPP0A
-
-
41.6
-
-
ns
CLK_LAPP0A
tCLK_LAPP1
-
-
41.6
-
-
ns
CLK_LAPP1
tCLK_LAPP1A
-
-
41.6
-
-
ns
CLK_LAPP1A
tCLK_TRC
-
-
20.8
-
-
ns
CLK_TRC
56
CONFIDENTIAL
tCLK_HSSPI
-
-
41.6
-
-
ns
CLK_HSSPI
tCLK_SYSC0H
-
-
41.6
-
-
ns
CLK_SYSC0H
tCLK_COMH
-
-
41.6
-
-
ns
CLK_COMH
tCLK_RAM0H
-
-
41.6
-
-
ns
CLK_RAM0H
tCLK_RAM1H
-
-
41.6
-
-
ns
CLK_RAM1H
tCLK_SYSC0P
-
-
41.6
-
-
ns
CLK_SYSC0P
tCLK_COMP
-
-
41.6
-
-
ns
CLK_COMP
tCANFD_CCLK
-
-
25.0
-
-
ns
CANFD_CCLK
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
−
Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
3.5
2
4
96
Internal clock frequency FCPU_CLK(MHz)
Note: A supply voltage that is equal to or less than the set voltage for low-voltage detection causes a reset.
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D a t a S h e e t
Relationship between the oscillation clock frequency and internal clock frequency
Oscillation Clock
Frequency
−
Main Clock
PLL Multiplier
PLL Output Division
Setting
Setting
PLL Clock
4 MHz
4 MHz
144
6
96 MHz
4 MHz
4 MHz
120
6
80 MHz
Oscillation circuit example
X0
X1
R
C1
C2
Notes:
· When configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator manufacturers
for the design.
· The maximum PLL clock frequency must be 96MHz.
Output division configuration can be set by the following.
- PLLDIVM bit in SYSC0_RUNPLL0CNTR register
- PLLDIVM bit in SYSC0_PSSPLL0CNTR register
- SSCGDIVM bit in SYSC0_RUNSSCG0CNTR0 register
- SSCGDIVM bit in SYSC0_PSSSSCG0CNTR0 register
(e.g. If PLLout is 576MHz, these settings must be configured as "multiply by 6" and over multiplication setting)
AC characteristics are specified by the following measurement reference voltage values.
−
Input signal waveform
Hysteresis input pin (Automotive)
−
Output signal waveform
Output pin
0.8VCC
2.4V
0.5VCC
0.8V
Hysteresis input pin (CMOS Schmitt)
0.7VCC
0.3VCC
Hysteresis input pin (TTL)
2.3V
0.8V
58
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D a t a S h e e t
12.4.3
Reset Input
Parameter
Symbol
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Pin Name
Conditions
Reset
input time
Width for reset
tRSTL
RSTX
Value
Unit
Min
Max
10
-
µs
1
-
µs
Remarks
-
input removal
tRSTL
RSTX
0.2VCC
January 16, 2015, S6J311A_DS708-00004-1v0-E
CONFIDENTIAL
0.2VCC
59
D a t a S h e e t
12.4.4
Power-on Conditions
Parameter
Symbol
Level detection
voltage
Level release
voltage
Level detection
hysteresis width
Level detection time
Pin
Name
(TA: Recommended operating conditions, VSS=0.0 V)
Conditions
Value
Min
Typ
Max
Unit
Remarks
-
VCC
-
2.15
2.35
2.55
V
-
VCC
-
2.25
2.45
2.65
V
-
VCC
-
-
100
-
mV
-
-
-
-
-
30
μs
*1
-
-
4
mV/µs
*2
50
-
-
ms
*3
VCC = at level
Slope detection
-
undetected standard
VCC
detection
release level
time
Power off time
-
VCC
-
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the
possibility to generate or release after the power supply voltage has exceeded the detection voltage
range.
*2: When setting the power supply fluctuation to less than this standard, "Level detection time" can be
longer than the maximum standard defined in this table. This is the standard when the power supply
fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
60
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D a t a S h e e t
12.4.5 Multi-function Serial
12.4.5.1 CSIO Timing (SMR:MD[2:0]=010B)
(5-1-1) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal
Detect Level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Serial clock
cycle time
SCK ↓ → SOT
delay time
Valid SIN → SCK ↑
setup time
SCK ↑→ Valid SIN
hold time
Serial clock
Symbol
Pin Name
tSCYC
SCK0 to SCK3
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
tIVSHI
tSHIXI
Master
mode
Max
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCP0A +10
-
ns
2tCLK_LCP0A -10
-
ns
-
45
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
IOL=-2mA,
IOH=2mA),
SCK0 to SCK3,
SIN0 to SIN3
Unit
Min
(CL=50pF,
(CL=20pF,
IOL=-1mA,
IOH=1mA)
tSHSL
"H" pulse width
Value
Conditions
Remarks
SCK0 to SCK3
Serial clock
tSLSH
"L" pulse width
SCK ↓→ SOT
tSLOVE
delay time
Valid SIN → SCK ↑
setup time
SCK ↑ → Valid SIN
hold time
tIVSHE
tSHIXE
Slave
SCK0 to SCK3,
SOT0 to SOT3
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK fall time
tF
SCK0 to SCK3
SCK rise time
tR
SCK0 to SCK3
IOH=1mA)
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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D a t a S h e e t
tSCYC
SCK
VOH
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
tR
VIH
tIVSHE
tSHIXE
tSLOVE
VOH
VOL
VIH
VIL
VIH
VIL
Slave mode
62
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D a t a S h e e t
(5-1-2) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal
Detect Level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Serial clock
cycle time
SCK ↑ → SOT
delay time
Valid SIN → SCK ↓
Symbol
Pin Name
tSCYC
SCK0 to SCK3
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
(CL=50pF,
SCK0 to SCK3,
SIN0 to SIN3
(CL=20pF,
tIVSLI
setup time
SCK ↓ → Valid SIN
tSLIXI
hold time
Serial clock
Conditions
Master
mode
IOL=-2mA,
IOH=2mA),
IOL=-1mA,
IOH=1mA)
tSHSL
"H" pulse width
Value
Unit
Min
Max
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCP0A +10
-
ns
2tCLK_LCP0A -10
-
ns
-
45
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Remarks
SCK0 to SCK3
Serial clock
tSLSH
"L" pulse width
SCK ↑ → SOT
tSHOVE
delay time
Valid SIN → SCK ↓
tIVSLE
setup time
SCK ↓ → Valid SIN
tSLIXE
hold time
Slave
SCK0 to SCK3,
SOT0 to SOT3
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK fall time
tF
SCK0 to SCK3
SCK rise time
tR
SCK0 to SCK3
IOH=1mA)
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSHOVI
VO
VOL
SOT
tIVSLI
tSLIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
SCK
VIL
tR
SOT
VIH
tSLSH
VIH
tF
tSHOVE
VIL
VOH
VOL
tIVSLE
SIN
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
64
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
(5-1-3) SPI Supported (SCR:SPI=1), and Serial Clock Output Signal Detect Level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Serial clock
cycle time
SCK ↑ → SOT
delay time
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
SOT → SCK ↓
Symbol
Pin Name
tSCYC
SCK0 to SCK3
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
tIVSLI
tSLIXI
tSOVLI
delay time
Serial clock
Max
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCP0A -30
-
ns
tCLK_LCP0A +10
-
ns
2tCLK_LCP0A -10
-
ns
-
45
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK0 to SCK3,
SOT0 to SOT3
IOH=1mA)
Unit
Min
Master
tSHSL
"H" pulse width
Value
Conditions
Remarks
SCK0 to SCK3
Serial clock
tSLSH
"L" pulse width
SCK ↑ → SOT
tSHOVE
delay time
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
tIVSLE
tSLIXE
Slave
SCK0 to SCK3,
SOT0 to SOT3
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK fall time
tF
SCK0 to SCK3
SCK rise time
tR
SCK0 to SCK3
IOH=1mA)
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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65
D a t a S h e e t
tSCYC
SCK
VOH
VOL
tSOVLI
VOL
tSHO
VOH
VOL
SOT
VOH
VOL
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
SCK
SIN
VIL
tF
*
SOT
VIL
tR
VIH
VIH
tSHOV
VOH
VOL
VIL
VO
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
* Changes when writing to the TDR
Slave mode
66
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S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
(5-1-4) SPI Supported (SCR:SPI=1), and Serial Clock Output Signal Detect Level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Serial clock
cycle time
SCK ↓ → SOT
delay time
Valid SIN → SCK ↑
Symbol
Pin Name
tSCYC
SCK0 to SCK3
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
tIVSHI
setup time
SCK ↑→ Valid SIN
tSHIXI
hold time
SOT → SCK ↑
tSOVHI
delay time
Serial clock
Conditions
Master
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK0 to SCK3,
SOT0 to SOT3
IOH=1mA)
tSHSL
"H" pulse width
Value
Unit
Min
Max
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCP0A -30
-
ns
tCLK_LCP0A +10
-
ns
2tCLK_LCP0A -10
-
ns
-
45
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Remarks
SCK0 to SCK3
Serial clock
tSLSH
"L" pulse width
SCK ↓ → SOT
tSLOVE
delay time
Valid SIN → SCK ↑
tIVSHE
setup time
SCK ↑ → Valid SIN
tSHIXE
hold time
Slave
SCK0 to SCK3,
SOT0 to SOT3
mode
(CL=50pF,
IOL=-2mA,
SCK0 to SCK3,
SIN0 to SIN3
IOH=2mA),
(CL=20pF,
IOL=-1mA,
SCK fall time
tF
SCK0 to SCK3
SCK rise time
tR
SCK0 to SCK3
IOH=1mA)
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
January 16, 2015, S6J311A_DS708-00004-1v0-E
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67
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSOVH
tSLOVI
VOH
VOL
SOT
VOH
VOL
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIL
tR
*
SOT
VIH
tF
VOH
VOL
VIL
VIL
VIH
tSLO
VOH
VOL
tSHIXE
tIVSHE
SIN
VIH
VIH
VIL
VIH
VIL
* Changes when writing to the TDR
Slave mode
68
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D a t a S h e e t
(5-1-5) Serial Chip Select Used (SCSCR:CSEN=1)
 Mark level "H" of serial clock output (SMR, SCSFR:SCINV=0)
 Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↓ → SCK ↓
tCSSI
setup time
SCK ↑ → SCS ↑
tCSHI
hold time
Pin Name
Conditions
Master
SCK0 to SCK3,
mode
SCS0x to SCS3x
(CL=50pF,
IOL=-2mA,
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_LCP0A +30
-
ns
0
-
ns
3tCLK_LCP0A +30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
IOH=2mA),
SCS
tCSDI
deselect time
SCS0x to SCS3x
(CL=20pF,
tCSDS*3-50
IOL=-1mA,
+5tCLK_LCP0A
IOH=1mA)
SCS ↓ → SCK ↓
tCSSE
setup time
SCK ↑ → SCS ↑
tCSHE
hold time
SCS
tCSDE
deselect time
SCS ↓ → SOT
tDSE
delay time
SCS ↑ → SOT
tDEE
delay time
SCK0 to SCK3,
Slave
SCS0x to SCS3x
mode
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS0x to SCS3x,
IOL=-1mA,
SOT0 to SOT3
IOH=1mA)
Master
mode
round
operation
SCK ↓ → SCS ↓
clock switching
tSCC
time
SCK0 to SCK3,
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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D a t a S h e e t
SCS output
VOH
VOL
tCSSI
SCK output
VOL
tCSHI
VOH
tCSDI
VOH
VOL
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
VIL
tCSDE
tCSHE
VIL
tCSSE
SCK input
VIH t
DEE
VIL
SOT
(Normal
synchronous
transfer)
VOL
tDSE
SOT
(SPI compatible)
VIH
VOH
VOL
Slave mode
SCSx output
tSCC
SCSy output
SCK output
VOL
VOL
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
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(5-1-6) Serial Chip Select Used (SCSCR:CSEN=1)
 Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
 Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↓→ SCK ↑
Pin Name
Master
tCSSI
setup time
SCK ↓→ SCS ↑
tCSHI
hold time
Conditions
mode
SCK0 to SCK3,
SCS0x to SCS3x
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_LCP0A +30
-
ns
0
-
ns
3tCLK_LCP0A +30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS
tCSDI
deselect time
SCS ↓ → SCK ↑
tCSSE
setup time
SCK ↓ → SCS ↑
tCSHE
hold time
SCS
tCSDE
deselect time
SCS ↓ → SOT
tDSE
delay time
SCS ↑ → SOT
tDEE
delay time
SCS0x to SCS3x
IOL=-1mA,
tCSDS*3-50+5
IOH=1mA)
tCLK_LCP0A
SCK0 to SCK3,
Slave
SCS0x to SCS3x
mode
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS0x to SCS3x,
IOL=-1mA,
SOT0 to SOT3
IOH=1mA)
Master
mode
round
operation
SCK ↑ → SCS ↓
clock switching
tSCC
time
SCK0 to SCK3,
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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SCS output
VOH
VOL
tCSH
VOL
tCSSI
VOH
SCK output
VOH
tCSD
I
VOL
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
SCK input
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
VIH
VIL
tCSDE
tCSHE
VIL
tCSSE
VIL
VIH
tDEE
VOL
tDSE
VOH
VOL
Slave mode
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D a t a S h e e t
SCSx output
tSCC
SCSy output
VOL
VOH
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
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D a t a S h e e t
(5-1-7) Serial Chip Select Used (SCSCR:CSEN=1)
 Serial clock output signal detect level "H" (SMR, SCSFR:SCINV=0)
 Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
SCS ↑ → SCK ↓
setup time
SCK ↑ → SCS ↓
hold time
Symbol
tCSSI
tCSHI
Pin Name
Conditions
Master
SCK0 to SCK3,
mode
SCS0x to SCS3x
(CL=50pF,
IOL=-2mA,
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_LCP0A +30
-
ns
0
-
ns
3tCLK_LCP0A +30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
IOH=2mA),
SCS
deselect time
tCSDI
SCS0x to SCS3x
(CL=20pF,
tCSDS*3-50+5
IOL=-1mA,
tCLK_LCP0A
IOH=1mA)
SCS ↑ → SCK ↓
setup time
SCK ↑ → SCS ↓
hold time
SCS
deselect time
SCS ↑ → SOT
delay time
SCS ↓ → SOT
delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
SCK0 to SCK3,
SCS0x to SCS3x
Slave
mode
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS0x to SCS3x,
IOL=-1mA,
SOT0 to SOT3
IOH=1mA)
Master
mode
round
operation
SCK ↓ → SCS ↑
clock switching
time
tSCC
SCK0 to SCK3,
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
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Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual
SCS output
tCSDI
VOH
VOH
SCK output
VOL
tCSHI
tCSSI
VOH
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
SCS input
tCSDE
VIH
VIH
VIL
tCSHE
tCSSE
VIH
SCK input
VIL
SOT
(Normal Sync
transfer)
tDEE
VOL
tDSE
SOT
(SPI compatible)
VOH
VOL
Slave mode
tSCC
SCSx output
SCSy output
VOL
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value.)
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D a t a S h e e t
(5-1-8) Serial Chip Select Used (SCSCR:CSEN=1)
 Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
 Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
SCS ↑ → SCK ↑
setup time
SCK ↓ → SCS ↓
hold time
Symbol
tCSSI
tCSHI
Pin Name
Conditions
Master
SCK0 to SCK3,
mode
SCS0x to SCS3x
(CL=50pF,
IOL=-2mA,
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_LCP0A+30
-
ns
0
-
ns
3tCLK_LCP0A+30
-
ns
-
50
ns
0
-
ns
Remarks
IOH=2mA),
SCS
deselect time
tCSDI
SCS0x to SCS3x
(CL=20pF,
tCSDS*3-50+5
IOL=-1mA,
tCLK_LCP0A
IOH=1mA)
SCS ↑ → SCK ↑
setup time
SCK ↓ → SCS ↓
hold time
SCS
deselect time
SCS ↑ → SOT
delay time
SCS ↓ → SOT
delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
SCK0 to SCK3,
Slave
SCS0x to SCS3x
mode
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS0x to SCS3x,
IOL=-1mA,
SOT0 to SOT3
IOH=1mA)
Master
mode
round
operation
SCK ↑ → SCS ↑
clock switching
time
tSCC
SCK0 to SCK3,
(CL=50pF,
SCS0x to SCS3x
IOL=-2mA,
3tCLK_LCP0A+0
3tCLK_LCP0A
+50
ns
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
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D a t a S h e e t
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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D a t a S h e e t
SCS output
tCSDI
VOH
VOH
VOH
SCK output
VOL
tCSHI
tCSSI
VOL
SOT
(Normal synchronous transfer)
SOT
(SPI compatible)
Master mode
tCSDE
SCS input
VIH
VIH
SCK input
VIL
SOT
(Normal
synchronous
transfer)
tDEE
VOL
tDSE
SOT
(SPI compatible)
VIL
tCSHE
tCSSE
VOH
VOL
Slave mode
SCSx output
tSCC
VOH
SCSy output
SCK output
VOH
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
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12.4.5.2
UART (Async Serial Interface) Timing
(SMR:MD[2:0]=000B, 001B)
(5-2-1) External clock selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
Pin Name
tSLSH
"L" pulse width
Serial clock
(CL=50pF,
IOL=-2mA,
tSHSL
"H" pulse width
SCK0 to SCK3
SCK fall time
tF
SCK rise time
tR
VIL
IOH=2mA),
Max
tCLK_LCP0A +10
-
ns
tCLK_LCP0A +10
-
ns
-
5
ns
-
5
ns
(CL=20pF,
IOH=1mA)
tF
tSHSL
VIH
VIH
Unit
Min
IOL=-1mA,
tR
SCK
Value
Conditions
Remarks
tSLSH
VIL
VIL
VIH
External clock selected
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12.4.5.3 LIN Interface (v2.1) (LIN Communication Control Interface (v2.1))
Timing (SMR:MD[2:0]=011B)
(5-3-1) External Clock Selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Serial clock
"L" pulse width
Serial clock
"H" pulse width
Symbol
Pin Name
Conditions
tSLSH
(CL=50pF,
IOL=-2mA,
tSHSL
SCK0 to SCK3
SCK fall time
tF
SCK rise time
tR
Max
tCLK_LCP0A+10
-
ns
tCLK_LCP0A+10
-
ns
-
5
ns
-
5
ns
(CL=20pF,
IOH=1mA)
VIL
tF
tSHSL
VIH
VIH
Unit
Min
IOL=-1mA,
tR
SCK
IOH=2mA),
Value
VIL
Remarks
tSLSH
VIL
VIH
External clock selected
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D a t a S h e e t
12.5 Timer Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Input pulse width
tTWH,
tTWL
Pin Name
Conditions
IN0 to IN11
-
TEXT0 to 5
-
TIOA0 to TIOA29
−
Min
4tCLK_LCP0A
100
4tCLK_LCP0A
100
4tCLK_LCP0A
-
TIOB0 to TIOB7
Value
100
Max
Unit
-
ns
-
ns
-
ns
Remarks
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
Timer input timing
INx
TEXTx
TIOAx,TIOBx
tTIWH
VIH
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tTIWL
VIH
VIL
VIL
81
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12.6 Trigger Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Input pulse width
−
Symbol
tTRGH,
tTRGL
Pin Name
Conditions
INT0 to INT15
INT0 to INT15
Value
Unit
Min
Max
-
100
-
ns
-
1
-
µs
Remarks
Stop mode
Trigger input timing
tTRGH
INTx
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CONFIDENTIAL
VIH
tTRGL
VIH
VIL
VIL
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
12.7 NMI Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Input pulse width
−
Symbol
Pin Name
Conditions
tNMIL
NMIX
-
Value
Min
Max
300
-
Unit
Remarks
ns
NMIX input timing
tNMIL
NMIX
VIH
VIH
VIL
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83
D a t a S h e e t
12.8 Low-Voltage Detection (External Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Detection voltage
Symbol
Pin Name
Conditions
VDP5
VCC
-
VDL0
VCC
VDL1
VCC
VDL2
VCC
*1
*3
*1
*4
*1
*5
Value
Unit
Min
Typ
Max
3.5
-
5.25
V
3.6
3.8
4.0
V
3.8
4.0
4.2
V
4
4.2
4.4
V
Remarks
When
power-supply
voltage falls
and detection
level is set
initially
When
Hysteresis width
VHYS
VCC
-
-
100
-
mV
power-supply
voltage rises
Low-voltage detection
time
Power supply voltage
regulation
Td
-
-
-
-
30
μs
-
VCC
-
-2
-
2
V/ms
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (Td), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage
regulation to do low-voltage detection by detecting voltage (VDL)
*3: SYSC0_RUNLVDCFGR.LVDH1V = 0100B or SYSC0_PSSLVDCFGR.LVDH1V = 0100B
*4: SYSC0_RUNLVDCFGR.LVDH1V = 0101B or SYSC0_PSSLVDCFGR.LVDH1V = 0101B
*5: SYSC0_RUNLVDCFGR.LVDH1V = 0110B or SYSC0_PSSLVDCFGR.LVDH1V = 0110B
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12.9 Low-Voltage Detection (Internal Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Symbol
Pin Name
Conditions
VRDP5
-
VRDL
-
Value
Unit
Min
Typ
Max
-
0.6
-
1.4
V
*
0.9
0.95
1.0
V
Remarks
When
Detection voltage
power-supply
voltage falls
When
Hysteresis width
VRHYS
-
-
-
75
-
mV
power-supply
voltage rises
Low-voltage detection
time
TRd
-
-
-
-
30
μs
*: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (TRd), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
12.10 Low-Voltage Detection (1.2 V Power Supply Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Symbol
Pin Name
Conditions
VRDP5
-
-
VRDL0
-
VRDL1
-
Detection voltage
*1
*2
*1
*3
Value
Unit
Remarks
Min
Typ
Max
0.6
-
1.4
V
0.92
0.97
1.02
V
When
1.02
1.07
1.12
V
voltage falls
power-supply
When
Hysteresis width
VRHYS
-
-
-
75
-
mV
power-supply
voltage rises
Low-voltage detection
time
TRd
-
-
-
-
30
μs
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (TRd), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
*2: SYSC0_RUNLVDCFGR.LVDL1V = 10B or SYSC0_PSSLVDCFGR.LVDL1V = 10B
*3: SYSC0_RUNLVDCFGR.LVDL1V = 11B or SYSC0_PSSLVDCFGR.LVDL1V = 11B
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12.11 A/D Converter
12.11.1 Electrical Characteristics
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Resolution
-
Total Error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
±12
LSB
*3
Integral Nonlinearity
-
-
-
-
±4.0
LSB
*4
Differential Nonlinearity
-
-
-
-
±1.9
LSB
*4
Zero transition voltage
VZT
*6
Full-scale transition voltage
VFST
*6
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
*7
-1.0
-
1.0
*8
-2.0
-
2.0
*9
-3.0
-
3.0
VAIN
*6
AVSS
-
AVRH
V
AVRH
AVRH0, AVRH1
4.5
-
5.25
V
-
0.0
-
V
-
500
900
µA
per one unit
-
1.0
100
µA
*2
-
1
2
mA
per one unit
-
-
5.0
µA
*2
*10
-
-
4
LSB
AN32 to AN62
-
-
4
LSB
Analog port input current
IAIN
Analog input voltage
Reference voltage
AVRL
IA
Power supply current
IAH
IR
IRH
Variation between channels
-
AVRL0/AVSS0,
AVRL1/AVSS1
AVCC
AVRH
AVRL
-11.5LSB
AVRH
-13.5LSB
-
AVRL
+12.5LSB
AVRH
+10.5LSB
V
*5
V
µA
VAVSS≤
VAIN≤VAVCC
AVCC≥AVRH
*1: Time for each channel
*2: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU
is stopped.
*3: Total Error is a comprehensive static error that includes the linearity. 1LSB=(AVRH-AVRL)/4096
*4: 1LSB=(VFST-VZT)/4094
*5: 1LSB=(AVRH-AVRL)/4096
*6: AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN62
*7: AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN42
*8: AN0 to AN2, and AN43
*9: AN44 to AN62
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*10: AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN31
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12.11.2 Notes on Using A/D Converters
About the output impedance of an external circuit for analog input
When the external impedance is too high, the analog voltage sampling time may become insufficient. In
this case, we recommend attaching a capacitor (about 0.1 µF) to an analog input pin.
Analog Input Circuit Model
Rext
Analog Input
Rint
Source
Comparator
Cext
Cint
Rint : Analog input impedance
3.9 kilo ohms (max) (4.5V≤AVCC≤5.25V)
Cint : Capacitance of MCU input pin
11.0pF (max) (4.5V≤AVCC≤5.25V)
Rext : External driving impedance
Cext : Capacitance of PCB at A/D converter input
The following approximation formula for the replacement model above can be used:
sampling time (minimum) = 9 × ((Rint + Rext) × Cint + Rext × Cext)
Note: Listed values must be considered as reference values.
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D a t a S h e e t
12.11.3 Definition of terms
Resolution: Analog variation that is recognized by an A/D converter
*
Integral Nonlinearity error : Deviation of the straight line connecting the zero transition point ("0000 0000
0000" <--> "0000 0000 0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from
actual conversion characteristics includes zero transition error, full-scale transition error, and non-linearity
error.
Differential Nonlinearity error: Deviation from the ideal value of the input voltage required for changing the
output code by 1 LSB
Total error: Difference between the actual value and the theoretical value. The total error includes zero
transition error, full-scale transition error, and non linearity error.
*: Represented as "Linearity error" in the former product series.
Total error
FFF
FFE
Actual conversion
characteristics
1.5LSB
{1 LSB (N - 1) + 0.5LSB}
Digital output
FFD
V NT
(Actually-measured
value)
004
003
Actual conversion
characteristics
002
001
AVRL
(AVSS)
Ideal characteristics
0.5LSB
Analog input
AVRH
Total error of digital output N =
1LSB(Ideal value) =
VNT- {1 LSB × (N-1) + 0.5LSB}
1LSB
AVRH - AVRL
4096
[LSB]
[V]
N: A/D converter digital output value.
VZT(Ideal value) = AVRL + 0.5LSB[V]
VFST(Ideal value) = AVRH - 1.5LSB[V]
VNT: Voltage at which the digital output changes from "(N – 1)" to "N".
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
Integral Nonlinearity
Differential Nonlinearity
Ideal characteristics
FFE
Actual conversion
characteristics
FFD
{1 LSB (N - 1) + VZT}
004
003
002
N+1
VFST(Actuallymeasured
value)
V NT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Digital output
FFF
Actual conversion
characteristics
N
V (N+1)T
(Actuallymeasured
V NT
value)
(Actually-measured value)
Actual conversion
characteristics
N-1
N-2
001
VZT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVSS
(AVRL)
AVRH
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
Analog input
VNT- {1 LSB × (N-1) + VZT}
1LSB
V(N+1) T- VNT
1LSB
VFST - VZT
4094
AVRH
[LSB]
-1 LSB [LSB]
[V]
VZT: Voltage for which digital output changes from "0x000" to "0x001"
VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF".
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12.12 Flash Memory
Value
Parameter
Unit
Remarks
Min
Typ
Max
-
300
1100
ms
-
800
3700
ms
8-bit write time
-
15
288
µs
System-level overhead time excluded*1
16-bit write time
-
19
384
µs
System-level overhead time excluded*1
32-bit write time
-
27
567
µs
System-level overhead time excluded*1
64-bit write time
-
45
945
µs
System-level overhead time excluded*1
-
19
384
µs
System-level overhead time excluded*1
-
23
483
µs
System-level overhead time excluded*1
-
31
651
µs
System-level overhead time excluded*1
-
49
1029
µs
System-level overhead time excluded*1
Sector erase time
8-bit (with ECC)
write time
16-bit (with ECC)
write time
32-bit (with ECC)
write time
64-bit (with ECC)
write time
1,000/20 years,
Erase count*2/
Data retention time
8-KB sector*1
Internal preprogramming time included
64-KB sector*1
Internal preprogramming time included
Temperature at write/erase time
-
10,000/10 years,
-
-
Average temperature TA=+85 degrees
Celsius
100,000/5 years
*1: Guaranteed value for up to 100,000 erases
*2: Number of erases for each sector
Notes:
−
−
While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited.
In the application system where VCC might be shut down while writing or erasing, be sure to turn the
power off by using an external low-voltage detection function.
−
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL),
hold VCC at 2.7V or more within the duration calculated by the following expression:
1
2
Td* [µs] + (1 / FCRF* [MHz]) x 1029 + 25 [µs]
*1 : See "12.8 Low-voltage detection (external low-voltage detection)"
*2 : See "12.4.1 Source clock timing"
January 16, 2015, S6J311A_DS708-00004-1v0-E
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13. Ordering Information
Part Number
Package
S6J311xHAASEy0000
144-pin Plastic TEQFP (LEU144)
Note:
−
"x"/"y" is a part number option. For the part number option, see the following table.
For details on each package, see "PACKAGE DIMENSIONS."
14. Part Number Option
Part Number Option "x"
FLASH Memory
A
1MByte
9
768KByte
8
512KByte
Part Number Option "y"
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1
Sn-Bi & Halogen Free
2
PureSn & Halogen Free
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
15. Package Dimensions
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
16. Major Changes
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 1.0
1,3
Cover
Added the family product names(S6J3119HAA / S6J3118HAA)
1,3
Cover
Revised the level of this data sheet as full production
6
7
2. Features
2.2 Peripheral Functions
2. Features
2.2 Peripheral Functions
Added the information about the memory capacity expansion
Revised the CAN transfer speed to 5Mbps
9
3. Product Lineup
Added the specifications as full production
11
4. Pin Assignment
Revised the product names of title S6J311AHAA-> S6J311xHAA
12
5. Pin Description
Revised the product names of title S6J311AHAA-> S6J311xHAA
12~21
5. Pin Description
Revised the product names of Pin No. S6J311AHAA-> S6J311xHAA
30
8. Handling Devices
Revised the note of “About power supply pins”
32
8. Handling Devices
Revised the note of “About C pin processing”(Delete “and pin 38”)
33
9. Block Diagram
Revised the block diagram of S6J311xHAA as full production
34
10. Memory Map
36
10.Memory Map
Revised the product names of title S6J311AHAA-> S6J311xHAA
12. Electrical Characteristics
Added the product names S6J311AHAA-> S6J311xHAA
42,44,52,55
42
42
42
43
44
44
44
45
52
55
55
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.3 DC Characteristics
12. Electrical Characteristics
12.3 DC Characteristics
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
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CONFIDENTIAL
12.4.2 Internal Clock Timing
Revised the memory map of S6J311xHAA
(added information of S6J3119HAA / S6J3118HAA)
Revised “Remarks” of Analog supply voltage to “AVCC=VCC”
Revised the note of *2
Revised the symbol of Maximum clamp current
Moved the note of *8 to the bottom of note
Delete the information about CS2
Revised C pin connection diagram
Added “Remarks” of Smoothing capacitor
Revised the minimum value of VIH6
2.0 -> 2.3
Revised the following DC characteristics
ICC5, ICCS5, ICCT52, ICCH52
Revised the product names in the table S6J311AHAA-> S6J311xHAA
Delete the line of FCD0_CLK and tCD0_CLK
S6J311A_DS708-00004-1v0-E, January 16, 2015
D a t a S h e e t
Page
57
58
60
60
75
82
86
86
89
91
Section
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.4 Power-on Conditions
12. Electrical Characteristics
12.4.4 Power-on Conditions
12. Electrical Characteristics
12.4.5.1 CSIO Timing (SMR:MD[2:0]=010B)
12. Electrical Characteristics
12.6 Trigger Input Timing
12. Electrical Characteristics
12.11.1 Electrical Characteristics
12. Electrical Characteristics
12.11.1 Electrical Characteristics
12. Electrical Characteristics
12.11.3 Definition of Terms
12. Electrical Characteristics
12.12 Definition of Terms
Change Results
Revised the note as follow
FCDO_CLK->FCPU_CLK
Revised the voltage value of Hysteresis input pin (TTL).
2.0V -> 2.3V
Revised the value of Level detection voltage
Added the line of Level release voltage
Added the Figure of 5-1-7(1st, 2nd, 3rd)
Deleted the following pin names in the table of “Input pulse width” and
figure of “Trigger input timing”
“RX0”, “RXx”
Revised the value of “Analog port input current” in the table, and revised
the pin name note *7 to *9
Revised the pin name note of “Variation between channels”
*7 -> *10
Revised the note of “Total error”
Deleted the note *3
92
13. Ordering Information
Revised the note of “Package”
92
14. Part Number Option
Added the part number options as full production
January 16, 2015, S6J311A_DS708-00004-1v0-E
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the
respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2014-2015 Spansion
TM
TM
®
®
®
TM
All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
ORNAND , Easy DesignSim , Traveo
TM
and combinations thereof, are trademarks and registered trademarks of Spansion
LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks
of their respective owners.
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