2.1 MB

The following document contains information on Cypress products.
S6J3120 Series
32-bit Microcontroller
Spansion® TraveoTM Family
S6J312AHAA
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.
Publication Number S6J312A_DS708-00005
CONFIDENTIAL
Revision 0.1
Issue Date August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
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“This document contains information on one or more products under development at Spansion
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Preliminary
The Preliminary designation indicates that the product development has progressed such that a
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“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
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Some data sheets contain a combination of products with different designations (Advance Information,
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designations wherever necessary, typically on the first page, the ordering information page, and pages
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disclaimer on the first page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal
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may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
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volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered
may occur.”
Questions regarding these document designations may be directed to your local sales office.
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CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
S6J3120 Series
32-bit Microcontroller
Spansion® TraveoTM Family
S6J312AHAA
Data Sheet (Preliminary)
1. DESCRIPTION
This section provides an overview of the S6J3120 series.
®
The S6J3120 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM
Cortex-R5 CPU as a CPU.
Notes:
−
®
ARM, Cortex , Thumb are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number S6J312A_DS708-00005
Revision 0.1
Issue Date August 7, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product
qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to changes in technical specifications.
CONFIDENTIAL
D a t a S h e e t ( P r e l i m i n a r y )
Table of Contents
1.
DESCRIPTION ..................................................................................................................................... 3
2.
FEATURES .......................................................................................................................................... 6
2.1
Cortex-R5 Core ........................................................................................................................ 6
2.2
Peripheral Functions ................................................................................................................ 7
3.
PRODUCT LINEUP ........................................................................................................................... 10
4.
PIN ASSIGNMENT ............................................................................................................................ 12
5.
PIN DESCRIPTION ............................................................................................................................ 13
6.
I/O CIRCUIT TYPES .......................................................................................................................... 30
7.
HANDLING PRECAUTIONS ............................................................................................................. 33
7.1
Precautions for Product Design.............................................................................................. 33
7.2
Precautions for Package Mounting ........................................................................................ 35
7.3
Precautions for Use Environment........................................................................................... 37
8.
HANDLING DEVICES ........................................................................................................................ 38
9.
BLOCK DIAGRAM ............................................................................................................................ 42
10. MEMORY MAP .................................................................................................................................. 43
11. PIN STATUSES IN CPU STATUS ..................................................................................................... 49
12. ELECTRICAL CHARACTERISTICS ................................................................................................. 52
12.1 Absolute Maximum Ratings.................................................................................................... 52
12.2 Recommended operating conditions ...................................................................................... 54
12.3 DC characteristics .................................................................................................................. 55
12.4 AC characteristics .................................................................................................................. 67
12.4.1 Source clock timing .................................................................................................... 67
12.4.2 Internal clock timing ................................................................................................... 69
12.4.3 Reset input ................................................................................................................. 73
12.4.4 Power-on conditions................................................................................................... 74
12.4.5 Clock output timing..................................................................................................... 75
12.4.6 External bus interface timing ...................................................................................... 76
12.4.7 Multi-function serial .................................................................................................... 79
12.4.8 HS-SPI timing............................................................................................................. 99
12.4.9 High current output slew rate ................................................................................... 103
12.5 Timer input timing ................................................................................................................. 104
12.6 QPRC timing ........................................................................................................................ 105
12.7 Trigger input timing .............................................................................................................. 108
12.8 NMI input timing ................................................................................................................... 109
12.9 Low-voltage detection (external low-voltage detection)........................................................ 110
12.10 Low-voltage detection (internal low-voltage detection)......................................................... 111
12.11 Low-voltage detection (1.2 V power supply low-voltage detection) ...................................... 111
12.12 A/D converter ....................................................................................................................... 112
12.12.1
Electrical characteristics ................................................................................. 112
12.12.2
Notes on Using A/D converters ...................................................................... 113
12.12.3
Definition of terms .......................................................................................... 114
12.13 Flash memory ...................................................................................................................... 116
13. ORDERING INFORMATION ............................................................................................................ 117
14. PART NUMBER OPTION ................................................................................................................ 117
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15. PACKAGE DIMENSIONS ................................................................................................................ 118
16. MAJOR CHANGES IN THIS EDITION ............................................................................................ 119
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2. FEATURES
This section explains the features of the S6J3120 series.
2.1
Cortex-R5 Core
This section explains the Cortex-R5 CPU core.
− ARM® Cortex®-R5
− 32-bit ARM architecture
−
2-instruction issuance super scalar
−
8-stage pipeline
− ARMv7/Thumb®-2 instruction set
− MPU (memory protection) equipped
−
16-area support
− ECC support for the TCM ports
1-bit error correction and 2-bit error detection (SEC-DED)
− TCM ports
2 TCM ports
−
ATCM port
−
BTCM port (B0TCM, B1TCM)
− Caches
−
Instruction cache 16 KB
−
Data cache 16 KB
− VIC port
Low latency interrupt
− AXI master interface
64-bit AXI interface (instruction/data access)
32-bit AXI interface (I/O access)
− AXI slave interface
64-bit AXI interface (TCM port access)
− ETM-R5 trace
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2.2
Peripheral Functions
This section explains peripheral functions.
− Clock generation
−
Main clock oscillation (4 MHz)
−
No sub clock oscillation
−
CR oscillation (100 kHz)
−
CR oscillation (4 MHz)
− Built-in flash memory size
−
Program: 1024 K + 64 KB (S6J312AHAA)
−
Work: 112 KB (S6J312AHAA)
− Built-in RAM size
−
TCRAM 64 KB
−
System SRAM 16 KB (S6J312AHAA)
−
Backup RAM 8 KB (S6J312AHAA)
− General-purpose ports: 112 channels (S6J312AHAA)
− External bus interface
−
24-bit address, 16-bit data
− DMA controller
−
Up to 16 channels can be activated simultaneously.
− A/D converter (successive approximation type)
−
12-bit resolution, 2 units mounted: Max 50 channels (22 channels + 28 channels)
(S6J312AHAA)
− External interrupt input: 16 channels
−
Level ("H"/"L") and edge (rising/falling) can be detected.
− Multi-function serial (transmission and reception FIFOs mounted) :Max 10 channels
(S6J312AHAA)
<UART (asynchronous serial interface) >
−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Parity check can be enabled/disabled.
−
Built-in dedicated baud rate generator
−
An external clock can be used as a transfer clock.
−
Parity, frame, overrun error detection functions are available.
−
DMA transfer is supported.
<CSIO (synchronous serial interface) >
−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Support for SPI. Both master and slave roles are supported. Data length in bits can be set to a
value from 5 to 16 or one of the values of 20, 24, and 32.
−
Built-in dedicated baud rate generator (master operation)
−
External clock input is enabled (slave operation).
−
Overrun error detection function is available.
−
DMA transfer is supported.
−
Serial chip select SPI function
<LIN-UART (asynchronous serial interface for LIN) >
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−
Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO
−
Support for LIN protocol revision 2.1
−
Both master and slave roles are supported.
−
Framing error and overrun error detection
−
LIN Synch break generation and detection, LIN Synch Delimiter generation
−
Built-in dedicated baud rate generator
−
The external clock can be adjusted by the reload counter.
DMA transfer is supported.
− CAN controller: CAN-FD Max 3 channels
−
CAN transfer speed :1Mbps
−
CAN Clock :Max 40MHz
−
192 message buffers/channel (reception message buffer size)
− Base timer: Max 30 channels
−
16bit Timer.
−
It is selectable by 4 functions of the PWM/PPG/PWC/Reload Timer.
−
2-channel cascade connection enables operation as a 32-bit timer.(PWC and Reload Timer)
− Reload timer: Max 10 channels
−
32bit Timer.
− Free-run timer: Max 6 channels
−
32bit Timer.
−
Main clock oscillation and CR oscillation are available.
−
Free-run timer output can work in combination with an input capture and an output compare.
− Input capture: Max 12 channels
−
32bit Timer.
− Output compare: Max 12 channels
−
32bit Timer.
− Sound generator : Max 3 channels
−
Frequency and amplitude sequencers provided
− Stepping motor controller : Max 4 channels
−
8/10-bit PWM
−
High current output supported (4 lines × 4 channels)
−
Can refer back electromotive force using pin-shared A/D converter
− LCD controller
−
Common output : 4 , Segment output : 32
−
Duty drive (SEG0 to SEG31) and static drive (ST0 to ST8) can be switched.
−
Each of COM0 to COM3, SEG0 to SEG31, V0, V1, V2, and V3 pins for duty drive can be
switched to the general-purpose port. (The SEG23 to SEG31 pins can be switched to static
driving.)
−
V0, V1, V2 and V3 pin can be used as the general-purpose port. But V3 pin cannot be used as
an output pin.
−
Each of ST0 to ST8 pins for static drive can be switched to the general-purpose port, or it can
be switched to the segment output of duty drive.
− Quad position & revolution counter(QPRC) : Max 2 channels
− Real time clock (RTC) (day/hour/minute/second)
−
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CONFIDENTIAL
Main clock oscillation or CR oscillation (100 kHz) can be selected as an operation clock.
S6J312A_DS708-00005-0v01-E, August 7, 2014
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− Calibration: Real time clock (RTC) driven by the CR clock
−
Correction can be done by configuring the prescaler of the real time clock based on the ratio
between the main clock and the CR clock.
− Clock supervisor
−
Abnormality (such as damaged crystal) of the main clock oscillation (4 MHz) can be monitored.
−
The clock can switch to the CR clock when an abnormality is detected.
−
PLL abnormality can be detected.
− CRC generation
−
Fixed-length CRC
−
CCITT CRC16 generator polynomial: 0x1021
−
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
− DDR HS-SPI
−
2
E PROM and the flash device of the Single/Dual/Quad-SPI protocol can be connected.
− Watchdog timer
−
Hardware watchdog
−
Software watchdog
− NMI
− I/O relocation
−
Peripheral function pin locations can be changed.
− Low-power consumption control
−
Standby function
−
Power-off function
− Power-on reset
− Low-voltage detection reset
− Security
−
Flash security
−
Interface security (JTAG + test port)
−
SHE
−
Unique device ID
− Package: LEU144 (S6J312AHAA)
− CMOS 55 nm technology
− Power supply
−
5 V single power supply
−
The voltage step-down circuit generates internal 1.2 V from 5 V.
−
5 V power supply is used for I/O.
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3. PRODUCT LINEUP
The following table lists the product lineup of the S6J3120 series.
Table 3-1 Product lineup
S6J312AHAA
CPU core
Coretex-R5
CMOS 55 nm technology
55 nm
Package
LEU144
Main clock
4 MHz
100 kHz
Built-in CR oscillator
4 MHz
Maximum CPU operating frequency
112 MHz
1024K bytes
Flash
Program
Small sector (8 KB x 8)
Work
RAM
+
112K bytes
TCRAM
64K bytes
System SRAM
16K bytes
Backup RAM
8K bytes
Watchdog timer
1 channel (hardware)
1 channel (software)
Clock supervisor
YES
External power supply, low-voltage detection reset
YES
Internal power supply, low-voltage detection reset
YES
NMI request
YES
External interrupt
16 channels
DMA controller
16 channels
CAN-FD
Multi-function serial
3 channels
(192 msg buffers/ch)
10 channels
12-bit (2 units)
A/D converter
Unit 0 x 22 channels
Unit 1 x 28 channels
Free-run timer
6 channels
Input capture
12 channels
Output compare
12 channels
Base timer (16-bit)
30 channels
Real time clock (RTC)
1 channel
CR clock calibration
YES
CRC generation
YES
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D a t a S h e e t ( P r e l i m i n a r y )
S6J312AHAA
Low-power consumption mode
SHE
External BUS I/F
Standby function
Power-off function
YES
Address : 24-bit Data :16-bit
Reload Timer(32bit)
10 channels
Quad Position & Revolution Counter
2 channels
DDR HS-SPI
LCD Controller
Sound Generator
Stepping Motor Controller
General-purpose port GPIO
Power supply
Operation assurance temperature (Ta)
On-chip debugger (JTAG)
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YES
32seg x 4com(Static drive 8seg x 1com)
3 channels
4 channels
112 channels
5 V ± 10%
-40 °C to +105 °C
YES
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4. PIN ASSIGNMENT
The following figures show the pin assignment of the S6J3120 series.
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VCC
P421/INT12_1/SIN2_1/TRACECTL/MAD01/SEG7
P420/SCK2_1/TRACECLK/MAD02/SEG6
P418/INT14_0/SCS22_0/TIOB23_0/TOT33/MAD03/SEG5
P417/INT15_1/SOT10_1/TIOA23_1/TIN33/MAD04/SEG4
P416/SIN10_1/IN5_0/TIOA22_1/TOT32/MAD05/SEG3
P414/SCS21_0/TIN32/MAD06/SEG2
P413/INT14_1/SCS20_0/SCS103_1/TOT19/MAD07/SEG1
P411/INT13_1/SCK2_0/SCS101_1/TIOB24_0/TRACEDATA7/TIN19/MAD08/SEG0
P409/SOT2_0/TIOA24_1/TRACEDATA6/TOT18/MAD09/COM3
P408/SIN2_0/TRACEDATA5/TIN18/MAD10/COM2
P407/SCK12_0/SCK10_1/TRACEDATA4/MAD11/COM1
P406/TX2_1/SOT12_0/TRACEDATA3/MAD12/COM0/SGO2_1
P405/INT11_0/RX2_1/SIN12_0/IN4_0/TRACEDATA2/MAD13/V0/SGA2_1
P404/SCS120_0/IN3_0/TRACEDATA1/MAD14/V1/SGO1_1
P403/IN2_0/TRACEDATA0/V2/SGA1_1
P402/INT2_0/RX1_0/IN1_0/V3
P401/TX1_0/IN0_0
C
VSS
VCC
RSTX
P400/MCSX2/SGO0_1
P331/MCSX3/SGA0_1
VSS
X1
X0
MD
NMIX
P327/WOT
TCK
TMS
TDI/P324
TDO/P323
TRST/P322
VCC
Figure 4-1 Pin Assignment for S6J312AHAA
VSS
P000/SOT2_1/AIN8_0/MAD00/SEG8
P001/SCS20_1/BIN8_0/MDATA15/SEG9
P003/SCS22_1/ZIN8_0/MDATA14/SEG10
P005/SIN3_0/IN6_0/AIN9_0/MDATA13/SEG11
P006/SOT3_0/IN7_0/BIN9_0/MDATA12/SEG12
P007/SCK3_0/IN8_0/ZIN9_0/MDATA11/SEG13
P008/SCS30_0/IN9_0/TIOA0_0/MDATA10/SEG14
P009/INT0_1/SIN11_0/IN10_0/TIOA1_0/MDATA09/SEG15
P010/SOT11_0/IN11_0/TIOA2_0/MDATA08/SEG16
P012/SCK11_0/OUT5_0/TIOA3_0/MOEX/SEG17
P013/SCS110_0/OUT6_0/TIOA4_0/MWEX/SEG18
P015/SCS111_0/OUT7_0/TIOA5_0/MCSX0/SEG19
P016/SCS112_0/OUT8_0/TIOA6_0/MCSX1/SEG20
P017/SCS113_0/OUT9_0/TIOA7_0/MDQM0/SEG21
P018/OUT10_0/TIOA8_0/MDQM1/SEG22
P019/TEXT0_0/OUT11_0/TIOB0_0/MAD15/SEG23/ST0
P020/SOT0_0/TEXT1_0/TIOB1_0
P021/SCK0_0/SCK4_1/TIOB2_0
P022/INT3_0/SIN0_0/TIOB3_0
P023/SCS0_0/SIN4_1/TIOB4_0/MAD16/SEG24/ST1
P024/SOT4_1/TIOB5_0/MAD17/SEG25/ST2
P027/SCS42_1/TEXT0_1/TIOB6_0/TIOA4_1/MAD18/SEG26/ST3
P028/SIN1_0/OUT0_1/TIOB7_0/MAD19/SEG27/ST4
P029/SOT1_0/OUT1_1/MAD20/SEG28/ST5
P030/SCS43_1/OUT2_1/TIOB8_0/MAD21/SEG29/ST6
P031/SCS1_0/OUT3_1/MAD22/SEG30/ST7
P100/SCK1_0/OUT4_1/MAD23/SEG31/ST8
P101/AN3/OUT5_1/MDATA07
P103/AN5/OUT6_1/TIOB9_0/MDATA06
P105/OUT7_1/TIOA9_0/MDATA05
P106/TX1_2/OUT8_1/TIN0/MDATA04
P107/INT2_1/RX1_2/OUT9_1/TIOA10_0/TOT0/MDATA03
P108/INT3_1/AN6/OUT10_1/TIOA11_0/TIN1/MRDY
P109/OUT11_1/TIOA12_0/TOT1/MCLK
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
●
TOP VIEW
LEU144
VSS
P321
DVSS
DVCC
P317/INT11_1/AN62/RX1_1/SIN10_0/TIOB29_0/TIOA9_1/PWM2M3
P315/AN61/TX1_1/SCS100_0/IN5_1/TIOB28_0/TIOA8_1/PWM2P3
P314/AN60/SCK10_0/IN4_1/TIOB27_0/TIOA7_1/PWM1M3
P313/INT10_1/AN59/SOT10_0/IN3_1/TIOB26_0/PWM1P3
P312/AN58/SCS101_0/IN2_1/TIOB25_0/PWM2M2
P309/AN57/IN1_1/TIOA29_1/PWM2P2
P308/AN56/IN0_1/TIOA28_1/PWM1M2
P307/INT1_0/AN55/RX0_0/SCS102_0/TIOB18_0/PWM1P2
DVSS
DVCC
P305/AN53/TEXT5_0/TIOA29_0/PWM2M1
P304/AN52/TEXT4_0/TIOA20_1/PWM2P1
P302/AN51/TIOA19_1/PWM1M1
P301/AN50/OUT4_0/TIOA18_1/PWM1P1
P300/AN49/OUT3_0/TIOA28_0/PWM2M0
P231/AN48/OUT2_0/TIOA27_0/PWM2P0
P230/AN47/OUT1_0/TIOA26_0/PWM1M0
P229/INT8_0/AN46/RX0_1/OUT0_0/TIOA25_0/PWM1P0
DVSS
DVCC
AVCC1
AVRH1
AVSS1/AVRL1
P226/AN43/SCK8_0/IN11_2/TIOA17_1
P225/INT0_0/AN42/RX0_2/SOT8_0/IN10_2/TIOB17_0/ZIN9_1
P224/AN41/TX0_2/SCS80_0/IN9_2/BIN9_1
P223/AN40/SCS81_0/IN8_2/AIN9_1
P222/INT7_0/AN39/RX2_0/SIN8_0/IN7_2
P220/AN38/TX2_0/SCS83_0/IN6_2/TIOB16_0
P219/AN37/TEXT3_0/TIOB15_0
P218/AN36/TEXT2_0/TIOB14_0
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P215/INT9_1/SCK8_1/IN5_2/TIOA16_1/SPIDAT3
P214/SOT8_1/IN4_2/TIOA15_1/SPISEL0
P213/INT8_1/SIN8_1/IN3_2/TIOA14_1/SPIDAT1
P212/AN35/SCS41_0/SCS80_1/IN2_2/TIOA13_1/SPIDAT2
P211/AN34/SCS40_0/IN1_2/TIOA22_0/SPIDAT0
P210/INT6_0/AN33/SIN4_0/IN0_2/TIOA21_0/SPICLK
P209/AN32/SOT4_0/TIOA20_0/SPISEL1
P208/AN31/SCS42_0/TIOA19_0/SPISEL2
P207/INT7_1/AN30/SCK4_0/TEXT5_1/SPISEL3
P206/AN29/SCS43_0/TEXT4_1/TIOB22_0
P205/AN28/TEXT3_1/TIOB21_0/ZIN8_1
P204/AN27/IN11_1/TIOB20_0/BIN8_1
P203/IN10_1/TIOB19_0/AIN8_1
P202/INT6_1/SCK9_0/IN9_1
P131/AN24/SOT9_0/IN8_1
P130/INT5_0/AN23/SIN9_0/IN7_1
P129/AN22/IN6_1/SGO2_0
P128/AN21/TEXT2_1/SGA2_0
P127/AN20/TEXT1_1/SGO1_0
P126/AN19/SGA1_0
P123/AN18/SCS93_0/TIOA12_1/SGO0_0
P122/AN17/SCS92_0/TIOA11_1/SGA0_0
P120/AN15/SCS91_0/TOT17
P119/AN14/SCS90_0/TIOB13_0/TIN17
P118/INT5_1/AN13/TIOB12_0/TOT16
P117/INT4_1/AN12/TIOB11_0/TIN16
P115/TIOB10_0/TOT3
AVSS0/AVRL0
AVRH0
AVCC0
P114/AN10/TIOA6_1/TIN3/MDATA00
P113/TIOA5_1/TOT2/MDATA01
P112/AN9/TIOA13_0/TIN2/MDATA02
C
VSS
12
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
5. PIN DESCRIPTION
This section provides a list of the pin functions of the S6J3120 series
Table 5-1 S6J312AHAA Pin Functions
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
2
3
4
5
6
7
P000
-
General-purpose I/O port
SOT2_1
-
Multi-function serial ch.2 serial data output pin (1)
AIN8_0
-
MAD00
-
External bus interface address bit0 output pin
SEG8
-
LCDC segment 8 (Duty) output pin
P001
-
General-purpose I/O port
SCS20_1
-
BIN8_0
-
MDATA15
-
External bus interface data bus bit15 I/O pin
SEG9
-
LCDC segment 9 (Duty) output pin
P003
-
General-purpose I/O port
SCS22_1
-
Multi-function serial ch.2 serial chip select 2 output pin (1)
ZIN8_0
-
MDATA14
-
External bus interface data bus bit14 I/O pin
SEG10
-
LCDC segment 10 (Duty) output pin
P005
-
General-purpose I/O port
SIN3_0
-
Multi-function serial ch.3 serial data input pin (0)
IN6_0
-
AIN9_0
-
MDATA13
-
External bus interface data bus bit13 I/O pin
SEG11
-
LCDC segment 11 (Duty) output pin
P006
-
General-purpose I/O port
SOT3_0
-
Multi-function serial ch.3 serial data output pin (0)
IN7_0
-
BIN9_0
-
MDATA12
-
External bus interface data bus bit12 I/O pin
SEG12
-
LCDC segment 12 (Duty) output pin
P007
-
General-purpose I/O port
SCK3_0
-
Multi-function serial ch.3 clock I/O pin (0)
IN8_0
-
ZIN9_0
-
MDATA11
-
External bus interface data bus bit11 I/O pin
SEG13
-
LCDC segment 13 (Duty) output pin
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
K
QPRC ch.8 AIN input pin (0)
Multi-function serial ch.2 serial chip select 0 I/O pin (1)
K
K
K
K
K
QPRC ch.8 BIN input pin (0)
QPRC ch.8 ZIN input pin (0)
Input capture ch.6 input pin (0)
QPRC ch.9 AIN input pin (0)
Input capture ch.7 input pin (0)
QPRC ch.9 BIN input pin (0)
Input capture ch.8 input pin (0)
QPRC ch.9 ZIN input pin (0)
13
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
8
9
10
11
12
13
14
CONFIDENTIAL
P008
-
SCS30_0
-
Multi-function serial ch.3 serial chip select 0 I/O pin (0)
IN9_0
-
Input capture ch.9 input pin (0)
TIOA0_0
-
MDATA10
-
External bus interface data bus bit10 I/O pin
SEG14
-
LCDC segment 14 (Duty) output pin
P009
-
General-purpose I/O port
INT0_1
-
INT0 external interrupt input pin (1)
SIN11_0
-
Multi-function serial ch.11 serial data input pin (0)
IN10_0
-
TIOA1_0
-
Base timer ch.1 TIOA I/O pin (0)
MDATA09
-
External bus interface data bus bit9 I/O pin
SEG15
-
LCDC segment 15 (Duty) output pin
P010
-
General-purpose I/O port
SOT11_0
-
Multi-function serial ch.11 serial data output pin (0)
IN11_0
-
TIOA2_0
-
MDATA08
-
External bus interface data bus bit8 I/O pin
SEG16
-
LCDC segment 16 (Duty) output pin
P012
-
General-purpose I/O port
SCK11_0
-
Multi-function serial ch.11 clock I/O pin (0)
OUT5_0
-
TIOA3_0
-
MOEX
-
External bus interface read enable output pin
SEG17
-
LCDC segment 17 (Duty) output pin
P013
-
General-purpose I/O port
SCS110_0
-
Multi-function serial ch.11 serial chip select 0 I/O pin (0)
OUT6_0
-
TIOA4_0
-
MWEX
-
External bus interface write enable output pin
SEG18
-
LCDC segment 18 (Duty) output pin
P015
-
General-purpose I/O port
SCS111_0
-
Multi-function serial ch.11 serial chip select 1 I/O pin (0)
OUT7_0
-
TIOA5_0
-
MCSX0
-
External bus interface chip select 0 output pin
SEG19
-
LCDC segment 19 (Duty) output pin
General-purpose I/O port
K
K
K
K
K
K
Base timer ch.0 TIOA output pin (0)
Input capture ch.10 input pin (0)
Input capture ch.11 input pin (0)
Base timer ch.2 TIOA output pin (0)
Output compare ch.5 output pin (0)
Base timer ch.3 TIOA I/O pin (0)
Output compare ch.6 output pin (0)
Base timer ch.4 TIOA output pin (0)
Output compare ch.7 output pin (0)
Base timer ch.5 TIOA I/O pin (0)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
14
15
16
17
18
19
20
21
P016
-
SCS112_0
-
Multi-function serial ch.11 serial chip select 2 I/O pin (0)
OUT8_0
-
Output compare ch.8 output pin (0)
TIOA6_0
-
MCSX1
-
External bus interface chip select 1 output pin
SEG20
-
LCDC segment 20 (Duty) output pin
P017
-
General-purpose I/O port
SCS113_0
-
Multi-function serial ch.11 serial chip select 3 I/O pin (0)
OUT9_0
-
Output compare ch.9 output pin (0)
TIOA7_0
-
MDQM0
-
External bus interface byte mask 0 output pin
SEG21
-
LCDC segment 21 (Duty) output pin
P018
-
General-purpose I/O port
OUT10_0
-
TIOA8_0
-
MDQM1
-
External bus interface byte mask 1 output pin
SEG22
-
LCDC segment 22 (Duty) output pin
P019
-
General-purpose I/O port
TEXT0_0
-
Free-run timer 0 clock input pin (0)
OUT11_0
-
TIOB0_0
-
MAD15
-
SEG23/ST0
-
LCDC segment 23 (Duty) / segment 0 (Static) output pin
P020
-
General-purpose I/O port
SOT0_0
-
TEXT1_0
-
TIOB1_0
-
Base timer ch.1 TIOB input pin (0)
P021
-
General-purpose I/O port
K
K
Base timer ch.6 TIOA output pin (0)
Base timer ch.7 TIOA I/O pin (0)
Output compare ch.10 output pin (0)
K
K
Base timer ch.8 TIOA output pin (0)
Output compare ch.11 output pin (0)
Base timer ch.0 TIOB input pin (0)
External bus interface address bit15 output pin
Q
Multi-function serial ch.0 serial data output pin (0)
Free-run timer 1 clock input pin (0)
SCK0_0
-
SCK4_1
-
TIOB2_0
-
Base timer ch.2 TIOB input pin (0)
P022
-
General-purpose I/O port
INT3_0
-
SIN0_0
-
Q
Q
Multi-function serial ch.0 clock I/O pin (0)
Multi-function serial ch.4 clock I/O pin (1)
INT3 external interrupt input pin (0)
Multi-function serial ch.0 serial data input pin (0)
TIOB3_0
-
Base timer ch.3 TIOB input pin (0)
P023
-
General-purpose I/O port
SCS0_0
-
Multi-function serial ch.0 serial chip select 0 I/O pin (0)
SIN4_1
-
TIOB4_0
-
MAD16
-
External bus interface address bit16 output pin
SEG24/ST1
-
LCDC segment 24 (Duty) / segment 1 (Static) output pin
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
General-purpose I/O port
K
Multi-function serial ch.4 serial data input pin (1)
Base timer ch.4 TIOB input pin (0)
15
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
22
23
24
25
26
27
28
16
CONFIDENTIAL
P024
-
General-purpose I/O port
SOT4_1
-
TIOB5_0
-
Multi-function serial ch.4 serial data output pin (1)
MAD17
-
External bus interface address bit17 output pin
SEG25/ST2
-
LCDC segment 25 (Duty) / segment 2 (Static) output pin
P027
-
General-purpose I/O port
SCS42_1
-
Multi-function serial ch.4 serial chip select 2 I/O pin (1)
TEXT0_1
-
TIOB6_0
-
TIOA4_1
-
Base timer ch.4 TIOA output pin (1)
MAD18
-
External bus interface address bit18 output pin
SEG26/ST3
-
LCDC segment 26 (Duty) / segment 3 (Static) output pin
P028
-
General-purpose I/O port
SIN1_0
-
Multi-function serial ch.1 serial data input pin (0)
OUT0_1
-
Output compare ch.0 output pin (1)
TIOB7_0
-
MAD19
-
External bus interface address bit19 output pin
SEG27/ST4
-
LCDC segment 27 (Duty) / segment 4 (Static) output pin
P029
-
General-purpose I/O port
K
Base timer ch.5 TIOB input pin (0)
Free-run timer 0 clock input pin (1)
K
K
Base timer ch.6 TIOB input pin (0)
Base timer ch.7 TIOB input pin (0)
SOT1_0
-
OUT1_1
-
Multi-function serial ch.1 serial data output pin (0)
MAD20
-
External bus interface address bit20 output pin
SEG28/ST5
-
LCDC segment 28 (Duty) / segment 5 (Static) output pin
P030
-
General-purpose I/O port
SCS43_1
-
Multi-function serial ch.4 serial chip select 3 I/O pin (1)
OUT2_1
-
TIOB8_0
-
MAD21
-
External bus interface address bit21 output pin
SEG29/ST6
-
LCDC segment 29 (Duty) / segment 6 (Static) output pin
P031
-
General-purpose I/O port
SCS1_0
-
Multi-function serial ch.1 serial chip select 0 I/O pin (0)
OUT3_1
-
MAD22
-
External bus interface address bit22 output pin
SEG30/ST7
-
LCDC segment 30 (Duty) / segment 7 (Static) output pin
P100
-
General-purpose I/O port
SCK1_0
-
Multi-function serial ch.1 clock I/O pin (0)
OUT4_1
-
MAD23
-
External bus interface address bit23 output pin
SEG31/ST8
-
LCDC segment 31 (Duty) / segment 8 (Static) output pin
K
K
K
K
Output compare ch.1 output pin (1)
Output compare ch.2 output pin (1)
Base timer ch.8 TIOB input pin (0)
Output compare ch.3 output pin (1)
Output compare ch.4 output pin (1)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
29
30
31
32
33
34
35
P101
-
AN3
-
OUT5_1
-
MDATA07
-
P103
-
General-purpose I/O port
AN5
-
ADC analog 5 input pin
OUT6_1
-
TIOB9_0
-
Base timer ch.9 TIOB input pin (0)
MDATA06
-
External bus interface data bit6 I/O pin
P105
-
General-purpose I/O port
OUT7_1
-
TIOA9_0
-
MDATA05
-
P106
-
General-purpose I/O port
TX1_2
-
CAN transmission data 1 output pin (2)
OUT8_1
-
TIN0
-
Reload timer ch.0 event input pin (0)
MDATA04
-
External bus interface data bit4 I/O pin
P107
-
General-purpose I/O port
INT2_1
-
INT2 external interrupt input pin (1)
RX1_2
-
CAN reception data 1 input pin (2)
OUT9_1
-
TIOA10_0
-
Base timer ch.10 TIOA output pin (0)
TOT0
-
Reload timer ch.0 output pin (0)
MDATA03
-
External bus interface data bit3 I/O pin
P108
-
General-purpose I/O port
INT3_1
-
INT3 external interrupt input pin (1)
AN6
-
ADC analog 6 input pin
OUT10_1
-
TIOA11_0
-
Base timer ch.11 TIOA I/O pin (0)
TIN1
-
Reload timer ch.1 event input pin (0)
MRDY
-
External bus interface ready input pin
P109
-
General-purpose I/O port
OUT11_1
-
Output compare ch.11 output pin (1)
TIOA12_0
-
TOT1
-
Reload timer ch.1 output pin (0)
MCLK
-
External bus interface system clock output pin
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
General-purpose I/O port
B
ADC analog 3 input pin
Output compare ch.5 output pin (1)
External bus interface data bit7 I/O pin
B
Q
Output compare ch.6 output pin (1)
Output compare ch.7 output pin (1)
Base timer ch.9 TIOA I/O pin (0)
External bus interface data bit5 I/O pin
Q
Q
B
Q
Output compare ch.8 output pin (1)
Output compare ch.9 output pin (1)
Output compare ch.10 output pin (1)
Base timer ch.12 TIOA output pin (0)
17
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
39
40
41
45
46
47
48
49
50
18
CONFIDENTIAL
P112
-
General-purpose I/O port
AN9
-
TIOA13_0
-
TIN2
-
MDATA02
-
External bus interface data bit2 I/O pin
P113
-
General-purpose I/O port
TIOA5_1
-
TOT2
-
MDATA01
-
External bus interface data bit1 I/O pin
P114
-
General-purpose I/O port
AN10
-
TIOA6_1
-
TIN3
-
Reload timer ch.3 event input pin (0)
MDATA00
-
External bus interface data bit0 I/O pin
P115
-
General-purpose I/O port
TIOB10_0
-
TOT3
-
Reload timer ch.3 output pin (0)
P117
-
General-purpose I/O port
INT4_1
-
INT4 external interrupt input pin (1)
AN12
-
TIOB11_0
-
Base timer ch.11 TIOB input pin (0)
TIN16
-
Reload timer ch.16 event input pin (0)
P118
-
General-purpose I/O port
INT5_1
-
INT5 external interrupt input pin (1)
AN13
-
TIOB12_0
-
Base timer ch.12 TIOB input pin (0)
TOT16
-
Reload timer ch.16 output pin (0)
P119
-
General-purpose I/O port
AN14
-
SCS90_0
-
TIOB13_0
-
Base timer ch.13 TIOB input pin (0)
TIN17
-
Reload timer ch.17 event input pin (0)
P120
-
General-purpose I/O port
AN15
-
SCS91_0
-
TOT17
-
Reload timer ch.17 output pin (0)
P122
-
General-purpose I/O port
ADC analog 9 input pin
B
Base timer ch.13 TIOA I/O pin (0)
Reload timer ch.2 event input pin (0)
Q
Base timer ch.5 TIOA I/O pin (1)
Reload timer ch.2 output pin (0)
ADC analog 10 input pin
B
Q
B
B
Base timer ch.6 TIOA output pin (1)
Base timer ch.10 TIOB input pin (0)
ADC analog 12 input pin
ADC analog 13 input pin
ADC analog 14 input pin
B
B
Multi-function serial ch.9 serial chip select 0 I/O pin (0)
ADC analog 15 input pin
Multi-function serial ch.9 serial chip select 1 I/O pin (0)
AN17
-
SCS92_0
-
ADC analog 17 input pin
TIOA11_1
-
Base timer ch.11 TIOA I/O pin (1)
SGA0_0
-
Sound generator ch.0 SGA output pin (0)
B
Multi-function serial ch.9 serial chip select 2 I/O pin (0)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
51
52
53
54
55
56
57
58
59
P123
-
AN18
-
SCS93_0
-
TIOA12_1
-
Base timer ch.12 TIOA output pin (1)
SGO0_0
-
Sound generator ch.0 SGO output pin (0)
P126
-
General-purpose I/O port
AN19
-
ADC analog 18 input pin
B
B
Multi-function serial ch.9 serial chip select 3 I/O pin (0)
ADC analog 19 input pin
SGA1_0
-
Sound generator ch.1 SGA output pin (0)
P127
-
General-purpose I/O port
AN20
-
TEXT1_1
-
SGO1_0
-
Sound generator ch.1 SGO output pin (0)
P128
-
General-purpose I/O port
B
ADC analog 20 input pin
Free-run timer 1 clock input pin (1)
AN21
-
TEXT2_1
-
SGA2_0
-
Sound generator ch.2 SGA output pin (0)
P129
-
General-purpose I/O port
AN22
-
IN6_1
-
SGO2_0
-
Sound generator ch.2 SGO output pin (0)
P130
-
General-purpose I/O port
INT5_0
-
INT5 external interrupt input pin (0)
B
B
B
ADC analog 21 input pin
Free-run timer 2 clock input pin (1)
ADC analog 22 input pin
Input capture ch.6 input pin (1)
AN23
-
SIN9_0
-
Multi-function serial ch.9 serial data input pin (0)
IN7_1
-
Input capture ch.7 input pin (1)
P131
-
General-purpose I/O port
AN24
-
SOT9_0
-
IN8_1
-
Input capture ch.8 input pin (1)
P202
-
General-purpose I/O port
INT6_1
-
B
Q
ADC analog 23 input pin
ADC analog 24 input pin
Multi-function serial ch.9 serial data output pin (0)
INT6 external interrupt input pin (1)
SCK9_0
-
IN9_1
-
Input capture ch.9 input pin (1)
P203
-
General-purpose I/O port
IN10_1
-
TIOB19_0
-
AIN8_1
-
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
General-purpose I/O port
Q
Multi-function serial ch.9 clock I/O pin (0)
Input capture ch.10 input pin (1)
Base timer ch.19 TIOB input pin (0)
QPRC ch.8 AIN input pin (1)
19
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
60
61
62
63
64
65
66
20
CONFIDENTIAL
P204
-
General-purpose I/O port
AN27
-
IN11_1
-
ADC analog 27 input pin
TIOB20_0
-
Base timer ch.20 TIOB input pin (0)
BIN8_1
-
QPRC ch.8 BIN input pin (1)
P205
-
General-purpose I/O port
AN28
-
ADC analog 28 input pin
TEXT3_1
-
TIOB21_0
-
Base timer ch.21 TIOB input pin (0)
ZIN8_1
-
QPRC ch.8 ZIN input pin (1)
P206
-
General-purpose I/O port
AN29
-
ADC analog 29 input pin
SCS43_0
-
TEXT4_1
-
Free-run timer 4 clock input pin (1)
TIOB22_0
-
Base timer ch.22 TIOB input pin (0)
P207
-
General-purpose I/O port
INT7_1
-
INT7 external interrupt input pin (1)
AN30
-
SCK4_0
-
TEXT5_1
-
Free-run timer 5 clock input pin (1)
SPISEL3
-
HS-SPI slave select 3 output pin
P208
-
General-purpose I/O port
B
B
B
B
Input capture ch.11 input pin (1)
Free-run timer 3 clock input pin (1)
Multi-function serial ch.4 serial chip select 3 I/O pin (0)
ADC analog 30 input pin
Multi-function serial ch.4 clock I/O pin (0)
AN31
-
SCS42_0
-
ADC analog 31 input pin
TIOA19_0
-
Base timer ch.19 TIOA I/O pin (0)
SPISEL2
-
HS-SPI slave select 2 output pin
P209
-
General-purpose I/O port
AN32
-
ADC analog 32 input pin
SOT4_0
-
TIOA20_0
-
Base timer ch.20 TIOA output pin (0)
SPISEL1
-
HS-SPI slave select 1 output pin
P210
-
General-purpose I/O port
INT6_0
-
INT6 external interrupt input pin (0)
AN33
-
ADC analog 33 input pin
SIN4_0
-
IN0_2
-
Input capture ch.0 input pin (2)
TIOA21_0
-
Base timer ch.21 TIOA I/O pin (0)
SPICLK
-
HS-SPI clock output pin
B
B
B
Multi-function serial ch.4 serial chip select 2 I/O pin (0)
Multi-function serial ch.4 serial data output pin (0)
Multi-function serial ch.4 serial data input pin (0)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
67
68
69
70
71
74
75
P211
-
General-purpose I/O port
AN34
-
ADC analog 34 input pin
SCS40_0
-
IN1_2
-
TIOA22_0
-
Base timer ch.22 TIOA output pin (0)
SPIDAT0
-
HS-SPI data 0 I/O pin
P212
-
General-purpose I/O port
Multi-function serial ch.4 serial chip select 0 I/O pin (0)
Input capture ch.1 input pin (2)
AN35
-
ADC analog 35 input pin
SCS41_0
-
Multi-function serial ch.4 serial chip select 1 I/O pin (0)
SCS80_1
-
IN2_2
-
Input capture ch.2 input pin (2)
TIOA13_1
-
Base timer ch.13 TIOA I/O pin (1)
SPIDAT2
-
HS-SPI data 2 I/O pin
P213
-
General-purpose I/O port
INT8_1
-
INT8 external interrupt input pin (1)
SIN8_1
-
IN3_2
-
TIOA14_1
-
Base timer ch.14 TIOA output pin (1)
SPIDAT1
-
HS-SPI data 1 I/O pin
P214
-
General-purpose I/O port
SOT8_1
-
Multi-function serial ch.8 serial data output pin (1)
IN4_2
-
TIOA15_1
-
Base timer ch.15 TIOA I/O pin (1)
SPISEL0
-
HS-SPI slave select 0 output pin
P215
-
General-purpose I/O port
INT9_1
-
INT9 external interrupt input pin (1)
SCK8_1
-
IN5_2
-
TIOA16_1
-
Base timer ch.16 TIOA output pin (1)
SPIDAT3
-
HS-SPI data 3 I/O pin
P218
-
General-purpose I/O port
B
Q
Q
Q
Multi-function serial ch.8 serial chip select 0 I/O pin (1)
Multi-function serial ch.8 serial data input pin (1)
Input capture ch.3 input pin (2)
Input capture ch.4 input pin (2)
Multi-function serial ch.8 clock I/O pin (1)
Input capture ch.5 input pin (2)
AN36
-
TEXT2_0
-
TIOB14_0
-
P219
-
General-purpose I/O port
AN37
-
ADC analog 37 input pin
TEXT3_0
-
TIOB15_0
-
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
B
B
ADC analog 36 input pin
Free-run timer 2 clock input pin (0)
Base timer ch.14 TIOB input pin (0)
B
Free-run timer 3 clock input pin (0)
Base timer ch.15 TIOB input pin (0)
21
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
76
77
78
79
80
81
22
CONFIDENTIAL
P220
-
General-purpose I/O port
ADC analog 38 input pin
AN38
-
TX2_0
-
SCS83_0
-
IN6_2
-
Input capture ch.6 input pin (2)
TIOB16_0
-
Base timer ch.16 TIOB input pin (0)
P222
-
General-purpose I/O port
INT7_0
-
INT7 external interrupt input pin (0)
AN39
-
RX2_0
-
SIN8_0
-
Multi-function serial ch.8 serial data input pin (0)
IN7_2
-
Input capture ch.7 input pin (2)
P223
-
General-purpose I/O port
B
B
CAN transmission data 2 output pin (0)
Multi-function serial ch.8 serial chip select 3 I/O pin (0)
ADC analog 39 input pin
CAN reception data 2 input pin (0)
AN40
-
SCS81_0
-
ADC analog 40 input pin
IN8_2
-
Input capture ch.8 input pin (2)
AIN9_1
-
QPRC ch.9 AIN input pin (1)
P224
-
General-purpose I/O port
AN41
-
ADC analog 41 input pin
TX0_2
-
SCS80_0
-
IN9_2
-
Input capture ch.9 input pin (2)
BIN9_1
-
QPRC ch.9 BIN input pin (1)
P225
-
General-purpose I/O port
INT0_0
-
INT0 external interrupt input pin (0)
ADC analog 42 input pin
B
B
Multi-function serial ch.8 serial chip select 1 I/O pin (0)
CAN transmission data 0 output pin (2)
Multi-function serial ch.8 serial chip select 0 I/O pin (0)
AN42
-
RX0_2
-
SOT8_0
-
IN10_2
-
Input capture ch.10 input pin (2)
TIOB17_0
-
Base timer ch.17 TIOB input pin (0)
ZIN9_1
-
QPRC ch.9 ZIN input pin (1)
P226
-
General-purpose I/O port
AN43
-
ADC analog 43 input pin
SCK8_0
-
IN11_2
-
Input capture ch.11 input pin (2)
TIOA17_1
-
Base timer ch.17 TIOA I/O pin (1)
B
B
CAN reception data 0 input pin (2)
Multi-function serial ch.8 serial data output pin (0)
Multi-function serial ch.8 clock I/O pin (0)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
87
88
89
90
91
92
93
94
P229
-
General-purpose I/O port
INT8_0
-
INT8 external interrupt input pin (0)
AN46
-
ADC analog 46 input pin
RX0_1
-
OUT0_0
-
Output compare ch.0 output pin (0)
TIOA25_0
-
Base timer ch.25 TIOA I/O pin (0)
PWM1P0
-
SMC ch.0 (P1) output pin
P230
-
General-purpose I/O port
AN47
-
ADC analog 47 input pin
OUT1_0
-
TIOA26_0
-
Base timer ch.26 TIOA output pin (0)
PWM1M0
-
SMC ch.0 (M1) output pin
P231
-
General-purpose I/O port
M
CAN reception data 0 input pin (1)
Output compare ch.1 output pin (0)
AN48
-
OUT2_0
-
TIOA27_0
-
Base timer ch.27 TIOA I/O pin (0)
PWM2P0
-
SMC ch.0 (P2) output pin
P300
-
General-purpose I/O port
AN49
-
ADC analog 49 input pin
OUT3_0
-
TIOA28_0
-
Base timer ch.28 TIOA output pin (0)
PWM2M0
-
SMC ch.0 (M2) output pin
P301
-
General-purpose I/O port
AN50
-
ADC analog 50 input pin
OUT4_0
-
TIOA18_1
-
Base timer ch.18 TIOA output pin (1)
PWM1P1
-
SMC ch.1 (P1) output pin
P302
-
General-purpose I/O port
ADC analog 48 input pin
M
M
M
Output compare ch.2 output pin (0)
Output compare ch.3 output pin (0)
Output compare ch.4 output pin (0)
AN51
-
TIOA19_1
-
PWM1M1
-
P304
-
General-purpose I/O port
AN52
-
ADC analog 52 input pin
TEXT4_0
-
TIOA20_1
-
Base timer ch.20 TIOA output pin (1)
PWM2P1
-
SMC ch.1 (P2) output pin
P305
-
General-purpose I/O port
M
ADC analog 51 input pin
Base timer ch.19 TIOA I/O pin (1)
SMC ch.1 (M1) output pin
M
Free-run timer 4 clock input pin (0)
AN53
-
TEXT5_0
-
TIOA29_0
-
Base timer ch.29 TIOA I/O pin (0)
PWM2M1
-
SMC ch.1 (M2) output pin
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
M
ADC analog 53 input pin
M
Free-run timer 5 clock input pin (0)
23
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
97
98
99
100
101
102
24
CONFIDENTIAL
P307
-
General-purpose I/O port
INT1_0
-
INT1 external interrupt input pin (0)
AN55
-
ADC analog 55 input pin
RX0_0
-
M
CAN reception data 0 input pin (0)
SCS102_0
-
Multi-function serial ch.10 serial chip select 2 I/O pin (0)
TIOB18_0
-
Base timer ch.18 TIOB input pin (0)
PWM1P2
-
SMC ch.2 (P1) output pin
P308
-
General-purpose I/O port
AN56
-
ADC analog 56 input pin
IN0_1
-
TIOA28_1
-
Base timer ch.28 TIOA output pin (1)
PWM1M2
-
SMC ch.2 (M1) output pin
P309
-
General-purpose I/O port
M
Input capture ch.0 input pin (1)
AN57
-
IN1_1
-
ADC analog 57 input pin
TIOA29_1
-
Base timer ch.29 TIOA I/O pin (1)
PWM2P2
-
SMC ch.2 (P2) output pin
P312
-
General-purpose I/O port
AN58
-
ADC analog 58 input pin
SCS101_0
-
IN2_1
-
TIOB25_0
-
Base timer ch.25 TIOB input pin (0)
PWM2M2
-
SMC ch.2 (M2) output pin
P313
-
General-purpose I/O port
INT10_1
-
INT10 external interrupt input pin (1)
AN59
-
SOT10_0
-
IN3_1
-
Input capture ch.3 input pin (1)
TIOB26_0
-
Base timer ch.26 TIOB input pin (0)
PWM1P3
-
SMC ch.3 (P1) output pin
P314
-
General-purpose I/O port
AN60
-
ADC analog 60 input pin
SCK10_0
-
Multi-function serial ch.10 clock I/O pin (0)
IN4_1
-
TIOB27_0
-
Base timer ch.27 TIOB input pin (0)
TIOA7_1
-
Base timer ch.7 TIOA I/O pin (1)
PWM1M3
-
SMC ch.3 (M1) output pin
M
M
Input capture ch.1 input pin (1)
Multi-function serial ch.10 serial chip select 1 I/O pin (0)
Input capture ch.2 input pin (1)
ADC analog 59 input pin
M
M
Multi-function serial ch.10 serial data output pin (0)
Input capture ch.4 input pin (1)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
103
104
107
110
P315
-
General-purpose I/O port
AN61
-
ADC analog 61 input pin
TX1_1
-
CAN transmission data 1 output pin (1)
SCS100_0
-
IN5_1
-
TIOB28_0
-
Base timer ch.28 TIOB input pin (0)
TIOA8_1
-
Base timer ch.8 TIOA output pin (1)
M
Multi-function serial ch.10 serial chip select 0 I/O pin (0)
Input capture ch.5 input pin (1)
PWM2P3
-
SMC ch.3 (P2) output pin
P317
-
General-purpose I/O port
INT11_1
-
INT11 external interrupt input pin (1)
AN62
-
ADC analog 62 input pin
RX1_1
-
SIN10_0
-
TIOB29_0
-
Base timer ch.29 TIOB input pin (0)
TIOA9_1
-
Base timer ch.9 TIOA I/O pin (1)
PWM2M3
-
SMC ch.3 (M2) output pin
P321
-
TRST
N
M
D
J
CAN reception data 1 input pin (1)
Multi-function serial ch.10 serial data input pin (0)
General-purpose output port
JTAG test reset input pin
P322
-
TDO
-
P323
-
TDI
-
P324
-
113
TMS
-
E
JTAG test mode state input pin
114
TCK
-
E
JTAG test clock input pin
P327
-
WOT
-
116
NMIX
-
F
Non-maskable interrupt input pin
117
MD
-
C
Mode pin
118
X0
-
G
Main clock oscillation input pin
119
X1
-
G
Main clock oscillation output pin
P331
-
MCSX3
-
Q
External bus interface chip select 3 output pin
SGA0_1
-
P400
-
MCSX2
-
SGO0_1
-
RSTX
N
111
112
115
121
122
123
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
I
D
Q
General-purpose output port
JTAG test data output pin
General-purpose output port
JTAG test data input pin
General-purpose output port
General-purpose I/O port
RTC output pin
General-purpose I/O port
Sound generator ch.0 SGA output pin (1)
General-purpose I/O port
Q
External bus interface chip select 2 output pin
Sound generator ch.0 SGO output pin (1)
F
External reset input pin
25
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
127
128
129
130
131
132
26
CONFIDENTIAL
P401
-
General-purpose I/O port
TX1_0
-
IN0_0
-
Input capture ch.0 input pin (0)
P402
-
General-purpose I/O port (Input only. No output.)
INT2_0
-
RX1_0
-
IN1_0
-
Input capture ch.1 input pin (0)
V3
-
LCDC reference voltage V3 input pin
P403
-
General-purpose I/O port
IN2_0
-
Input capture ch.2 input pin (0)
TRACEDATA0
-
V2
-
LCDC reference voltage V2 input pin
SGA1_1
-
Sound generator ch.1 SGA output pin (1)
P404
-
General-purpose I/O port
SCS120_0
-
Multi-function serial ch.12 serial chip select 0 I/O pin (0)
IN3_0
-
Input capture ch.3 input pin (0)
TRACEDATA1
-
MAD14
-
External bus interface address bit14 output pin
V1
-
LCDC reference voltage V1 input pin
SGO1_1
-
Sound generator ch.1 SGO output pin (1)
P405
-
General-purpose I/O port
INT11_0
-
INT11 external interrupt input pin (0)
RX2_1
-
CAN reception data 2 input pin (1)
SIN12_0
-
Multi-function serial ch.12 serial data input pin (0)
IN4_0
-
TRACEDATA2
-
Trace data 2 output pin
MAD13
-
External bus interface address bit13 output pin
V0
-
LCDC reference voltage V0 input pin
SGA2_1
-
Sound generator ch.2 SGA output pin (1)
P406
-
General-purpose I/O port
TX2_1
-
CAN transmission data 2 output pin (1)
SOT12_0
-
TRACEDATA3
-
MAD12
-
External bus interface address bit12 output pin
COM0
-
LCDC segment(duty) common 0 output pin
SGO2_1
-
Sound generator ch.2 SGO output pin (1)
Q
CAN transmission data 1 output pin (0)
INT2 external interrupt input pin (0)
L
B
B
B
CAN reception data 1 input pin (0)
Trace data 0 output pin
Trace data 1 output pin
Input capture ch.4 input pin (0)
Multi-function serial ch.12 serial data output pin (0)
K
Trace data 3 output pin
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
133
134
135
136
137
138
P407
-
SCK12_0
-
Multi-function serial ch.12 clock I/O pin (0)
SCK10_1
-
Multi-function serial ch.10 clock I/O pin (1)
TRACEDATA4
-
MAD11
-
External bus interface address bit11 output pin
COM1
-
LCDC segment(duty) common 1 output pin
P408
-
General-purpose I/O port
SIN2_0
-
Multi-function serial ch.2 serial data input pin (0)
TRACEDATA5
-
Trace data 5 output pin
TIN18
-
MAD10
-
External bus interface address bit10 output pin
COM2
-
LCDC segment(duty) common 2 output pin
P409
-
General-purpose I/O port
SOT2_0
-
Multi-function serial ch.2 serial data output pin (0)
TIOA24_1
-
Base timer ch.24 TIOA output pin (1)
TRACEDATA6
-
TOT18
-
Reload timer ch.18 output pin (0)
MAD09
-
External bus interface address bit9 output pin
COM3
-
LCDC segment(duty) common 3 output pin
P411
-
General-purpose I/O port
INT13_1
-
INT13 external interrupt input pin (1)
SCK2_0
-
Multi-function serial ch.2 clock I/O pin (0)
SCS101_1
-
TIOB24_0
-
TRACEDATA7
-
Trace data 7 output pin
TIN19
-
Reload timer ch.19 event input pin (0)
MAD08
-
External bus interface address bit8 output pin
K
K
K
Trace data 4 output pin
Reload timer ch.18 event input pin (0)
Trace data 6 output pin
Multi-function serial ch.10 serial chip select 1 I/O pin (1)
K
Base timer ch.24 TIOB input pin (0)
SEG0
-
LCDC segment 0 (Duty) output pin
P413
-
General-purpose I/O port
INT14_1
-
INT14 external interrupt input pin (1)
SCS20_0
-
SCS103_1
-
TOT19
-
Reload timer ch.19 output pin (0)
MAD07
-
External bus interface address bit7 output pin
SEG1
-
LCDC segment 1 (Duty) output pin
P414
-
General-purpose I/O port
SCS21_0
-
TIN32
-
MAD06
-
External bus interface address bit6 output pin
SEG2
-
LCDC segment 2 (Duty) output pin
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
General-purpose I/O port
Multi-function serial ch.2 serial chip select 0 I/O pin (0)
K
Multi-function serial ch.10 serial chip select 3 I/O pin (1)
Multi-function serial ch.2 serial chip select 1 output pin (0)
K
Reload timer ch.32 event input pin (0)
27
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
P416
-
SIN10_1
-
Multi-function serial ch.10 serial data input pin (1)
IN5_0
-
Input capture ch.5 input pin (0)
TIOA22_1
-
TOT32
-
Reload timer ch.32 output pin (0)
MAD05
-
External bus interface address bit5 output pin
SEG3
-
LCDC segment 3 (Duty) output pin
P417
-
General-purpose I/O port
INT15_1
-
INT15 external interrupt input pin (1)
SOT10_1
-
Multi-function serial ch.10 serial data output pin (1)
TIOA23_1
-
TIN33
-
Reload timer ch.33 event input pin (0)
MAD04
-
External bus interface address bit4 output pin
SEG4
-
LCDC segment 4 (Duty) output pin
P418
-
General-purpose I/O port
INT14_0
-
INT14 external interrupt input pin (0)
SCS22_0
-
TIOB23_0
-
TOT33
-
Reload timer ch.33 output pin (0)
MAD03
-
External bus interface address bit3 output pin
SEG5
-
LCDC segment 5 (Duty) output pin
P420
-
General-purpose I/O port
SCK2_1
-
TRACECLK
-
MAD02
-
External bus interface address bit2 output pin
SEG6
-
LCDC segment 6 (Duty) output pin
P421
-
General-purpose I/O port
INT12_1
-
INT12 external interrupt input pin (1)
SIN2_1
-
Multi-function serial ch.2 serial data input pin (1)
TRACECTL
-
MAD01
-
External bus interface address bit1 output pin
SEG7
-
LCDC segment 7 (Duty) output pin
42
AVCC0
-
-
Analog power supply pin for AD converter unit 0
84
AVCC1
-
-
Analog power supply pin for AD converter unit 1
43
AVRH0
-
-
Upper-limit reference voltage pin for AD converter unit 0
83
AVRH1
-
-
Upper-limit reference voltage pin for AD converter unit 1
-
-
-
-
139
140
141
142
143
44
82
28
CONFIDENTIAL
AVSS0
AVRL0
AVSS1
AVRL1
General-purpose I/O port
K
K
Base timer ch.22 TIOA output pin (1)
Base timer ch.23 TIOA I/O pin (1)
Multi-function serial ch.2 serial chip select 2 output pin (0)
K
Base timer ch.23 TIOB input pin (0)
Multi-function serial ch.2 clock I/O pin (1)
K
K
Trace clock
Trace control
GND pin for AD converter unit 0
Lower-limit reference voltage pin for AD converter unit 0
GND pin for AD converter unit 1
Lower-limit reference voltage pin for AD converter unit 1
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
I/O
Pin No.
Pin Name
Polarity
Circuit
Function
Type
38
126
C
-
-
External capacity connection output pin
VCC
-
-
Power supply pin
VSS
-
-
GND
DVCC
-
-
Power Supply pin for SMC high current
DVSS
-
-
GND pin for SMC high current
36
72
109
124
144
1
37
73
108
120
125
85
95
105
86
96
106
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
29
D a t a S h e e t ( P r e l i m i n a r y )
6. I/O CIRCUIT TYPES
This section explains I/O circuit types.
Type
A
Circuit
Overview
Pull-up control
Digital output
Digital output
Pull-down control
−
General-purpose I/O port with analog input
−
Output of 1 mA or 2 mA selectable
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
CMOS hysteresis input
−
General-purpose I/O port with analog input
−
Output of 1 mA or 2 mA selectable
CMOS input
PSS control
Analog input
B
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
Analog input
C
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
Automotive/CMOS hysteresis input selectable
−
Mode input
−
CMOS hysteresis input
−
JTAG
−
General-purpose output port
−
Output of 2 mA
Mode
input
Control
D
Pull-up control
Digital output
Digital output
−
50 kΩ with pull-up resistor control
−
TTL input
TTL input
30
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Type
Circuit
Overview
E
Pull-up control
−
JTAG
−
50 kΩ with pull-up resistor control
−
TTL input
−
CMOS hysteresis input
−
50 kΩ with pull-up resistor
−
Main oscillation I/O
−
JTAG
−
Output of 2 mA
−
JTAG
−
General-purpose output port
−
Output of 2 mA
−
50 kΩ with pull-down resistor control
−
TTL input
−
General-purpose I/O port with COM/SEG output
−
Output of 1 mA or 2 mA selectable
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
Automotive/CMOS hysteresis input selectable
TTL input
F
CMOS-hys input
G
Input
Standby
control
I
Digital output
Digital output
J
Digital output
Digital output
Pull-down control
TTL input
K
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
COM/SEG output
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
Type
L
Circuit
Pull-up control
Overview
−
General-purpose I/O port with LCDC V3 input
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
Automotive/CMOS hysteresis input selectable
−
General-purpose I/O port with analog input
−
Output of 1 mA or 2 mA or 30mA selectable
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
Automotive/CMOS hysteresis input selectable
−
General-purpose I/O port
−
Output of 1 mA or 2 mA selectable
−
50 kΩ with pull-up resistor control
−
50 kΩ with pull-down resistor control
−
Automotive/CMOS hysteresis input selectable
Pull-down control
Automotive/
CMOS input
PSS control
LCDC V3 input
M
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
Analog input
Q
Pull-up control
Digital output
Digital output
Pull-down control
Automotive/
CMOS input
PSS control
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D a t a S h e e t ( P r e l i m i n a r y )
7. HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
7.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not
exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the
data sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to
power supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to
cause deterioration within the device, and in extreme cases leads to permanent damage of
the device. Try to prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large
capacitance can cause large current flows. Such conditions if present for extended periods
of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of
operation. Such pins should be connected through an appropriate resistance to a power
supply pin or ground pin.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate.
When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor
structures) may be formed, causing large current levels in excess of several hundred mA to flow
continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This
should include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and
standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment,
personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy
controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are
requested to consult with sales representatives before such use. The company will not be responsible for
damages arising from such use without prior approval.
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D a t a S h e e t ( P r e l i m i n a r y )
7.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion’s recommended conditions. For
detailed information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute
ratings for storage temperature. Mounting processes should conform to Spansion recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces
can lead to contact deterioration after long periods. For this reason it is recommended that the surface
treatment of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore
leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin
pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to
solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages
in accordance with Spansion ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental
conditions will cause absorption of moisture. During mounting, the application of heat to a package that
has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages
to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the
product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity,
and at temperatures between 5 ˚C and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their
aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the
Spansion recommended conditions for baking.
Condition: 125 ˚C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must
take the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through
high resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures
to minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed
board assemblies.
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S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
7.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit
boards. If high humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause
abnormal operation. In such cases, use anti-static measures or processing to prevent
discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that
will adversely affect the device. If you use devices in such conditions, consider ways to
prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic
radiation. Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near
combustible substances. If devices begin to smoke or burn, there is danger of the release of
toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
8. HANDLING DEVICES
For latch-up prevention
The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an
input or output pin is higher than VCC or lower than VSS; or the voltage applied between a VCC pin
and a VSS pin exceeds the rating. A latch-up causes a rapid increase in the power supply current,
possibly resulting in thermal damage to an element. When using the device, take sufficient care not to
exceed the maximum rating.
Also be careful that analog power supplies (AVCC0, AVCC1, AVRH0, and AVRH1) and analog inputs
do not exceed the digital power supply (VCC) at the analog system power-on and power-off times.
VCC and DVCC must be set to the same voltage.
The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and
analog supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1), and the power supply voltage of
high-current output buffer pins (DVCC), or turn on the digital supply voltage (VCC) and then the analog
supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1), and the power supply voltage of high-current
output buffer pins (DVCC).
About handling unused pins
Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take
measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kiloohms
or higher.
If there are any unused input/output pins, set them to the output state and then open them, or set them
to the input state and handle them in the same way as input pins.
About power supply pins
If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that
should be at the same potential are connected to each other inside the device to prevent malfunctions
such as latch-up. However, to reduce unwanted emissions, prevent malfunctions of strobe signals
caused by an increase of the ground level, and observe standards on total output current, be sure to
connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS
power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS
systems, the device does not operate normally even within the guaranteed operating range.
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S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Figure 8-1 Pin Assignment
In addition, consider connecting with low impedance from the power supply source to the VCC and
VSS of this device.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of
C pin is recommended to use as a bypass capacitor between the VCC pin and the VSS pin.
About the crystal oscillation circuit
Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a
way that the X0 and X1 pins, the crystal oscillator (or ceramic resonator), and a bypass capacitor to
ground are located very close to the device.
We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground.
About the mode pin (MD)
Use mode pin MD by directly connecting it to a VCC or VSS pin. To prevent noise from causing the
device to accidentally enter test mode, reduce the pattern length between each mode pin and a VCC
or VSS pin on the printed circuit board, and connect them with low impedance.
About the power-on time
To prevent the internal built-in voltage step-down circuit from malfunctioning, secure a voltage rise time
of 50 µs (between 0.2 V and 2.7 V) or longer at the power-on time.
Point to note during PLL clock operation
While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue
operating with the free running frequency of the internal self-oscillator circuit. This operation is outside
of the guaranteed range.
Power supply pin processing of an A/D converter
Even when no A/D converter is used, establish a connection such that AVCC=AVRH=VCC and
AVSS/AVRL=VSS.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
Points to note about using external clocks
External clocks are not supported.
External direct clock input cannot be used.
Power-on sequence of the power supply analog inputs of an A/D converter
Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC,
AVRH, and AVRL) and analog inputs (AN3, AN5 to AN6, AN9 to AN10, AN12 to AN15, AN17 to AN24,
AN27 to AN43, AN46 to AN53, and AN55 to AN62) of an A/D converter.
At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn
off the digital power supply (VCC). Perform these power-on and power-off operations without AVRH
exceeding AVCC. Even when using a pin shared with an analog input as an input port, do not allow the
input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital supply voltage
simultaneously is not a problem.)
Treatment of power supplies for high current output buffer pins (DVCC, DVSS)
Be sure to turn on the digital power supply voltage (VCC) first, and then turn on the power supply
voltage for high current output buffer pins (DVCC, DVSS). Also, turn off the power supplies for high
current output buffer pins first, and then turn off the digital power supply voltage (VCC).
Even if the high current output buffer pins are used as general-purpose ports, the power supply
voltage of high current output buffer pins (DVCC, DVSS) must be powered. (The power supplies of
high current output buffer pins and the digital power supplies can be turned on or off simultaneously.)
Connect the pins to have DVCC=VCC and DVSS=VSS.
About C pin processing
This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin (pin
126 and pin 38 in S6J312AHAA specifications) for internal stabilization of the device. For the standard
values, see "Recommended operating conditions" in the latest data sheet.
Precautions on designing a mounting substrate
Measures against heat generation from the package must be taken for the mounting substrate to
observe the absolute maximum rating (operating temperature). Design a mounting substrate with 4 or
more layers. Connect the back of the package stage and the substrate pad with solder paste. Arrange
thermal via holes on the substrate pad. For detailed information about mount conditions, contact your
sales representative.
Notes on writing to a register containing a status flag
In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a
function, it is important to take care not to accidentally clear the status flag.
Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then
set the control bit to the desired value.
Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit
instructions have only 1-bit access). In such cases, byte, half-word, or word access is used to write to
the control bits and a status flag simultaneously. However, at this time, be careful not to accidentally
clear bits other than the intended ones (the status flag bit in this case).
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S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Note: Bit instructions take this point into account for registers that support bit-band units, so it does not
need to be a concern. You need to take care when using bit instructions for registers that do not
support bit-band units.
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
41
D a t a S h e e t ( P r e l i m i n a r y )
9. BLOCK DIAGRAM
This section provides block diagrams of the S6J3120 series.
Figure 9-1 S6J312AHAA Block Diagram
Trace I/F(8Pin)
Debug I/F (JTAG/SWD)
Power Domain 2
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
Bus Config Group
From/To PPU-SLAVEs
- Bus Performance Counters
- Misc Register Module
DAP
CLK_DBG
CLK_LLPBM2
Security
APB-M
PPU Master
APB-S
AHB-M
CLK_HPM
Debug APB
CLK_HPM
Trace Group
CLK_CPU
CLK_DBG
ATB
CLK_ATB
Core Group (1-Core)
Power Domain 3
Security
Checker
ETB (Trace Buffer)
16KB
CLK_TRC
From/To
CommonPERI#2
From/To
CommonPERI#2
AHB2APB
(Priviledge
Protection)
APB-32
CLK_LLPBM2
Debug APB
CLK_FCLK
CLK_SHE
TCFLASH #0
1MB + 64KB
+
EEFlash #0
112KB
WorkFlash
TCF
AHB-64
AHB-64
(Reg & Data) (Reg)
AHB-64
CLK_MEMC
AXI-64
AHB-32
CLK_SHE
CLK_SHE
TCF
AXI-64
(data)
CLK_MEMC
Flash Group
SHE Group
CLK_CPU
From/To
Memory Config Grp.
ETMTM
#0
TCF
ATCM #0
Procceser
TCRAM #0
(2bank)
64KB
(32KB×2)
AXI-64
- DMAC 16.ch
- ReloadTimer 4ch
CLK_DMA
MPU
#0
AXI-64
CLK_CPU
16KB
16KB
EBI
AXI2AHB
AXI2AHB
CLK_HPM
LLPP
AXI32-M AHB32
AXI-64
CLK_CPU
EBI Group
DDR
HSSPI
D$
#0
I$
#0
AXI-M AXI-S
CLK_CPU
DDRHSSPI Group
DMAC Complex #0
CortexTM -R5
ATCM
#0
AHB-64
CLK_MEMC
From/To
Memory Config Grp.
CPU #0
B0TCM
B1TCM
#0
AXI-32
CLK_CPU
From/To CommonPERI#2
DMAC Config
AHB-32
CLK_HPM2
AHB-32
CLK_CPU
AHB-64
CLK_HPM
AHB-32
CLK_HPM2
AXI-32
CLK_HSSPI
AXI-32
CLK_EXTBUS
High Performance Matrix (HPM)
AXI-64
AXI-64
AHB-32
AHB-32
CLK_HPM
CLK_HPM
System SRAM
16KB
CLK_SYSC1
EAM
CLK_MEMC
CLK_HPM
AHB-32
CLK_CPU
AHB-64
CLK_HPM
From/To
Flash Group
BBU
BBU
AHB-32
CLK_LLPBM
Low Latency Peripheral Bus Matrix (LLPBM)
AHB-32
CLK_LLPBM
AHB-32
BBU
BBU
Power Domain 6_0
CLK_SYSCH0H
System
Controller(SYSC)
BootROM
16KB
SW-Watchdog
CSV(for PLL)
Timing
Protection
(TPU) #0
SYSC1
CLK_SYSC1
State manage
LVD
Fast-CR
Slow-CR
PLL0
SSCG PLL0
CLK_CAN
Wakeup
Request #0
#0 TCM SRAM
(Config)
Memory & Config Group
CLK_MEMC
RTC
CLK_LCP0A
Peripheral
Bus Bridge
C
CLK_LCP1A
Base Timer
30ch
Reload Timer
4ch
M.F.S
5ch
QPRC
2ch
32Bit FRT
6ch
M.F.S
5ch
32Bit ICU
12ch
SMC
4ch
32Bit OCU
12ch
LCDC
32seg×4com
Peripheral
Bus Bridge
CLK_HPM
CRC
4ch
P
Peripheral
Bus Bridge
CLK_LLPBM2
P
Bus Config
Group
(Config)
GPIO
Reload Timer
2ch
DMAC
Complex #0
(Config)
PPU Master
(Cnofig)
12Bit A/DC
Unit0×22ch
Power Domain 3
Reload Timer
4ch
Wakeup-detect
Clock Calibration
CLK_LCP1A
Peripheral
Bus Bridge
RAM
RAM
PONR
CSV
CLK_LLPBM
CLK_LCP0A
CAN-FD
3ch
IRC #0
512 Vectors
CLK_MEMC
EICU 16ch
CAN Prescaler (CLK_CAN)
Backup RAM 4KB
(8+5 bit width RAM x 4)
Power
Domain 4_1
Backup RAM 4KB
(8+5 bit width RAM x 4)
CLK_LCP
Power manage
Source Clock
Timer
CLK_LLPBM
BBU
CLK_LLPBM
Clock manage
CLK_RAM1H
Power CLK_RAM0H
Domain 4_0
Reset manage
AHB-32
Flash Group I/F
Clock divide
and distribution
CLK_COMH
ECC-ed RAM I/F
State manage (2)
From/To
Core-Group
AHB-32
CLK_LLPBM
BBU
Common PERI #1
Group
Common PERI #2
Group
SG
3ch
Common PERI #0
Group
H/W Watchdog
EXT-IRQ
16ch
NMI
MCU Config Group
42
CONFIDENTIAL
Power Domain 1
(Always on)
Common PERI #0
Group
12Bit A/DC
Unit1×28ch
Power Domain 1 (Always on)
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
10. MEMORY MAP
This section explains the memory map.
Figure 10-1 Memory Map
S6J312AHAA
ADDRESS
START
END
group
0x0000_0000
part
TCRAM
0x0000_FFFF
(Main 64KByte)
0x0001_0000
0x007F_FFFF
Reserved
0x0080_0000
0x009E_FFFF
Reserved
0x009F_0000
TCM_FLASH
0x009F_FFFF
(Small Sector 8KByte×8)
0x00AF_FFFF
(Code 1MByte)
0x00A0_0000
TCM_FLASH
Internal area for CR5
0x00B0_0000
0x00DF_FFFF
Complex
Reserved
0x00E0_0000
0x00FF_FFFF
Reserved
0x0100_0000
0x019E_FFFF
Reserved
0x019F_FFFF
(Small Sector 8KByte×8 *Mirror)
0x01AF_FFFF
(Code 1MByte *Mirror)
0x019F_0000
AXI_FLASH_MEMORY
0x01A0_0000
AXI_FLASH_MEMORY
0x01B0_0000
Reserved
0x01DF_FFFF
0x01E0_0000
0x01FF_FFFF
Reserved
0x0200_0000
SYSTEM SRAM
0x0200_3FFF
0x0200_4000
(16KByte)
0x0203_FFFF
Reserved
0x0204_0000
0x027F_FFFF
Reserved
0x0280_0000
0x0280_0FFF
Exclusive Access Memory
0x0280_1000
0x03FF_FFFF
Reserved
0x0400_0000
0x05FF_FFFF
AXI_SLAVE_CORE0
0x0600_0000
Reserved
0x0DFF_FFFF
0x0E00_0000
WORK_FLASH
(112KByte mirror area 1)
0x0E01_BFFF
0x0E01_C000
0x0E0F_FFFF
0x0E10_0000
0x0E1F_FFFF
0x0E20_0000
Shared Flash and memory
area
Reserved
WORK_FLASH
(112KByte mirror area 3)
0x0E21_BFFF
0x0E21_C000
Reserved
0x0E2F_FFFF
Reserved
0x0E30_0000
WORK_FLASH
(112KByte mirror area 4)
0x0E31_BFFF
0x0E31_C000
0x0E3F_FFFF
0x0E40_0000
0x0E7F_FFFF
Reserved
Reserved
0x0E80_0000
Backup RAM
0x0E80_1FFF
8KByte
0x0E80_2000
0x0E80_FFFF
Reserved
0x0E81_0000
0x0E87_FFFF
Reserved
0x0E88_0000
Reserved
0x0FFF_FFFF
0x1000_0000
0x1FFF_FFFF
External bus area
EBI_MEMORY(SRAM/FLASH)
Reserved
Reserved
HSSPI memory area
HSSPI0_MEMORY
Reserved
Reserved
0x2000_0000
0x7FFF_FFFF
0x8000_0000
0x8FFF_FFFF
0x9000_0000
0xAFFF_FFFF
0xB000_0000
0xB483_FFFF
Peri_area
0xB484_0000
0xB484_FFFF
APPS#5
0xB485_0000
Peri area
Peri_area
0xB48B_FFFF
0xB48C_0000
0xB48C_FFFF
APPS#7
0xB48D_0000
0xB7FF_FFFF
Peri_area
0xB800_0000
0xBFFF_FFFF
0xC000_0000
0xFFFE_DFFF
0xFFFE_E000
0xFFFE_FFFF
0xFFFF_0000
0xFFFF_3FFF
0xFFFF_4000
0xFFFF_FFFF
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Reserved
Error Config
BootROM
Reserved
ERRCFG
BootRom
Reserved
43
D a t a S h e e t ( P r e l i m i n a r y )
Only the CPU core can access 0000_0000 ~ 01FF_FFFF. Bus masters other than the CPU core
cannot access the region.
Internal area of CR5 complex (0000_0000 ~ 01FF_FFFF) is mapped to AXI_SLAVE_CORE0. All bus
masters can access to internal area of CR5 complex via AXI_SLAVE_CORE0.
In each of the following memory area combinations, the areas are physically the same memory area.
1. TCM FLASH (0x00A0_0000 -) and AXI FLASH MEMORY (0x01A0_0000 -)
2. TCM FLASH Small Sector (0x009F_0000 -) and AXI FLASH MEMORY Small Sector
(0x019F_0000 -)
3. WORKFLASH (0x0E00_0000 -), WORKFLASH (0x0E20_0000 -), and WORKFLASH
(0x0E30_0000 -)
− The differences between the TCM FLASH and AXI FLASH include the following.
Function
High-speed Access Using Dedicated Bus
Write and Erase
TCM FLASH
AXI FLASH
Applicable
Not applicable
Not applicable
Applicable
(Read-only)
Read
Applicable
Applicable
− The differences between WORKFLASH areas include the following.
Area
Function
WORKFLASH Area 1
Used in write operation (with ECC)
WORKFLASH Area 3
Used in write operation (without ECC)
WORKFLASH Area 4
Used in read operation
− Terms are as follows.
Term
Description
TCM RAM
Main RAM
TCM FLASH
Program FLASH (TCM area)
AXI FLASH
Program FLASH (AXI area)
SYSTEM RAM
System RAM
AXI SLAVE CORE
AXI CPU control area
WORKFLASH
FLASH for work
BACKUP RAM
Backup RAM
This is physically the same as the TCM FLASH.
44
CONFIDENTIAL
EBI MEMORY
Memory for External bus interface
HSSPI0 MEMORY
Memory for DDR HS-SPI
Peri area
Entire area for peripheral functions
APPS#5
Part of area for peripheral functions
APPS#7
Part of area for peripheral functions
ERRCFG
Error configuration area
BootROM
ROM for reset boot
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
S6J312AHAA Peripheral Map
START
Address
END
Address
B000_0000
B010_7FFF
Reserved
B010_0000
B010_03FF
EBI registers
B010_0400
B010_0FFF
Reserved
B010_1000
B010_13FF
DDR_HSSPI
B010_0400
B010_7FFF
Reserved
-
B010_8000
B010_80FF
SystemSRAM
SystemSRAM registers
-
B010_8100
B030_0000
B02F_FFFF
B030_7FFF
SYSC1
Reserved
System Controller #1
-
B030_8000
B03F_FFFF
SYSC1
SWDT
-
B040_0000
B040_7FFF
M EM ORY_CONFIG_GROUP
IRC0
21
B040_8000
B040_FFFF
M EM ORY_CONFIG_GROUP
TPU0
19
B041_0000
B041_0FFF
M EM ORY_CONFIG_GROUP
TCRAM Control Status Register
16
B041_1000
B041_1FFF
M EM ORY_CONFIG_GROUP
TCFlash Control Status Register
17
B041_2000
B041_20FF
M EM ORY_CONFIG_GROUP
WFlash Control Status Register
B041_2100
B04F_FFFF
B050_0000
B05F_FFFF
B060_0000
B060_007F
B060_0080
Group
Function
PPU No
0
1
18
Reserved
-
Reserved
Protection register area
-
M CU_CONFIG_GROUP
B060_00FF
M CU_CONFIG_GROUP
RUN profile register area
-
B060_0100
B060_017F
M CU_CONFIG_GROUP
PSS profile register area
-
B060_0180
B060_01FF
M CU_CONFIG_GROUP
APP profile register area
-
B060_0200
B060_027F
M CU_CONFIG_GROUP
STS profile register area
-
B060_0280
B060_02FF
M CU_CONFIG_GROUP
System register area
-
B060_0300
B060_037F
M CU_CONFIG_GROUP
CSV
-
B060_0380
B060_03FF
M CU_CONFIG_GROUP
RESET
B060_0400
B060_047F
M CU_CONFIG_GROUP
SCT(Fast CR)
34
B060_0480
B060_04FF
M CU_CONFIG_GROUP
SCT(Slow CR)
33
B060_0500
B060_05FF
M CU_CONFIG_GROUP
SCT(M ain clock)
35
B060_0600
B060_067F
M CU_CONFIG_GROUP
Clock System
-
B060_0680
B060_06FF
M CU_CONFIG_GROUP
Special register area
-
B060_0700
B060_07FF
M CU_CONFIG_GROUP
Debug register area
-
B060_0800
B060_BFFF
M CU_CONFIG_GROUP
M ode
-
B060_C000
B060_FFFF
M CU_CONFIG_GROUP
HWDT
B061_0000
B061_7FFF
B061_8000
B061_FFFF
M CU_CONFIG_GROUP
RTC
B062_0000
B063_FFFF
M CU_CONFIG_GROUP
EIC
B064_0000
B065_FFFF
B066_0000
B067_FFFF
B068_0000
B068_7FFF
M CU_CONFIG_GROUP
BURAM IF
B068_8000
B068_83FF
M CU_CONFIG_GROUP
EICU
B068_8400
B068_87FF
M CU_CONFIG_GROUP
CR_Calibration
38
B068_8800
B068_8BFF
M CU_CONFIG_GROUP
IRQ ALL
42
B068_8C00
B068_FFFF
M CU_CONFIG_GROUP
CAN Prescaler
B069_0000
B06F_FFFF
B070_0000
B07F_FFFF
Reserved
-
B080_0000
B0FF_FFFF
Bit RM W alias
BBU for M CU Config (Covers B060_0000 -- B06F_FFFF)
-
B100_0000
B110_0000
B10F_FFFF
B11F_FFFF
Bit RM W alias
Bit RM W alias
BBU for SYSC1 (Covers B030_0000 -- B031_FFFF)
BBU for M EM C (Covers B040_0000 -- B041_FFFF)
-
B120_0000
B1FF_FFFF
Reserved
-
B200_0000
B20F_FFFF
B210_0000
B46F_FFFF
Reserved
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
-
32
-
Reserved
-
Reserved
-
Reserved
SHE
-
37
43
-
SHE configuration registers
Reserved
63
-
45
D a t a S h e e t ( P r e l i m i n a r y )
START
Address
END
Address
Group
Function
B470_0000
B470_3FFF
CommonPERI #2
DM AC #0 registers
B470_4000
B470_FFFF
B471_0000
B471_0FFF
B471_1000
B471_3FFF
B471_4000
B471_4FFF
B471_5000
B471_7FFF
PPU No
64
Reserved
CommonPERI #2
-
M PU for DM AC#0
66
Reserved
CommonPERI #2
-
DM A Complex #0 registers (Additional registers, RLTs)
Reserved
68
-
B471_8000
B471_83FF
CommonPERI #2
CRC#0
70
B471_8400
B471_87FF
CommonPERI #2
CRC#1
71
B471_8800
B471_8BFF
CommonPERI #2
CRC#2
72
B471_8C00
B471_8FFF
CommonPERI #2
CRC#3
73
B471_9000
B473_7FFF
B473_8000
B473_FFFF
CommonPERI #2
GPIO
74
B474_0000
B474_7FFF
CommonPERI #2
PPC
75
B474_8000
B475_0000
B474_FFFF
B475_7FFF
CommonPERI #2
CommonPERI #2
RIC
PPU
-
B475_8000
B478_7FFF
Reserved
-
B478_8000
B478_83FF
CommonPERI #2
Reload Timer ch.32
160
B478_8400
B478_87FF
CommonPERI #2
Reload Timer ch.33
161
B478_8800
B478_FBFF
B478_FC00
B478_FFFF
B479_0000
B47F_FFFF
Reserved
Reserved
CommonPERI #2
-
76
-
M isc registers
Reserved
82
-
B480_0000
B480_03FF
CommonPERI #0
M .F.Serial ch.0
176
B480_0400
B480_07FF
CommonPERI #0
M .F.Serial ch.1
177
B480_0800
B480_0BFF
CommonPERI #0
M .F.Serial ch.2
178
B480_0C00
B480_0FFF
CommonPERI #0
M .F.Serial ch.3
179
B480_1000
B480_13FF
CommonPERI #0
B480_1400
B480_7FFF
M .F.Serial ch.4
Reserved
180
-
B480_8000
B480_83FF
CommonPERI #0
BaseTimer ch.0
88
B480_8400
B480_87FF
CommonPERI #0
BaseTimer ch.1
89
B480_8800
B480_8BFF
CommonPERI #0
BaseTimer ch.2
90
B480_8C00
B480_8FFF
CommonPERI #0
BaseTimer ch.3
91
B480_9000
B480_93FF
CommonPERI #0
BaseTimer ch.4
92
B480_9400
B480_97FF
CommonPERI #0
BaseTimer ch.5
93
B480_9800
B480_9BFF
CommonPERI #0
BaseTimer ch.6
94
B480_9C00
B480_9FFF
CommonPERI #0
BaseTimer ch.7
95
B480_A000
B480_A3FF
CommonPERI #0
BaseTimer ch.8
96
B480_A400
B480_A7FF
CommonPERI #0
BaseTimer ch.9
97
B480_A800
B480_ABFF
CommonPERI #0
BaseTimer ch.10
98
B480_AC00
B480_AFFF
CommonPERI #0
BaseTimer ch.11
99
B480_B000
B480_FFFF
B481_0000
B481_03FF
CommonPERI #0
Reload Timer ch.0
128
B481_0400
B481_07FF
CommonPERI #0
Reload Timer ch.1
129
Reserved
-
B481_0800
B481_0BFF
CommonPERI #0
Reload Timer ch.2
130
B481_0C00
B481_0FFF
CommonPERI #0
Reload Timer ch.3
131
B481_1000
B481_FFFF
B482_0000
B482_03FF
CommonPERI #0
FRT ch.0
208
B482_0400
B482_07FF
CommonPERI #0
FRT ch.1
209
Reserved
-
B482_0800
B482_0BFF
CommonPERI #0
FRT ch.2
210
B482_0C00
B482_0FFF
CommonPERI #0
FRT ch.3
211
B482_1000
B482_13FF
CommonPERI #0
FRT ch.4
212
B482_1400
B482_17FF
CommonPERI #0
FRT ch.5
213
B482_1800
B482_7FFF
B482_8000
B482_83FF
CommonPERI #0
ICU ch.0 / ch1
224
B482_8400
B482_87FF
CommonPERI #0
ICU ch.2 / ch3
225
Reserved
-
B482_8800
B482_8BFF
CommonPERI #0
ICU ch.4 / ch5
226
B482_8C00
B482_8FFF
CommonPERI #0
ICU ch.6 / ch7
227
B482_9000
B482_93FF
CommonPERI #0
ICU ch.8 / ch9
228
B482_9400
B482_97FF
CommonPERI #0
ICU ch.10 / ch11
229
B482_9800
B482_FFFF
46
CONFIDENTIAL
Reserved
-
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
START
Address
END
Address
Group
Function
B483_0000
B483_03FF
CommonPERI #0
OCU ch.0 / ch1
240
B483_0400
B483_07FF
CommonPERI #0
OCU ch.2 / ch3
241
242
PPU No
B483_0800
B483_0BFF
CommonPERI #0
OCU ch.4 / ch5
B483_0C00
B483_0FFF
CommonPERI #0
OCU ch.6 / ch7
243
B483_1000
B483_13FF
CommonPERI #0
OCU ch.8 / ch9
244
B483_1400
B483_17FF
CommonPERI #0
OCU ch.10 / ch11
B483_1800
B483_FBFF
Reserved
245
-
B483_FC00
B483_FFFF
Common PERI #0
M isc registers
B484_0000
B484_FFFF
APPS #5
APPS#5 area
-
80
Reserved
-
B485_0000
B487_FFFF
B488_0000
B488_03FF
CommonPERI #1
M .F.Serial ch.8
184
B488_0400
B488_07FF
CommonPERI #1
M .F.Serial ch.9
185
B488_0800
B488_0BFF
CommonPERI #1
M .F.Serial ch.10
186
B488_0C00
B488_0FFF
CommonPERI #1
M .F.Serial ch.11
187
B488_1000
B488_13FF
CommonPERI #1
B488_1400
B488_FFFF
M .F.Serial ch.12
Reserved
188
-
B489_0000
B489_03FF
CommonPERI #1
Reload Timer ch.16
144
B489_0400
B489_07FF
CommonPERI #1
Reload Timer ch.17
145
B489_0800
B489_0BFF
CommonPERI #1
Reload Timer ch.18
146
B489_0C00
B489_0FFF
CommonPERI #1
Reload Timer ch.19
147
B489_1000
B489_7FFF
B489_8000
B489_83FF
CommonPERI #1
QPRC ch.8
200
B489_8400
B489_87FF
CommonPERI #1
QPRC ch.9
201
Reserved
-
B489_8800
B48B_0FFF
Reserved
-
B48B_1000
B48B_FBFF
Reserved
-
B48B_FC00
B48B_FFFF
CommonPERI #1
M isc registers
B48C_0000
B48C_FFFF
APPS #7
APPS#7 area
-
Reserved
-
81
B48D_0000
B48F_FFFF
B490_0000
B490_FFFF
CommonPERI #0
CAN_FD ch0
256
B491_0000
B491_FFFF
CommonPERI #0
CAN_FD ch1
257
CommonPERI #0
CAN_FD ch2
Bit RM W alias
Reserved
BBU for CommonPERI#0 (Covers B490_0000 -- B497_FFFF)
-
B492_0000
B492_FFFF
B493_0000
B4C0_0000
B4BF_FFFF
B4FF_FFFF
B500_0000
B5FF_FFFF
Reserved
-
B600_0000
B700_0000
B780_0000
B7C0_0000
B6FF_FFFF
B77F_FFFF
B7BF_FFFF
B7FF_FFFF
Reserved
BBU alias for CommonPERI#2 (Covers B470_0000 -- B47F_FFFF)
BBU alias for CommonPERI#0 (Covers B480_0000 -- B487_FFFF)
BBU alias for CommonPERI#1 (Covers B488_0000 -- B48F_FFFF)
-
B800_0000
FFFE_DFFF
Reserved
-
FFFE_E000
FFFE_FBFC
Error Config
IRC
FFFE_FC00
FFFE_FFFF
Error Config
BootROM I/F
Bit RM W alias
Bit RM W alias
Bit RM W alias
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
258
20
47
D a t a S h e e t ( P r e l i m i n a r y )
- APPS#5 area
START
Address
B484_0000
B484_0400
B484_0800
B484_0C00
B484_3800
B484_3C00
B484_4000
B484_4400
B484_4800
B484_4C00
B484_5000
B484_5400
B484_5800
B484_5C00
B484_6000
B484_6400
B484_6800
B484_6C00
B484_7000
B484_7400
B484_7800
B484_7C00
B484_8000
B484_8400
B484_8800
B484_8C00
END
Address
B484_03FF
B484_07FF
B484_0BFF
B484_37FF
B484_3BFF
B484_3FFF
B484_43FF
B484_47FF
B484_4BFF
B484_4FFF
B484_53FF
B484_57FF
B484_5BFF
B484_5FFF
B484_63FF
B484_67FF
B484_6BFF
B484_6FFF
B484_73FF
B484_77FF
B484_7BFF
B484_7FFF
B484_83FF
B484_87FF
B484_8BFF
B484_FFFF
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
Function
Sound Generator ch.0
Sound Generator ch.1
Sound Generator ch.2
Reserved
BaseTimer ch.12
BaseTimer ch.13
BaseTimer ch.14
BaseTimer ch.15
BaseTimer ch.16
BaseTimer ch.17
BaseTimer ch.18
BaseTimer ch.19
BaseTimer ch.20
BaseTimer ch.21
BaseTimer ch.22
BaseTimer ch.23
BaseTimer ch.24
BaseTimer ch.25
BaseTimer ch.26
BaseTimer ch.27
BaseTimer ch.28
BaseTimer ch.29
A/D unit0
A/D unit1
A/D analog input control
Reserved
PPU No
264
265
266
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
-
Function
Reserved
Stepper M otor Control ch.0
Stepper M otor Control ch.1
Stepper M otor Control ch.2
Stepper M otor Control ch.3
Reserved
SM C Trigger Generator
Liquid Crystal Display Controller
Liquid Crystal Display input/output control
Reserved
PPU No
316
317
318
319
322
323
324
-
- APPS#7 area
START
Address
B48C_0000
B48C_4000
B48C_4400
B48C_4800
B48C_4C00
B48C_5000
B48C_5800
B48C_5C00
B48C_6000
B48C_6400
48
CONFIDENTIAL
END
Address
B48C_3FFF
B48C_43FF
B48C_47FF
B48C_4BFF
B48C_4FFF
B48C_57FF
B48C_5BFF
B48C_5FFF
B48C_63FF
B48C_FFFF
APPS #7
APPS #7
APPS #7
APPS #7
APPS #7
APPS #7
APPS #7
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
11. PIN STATUSES IN CPU STATUS
Table 11-1 Pin state table (1/2)
2
3
4
5
6
7
8
P000/SOT2_1/AIN8_0/MAD00/SEG8
P001/SCS20_1/BIN8_0/MDATA15/SEG9
P003/SCS22_1/ZIN8_0/MDATA14/SEG10
P005/SIN3_0/IN6_0/AIN9_0/MDATA13/SEG11
P006/SOT3_0/IN7_0/BIN9_0/MDATA12/SEG12
P007/SCK3_0/IN8_0/ZIN9_0/MDATA11/SEG13
P008/SCS30_0/IN9_0/TIOA0_0/MDATA10/SEG14
9
P009/INT0_1/SIN11_0/IN10_0/TIOA1_0/MDATA09/SEG15
10
11
12
13
14
15
16
P010/SOT11_0/IN11_0/TIOA2_0/MDATA08/SEG16
P012/SCK11_0/OUT5_0/TIOA3_0/MOEX/SEG17
P013/SCS110_0/OUT6_0/TIOA4_0/MWEX/SEG18
P015/SCS111_0/OUT7_0/TIOA5_0/MCSX0/SEG19
P016/SCS112_0/OUT8_0/TIOA6_0/MCSX1/SEG20
P017/SCS113_0/OUT9_0/TIOA7_0/MDQM0/SEG21
P018/OUT10_0/TIOA8_0/MDQM1/SEG22
Hi-Z/Input blocked
Hi-Z/
Last
status
retained
Hi-Z/
Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Status
immediately
before the
shutdown retaine
*6
Last state
retained
*3
*6
Output
"L"/
Input
blocked
Output "L"/
Input blocked
Output "L"/
Input blocked
Hi-Z/Input blocked
Hi-Z/
Last
status
retained
Hi-Z/
Input
blocked
Hi-Z/
Input blocked
Hi-Z/
Input blocked
Status
immediately
before the
shutdown retaine
Last state
retained
*3
P023/SCS0_0/SIN4_1/TIOB4_0/MAD16/SEG24/ST1
P024/SOT4_1/TIOB5_0/MAD17/SEG25/ST2
P027/SCS42_1/TEXT0_1/TIOB6_0/TIOA4_1/MAD18/SEG26/ST3
P028/SIN1_0/OUT0_1/TIOB7_0/MAD19/SEG27/ST4
P029/SOT1_0/OUT1_1/MAD20/SEG28/ST5
P030/SCS43_1/OUT2_1/TIOB8_0/MAD21/SEG29/ST6
P031/SCS1_0/OUT3_1/MAD22/SEG30/ST7
P100/SCK1_0/OUT4_1/MAD23/SEG31/ST8
P101/AN3/OUT5_1/MDATA07
P103/AN5/OUT6_1/TIOB9_0/MDATA06
P105/OUT7_1/TIOA9_0/MDATA05
P106/TX1_2/OUT8_1/TIN0/MDATA04
P107/INT2_1/RX1_2/OUT9_1/TIOA10_0/TOT0/MDATA03
Output
"L"/
Last
status
retained
Output
"L"/
Input
blocked
Output "L"/
Input blocked
Output "L"/
Input blocked
Status
immediately
before the
shutdown retaine
*6
Last state
retained
*3
*6
Output "L"/Input blocked
Last state
retained
With control
47 P118/INT5_1/AN13/TIOB12_0/TOT16
48
49
50
51
52
53
54
55
P119/AN14/SCS90_0/TIOB13_0/TIN17
P120/AN15/SCS91_0/TOT17
P122/AN17/SCS92_0/TIOA11_1/SGA0_0
P123/AN18/SCS93_0/TIOA12_1/SGO0_0
P126/AN19/SGA1_0
P127/AN20/TEXT1_1/SGO1_0
P128/AN21/TEXT2_1/SGA2_0
P129/AN22/IN6_1/SGO2_0
56 P130/INT5_0/AN23/SIN9_0/IN7_1
57 P131/AN24/SOT9_0/IN8_1
58 P202/INT6_1/SCK9_0/IN9_1
59
60
61
62
P203/IN10_1/TIOB19_0/AIN8_1
P204/AN27/IN11_1/TIOB20_0/BIN8_1
P205/AN28/TEXT3_1/TIOB21_0/ZIN8_1
P206/AN29/SCS43_0/TEXT4_1/TIOB22_0
63 P207/INT7_1/AN30/SCK4_0/TEXT5_1/SPISEL3
64 P208/AN31/SCS42_0/TIOA19_0/SPISEL2
65 P209/AN32/SOT4_0/TIOA20_0/SPISEL1
66 P210/INT6_0/AN33/SIN4_0/IN0_2/TIOA21_0/SPICLK
67 P211/AN34/SCS40_0/IN1_2/TIOA22_0/SPIDAT0
68 P212/AN35/SCS41_0/SCS80_1/IN2_2/TIOA13_1/SPIDAT2
69 P213/INT8_1/SIN8_1/IN3_2/TIOA14_1/SPIDAT1
70 P214/SOT8_1/IN4_2/TIOA15_1/SPISEL0
71 P215/INT9_1/SCK8_1/IN5_2/TIOA16_1/SPIDAT3
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
Hi-Z/Input
blocked
*1
Hi-Z/Input blocked
Hi-Z/
Last
status
retained
Hi-Z/
Input
blocked
Hi-Z/
Input blocked
Hi-Z/
Input blocked
Status
immediately
before the
shutdown retaine
Last state
retained
*3
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*6
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Timer mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
CPU Sleep mode
Internal Reset Factor
*2
After internal reset
issuance (Before GPORT
setting)
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
Internal reset
issuance in
progress
Stop mode *4
Output "L"/Input blocked
20 P022/INT3_0/SIN0_0/TIOB3_0
P109/OUT11_1/TIOA12_0/TOT1/MCLK
P112/AN9/TIOA13_0/TIN2/MDATA02
P113/TIOA5_1/TOT2/MDATA01
P114/AN10/TIOA6_1/TIN3/MDATA00
P115/TIOB10_0/TOT3
P117/INT4_1/AN12/TIOB11_0/TIN16
Sleep mode
Hi-Z/Input
blocked
*6
Last state
retained
*3
*6
Hi-Z/Input
blocked
*6
19 P021/SCK0_0/SCK4_1/TIOB2_0
35
39
40
41
45
46
External Reset
Factor 3
Output
"L"/
Last
status
retained
18 P020/SOT0_0/TEXT1_0/TIOB1_0
34 P108/INT3_1/AN6/OUT10_1/TIOA11_0/TIN1/MRDY
After external
factor
releasing
Hi-Z/Input
blocked
*6
17 P019/TEXT0_0/OUT11_0/TIOB0_0/MAD15/SEG23/ST0
21
22
23
24
25
26
27
28
29
30
31
32
33
External Reset Factor 2
External factor
generation in
progress
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
GPORTEN
Control
After external
factor
releasing
Internal reset
issuance in
progress
Pin Name
Internal reset
issuance in
progress
Pin No.
External
factor
generation in
progress
Before internal
reset issuance
External Reset Factor 1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*6
Last state
retained
*3
Last state
retained
*3
*6
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
49
D a t a S h e e t ( P r e l i m i n a r y )
Table 11-2 Pin state table (2/2)
74 P218/AN36/TEXT2_0/TIOB14_0
75 P219/AN37/TEXT3_0/TIOB15_0
76 P220/AN38/TX2_0/SCS83_0/IN6_2/TIOB16_0
78 P223/AN40/SCS81_0/IN8_2/AIN9_1
79 P224/AN41/TX0_2/SCS80_0/IN9_2/BIN9_1
80 P225/INT0_0/AN42/RX0_2/SOT8_0/IN10_2/TIOB17_0/ZIN9_1
81 P226/AN43/SCK8_0/IN11_2/TIOA17_1
87 P229/INT8_0/AN46/RX0_1/OUT0_0/TIOA25_0/PWM1P0
P230/AN47/OUT1_0/TIOA26_0/PWM1M0
P231/AN48/OUT2_0/TIOA27_0/PWM2P0
P300/AN49/OUT3_0/TIOA28_0/PWM2M0
P301/AN50/OUT4_0/TIOA18_1/PWM1P1
P302/AN51/TIOA19_1/PWM1M1
P304/AN52/TEXT4_0/TIOA20_1/PWM2P1
P305/AN53/TEXT5_0/TIOA29_0/PWM2M1
With control
Hi-Z/Input blocked
Hi-Z/
Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Status
immediately
Last state
before the
retained
shutdown retaine
Last state
retained
*3
98 P308/AN56/IN0_1/TIOA28_1/PWM1M2
99 P309/AN57/IN1_1/TIOA29_1/PWM2P2
100 P312/AN58/SCS101_0/IN2_1/TIOB25_0/PWM2M2
101 P313/INT10_1/AN59/SOT10_0/IN3_1/TIOB26_0/PWM1P3
102 P314/AN60/SCK10_0/IN4_1/TIOB27_0/TIOA7_1/PWM1M3
103 P315/AN61/TX1_1/SCS100_0/IN5_1/TIOB28_0/TIOA8_1/PWM2P3
104 P317/INT11_1/AN62/RX1_1/SIN10_0/TIOB29_0/TIOA9_1/PWM2M3
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Pull-up
(Hi-Z
*5)
Pull-up
(Last state
retained
*3
*5)
Pull-up
(Hi-Z
*5)
Input enabled
(Last state
retained
*3
*5)
Input enabled
(Hi-Z/Input
blocked
*5)
Input enabled
(Last state
retained
*3
*5)
Input enabled
(Hi-Z/Input
blocked
*5)
Input enabled
Input enabled
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
-
With control
Hi-Z/Input blocked
Hi-Z
/Last
Hi-Z/Input
status
blocked
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
-
Input enabled
Input enabled
Input enabled
Input enabled
With control
Status
immediately
Last state
before the
retained
shutdown retaine
Input enabled
Last state
retained
*3
Hi-Z/Input
blocked
Input enabled
Last state
retained
*3
Hi-Z/Input
blocked
Input enabled
-
Hi-Z/Input blocked
132 P406/TX2_1/SOT12_0/TRACEDATA3/MAD12/COM0/SGO2_1
133 P407/SCK12_0/SCK10_1/TRACEDATA4/MAD11/COM1
Output "L"/Input blocked
134 P408/SIN2_0/TRACEDATA5/TIN18/MAD10/COM2
135 P409/SOT2_0/TIOA24_1/TRACEDATA6/TOT18/MAD09/COM3
Status
immediately
Last state
before the
retained
shutdown retaine
Input enabled
Input enabled
Hi-Z
/Last
status
retained
Hi-Z
/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Status
immediately
before the
shutdown retaine
Last state
retained
*3
Output
"L"/
Last
status
retained
Output
"L"/
Input
blocked
Output "L"/
Input blocked
Last state
retained
*3
Output "L"/
Input blocked
Last state
retained
With control
Status
immediately
before the
shutdown retaine
*6
138 P414/SCS21_0/TIN32/MAD06/SEG2
139 P416/SIN10_1/IN5_0/TIOA22_1/TOT32/MAD05/SEG3
140 P417/INT15_1/SOT10_1/TIOA23_1/TIN33/MAD04/SEG4
Hi-Z/Input blocked
Hi-Z
/Last
status
retained
Hi-Z
/Input
blocked
Hi-Z
/Input blocked
Hi-Z
/Input blocked
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
137 P413/INT14_1/SCS20_0/SCS103_1/TOT19/MAD07/SEG1
CONFIDENTIAL
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
(Last state
retained
*3
*5)
131 P405/INT11_0/RX2_1/SIN12_0/IN4_0/TRACEDATA2/MAD13/V0/SGA2_1
50
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Input enabled
129 P403/IN2_0/TRACEDATA0/V2/SGA1_1
130 P404/SCS120_0/IN3_0/TRACEDATA1/MAD14/V1/SGO1_1
143 P421/INT12_1/SIN2_1/TRACECTL/MAD01/SEG7
Hi-Z/Input
blocked
Input enabled
Input enabled
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Input enabled
-
Input
enabled
(Last
state
retained
*5)
Input
enabled
Last state
retained
*3
Hi-Z/Input
blocked
*1
Input enabled
-
128 P402/INT2_0/RX1_0/IN1_0/V3
142 P420/SCK2_1/TRACECLK/MAD02/SEG6
Hi-Z/Input
blocked
*1
Input enabled
-
127 P401/TX1_0/IN0_0
141 P418/INT14_0/SCS22_0/TIOB23_0/TOT33/MAD03/SEG5
Hi-Z/Input
blocked
*1
Input enabled
-
-
122 P400/MCSX2/SGO0_1
136 P411/INT13_1/SCK2_0/SCS101_1/TIOB24_0/TRACEDATA7/TIN19/MAD08/SEG0
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
121 P331/MCSX3/SGA0_1
123 RSTX
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
113 TMS
114 TCK
NMIX
MD
X0
X1
Hi-Z/Input
blocked
Pull-up
112 TDI/P324
116
117
118
119
Pull-up
(Last
state
retained
*5)
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Pull-up
107 P321
115 P327/WOT
Pull-up
(Status
immediately
before the
shutdown retaine
*5)
Input enabled
(Status
immediately
before the
shutdown retaine
*5)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
97 P307/INT1_0/AN55/RX0_0/SCS102_0/TIOB18_0/PWM1P2
110 TRST/P322
111 TDO/P323
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Hi-Z/Input
blocked
77 P222/INT7_0/AN39/RX2_0/SIN8_0/IN7_2
88
89
90
91
92
93
94
Timer mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
When High Impedance
Enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Stop mode *4
High impedance
disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
Sleep mode
CPU Sleep mode
Internal Reset Factor
*2
After internal reset
issuance (Before GPORT
setting)
External Reset
Factor 3
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
After external
factor
releasing
Internal reset
issuance in
progress
External Reset Factor 2
External factor
generation in
progress
Internal reset
issuance in
progress
After internal reset
issuance (Before GPORT
setting)
Internal reset
issuance in
progress
GPORTEN
Control
Internal reset
issuance in
progress
Pin No.
Pin Name
After external
factor
releasing
Before internal
reset issuance
External Reset Factor 1
External
factor
generation in
progress
Last state
retained
*3
*6
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
Last state
retained
*3
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*1
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*1
*6
Hi-Z/Input
blocked
*1
*6
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*1
*6
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*1
*6
Last state
retained
*3
*6
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*1
*6
Hi-Z/Input
blocked
*6
Hi-Z/Input
blocked
*1
*6
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
*1: Input disable is not valid when external interrupts are enabled.
*2: Recovery from standby (power off) becomes a factor.
*3: The pin state from the time that HOLDIO_PD2 was set (SYSC0_SPECFGR.HOLDIO_PD2=1) is retained. If
power-off has not occurred and HOLDIO_PD2 has not been set (SYSC0_SPECFGR.HOLDIO_PD2=0), the last
state is retained.
*4: To power off power domains 2 and 3, be sure to set HOLDIO_PD2 (SYSC0_SPECFGR.HOLDIO_PD2=1).
*5: The pin state when the PORT function is enabled is shown.
*6: When Port is used as LCD setting, PIN state becomes the following.
Power Domain 2
control
mode
-
Main oscillation
enable setting
PIN state
Power-off
Power-on
Except PSS Main oscillation
PSS Main oscillation
Timer mode
Timer mode
-
-
Output "L" /
Output "L" /
Input blocked
Input blocked
enable (LCR0:LCEN=1)
Retention of LCD display
disable (LCR0:LCEN=0)
Output "L" /
Input blocked
-External Reset Factor 1
Power-on reset (PONR)
RAM retention low-voltage detection reset (RVD)
Internal power supply low-voltage detection reset (LVDL1R)
RSTX pin + MD pin simultaneous assert reset (INITX)
-External Reset Factor 2
RSTX pin input reset (RSTX)
-External Reset Factor 3
Hardware watchdog reset (HWDR)
Software watchdog reset (SWDR)
PLL clock supervisor reset (CSVPRn)
SSCG clock supervisor reset (CSVSRn)
Profile error reset (PRFERR)
Software trigger hard reset (SHRST)
Software reset (SRST)
-Internal Reset Factor
Standby transition reset/ Power domain reset
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
51
D a t a S h e e t ( P r e l i m i n a r y )
12. ELECTRICAL CHARACTERISTICS
12.1 Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
*1, *2
Analog supply voltage
*1
Analog reference voltage
Input voltage*1
Analog pin input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp current
"L"-level maximum output current*3
"L"-level average output current*4
"L"-level total output current*5
"H"-level maximum output current
"H"-level average output current*4
"H"-level total output current*5
*3
Rating
Unit
Max
VCC
VSS-0.3
VSS+6.0
V
DVCC
VSS-0.3
VSS+6.0
V
DVCC=VCC
AVCC
VSS-0.3
VSS+6.0
V
AVCC≤VCC
AVRH≤AVCC
AVRH
VSS-0.3
VSS+6.0
V
VI1
VSS-0.3
VCC+0.3
V
VI2
DVSS-0.3
DVCC+0.3
V
VIA1
VSS-0.3
VCC+0.3
V
VIA2
DVSS-0.3
DVCC+0.3
V
VO1
VSS-0.3
VCC+0.3
V
VO2
DVSS-0.3
DVCC+0.3
V
ICLAMP
-
4
mA
SMC shared pin
SMC shared pin
SMC shared pin
*8
Σ|ICLAMP |
-
20
mA
*8
IOL1
-
3.5
mA
When setting is 1 mA*6
IOL2
-
7
mA
When setting is 2 mA
IOL3
-
40
mA
When setting is 30 mA*7
IOLAV1
-
1
mA
When setting is 1 mA*6
IOLAV2
-
2
mA
When setting is 2 mA
IOLAV3
-
30
mA
When setting is 30 mA*7
ΣIOL1
-
40
mA
*6
ΣIOL2
-
150
mA
*7
IOH1
-
-3.5
mA
When setting is 1 mA*6
IOH2
-
-7
mA
When setting is 2 mA
IOH3
-
-40
mA
When setting is 30 mA*7
IOHAV1
-
-1
mA
When setting is 1 mA*6
IOHAV2
-
-2
mA
When setting is 2 mA
IOHAV3
-
-30
mA
When setting is 30 mA*7
ΣIOH1
-
-40
mA
*6
ΣIOH2
-
-150
mA
*7
Power consumption
PD
-
2000
mW
Operating temperature
TA
-40
+105
°C
Tstg
-55
+150
°C
Storage temperature
Remarks
Min
S6J312AHAA*9
*1: These parameters are based on the condition that VSS=DVSS=AVSS=0.0V.
*2: VCC and DVCC must be set to the same voltage. Caution must be taken that AVCC and DVCC does
not exceed VCC upon power-on and under other circumstances.
*3: The maximum output current is defined as the value of the peak current flowing through any one of
the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of
the corresponding pins for a 10 ms period. The average value is the operation current X the operation
ratio.
52
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
*5: The total output current is defined as the maximum current value flowing through all of corresponding
pins.
*6: Corresponding pins: general-purpose ports
*7: Corresponding pins: P229 to P231, P300 to P302, P304 to P305, P307 to P309, P312 to P315, P317
*8: Corresponding pins: All general-purpose ports and analog input pins.
−
Use the device within the recommended operating conditions.
−
Use the device with direct voltage (current).
−
The + B signal should always be applied by connecting a limiting resistor between the + B
signal and the microcontroller.
−
The value of the limiting resistor should be set so that the current input to the microcontroller
pin does not exceed rated values at any time regardless of instantaneously or constantly when
the + B signal is input.
−
Note that when the microcontroller drive current is low, such as in the low-power consumption
modes, the + B input potential can increase the potential at the VCC pin via a protective diode,
possibly affecting other devices.
−
Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the
power is supplied through the pin, the microcontroller may operate incompletely.
−
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the
power-on reset may not function in the power supply voltage.
−
Do not leave + B input pins open.
*9: It is standard when four-layer substrate is used.
Example of a recommended circuit
S6J3120 series
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed
any of these ratings.
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
53
D a t a S h e e t ( P r e l i m i n a r y )
12.2 Recommended operating conditions
(VSS=DVSS=AVSS=0.0 V)
Parameter
Supply voltage
Smoothing capacitor*
Operating temperature
Symbol
Rating
Min
Unit
Max
VCC
4.5
5.5
V
DVCC
4.5
5.5
V
AVCC
4.5
5.5
V
VCC
3.5
5.5
V
DVCC
3.5
5.5
V
AVCC
3.5
5.5
Recommended operation assurance range
Operation assurance range
V
4.7
CS1
Remarks
µF
Tolerance of up to ±40%, 126pin
CS2
100
1000
pF
38pin
TA
-40
+105
°C
S6J312AHAA
*: For the connections of smoothing capacitor CS1, CS2, see the following diagram.
· C pin connection diagram
C(126pin)
CS1
VSS
VSS
C(38pin)
AVSS
CS2
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device
and could result in device failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on
this data sheet. If you are considering application under any conditions other than listed herein, please
contact sales representatives beforehand.
54
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.3 DC characteristics
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0.7×VCC
-
VCC+0.3
V
0.7×DVCC
-
DVCC+0.3
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"H" level
input voltage
VIH1
P126 to P131,
CMOS
P202 to P215,
Schmitt
P218 to P220,
P222 to P226,
P327, P331,
input level
selected
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
P312 to P315, P317
August 7, 2014, S6J312A_DS708-00005-0v01-E
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55
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0.8×VCC
-
VCC+0.3
V
0.8×DVCC
-
DVCC+0.3
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
VIH2
P202 to P215,
P218 to P220,
P222 to P226,
"H" level
Automotive
input level
selected
P327 to P331
input voltage
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
P312 to P315, P317
VIH4
RSTX, NMIX
-
0.7×VCC
-
VCC+0.3
V
VIH5
MD
-
0.7×VCC
-
VCC+0.3
V
2.0
-
VCC+0.3
V
VIH6
56
CONFIDENTIAL
TRST, TCK, TDI,
TMS
TTL input
level
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
Vss-0.3
-
0.3×VCC
V
DVss-0.3
-
0.3×DVCC
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
"L" level
input voltage
VIL1
P126 to P131,
CMOS
P202 to P215,
Schmitt
P218 to P220,
P222 to P226,
P327 to P331,
input level
selected
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
P312 to P315, P317
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
Vss-0.3
-
0.5×VCC
V
DVss-0.3
-
0.5×DVCC
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
VIL2
P202 to P215,
P218 to P220,
P222 to P226,
"L" level
Automotive
input level
selected
P327, P331
input voltage
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
P312 to P315, P317
VIL4
RSTX, NMIX
-
Vss-0.3
-
0.3×VCC
V
VIL5
MD
-
Vss-0.3
-
0.3×VCC
V
Vss-0.3
-
0.8
V
VIL6
58
CONFIDENTIAL
TRST, TCK, TDI,
TMS
TTL input
level
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
Vcc-0.5
-
Vcc
V
DVcc-0.5
-
DVcc
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
"H" level
output
voltage
VOH1
Vcc=4.5 V
IOH=-2.0 mA
P218 to P220,
P222 to P226,
P321 to P324,
P327, P331,
P400 to P401,
P403 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
DVcc=4.5 V
IOH=-2.0 mA
P312 to P315, P317
August 7, 2014, S6J312A_DS708-00005-0v01-E
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59
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
Vcc-0.5
-
Vcc
V
DVcc-0.5
-
DVcc
V
DVcc-0.5
-
DVcc
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
"H" level
output
VOH2
voltage
Vcc=4.5 V
IOH=-1.0 mA
P218 to P220,
P222 to P226,
P321 to P324,
P327, P331,
P400 to P401,
P403 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
DVcc=4.5 V
IOH=-1.0 mA
P312 to P315, P317
P229 to P231,
"H" level
output
voltage
VOH3
P300 to P302,
DVcc=4.5 V
P304 to P305,
IOH=-30.0
P307 to P309,
mA
P312 to P315, P317
60
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0
-
0.4
V
0
-
0.4
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
"L" level
output
voltage
VOL1
Vcc=4.5 V
IOL=2.0 mA
P218 to P220,
P222 to P226,
P321 to P324,
P327, P331,
P400 to P401
P403 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
DVcc=4.5 V
IOL=2.0 mA
P312 to P315, P317
August 7, 2014, S6J312A_DS708-00005-0v01-E
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61
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0
-
0.4
V
0
-
0.4
V
0
-
0.55
V
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
"L" level
output
VOL2
voltage
Vcc=4.5 V
IOL=1.0 mA
P218 to P220,
P222 to P226,
P321 to P324,
P327, P331,
P400 to P401
P403 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P229 to P231,
P300 to P302,
P304 to P305,
P307 to P309,
DVcc=4.5 V
IOL=1.0 mA
P312 to P315, P317
P229 to P231,
P300 to P302,
"L" level
output
voltage
VOL3
P304 to P305,
P307 to P309,
DVcc=4.5 V
IOL=30.0 mA
P312 to P315, P317
62
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Input leakage
current
Symbol
Pin Name
IIL
All input pins
RUP1
RSTX, NMIX
Conditions
VCC=DVCC=AVCC=5.5 V
VSS < VI < VCC
-
Value
Unit
Min
Typ
Max
-5
-
+5
µA
25
-
100
kΩ
25
-
100
kΩ
25
-
100
kΩ
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
Pull-up
RUP2
P202 to P215,
P218 to P220,
P222 to P226,
P229 to P231,
P300 to P302,
resistor
Pull-up resistor
selected
P304 to P305,
P307 to P309,
P312 to P315, P317
P327, P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
P321,
RUP3
TDI(P324), TMS,
-
TCK
August 7, 2014, S6J312A_DS708-00005-0v01-E
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63
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
25
-
100
kΩ
-
25
-
100
kΩ
-
-
5
15
pF
Remarks
P000 to P001, P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101, P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
Pull-down
RDOWN1
P202 to P215,
P218 to P220,
P222 to P226,
P229 to P231,
P300 to P302,
resistor
Pull-down resistor
selected
P304 to P305,
P307 to P309,
P312 to P315, P317
P327, P331,
P400 to P409, P411,
P413 to P414,
P416 to P418,
P420 to P421
RDOWN2
TRST(P322)
Pins other than
Input
capacitance
CIN
VCC, VSS,
AVCC0, AVCC1,
AVSS0, AVSS1
64
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin
Name
Conditions
Normal operation
ICC5
Flash
write/erase
Power
supply
current
S6J312AH
AA
Value
Unit
Remarks
225
mA
Operating at 112 MHz
125
255
mA
Operating at 112 MHz
Operating at 112 MHz
Min
Typ
Max
-
100
-
ICCS5
CPU Sleep
-
60
160
mA
ICCT5
Timer mode
-
480
1450
µA
-
1340
2525
µA
-
480
1450
µA
-
40
115
µA
-
700
885
µA
-
40
110
µA
Timer mode
ICCT5M
VCC
ICCH5
ICCT52
(Main OSC)
Stop mode
Timer mode
(Shutdown)
Timer mode
ICCT52M
(Main OSC)
(Shut down)
ICCH52
Stop mode
(Shutdown)
TA=25°C
Slow-CR source Oscillation
TA=25°C
Main source Oscillation*
TA=25°C
TA=25°C
Slow-CR source Oscillation
TA=25°C
Main source Oscillation*
TA=25°C
Refer to Hardware manual "APPENDIX State transition" for Internal clock frequency setting / Setting of the power domain /
Regulator setting.
*: The external load capacitance connected to X0/X1 is considerd as 10pF.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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65
D a t a S h e e t ( P r e l i m i n a r y )
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
High current
PWM1Pn,
Output drive
PWM1Mn,
Capacity
ΔVOH3
PWM2Mn
deviation1
(n=0 to 3)
High current
PWM1Pn,
Output drive
PWM1Mn,
ΔVOL3
PWM2Mn
Deviation2
(n=0 to 3)
LCD divider
resistor
COM0 to COM3
output impedance
SEG00 to SEG31
output impedance
Unit
Remarks
Min
Typ
Max
-
-
90
mV
*
-
-
90
mV
*
-
6.25
12.5
25
kΩ
-
-
-
4.5
kΩ
-
-
-
17
kΩ
TA=25°C
-0.5
-
+0.5
µA
IOH=-30.0mA
Maximum
deviation of VOH3
DVCC=4.5V
IOH=-30.0mA
PWM2Pn,
Phase to phase
Value
DVCC=4.5V
PWM2Pn,
Phase to phase
Capacity
Conditions
Maximum
deviation of VOL3
V0 to V1,
RLCD
V1 to V2,
V2 to V3
RVCOM
RVSEG
COMm
(m=0 to 3)
SEGn
(n=00 to 31)
V0 to V3,
LCDC leak
current
COMm
ILCDC
(m=0 to 3)
SEGn
(n=00 to 31)
*: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of VOH3/VOL3 for
each pin is defined. Same for other channels.
66
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4 AC characteristics
12.4.1
Source clock timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Source oscillation clock
frequency
Source oscillation clock
cycle time
CAN PLL jitter
(during lock)
Built-in slow-CR
oscillation frequency
Built-in fast-CR
oscillation frequency
PLL input clock
frequency
PLL macro oscillation
clock frequency
SSCG-PLL input clock
frequency
SSCG-PLL macro
oscillation clock
frequency
Value
Pin
Cond
Name
itions
Min
Typ
Max
FC
X0, X1
-
-
4
-
MHz
tCYL
X0, X1
-
-
250
-
ns
tPJ
-
-
-10
-
+10
ns
FCRS
-
-
50
100
150
kHz
FCRF
-
-
2.4
4
6.0
MHz
FPLLI
-
-
-
4
-
MHz
FPLLO
-
-
400
-
512
MHz
FSSCGPLLI
-
-
-
4
-
MHz
FSSCGPLLO
-
-
400
-
512
MHz
Symbol
Unit
Remarks
*
*: The maximum/minimum values have been standardized with the main clock and PLL clock in use.
−
X0 and X1 clock timing
tCYL
X0
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
67
D a t a S h e e t ( P r e l i m i n a r y )
−
CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
t1
t2
t3
tn-1
tn
Ideal clock
Slow
PLL output
t1
t2
t3
tn-1
tn
Fast
68
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4.2
Parameter
Internal clock timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Symbol
Pin Name
Conditions
FCD0_CLK
-
FCLK_CPU
-
FCLK_FCLK
FCLK_ATB
S6J312AHAA Value
Unit
Remarks
Min
Typ
Max
-
-
-
112
MHz
CD0_CLK
-
-
-
112
MHz
CLK_CPU
-
-
-
-
56
MHz
CLK_FCLK
-
-
-
-
56
MHz
CLK_ATB
FCLK_DBG
-
-
-
-
56
MHz
CLK_DBG
FCLK_HPM
-
-
-
-
28
MHz
CLK_HPM
FCLK_HPM2
-
-
-
-
14
MHz
CLK_HPM2
FCLK_DMA
-
-
-
-
28
MHz
CLK_DMA
FCLK_MEMC
-
-
-
-
28
MHz
CLK_MEMC
FCLK_EXTBUS
-
-
-
-
25
MHz
CLK_EXTBUS
FCLK_SYSC1
-
-
-
-
28
MHz
CLK_SYSC1
FCLK_HAPP0A0
-
-
-
-
28
MHz
CLK_HAPP0A0
FCLK_HAPP0A1
-
-
-
-
28
MHz
CLK_HAPP0A1
FCLK_HAPP1B0
-
-
-
-
28
MHz
CLK_HAPP1B0
FCLK_HAPP1B1
-
-
-
-
28
MHz
CLK_HAPP1B1
FCLK_LLPBM
-
-
-
-
112
MHz
CLK_LLPBM
Internal
FCLK_LLPBM2
-
-
-
-
56
MHz
CLK_LLPBM2
clock
FCLK_LCP
-
-
-
-
56
MHz
CLK_LCP
frequency
FCLK_LCP0
-
-
-
-
28
MHz
CLK_LCP0
FCLK_LCP0A
-
-
-
-
28
MHz
CLK_LCP0A
FCLK_LCP1
-
-
-
-
28
MHz
CLK_LCP1
FCLK_LCP1A
-
-
-
-
28
MHz
CLK_LCP1A
FCLK_LAPP0
-
-
-
-
28
MHz
CLK_LAPP0
FCLK_LAPP0A
-
-
-
-
28
MHz
CLK_LAPP0A
FCLK_LAPP1
-
-
-
-
28
MHz
CLK_LAPP1
FCLK_LAPP1A
-
-
-
-
28
MHz
CLK_LAPP1A
FCLK_TRC
-
-
-
-
56
MHz
CLK_TRC
FCLK_HSSPI
-
-
-
-
28
MHz
CLK_HSSPI
FCLK_SYSC0H
-
-
-
-
28
MHz
CLK_SYSC0H
FCLK_COMH
-
-
-
-
28
MHz
CLK_COMH
FCLK_RAM0H
-
-
-
-
28
MHz
CLK_RAM0H
FCLK_RAM1H
-
-
-
-
28
MHz
CLK_RAM1H
FCLK_SYSC0P
-
-
-
-
28
MHz
CLK_SYSC0P
FCLK_COMP
-
-
-
-
28
MHz
CLK_COMP
FCANFD_CCLK
-
-
-
-
40
MHz
CANFD_CCLK
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
69
D a t a S h e e t ( P r e l i m i n a r y )
Parameter
Symbol
tCD0_CLK
Pin Name
Conditions
-
-
S6J312AHAA Value
Min
Typ
Max
8.93
-
-
Unit
ns
Remarks
CD0_CLK
tCLK_CPU
-
-
8.93
-
-
ns
CLK_CPU
tCLK_FLASH
-
-
17.86
-
-
ns
CLK_FCLK
tCLK_ATB
-
-
17.86
-
-
ns
CLK_ATB
tCLK_DBG
-
-
17.86
-
-
ns
CLK_DBG
tCLK_HPM
-
-
35.72
-
-
ns
CLK_HPM
tCLK_HPM2
-
-
71.43
-
-
ns
CLK_HPM2
tCLK_FMA
-
-
35.72
-
-
ns
CLK_DMA
tCLK_MEMC
-
-
35.72
-
-
ns
CLK_MEMC
tCLK_EXTBUS
-
-
40.00
-
-
ns
CLK_EXTBUS
tCLK_SYSC1
-
-
35.72
-
-
ns
CLK_SYSC1
tCLK_HAPP0A0
-
-
35.72
-
-
ns
CLK_HAPP0A0
tCLK_HAPP0A1
-
-
35.72
-
-
ns
CLK_HAPP0A1
tCLK_HAPP1B0
-
-
35.72
-
-
ns
CLK_HAPP1B0
tCLK_HAPP1B1
-
-
35.72
-
-
ns
CLK_HAPP1B1
tCLK_LLPBM
-
-
8.93
-
-
ns
CLK_LLPBM
Internal
tCLK_LLPBM2
-
-
17.86
-
-
ns
CLK_LLPBM2
clock
tCLK_LCP
-
-
17.86
-
-
ns
CLK_LCP
cycle time
tCLK_LCP0
-
-
35.72
-
-
ns
CLK_LCP0
tCLK_LCP0A
-
-
35.72
-
-
ns
CLK_LCP0A
tCLK_LCP1
-
-
35.72
-
-
ns
CLK_LCP1
tCLK_LCP1A
-
-
35.72
-
-
ns
CLK_LCP1A
70
CONFIDENTIAL
tCLK_LAPP0
-
-
35.72
-
-
ns
CLK_LAPP0
tCLK_LAPP0A
-
-
35.72
-
-
ns
CLK_LAPP0A
tCLK_LAPP1
-
-
35.72
-
-
ns
CLK_LAPP1
tCLK_LAPP1A
-
-
35.72
-
-
ns
CLK_LAPP1A
tCLK_TRC
-
-
17.86
-
-
ns
CLK_TRC
tCLK_HSSPI
-
-
35.72
-
-
ns
CLK_HSSPI
tCLK_SYSC0H
-
-
35.72
-
-
ns
CLK_SYSC0H
tCLK_COMH
-
-
35.72
-
-
ns
CLK_COMH
tCLK_RAM0H
-
-
35.72
-
-
ns
CLK_RAM0H
tCLK_RAM1H
-
-
35.72
-
-
ns
CLK_RAM1H
tCLK_SYSC0P
-
-
35.72
-
-
ns
CLK_SYSC0P
tCLK_COMP
-
-
35.72
-
-
ns
CLK_COMP
tCANFD_CCLK
-
-
25.00
-
-
ns
CANFD_CCLK
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D a t a S h e e t ( P r e l i m i n a r y )
−
Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
3.5
2
4
112
Internal clock frequency FCDO_CLK(MHz)
Note: A supply voltage that is equal to or less than the set voltage for low-voltage detection causes a reset.
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Relationship between the oscillation clock frequency and internal clock frequency
Oscillation Clock
Frequency
−
Main Clock
PLL Multiplier
PLL Output Division
Setting
Setting
PLL Clock
4 MHz
4 MHz
112
4
112 MHz
4 MHz
4 MHz
120
6
80 MHz
Oscillation circuit example
X0
X1
R
C1
C2
Notes:
· When configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator manufacturers
for the design.
· The maximum PLL clock frequency must be 112MHz.
Output division configuration can be set by the following.
- PLLDIVM bit in SYSC0_RUNPLL0CNTR register
- PLLDIVM bit in SYSC0_PSSPLL0CNTR register
- SSCGDIVM bit in SYSC0_RUNSSCG0CNTR0 register
- SSCGDIVM bit in SYSC0_PSSSSCG0CNTR0 register
(e.g. If PLLout is 448MHz, these settings must be configured as "multiply by 4" and over multiplication setting)
AC characteristics are specified by the following measurement reference voltage values.
−
Input signal waveform
Hysteresis input pin (Automotive)
−
Output signal waveform
Output pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis input pin (CMOS Schmitt)
0.7Vcc
0.3Vcc
Hysteresis input pin (TTL)
2.0V
0.8V
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12.4.3
Reset input
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
Reset
input time
Width for reset
tRSTL
RSTX
Value
Unit
Min
Max
10
-
µs
1
-
µs
Remarks
-
input removal
tRSTL
RSTX
0.2Vcc
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12.4.4
Power-on conditions
Parameter
Symbol
Level detection
voltage
Level detection
hysteresis width
Level detection time
Pin
Name
(TA: Recommended operating conditions, VSS=0.0 V)
Conditions
Value
Min
Typ
Max
Unit
Remarks
-
VCC
-
2.25
2.45
2.65
V
-
VCC
-
-
100
-
mV
-
-
-
-
-
30
μs
*1
-
-
4
mV/µs
*2
50
-
-
ms
*3
VCC = at
level
Slope detection
-
undetected standard
VCC
detection
release level
time
Power off time
-
VCC
-
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the
possibility to generate or release after the power supply voltage has exceeded the detection voltage
range.
*2: When setting the power supply fluctuation to less than this standard, "Level detection time" can be
longer than the maximum standard defined in this table. This is the standard when the power supply
fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
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12.4.5
Clock output timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
Symbol
Pin Name
Cycle time
tCYC
MCLK
Clock high width *1
tCHCL
MCLK
Conditions
2mA is
Value
Unit
Min
Max
40
-
ns
dHtcyc - 7
dHtcyc + 7
ns
dLtcyc - 7
dLtcyc + 7
ns
Remarks
selected in
ODR bit in
PPC_PCFGR
Clock low width *2
tCLCH
MCLK
register.
*1: If division-ratio is even value, dH is equivalent to 0.5.
Otherwise, dH is calculated as the following.
dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429.
*2: If division-ratio is even value, dL is equivalent to 0.5.
Otherwise, dL is calculated as the following.
dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571.
−
Clock output timing
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12.4.6 External bus interface timing
12.4.6.1 Common timing between read and write
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
Cycle time
(without MRDY)
Cycle time
(with MRDY)
Symbol
Pin Name
tCYC
tCYC
Value
Unit
Min
Max
MCLK
40
-
ns
MCLK
50
-
ns
Remarks
If using MRDY,
2mA is selected in
tCSO
Address delay time
tAO
MCLK,
PPC_PCFGR register.
MCSX0 to MCSX3
MCLK,
MAD00 to MAD23
RDY setup time
tRDYS
MCLK, MRDY
RDY hold time
tRDYH
MCLK, MRDY
"CMOS Schmitt input"
and "Disable noise
filter" are selected in
PPC_PCFGR register.
set MCLK to
20MHz or less.
ODR bit in
CS delay time
−
Conditions
0.5
18
ns
0.5
18
ns
21
-
ns
0
-
ns
External bus I/F common timing
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12.4.6.2 Read timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Max
21+tcyc
-
ns
0
-
ns
0.5
18
ns
Remarks
MOEX,
Data setup time
Data hold time
tDSR
tDHR
MDATA00 to
"CMOS Schmitt input"
MDATA15
and "Disable noise
MOEX,
filter" are selected in
MDATA00 to
PPC_PCFGR register.
MDATA15
2mA is selected in
MOEX delay time
tRDO
MCLK, MOEX
ODR bit in
PPC_PCFGR register.
−
External bus I/F read timing
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12.4.6.3 Write timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
MWEX delay time
Byte mask delay
time
Data delay time
Symbol
Pin Name
tWEO
MCLK, MWEX
tWRO
tDO
Conditions
MCLK,
MDQM0 to MDQM1
Value
Unit
Min
Max
0.5
18
ns
0.5
18
ns
0.5
18
ns
-
18
ns
Remarks
2mA is selected in
MCLK,
ODR bit in
MDATA00 to
PPC_PCFGR register.
MDATA15
Data delay time
(Hi-Z output)
−
MCLK,
tDOZ
MDATA00 to
MDATA15
External bus I/F write timing
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12.4.7 Multi-function serial
12.4.7.1 CSIO timing (SMR:MD[2:0]=010B)
(5-1-1) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect
level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Serial clock
Symbol
tSCYC
cycle time
SCK ↓ → SOT
tSLOVI
delay time
Pin Name
SCK0 to SCK4,
SCK8 to SCK12
Master
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
(CL=50pF,
SOT8 to SOT12
Valid SIN → SCK ↑
setup time
SCK ↑→ Valid SIN
hold time
Serial clock
tIVSHI
tSHIXI
tSHSL
"H" pulse width
Serial clock
tSLSH
"L" pulse width
SCK ↓→ SOT
tSLOVE
delay time
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
Valid SIN → SCK ↑
setup time
SCK ↑ → Valid SIN
hold time
tIVSHE
tSHIXE
SCK fall time
tF
SCK rise time
tR
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
Max
4tCLK_LCPnA*
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCPnA* +10
-
ns
2tCLK_LCPnA* -10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
IOL=-2mA,
Remarks
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK8 to SCK12
SOT8 to SOT12
Unit
Min
mode
SCK0 to SCK4,
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
Value
Conditions
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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tSCYC
SCK
VOH
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
tR
VIH
tIVSHE
tSHIXE
tSLOVE
VOH
VOL
VIH
VIL
VIH
VIL
Slave mode
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D a t a S h e e t ( P r e l i m i n a r y )
(5-1-2) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect
level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
tSCYC
cycle time
SCK ↑ → SOT
tSHOVI
delay time
Pin Name
SCK0 to SCK4,
SCK8 to SCK12
Master
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
mode
SOT8 to SOT12
Valid SIN → SCK ↓
tIVSLI
setup time
SCK ↓ → Valid SIN
tSLIXI
hold time
Serial clock
tSHSL
"H" pulse width
Serial clock
tSLSH
"L" pulse width
SCK ↑ → SOT
tSHOVE
delay time
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
tIVSLE
setup time
SCK ↓ → Valid SIN
tSLIXE
hold time
SCK fall time
tF
SCK rise time
tR
(CL=50pF,
IOL=-2mA,
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
Unit
Min
Max
4tCLK_LCPnA*
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCPnA* +10
-
ns
2tCLK_LCPnA* -10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Remarks
IOL=-1mA,
IOH=1mA)
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
Value
IOH=2mA),
(CL=20pF,
SCK0 to SCK4,
SOT8 to SOT12
Valid SIN → SCK ↓
Conditions
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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tSCYC
VOH
SCK
VOL
tSHOVI
VO
VOL
SOT
tIVSLI
tSLIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
SCK
VIL
tR
SOT
VIH
tSLSH
VIH
tF
tSHOVE
VIL
VOH
VOL
tIVSLE
SIN
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
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(5-1-3) SPI supported (SCR:SPI=1), and serial clock output signal detect level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Serial clock
Symbol
tSCYC
cycle time
SCK ↑ → SOT
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
SOT → SCK ↓
delay time
Value
Conditions
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
Master
SOT8 to SOT12
(CL=50pF,
tIVSLI
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
IOL=-2mA,
tSLIXI
SIN8 to SIN12
tSOVLI
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
tSHOVI
delay time
Pin Name
Unit
Min
Max
4tCLK_LCPnA*
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCPnA* -30
-
ns
tCLK_LCPnA* +10
-
ns
2tCLK_LCPnA* -10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
mode
IOH=2mA),
(CL=20pF,
IOL=-1mA,
Remarks
IOH=1mA)
SOT8 to SOT12
Serial clock
tSHSL
"H" pulse width
Serial clock
tSLSH
"L" pulse width
SCK ↑ → SOT
tSHOVE
delay time
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
SOT8 to SOT12
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
tIVSLE
tSLIXE
SCK fall time
tF
SCK rise time
tR
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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tSCYC
SCK
VOH
VOL
tSOVLI
VOL
tSHO
VOH
VOL
SOT
VOH
VOL
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
SCK
SIN
VIL
tF
*
SOT
VIL
tR
VIH
VIH
tSHOV
VOH
VOL
VIL
VO
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
* Changes when writing to the TDR
Slave mode
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(5-1-4) SPI supported (SCR:SPI=1), and serial clock output signal detect level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
tSCYC
cycle time
SCK ↓ → SOT
Valid SIN → SCK ↑
setup time
SCK ↑→ Valid SIN
hold time
SOT → SCK ↑
delay time
Conditions
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
Master
SOT8 to SOT12
(CL=50pF,
tIVSHI
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
IOL=-2mA,
tSHIXI
SIN8 to SIN12
tSOVHI
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
tSLOVI
delay time
Pin Name
mode
IOH=2mA),
(CL=20pF,
IOL=-1mA,
Value
Unit
Min
Max
4tCLK_LCPnA*
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCPnA* -30
-
ns
tCLK_LCPnA* +10
-
ns
2tCLK_LCPnA* -10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Remarks
IOH=1mA)
SOT8 to SOT12
Serial clock
tSHSL
"H" pulse width
Serial clock
tSLSH
"L" pulse width
SCK ↓ → SOT
tSLOVE
delay time
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12,
SOT0 to SOT4,
SOT8 to SOT12
Valid SIN → SCK ↑
tIVSHE
setup time
SCK ↑ → Valid SIN
tSHIXE
hold time
SCK fall time
tF
SCK rise time
tR
SCK0 to SCK4,
SCK8 to SCK12,
SIN0 to SIN4,
SIN8 to SIN12
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK4,
SCK8 to SCK12
SCK0 to SCK4,
SCK8 to SCK12
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
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tSCYC
VOH
VOH
SCK
VOL
tSOVH
tSLOVI
VOH
VOL
SOT
VOH
VOL
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIL
tR
*
SOT
VIH
tF
VOH
VOL
VIL
VIL
VIH
tSLO
VOH
VOL
tSHIXE
tIVSHE
SIN
VIH
VIH
VIL
VIH
VIL
* Changes when writing to the TDR
Slave mode
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D a t a S h e e t ( P r e l i m i n a r y )
(5-1-5) Serial chip select used (SCSCR:CSEN=1)
 Mark level "H" of serial clock output (SMR, SCSFR:SCINV=0)
 Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↓ → SCK ↓
tCSSI
setup time
SCK ↑ → SCS ↑
tCSHI
hold time
Pin Name
Conditions
SCK0 to SCK4,
Master
SCK8 to SCK12,
mode
SCS0x to SCS4x,
(CL=50pF,
SCS8x to SCS12x
IOL=-2mA,
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
-
ns
-
ns
-
ns
-
40
ns
0
-
ns
Remarks
IOH=2mA),
SCS
tCSDI
deselect time
SCS0x to SCS4x,
(CL=20pF,
tCSDS*3-50
SCS8x to SCS12x
IOL=-1mA,
+5tCLK_LCPnA*4
IOH=1mA)
SCS ↓ → SCK ↓
tCSSE
setup time
SCK ↑ → SCS ↑
tCSHE
hold time
SCS
tCSDE
deselect time
SCS ↓ → SOT
tDSE
delay time
SCS ↑ → SOT
tDEE
delay time
3tCLK_LCPnA*4
SCK0 to SCK4,
SCK8 to SCK12,
Slave
+30
SCS0x to SCS4x,
mode
SCS8x to SCS12x
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
3tCLK_LCPnA*4
SCS8x to SCS12x
IOH=2mA),
+30
SCS0x to SCS4x,
(CL=20pF,
SCS8x to SCS12x,
IOL=-1mA,
SOT0 to SOT4,
IOH=1mA)
SOT8 to SOT12
0
Master
mode
round
SCK ↓ → SCS ↓
clock switching
tSCC
time
SCK0 to SCK4,
operation
SCK8 to SCK12,
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
SCS8x to SCS12x
IOH=2mA),
3tCLK_LCPnA*4 +0
3tCLK_LCPnA*4
+50
ns
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
*4 tCLK_LCPnA
n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
SCS
VOH
VOL
tCSSI
SCK
VOL
tCSHI
VOH
tCSDI
VOH
VOL
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
VIL
tCSDE
tCSHE
VIL
tCSSE
SCK input
VIH t
DEE
VIL
SOT
(Normal
synchronous
transfer)
VOL
tDSE
SOT
(SPI compatible)
VIH
VOH
VOL
Slave mode
SCSx
tSCC
SCSy output
SCK output
VOL
VOL
Clock switching example by master mode round operation
(x,y=0,1,2,3,4,8,9,10,11,12: x and y are different value)
88
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
(5-1-6) Serial chip select used (SCSCR:CSEN=1)
 Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
 Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↓→ SCK ↑
tCSSI
setup time
SCK ↓→ SCS ↑
tCSHI
hold time
Pin Name
Conditions
Master
SCK0 to SCK4,
SCK8 to SCK12,
SCS0x to SCS4x,
SCS8x to SCS12x
mode
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
-
ns
-
ns
-
ns
-
40
ns
0
-
ns
Remarks
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
SCS
tCSDI
deselect time
SCS ↓ → SCK ↑
tCSSE
setup time
SCK ↓ → SCS ↑
tCSHE
hold time
SCS
tCSDE
deselect time
SCS ↓ → SOT
tDSE
delay time
SCS ↑ → SOT
tDEE
delay time
SCS0x to SCS4x,
IOL=-1mA,
tCSDS*3-50+5
SCS8x to SCS12x
IOH=1mA)
tCLK_LCPnA*4
3tCLK_LCPnA*4
SCK0 to SCK4,
+30
SCK8 to SCK12,
Slave
SCS0x to SCS4x,
mode
SCS8x to SCS12x
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
3tCLK_LCPnA*4
SCS8x to SCS12x
IOH=2mA),
+30
SCS0x to SCS4x,
(CL=20pF,
SCS8x to SCS12x,
IOL=-1mA,
SOT0 to SOT4,
IOH=1mA)
SOT8 to SOT12
0
Master
mode
round
SCK ↑ → SCS ↓
clock switching
tSCC
time
SCK0 to SCK4,
operation
SCK8 to SCK12,
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
SCS8x to SCS12x
IOH=2mA),
3tCLK_LCPnA*4 +0
3tCLK_LCPnA*4
+50
ns
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
*4 tCLK_LCPnA
n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
SCS output
VOH
VOL
tCSH
VOL
tCSSI
VOH
SCK output
VOH
tCSD
I
VOL
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
SCK input
SOT
(Normal
synchronous
transfer)
SOT
(SPI compatible)
VIH
VIL
tCSDE
tCSHE
VIL
tCSSE
VIL
VIH
tDEE
VOL
tDSE
VOH
VOL
Slave mode
90
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
SCSx output
tSCC
SCSy output
VOL
VOH
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2,3,4,8,9,10,11,12: x and y are different value)
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
(5-1-7) Serial chip select used (SCSCR:CSEN=1)
 Serial clock output signal detect level "H" (SMR, SCSFR:SCINV=0)
 Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
SCS ↑ → SCK ↓
setup time
SCK ↑ → SCS ↓
hold time
Symbol
tCSSI
tCSHI
Pin Name
Conditions
SCK0 to SCK4,
Master
SCK8 to SCK12,
mode
SCS0x to SCS4x,
(CL=50pF,
SCS8x to SCS12x
IOL=-2mA,
Value
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
-
ns
-
ns
-
ns
-
40
ns
0
-
ns
Remarks
IOH=2mA),
SCS
deselect time
tCSDI
SCS0x to SCS4x,
(CL=20pF,
tCSDS*3-50+5
SCS8x to SCS12x
IOL=-1mA,
tCLK_LCPnA*4
IOH=1mA)
SCS ↑ → SCK ↓
setup time
SCK ↑ → SCS ↓
hold time
SCS
deselect time
SCS ↑ → SOT
delay time
SCS ↓ → SOT
delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
3tCLK_LCPnA*4
SCK0 to SCK4,
SCK8 to SCK12,
Slave
+30
SCS0x to SCS4x,
mode
SCS8x to SCS12x
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
3tCLK_LCPnA*4
SCS8x to SCS12x
IOH=2mA),
+30
SCS0x to SCS4x,
(CL=20pF,
SCS8x to SCS12x,
IOL=-1mA,
SOT0 to SOT4,
IOH=1mA)
SOT8 to SOT12
0
Master
mode
round
SCK ↓ → SCS ↑
clock switching
tSCC
time
SCK0 to SCK4,
operation
SCK8 to SCK12,
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
SCS8x to SCS12x
3tCLK_LCPnA*4 +0
3tCLK_LCPnA*4
+50
ns
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
*4 tCLK_LCPnA
92
CONFIDENTIAL
n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual
August 7, 2014, S6J312A_DS708-00005-0v01-E
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93
D a t a S h e e t ( P r e l i m i n a r y )
(5-1-8) Serial chip select used (SCSCR:CSEN=1)
 Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
 Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
SCS ↑ → SCK ↑
setup time
SCK ↓ → SCS ↓
hold time
Symbol
tCSSI
tCSHI
Value
Pin Name
Conditions
SCK0 to SCK4,
Master
SCK8 to SCK12,
mode
SCS0x to SCS4x,
(CL=50pF,
SCS8x to SCS12x
IOL=-2mA,
SCS0x to SCS4x,
(CL=20pF,
tCSDS*3-50+5
SCS8x to SCS12x
IOL=-1mA,
tCLK_LCPnA*4
Unit
Min
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_LCPnA*4+30
-
ns
0
-
ns
3tCLK_LCPnA*4+30
-
ns
-
40
ns
0
-
ns
Remarks
IOH=2mA),
SCS
deselect time
tCSDI
IOH=1mA)
SCS ↑ → SCK ↑
setup time
SCK ↓ → SCS ↓
hold time
SCS
deselect time
SCS ↑ → SOT
delay time
SCS ↓ → SOT
delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
SCK0 to SCK4,
SCK8 to SCK12,
Slave
SCS0x to SCS4x,
mode
SCS8x to SCS12x
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
SCS8x to SCS12x
IOH=2mA),
SCS0x to SCS4x,
(CL=20pF,
SCS8x to SCS12x,
IOL=-1mA,
SOT0 to SOT4,
IOH=1mA)
SOT8 to SOT12
Master
mode
round
SCK ↑ → SCS ↑
clock switching
tSCC
time
SCK0 to SCK4,
operation
SCK8 to SCK12,
(CL=50pF,
SCS0x to SCS4x,
IOL=-2mA,
SCS8x to SCS12x
IOH=2mA),
3tCLK_LCPnA*4+0
3tCLK_LCPnA*4
+50
ns
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1: tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the hardware manual.
*4 tCLK_LCPnA
94
CONFIDENTIAL
n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
August 7, 2014, S6J312A_DS708-00005-0v01-E
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D a t a S h e e t ( P r e l i m i n a r y )
SCS output
tCSDI
VOH
VOH
VOH
SCK output
VOL
tCSHI
tCSSI
VOL
SOT
(Normal synchronous transfer)
SOT
(SPI compatible)
Master mode
tCSDE
SCS input
VIH
VIH
SCK input
VIL
SOT
(Normal
synchronous
transfer)
tDEE
VOL
tDSE
SOT
(SPI compatible)
VIL
tCSHE
tCSSE
VOH
VOL
Slave mode
tSCC
SCSx
VOH
SCSy output
SCK output
VOH
Clock switching example by master mode round operation
(x,y=0,1,2,3,4,8,9,10,11,12: x and y are different value)
96
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4.7.2
UART (Async Serial Interface) timing
(SMR:MD[2:0]=000B, 001B)
(5-2-1) External clock selected (BGR:EXT=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
Pin Name
tSLSH
"L" pulse width
Serial clock
tSHSL
"H" pulse width
SCK fall time
tF
SCK rise time
tR
Value
Conditions
(CL=50pF,
IOL=-2mA,
SCK0 to SCK4,
IOH=2mA),
SCK8 to SCK12
Unit
Min
Max
tCLK_LCPnA* +10
-
ns
tCLK_LCPnA* +10
-
ns
-
5
ns
-
5
ns
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Remarks
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
tR
SCK
VIL
tF
tSHSL
VIH
VIH
tSLSH
VIL
VIL
VIH
External clock selected
August 7, 2014, S6J312A_DS708-00005-0v01-E
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97
D a t a S h e e t ( P r e l i m i n a r y )
12.4.7.3 LIN interface (v2.1) (LIN communication control interface (v2.1))
timing (SMR:MD[2:0]=011B)
(5-3-1) External clock selected (BGR:EXT=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Serial clock
"L" pulse width
Serial clock
"H" pulse width
Symbol
Pin Name
Conditions
tSLSH
tSHSL
SCK fall time
tF
SCK rise time
tR
(CL=50pF,
IOL=-2mA,
SCK0 to SCK4,
SCK8 to SCK12
IOH=2mA),
Value
Unit
Min
Max
tCLK_LCPnA*+10
-
ns
tCLK_LCPnA*+10
-
ns
-
5
ns
-
5
ns
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Remarks
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
tR
SCK
VIL
tF
tSHSL
VIH
VIH
VIL
tSLSH
VIL
VIH
External clock selected
98
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4.8 HS-SPI timing
12.4.8.1 SDR mode timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
Symbol
Pin Name
Cycle time
tCYCM
Clock high width
Clock low width
Conditions
Value
Unit
Min
Max
SPICLK
62.5
-
ns
tCWH
SPICLK
0.5tCYCM – 4
-
ns
tCWL
SPICLK
0.5tCYCM – 4
-
ns
2mA is selected in
SPICLK start time
tOSLSKSDR
(mode0 / mode4)
SPISEL0 to
PPC_PCFGR
1.5tCYCM – 15
-
ns
register.
setting value of
SS2CD bit is
01B
SPISEL3
SPICLK end →
Invalid SPISEL time
SPICLK,
Slave mode is
not supported.
Minimum
ODR bit in
Valid SPISEL →
Remarks
tOSKSLSDR
tCYCM – 10
-
ns
-10
10
ns
14
-
ns
0.5tCYCM
-
ns
0
-
ns
(mode0 / mode4)
SPICLK,
SPIDAT output time
tOSDATSDR
SPIDAT0 to
SPIDAT3
SPIDAT setup
SPIDAT hold
(mode0)
SPIDAT hold
(mode4)
"CMOS Schmitt
tDSSETSDR
SPICLK,
tSDHOLDSDR0
SPIDAT0 to
SPIDAT3
tSDHOLDSDR4
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
input" and "Disable
noise filter" are
selected in
PPC_PCFGR
register.
99
D a t a S h e e t ( P r e l i m i n a r y )
−
SPI-I/F SDR mode 0 timing
−
SPI-I/F SDR mode 4 timing
100
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4.8.2 DDR mode timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
(External load capacitance 16pF)
Parameter
Symbol
Pin Name
Cycle time
tCYCM
Clock high width
Clock low width
Conditions
Value
Unit
Min
Max
SPICLK
62.5
-
ns
tCWH
SPICLK
0.5tCYCM – 4
-
ns
tCWL
SPICLK
0.5tCYCM – 4
-
ns
2mA is selected in
ODR bit in
Valid SPISEL →
SPICLK start time
tOSLSKDDR
(mode0)
SPISEL0 to
PPC_PCFGR
register.
SPISEL3
SPICLK end →
Invalid SPISEL time
SPICLK,
SPICLK,
SPIDAT output time
tOSDATDDR
SPIDAT0 to
SPIDAT3
SPIDAT setup
"CMOS Schmitt
tDSSETDDR
SPICLK,
SPIDAT hold
(mode0)
SPIDAT0 to
tSDHOLDDDR
1.75tCYCM –
15
SPIDAT3
input" and "Disable
-
ns
setting value of
SS2CD bit is
01B
10
(mode0)
Slave mode is
not supported.
Minimum
0.75tCYCM –
tOSKSLDDR
Remarks
-
ns
0.25tCYCM –
0.25tCYCM +
10
10
14
-
ns
0
-
ns
ns
noise filter" are
selected in
PPC_PCFGR
register.
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
101
D a t a S h e e t ( P r e l i m i n a r y )
−
SPI-I/F DDR mode 0 timing
102
CONFIDENTIAL
S6J312A_DS708-00005-0v01-E, August 7, 2014
D a t a S h e e t ( P r e l i m i n a r y )
12.4.9
High current output slew rate
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Value
Parameter
Symbol
Pin Name
Conditions
Min
Typ
Max
15
-
100
Unit
Remarks
P229 to P231,
P300 to P302,
Output rise / fall time
tR2,
P304 to P305,
tF2
P307 to P309,
-
ns
load capacitance
85pF
P312 to P315,
P317
−
Slew rate output timing
VH
VL
VH
VL
VH=VOL2+0.9 × (VOH2-VOL2)
VL=VOL2+0.1 × (VOH2-VOL2)
t R2
August 7, 2014, S6J312A_DS708-00005-0v01-E
CONFIDENTIAL
t F2
103
D a t a S h e e t ( P r e l i m i n a r y )
12.5 Timer input timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
TIN0 to TIN3,
tTWH,
tTWL
TIN32 to TIN33
-
IN0 to IN11
-
TEXT0 to 5
-
TIOA0 to TIOA29
100
4tCLK_LLPBM2
100
4tCLK_LCP0A
100
4tCLK_LCP0A
100
4tCLK_LCP0A
-
TIOB0 to TIOB29
Min
4tCLK_LCPnA*
-
TIN16 to TIN19
Input pulse width
Value
Conditions
100
Max
Unit
-
ns
-
ns
-
ns
-
ns
-
ns
Remarks
4tCLK_LCPnA* ≥100 ns
4tCLK_LCPnA* <100 ns
4tCLK_LLPBM2 ≥100 ns
4tCLK_LLPBM2 <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
*: n=0:ch.0 to ch.3, n=1:ch.16 to ch.19
−
Timer input timing
TINx
INx
TEXTx
TIOAx,TIOBx
104
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tTIWH
VIH
tTIWL
VIH
VIL
VIL
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12.6 QPRC timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Conditions
AIN pin "H" width
tAHL
AIN8 to AIN9
-
AIN pin "L" width
tALL
AIN8 to AIN9
-
BIN pin "H" width
tBHL
BIN8 to BIN9
-
BIN pin "L" width
tBLL
BIN8 to BIN9
-
Time from AIN pin "H" level
to BIN rise
Time from BIN pin "H" level
to AIN fall
Time from AIN pin "L" level
to BIN fall
Time from BIN pin "L" level
to AIN rise
Time from BIN pin "H" level
to AIN rise
Time from AIN pin "H" level
to BIN fall
Time from BIN pin "L" level
to AIN fall
Time from AIN pin "L" level
to BIN rise
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
ZIN pin "H" width
tZHL
ZIN pin "L" width
tZLL
Time from determined ZIN level
to AIN/BIN rise and fall
Time from AIN/BIN rise and fall time
to determined ZIN level
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
AIN8 to AIN9,
BIN8 to BIN9
Min
Max
4tCLK_LCP1A
-
Unit
Remarks
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
ns
4tCLK_LCP1A
≥ 100 ns
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
ZIN8 to ZIN9
QCR:CGSC="0"
ZIN8 to ZIN9
QCR:CGSC="0"
AIN8 to AIN9,
tZABE
BIN8 to BIN9,
QCR:CGSC="1"
ZIN8 to ZIN9
AIN8 to AIN9,
tABEZ
August 7, 2014, S6J312A_DS708-00005-0v01-E
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AIN8 to AIN9,
Value
BIN8 to BIN9,
QCR:CGSC="1"
ZIN8 to ZIN9
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tALL
tAHL
AIN
tADBD
tBUAD
tAUBU
tBDAU
BIN
tBHL
tBLL
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
106
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tALL
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D a t a S h e e t ( P r e l i m i n a r y )
tZHL
ZIN
tZLL
ZIN
tABEZ
tZABE
AIN/BIN
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12.7 Trigger input timing
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin Name
Conditions
INT0 to INT15
RX0 to RX2
INT0 to INT15
RX0 to RX2
−
Value
Unit
Min
Max
-
100
-
ns
-
5tCLK_LLPBM2
-
ns
-
1
-
µs
Remarks
Stop mode
Trigger input timing
tTRGH
INTx
RXx
108
CONFIDENTIAL
VIH
tTRGL
VIH
VIL
VIL
S6J312A_DS708-00005-0v01-E, August 7, 2014
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12.8 NMI input timing
(TA: Recommended operating conditions, Vcc=5.0 V ±10%, VSS=AVSS=0.0 V)
Parameter
Input pulse width
−
Symbol
Pin Name
Conditions
tNMIL
NMIX
-
Value
Min
Max
300
-
Unit
Remarks
ns
NMIX input timing
tNMIL
NMIX
VIH
VIH
VIL
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VIL
109
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12.9 Low-voltage detection (external low-voltage detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Detection voltage
Symbol
Pin Name
Conditions
VDP5
VCC
-
VDL0
VCC
VDL1
VCC
VDL2
VCC
*1
*3
*1
*4
*1
*5
Value
Unit
Min
Typ
Max
3.5
-
5.5
V
3.6
3.8
4.0
V
3.8
4.0
4.2
V
4
4.2
4.4
V
Remarks
When
power-supply
voltage falls
and detection
level is set
initially
When
Hysteresis width
VHYS
VCC
-
-
100
-
mV
power-supply
voltage rises
Low-voltage detection
time
Power supply voltage
regulation
Td
-
-
-
-
30
μs
-
VCC
-
-2
-
2
V/ms
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (Td), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage
regulation to do a low-voltage detection by detecting voltage (VDL)
*3: SYSC0_RUNLVDCFGR.LVDH1V = 0100B or SYSC0_PSSLVDCFGR.LVDH1V = 0100B
*4: SYSC0_RUNLVDCFGR.LVDH1V = 0101B or SYSC0_PSSLVDCFGR.LVDH1V = 0101B
*5: SYSC0_RUNLVDCFGR.LVDH1V = 0110B or SYSC0_PSSLVDCFGR.LVDH1V = 0110B
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12.10 Low-voltage detection (internal low-voltage detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Symbol
Pin Name
Conditions
VRDP5
-
VRDL
-
Value
Unit
Min
Typ
Max
-
0.6
-
1.4
V
*
0.9
0.95
1.0
V
Remarks
When
Detection voltage
power-supply
voltage falls
When
Hysteresis width
VRHYS
-
-
-
75
-
mV
power-supply
voltage rises
Low-voltage detection
time
TRd
-
-
-
-
30
μs
*: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (TRd), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
12.11 Low-voltage detection (1.2 V power supply low-voltage detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply voltage
range
Symbol
Pin Name
Conditions
VRDP5
-
-
VRDL0
-
VRDL1
-
Detection voltage
*1
*2
*1
*3
Value
Unit
Remarks
Min
Typ
Max
0.6
-
1.4
V
0.92
0.97
1.02
V
When
1.02
1.07
1.12
V
voltage falls
power-supply
When
Hysteresis width
VRHYS
-
-
-
75
-
mV
power-supply
voltage rises
Low-voltage detection
time
TRd
-
-
-
-
30
μs
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less
than the low-voltage detection time (TRd), there is the possibility to generate or release after the power
supply voltage has exceeded the detection voltage range.
*2: SYSC0_RUNLVDCFGR.LVDL1V = 10B or SYSC0_PSSLVDCFGR.LVDL1V = 10B
*3: SYSC0_RUNLVDCFGR.LVDL1V = 11B or SYSC0_PSSLVDCFGR.LVDL1V = 11B
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12.12 A/D converter
12.12.1 Electrical characteristics
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Resolution
-
Total Error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
±12
LSB
*3
Integral Nonlinearity
-
-
-
-
±4.0
LSB
*4
Differential Nonlinearity
-
-
-
-
±1.9
LSB
*4
Zero transition voltage
VZT
*6
Full-scale transition voltage
VFST
*6
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
Analog port input current
IAIN
*6
-2.0
-
2.0
µA
Analog input voltage
VAIN
*6
AVSS
-
AVRH
V
AVRH
AVRH0,AVRH1
4.5
-
5.5
V
-
0.0
-
V
-
500
900
µA
per one unit
-
1.0
100
µA
*2
-
1
2
mA
per one unit
-
-
5.0
µA
*2
-
-
4
LSB
-
-
4
LSB
Reference voltage
AVRL
IA
Power supply current
IAH
IR
IRH
AVRL0/AVSS0,
AVRL1/AVSS1
AVCC
AVRH
*7
Variation between channels
-
AVRL
-11.5LSB
AVRH
-13.5LSB
AVRL
-
+12.5LSB
AVRH
-
+10.5LSB
V
*5
V
VAVSS≤
VAIN≤VAVCC
AVcc≥AVRH
AN32 to AN43,
AN46 to AN53,
AN55 to AN62
*1: Time for each channel
*2: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and
CPU is stopped.
*3: Total Error is a comprehensive static error that includes the linearity. 1LSB=(AVRH-AVRL)/4096
*4: 1LSB=(VFST-VZT)/4094
*5: 1LSB=(AVRH-AVRL)/4096
*6: AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, AN27 to AN43, AN46 to AN53, and AN55
to AN62
*7: AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN31
112
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12.12.2 Notes on Using A/D converters
About the output impedance of an external circuit for analog input
When the external impedance is too high, the analog voltage sampling time may become insufficient. In
this case, we recommend attaching a capacitor (about 0.1 µF) to an analog input pin.
Analog input circuit model
Rext
Analog input
Rint
Comparator
Source
Cext
Rint
Cint
Rext
Cext
Cint
: Analog input impedance
3.9 kiloohms (max) (4.5 V≤AVcc≤5.5 V)
: Capacitance of MCU input pin
11.0pF (max) (4.5 V≤AVcc≤5.5 V)
: External driving impedance
: Capacitance of PCB at A/D converter input
The following approximation formula for the replacement model above can be used:
sampling time (minimum) = 9 x ( (Rin + Rext ) x Cin + Rext x Cext )
Note: Listed values must be considered as reference values.
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12.12.3 Definition of terms
Resolution: Analog variation that is recognized by an A/D converter
*
Integral Nonlinearity error : Deviation of the straight line connecting the zero transition point ("0000 0000
0000" <--> "0000 0000 0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from
actual conversion characteristics includes zero transition error, full-scale transition error, and non-linearity
error.
Differential Nonlinearity error: Deviation from the ideal value of the input voltage required for changing the
output code by 1 LSB
Total error : Difference between the actual value and the theoretical value. The total error
*: Represented as "Linearity error" in the former product series.
Total error
FFF
FFE
Actual conversion
characteristics
1.5LSB
{1 LSB (N - 1) + 0.5LSB}
Digital output
FFD
V NT
(Actually-measured
value)
004
003
Actual conversion
characteristics
002
001
AVRL
(AVSS)
Ideal characteristics
0.5LSB
Analog input
AVRH
Total error of digital output N =
1LSB(Ideal value) =
VNT- {1 LSB × (N-1) + 0.5LSB}
1LSB
AVRH - AVRL
4096
[LSB]
[V]
N: A/D converter digital output value.
VZT(Ideal value) = AVRL + 0.5LSB[V]
VFST(Ideal value) = AVRH - 1.5LSB[V]
VNT: Voltage at which the digital output changes from "(N – 1)" to "N".
114
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Integral Nonlinearity
Differential Nonlinearity
Ideal characteristics
FFE
Actual conversion
characteristics
FFD
{1 LSB (N - 1) + VZT}
004
003
002
N+1
VFST(Actuallymeasured
value)
V NT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Digital output
FFF
Actual conversion
characteristics
N
V (N+1)T
(Actuallymeasured
V NT
value)
(Actually-measured value)
Actual conversion
characteristics
N-1
N-2
001
VZT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVSS
(AVRL)
AVRH
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
Analog input
VNT- {1 LSB × (N-1) + VZT}
1LSB
V(N+1) T- VNT
1LSB
VFST - VZT
4094
AVRH
[LSB]
-1 LSB [LSB]
[V]
VZT: Voltage for which digital output changes from "0x000" to "0x001"
VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF".
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12.13 Flash memory
Rating
Parameter
Unit
Remarks
Min
Typ*3
Max*3
-
300
1100
ms
-
800
3700
ms
8-bit write time
-
15
288
µs
System-level overhead time excluded*1
16-bit write time
-
19
384
µs
System-level overhead time excluded*1
32-bit write time
-
27
567
µs
System-level overhead time excluded*1
64-bit write time
-
45
945
µs
System-level overhead time excluded*1
-
19
384
µs
System-level overhead time excluded*1
-
23
483
µs
System-level overhead time excluded*1
-
31
651
µs
System-level overhead time excluded*1
-
49
1029
µs
System-level overhead time excluded*1
Sector erase time
8-bit (with ECC)
write time
16-bit (with ECC)
write time
32-bit (with ECC)
write time
64-bit (with ECC)
write time
1,000/20 years,
Erase count*2/
Data retention time
8-KB sector*1
Internal preprogramming time included
64-KB sector*1
Internal preprogramming time included
Temperature at write/erase time
-
10,000/10 years,
-
-
Average temperature TA=+85 degrees
Celsius
100,000/5 years
*1: Guaranteed value for up to 100,000 erases
*2: Number of erases for each sector
*3: Target value
Notes:
−
−
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might be shut down while writing or erasing, be sure to turn the
power off by using an external low-voltage detection function.
−
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL),
hold Vcc at 2.7V or more within the duration calculated by the following expression:
1
2
Td* [µs] + (1 / FCRF* [MHz]) x 1029 + 25 [µs]
*1 : See "12.8 Low-voltage detection (external low-voltage detection)"
*2 : See "12.4.1 Source clock timing"
116
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13. ORDERING INFORMATION
Part Number
Package
S6J312xHAASEy0000
Plastic, LEU144
Note:
−
"x"/"y" is an part number option. For the part number option, see the following table.
For details on each package, see "PACKAGE DIMENSIONS."
14. PART NUMBER OPTION
Part Number Option "x"
FLASH
A
1MByte
Part Number Option "y"
1
Sn-Bi & Halogen Free
2
PureSn & Halogen Free
August 7, 2014, S6J312A_DS708-00005-0v01-E
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15. PACKAGE DIMENSIONS
118
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16. MAJOR CHANGES IN THIS EDITION
Page
Section
Change Results
Revision 0.1
-
-
August 7, 2014, S6J312A_DS708-00005-0v01-E
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Initial release
119
D a t a S h e e t ( P r e l i m i n a r y )
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the
respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2014 Spansion
TM
ORNAND
®
®
®
TM
All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and
other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
120
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S6J312A_DS708-00005-0v01-E, August 7, 2014
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