The following document contains information on Cypress products.
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS709-00002-1v0-E
610-PRE20110422E
32-bit ARMTM CortexTM-M4F based Microcontroller
MB9B460R Series
MB9BF466M/N/R, MB9BF467M/N/R,
MB9BF468M/N/R
DESCRIPTION
The MB9B460R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and competitive cost.
These series are based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART,
CSIO, I2C, LIN).
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.11
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B460R Series
FEATURES
32-bit ARM Cortex-M4F Core
・ Processor version: r2p1
・ Up to 160 MHz Frequency Operation
・ FPU built-in
・ Support DSP instruction
・ Memory Protection Unit (MPU): improves the reliability of an embedded system
・ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128
peripheral interrupts and 16 priority levels
・ 24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash memories.
・ MainFlash memory
・ Up to 1024 Kbytes
・ Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
・ The read access to Flash memory can be achieved without wait-cycle up to operation frequency of
72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory
can be obtained by Flash Accelerator System.
・ Security function for code protection
・ WorkFlash memory
・ 32 Kbytes
・ Read cycle:
・6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
・4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
・2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
・0wait-cycle: the operation frequency up to 40MHz
・ Security function is shared with code protection
[SRAM]
This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to
I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of
Cortex-M4F core.
・ SRAM0: Up to 64 Kbytes
・ SRAM1: Up to 32 Kbytes
・ SRAM2: Up to 32 Kbytes
External Bus Interface
・ Supports SRAM, NOR, NAND Flash and SDRAM device
・ Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
・ 8/16-bit Data width
・ Up to 25-bit Address bit
・ Supports Address/Data multiplex
・ Supports external RDY function
・ Supports scramble function
・ Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
・ Possible to set two kinds of the scramble key
Note: It is necessary to prepare the dedicated software library to use the scramble function.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
CAN Interface (Max 2 channels)
・ Compatible with CAN Specification 2.0A/B
・ Maximum transfer rate: 1 Mbps
・ Built-in 32 message buffer
Multi-function Serial Interface (Max 8 channels)
・ 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication
mode or bit length.)
・ Operation mode is selectable from the followings for each channel.
・ UART
・ CSIO
・ LIN
・ I 2C
[UART]
・ Full-duplex double buffer
・ Selection with or without parity supported
・ Built-in dedicated baud rate generator
・ External clock available as a serial clock
・ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・ Full-duplex double buffer
・ Built-in dedicated baud rate generator
・ Overrun error detect function available
・ Serial chip select function (ch.6 and ch.7 only)
・ Supports high-speed SPI (ch.4 and ch.6 only)
・ Data length 5 to 16-bit
[LIN]
・ LIN protocol Rev.2.1 supported
・ Full-duplex double buffer
・ Master/Slave mode supported
・ LIN break field generation (can change to 13 to 16-bit length)
・ LIN break delimiter generation (can change to 1 to 4-bit length)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
・ Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported
・ Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・ 8 independently configured and operated channels
・ Transfer can be started by software or request from the built-in peripherals
・ Transfer address area: 32-bit (4 Gbytes)
・ Transfer mode: Block transfer/Burst transfer/Demand transfer
・ Transfer data type: bytes/half-word/word
・ Transfer block count: 1 to 16
・ Number of transfers: 1 to 65536
DSTC (Descriptor System data Transfer Controller) (128 channels)
The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor
system and, following the specified contents of the Descriptor which has already been constructed on the
memory, can access directly the memory /peripheral device and performs the data transfer operation.
It supports the software activation, the hardware activation and the chain activation functions.
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MB9B460R Series
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
・ Successive Approximation type
・ Built-in 3 units
・ Conversion time: 0.5μs @ 5V
・ Priority conversion available (priority at 2levels)
・ Scanning conversion mode
・ Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
DA converter (Max 2 channels)
・ R-2R type
・ 12-bit resolution
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each channel.
・ 16-bit PWM timer
・ 16-bit PPG timer
・ 16/32-bit reload timer
・ 16/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
・ Capable of pull-up control per pin
・ Capable of reading pin level directly
・ Built-in the port relocate function
・ Up to 100 high-speed general-purpose I/O ports @ 120pin Package
・ Some pin is 5V tolerant I/O.
See "PIN DESCRIPTION" and "I/O CIRCUIT TYPE" for the corresponding pins.
Multi-function Timer (Max 2 units)
The Multi-function timer is composed of the following blocks.
Minimum resolution : 6.25 ns
・ 16-bit free-run timer × 3ch./unit
・ Input capture × 4ch./unit
・ Output compare × 6ch./unit
・ A/D activation compare × 6ch./unit
・ Waveform generator × 3ch./unit
・ 16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
・ PWM signal output function
・ DC chopper waveform output function
・ Dead time function
・ Input capture function
・ A/D convertor activate function
・ DTIF (Motor emergency stop) interrupt function
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
・ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
・ Timer interrupt function after set time or each set time.
・ Capable of rewriting the time with continuing the time count.
・ Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (Max 2 channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・ 16-bit position counter
・ 16-bit revolution counter
・ Two 16-bit compare registers
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
Watch Counter
The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the
main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
・ External interrupt input pin: Max 16 pins
・ Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
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MB9B460R Series
SD Card Interface
It is possible to use the SD card that conforms to the following standards.
・ Part 1 Physical Layer Specification version 3.01
・ Part E1 SDIO Specification version 3.00
・ Part A2 SD Host Controller Standard Specification version 3.00
・ 1-bit or 4-bit data bus
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
・ Main clock
・ Sub Clock
・ High-speed internal CR Clock
・ Low-speed internal CR Clock
・ Main PLL Clock
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
[Resets]
・ Reset requests from INITX pin
・ Power on reset
・ Software reset
・ Watchdog timers reset
・ Low voltage detector reset
・ Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
・ LVD1: error reporting via interrupt
・ LVD2: auto-reset operation
Low-power Consumption Mode
Six low-power consumption modes are supported.
・ SLEEP
・ TIMER
・ RTC
・ STOP
・ Deep standby RTC (selectable from with/without RAM retention)
・ Deep standby stop (selectable from with/without RAM retention)
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
VBAT
The consumption power during the RTC operation can be reduced by supplying the power supply
independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be
used.
・ RTC
・ 32 kHz oscillation circuit
・ Power-on circuit
・ Back up register : 32 bytes
・ Port circuit
Debug
・ Serial Wire JTAG Debug Port (SWJ-DP)
・ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Three Power Supplies
・Wide range voltage
: VCC = 2.7V to 5.5V
・Power supply for VBAT : VBAT = 2.7V to 5.5V
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
PRODUCT LINEUP
Memory size
Product name
MB9BF466M/N/R
MB9BF467M/N/R
MB9BF468M/N/R
MainFlash memory
WorkFlash memory
On-chip SRAM
SRAM0
SRAM1
SRAM1
512 Kbytes
32 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
768 Kbytes
32 Kbytes
96 Kbytes
48 Kbytes
24 Kbytes
24 Kbytes
1024 Kbytes
32 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
Function
MB9BF466M
MB9BF467M
MB9BF468M
Product name
Pin count
100/112
120/144
Cortex-M4F, MPU, NVIC 128ch.
160 MHz
2.7V to 5.5V
2ch. (Max)
8ch.
128ch.
Addr:25-bit (Max),
Addr:25-bit (Max),
Addr:19-bit (Max),
R/W data: 8/16-bit
R/W data: 8/16-bit
R/W data: 8-bit
(Max),
(Max),
(Max),
CS:9 (Max),
CS:9 (Max),
CS:5 (Max),
SRAM,
SRAM,
SRAM,
NOR Flash,
NOR Flash,
NOR Flash
NAND Flash,
SDRAM
SDRAM
Freq.
Power supply voltage range
CAN
DMAC
DSTC
External Bus Interface
MF Timer
MB9BF466R
MB9BF467R
MB9BF468R
80
CPU
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation compare
Input capture
Free-run timer
Output compare
Waveform generator
PPG
SD Card Interface
QPRC
Dual Timer
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog Timer
External Interrupts
I/O Ports
12-bit A/D Converter
MB9BF466N
MB9BF467N
MB9BF468N
8ch. (Max)
8ch. (Max)
6ch.
4ch.
3ch.
6ch.
3ch.
3ch.
2 units (Max)
63pins (Max)
16ch. (3 units)
1 unit
2ch. (Max)
1 unit
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
16pins (Max) + NMI × 1
80pins (Max)
100pins (Max)
24ch. (3 units)
12-bit D/A Converter
2 units (Max)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz (±2%)
Built-in CR
Low-speed
100 kHz (Typ)
Debug Function
SWJ-DP/ETM
Unique ID
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
PACKAGES
Product name
Package
LQFP: FPT-80P-M37 (0.5mm pitch)
LQFP: FPT-80P-M40 (0.65mm pitch)
QFP: FPT-100P-M36 (0.65mm pitch)
LQFP: FPT-100P-M23 (0.5mm pitch)
LQFP: FPT-120P-M37 (0.5mm pitch)
BGA: BGA-112P-M05 (0.5mm pitch)
BGA: BGA-144P-M09 (0.5mm pitch)
MB9BF466M
MB9BF467M
MB9BF468M
-
-
MB9BF466N
MB9BF467N
MB9BF468N
-
-
MB9BF466R
MB9BF467R
MB9BF468R
: Supported
Note : See "PACKAGE DIMENSIONS" for detailed information on each package.
10
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
PIN ASSIGNMENT
・ FPT-80P-M37/M40
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
59
P21/AN17/SIN0_0/INT06_1
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
58
P22/CROUT_0/AN16/TIOB7_1/SOT0_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
57
P23/AN15/TIOA7_1/SCK0_0/RTO00_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
56
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
55
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
54
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
53
P18/AN08/SCK2_2/MAD15_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
52
AVRH
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
51
AVRL
50
AVSS
49
AVCC
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
13
48
P17/AN07/SOT2_2/WKUP3/MAD14_0
P3A/TIOA0_1/AIN0_0/RTO00_0
14
47
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3B/TIOA1_1/BIN0_0/RTO01_0
15
46
P15/AN05/SCK0_1/MAD12_0
P3C/TIOA2_1/ZIN0_0/RTO02_0
16
45
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3D/TIOA3_1/RTO03_0/MAD00_0
17
44
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3E/TIOA4_1/RTO04_0/MAD01_0
18
43
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3F/TIOA5_1/RTO05_0/MAD02_0
19
42
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
VSS
20
41
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
32
33
34
35
36
37
38
39
40
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
28
VBAT
P4B/TIOB1_0/SCS7_1/MAD03_0
27
P49/VWAKEUP
31
26
P48/VREGCTL
30
25
P47/X1A
VCC
24
P46/X0A
29
23
INITX
C
22
VSS
21
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
LQFP - 80
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
r5.0
MB9B460R Series
・ FPT-100P-M23
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
74
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
73
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
72
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
71
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
70
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
69
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
68
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
67
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
66
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P1C/AN12/CTS4_1/IC03_1/MAD19_0
65
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
13
63
AVRH
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
14
62
AVRL
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
15
61
AVSS
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
16
60
AVCC
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
LQFP - 100
64
P18/AN08/SCK2_2/MAD15_0
17
59
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
18
58
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
19
57
P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
20
56
P14/AN04/SOT0_1/IC03_2/MAD11_0
49
50
VSS
43
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
PE3/X1
42
P4B/TIOB1_0/SCS7_1/MAD03_0
48
41
PE2/X0
40
VSS
VCC
47
39
C
MD0
38
VBAT
46
37
P49/VWAKEUP
45
36
PE0/MD1
35
P47/X1A
P48/VREGCTL
44
34
P46/X0A
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
33
INITX
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
32
VCC
P45/TIOB0_0/RTO15_1/DA1
51
31
25
30
VSS
P44/TIOA4_0/RTO14_1/DA0
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
52
29
24
P42/TIOA2_0/RTO12_1/MSDWEX_0
P3F/TIOA5_1/RTO05_0/MAD02_0
28
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P41/TIOA1_0/RTO11_1/INT13_1
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
53
27
54
23
26
55
22
P3E/TIOA4_1/RTO04_0/MAD01_0
VCC
21
P3D/TIOA3_1/RTO03_0/MAD00_0
P40/TIOA0_0/RTO10_1/INT12_1
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P17/AN07/SOT2_2/WKUP3/MAD14_0
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r5.0
MB9B460R Series
・FPT-120P-M37
VCC
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/SIN5_1/INT03_0/S_CD_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2
P65/TIOB7_0/SCK5_1
P66/ADTG_8/SIN3_0/INT11_2
P67/TIOA7_2/SOT3_0
P68/TIOB7_2/SCK3_0/INT00_2
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
(TOP VIEW)
1
90
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
89
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
88
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
4
87
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
86
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
6
85
P24/RX1_0/SIN2_1/RTO01_1/INT01_2
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
84
P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
83
P26/TIOB5_0/SCK2_1/RTO03_1
P57/SCK6_0/MADATA07_0
9
82
P27/TIOA6_2/RTO04_1/INT02_2
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0
10
81
P1F/ADTG_4/TIOB6_2/RTO05_1
P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0
11
80
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0
12
79
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
LQFP - 120
P5B/CTS4_2/MADATA11_0
13
78
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0
14
77
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0
15
76
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0
16
75
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0
17
74
P18/AN08/SCK2_2/MAD15_0
P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0
18
73
AVRH
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0
19
72
AVRL
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0
20
71
AVSS
P37/SOT5_2/IC01_0/INT05_2/MNREX_0
21
70
AVCC
50
51
52
53
54
55
56
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
P70/TX0_0/TIOA4_2/AIN0_1/IC13_1
P71/RX0_0/TIOB4_2/BIN0_1/IC12_1/INT15_1
P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2
P73/TIOB6_0/SOT2_0/IC10_1/INT03_2
P74/SCK2_0/DTTI1X_1
PE0/MD1
60
49
VSS
48
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
59
47
P4B/TIOB1_0/SCS7_1/MAD03_0
PE3/X1
46
58
45
VSS
VCC
57
44
C
MD0
43
PE2/X0
42
VBAT
VCC
P49/VWAKEUP
61
41
30
P48/VREGCTL
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS
40
62
39
29
P47/X1A
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0
P46/X0A
63
38
28
INITX
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0
37
64
36
27
P44/TIOA4_0/RTO14_1/DA0
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0
P45/TIOB0_0/RTO15_1/DA1
P14/AN04/SOT0_1/IC03_2/MAD11_0
65
35
66
26
34
25
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
33
67
P41/TIOA1_0/RTO11_1/INT13_1
24
P42/TIOA2_0/RTO12_1/MSDWEX_0
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
32
P17/AN07/SOT2_2/WKUP3/MAD14_0
68
31
69
VCC
22
23
P40/TIOA0_0/RTO10_1/INT12_1
P38/SCK5_2/IC00_0/INT06_2
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
r5.0
MB9B460R Series
・FPT-100P-M36
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
VCC
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
VSS
P20/AN18/AIN1_1/INT05_0/MAD24_0
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
81
50
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
82
49
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
83
48
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
84
47
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
85
46
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
86
45
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
87
44
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
88
43
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
89
42
P18/AN08/SCK2_2/MAD15_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
90
41
AVRH
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
91
40
AVRL
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
92
39
AVSS
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
93
38
AVCC
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
94
37
P17/AN07/SOT2_2/WKUP3/MAD14_0
QFP - 100
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
31
7
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3D/TIOA3_1/RTO03_0/MAD00_0 100
P42/TIOA2_0/RTO12_1/MSDWEX_0
32
6
99
5
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P41/TIOA1_0/RTO11_1/INT13_1
33
P40/TIOA0_0/RTO10_1/INT12_1
98
4
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
3
34
VCC
97
2
P15/AN05/SCK0_1/MAD12_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
1
P16/AN06/SIN2_2/INT14_1/MAD13_0
35
VSS
36
96
P3F/TIOA5_1/RTO05_0/MAD02_0
95
P3E/TIOA4_1/RTO04_0/MAD01_0
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r5.0
MB9B460R Series
・BGA-112P-M05
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
P81
P80
VCC
VSS
TCK/
SWCLK
VSS
AN21
P0A
P0B
VSS
P0E
VSS
B
VCC
VSS
P60
P61
P62
TRSTX SWDIO
AN22
AN19
P0C
P0D
VSS
VCC
C
P50
P51
P52
AN23
AN20
VSS
AN18
AN17
D
P53
P54
AN16
AN15
E
P55
P56
P30
AN14
AN13
AVRH
F
P31
P32
P33
AN12
AN11
AVRL
G
P34
P35
P36
AN10
AN09
AVSS
H
VSS
P37
P38
AN08
AN07
AVCC
J
P39
P3A
P3B
AN06
AN05
AN04
K
P3C
P3D
AN03
AN02
L
P3E
P3F
P43
VSS
AN01
AN00
M
VCC
VSS
P42
N
VSS
P40
P41
P63
TMS/
TDI
TDO/
SWO
index
P45
P48
P4B
P4C
P4E
P44
VSS
INITX
P49
VCC
P4D
MD1
MD0
VSS
VCC
VSS
X0A
X1A
VSS
VBAT
C
VSS
X0
X1
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
r5.0
MB9B460R Series
・BGA-144P-M09
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
P81
P80
VCC
VSS
P66
VSS
VSS
AN21
VSS
P0C
VCC
VSS
B
VCC
VSS
P60
P61
P63
P67
TCK/
SWCLK
TDO/
SWO
AN20
P0B
VSS
VSS
P0E
C
P50
P51
VSS
P62
P64
P68
TDI
AN23
AN19
P0D
VSS
AN18
VSS
D
P52
P53
P54
VSS
P65
AN22
P0A
VSS
AN17
AN16
AN15
E
P55
P56
P57
P58
index
P24
P25
P26
P27
F
P59
P5A
P5B
P30
P1F
AN14
AN13
AN12
G
P31
P32
P33
P34
AN11
AN10
AN09
AVRH
H
P35
P36
P37
P38
AN08
AN07
AN06
AVRL
J
P39
P3A
P3B
P3C
AN05
AN04
AN03
AVSS
K
VSS
P3D
P3E
VSS
P45
P49
P4C
P70
P72
VSS
AN02
AN01
AVCC
L
P3F
P41
VSS
P44
VSS
P48
P4B
P4E
P71
P74
VSS
AN00
VSS
M
VCC
VSS
P43
VSS
X1A
VSS
VSS
P4D
VCC
P73
MD0
VSS
VCC
N
VSS
P40
P42
INITX
X0A
VSS
VBAT
C
VSS
MD1
X0
X1
VSS
TMS/
TRSTX SWDIO
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
16
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r5.0
MB9B460R Series
PIN DESCRIPTION
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
1
1
1
79
B1
B1
2
2
2
80
C1
C1
3
3
3
81
C2
C2
4
4
4
82
C3
D1
5
5
5
83
D1
D2
6
6
6
84
D2
D3
7
7
7
85
E1
E1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
VCC
P50
CTS4_0
AIN0_2
RTO10_0
(PPG10_0)
INT00_0
MADATA00_0
P51
RTS4_0
BIN0_2
RTO11_0
(PPG10_0)
INT01_0
MADATA01_0
P52
SCK4_0
(SCL4_0)
ZIN0_2
RTO12_0
(PPG12_0)
MADATA02_0
P53
TIOA1_2
SOT4_0
(SDA4_0)
RTO13_0
(PPG12_0)
MADATA03_0
P54
TIOB1_2
SIN4_0
RTO14_0
(PPG14_0)
INT02_0
MADATA04_0
P55
ADTG_1
SIN6_0
RTO15_0
(PPG14_0)
INT07_2
MADATA05_0
I/O
circuit
type
-
Pin state
type
-
E
K
E
K
E
I
E
I
E
K
E
K
17
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
8
8
8
86
E2
E2
9
-
-
-
-
E3
10
-
-
-
-
E4
11
-
-
-
-
F1
12
-
-
-
-
F2
13
-
-
-
-
F3
9
9
87
E3
-
-
-
-
10
10
88
F1
-
-
-
-
14
14
15
15
18
FUJITSU SEMICONDUCTOR CONFIDENTIAL
F4
F4
G1
G1
Pin Name
P56
SOT6_0
(SDA6_0)
DTTI1X_0
INT08_2
MADATA06_0
P57
SCK6_0
(SCL6_0)
MADATA07_0
P58
SIN4_2
AIN1_0
INT04_2
MADATA08_0
P59
RX1_1
SOT4_2
(SDA4_2)
BIN1_0
INT07_1
MADATA09_0
P5A
TX1_1
SCK4_2
(SCL4_2)
ZIN1_0
MADATA10_0
P5B
CTS4_2
MADATA11_0
P30
TIOB0_1
RTS4_2
INT15_2
WKUP1
MADATA07_0
MADATA12_0
P31
TIOB1_1
SIN3_1
INT09_2
MADATA08_0
MADATA13_0
I/O
circuit
type
Pin state
type
E
K
E
I
E
K
E
K
E
I
E
I
E
Q
I
K
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
16
16
17
17
18
18
19
19
LQFP100
LQFP80
QFP100
BGA112
11
11
89
F2
-
-
-
-
12
12
90
F3
-
-
-
-
13
-
91
G1
-
-
-
-
14
-
92
G2
-
-
-
-
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
BGA144
G2
G2
G3
G3
G4
G4
H1
H1
Pin Name
P32
TIOB2_1
SOT3_1
(SDA3_1)
INT10_1
MADATA09_0
MADATA14_0
P33
ADTG_6
TIOB3_1
SCK3_1
(SCL3_1)
INT04_0
MADATA10_0
MADATA15_0
P34
TX0_1
TIOB4_1
FRCK0_0
MADATA11_0
MNALE_0
P35
RX0_1
TIOB5_1
IC03_0
INT08_1
MADATA12_0
MNCLE_0
I/O
circuit
type
Pin state
type
N
K
N
K
E
I
E
K
19
r5.0
MB9B460R Series
Pin No
LQFP120
20
20
21
21
22
LQFP100
LQFP80
QFP100
BGA112
15
-
93
G3
-
-
-
-
16
-
94
H2
-
-
-
-
17
-
95
H3
-
23
BGA144
H2
H2
H3
H3
H4
-
18
13
96
J1
J1
97
J2
J2
98
J3
J3
-
24
19
14
-
25
20
15
-
20
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P36
SIN5_2
IC02_0
INT09_1
MADATA13_0
MNWEX_0
P37
SOT5_2
(SDA5_2)
IC01_0
INT05_2
MADATA14_0
MNREX_0
P38
SCK5_2
(SCL5_2)
IC00_0
INT06_2
MADATA15_0
P39
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
MSDCLK_0
P3A
TIOA0_1
AIN0_0
RTO00_0
(PPG00_0)
MSDCKE_0
P3B
TIOA1_1
BIN0_0
RTO01_0
(PPG00_0)
MRASX_0
I/O
circuit
type
Pin state
type
E
K
E
K
E
K
L
I
G
I
G
I
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
26
LQFP100
21
LQFP80
16
QFP100
BGA112
BGA144
99
K1
J4
-
27
22
17
100
K2
K2
28
23
18
1
L1
K3
29
24
19
2
L2
L1
30
31
25
26
20
-
3
4
N1
M1
N1
M1
32
27
-
5
N2
N2
33
28
-
6
N3
L2
34
29
-
7
M3
N3
35
30
-
8
L3
M3
36
31
21
9
M4
L4
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P3C
TIOA2_1
ZIN0_0
RTO02_0
(PPG02_0)
MCASX_0
P3D
TIOA3_1
RTO03_0
(PPG02_0)
MAD00_0
P3E
TIOA4_1
RTO04_0
(PPG04_0)
MAD01_0
P3F
TIOA5_1
RTO05_0
(PPG04_0)
MAD02_0
VSS
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
MSDWEX_0
P43
ADTG_7
TIOA3_0
RTO13_1
(PPG12_1)
MCSX8_0
P44
TIOA4_0
RTO14_1
(PPG14_1)
DA0
I/O
circuit
type
Pin state
type
G
I
G
I
G
I
G
I
-
-
G
K
G
K
G
I
G
I
R
J
21
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
37
32
22
10
L5
K5
38
33
23
11
M6
N4
39
34
24
12
N5
N5
40
35
25
13
N6
M5
41
36
26
14
L6
L6
42
37
27
15
M7
K6
43
44
45
46
38
39
40
41
28
29
30
31
16
17
18
19
N8
N9
N10
M8
N7
N8
N9
M9
47
42
32
20
L7
L7
48
43
33
21
L8
K7
49
44
34
22
M9
M8
50
45
35
23
L9
L8
51
-
-
-
-
K8
22
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P45
TIOB0_0
RTO15_1
(PPG14_1)
DA1
INITX
P46
X0A
P47
X1A
P48
VREGCTL
P49
VWAKEUP
VBAT
C
VSS
VCC
P4B
TIOB1_0
SCS7_1
MAD03_0
P4C
TIOB2_0
SCK7_1
(SCL7_1)
AIN1_2
MAD04_0
P4D
TIOB3_0
SOT7_1
(SDA7_1)
BIN1_2
INT13_2
MAD05_0
P4E
TIOB4_0
SIN7_1
ZIN1_2
FRCK1_1
INT11_1
WKUP2
MAD06_0
P70
TX0_0
TIOA4_2
AIN0_1
IC13_1
I/O
circuit
type
Pin state
type
R
J
B
C
P
S
Q
T
O
U
O
U
-
-
E
I
N
I
N
K
I
Q
E
I
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
52
-
-
-
-
L9
53
-
-
-
-
K9
54
-
-
-
-
M10
55
-
-
-
-
L10
56
46
36
24
M10
N10
57
47
37
25
M11
M11
58
48
38
26
N11
N11
59
49
39
27
N12
N12
60
61
50
51
40
-
28
29
N13
M13
N13
M13
62
52
41
30
L13
L12
63
53
42
31
L12
K12
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P71
RX0_0
TIOB4_2
BIN0_1
IC12_1
INT15_1
P72
TIOA6_0
SIN2_0
ZIN0_1
IC11_1
INT14_2
P73
TIOB6_0
SOT2_0
(SDA2_0)
IC10_1
INT03_2
P74
SCK2_0
(SCL2_0)
DTTI1X_1
PE0
MD1
MD0
PE2
X0
PE3
X1
VSS
VCC
P10
AN00
RX1_2
SIN1_1
FRCK0_2
INT02_1
MAD07_0
P11
AN01
TX1_2
SOT1_1
(SDA1_1)
IC00_2
MAD08_0
I/O
circuit
type
Pin state
type
E
K
E
K
E
K
E
I
C
E
J
D
A
A
A
B
-
-
F
M
F
L
23
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
64
54
43
32
K13
K11
65
55
44
33
K12
J12
66
56
45
34
J13
J11
67
57
46
35
J12
J10
68
58
47
36
J11
H12
69
59
48
37
H12
H11
70
71
72
73
60
61
62
63
49
50
51
52
38
39
40
41
H13
G13
F13
E13
K13
J13
H13
G13
74
64
53
42
H11
H10
75
65
54
43
G12
G12
24
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P12
AN02
SCK1_1
(SCL1_1)
IC01_2
RTCCO_1
SUBOUT_1
MAD09_0
P13
AN03
SIN0_1
IC02_2
INT03_1
MAD10_0
P14
AN04
SOT0_1
(SDA0_1)
IC03_2
MAD11_0
P15
AN05
SCK0_1
(SCL0_1)
MAD12_0
P16
AN06
SIN2_2
INT14_1
MAD13_0
P17
AN07
SOT2_2
(SDA2_2)
WKUP3
MAD14_0
AVCC
AVSS
AVRL
AVRH
P18
AN08
SCK2_2
(SCL2_2)
MAD15_0
P19
AN09
SIN4_1
IC00_1
INT05_1
MAD16_0
I/O
circuit
type
Pin state
type
F
L
F
M
F
L
F
L
F
M
F
P
-
-
F
L
F
M
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
76
66
55
44
G11
G11
77
67
56
45
F12
G10
78
68
-
46
F11
F13
79
69
-
47
E12
F12
80
70
-
48
E11
F11
81
-
-
-
-
F10
82
-
-
-
-
E13
83
-
-
-
-
E12
84
-
-
-
-
E11
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P1A
AN10
SOT4_1
(SDA4_1)
IC01_1
MAD17_0
P1B
AN11
SCK4_1
(SCL4_1)
IC02_1
MAD18_0
P1C
AN12
CTS4_1
IC03_1
MAD19_0
P1D
AN13
RTS4_1
DTTI0X_1
MAD20_0
P1E
AN14
ADTG_5
FRCK0_1
MAD21_0
P1F
ADTG_4
TIOB6_2
RTO05_1
(PPG04_1)
P27
TIOA6_2
RTO04_1
(PPG04_1)
INT02_2
P26
TIOB5_0
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
P25
TX1_0
TIOA5_0
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
I/O
circuit
type
Pin state
type
M
L
M
L
F
L
F
L
F
L
E
I
E
K
E
I
E
I
25
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
85
-
86
71
LQFP80
-
57
QFP100
BGA112
BGA144
-
-
E10
49
D13
D13
50
D12
D12
51
C13
D11
-
87
72
58
59
88
73
89
74
-
52
C12
C12
90
91
75
76
60
61
53
54
A13
B13
A13
A12
92
77
62
55
A12
B13
93
78
63
56
B11
C10
59
-
26
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P24
RX1_0
SIN2_1
RTO01_1
(PPG00_1)
INT01_2
P23
AN15
TIOA7_1
SCK0_0
(SCL0_0)
RTO00_1
(PPG00_1)
MAD22_0
P22
CROUT_0
AN16
TIOB7_1
SOT0_0
(SDA0_0)
ZIN1_1
P21
AN17
SIN0_0
BIN1_1
INT06_1
MAD23_0
P20
AN18
AIN1_1
INT05_0
MAD24_0
VSS
VCC
P0E
TIOB5_2
SCS6_1
IC13_0
S_CLK_0
MDQM1_0
P0D
TIOA5_2
SCK6_1
(SCL6_1)
IC12_0
S_CMD_0
MDQM0_0
I/O
circuit
type
Pin state
type
E
K
F
L
F
L
F
M
F
M
-
-
L
I
L
I
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
94
79
64
57
B10
A11
95
80
65
58
A10
B10
96
81
66
59
A9
D9
60
B9
C9
67
97
82
67
98
83
-
61
C9
B9
99
84
-
62
A8
A9
100
85
-
63
B8
D8
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P0C
TIOA6_1
SOT6_1
(SDA6_1)
IC11_0
S_DATA1_0
MALE_0
P0B
TIOB6_1
SIN6_1
IC10_0
INT00_1
S_DATA0_0
MCSX0_0
P0A
SIN1_0
FRCK1_0
INT12_2
S_DATA3_0
MCSX1_0
P09
AN19
TRACED0
TIOA3_2
SOT1_0
(SDA1_0)
S_DATA2_0
MCSX5_0
P08
AN20
TRACED1
TIOB3_2
SCK1_0
(SCL1_0)
MCSX4_0
P07
AN21
TRACED2
TIOA0_2
SCK7_0
(SCL7_0)
MCLKOUT_0
P06
AN22
TRACED3
TIOB0_2
SOT7_0
(SDA7_0)
MCSX3_0
I/O
circuit
type
Pin state
type
L
I
L
K
L
K
M
N
F
N
F
N
F
N
27
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
101
86
-
64
C8
C8
102
87
68
65
C7
B8
103
88
69
66
B7
D7
104
89
70
67
C6
C7
105
90
71
68
A6
B7
106
91
72
69
B6
D6
107
92
-
70
A5
A7
108
-
-
-
-
C6
109
-
-
-
-
B6
110
-
-
-
-
A6
111
-
-
-
-
D5
112
-
-
-
-
C5
28
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
P05
AN23
ADTG_0
TRACECLK
SIN7_0
INT01_1
MCSX2_0
P04
TDO
SWO
P03
TMS
SWDIO
P02
TDI
MCSX6_0
P01
TCK
SWCLK
P00
TRSTX
MCSX7_0
VSS
P68
TIOB7_2
SCK3_0
(SCL3_0)
INT00_2
P67
TIOA7_2
SOT3_0
(SDA3_0)
P66
ADTG_8
SIN3_0
INT11_2
P65
TIOB7_0
SCK5_1
(SCL5_1)
P64
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
I/O
circuit
type
Pin state
type
F
O
E
G
E
G
E
H
E
G
E
H
-
-
E
K
E
I
E
K
E
I
E
K
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
93
73
71
C5
-
-
-
-
93
73
71
C5
114
94
74
72
B5
C4
115
95
75
73
B4
B4
116
96
76
74
B3
B3
117
118
119
120
-
97
98
99
100
-
77
78
79
80
-
75
76
77
78
-
A4
A3
A2
A1
A7
B2
B12
C11
H1
N4
M5
N7
L11
A11
M12
M2
A4
A3
A2
A1
A5
A8
A10
B2
B11
B12
C3
C11
C13
D4
D10
K1
113
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
BGA144
B5
Pin Name
P63
CROUT_1
RX0_2
SIN5_1
INT03_0
S_CD_0
MWEX_0
P62
ADTG_3
TX0_2
SIN5_0
INT04_1
S_WP_0
MOEX_0
P61
TIOB2_2
SOT5_0
(SDA5_0)
RTCCO_0
SUBOUT_0
P60
TIOA2_2
SCK5_0
(SCL5_0)
NMIX
WKUP0
MRDY_0
VCC
P80
P81
VSS
I/O
circuit
type
Pin state
type
E
K
I
K
E
I
I
F
H
H
-
R
R
-
29
r5.0
MB9B460R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
-
-
-
-
-
K4
K10
L3
L5
L11
L13
M2
M4
M6
M7
M12
N6
30
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin Name
VSS
I/O
circuit
type
-
Pin state
type
-
DS709-00002-1v0-E
r5.0
MB9B460R Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin
function
ADC
Base
Timer 0
Pin name
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
Function description
A/D converter external trigger input
pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
101
7
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
87
88
89
97
98
99
100
101
32
24
99
37
14
100
86
7
18
94
70
12
30
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
86
27
19
84
32
9
85
7
13
74
12
41
42
43
44
45
46
47
48
53
54
55
56
57
58
59
67
14
22
9
-
64
85
96
72
48
90
8
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
64
5
97
62
10
87
63
BGA
112
BGA
144
C8
E1
J1
B5
E11
F3
L3
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
D12
C13
C12
B9
C9
A8
B8
C8
N2
J2
A8
L5
E3
B8
C8
E1
J1
C4
F10
F11
G3
M3
A6
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D12
D11
C12
C9
B9
A9
D8
C8
N2
J2
A9
K5
F4
D8
31
r5.0
MB9B460R Series
Pin
function
Base
Timer 1
Base
Timer 2
Base
Timer 3
Base
Timer 4
Base
Timer 5
Base
Timer 6
Base
Timer 7
CAN 0
Pin name
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
Function description
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
32
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
33
25
5
47
15
6
34
26
116
48
16
115
35
27
97
49
17
98
36
28
51
50
18
52
84
29
93
83
19
92
53
94
82
54
95
81
112
86
109
111
87
108
51
18
114
52
19
113
28
20
5
42
10
6
29
21
96
43
11
95
30
22
82
44
12
83
31
23
45
13
24
78
14
77
79
80
71
72
13
94
14
93
15
5
32
10
6
16
76
33
11
75
17
67
34
12
21
18
35
19
63
62
64
65
57
58
74
73
6
98
83
20
88
84
7
99
74
21
89
73
8
100
60
22
90
61
9
1
23
91
2
56
92
55
57
58
49
50
91
72
92
71
BGA
112
BGA
144
N3
J3
D1
L7
F1
D2
M3
K1
B3
L8
F2
B4
L3
K2
B9
M9
F3
C9
M4
L1
L9
G1
L2
B11
G2
A12
B10
A10
D13
D12
G1
B5
G2
C5
L2
J3
D2
L7
G1
D3
N3
J4
B3
K7
G2
B4
M3
K2
C9
M8
G3
B9
L4
K3
K8
L8
G4
L9
E11
L1
C10
E12
H1
B13
K9
A11
E13
M10
B10
F10
C5
D13
B6
D5
D12
C6
K8
G4
C4
L9
H1
B5
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Pin name
CAN 1
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
SWCLK
SWDIO
Debugger
External
Bus
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
Function description
CAN interface ch.1 TX output pin
CAN interface ch.1 RX output pin
Serial wire debug interface clock input
pin
Serial wire debug interface data input /
output pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
Trace CLK output pin of ETM
Trace data output pin of ETM
J-TAG test reset Input pin
External bus interface address bus
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
84
12
63
85
11
62
53
52
42
41
31
30
L12
L13
E11
F2
K12
E10
F1
L12
105
90
71
68
A6
B7
103
88
69
66
B7
D7
102
105
104
102
103
101
97
98
99
100
106
27
28
29
47
48
49
50
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
88
89
87
90
89
87
88
86
82
83
84
85
91
22
23
24
42
43
44
45
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
73
74
68
71
70
68
69
72
17
18
19
32
33
34
35
41
42
43
44
45
46
47
48
53
54
55
56
-
65
68
67
65
66
64
60
61
62
63
69
100
1
2
20
21
22
23
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
51
52
C7
A6
C6
C7
B7
C8
B9
C9
A8
B8
B6
K2
L1
L2
L7
L8
M9
L9
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
C13
C12
B8
B7
C7
B8
D7
C8
C9
B9
A9
D8
D6
K2
K3
L1
L7
K7
M8
L8
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D11
C12
33
r5.0
MB9B460R Series
Pin
function
External
Bus
Pin name
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MCSX8_0
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
MDQM1_0
MALE_0
MRDY_0
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
MWEX_0
Function description
External bus interface chip select
output pin
External bus interface data bus
(Address / data multiplex bus)
External bus interface byte mask signal
output pin
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY
input signal
External bus interface external clock
output pin
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable
signal to control NAND Flash
External bus interface write enable
signal to control NAND Flash
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
34
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
95
96
101
100
98
97
104
106
35
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
93
92
80
81
86
85
83
82
89
91
30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
78
77
65
66
67
70
72
2
3
4
5
6
7
8
9
10
11
12
63
62
58
59
64
63
61
60
67
69
8
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
56
55
A10
A9
C8
B8
C9
B9
C6
B6
L3
C1
C2
C3
D1
D2
E1
E2
E3
F1
F2
F3
G1
G2
G3
H2
H3
B11
A12
B10
D9
C8
D8
B9
C9
C7
D6
M3
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
C10
B13
94
79
64
57
B10
A11
116
96
76
74
B3
B3
99
84
-
62
A8
A9
18
-
-
-
-
G4
19
-
-
-
-
H1
21
-
-
-
-
H3
20
-
-
-
-
H2
114
94
74
72
B5
C4
113
93
73
71
C5
B5
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Pin name
MSDCLK_0
MSDCKE_0
External
Bus
MRASX_0
MCASX_0
MSDWEX_0
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_1
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
Function description
SDRAM interface
SDRAM clock output pin
SDRAM interface
SDRAM clock enable pin
SDRAM interface
SDRAM row address strobe pin
SDRAM interface
SDRAM column address strobe pin
SDRAM interface
SDRAM write enable pin
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
23
18
-
96
J1
J1
24
19
-
97
J2
J2
25
20
-
98
J3
J3
26
21
-
99
K1
J4
34
29
-
7
M3
N3
2
95
108
3
101
85
6
62
82
113
65
54
17
114
10
89
75
21
88
22
11
7
19
8
20
15
16
112
50
110
32
96
33
49
68
53
52
14
116
2
80
3
86
6
52
93
55
12
94
74
65
16
73
17
7
14
8
15
10
11
45
27
81
28
44
58
9
96
2
65
3
6
41
73
44
12
74
54
59
7
8
10
11
35
66
34
47
9
76
80
58
81
64
84
30
71
33
90
72
52
43
94
51
95
85
92
86
93
88
89
23
5
59
6
22
36
87
74
C1
A10
C2
C8
D2
L13
C5
K12
F3
B5
C12
G12
H2
C13
H3
E1
G2
E2
G3
F1
F2
L9
N2
A9
N3
M9
J11
E3
B3
C1
B10
C6
C2
C8
E10
D3
L12
E13
B5
J12
M10
G3
C4
E4
C12
G12
H3
D11
H4
F1
E1
H1
E2
H2
G1
G2
C5
L8
A6
N2
D9
L2
M8
H12
K9
L9
F4
B3
35
r5.0
MB9B460R Series
Pin
function
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
Function description
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
36
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
81
89
88
87
86
85
84
83
82
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
74
73
72
71
-
72
71
70
69
68
67
66
65
64
63
62
41
42
43
44
45
46
47
48
53
54
55
56
59
58
57
-
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
52
51
50
49
-
BGA
112
BGA
144
B6
A6
C6
B7
C7
C8
B8
A8
C9
B9
A9
A10
B10
B11
A12
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
C12
C13
D12
D13
-
D6
B7
C7
D7
B8
C8
D8
A9
B9
C9
D9
B10
A11
C10
B13
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
F10
C12
D11
D12
D13
E10
E11
E12
E13
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
Function description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
39
40
41
42
47
48
49
50
2
3
4
5
6
7
8
9
10
11
12
13
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
34
35
36
37
42
43
44
45
2
3
4
5
6
7
8
-
9
10
11
12
13
14
15
16
17
18
19
21
22
24
25
26
27
32
33
34
35
2
3
4
5
6
7
8
-
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
12
13
14
15
20
21
22
23
80
81
82
83
84
85
86
-
BGA
112
BGA
144
E3
F1
F2
F3
G1
G2
G3
H2
H3
J1
J2
J3
K1
K2
L1
L2
N2
N3
M3
L3
M4
L5
N5
N6
L6
M7
L7
L8
M9
L9
C1
C2
C3
D1
D2
E1
E2
-
F4
G1
G2
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
K2
K3
L1
N2
L2
N3
M3
L4
K5
N5
M5
L6
K6
L7
K7
M8
L8
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
37
r5.0
MB9B460R Series
Pin
function
GPIO
Pin name
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
Multifunction
Serial
0
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
Multifunction
Serial
1
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
Function description
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0
input pin
Multi-function serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SCL0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.1
input pin
Multi-function serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a CSIO (operation modes 4)
and as SCL1 when it is used in an I2C
(operation mode 4).
38
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
116
115
114
113
112
111
110
109
108
51
52
53
54
55
118
119
56
58
59
88
65
96
95
94
93
98
99
46
48
49
73
55
76
75
74
73
78
79
36
38
39
59
44
74
73
72
71
76
77
24
26
27
51
33
B3
B4
B5
C5
A3
A2
M10
N11
N12
C13
K12
B3
B4
C4
B5
C5
D5
A6
B6
C6
K8
L9
K9
M10
L10
A3
A2
N10
N11
N12
D11
J12
87
72
58
50
D12
D12
66
56
45
34
J13
J11
86
71
57
49
D13
D13
67
57
46
35
J12
J10
96
62
81
52
66
41
59
30
A9
L13
D9
L12
97
82
67
60
B9
C9
63
53
42
31
L12
K12
98
83
-
61
C9
B9
64
54
43
32
K13
K11
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Multifunction
Serial
2
Pin name
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SOT3_0
(SDA3_0)
Multifunction
Serial
3
SOT3_1
(SDA3_1)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
Multifunction
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
CTS4_0
CTS4_1
CTS4_2
RTS4_0
RTS4_1
RTS4_2
Function description
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
53
85
68
58
47
36
J11
K9
E10
H12
Multi-function serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
54
-
-
-
-
M10
84
-
-
-
-
E11
69
59
48
37
H12
H11
Multi-function serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a CSIO (operation modes 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
55
-
-
-
-
L10
83
-
-
-
-
E12
74
64
53
42
H11
H10
Multi-function serial interface ch.3
input pin
110
15
10
10
88
F1
A6
G1
109
-
-
-
-
B6
16
11
11
89
F2
G2
108
-
-
-
-
C6
17
12
12
90
F3
G3
6
75
10
6
65
-
6
54
-
84
43
-
D2
G12
-
D3
G12
E4
5
5
5
83
D1
D2
76
66
55
44
G11
G11
11
-
-
-
-
F1
4
4
4
82
C3
D1
77
67
56
45
F12
G10
12
-
-
-
-
F2
2
78
13
3
79
14
2
68
3
69
9
2
3
9
80
46
81
47
87
C1
F11
C2
E12
E3
C1
F13
F3
C2
F12
F4
Multi-function serial interface ch.2
input pin
Multi-function serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation modes 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.4
input pin
Multi-function serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation modes 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.4
CTS input pin
Multi-function serial interface ch.4
RTS output pin
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
r5.0
MB9B460R Series
Pin
function
Multifunction
Serial
5
Pin name
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
Multifunction
Serial
6
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCS6_1
SIN7_0
SIN7_1
SOT7_0
(SDA7_0)
Multifunction
Serial
7
SOT7_1
(SDA7_1)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
SCS7_1
Function description
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
114
113
20
94
15
74
-
72
93
B5
G3
C4
B5
H2
Multi-function serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
115
95
75
73
B4
B4
112
-
-
-
-
C5
21
16
-
94
H2
H3
Multi-function serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation modes 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
116
96
76
74
B3
B3
111
-
-
-
-
D5
22
17
-
95
H3
H4
Multi-function serial interface ch.6
input pin
7
95
7
80
7
65
85
58
E1
A10
E1
B10
8
8
8
86
E2
E2
94
79
64
57
B10
A11
9
-
-
-
-
E3
93
78
63
56
B11
C10
92
77
62
55
A12
B13
101
50
86
45
35
64
23
C8
L9
C8
L8
100
85
-
63
B8
D8
49
44
34
22
M9
M8
99
84
-
62
A8
A9
48
43
33
21
L8
K7
47
42
32
20
L7
L7
Multi-function serial interface ch.5
input pin
Multi-function serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation modes 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.6
serial chip select pin
Multi-function serial interface ch.7
input pin
Multi-function serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a CSIO (operation modes 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.7
serial chip select pin
40
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Pin name
Function description
DTTI0X_0
Input signal controlling wave form
generator outputs RTO00 to RTO05 of
Multi-function timer 0.
DTTI0X_1
Multifunction
Timer
0
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
16-bit free-run timer ch.0 external
clock input pin
16-bit input capture ch.0 input pin of
Multi-function timer 0.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
23
18
13
96
J1
J1
79
69
-
47
E12
F12
18
80
62
22
75
63
21
76
64
20
77
65
19
78
66
13
70
52
17
65
53
16
66
54
15
67
55
14
68
56
41
54
42
55
43
56
44
45
91
48
30
95
43
31
94
44
32
93
45
33
92
46
34
G1
E11
L13
H3
G12
L12
H2
G11
K13
G3
F12
K12
G2
F11
J13
G4
F11
L12
H4
G12
K12
H3
G11
K11
H2
G10
J12
H1
F13
J11
24
19
14
97
J2
J2
86
71
57
49
D13
D13
25
20
15
98
J3
J3
85
-
-
-
-
E10
26
21
16
99
K1
J4
84
-
-
-
-
E11
27
22
17
100
K2
K2
83
-
-
-
-
E12
28
23
18
1
L1
K3
82
-
-
-
-
E13
29
24
19
2
L2
L1
81
-
-
-
-
F10
41
r5.0
MB9B460R Series
Pin
function
Pin name
Function description
DTTI1X_0
Input signal controlling wave form
generator outputs RTO10 to RTO15 of
Multi-function timer 1.
DTTI1X_1
Multifunction
Timer
1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
16-bit free-run timer ch.1 external
clock input pin
16-bit input capture ch.1 input pin of
Multi-function timer 1.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is
used in PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is
used in PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is
used in PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is
used in PPG1 output modes.
42
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
8
8
8
86
E2
E2
55
-
-
-
-
L10
96
50
95
54
94
53
93
52
92
51
81
45
80
79
78
77
-
66
35
65
64
63
62
-
59
23
58
57
56
55
-
A9
L9
A10
B10
B11
A12
-
D9
L8
B10
M10
A11
K9
C10
L9
B13
K8
2
2
2
80
C1
C1
32
27
-
5
N2
N2
3
3
3
81
C2
C2
33
28
-
6
N3
L2
4
4
4
82
C3
D1
34
29
-
7
M3
N3
5
5
5
83
D1
D2
35
30
-
8
L3
M3
6
6
6
84
D2
D3
36
31
21
9
M4
L4
7
7
7
85
E1
E1
37
32
22
10
L5
K5
DS709-00002-1v0-E
r5.0
MB9B460R Series
Pin
function
Quadrature
Position/
Revolution
Counter
0
Quadrature
Position/
Revolution
Counter
1
Real-time
clock
Pin name
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
WKUP0
Low-Po
wer
Consump
tion
Mode
WKUP1
WKUP2
WKUP3
DAC
VBAT
DA0
DA1
VREGCTL
VWAKEUP
S_CLK_0
S_CMD_0
SD I/F
S_DATA1_0
S_DATA0_0
S_DATA3_0
S_DATA2_0
S_CD_0
S_WP_0
RESET
INITX
Function description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
0.5 seconds pulse output pin of
Real-time clock
Sub clock output pin
Deep standby mode return signal input
pin 0
Deep standby mode return signal input
pin 1
Deep standby mode return signal input
pin 2
Deep standby mode return signal input
pin 3
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
On-board regulator control pin
The return signal input pin from a
hibernation state
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
SD memory card interface
SD memory card data bus
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
External Reset Input pin.
A reset is valid when INITX="L".
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
24
51
2
25
52
3
26
53
4
10
89
48
11
88
49
12
87
50
115
64
23
115
64
23
19
2
20
3
21
4
74
43
73
44
72
45
95
54
18
95
54
18
14
2
15
3
16
4
33
34
35
75
43
13
75
43
13
97
80
98
81
99
82
52
21
51
22
50
23
73
32
96
73
32
96
J2
C1
J3
C2
K1
C3
C12
L8
C13
M9
D12
L9
B4
K13
J1
B4
K13
J1
J2
K8
C1
J3
L9
C2
J4
K9
D1
E4
C12
K7
F1
D11
M8
F2
D12
L8
B4
K11
J1
B4
K11
J1
116
96
76
74
B3
B3
14
9
9
87
E3
F4
50
45
35
23
L9
L8
69
59
48
37
H12
H11
36
37
41
31
32
36
21
22
26
9
10
14
M4
L5
L6
L4
K5
L6
42
37
27
15
M7
K6
92
77
62
55
A12
B13
93
78
63
56
B11
C10
94
95
96
97
79
80
81
82
64
65
66
67
57
58
59
60
B10
A10
A9
B9
A11
B10
D9
C9
113
93
73
71
C5
B5
114
94
74
72
B5
C4
38
33
23
11
M6
N4
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MB9B460R Series
Pin
function
Pin name
MD1
MODE
MD0
Function description
Mode 1 pin.
During serial programming to Flash
memory, MD1="L" must be input.
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
VCC
Power supply Pin
GND
VSS
GND Pin
GND
VSS
GND Pin
CLOCK
X0
X1
X0A
X1A
CROUT_0
CROUT_1
POWER
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
44
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
56
46
36
24
M10
N10
57
47
37
25
M11
M11
1
31
46
61
91
117
107
30
45
60
90
120
58
59
39
40
87
113
1
26
41
51
76
97
92
25
40
50
75
100
48
49
34
35
72
93
1
31
61
77
20
30
40
60
80
38
39
24
25
58
73
79
4
19
29
54
75
70
3
18
28
53
78
26
27
12
13
50
71
B1
M1
M8
M13
B13
A4
A5
N1
N10
N13
A13
A1
A7
B2
B12
C11
H1
N4
M5
N7
L11
A11
M12
M2
N11
N12
N5
N6
D12
C5
B1
M1
M9
M13
A12
A4
A7
N1
N9
N13
A13
A1
A5
A8
A10
B2
B11
B12
C3
C11
C13
D4
D10
K1
K4
K10
L3
L5
L11
L13
M2
M4
M6
M7
M12
N6
N11
N12
N5
M5
D12
B5
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Pin
function
Pin name
AVCC
ADC
POWER
AVRL
AVRH
VBAT
POWER
ADC
GND
C pin
VBAT
AVSS
C
Function description
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference
voltage input pin
A/D converter analog reference
voltage input pin
VBAT power supply pin.
Backup power supply (battery etc.) and
system power supply.
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
Pin No
LQFP LQFP LQFP QFP
120 100
80
100
BGA
112
BGA
144
70
60
49
38
H13
K13
72
62
51
40
F13
H13
73
63
52
41
E13
G13
43
38
28
16
N8
N7
71
61
50
39
G13
J13
44
39
29
17
N9
N8
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I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the main oscillation is
selected.
・ Oscillation feedback resistor
: Approximately 1MΩ
・ With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
・ CMOS level hysteresis input
・Pull-up resistor
: Approximately 50kΩ
B
Pull-up resistor
Digital input
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Type
Circuit
Remarks
C
Digital input
・ Open drain output
・CMOS level hysteresis input
Digital output
N-ch
E
P-ch
Digital output
P-ch
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -4mA, IOL = 4mA
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
Digital output
P-ch
・ CMOS level output
・ CMOS level hysteresis input
・ With input control
・ Analog input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -4mA, IOL = 4mA
Digital output
N-ch
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
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Type
Circuit
Remarks
G
P-ch
Digital output
P-ch
N-ch
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -12mA, IOL = 12mA
Digital output
R
Pull-up resistor
control
Digital input
Standby mode
control
・ CMOS level output
・ CMOS level hysteresis input
・ With standby mode control
H
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode
Control
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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Type
Circuit
Remarks
I
P-ch
P-ch
N-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
・ With standby mode control
・ IOH = -4mA, IOL = 4mA
・Available to control of PZR
registers.
Digital output
R
Pull-up resistor
control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
L
P-ch
P-ch
N-ch
R
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -8mA, IOL = 8mA
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
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Type
Circuit
Remarks
M
P-ch
P-ch
N-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ With input control
・ Analog input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -8mA, IOL = 8mA
Digital output
Pull-up resistor
control
Digital input
R
Standby mode
control
Analog input
Input control
N
P-ch
P-ch
N-ch
R
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -4mA, IOL = 4mA
(GPIO)
・IOL = 20mA
(Fast Mode Plus)
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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Type
Circuit
Remarks
O
P-ch
P-ch
N-ch
Pull-up resistor
control
Digital output
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・5V tolerant
・With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
・ For I/O setting, refer to
VBAT Domain in the
PERIPHERAL MANUAL
R
Digital input
Standby mode
control
P
P-ch
P-ch
X0A
N-ch
Pull-up resistor
control
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
・ For I/O setting, refer to
VBAT Domain in the
PERIPHERAL MANUAL
Digital output
R
Digital input
Standby mode
control
OSC
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MB9B460R Series
Type
Circuit
Remarks
Q
It is possible to select the sub
oscillation / GPIO function
Pull-up resistor
control
Digital output
P-ch
P-ch
X1A
Digital output
N-ch
R
Digital input
Standby mode
control
OSC
When the sub oscillation is
selected.
・ Oscillation feedback resistor
: Approximately 10MΩ
・ With Standby mode control
・ When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
・ For I/O setting, refer to
VBAT Domain in the
PERIPHERAL MANUAL
RX
Standby mode
control
Clock input
R
P-ch
P-ch
N-ch
Pull-up resistor
control
Digital output
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Analog output
・With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・IOH = -12mA, IOL = 12mA
(4.5V～5.5V)
・IOH = -8mA, IOL = 8mA
(2.7V～4.5V)
R
Digital input
Standby mode
control
Analog output
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HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-2Ea
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Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications
(computers, office automation and other office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions.
For detailed information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised to
mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
54
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Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly
moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in
their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
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3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental
conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
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HANDLING DEVICES
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between VCC and VSS near this device.
Power supply pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization,
suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial
frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate
does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize
the oscillation.
• Surface mount type
Size
: More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
• Lead type
Load capacitance : Approximately 6 pF to 7 pF
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Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Set as External
clock input
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
58
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VBAT → VCC
VCC → AVCC → AVRH
Turning off : VCC → VBAT
AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of
P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with
the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the
ground pattern between them in order to avoid this possibility.
Device
P46/
X0A
P47/
X1A
P48/
P49/
VREGCTL VWAKEUP
Not allowed to run
both wirings in parallel
Ground
Insert the ground pattern
Handling when using debug pins
When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other
peripheral functions, only set them as output, do not set them as input.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
59
r1.0
MB9B460R Series
BLOCK DIAGRAM
MB9BF466M/N/R, F467M/N/R, F468M/N/R
TRSTX,TCK,
TDI,TMS
TDO
TRACEDx,
TRACECLK
SWJ-DP
ETM*
TPIU*
ROM
Table
SRAM0
32/48/64 Kbytes
SRAM1
16/24/32 Kbytes
Cortex-M4 Core I
@160 MHz(Max)
MPU NVIC
Multi-layer AHB (Max 160 MHz)
D
FPU
Sys
AHB-APB Bridge:
APB0(Max 80 MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
SRAM2
16/24/32 Kbytes
MainFlash I/F
Trace Buffer
(16 Kbytes)
Security
WorkFlash I/F
MainFlash
1 Mbytes/
768 Kbytes/
512 Kbytes
WorkFlash
32 Kbytes
DMAC
8ch.
CSV
DSTC
CLK
SD-CARD I/F
AHB-AHB Bridge
CAN
Source Clock
X0
X1
X0A
X1A
Main
Osc
PLL
VBAT Domain
Sub
Osc
CR
100 kHz
CR
4 MHz
CAN
GPIO
PIN-Function-Ctrl
ANxx
Unit 1
Unit 2
Base Timer
16-bit 16ch./
32-bit 8ch.
FRCK0
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
AHB-APB Bridge : APB2 (Max 80 MHz)
QPRC
2ch.
A/D Activation Compare
6ch.
IC0x
CAN Prescaler
Power-On
Reset
LVD Ctrl
LVD
IRQ-Monitor
Regulator
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
C
Watch Counter
Deep Standby Ctrl
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer × 2
WKUPx
Peripheral Clock Gating
Low-speed CR Prescaler
VBAT Domain
Real-Time Clock
Port Ctrl.
VWAKEUP
VREGCTL
RTCCO,
SUBOUT
External Interrupt
Controller
16pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
Multi-function Serial I/F
8ch.
HW flow control(ch.4)
SCKx
SINx
SOTx
CTS4
RTS4
12-bit D/A Converter
2units
DAx
DTTI0X
RTO0x
.
.
.
CRC Accelerator
AHB-APB Bridge : APB1 (Max 160 MHz)
AINx
BINx
ZINx
P0x,
P1x,
MADATAx
12-bit A/D Converter
Unit 0
ADTGx
TIOBx
TX1,
RX1
MADx
External Bus I/F
TIOAx
TX0,
RX0
PEx
CROUT
AVCC,
AVSS,
AVRH
S_CLK,S_CMD
S_DATAx
S_CD,S_WP
*: For the MB9BF466M, MB9BF467M and MB9BF468M, ETM is not available.
60
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
MEMORY SIZE
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
MEMORY MAP
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4007_0000
0x4006_F000
0x4006_E000
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M4 Private
Peripherals
0x4006_4000
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
GPIO
SD-Card I/F
Reserved
CAN ch.1
CAN ch.0
DSTC
DMAC
Reserved
0x4004_0000
0x4003_F000
External Device
Area
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
32 Mbytes
Bit band alias
Peripherals
0x4000_0000
Reserved
0x2400_0000
0x2200_0000
32 Mbytes
Bit band alias
Reserved
0x2010_0000
0x200E_0000
0x200C_0000
See "Memory Map (2)"
for the memory size
details.
0x2004_8000
0x2004_0000
0x2003_8000
0x2000_0000
0x1FFF_0000
0x0050_0000
0x0040_0000
WorkFlash I/F
WorkFlash
Reserved
SRAM2
SRAM1
Reserved
SRAM0
Reserved
Security/CR Trim
MainFlash
0x0000_0000
Reserved
0x4003_C800
0x4003_C100 Peripheral Clock Gating
0x4003_C000 Low Speed CR Prescaler
0x4003_B000
RTC/Port Ctrl
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4003_8000
MFS
0x4003_7000
CAN prescaler
Reserved
0x4003_6000
0x4003_5000
LVD/DS mode
0x4003_4000
Reserved
0x4003_3000
D/AC
Reserved
0x4003_2000
0x4003_1000
Int-Req.Read
0x4003_0000
EXTI
0x4002_F000
Reserved
0x4002_E000
CR Trim
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_2000
0x4002_1000
0x4002_0000
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
EXT-bus I/F
Reserved
A/DC
QPRC
Base Timer
PPG
Reserved
MFT Unit1
MFT Unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
MainFlash I/F
61
r1.0
MB9B460R Series
Memory Map (2)
MB9BF468M/N/R
0x2008_0000
MB9BF467M/N/R
0x2008_0000
Reserved
0x200C_8000
0x200C_0000
0x2008_0000
Reserved
0x200C_8000
WorkFlash
32 Kbytes
MB9BF466M/N/R
0x200C_0000
Reserved
Reserved
0x200C_8000
WorkFlash
32 Kbytes
0x200C_0000
Reserved
0x2004_8000
WorkFlash
32 Kbytes
Reserved
0x2004_6000
SRAM2
32 Kbytes
0x2004_0000
0x2004_0000
SRAM1
32 Kbytes
0x2003_A000
SRAM2
24 Kbytes
SRAM1
24 Kbytes
0x2004_4000
0x2004_0000
0x2003_C000
SRAM2
16 Kbytes
SRAM1
16 Kbytes
0x2003_8000
0x2000_0000
0x2000_0000
SRAM0
64 Kbytes
Reserved
Reserved
Reserved
0x1FFF_4000
0x2000_0000
SRAM0
48 Kbytes
0x1FFF_8000
SRAM0
32 Kbytes
0x1FFF_0000
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
Reserved
Reserved
Reserved
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
0x0040_2000
0x0040_0000
CR trimming
Security
Reserved
Reserved
0x0010_0000
Reserved
0x000C_0000
MainFlash
1 Mbytes
0x0000_0000
0x0008_0000
MainFlash
768 Kbytes
0x0000_0000
62
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MainFlash
512 Kbytes
0x0000_0000
DS709-00002-1v0-E
r1.0
MB9B460R Series
Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4006_E000
0x4006_F000
0x4006_7000
0x200E_0000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4003_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_4FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
0x200E_FFFF
Bus
AHB
APB0
APB1
APB2
AHB
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Peripherals
MainFlash I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
D/A Converter
Reserved
Low Voltage Detector
Deep standby mode Controller
Reserved
CAN prescaler
Multi-function serial Interface
CRC
Watch Counter
RTC/Port Ctrl
Low-speed CR Prescaler
Peripheral Clock Gating
Reserved
External Memory interface
Reserved
DMAC register
DSTC register
CAN ch.0
CAN ch.1
Reserved
SD-Card I/F
GPIO
Reserved
WorkFlash I/F register
63
r1.0
MB9B460R Series
PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
・ INITX=0
This is the period when the INITX pin is the "L" level.
・ INITX=1
This is the period when the INITX pin is the "H" level.
・ SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
・ SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
・ Input enabled
Indicates that the input function can be used.
・ Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
・ Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
・ Setting disabled
Indicates that the setting is disabled.
・ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
・ Analog input is enabled
Indicates that the analog input is enabled.
・ Trace output
Indicates that the trace function can be used.
・ GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
・ Setting prohibition
Prohibition of a setting by specification limitation.
64
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
Pin status type
・ List of Pin Status
A
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
‐
‐
Power supply
stable
INITX=0 INITX=1
‐
‐
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
‐
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Power supply
stable
Power supply
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Main crystal
oscillator
input pin/
External
main clock
input
selected
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
Setting
disabled
External
main clock
input
selected
Setting
disabled
Main crystal
oscillator
output pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
C
INITX
input pin
D
E
Device
internal
reset
state
Maintain
previous
state
GPIO
selected
B
INITX
input
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Input
enabled
Input
enabled
Input
enabled
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Return from
Deep
standby
mode state
Power
supply
stable
INITX=1
-
GPIO
selected
Input
enabled
GPIO
selected
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
Pull-up /
Input
enabled
Hi-Z /
Hi-Z /
Maintain
Maintain
Internal
Internal
previous
previous
input fixed
input fixed
state
state
at "0"
at "0"
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
Hi-Z /
Hi-Z / state/When state/When state/When state/When state/When state/When
Internal Internal oscillation oscillation oscillation oscillation oscillation oscillation
input
input
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
fixed
fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
at "0"
Pull-up / Pull-up / Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Input
Input
Input
Input
Input
Input
Input
Input
enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
Mode
input pin
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
input pin
Input
enabled
Input
Input
enabled enabled
Setting Setting
disabled disabled
Input
enabled
Hi-Z /
Input
enabled
Input
enabled
Hi-Z /
Input
enabled
Input
enabled
Setting
disabled
Input
enabled
Maintain
previous
state
Input
enabled
GPIO
selected
Input
enabled
Maintain
previous
state
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
GPIO
selected
GPIO
selected
65
r1.0
Pin status type
MB9B460R Series
Function
group
NMIX
selected
F
Resource
other than
above
selected
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
state
Power
supply
unstable
‐
‐
INITX=0 INITX=1
‐
‐
Setting
disabled
Setting Setting
disabled disabled
Hi-Z
GPIO
selected
JTAG
selected
INITX
input
state
Hi-Z
Power supply
stable
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Pull-up / Pull-up /
Input
Input
enabled enabled
G
H
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
JTAG
selected
Hi-Z
Pull-up / Pull-up /
Input
Input
enabled enabled
Resource
other than
above
selected
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Hi-Z
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Setting
disabled
Setting Setting
disabled disabled
Resource
selected
I
J
GPIO
selected
Analog
output
selected
Resource
other than
above
selected
GPIO
selected
Hi-Z
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
‐
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Power supply
stable
Power supply
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
*2
Maintain
previous
state
66
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Maintain
previous
state
Hi-Z /
WKUP
input
enabled
Power
supply
stable
INITX=1
-
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Return from
Deep
standby
mode state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
*3
GPIO
Hi-Z /
selected
Internal
Internal
Hi-Z /
input fixed
Internal input fixed
at "0"
at "0"
input fixed
at "0"
GPIO
selected
DS709-00002-1v0-E
r1.0
Pin status type
MB9B460R Series
K
Function
group
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Analog input
selected
Power-on
reset or
low-voltage
detection
state
Analog input
selected
M
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Device
internal
reset
state
Power
supply
unstable
‐
‐
INITX=0 INITX=1
‐
‐
Setting
disabled
Setting Setting
disabled disabled
Power supply
stable
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
‐
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Power supply
stable
Power supply
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
Return from
Deep
standby
mode state
Power
supply
stable
INITX=1
-
GPIO
selected
Hi-Z
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Hi-Z
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal Internal
Internal
Internal
Internal
Internal
Internal
Internal
input
input
input fixed input fixed input fixed input fixed input fixed input fixed
fixedat fixedat
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
"0" /
"0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog Analog
input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
L
Resource
other than
above
selected
GPIO
selected
INITX
input
state
Setting
disabled
Hi-Z
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal Internal
Internal
Internal
Internal
Internal
Internal
Internal
input
input
input fixed input fixed input fixed input fixed input fixed input fixed
fixed
fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" / at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog Analog
input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
Maintain
previous
state
Setting
disabled
GPIO
selected
Setting Setting
disabled disabled
Maintain
previous
state
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
selected
67
r1.0
Pin status type
MB9B460R Series
N
Function
group
Power
supply
unstable
‐
‐
Analog input
selected
Hi-Z
Trace
selected
Resource
other than
above
selected
GPIO
selected
Setting
disabled
Analog input
selected
O
Power-on
reset or
low-voltage
detection
state
Trace
selected
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Hi-Z
Setting
disabled
INITX
input
state
Device
internal
reset
state
Power supply
stable
INITX=0 INITX=1
‐
‐
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
‐
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Power supply
stable
Power supply
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Return from
Deep
standby
mode state
Power
supply
stable
INITX=1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal Internal
Internal
Internal
Internal
Internal
Internal
Internal
input
input
input fixed input fixed input fixed input fixed input fixed input fixed
fixed
fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at"0" / at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog Analog
input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
Trace
output
GPIO
Hi-Z /
Maintain
Maintain
selected
Setting Setting
Internal
GPIO
Hi-Z /
previous
previous
Internal
disabled disabled
input fixed selected
Internal
state
state
input fixed
at "0"
input fixed
at "0"
at "0"
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal Internal
Internal
Internal
Internal
Internal
Internal
Internal
input
input
input fixed input fixed input fixed input fixed input fixed input fixed
fixed
fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" / at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog Analog
input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
Trace
output
Setting Setting
disabled disabled
Maintain
previous
state
68
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
selected
DS709-00002-1v0-E
r1.0
Pin status type
MB9B460R Series
Function
group
Power
supply
unstable
‐
‐
Analog input
selected
P
Power-on
reset or
low-voltage
detection
state
Hi-Z
WKUP
enabled
Resource
other than
above
selected
GPIO
selected
Setting
disabled
INITX
input
state
Device
internal
reset
state
Power supply
stable
INITX=0 INITX=1
‐
‐
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
‐
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Power supply
stable
Power supply
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Q
R
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
GPIO
selected
Power
supply
stable
INITX=1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal Internal
Internal
Internal
Internal
Internal
Internal
Internal
input
input
input fixed input fixed input fixed input fixed input fixed input fixed
fixedat fixedat
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
"0" /
"0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog Analog
input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
Hi-Z /
Maintain
WKUP
WKUP
previous
input
input
state
enabled
enabled
Maintain
Maintain
Setting Setting
GPIO
previous
previous
GPIO
disabled disabled
selected
Hi-Z /
Hi-Z /
state
state
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
WKUP
enabled
Setting
disabled
Return from
Deep
standby
mode state
Maintain
previous
state
Setting Setting
disabled disabled
Maintain
previous
state
Hi-Z
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Hi-Z
Hi-Z /
Hi-Z /
Input
Input
enabled enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
GPIO
selected
GPIO
selected
69
r1.0
MB9B460R Series
*1 : Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode,
and Deep standby STOP mode.
*2 : Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*3 : Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
70
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
VBAT pin status type
・ List of VBAT Domain Pin Status
S
T
VBAT
Power-on
reset
INITX
input
state
Function
group
Device Run mode
internal or SLEEP
reset
mode
state
state
Power
Power
supply Power supply stable supply
unstable
stable
TIMER mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
Return
from
from
VBAT
Deep
VBAT
RTC
RTC
standby
mode state
mode
mode
state
state
Power supply stable
Power supply stable
Power
Power
Power
supply supply stable supply
stable
stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
‐
‐
INITX=0
‐
INITX=1
‐
INITX=1
‐
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Sub crystal
oscillator
input pin /
External
sub clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
External
sub clock
input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Sub crystal
oscillator
output pin
Hi-Z /
Internal
input
fixed at
"0"/
or Input
enable
Resource
selected
Hi-Z
U
GPIO
selected
Hi-Z /
Internal
input
fixed
at "0"
Hi-Z /
Internal
input
fixed
at "0"
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at "0"
at "0"
at "0"
Input
enabled
Input
enabled
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at "0"
at "0"
Hi-Z /
Maintain Maintain
Maintain
Internal
previous previous
previous
input fixed
state
state
state
at "0"
Maintain
Maintain
Maintain
previous
previous
previous
state/When state/When state/When
Maintain oscillation oscillation oscillation
previous
stops*,
stops*,
stops*,
state
Hi-Z /
Hi-Z /
Hi-Z/
Internal
Internal
Internal
input fixed input fixed input fixed
at "0"
at "0"
at "0"
Maintain Maintain Maintain
previous previous previous
state
state
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
INITX=1
-
-
-
GPIO
selected
Setting
prohibition
-
Input
enabled
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*,
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Maintain Maintain
previous previous
state
state
Setting
prohibition
Maintain Maintain
previous previous
state
state
Maintain
previous
state/When
oscillation Maintain Maintain
stops*,
previous previous
Hi-Z/
state
state
Internal
input fixed
at "0"
Maintain
previous
state
Maintain Maintain
previous previous
state
state
* : Oscillation is stopped at STOP mode and Deep standby STOP mode.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
-
71
r1.0
MB9B460R Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage *1, *2
Power supply voltage (VBAT) *1 ,*3
Analog power supply voltage *1 ,*4
Analog reference voltage *1 ,*4
Symbol
VCC
VBAT
AVCC
AVRH
Rating
Min
Max
Unit
Remarks
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
V
VSS + 6.5
V
VSS + 6.5
V
VSS + 6.5
V
VCC + 0.5
VSS - 0.5
V
(≤ 6.5V)
Input voltage *1
VI
VSS - 0.5
VSS + 6.5
V
5V tolerant
AV
+
0.5
CC
Analog pin input voltage *1
VIA
VSS - 0.5
V
(≤ 6.5V)
VCC + 0.5
Output voltage *1
VO
VSS - 0.5
V
(≤ 6.5V)
10
mA
4mA type
20
mA
8mA type
5
"L" level maximum output current *
IOL
20
mA
12mA type
22.4
mA
I2C Fm+
4
mA
4mA type
8
mA
8mA type
"L" level average output current *6
IOLAV
12
mA
12mA type
20
mA
I2C Fm+
"L" level total maximum output current
∑IOL
100
mA
"L" level total maximum output current *7 ∑IOLAV
50
mA
- 10
mA
4mA type
"H" level maximum output current *5
IOH
- 20
mA
8mA type
- 20
mA
12mA type
-4
mA
4mA type
"H" level average output current *6
IOHAV
-8
mA
8mA type
- 12
mA
12mA type
"H" level total maximum output current
∑IOH
- 100
mA
"H" level total average output current *7
∑IOHAV
- 50
mA
Storage temperature
TSTG
- 55
+ 150
°C
*1 : These parameters are based on the condition that V SS = AVSS = 0.0V.
*2 : VCC must not drop below VSS - 0.5V.
*3 : VBAT must not drop below VSS - 0.5V.
*4 : Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
*5 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*6 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100ms period.
*7 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
72
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
2. Recommended Operating Conditions
Parameter
Symbol
Conditions
Min
Value
Max
Unit
Remarks
Power supply voltage
VCC
2.7
5.5
V
Power supply voltage (VBAT)
VBAT
2.7
5.5
V
Analog power supply voltage
AVCC
2.7
5.5
V
AVCC=VCC
Analog reference voltage
AVRH
AVSS
AVCC
V
Junction temperature
Tj
- 40
+ 125
°C
Operating
temperature
Ambient temperature
Ta
- 40
*
°C
* : The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed the
junction temperature (Tj).
The calculation formula of the ambient temperature (Ta) is shown below.
Ta(Max) = Tj(Max) - Pd(Max) × θja
Pd : Power dissipation (W)
θja : Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL
IOH
VOL
VOH
: "L" level output current
: "H" level output current
: "L" level output voltage
: "H" level output voltage
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for package thermal resistance and maximum permissible power
Thermal
Maximum permissible power
resistance θja
(mW)
Package
Printed circuit board
(°C/W)
Ta=+85°C
Ta=+105°C
FPT-80P-M37
(0.5mm pitch)
FPT-80P-M40
(0.65mm pitch)
FPT-100P-M23
(0.5mm pitch)
FPT-100P-M36
(0.65mm pitch)
FPT-120P-M37
(0.5mm pitch)
BGA-112P-M05
(0.5mm pitch)
BGA-144P-M09
(0.5mm pitch)
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
60
39
58
38
57
38
48
34
62
43
60
40
55
40
667
1026
690
1053
702
1053
833
1177
645
930
667
1000
727
1000
333
513
335
526
351
526
417
588
323
465
333
500
364
500
73
r1.0
MB9B460R Series
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
Calculation method of power dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL
IOH
VOL
VOH
: "L" level output current
: "H" level output current
: "L" level output voltage
: "H" level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT) : Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO) : Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value
does not include ICC (IO) for a value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT : Pin internal load capacitance
CEXT : External load capacitance of output pin
fSW : Pin switching frequency
Parameter
Pin internal load
capacitance
Symbol
CINT
Conditions
Capacitance value
4mA type
1.93pF
8mA type
3.45pF
12mA type
3.42pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself.
(1) Measure current value ICC (Typ) at normal temperature (+25°C).
(2) Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Maximum leak current at
operating
Symbol
Conditions
Current value
ICC(leak_max)
Tj = +125°C
Tj = +105°C
Tj = +85°C
45.5mA
26.8mA
16.2mA
74
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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Current explanation diagram
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
VCC
A
ICC
Chip
ICC(INT)
ΣICC(IO)
A IOL
Regulator
V VOL
・・・
Flash
VOH
A
IOH
・・・
Logic
V
RAM
ICC(IO)
CEXT
・・・
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
75
r1.0
MB9B460R Series
3. DC Characteristics
(1) Current Rating
Parameter Symbol
Power
supply
current
ICC
Parameter Symbol
Power
supply
current
ICC
Pin
name
VCC
Pin
name
VCC
Conditions
Frequency*4
Normal
operation*5,*6
(PLL)
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
Conditions
Frequency*7
Normal
operation*8
(PLL)
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
Value
Unit
Typ*1 Max*2
54
49
41
35
28
22
16
8.9
5.1
3.8
34
31
26
22
18
14
10
6.2
3.8
3.1
103
98
90
84
77
71
64
58
54
53
83
80
75
71
67
63
59
55
53
52
mA
*3
When all
peripheral
clocks are ON
mA
*3
When all
peripheral
clocks are OFF
Value
Unit
Typ*1 Max*2
74
68
59
52
44
36
27
17
8.3
5.4
51
47
42
37
33
28
21
13
6.9
4.6
126
120
112
104
97
89
79
67
58
55
103
100
94
90
85
80
73
64
56
54
Remarks
Remarks
mA
*3
When all
peripheral
clocks are ON
mA
*3
When all
peripheral
clocks are OFF
*1: Ta=+25°C, VCC=3.3V
*2: Tj=+125°C, VCC=5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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Parameter Symbol
Power
supply
current
ICC
Pin
name
VCC
Conditions
Normal
operation*5
(PLL)
Value
Frequency*4
Unit
(MHz)
Typ*1 Max*2
72MHz
60MHz
48MHz
36MHz
24MHz
12MHz
8MHz
4MHz
72MHz
60MHz
48MHz
36MHz
24MHz
12MHz
8MHz
4MHz
46
40
33
27
19
11
8.5
5.5
33
29
25
20
15
9.2
6.9
4.6
98
92
85
78
70
61
58
55
85
81
76
71
65
59
56
54
Remarks
mA
*3
When all
peripheral
clocks are ON
mA
*3
When all
peripheral
clocks are OFF
*1: Ta=+25°C, VCC=3.3V
*2: Tj=+125°C, VCC=5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Parameter Symbol
Pin
name
Conditions
Normal
operation*5
(built-in
high-speed CR)
Power
supply
current
ICC
VCC
Normal
operation*5
(sub oscillation)
Normal
operation*5
(built-in
low-speed CR)
Frequency*4
Value
Typ*1 Max*2
Unit
3.3
51
mA
2.8
51
mA
0.64
48
mA
0.56
48
mA
0.64
48
mA
0.58
48
mA
4MHz
32kHz
100kHz
Remarks
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*1: Ta=+25°C, VCC=3.3V
*2: Tj=+125°C, VCC=5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
77
r1.0
MB9B460R Series
Parameter Symbol
Power
supply
current
ICCS
Parameter Symbol
Power
supply
current
ICCS
Value
Pin
Conditions Frequency*4
name
Typ*1 Max*2
VCC
SLEEP
operation
(PLL)
Pin
Conditions
name
VCC
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
Frequency*5
SLEEP
operation
(PLL)
72MHz
60MHz
48MHz
36MHz
24MHz
12MHz
8MHz
4MHz
72MHz
60MHz
48MHz
36MHz
24MHz
12MHz
8MHz
4MHz
35
32
27
23
19
15
11
6.5
4.1
3.3
16
14
12
11
9.0
7.4
5.6
3.9
2.9
2.6
84
81
76
72
68
64
60
55
53
52
65
63
61
60
58
56
54
53
52
51
Value
Typ*1 Max*2
22
19
16
12
9.0
5.8
4.6
3.6
9.5
8.3
7.1
5.8
4.6
3.5
3.0
2.7
71
68
64
61
58
55
54
52
58
57
56
55
53
52
52
51
Unit
Remarks
mA
*3
When all
peripheral clocks
are ON
mA
*3
When all
peripheral clocks
are OFF
Unit
Remarks
mA
*3
When all
peripheral clocks
are ON
mA
*3
When all
peripheral clocks
are OFF
*1: Ta=+25°C, VCC=3.3V
*2: Tj=+125°C, VCC=5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
78
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
Parameter Symbol
Pin
name
Conditions
SLEEP
operation
(built-in
high-speed CR)
Power
supply
current
ICCS
VCC
SLEEP
operation
(sub oscillation)
SLEEP
operation
(built-in
low-speed CR)
Frequency*4
Value
Unit
Typ*1 Max*2
1.5
49
mA
1.0
49
mA
0.59
48
mA
0.51
48
mA
0.61
48
mA
0.53
48
mA
4MHz
32kHz
100kHz
Remarks
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*3
When all
peripheral clocks
are ON
*3
When all
peripheral clocks
are OFF
*1: Ta=+25°C, VCC=3.3V
*2: Tj=+125°C, VCC=5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
79
r1.0
MB9B460R Series
Parameter
Symbol
Pin
name
ICCH
Conditions
STOP mode
TIMER mode
(built-in
high-speed CR)
Power
supply
current
ICCT
VCC
TIMER mode
(sub oscillation)
TIMER mode
(built-in
low-speed CR)
ICCR
RTC mode
(sub oscillation)
Frequency
-
4MHz
32kHz
100kHz
32kHz
Value
Unit
Typ*1 Max*2
0.33
1.8
mA
-
15
mA
-
22
mA
0.70
2.2
mA
-
16
mA
-
22
mA
0.33
1.8
mA
-
15
mA
-
22
mA
0.34
1.8
mA
-
15
mA
-
22
mA
0.33
1.8
mA
-
15
mA
-
22
mA
Remarks
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3V
*2: VCC=5.5V
*3: When all ports are fixed.
*4: When LVD is off
80
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
Parameter Symbol
Pin
name
Conditions
Frequency
Deep standby
STOP mode
(When RAM
is off)
ICCHD
Value
Typ*1 Max*2
Unit
29
140
μA
-
644
μA
-
1011
μA
48
273
μA
-
2676
μA
-
4162
μA
29
140
μA
-
644
μA
-
1011
μA
48
273
μA
-
2676
μA
-
4162
μA
0.015
0.29
μA
-
5.77
μA
-
10.6
μA
1.53
22.6
μA
-
35.2
μA
-
41.8
μA
Deep standby
STOP mode
(When RAM
is on)
VCC
Power
supply
current
Deep standby
RTC mode
(When RAM
is off)
ICCRD
32kHz
Deep standby
RTC mode
(When RAM
is on)
RTC stop
ICCVBAT
VBAT
RTC
operation
Remarks
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4, *5
Ta=+25°C
*3, *4, *5
Ta=+85°C
*3, *4, *5
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3V
*2: VCC=5.5V
*3: When all ports are fixed.
*4: When LVD is off
*5: When sub oscillation is OFF
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
81
r1.0
MB9B460R Series
Parameter
Low-voltage
detection
circuit (LVD)
power supply
current
Symbol Pin name Conditions
ICCLVD
Main flash
memory
write/erase
current
ICCFLASH
Work flash
memory
write/erase
current
ICCWFLASH
VCC
Peripheral current dissipation
Clock
Peripheral
system
HCLK
PCLK1
PCLK2
Min
Value
Typ Max
Remarks
For occurrence of
interrupt
At operation
-
4
7
μA
At
Write/Erase
-
13.4
15.9
mA
At
Write/Erase
-
11.5
13.6
mA
Unit
Frequency (MHz)
40
80
160
Unit
mA
GPIO
All ports
0.22
0.43
0.85
DMAC
-
0.74
1.48
2.88
DSTC
-
0.32
0.61
1.17
External bus I/F
-
0.14
0.27
0.55
SD card I/F
-
0.93
1.81
3.63
CAN
1ch.
0.02
0.06
0.11
Base timer
4ch.
0.16
0.34
0.66
1unit/4ch.
0.55
1.09
2.17
1unit
0.04
0.09
0.17
A/DC
1unit
0.20
0.39
0.78
Muli-function serial
1ch.
0.31
0.62
-
Multi-functional
timer/PPG
Quadrature
position/Revolution
counter
Unit
Remarks
mA
82
FUJITSU SEMICONDUCTOR CONFIDENTIAL
mA
DS709-00002-1v0-E
r1.0
MB9B460R Series
(2) Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter Symbol Pin name
"H" level
input voltage
(hysteresis
input)
"L" level input
voltage
(hysteresis
input)
VIHS
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as
I2C Fm+
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as
I2C Fm+
4mA type
VOH
8mA type
"H" level
output voltage
12mA type
The pin
doubled as
I2C Fm+
Min
Value
Typ
Max
-
VCC×0.8
-
VCC + 0.3
V
-
VCC×0.8
-
VSS + 5.5
V
-
VCC×0.7
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS
-
VCC×0.3
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
Conditions
VCC ≥ 4.5 V,
IOH = - 4mA
VCC < 4.5 V,
IOH = - 2mA
VCC ≥ 4.5 V,
IOH = - 8mA
VCC < 4.5 V,
IOH = - 4mA
VCC ≥ 4.5 V,
IOH = - 12mA
VCC < 4.5 V,
IOH = - 8mA
VCC ≥ 4.5 V,
IOH = - 4mA
VCC < 4.5 V,
IOH = - 3mA
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Unit Remarks
At GPIO
83
r1.0
MB9B460R Series
Parameter Symbol Pin name
4mA type
8mA type
"L" level
output voltage
VOL
12mA
type
The pin
doubled as
I2C Fm+
Input leak
current
Pull-up
resistor value
Input
capacitance
Conditions
VCC ≥ 4.5 V,
IOL = 4mA
VCC < 4.5 V,
IOL = 2mA
VCC ≥ 4.5 V,
IOH = 8mA
VCC < 4.5 V,
IOH = 4mA
VCC ≥ 4.5 V,
IOL = 12mA
VCC < 4.5 V,
IOL = 8mA
VCC ≥ 4.5 V,
IOH = 4mA
VCC < 4.5 V,
IOH = 3mA
VCC ≤ 5.5 V,
IOH = 20mA
Min
Value
Typ
Max
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
Unit Remarks
V
At I2C
Fm+
IIL
-
-
-5
-
+5
μA
RPU
Pull-up pin
VCC ≥ 4.5 V
VCC < 4.5 V
25
30
50
80
100
200
kΩ
CIN
Other than
VCC,
VBAT,
VSS,
AVCC,
AVSS,
AVRH
-
-
5
15
pF
84
FUJITSU SEMICONDUCTOR CONFIDENTIAL
At
GPIO
DS709-00002-1v0-E
r1.0
MB9B460R Series
4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Pin
Conditions
name
FCH
tCYLH
X0,
X1
tCF,
tCR
Value
Min
Max
Unit
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
PWH/tCYLH,
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
MHz
MHz
ns
Remarks
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
When using external
clock
Base clock
(HCLK/FCLK)
Internal operating
F
80
MHz
APB0 bus clock*2
CP0
clock*1 frequency
FCP1
160
MHz APB1 bus clock*2
FCP2
80
MHz APB2 bus clock*2
Base clock
tCYCC
6.25
ns
(HCLK/FCLK)
Internal operating
t
12.5
ns
APB0 bus clock*2
CYCP0
clock*1 cycle time
tCYCP1
6.25
ns
APB1 bus clock*2
tCYCP2
12.5
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter:Clock" in "FM4 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data
sheet.
FCC
-
-
-
160
MHz
X0
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
85
r1.0
MB9B460R Series
(2) Sub Clock Input Characteristics
(VBAT = 2.7V to 5.5V, VSS = 0V)
Parameter
Pin
Conditions
name
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
tCYLL
-
10
-
31.25
μs
-
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
Symbol
1/
tCYLL
Input frequency
X0A,
X1A
Input clock cycle
Input clock pulse width
0.8 × VBAT
Unit
VBAT
X0A
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
VBAT
VBAT
VBAT
(3) Built-in CR Oscillation Characteristics
・ Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Symbol
FCRH
Conditions
Value
Min Typ Max
Tj = -20°C to + 105°C
3.92
4
4.08
Tj = - 40°C to + 125°C
3.88
4
4.12
Unit
Remarks
When trimming*
MHz
When not
trimming
*: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
Clock frequency
FCRH
Tj = - 40°C to + 125°C
3
4
5
・ Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Symbol
Condition
FCRL
-
86
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Min
50
Value
Typ Max
100
150
Unit
Remarks
kHz
DS709-00002-1v0-E
r1.0
MB9B460R Series
(4-1) Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*1
tLOCK
200
μs
(LOCK UP time)
PLL input clock frequency
FPLLI
4
16
MHz
PLL multiplication rate
13
80 multiplier
PLL macro oscillation clock frequency
FPLLO
200
320
MHz
Main PLL clock frequency*2
FCLKPLL
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family
PERIPHERAL MANUAL".
(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input
clock of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Min
Unit
Remarks
Typ Max
PLL oscillation stabilization wait time*1
tLOCK
200
μs
(LOCK UP time)
PLL input clock frequency
FPLLI
3.8
4
4.2
MHz
PLL multiplication rate
50
75 multiplier
PLL macro oscillation clock frequency
FPLLO
190
320
MHz
Main PLL clock frequency*2
FCLKPLL
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency
and temperature has been trimmed.
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Reset input time
Symbol
Pin
name
Condition
tINITX
INITX
-
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Value
Min
Max
500
-
Unit Remarks
ns
87
r1.0
MB9B460R Series
(6) Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Power supply rising
time
Power supply shut
down time
Time until releasing
Power-on reset
Value
Pin
name
Tr
Toff
VCC
Tprt
Unit
Min
Max
0
-
ms
1
-
ms
0.33
0.60
ms
Remarks
VCC_minimum
VCC
VDL_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
Toff
RST Active
Release
CPU Operation
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions.
・ VDL_minimum : Minimum detection voltage of Low-Voltage detection reset.
See "8. Low-Voltage Detection Characteristics".
(7) GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Symbol
Pin name
Conditions
tPCYCLE
Pxx*
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
-
50
32
Unit
MHz
MHz
*: GPIO is a target.
Pxx
tPCYCLE
88
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
(8) External Bus Timing
・ External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
VCC ≥ 4.5 V
50*2
MHz
VCC < 4.5 V
32*3
MHz
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see "Chapter: External Bus Interface" in "FM4 Family
PERIPHERAL MANUAL".
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz.
Output frequency
tCYCLE
MCLKOUT*1
0.8 × Vcc
0.8 × Vcc
MCLK
tCYCLE
・ External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Signal input characteristics
Signal output characteristics
Symbol
Conditions
VIH
VIL
VOH
-
VOL
Signal input
VIH
VIL
VIH
VIL
Signal output
VOH
VOL
VOH
VOL
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
89
r1.0
MB9B460R Series
・ Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
VCC ≥ 4.5V
MOEX
tOEW
MOEX
MCLK×n-3
Mininum pulse width
VCC < 4.5V
VCC ≥ 4.5V
-9
MCSX↓→Address
MCSX[7:0],
tCSL – AV
output delay time
MAD[24:0]
VCC < 4.5V
-12
VCC ≥ 4.5V
MOEX↑→Address
MOEX,
tOEH - AX
0
hold time
MAD[24:0]
VCC < 4.5V
VCC ≥ 4.5V
MCLK×m-9
MCSX↓→
tCSL - OEL
MOEX↓ delay time
VCC < 4.5V
MCLK×m-12
MOEX,
MCSX[7:0]
VCC ≥ 4.5V
MOEX↑→
tOEH - CSH
0
MCSX↑ time
VCC < 4.5V
VCC ≥ 4.5V
MCLK×m-9
MCSX↓→MDQM↓
MCSX,
tCSL - RDQML
delay time
MDQM[1:0]
VCC < 4.5V
MCLK×m-12
VCC ≥ 4.5V
20
Data set up→MOEX↑
MOEX,
tDS - OE
time
MADATA[15:0]
VCC < 4.5V
38
VCC ≥ 4.5V
MOEX↑→
MOEX,
tDH - OE
0
Data hold time
MADATA[15:0]
VCC < 4.5V
VCC ≥ 4.5V
MWEX
tWEW
MWEX
MCLK×n-3
Mininum pulse width
VCC < 4.5V
VCC ≥ 4.5V
MWEX↑→Address
MWEX,
tWEH - AX
0
output delay time
MAD[24:0]
VCC < 4.5V
VCC ≥ 4.5V
MCLK×n-9
MCSX↓→MWEX↓
tCSL - WEL
delay time
VCC < 4.5V
MCLK×n-12
MWEX,
MCSX[7:0]
VCC ≥ 4.5V
MWEX↑→MCSX↑
tWEH - CSH
0
delay time
VCC < 4.5V
VCC ≥ 4.5V
MCLK×n-9
MCSX↓→MDQM↓
MCSX,
tCSL-WDQML
delay time
MDQM[1:0]
VCC < 4.5V
MCLK×n-12
VCC ≥ 4.5V
MCLK-9
MCSX↓→
MCSX,
tCSL-DX
Data output time
MADATA[15:0]
VCC < 4.5V
MCLK-12
VCC ≥ 4.5V
MWEX↑→
MWEX,
tWEH - DX
0
Data hold time
MADATA[15:0]
VCC < 4.5V
Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16)
90
FUJITSU SEMICONDUCTOR CONFIDENTIAL
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
DS709-00002-1v0-E
r1.0
MB9B460R Series
tCYCLE
MCLK
tOEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tWEH-CSH
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DX
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
91
r1.0
MB9B460R Series
・ Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK,
MAD[24:0]
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
tCSL
MCLK,
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK,
MOEX
MOEX delay time
tREH
Data set up
→MCLK↑ time
MCLK↑→
Data hold time
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
tDS
tDH
tWEL
MCLK,
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
tDQMH
MCLK,
MDQM[1:0]
MCLK↑→
MCLK,
tODS
Data output time
MADATA[15:0]
MCLK↑→
MCLK,
tOD
Data hold time
MADATA[15:0]
Note: When the external load capacitance CL = 30pF
Value
Min
1
1
1
1
1
Max
9
12
9
12
9
12
9
12
9
12
Unit
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
tCYCLE
MCLK
MCSX[7:0]
tCSL
MAD[24:0]
tAV
tCSH
tAV
Address
MOEX
MDQM[1:0]
Address
tREL
tREH
tDQML
tDQMH
MWEX
tDS
MADATA[15:0]
tDQML
tDQMH
tWEL
tWEH
tDH
RD
tOD
WD
Invalid
tODS
92
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
・ Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
0
10
20
VCC ≥ 4.5V
MCLK×n+0
MCLK×n+10
VCC < 4.5V
MCLK×n+0
Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16)
MCLK×n+20
Multiplexed address
delay time
tALE-CHMADV
Multiplexed address
hold time
tCHMADH
MALE,
MADATA[15:0]
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
93
r1.0
MB9B460R Series
・ Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK↑→
Multiplexed address
delay time
tCHMADV
MCLK↑→
Multiplexed data
output time
tCHMADX
Pin name
Conditions
MCLK,
ALE
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Min
Value
Max
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
VCC ≥ 4.5V
MCLK,
MADATA[15:0]
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Note: When the external load capacitance CL = 30pF
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
94
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
・ NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5V
MNREX
tNREW
MNREX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
20
Data set up
MNREX,
tDS – NRE
→MNREX↑ time
MADATA[15:0] VCC < 4.5V
38
VCC ≥ 4.5V
MNREX↑→
MNREX,
tDH – NRE
0
Data hold time
MADATA[15:0] VCC < 4.5V
VCC ≥ 4.5V MCLK×m-9
MNALE↑→
MNALE,
tALEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V MCLK×m-9
MNALE↓→
MNALE,
tALEL - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V MCLK×m-9
MNCLE↑→
MNCLE,
tCLEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5V MCLK×m-12
VCC ≥ 4.5V
MNWEX↑→
MNCLE,
tNWEH - CLEL
0
MNCLE delay time
MNWEX
VCC < 4.5V
VCC ≥ 4.5V
MNWEX
tNWEW
MNWEX
MCLK×n-3
Min pulse width
VCC < 4.5V
VCC ≥ 4.5V
-9
MNWEX↓→
MNWEX,
tNWEL – DV
Data output time
MADATA[15:0] VCC < 4.5V
-12
VCC ≥ 4.5V
MNWEX↑→
MNWEX,
tNWEH – DX
0
Data hold time
MADATA[15:0] VCC < 4.5V
Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16)
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Max
Unit
-
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
+9
+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
95
r1.0
MB9B460R Series
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
96
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Read
DS709-00002-1v0-E
r1.0
MB9B460R Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Write
97
r1.0
MB9B460R Series
・ External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MCLK↑
MRDY input
setup time
Symbol
tRDYI
Pin name Conditions
MCLK,
MRDY
Value
Min
VCC ≥ 4.5V
19
VCC < 4.5V
37
Max
-
Unit Remarks
ns
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycle
Extended
MOEX
MWEX
MRDY
tRDYI
0.5×VCC
98
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
・ SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Output frequency
Symbol
tCYCSD
Pin name
MSDCLK
MSDCLK,
Address delay time
tAOSD
MAD[15:0]
MSDCLK↑→Data output
MSDCLK,
tDOSD
delay time
MADATA[31:0]
MSDCLK↑→Data output
MSDCLK,
tDOZSD
Hi-Z time
MADATA[31:0]
MSDCLK,
MDQM[1:0] delay time
tWROSD
MDQM[1:0]
MSDCLK,
MCSX delay time
tMCSSD
MCSX8
MSDCLK,
MRASX delay time
tRASSD
MRASX
MSDCLK,
MCASX delay time
tCASSD
MCASX
MSDCLK,
MSDWEX delay time
tMWESD
MSDWEX
MSDCLK,
MSDCKE delay time
tCKESD
MSDCKE
MSDCLK,
Data set up time
tDSSD
MADATA[31:0]
MSDCLK,
Data hold time
tDHSD
MADATA[31:0]
Note: When the external load capacitance CL = 30pF
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Value
Unit
Min
Max
-
32
MHz
2
12
ns
2
12
ns
2
20
ns
1
12
ns
2
12
ns
2
12
ns
2
12
ns
2
12
ns
2
12
ns
23
-
ns
0
-
ns
99
r1.0
MB9B460R Series
SDRAM Access
tCYCSD
MSDCLK
tAOSD
Address
MAD[24:0]
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
MADATA[15:0]
tDHSD
RD
tDOSD
MADATA[15:0]
100
FUJITSU SEMICONDUCTOR CONFIDENTIAL
tDOZSD
WD
DS709-00002-1v0-E
r1.0
MB9B460R Series
(9) Base Timer Input Timing
・ Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
・ Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see " BLOCK DIAGRAM" in this
data sheet.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
101
r1.0
MB9B460R Series
(10) UART Timing
・ Synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
tSLOVI
SIN→SCK↑
setup time
tIVSHI
SCK↑→SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK↓→SOT delay time
tSLOVE
SIN→SCK↑
setup time
tIVSHE
SCK↑→SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock operation
SINx
SCKx,
SINx
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Unit
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tCYCP 10
tCYCP +
10
SCKx,
External shift
SOTx
clock
SCKx,
operation
SINx
SCKx,
SINx
SCKx
SCKx
-
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
102
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
SCK
VIH
tF
SOT
SIN
tSHSL
VIL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
103
r1.0
MB9B460R Series
・ Synchronous serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
setup time
tIVSLI
SCK↓→SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK↑→SOT delay time
tSHOVE
SIN→SCK↓
setup time
tIVSLE
SCK↓→SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
Conditions
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock operation
SINx
SCKx,
SINx
SCKx,
SOTx External shift
SCKx, clock operation
SINx
SCKx,
SINx
SCKx
SCKx
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Unit
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
104
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
VIL
tR
SOT
tSLSH
VIH
VIH
VIL
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
VIH
VIL
SIN
tSLIXE
VIH
VIL
MS bit = 1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
105
r1.0
MB9B460R Series
・ Synchronous serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
Conditions
name
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Unit
Min
Max
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock operation
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
setup time
tIVSLI
SCK↓→SIN hold time
tSLIXI
SOT→SCK↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK↑→SOT delay time
tSHOVE
SIN→SCK↓
setup time
tIVSLE
SCK↓→SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
tF
tR
SCKx,
SOTx External shift
SCKx, clock operation
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
106
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
SOT
VOL
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
107
r1.0
MB9B460R Series
・ Synchronous serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
tSLOVI
SIN→SCK↑
setup time
tIVSHI
SCK↑→SIN hold time
tSHIXI
SOT→SCK↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK↓→SOT delay time
tSLOVE
SIN→SCK↑
setup time
tIVSHE
SCK↑→SIN hold time
tSHIXE
SCK falling time
SCK rising time
Notes:
tF
tR
Conditions
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock operation
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx External shift
SCKx, clock operation
SINx
SCKx,
SINx
SCKx
SCKx
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Unit
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
108
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIH
VIL
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
109
r1.0
MB9B460R Series
・ When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
SCS↓→SUT delay time
SCS↑→SUT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
110
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
SCS
output
tCSDI
tCSSI
tCSHI
tCSSE
tCSHE
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
111
r1.0
MB9B460R Series
・ When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
SCS↓→SOT delay time
SCS↑→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
112
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
SCS
output
tCSDI
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
113
r1.0
MB9B460R Series
・ When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
SCS↑→SOT delay time
SCS↓→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
114
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
tCSDI
SCS
output
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
SCS
input
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
115
r1.0
MB9B460R Series
・ When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
SCS↑→SOT delay time
SCS↓→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
(*1)-50
(*1)+0
(*2)+0
(*2)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
3tCYCP+30
0
3tCYCP+30
40
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
116
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
tCSDI
SCS
output
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
117
r1.0
MB9B460R Series
・ High-speed synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCKx
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
tSLSH
SCKx
tSHSL
SCKx
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
SCK↑→SIN hold time
tSHIXE
Parameter
Serial clock "L" pulse
width
Serial clock "H" pulse
width
SCK falling time
SCK rising time
Notes:
tF
tR
Conditions
Internal shift
clock
operation
VCC < 4.5V
Min
Max
SCKx,
SINx
SCKx
SCKx
Unit
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
14
12.5*
-
12.5
-
ns
5
-
5
-
ns
-
ns
-
ns
2tCYCP
–5
tCYCP
+ 10
External shift
clock
operation
VCC ≥ 4.5V
Min
Max
-
2tCYCP
–5
tCYCP
+ 10
-
15
-
15
ns
5
-
5
-
ns
5
-
5
-
ns
-
5
5
-
5
5
ns
ns
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the following pins.
No chip select : SIN4_1, SOT4_1, SCK4_1
Chip select
: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
118
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
SCK
VIH
tF
SOT
SIN
tSHSL
VIL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
119
r1.0
MB9B460R Series
・ High-speed synchronous serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCKx
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
Serial clock "L" pulse
width
Parameter
Conditions
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
Unit
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
14
12.5*
-
12.5
-
ns
SCKx,
SINx
5
-
5
-
ns
tSLSH
SCKx
2tCYCP
–5
-
2tCYCP
–5
-
ns
Serial clock "H" pulse
width
tSHSL
SCKx
tCYCP
+ 10
-
tCYCP
+ 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
tF
tR
SCKx
SCKx
-
5
5
-
5
5
ns
ns
SCK falling time
SCK rising time
Notes:
Internal shift
clock
operation
External shift
clock
operation
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the following pins.
No chip select : SIN4_1, SOT4_1, SCK4_1
Chip select
: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
120
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
VIL
tR
SOT
tSLSH
VIH
VIH
VIL
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
VIH
VIL
SIN
tSLIXE
VIH
VIL
MS bit = 1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
121
r1.0
MB9B460R Series
・ High-speed synchronous serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
14
12.5*
-
12.5
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP
– 10
-
2tCYCP
– 10
-
ns
Serial clock "L" pulse
width
tSLSH
SCKx
2tCYCP
–5
-
2tCYCP
–5
-
ns
Serial clock "H" pulse
width
tSHSL
SCKx
tCYCP
+ 10
-
tCYCP
+ 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
tF
tR
SCKx
SCKx
-
5
5
-
5
5
ns
ns
Parameter
SCK falling time
SCK rising time
Notes:
Conditions
Internal shift
clock
operation
External shift
clock
operation
Unit
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the following pins.
No chip select : SIN4_1, SOT4_1, SCK4_1
Chip select
: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
122
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
SOT
VOL
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
123
r1.0
MB9B460R Series
・ High-speed synchronous serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
Symbol
Pin
name
Internal shift clock
operation
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
14
12.5*
-
12.5
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP
– 10
-
2tCYCP
– 10
-
ns
Serial clock "L" pulse
width
tSLSH
SCKx
2tCYCP
–5
-
2tCYCP
–5
-
ns
Serial clock "H" pulse
width
tSHSL
SCKx
tCYCP
+ 10
-
tCYCP
+ 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
tF
tR
SCKx
SCKx
-
5
5
-
5
5
ns
ns
Parameter
SCK falling time
SCK rising time
Notes:
Conditions
Internal shift
clock
operation
External shift
clock
operation
Unit
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
These characteristics only guarantee the following pins.
No chip select : SIN4_1, SOT4_1, SCK4_1
Chip select
: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
124
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIH
VIL
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
125
r1.0
MB9B460R Series
・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
SCS↓→SOT delay time
SCS↑→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Conditions
Internal shift
clock
operation
External shift
clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
126
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
SCS
output
tCSDI
tCSSI
tCSHI
tCSSE
tCSHE
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
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127
r1.0
MB9B460R Series
・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
SCS↓→SOT delay time
SCS↑→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
128
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
SCS
output
tCSDI
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
129
r1.0
MB9B460R Series
・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
SCS↑→SOT delay time
SCS↓→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Conditions
Internal shift
clock
operation
External shift
clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
130
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
tCSDI
SCS
output
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
SCS
input
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
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131
r1.0
MB9B460R Series
・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
SCS↑→SOT delay time
SCS↓→SOT delay time
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Internal shift
clock
operation
External
shift clock
operation
VCC < 4.5V
Min
Max
VCC ≥ 4.5V
Min
Max
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
(*1)-20
(*1)+0
(*2)+0
(*2)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
3tCYCP+15
0
3tCYCP+15
25
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data
sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
132
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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MB9B460R Series
tCSDI
SCS
output
tCSSI
tCSHI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
133
r1.0
MB9B460R Series
・ External clock (EXT = 1) : when in asynchronous mode only
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
tR
SCK
VIL
Condition
CL = 30pF
Value
Min
Max
tCYCP + 10
tCYCP + 10
-
tSHSL
VIH
134
FUJITSU SEMICONDUCTOR CONFIDENTIAL
5
5
VIL
Remarks
ns
ns
ns
ns
tF
tSLSH
VIH
Unit
VIL
VIH
DS709-00002-1v0-E
r1.0
MB9B460R Series
(11) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol
Pin name
Conditions
Value
Unit
Min
Max
Remarks
A/D converter trigger
input
2tCYCP*1
ns
Free-run timer input
FRCKx
clock
Input pulse
tINH,
ICxx
Input capture
width
tINL
1
DTTIxX
2tCYCP*
ns
Waveform generator
2tCYCP + 100*1 ns
INT00 to INT31,
External interrupt,
NMIX
NMI
500*2
ns
WKUPx
500*3
ns
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "BLOCK DIAGRAM" in this data sheet.
*2: When in STOP mode, in timer mode.
*3: When in deep standby RTC mode, in deep standby STOP mode.
ADTG
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
135
r1.0
MB9B460R Series
(12) Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Conditions
Min
Max
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
BIN rising time from
PC_Mode2 or
tAUBU
AIN pin "H" level
PC_Mode3
AIN falling time from
PC_Mode2 or
tBUAD
BIN pin "H" level
PC_Mode3
BIN falling time from
PC_Mode2 or
tADBD
AIN pin "L" level
PC_Mode3
AIN rising time from
PC_Mode2 or
tBDAU
BIN pin "L" level
PC_Mode3
AIN rising time from
PC_Mode2 or
tBUAU
BIN pin "H" level
PC_Mode3
2tCYCP*
BIN falling time from
PC_Mode2 or
tAUBD
AIN pin "H" level
PC_Mode3
AIN falling time from
PC_Mode2 or
tBDAD
BIN pin "L" level
PC_Mode3
BIN rising time from
PC_Mode2 or
tADBU
AIN pin "L" level
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rising and falling
time from determined ZIN
tZABE
QCR:CGSC="1"
level
Determined ZIN level from
AIN/BIN rising and falling
tABEZ
QCR:CGSC="1"
time
* : tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see
"BLOCK DIAGRAM" in this data sheet.
Unit
ns
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
136
FUJITSU SEMICONDUCTOR CONFIDENTIAL
tBLL
DS709-00002-1v0-E
r1.0
MB9B460R Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
137
r1.0
MB9B460R Series
2
(13) I C Timing
・Typical mode, high-speed mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCL clock frequency
(Repeated) START
condition hold time
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
(Repeated) START
condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup
time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Symbol
Conditions
Typical mode
High-speed
mode
Min
Max
Unit Remarks
Min
Max
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
tHDDAT
CL = 30pF,
R = (Vp/IOL)*1
2MHz ≤
2tCYCP*4
2tCYCP*4
ns
tCYCP<40MHz
40MHz ≤
4tCYCP*4
4tCYCP*4
ns
tCYCP<60MHz
60MHz ≤
6tCYCP*4
6tCYCP*4
ns
tCYCP<80MHz
80MHz ≤
8tCYCP*4
8tCYCP*4
ns
tCYCP<100MHz
Noise filter
tSP
*5
100MHz ≤
10tCYCP*4
10tCYCP*4
ns
tCYCP<120MHz
120MHz ≤
12tCYCP*4
12tCYCP*4
ns
tCYCP<140MHz
140MHz ≤
14tCYCP*4
14tCYCP*4
ns
tCYCP<160MHz
160MHz ≤
16tCYCP*4
16tCYCP*4
ns
tCYCP<180MHz
*1 : R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : A high-speed mode I2C bus device can be used on a typical mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
*5 : The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
138
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
・Fast mode plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Symbol
Conditions
Fast mode plus
(Fm+)*6
Min
Max
Unit Remarks
FSCL
0
1000
kHz
tHDSTA
0.26
-
μs
tLOW
tHIGH
tSUSTA
0.5
0.26
0.26
-
μs
μs
μs
0
0.45*2, *3
μs
tSUDAT
50
-
ns
tSUSTO
0.26
-
μs
tBUF
0.5
-
μs
tHDDAT
CL = 30pF,
R = (Vp/IOL)*1
60MHz ≤
6 tCYCP*4
ns
tCYCP<80MHz
80MHz ≤
8 tCYCP*4
ns
tCYCP<100MHz
100MHz ≤
10 tCYCP*4
ns
tCYCP<120MHz
Noise filter
tSP
*5
120MHz ≤
12 tCYCP*4
ns
tCYCP<140MHz
140MHz ≤
14 tCYCP*4
ns
tCYCP<160MHz
160MHz ≤
16 tCYCP*4
ns
tCYCP<180MHz
*1 : R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : A high-speed mode I2C bus device can be used on a typical mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5 : The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6 : When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I 2C Fm+ in the EPFR
register. See "CHAPTER: I/O PORT" in "FM4 Family PERIPHERAL MANUAL" for the details.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
139
r1.0
MB9B460R Series
SDA
SCL
140
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
(14) SD Card Interface Timing
・Default-Speed Mode
・ Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol Pin name Conditions
Value
Min
Remarks
Max
Clock frequency Data
fPP
S_CLK
0
16
MHz
Transfer Mode
Clock frequency
fOD
S_CLK
0*/100
400
kHz
CCARD ≤
Identification Mode
10pF
Clock low time
tWL
S_CLK
10
ns
(1card)
Clock high time
tWH
S_CLK
10
ns
Clock rising time
tTLH
S_CLK
10
ns
Clock falling time
tTHL
S_CLK
10
ns
*: 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is
required.
・ Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol Pin name Conditions
Input set-up time
tISU
Input hold time
tIH
S_CMD,
S_DATA3:0
S_CMD,
S_DATA3:0
Value
Remarks
Min
Max
5
-
ns
5
-
ns
CCARD ≤
10pF
(1card)
・ Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol Pin name Conditions
Output Delay time during
Data Transfer Mode
Output Delay time durinn
Identification Mode
tODLY
tODLY
S_CMD,
S_DATA3:0
S_CMD,
S_DATA3:0
Value
Max
0
22
ns
0
50
ns
CCARD ≤
40pF
(1card)
tWH
tWL
S_CLK
(SD Clock)
VIH
tTHL
S_CMD,
S_DATA3:0
(Card Input)
S_CMD,
S_DATA3:0
(Card Output)
Remarks
Min
VIL
VIL
tISU
VIH
VIH
tTLH
tIH
VIH
VIH
VIL
VIL
tODLY(Max)
tODLY(Min)
VOH
VOH
VOL
VOL
Defalt-Speed Mode
Note: The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because
this model is the Host.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
141
r1.0
MB9B460R Series
・High-Speed Mode
・ Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Clock frequency Data
Transfer Mode
Clock low time
Clock high time
Clock rising time
Clock falling time
Value
Symbol Pin name Conditions
fPP
Max
0
32
MHz
7
7
-
3
3
ns
ns
ns
ns
S_CLK
tWL
tWH
tTLH
tTHL
CCARD ≤
10pF
(1card)
S_CLK
S_CLK
S_CLK
S_CLK
Remarks
Min
・ Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Value
Symbol Pin name Conditions
Input set-up time
tISU
Input hold time
tIH
S_CMD,
S_DATA3:0
S_CMD,
S_DATA3:0
Remarks
Min
Max
8
-
ns
2
-
ns
CCARD ≤
10pF
(1card)
・ Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Output Delay time during
Data Transfer Mode
Output Hold time
Value
Symbol Pin name Conditions
tODLY
tOH
Max
-
22
ns
2.5
-
ns
-
40
pF
CL ≤ 40pF
(1card)
CL ≥ 15pF
(1card)
S_CMD,
S_DATA3:0
S_CMD,
S_DATA3:0
Total System capacitance for
CL
1card
each line*
*: In order to satisfy severe timing, host shall drive only one card.
tWH
tWL
S_CLK
(SD Clock)
S_CMD,
S_DATA3:0
(Card Input)
S_CMD,
S_DATA3:0
(Card Output)
50%VCC
VIH
tTHL
VIH
VIL
VIL
50%VCC
tTLH
tISU
tODLY(Max)
Remarks
Min
VIH
tIH
VIH
VIH
VIL
VIL
tOH(Min)
VOH
VOH
VOL
VOL
High-Speed Mode
Notes: ・The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input
because this model is the Host.
・In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same
values.
142
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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MB9B460R Series
(15) ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Value
Min
Max
Symbol
Pin name
Conditions
Data hold
tETMH
TRACECLK,
TRACED[3:0]
VCC ≥ 4.5V
2
9
VCC < 4.5V
2
15
TRACECLK
frequency
1/
tTRACE
VCC ≥ 4.5V
-
50
MHz
VCC < 4.5V
-
32
MHz
VCC ≥ 4.5V
20
-
ns
VCC < 4.5V
31.25
-
ns
TRACECLK
TRACECLK
clock cycle
tTRACE
Unit
Remarks
ns
Note: When the external load capacitance CL= 30pF.
HCLK
TRACECLK
TRACED[3:0]
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
143
r1.0
MB9B460R Series
(16) JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI hold time
tJTAGH
TMS, TDI
TCK,
TDO delay time
tJTAGD
TDO
Note: When the external load capacitance CL= 30pF.
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
TMS, TDI setup time
Symbol
tJTAGS
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
45
ns
Remarks
TCK
TMS/TDI
TDO
144
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
5. 12-bit A/D Converter
・Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter
Symbol
Pin
name
Min
Value
Typ
Max
Resolution
Integral
Nonlinearity
Differential
Nonlinearity
Zero transition
voltage
Full-scale transition
voltage
Conversion time
-
-
-
-
12
bit
-
-
- 4.5
-
+ 4.5
LSB
-
-
-2.5
-
+ 2.5
LSB
-
+ 15
mV
-
AVRH + 15
mV
-
-
μs
10
μs
1000
1000
ns
VZT
VFST
-
AN00 to
- 15
AN23
AN00 to
AVRH - 15
AN23
0.5*1
Sampling time
Ts
-
Compare clock
cycle*3
Tcck
-
*2
*2
25
50
-
Unit
Remarks
AVRH = 2.7V
to 5.5V
AVCC ≥ 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
State transition time
to operation
Tstt
1.0
μs
permission
A/D 1unit
Power supply
0.69
0.92
mA
operation
current (analog +
AVCC
digital)
1.0
18
μA When A/D stop
A/D 1unit
Reference power
1.1
1.97
mA operation
supply current
AVRH
AVRH=5.5V
(between AVRH and
AVSS)
0.3
6.3
μA When A/D stop
Analog input
CAIN
12.05
pF
capacity
1.2
AVCC ≥ 4.5V
Analog input
RAIN
kΩ
resistance
1.8
AVCC < 4.5V
Interchannel
4
LSB
disparity
Analog port input
AN00 to
5
μA
current
AN23
Analog input
AN00 to
AVSS
AVRH
V
voltage
AN23
Reference voltage
AVRH
2.7
AVCC
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of
compare time: 350ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare
clock cycle (Tcck). For setting*4 of sampling time and compare clock cycle, see "Chapter: A/D Converter" in
"FM4 Family PERIPHERAL MANUAL Analog Macro Part". The register setting of the A/D Converter is
reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy
(Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock
and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is
connected to, see "BLOCK DIAGRAM" in this data sheet.
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145
r1.0
MB9B460R Series
Analog
signal source
Rext
AN00 ~ AN23
Analog input pin
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : Input resistance of A/D = 1.2kΩ at 4.5V < AVCC < 5.5V
Input resistance of A/D = 1.8kΩ at 2.7V < AVCC < 4.5V
CAIN : Input capacity of A/D = 12.05pF at 2.7V < AVCC < 5.5V
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
146
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
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・Definition of 12-bit A/D Converter Terms
・ Resolution
・ Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
・ Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Differential Nonlinearity
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
VNT
(Actually-measured
value)
0x(N-2)
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
:
:
:
:
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
1LSB =
N
VZT
VFST
VNT
AVRH
Analog input
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
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147
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MB9B460R Series
6. 12-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7Vto5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Resolution
Integral Nonlinearity*
Differential
Nonlinearity*
INL
Output voltage offset
Analog output
impedance
Power supply current*
Pin
name
DNL
DAx
VOFF
RO
IDDA
AVCC
Min
Value
Typ Max
Unit
- 16
-
12
+ 16
bit
LSB
- 0.98
-
+ 1.5
LSB
- 20.0
3.10
2.0
3.80
-
10.0
+ 1.4
4.50
-
mV
mV
kΩ
MΩ
260
330
410
μA
400
510
620
μA
-
-
14
μA
IDSA
Remarks
When setting 0x000
When setting 0xFFF
D/A operation
When D/A stop
D/A 1unit operation
AVCC=3.3V
D/A 1unit operation
AVCC=5.0V
When D/A stop
*: During no load
148
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
7. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
Parameter
Detected voltage
Released voltage
Min
Value
Typ
Max
2.25
2.30
2.45
2.50
2.65
2.70
Min
Value
Typ
Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
4480×
tCYCP*
μs
Symbol Conditions
VDL
VDH
-
Unit
V
V
Remarks
When voltage drops
When voltage rises
(2) Interrupt of Low-Voltage Detection
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
SVHI = 00111
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
SVHI = 11000
-
Unit
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
149
r1.0
MB9B460R Series
8. MainFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Parameter
Sector erase
time
Half word
(16-bit)
write time
Value
Typ
Max
-
0.7
0.3
3.7
1.1
-
12
Min
Large Sector
Small Sector
Write cycles
< 100 times
Write cycles
> 100 times
Chip erase time
Unit
Remarks
s
Includes write time prior to internal erase
μs
Not including system-level overhead time
s
Includes write time prior to internal erase
100
200
-
13.6
68
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C) .
9. WorkFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Min
Value
Typ
Max
Sector erase time
Half word (16-bit)
write time
-
0.3
-
Chip erase time
-
Parameter
Unit
Remarks
1.5
s
Includes write time prior to internal erase
20
200
μs
Not including system-level overhead time
1.2
6
s
Includes write time prior to internal erase
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C) .
150
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
10. Standby Recovery Time
(1) Recovery cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is shown.
・Recovery count time
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Sleep mode
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
Low-speed CR timer mode
Value
Typ
Unit
Max*
μs
HCLK×1
80
μs
450
900
μs
881
1136
μs
270
581
μs
240
480
308
667
μs
308
667
μs
40
Sub timer mode
RTC mode
stop mode
(High-speed CR /Main/PLL run mode return)
RTC mode
stop mode
(Low-speed CR/sub run mode return)
Ticnt
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
Remarks
without
RAM
retention
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
・Example of standby recovery operation (when in external interrupt recovery*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
151
r1.0
MB9B460R Series
・Example of standby recovery operation (when in internal resource interrupt recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes: ・The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM4 Family
PERIPHERAL MANUAL.
・When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM4
Family PERIPHERAL MANUAL".
152
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
(2) Recovery cause: Reset
The time from reset release to the program operation start is shown.
・Recovery count time
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Typ
Max*
Sleep mode
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
Low-speed CR timer mode
Sub timer mode
RTC mode
stop mode
Unit
111
267
μs
111
267
μs
258
569
μs
258
569
μs
258
569
μs
Remarks
Trcnt
μs
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
308
669
μs
without
RAM
retention
with RAM
retention
:
* The maximum value depends on the built-in CR accuracy.
・Example of standby recovery operation (when in INITX recovery)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Start
153
r1.0
MB9B460R Series
・Example of standby recovery operation (when in internal resource reset recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery
cause.
Notes: ・The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM4 Family
PERIPHERAL MANUAL.
・The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See
"(6) Power-on Reset Timing" in "4. AC Characteristics" in "ELECTRICAL CHARACTERISTICS"
for the detail on the time during the power-on reset/low-voltage detection reset.
・When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock
or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main
PLL clock stabilization wait time.
・The internal resource reset means the watchdog reset and the CSV reset.
154
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
ORDERING INFORMATION
Part number
Package
MB9BF468MPMC
MB9BF467MPMC
Plastic・LQFP (0.5mm pitch), 80 pin
(FPT-80P-M37)
MB9BF466MPMC
MB9BF468MPMC1
MB9BF467MPMC1
Plastic・LQFP (0.65mm pitch), 80 pin
(FPT-80P-M40)
MB9BF466MPMC1
MB9BF468NPMC
MB9BF467NPMC
Plastic・LQFP (0.5mm pitch), 100 pin
(FPT-100P-M23)
MB9BF466NPMC
MB9BF468RPMC
MB9BF467RPMC
Plastic・LQFP (0.5mm pitch), 120 pin
(FPT-120P-M37)
MB9BF466RPMC
MB9BF468NBGL
MB9BF467NBGL
Plastic・PFBGA (0.5mm pitch), 112 pin
(BGA-112P-M05)
MB9BF466NBGL
MB9BF468RBGL
MB9BF467RBGL
Plastic・PFBGA (0.5mm pitch), 144 pin
(BGA-144P-M09)
MB9BF466RBGL
MB9BF468NPQC
MB9BF467NPQC
Plastic・QFP (0.65mm pitch), 100 pin
(FPT-100P-M36)
MB9BF466NPQC
DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
155
r1.0
MB9B460R Series
PACKAGE DIMENSIONS
120-pin plastic LQFP
(FPT-120P-M37)
120-pin plastic LQFP
(FPT-120P-M37)
Lead pitch
0.50 mm
Package width ×
package length
16.0 mm × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16 × 16-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 ± 0.20(.709 ± .008) SQ
* 16.00 ± 0.10(.630 ± .004) SQ
90
61
91
Details of "A" part
60
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60 ± 0.15
(.024 ± .006)
"A"
LEAD No.
1
30
0.50(.020)
C
0.10 ± 0.05
(.004 ± .002)
(Stand off)
31
120
0.22 ± 0.05
(.009 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1
156
FUJITSU SEMICONDUCTOR CONFIDENTIAL
+0.05
0.145–0.03
( .006+.002
–.001 )
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
DS709-00002-1v0-E
r1.0
MB9B460R Series
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
26
"A"
1
C
0.60±0.15
(.024±.006)
25
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0°~8°
0.50±0.20
(.020±.008)
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS709-00002-1v0-E
157
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B460R Series
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14 × 20-0.65
(FPT-100P-M36)
100-pin plastic QFP
(FPT-100P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90± 0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32 ± 0.05
(.013±.002)
0.13(.005)
M
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
0.17 ± 0.06
(.007 ±. 002)
0.80 ± 0.20
(.031 ±. 008)
0.88 ± 0.15
(.035 ±. 006)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
Dimensions in mm (inches).
Note: The valuesin parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
158
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551 ± .008)SQ
*12.00± 0.10(.472 ± .004)SQ
60
0.145± 0.055
(.006 ± .002)
41
Details of "A" part
40
61
+0.20
1.50 –0.10
(Mounting height)
–.004
.059 +.008
0.25(.010)
0~8°
0.08(.003)
INDEX
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.05
(.004 ± .002)
(Stand off)
21
80
"A"
1
20
0.50(.020)
0.22± 0.05
(.009± .002)
C
0.08(.003)
M
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS709-00002-1v0-E
159
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B460R Series
80-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
Details of "A" part
40
61
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
21
80
0.65(.026)
C
0.60±0.15
(.024±.006)
20
1
0.32±0.06
(.013±.002)
0.10±0.05
(.004±.002)
0.13(.005)
M
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
160
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
112-ball plastic FBGA
Ball pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.35 mm Max.
Weight
0.10 g
(BGA-112P-M05)
112-ball plastic FBGA
(BGA-112P-M05)
6.00(.236)REF
7.00±0.10(.276±.004)
0.20(.008) S B
B
A
7.00±0.10
(.276±.004)
6.00(.236)
REF
0.50(.020)
TYP
0.20(.008) S A
(INDEX AREA)
S
0.10(.004) S
C
0.25±0.10
(.010±.004)
(Stand off)
0.50(.020)
TYP
13
12
11
10
9
8
7
6
5
4
3
2
1
N M L K J H G F E D C B A
INDEX
(NO BALL)
112-ø0.30±0.10
ø0.05(.002) M S A B
(112-ø.012±.004)
1.15±0.20
(.045±.008)
(Seated height)
2008-2010 FUJITSU SEMICONDUCTOR LIMITED B112005S-c-2-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS709-00002-1v0-E
161
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B460R Series
144-pin plastic FBGA
Lead pitch
0.5 mm
Package width ×
package length
7.0 mm × 7.0 mm
Sealing method
Plastic mold
Mounting height
1.3 mm MAX
Weight
0.11 g
(BGA-144P-M09)
144-pin plastic FBGA
(BGA-144P-M09)
7.00±0.10(.276±.004)
0.20(.008) S A
6.00(.236)
0.50(.020)
A
13
12
11
10
9
8
7
6
5
4
3
2
1
B
7.00±0.10
(.276±.004)
6.00(.236)
0.50(.020)
INDEX AREA
N M L K J H G F E D C B A
INDEX
(No Ball)
0.20(.008) S B
S
0.08(.003) S
C
0.25±0.10
(.010±.004)
(STAND OFF)
144-ø0.30±0.10
(144-ø.012±.004)
ø0.05(.002)
M
S A B
1.15±0.15
(.045±.006)
(SEATED HEIGHT)
2010 FUJITSU SEMICONDUCTOR LIMITED HMbB144-09Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
162
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS709-00002-1v0-E
r1.0
MB9B460R Series
MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
-
-
Change Results
Preliminary → Data Sheet
■DESCRIPTION
Deleted the following description :
The products which are described in this data sheet
are placed into TYPE4 product categories in "FM4
Family PERIPHERAL MANUAL".
■FEATURES
Multi-function Serial Interface
[I2C]
Revised the following description :
Fast mode Plus (Fm+) (Max 1000 kbps, only for
ch.3 and ch.7) supported
→Fast mode Plus (Fm+) (Max 1000 kbps, only for
ch.3=ch.A and ch.7=ch.B) supported
7
■FEATURES
Unique ID
Added new section
9
■PRODUCT LINEUP
Function
Added “Unique ID”
51, 52
■I/O CIRCUIT TYPE
Revised the remarks of “Type O, P, Q”
59
■HANDLING DEVICES
Handling when using debug pins
Added new section
60
■BLOCK DIAGRAM
Revised the block diagram
73
■ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
Revised “Table for package thermal resistance and
maximum permissible power”
■ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
• Revised the value of TBD
• Revised the unit of “ICCHD”, “ICCRD”,
“ICCVBAT”
mA → µA
• Added the note to “ICCVBAT”
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(2) Sub Clock Input Characteristics
Revised the waveform chart
86
86
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Built-in CR OscillationCharacteristics
• Revised the value of TBD
• Revised the table and the note of “Built-in
High-speed CR”
145
■ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter
・Electrical Characteristics for the A/D
Converter
• Revised the value of TBD
• Revised the condition of the electrical
characteristics table
148
■ELECTRICAL CHARACTERISTICS
6. 12-bit D/A Converter
・Electrical Characteristics for the D/A
Converter
• Revised the value of TBD
• Revised the condition and Remarks of the
electrical characteristics table
151
■ELECTRICAL CHARACTERISTICS
10. Standby Recovery Time
(1) Recovery cause: Interrupt/WKUP
• Revised the value of TBD
• Revised the table of Recovery count time
1
3
76 to 81
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MB9B460R Series
Page
153
Section
■ELECTRICAL CHARACTERISTICS
10. Standby Recovery Time
(2) Recovery cause:Reset
164
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Change Results
• Revised the value of TBD
• Revised the table of Recovery count time
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r1.0
MB9B460R Series
DS709-00002-1v0-E
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r1.0
MB9B460R Series
166
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r1.0
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DS709-00002-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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r1.0
MB9B460R Series
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extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other
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FUJITSU SEMICONDUCTOR CONFIDENTIAL