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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM71-10139-5E
FR60Lite
32-BIT MICROCONTROLLER
MB91210 Series
HARDWARE MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91210 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
The MB91210 series is a Fujitsu's line of general-purpose, 32-bit RISC microcontrollers designed for
embedded control applications which require high-speed real-time processing, such as in consumer
products. The CPU used in this series is the FR 60Lite compatible with the FR family.
The MB91210 series contains a LIN-UART and a CAN controller.
Note: FR, the abbreviation of Fujitsu RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Organization of this manual
This manual consists of the following 20 chapters and an appendix:
CHAPTER 1 OVERVIEW
The FR family is a line of standard single-chip microcontrollers based on a 32-bit high-performance
RISC CPU and integrating a variety of I/O resources and bus control functions for embedded control
applications which require high-performance, high-speed processing by the CPU.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on handling the FR family.
CHAPTER 3 CPU AND CONTROL BLOCK
This chapter provides basic information required to understand the CPU core functions of the FR family.
It covers architecture, specifications, and instructions.
CHAPTER 4 RESET
This chapter describes a reset.
CHAPTER 5 I/O PORTS
This chapter gives an overview of I/O ports and describes their register configuration and functions.
CHAPTER 6 INTERRUPT CONTROLLER
This chapter gives an overview of the interrupt controller and describes its register configuration/
functions and its operations.
CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
This chapters gives an overview of the external interrupt control unit and describes its register
configuration/functions and its operations.
CHAPTER 8 REALOS-RELATED HARDWARE
REALOS-related hardware is used by the real-time OS. Therefore, when REALOS is used, the hardware
cannot be used with the user program.
CHAPTER 9 DMAC (DMA CONTROLLER)
This chapter explains the overview of DMAC, configurations/functions of the register, and operations of
DMAC.
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CHAPTER 10 CAN CONTROLLER
This chapter describes the functions and operations of the CAN controller.
CHAPTER 11 LIN-UART
This chapter explains the functions and operations of the UART with LIN function.
CHAPTER 12 16-BIT RELOAD TIMER
This chapter explains the register configuration/ function and timer operation of the 16-bit reload timer.
CHAPTER 13 16-BIT FREE-RUN TIMER
This section explains the functions and operations of the 16-bit free-run timer.
CHAPTER 14 INPUT CAPTURE
This chapter explains the functions and operations of the input capture.
CHAPTER 15 OUTPUT COMPARE UNIT
This chapter describes the operations and functions of the output compare unit.
CHAPTER 16 PPG TIMER
This chapter explains about the PPG timer.
CHAPTER 17 REAL TIME CLOCK
This chapter explains the register configuration and the functions of the real time clock (hereinafter
referred to as RTC) and the operation of RTC module.
CHAPTER 18 A/D CONVERTER
This chapter explains the overview of the A/D converter, the configuration/function of the registers, and
the operation of the A/D converter.
CHAPTER 19 FLASH MEMORY
This chapters gives an overview of flash memory and describes the register configuration/functions and
the operations.
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
This chapters gives an overview of flash memory product for examples of serial programming connection.
APPENDIX
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of
the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2007-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
OVERVIEW..................................................................................................... 1
Features.................................................................................................................................................. 2
Block Diagram ........................................................................................................................................ 5
Package Dimensions .............................................................................................................................. 6
Pin Assignment....................................................................................................................................... 8
Memory Maps ....................................................................................................................................... 10
List of Pin Functions ............................................................................................................................. 12
I/O Circuit Types ................................................................................................................................... 21
HANDLING DEVICES .................................................................................. 23
Precautions on Handling the Device..................................................................................................... 24
CHAPTER 3
CPU AND CONTROL BLOCK ..................................................................... 27
3.1 Memory Space...................................................................................................................................... 28
3.2 Internal Architecture.............................................................................................................................. 29
3.2.1
Overview of Instructions ............................................................................................................. 33
3.3 Programming Model ............................................................................................................................. 35
3.3.1
General-purpose Registers ........................................................................................................ 36
3.3.2
Dedicated Register ..................................................................................................................... 37
3.4 Data Structure....................................................................................................................................... 45
3.5 Memory Map......................................................................................................................................... 47
3.6 Branch Instructions ............................................................................................................................... 48
3.7 EIT (Exception, Interruption, and Trap) ................................................................................................ 51
3.7.1
EIT Interrupt Levels .................................................................................................................... 52
3.7.2
ICR (Interrupt Control Register).................................................................................................. 54
3.7.3
SSP (System Stack Pointer)....................................................................................................... 55
3.7.4
TBR (Table Base Register) ........................................................................................................ 56
3.7.5
Multiple EIT Processing.............................................................................................................. 60
3.7.6
Operation.................................................................................................................................... 62
3.8 Operating Modes .................................................................................................................................. 66
3.8.1
Bus Modes.................................................................................................................................. 67
3.8.2
Mode Setting .............................................................................................................................. 68
3.9 Clock Generation Control ..................................................................................................................... 70
3.9.1
PLL Control................................................................................................................................. 71
3.9.2
Oscillation Stabilization Wait and PLL Lock Wait Time .............................................................. 73
3.9.3
Clock Distribution........................................................................................................................ 75
3.10 Clock Division ....................................................................................................................................... 77
3.10.1
Block Diagram of Clock Generation Control Block ..................................................................... 78
3.10.2
Detailed Explanation of Registers in Clock Generation Control Block ....................................... 79
3.10.3
Peripheral Circuits in Clock Control Block ................................................................................ 100
3.11 Device State Control........................................................................................................................... 104
3.11.1
Device States and Various Transitions..................................................................................... 105
3.11.2
Low-power Consumption Mode................................................................................................ 108
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3.12 Main Oscillation Stabilization Wait Timer............................................................................................ 113
3.13 Pseudo Sub Clock .............................................................................................................................. 120
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
5.6
RESET ........................................................................................................ 121
Overview of a Reset ........................................................................................................................... 122
Reset Factors and Oscillation Stabilization Wait Time ....................................................................... 124
Reset Levels ....................................................................................................................................... 126
External Reset Pin .............................................................................................................................. 128
Reset Operation.................................................................................................................................. 129
Reset Source Bits ............................................................................................................................... 130
Pin States at a Reset .......................................................................................................................... 132
I/O PORTS.................................................................................................. 133
Overview of I/O Ports.......................................................................................................................... 134
Port Data Registers (PDRs) and Data Direction Registers (DDRs).................................................... 136
Settings of Port Function Registers .................................................................................................... 138
Selecting Pin Input Levels .................................................................................................................. 148
Pull-up/Pull-down Control Registers ................................................................................................... 150
Input Data Direct Read Registers ....................................................................................................... 152
CHAPTER 6
INTERRUPT CONTROLLER ..................................................................... 153
6.1 Overview of Interrupt Controller.......................................................................................................... 154
6.2 Interrupt Controller Registers.............................................................................................................. 157
6.2.1
Interrupt Control Register (ICR)................................................................................................ 158
6.2.2
Hold Request Cancel Request Register (HRCL)...................................................................... 159
6.3 Operations of Interrupt Controller ....................................................................................................... 160
CHAPTER 7
EXTERNAL INTERRUPT CONTROL UNIT............................................... 167
7.1 Overview of External Interrupt Control Unit ........................................................................................ 168
7.2 Registers of External Interrupt Control Unit ........................................................................................ 170
7.2.1
Interrupt Enable Register (ENIR).............................................................................................. 171
7.2.2
External Interrupt Source Register (EIRR) ............................................................................... 172
7.2.3
External Interrupt Request Level Setting Register (ELVR)....................................................... 173
7.2.4
Relocating External Interrupt Inputs ......................................................................................... 174
7.3 Operations of External Interrupt Control Unit...................................................................................... 176
CHAPTER 8
REALOS-RELATED HARDWARE ............................................................ 181
8.1 Delay Interrupt Module ....................................................................................................................... 182
8.1.1
Overview of Delay Interrupt Module ......................................................................................... 183
8.1.2
Registers of Delay Interrupt Module ......................................................................................... 184
8.1.3
Operation of Delay Interrupt Module ........................................................................................ 185
8.2 Bit Search Module .............................................................................................................................. 186
8.2.1
Overview of Bit Search Module ................................................................................................ 187
8.2.2
Registers of Bit Search Module ................................................................................................ 189
8.2.3
Operations of Bit Search Module.............................................................................................. 191
CHAPTER 9
DMAC (DMA CONTROLLER).................................................................... 195
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9.1 Overview of DMAC ............................................................................................................................. 196
9.2 Detail Explanation of Registers of DMAC ........................................................................................... 199
9.2.1
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register A .................................................. 200
9.2.2
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register B .................................................. 205
9.2.3
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Destination Address Setting Registers ... 212
9.2.4
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC Overall Control Register ......................................... 215
9.3 Operating Explanation of DMAC......................................................................................................... 218
9.3.1
Overview of Operations ............................................................................................................ 219
9.3.2
Setting of Transfer Request...................................................................................................... 221
9.3.3
Transfer Sequence ................................................................................................................... 222
9.3.4
General DMA Transfer ............................................................................................................. 224
9.3.5
Addressing Mode...................................................................................................................... 225
9.3.6
Data Type ................................................................................................................................. 226
9.3.7
Transfer Count Control ............................................................................................................. 227
9.3.8
CPU Control ............................................................................................................................. 228
9.3.9
Start of Operation ..................................................................................................................... 229
9.3.10
Acceptance and Transfer of Transfer Request......................................................................... 230
9.3.11
Peripheral Interrupt Clear by DMA ........................................................................................... 231
9.3.12
Pause ....................................................................................................................................... 232
9.3.13
Termination/Stop of Operation ................................................................................................. 233
9.3.14
Stop By Error ............................................................................................................................ 234
9.3.15
DMAC Interrupt Control ............................................................................................................ 235
9.3.16
DMA transfer during the sleep mode........................................................................................ 236
9.3.17
Channel Selection and Control................................................................................................. 237
9.4 Operation Flow of DMAC.................................................................................................................... 239
9.5 Data Path of DMAC ............................................................................................................................ 241
CHAPTER 10 CAN CONTROLLER .................................................................................. 243
10.1 Features of CAN ................................................................................................................................. 244
10.2 Block Diagram of CAN........................................................................................................................ 245
10.3 Registers of CAN ................................................................................................................................ 246
10.4 Functions of CAN Resisters................................................................................................................ 253
10.4.1
Overall Control Register ........................................................................................................... 254
10.4.1.1
CAN Control Register (CTRLR)........................................................................................... 255
10.4.1.2
CAN Status Register (STATR) ............................................................................................ 258
10.4.1.3
CAN Error Counter (ERRCNT)............................................................................................ 261
10.4.1.4
CAN Bit Timing Resister (BTR) ........................................................................................... 262
10.4.1.5
CAN Interrupt Register (INTR) ............................................................................................ 263
10.4.1.6
CAN Test Register (TESTR) ............................................................................................... 265
10.4.1.7
CAN Prescaler Extended Register (BRPER) ...................................................................... 267
10.4.2
Message Interface Register...................................................................................................... 268
10.4.2.1
IFx Command Request Resister (IFxCREQ)....................................................................... 269
10.4.2.2
IFx Command Mask Resister (IFxCMSK) ........................................................................... 272
10.4.2.3
IFx Mask Resister 1 and 2 (IFxMSK1, IFxMSK2)................................................................ 276
10.4.2.4
IFx Arbitration Resister 1 and 2 (IFxARB1, IFxARB2)......................................................... 277
10.4.2.5
IFx Message Control Resister (IFxMCTR) .......................................................................... 278
10.4.2.6
IFx Data Resister A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) ................ 279
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10.4.3
Message Object........................................................................................................................ 280
10.4.4
Message Handler Register ....................................................................................................... 286
10.4.4.1
CAN Transmission Request Registers (TREQR1, TREQR2) ............................................. 287
10.4.4.2
CAN New Data Resisters (NEWDT1, NEWDT2) ................................................................ 289
10.4.4.3
CAN Interrupt Pending Registers (INTPND1, INTPND2) .................................................... 291
10.4.4.4
CAN Message Valid Registers (MSGVAL1, MSGVAL2)..................................................... 293
10.4.5
CAN Prescaler Register (CANPRE) ......................................................................................... 295
10.5 Functions of CAN................................................................................................................................ 296
10.5.1
Message Object........................................................................................................................ 297
10.5.2
Message Transmission Operation............................................................................................ 299
10.5.3
Message Reception Operation ................................................................................................. 302
10.5.4
Function of FIFO Buffer ............................................................................................................ 306
10.5.5
Interrupt Function ..................................................................................................................... 308
10.5.6
Bit Timing.................................................................................................................................. 309
10.5.7
Test Mode................................................................................................................................. 312
10.5.8
Software Initialization................................................................................................................ 317
10.5.9
CAN Clock Prescaler................................................................................................................ 318
CHAPTER 11 LIN-UART ................................................................................................... 321
11.1 Overview of UART .............................................................................................................................. 322
11.2 Configuration of UART........................................................................................................................ 325
11.3 Registers of UART.............................................................................................................................. 330
11.3.1
Serial Control Register (SCR) .................................................................................................. 332
11.3.2
Serial Mode Register (SMR)..................................................................................................... 335
11.3.3
Serial Status Register (SSR) .................................................................................................... 338
11.3.4
Reception/Transmission Data Register (RDR/TDR) ................................................................ 341
11.3.5
Extended Status/Control Register (ESCR)............................................................................... 343
11.3.6
Extended Communication Control Register (ECCR)................................................................ 346
11.3.7
Baud Rate/Reload Counter Register (BGR)............................................................................. 349
11.4 Interrupts of UART.............................................................................................................................. 351
11.4.1
Reception Interrupt Generation and Flag Set Timing ............................................................... 355
11.4.2
Transmission Interrupt Generation and Flag Set Timing.......................................................... 357
11.5 UART Baud Rates .............................................................................................................................. 359
11.5.1
Baud Rate Setting .................................................................................................................... 361
11.5.2
Restart of Reload Counter........................................................................................................ 364
11.6 Operations of UART ........................................................................................................................... 366
11.6.1
Operation in Asynchronous Mode (Operation Mode 0 and Mode 1) ........................................ 368
11.6.2
Operation in Synchronous Mode (Operation Mode 2).............................................................. 371
11.6.3
Operation with LIN Function (Operation Mode 3)..................................................................... 374
11.6.4
Direct Access to Serial Pins ..................................................................................................... 378
11.6.5
Bidirectional Communication Function (Normal Mode) ............................................................ 379
11.6.6
Master/Slave Communication Function (Multiprocessor Mode) ............................................... 381
11.6.7
LIN Communication Function ................................................................................................... 384
11.6.8
LIN Communication Mode (Operation Mode 3) LIN-UART Sample Flowchart ........................ 385
11.7 Notes on Using UART ........................................................................................................................ 388
CHAPTER 12 16-BIT RELOAD TIMER............................................................................. 391
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12.1 Overview of 16-Bit Reload Timer........................................................................................................ 392
12.2 Registers of 16-Bit Reload Timer........................................................................................................ 393
12.2.1
Control Status Register (TMCSR) ............................................................................................ 394
12.2.2
16-Bit Timer Register (TMR) .................................................................................................... 397
12.2.3
16-Bit Reload Register (TMRLR).............................................................................................. 398
12.3 Operations of 16-Bit Reload Timer ..................................................................................................... 399
CHAPTER 13 16-BIT FREE-RUN TIMER ......................................................................... 403
13.1 Overview of 16-Bit Free-Run Timer .................................................................................................... 404
13.2 Registers of 16-Bit Free-Run Timer.................................................................................................... 405
13.2.1
Timer Data Register (TCDT) .................................................................................................... 406
13.2.2
Timer Control Status Register (TCCS) ..................................................................................... 407
13.3 Operations of 16-Bit Free-Run Timer ................................................................................................. 410
13.4 Notes on Using 16-Bit Free-Run Timer .............................................................................................. 412
CHAPTER 14 INPUT CAPTURE....................................................................................... 413
14.1 Overview of Input Capture .................................................................................................................. 414
14.2 Registers of Input Capture.................................................................................................................. 415
14.2.1
Input Capture Register (IPCP).................................................................................................. 416
14.2.2
Input Capture Control Register (ICS) ....................................................................................... 417
14.3 Operations of Input Capture ............................................................................................................... 419
CHAPTER 15 OUTPUT COMPARE UNIT ........................................................................ 421
15.1 Overview of the Output Compare Unit................................................................................................ 422
15.2 Resisters of the Output Compare Unit................................................................................................ 423
15.2.1
Compare Resister (OCCP)....................................................................................................... 424
15.2.2
Control Register (OCS) ............................................................................................................ 425
15.3 Operations of the Output Compare Unit ............................................................................................. 428
CHAPTER 16 PPG TIMER ................................................................................................ 431
16.1 Overview of PPG Timer ...................................................................................................................... 432
16.2 Block Diagram of PPG Timer.............................................................................................................. 433
16.3 Registers of PPG Timer...................................................................................................................... 436
16.3.1
PPG Operating Mode Control Register (PPGC)....................................................................... 438
16.3.2
Reload Register (PRLL/PRLH)................................................................................................. 441
16.3.3
PPG Start Register (TRG) ........................................................................................................ 443
16.3.4
Output Reverse Register (REVC)............................................................................................. 444
16.4 Operating Explanation of PPG Timer ................................................................................................. 445
CHAPTER 17 REAL TIME CLOCK................................................................................... 451
17.1 Configuration of Real Time Clock Registers....................................................................................... 452
17.2 Block Diagram of Real Time Clock ..................................................................................................... 454
17.3 Details of Real Time Clock Registers ................................................................................................. 455
17.4 Clock Calibration Unit of Real Time Clock.......................................................................................... 460
17.5 Clock Calibration Unit Registers of Real Time Clock.......................................................................... 462
17.5.1
Calibration Unit Control Register (CUCR) ................................................................................ 463
17.5.2
Sub Timer Data Register (CUTD)............................................................................................. 465
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17.5.3
Main Timer Data Register (CUTR) ........................................................................................... 467
17.6 About the Use for Clock Calibration Unit of Real Time Clock............................................................. 468
CHAPTER 18 A/D CONVERTER ...................................................................................... 469
18.1 Overview of A/D Converter ................................................................................................................. 470
18.2 Block Diagram of A/D Converter......................................................................................................... 471
18.3 Registers of A/D Converter................................................................................................................. 472
18.3.1
Analog Input Enable Register (ADER) ..................................................................................... 474
18.3.2
A/D Control Status Register (ADCS) ........................................................................................ 475
18.3.3
Data Register (ADCR1, ADCR0).............................................................................................. 481
18.3.4
Conversion Time Setting Register (ADCT)............................................................................... 482
18.3.5
Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH)................. 484
18.4 Operation of A/D Converter ................................................................................................................ 486
CHAPTER 19 FLASH MEMORY....................................................................................... 489
19.1 Overview of Flash Memory ................................................................................................................. 490
19.2 Flash Memory Registers..................................................................................................................... 494
19.2.1
Flash Memory Control/Status Register (FLCR)........................................................................ 495
19.2.2
Flash Memory Wait Register (FLWC)....................................................................................... 497
19.3 Operations of Flash Memory .............................................................................................................. 499
19.4 Flash Memory Automatic Algorithms .................................................................................................. 501
19.4.1
Command Sequence................................................................................................................ 502
19.4.2
Confirming Automatic Algorithm Execution States ................................................................... 506
19.5 Details of Programming and Erasing Flash Memory .......................................................................... 511
19.5.1
Read/Reset State ..................................................................................................................... 512
19.5.2
Programming Data ................................................................................................................... 513
19.5.3
Erasing Data (Chip Erase)........................................................................................................ 515
19.5.4
Erasing Data (Sector Erase)..................................................................................................... 516
19.5.5
Suspending Sector Erasure...................................................................................................... 518
19.5.6
Resuming Sector Erasure ........................................................................................................ 519
19.6 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems ............................................... 520
19.7 Notes on Flash Memory Programming ............................................................................................... 523
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION...................... 525
20.1 Serial Programming Connection Examples ........................................................................................ 526
20.2 Serial (Asynchronous) Programming Example................................................................................... 538
APPENDIX ........................................................................................................................... 543
APPENDIX A I/O Map................................................................................................................................ 544
APPENDIX B Vector Table ........................................................................................................................ 562
APPENDIX C Status of Each Pin in Each CPU state................................................................................. 566
APPENDIX D INSTRUCTION LISTS ......................................................................................................... 571
D.1
FR Family Instruction Lists.......................................................................................................... 576
INDEX
............................................................................................................................ 593
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
213
CHAPTER 9 DMAC (DMA
CONTROLLER)
9.2.3 DMAC-ch.0, ch.1, ch.2, ch.3,
ch.4 Transfer Source/Destination
Address Setting Registers
■ Bit Function of DMASA0 to
DMASA4/DMADA0 to DMADA4
Corrected the following description.
"00000000 00000000 00000000 00000000B"
→
000000H
247
CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
■ List of Overall Control Register
Table 10.3-1
Corrected the CAN prescaler extended register (BRPER) of Baseaddr + 0CH.
BRPER → BRPE
248
■ List of Message Interface Register
Table 10.3-2
Corrected the IF1 mask register 2 of Base-addr + 14H.
Msk28 to MXtd. MDir, Msk24 → Msk28 to Msk24
Corrected the IF1 arbitration register 2 of Base-addr + 18H.
Dir, ID28 to MsgVal, Xtd,Dir, ID24 → Dir, ID28 to ID24
Corrected the IF2 mask register 2 of Base-addr + 44H.
Msk28 to MXtd. MDir, Msk24 → Msk28 to Msk24
249
Corrected the IF2 arbitration register 2 of Base-addr + 48H.
Dir, ID28 to MsgVal, Xtd,Dir, ID24 → Dir, ID28 to ID24
269
10.4 Functions of CAN Resisters
10.4.2.1 IFx Command Request
Resister (IFxCREQ)
■ Register Configuration
Corrected the Figure 10.4-8.
bit5 : res → Message Number
270
■ Register Function
Corrected the bit range of Reserved bits.
[bit14 to bit5] → [bit14 to bit6]
Corrected the bit range of Message Number: Message number (for
32-message buffer CAN).
[bit4 to bit0] → [bit5 to bit0]
271
Corrected the bit range of Message Number: Message number (for
128-message buffer CAN).
[bit4 to bit0] → [bit7 to bit0]
276
10.4.2.3 IFx Mask Resister 1 and 2
(IFxMSK1, IFxMSK2)
■ Register Configuration
Figure 10.4-10
Corrected the bit13.
R/W → R
315
10.5.7 Test Mode
■ Basic Mode
Corrected bit name of description.
Busy bit → BUSY bit
xiii
Page
349
364
-
490
Changes (For details, refer to main body.)
CHAPTER 11 LIN-UART
11.3.7 Baud Rate/Reload Counter
Register (BGR)
■ Baud Rate/Reload Counter Register
(BGR)
Corrected the [bit14 to bit8].
BGR1 → B14 to B08
11.5.2 Restart of Reload Counter
■ Software Restart
Corrected the Figure 11.5-3.
Reset → REST
CHAPTER 19 FLASH MEMORY
Corrected the term.
• write/erase → data write/erase
• sector erase wait → sector erase time-out
19.1 Overview of Flash Memory
Corrected the summary sentence.
544 Kbytes (MB91F211B) /288 Kbytes (MB91F213A/F218S)
Corrected the [bit7 to bit0].
BGR0 → B07 to B00
→
288 Kbytes (MB91F211B) /544 Kbytes (MB91F213A/F218S)
502
19.4.1 Command Sequence
■ Command Sequences for Automatic
Algorithms
Corrected the command sequence in Table 19.4-1.
• Read/reset → Reset
• program → Data program
• Deleted "RA" and "RD" from the line of reset.
Changed Table 19.4-1.
Changed the data column to the half word (16 bits).
Changed Table 19.4-1.
Deleted the line of "Continuous mode", "Continuous write", and
"Continuous mode reset".
503
504
■ Reset Command
Corrected the command name.
Read/Reset Command → Reset Command
■ Program (Data Write)
Corrected the term.
bit7 → data polling flag (DQ7)
■ Chip Erase
Corrected the term.
• bit7 → data polling flag (DQ7)
• Automatic erasure → Chip erase automatic algorithm
■ Sector Erase
Corrected the term.
• bit7 → data polling flag (DQ7)
• bit3 → sector erase timer flag (DQ3)
Corrected the sector erase time-out period.
80μs → minimum of 50 μs
505
■ Erase Suspend
Corrected the term.
• ready/busy output →
RDY bit in the flash memory control/status register (FLCR)
• bit7 → data polling flag (DQ7)
• bit6 → toggle bit flag (DQ6)
xiv
Page
506
Changes (For details, refer to main body.)
19.4.2 Confirming Automatic
Algorithm Execution States
■ RDY Bit
Corrected the term.
Ready/Busy Signal (RDY/BUSYX) → RDY Bit
■ Hardware Sequence Flag
Corrected figure 19.4-1.
• Deleted "For word read".
• Deleted "bit4:ERIP".
507
Corrected table 19.4-2.
• Automatic program operation → Data program
• Programming in automatic erase → Chip erase
• Automatic erase operation →
Sector erase (It divides into "Time-out period" and "Erase period".)
• Program/erase operation in automatic erase → Chip/sector erase
• Deleted the column of "ERIP".
508
Corrected the explanation of [bit7] DPOLL: Data polling flag (DQ7).
• chip/sector erase operation: → chip erase operation:
• Added "• During a sector erase operation:".
• Added the explanation of the restriction matter of data polling flag
(DQ7).
• Corrected the explanation, added the restriction matter.
509
Deleted the item of "[bit4] ERIP: Erase indicator flag".
512
19.5.1 Read/Reset State
Corrected the command name.
Read/Reset command → Reset command
513
19.5.2 Programming Data
■ Addressing
Corrected the data written by 1st data program command.
only one word → only halfword (16 bits)
■ Flash Memory Programming
Procedure
Corrected the term.
• data polling flag (DPOLL) → data polling flag (DQ7)
• toggle bit flag (TOGGLE) → toggle bit flag (DQ6)
• timing limit over flag (TLOVER) → timing limit over flag (DQ5)
514
516
516
517
518
Changed Figure 19.5-1.
The data of the writing command sequence is changed to the half
word (16 bits).
19.5.4 Erasing Data (Sector Erase)
Corrected the sector erase time-out period.
50μs → minimum of 50 μs
■ Notes on Specifying Multiple
Sectors
Corrected the term.
• sector erase wait → sector erase time-out
• sector erase timer (hardware sequence flag, SETIMR) →
sector erase timer flag (DQ3)
■ Sector Erasing Procedure
Corrected the term.
• data polling flag (DPOLL) → data polling flag (DQ7)
• toggle bit flag (TOGGLE) → toggle bit flag (DQ6)
• timing limit over flag (TLOVER) → timing limit over flag (DQ5)
■ Restrictions on Data Polling Flag
(DQ7)
Added the item of "■ Restrictions on Data Polling Flag (DQ7)".
19.5.5 Suspending Sector Erasure
Corrected the term.
sector erase wait → sector erase time-out
Corrected the flow chart of Figure 19.5-2.
xv
Page
520 to
522
Changes (For details, refer to main body.)
19.6 Restrictions on Data Polling Flag
(DQ7) and How to Avoid
Problems
Added "19.6 Restrictions on Data Polling Flag (DQ7) and How to
Avoid Problems".
19.7 Notes on Flash Memory
Programming
Corrected the term.
• flash memory reprogramming mode → FR-CPU programming
• FMCS register → FLCR register
CHAPTER 20 EXAMPLES OF
SERIAL
PROGRAMMING
CONNECTION
Added "CHAPTER 20".
(Moved section 19.7 and section 19.8 to CHAPTER 20.)
APPENDIX D INSTRUCTION
LISTS
■ How to Read the Instruction Lists
Changed explanation 5) .
Ready function → wait cycle
582
■ Memory Load Instructions
Corrected "Note:".
o4 → u4
583
■ Memory Store Instructions
Corrected "Note:".
o4 → u4
584
D.1 FR Family Instruction Lists
■ Normal Branch (No Delay)
Instructions
Changed Notes.
S flag → Stack flag (S)
523
-
572
ST Rs, or @R15 instruction → "ST Rs, @-R15" instruction
The vertical lines marked in the left side of the page show the changes.
xvi
CHAPTER 1
OVERVIEW
The FR family is a line of standard single-chip
microcontrollers based on a 32-bit high-performance
RISC CPU and integrating a variety of I/O resources and
bus control functions for embedded control applications
which require high-performance, high-speed processing
by the CPU.
1.1 Features
1.2 Block Diagram
1.3 Package Dimensions
1.4 Pin Assignment
1.5 Memory Maps
1.6 List of Pin Functions
1.7 I/O Circuit Types
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
1
CHAPTER 1 OVERVIEW
1.1 Features
1.1
MB91210 Series
Features
This section summarizes the features of the MB91210 series.
■ Features of the FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency of 40 MHz [PLL used: 4-MHz oscillation frequency]
• 16-bit fixed-length instructions (basic instructions), one instruction per cycle
• Memory-to-memory transfer, bit manipulation, barrel shift, and other instructions:
Instructions appropriate for embedded applications
• Function entry/exit instructions, multi-register load/store instructions:
Instructions compatible with high-level languages
• Register interlock function: Facilitating assembly-language coding
• Built-in multiplier/instruction-level support:
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
• Harvard architecture enabling simultaneous execution of program access and data access
• Instruction-compatible with the FR family
■ Internal Memory
Flash memory
RAM
MB91F211B
288 Kbytes
16 Kbytes
MB91F213A
544 Kbytes
24 Kbytes
MB91213A
544 Kbytes (MASK ROM)
24 Kbytes
MB91F218S
544 Kbytes
24 Kbytes
■ DMA Controller
• Capable of operation through up to 5 channels
• 2 transfer sources (internal peripheral/software)
■ Bit Search Module (Used by REALOS)
Searches for the position of the first bit varying between 1 and 0 in the MSB of a word.
2
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.1 Features
MB91210 Series
■ UART with LIN Function (7 Channels)
• Asynchronous (start-stop synchronous) or clock-synchronous communication
• Synch-Break detection
• Built-in baud rate generator for each channel
• Capable of supporting SPI (mode 2: clock synchronous communication mode)
■ CAN Controller (3 Channels)
• Maximum transfer rate: 1 Mbps
• 32 message buffers
■ Various Timers
• 16-bit reload timer (3 channels)
Internal clock selectable from among results of dividing the machine clock frequency by 2, 8, and 32
• 16-bit free-run timer (4 channels)
• Output compare unit (8 channels)
• Input capture unit (8 channels)
• 8/16-bit PPG timer (16 channels/8 channels)
Clock source selectable from among results of dividing the peripheral clock frequency by 1, 2, 16, and
64
■ Interrupt Controller
• Interrupts from internal peripherals
• Software-programmable priority level (16 levels)
■ External Interrupts (16 Channels)
• Input selectable from among multiple pins
• Available as CAN wakeup function
Noise filter inserted for CAN wakeup (Typ=4 μs)
■ A/D Converter (32 Channels)
• 10-bit resolution
• Successive approximation type
Conversion time: 3 μs
• Conversion modes (single conversion mode and continuous conversion mode)
• Activation sources (software, external trigger, and peripheral interrupt)
■ Other Interval Timer/Counter
16-bit time-base timer/watchdog timer
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
3
CHAPTER 1 OVERVIEW
1.1 Features
MB91210 Series
■ Other Features
• Internal oscillation circuit as a clock source, allowing PLL multiplication to be selected.
• INITX provided as a reset pin
• Watchdog timer and software resets available
• Supporting stop mode, sleep mode, and real-time clock mode as low-power consumption modes,
enabling the CPU to operate at 32 kHz to reduce power consumption.
• Gear function
Allowing various combinations of clock frequencies to be generated by setting PLL multipliers (1/2/4/8/
10) and clock frequency divisors (1 to 16).
• Built-in time-base timer
• Package: LQFP-100, LQFP-144
• CMOS technology (0.18 μm)
• Supply voltage: 3.5 V to 5.5 V
The internal circuit is supplied with power at 1.8 V via the built-in voltage step down circuit.
■ Function Comparison
MB91V210
MB91F211B
MB91F213A
MB91213A
MB91F218S
Evaluation
product
Flash memory
product
Flash memory
product
MASK ROM
product
Flash memory
product
BGA-420
LQFP-100
LQFP-144
External SRAM
288 Kbytes
544 Kbytes
RAM size
4 Kbytes +
32 Kbytes
4 Kbytes +
12 Kbytes
4 Kbytes + 20 Kbytes
External interrupt
16 channels
16 channels
16 channels
DMA Controller
5 channels
5 channels
5 channels
External sub clock
Yes
Yes
Pseudo sub clock
No
Yes
No
RTC
Yes
Yes
Yes
3 channels
(128 msg/ch)
1 channel
(32 msg/ch)
3 channels (32 msg/ch)
LIN-UART
7 channels
4 channels
(Support LIN)
1 channel
(Non-support LIN)
7 channels
Reload Timer
3 channels
3 channels
3 channels
Free-run timer
4 channels
2 channels
4 channels
Input Capture (ICU)
8 channels
4 channels
8 channels
Output Compare
(OCU)
8 channels
4 channels
8 channels
8bits × 16 channels
(16bits × 8 channels)
8bits × 8 channels
(16bits × 4 channels)
8bits × 16 channels
(16bits × 8 channels)
32 channels
16 channels
32 channels
Package
ROM/Flash size
CAN Controller
8/16bits PPG
A/D Converter
4
Yes
FUJITSU MICROELECTRONICS LIMITED
No
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.2 Block Diagram
MB91210 Series
1.2
Block Diagram
This section provides a block diagram of the MB91210 series.
■ Block Diagram of MB91210 Series
Figure 1.2-1 Block Diagram
FR CPU core
Bit search
D-bus RAM
Bus converter
Flash
DMA controller
F-bus RAM
RX
TX
CAN
32
16 adapter
X0, X1
X0A, X1A
MD3 to MD0
Clock
control
INITX
PORT I/F
PORT
Reload timer
TIN
TOT
Interrupt
controller
INT
SIN
SOT
SCK
External interrupt
ICU
IN
LIN-UART
Free-run timer
FRCK
BRG for UART
OCU
OUT
8/16-bit PPG
PPG
RTC
AN
ATGX
CM71-10139-5E
10-bit A/D
converter
FUJITSU MICROELECTRONICS LIMITED
5
CHAPTER 1 OVERVIEW
1.3 Package Dimensions
1.3
MB91210 Series
Package Dimensions
This section shows the package dimensions of the MB91210 series.
■ LQFP-100
Figure 1.3-1 Package Dimensions of LQFP-100
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
6
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.3 Package Dimensions
MB91210 Series
■ LQFP-144
Figure 1.3-2 Package Dimensions of LQFP-144
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7
C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
7
CHAPTER 1 OVERVIEW
1.4 Pin Assignment
1.4
MB91210 Series
Pin Assignment
This section shows the pin assignment of the MB91210 series.
■ Pin Assignment of MB91F211B
P44/IN0
P43
P42
P41
P40
P17/SCK4
P16/SOT4
P15/SIN4
VCC
VSS
P14/SCK3
P13/SOT3
P12/SIN3
P11/TOT1
P10/TIN1
P07/INT15R
P06/INT14R
P05/INT13R
P04/INT12R
P03/INT11R
P02/INT10R
P01/INT9R
P00/INT8R
X1A (P73)
X0A (P72)
85
84
83
82
81
80
79
78
77
76
INT
CAN
RLT
UART
UART
UART
PPG
ICU
RLT
INT
(PPG)
RLT
ADC
VSS
X1
X0
MD3
MD2
MD1
MD0
INITX
PD7/SCK1
PD6/SOT1
PD5/SIN1
PD4/SCK0
PD3/SOT0
PD2/SIN0
PD1/TOT0
PD0/TINO/ATGX
VCC
VSS
57
56
55
54
53
PB7/INT7R
PB6/INT6R
PB5/INT5R
PB4/INT4R
PB3/INT3R
52
51
PB2/INT2R
PB1/INT1R
P90/AN0/PPG0R
P91/AN1/PPG2R
P92/AN2/PPG4R
P93/AN3/PPG6R
P94/AN4
P95/AN5
P96/AN6
P97/AN7
AVCC
AVSS/AVRL
AVRH
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
PA4/AN12
PA5/AN13
PA6/AN14
PA7/AN15
PB0/INT0R
VCC
P82
P83
P84/TIN2
P85/TOT2
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
50
24
25
UART
OCU
19
20
21
22
23
UART
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PE2/SCK2
P70/RX0/INT8
P71/TX0
P74/OUT0
P75/OUT1
P76/OUT2
P77/OUT3
P80/FRCK0
P81/FRCK1
C
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FRT
P45/IN1
P46/IN2
P47/IN3
P50/PPG1
P51/PPG3
P52/PPG5
P53/PPG7
P54
P55
P56
P57
P60
PE0/SIN2
PE1/SOT2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
Figure 1.4-1 Pin Assignment of MB91F211B
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CM71-10139-5E
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P82/FRCK2
P83/FRCK3
P84/TIN2
P85/TOT2
P90/AN0/PPG0R
P91/AN1/PPG2R
P92/AN2/PPG4R
P93/AN3/PPG6R
P94/AN4/PPG8R
P95/AN5/PPGAR
P96/AN6/PPGCR
P97/AN7/PPGER
PA0/AN8/SIN2R
PA1/AN9/SOT2R
PA2/AN10/SCK2R
PA3/AN11
PA4/AN12
PA5/AN13
PA6/AN14
PA7/AN15
AVCC
AVSS/AVRL
AVRH
PB0/AN16/INT0R
PB1/AN17/INT1R
PB2/AN18/INT2R
PB3/AN19/INT3R
PB4/AN20/INT4R
PB5/AN21/INT5R
PB6/AN22/INT6R
PB7/AN23/INT7R
PC0/AN24
PC1/AN25
VSS
P75/OUT1
P76/OUT2
31
32
P77/OUT3
P80/FRCK0
33
34
C
35
VSS
36
8
9
10
11
P51/PPG3
P52/PPG5
P53/PPG7
P54/IN4
12
13
14
15
P55/IN5
16
P56/IN6
P57/IN7
P60/OUT6
17
18
19
ICU
UART
MD3
MD2
MD1
MD0
101
100
99
98
INITX
PF7/INT7
PF6/INT6
PF5/INT5
97
96
95
94
PF4/INT4
PF3/INT3
PF2/INT2
PF1/INT1
INT
PPG
P45/IN1
P46/IN2
P47/IN3
P50/PPG1
105
104
103
102
ICU
4
5
6
7
PPG
P41/PPGB
P42/PPGD
P43/PPGF
P44/IN0
OCU
1
2
3
RLT
UART
29
30
UART
P73/TX1
P74/OUT0
OCU
VCC
P37/INT15
P40/PPG9
ADC
24
25
26
27
28
CAN
VCC
P64
P70/RX0/INT8
P71/TX0
P72/RX1/INT9
FRT
21
22
23
37
20
P62
P63
VSS
VCC
P61/OUT7
P81/FRCK1
FRT
INT
CAN
(PPG)
PPG
UART
RLT
UART
RLT
OCU
(UART)
UART
(INT)
FUJITSU MICROELECTRONICS LIMITED
109 X0A
110 X1A
111 VSS
112 VCC
113 P00/SIN5/INT8R
114 P01/SOT5/INT9R
115 P02/SCK5/INT10R
116 P03/SIN6/INT11R
117 P04/SOT6/INT12R
118 P05/SCK6/INT13R
119 P06/OUT4/INT14R
120 P07/OUT5/INT15R
121 P10/TIN1
122 P11/TOT1
123 P12/SIN3
124 P13/SOT3
125 P14/SCK3
126 P15/SIN4
127 P16/SOT4
128 P17/SCK4
129 P20/PPG0
130 P21/PPG2
131 P22/PPG4
132 P23/PPG6
133 P24/PPG8
134 P25/PPGA
135 P26/PPGC
136 P27/PPGE
137 P30/RX2/INT10C
138 P31/TX2
139 P32/INT10
140 P33/INT11
141 P34/INT12
142 P35/INT13
143 P36/INT14
144 VSS
MB91210 Series
CHAPTER 1 OVERVIEW
1.4 Pin Assignment
■ Pin Assignment of MB91213A/F213A/F218S
Figure 1.4-2 Pin Assignment of MB91213A/F213A/F218S
UART
108 VSS
107 X1
106 X0
(INT)
ADC
93
VCC
92
91
90
VSS
PF0/INT0
PE2/SCK2
89
PE1/SOT2
88
87
86
PE0/SIN2
PD7/SCK1
PD6/SOT1
85
84
PD5/SIN1
PD4/SCK0
83
82
81
PD3/SOT0
PD2/SIN0
PD1/TOT0
80
79
PD0/TIN0/ATGX
PC7/AN31
78
77
PC6/AN30
PC5/AN29
76
PC4/AN28
75
74
PC3/AN27
PC2/AN26
73
VCC
9
CHAPTER 1 OVERVIEW
1.5 Memory Maps
1.5
MB91210 Series
Memory Maps
This section provides memory maps of the MB91210 series.
■ Memory Maps of MB91210 Series
Figure 1.5-1 Memory Maps
MB91V210
0000 0000H
0000 0400H
MB91213A MB91F213A/F218S Direct
MB91F211B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibit
CAN
Access inhibit
Access inhibit
CAN
CAN
Access inhibit
Access inhibit
F-bus RAM
F-bus RAM
D-bus RAM
D-bus RAM
Access inhibit
Access inhibit
Mask ROM
Flash memory
Access inhibit
Access inhibit
0001 0000H Access inhibit
0002 0000H
CAN
0002 0100H
0002 0300H Access inhibit
0003 8000H
Access inhibit
addressing
area
0003 B000H
F-bus RAM
0003 D000 H
F-bus RAM
0004 0000H
0004 1000H
D-bus RAM
D-bus RAM
Access inhibit
0005 0000H
Access inhibit
External
SRAM
000B 8000 H
0007 8000H
Flash memory
0010 0000H
Access inhibit
Access inhibit
Use the D-bus RAM as an area for stacking data. Because instruction fetch is not performed in the D-bus
RAM, if the code area is configured in D-bus memory then there is a risk of the CPU running out of control
due to incorrect data being interpreted (recognized) as code.
10
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.5 Memory Maps
MB91210 Series
■ Sector Configuration of Flash Memory
Figure 1.5-2 Sector Configuration (544K bytes)
078000H
088000H
098000H
0A8000H
0B8000H
0C8000H
0D8000H
0E8000H
0F8000 H
0FA000 H
0FC000 H
0FE000H
100000 H
SA4 (64K bytes)
SA5 (64K bytes)
SA6 (64K bytes)
SA7 (64K bytes)
SA8 (64K bytes)
SA9 (64K bytes)
SA10 (64K bytes)
SA11 (64K bytes)
SA0 (8K bytes)
SA1 (8K bytes)
SA2 (8K bytes)
SA3 (8K bytes)
32 bits
Figure 1.5-3 Sector Configuration (288K bytes)
0B8000H
SA4 (64 K bytes)
0C8000H
SA5 (64 K bytes)
0D8000H
SA6 (64 K bytes)
0E8000H
SA7 (64 K bytes)
0F8000H
0FA000H
0FC000H
0FE000H
100000H
SA0 (8 K bytes)
SA1 (8 K bytes)
SA2 (8 K bytes)
SA3 (8 K bytes)
32 bits
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
11
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
1.6
MB91210 Series
List of Pin Functions
This section lists the pin functions of the MB91210 series.
■ List of Pin Functions
Table 1.6-1 List of Pin Functions (1 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
Pin name
73
106
X0
74
107
68
I/O circuit
type
Main clock input pin
X1
OA
OB
101
INITX
D
System reset input pin
72 to 69
105 to 102
MD3 to MD0
C
Operation mode input pin
76
109
X0A
77
110
X1A
WA
WB
P00
78
113
INT8R
A
114
INT9R
A
115
INT10R
A
116
INT11R
General-purpose I/O port
A
SIN6 *
117
INT12R
General-purpose I/O port
A
SOT6 *
118
INT13R
SCK6 *
External interrupt request 12 input pin
(Selected along with P34 pin)
UART6 serial data output pin
P05
83
External interrupt request 11 input pin
(Selected along with P33 pin)
UART6 serial data input pin
P04
82
External interrupt request 10 input pin
(Selected along with P32 pin)
UART5 serial communication clock I/O pin
P03
81
External interrupt request 9 input pin
(Selected along with P72 pin)
General-purpose I/O port
SCK5 *
—
External interrupt request 8 input pin
(Selected along with P70 pin)
UART5 serial data output pin
P02
80
Sub clock output pin
General-purpose I/O port
SOT5 *
—
Sub clock input pin
UART5 serial data input pin
P01
79
Main clock output pin
General-purpose I/O port
SIN5 *
—
12
Pin description
General-purpose I/O port
A
External interrupt request 13 input pin
(Selected along with P35 pin)
UART6 serial communication clock I/O pin
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (2 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
Pin name
I/O circuit
type
P06
84
119
INT14R
General-purpose I/O port
A
OUT4 *
—
120
General-purpose I/O port
A
OUT5 *
—
86
121
87
122
88
123
89
124
90
125
93
126
94
127
95
128
—
129
—
130
—
131
—
132
—
133
—
134
CM71-10139-5E
INT15R
P10
TIN1
P11
TOT1
P12
SIN3
P13
SOT3
P14
SCK3
P15
SIN4
P16
SOT4
P17
SCK4
P20
PPG0
P21
PPG2
P22
PPG4
P23
PPG6
P24
PPG8
P25
PPGA
External interrupt request 14 input pin
(Selected along with P36 pin)
Output compare 4 output pin
P07
85
Pin description
External interrupt request 15 input pin
(Selected along with P37 pin)
Output compare 5 output pin
A
A
A
A
A
A
A
A
A
A
A
A
A
A
General-purpose I/O port
Reload timer 1 external event input pin
General-purpose I/O port
Reload timer 1 output pin
General-purpose I/O port
UART3 serial data input pin
General-purpose I/O port
UART3 serial data output pin
General-purpose I/O port
UART3 serial communication clock I/O pin
General-purpose I/O port
UART4 serial data input pin
General-purpose I/O port
UART4 serial data output pin
General-purpose I/O port
UART4 serial communication clock I/O pin
General-purpose I/O port
PPG0 output pin
General-purpose I/O port
PPG2 output pin
General-purpose I/O port
PPG4 output pin
General-purpose I/O port
PPG6 output pin
General-purpose I/O port
PPG8 output pin
General-purpose I/O port
PPGA output pin
FUJITSU MICROELECTRONICS LIMITED
13
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (3 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
—
135
—
136
Pin name
P26
PPGC
P27
PPGE
I/O circuit
type
A
A
P30
—
137
138
—
139
—
140
—
141
—
142
—
143
—
2
RX2
A
P31
A
TX2
INT10
INT11
INT12
A
P36
INT14
—
14
PPG9 *
A
External interrupt request 13 input pin
(Selected along with P05 pin)
External interrupt request 14 input pin
(Selected along with P06 pin)
External interrupt request 15 input pin
(Selected along with P07 pin)
PPG9 output pin
PPGD *
PPGF *
PPGB output pin
General-purpose I/O port
A
P43
6
External interrupt request 12 input pin
(Selected along with P04 pin)
General-purpose I/O port
*
P42
5
External interrupt request 11 input pin
(Selected along with P03 pin)
General-purpose I/O port
A
P41
99
—
A
P40
98
External interrupt request 10 input pin
(Selected along with P30 pin)
General-purpose I/O port
INT15
PPGB
CAN2 output pin
General-purpose I/O port
A
P37
—
General-purpose I/O port
General-purpose I/O port
INT13
4
CAN2 input pin
General-purpose I/O port
A
P35
97
PPGE output pin
General-purpose I/O port
A
P34
—
General-purpose I/O port
General-purpose I/O port
A
P33
3
PPGC output pin
External interrupt request 10 input pin
(Selected along with P32 pin)
P32
96
General-purpose I/O port
General-purpose I/O port
INT10C
—
Pin description
PPGD output pin
General-purpose I/O port
A
PPGF output pin
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (4 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
100
7
1
8
2
9
3
10
4
11
5
12
6
13
7
14
8
—
A
IN1
P46
A
IN2
P47
A
IN3
P50
A
PPG1
P51
A
PPG3
P52
A
PPG5
P53
A
PPG7
IN6 *
P60
OUT6
General-purpose I/O port
Input capture 1 input pin
General-purpose I/O port
Input capture 2 input pin
General-purpose I/O port
Input capture 3 input pin
General-purpose I/O port
PPG1 output pin
General-purpose I/O port
PPG3 output pin
General-purpose I/O port
PPG5 output pin
General-purpose I/O port
PPG7 output pin
Input capture 4 input pin
Input capture 5 input pin
Input capture 6 input pin
General-purpose I/O port
A
IN7 *
19
Input capture 0 input pin
General-purpose I/O port
A
P57
18
General-purpose I/O port
General-purpose I/O port
A
*
P56
17
Pin description
General-purpose I/O port
A
IN4 *
IN5
12
—
P45
P55
11
—
A
IN0
16
10
—
P44
I/O circuit
type
P54
15
9
—
Pin name
Input capture 7 input pin
General-purpose I/O port
*
P61
A
General-purpose I/O port
—
20
—
21
P62
A
General-purpose I/O port
—
22
P63
A
General-purpose I/O port
—
25
P64
A
General-purpose I/O port
OUT7
A
Output compare 6 output pin
P70
16
26
RX0
INT8
CM71-10139-5E
Output compare 7 output pin
General-purpose I/O port
A
CAN0 input pin
External interrupt request 8 input pin
(Selected along with P00 pin)
FUJITSU MICROELECTRONICS LIMITED
15
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (5 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
17
27
(76)
—
(77)
—
28
A
TX0
29
19
31
20
32
21
33
22
34
23
38
27
RX1
A
28
P73
A
TX1
P74
A
OUT0
P75
A
OUT1
P76
A
OUT2
P77
A
OUT3
P80
FRCK0
P81
FRCK1
A
A
A
P83
FRCK3
29
41
30
42
43
P84
TIN2
P85
TOT2
A
A
A
AN0
B
AN1
PPG2R
16
CAN1 output pin
General-purpose I/O port
Output compare 0 output pin
General-purpose I/O port
Output compare 1 output pin
General-purpose I/O port
Output compare 2 output pin
General-purpose I/O port
Output compare 3 output pin
General-purpose I/O port
Free-run timer 0 external clock input pin
General-purpose I/O port
Free-run timer 1 external clock input pin
Free-run timer 2 external clock input pin
Free-run timer 3 external clock input pin
General-purpose I/O port
Reload timer 2 external event input pin
General-purpose I/O port
Reload timer 2 output pin
A/D converter analog input pin
PPG0 output pin (Selected along with P20 pin)
P91
44
General-purpose I/O port
General-purpose I/O port
PPG0R
32
CAN1 input pin
General-purpose I/O port
*
P90
31
CAN0 output pin
General-purpose I/O port
FRCK2 *
40
General-purpose I/O port
External interrupt request 9 input pin
(Selected along with P01 pin)
P82
39
Pin description
General-purpose I/O port
INT9
30
—
P71
I/O circuit
type
P72
18
—
Pin name
General-purpose I/O port
B
A/D converter analog input pin
PPG2 output pin (Selected along with P21 pin)
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (6 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
Pin name
I/O circuit
type
P92
33
45
General-purpose I/O port
AN2
B
PPG4R
46
General-purpose I/O port
AN3
B
PPG6R
47
AN4
B
48
—
General-purpose I/O port
AN5
PPGAR
B
*
49
General-purpose I/O port
AN6
B
PPGCR *
—
50
General-purpose I/O port
AN7
B
PPGER *
—
51
General-purpose I/O port
AN8
B
PA1
43
52
General-purpose I/O port
AN9
B
PA2
44
53
—
45
54
46
55
47
56
General-purpose I/O port
AN10
SCK2R
PA3
AN11
PA4
AN12
PA5
AN13
A/D converter analog input pin
UART2 serial data output pin
(Selected along with PE1 pin)
SOT2R *
—
A/D converter analog input pin
UART2 serial data input pin
(Selected along with PE0 pin)
SIN2R *
—
A/D converter analog input pin
PPGE output pin (Selected along with P27 pin)
PA0
42
A/D converter analog input pin
PPGC output pin (Selected along with P26 pin)
P97
38
A/D converter analog input pin
PPGA output pin (Selected along with P25 pin)
P96
37
A/D converter analog input pin
PPG8 output pin (Selected along with P24 pin)
P95
36
CM71-10139-5E
General-purpose I/O port
PPG8R *
—
A/D converter analog input pin
PPG6 output pin (Selected along with P23 pin)
P94
35
A/D converter analog input pin
PPG4 output pin (Selected along with P22 pin)
P93
34
Pin description
B
*
A/D converter analog input pin
UART2 clock I/O pin (Selected along with PE2 pin)
B
B
B
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
FUJITSU MICROELECTRONICS LIMITED
17
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (7 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
48
57
49
58
Pin name
PA6
AN14
PA7
AN15
I/O circuit
type
B
B
PB0
50
62
INT0R
B
63
INT1R
B
64
INT2R
B
65
INT3R
B
66
INT4R
General-purpose I/O port
B
AN20 *
—
67
INT5R
General-purpose I/O port
B
AN21 *
—
68
INT6R
General-purpose I/O port
B
AN22 *
—
69
—
18
INT7R
AN23 *
External interrupt request 6 input pin
(Selected along with PF6 pin)
A/D converter analog input pin
PB7
57
External interrupt request 5 input pin
(Selected along with PF5 pin)
A/D converter analog input pin
PB6
56
External interrupt request 4 input pin
(Selected along with PF4 pin)
A/D converter analog input pin
PB5
55
External interrupt request 3 input pin
(Selected along with PF3 pin)
A/D converter analog input pin
PB4
54
External interrupt request 2 input pin
(Selected along with PF2 pin)
General-purpose I/O port
AN19 *
—
External interrupt request 1 input pin
(Selected along with PF1 pin)
A/D converter analog input pin
PB3
53
External interrupt request 0 input pin
(Selected along with PF0 pin)
General-purpose I/O port
AN18 *
—
A/D converter analog input pin
A/D converter analog input pin
PB2
52
General-purpose I/O port
General-purpose I/O port
AN17 *
—
A/D converter analog input pin
A/D converter analog input pin
PB1
51
General-purpose I/O port
General-purpose I/O port
AN16 *
—
Pin description
General-purpose I/O port
B
External interrupt request 7 input pin
(Selected along with PF7 pin)
A/D converter analog input pin
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (8 / 9)
Pin No.
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
—
70
—
71
—
74
—
75
—
76
—
77
—
78
—
79
Pin name
PC0
AN24
PC1
AN25
PC2
AN26
PC3
AN27
PC4
AN28
PC5
AN29
PC6
AN30
PC7
AN31
I/O circuit
type
B
B
B
B
B
B
B
B
PD0
60
80
TIN0
81
62
82
63
83
64
84
65
85
66
86
67
87
13
88
CM71-10139-5E
PD1
TOT0
PD2
SIN0
PD3
SOT0
PD4
SCK0
PD5
SIN1
PD6
SOT1
PD7
SCK1
PE0
SIN2
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A
Reload timer 0 external event input pin
A/D converter trigger input pin
ATGX
61
Pin description
A
A
A
A
A
A
A
A
General-purpose I/O port
Reload timer 0 output pin
General-purpose I/O port
UART0 serial data input pin
General-purpose I/O port
UART0 serial data output pin
General-purpose I/O port
UART0 serial communication clock I/O pin
General-purpose I/O port
UART1 serial data input pin
General-purpose I/O port
UART1 serial data output pin
General-purpose I/O port
UART1 serial communication clock I/O pin
General-purpose I/O port
UART2 serial data input pin
FUJITSU MICROELECTRONICS LIMITED
19
CHAPTER 1 OVERVIEW
1.6 List of Pin Functions
MB91210 Series
Table 1.6-1 List of Pin Functions (9 / 9)
Pin No.
I/O circuit
type
LQFP-100
(MB91F211B)
LQFP-144
(MB91213A/
F213A/F218S)
14
89
15
90
—
91
—
94
—
95
—
96
—
97
—
98
−
99
−
100
26, 59, 92
1, 24, 37, 73, 93,
112
VCC
—
Power-supply input pins (5V)
25, 58, 75, 91
23, 36, 72, 92,
108, 111, 144
VSS
—
GND pins
24
35
C
—
Power regulating capacitor pin
39
59
AVCC
—
A/D converter analog power-supply input pin
40
60
AVSS
—
A/D converter analog GND pin
AVRL
—
Power regulating capacitor pin
41
61
AVRH
—
Power regulating capacitor pin
Pin name
PE1
SOT2
PE2
SCK2
PF0
INT0
PF1
INT1
PF2
INT2
PF3
INT3
PF4
INT4
PF5
INT5
PF6
INT6
PF7
INT7
A
A
A
A
A
A
A
A
A
A
Pin description
General-purpose I/O port
UART2 serial data output pin
General-purpose I/O port
UART2 serial communication clock I/O pin
General-purpose I/O port
External interrupt request 0 input pin
General-purpose I/O port
External interrupt request 1 input pin
General-purpose I/O port
External interrupt request 2 input pin
General-purpose I/O port
External interrupt request 3 input pin
General-purpose I/O port
External interrupt request 4 input pin
General-purpose I/O port
External interrupt request 5 input pin
General-purpose I/O port
External interrupt request 6 input pin
General-purpose I/O port
External interrupt request 7 input pin
* : MB91213A/F213A/F218S only.
20
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB91210 Series
1.7
I/O Circuit Types
This section shows the I/O circuit types of the MB91210 series.
■ I/O Circuit Types
Table 1.7-1 I/O Circuit Types (1 / 2)
Type
Circuit
A
Remarks
Pull-up control
P-ch
P-ch
Pout
N-ch
N-ch
Nout
• CMOS level output
• CMOS hysteresis input
(With standby-time input cut-off function)
• Automotive input
(With standby-time input cut-off function)
Pull-down control
CMOS hysteresis input
Automotive input
Standby control for
input control
B
Pull-up control
• CMOS level output
• CMOS hysteresis input
(With standby-time input cut-off function)
P-ch
P-ch
Pout
N-ch
N-ch
Nout
• Automotive input
(With standby-time input cut-off function)
• A/D analog input
Pull-down control
CMOS hysteresis input
Automotive input
Standby control for
input control
Analog input
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
21
CHAPTER 1 OVERVIEW
1.7 I/O Circuit Types
MB91210 Series
Table 1.7-1 I/O Circuit Types (2 / 2)
Type
C
Circuit
Remarks
Masked ROM product
Hysteresis input
Mask ROM product
• CMOS hysteresis input
• MD2 With pull-down control
Flash memory product
• With high-voltage control signal for testing
• MD2 Without pull-down control
Flash memory product
N-ch
N-ch
N-ch
N-ch
Control signal
Mode input
N-ch
Diffused resistor
D
• CMOS hysteresis input
Pull-up resistor
CMOS hysteresis input
E
• CMOS hysteresis input
CMOS hysteresis input
Pull-down resistor
OA
OB
X1
Xout
Oscillation circuit
High-speed oscillation feedback resistor =
approx. 1 MΩ
X0
Standby control signal
WA
WB
X1A
Xout
Oscillation circuit
Low-speed oscillation feedback resistor =
approx. 20 MΩ (MB91213A/F213A/F218S/V210)
approx. 10 MΩ (MB91F211B)
X0A
Standby control signal
22
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 2
HANDLING DEVICES
This chapter provides precautions on handling the FR
family.
2.1 Precautions on Handling the Device
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
23
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
2.1
MB91210 Series
Precautions on Handling the Device
This section explains how to prevent latch-up, how to process pins and circuits as well
as the input method used on power-up.
■ Preventing Latch-up
Latch-up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is
applied to either the input or output pins, or when a voltage is applied between VCC and VSS that exceeds
the rated voltage. When latch-up occurs, the power-supply current surges significantly, which may damage
some elements due to the excess heat, so great care must be taken to ensure that the maximum rating is
never exceeded during use.
■ Processing Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Process such pins by, for
example, using a pull-up or pull-down resistor.
■ Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
■ Power Supply Pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the
device to avoid abnormal operations including latch-up. However, you must connect these VCC and VSS
pins to the same potential power supply and a ground line externally to lower the electro-magnetic emission
level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform
to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins
of this device at the lowest possible impedance.
It is also advisable to connect a ceramic capacitor of approx. 0.1 μF as a bypass capacitor between VCC
and VSS near this device.
The MB91210 series comes with a built-in regulator. When using the device at 5V, supply 5V to the VCC
pins and always connect a bypass capacitor of approx. 1 μF to the C pin for use by the regulator.
■ Crystal Oscillation Circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to
ground are located as close to the device as possible. It is also strongly recommended to design the PC
board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation
can be expected with such a layout.
If you plan to use a dual clock product as a single clock product, the sub clock is still required.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
24
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
MB91210 Series
■ Note on Using an External Clock
When using an external clock, you must input clock signals with opposite phase to the X0 and X1 pins
simultaneously. Note that you cannot input signals only to the X0 pin. Furthermore, do not use STOP mode
(oscillation stop mode), when using an external clock (the X1 pin stops by "H" output in STOP mode).
Figure 2.1-1 Example of Using External Clock (Normal)
X0
X1
(Note) STOP mode (oscillation stop mode) cannot be used.
Always use NC pin and OPEN pin opened.
■ Mode Pins (MD0 to MD3)
These pins should be connected directly to VCC pin or VSS pin. To prevent the device from
malfunctioning due to noise, the pattern length between each mode pin and VCC or VSS on the printed
circuit board should be as short as possible, and they should be connected at low impedance. Furthermore,
connect the MD3 pin via a resistance of 0Ω.
■ Operation on Power-up
On power-up, you must maintain the INITX pin at the "L" level.
■ Source Oscillation Input on Power-up
When turning on the power, maintain clock input until the device is released from the oscillation
stabilization wait state.
■ Treatment of A/D Converter Power Supply Pins
Even when the A/D converter is not used, connect the A/D converter power supply pins to ensure AVCC =
VCC and AVSS = VSS.
■ A/D Converter Analog Power Supply Input Sequence
Be sure to turn on the power (AVCC, AVRH) to the A/D converter and apply analog inputs (AN0 to
AN31) after turning on the digital power (VCC). For power-off, turn off the digital power (VCC) after
turning off the power to the A/D converter and turning off the analog inputs. When using a pin designed
also for an analog input as an input port, be sure that the input voltage does not exceed AVCC.
■ Caution for Operation during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
■ Writing to Flash
Note that Flash write/erase is not guaranteed in the sub clock mode.
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CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
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MB91210 Series
CM71-10139-5E
CHAPTER 3
CPU AND CONTROL
BLOCK
This chapter provides basic information required to
understand the CPU core functions of the FR family. It
covers architecture, specifications, and instructions.
3.1 Memory Space
3.2 Internal Architecture
3.3 Programming Model
3.4 Data Structure
3.5 Memory Map
3.6 Branch Instructions
3.7 EIT (Exception, Interruption, and Trap)
3.8 Operating Modes
3.9 Clock Generation Control
3.10 Clock Division
3.11 Device State Control
3.12 Main Oscillation Stabilization Wait Timer
3.13 Pseudo Sub Clock
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CHAPTER 3 CPU AND CONTROL BLOCK
3.1 Memory Space
3.1
MB91210 Series
Memory Space
The logical address space of the FR family is 4GB (232 locations) and the CPU performs
linear access.
■ Direct Addressing Area
The following area of the address space is used for I/O.
This area is called the direct addressing area and the operand address can be specified directly in the
instruction.
A direct area varies depending on the size of the accessed data as follows.
: 000H to 0FFΗ
• Byte data access
• Half-word data access : 000H to 1FFH
• Word data access
: 000H to 3FFH
■ Memory Map
Figure 3.1-1 shows the memory map of the device.
Figure 3.1-1 Memory Map
0000 0000H
0000 0400H
Single-chip
mode
I/O
I/O
0001 0000H
0002 0000H Access inhibit
F-bus area
0004 0000H
D-bus area
0005 0000H
User ROM
area
Internal ROM / External ROM /
external bus
external bus
mode
mode
I/O
I/O
I/O
I/O
Access inhibit
Access inhibit
F-bus area
F-bus area
D-bus area
D-bus area
Direct
addressing area
See I/O Map.
User ROM
area
0010 0000H
External
area
Access inhibit
External
area
FFFF FFFFH
The mode is determined by the vector fetch performed after INITX is negated. (For details on setting the
mode, see "3.8.2 Mode Setting".)
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
3.2
Internal Architecture
This section outlines the structure of the internal architecture and the instructions used
for the FR family.
■ Overview of Internal Architecture
As well as adopting a RISC architecture, the FR family CPU is a high performance core featuring advanced
instructions for embedded applications.
■ Features of Internal Architecture
• Adoption of a RISC architecture
Basic instruction: one instruction = one cycle
• 32-bit architecture
General-purpose registers: 32 bits × 16 registers
• Linear memory space of 4 GB
• Multipliers provided
32-bit by 32-bit multiplication: 5 cycles
16-bit by 16-bit multiplication: 3 cycles
• Reinforced interrupt processing function
High-speed response speed (6 cycles)
Multiple interruption supported
Level mask function (16 levels)
• Reinforced instruction for I/O operation
Memory-to-memory transfer instruction
Bit manipulation instruction
• High code efficiency
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode / Stop mode
Gear function
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
■ Structure of Internal Architecture
The CPU of the FR family uses the Harvard architecture with separate instruction bus and data bus.
A 32-bit ←→ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between
the CPU and peripherals.
A Harvard ←→ Princeton bus converter is connected to the I-bus and D-bus to provide an interface
between the CPU and the bus controller.
Figure 3.2-1 shows the structure of the internal architecture.
Figure 3.2-1 Structure of Internal Architecture
FR CPU
D-bus
I-bus
32
I-address
Harvard
32
External address
24
I-data
External data
16
D-address
32
Data RAM
D-data
Princeton bus
converter
32
32-bit
Address
32
16-bit bus
converter
Data
32
16
F-bus
R-bus
Peripheral resource
30
Internal I/O
Bus converter
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
■ CPU
The 32-bit RISC architecture of the FR family has been compactly implemented in this CPU. A five-stage
instruction pipeline system is used to enable the execution of one instruction per cycle. The pipeline is
composed of the following stages.
Figure 3.2-2 shows the instruction pipeline.
• Instruction fetch (IF)
: Outputs an instruction address and fetches the instruction.
• Instruction decode (ID) : Decodes the fetched instruction. It also reads from a register.
• Execution (EX)
: Executes an arithmetic operation.
• Memory access (MA)
: Accesses the memory for load or store operation.
• Write-back (WB)
: Writes the arithmetic operation result (or loaded memory data) to a register.
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
Instructions are always executed in the correct order. This means that if Instruction A enters the pipeline
before Instruction B, Instruction A always reaches the write-back stage before Instruction B does.
As a rule, the execution speed of instructions is based on one instruction per cycle. However, more than one
cycle are required to execute instructions such as load/store instructions with memory wait, branch
instructions without a delay slot, and multi-cycle instructions. Moreover, the execution speed of an
instruction also decreases, when the supply of the instruction is delayed.
■ 32-bit ←→ 16-bit Bus Converter
The 32-bit ←→ 16-bit bus converter provides an interface between the F-bus (high-speed 32-bit access)
and the R-bus (16-bit access) to enable data access from the CPU to the built-in peripheral circuits.
When 32-bit access is performed from the CPU to the R-bus, the bus converter converts it into two sets of
16-bit access. Some built-in peripheral circuits have access-width restrictions.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
■ Harvard ←→ Princeton Bus Converter
The Harvard ←→ Princeton bus converter adjusts instruction access from the CPU to data access to
provide a seamless interface with an external bus.
The CPU is structured in the Harvard architecture in which the instruction bus exists independently from
the data bus. On the other hand, the bus controller, which controls the external bus, is structured in the
single-bus-based Princeton architecture. This bus converter assigns an order of priority for the instruction
access from the CPU and data access to control access to the bus controller. This mechanism allows the
external bus access order to be always optimized.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
3.2.1
Overview of Instructions
The FR family supports not only a regular RISC instruction set but also logic
operations, bit manipulation and direct addressing instructions, which are optimized for
embedded applications.
Each instruction is 16-bit length (some are 32 or 48-bit length) to ensure excellent
efficiency in memory usage.
The instruction set can be divided into the following function groups:
• Arithmetic operation
• Load/store
• Branching
• Logic operation and bit manipulation
• Direct addressing
• Others
■ Arithmetic Operation
There are the standard arithmetic operation instructions (addition, subtraction and comparison) and shift
instructions (logic shift and arithmetic operation shift) available. For addition and subtraction, the following
operations are also possible: operation with carry, used for multi-word operation; and operation with an
unchanged flag value, useful for address calculation. The provided instructions also include 32-bit-by-32bit and 16-bit-by-16-bit multiplication instructions, 32-bit-by-32-bit step division instructions as well as
immediate transfer instructions that set an immediate value in a register, and register-to-register transfer
instructions.
All arithmetic operation instructions are performed using general-purpose registers and multiplication and
division registers in the CPU.
■ Load and Store
Load and store instructions are used to read from and write to external memory. They are also used to read
from and write to peripheral circuits (I/O) on the chip.
The load and store instructions are provided with three access lengths: byte, half-word, and word length. In
addition to the general register-indirect memory addressing, some instructions support register-indirect
memory addressing with the displacement or register increment/decrement feature.
■ Branching
Branch instructions are used for branching, calling, interrupting and returning purposes. Some have a delay
slot while the others don't, enabling instruction optimization for each application. The branch instructions
are detailed in "3.6 Branch Instructions".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.2 Internal Architecture
MB91210 Series
■ Arithmetic Operation and Bit Manipulation
The logic operation instruction can be used to perform a logic operation such as AND, OR, EOR between
general-purpose registers or between a general-purpose register and the memory (and I/O). The bit
manipulation instruction can be used to directly manipulate the content of the memory (and I/O).
General register indirect memory addressing is supported.
■ Direct Addressing
The direct addressing instruction is used to provide access between I/O and a general-purpose register or
between I/O and the memory. I/O address can be specified directly in the instruction, rather than indirectly
by a register, to enable high-speed, highly efficient access. Some instructions support register-indirect
memory addressing with the register increment/decrement feature.
■ Overview of Other Instructions
Other instructions are used to set a flag in the PS register, perform stack operation, and add sign/zero
extension. They also include function entry/exit instructions supporting high-level language as well as
register multi-load/store instructions.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
3.3
Programming Model
This section explains the programming model, general-purpose registers and dedicated
registers of the FR family.
■ Basic Programming Model
Figure 3.3-1 shows the basic programming model of FR family.
Figure 3.3-1 Basic Programming Model
32-bit
Initial value
XXXX XXXXH
R0
...
R1
...
...
General-purpose
register
...
...
...
R12
R13
AC
R14
FP
R15
SP
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication/division result
register
MDH
MDL
CM71-10139-5E
...
...
ILM
...
XXXX XXXXH
0000 0000H
SCR
FUJITSU MICROELECTRONICS LIMITED
CCR
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
3.3.1
MB91210 Series
General-purpose Registers
Registers R0 to R15 are general-purpose registers.
They are used as accumulators for various types of arithmetic operations and as
memory access pointers.
■ General-purpose Register
Figure 3.3-2 shows the configuration of a general-purpose register.
Figure 3.3-2 Configuration of General-purpose Register
32-bit
Initial value
R0
XXXX XXXXH
R1
R12
R13
R14
AC
FP
XXXX XXXXH
R15
SP
0000 0000H
Of the 16 registers, the following are intended for special applications; therefore, they have some advanced
instructions.
• R13:
Virtual accumulator
• R14:
Frame pointer
• R15:
Stack pointer
The initial value at a reset is undefined for R0 to R14, but defined as 00000000Η (SSP value) for R15.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
3.3.2
Dedicated Register
A dedicated register is used for a specific purpose.
The FR family is provided with the following dedicated register:
• PS (Program Status)
• CCR (Condition Code Register)
• SCR (System Condition code Register)
• ILM
• PC (Program Counter)
• TBR (Table Base Register)
• RP (Return Pointer)
• SSP (System Stack Pointer)
• USP (User Stack Pointer)
• Multiply & Divide register
■ PS (Program Status)
PS is a register that retains the program status and divided into three parts: ILM, SCR and CCR.
All of the undefined bits are reserved. Reading them always returns "0".
Writing is invalid.
The register configuration of PS (Program Status) is shown below.
bit 31
20
16
ILM
CM71-10139-5E
10
87
SCR
FUJITSU MICROELECTRONICS LIMITED
0
CCR
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ CCR (Condition Code Register)
The register configuration of CCR (Condition Code Register) is shown below.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
S
I
N
Z
V
C
--00XXXXB
[bit5] S: Stack flag
This bit selects the stack pointer to be used as R15.
Value
Description
0
SSP is used as R15.
Set to "0" automatically when EIT occurs. (Note that the value before the bit was cleared is
saved on the stack.)
1
USP is used as R15.
• It is cleared to "0" by a reset.
• Set it to "0" when executing the RETI instruction.
[bit4] I: Interrupt enable flag
This bit enables and disables a user interrupt request.
Value
Description
0
Disables user interrupt.
Cleared to "0" when INT instruction is executed. (Note that the value before the bit was
cleared is saved on the stack.)
1
Enables user interrupt.
Controls the masking of a user interrupt request using the value retained in ILM.
It is cleared to "0" by a reset.
[bit3] N: Negative flag
This bit indicates the sign when the arithmetic operation result is represented as a two's complement
integer.
Value
Description
0
Indicates that the operation has resulted in a positive value.
1
Indicates that the operation has resulted in a negative value.
The initial state at a reset is undefined.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
[bit2] Z: Zero flag
This bit indicates whether the operation result is "0".
Value
Description
0
Indicates that the operation has resulted in a value other than "0".
1
Indicates that the operation has resulted in "0".
The initial state at a reset is undefined.
[bit1] V: Overflow flag
This bit assumes the operand used in an operation as a two's complement integer and indicates whether
an overflow has occurred due to the operation.
Value
Description
0
Indicates that no overflow has occurred due to the operation.
1
Indicates that an overflow has occurred due to the operation.
The initial state at a reset is undefined.
[bit0] C: Carry flag
This bit indicates whether an operation has resulted in a carry or borrow from the most significant bit.
Value
Description
0
Indicates that neither a carry nor borrow has occurred.
1
Indicates that either a carry or borrow has occurred.
The initial state at a reset is undefined.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ SCR (System Condition Code Register)
The register configuration of SCR (System Condition code Register) is shown below.
bit10
bit9
bit8
Initial value
D1
D0
T
XX0B
[bit10, bit9] D1, D0: Step division flag
These bits hold the intermediate data obtained when step division is executed.
Do not modify these bits while division processing is being executed. To perform other processing
while executing a step division, save and restore the value of the PS register to ensure that the step
division is restarted.
• The initial state at a reset is undefined.
• To set these bits, execute the DIV0S instruction with the dividend and the divisor to be referenced.
• To forcibly clear these bits, execute the DIV0U instruction.
• Do not perform the process expecting the D0 and D1 bits in the PS register before EIT branching in
the EIT processing routine, which simultaneously accepts DIV0S/DIV0U instruction, user interrupt
and NMI.
• The D0 and D1 bits in the PS register may not indicate the correct value if the operation is stopped
by break or step execution immediately before the DIV0S/DIV0U instruction. Note, however, that
the correct value will be calculated after return.
[bit8] T: Step trace trap flag
This flag specifies whether the step trace trap is to be enabled.
Value
Description
0
Disables the step trace trap.
1
Enables the step trace trap.
With this setting, all the user NMI and user interrupts are prohibited.
• This bit is initialized to "0" by a reset.
• The step trace trap function is used by an emulator. When used by the emulator, this function cannot
be used in the user program.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ ILM
The register configuration of ILM is shown below.
bit20
bit19
bit18
bit17
bit16
Initial value
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
This register retains an interrupt level mask value. The value retained in the ILM register is used as a level
mask.
The CPU accepts only interrupt requests sent to it with an interrupt level higher than the level indicated by
the ILM.
The highest level is 0 (00000B) and the lowest level is 31 (11111B).
There are restrictions on the values that can be set by the program.
• If the original value is between 16 and 31:
The new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
• If the original value is between 0 and 15:
An arbitrary value between 0 and 31 may be set.
This register is initialized to 15 (01111B) by a reset.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ PC (Program Counter)
The register configuration of PC (Program Counter) is shown blow.
bit31
bit0
PC
Initial value
XXXXXXXXH
[bit31 to bit0]
These bits indicate the address of the instruction executed with the program counter.
Bit0 is set to "0", when PC is updated with the execution of an instruction. Bit0 may be set to "1" only
when an odd-numbered location is specified as the branch target address. Even in this case, bit0 is
invalid; therefore, an instruction must be placed at the address with a multiple of 2.
The initial value at a reset is undefined.
■ TBR (Table Base Register)
The register configuration of TBR (Table Base Register) is shown below.
bit31
bit0
TBR
Initial value
000FFC00H
TBR is used to retain the start address of the vector table to be used for EIT processing.
The initial value at a reset is 000FFC00H.
■ RP (Return Pointer)
The register configuration of RP (Return Pointer) is shown below.
bit31
bit0
RP
Initial value
XXXXXXXXH
RP retains the address used for returning from the sub routine.
When the CALL instruction is executed, the PC value is transferred to the RP.
When the RET instruction is executed, the content of RP is transferred to PC.
The initial value at a reset is undefined.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ SSP (System Stack Pointer)
The register configuration of SSP (System Stack Pointer) is shown below.
bit31
bit0
SSP
Initial value
00000000H
SSP stands for system stack pointer.
It serves as R15 when the S flag is set to "0".
The SSP can also be specified explicitly. Moreover, it can be used as a stack pointer to specify the stack
that will save the PS and PC when EIT occurs.
The initial value at a reset is 00000000H.
■ USP (User Stack Pointer)
The register configuration of USP (User Stack Pointer) is shown below.
bit31
USP
bit0
Initial value
XXXXXXXXH
USP stands for user stack pointer.
It serves as R15 when the S flag is set to "1".
USP can also be specified explicitly.
The initial value at a reset is undefined.
It cannot be used with the RETI instruction.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.3 Programming Model
MB91210 Series
■ Multiply & Divide Register (Multiply & Divide Register)
The register configuration of the Multiply & Divide register is shown below.
bit31
bit0
MDH
MDL
This register is used for multiplication and division. Each is 32-bit length.
The initial value at a reset is undefined.
• For multiplication:
The 64-bit operation result from a 32-bit-by-32-bit multiplication is stored in the multiplication/division
result storage register in the following format.
MDH : Upper 32 bits
MDL : Lower 32 bits
For a 16-bit-by-16-bit multiplication, the result is stored in the following format.
MDH : Undefined
MDL : Result of 32 bits
• For division:
The dividend is stored in MDL when the calculation starts.
When a division is performed by executing DIV0S/DIV0U, DIV1, DIV2, DIV3 or DIV4S instruction,
the result is stored in MDL and MDH.
MDH : Remainder
MDL : Quotient
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CHAPTER 3 CPU AND CONTROL BLOCK
3.4 Data Structure
MB91210 Series
3.4
Data Structure
This section explains the data structure of the FR family.
■ Bit Ordering
The FR family has adopted a little endian system for bit ordering. Figure 3.4-1 shows the data arrangement
for bit ordering.
Figure 3.4-1 Data Arrangement for Bit Ordering
bit
31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
MSB
0
LSB
■ Byte Ordering
The FR family has adopted a big endian system for byte ordering.
Figure 3.4-2 shows the data arrangement for byte ordering.
Figure 3.4-2 Data Arrangement for Byte Ordering
Memory
MSB
bit 31
23
15
7
LSB
0
10101010B 11001100B 11111111B 00010001B
Bit
7
0
Location n 10101010B
Location (n+1) 11001100B
Location (n+2) 11111111B
Location (n+3) 00010001B
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CHAPTER 3 CPU AND CONTROL BLOCK
3.4 Data Structure
MB91210 Series
■ Word Alignment
● Program access
The program for the FR family must be placed at the address with a multiple of 2.
Bit0 in the PC is set to "0" when the PC is updated with the execution of an instruction.
Bit0 may be set to "1" only when an odd-numbered location is specified as the branch target address. Even
in this case, bit0 is invalid; therefore, an instruction must be placed at the address with a multiple of 2.
There is no exception for the use of an odd-numbered address.
● Data access
In the FR family, addresses are aligned forcibly, depending on the width of the data to be accessed, as
shown below.
: The address has a multiple of 4. (The lowest 2 bits are forcibly set to 00B.)
Word access
Half-word access : The address has a multiple of 2. (The lowest bit is forcibly set to "0".)
Byte access
: Not forcibly set
In word and half-word data access, some bits are forcibly set to "0" only for the calculation result of the
effective address.
In the addressing mode @(R13, Ri), for example, the register before addition is used as it is (even when the
least significant bit is "1"), and the low bits of the addition result are masked. In other words, the register
before the calculation is not masked.
[Example] LD @(R13, R2), R0
R13
00002222H
R2
00000003H
+)
Addition result
Address pin
46
00002225H
Lower 2 bits forcibly masked
00002224H
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CHAPTER 3 CPU AND CONTROL BLOCK
3.5 Memory Map
MB91210 Series
3.5
Memory Map
This section explains the memory map of the FR family.
■ Memory Map
The FR family has a 32-bit linear address space.
The memory map is illustrated in Figure 3.5-1.
Figure 3.5-1 Memory Map
0000 0000H
Byte data
0000 0100H
Half-word data
0000 0200H
Direct
addressing area
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
Initial area
FFFF FFFFH
● Direct Addressing Area
The following area of the address space is used for I/O. In this area, the operand address can be specified
directly in the instruction, using the direct addressing.
The size of an address area that can be specified for direct addressing varies, depending on the data length.
: 000H to 0FFH
• Byte data (8-bit)
• Half-word data (16-bit) : 000H to 1FFH
• Word data (32-bit)
: 000H to 3FFH
● Initial Area of the Vector Table
The area from 000FFC00H to 000FFFFFH is used as the initial area of the EIT vector table.
The vector table to be used during EIT processing can be placed at any address by rewriting TBR.
However, the table will be relocated to this address when initialized by a reset.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.6 Branch Instructions
3.6
MB91210 Series
Branch Instructions
In the FR family, a branch instruction can be specified to operate either with or without
a delay slot.
■ Operation with a Delay Slot
● Instructions
The instructions listed below perform operation with a delay slot.
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D
label9
BNE:D label9
BC:D
label9
BNC:D label9
BN:D
label9
BP:D
BV:D
label9
BNV:D label9
BLT:D
label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D
label9
BHI:D
label9
label9
● Operating Explanation
In the operation with a delay slot, branching occurs after the instruction placed immediately after the
branch instruction (called "delay slot") is executed before the instruction at the branch target is executed.
The dummy execution speed is 1 cycle because the instruction with a delay slot is executed before
branching. However, if a valid instruction cannot be placed in the delay slot, a NOP instruction must be
placed instead.
[Example]
; Alignment of instructions
ADD
R1, R2
;
BRA:D LABEL
; Branch instruction
MOV
R2, R3
; Delay slot ---- executed before branching
R3, @R4
; Branch target
…
LABEL:
ST
In case of a conditional branch instruction, the instruction placed in the delay slot is executed regardless of
whether the branch condition is satisfied.
In case of delayed branch instructions, the execution order of some instructions appears to be inverted. This
is however only applicable to the updating of PC. Other operations (updating/referencing a register, etc.)
are executed in the order as described.
The following section provides specific details.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.6 Branch Instructions
MB91210 Series
• Ri, which is referenced by the JMP:D @Ri / CALL:D @Ri instruction, is not affected even when
updated by the instruction in the delay slot.
[Example]
LDI:32
#Label, R0
JMP:D
@R0
LDI:8
#0,
; Branch to Label
R0
; Branch target address not affected
…
• RP, which is referenced by the RET:D instruction, is not affected even when updated by the instruction
in the delay slot.
[Example]
RET:D
MOV
; Branch to the preset address indicated by RP
R8,
RP
; Return operation not affected
…
• The flag referenced by the Bcc:D rel instruction is also not affected by the instruction in the delay slot.
[Example]
ADD
#1,
R0
BC:D
Overflow
AND CCR #0
; Flag change
; Branching based on the execution result of the above instruction
; This flag update is not referenced by the above branch instruction.
…
• When RP is referenced by the instruction in the delay slot of the CALL:D instruction, the updated
content is read by the CALL:D instruction.
[Example]
CALL:D Label
MOV
RP,
; RP update and branching
R0
; RP of the execution result in the CALL:D above is transferred
…
■ Restrictions on the Operation with a Delay Slot
● Instructions that can be placed in the delay slot
Only the instructions which meet the following conditions can be executed in the delay slot.
• 1-cycle instruction
• Not a branch instruction
• Instruction that does not affect the operation even if the order is changed
The "1-cycle instruction" refers to an instruction with "1", "a", "b", "c" or "d" indicated in the column for
the number of cycles on the instruction list.
● Step trace trap
Step trace trap does not occur between the execution of a branch instruction with a delay slot and the delay
slot.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.6 Branch Instructions
MB91210 Series
● Interrupt and NMI
Neither an interrupt nor NMI can be accepted between the execution of a branch instruction with a delay
slot and the delay slot.
● Undefined instruction exception
If the delay slot contains an undefined instruction, no undefined instruction exception occurs. In this case,
the undefined instruction operates as a NOP instruction.
■ Operation without a Delay Slot
● Instructions
The instructions listed below perform branching without a delay slot.
JMP
@Ri
CALL
label12
CALL
@Ri
RET
BRA
label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE
label9
BGT
label9
BLS
label9
BHI
label9
● Operating Explanation
The operation without a delay slot is executed strictly according to the order of instructions as arranged.
The immediately following instruction is never executed before branching.
[Example]
; Alignment of instructions
ADD
R1, R2
;
BRA
LABEL
; Branch instruction (no delay slot)
MOV
R2, R3
; Not executed
…
LABEL: ST
R3, @R4 ; Branch target
The number of execution cycles for a branch instruction without a delay slot is 2 cycles for branching, and
1 cycle for no branching.
As a branch instruction without a delay slot cannot contain an appropriate instruction in a delay slot, it can
have higher instruction code efficiency than a branch instruction with a delay slot, which describes NOP.
High execution speed and code efficiency can be both achieved by selecting the operation with a delay slot
when a valid instruction can be placed in the delay slot, and selecting the operation without a delay slot
otherwise.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
3.7
EIT (Exception, Interruption, and Trap)
EIT, which is the generic term for "Exception", "Interrupt", and "Trap", indicates that the
current program is suspended due to an event generated when another program is
being executed while the current one is still running.
The exception is an event which occurs in relation to the context under execution.
Execution continues from the instruction that caused the exception.
The interruption is an event which occurs without any relation to the context under
execution. The event source is hardware.
The trap is an event which occurs in relation to the context under execution. Some
traps, such as system calls, are specified by the program. Execution continues from the
instruction after the instruction that caused the trap.
■ Features of EIT
• Interruption supporting multiple interrupt
• Level mask function for interruption (15 levels available to the user)
• Trap instruction (INT)
• EIT for activating an emulator (hardware/software)
■ EIT Sources
The following are used as EIT sources:
• Reset
• User interrupt (internal resource and external interrupts)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absent trap
• Coprocessor error trap
Note:
There are EIT-related restrictions on the delay slot of a branch instruction. For details, see "3.6
Branch Instructions".
■ Returning from EIT
The RETI instruction is used for the return from EIT.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
3.7.1
MB91210 Series
EIT Interrupt Levels
The interrupt levels range from 0 to 31, which are managed by 5 bits.
■ EIT Interrupt Levels
Table 3.7-1 shows the allocation of these levels.
Table 3.7-1 Interrupt Levels
Level
Interrupt source
Binary
Decimal
00000
0
(Reserved for system)
…
…
…
…
…
…
00011
3
(Reserved for system)
00100
4
00101
5
(Reserved for system)
…
…
…
…
…
…
01110
14
(Reserved for system)
01111
15
NMI (for user)
10000
16
Interrupt
10001
17
Interrupt
…
…
…
…
…
…
11110
30
Interrupt
11111
31
—
{
INTE instruction
Step trace trap
Note
If the original value of ILM is between 16 and 31,
the value of this range cannot be set in the ILM by
the program.
When ILM is set, a user interrupt is disabled.
When ICR is set, an interrupt is disabled.
The operation is enabled at levels 16 to 31.
The interrupt level does not affect the undefined interrupt exception, coprocessor absent trap, coprocessor
error trap or INT instruction. It also does not change ILM.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
■ I Flag
I flag is used to enable or disable interrupts. It is provided as bit4 in CCR of the PS register.
Value
Description
0
Disables user interrupt.
Cleared to "0" when INT instruction is executed.
(Note that the value before the bit was cleared is saved on the stack.)
1
Enables user interrupt.
The masking of the interrupt request is controlled by the value retained in ILM.
■ ILM
ILM is a PS register (bit20 to bit16) that retains the interrupt level mask value.
The CPU accepts only interrupt requests sent to it with an interrupt level higher than the level indicated by
the ILM.
The highest level is 0 (00000B) and the lowest level is 31 (11111B).
There are restrictions on the values that can be set by the program. If the original value is between 16 and
31, the new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
If the original value is between 0 and 15, an arbitrary value between 0 and 31 may be set. STILM
instruction is used to set an arbitrary value.
■ Level Masking for Interrupt/NMI
When NMI or interrupt request is generated, the interrupt level of the interrupt source (see Table 3.7-1) is
compared with the level mask value retained in ILM. Then, if the following condition is satisfied, it will be
masked and the request will not be accepted.
Interrupt level of interrupt source ≥ Level mask value
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
3.7.2
MB91210 Series
ICR (Interrupt Control Register)
ICR is a register located in the interrupt controller and used to set a certain level to each
interrupt request. ICR is provided to support the input of various interrupt requests. ICR
is mapped in the I/O space and accessed from the CPU via a bus.
■ Bit Configuration of ICR
The bit configuration of ICR is shown below.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
Initial value
---111111B
[bit4]
ICR4 is always set to "1".
[bit3 to bit0] ICR3 to ICR0
These are lower 4 bits of the interrupt level of the corresponding interrupt source. They are readable/
writable. Combined with bit4, ICR can be used to set any value between 16 and 31.
■ ICR Mapping
Table 3.7-2 lists interrupt sources, interrupt control registers, and interrupt vectors.
Table 3.7-2 Interrupt Sources, Interrupt Control Registers and Interrupt Vectors
Interrupt control register
Interrupt
source
Corresponding interrupt vector
No.
No.
Address
Address
Hexadecimal
Decimal
IRQ00
ICR00
00000440H
10H
16
TBR+3BCH
IRQ01
ICR01
00000441H
11H
17
TBR+3B8H
IRQ02
ICR02
00000442H
12H
18
TBR+3B4H
…
…
…
…
…
…
…
…
…
…
…
…
IRQ45
ICR45
0000046DH
3DH
61
TBR+308H
IRQ46
ICR46
0000046EH
3EH
62
TBR+304H
IRQ47
ICR47
0000046FH
3FH
63
TBR+300H
• TBR initial value: 000FFC00H
• For details, see "CHAPTER 6 INTERRUPT CONTROLLER".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
3.7.3
SSP (System Stack Pointer)
SSP is used as the pointer that indicates the stack for saving and restoring data at the
acceptance of EIT or return.
■ SSP (System Stack Pointer)
The register configuration of SSP is shown below.
bit31
bit0
Initial value
00000000H
SSP
The content is reduced by 8 during EIT processing and 8 is added to it during return from the EIT executed
by the RETI instruction.
The initial value at a reset is 00000000H.
SSP also serves as R15 (general-purpose register) when the S flag in CCR is set to "0".
■ Interrupt Stack
This is the area indicated by SSP, where the PC and PS values are saved and restored.
After an interrupt, the PC is stored at the address indicated by SSP, and the PS at the address (SSP + 4).
Figure 3.7-1 shows the interrupt stack.
Figure 3.7-1 Interrupt Stack
[Before interrupt]
SSP
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
CM71-10139-5E
80000000H
7FFFFFFCH
7FFFFFF8H
FUJITSU MICROELECTRONICS LIMITED
PS
PC
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
3.7.4
MB91210 Series
TBR (Table Base Register)
The TBR (Table Base Register) indicates the start address of the EIT vector table.
■ TBR (Table Base Register)
The register configuration of TBR is shown below.
bit31
bit0
Initial value
000FFC00H
TBR
The vector address is calculated by adding the TBR and offset value determined for each EIT source.
The initial value at a reset is 000FFC00H.
■ EIT Vector Table
The EIT vector area is the 1 KB area starting from the address indicated by TBR.
Each vector consists of 4 bytes. The relationship between the vector number and vector address is as
follows.
vctadr = TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr : Vector address
vctofs : Vector offset
vct
: Vector number
The lower 2 bits of the addition result are always treated as 00B.
The initial area of the vector table by a reset is the area between 000FFC00H and 000FFFFFH.
Special functions are assigned to some vectors.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
Table 3.7-3 shows the vector table.
Table 3.7-3 Vector Table (1 / 3)
Interrupt source
Interrupt No.
HexaDecimal
decimal
Interrupt level
Offset
Default TBR address
Reset *1
0
00H
-
3FCH
000FFFFCH
Mode vector *1
1
01H
-
3F8H
000FFFF8H
(Reserved)
2
02H
-
3F4H
000FFFF4H
(Reserved)
3
03H
-
3F0H
000FFFF0H
(Reserved)
4
04H
-
3ECH
000FFFECH
(Reserved)
5
05H
-
3E8H
000FFFE8H
(Reserved)
6
06H
-
3E4H
000FFFE4H
Coprocessor absent trap
7
07H
-
3E0H
000FFFE0H
Coprocessor error trap
8
08H
-
3DCH
000FFFDCH
INTE instruction
9
09H
-
3D8H
000FFFD8H
(Reserved)
10
0AH
-
3D4H
000FFFD4H
(Reserved)
11
0BH
-
3D0H
000FFFD0H
Step trace trap
12
0CH
-
3CCH
000FFFCCH
NMI request (tool)
13
0DH
-
3C8H
000FFFC8H
Undefined instruction exception
14
0EH
-
3C4H
000FFFC4H
NMI request
15
0FH
15(FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10H
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11H
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12H
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13H
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14H
ICR04
3ACH
000FFFACH
External interrupt 5
21
15H
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16H
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17H
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18H
ICR08
39CH
000FFF9CH
Reload timer 1
25
19H
ICR09
398H
000FFF98H
Reload timer 2
26
1AH
ICR10
394H
000FFF94H
Maskable interrupt source *2
27
1BH
ICR11
390H
000FFF90H
Maskable interrupt source *2
28
1CH
ICR12
38CH
000FFF8CH
Maskable interrupt source *2
29
1DH
ICR13
388H
000FFF88H
Maskable interrupt source *2
30
1EH
ICR14
384H
000FFF84H
Maskable interrupt source *2
31
1FH
ICR15
380H
000FFF80H
Maskable interrupt source *2
32
20H
ICR16
37CH
000FFF7CH
Maskable interrupt source *2
33
21H
ICR17
378H
000FFF78H
Maskable interrupt source *2
34
22H
ICR18
374H
000FFF74H
Maskable interrupt source *2
35
23H
ICR19
370H
000FFF70H
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
Table 3.7-3 Vector Table (2 / 3)
Interrupt source
Interrupt No.
HexaDecimal
decimal
Interrupt level
Offset
Default TBR address
Maskable interrupt source *2
36
24H
ICR20
36CH
000FFF6CH
Maskable interrupt source *2
37
25H
ICR21
368H
000FFF68H
Maskable interrupt source *2
38
26H
ICR22
364H
000FFF64H
Maskable interrupt source *2
39
27H
ICR23
360H
000FFF60H
Maskable interrupt source *2
40
28H
ICR24
35CH
000FFF5CH
Maskable interrupt source *2
41
29H
ICR25
358H
000FFF58H
Maskable interrupt source *2
42
2AH
ICR26
354H
000FFF54H
Maskable interrupt source *2
43
2BH
ICR27
350H
000FFF50H
Maskable interrupt source *2
44
2CH
ICR28
34CH
000FFF4CH
Maskable interrupt source *2
45
2DH
ICR29
348H
000FFF48H
Maskable interrupt source *2
46
2EH
ICR30
344H
000FFF44H
Overflow of time-base timer
47
2FH
ICR31
340H
000FFF40H
Maskable interrupt source *2
48
30H
ICR32
33CH
000FFF3CH
Maskable interrupt source *2
49
31H
ICR33
338H
000FFF38H
Maskable interrupt source *2
50
32H
ICR34
334H
000FFF34H
Maskable interrupt source *2
51
33H
ICR35
330H
000FFF30H
Maskable interrupt source *2
52
34H
ICR36
32CH
000FFF2CH
Maskable interrupt source *2
53
35H
ICR37
328H
000FFF28H
Maskable interrupt source *2
54
36H
ICR38
324H
000FFF24H
Maskable interrupt source *2
55
37H
ICR39
320H
000FFF20H
Maskable interrupt source *2
56
38H
ICR40
31CH
000FFF1CH
Maskable interrupt source *2
57
39H
ICR41
318H
000FFF18H
Maskable interrupt source *2
58
3AH
ICR42
314H
000FFF14H
Maskable interrupt source *2
59
3BH
ICR43
310H
000FFF10H
Maskable interrupt source *2
60
3CH
ICR44
30CH
000FFF0CH
Maskable interrupt source *2
61
3DH
ICR45
308H
000FFF08H
Maskable interrupt source *2
62
3EH
ICR46
304H
000FFF04H
Delayed interrupt source bit
63
3FH
ICR47
300H
000FFF00H
(Reserved) (used in REALOS)
64
40H
-
2FCH
000FFEFCH
(Reserved) (used in REALOS)
65
41H
-
2F8H
000FFEF8H
(Reserved)
66
42H
-
2F4H
000FFEF4H
(Reserved)
67
43H
-
2F0H
000FFEF0H
(Reserved)
68
44H
-
2ECH
000FFEECH
(Reserved)
69
45H
-
2E8H
000FFEE8H
(Reserved)
70
46H
-
2E4H
000FFEE4H
(Reserved)
71
47H
-
2E0H
000FFEE0H
(Reserved)
72
48H
-
2DCH
000FFEDCH
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
Table 3.7-3 Vector Table (3 / 3)
Interrupt source
Interrupt No.
HexaDecimal
decimal
Interrupt level
Offset
Default TBR address
(Reserved)
73
49H
-
2D8H
000FFED8H
(Reserved)
74
4AH
-
2D4H
000FFED4H
(Reserved)
75
4BH
-
2D0H
000FFED0H
(Reserved)
76
4CH
-
2CCH
000FFECCH
(Reserved)
77
4DH
-
2C8H
000FFEC8H
(Reserved)
78
4EH
-
2C4H
000FFEC4H
(Reserved)
79
4FH
-
2C0H
000FFEC0H
80
50H
2BCH
000FFEBCH
to
to
to
to
Used by INT instruction
-
255
FFH
000H
000FFC00H
*1: Even when the TBR value is modified, the fixed addresses 000FFFFCH and 000FFFF8H are used for the reset vector
and mode vector respectively.
*2: The maskable interrupt source is defined for each model. For the vector table used in the MB91210 series, see
"APPENDIX B Interrupt Vector".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
3.7.5
MB91210 Series
Multiple EIT Processing
When more than one EIT source occur at the same time, the CPU selects and accepts
only one source. After executing the EIT sequence, it detects another EIT source to
continue the operation.
When acceptable EIT sources can no longer be detected, the CPU executes the
instruction of the handler for the last accepted EIT source.
For this reason, the following 2 elements determine the handler execution sequence for
EIT sources that occur at the same time.
• Priority order for accepting EIT sources
• Masking condition for other sources when one is accepted
■ Priority Levels for Accepting EIT Sources
The priority level for accepting EIT sources is the level used to select the source for executing the EIT
sequence in which PS and PC are saved, PC is updated (if necessary), and other sources are masked.
The handler of the first accepted source is not necessarily executed first.
Table 3.7-4 shows the priority levels for accepting EIT sources and the masking condition for other
sources.
Table 3.7-4 Priority Levels for Accepting EIT Sources and Masking Condition for Other
Sources
Priority level of
acceptance
Sources
Masking of other sources
1
Reset
Other sources are abandoned
2
Undefined instruction exception
Cancel
3
INT instruction
I flag = 0
4
Coprocessor absent trap
Coprocessor error trap
5
User interrupt
ILM = Level of accepted source
6
NMI (for user)
ILM=15
7
(INTE instruction)
ILM=4 *
8
NMI (for emulator)
ILM=4
9
Step trace trap
ILM=4
10
IINTE instruction
ILM=4
—
*: Level 6 is only possible when the INTE instruction and NMI for the emulator occur simultaneously.
(In the MB91210 series, the NMI for the emulator is used for a break by data access.)
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
Table 3.7-5 shows the execution sequence of the handlers of EIT sources that occur at the same time, in
conjunction with the masking process for the other sources after one is accepted.
Table 3.7-5 Execution Sequence of EIT Handlers
Execution Sequence of
Handlers
Source
1
Reset *1
2
Undefined instruction exception
3
Step trace trap *2
4
I NTE instruction *2
5
NMI (for user)
6
INT instruction
7
User interrupt
8
Coprocessor absent trap and coprocessor error trap
*1: Other sources are abandoned.
*2: When step execution is used for the INTE instruction, only the EIT for step trace trap occurs.
The source by INTE is ignored.
Figure 3.7-2 shows the multiple EIT processing.
Figure 3.7-2 Multiple EIT Processing
Main routine
Handler of NMI
Handler of INT
instruction
Priority level
(High) NMI occurs
(1) Executed first
(Low) INT instruction
is executed
(2) Executed next
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
3.7.6
MB91210 Series
Operation
This section explains various types of operations in the FR family.
In the following explanation, "PC" for the origin of transfer refers to the address of the
instruction that detected each EIT source. Depending on the instruction which has
detected EIT, the "address of the next instruction" varies as follows.
• LDI:32 …… PC + 6
• LDI:20, COPOP, COPLD, COPST, COPSV …… PC + 4
• Other instructions …… PC + 2
■ Operation of User Interrupt and NMI
When a user interrupt or user NMI interrupt request is generated, the following sequence is used to
determine whether or not to accept the request.
[Determining whether or not to accept interrupt request]
1) The interrupt levels of requests generated at the same time are compared, and the request with the
highest level (the smallest numeric value) is selected and retained.
For the level used for the comparison, the value held in the corresponding ICR is used for a
maskable interrupt and the predefined constant is used for the NMI.
2) If multiple requests holding the same level are generated, the request with the smallest interrupt
number is selected.
3) When the interrupt level is the same as the level mask value or greater, the interrupt request is
masked and is not accepted. When the interrupt level is lower than the level mask value, go to 4).
4) If the I flag is "0" when the selected interrupt request is intended for a maskable interrupt, the
interrupt request is masked and is not accepted. If the I flag is "1", go to 5).
If the selected interrupt request is intended for NMI, go to 5) regardless of the value of the I flag.
5) When the above conditions are met, the interrupt request is accepted at a boundary between
instruction processing sessions.
If a user interrupt/NMI request is accepted upon the detection of an EIT request, the CPU operates as
described below, using the interrupt number corresponding to the accepted interrupt request.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) Address of next instruction → (SSP)
5) Interrupt level of accepted request → ILM
6) "0" → S flag
7) (TBR + Vector offset of accepted interrupt request) → PC
Note: What is contained in parentheses represents a register-specified address.
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3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
A new EIT is detected before executing the first instruction of the handler upon the completion of the
interrupt sequence. If an acceptable EIT has been generated at this point, the CPU moves to the EIT
processing sequence.
If the ORCCR, STILM, or MOV Ri, PS instructions is executed to enable an interrupt while a user interrupt
or NMI source is being generated, the above instruction may be executed twice, before and after the
interrupt handler. Note however that this does not affect the operation as it is only the same value that is set
twice.
Do not perform the process expecting the PS register content before EIT branching in the EIT processing
routine.
■ Operation of INT Instruction
INT #u8:
Branches to the interrupt handler for the vector indicated by u8.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) PC + 2 → (SSP)
5) "0" → I flag
6) "0" → S flag
7) (TBR + 3FCH-4 × u8) → PC
■ Operation of INTE Instruction
INTE:
Branches to the interrupt handler for the vector #9.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) PC + 2 → (SSP)
5) 00100B → ILM
6) "0" → S flag
7) (TBR + 3D8H) → PC
Do not use the INTE instruction during the processing routine for the INTE instruction and step trace trap.
Also, EIT is not generated by INTE during the step execution.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
■ Operation of Step Trace Trap
A trap occurs on the execution of each instruction and execution breaks, if the T flag in SCR of PS is set to
enable the step trace function.
[Conditions for Step Trace Trap Detection]
1) T flag =1
2) Not a delayed branch instruction
3) During the execution of processing routine other than for INTE instruction and step trace trap
4) When the above conditions are met, execution breaks at a boundary of instruction operation.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) Address of next instruction → (SSP)
5) 00100B → ILM
6) "0" → S flag
7) (TBR + 3CCH) → PC
When the T flag is set to enable step trace trap, user NMI and user interrupt are disabled. Moreover, EIT is
not generated by the INTE instruction.
In the FR family, a trap is generated from the instruction following the instruction that set the T flag.
■ Operation of Undefined Instruction Exception
An undefined instruction exception occurs when an undefined instruction is detected during instruction
decoding.
[Conditions for detecting undefined instruction exception]
1) Undefined instruction detected during instruction decoding
2) Placed outside a delay slot (Not immediately after a delayed branch instruction).
3) When the above conditions are met, an undefined instruction exception occurs and execution breaks.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) PC → (SSP)
5) "0" → S flag
6) (TBR + 3C4H) → PC
The address saved as the PC is the address of the instruction that has detected the undefined instruction
exception.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.7 EIT (Exception, Interruption, and Trap)
MB91210 Series
■ Coprocessor Absent Trap
A coprocessor absent trap occurs, if a coprocessor instruction is executed to use an unmounted coprocessor.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) Address of next instruction → (SSP)
5) "0" → S flag
6) (TBR + 3E0H) → PC
■ Coprocessor Error Trap
A coprocessor error trap occurs, if an error occurs while using a coprocessor and then a coprocessor
instruction is executed to operate that coprocessor.
[Operation]
1) SSP-4 → SSP
2) PS → (SSP)
3) SSP-4 → SSP
4) Address of next instruction → (SSP)
5) "0" → S flag
6) (TBR + 3DCH) → PC
■ Operation of RETI Instruction
The RETI instruction is used to return from the EIT processing routine.
[Operation]
1) (R15) → PC
2) R15 + 4 → R15
3) (R15) → PS
4) R15 + 4 → R15
The RETI instruction must be executed when the S flag is "0".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.8 Operating Modes
3.8
MB91210 Series
Operating Modes
This section explains the operating modes of the FR family.
■ Overview of Operating Modes
The operating modes include bus mode and access mode.
■ Bus Mode
Bus mode is a mode that controls the operations of the internal ROM and external access function. It is
selected based on the content of the mode setting pins (MD3, MD2, MD1, and MD0) and the ROMA bit in
the mode data.
■ Access Mode
Access mode is a mode that controls the external data bus width. It is selected by the WTH1 and WTH0
bits in the mode register.
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3.8 Operating Modes
MB91210 Series
3.8.1
Bus Modes
The FR family is provided with the following 3 bus modes.
For details, see "3.1 Memory Space".
■ Bus Mode 0 (Single-chip Mode)
In this mode, the internal I/O, F-bus RAM and F-bus ROM are enabled, but access to other areas is
disabled.
The external pins serve as either a peripheral or general-purpose port. They do not function as bus pins.
■ Bus Mode 1 (Internal ROM / External Bus Mode)
In this mode, the internal I/O, F-bus RAM and F-bus ROM are enabled, and access to an externally
accessible area is handled as access to an external space. Some external pins serve as bus pins.
■ Bus Mode 2 (External ROM / External Bus Mode)
In this mode, the internal I/O and F-bus RAM are enabled but access to F-bus ROM is disabled so that all
access is handled as access to an external space. Some external pins serve as bus pins.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.8 Operating Modes
3.8.2
MB91210 Series
Mode Setting
In the FR family, each operating mode is set by the mode pins (MD3, MD2, MD1, and
MD0) and the mode register (MODR).
■ Mode Pins
4 pins (MD3, MD2, MD1, and MD0) are used for specification related to mode vector fetch.
Table 3.8-1 lists specification pertaining to mode vector fetch.
Table 3.8-1 Mode Vector Fetch Related Specification
Mode pins
MD3 to MD0
Mode name
Reset vector
access area
0000B
Internal ROM mode vector
Internal
0001B
External ROM mode vector
External
Remarks
Prohibited setting in
MB91210 series
Note that settings other than as specified above are prohibited.
Note:
The FR family does not support the external mode vector fetch using a multiplex bus.
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3.8 Operating Modes
MB91210 Series
■ Mode Register (MODR)
The data written to the mode register by mode vector fetch is called mode data.
Once the mode register (MODR) is set, the device runs in the operating mode set according to this register.
The mode register is set by any reset source. It cannot be written from the user program.
It can however be rewritten in emulator mode. In this case, use an 8-bit data transfer instruction.
It cannot be written by a 16/32-bit transfer instruction.
The details of the mode register are as follows.
[Detailed explanation of mode register]
MODR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0
0
0
0
0
ROMA
WTH1
WTH0
XXXXXXXXB
Operating mode setting bits
[bit7 to bit3] Reserved bits
Always set them to 00000B.
Operation is not guaranteed if a value other than 00000B is set.
[bit2] ROMA (Internal ROM enable bit)
This bit determines whether to enable the internal F-bus ROM areas.
ROMA
Function
Remarks
0
External ROM mode
Internal ROM area (50000H to FFFFFH) becomes an external
area.
1
Internal ROM mode
Internal F-bus ROM are enabled.
[bit1, bit0] WTH1, WTH0 (Bus width specification bits)
These bits specify the bus width for external bus mode.
CM71-10139-5E
WTH1
WTH0
Function
Remarks
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
—
Setting is prohibited
1
1
Single-chip mode
Single-chip mode
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CHAPTER 3 CPU AND CONTROL BLOCK
3.9 Clock Generation Control
3.9
MB91210 Series
Clock Generation Control
This section explains the clock generation control.
■ Generating Internal Operating Clock
In the MB91210 series, the internal operating clock is generated as follows.
• Selecting the source clock:
The clock supply source is selected.
• Generating the base clock
The base clock is generated by dividing the source clock by 2 or using PLL oscillation.
• Generating each internal clock
The base clock is divided to generate 4 types of operating clocks to be supplied to each block.
The following section explains how to generate and control each clock.
For details of the registers and flags in the following explanation, see "3.10.1 Block Diagram of Clock
Generation Control Block" and "3.10.2 Detailed Explanation of Registers in Clock Generation Control
Block".
■ Selecting the Source Clock
This section explains how the source clock is selected.
The source clock is the source oscillation generated in the built-in oscillation circuit by connecting an
oscillator to the X0/X1 and X0A/X1A external oscillator pin inputs.
All clock sources including the external bus clock are supplied from within MB91210 series.
The external oscillator pins and built-in oscillation circuit can use 2 types of clocks (main clock and sub
clock) and also switch between them during operation at any time.
• Main clock : Generated from the X0 and X1 pin inputs and intended for use as the high-speed clock.
• Sub clock : Generated from the X0A and X1A pin inputs and intended for use as the low-speed clock.
The main clock is multiplied by using the internally controllable main PLL.
The internal base clock can be selectively generated from the following source clocks.
• Main clock divided by 2
• Main clock multiplied using the main PLL
• Sub clock as it is
φ shows two dividing frequency of the source clock or the basic clock that PLL is oscillated. Therefore, the
system base clock is a clock generated in the internal base clock generation of the above-mentioned.
Selection of the source clock is controlled by the clock source control register (CLKR) setting.
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3.9 Clock Generation Control
MB91210 Series
3.9.1
PLL Control
The PLL oscillation circuit for the main clock can be controlled by enabling or disabling
its operation (oscillation) and setting the multiplication rate.
Each control operation is performed by setting the clock source control register
(CLKR).
This section explains such control operations.
■ Enabling PLL Operation
PLL1EN (bit10) in the clock source control register (CLKR) is used to enable/disable the oscillation
operation of the main PLL.
PLL2EN (bit11) in the clock source control register (CLKR) is used to enable/disable the oscillation
operation of the sub clock.
Both the PLL1EN and PLL2EN bits are initialized to "0" after a setting initialization reset (INIT) and the
PLL oscillation operation is stopped. While it is stopped, the PLL output cannot be selected as the source
clock.
Once program operation has started, set the multiplication rate for the PLL to be used as the clock source
and enable its operation, and then wait for the PLL lock wait time to elapse before switching the source
clock. In this case, it is recommended to use the time-base timer interrupt for the PLL lock wait time.
The PLL cannot be halted while the PLL output is selected as the source clock. (Writing to the register is
ignored.) When you wish to stop the PLL in such case as changing to stop mode, select the main clock
divided by 2 as the source clock before halting the PLL.
Note that if OSCD1 (bit0) and OSCD2 (bit1) in the standby control register (STCR) are set so that
oscillation is stopped during stop mode, the corresponding PLL is automatically stopped when moving to
stop mode. Therefore, it is not necessary to set the bits again to stop the operation. Afterwards, when
returning from the stop mode, PLL automatically begins the oscillation operation. The PLL does not stop
automatically if the oscillation is set to continue during stop mode. In this case, stop the operation before
changing to stop mode if necessary.
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3.9 Clock Generation Control
MB91210 Series
■ PLL Multiplication Rate
The multiplication rate for the main PLL is set by PLL1S2, PLL1S1 and PLL1S0 (bit14 to bit12) in the
clock source control register (CLKR).
All the bits are initialized to "0" after a setting initialization reset (INIT).
[Setting PLL multiplication rate]
When changing the PLL multiplication rate from its initial value, change it before or at the same time as
enabling the PLL operation after the program operation starts. Then wait for the PLL lock wait time to
elapse before switching the source clock. In this case, it is recommended to use the time-base timer
interrupt for the PLL lock wait time.
If you wish to change the PLL multiplication rate during operation, first change the source clock to any
clock other than the corresponding PLL. Then after changing the rate, wait for the lock wait time to
elapse before switching back the source clock, as in the case above.
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3.9 Clock Generation Control
MB91210 Series
3.9.2
Oscillation Stabilization Wait and PLL Lock Wait Time
If the operation of the clock selected as the source clock is not stable, an oscillation
stabilization wait time is required.
After the PLL starts operating, a wait time is required until the PLL locks in order to
allow the output to stabilize at the specified frequency.
This section explains the wait time used in various situations.
■ Wait Time after Power-on
After power-on, it is necessary to input "L" level to the INITX pin input (setting initialization reset pin). In
this state, as none of the PLL's are allowed to operate, it is not required to consider a lock wait time.
■ Wait Time after Setting Initialization
When a setting initialization reset (INIT) is released, the device goes to the oscillation stabilization wait
state. Here, the set oscillation stabilization wait time is internally generated.
In this state, as none of the PLL's are allowed to operate, it is not required to consider a lock wait time.
■ Wait Time after Enabling PLL Operation
If you enable the PLL in the stop state to operate after the program operation starts, the output of that PLL
cannot be used until the lock wait time elapses.
If the corresponding PLL is not selected as the source clock, the program can be executed even during the
lock wait time.
In this case, it is recommended to use the time-base timer interrupt for the PLL lock wait time.
■ Wait Time after Changing PLL Multiplication Rate
Even if you change the multiplication rate setting of the currently operating PLL after the program
operation starts, the output of that PLL must not be used until the lock wait time elapses.
If the corresponding PLL is not selected as the source clock, the program can be executed even during the
lock wait time.
In this case, the time-base timer interrupt can be used for the PLL lock wait time.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.9 Clock Generation Control
MB91210 Series
■ Wait Time after Returning from Stop Mode
After the program operation starts, the oscillation stabilization wait time set by the program is generated
internally after the device moves to stop mode and then returns from that mode.
If the device is set to halt the oscillation circuit for the clock selected as the source clock during stop mode,
the longer of the oscillation stabilization wait time for the oscillation circuit and the lock wait time for the
PLL in use is required as the wait time. Therefore, set the oscillation stabilization wait time before
changing to stop mode.
If the device is set not to halt the oscillation circuit for the clock selected as the source clock during stop
mode, the PLL is not halted automatically. Accordingly, no oscillation stabilization wait time is required
unless you halt the PLL. It is recommended to set the oscillation stabilization wait time to the minimum
value before changing to stop mode.
■ Wait Time after Switching from the Sub Clock to the Main Clock
When using the PLL after switching from the sub clock to the main clock, the output of that PLL must not
be used regardless of the value of PLL1EN (bit2) in the clock source register (CLKR), until the lock wait
time elapses.
If the corresponding PLL is not selected as the source clock, the program can be executed even during the
lock wait time.
In this case, it is recommended to use the time-base timer interrupt for the PLL lock wait time.
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3.9 Clock Generation Control
MB91210 Series
3.9.3
Clock Distribution
The operating clock for each function is generated based on the base clock generated
from the source clock.
There are 3 different internal operating clocks in total, and each clock can set its own
division ratio, independently from the other clocks.
This section explains these internal operating clocks.
■ CPU Clock (CLKB)
This clock is used for the CPU, internal memory and internal bus.
The following circuits use this clock:
• CPU
• Built-in RAM and built-in ROM
• Bit search module
• I-bus, D-bus, X-bus, F-bus
• DMA controller
• DSU
The maximum operable frequency is 40 MHz. Therefore, do not set any frequency combination of the
multiplication rate and division ratio that will exceed this frequency.
■ Peripheral Clock (CLKP)
This clock is used for peripheral circuits and peripheral bus.
The circuits which use this clock are listed below:
• Peripheral bus
• Clock control block (bus interface component only)
• Interrupt controller
• Peripheral I/O port
• I/O port bus
• External interrupt input
• UART
• 16-bit timer
• A/D converter
• Free-run timer
• Reload timer
• Input capture
• Output compare
• PPG
The maximum operable frequency is 40 MHz. Therefore, do not set any frequency combination of the
multiplication rate and division ratio that will exceed this frequency.
The processing performance of CPU is influenced from the setting of the Flash Memory Wait Register
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3.9 Clock Generation Control
MB91210 Series
(FLWC). Please adjust the setting of this register to the best value. Moreover, please see "19.2.2 Flash
Memory Wait Register (FLWC)".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.10 Clock Division
MB91210 Series
3.10
Clock Division
Each internal operating clock can set its own division ratio from the base clock,
independently from the other clocks. This function allows the most suitable operating
frequency to be provided to each circuit.
■ Setting Division Ratio
The division ratio is set by DIVR0 (basic clock division setting register 0) and DIVR1 (basic clock division
setting register 1).
Each register contains 4 setting bits which correspond to each of the operating clocks, and the value
"register setting + 1" is used as the division ratio for the base clock of that particular clock. Even when the
division ratio is set to an odd number, the duty ratio is always 50%.
If the setting is modified, the modified division ratio becomes valid from the rising edge of the next clock
signal.
■ Initializing the Division Ratio Setting
Even when an operation initialization reset occurs, the division ratio setting is not initialized and the setting
before the occurrence of the reset is maintained. The setting is initialized only when a setting initialization
reset occurs. In the initial state, the division ratio is "1" for all except the peripheral clock (CLKP).
Therefore, make sure to set the division ratio before changing the source clock to a faster one.
Note:
The maximum operable frequency is defined for each clock. Operation is not guaranteed if a
frequency, in combination with the source clock selection, PLL multiplication rate setting and division
ratio setting, is set to exceed the maximum frequency. In particular, take care to follow the correct
order in conjunction with modifying the source clock selection setting.
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3.10 Clock Division
3.10.1
MB91210 Series
Block Diagram of Clock Generation Control Block
Figure 3.10-1 shows a block diagram of the clock generation control block.
For details of the registers shown in the diagram, see "3.10.2 Detailed Explanation of
Registers in Clock Generation Control Block".
■ Block Diagram of Clock Generation Control Block
Figure 3.10-1 Block Diagram of Clock Generation Control Block
Peripheral stop control register
[Clock generation block]
CPU clock division
Selector
External bus clock division
Main oscillation
stabilization
wait timer (when
sub clock is selected)
X1
X0A
X1A
Oscillation
circuit
Oscillation
circuit
Selector
Peripheral clock
External bus clock
CLKR register
PLL
Main
oscillation
1/2
Sub clock
oscillation
Selector
X0
Selector
Peripheral
stop control
Peripheral clock division
CPU clock
Stop control
R-bus
DIVR0/DIVR1 register
[Stop/sleep control block]
Internal interrupt
STCR register
Internal reset
State
transition
control
circuit
Stop state
Sleep state
Reset generation F/F
Internal reset (RST)
Reset generation F/F
Internal reset (INIT)
[Reset source circuit]
INITX
RSRR register
[Watchdog control block]
Watchdog F/F
WPR register
Time-base counter
CTBR register
TBCR register
Overflow detection FF
Interrupt enabled
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Selector
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Time-base timer
interrupt request
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3.10 Clock Division
MB91210 Series
3.10.2
Detailed Explanation of Registers in Clock Generation
Control Block
This section explains the registers in the clock generation control block.
■ RSRR: Reset Source Register/Watchdog Timer Control Register
The register configuration of the reset source register and watchdog timer control register is shown below.
RSRR
Address
000480H
bit15
bit14
Reserved Reserved
R
R
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
WDOG
R
ERST
R
SRST
R
Reserved
WT1
R/W
WT0
R/W
X-***-00B
R
(*)… Initialized by a source.
R/W: Readable/writable
R:
Read only
X:
Undefined
RSRR retains the source of the most recently generated reset, sets the watchdog timer cycle and controls its
activation.
When this register is read, the retained reset source is cleared after read. If more than one reset occur before
the register is read, reset source flags are accumulated, and as a result, the multiple flags are set.
Writing to this register activates the watchdog timer. After that, the watchdog timer continues to operate
until a reset (RST) occurs.
[bit15] Reserved: reserved bit
This bit is reserved.
[bit14] Reserved: reserved bit
This bit is reserved.
[bit13] WDOG: Watchdog reset generation flag
It indicates whether the watchdog timer has generated a reset.
Value
Description
0
Watchdog timer has not generated INIT.
1
Watchdog timer has generated INIT.
• This bit is cleared to "0" at a reset by the INITX pin input upon power-up or immediately after
reading.
• It is readable. Writing has no effect on the bit value.
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[bit12] ERST: External reset generation flag
This bit indicates whether the INITX pin input has generated a reset.
Value
Description
0
INITX pin input has not generated INIT.
1
INITX pin input has generated INIT.
• ERST is cleared to "0" immediately after reading.
• It is readable. Writing has no effect on the bit value.
• When turning on the power, apply the "L" level to the INITX pin for 8 ms or longer (when the
external oscillation frequency is 4 MHz). Otherwise, the flag may not be set.
[bit11] SRST: Software reset generation flag
This bit indicates whether a reset has been generated by writing to the SRST bit in the STCR register
(software reset).
Value
Description
0
Software reset has not generated INIT.
1
Software reset has generated INIT.
• This bit is cleared to "0" at a reset by the INITX pin input upon power-up or immediately after reading.
• It is readable. Writing has no effect on the bit value.
[bit10] Reserved: reserved bit
This bit is reserved.
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[bit9, bit8] WT1, WT0: Watchdog timer interval time selection bits
These bits are used to select the cycle for the watchdog timer.
Based on the value written to the bits, the watchdog timer cycle is selected from the 4 options shown in
the following table.
Minimum interval for writing to WPR,
required to prevent a watchdog reset
from being generated
Time from when the last "5AH" is
written to WPR to when a watchdog
reset is generated
WT1
WT0
0
0
φ × 216 (initial value)
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
(φ: Cycle of system base clock)
• These bits are initialized to 00B by a reset.
• They are readable. Writing is allowed only once after a reset; succeeding write operations are not
valid.
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3.10 Clock Division
MB91210 Series
■ STCR: Standby Control Register
The configuration of the standby control register is shown below.
STCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000481H
STOP
R/W
SLEEP
HIZ
SRST
OS1
OS0
OSCD2
OSCD1
00110011B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
STCR controls the operating mode of the device.
STCR is used to place the device in one of the 2 standby modes (stop/sleep) and stop the pin operation and
oscillation during stop mode as well as to set the oscillation stabilization wait time and issue a software
reset.
Note:
To place the device in a standby mode, always follow the sequence shown below.
(LDI#value_of_standby,R0) ; "value_of_standby" is the data written to STCR.
(LDI#_STCR,R12)
; "_STCR" is the address of STCR (481H)
STB
; Writing to standby control register (STCR)
R0,@R12
LDUB @R12,R0
; Reading from STCR for synchronous standby
LDUB @R12,R0
; Another dummy read from STCR
NOP
; NOP (for timing adjustment) × 5
NOP
NOP
NOP
NOP
[bit7] STOP: STOP mode bit
This bit directs the device to enter stop mode. If "1" is written to the SLEEP bit (bit6) and this bit at the
same time, the device enters stop mode, as the STOP mode bit has higher priority.
Value
Description
0
Device does not enter stop mode. [Initial value]
1
Device enters stop mode.
• This bit is initialized to "0" by a reset or an event that recovers the device from stop mode.
• It is readable and writable.
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[bit6] SLEEP: SLEEP mode bit
This bit directs the device to enter sleep mode. If "1" is written to the STOP bit (bit7) and this bit at the
same time, the device enters stop mode, as the STOP mode bit has higher priority.
Value
Description
0
Device does not enter sleep mode. [Initial value]
1
Device enters sleep mode.
• This bit is initialized to "0" by a reset or an event that recovers the device from sleep mode.
• It is readable and writable.
[bit5] HIZ: Hi-Z mode bit
This bit controls the pin state in stop mode.
Value
Description
0
Retains the pin state before transition to stop mode
1
Sets the pin output to high impedance during stop mode. [Initial value]
• This bit is initialized to "1" by a reset.
• It is readable and writable.
[[bit4] SRST: Software reset bit
SRST directs the issue of a software reset.
Value
Description
0
Issues a software reset
1
Does not issue a software reset. [Initial value]
• This bit is initialized to "1" by a reset.
• It is readable and writable. Reading always returns "1".
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[bit3, bit2] OS1, OS0: Oscillation stabilization wait time selection bits
These bits set the oscillation stabilization wait time after a reset or after the device returns from stop
mode.
Based on the value written to the bits, the oscillation stabilization wait time is selected from the 4
options shown in the following table.
OS1
OS0
Oscillation stabilization
wait time
Source oscillation:
4 MHz
Sub clock oscillation:
32 kHz
0
0
× 214
8.2 ms
512 ms
0
1
× 216
32.8 ms
2.0 s
1
0
× 210
512 μs
32.0 ms
1
1
× 21
1.0 μs
62.5 μs
φ represents the cycle of the system base clock. Here, it is twice the cycle of the input source oscillation.
• These bits are initialized to 00B by a reset.
• They are readable and writable.
• These bits are not initialized by software reset or watchdog reset.
[bit1] OSCD2: Sub clock oscillation stop bit
OSCD2 stops the sub clock oscillation in stop mode.
Value
Description
0
Does not stop sub clock oscillation during stop mode.
1
Stops sub clock oscillation during stop mode. [Initial value]
• This bit is initialized to "1" by a reset.
• It is readable and writable.
• For MB91F218S, "1" is fixed. Writing is invalid and reading returns "1".
[bit0] OSCD1: Main clock oscillation stop bit
OSCD1 stops the oscillation of the main clock in stop mode.
Value
Description
0
Does not stop the main clock oscillation during stop mode.
1
Stops the main clock oscillation during stop mode. [Initial value]
• This bit is initialized to "1" by a reset.
• It is readable and writable.
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MB91210 Series
■ TBCR: Time-base Counter Control Register
The configuration of the time-base counter control register is shown below.
TBCR
Address
bit15
bit14
bit13
bit12
bit11
000482H
TBIF
TBIE
TBC2
TBC1
TBC0
R/W
R/W
R/W
R/W
R/W
bit10
bit9
bit8
Reserved Reserved Reserved
R/W
R
Initial value
00XXXX11B
R
R/W: Readable/writable
R:
Read only
X:
Undefined
TBCR controls interrupts such as time-base timer interrupts.
TBCR is used to enable time-base timer interrupts as well as select the interrupt interval time.
[bit15] TBIF: Time-base timer interrupt flag
TBIF is a time-base timer interrupt flag.
It indicates that the time-base counter has exceeded the specified interval time (set by bit13 to bit11:
TBC2 to TBC0).
A time-base timer interrupt request is generated, if this bit is set to "1" while TBIE (bit14) is enabled to
generate an interrupt (TBIE=1).
Clearing source
Writing "0" through instruction
Setting source
Expiration of the set interval time
(Detecting the falling edge of the output of the time-base counter)
• This bit is initialized to "0" by a reset.
• It is readable and writable. For write operation, however, only "0" can be written. Writing "1" does
not change the bit value.
• Reading by read-modify-write (RMW) instruction always returns "1".
[bit14] TBIE: Time-base timer interrupt enable bit
TBIE enables the output of a time-base timer interrupt request.
TBIE controls the output of an interrupt request due to the expiration of the interval time of the timebase counter. If TBIF (bit15) is set to "1" when this bit is "1", a time-base timer interrupt request is
generated.
Value
Description
0
Disables the output of time-base timer interrupt request. [Initial value]
1
Enables the output of time-base timer interrupt request.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
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[bit13 to bit11] TBC2, TBC1, TBC0: Time-base timer counter selection bits
These bits set the interval time for the time-base counter used in the time-base timer.
Based on the value written to these bits, the interval time is selected from the 8 options shown in the
following table.
TBC2 TBC1 TBC0
Timer interval
time
When source oscillation
= 4 MHz, and PLL =
multiply-by-10
When sub clock =
32 kHz
0
0
0
φ × 211
51.2 μs
61.4 ms
0
0
1
φ × 212
102.4 μs
123 ms
0
1
0
φ × 213
204.8 μs
246 ms
0
1
1
φ × 222
104.9 ms
126 s
1
0
0
φ × 223
209.7 ms
256 s
1
0
1
φ × 224
419.4 ms
512 s
1
1
0
φ × 225
838.9 ms
1024 s
1
1
1
φ × 226
1677.7 ms
2048 s
φ represents the cycle of the system base clock.
• The initial value is undefined. Always set a value before enabling an interrupt.
• These bits are readable and writable.
[bit10] Reserved: reserved bit
This bit is reserved. The read value is undefined. Writing has no effect on operation.
[bit9, bit8] Reserved: reserved bits
These bits are reserved. The read value is 11Β.
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MB91210 Series
■ CTBR: Time-base Counter Clear Register
The configuration of the time-base counter clear register is shown below.
CTBR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000483H
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
W
W
W
W
W
W
W
W:
X:
Write only
Undefined
CTBR is used to initialize the time-base counter.
When A5H and 5AH are written to this register consecutively, all the bits of the time-base counter are
cleared to "0" immediately after 5AH is written. There is no time limit between writing A5H and 5AH.
However, if data other than 5AH is written after A5H is written, clear operation will not be performed even
when 5AH is written, unless A5H is written again.
The read value of this register is undefined.
Note:
When this register is used to clear the time-base counter, there will be temporary fluctuations in the
oscillation stabilization wait interval, watchdog timer cycle, and time-base timer cycle.
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MB91210 Series
■ CLKR: Clock Source Control Register
The configuration of the clock source control register is shown below.
CLKR
Address
bit15
000484H
bit14
Reserved PLL1S2
R/W
R/W
bit13
bit12
bit11
bit10
PLL1S1 PLL1S0 PLL2EN PLL1EN
R/W
R/W
R/W
bit9
bit8
Initial value
CLKS1
CLKS0
00000000B
R/W
R/W
R/W
R/W: Readable/writable
CLKR selects the clock source to be used as the system base clock and controls the PLL.
This register is used to select one out of the three available clock sources. It is also used to enable the
operation of the dual clock PLL (operation of both main clock and sub clock) and select the multiplication
rate.
[bit15] Reserved: reserved bit
This bit is reserved. Always set it to "0".
[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0: PLL multiplication rate selection bits
These bits are used to select the multiplication rate for the main PLL.
The multiplication rate for the main PLL is selected from 8 options.
Do not rewrite these bits while the main PLL is selected as the clock source.
The maximum operable frequency is 40 MHz. Therefore, do not set any higher frequency.
Main PLL
multiplication rate
PLL1S2
PLL1S1
PLL1S0
0
0
0
× 1 (equal)
Setting is disabled.
0
0
1
× 2 (multiply-by-2)
When source oscillation = 4 MHz: φ= 125ns (8 MHz)
0
1
0
× 4 (multiply-by-4)
When source oscillation = 4 MHz: φ= 62.5ns (16 MHz)
0
1
1
× 6 (multiply-by-6)
When source oscillation = 4 MHz: φ= 41.7ns (24 MHz)
1
0
0
× 8 (multiply-by-8)
When source oscillation = 4 MHz: φ= 31.3ns (32 MHz)
1
0
1
× 10 (multiply-by-10)
When source oscillation = 4 MHz: φ= 25.0ns (40 MHz)
1
1
0
× 12 (multiply-by-12)
Setting disabled
1
1
1
× 16 (multiply-by-16)
Setting disabled
Main Oscillation (4 MHz)
φ represents the cycle of the system base clock.
• These bits are initialized to 000B by a reset.
• They are readable and writable.
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[bit11] PLL2EN: Sub clock selection enable bit
PLL2EN is a selection enable bit for the sub clock.
Do not rewrite this bit while the sub clock is selected as the clock source. Also, do not select the sub
clock as the clock source while this bit is set to "0" (due to the settings of bit9 and bit8: CLKS1 and
CLKS0).
If OSCD2 (bit1) in STCR is "1", the sub clock will be stopped during stop mode, even when PLL2EN is
"1". The operation will be enabled again after return from stop mode.
Value
Description
0
Disables sub clock selection. [Initial value]
1
Enables sub clock selection.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
Note:
In a product without sub clock oscillation, PLL2EN is fixed to "0" and writing is invalid.
[bit10] PLL1EN: Main PLL enable bit
PLL1EN is an operation enable bit for the main PLL.
Do not rewrite this bit while the main PLL is selected as the clock source. Also, do not select the main
PLL as the clock source while this bit is set to "0" (due to the settings of bit9 and bit8: CLKS1 and
CLKS0).
If OSCD1 (bit0) in STCR is "1", the main PLL will be stopped during stop mode, even when PLL1EN
is "1". The operation will be enabled again after return from stop mode.
Value
Description
0
Stops main PLL. [Initial value]
1
Enables main PLL operation.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
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[bit9, bit8] CLKS1, CLKS0: Clock source selection bits
These bits set the clock source to be used.
Based on the value written to the bits, the clock source is selected from the 3 options shown in the
following table.
Note that the value of CLKS0 (bit8) cannot be modified while CLKS1 (bit9) is "1".
Unchangeable combination
Changeable combination
00B→11B
00B→01B or 10B
01B→10B
01B→11B or 00B
10B→01B or 11B
10B→00B
11B→00B or 10B
11B→01B
For the above reason, write 01B first, then write 11B to switch from the initial state to the sub clock
selection.
CLKS1
CLKS0
Clock source setting
0
0
Source oscillation input from X0/X1 divided by 2 [Initial value]
0
1
Source oscillation input from X0/X1 divided by 2
1
0
Main PLL
1
1
Sub clock
• These bits are initialized to 00B by a reset.
• They are readable and writable.
To operate in sub clock operation mode, set PLL1EN to "0" to stop the PLL operation.
• For MB91F218S, CLKS0 bit is fixed to "0". Writing is invalid and reading returns "0".
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MB91210 Series
■ WPR: Watchdog Reset Generation Postpone Register
The configuration of the watchdog reset generation postpone register is shown below.
WPR
Address
bit7
D7
W
000485H
W:
X:
bit6
D6
W
bit
D5
W
bit4
D4
W
bit3
D3
W
bit2
bit1
D2
W
D1
W
bit0
Initial value
D0
W
XXXXXXXXB
Write only
Undefined
WPR is a register used to postpone the generation of a watchdog reset.
When A5H and 5AH are written to this register consecutively, F/F for detecting the watchdog timer is
cleared immediately after 5AH is written, to postpone the generation of a watchdog reset.
There is no time limit between writing A5H and 5AH. However, if data other than 5AH is written after A5H
is written, clear operation will not be performed even when 5AH is written, unless A5H is written again.
Table 3.10-1 shows the relationship between the time interval pertaining to the generation of watchdog
resets and the RSRR register value.
Unless the writing of both pieces of the data is completed within this interval, a watchdog reset is
generated. The time spent until the generation of a watchdog reset and the writing interval required to
inhibit the generation vary depending on the state of WT1 (bit9) and WT0 (bit8) in the RSRR register.
Table 3.10-1 Time Interval of Watchdog Reset Generation
Minimum interval for writing to WPR,
required to prevent a watchdog reset to
be generated by RSRR
Time from when the last 5AH is written
to WPR to when a watchdog reset is
generated
WT1
WT0
0
0
φ × 216 (initial value)
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
φ represents the cycle of system base clock. WT1 and WT0 are bit9 and bit8 of RSRR, used to set the cycle
of the watchdog timer.
When the CPU is not in operation, such as during stop mode or sleep mode, clear operation is performed
automatically. Therefore, once such condition occurs, a watchdog reset is postponed automatically.
The read value of this register is undefined.
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MB91210 Series
■ DIVR0: Basic Clock Division Setting Register 0
The configuration of the basic clock division setting register 0 is shown below.
DIVR0
Address
000486H
bit15
B3
R/W
bit14
B2
R/W
bit13
B1
R/W
bit12
B0
R/W
bit11
P3
R/W
bit10
P2
R/W
bit9
P1
R/W
bit8
Initial value
P0
R/W
00000011B
R/W: Readable/writable
DIVR0 is a register used to control the division ratio of the base clock for each internal clock.
This register sets the division ratio between the CPU and the clock of the internal bus (CLKB), a peripheral
circuit and peripheral bus clock (CLKP).
Note:
The maximum operable frequency is defined for each clock. Operation is not guaranteed if a
frequency, in combination with the source clock selection, PLL multiplication rate setting and division
ratio setting, is set to exceed the maximum frequency. In particular, take care to follow the correct
order in conjunction with modifying the source clock selection setting.
When a setting of this register is changed, the new division ratio becomes valid from the next clock rate.
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[bit15 to bit12] B3, B2, B1, B0: CLKB division selection bits
These bits are used to set the clock division ratio for the CPU clock (CLKB). They set the clock
division ratio for the CPU, internal memory and internal bus clock (CLKB).
Based on the value written to these bits, the division ratio (clock frequency) of the base clock for the
CPU and internal bus clocks is selected from the 16 options shown in the following table.
The maximum operable frequency is 40 MHz. Therefore, do not set any division ratio that will cause
this frequency to be exceeded.
Clock division ratio
Clock frequency: When source oscillation
is 4 MHz, and PLL is multiplied by 10
B3
B2
B1
B0
0
0
0
0
φ
40.0 MHz [Initial value]
0
0
0
1
φ × 2 (Divided-by-2)
20.0 MHz
0
0
1
0
φ × 3 (Divided-by-3)
13.3 MHz
0
0
1
1
φ × 4 (Divided-by-4)
10.0 MHz
0
1
0
0
φ × 5 (Divided-by-5)
8.00 MHz
0
1
0
1
φ × 6 (Divided-by-6)
6.67 MHz
0
1
1
0
φ × 7 (Divided-by-7)
5.71 MHz
0
1
1
1
φ × 8 (Divided-by-8)
5.00 MHz
…
…
…
…
1
1
1
1
…
φ × 16 (Divided-by-16)
…
2.50 MHz
φ represents the cycle of the system base clock.
• These bits are initialized to 0000B by a reset.
• They are readable and writable.
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[bit11 to bit8] P3, P2, P1, P0: CLKP division selection bits
These bits are used to set the division ratio for the peripheral clock (CLKP).
They set the division ratio for the clock used for peripheral circuits and peripheral bus (CLKP).
Based on the value written to these bits, the division ratio (clock frequency) of the base clock for the
peripheral circuit and peripheral bus clocks is selected from the 16 options shown in the following table.
The maximum operable frequency is 40 MHz. Therefore, do not set any division ratio that will cause
this frequency to be exceeded.
Clock division ratio
Clock frequency: When source oscillation
is 4 MHz, and PLL is multiplied by 10
P3
P2
P1
P0
0
0
0
0
φ
40.0 MHz
0
0
0
1
φ × 2 (Divided-by-2)
20.0 MHz
0
0
1
0
φ × 3 (Divided-by-3)
13.3 MHz
0
0
1
1
φ × 4 (Divided-by-4)
10.0 MHz [Initial value]
0
1
0
0
φ × 5 (Divided-by-5)
8.00 MHz
0
1
0
1
φ × 6 (Divided-by-6)
6.67 MHz
0
1
1
0
φ × 7 (Divided-by-7)
5.71 MHz
0
1
1
1
φ × 8 (Divided-by-8)
5.00 MHz
…
…
…
…
1
1
1
1
…
φ × 16 (Divided-by-16)
…
2.50 MHz
φ represents the cycle of the system base clock.
• These bits are initialized to 0011B by a reset.
• They are readable and writable.
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MB91210 Series
■ DIVR1: Basic Clock Division Setting Register 1
The configuration of the basic clock division setting register 1 is shown below.
DIVR1
Address
bit7
bit6
bit5
bit4
000487H
T3
R/W
T2
R/W
T1
R/W
T0
R/W
bit3
bit2
bit1
bit0
Reserved Reserved Reserved Reserved
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W: Readable/writable
DIVR1 is a register used to control the division ratio of the base clock for each internal clock.
This register sets the division ratio of the clock for an external expansion bus interface (CLKT).
Note:
The maximum operable frequency is defined for each clock. Operation is not guaranteed if a
frequency, in combination with the source clock selection, PLL multiplication rate setting and division
ratio setting, is set to exceed the maximum frequency. In particular, take care to follow the correct
order in conjunction with modifying the source clock selection setting.
When a setting of this register is changed, the new division ratio becomes valid from the next clock rate.
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[bit7 to bit4] T3, T2, T1, T0: CLKT division selection bits
These bits are used to set the clock division ratio for the external bus clock (CLKT).
They set the clock division ratio for the clock of the external bus interface (CLKT).
Based on the value written to these bits, the division ratio (clock frequency) of the base clock for the
external expansion bus interface is selected from the 16 options shown in the following table.
The maximum operable frequency is 10 MHz. Therefore, do not set any division ratio that will cause
this frequency to be exceeded.
Clock division ratio
Clock frequency: When source oscillation
is 4 MHz, and PLL is multiplied by 10
T3
T2
T1
T0
0
0
0
0
φ
40.0 MHz [Initial value]
0
0
0
1
φ × 2 (Divided-by-2)
20.0 MHz
0
0
1
0
φ × 3 (Divided-by-3)
13.3 MHz
0
0
1
1
φ × 4 (Divided-by-4)
10.0 MHz
0
1
0
0
φ × 5 (Divided-by-5)
8.00 MHz
0
1
0
1
φ × 6 (Divided-by-6)
6.67 MHz
0
1
1
0
φ × 7 (Divided-by-7)
5.71 MHz
0
1
1
1
φ × 8 (Divided-by-8)
5.00 MHz
…
…
…
…
1
1
1
1
…
φ × 16 (Divided-by-16)
…
2.50 MHz
φ represents the cycle of the system base clock.
• These bits are initialized to 0000B by a reset.
• They are readable and writable.
[bit3 to bit0] Reserved: reserved bits
• These bits are initialized to 0000B by a reset.
• Always write 0000B to the bits.
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MB91210 Series
■ OSCCR: Oscillation Control Register
The configuration of the oscillation control register is shown below.
OSCCR
Address
00048AH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved OSCDS1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXX0B
R/W
R/W: Readable/writable
X:
Undefined
OSCCR is a register used to control the main oscillation during sub clock operation.
[bit15 to bit9] Reserved: reserved bits
These bits are reserved.
[bit8] OSCDS1: Main oscillation stop control bit (in sub clock operation mode)
OSCDS1 is used to stop the main oscillation while the sub clock is selected.
Writing "1" to this bit stops the main oscillation when the sub clock is selected as the clock source.
"1" cannot be written to this bit when the main clock is selected.
Do not select the main clock while this bit is "1". Set it to "0" and wait until the main oscillation
stabilizes before switching to the main clock. In this case, maintain the oscillation stabilization wait
time using the main oscillation stabilization wait timer. Moreover, the main oscillation stabilization wait
time is required when the clock source is switched to the main clock by INIT. At this point, the
operation after return is not guaranteed unless the settings of OS1 and OS0 (bit3 and bit2) in the standby
control register (STCR) satisfy the main oscillation stabilization wait time.
In the above case, set OS1 and OS0 in STCR to a value that will satisfy both the sub clock oscillation
stabilization wait time and the main oscillation stabilization wait time.
For information about the oscillation stabilization waiting, see "3.9.2 Oscillation Stabilization Wait
and PLL Lock Wait Time".
Value
Description
0
Does not stop main oscillation during execution of sub clock. [Initial value]
1
Stop main oscillation during execution of sub clock.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
• For MB91F218S, setting value does not effect the operations.
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MB91210 Series
■ PLLC: PLL Control Register
The configuration of the PLL control register is shown below.
PLLC
Address
000494H
bit15
bit13
Reserved Reserved
R
R/W:
R:
X:
-:
bit14
R/W
bit12
bit11
bit10
bit9
bit8
Initial value
X1000101B
-
-
-
Reserved
DIVS1
DIVS0
R
R
R
R/W
R/W
R/W
Readable/writable
Read only
Undefined
Undefined bit
This register sets the PLL output frequency. Use this in combination with the PLL1S2 to PLL1S0 bits of
the CLKR register.
[bit15] Reserved bit
The reading value is undefined.
No effect on writing.
[bit14] Reserved bit
Set this bit to "1".
[bit13 to bit11] Unused bits
000B is read.
No effect on writing.
[bit10] Reserved bit
Set this bit to "1".
[bit9, bit8] PLL divided selection bits
The circuit of dividing frequency of PLL clock is selected. Set this in accordance with the PLL output
frequency being used. These bits can only be changed when the PLL1EN bit of the CLKR register is set
to "0" (PLL stopped). When the PLL1EN bit is set to "1", the write is ignored and the value is not
updated.
98
DIVS1
DIVS0
System clock frequency
0
0
Setting disabled
0
1
2 divided [initial value]
32 MHz to 40 MHz
1
0
4 divided
16 MHz to 32 MHz
1
1
8 divided
8 MHz to 16 MHz
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CHAPTER 3 CPU AND CONTROL BLOCK
3.10 Clock Division
MB91210 Series
CM71-10139-5E
DIVS[1:0]
PLL
Oscillator
Output
[MHz]
Output to
the Clock
Unit
[MHz]
8
11B
64
8
010B
4
10B
64
16
4
010B
8
11B
128
16
4
6
011B
4
10B
96
24
4
8
100B
2
01B
64
32
4
8
100B
4
10B
128
32
4
10
101B
2
01B
80
40
5
2
001B
8
11B
80
10
5
4
010B
4
10B
80
20
5
6
011B
4
10B
120
30
5
8
100B
2
01B
80
40
10
1
000B
8
11B
80
10
10
2
001B
4
10B
80
20
10
4
010B
2
01B
80
40
16
1
000B
4
10B
64
16
16
1
000B
8
11B
128
16
16
2
001B
2
01B
64
32
16
2
001B
4
10B
128
32
Input
Frequenc
y [MHz]
CLKR
Setting
Multiplier
PLL1S[2:0]
PLLC
Setting
Divider
4
2
001B
4
4
4
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CHAPTER 3 CPU AND CONTROL BLOCK
3.10 Clock Division
3.10.3
MB91210 Series
Peripheral Circuits in Clock Control Block
This section explains the peripheral circuit functions contained in the clock control
block.
■ Time-base Counter
The clock control block includes a 26-bit time-base counter which runs on the system base clock.
In addition to measuring the oscillation stabilization wait time, the time-base counter is used for the
following applications.
• Watchdog timer:
The bit output of the time-base counter is used to measure the watchdog timer for detecting system
hang-up.
• Time-base timer:
The output of the time-base counter is used to generate interval interrupts.
● Watchdog timer
The watchdog timer detects program hang-up, using the output of the time-base counter. When the
generation of a watchdog reset is no longer postponed during the set interval by an event such as program
hang-up, a setting initialization reset request is generated as a watchdog reset.
[Activating the watchdog timer and setting the cycle]
The watchdog timer is activated when RSRR (reset source register/watchdog timer control register) is
written to for the first time after a reset. At this point, WT1 and WT0 (bit9 and bit8) are used to set the
interval time for the watchdog timer. For setting the interval time, only the time set in the initial write
operation becomes valid. Any succeeding write attempts are ignored.
[Postponing the generation of watchdog reset]
Once the watchdog timer is activated, data must be written periodically to WPR (watchdog reset
generation postpone register) in the order of A5H and 5AH, using the program.
This procedure initializes the flag for generating a watchdog reset.
[Generating watchdog reset]
The flag for generating a watchdog reset is set at the falling edge of the output of the time-base counter
in the set interval. If the flag has been set when the second falling edge is detected, a setting
initialization reset request is generated as a watchdog reset.
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MB91210 Series
[Stopping the watchdog timer]
Once the watchdog timer is activated, it cannot be stopped until an operation initialization reset is
generated.
The watchdog timer can be stopped under the following condition in which an operation initialization
reset is generated, and it does not function until reactivated by program operation.
• Operation initialization reset (RST) state
• Setting initialization reset (INIT) state
• Oscillation stabilization wait reset (RST) state
[Suspending the watchdog timer (automatically delayed generation)]
While the CPU's program operation is stopped, the watchdog timer once initializes the flag for
generating a watchdog reset to postpone the generation of such reset. "Suspended program operation"
refers to specific operations listed below.
• Sleep state
• Stop state
• Oscillation stabilization wait RUN state
• Break when emulator debugger and monitor debugger is used
• Period from execution of INTE instruction to execution of RETI instruction
• Step trace trap
(Break for each instruction when T flag in PS register is set to "1")
When the time-base counter is cleared, the flag for generating a watchdog reset is also initialized at the
same time, and the generation of a watchdog reset is postponed.
Note that a watchdog reset may not be generated if system hang-up results in the above state. In that
case, perform a reset from the external INITX pin.
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3.10 Clock Division
MB91210 Series
● Time-base timer
The time-base timer is a timer that generates interval interrupts using the output of the time-base counter.
The timer is suitable for measuring relatively long times, up to {base clock × 227} cycles such as for the
PLL lock wait time and sub clock oscillation stabilization wait time.
A time-base timer interrupt request is generated when the falling edge of the output of the time-base
counter corresponding to the set interval is detected.
[Activating the time-base timer and setting the interval]
The time-base timer sets the interval time using TBC2 to TBC0 (bit13 to bit11) in the time-base counter
control register (TBCR).
The falling edge of the output of the time-base counter corresponding to the set interval is always
detected. Therefore, after setting the interval time, clear TBIF (bit15) first, then set TBIE (bit14) to "1"
to enable the output of an interrupt request.
When changing the interval time, disable the output of an interrupt request by setting TBIE (bit14) to
"0" beforehand.
The time-base counter always continues to count without being affected by the above settings. To
achieve the accurate interval interrupt time, clear the time-base counter before enabling interrupts.
Otherwise, an interrupt request may be generated immediately after interrupts are enabled.
[Clearing the time-base counter by program]
When A5H and 5AH are written to the time-base counter clear register (CTBR) in that order, all the bits
of the time-base counter are cleared to "0" immediately after 5AH is written. There is no time limit
between writing A5H and 5AH. However, if data other than 5AH is written after A5H is written, clear
operation will not be performed even when 5AH is written, unless A5H is written again.
When this time-base counter is cleared, the flag for generating a watchdog reset is also initialized
simultaneously, and the generation of a watchdog reset is postponed temporarily.
[Clearing the time-base counter by the device state]
When the device enters the following state, all the bits of the time-base counter are cleared to "0".
• Stop state
• Setting initialization reset (INIT) state
Particularly in stop state, a time-base timer interval interrupt may occur unintentionally, as the timebase counter is used to measure the oscillation stabilization wait time.
Therefore, disable time-base timer interrupts and do not use the time-base timer before transition to stop
mode.
In any other state, an operation initialization reset is generated automatically. Consequently, time-base
timer interrupts are disabled automatically.
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3.10 Clock Division
MB91210 Series
● Main oscillation stabilization wait timer (when sub clock is selected)
This is a 26-bit timer that is synchronized with the main clock to count up, without being affected by the
clock source selection or division setting.
The timer is used to measure the main oscillation stabilization wait time during sub clock operation.
The main oscillation can be controlled in sub clock operation by OSCDS1 (bit8) in OSCCR (oscillation
control register). This timer is used to measure the oscillation stabilization wait time, when the main
oscillation is stopped and then restarted.
Use the following procedure to switch to the main clock operation from the sub clock operation with the
main clock being stopped.
1) Clear the main oscillation stabilization wait timer.
2) Set OSCDS1 (bit8) in the oscillation control register (OSCCR) to "0" to start the main oscillation.
3) Use the main oscillation stabilization wait timer to wait until the main clock becomes stable.
4) Once the main clock stabilizes, use CLKS1 and CLKS0 (bit9 and bit8) in the clock source register
(CLKR) to switch from the sub clock to the main clock.
Note:
If the clock is switched to the main clock without waiting until it becomes stable, an unstable clock
signal will be supplied; therefore, the resulting operation will not be guaranteed. Always wait until the
clock stabilizes before switching to the main clock. For details about the main oscillation stabilization
wait timer, see "3.12 Main Oscillation Stabilization Wait Timer".
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CHAPTER 3 CPU AND CONTROL BLOCK
3.11 Device State Control
3.11
MB91210 Series
Device State Control
This section explains various states of the MB91210 series and how they are controlled.
■ Overview of Device State Control
The MB91210 series is provided with the following device states.
• RUN state (normal operation)
• Sleep state
• Stop state
• Oscillation stabilization wait RUN state
• Oscillation stabilization wait reset (RST) state
• Operation initialization reset (RST) state
• Setting initialization reset (INIT) state
The following section details sleep mode and stop mode, which are used as low-power consumption modes.
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3.11 Device State Control
MB91210 Series
3.11.1
Device States and Various Transitions
Figure 3.11-1 shows the device state transitions of the MB91210 series.
■ Device States
Figure 3.11-1 Device States
1
2
3
4
5
6
7
8
9
10
INITX pin = 0 (INIT)
INITX pin = 1 (INIT released)
Oscillation stabilization wait completed
Reset (RST) released
Software reset (RST)
Sleep (instruction written)
Stop (instruction written)
Interrupt
External interrupt requiring no clock
Main clock → sub clock switched
(instruction written)
11 Sub clock → main clock switched
(instruction written)
12 Watchdog reset (INIT)
13 Sub clock sleep (instruction written)
Priority order of transition requests
Setting initialization reset (INIT)
Highest Oscillation stabilization wait
↓
completed
↓
Operation initialization reset (RST)
↓
Interrupt request
↓
Lowest Stop
Sleep
Power-on
1
Setting initialization (INIT)
2
Main clock mode
1
Main stop
9
Main oscillation
stabilization
wait reset
3
1
Program reset
(RST)
1
1
Oscillation stabilization wait RUN 3
4
7
1
Main sleep
12
Main clock
operation
6
8
1, 5
10
Sub clock mode
1
Sub clock sleep
Oscillation stabilization wait RUN
12
Sub clock
operation
13
3
1
1
11
8
7
5
1
4
Program reset
(RST)
1
9
Sub clock stop
Sub clock stop
(Note)
To switch the clock source between the main clock and sub clock, switch CLKS1
and CLKS0 (bit1 and bit0) in the clock source register (CLKR) while a stable
supply of the switched clock is maintained in operation mode.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.11 Device State Control
MB91210 Series
■ Operational States of Device
The MB91210 series is provided with the following device operational states.
● RUN state (normal operation)
In this state, the program is being executed.
All internal clocks are supplied to keep all circuits operable. Only the clock for the 16-bit peripheral bus,
however, is stopped unless the bus is accessed.
Various state transition requests are accepted.
● Sleep state
In this state, the program is stopped. The device is placed in this state by program operation.
Only the execution of the program by the CPU is stopped, while the peripheral circuits are maintained
operable. The built-in memory and internal/external buses remain stopped unless requested by the DMA
controller. When a valid interrupt request is generated, this state is released and the device enters the RUN
state (normal operation).
When a setting initialization reset request is generated, the device enters the setting initialization reset
(INIT) state.
● Stop state
In this state, the device is stopped. The device is placed in this state by program operation.
In the stop state, all the internal circuits are stopped. The internal clocks are all stopped and the oscillation
circuit and PLL can be stopped by setting. Also, the external pins can be set to the same high impedance by
setting (except some pins).
The device enters the oscillation stabilization wait RUN state when a specific (non-clock-based) valid
interrupt occurs or when a main oscillation stabilization wait timer interrupt request is generated during
oscillation operation.
When a setting initialization reset request is generated, the device enters the setting initialization reset
(INIT) state.
● Oscillation stabilization wait RUN state
In this state, the device is stopped. The device enters this state when returning from the stop state.
All the internal circuits except the clock generation control block (time-base counter and device state
control component) are stopped. While all the internal clocks are stopped, the oscillation circuit and the
PLL which has been enabled to operate are in operation.
This state releases the high impedance control of the external pins used in the stop state.
The device enters the RUN state (normal operation) when the set oscillation stabilization wait time has
elapsed.
When a setting initialization reset request is generated, the device enters the setting initialization reset
(INIT) state.
● Oscillation stabilization wait reset (RST) state
In this state, the device is stopped. The device enters this state after returning from the stop state or setting
initialization reset (INIT) state.
All the internal circuits except the clock generation control block (time-base counter and device state
control component) are stopped. While all the internal clocks are stopped, the oscillation circuit and the
PLL which has been enabled to operate are in operation.
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This state releases the high impedance control of the external pins used in the stop state.
It outputs an operation initialization reset (RST) to the internal circuits.
The device enters the oscillation stabilization wait reset (RST) state when the set oscillation stabilization
wait time has elapsed.
When a setting initialization reset (INIT) request is generated, the device enters the setting initialization
reset (INIT) state.
● Operation initialization reset (RST) state
In this state, the program is initialized. The device enters this state once the oscillation stabilization wait
reset (RST) state ends.
The execution of the program by the CPU is stopped and the program counter is initialized. Most peripheral
circuits are initialized. All the internal clocks, the oscillation circuit and the PLL which has been enabled to
operate are in operation.
An operation initialization reset (RST) is output to the internal circuits.
When the operation initialization reset (RST) request is lost, the device enters the RUN state (normal
operation) to execute the operation initialization reset sequence. If the device has just returned from the
setting initialization reset (INIT) state, it will execute the setting initialization reset sequence.
When a setting initialization reset (INIT) request is generated, the device enters the setting initialization
reset (INIT) state.
● Setting initialization reset (INIT) state
In this state, all settings are initialized. The device enters this state when a setting initialization reset (INIT)
request is accepted.
The execution of the program by the CPU is stopped and the program counter is initialized. All the
peripheral circuits are initialized. Although the oscillation circuit is in operation, the PLL stops operation.
All the internal clocks are stopped while the "L" level is being input to the external INITX pin. In other
times, they operate.
A setting initialization reset (INIT) and operation initialization reset (RST) are output to the internal
circuits.
When the setting initialization reset (INIT) request is lost, this state is released and the device enters the
oscillation stabilization wait reset (RST) state. After that, the device goes through the operation
initialization reset (RST) state and executes the setting initialization reset sequence.
● Priority order of state transition requests
In any state, the device follows the priority order of the state transition requests, shown below. Note that
some requests can be generated only in a particular state; therefore, they are only valid in that state.
[Highest] Setting initialization reset (INIT) request
↓
Oscillation stabilization wait time completed
(This occurs only in oscillation stabilization wait reset state and oscillation stabilization wait
RUN state)
↓
Valid interrupt request (Generated only in RUN, sleep and stop state)
↓
Stop mode request (register written) (Generated only in RUN state)
[Lowest]
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Sleep mode request (register written) (Generated only in RUN state)
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CHAPTER 3 CPU AND CONTROL BLOCK
3.11 Device State Control
MB91210 Series
3.11.2 Low-power Consumption Mode
Of all the operational states available in the MB91210 series, this section explains the
low-power consumption modes as well as how to use them.
The MB91210 series is provided with the following low-power consumption modes.
• Sleep mode
The device is set to sleep mode by writing to a register.
• Stop mode
The device is set to stop mode by writing to a register.
Each mode is explained below.
■ Sleep Mode
When "1" is written to the SLEEP bit (bit6) in the standby control register (STCR), sleep mode is selected
and the device enters sleep mode.
After that, the device remains in sleep state until an event allowing the device to recover from sleep state
occurs.
When "1" is written to both the STOP bit (bit7) in the standby control register (STCR) and this bit, the
STOP bit (bit7) has higher priority; therefore, the device enters the stop state.
For information about the sleep state, also see "● Sleep state" in "■ Operational States of Device" in
"3.11.1 Device States and Various Transitions".
[Transition to sleep mode]
To set the device to sleep mode, always follow the sequence shown below.
(LDI#value_of_sleep,R0)
; "value_of_sleep" is the data written to STCR.
(LDI#_STCR,R12)
; "_STCR" is the address of STCR (481H).
STB R0,@R12
; Writing to the standby control register (STCR)
[email protected],R0
; Reading from STCR for synchronous standby
[email protected],R0
; Another dummy read from STCR
NOP
; NOP (for timing adjustment) × 5
NOP
NOP
NOP
NOP
[Circuits that stop in sleep state]
• Execution of program by CPU
• Bit search module (It however operates during DMA transfer.)
• Various types of built-in memory (It however operates during DMA transfer.)
• Internal/external buses (They however operate during DMA transfer.)
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MB91210 Series
[Circuits that do not stop in sleep state]
• Oscillation circuit
• PLL enabled to operate
• Clock generation control block
• Interrupt controller
• Peripheral circuits
• DMA controller
• DSU
• Main oscillation stabilization wait timer
[Events that recover the device from sleep state]
• Generation of a valid interrupt request
When an interrupt request holding an interrupt level other than for disabling interrupt (1FH) is
generated, the device is released from sleep mode and enters the RUN state (normal state).
To maintain the device in sleep mode even when an interrupt request is generated, set the relevant
ICR to disable interrupts (1FH) for the interrupt level.
• Generation of a setting initialization reset (INIT) request
When a setting initialization reset (INIT) request is generated, the device enters the setting
initialization reset (INIT) state unconditionally.
For information about the priority order of the recovery events, see "3.11.1 Device States and Various
Transitions"
[Synchronous standby operation]
The device does not enter the sleep state only by writing to the SLEEP bit.
After the write operation, the STCR register must also be read from in order to set the device to the
sleep state.
When using sleep mode, always use the sequence described in [Transition to sleep mode].
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CHAPTER 3 CPU AND CONTROL BLOCK
3.11 Device State Control
MB91210 Series
■ Stop Mode
When "1" is written to the STOP bit (bit7) in the standby control register (STCR), stop mode is selected
and the device enters the stop state. After that, the device remains in the stop state, until an event allowing
the device to recover from the stop state occurs.
When "1" is written to both the SLEEP bit (bit6) in the standby control register (STCR) and this bit, the
STOP bit (bit7) has higher priority; therefore, the device enters the stop state.
For information about the stop state, also see the "● Stop state" section of "3.11.1 Device States and
Various Transitions".
[Transition to stop mode]
To set the device to stop mode, always follow the sequence shown below.
/* STCR write */
ldi #_STCR, R0
; STCR register (0x0481)
ldi #Val_of_Stby, rl
; Val_of_Stby is write data to STCR.
stb rl,@r0
; Write to STCR
/* STBR write */
ldi #_CTBR, r2
; CTBR register (0x0483)
ldi #0xA5, rl
; Clear command (1)
stb rl,@r2
; Write A5 to CTBR
ldi #0xA5, rl
; Clear command (2)
stb rl,@r2
;Write A5 to CTBR
/* Here, clear time-base counter */
ldub @r0, rl
; Read STCR
/* Start a synchronous stand-by transition */
ldub @r0, rl
; Read dummy STCR
nop
; NOP to adjust timing × 5
nop
nop
nop
nop
[Circuits that halt in stop state]
• Oscillation circuit that has been set to stop
The oscillation circuit for the sub clock that is in the stop state is set to halt, when OSCD2 (bit1) in
the standby control register (STCR) is set to "1".
When OSCD1 (bit0) in the standby control register (STCR) is set to "1", the oscillation circuit for
the main clock that is in the stop state is set to halt. In this case, the main oscillation stabilization
wait timer also halts.
• PLL that is connected to the oscillation circuit either disabled to operate or set to halt
When OSCD1 (bit0) in the standby control register (STCR) is set to "1", the PLL for the main clock
that is in the stop state is set to halt, even if PLL1EN (bit10) in the clock source control register
(CLKR) is set to "1".
• All the internal circuits except the [Circuits that do not halt in stop state]
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MB91210 Series
[Circuits that do not halt in stop state]
• Oscillation circuits that are not set to halt:
The oscillation circuit for the sub clock that is in the stop state does not halt, when OSCD2 (bit1) in
the standby control register (STCR) is set to "0".
The oscillation circuit for the main clock that is in the stop state does not halt, when OSCD1 (bit0) in
the standby control register (STCR) is set to "0". In this case, the main oscillation stabilization wait
timer also does not halt.
• PLL that is connected to the oscillation circuit which is enabled to operate and not set to halt:
When OSCD1 (bit0) in the standby control register (STCR) is set to "0", the PLL for the main clock
that is in the stop state does not halt, if PLL1EN (bit10) in the clock source control register (CLKR)
is set to "1".
[High-impedance control of pins in stop state]
The pin outputs in the stop state are set to high impedance, if the HIZ bit (bit5) in the standby control
register (STCR) is set to "1".
The pin outputs in the stop state retain the value used before the transition to the stop state, if the HIZ
bit (bit5) in the standby control register (STCR) is set to "0".
[Events that recover the device from stop state]
• Generation of a specific (non-clock-based) valid interrupt request
Only the following are valid: external interrupt input pin (INTn pin), main oscillation stabilization
wait timer interrupt during main oscillation, and RTC interrupt.
When an interrupt request holding an interrupt level other than for disabling interrupt (1FH) is
generated, the device is released from stop mode and enters the RUN state (normal state).
To maintain the device in stop mode even when an interrupt request is generated, set the relevant
ICR to disable interrupts (1FH) for the interrupt level.
• Main oscillation stabilization wait timer interrupt
If a main oscillation stabilization wait timer interrupt request is generated, either when OSCDS1
(bit8) in the oscillation control register (OSCCR) is set to "0" with the sub clock being selected, or
when OSCD1 (bit0) in the standby control register (STCR) is set to "0" with the main clock being
selected, the device is released from stop mode and enters the RUN state (normal state).
To maintain the device in stop mode even when an interrupt request is generated, stop the main
oscillation stabilization wait timer or disable the interrupt enable bit of the main oscillation
stabilization wait timer.
• Generation of a setting initialization reset request
When a setting initialization reset request is generated, the device enters the setting initialization
reset (INIT) state unconditionally.
For information about the priority order of the recovery events, see the "● Priority order of state
transition requests" section of "3.11.1 Device States and Various Transitions".
[Clock source selection in stop mode]
Select the main clock divided by 2 as the source clock before setting stop mode. For details, see "3.9
Clock Generation Control", especially "3.9.1 PLL Control" in that section.
Note that the same restrictions as in normal operation apply when setting the division ratio.
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3.11 Device State Control
MB91210 Series
■ Synchronous Standby Operation
The device does not enter the stop state only by writing to the STOP bit. After the write operation, the
STCR register must also be read from in order to set the device to the stop state.
After the STOP bit is written, the device does not enter the stop state until the reading from the STCR
register is completed. This is because the CPU continues to use the bus until the value read from the STCR
register is stored in the CPU. As a result, after an instruction to write to the STOP bit and another
instruction to read from the STCR, it is only necessary to place 2 NOP instructions, regardless of the
division ratio relationship between the CPU clock (CLKB) and peripheral clock (CLKP). This prevents the
succeeding instructions from being executed before the device enters the stop state.
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3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
3.12
Main Oscillation Stabilization Wait Timer
The main oscillation stabilization wait timer is a 23-bit counter that is synchronized with
the main clock to count up. It includes an interval timer function that continues to
generate interrupts in regular time intervals.
This timer uses the main clock to secure the oscillation stabilization wait time, when the
main oscillation is temporarily suspended during sub clock operation and restarted
using OSCDS1 (bit8) in the oscillation control register (OSCCR).
■ Interval Times of the Main Oscillation Stabilization Wait Timer
Table 3.12-1 shows the interval times of the main oscillation stabilization wait timer. The following 3
interval times are available for selection.
Table 3.12-1 Interval Times of Main Oscillation Stabilization Wait Timer
Main clock cycle
Interval time
213/FCL(2.048 ms)
1/FCL(approx. 250 ns)
214/FCL(4.096 ms)
216/FCL(16.38 ms)
Note: FCL represents the main clock oscillation frequency.
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CHAPTER 3 CPU AND CONTROL BLOCK
3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
■ Block Diagram of the Main Oscillation Stabilization Wait Timer
Figure 3.12-1 shows a block diagram of the main oscillation stabilization wait timer.
Figure 3.12-1 Block Diagram of Main Oscillation Stabilization Wait Timer
Counter for the main
oscillation stabilization
wait timer
FCL
0
1
12
14 15
22
21
22
213 214 215 216
13
223
Interval
timer
selector
Reset
WIF
WIE
WEN
WS1
Counter
clear circuit
WS0 WCL
IRQ
● Main oscillation stabilization wait timer
This timer is a 23-bit up-counter that uses the source oscillation of the main clock for its count clock.
● Counter clear circuit
This circuit clears the counter at a reset, other than the OSCR register setting (WCL=0).
● Interval timer selector
Out of 3 different division outputs of the counter for the main oscillation stabilization wait timer, this
circuit selects one to be used for the interval timer. The falling edge of the selected division output is used
as the interrupt source.
● Main oscillation stabilization wait register (OSCR)
This register selects the interval time, clears the counter, controls interrupts and checks the interrupt state.
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3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
■ Explanation of the Main Oscillation Stabilization Wait Timer Register
The configuration of the main oscillation stabilization wait timer register is shown below.
OSCR
Address
bit15
bit14
bit13
000490H
WIF
WIE
WEN
R/W
R/W
R/W
bit12
bit11
Reserved Reserved
R/W
R/W
bit10
bit9
bit8
Initial value
WS1
WS0
WCL
000XX000B
R/W
R/W
W
R/W: Readable/writable
W: Write only
X:
Undefined
[bit15] WIF: Timer interrupt flag
WIF is the flag for main oscillation stabilization wait interrupt requests.
It is set to "1" at the falling edge of the selected division output for the interval timer.
A main oscillation stabilization interrupt request is output, when this bit and the interrupt request enable
bit are set to "1".
Value
Description
0
No request for main oscillation stabilization interrupt. [Initial value]
1
Request for main oscillation stabilization interrupt
• This bit is initialized to "0" by a reset.
• It is readable and writable. For write operation, however, only "0" can be written. Writing "1" does
not change the bit value.
• Reading by read-modify-write (RMW) instruction always returns "1".
[bit14] WIE: Timer interrupt enable bit
WIE enables/disables the output of an interrupt request to the CPU. A main oscillation stabilization
interrupt request is output, when this bit and the main oscillation stabilization interrupt request flag bit
are set to "1".
Value
Description
0
Disables the output of main oscillation stabilization interrupt request. [Initial value]
1
Enables the output of main oscillation stabilization interrupt request.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
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3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
[bit13] WEN: Timer operation enable bit
WEN enables the timer operation.
When this bit is set to "1", the timer performs count operation.
Value
Description
0
The timer stops. [Initial value]
1
The timer operates.
• This bit is initialized to "0" by a reset.
• It is readable and writable.
[bit12, bit11] Reserved: reserved bits
These bits are reserved. For write operation, write "0" to the bits. ("1" is not allowed to be written.)
The read value is undefined.
[bit10, bit9] WS1, WS0: Timer interval time selection bits
These bits select the cycle for the interval timer.
The cycle is selected from the following 3 output bits of the counter for the main oscillation
stabilization wait timer.
Interval timer cycle (When FCL=4 MHz)
WS1
WS0
0
0
Setting is prohibited [Initial value]
0
1
213/FCL (2.048 ms)
1
0
214/FCL (4.096 ms)
1
1
216/FCL (16.38 ms)
• These bits are initialized to 00B by a reset.
• They are readable and writable.
• To use the main oscillation stabilization wait time timer, write data to this register.
[bit8] WCL: Timer clear bit
When "0" is written to WCL, the oscillation stabilization wait timer is cleared to "0".
For write operation, only "0" can be written. Writing "1" has no effect on operation.
Reading always returns "1".
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3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
■ Main Oscillation Stabilization Wait Interrupt
The counter for the main oscillation stabilization wait timer counts on the main clock, and sets the main
oscillation stabilization wait interrupt request flag (WIF) to "1" when the set interval time has elapsed. In
this case, if the interrupt request enable bit has been enabled (WIE=1), an interrupt request is generated to
the CPU. However, if the oscillation of the main clock is stopped (see "■ Operation of Interval Timer
Function"), the count operation also stops. As a result, no main oscillation stabilization wait interrupt is
generated.
To clear an interrupt request, write "0" to the WIF flag in the interrupt processing routine.
Note that WIF is set at the falling edge of the specified division output, regardless of the WIE value.
Note:
When enabling the output of an interrupt request (WIE=1) after reset release or modifying WS1
(bit0), always clear WIF and WCL at the same time (WIF=WCL=0).
Reference:
• When WIF is set to "1", an interrupt request is generated as soon as WIE is enabled from the
disabled state (0→1).
• WIF is not set, if the counter is cleared (OSCR:WCL=1) at the same time as an overflow
generates at the selected bit.
■ Operation of Interval Timer Function
The counter for the main oscillation stabilization wait timer counts up on the main clock. Under the
following conditions, however, the count operation stops because the oscillation of the main clock stops.
• When WEN is set to "0"
If the device enters stop mode when the main oscillation is set to stop in stop mode (bit0:OSCD1 in the
standby control register (STCR) = 1), the count operation stops during stop mode.
In the MB91210 series, OSCD1 is initialized to "1" at a reset. Therefore, to operate the main oscillation
stabilization wait timer even during stop mode, set OSCD1 to "0" before the device enters standby
mode.
• When OSCDS1 (bit8) in the oscillation control register (OSCCR) is set to "1" in sub clock mode, the
main oscillation stops and the timer also stops the count operation.
When the counter is cleared (WCL=0), it starts count operation from 000000H. Once it reaches 7FFFFFΗ, it
goes back to 000000H and continues to count. When a falling edge is generated at the selected division
output for the interval timer, the main oscillation stabilization wait interrupt request bit (WIF) is set to "1".
This means that a main oscillation stabilization wait timer interrupt request is generated at every selected
interval time, based on the cleared time.
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3.12 Main Oscillation Stabilization Wait Timer
MB91210 Series
■ Operation of Clock Supply Function
In the MB91210 series, the time-base counter is used to secure the oscillation stabilization wait timer after
INIT or stop mode. However, to secure the oscillation stabilization wait time for the main clock when the
sub clock is selected as the clock source, the main oscillation stabilization wait timer is used, as it operates
on the main clock regardless of the clock source selection.
To perform the main clock oscillation stabilization wait from the main oscillation stop state in the sub clock
operation, follow the procedure described below.
1) Set the time required to stabilize the oscillation of the main clock in WS1 and WS0 and clear the
counter to "0" (WS1 and WS0 =oscillation stabilization wait time; write "0" to WCL).
To perform processing after the completion of oscillation stabilization wait by an interrupt, also
initialize the interrupt flag (write "0" to WIF and WIE).
2) Start the oscillation of the main clock (write "0" to bit8:OSCDS1 in OSCCR).
3) Wait until the WIF flag is set to "1" by program.
4) Make sure that the WIF flag has been set to "1" and then perform the processing after the
completion of the oscillation stabilization wait. If interrupts are enabled, an interrupt occurs when
WIF is set to "1". In this case, perform the processing after the completion of the oscillation
stabilization wait in the interrupt routine.
Also, when switching from the sub clock to main clock, make sure that WIF has been set to "1"
beforehand, as described in 4). (If the clock is switched to the main clock without waiting until the
oscillation stabilizes, an unstable clock signal is supplied through the device, and the succeeding
operation is not guaranteed.)
■ Operation of the Main Oscillation Stabilization Wait Timer
Figure 3.12-2 shows the state of the counter during transition to the main clock when the main oscillation
stabilization wait timer is activated.
Figure 3.12-2 State of Counter During Transition to Main Clock when Main Oscillation
Stabilization Wait Timer is Activated
7FFFFFH
Counter value
000000H
Main clock oscillation stabilization wait time
• Clear the timer (WCL=1) * When not "0"
• Set the interval time (WS1,WS0=11B)
• Start the main oscillation
(OSCCR: OSCDS1=0)
WIF (interrupt request)
Cleared in
interrupt routine
WIE (interrupt masking)
Clock mode
Sub clock
Main clock
• Change from sub clock to main clock
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CHAPTER 3 CPU AND CONTROL BLOCK
3.12 Main Oscillation Stabilization Wait Timer
■ Notes on Using the Main Oscillation Stabilization Wait Timer
The oscillation stabilization wait time should be used for reference only, as the oscillation cycle is unstable
immediately after the oscillation starts.
While the oscillation of the main clock is stopped, the counter is also stopped. Consequently, no main
oscillation stabilization interrupt occurs. Therefore, to perform any processing using a main oscillation
stabilization interrupt, do not stop the main oscillation.
If the WIF flag set request and the clearing to "0" from the CPU occur simultaneously, the flag set request
will have higher priority; therefore, the clearing to "0" will be cancelled.
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3.13 Pseudo Sub Clock
3.13
MB91210 Series
Pseudo Sub Clock
The pseudo sub clock is the circuit that divides the main clock oscillation by 128 and
uses it as the sub clock. Only MB91F211B is equipped with the pseudo sub clock.
The pseudo sub clock can be used when the mode pins are set to MD[3:0] = 0011B.
■ Block Diagram of Pseudo Sub Clock
X0
X1
Main
oscillation cell
XIN1
X
OSCD
CLK
enable
X0A
X1A
Sub
oscillation cell
X
1/128
CL
1
XIN2
0
OSCD
Clock
Generation
Unit
MD pin decode
0: with external oscillation
(MD[3:0]=0011B)
1: without external oscillation
(other than MD[3:0]=0011B)
0: OSCD1
1: OSCD1 & OSCD2
OSCD1
OSCD2
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CHAPTER 4
RESET
This chapter describes a reset.
4.1 Overview of a Reset
4.2 Reset Factors and Oscillation Stabilization Wait Time
4.3 Reset Levels
4.4 External Reset Pin
4.5 Reset Operation
4.6 Reset Source Bits
4.7 Pin States at a Reset
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4.1 Overview of a Reset
4.1
MB91210 Series
Overview of a Reset
When a reset occurs, the CPU immediately aborts the processing of the current task
and enters the reset release wait state. When released from the reset, the CPU starts
processing at the address pointed to by the reset vector.
A reset is caused by the following three different factors (trigger events):
• Reset request via external reset pin (INITX)
• Software reset request
• Watchdog timer time-out
■ Reset Factors
Table 4.1-1 lists reset factors.
Table 4.1-1 Reset Factors
Oscillation stabilization wait
Reset
Generation factor
Internal
generation
timing
Reset
level
Main
oscillation
stopped
Stop
state
Else
External reset
"L" input to INITX pin
Synchronous
INIT
Yes
Yes
Yes
Software reset
Writing "0" to the SRST bit in
the standby control register
(STCR)
Synchronous
INIT
Yes
—
No
Watchdog timer
Watchdog timer time-out
Synchronous
INIT
Yes
—
No
When a reset factor occurs, the main oscillation clock is halved in frequency for use as the machine clock.
● External reset
An external reset is generated when the "L" level signal is input to the external reset (INITX) pin.
When turning the power on, set the input level at the INITX pin to "L" to cause a settings initialization reset
(INIT). Immediately after turning the power on, in addition, hold the "L" level input to the INITX pin
during the stabilization wait time required for the oscillation circuit to reserve the regulator stabilization
wait time.
● Software reset
A software reset is an internal reset generated when "0" is written to the SRST bit in the standby control
register (STCR).
● Watchdog reset
A watchdog reset is generated when the watchdog timer overflows without A5H and 5AH written in
succession to the watchdog reset postpone register (WPR) within a prescribed time after the watchdog
timer is activated.
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4.1 Overview of a Reset
MB91210 Series
Note:
If a reset factor occurs during a write operation (during the execution of a transfer instruction) except
when the power is turned on or a voltage drop occurs, the CPU enters the reset release wait state
upon completion of the instruction. Even when a reset is input during a write, therefore, the CPU
completes the write normally. If a reset occurs during the execution of a Load Multiple Registers
(LDM) or Store Multiple Registers (STM) instruction, the CPU accepts the reset before completing
the transfer for the specified registers, and therefore, it does not guarantee all the data is transferred.
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CHAPTER 4 RESET
4.2 Reset Factors and Oscillation Stabilization Wait Time
MB91210 Series
Reset Factors and Oscillation Stabilization Wait Time
4.2
There are three types of reset factors, each of which requires a different oscillation
stabilization wait time at the reset.
■ Reset Factors and Oscillation Stabilization Wait Time
Table 4.2-1 shows each reset factor and the oscillation stabilization wait time for that reset.
Table 4.2-1 Reset Factors and Oscillation Stabilization Wait Time
Oscillation stabilization wait time
Reset
Reset factor
Main
oscillation
stopped
Stop state
Else
External pin
Input "L" to INITX pin
OS bit setting
OS bit setting
OS bit setting
Software reset
Writing "0" to the SRST bit in the Standby control
register (STCR)
OS bit setting
—
No
Watchdog timer
Watchdog timer overflow
OS bit setting
—
No
The oscillation stabilization wait time is reserved by setting the OS bit in the standby control register
(STCR).
Table 4.2-2 shows oscillation stabilization wait time depending on the setting of the standby control
register (STCR).
Table 4.2-2 Oscillation Stabilization Wait Time by Standby Control Register (STCR) Setting
Oscillation stabilization wait time
Values in ( ) assume an oscillation clock
frequency of 4 MHz.
Oscillation stabilization wait time
Values in ( ) assumes an oscillation clock
frequency of 32 kHz.
OS1
OS0
0
0
× 215 (8.2 ms) [Initial value]
× 214 (512 ms) [Initial value]
0
1
× 217 (32.8 ms)
× 216 (2.08 s)
1
0
× 211 (512 μs)
× 210 (32 ms)
1
1
× 22 (1.0 μs)
× 21 (62.5 μs)
Note:
In general, a ceramic or quartz resonator requires an oscillation stabilization wait time of several to
tens of ms to become stable at its natural frequency after starting oscillating. Set a value appropriate
for the resonator to be used.
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4.2 Reset Factors and Oscillation Stabilization Wait Time
MB91210 Series
■ Oscillation Stabilization Wait Time When the Power is Turned On
When turning the power on, set the input level of the INITX pin to "L". When turning the power on, keep
the "L" level input period for the regulator stabilization time (Oscillation time of oscillator) + (10 × base
clock) + 15 μs (Internal voltage regulator circuit stabilization time). In addition, the power-on stabilization
wait time (217 × base clock) is ensured for the internal circuit. After that, the value set in the OS bit is ensured
as the oscillation stabilization wait time.
Figure 4.2-1 Relationship between External Reset and Internal Operation
(Power-on Wait Time < INITX "L" (recommended))
Vcc
CLK
INITX
a
b
CPU operation
Power-on
stabilization wait time
Oscillation
stabilization wait time
a: Oscillation time of oscillator
b: 10 ✕ base clock + 15 μ s
Figure 4.2-2 Relationship between External Reset and Internal Operation
(Power-on Wait Time > INITX "L")
Vcc
CLK
INITX
a
b
CPU operation
Oscillation
Power-on
stabilization
stabilization wait time wait time
a: Oscillation time of oscillator
b: 10 × base clock + 15 μs
■ Return Via the INITX Pin in STOP Mode
When returning by the INITX pin in stop mode, keep the "L" level input period for 15 μs or longer to the
INITX pin. (After release of reset, the device returns after waiting for the period set in the OS bit.)
■ Return Via the External Interrupt in STOP Mode
When returning from stop mode by the external interrupt, keep the level detection period for 15 μs or
longer. (After the interrupt, the device returns from stop mode after waiting for the period set in the OS bit.)
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4.3 Reset Levels
4.3
MB91210 Series
Reset Levels
The reset operations of the FR family are classified into two levels, each of which has
different reset factors and initialization operations. This section describes these reset
levels.
■ Settings Initialization Reset (INIT)
The settings initialization reset (INIT) is the highest-level reset to initialize all settings.
The external pin input, watchdog reset, and software reset have a reset level of settings initialization reset
(INIT). When a settings initialization reset (INIT) occurs, an operation initialization reset (RST) occurs as
well.
The settings initialization reset (INIT) initializes the following items:
• Device operation mode (bus mode and external bus width settings)
• Clock generation/ control settings
- Clock source selection (CLKS: Main clock divided by 2)
- Clock frequency division settings (peripheral: × 4, CPU: × 1, external bus: × 1)
- Watchdog timer cycle (WT1, WT0: 216/base clock cycle) *
- Oscillation stabilization wait time (OS1, OS0:214/HCLK)
- Stop-time oscillation disable mode (OSCD1: Disables main clock oscillation during stop)
- Time-base timer interrupt (TBIE: Disabled)
- Main PLL multiplier (PLL1S: x1)
- PLL operation enable (PLL1E: PLL disabled)
• All the settings initialized by operation initialization reset (RST)
• The pin status control bit at stop time is in the Hi-Z state with HIZ=1.
*: When a settings initialization reset (INIT) occurs, the watchdog timer stops and remains inactive until
reactivated by a program operation.
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4.3 Reset Levels
MB91210 Series
■ Operation Initialization Reset (RST)
A normal-level reset that initializes the operation of a program is called an operation initialization reset
(RST).
If a settings initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs at the same
time.
The operation initialization reset (RST) initializes the following items:
• Program operation
• CPU and internal buses
• Settings for clock generation control
- Watchdog timer cycle (WT1, WT0: 216/base clock cycle)
- Time-base timer interrupt (TBIE: Disabled)
• Register settings of peripheral circuits
• I/O port settings
• Device operation mode (bus mode and external bus width settings)
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4.4 External Reset Pin
4.4
MB91210 Series
External Reset Pin
The external reset pin (INITX pin) is dedicated to reset input; it generates an internal
reset upon "L" level input. Although the internal reset occurs in synchronization with
the machine clock, external pins are reset asynchronously.
■ Block Diagram of External Reset Pin
Figure 4.4-1 Block Diagram of External Reset Pin
Machine clock
(PLL multiplier circuit, Frequency-halved HCLK)
INITX
pin
P-ch
P-ch
Synchronization
circuit
N-ch
Input buffer
Clock-synchronous
Internal reset signal
Note:
To prevent a reset during a write operation from destroying memory, initialize the internal circuit
through INITX pin input in a cycle in which memory is not destroyed. The initialization of the internal
circuit requires a clock. For operation with the external clock, supply the clock input at reset input.
■ External Pin Reset Timing
Each external pin is reset asynchronously with input to the external reset (INITX) pin.
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4.5 Reset Operation
MB91210 Series
4.5
Reset Operation
When a reset is released, the locations from which to read mode data and a reset vector
are selected depending on the mode pin settings and a mode fetch is performed. The
mode fetch determines the CPU operation mode and the address at which to start
execution after the reset operation. At a reset to return from a stop after the power is
turned on, a mode fetch is performed after the oscillation stabilization wait time passes.
■ Outline of Reset Operation
Figure 4.5-1 illustrates the reset operation flow.
Figure 4.5-1 Reset Operation Flow
External reset when the power is turned on
External reset
Software reset
Watchdog timer reset
During a reset
Inactive
Main oscillation
Oscillation stabilization wait reset state
Active
Mode data fetch
Mode fetch
(reset operation)
Normal operation
(Run state)
Reset vector fetch
Instruction execution with instruction code read
from the address located by the reset vector
■ Mode Pins
The mode pins (MD0 to MD3) specify how to fetch the reset vector and mode data. They are fetched in the
reset sequence.
■ Mode Fetch
When released from a reset, the CPU fetches the reset vector and mode data into the corresponding
registers in the CPU core. The reset vector and mode data are assigned FFFFCH and FFFF8H, respectively.
Immediately after released from the reset, the CPU output these addresses to the internal bus to fetch the
reset vector and mode data. Through this mode fetch, the CPU starts processing from the address located by
the reset vector.
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CHAPTER 4 RESET
4.6 Reset Source Bits
4.6
MB91210 Series
Reset Source Bits
A reset factor can be identified by reading the reset source register/watchdog timer
control register (RSRR).
■ Reset
As illustrated in Figure 4.6-1, flip-flops are provided for individual types of reset factors. The contents are
obtained by reading the reset source register/watchdog timer control register (RSRR). To identify a reset
factor after the reset is released, process the values read from the reset source register/watchdog timer
control register (RSRR) by software and branch them to an appropriate program.
Figure 4.6-1 Reset Source Bit Block Diagram
INITX pin
Not cleared
periodically
External reset
request detection circuit
Watchdog timer
control register
(RSRR)
Watchdog timer
reset detection circuit
RST bit set
RST bit write
detection circuit
Internal reset
D CL
F/F
Q CK
D CL
F/F
Q CK
D CL
F/F
Q CK
Q CL
F/F
D CK
System base
clock
Watchdog timer
control register
(RSRR) read
Internal data bus
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4.6 Reset Source Bits
MB91210 Series
■ Reset Source Bits and Reset Factors
Figure 4.6-2 shows the reset source bits (in RSRR), and Table 4.6-1 shows the contents and correspondence
to reset factors. For details, see "3.9 Clock Generation Control".
Figure 4.6-2 Reset Source Bit Configuration (RSRR)
RSRR
Address
000480H
bit15
bit14
Reserved Reserved
R
R
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
WDOG
R
ERST
R
SRST
R
Reserved
WT1
R/W
WT0
R/W
X-***-00B
R
(*)… Initialized by a source.
R/W: Readable/writable
R:
Read only
X:
Undefined
Table 4.6-1 Reset Source Bit Settings and Reset Factors
Reset factor
ERST
WDOG
SRST
Reset request generated upon watchdog timer overflow
*
1
*
External reset request from INITX pin
1
*
*
Software reset request
*
*
1
*: Previous state held
■ Notes on Reset Source Bits
● If multiple reset factors are generated
If multiple reset factors occur, their corresponding reset factor bits are set to "1" in the reset source register/
watchdog timer control register (RSRR). For example, if an external reset request via the INITX pin and a
watchdog timer overflow occur at the same time, both of the ERST and WDOG bits are set to "1".
● Clearing reset source bits
Reset source bits are cleared only when the reset source register/watchdog timer control register (RSRR) is
read. The flag set in the bit corresponding to each reset factor is not cleared (but remains "1") even when a
reset occurs with another reset factor.
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4.7 Pin States at a Reset
4.7
MB91210 Series
Pin States at a Reset
This section explains the state of each pin at a reset.
■ Pin States during a Reset
The states of pins are determined by the settings of the mode pins (MD3 to MD0 = 000XB).
● When internal vector mode is set (MD3, MD2, MD1, MD0 = 0000B)
All of the I/O pins (peripheral resource pins) are placed at high impedance. Mode data is read from internal
ROM.
● When external vector mode is set (MD3, MD2, MD1, MD0 = 0001B)
All of the I/O pins (peripheral resource pins) are placed at high impedance. Mode data is read from external
ROM.
Note:
The MB91210 series supports only internal vector mode.
■ Pin States after Mode Data is Read
The states of pins after mode data is read are determined by the mode data.
● When single-chip mode is selected
All of the I/O pins (peripheral resource pins) are placed at high impedance. The reset vector is read from
internal ROM.
● When external bus mode is selected
All of the I/O pins (peripheral resource pins) are placed at high impedance. The reset vector is read from
external ROM.
Note:
For those pins which are placed at high impedance when a reset factor occurs, take measures to
prevent the devices connected to the pins from malfunctioning.
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CHAPTER 5
I/O PORTS
This chapter gives an overview of I/O ports and
describes their register configuration and functions.
5.1 Overview of I/O Ports
5.2 Port Data Registers (PDRs) and Data Direction Registers (DDRs)
5.3 Settings of Port Function Registers
5.4 Selecting Pin Input Levels
5.5 Pull-up/Pull-down Control Registers
5.6 Input Data Direct Read Registers
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CHAPTER 5 I/O PORTS
5.1 Overview of I/O Ports
5.1
MB91210 Series
Overview of I/O Ports
This section gives an overview of the I/O ports of the MB91210 series.
■ Basic Block Diagram of Ports
The MB91210 series can use its pins as I/O ports when they are set not to serve for output to their
respective peripherals.
Figure 5.1-1 is a basic block diagram of ports.
Figure 5.1-1 Basic Block Diagrams of Ports
R-bus
PILR
PIDR read
CMOS Schmitt
Peripheral input
0
0
CLKP
PDR read
PPER
PPCR
PIDR
Automotive
1
50 kΩ
Pull-up/
pull-down
control
Output
driver
Peripheral output
Peripheral output
1
Pin
Output
MUX
PDR
50 kΩ
DDR
PFR
134
Port
direction
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CHAPTER 5 I/O PORTS
5.1 Overview of I/O Ports
MB91210 Series
■ General Specifications of Ports
• Each port has a port data register (PDR) to store output data. A reset does not initialize the PDR register.
• Each port has a data direction register (DDR) to switch its data direction between input and output. A
reset switches the data direction of all ports to input (DDR=00H).
- Port input mode (PFR=0 & DDR=0)
PDR read : Reads the level at the corresponding external pin.
PDR write : Writes a set value to the port data register.
- Port output mode (PFR=0 & DDR=1)
PDR read : Reads a value from the port data register.
PDR write : Writes a set value to the port data register to output it to the corresponding external pin.
- Peripheral output mode (PFR=1)
PDR read : Reads the output value from the corresponding peripheral.
PDR write : Writes a set value to the port data register.
- The read-modify-write (RMW) instruction for a port data register reads the register set value
irrespective of the state of the corresponding port.
- Barring some unique circumstance, the input to a peripheral is always connected to a pin. Usually,
use the port input mode for input to a peripheral.
• Each port has an input data direct read register (PIDR). The register is read-only; it can be used to
directly read the input value even when the port is in the output state.
• Each port has a port input level register (PILR) that allows the pin input level to be switched by
software. The input level can be selected to be either CMOS Schmitt trigger or CMOS automotive
Schmitt trigger.
• Each port has a pull-up/pull-down enable register (PPER) and a pull-up/pull-down control register,
allowing a 50kΩ pull-up/pull-down resistor to be set for the corresponding pin.
• Each port has a port function register (PFR) used mainly for controlling the output of the corresponding
peripheral.
• If the HIZ bit in the standby control register (STCR) is set in STOP mode, the input maintains the value
immediately prior to standby. Note, however, that the external interrupt inputs to their respective pins
are not fixed and can be used as interrupts when the interrupts are enabled (with the ENIR bit set and the
EISSR register selecting the input pins).
• Two-way signals of peripherals (such as the SCK of the LIN-UART) are enabled by the PFR register.
Notes:
• When a port is switched from peripheral output (PFR=1) to port input (PFR=0) with DDR=0, the
PDR value (register set value) is output for one CLKP cycle.
• There is no register for switching between general-purpose port input and peripheral input.
A value input from an external pin is always transmitted to a general-purpose port and a
peripheral circuit.
Also even when DDR is set to output, a value output to the outside is always transmitted to a
general-purpose port and a peripheral circuit.
To use ports as peripheral input, set DDR to input to enable input signals from each peripheral.
• For MB91F211B, the sub clock pins X0A and X1A become the I/O ports P72 and P73 only when
the mode pins MD3 to MD0 are set to 0011B. When the mode pins MD3 to MD0 are set to 0000B,
the pins X0A and X1A are enabled as sub clock pins. At this time, input as P72 and P73 is fixed
to "0" internally.
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CHAPTER 5 I/O PORTS
5.2 Port Data Registers (PDRs) and Data Direction Registers (DDRs)
5.2
MB91210 Series
Port Data Registers (PDRs) and
Data Direction Registers (DDRs)
This section lists the port data registers (PDRs) and data direction registers (DDRs).
■ Port Data Registers (PDRs)
Figure 5.2-1 Port Data Registers (PDRs)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PDR0
000000H
PDR07
PDR06
PDR05
PDR04
PDR03
PDR02
PDR01
PDR00
XXXXXXXXB
PDR1
000001H
PDR17
PDR16
PDR15
PDR14
PDR13
PDR12
PDR11
PDR10
XXXXXXXXB
PDR2
000002H
PDR27
PDR26
PDR25
PDR24
PDR23
PDR22
PDR21
PDR20
XXXXXXXXB
PDR3
000003H
PDR37
PDR36
PDR35
PDR34
PDR33
PDR32
PDR31
PDR30
XXXXXXXXB
PDR4
000004H
PDR47
PDR46
PDR45
PDR44
PDR43
PDR42
PDR41
PDR40
XXXXXXXXB
PDR5
000005H
PDR57
PDR56
PDR55
PDR54
PDR53
PDR52
PDR51
PDR50
XXXXXXXXB
PDR6
000006H
-
-
-
PDR64
PDR63
PDR62
PDR61
PDR60
---XXXXXB
PDR7
000007H
PDR77
PDR76
PDR75
PDR74
PDR73
PDR72
PDR71
PDR70
XXXXXXXXB
PDR8
000008H
-
-
PDR85
PDR84
PDR83
PDR82
PDR81
PDR80
--XXXXXXB
PDR9
000009H
PDR97
PDR96
PDR95
PDR94
PDR93
PDR92
PDR91
PDR90
XXXXXXXXB
PDRA
00000AH PDRA7
PDRA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
XXXXXXXXB
PDRB
00000BH PDRB7
PDRB6
PDRB5
PDRB4
PDRB3
PDRB2
PDRB1
PDRB0
XXXXXXXXB
PDRC
00000CH PDRC7 PDRC6 PDRC5 PDRC4 PDRC3 PDRC2 PDRC1 PDRC0
XXXXXXXXB
PDRD
00000DH PDRD7 PDRD6 PDRD5 PDRD4 PDRD3 PDRD2 PDRD1 PDRD0
XXXXXXXXB
PDRE
00000EH
-
-
-
-
-
PDRE2
PDRE1
PDRE0
-----XXXB
PDRF
00000FH
PDRF7
PDRF6
PDRF5
PDRF4
PDRF3
PDRF2
PDRF1
PDRF0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
X:
Undefined
-:
Undefined bit
The initial value of each PDR is indeterminate. Set its value before use.
136
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CHAPTER 5 I/O PORTS
5.2 Port Data Registers (PDRs) and Data Direction Registers (DDRs)
MB91210 Series
■ Data Direction Registers (DDRs)
Figure 5.2-2 Data Direction Registers (DDRs)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DDR0
000400H
DDR07
DDR06
DDR05
DDR04
DDR03
DDR02
DDR01
DDR00
00000000B
DDR1
000401H
DDR17
DDR16
DDR15
DDR14
DDR13
DDR12
DDR11
DDR10
00000000B
DDR2
000402H
DDR27
DDR26
DDR25
DDR24
DDR23
DDR22
DDR21
DDR20
00000000B
DDR3
000403H
DDR37
DDR36
DDR35
DDR34
DDR33
DDR32
DDR31
DDR30
00000000B
DDR4
000404H
DDR47
DDR46
DDR45
DDR44
DDR43
DDR42
DDR41
DDR40
00000000B
DDR5
000405H
DDR57
DDR56
DDR55
DDR54
DDR53
DDR52
DDR51
DDR50
00000000B
DDR6
000406H
-
-
-
DDR64
DDR63
DDR62
DDR61
DDR60
---00000B
DDR7
000407H
DDR77
DDR76
DDR75
DDR74
DDR73
DDR72
DDR71
DDR70
00000000B
DDR8
000408H
-
-
DDR85
DDR84
DDR83
DDR82
DDR81
DDR80
--000000B
DDR9
000409H
DDR97
DDR96
DDR95
DDR94
DDR93
DDR92
DDR91
DDR90
00000000B
DDRA
00040AH DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
00000000B
DDRB
00040BH DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
00000000B
DDRC 00040CH DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
00000000B
DDRD 00040DH DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
00000000B
DDRE
00040EH
-
-
-
-
-
DDRE2 DDRE1 DDRE0
DDRF
00040FH
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-----000B
00000000B
R/W: Readable/Writable
X:
Undefined
-:
Undefined bit
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
5.3
MB91210 Series
Settings of Port Function Registers
This section describes the functions of port functions registers.
When a pin is switched from peripheral output to port input by the PFR register, the
PDR register value is output for one cycle. Set the PDR register to an appropriate value.
The PDR's initial value is indeterminate.
■ Port 0
Figure 5.3-1 Port Function Register (PFR0)
PFR0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000420H
PFR07
R/W
PFR06
R/W
PFR05
R/W
PFR04
R/W
-
PFR02
R/W
PFR01
R/W
-
0000-00-B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR07
PFR06
PFR05
PFR04
PFR02
PFR01
138
Value
Function
0
General-purpose port
1
OCU5 output
0
General-purpose port
1
OCU4 output
0
General-purpose port
1
UART6 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART6.
0
General-purpose port
1
UART6 SOT output
0
General-purpose port
1
UART5 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART5.
0
General-purpose port
1
UART5 SOT output
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 1
Figure 5.3-2 Port Function Register (PFR1)
PFR1
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000421H
PFR17
R/W
PFR16
R/W
-
PFR14
R/W
PFR13
R/W
-
PFR11
R/W
-
00-00-0-B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR17
PFR16
PFR14
PFR13
PFR11
CM71-10139-5E
Value
Function
0
General-purpose port
1
UART4 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART4.
0
General-purpose port
1
UART4 SOT output
0
General-purpose port
1
UART3 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART3.
0
General-purpose port
1
UART3 SOT output
0
General-purpose port
1
TOT output of reload timer 1
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 2
Figure 5.3-3 Port Function Register (PFR2)
PFR2
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000422H
PFR27
R/W
PFR26
R/W
PFR25
R/W
PFR24
R/W
PFR23
R/W
PFR22
R/W
PFR21
R/W
PFR20
R/W
00000000B
R/W: Readable/writable
Bit
PFR27
PFR26
PFR25
PFR24
PFR23
PFR22
PFR21
PFR20
Value
Function
0
General-purpose port
1
PPGE output
0
General-purpose port
1
PPGC output
0
General-purpose port
1
PPGA output
0
General-purpose port
1
PPG8 output
0
General-purpose port
1
PPG6 output
0
General-purpose port
1
PPG4 output
0
General-purpose port
1
PPG2 output
0
General-purpose port
1
PPG0 output
■ Port 3
Figure 5.3-4 Port Function Register (PFR2)
PFR3
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000423H
-
-
-
-
-
-
PFR31
R/W
PFR30
R/W
------00B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR31
PFR30
140
Value
Function
0
General-purpose port
1
CAN2 TX output
0
General-purpose port
1
INT10 with EISSR10=0
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 4
Figure 5.3-5 Port Function Register (PFR4)
PFR4
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000424H
PFR47
R/W
PFR46
R/W
PFR45
R/W
PFR44
R/W
PFR43
R/W
PFR42
R/W
PFR41
R/W
PFR40
R/W
00000000B
R/W: Readable/writable
Bit
PFR47
PFR46
PFR45
PFR44
PFR43
PFR42
PFR41
PFR40
CM71-10139-5E
Value
Function
0
General-purpose port
1
The LSYN output of UART3 is connected to ICU3.
0
General-purpose port
1
The LSYN output of UART2 is connected to ICU2.
0
General-purpose port
1
The LSYN output of UART1 is connected to ICU1.
0
General-purpose port
1
The LSYN output of UART0 is connected to ICU0.
0
General-purpose port
1
PPGF output
0
General-purpose port
1
PPGD output
0
General-purpose port
1
PPGB output
0
General-purpose port
1
PPG9 output
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 5
Figure 5.3-6 Port Function Register (PFR5)
PFR5
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000425H
-
PFR56
R/W
PFR55
R/W
PFR54
R/W
PFR53
R/W
PFR52
R/W
PFR51
R/W
PFR50
R/W
-0000000B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR56
PFR55
PFR54
PFR53
PFR52
PFR51
PFR50
Value
Function
0
General-purpose port
1
The LSYN output of UART6 is connected to ICU6.
0
General-purpose port
1
The LSYN output of UART5 is connected to ICU5.
0
General-purpose port
1
The LSYN output of UART4 is connected to ICU4.
0
General-purpose port
1
PPG7 output
0
General-purpose port
1
PPG5 output
0
General-purpose port
1
PPG3 output
0
General-purpose port
1
PPG1 output
■ Port 6
Figure 5.3-7 Port Function Register (PFR6)
PFR6
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000426H
-
-
-
-
-
-
PFR61
R/W
PFR60
R/W
------00B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR61
PFR60
142
Value
Function
0
General-purpose port
1
OCU7 output
0
General-purpose port
1
OCU6 output
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CM71-10139-5E
CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 7
Figure 5.3-8 Port Function Register (PFR7)
PFR7
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000427H
PFR77
R/W
PFR76
R/W
PFR75
R/W
PFR74
R/W
PFR73
R/W
-
PFR71
R/W
-
00000-0-B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR77
PFR76
PFR75
PFR74
PFR73
PFR71
Value
Function
0
General-purpose port
1
OCU3 output
0
General-purpose port
1
OCU2 output
0
General-purpose port
1
OCU1 output
0
General-purpose port
1
OCU0 output
0
General-purpose port
1
CAN1 TX output
0
General-purpose port
1
CAN0 TX output
■ Port 8
Figure 5.3-9 Port Function Register (PFR8)
PFR8
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000428H
PFR87
R/W
PFR86
R/W
PFR85
R/W
-
-
-
-
-
000-----B
R/W: Readable/writable
-:
Undefined bit
Bit
PFR87
PFR86
PFR85
CM71-10139-5E
Value
Function
0
General-purpose port
1
Setting is prohibited
0
General-purpose port
1
Setting is prohibited
0
General-purpose port
1
Output of reload timer 2
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port 9
Figure 5.3-10 Port Function Register (PFR9)
PFR9
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000429H
PFR97
R/W
PFR96
R/W
PFR95
R/W
PFR94
R/W
PFR93
R/W
PFR92
R/W
PFR91
R/W
PFR90
R/W
00000000B
R/W: Readable/writable
Bit
PFR97
PFR96
PFR95
PFR94
PFR93
PFR92
PFR91
PFR90
144
Value
Function
0
General-purpose port
1
PPGE output
0
General-purpose port
1
PPGC output
0
General-purpose port
1
PPGA output
0
General-purpose port
1
PPG8 output
0
General-purpose port
1
PPG6 output
0
General-purpose port
1
PPG4 output
0
General-purpose port
1
PPG2 output
0
General-purpose port
1
PPG0 output
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CM71-10139-5E
CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port A
Figure 5.3-11 Port Function Register (PFRA)
PFRA
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042AH
-
-
-
-
-
PFRA2
R/W
PFRA1
R/W
PFRA0
R/W
-----000B
R/W: Readable/writable
-:
Undefined bit
Bit
Value
PFRA2
PFRA1
PFRA0
Function
0
General-purpose port
1
UART2 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART2.
When SCK is input, PE2 input is disabled.
0
General-purpose port
1
UART2 SOT output
0
General-purpose port
1
UART2 SIN input
PE0 input is disabled.
■ Port B
Figure 5.3-12 Port Function Register (PFRB)
PFRB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042BH
-
-
-
-
-
-
-
-
--------B
-:
Undefined bit
■ Port C
Figure 5.3-13 Port Function Register (PFRC)
PFRC
-:
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042CH
-
-
-
-
-
-
-
-
--------B
Undefined bit
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CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port D
Figure 5.3-14 Port Function Register (PFRD)
PFRD
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042DH
PFRD7
R/W
PFRD6
R/W
-
PFRD4
R/W
PFRD3
R/W
-
PFRD1
R/W
-
00-00-0-B
R/W: Readable/writable
-:
Undefined bit
Bit
PFRD7
PFRD6
PFRD4
PFRD3
PFRD1
Value
Function
0
General-purpose port
1
UART1 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART.
0
General-purpose port
1
UART1 SOT output
0
General-purpose port
1
UART0 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART0.
0
General-purpose port
1
UART0 SOT output
0
General-purpose port
1
Output of reload timer 0
■ Port E
Figure 5.3-15 Port Function Register (PFRE)
PFRE
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042EH
-
-
-
-
-
PFRE2
R/W
PFRE1
R/W
-
-----00-B
R/W: Readable/writable
-:
Undefined bit
Bit
PFRE2
PFRE1
146
Value
Function
0
General-purpose port
1
UART2 SCK
The SCK I/O direction is switched by the SCKE bit of SMR in UART2.
0
General-purpose port
1
UART2 SOT output
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CM71-10139-5E
CHAPTER 5 I/O PORTS
5.3 Settings of Port Function Registers
MB91210 Series
■ Port F
Figure 5.3-16 Port Function Register (PFRF)
PFRF
-:
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042FH
-
-
-
-
-
-
-
-
--------B
Undefined bit
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CHAPTER 5 I/O PORTS
5.4 Selecting Pin Input Levels
5.4
MB91210 Series
Selecting Pin Input Levels
The input level of each pin can be selected by software to be either CMOS Schmitt
trigger or CMOS automotive Schmitt trigger.
■ Pin Input Levels
Table 5.4-1 lists the input levels available.
Table 5.4-1 Input Levels
Name
VIH
VIL
CMOS Schmitt trigger
VIL = 0.3 × VCC
VIH = 0.7 × VCC
CMOS automotive Schmitt trigger
VIL = 0.5 × VCC
VIH = 0.8 × VCC
■ Selecting a Pin Input Level
The input level of each pin is selected by using the corresponding pin input level select register (PILR).
Table 5.4-2 lists the settings of pin input level select registers.
As switching the input level of a pin using the PILR register may generate an edge, stop the peripheral that
inputs data from the pin. You should set the PILR register before activating the peripheral.
Table 5.4-2 Setting of Pin Input Level Select Register
Pin input level
Bit
Input signal
0 [Initial value]
PILRxy
148
General-purpose port peripheral
input
CMOS Schmitt trigger
FUJITSU MICROELECTRONICS LIMITED
1
CMOS automotive Schmitt
trigger
CM71-10139-5E
CHAPTER 5 I/O PORTS
5.4 Selecting Pin Input Levels
MB91210 Series
Figure 5.4-1 Pin Input Level Select Register (PILR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PILR0
000540H PILR07
PILR06
PILR05
PILR04
PILR03
PILR02
PILR01
PILR00
00000000B
PILR1
000541H PILR17
PILR16
PILR15
PILR14
PILR13
PILR12
PILR11
PILR10
00000000B
PILR2
000542H PILR27
PILR26
PILR25
PILR24
PILR23
PILR22
PILR21
PILR20
00000000B
PILR3
000543H PILR37
PILR36
PILR35
PILR34
PILR33
PILR32
PILR31
PILR30
00000000B
PILR4
000544H PILR47
PILR46
PILR45
PILR44
PILR43
PILR42
PILR41
PILR40
00000000B
PILR5
000545H PILR57
PILR56
PILR55
PILR54
PILR53
PILR52
PILR51
PILR50
00000000B
PILR6
000546H
-
-
PILR64
PILR63
PILR62
PILR61
PILR60
---00000B
PILR7
000547H PILR77
PILR76
PILR75
PILR74
PILR73
PILR72
PILR71
PILR70
00000000B
PILR8
000548H
PILR9
000549H PILR97
-
-
-
PILR85
PILR84
PILR83
PILR82
PILR81
PILR80
--000000B
PILR96
PILR95
PILR94
PILR93
PILR92
PILR91
PILR90
00000000B
PILRA 00054AH PILRA7 PILRA6 PILRA5 PILRA4 PILRA3 PILRA2 PILRA1 PILRA0
00000000B
PILRB 00054BH PILRB7 PILRB6 PILRB5 PILRB4 PILRB3 PILRB2 PILRB1 PILRB0
00000000B
PILRC 00054CH PILRC7 PILRC6 PILRC5 PILRC4 PILRC3 PILRC2 PILRC1 PILRC0
00000000B
PILRD 00054DH PILRD7 PILRD6 PILRD5 PILRD4 PILRD3 PILRD2 PILRD1 PILRD0
00000000B
PILRE 00054EH
PILRE2 PILRE1 PILRE0
--000000B
PILRF 00054FH PILRF7 PILRF6 PILRF5 PILRF4 PILRF3 PILRF2 PILRF1 PILRF0
00000000B
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
R/W
R/W
R/W
R/W: Readable/Writable
-:
Undefined bit
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CHAPTER 5 I/O PORTS
5.5 Pull-up/Pull-down Control Registers
5.5
MB91210 Series
Pull-up/Pull-down Control Registers
Pins can be added with a 50kΩ pull-up or pull-down resistor. This function can be
controlled by software using the bit for each pin.
■ Pull-up/Pull-down Control
The pull-up/pull-down function is enabled by the port pull-up/pull-down enable register (PPER); pull-up/
pull-down control is exercised according to the port pull-up/pull-down control register (PPCR).
Pin pull-up/pull-down control is disabled automatically in the following cases:
• Port in the output state
• In STOP mode
■ Port Pull-up/Pull-down Enable Registers
Table 5.5-1 shows the settings of port pull-up/pull-down enable registers.
Table 5.5-1 Settings of Port Pull-up/Pull-down Enable Registers
Port pull-up/pull-down enable register
Bit
PPERxy
0 [Initial value]
1
Disables pull-up/pull-down control.
Enables pull-up/pull-down control.
Figure 5.5-1 Port Pull-up/Pull-down Enable Registers (PPER)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PPER0 000500H PPER07 PPER06 PPER05 PPER04 PPER03 PPER02 PPER01 PPER00
00000000B
PPER1 000501H PPER17 PPER16 PPER15 PPER14 PPER13 PPER12 PPER11 PPER10
00000000B
PPER2 000502H PPER27 PPER26 PPER25 PPER24 PPER23 PPER22 PPER21 PPER20
00000000B
PPER3 000503H PPER37 PPER36 PPER35 PPER34 PPER33 PPER32 PPER31 PPER30
00000000B
PPER4 000504H PPER47 PPER46 PPER45 PPER44 PPER43 PPER42 PPER41 PPER40
00000000B
PPER5 000505H PPER57 PPER56 PPER55 PPER54 PPER53 PPER52 PPER51 PPER50
00000000B
PPER6 000506H
-
-
-
PPER64 PPER63 PPER62 PPER61 PPER60
---00000B
PPER7 000507H PPER77 PPER76 PPER75 PPER74 PPER73 PPER72 PPER71 PPER70
00000000B
PPER8 000508H
PPER85 PPER84 PPER83 PPER82 PPER81 PPER80
--000000B
PPER9 000509H PPER97 PPER96 PPER95 PPER94 PPER93 PPER92 PPER91 PPER90
00000000B
PPERA 00050AH PPERA7 PPERA6 PPERA5 PPERA5 PPERA4 PPERA3 PPERA1 PPERA0
00000000B
-
-
PPERB 00050BH PPERB7 PPERB6 PPERB5 PPERB4 PPERB3 PPERB2 PPERB1 PPERB0
00000000B
PPERC 00050CH PPERC7 PPERC6 PPERC5 PPERC4 PPERC3 PPERC2 PPERC1 PPERC0
PPERD 00050DH PPERD7 PPERD6 PPERD5 PPERD4 PPERD3 PPERD2 PPERD1 PPERD0
00000000B
PPERE 00050EH
PPERE2 PPERE1 PPERE0
PPERF 00050FH PPERF7 PPERF6 PPERF5 PPERF4 PPERF3 PPERF2 PPERF1 PPERF0
-----000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
R/W
R/W: Readable/Writable
-:
Undefined bit
150
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CHAPTER 5 I/O PORTS
5.5 Pull-up/Pull-down Control Registers
MB91210 Series
■ Port Pull-up/Pull-down Control Registers
Table 5.5-2 shows the settings of port pull-up/pull-down control registers. The setting of each bit is valid
only with the corresponding PPER bit set.
Table 5.5-2 Settings of Port Pull-up/Pull-down Control Registers
Port pull-up/pull-down control register
Bit
PPCRxy
0
1 (Initial value)
Pull-down
Pull-up
Figure 5.5-2 Port Pull-up/Pull-down Control Registers (PPCR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PPCR0 000520H PPCR07 PPCR06 PPCR05 PPCR04 PPCR03 PPCR02 PPCR01 PPCR00
11111111B
PPCR1 000521H PPCR17 PPCR16 PPCR15 PPCR14 PPCR13 PPCR12 PPCR11 PPCR10
11111111B
PPCR2 000522H PPCR27 PPCR26 PPCR25 PPCR24 PPCR23 PPCR22 PPCR21 PPCR20
11111111B
PPCR3 000523H PPCR37 PPCR36 PPCR35 PPCR34 PPCR33 PPCR32 PPCR31 PPCR30
11111111B
PPCR4 000524H PPCR47 PPCR46 PPCR45 PPCR44 PPCR43 PPCR42 PPCR41 PPCR40
11111111B
PPCR5 000525H PPCR57 PPCR56 PPCR55 PPCR54 PPCR53 PPCR52 PPCR51 PPCR50
11111111B
PPCR6 000526H
-
-
-
PPCR64 PPCR63 PPCR62 PPCR61 PPCR60
---11111B
PPCR7 000527H PPCR77 PPCR76 PPCR75 PPCR74 PPCR73 PPCR72 PPCR71 PPCR70
11111111B
PPCR8 000528H
PPCR85 PPCR84 PPCR83 PPCR82 PPCR81 PPCR80
--111111B
PPCR9 000529H PPCR97 PPCR96 PPCR95 PPCR94 PPCR93 PPCR92 PPCR91 PPCR90
11111111B
PPCRA 00052AH PPCRA7 PPCRA6 PPCRA5 PPCRA4 PPCRA3 PPCRA2 PPCRA1 PPCRA0
11111111B
PPCRB 00052BH PPCRB7 PPCRB6 PPCRB5 PPCRB4 PPCRB3 PPCRB2 PPCRB1 PPCRB0
11111111B
PPCRC 00052CH PPCRC7 PPCRC6 PPCRC5 PPCRC4 PPCRC3 PPCRC2 PPCRC1 PPCRC0
11111111B
PPCRD 00052DH PPCRD7 PPCRD6 PPCRD5 PPCRD4 PPCRD3 PPCRD2 PPCRD1 PPCRD0
11111111B
PPCRE 00052EH
PPCRE2 PPCRE1 PPCRE0
PPCRF 00052FH PPCRF7 PPCRF6 PPCRF5 PPCRF4 PPCRF3 PPCRF2 PPCRF1 PPCRF0
-----111B
-
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
R/W
R/W: Readable/Writable
-:
Undefined bit
Note:
While pull-up or pull-down control is enabled (PPER=1), write access to the corresponding PPCR bit
is invalid, preventing the register value from being updated. The PPCR setting can be changed only
with the corresponding PPER bit containing "0".
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CHAPTER 5 I/O PORTS
5.6 Input Data Direct Read Registers
5.6
MB91210 Series
Input Data Direct Read Registers
Reading an input data direct read register returns the level at the corresponding pin
irrespective of the state of the port.
■ Input Data Direct Read Registers (PIDRs)
Figure 5.6-1 Input Data Direct Read Registers (PIDRs)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
0
Initial value
PIDR0 000620H PIDR07 PIDR06 PIDR05 PIDR04 PIDR03 PIDR02 PIDR01 PIDR00 XXXXXXXXB
PIDR1 000621H PIDR17 PIDR16 PIDR15 PIDR14 PIDR13 PIDR12 PIDR11 PIDR10 XXXXXXXXB
PIDR2 000622H PIDR27 PIDR26 PIDR25 PIDR24 PIDR23 PIDR22 PIDR21 PIDR20 XXXXXXXXB
PIDR3 000623H PIDR37 PIDR36 PIDR35 PIDR34 PIDR33 PIDR32 PIDR31 PIDR30 XXXXXXXXB
PIDR4 000624H PIDR47 PIDR46 PIDR45 PIDR44 PIDR43 PIDR42 PIDR41 PIDR40 XXXXXXXXB
PIDR5 000625H PIDR57 PIDR56 PIDR55 PIDR54 PIDR53 PIDR52 PIDR51 PIDR50 XXXXXXXXB
PIDR6 000626H
-
-
-
PIDR64 PIDR63 PIDR62 PIDR61 PIDR60
---XXXXXB
PIDR7 000627H PIDR77 PIDR76 PIDR75 PIDR74 PIDR73 PIDR72 PIDR71 PIDR70 XXXXXXXXB
PIDR8 000628H
-
-
PIDR85 PIDR84 PIDR83 PIDR82 PIDR81 PIDR80
--XXXXXXB
PIDR9 000629H PIDR97 PIDR96 PIDR95 PIDR94 PIDR93 PIDR92 PIDR91 PIDR90 XXXXXXXXB
PIDRA 00062AH PIDRA7 PIDRA6 PIDRA5 PIDRA4 PIDRA3 PIDRA2 PIDRA1 PIDRA0 XXXXXXXXB
PIDRB 00062BH PIDRA7 PIDRA6 PIDRB5 PIDRB4 PIDRB3 PIDRB2 PIDRB1 PIDRB0 XXXXXXXXB
PIDRC 00062CH PIDRC7 PIDRC6 PIDRC5 PIDRC4 PIDRC3 PIDRC2 PIDRC1 PIDRC0 XXXXXXXXB
PIDRD 00062DH PIDRD7 PIDRD6 PIDRD5 PIDRD4 PIDRD3 PIDRD2 PIDRD1 PIDRD0 XXXXXXXXB
PIDRE 00062EH
PIDRE2 PIDRE1 PIDRE0
-----XXXB
PIDRF 00062FH PIDRF7 PIDRF6 PIDRF5 PIDRF4 PIDRF3 PIDRF2 PIDRF1 PIDRF0 XXXXXXXXB
R
R:
X:
-:
152
R
R
R
R
R
R
R
Read only
Undefined
Undefined bit
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 6
INTERRUPT CONTROLLER
This chapter gives an overview of the interrupt
controller and describes its register configuration/
functions and its operations.
6.1 Overview of Interrupt Controller
6.2 Interrupt Controller Registers
6.3 Operations of Interrupt Controller
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CHAPTER 6 INTERRUPT CONTROLLER
6.1 Overview of Interrupt Controller
6.1
MB91210 Series
Overview of Interrupt Controller
The interrupt controller receives and arbitrates interrupts.
■ Hardware Configuration of the Interrupt Controller
This module consists of the following components:
• ICR register
• Interrupt priority judgment circuit
• Interrupt level and interrupt number (vector) generation unit
• Hold request cancel request generation unit
■ Main Functions of the Interrupt Controller
This module has the following main functions:
• Detection of NMI requests and interrupt requests
• Priority judgment (by interrupt level and number)
• Transmission of the interrupt level of the interrupt source selected by priority judgment (to the CPU)
• Transmission of the interrupt number of the interrupt source selected by priority judgment (to the CPU)
• Generation of a request (to the CPU) to return from stop mode on occurrence of an NMI or an interrupt
of an interrupt level other than 11111B
• Generation of a request to the bus master to cancel a hold request
Note:
The MB91210 series supports no NMI.
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CHAPTER 6 INTERRUPT CONTROLLER
6.1 Overview of Interrupt Controller
MB91210 Series
■ List of Interrupt Controller Registers
Figure 6.1-1 lists the registers of the interrupt controller.
Figure 6.1-1 List of Interrupt Controller Registers
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 000440H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address: 000441H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address: 000442H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address: 000443H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address: 000444H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address: 000445H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address: 000446H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address: 000447H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address: 000448H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address: 000449H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address: 00044AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address: 00044BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address: 00044CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address: 00044DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address: 00044EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address: 00044FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address: 000450H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address: 000451H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address: 000452H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address: 000453H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address: 000454H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address: 000455H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address: 000456H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address: 000457H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address: 000458H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address: 000459H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address: 00045AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address: 00045BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address: 00045CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address: 00045DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address: 00045EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address: 00045FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
Address: 000460H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
Address: 000461H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address: 000462H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address: 000463H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address: 000464H
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
ICR36
(Continued)
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CHAPTER 6 INTERRUPT CONTROLLER
6.1 Overview of Interrupt Controller
MB91210 Series
(Continued)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 000465H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
Address: 000466H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address: 000467H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address: 000468H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address: 000469H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address: 00046AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address: 00046BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address: 00046CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address: 00046DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address: 00046EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address: 00046FH
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
ICR47
Address: 000045H
MHALTI
R/W
-
-
LVL4
R
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
HRCL
R/W: Readable/writable
R:
Read only
-:
Undefined bit
■ Interrupt Controller Block Diagram
Figure 6.1-2 is a block diagram of the interrupt controller.
Figure 6.1-2 Interrupt Controller Block Diagram
WAKEUP (Level ≠ 11111B: "1")
UNMI
Priority judgment
NMI
processing
LVL4 to LVL0
5
Level/
vector
generation
Level judgment
RI00
·
·
·
RI47
(DLYIRQ)
ICR00
·
·
·
ICR47
Vector
judgment
6
Hold
request
cancel
request
MHALTI
VCT5 to VCT0
R-bus
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CHAPTER 6 INTERRUPT CONTROLLER
6.2 Interrupt Controller Registers
MB91210 Series
6.2
Interrupt Controller Registers
This section describes the register configuration and functions of the interrupt
controller.
■ Details of Interrupt Controller Registers
The interrupt controller has the following two types of registers:
• Interrupt Control Register (ICR)
• Hold Request Cancel Request Register (HRCL)
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CHAPTER 6 INTERRUPT CONTROLLER
6.2 Interrupt Controller Registers
6.2.1
MB91210 Series
Interrupt Control Register (ICR)
An interrupt control register (ICR) is provided for each interrupt input to set the
interrupt level of the corresponding interrupt request.
■ Bit Configuration of Interrupt Control Register (ICR)
The interrupt control register (ICR) consists of the following bits:
Figure 6.2-1 Interrupt Control Register (ICR)
ICR
Address
ch.0 000440H
to
ch.47 00046FH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
---11111B
-
-
-
R
R/W
R/W
R/W
R/W
R/W: Readable/writable
-:
Undefined bit
[bit4 to bit0] ICR4 to ICR0
These bits are interrupt level setting bits to specify the interrupt level of the corresponding interrupt
request.
The CPU masks the interrupt request if the interrupt level set in this register is greater than or equal to
the level mask value set in the ILM register of the CPU.
The bits are initialized to 11111B at a reset.
Table 6.2-1 lists the available settings of the interrupt level setting bits and their respective interrupt levels.
Table 6.2-1 Available Settings of Interrupt Level Setting Bits and Corresponding
Interrupt Levels
ICR4*
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ICR3
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
ICR2
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
ICR1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
ICR0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Interrupt level
0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
System-reserved
NMI
Highest level available
(High)
1
1
1
1
1
31
*: ICR4 is fixed to be "1"; "0" cannot be written to it.
158
FUJITSU MICROELECTRONICS LIMITED
(Low)
Interrupts disabled
CM71-10139-5E
CHAPTER 6 INTERRUPT CONTROLLER
6.2 Interrupt Controller Registers
MB91210 Series
6.2.2
Hold Request Cancel Request Register (HRCL)
The hold request cancel request register (HRCL) is a level setting register for
generating a request to cancel a hold request.
■ Bit Configuration of Hold Request Cancel Request Register (HRCL)
The hold request cancel request register (HRCL) consists of the following bits:
Figure 6.2-2 Hold Request Cancel Request Register (HRCL)
HRCL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000045H
MHALTI
-
-
LVL4
LVL3
LVL2
LVL1
LVL0
0--11111B
R/W
-
-
R
R/W
R/W
R/W
R/W
R/W: Readable/writable
R:
Read only
-:
Undefined bit
[bit7] MHALTI
MHALTI is a DMA transfer inhibit bit using an NMI request. The bit is set to "1" by an NMI request
and is cleared by writing "0". Clear this bit at the end of the NMI routine in the same way as in standard
interrupt routines.
Note:
The MB91210 series supports no NMI.
[bit4 to bit0] LVL4 to LVL0
These bits set the interrupt level for generating a request to the bus master to cancel a hold request.
If an interrupt request with a higher priority level than the interrupt level set in this register occurs, a
request to cancel the hold request is issued to the bus master.
The LVL4 bit is fixed to be "1"; "0" cannot be written to it.
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CHAPTER 6 INTERRUPT CONTROLLER
6.3 Operations of Interrupt Controller
6.3
MB91210 Series
Operations of Interrupt Controller
This section describes the operations of the interrupt controller.
■ Determining the Priority
This module selects the highest-priority interrupt among any interrupt sources that occur simultaneously
and outputs its interrupt level and interrupt number to the CPU.
The criteria for determining the priority of interrupt sources are as follows.
1) NMI
2) Interrupt source that satisfies the following conditions
- Interrupt source whose interrupt level is not 31. (31 indicates "interrupt disabled".)
- Interrupt source with the lowest interrupt level value.
- Interrupt source with the smallest interrupt number while satisfying the above
If no interrupt source is selected by the above criteria, 31 (11111B) is output as the interrupt level. The
interrupt number in this case is indeterminate.
Table 6.3-1 lists interrupt sources and their respective interrupt numbers and interrupt levels.
Note:
The MB91210 series supports no NMI.
Table 6.3-1 Interrupt Sources and Their Respective Interrupt Numbers and Levels (1 / 3)
Interrupt No.
Decimal
Hexadecimal
Interrupt level
Offset
TBR default
address
Resource
number
Reset
0
00H
—
3FCH
000FFFFCH
—
Mode vector
1
01H
—
3F8H
000FFFF8H
—
(Reserved)
2
02H
—
3F4H
000FFFF4H
—
(Reserved)
3
03H
—
3F0H
000FFFF0H
—
(Reserved)
4
04H
—
3ECH
000FFFECH
—
(Reserved)
5
05H
—
3E8H
000FFFE8H
—
(Reserved)
6
06H
—
3E4H
000FFFE4H
—
Coprocessor absence trap
7
07H
—
3E0H
000FFFE0H
—
Coprocessor error trap
8
08H
—
3DCH
000FFFDCH
—
INTE instruction
9
09H
—
3D8H
000FFFD8H
—
(Reserved)
10
0AH
—
3D4H
000FFFD4H
—
(Reserved)
11
0BH
—
3D0H
000FFFD0H
—
Step trace trap
12
0CH
—
3CCH
000FFFCCH
—
Interrupt source
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CHAPTER 6 INTERRUPT CONTROLLER
6.3 Operations of Interrupt Controller
MB91210 Series
Table 6.3-1 Interrupt Sources and Their Respective Interrupt Numbers and Levels (2 / 3)
Interrupt No.
Decimal
Hexadecimal
Interrupt level
Offset
TBR default
address
Resource
number
NMI request (tool)
13
0DH
—
3C8H
000FFFC8H
—
Undefined instruction exception
14
0EH
—
3C4H
000FFFC4H
—
NMI request
15
0FH
15(FH) fixed
3C0H
000FFFC0H
—
External interrupt 0
16
10H
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11H
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12H
ICR02
3B4H
000FFFB4H
—
External interrupt 3
19
13H
ICR03
3B0H
000FFFB0H
—
External interrupt 4
20
14H
ICR04
3ACH
000FFFACH
—
External interrupt 5
21
15H
ICR05
3A8H
000FFFA8H
—
External interrupt 6
22
16H
ICR06
3A4H
000FFFA4H
—
External interrupt 7
23
17H
ICR07
3A0H
000FFFA0H
—
Reload timer 0
24
18H
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19H
ICR09
398H
000FFF98H
9
Reload timer 2
26
1AH
ICR10
394H
000FFF94H
10
Reception by UART 0
27
1BH
ICR11
390H
000FFF90H
0
Transmission by UART 0
28
1CH
ICR12
38CH
000FFF8CH
3
Reception by UART 1
29
1DH
ICR13
388H
000FFF88H
1
Transmission by UART 1
30
1EH
ICR14
384H
000FFF84H
4
Reception by UART 2
31
1FH
ICR15
380H
000FFF80H
2
Transmission by UART 2
32
20H
ICR16
37CH
000FFF7CH
5
CAN 0
33
21H
ICR17
378H
000FFF78H
—
CAN 1
34
22H
ICR18
374H
000FFF74H
—
Reception by UART 3/5
35
23H
ICR19
370H
000FFF70H
—
Transmission by UART 3/5
36
24H
ICR20
36CH
000FFF6CH
—
Reception by UART 4/6
37
25H
ICR21
368H
000FFF68H
—
Transmission by UART 4/6
38
26H
ICR22
364H
000FFF64H
—
AD converter
39
27H
ICR23
360H
000FFF60H
15
RTC/CAN 2
40
28H
ICR24
35CH
000FFF5CH
—
ICU 0
41
29H
ICR25
358H
000FFF58H
11
ICU 1
42
2AH
ICR26
354H
000FFF54H
12
ICU 2/3
43
2BH
ICR27
350H
000FFF50H
—
ICU 4/5/6/7
44
2CH
ICR28
34CH
000FFF4CH
—
FRT 0/1/2/3
45
2DH
ICR29
348H
000FFF48H
—
Main oscillation stabilization wait timer
46
2EH
ICR30
344H
000FFF44H
—
TBT overflow
47
2FH
ICR31
340H
000FFF40H
—
OCU 0/1/2/3
48
30H
ICR32
33CH
000FFF3CH
—
Interrupt source
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6.3 Operations of Interrupt Controller
MB91210 Series
Table 6.3-1 Interrupt Sources and Their Respective Interrupt Numbers and Levels (3 / 3)
Interrupt No.
Decimal
Hexadecimal
Interrupt level
Offset
TBR default
address
Resource
number
OCU 4/5/6/7
49
31H
ICR33
338H
000FFF38H
—
PPG 0
50
32H
ICR34
334H
000FFF34H
13
PPG 1
51
33H
ICR35
330H
000FFF30H
14
PPG 2/3
52
34H
ICR36
32CH
000FFF2CH
—
PPG 4/5/6/7
53
35H
ICR37
328H
000FFF28H
—
PPG 8/9/A/B
54
36H
ICR38
324H
000FFF24H
—
PPG C/D/E/F
55
37H
ICR39
320H
000FFF20H
—
External interrupt 8
56
38H
ICR40
31CH
000FFF1CH
—
External interrupt 9
57
39H
ICR41
318H
000FFF18H
—
External interrupt 10
58
3AH
ICR42
314H
000FFF14H
—
External interrupt 11
59
3BH
ICR43
310H
000FFF10H
—
External interrupt 12/13
60
3CH
ICR44
30CH
000FFF0CH
—
External interrupt 14/15
61
3DH
ICR45
308H
000FFF08H
—
DMA (termination, error)
62
3EH
ICR46
304H
000FFF04H
—
Delayed interrupt source bit
63
3FH
ICR47
300H
000FFF00H
—
(Reserved) (Used by REALOS)
64
40H
—
2FCH
000FFEFCH
—
(Reserved) (Used by REALOS)
65
41H
—
2F8H
000FFEF8H
—
(Reserved)
66
42H
—
2F4H
000FFEF4H
—
(Reserved)
67
43H
—
2F0H
000FFEF0H
—
(Reserved)
68
44H
—
2ECH
000FFEECH
—
(Reserved)
69
45H
—
2E8H
000FFEE8H
—
(Reserved)
70
46H
—
2E4H
000FFEE4H
—
(Reserved)
71
47H
—
2E0H
000FFEE0H
—
(Reserved)
72
48H
—
2DCH
000FFEDCH
—
(Reserved)
73
49H
—
2D8H
000FFED8H
—
(Reserved)
74
4AH
—
2D4H
000FFED4H
—
(Reserved)
75
4BH
—
2D0H
000FFED0H
—
(Reserved)
76
4CH
—
2CCH
000FFECCH
—
(Reserved)
77
4DH
—
2C8H
000FFEC8H
—
(Reserved)
78
4EH
—
2C4H
000FFEC4H
—
(Reserved)
79
4FH
—
2C0H
000FFEC0H
—
80
50H
2BCH
000FFEBCH
to
to
to
to
255
FFH
000H
000FFC00H
Interrupt source
Used for INT instruction
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CHAPTER 6 INTERRUPT CONTROLLER
6.3 Operations of Interrupt Controller
MB91210 Series
■ NMI (Non Maskable Interrupt)
The NMI has the highest priority of all the interrupt sources handled by this module. Accordingly, the NMI
is always selected if it generates at the same time as another interrupt source.
● Occurrence of an NMI
When an NMI occurs, the following items of information are passed to the CPU:
Interrupt level
: 15 (01111B)
Interrupt number : 15 (0001111B)
● Detection of an NMI
The external interrupt/NMI module sets and detects NMIs. This module only generates the interrupt level,
interrupt number, and MHALTI in response to an NMI request.
● Inhibition of DMA transfer by NMI
When an NMI request occurs, the MHALTI bit in the HRCL register is set to "1" to inhibit DMA transfer.
To release DMA transfer from being inhibited, clear the MHALTI bit to "0" at the end of the NMI routine.
Note:
The MB91210 series supports no NMI.
■ Hold Request Cancel Request
If you want to process high- priority interrupts during a CPU hold (during DMA transfer), the module that
generated the hold request needs to cancel the request. Use the HRCL register to set the reference interrupt
level at which a request to cancel is to be generated.
● Generation criteria
If an interrupt source with a higher priority level than the level set in the HRCL register occurs, a request to
cancel the hold request is generated.
If interrupt level in HRCL register > level of interrupt after priority judgment, then generate cancel
request.
If interrupt level in HRCL register ≤ level of interrupt after priority judgment, then do not generate
cancel request.
The cancel request remains active until the interrupt source that generated the cancel request is cleared and
therefore no DMA transfer occurs during this time. Always clear the associated interrupt source. As the
MHALTI bit in the HRCL register is set to "1" when an NMI is used, the cancel request is active.
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6.3 Operations of Interrupt Controller
MB91210 Series
● Possible levels
The values able to be set in the HRCL register are 10000B to 11111B, the same as in the ICR.
If 11111B is set, a cancel request is generated for all interrupt levels. If 10000B is set, a cancel request is
only generated for an NMI.
Table 6.3-2 shows the interrupt level settings for generating a request to cancel a hold request.
Table 6.3-2 Interrupt Level Settings That Generate a Hold Request Cancel Request
16
NMI only
17
NMI, interrupt level 16
18
NMI, interrupt levels 16 and 17
~
Interrupt levels that generate a cancel request
~
HRCL register
31
NMI, interrupt levels 16 to 30 [Initial value]
Once a reset occurs, DMA transfer is inhibited for all interrupt levels. As this means that no DMA transfer
will be performed when an interrupt occurs, set the required value in the HRCL register.
■ Returning from Standby (Stop or Sleep) Mode
The function for using an interrupt request to return from stop mode is performed by this module. If even
one interrupt request from a peripheral including an NMI (with interrupt level other than 11111B) occurs, a
request to return from stop mode is issued to the clock control unit.
As the priority judgment unit restarts operation once the clock supply starts after recovery from stop mode,
the CPU is able to execute instructions until the priority judgment unit produces a result.
The same operation occurs when returning from sleep mode. Access to the registers in this module remains
possible even in sleep mode.
Notes:
• The device also returns from stop mode when an NMI request occurs. However, make NMI
settings such that a valid input is detected in stop mode.
• Set the interrupt level for interrupt sources that you do not want to cause the device to return from
stop or sleep mode to 11111B in the corresponding peripheral control register.
• The MB91210 series supports no NMI.
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CHAPTER 6 INTERRUPT CONTROLLER
6.3 Operations of Interrupt Controller
MB91210 Series
■ Example of Using the Function to Generate a Request to Cancel a Hold Request
(HRCR)
If you want the CPU to perform high-priority processing during DMA transfer, you need to cancel the hold
state by requesting the DMA to cancel its hold request. This example uses an interrupt to cause the DMA to
cancel its hold request and to give priority to CPU operation.
● Control registers
(1) HRCL (Hold request cancel level setting register): this module:
If an interrupt with a higher-priority level than the interrupt level set in this register occurs, a request to
cancel the hold request is passed to the DMA. Set the level to use as the criterion.
(2) ICR: this module:
Set an interrupt level with a higher priority than the level set in the HRCL register in the ICRs of the
interrupt sources you want to use.
● Hardware configuration
Figure 6.3-1 shows the flow of each signal for a hold request.
Figure 6.3-1 Hold Request Signal Flow
This module
IRQ
Bus access request
MHALTI
I-unit
(ICR)
(HRCL)
DHREQ
DMA
CPU
B-unit
DHREQ: D-bus hold request
DHACK: D-bus hold acknowledge
IRQ:
Interrupt request
MHALTI: Hold request cancel request
DHACK
● Sequence
Figure 6.3-2 shows an interrupt level: HRCL < ICR (LEVEL).
Figure 6.3-2 Interrupt Level: HRCL < ICR (LEVEL)
RUN
CPU
Bus hold
Interrupt processing
(1)
Bus hold (DMA transfer)
(2)
Bus access request
DHREQ
DHACK
IRQ
LEVEL
MHALTI
Example of interrupt routine
(1) Clear interrupt source
to
(2) RETI
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6.3 Operations of Interrupt Controller
MB91210 Series
When an interrupt request occurs and the interrupt level changes, the MHALTI signal to the DMA goes
active if the new level has a higher priority than the level set in the HRCL register. This causes the DMA to
cancel access requests and the CPU to return from the hold state and start processing the interrupt.
Figure 6.3-3 shows interrupt level: HRCL < ICR (interrupt I) < ICR (interrupt II).
Figure 6.3-3 Interrupt Level: HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
Bus hold
CPU
Interrupt
Interrupt I processing II
(3)
(4)
Interrupt
processing I
(1)
Bus hold (DMA transfer)
(2)
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
Example of interrupt routine
(1), (3) Clear interrupt source
to
(2), (4) RETI
The above example shows the case when a higher priority interrupt occurs during execution of interrupt
routine I.
DHREQ remains low while the interrupt with an interrupt level higher than the interrupt level set in the
HRCL register is present.
Note:
Pay due attention to the relationship between the interrupt levels set in the HRCL register and ICRs.
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CHAPTER 7
EXTERNAL INTERRUPT
CONTROL UNIT
This chapters gives an overview of the external interrupt
control unit and describes its register configuration/
functions and its operations.
7.1 Overview of External Interrupt Control Unit
7.2 Registers of External Interrupt Control Unit
7.3 Operations of External Interrupt Control Unit
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.1 Overview of External Interrupt Control Unit
MB91210 Series
Overview of External Interrupt Control Unit
7.1
The external interrupt control unit is a block that controls external interrupt requests
input to INT pins.
The level of a request to be detected can be selected from among the following four:
• "H" level
• "L" level
• Rising edge
• Falling edge
■ List of Registers of External Interrupt Control Unit
The registers of the external interrupt control unit are listed below.
Figure 7.1-1 List of Registers of External Interrupt Control Unit
ENIR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000041H
0000D1H
EN7
R/W
EN6
R/W
EN5
R/W
EN4
R/W
EN3
R/W
EN2
R/W
EN1
R/W
EN0
R/W
00000000B
EIRR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000040H
0000D0H
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ELVR (upper bytes)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000042H
0000D2H
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
LB4
R/W
LA4
R/W
00000000B
ELVR (lower bytes)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000043H
0000D3H
LB3
R/W
LA3
R/W
LB2
R/W
LA2
R/W
LB1
R/W
LA1
R/W
LB0
R/W
LA0
R/W
00000000B
R/W: Readable/writable
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.1 Overview of External Interrupt Control Unit
MB91210 Series
■ Block Diagram of External Interrupt Control Unit
Figure 7.1-2 is a block diagram of the external interrupt control unit.
Figure 7.1-2 Block Diagram of External Interrupt Control Unit
R-bus
8
17
Interrupt
request
Interrupt enable register
Gate
16
Source F/F
Edge detection circuit
INT0 to
INT15
8
Interrupt source register
16
Request level setting register
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
7.2
MB91210 Series
Registers of External Interrupt Control Unit
This section describes the register configuration and functions of the external interrupt
control unit.
■ Details of Registers of External Interrupt Control Unit
The external interrupt control unit has the following three types of registers:
• Interrupt Enable Register (ENIR)
• External Interrupt Source Register (EIRR)
• External Interrupt Request Level Setting Register (ELVR)
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
MB91210 Series
7.2.1
Interrupt Enable Register (ENIR)
The interrupt enable register (ENIR) controls the masking of the external interrupt
request output.
■ Bit Configuration of Interrupt Enable Register (ENIR)
The interrupt enable register consists of the following bits.
Figure 7.2-1 Interrupt Enable Register (ENIR)
ENIR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0 to ch.7 000041H
ch.8 to ch.15 0000D1H
EN7
R/W
EN6
R/W
EN5
R/W
EN4
R/W
EN3
R/W
EN2
R/W
EN1
R/W
EN0
R/W
00000000B
R/W: Readable/writable
When "1" is written to a bit in this register, the interrupt request output corresponding to the bit is enabled
(for example, EN0 controls the enabling of INT0), and the interrupt request is output to the interrupt
controller. The pin corresponding to the bit to which "0" is written holds the interrupt source but does not
generate a request to the interrupt controller.
Immediately before enabling an external interrupt (ENIR:EN=1), clear the corresponding external interrupt
source bit (EIRR:ER).
In stop mode, input is possible while external interrupts are enabled (ENIR:EN=1). Otherwise, the value
valid immediately before transition to stop mode is passed to the inside.
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
7.2.2
MB91210 Series
External Interrupt Source Register (EIRR)
The external interrupt source register (EIRR) is a register to indicate that a
corresponding external interrupt request exists when read, and to clear a content of the
flip-flop showing this request when written.
■ Bit Configuration of External Interrupt Source Register (EIRR)
The external interrupt source register consists of the following bits.
Figure 7.2-2 External Interrupt Source Register (EIRR)
EIRR
Address
bit7
ch.0 to ch.7 000040H
ch.8 to ch.15 0000D0H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The operation performed when this EIRR register is read depends on the read value as follows.
When a bit contains "1", it indicates that there is an external interrupt request at the pin corresponding to
that bit. Writing "0" to a bit in this register clears the request flip-flop of that bit.
Writing "1" to this register is invalid.
When read by a read-modify-write (RMW) instruction, the register returns "1".
Each external interrupt source bit (EIRR:ER) is enabled only when the corresponding external interrupt
enable bit (ENIR:EN) contains "1". When the external interrupt is not enabled (ENIR:EN=0), the external
interrupt source bit may be set whether there is an external interrupt source or not.
Immediately before enabling an external interrupt (ENIR:EN=1), clear the corresponding external interrupt
source bit (EIRR:ER).
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
MB91210 Series
7.2.3
External Interrupt Request Level Setting Register (ELVR)
The external interrupt request level setting register (ELVR) is a register to select request
detections.
■ Bit Configuration of External Interrupt Request Level Setting Register (ELVR)
The external interrupt request level setting register (ELVR) consists of the following bits.
Figure 7.2-3 External Interrupt Request Level Setting Register (ELVR)
ELVR (upper bytes)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch.0 to ch.7 000042H
ch.8 to ch.15 0000D2H
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
LB4
R/W
LA4
R/W
00000000B
ELVR (lower bytes)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0 to ch.7 000043H
ch.8 to ch.15 0000D3H
LB3
R/W
LA3
R/W
LB2
R/W
LA2
R/W
LB1
R/W
LA1
R/W
LB0
R/W
LA0
R/W
00000000B
R/W: Readable/writable
In the ELVR register, two bits are assigned to each interrupt channel, which results in the settings shown in
the table below.
When each bit in the EIRR register is cleared while the level is in the request input level, the corresponding
bit is set again as long as the input is at active level.
Table 7.2-1 shows assignment of ELVR.
Table 7.2-1 Assignment of ELVR
LBx, LAx
Operation
00B
"L" level indicates the presence of a request. [Initial value]
01B
"H" level indicates the presence of a request.
10B
A rising edge indicates the presence of a request.
11B
A falling edge indicates the presence of a request.
Note:
Changing the external interrupt request level may cause an interrupt source internally. After
changing the external interrupt request level, therefore, clear the external interrupt source register
(EIRR).
Before writing to clear the external interrupt source register, read external interrupt request level
register once.
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
7.2.4
MB91210 Series
Relocating External Interrupt Inputs
The MB91210 series has 16 channels of external interrupt inputs (INT0 to INT15). INT0 to
INT15 can be relocated from the pins to which they are initially assigned to other pins.
This relocation is enabled by setting the external interrupt input pin select register
(EISSR).
■ External Interrupt Input Pin Select Register (EISSR)
Figure 7.2-4 External Interrupt Input Pin Select Register (EISSR)
EISSR upper byte
Address
0001AAH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EISSR15 EISSR14 EISSR13 EISSR12 EISSR11 EISSR10 EISSR9 EISSR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
EISSR lower byte
Address
0001ABH
EISSR7 EISSR6 EISSR5 EISSR4 EISSR3 EISSR2 EISSR1 EISSR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W: Readable/writable
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.2 Registers of External Interrupt Control Unit
MB91210 Series
Table 7.2-2 shows the relocation of external interrupt input pins.
Table 7.2-2 Relocation of External Interrupt Input Pins
Bit
External interrupt
channel
External interrupt input pin
0 [Initial value]
1
EISSR15
INT15
P37
P07
EISSR14
INT14
P36
P06
EISSR13
INT13
P35
P05
EISSR12
INT12
P34
P04
EISSR11
INT11
P33
P03
EISSR10
INT10
P32/P30(RX2)
P02
EISSR9
INT9
P72 (RX1)
P01
EISSR8
INT8
P70 (RX0)
P00
EISSR7
INT7
PF7
PB7
EISSR6
INT6
PF6
PB6
EISSR5
INT5
PF5
PB5
EISSR4
INT4
PF4
PB4
EISSR3
INT3
PF3
PB3
EISSR2
INT2
PF2
PB2
EISSR1
INT1
PF1
PB1
EISSR0
INT0
PF0
PB0
Before setting the EISSR register to switch an external interrupt input pin, set the ENIR register bit for the
corresponding channel to "0" (interrupt disabled). Switching the input pin with that bit containing "1"
(interrupt enabled) may cause an interrupt immediately.
For MB91F211B, be sure to set all the bits except EISSR8 to a value other than "1" before using.
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.3 Operations of External Interrupt Control Unit
7.3
MB91210 Series
Operations of External Interrupt Control Unit
This section describes the operations of the external interrupt control unit.
■ Operations of an External Interrupt
If, after a request level and an enable register are set, a request defined in the ELVR register is input to the
corresponding pin, this module generates an interrupt request signal to the interrupt controller.
The interrupt controller identifies the priorities of interrupts simultaneously generated within the interrupt
controller and, if it determines that the interrupt request from this resource has the highest priority,
generates the corresponding interrupt.
Figure 7.3-1 shows the external interrupt operation.
Figure 7.3-1 External Interrupt Operation
External interrupt Resource request
ELVR
Interrupt controller
ICR Y Y
EIRR
ENIR
CPU
IL
CMP
ICR X X
CMP
ILM
Source
■ Operating Procedure for an External Interrupt
Set up the registers located inside the external interrupt control unit as follows:
1. Set that general-purpose I/O port as an input port which also serves as a pin to be used as an external
interrupt input.
2. Disable the target bit in the interrupt enable register (ENIR).
3. Set the target bit in the external interrupt request level setting register (ELVR).
4. Read the external interrupt request level setting register (ELVR)
5. Clear the target bit in the external interrupt source register (EIRR).
6. Enable the target bit in the interrupt enable register (ENIR).
Simultaneous writing of 16-bit data is supported for steps 5 and 6.
Before setting a register in this module, you must disable the enable register. In addition, before enabling
the enable register, you must clear the interrupt source register. This procedure is required to prevent an
interrupt source from occurring by mistake while a register is being set or an interrupt is enabled.
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.3 Operations of External Interrupt Control Unit
MB91210 Series
■ External Interrupt Request Level
If the request level is an edge request, a pulse width of at least 3 machine cycles (peripheral clock machine
cycles) is required to detect an edge.
When the request input level is a level setting, the required pulse width is a minimum of 3 machine cycles.
While the interrupt input pin is holding its active level, the interrupt request to the interrupt controller keeps
on being generated even with the external interrupt source register cleared.
If the request input level is a level setting, a request input is entered from outside and is then cancelled, the
request to the interrupt controller remains active because a source holding circuit exists internally.
The external interrupt source register must be cleared to cancel a request to the interrupt controller.
Figure 7.3-2 illustrates the clearing of the source holding circuit when a level is set.
Figure 7.3-2 Clearing the Source Holding Circuit When a Level is Set
Interrupt input
Level detection
Source F/F
(source holding circuit)
Enable gate
Interrupt
controller
Holds a source unless it is cleared.
Figure 7.3-3 shows an interrupt source and an interrupt request to the interrupt controller when interrupts
are enabled.
Figure 7.3-3 Interrupt Source with Interrupts Enables and Interrupt Request to Interrupt Controller
Interrupt source
"H" level
Interrupt request to
interrupt controller
Becomes inactive when the source F/F is cleared
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.3 Operations of External Interrupt Control Unit
MB91210 Series
■ Notes If Restoring from STOP Status Performed Using an External Interrupt
During STOP status, external interrupt signals that are first entered to the INT pin are entered
asynchronously, to enable recovery from the STOP status. However the period from that STOP being
released to the passage of oscillation stabilization wait time, contains a period during which other external
interrupt signal inputs cannot be identified (Period b+c+d for Figure 7.3-4). To synchronize external input
signals after the STOP has been released with the internal clock, while the clock is not stable, interrupt
sources cannot be stored.
Consequently, if sending external interrupt inputs after the STOP has been released, input external interrupt
signals after the oscillation stabilization wait time has elapsed.
Figure 7.3-4 Recovery Operation Sequence Using External Interrupts from STOP Status
INT1
INT0
Internal
STOP
Regulator
"H"
"L"
Internal
operation
(RUN)
Implement instruction (RUN)
X0
Internal
clock
Interrupt flag clear
INTR0
INTE0
"1" (Set to enable before switching to STOP mode)
INTR1
INTE1
"1" enable (Set before switching to STOP mode)
(e)RUN
(a) STOP (b) Regulator stabilization wait time (d) Oscillation stabilization wait time
(c) Oscillator oscillation time
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CHAPTER 7 EXTERNAL INTERRUPT CONTROL UNIT
7.3 Operations of External Interrupt Control Unit
MB91210 Series
■ Recovery Operations from STOP Status
The STOP recovery operation using external interrupts is performed as described below.
● Processing before transiting to STOP
Setting External Interrupt Route
It is necessary to permit the external interrupt input route for release STOP status before the device
transits to STOP status. These configuration are made using the EISSR register and ENIR register.
Under normal conditions (i.e., any status other than STOP), the interrupt input route is permitted, so
there is no need for special recognition. In STOP status, however, the input path is controlled by the
ENIR register value.
Pin name used for STOP release
P37/INT15
ENIR register
ENIR1[7]=1
P07INT15R
P36/INT14
ENIR1[6]=1
ENIR1[5]=1
ENIR1[4]=1
ENIR1[3]=1
EISSR[11]=0
EISSR[11]=1
ENIR1[2]=1
EISSR[10]=0, PFR3[0]=0
P30/INT10C
EISSR[10]=0, PFR3[0]=1
P02/INT10R
EISSR[10]=1
P72/INT9
ENIR1[1]=1
P01/INT9R
P70/INT8
PF7/INT7
ENIR1[0]=1
ENIR0[7]=1
ENIR0[6]=1
PB4/INT4R
EISSR[6]=0
EISSR[6]=1
ENIR0[5]=1
PB5/INT5R
PF4/INT4
EISSR[7]=0
EISSR[7]=1
PB6/INT6R
PF5/INT5
EISSR[8]=0
EISSR[8]=1
PB7/INT7R
PF6/INT6
EISSR[9]=0
EISSR[9]=1
P00/INT8R
CM71-10139-5E
EISSR[12]=0
EISSR[12]=1
P03/INT11R
P32/INT10
EISSR[13]=0
EISSR[13]=1
P04/INT12R
P33/INT11
EISSR[14]=0
EISSR[14]=1
P05/INT13R
P34/INT12
EISSR[15]=0
EISSR[15]=1
P06/INT14R
P35/INT13
EISSR register
EISSR[5]=0
EISSR[5]=1
ENIR0[4]=1
EISSR[4]=0
EISSR[4]=1
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7.3 Operations of External Interrupt Control Unit
Pin name used for STOP release
PF3/INT3
MB91210 Series
ENIR register
ENIR0[3]=1
PB3/INT3R
EISSR register
EISSR[3]=0
EISSR[3]=1
PF2/INT2
ENIR0[2]=1
PB2/INT2R
EISSR[2]=0
EISSR[2]=1
PF1/INT1
ENIR0[1]=1
PB1/INT1R
EISSR[1]=0
EISSR[1]=1
PF0/INT0
ENIR0[0]=1
PB0/INT0R
EISSR[0]=0
EISSR[0]=1
External Interrupt Inputs
If recovering from STOP status, the external interrupt signals send an input signal asynchronously.
When this interrupt signal is enabled, the internal STOP signal is immediately turned OFF. At the same
time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Regulator Stabilization Wait Time
When the internal STOP signal is turned OFF, the switching operation from the regulator on STOP to
the regulator on RUN will start. If the internal operations start before the voltage output of the regulator
on RUN has stabilized, stabilization wait time for the internal outputs voltage will be required due to
operational instability. During this time, the clock will stop.
● Oscillator Oscillation Time
After the regulator stabilization wait time has ended, the clock will start to oscillate. The oscillator
oscillation time depends on the oscillator used.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by bits OS1 and OS0 on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt instruction operations from the external interrupt, it also becomes possible to
receive external interrupt sources other than the recovery from STOP status.
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CHAPTER 8
REALOS-RELATED
HARDWARE
REALOS-related hardware is used by the real-time OS.
Therefore, when REALOS is used, the hardware cannot
be used with the user program.
8.1 Delay Interrupt Module
8.2 Bit Search Module
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CHAPTER 8 REALOS-RELATED HARDWARE
8.1 Delay Interrupt Module
8.1
MB91210 Series
Delay Interrupt Module
This section explains the overview of the delay interrupt module, configuration/
functions of the registers, and operations of the module.
■ Overview of Delay Interrupt Module
The delay interrupt module generates an interrupt to switch tasks.
Software can generate or clear an interrupt request for the CPU by using this module.
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CHAPTER 8 REALOS-RELATED HARDWARE
8.1 Delay Interrupt Module
MB91210 Series
8.1.1
Overview of Delay Interrupt Module
This section explains the register list, details, and operations of the delay interrupt
module.
■ Register List of Delay Interrupt Module
Register list of the delay interrupt module is as follows:
Figure 8.1-1 Register List of Delay Interrupt Module
DICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000044H
-
-
-
-
-
-
-
DLYI
-------0B
-
-
-
-
-
-
-
R/W
R/W: Readable/writable
-:
Undefined bit
■ Block Diagram of Delay Interrupt Module
Figure 8.1-2 shows a block diagram of the delay interrupt module.
Figure 8.1-2 Block Diagram of Delay Interrupt Module
R-bus
Interrupt
request
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CHAPTER 8 REALOS-RELATED HARDWARE
8.1 Delay Interrupt Module
8.1.2
MB91210 Series
Registers of Delay Interrupt Module
This section explains the register configurations/functions of the delay interrupt
module.
■ Delay Interrupt Module Register (DICR)
DICR controls the delay interrupt.
The bit configuration of the delay interrupt module register (DICR) is as follows:
Figure 8.1-3 Delay Interrupt Module Register (DICR)
DICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000044H
-
-
-
-
-
-
-
DLYI
-------0B
-
-
-
-
-
-
-
R/W
R/W: Readable/writable
-:
Undefined bit
[bit0] DLYI
DLYI
Description
0
No release and request of delay interrupt source [Initial value]
1
Generated delay interrupt source
This bit controls generating and releasing of the corresponding interrupt sources.
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8.1.3
CHAPTER 8 REALOS-RELATED HARDWARE
8.1 Delay Interrupt Module
Operation of Delay Interrupt Module
The delay interrupt is an interrupt generated for switching tasks. Use this function to
allow a software program to generate an interrupt request for the CPU or to clear an
interrupt request.
■ Interrupt Number
A delay interrupt is assigned to the interrupt source corresponding to the largest interrupt number.
On the MB91210 series, a delay interrupt is assigned to interrupt number 63 (3FH).
■ DLYI Bit of DICR
Writing "1" to this bit generates a delay interrupt source. Writing "0" clears a delay interrupt source.
This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bit and switch
tasks in the interrupt routine.
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
8.2
MB91210 Series
Bit Search Module
This section explains the overview of the bit search module, configurations/functions of
the registers, and operations of the module.
■ Overview of Bit Search Module
The bit search module searches for 0, 1, or any points of change for data written to the input register and
then returns the detected bit locations.
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
8.2.1
Overview of Bit Search Module
This section explains the register configurations/functions of the bit search module.
■ Register List of Bit Search Module
Register list of the bit search module is as follows:
Figure 8.2-1 Register List of Bit Search Module
BSD0
Address
bit31
bit0
0003F0H
Initial value
XXXXXXXXH
W
BSD1
Address
bit31
bit0
Initial value
XXXXXXXXH
0003F4H
R/W
BSDC
Address
bit31
bit0
Initial value
XXXXXXXXH
0003F8H
W
BSRR
Address
bit31
bit0
0003FCH
Initial value
XXXXXXXXH
R
R/W:
R:
W:
X:
Readable/writable
Read only
Write only
Undefined
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
■ Block Diagram of Bit Search Module
Figure 8.2-2 shows a block diagram of the bit search module.
Figure 8.2-2 Block Diagram of Bit Search Module
D-bus
Input latch
Address decoder
Detection mode
0/1 detection data
Bit search circuit
Search result
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
8.2.2
Registers of Bit Search Module
This section explains the register configurations/functions of the bit search module.
■ 0 Detection Data Register (BSD0)
0 detection is performed for written value.
Shown below is the configuration of the 0 detection data register (BSD0):
Figure 8.2-3 0 Detection Data Register (BSD0)
BSD0
Address
bit31
bit0
0003F0H
Initial value
XXXXXXXXH
W
W:
X:
Write only
Undefined
The initial value after a reset is undefined. The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer (Do not use 8-bit or 16-bit length data transfer
instructions).
■ 1 Detection Data Register (BSD1)
Shown below is the configuration of the 1 detection data register (BSD1):
Figure 8.2-4 1 Detection Data Register (BSD1)
BSD1
Address
bit31
bit0
Initial value
XXXXXXXXH
0003F4H
R/W
R/W: Readable/writable
X:
Undefined
Use a 32-bit length data transfer instruction for data transfer (Do not use 8-bit or 16-bit length data transfer
instructions).
• Writing:
1 detection is performed for the written value.
• Reading:
Saved data of the internal state in the bit search module is read. This register is used to save/restore to
the original state when the bit search module is used by, for example, an interrupt handler.
Even though data is written to the 0 detection, change point detection, or data register, the data can be
saved/restored only by using the 1 detection data register.
The initial value after a reset is undefined.
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
■ Change Point Detection Data Register (BSDC)
Point of change is detected in the written value.
Shown below is the configuration of the change point detection data register (BSDC):
BSDC
Address
bit31
bit0
Initial value
XXXXXXXXH
0003F8H
W
W:
X:
Write only
Undefined
The initial value after a reset is undefined.
The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer (Do not use 8-bit or 16-bit length data transfer
instructions).
■ Detection Result Register (BSRR)
The result of 0 detection, 1 detection, or change point detection is read.
The data register that is written last determines which detection result will be read.
Register configuration of the detection result register (BSRR) is as follows:
BSRR
Address
bit31
bit0
0003FCH
Initial value
XXXXXXXXH
R
R:
X:
190
Read only
Undefined
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
8.2.3
Operations of Bit Search Module
This section explains the operations of the bit search module.
■ 0 Detection
The bit search module scans data written to the 0 detection data register from MSB to LSB and returns the
location where the first "0" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is described in Table 8.2-1.
If "0" is not found (in other words, if the value is FFFFFFFFH), 32 is returned as the search result.
[Execution Example]
Written data
Read value (decimal)
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
■ 1 Detection
The bit search module scans data written to the 1 detection data register from MSB to LSB and returns the
location where the first "1" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is described in Table 8.2-1.
If "1" is not found (in other words, if the value is 00000000H), 32 is returned as the search result.
[Execution Example]
Written data
CM71-10139-5E
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
■ Change Point Detection
The bit search module scans data written to the change point detection data register from bit30 to LSB for
comparison with the MSB value.
The first location where a value that is different from that of the MSB is detected is returned. The detection
result can be obtained by reading the detection result register.
The relationship between the detected location and the return value is described in Table 8.2-1.
If a change point is not detected, 32 is returned. In change point detection, 0 is never returned as a result.
[Execution Example]
Written data
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
Table 8.2-1 shows the bit locations and return values (decimal).
Table 8.2-1 Bit Locations and Return Values (Decimal)
Detected bit
location
Return
value
Detected bit
location
Return
value
Detected bit
location
Return
value
Detected bit
location
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Does not exist
32
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
MB91210 Series
■ Process of Save/Restore
If it is necessary to save and restore the internal state of the bit search module, such as when the bit search
module is used in an interrupt handler, use the following procedure:
1) Read the 1 detection data register and save its content (save).
2) Use the bit search module.
3) Write the data saved in 1) to the 1 detection data register (restore).
With the above operation, the value obtained when the detection result register is read the next time
corresponds to the value written to the bit search module before 1).
If the data register written to last is the 0 detection or change point detection register, the value is restored
correctly with the above procedure.
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CHAPTER 8 REALOS-RELATED HARDWARE
8.2 Bit Search Module
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CM71-10139-5E
CHAPTER 9
DMAC (DMA CONTROLLER)
This chapter explains the overview of DMAC,
configurations/functions of the register, and operations
of DMAC.
9.1 Overview of DMAC
9.2 Detail Explanation of Registers of DMAC
9.3 Operating Explanation of DMAC
9.4 Operation Flow of DMAC
9.5 Data Path of DMAC
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.1 Overview of DMAC
9.1
MB91210 Series
Overview of DMAC
This module is used to carry out the DMA (Direct Memory Access) transfer in the FR
family devices.
The DMA transfer controlled by this module enables various data to be transferred
quickly without using CPU, resulting into an improvement of the system performance.
■ Hardware Configuration of DMAC
This module is composed of the following items:
• Five independent DMA channels
• Five independent channels access control circuit
• 20-bit address register (reload selectable: ch.0 to ch.3)
• 24-bit address register (reload selectable: ch.4)
• 16-bit transfer count register (reload selectable: one for each channel)
• 4-bit block count register (one for each channel)
• Two-cycle transfer
■ Primary Functions of DMAC
The data transfer in this module has the following functions:
● Data can be transferred independently from multiple channels (five channels)
• Priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
• Priority can be rotated between ch.0 and ch.1
• DMAC activation source
- Internal peripheral request (interrupt request shared -- including external interrupt)
- Software request (register programming)
• Transfer mode
- Burst transfer/step transfer/block transfer
- Addressing mode: 20 bit (24 bit) address specification
(Increased/reduced/fixed: Range of change in address is ±1, 2, 4 fixed)
- Data type: byte/half word/word length
- Single shot/reload selectable
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.1 Overview of DMAC
MB91210 Series
■ Overview of the DMAC Register
Figure 9.1-1 shows the overview of the DMAC Register.
Figure 9.1-1 Overview of the DMAC Register
bit 31
DMAC-ch.0 Control/Status register A
DMACA0
00000200H
DMAC-ch.0 Control/Status register B
DMACB0
00000204H
DMAC-ch.1 Control/Status register A
DMACA1
00000208H
DMAC-ch.1 Control/Status register B
DMACB1
0000020CH
DMAC-ch.2 Control/Status register A
DMACA2
00000210H
DMAC-ch.2 Control/Status register B
DMACB2
00000214H
DMAC-ch.3 Control/Status register A
DMACA3
00000218H
DMAC-ch.3 Control/Status register B
DMACB3
0000021CH
DMAC-ch.4 Control/Status register A
DMACA4
00000220H
DMAC-ch.4 Control/Status register B
DMACB4
00000224H
Overall control register
DMACR
00000240H
DMAC-ch.0 Transfer source address register
DMASA0
00001000H
DMAC-ch.0 Transfer destination address register
DMADA0
00001004H
DMAC-ch.1 Transfer source address register
DMASA1
00001008H
DMAC-ch.1 Transfer source address register
DMADA1
0000100CH
DMAC-ch.2 Transfer source address register
DMASA2
00001010H
DMAC-ch.2 Transfer destination address register
DMADA2
00001014H
DMAC-ch.3 Transfer source address register
DMASA3
00001018H
DMAC-ch.3 Transfer destination address register
DMADA3
0000101CH
DMAC-ch.4 Transfer source address register
DMASA4
00001020H
DMAC-ch.4 Transfer destination address register
DMADA4
00001024H
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23
16
15
8
7
0
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.1 Overview of DMAC
MB91210 Series
■ Block Diagram of DMAC
Figure 9.1-2 shows the block diagram of DMAC.
DMA transfer request
to bus controller
Buffer
Selector
DTC 2 step register DTCR
DMA activation
source
selection circuit
& request
acceptance
control
Counter
Buffer
BLK register
Selector
To interrupt controller
IRQ[4:0]
Peripheral interrupt clear
MCLREQ
TYPE.MOD,WS
DMA control
DMASA 2 step register
SADM,SASZ[7:0] SADR
DMADA 2 step register
DADM,DASZ[7:0]
Write back
Selector
Counter buffer
Counter buffer
Address
Address counter
Access
198
ERIR,EDIR
Selector
Read/write
control
State
transition
circuit
Bus control part
To bus
controller
DSS[2:0]
Priority circuit
Bus control part
Read
Write
Peripheral activation request/stop input
X-bus
Counter
Write back
Figure 9.1-2 Block Diagram of DMAC
DADR
Write back
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
9.2
Detail Explanation of Registers of DMAC
This section explains the details about each of the DMAC registers.
■ Notes on Setting Register
If setting this DMAC, there is a bit that needs to be executed when DMA is stopped. If it is set during the
operation (transfer), this DMAC may not normally operate.
The * mark indicates the bit that effects the operation if set during the DMAC transfer. This bit should be
rewritten when the DMAC transfer is stopped (is not permitted to activate or halted).
If it is set when the DMA transfer is not permitted to activate (DMACR:DMAE=0 or DMACA:DENB=0),
the setting is enabled after the activation is permitted.
If it is set when the DMA transfer is halted (DMACR:DMAH[3:0] ≠ 0000B or DMACA:PAUS=1), the
setting is enabled after the halt is cancelled.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
9.2.1
MB91210 Series
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4
Control/Status Register A
DMACA0 to DMACA4 are the registers that control the operations of each of the DMAC
channels, and they exist independently for each of the channels.
■ Bit Function of DMACA0 to DMACA4
The bit functions for DMACA0 to DMACA4 are as follows:
Figure 9.2-1 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register A (DMACA0 to DMACA4)
DMACA
Address
bit31
bit30
bit29
000200H
000208H
000210H
000218H
000220H
bit28
bit27
bit26
bit25
bit24
DENB
PAUS
STRG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
00000000B
IS[4:0]
R
R
R
R
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
Initial value
00000000B
DTC[7:0]
R/W
Initial value
00000000B
DTC[15:8]
R/W
Initial value
00000000B
BLK[3:0]
Reserved Reserved Reserved Reserved
Initial value
R/W
R/W
R/W
R/W: Readable/writable
R:
Read only
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit31] DENB (Dma ENaBle): DMA Operation Enable Bit
Corresponds to each of the transfer channels and enables/disables the DMA transfer activation.
The activated channel starts the DMA transfer when the transfer request occurs and are accepted. Any
transfer request, if requested on the channel that is disabled to activate, is invalid.
If the activated channel transfer is completed by specified counts, this bit turns to "0" and the transfer
stops.
Writing "0" to this bit forcibly stops the transfer. However, be sure to halt DMA in the PAUS bit
[DMACA bit30] before forcibly stopping the operation (write "0"). If it is stopped forcibly without
halting it, DMA is stopped but the transfer data is not guaranteed. Check if it is stopped with the DSS2
to DSS0 bit (the DMACB bit18 to bit16)
DENB
Function
0
Corresponding channel DMA operation disabled [Initial value]
1
Corresponding channel DMA operation enabled
• Initialized to "0" if the stop request is accepted when reset.
• Readable and writable.
If operations of all the channels are disabled with the bit15:DMAE bit, a bit in the DMAC full control
register DMACR, writing "1" to this bit is invalid and it remains the stop status. If the operation is
disabled with the bit15: DMAE of DMACR when the operation is enabled by this bit, this bit turns to
"0" and the transfer is stopped (forcibly stopped).
[bit30] PAUS (PAUSe): Instruction for Pause
Pauses the DMA transfer for the corresponding channel. If this bit is set, the DMA transfer is not
executed before this bit is cleared again (when DMA is paused, the DSS bit is 1XXB).
If this bit is set before activation, it keeps paused.
A transfer request that occurs when this bit is set can be accepted, but the transfer is not started unless
this bit is cleared (see "9.3.10 Acceptance and Transfer of Transfer Request").
PAUS
Function
0
Corresponding channel DMA operation enabled [Initial value]
1
Corresponding channel DMA paused
• Initialized to "0" when reset.
• Readable and writable.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit29] STRG (Software TRiGger): Transfer Request
Generates the DMA transfer request for the corresponding channel. If "1" is written to this bit, a transfer
request occurs when writing to the register is complete, starting the transfer to the corresponding
channel. However, if the corresponding channel is not activated, any operation to this bit is disabled.
Reference:
If the channel is activated by writing to the DMAE bit at the same time when a transfer request
occurs from this bit, the transfer request is enabled and the transfer is started. The transfer request
is enabled just when "1" is written to the PAUS bit, but the DMA transfer is not started until the PAUS
bit is returned to "0".
STRG
Function
0
Disabled [Initial value]
1
DMA activation request
• Initialized to "0" when reset.
• The read value is always "0".
• The write value only works on "1". "0" does not effect the operations.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer Source Selection
Select the transfer request source as follows. However, the software transfer request by the STRG bit
function is enabled regardless of this setting.
IS
Function
00000B
Hardware
00001B
↓
01111B
Setting prohibited
↓
Setting prohibited
10000B
UART0 (Reception complete)
10001B
UART1 (Reception complete)
10010B
UART2 (Reception complete)
10011B
UART0 (Transmission complete)
10100B
UART1 (Transmission complete)
10101B
UART2 (Transmission complete)
10110B
External interrupt 0
10111B
External interrupt 1
11000B
Reload timer 0
11001B
Reload timer 1
11010B
Reload timer 2
11011B
ICU 0
11100B
ICU 1
11101B
PPG 0
11110B
PPG 1
11111B
AD converter
• Initialized to 00000B when reset.
• Readable and writable.
If setting DMA activation with the interrupt of peripheral functions (IS=1XXXXB), the selected
function should disable the interrupt in the ICR register. When the software transfer request causes the
DMA transfer to be activated if the DMA activation with the interrupt of peripheral functions is set, the
source is cleared for the appropriate peripherals after the transfer is complete. Therefore, the original
transfer request can be cleared, so do not activate the transfer by the software transfer request if the
DMA transfer is set through the interrupt of peripheral functions.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit23 to bit20] (Reserved)*: Reserved Bits
The read value is fixed as 0000B. The write is disabled.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block Size Specification
Specifies the block size for the corresponding channel at the time of the block transfer. The value
specified in this bit is the number of words in a transfer unit at a time (in other words, the repeat count
of the data range setting).
Set 01H (size 1) if the block transfer is not to be performed.
BLK
XXXXB
Function
The block size specification for the corresponding channel
• Initialized to 0000B when reset.
• Readable and writable.
• If all the bits are set to "0", the block size is 16 words.
• When reading, the block size (reload value) is always read.
[bit15 to bit0] DTC15 to DTC0 (Dma Terminal Count register)*: Transfer count register
This is a register that stores the transfer counts. Each register has 16-bit length.
Every register has its reload register. If reloading of the transfer count register is used for the enabled
channel, the initial value is automatically returned to the register when the transfer is complete.
DTC
XXXXH
Function
The transfer counts specification for the corresponding channel
When the DMA transfer is activated, this register's data is stored in the counter buffer for the DMA
transfer counter and is counted by -1 (subtracted by 1) per transfer unit. DMA is finished by writing
back the content of the counter buffer to this register when the DMA transfer is finished. Therefore, you
cannot read the specified value of the transfer counts during the DMA operation.
• Initialized to 00000000_00000000B when reset.
• Readable and writable. Be sure to use the half word length or word length to access to DTC.
• The read value is the count value. The reload value cannot be read.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
9.2.2
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4
Control/Status Register B
DMACB0 to DMACB4 are the registers that control the operations of each DMAC
channel, and they exist independently for each of the channels.
■ Bit Function of DMACB0 to DMACB4
The bit functions for DMACB0 to DMACB4 are as follows:
Figure 9.2-2 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register B (DMACB0 to DMACB4)
DMACB
Address
000204H
00020CH
000214H
00021CH
000224H
bit31
bit30
TYPE[1:0]
bit29
bit28
bit27
MOD[1:0]
bit26
WS[1:0]
bit25
bit24
Initial value
SADM
DADM
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
DTCR
SADR
DADR
ERIE
EDIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
00000000B
DSS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
Initial value
00000000B
DASZ[7:0]
R/W
Initial value
00000000B
SASZ[7:0]
R/W
Initial value
R/W
R/W
R/W
R/W: Readable/writable
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer Type Setting
Select the operation type for the corresponding channel as follows:
Two-cycle transfer mode:
This is a mode in which the read and write operations are transferred repeatedly by the transfer counts
after setting the transfer source address (DMASA) and the transfer destination address (DMADA).
TYPE
Function
00B
Two-cycle transfer [Initial value]
01B
Setting prohibited
10B
Setting prohibited
11B
Setting prohibited
• Initialized to 00B when reset.
• Readable and writable.
• Be sure to set the value to 00B.
[bit29, bit28] MOD1, MOD0 (MODe)*: Transfer Mode Setting
Select the operation mode for the corresponding channel as follows:
MOD
Function
00B
Block/step transfer mode [Initial value]
01B
Burst transfer mode
10B
Setting prohibited
11B
Setting prohibited
• Initialized to 00B when reset.
• Readable and writable.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit27, bit26] WS (Word Size): Transfer Data Range Setting
Select the transfer data range for the corresponding channel. Transfer the data by the specified number
of times on a data-range basis specified in this register.
WS
Function
00B
Transfer on a byte basis [Initial value]
01B
Transfer on a half word basis
10B
Transfer on a word range basis
11B
Setting prohibited
• Initialized to 00B when reset.
• Readable and writable.
[bit25] SADM (Source-ADdr, count-Mode select)*:
Transfer Source Address Count Mode Specification
Specifies the processing of the source address per transfer for the corresponding channel.
Address is incremented/decremented after each transfer is complete based on the specified source
address count range (SASZ) and the next accessing address is written to the corresponding address
register (DMASA) when the transfer is complete.
Therefore, the transfer source address register is not updated until the DMA transfer is finished.
To fix the address, specify this bit to "0" or "1" and set the address count range (SASZ, DASZ) to "0".
SADM
Function
0
The transfer source address is incremented. [Initial value]
1
The transfer source address is decremented.
• Initialized to "0" when reset.
• Readable and writable.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit24] DADM (Destination-ADdr, Count-Mode select)*:
Transfer Destination Address Count Mode Specification
Specifies the processing of the destination address per transfer for the corresponding channel.
Address is incremented/decremented after each transfer is complete based on the specified destination
address count range (DASZ) and the next accessing address is written to the corresponding address
register (DMADA) when the transfer is complete.
Therefore, the transfer destination address register is not updated until the DMA transfer is finished.
To fix the address, specify this bit to "0" or "1" and set the address count range (SASZ, DASZ) to "0".
DADM
Function
0
The transfer destination address is incremented. [Initial value]
1
The transfer destination address is decremented.
• Initialized to "0" when reset.
• Readable and writable.
[bit23] DTCR (DTC-reg, Reload)*: Transfer Count Register Reload Specification
Controls the reload function of the transfer count register for the corresponding channel.
If the reload operation is enabled by this bit, the count register value is returned to the initial value and
stopped when the transfer is finished, resulting into a status where it is waiting for a transfer request
(activation request by the STRG or IS setting). (If this bit is "1", the DENB bit is not cleared.)
Setting DENB=0 or DMAE=0 forcibly stops the operation.
If the reload operation of the counter is disabled, specifying the reload in the address register makes the
operation single shot which would be stopped when the transfer is finished. In this case, the DENB bit
is cleared.
DTCR
Function
0
Disable the reload of the transfer count register [Initial value]
1
Enable the reload of the transfer count register
• Initialized to "0" when reset.
• Readable and writable.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit22] SADR (Source-ADdr.-reg, Reload)*: Transfer Source Address Register Reload
Specification
Controls the reload function of the transfer source address register for the corresponding channel.
If the reload operation is enabled by this bit, the transfer source address register value is returned to the
initial value when the transfer is finished.
If the reload operation of the counter is disabled, specifying the reload in the address register makes the
operation single shot which would be stopped when the transfer is finished. In this case, the address
register value is stopped with the initial setting value having been reloaded.
If the reload operation is disabled by this bit when the transfer is finished, the address register value is
the next access address to the last address (or incremented address if the address increment is specified).
SADR
Function
0
Disable the reload of the transfer source address register [Initial value]
1
Enable the reload of the transfer source address register
• Initialized to "0" when reset.
• Readable and writable.
[bit21] DADR (Dest.-ADdr.-reg, Reload)*: Transfer Destination Address Register Reload
Specification
Controls the reload function of the transfer destination address register for the corresponding channel.
If the reload operation is enabled by this bit, the transfer destination address register value is returned to
the initial value when the transfer is finished.
Other details of the function are equivalent to the content of bit22:SADR.
DADR
Function
0
Disable the reload of the transfer destination address register [Initial value]
1
Enable the reload of the transfer destination address register
• Initialized to "0" when reset.
• Readable and writable.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit20] ERIE (ERror Interrupt Enable)*: Error Interrupt Output Enable
Controls the interrupt when finished due to an occurrence of error. The content of occurred error is
indicated in DSS2 to DSS0. Note that this interrupt occurs not because of every finish source, but
particular finish sources (see the explanation of the DSS2 to DSS0 bits).
ERIE
Function
0
Error Interrupt Request Output Disabled [Initial value]
1
Error Interrupt Request Output Enabled
• Initialized to "0" when reset.
• Readable and writable.
[bit19] EDIE (EnD Interrupt Enable)*: End Interrupt Output Enable
Controls the interrupt occurrence when normally finished.
EDIE
Function
0
End Interrupt Request Output Disabled [Initial value]
1
End Interrupt Request Output Enabled
• Initialized to "0" when reset.
• Readable and writable.
[bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer Stop Source Display
Displays a 3-bit code (end code) that indicates the source of the DMA transfer stop/finish for the
corresponding channel.
The contents of the end code are as follows:
DSS
000B
Function
Initial value
None
—
X01B
Interrupt occurred
None
X10B
Transfer stop request
Error
X11B
Normal termination
End
1XXB
Pausing DMA (DMAH, PAUS bit, interrupt, and so on)
None
The transfer stop request is set only if the request from peripheral circuit is used.
The "interrupt occurrence" column indicates the type of possible interrupt requests.
• Initialized to 000B when reset.
• Cleared by writing 000B.
• Readable and writable, but only 000B can be written to this bit.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*:
Transfer Source Address Account Size Specification
Specifies the increment/decrement range of the transfer source address (DMASA) per transfer for the
corresponding channel.
The value set to this bit is the address increment/decrement range per transfer. The address increment/
decrement range follows the instruction of the transfer source address count mode (SADM).
SASZ
Function
00H
Address fixed
01H
Transfer on a byte basis
02H
Transfer on a half word basis
04H
Transfer on a word basis
Others
Setting prohibited
• Initialized to 00000000B when reset.
• Readable and writable.
• If set to other than address fixed, set the same transfer unit as the transfer data range (WS).
[bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*:
Transfer Destination Address Count Size Specification
Specifies the increment/decrement range of the transfer destination address (DMADA) per transfer for
the corresponding channel. The value set to this bit is the address increment/decrement range per
transfer. The address increment/decrement range follows the instruction of the transfer destination
address count mode (DADM).
DASZ
Function
00H
Address fixed
01H
Transfer on a byte basis
02H
Transfer on a half word basis
04H
Transfer on a word basis
Others
Setting prohibited
• Initialized to 00000000B when reset.
• Readable and writable.
• If set to other than address fixed, set the same transfer unit as the transfer data range (WS).
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.2 Detail Explanation of Registers of DMAC
MB91210 Series
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/
Destination Address Setting Registers
9.2.3
DMASA0 to DMASA4/DMADA0 to DMADA4 are the registers that control the operations
of each DMAC channel, and they exist independently for each channel.
■ Bit Function of DMASA0 to DMASA4/DMADA0 to DMADA4
The bit functions for DMASA0 to DMASA4/DMADA0 to DMADA4 are as follows:
● DMASA
Figure 9.2-3 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source Address Setting Registers
(DMASA0 to DMASA4)
DMASA
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
001000H
001008H
001010H
001018H
001020H
-
-
-
-
-
-
-
-
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
00000000B
DMASA[23:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
Initial value
00000000B
DMASA[7:0]
R/W
Initial value
00000000B
DMASA[15:8]
R/W
Initial value
R/W
R/W
R/W
R/W: Readable/writable
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
● DMADA
Figure 9.2-4 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Destination Address Setting Registers
(DMADA0 to DMADA4)
DMADA
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
001004H
00100CH
001014H
00101CH
001024H
-
-
-
-
-
-
-
-
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
00000000B
DMADA[23:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
Initial value
00000000B
DMADA[7:0]
R/W
Initial value
00000000B
DMADA[15:8]
R/W
Initial value
R/W
R/W
R/W
R/W: Readable/writable
These are a set of registers that store the transfer source/destination addresses. ch.0 to ch.3 has 20-bit
length, ch.4 has 24-bit length.
[bit23 to bit0] DMASA23 to DMASA0 (DMA Source Addr)*: Transfer Source Address Setting
Sets the transfer source address.
[bit23 to bit0] DMADA23 to DMADA0 (DMA Destination Addr)*: Transfer Destination
Address Setting
Sets the transfer destination address.
When the DMA transfer is activated, this register's data is stored in the counter buffer for the DMA
address counter and is counted per transfer based on the setting. DMA is finished by writing back the
content of the counter buffer to this register when the DMA transfer is finished. Therefore, you cannot
read the address counter value during the DMA operation.
Every register has its reload register. If reloading of the transfer source/destination address register is
used for the enabled channel, the initial value is automatically returned to the register when the transfer
is complete. In this case, other address registers are not effected.
• Initialized to 000000H when reset.
• Readable and writable. With this register, be sure to use 32-bit data for access.
• The read value is an address value before transfer when the transfer is being executed, and the next
access address value when the transfer is finished. The reload value cannot be read. Therefore, the
transfer address cannot be read at real time.
• Set "0" to a nonexistent upper bit.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
Note:
Do not use this register to set the register of DMAC itself. The DMA transfer cannot be executed to
the register of DMAC itself.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
9.2.4
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4
DMAC Overall Control Register
DMACR is a register that controls the operation for the whole DMA5 channel. With this
register, be sure to use byte length for access.
■ Bit Function of DMACR
The bit functions for DMACR are as follows:
Figure 9.2-5 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC Overall Control Register (DMACR)
DMACR
Address
000240H
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
DMAH3 DMAH2 DMAH1 DMAH0
Initial value
0XX00000B
DMAE
-
-
PM01
R/W
R
R
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
XXXXXXXXB
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
R
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
-
-
XXXXXXXXB
R
R
R
R
R
R
R
R
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
-
-
XXXXXXXXB
R
R
R
R
R
R
R
R
R/W: Readable/writable
R:
Read only
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit31] DMAE (DMA Enable): DMA Operation Enable
Controls the operations of all the DMA channels.
If the DMA operation is disabled by this bit, the transfer operations of all the channels are disabled
regardless of the settings of activation/stop and operation status of the channels. The channel in the
process of transfer turns down the request and stops the transfer at the block boundary. Any activation
operation for each channel is invalid in the disabled state.
If the DMA operation is enabled by this bit, the activation/stop operation is valid for each channel. The
channels will not be activated by enabling the DMA operation with this bit.
Writing "0" to this bit forcibly stops the transfer. However, be sure to pause DMA in the DMAH3 to
DMAH0 bits (DMACR:bit27 to bit24) before forcibly stopping the operation (write "0"). If it is stopped
forcibly without halting it, DMA is stopped but the transfer data is not guaranteed. To check if it is
stopped, see the DSS2 to DSS0 bits (the DMACB bit18 to bit16).
DMAE
Function
0
All the channels' DMA operation disabled [Initial value]
1
All the channels' DMA operation enabled
• Initialized to "0" when reset.
• Readable and writable.
[bit28] PM01 (Priority Mode ch.0, ch.1 robin): Channel Priority Rotation
Set if the priority of ch.0. ch.1 should be rotated for each transfer.
PM01
Function
0
Priority fixed (ch.0 > ch.1) [Initial value]
1
Priority rotated (ch.1 > ch.0)
• Initialized to "0" when reset.
• Readable and writable.
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9.2 Detail Explanation of Registers of DMAC
MB91210 Series
[bit27 to bit24] DMAH3 to DMAH0 (DMA Halt): DMA Pause
Controls pausing of all the DMA channels. If these bits are set, all the channels' DMA transfers are not
executed before these bits are cleared again.
If these bits are set before activation, the channels keep paused.
When these bits are set, all the transfer requests that occur on the channel with the DMA transfer
enabled (DENB=1) are valid and the transfer is started by clearing these bits.
DMAH
0000B
Other than
0000B
Function
All the channels DMA operation enabled [Initial value]
All the channels' DMA halted
• Initialized to 0000B when reset.
• Readable and writable.
[bit30, bit29, bit23 to bit0] Reserved: Reserved Bits
The read value is undefined.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
9.3
MB91210 Series
Operating Explanation of DMAC
This section explains the overview of the operations, the details about transfer request
configurations and transfer sequence, and the detailed information during the
operations of DMAC.
■ Overview of DMAC
This block is a multifunction DMA controller built in the FR family that controls the quick data transfer
without receiving any instructions from CPU.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.1
Overview of Operations
This section explains the overview of the DMAC operations.
■ Primary Operations of DMAC
Each of the transfer channels independently sets the respective functions.
If the activation is enabled, the channels does not execute the transfer operation until the specified transfer
request is detected.
By detecting a transfer request, the DMA transfer request is output to the bus controller, and the bus
controller controls the operation to obtain the bus right and start the transfer. The transfer is performed
according to the sequence based on the mode setting specified independently for each channel.
■ Transfer Mode
Each of the DMA channels executes the transfer operation according to the transfer mode specified in the
MOD1, MOD0 bits in the respective DMACB registers.
● Block/Step Transfer
Transfers one block transfer unit for each transfer request. DMA stops the transfer request to the bus
controller until the next transfer request is accepted.
1 block transfer unit: Specified block size (DMACA:BLK3 to BLK0)
● Burst Transfer
Transfers repeatedly for a transfer request until the specified number of transfers is complete.
Specified number of transfers:
Block size × Number of transfers (DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0)
■ Transfer Type
● Two-cycle Transfer (Normal Transfer)
The DMA controller operates as a unit of the read and write operations.
The data is read from the address of the transfer source register, and written to the address of the transfer
destination register.
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9.3 Operating Explanation of DMAC
MB91210 Series
■ Transfer Address
This section explains about addressing. The address is set independently for each channel's transfer source/
destination.
● Specifying Address in Two-cycle Transfer
Access to the value as the address that is read from the register (DMASA, DMADA) in which the address
is set in advance.
After the transfer request is accepted, DMA starts the transfer after storing the address from the register to
the temporary storage buffer.
The address to be accessed next is generated (addition, subtraction, or fix can be selected) at the address
counter for each transfer (access) and returned to the temporary storage buffer. The content of this
temporary storage buffer is written back to the register (DMASA, DMADA) for each completion of a block
transfer unit.
Therefore, the address register (DMASA, DMADA) value is updated only on a block-transfer-unit basis,
and the address cannot be known at real time.
■ Transfer Count and Transfer Termination
● Transfer Count
The transfer count register is decremented (by -1) for each completion of a block transfer unit. If the
transfer count register is "0", then the specified number of transfers is finished, resulting into a stop or reactivation (1) after the end code is displayed.
The transfer count register value is updated only on a block-transfer unit basis, similarly to the address
register.
If the reload of the transfer count register is disabled, the transfer is terminated. If it is enabled, the register
value is initialized, resulting into a status where the transfer is waited (DMACB:DTCR).
● Transfer Termination
The sources of the transfer termination are as follows. When terminated, one of the source is displayed as a
end code (DMACB:DSS2 to DSS0).
• End of specified number of transfers (DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0) →
Normal Termination
• Occurrence of Transfer Stop Request from Peripheral Circuit → Error
• Occurrence of Address Error → Error
• Occurrence of Reset → Reset
The transfer stop source is displayed (DSS) for each of the termination sources, and the transfer termination
interrupt/error interrupt can be generated.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.2
Setting of Transfer Request
There are two types of the transfer request that activates the DMA transfer.
• Built-in peripheral request
• Software request
The software request can always be used regardless of other request settings.
■ Built-in Peripheral Request
Generates a transfer request due to an occurrence of the built-in peripheral circuit.
Set which of the peripheral interrupts generates a transfer request for each channel
(DMACA:IS4 to IS0=1XXXXB).
Note:
The interrupt request used for a transfer request can be seen as an interrupt request to CPU, so
disable the interruption for the interrupt controller setting (ICR register).
■ Software Request
Generates a transfer request by writing to the trigger bit in the register (DMACA:STRG).
It is independent of the transfer request shown above, and it can always be used.
If a software request is issued simultaneously with activation (enabling of transfer), the DMA transfer
request is immediately output to the bus controller to start the transfer.
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9.3 Operating Explanation of DMAC
9.3.3
MB91210 Series
Transfer Sequence
You can independently set the transfer type (DMACB:TYPE1,TYPE0) and transfer mode
(MOD1,MOD0) to determine the operation sequence after the DMA transfer is activated for
each channel.
■ Selecting the Transfer Sequence
The following sequence can be selected depending on the register setting:
• Burst two-cycle transfer
• Block/step two-cycle transfer
■ Burst Two-Cycle Transfer
Repeats the transfer for a transfer source at the specified number of transfers. For the two-cycle transfer, the
transfer source/destination address can be specified with 20-bit area (ch.0 to ch.3) or 24-bit area (ch.4).
The transfer source can select the peripheral transfer request/software transfer request.
Table 9.3-1 shows the possible transfer addresses for the burst two-cycle transfer:
Table 9.3-1 Possible Transfer Addresses for the Burst Two-Cycle Transfer
Transfer Source Address Specification
20 (24) bit whole area can be specified
Direction Transfer Destination Address Specification
→
20 (24) bit whole area can be specified
[Features of Burst Transfer]
• If one transfer request is accepted, the transfer is repeated until the transfer count register turns to "0".
Number of transfers is block size × number of transfers (DMACA:BLK3 to BLK0 × DMACA:DTC15
to DTC0).
• If another request occurs during the transfer, it is ignored.
• If the reload function of the transfer count register is enabled, the next transfer request is accepted after
the transfer is finished.
• If another channel's transfer request with a higher priority is accepted during the transfer, the channel is
switched at the end of the current block transfer unit, and it is not returned until the transfer request for
the channel is cleared.
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9.3 Operating Explanation of DMAC
MB91210 Series
■ Step/Block Two-Cycle Transfer
For the step/block transfer (in which the transfer is executed for each transfer request at the specified
number of blocks), the transfer source/destination address can be specified with 20-bit area (ch.0 to ch.3) or
24-bit area (ch.4).
Table 9.3-2 shows the available transfer addresses for the step/block two-cycle transfer:
Table 9.3-2 Possible Transfer Addresses for the Step/Block Two-Cycle Transfer
Transfer Source Address Specification
20 (24) bit whole area can be specified
Direction Transfer Destination Address Specification
→
20 (24) bit whole area can be specified
■ Step Transfer
If "1" is set to the block size, the sequence turns to the step transfer sequence.
[Features of Step Transfer]
• If a transfer request is accepted once, the transfer is executed once and stopped after the transfer request
is cleared (the DMA transfer request is turned down to the bus controller).
• If another request occurs during the transfer, it is ignored.
• If another channel's transfer request with a higher priority is accepted during the transfer, the channel is
switched after the transfer is stopped and the new transfer is started. Priority in the step transfer works
only if multiple transfer requests occur simultaneously.
■ Block Transfer
If other value than "1" is set to the block size, the sequence turns to the block transfer sequence.
[Features of Block Transfer]
The operation is the same except one transfer unit is composed of multiple numbers (blocks) of the
transfer cycle.
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9.3 Operating Explanation of DMAC
9.3.4
MB91210 Series
General DMA Transfer
This section explains the operations of DMA.
■ Block Size
One transfer unit of the transfer data is a collection of the data, number of which is specified in the block
size specification register (× the data range).
Since the data transferred in one transfer cycle is fixed to the value specified with the data range, a transfer
unit is composed of the number of the transfer cycles with the block size specified value.
If a transfer request with a higher priority is accepted during the transfer or if the transfer pause is
requested, even the block transfer is stopped only at the end of one transfer unit. This enables the data to be
protected for the data block that is not expected to be divided or paused, but the response can be
downgraded if the block size is large.
Though it is stopped immediately only when the reset occurs, the content of the data being transferred is
not secured.
■ Reload Operation
This module enables to set the three types of the reload function for each channel:
• Transfer Count Register Reload Function
After the specified number of transfers are finished, the initial value is reset in the transfer count register
to wait for acceptance of an activation.
Set it if the whole transfer sequence is repeated.
If the reload is not specified, the count register value remains "0" after the specified number of transfers
is complete, and the subsequent transfer is not performed.
• Reload Function of the Transfer Source Address Register
After the specified number of transfers are finished, the initial value is reset in the transfer source
address register.
Set if the transfer is repeated from the fixed area in the transfer source address area.
If the reload is not specified, the transfer source address register value is the next address after the
specified number of transfers are complete. It is used if the address area is not fixed.
• Reload Function of the Transfer Destination Address Register
After the specified number of transfers are finished, the initial value is reset in the transfer destination
address register.
Set if the transfer is repeated to the fixed area in the transfer destination address area.
If the reload is not specified, the transfer destination address register value is the next address after the
specified number of transfers is completed.
If the reload function of the transfer source/destination register is enabled only, the re-activation is not
performed after the specified number of the transfers are complete. Each of the address register values is
reset only.
[Special Case of Operation Mode and Reload Operation]
If the burst/block/step transfer mode is used for the transfer, the data is not transferred when the transfer
is complete, until the transfer is halted after reloaded and then a new transfer request input is detected.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.5
Addressing Mode
The transfer destination/source address is specified independently for each of the
transfer channel.
This section explains how to specify the address. The transfer sequence should be
used to set it.
■ Address Register Specification
For the two-cycle transfer mode, set the transfer source address in the transfer source address setting
register (DMASA) and the transfer destination address in the transfer destination address setting register
(DMADA).
[Features of Address Register]
Register with 20-bit (ch.0 to ch.3) or 24-bit (ch.4) length.
[Functions of Address Register]
• Read for each access and sent to the address bus.
• At the same time, the address for the next access is calculated with the address counter, and the
address register is updated with the address of the calculation result.
• The address calculation is selected from addition/subtraction independently for each channel/
destination/source. Increment/decrement range of the address depends on the value of the address
count size specification register (DMACB:SASZ, DASZ).
• If the reload function is disabled, the calculated address is left in the last address in the address
register after the transfer is complete. If the reload function is enabled, the initial value of the address
is reloaded.
Reference:
If overflow/underflow occurs in the wake of the calculation of the 20-bit or 24-bit length address, it is
detected as an address error, resulting into a halt of the transfer for the channel (see "the description
of the Transfer Stop Source Display bit (DMACB:DSS2 to DSS0)".
Notes:
• Do not set the address of the register of DMAC itself in the address register.
• Do not use DMAC to perform the transfer to the register of DMAC itself.
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9.3 Operating Explanation of DMAC
9.3.6
MB91210 Series
Data Type
The data length (data range) transferred in one transfer should be selected from one of
the followings:
• Byte
• Half word
• Word
■ Access Address
Because the word boundary specification is kept for the DMA transfer, the different lower bit is ignored if
the specified address does not match the data length in the transfer source/destination address specification.
• Word:
Actual access address is 4 byte in which the lower 2 bits starts with 00B.
• Half word:
Actual access address is 2 byte in which the lower 1 bit starts with "0".
• Byte:
Actual access address matches the address specification.
If the lower bit of the transfer source address does not match that of the transfer destination address, the
same address at the time of setting is output on the internal address bus, but the address is fixed on each of
the transfer targets on the bus, based on the rule described above.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.7
Transfer Count Control
The transfer count is specified within a range of 16-bit length (1 to 65536) at maximum.
The transfer count specification value is set in the transfer count register
(DMACA:DTC).
■ Transfer Count Register and Reload Operation
The register value is stored in the temporary storage buffer when the transfer is started, and decremented by
the transfer counter. When this counter value turns to "0", it is detected as completion of specified number
of the transfers, and the transfer for the channel is stopped or re-activation is waited (when the reload is
specified).
[Features of Transfer Count Registers]
• Each of the registers has 16-bit length.
• Every register has its reload register.
• If activated when the register value is "0", the transfer is repeated 65536 times.
[Reload Operation]
• Valid only if the reload function is enabled.
• The initial value of the count register is evacuated to the reload register when the transfer is
activated.
• If the count turns to "0" using the transfer counter, the transfer is notified as completed, and the
initial value is read from the reload register and written to the count register.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
9.3.8
MB91210 Series
CPU Control
If the DMA transfer request is accepted, DMA issues the transfer request to the bus
controller.
The bus controller passes the right to use the internal bus to DMA at the break of the
bus operation to start the DMA transfer.
■ DMA Transfer and Interrupt
If there occurs the NMI request or an interrupt request with a higher priority than the hold suppression level
specified in the interrupt controller's HRCL register when the DMA transfer is performed, DMAC
temporarily turns down the transfer request to the bus controller at the boundary of the transfer unit (1
block), and pauses the transfer until the interrupt request is cleared. The transfer request is internally kept
during this time. If the interrupt request is cleared, then DMAC issues the transfer request to the bus
controller to obtain the right to use the bus and resume the DMA transfer.
If the interrupt level is lower than a level specified in the HRCL register, the interrupt is not accepted until
the DMA transfer is complete. And if the DMA transfer request occurs when the interrupt with a lower
level than the value specified in HRCL is processed, the transfer request is accepted and the process of the
interrupt is paused until the transfer is complete.
By default, the level of the DMA transfer request is the lowest. This stops the transfer for all the interrupt
requests and processes the interrupt first.
■ DMA Suppression
If the interrupt source with a higher priority occurs during the DMA transfer, the FR family halts the DMA
and branches to the appropriate interrupt routine. This function is valid as long as the interrupt request
exists. However, the suppression function does not work if the interrupt source is cleared, resulting that the
DMA transfer resumes in the interrupt process routine.
Therefore, use the DMA suppression function, if you do not want the DMA transfer to be resumed in the
process routine of the interrupt source with a level which halts the DMA transfer.
The DMA suppression function is activated when other value than "0" is written to the DMAH3 to
DMAH0 bits in the DMA overall control register, and stopped when "0" is written.
This function is mainly used in the interrupt process routine. Before the interrupt source is cleared in the
interrupt process routine, the content of the DMA suppression register is incremented by 1. This prevents
the subsequent DMA transfer from being performed.
After the interrupt process is addressed, the content of the DMAH3 to DMAH0 bits are decremented by 1
before the return.
If there are multiple interrupts, the content of the DMAH3 to DMAH0 bits are not "0" yet, meaning that the
DMA transfer continues to be suppressed. If there are not multiple interrupts, the content of the DMAH3 to
DMAH0 bits are "0", meaning that the DMA transfer request is immediately enabled.
Notes:
• As number of the register's bits are 4 bits, this function cannot be used for multiple interrupts with
over 15 levels.
• The priority order of the DMA tasks should be placed at least 15-level higher than other interrupt
levels.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.9
Start of Operation
Starting the DMA transfer is controlled independently for each channel, but you must
enable all the channels' operations before that.
■ All the Channels' Operation Enabled
Before activating each of the DMAC channels, you must enable all the channels' operation using the DMA
operation enable bit (DMACR:DMAE) in advance.
If not enabled, any activation settings or occurred transfer requests are invalid.
■ Transfer Activation
Use the operation enable bit in the control register of each channel to activate the transfer operation. When
the transfer request is accepted for the activated channel, the DMA transfer operation is started in the
specified mode.
■ Activation from Pausing State
If each or all of the channels control is paused before the activation, the state remains after activating the
transfer operation. If a transfer request is issued at this time, the request is accepted and maintained.
The transfer is started at the time when the pausing is deactivated.
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9.3 Operating Explanation of DMAC
9.3.10
MB91210 Series
Acceptance and Transfer of Transfer Request
This section explains the acceptance and transfer of the transfer request.
■ Acceptance and Transfer of Transfer Request
When activated, the transfer request specified for each channel starts to be sampled.
If the peripheral interrupt activation is selected, the DMAC transfers are continued until the transfer request
is cleared. Once cleared, the transfer is stopped by the transfer unit (peripheral interrupt activation).
Because the peripheral interrupt is detected by level, the interrupt should be performed with the interrupt
cleared by DMA.
The transfer request is always accepted, even when other channel's request is accepted to perform the
transfer. The channel to transfer for each transfer unit is determined based on a judgment of the priority.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.11
Peripheral Interrupt Clear by DMA
This DMA has a function to clear the peripheral interrupt. This function works when the
peripheral interrupt is selected for the DMA activation source (when IS[4:0]=1XXXXB).
The peripheral interrupt is cleared only for the specified activation source. This means
the peripheral function specified only in IS4 to IS0 is cleared.
■ Timing of Occurrence for Interrupt Clear by DMA
The timing of occurrence depends on the transfer mode (see "9.4 Operation Flow of DMAC").
[Block/Step Transfer]
If the block transfer is selected, a signal occurs for clearing the peripheral interrupt by one block (step)
transfer.
[Burst Transfer]
If the burst transfer is selected, a signal occurs for clearing the peripheral interrupt after the assigned
transfers are complete.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
9.3.12
MB91210 Series
Pause
This section explains when the DMA transfer is paused.
■ Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the Channels Simultaneously)
If pause is set by the pause bit, the corresponding channel's transfer is stopped until the pause deactivation
is reset. Pause should be checked in the DSS bit.
If the pause is deactivated, the transfer is resumed.
■ NMI/Hold Suppression Level Interrupt Process
If there occurs an NMI request or an interrupt request with a higher level than the hold suppression level,
all the channels being transferred are paused at the boundary of the transfer unit, and the NMI/interrupt is
processed first after opening the bus right. The transfer request accepted during the processing of the NMI/
interrupt is maintained and waits for the NMI/interrupt process to be finished.
The channel in which the request is retained resumes the transfer after the NMI/interrupt process is
complete.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.13
Termination/Stop of Operation
Termination of the DMA transfer is controlled independently for each channel, but you
can disable all the channels' operations.
■ Transfer Termination
If the reload operation is invalid, the transfer is stopped when the transfer count register turns to "0". The
subsequent transfer requests become invalid after "normal termination" is displayed in the end code (the
DMACA: DENB bit is cleared).
If the reload operation is valid, the initial value is reloaded when the transfer count register turns to "0". A
transfer request is being waited after "normal termination" is displayed in the end code (the DMACA:
DENB bit is not cleared).
■ All the Channels' Operation Disabled
If the DMA operation enable bit DMAE disables all the channels' operations, all the DMAC operations are
stopped, including those of running channels. If all the channels' DMA operations are enabled again after
that, a transfer is not performed unless it is re-activated for each channel. In this case, interrupt does not
occur at all.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
9.3.14
MB91210 Series
Stop By Error
As some cases where the transfer is stopped due to other source than the normal
termination by completion of the specified number of transfers, there are stop and halt
by various errors.
■ Occurrence of Transfer Stop Request from Peripheral Circuit
Some peripheral circuits that output the transfer request can generate the transfer stop request when an error
(such as receive/send error around the communication system) is detected.
If this transfer stop request is received, DMAC stops the corresponding channel's transfer, displaying
"transfer stop request" in the end code.
■ Occurrence of Address Error
When an addressing is performed inappropriately in each addressing mode, it is detected as an address
error. "Inappropriate addressing" is, for example, "when 20 bit address is specified, overflow/underflow
occurs in the address counter".
If an address error is detected, the corresponding channel's transfer is stopped, displaying "occurrence of
address error" in the end code.
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9.3 Operating Explanation of DMAC
MB91210 Series
9.3.15
DMAC Interrupt Control
The DMAC interrupt control can output an interrupt for each DMAC channel,
independently of the peripheral interrupt, which becomes a transfer request.
■ Interrupt That can Output the DMAC Interrupt Control
• Transfer end interrupt: Occurs only for normal termination.
• Error Interrupt:
Transfer stop request from the peripheral circuit (Error due to peripheral)
Occurrence of address error (Error due to software)
These interrupts are all output according to the content of the end code.
The interrupt request can be cleared by writing 000B to DSS2 through DSS0 (end code) of DMACB.
The end code must be cleared by writing 000B for reactivation.
If the reload operation is valid, it is automatically reactivated, but the end code is not cleared in this case,
meaning that the data remains until a new end code is written when the transfer is finished.
There is only one type of the end source that can be displayed in the end code, so if the multiple sources
occur simultaneously, the result of the priority judgment is displayed. Interrupt that occurs in this case
follows the displayed end code.
The priority of the end code is shown in the following (from the top with the highest priority):
• Reset
• Clear by writing 000B
• Peripheral stop request
• Normal termination
• Stop upon detection of address error
• Channel selection and control
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
9.3.16
MB91210 Series
DMA transfer during the sleep mode
DMAC can operate during the sleep mode.
This section explains the DMA transfer during the sleep mode.
■ Notes on DMA Transfer During the Sleep Mode
If the operation during the sleep mode is expected, you should consider the following:
• As CPU is being stopped, the DMAC register cannot be rewritten. The setting should be finished before
entering the sleep mode.
• The sleep mode is deactivated by interrupt, and if interrupt around the DMAC activation source is
selected, the interrupt controller must be used to disable the interrupt.
Similarly, if the sleep mode is not expected to deactivate in the DMAC end interrupt, the interrupt should
be disabled.
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
MB91210 Series
9.3.17
Channel Selection and Control
You can set up to five channels simultaneously for the transfer channel.
Each channel can be set independently for each function.
■ Priority Among Channels
Only one channel is available for the DMA transfer, and the priority is set among the channels. The priority
setting has two modes; fix/rotation, and is selected for each channel group (described later).
● Fix Mode
Fixed from the smallest channel number.
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is accepted during the transfer, the transfer channel is switched to
the channel with the higher priority at the end of one transfer unit (number specified in the block size
specification register × data range).
After the higher priority transfers are finished, the original channel's transfer is resumed.
Figure 9.3-1 shows the DMA transfer in the fix mode.
Figure 9.3-1 DMA Transfer in Fix Mode
ch.0 Transfer request
ch.1 Transfer request
Bus operation
CPU
SA
DA
SA
ch.1
Transfer channel
DA
SA
ch.0
DA
SA
ch.0
DA
CPU
ch.1
ch.0 Transfer finished
ch.1 Transfer finished
● Rotation Mode (Between ch.0 and ch.1 only)
The priority level of the initial state is set the same as the fix mode after the operation is enabled, but the
priority of the channel changes by each transfer completion. Therefore, if the transfer request is output
simultaneously, the channels switches by each transfer unit.
This is a mode that is useful if the continuous/burst transfer is set.
Figure 9.3-2 shows the DMA transfer in the rotation mode.
Figure 9.3-2 DMA Transfer in Rotation Mode
ch.0 Transfer request
ch.1 Transfer request
Bus operation
Transfer channel
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.1
SA
DA
CPU
ch.0
ch.0 Transfer finished
ch.1 Transfer finished
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.3 Operating Explanation of DMAC
MB91210 Series
■ Channel Group
The priority is selected in the following unit.
Table 9.3-3 shows the settings of the DMA priority selection.
Table 9.3-3 Settings of DMA Priority Selection
238
Mode
Priority
Fix
ch.0 > ch.1
Rotation
ch.0 > ch.1
↑↓
ch.0 < ch.1
Remarks
The initial state is the upper side priority.
Upper side is reversed when the above setting is transferred.
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CM71-10139-5E
CHAPTER 9 DMAC (DMA CONTROLLER)
9.4 Operation Flow of DMAC
MB91210 Series
9.4
Operation Flow of DMAC
Figure 9.4-1 and Figure 9.4-2 show the operation flow of the DMA transfer.
■ Operation Flow of Block Transfer
Figure 9.4-1 Block Transfer
DMA stopped
DENB=>0
DENB=1
Reload enabled
Activation request
waiting
Activation request
Initialization
Load address, number of the
transfers, number of the blocks
Transfer source address access
Address operation
Transfer destination address access
Address operation
Block count -1
BLK=0
Transfer count -1
Write back address,
transfer count, number of
the blocks
DMA transfer finished
Only when the peripheral interrupt
activation source is selected
Clearing of
Interrupt
cleared
interrupt occurred
DTC=0
Occurrence of the DMA interrupt
Block Transfer
• Can be activated for every activation source (selected)
• Accessible to all the areas
• Configurable for the number of the blocks
• Cleared occurrence issued interrupts at the end of the block count
• The DMA interrupt is issued when the specified number of transfers is complete
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.4 Operation Flow of DMAC
MB91210 Series
■ Operation Flow of Burst Transfer
Figure 9.4-2 Burst Transfer
DMA stopped
DENB=>0
DENB=1
Reload enabled
Activation request
waiting
Initialization
Load address, number of the
transfers, number of the blocks
Transfer source address access
Address operation
Transfer destination address access
Address operation
Block count -1
BLK=0
Transfer count -1
DTC=0
Write back address,
transfer count, number of
the blocks
Interrupt
cleared
Only when the peripheral interrupt
activation source is selected
Clearing of interrupt occurred
DMA transfer finished
Occurrence of the DMA interrupt
Block Transfer
• Can be activated for every activation source (selected)
• Accessible to all the areas
• Configurable for the number of the blocks
• The DMA interrupt is issued when the specified number of transfers is complete
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.5 Data Path of DMAC
MB91210 Series
9.5
Data Path of DMAC
Indicates the operation of the data for each transfer.
■ Operation of Data in Two-cycle Transfer
Figure 9.5-1 and Figure 9.5-2 show the operation of the data in two-cycle transfer.
Figure 9.5-1 Built-in I/O Area → Built-in RAM Area Transfer
Built-in I/O Area => Built-in RAM Area Transfer
CPU
I-bus
X-bus
Bus
controller
D-bus
Data buffer
DMAC
Write cycle
I-bus
CPU
Read cycle
X-bus
Bus
controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
MB91210 series
DMAC
External bus I/F
MB91210 series
F-bus
RAM
I/O
I/O
Figure 9.5-2 Built-in RAM Area → Built-in I/O Area Transfer
Built-in RAM Area => Built-in I/O Area Transfer
X-bus
CPU
I-bus
Bus
controller
D-bus
Data buffer
DMAC
Write cycle
X-bus
I-bus
CPU
Read cycle
Bus
controller
D-bus
Data buffer
F-bus
RAM
CM71-10139-5E
I/O
FUJITSU MICROELECTRONICS LIMITED
External bus I/F
MB91210 series
DMAC
External bus I/F
MB91210 series
F-bus
RAM
I/O
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CHAPTER 9 DMAC (DMA CONTROLLER)
9.5 Data Path of DMAC
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MB91210 Series
CM71-10139-5E
CHAPTER 10
CAN CONTROLLER
This chapter describes the functions and operations of
the CAN controller.
10.1 Features of CAN
10.2 Block Diagram of CAN
10.3 Registers of CAN
10.4 Functions of CAN Resisters
10.5 Functions of CAN
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CHAPTER 10 CAN CONTROLLER
10.1 Features of CAN
10.1
MB91210 Series
Features of CAN
CAN complies with the CAN protocol ver2.0A/B that is the standard protocol for serial
communications. It is widely used in the industrial field such as the automobile and FA.
■ Features of CAN
CAN has the following features:
• Support of CAN protocol ver2.0A/B
• Support of up to 1Mbps of bit rate
• Individual identifier mask for each message object
• Support of the programmable FIFO mode
• Maskable interrupt
• Support of the programmable loop back mode for self-test operation
• Read and write to message buffer using interface register
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CHAPTER 10 CAN CONTROLLER
10.2 Block Diagram of CAN
MB91210 Series
10.2
Block Diagram of CAN
Figure 10.2-1 shows a block diagram of the CAN.
■ Block Diagram of CAN
Figure 10.2-1 Block Diagram of CAN
CAN_TX CAN_RX
C_CAN
Message RAM
Message handler
CAN controller
Register group
Interrupt
DataOUT
DataIN
Address[7:0]
Control
Reset
Clock
CPU interface
● CAN Controller
It controls serial registers for serial/parallel conversion used for transfer of CAN protocol and transmission/
reception message.
● Message RAM
It stores the message object.
● Register Group
It is all registers used in CAN.
● Message Handler
It controls message RAM and CAN controller.
● CPU Interface
It controls the interface in FR family internal bus.
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CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
10.3
MB91210 Series
Registers of CAN
CAN has the following resisters:
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing resister (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler extended register (BRPER)
• IFx command request resister (IFxCREQ)
• IFx command mask resister (IFxCMSK)
• IFx mask resister 1 and 2 (IFxMSK1, IFxMSK2)
• IFx arbitration 1 and 2 (IFxARB1, IFxARB2)
• IFx message control resister (IFxMCTR)
• IFx data resister A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• CAN transmission request resister 1 and 2 (TREQR1, TREQR2)
• CAN new data resister 1 and 2 (NEWDT1, NEWDT2)
• CAN interrupt pending resister 1 and 2 (INTPND1, INTPND2)
• CAN message valid resister 1 and 2(MSGVAL1, MSGVAL2)
• CAN clock prescaler resister (CANPRE)
The addresses represented by Base-addr in the register list starting on the following page are as follows.
CAN0 : 20000H
CAN1 : 20100H
CAN2 : 20200H
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CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
■ List of Overall Control Register
Table 10.3-1 List of Overall Control Register
Register
Address
Remarks
+0
+1
CAN control register (CTRLR)
Base-addr + 00H
bit15 to bit8
bit7 to bit0
+2
+3
CAN status register (STATR)
bit15 to bit8
CTRLR
Initial value
00000000B
STATR
00000001B
CAN error counter (ERRCNT)
Base-addr + 04H
Initial value
Initial value
CM71-10139-5E
CAN bit timing resister (BTR)
bit15 to bit8
bit7 to bit0
RP, REC[6:0]
TEC[7:0]
TSeg2[2:0],
TSeg1[3:0]
SJW[1:0],
BRP[5:0]
00000000B
00000000B
00100011B
00000001B
bit15 to bit8
bit7 to bit0
IntId15 to IntId8
IntId7 to IntId0
00000000B
00000000B
bit15 to bit8
bit7 to bit0
BRPE
Initial value
00000000B
bit7 to bit0
CAN prescaler extended register (BRPER)
Base-addr + 0CH
00000000B
bit15 to bit8
CAN interrupt register (INTR)
Base-addr + 08H
bit7 to bit0
00000000B
00000000B
CAN test register (TESTR)
bit15 to bit8
bit7 to bit0
TESTR
00000000B
r0000000B
The error counter is for
read-only.
The bit timing resister
becomes writable by CCE.
The interrupt register is
for read-only.
The test register becomes
available by TSET.
"r" of TESTR specifies the
value of CAN_RX pin.
Reserved bits
bit15 to bit8
bit7 to bit0
Reserved bit
Reserved bit
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
The prescaler extended
register becomes writable
by CCE.
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CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
■ List of Message Interface Register
Table 10.3-2 List of Message Interface Register (1 / 3)
Register
Address
Remarks
+0
+1
IF1 command request resister
(IF1CREQ)
Base-addr + 10H
Initial value
Base-addr + 14H
Initial value
bit15 to bit8
bit7 to bit0
BUSY
Mess.No.5 to
Mess.No.0
00000000B
00000001B
Initial value
IF1 command mask register (IF1CMSK)
bit15 to bit8
00000000B
Base-addr + 20H
Initial value
Base-addr + 24H
Initial value
248
00000000B
IF1 mask register 1 (IF1CMSK1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MXtd. MDir,
Msk28 to Msk24
Msk23 to Msk16
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
11111111B
11111111B
IF1 arbitration register 1 (IF1ARB1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MsgVal, Xtd, Dir,
ID28 to ID24
ID23 to ID16
ID15 to ID8
ID7 to ID0
00000000B
00000000B
00000000B
00000000B
bit15 to bit8
bit7 to bit0
IF1MCTR
Initial value
bit7 to bit0
IF1CMSK
IF1 message control register (IF1MCTR)
Base-addr + 1CH
+3
IF1 mask register 2 (IF1CMSK2)
IF1 arbitration register 2 (IF1ARB2)
Base-addr + 18H
+2
00000000B
00000000B
Reserved bits
bit15 to bit8
bit7 to bit0
Reserved bits
Reserved bits
00000000B
00000000B
IF1 data register A1 (IF1DTA1)
IF1 data register A2 (IF1DTA2)
bit7 to bit0
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[0]
Data[1]
Data[2]
Data[3]
00000000B
00000000B
00000000B
00000000B
IF1 data register B1 (IF1DTB1)
IF1 data register B2 (IF1DTB2)
bit7 to bit0
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[4]
Data[5]
Data[6]
Data[7]
00000000B
00000000B
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
Big Endian byte
Big Endian byte
CM71-10139-5E
CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
Table 10.3-2 List of Message Interface Register (2 / 3)
Register
Address
Remarks
+0
Base-addr + 30H
Initial value
+1
Initial value
IF1 data register A1 (IF1DTA1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[3]
Data[2]
Data[1]
Data[0]
00000000B
00000000B
00000000B
00000000B
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[7]
Data[6]
Data[5]
Data[4]
00000000B
00000000B
00000000B
00000000B
Initial value
Base-addr + 44H
Initial value
bit15 to bit8
bit7 to bit0
BUSY
Mess.No.5 to
Mess.No.0
00000000B
00000001B
Base-addr + 48H
Initial value
Base-addr + 4CH
CM71-10139-5E
bit7 to bit0
IF2CMSK
00000000B
00000000B
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MXtd. MDir,
Msk28 to Msk24
Msk23 to Msk16
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
11111111B
11111111B
IF2 arbitration register 1 (IF2ARB1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MsgVal, Xtd, Dir,
ID28 to ID24
ID23 to ID16
ID15 to ID8
ID7 to ID0
00000000B
00000000B
00000000B
00000000B
bit15 to bit8
bit7 to bit0
IF2MCTR
Initial value
bit15 to bit8
IF2 mask register 1 (IF2CMSK1)
IF2 message control register (IF2MCTR)
00000000B
00000000B
Little Endian byte
IF2 command mask register (IF2CMSK)
IF2 mask register 2 (IF2CMSK2)
IF2 arbitration register 2 (IF2ARB2)
Little Endian byte
IF1 data register B1 (IF1DTB1)
bit15 to bit8
IF2 command request resister
(IF2CREQ)
Base-addr + 40H
+3
IF1 data register A2 (IF1DTA2)
IF1 data register B2 (IF1DTB2)
Base-addr + 34H
+2
Reserved bit
bit15 to bit8
bit7 to bit0
Reserved bit
Reserved bit
00000000B
00000000B
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CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
Table 10.3-2 List of Message Interface Register (3 / 3)
Register
Address
Remarks
+0
Base-addr + 50H
Initial value
Base-addr + 54H
Initial value
Base-addr + 60H
Initial value
+1
Initial value
250
+3
IF2 data register A1 (IF2DTA1)
IF2 data register A2 (IF2DTA2)
bit7 to bit0
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[0]
Data[1]
Data[2]
Data[3]
00000000B
00000000B
00000000B
00000000B
IF2 data register B1 (IF2DTB1)
IF2 data register B2 (IF2DTB2)
bit7 to bit0
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[4]
Data[5]
Data[6]
Data[7]
00000000B
00000000B
00000000B
00000000B
IF2 data register A2 (IF2DTA2)
IF2 data register A1 (IF2DTA1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[3]
Data[2]
Data[1]
Data[0]
00000000B
00000000B
00000000B
00000000B
IF2 data register B2 (IF2DTB2)
Base-addr + 64H
+2
Big Endian byte
Big Endian byte
Little Endian byte
IF2 data register B1 (IF2DTB1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[7]
Data[6]
Data[5]
Data[4]
00000000B
00000000B
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
Little Endian byte
CM71-10139-5E
CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
■ List of Message Handler Register
Table 10.3-3 List of Message Handler Register
Register
Address
Remarks
+0
+1
CAN transmission request register 2
(TREQR2)
Base-addr + 80H
Initial value
Base-addr + 84H
Initial value
Base-addr + 94H
Initial value
Base-addr + A4H
bit15 to bit8
bit7 to bit0
TxRqst32 to
TxRqst25
TxRqst24 to
TxRqst17
TxRqst16 to
TxRqst9
TxRqst8 to
TxRqst1
00000000B
00000000B
00000000B
00000000B
Initial value
Base-addr + B4H
CM71-10139-5E
The transmission
request register is
for read-only.
Reserved area (it is used when the number of message buffers is more than 33)
CAN new data register 1 (NEWDT1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
NewDat32 to
NewData25
NewDat24 to
NewData17
NewData16 to
NewData9
NewData8 to
NewData1
00000000B
00000000B
00000000B
00000000B
The new data
register is for
read-only.
Reserved area (it is used when the number of message buffers is more than 33)
bit15 to bit8
bit7 to bit0
IntPnd32 to
IntPnd25
IntPnd24 to
IntPnd17
00000000B
00000000B
CAN interrupt pending register 1
(INTPND1)
The interrupt
pending register is
IntPnd16 to IntPnd9 IntPnd8 to IntPnd1 for read-only.
bit15 to bit8
bit7 to bit0
00000000B
00000000B
Reserved area (it is used when the number of message buffers is more than 33)
CAN message valid register 2
(MSGVAL2)
Base-addr +B0H
CAN transmission request register 1
(TREQR1)
bit7 to bit0
CAN interrupt pending register 2
(INTPND2)
Base-addr + A0H
+3
bit15 to bit8
CAN new data register 2 (NEWDT2)
Base-addr + 90H
+2
CAN message valid register 1
(MSGVAL1)
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MsgVal32 to
MsgVal25
MsgVal24 to
MsgVal17
MsgVal16 to
MsgVal9
MsgVal8 to
MsgVal1
00000000B
00000000B
00000000B
00000000B
The message valid
register is for readonly.
Reserved area (it is used when the number of message buffers is more than 33)
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CHAPTER 10 CAN CONTROLLER
10.3 Registers of CAN
MB91210 Series
■ Clock Prescaler Register
Table 10.3-4 Clock Prescaler Register
Register
Address
0001A8H
Initial value
252
Remarks
+0
+1
+2
+3
CAN prescaler
resister (CANPRE)
-
-
-
bit3 to bit0
-
-
-
CANPRE[3:0]
-
-
-
00000000B
-
-
-
FUJITSU MICROELECTRONICS LIMITED
CAN prescaler
CM71-10139-5E
CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4
Functions of CAN Resisters
256 bytes (64 words) of address space are allocated to CAN register. CPU is accessed
to message RAM through the message interface register.
This section lists the CAN registers and describes a detailed function of each register.
■ Registers of CAN
• Overall Control Register
- CAN control register (CTRLR)
- CAN status register (STATR)
- CAN error counter (ERRCNT)
- CAN bit timing resister (BTR)
- CAN interrupt register (INTR)
- CAN test register (TESTR)
- CAN prescaler extended register (BRPER)
• Message Interface Register
- IFx command request resister (IFxCREQ)
- IFx command mask resister (IFxCMSK)
- IFx mask resister 1 and 2 (IFxMSK1, IFxMSK2)
- IFx arbitration resister 1 and 2 (IFxARB1, IFxARB2)
- IFx message control resister (IFxMCTR)
- IFx data resister A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• Message Handler Register
- CAN transmission request resister 1 and 2 (TREQR1, TREQR2)
- CAN new data resister 1 and 2 (NEWDT1, NEWDT2)
- CAN interrupt pending resister 1 and 2 (INTPND1, INTPND2)
- CAN message valid resister 1 and 2(MSGVAL1, MSGVAL2)
• Prescaler Resister
CAN clock prescaler resister (CANPRE)
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
10.4.1
MB91210 Series
Overall Control Register
The overall control register controls the CAN protocol control and operating mode, and
provides status information.
■ Overall Control Register
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing resister (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler extended register (BRPER)
254
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4.1.1
CAN Control Register (CTRLR)
CAN control register (CTRLR) controls the operating mode of the CAN controller.
■ Register Configuration
Figure 10.4-1 CAN Control Register (CTRLR)
CAN control resister (CTRLR) upper byte
Address
Base+00H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
res
R
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
CAN control resister (CTRLR) lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
Base+01H
Test
R/W
CCE
R/W
DAR
R/W
res
R
EIE
R/W
SIE
R/W
IE
R/W
Init
R/W
00000001B
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit8] res: Reserved bits
00000000B is read from these bits.
Set to 00000000B for writing.
[bit7] Test: Test mode enable bit
Test
Function
0
Normal operations [Initial value]
1
Test mode
[bit6] CCE: Bit timing register write enable bit
CM71-10139-5E
CCE
Function
0
Disables writing to CAN bit timing register (BTR) and CAN prescaler extended register
(BRPER). [Initial value]
1
Enables writing to CAN bit timing register (BTR) and CAN prescaler extended register
(BRPER). When Init bit is "1", this bit is valid.
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[bit5] DAR: Automatic retransmission disable bit
DAR
Function
0
Enables automatic retransmission of messages on the arbitration lost or error detection.
[Initial value]
1
Disables automatic retransmission.
CAN controller performs automatic retransmission of the frame by the arbitration lost or error detection
in transferring shown in CAN specification (See ISO11898 and "6.3.3 Recovery Processing"). If
automatic retransmission is performed, reset DAR bit to "0". It is necessary to set DAR bit to "1" if you
make CAN operated in Time Triggered CAN environment (Refer to TTCAN and ISO11898-1).
In the mode where DAR bit is set to "1", there is a difference in operation between TxRqst bit and
NewDat bit in message object (see "10.4.3 Message Object" for the message object.):
• When frame transmission is started, TxRqst of message object is reset to "0", but NewDat bit
remains unchanged.
• When frame transmission terminates successfully, NewDat is reset to "0".
• If a transmission operates arbitration lost or error detection, NewDat remains unchanged. To restart
the transmission, it is necessary to set TxRqst to "1" by CPU.
[bit4] res: Reserved bits
"0" is read from this bit.
Set to "0" for writing.
[bit3] EIE: Error interrupt code enable bit
256
EIE
Function
0
A change in BOff or EWarn bit in the CAN status register (STATR) disables setting the
interrupt code to the CAN interrupt register (INTR). [Initial value]
1
A change in BOff or EWarn bit in the CAN status register (STATR) enables setting the
status interrupt code to the CAN interrupt register (INTR).
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[bit2] SIE: Status interrupt code enable bit
SIE
Function
0
A change in TxOk, RxOk or LEC bit in the CAN status register (STATR) disables
setting the interrupt code to the CAN interrupt register (INTR). [Initial value]
1
A change in TxOk, RxOk or LEC bit in the CAN status register (STATR) enables
setting the interrupt code to the CAN interrupt register (INTR).
The change of TxOk, RxOk and LEC bits generated by writing from CPU is not set in
CAN interrupt register (INTR).
[bit1] IE: Interrupt enable bit
IE
Function
0
Disables interrupt generation. [Initial value]
1
Enables interrupt generation.
[bit0] Init: Initialization bit
Init
Function
0
Enables the CAN controller operation.
1
Initialization [Initial value]
• The bus off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting/
releasing Init bit. If the device goes bus off, the CAN controller itself sets Init bit to "1", stopping all
bus operations. Once Init bit has been cleared to "0" from the bus off state, the bus operation is
stopped until the bus idle consecutively occurs 129 times (11 recessive bits generate once). At the
end of the bus off recovery sequence, the error counters will be reset.
• Set Init and CCE bits to "1" before writing to the CAN bit timing register (BTR).
• If you use the low-power consumption mode (stop mode and clock mode), write "1" to Init bit and
initialize the CAN controller before transmitting to the low-power consumption mode.
• When changing the division ratio of the clock supplied to CAN interface through the CAN prescaler
register (CANPRE), set Init bit to "1" before changing the CAN prescaler register.
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10.4 Functions of CAN Resisters
10.4.1.2
MB91210 Series
CAN Status Register (STATR)
CAN Status Register (STATR) displays the CAN status and the CAN bus state.
■ Register Configuration
Figure 10.4-2 CAN Status Register (STATR)
CAN status register (STATR) upper byte
Address
Base+02H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
res
R
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
Initial value
CAN status register (STATR) lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+03H
BOff
R
EWarn
R
EPass
R
RxOk
R/W
TxOk
R/W
R/W
LEC
R/W
R/W
00000000B
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit8] res: Reserved bits
"0" is read from these bits.
Set to "0" for writing.
[bit7] BOff: Bus Off bit
BOff
Function
0
CAN controller is not bus off state (bus active). [Initial value]
1
CAN controller is bus off state.
[bit6] EWarn: Warning bit
EWarn
258
Function
0
Both transmission and reception counters are less than 96. [Initial value]
1
Either transmission or reception counter is 96 or more.
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[bit5] EPass: Error passive bit
EPass
Function
0
Both transmission and reception counters are less than 128 (error active state).
[Initial value]
1
Reception counter sets RP bit to 1, and transmission counter is 128 or more (error
passive state).
[bit4] RxOk: Normal message reception bit
RxOk
Function
0
The message is not communicated successfully, or it is in the bus idle state.
[Initial value]
1
The message is communicated successfully.
[bit3] TxOk: Normal message transmission bit
TxOk
Function
0
The message is not transmitted successfully, or it is in the bus idle state. [Initial value]
1
The message is transmitted successfully.
Note:
RxOk and TxOk bits are reset only by CPU.
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[bit2 to bit0] LEC: Last error code bits
LEC
State
Function
000B
Normal
Indicates that transmission or reception is operated successfully. [Initial value]
001B
Stuff error
Indicates that consecutive 6-bit or more dominant or recessive is detected in the message.
010B
Form error
Indicates that a wrong fixed format part of a reception frame has been received.
011B
Ack error
Indicates that acknowledge from another node is not performed for the transmission message.
100B
Bit1 error
Indicates that in the transmission data of message other than arbitration field, dominant is
detected regardless of transmitting recessive.
101B
Bit0 error
Indicates that in the transmission data of message, recessive is detected regardless of
transmitting dominant.
This bit is set each time 11 recessive bits are detected during bus recovery. Reading this bit
can monitor the bus recovery sequence.
110B
CRC error
Indicates that the CRC data of the received message and the result of calculated CRC does not
match.
111B
Not detected
When the read value is 111B for LEC bit after writing 111B to the LEC bit by CPU, which
indicates that there was no transmission/ reception during the period (bus idle state).
LEC bit holds a code which indicates the type of the last error to occur on the CAN bus. This bit will be
set to 000B when a message has been transferred (reception/ transmission) without error. Set the
undetected code 111B by the CPU to check for updates of code.
- A status interrupt code (8000H) is set to the CAN interrupt register (INTR) when EIE bit is "1" if
BOff or EWarn bit is changed, or when SIE bit is "1" if RxOk, TxOk, or LEC bit is changed.
- Because RxOk and TxOk bits are updated by writing to CPU, RxOk and TxOk bits set by the CAN
controller are lost. If RxOk and TxOk bits are used, clear the bits within time of (45 × BT) after
setting RxOk or TxOk bit to "1". BT indicates 1 bit time.
- Do not write to the CAN status register (STATR) if an interrupt occurs due to change of LEC bit
when SIE bit is "1".
- A change of EPass bit or a write to RxOk, TxOk, or LEC bit by CPU will never generate a status
interrupt.
- EWarn bit is remained to set "1" even if BOff bit or EPass bit becomes "1".
- Reading this register will clear the status interrupt (8000H) in the CAN interrupt register (INTR).
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MB91210 Series
10.4.1.3
CAN Error Counter (ERRCNT)
CAN error counter (ERRCNT) shows the reception error passive display, the reception
error counter and transmission error counter.
■ Register Configuration
Figure 10.4-3 CAN Error Counter (ERRCNT)
CAN error counter (ERRCNT) upper byte
Address
Base+04H
bit15
bit14
bit13
bit12
RP
R
R
R
R
bit11
bit10
bit9
bit8
R
R
bit2
bit1
bit0
R
R
R
REC6 to REC0
R
R
Initial value
00000000B
CAN error counter (ERRCNT) lower byte
Address
bit7
bit6
bit5
R
R
R
Base+05H
R:
bit4
bit3
TEC7 to TEC0
R
R
Initial value
00000000B
Read only
■ Register Function
[bit15] RP: Reception error passive display
RP
Function
0
The reception error counter is not in the error passive state of the CAN specification.
[Initial value]
1
The reception error counter is in the error passive state of the CAN specification.
[bit14 to bit8] REC6 to REC0: Reception error counters
Reception error counter value, which range is 0 to 127.
[bit7 to bit0] TEC7 to TEC0: Transmission error counters
Transmission error counter value, which range is 0 to 255.
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10.4.1.4
MB91210 Series
CAN Bit Timing Resister (BTR)
CAN bit timing resister (BTR) sets the prescaler and bit timing.
■ Register Configuration
Figure 10.4-4 CAN Bit Timing Resister (BTR)
CAN bit timing resister (BTR) upper byte
Address
Base+06H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
res
R
R/W
TSeg2
R/W
R/W
R/W
TSeg1
R/W
R/W
R/W
bit2
bit1
bit0
R/W
R/W
R/W
Initial value
00100011B
CAN bit timing resister (BTR) lower byte
Address
bit7
bit6
bit5
bit4
bit3
R/W
R/W
R/W
R/W
SJW
Base+07H
R/W
BRP
Initial value
00000001B
R/W: Readable/Writable
R:
Read only
Set the CAN bit timing register (BTR) and CAN prescaler extended register (BRPER) while CCE and Init
bits in the CAN control register (CTRLR) are set to "1".
■ Register Function
[bit15] res: Reserved bit
"0" is read from this bit.
Set to "0" for writing.
[bit14 to bit12] TSeg2: Time segment 2 setting bits
Valid setting value is 0 to 7. The value of TSeg2+1 becomes time segment 2.
Time segment 2 is equivalent for the phase buffer segment (PHASE_SEG2) of CAN specification.
[bit11 to bit8] TSeg1: Time segment 1 setting bits
Valid setting value is 1 to 15. Setting "0" is disabled. The value of TSeg1+1 becomes time segment 1.
Time segment 1 is equivalent for the propagation segment (PROP_SEG) + phase buffer segment 1
(PHASE_SEG1) of CAN specification.
[bit7, bit6] SJW: Resynchronous jump width setting bits
Valid setting value is 0 to 3. The value of SJW+1 becomes the resynchronous jump width.
[bit5 to bit0] BRP: Baud rate prescaler setting bits
Valid setting value is 0 to 63. The value of BRP+1 becomes the baud rate prescaler.
The time quantum (tq) of CAN controller is determined by dividing the system clock (fsys).
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10.4 Functions of CAN Resisters
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10.4.1.5
CAN Interrupt Register (INTR)
CAN interrupt register (INTR) shows the message interrupt code and status interrupt
code.
■ Register Configuration
Figure 10.4-5 CAN Interrupt Register (INTR)
CAN interrupt register (INTR) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+08H
bit12
bit11
IntId15 to IntId8
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
Initial value
00000000B
CAN interrupt register (INTR) lower byte
Address
bit7
bit6
bit5
R
R
R
Base+09H
R:
bit4
bit3
IntId7 to IntId0
R
R
Initial value
00000000B
Read only
■ Register Function
IntId
Function
0000H
No interrupt
0001H to 0020H
The message interrupt code
(the source of the interrupt indicates the number of message object.)
0021H to 7FFFH
Unused
8000H
The status interrupt code
(interrupt by the change of the CAN status register)
8001H to FFFFH
Unused
If several interrupt codes are pending, the CAN interrupt register means the interrupt code with the highest
priority. Even if the interrupt code is set in the CAN interrupt register, when the interrupt code with the
highest priority is generated, the CAN interrupt register will be updated to the interrupt code with highest
priority.
The interrupt code with highest priority is in the order of the status interrupt code (8000H), the message
interrupt (0001H, 0002H, 0003H, ..., 0020H).
When IntId bit has a value other than 0000H and IE bit in the CAN control register is set to "1", the
interrupt signal to CPU becomes active. On the other hand, when the value of IntId becomes 0000H (the
source of interrupt is reset) or IE bit in the CAN control register is reset to "0", the interrupt signal gets
inactive.
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Clearing IntPnd bit of the corresponding message object (see "10.4.3 Message Object" for the message
object.) to "0" clears the message interrupt code.
Reading the CAN status register clears the status interrupt code.
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10.4.1.6
CAN Test Register (TESTR)
CAN test register (TESTR) sets the test mode and monitors RX pin. See "10.5.7 Test
Mode" for the operation.
■ Register Configuration
Figure 10.4-6 CAN Test Register (TESTR)
CAN test register (TESTR) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
res
R
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
Base+0AH
CAN test register (TESTR) lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
Base+0BH
Rx
R
Tx1
R/W
Tx0
R/W
LBack
R/W
Silent
R/W
Basic
R/W
res
R
res
R
r0000000B
R/W: Readable/Writable
R:
Read only
Initial value (r) for Rx in bit7 displays the level on CAN bus.
Set Test bit in the CAN control register to "1" before writing to the CAN test register. Test mode is enabled
when Test bit in the CAN control register is "1". The mode is changed from test mode to normal mode
when Test bit in the CAN control register is set to "0" during test mode.
■ Register Function
[bit15 to bit8] res: Reserved bits
00000000B is read from these bits.
Set to 00000000B for writing.
[bit7] Rx: RX pin monitoring bit
Rx
CM71-10139-5E
Function
0
Indicates that CAN bus is dominant.
1
Indicates that CAN bus is recessive.
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[bit6, bit5] Tx1, Tx0: TX pin control bits
Tx1,Tx0
Function
00B
Normal operations [Initial value]
01B
Sampling point is output to TX pin.
10B
Dominant is output to TX pin.
11B
Recessive is output to TX pin.
When Tx bit is set to a value other than 00B, the message cannot be transmitted.
[bit4] LBack: Loop back mode
LBack
Function
0
Disables the Loop back mode. [Initial value]
1
Enables the Loop back mode.
[bit3] Silent: Silent mode
Silent
Function
0
Disables the silent mode. [Initial value]
1
Enables the silent mode.
[bit2] Basic: Basic mode
Basic
Function
0
Disables the basic mode. [Initial value]
1
Enables the basic mode.
IF1 register and IF2 register are used as transmission message and reception message
respectively.
[bit1, bit0] res: Reserved bits
00B is read from these bits.
Set to 00B for writing.
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10.4.1.7
CAN Prescaler Extended Register (BRPER)
By combining with the prescaler set in the CAN bit timing, this CAN prescaler extended
register (BRPER) extends the prescaler used in the CAN controller.
■ Register Configuration
Figure 10.4-7 CAN Prescaler Extended Register (BRPER)
CAN prescaler extended register (BRPER) upper bit
Address
Base+0CH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
res
R
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
Initial value
CAN prescaler extended register (BRPER) lower bit
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+0DH
res
R
res
R
res
R
res
R
R/W
BRPE
R/W
R/W
R/W
00000000B
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit4] res: Reserved bits
00000000 0000B is read from these bits.
Set to 00000000 0000B for writing.
[bit3 to bit0] BRPE: Baud rate prescaler extended bits
By combining BRP bit in the CAN bit timing register with BRPE, the baud rate prescaler can be
extended up to 1023.
{BRPE (MSB: 4bit), BRP (LSB: 6bit)} + 1 becomes the value of the prescaler in the CAN controller.
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10.4.2
MB91210 Series
Message Interface Register
Two sets of message interface registers are provided to control the access from CPU to
the message RAM.
There are two sets of message interface registers for the use of controlling the CPU access to the message
RAM. The message interface registers avoid conflict between CPU access to the message RAM and access
from the CAN controller by buffering the data to be transferred (message object). A message object (see
"10.4.3 Message Object" for the message object) may be transferred between the message interface
register and the message RAM in one single transfer.
The functions of two sets of message interface registers are identical (except for the test basic mode) and
can operate independently. For example, they can be used the way that the message interface register of IF2
is used to read from message RAM while the message interface register of IF1 is used to write to message
RAM. Table 10.4-1 gives an overview for two sets of message interface registers.
Each message interface register consists of the command registers (command request and command mask
register) and message buffer registers controlled by those command registers (mask, arbitration, message
control and data register). The command mask register specifies the direction of the data transfer and which
parts of a message object will be transferred. The command request register is used to select a message
number and perform the operations set in the command mask register.
Table 10.4-1 IF1 and IF2 Message Interface Registers
Address
268
IF1 register set
Address
IF2 register set
Base-addr + 10H
IF1 command request
Base-addr + 40H
IF2 command request
Base-addr + 12H
IF1 command mask
Base-addr + 42H
IF2 command mask
Base-addr + 14H
IF1 mask 2
Base-addr + 44H
IF2 mask 2
Base-addr + 16H
IF1 mask 1
Base-addr + 46H
IF2 mask 1
Base-addr + 18H
IF1 arbitration 2
Base-addr + 48H
IF2 arbitration 2
Base-addr + 1AH
IF1 arbitration 1
Base-addr + 4AH
IF2 arbitration 1
Base-addr + 1CH
IF1 message control
Base-addr + 4CH
IF2 message control
Base-addr + 20H
IF1 data A1
Base-addr + 50H
IF2 data A1
Base-addr + 22H
IF1 data A2
Base-addr + 52H
IF2 data A2
Base-addr + 24H
IF1 data B1
Base-addr + 54H
IF2 data B1
Base-addr + 26H
IF1 data B2
Base-addr + 56H
IF2 data B2
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10.4 Functions of CAN Resisters
MB91210 Series
10.4.2.1
IFx Command Request Resister (IFxCREQ)
IFx command request resister (IFxCREQ) selects the message number of message RAM
and transfers between the message RAM and the message buffer registers. In the test
basic mode, IF1 and IF2 are used for transmission control and reception control
respectively.
■ Register Configuration
Figure 10.4-8 IFx Command Request Resister (IFxCREQ)
IFx command request resister (IFxCREQ) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
Base+10H,
Base+40H
BUSY
R/W
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
bit3
bit2
bit1
bit0
Initial value
R/W
R/W
IFx command request resister (IFxCREQ) lower byte
Address
bit7
bit6
bit5
bit4
Base+11H,
Base+41H
res
R/W
res
R/W
R/W
R/W
Message Number
R/W
R/W
00000001B
R/W: Readable/Writable
R:
Read only
■ Register Function
A message transfer between the message RAM and message buffer register (mask, arbitration, message
control and data register) is started as soon as the CPU has written the message number to the IFx
command request register. With this write operation, BUSY bit is set to "1" to notify the CPU that a
transfer is in progress. BUSY bit is reset to "0" when the transfer has finished.
When BUSY bit is "1" if access from CPU to the message interface register occurs, CPU is forced to wait
until BUSY bit becomes "0" (period of 3 to 6 clock cycles after writing to the command request register).
In the test basic mode, BUSY bit is used in different way: IF1 command request register is used as the
transmission message and indicates the start of the message transmission by setting BUSY bit to "1". When
the transmission is completed successfully, BUSY bit is reset to "0". Also, resetting BUSY bit to "0"
enables to suspend the message transfer at anytime.
IF2 command request register is used as the reception message and stores the received message into IF2
message interface register by setting BUSY bit to "1".
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[bit15] BUSY: BUSY flag bit
• Mode other than the test basic mode
BUSY
Function
0
Indicates that the data transfer is not in progress between the message interface register
and message RAM. [Initial value]
1
Indicates that the data transfer is in progress between the message interface register and
message RAM.
• Test basic mode
- IF1 command request resister (IF1CREQ)
BUSY
Function
0
Disables message transmission.
1
Enables message transmission.
- IF2 command request resister (IF2CREQ)
BUSY
Function
0
Disables message reception.
1
Enables message reception.
BUSY bit is readable and writable. Writing any value to this bit has no effect on operation in the mode
other than the test basic mode (see "10.5.7 Test Mode" for the basic mode).
[bit14 to bit6] res: Reserved bits
000000000B is read from these bits.
Set to 000000000B for writing.
[bit5 to bit0] Message Number: Message number (for 32-message buffer CAN)
Message Number
00H
270
Function
Setting is disabled.
If setting, it is regarded as 20H, and 20H will be read.
01H to 20H
Sets the message number for processing.
21H to 3FH
Setting is disabled.
If setting, it is regarded as 01H to 1FH, and these values will be read.
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10.4 Functions of CAN Resisters
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[bit7 to bit0] Message Number: Message number (for 128-message buffer CAN)
Message Number
00H
CM71-10139-5E
Function
Setting is disabled.
If setting, it is regarded as 20H, and 20H will be read.
01H to 80H
Sets the message number for processing.
81H to FFH
Setting is disabled.
If setting, it is regarded as 01H to 7FH, and these values will be read.
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IFx Command Mask Resister (IFxCMSK)
10.4.2.2
IFx command mask resister (IFxCMSK) controls the transfer direction between the
message interface register and message RAM, and selects which data should be
renewed. Also, this register will be invalid in the test basic mode.
■ Register Configuration
Figure 10.4-9 IFx Command Mask Resister (IFxCMSK)
IFx command mask resister (IFxCMSK) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
res
R
res
R
res
R
res
R
res
R
res
R
res
R
res
R
00000000B
bit3
bit2
bit1
bit0
Initial value
Data A
Data B
00000000B
R/W
R/W
Base+12H,
Base+42H
IFx command mask resister (IFxCMSK) lower byte
Address
bit7
Base+13H,
Base+43H
bit6
bit5
bit4
WR/RD
Mask
Arb
Control
CIP
TxRqst/
NewDat
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
R:
Read only
This register setting will be invalid in the test basic mode.
■ Register Function
[bit15 to bit8] res: Reserved bits
00000000B is read from these bits.
Set to 00000000B for writing.
[bit7] WR/RD: Write/Read control bit
WR/RD
Function
0
Indicates that data is read from message RAM. Reading from message RAM is executed
by writing to IFx command request register. Data read from message RAM depends on
the setting of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A and Data B bits.
[Initial value]
1
Indicates that data is written to message RAM. Writing to message RAM is executed by
writing to IFx command request register. Data written to message RAM depends on the
setting of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A and Data B bits.
The data of message RAM is undefined after reset. Reading the data from message RAM is disabled
with the data of message RAM undefined.
Bit6 to bit0 in the IFx command mask register has the different meaning depending on the setting of
transfer direction (WR/RD bit).
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● When the transfer direction is write (WR/RD=1)
[bit6] Mask: Mask data renewal bit
Mask
Function
0
The mask data of message object (ID mask + MDir + MXtd) is not renewed.
[Initial value]
1
The mask data of message object (ID mask + MDir + MXtd) is renewed.
[bit5] Arb: Arbitration data renewal bit
Arb
Function
0
The arbitration data of message object (ID + Dir + Xtd + MsgVal) is not renewed.
[Initial value]
1
The arbitration data of message object (ID + Dir + Xtd + MsgVal) is renewed.
[bit4] Control: Control data renewal bit
Control
Function
0
The control data of message object (IFx message control register) is not renewed.
[Initial value]
1
The control data of message object (IFx message control register) is renewed.
[bit3] CIP: Interrupt clear bit
The operation to CAN controller is not affected even if setting "0" or "1" to this bit.
[bit2] TxRqst/NewDat: Message Transmission request bit
TxRqst/NewDat
Function
0
The message object and TxRqst bit in the CAN transmission request register
are not renewed. [Initial value]
1
"1" is set to the message object and TxRqst bit in the CAN transmission request
register (transmission request).
If TxRqst/NewDat bit in the IFx command mask register is set to "1", the setting of TxRqst bit in the
IFx message control register will be invalid.
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[bit1] Data A: Data 0 to 3 renewal bit
Data A
Function
0
The data 0 to 3 of message object is not renewed. [Initial value]
1
The data 0 to 3 of message object is renewed.
[bit0] Data B: Data 4 to 7 renewal bit
Data B
Function
0
The data 4 to 7 of message object is not renewed. [Initial value]
1
The data 4 to 7 of message object is renewed.
● When the transfer direction is read (WR/RD=0)
IntPnd and NewDat bits can be reset to "0" by the read access to a message object. However, IntPnd and
NewDat bits that have not been reset by the read access yet are stored in IntPnd and NewDat bits in the IFx
message control register.
This register will be invalid in the test basic mode.
[bit6] Mask: Mask data renewal bit
Mask
Function
0
The data (ID mask + MDir + MXtd) is not transferred from the message object to IFx
mask registers 1 and 2. [Initial value]
1
The data (ID mask + MDir + MXtd) is transferred from the message object to IFx mask
registers 1 and 2.
[bit5] Arb: Arbitration data renewal bit
274
Arb
Function
0
The data (ID + Dir + Xtd + MsgVal) is not transferred from the message object to IFx
arbitration 1 and 2. [Initial value]
1
The data (ID + Dir + Xtd + MsgVal) is transferred from the message object to IFx
arbitration 1 and 2.
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[bit4] Control: Control data renewal bit
Control
Function
0
The data is not transferred from the message object to IFx message control register.
[Initial value]
1
The data is transferred from the message object to IFx message control register.
[bit3] CIP: Interrupt clear bit
CIP
Function
0
Message object and IntPnd bit in the CAN interrupt pending register are retained.
[Initial value]
1
Message object and IntPnd bit in the CAN interrupt pending register are cleared to "0".
[bit2] TxRqst/NewDat: Data renewal bit
TxRqst/NewDat
Function
0
Message object and NewDat bit in the CAN data renewal register are retained.
[Initial value]
1
Message object and NewDat bit in the CAN data renewal register are cleared to
"0".
[bit1] Data A: Data 0 to 3 renewal bit
Data A
Function
0
Message object and the data of the CAN data registers A1 and A2 are retained.
[Initial value]
1
Message object and the data of the CAN data registers A1 and A2 are renewed.
[bit0] Data B: Data 4 to 7 renewal bit
Data B
CM71-10139-5E
Function
0
Message object and the data of the CAN data registers B1 and B2 are retained.
[Initial value]
1
Message object and the data of the CAN data registers B1 and B2 are renewed.
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IFx Mask Resister 1 and 2 (IFxMSK1, IFxMSK2)
10.4.2.3
IFx mask resister 1 and 2 (IFxMSK1, IFxMSK2) are used for writing/ reading the message
object mask data of message RAM. Also, the mask data setting is invalid in the test
basic mode.
See "10.4.3 Message Object" for the function of each bit.
■ Register Configuration
Figure 10.4-10 IFx Mask Resister 1 and 2 (IFxMSK1, IFxMSK2)
IFx mask resister 2 (IFxMSK2) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Base+14H
Base+44H
MXtd
R/W
MDir
R/W
res
R
R/W
Msk28 to Msk24
R/W
R/W
R/W
R/W
bit4
bit3
Initial value
11111111B
IFx mask resister 2 (IFxMSK2) lower byte
Address
bit7
bit6
bit5
Base+15H
Base+45H
R/W
R/W
R/W
Msk23 to Msk16
R/W
R/W
bit2
bit1
bit0
R/W
R/W
R/W
Initial value
11111111B
IFx mask resister 1 (IFxMSK1) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Base+16H
Base+46H
R/W
R/W
R/W
Msk15 to Msk8
R/W
R/W
R/W
R/W
R/W
bit2
bit1
bit0
Initial value
11111111B
IFx mask resister 1 (IFxMSK1) lower byte
Address
bit7
Base+17H
Base+47H
R/W
bit6
R/W
bit5
bit4
R/W
Msk7 to Msk0
R/W
R/W
bit3
Initial value
11111111B
R/W
R/W
R/W
R/W: Readable/Writable
R:
Read only
See "10.4.3 Message Object" for the bit explanation of these registers.
"1" is read from the reserved bit in these registers (bit13 in the IFx mask register 2). Write "1" for writing.
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10.4.2.4
IFx Arbitration Resister 1 and 2 (IFxARB1, IFxARB2)
IFx arbitration resister 1 and 2 (IFxARB1, IFxARB2) are used for writing/ reading the
message object arbitration data of message RAM. Also, these resisters are invalid in the
test basic mode.
See "10.4.3 Message Object" for the function of each bit.
■ Register Configuration
Figure 10.4-11 IFx Arbitration Resister 1 and 2 (IFxARB1, IFxARB2)
IFx arbitration resister 2 (IFxARB2) upper byte
Address
Base+18H
Base+48H
bit15
bit14
bit13
bit12
bit11
MsgVal
R/W
Xtd
R/W
Dir
R/W
R/W
R/W
bit10
bit9
bit8
ID28 to ID24
R/W
R/W
R/W
Initial value
00000000B
IFx arbitration resister 2 (IFxARB2) lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+19H
Base+49H
R/W
R/W
R/W
ID23 to ID16
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
IFx arbitration resister 1 (IFxARB1) upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Base+1AH
Base+4AH
R/W
R/W
R/W
ID15 to ID8
R/W
R/W
R/W
R/W
R/W
bit2
bit1
bit0
Initial value
00000000B
IFx arbitration resister 1 (IFxARB1) lower byte
Address
bit7
Base+1BH
Base+4BH
R/W
bit6
R/W
bit5
bit4
R/W
ID7 to ID0
R/W
R/W
bit3
Initial value
00000000B
R/W
R/W
R/W
R/W: Readable/Writable
See "10.4.3 Message Object" for the bit explanation of these registers.
When MsgVal bit in the message object is cleared to "0" during the transmission, TxOk bit in the CAN
status register is set to "1" after the transmission is completed. However, because the message object and
TxRqst bit in the CAN transmission request register are not cleared to "0", clear TxRqst bit to "0" using the
message interface register.
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IFx Message Control Resister (IFxMCTR)
10.4.2.5
IFx message control resister (IFxMCTR) is used for read/write the message object
control data of message RAM. Also, IF1 message control register is invalid in the test
basic mode. NewDat and MsgLst bits in the IF2 message control register operates
normally, and DLC bit displays DLC of the received message. The other control bits
operate as invalid ("0").
See "10.4.3 Message Object" for the function of each bit.
■ Register Configuration
Figure 10.4-12 IFx Message Control Resister (IFxMCTR)
IFx message control resister (IFxMCTR) upper byte
Address
Base+1CH
Base+4CH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
NewDat
R/W
MsgLst
R/W
IntPnd
R/W
UMask
R/W
TxIE
R/W
RxIE
R/W
RmtEn
R/W
TxRqst
R/W
00000000B
Initial value
IFx message control resister (IFxMCTR) lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+1DH
Base+4DH
EoB
R/W
res
R
res
R
res
R
R/W
DLC3 to DLC0
R/W
R/W
R/W
00000000B
R/W: Readable/Writable
R:
Read only
See "10.4.3 Message Object" for the bit explanation of the IFx message control resister (IFxMCTR).
Depending on the setting of WR/RD bit in the IFx command mask register, TxRqst, NewDat and IntPnd
bits operate as follows:
● When the transfer direction is write (IFx command mask register: WR/RD=1)
Only when TxRqst/NewDat bit in the IFx command mask register is set to "0", TxRqst bit in this register is
valid.
● When the transfer direction is read (IFx command mask register: WR/RD=0)
When CIP bit in the IFx command mask register is set to "1" and the message object and IntPnd bit in the
CAN interrupt pending register are reset by writing to the IFx command request register, IntPnd bit that has
not been reset is stored in this register.
When TxRqst/NewDat bit in the IFx command mask register is set to "1" and the message object and
NewDat bit in the CAN data renewal register are reset by writing to the IFx command request register,
NewDat bit that has not been reset is stored in this register.
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10.4.2.6
IFx Data Resister A1, A2, B1 and B2
(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
IFx data resister A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) are used for
reading/writing the message object transmission/ reception data of message RAM.
These resisters are used for only transmission/ reception of data frame, not for
transmission/reception of remote frame.
■ Register Configuration
addr+0
addr+1
addr+2
addr+3
IFx message data A1 (addresses 20H, 50H)
Data(0)
Data(1)
-
-
IFx message data A2 (addresses 22H, 52H)
-
-
Data(2)
Data(3)
IFx message data B1 (addresses 24H, 54H)
Data(4)
Data(5)
-
-
IFx message data B2 (addresses 26H, 56H)
-
-
Data(6)
Data(7)
IFx message data A2 (addresses 30H, 60H)
Data(3)
Data(2)
-
-
IFx message data A1 (addresses 32H, 62H)
-
-
Data(1)
Data(0)
IFx message data B2 (addresses 34H, 64H)
Data(7)
Data(6)
-
-
IFx message data B1 (addresses 36H, 66H)
-
-
Data(5)
Data(4)
Figure 10.4-13 IFx Data Resister A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
IFxDTA1, IFxDTA2 IFxDTB1, IFxDTB2
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
Data
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W
R/W
R/W
R/W: Readable/Writable
■ Register Function
● Setting of the transmission message data
The setting data is transmitted in order of MSB (bit7 and bit15), Data(0), Data(1), ..., Data(7).
● Reception message data
The reception message data is stored in order of MSB (bit7 and bit15), Data(0), Data(1), ..., Data(7).
When the reception message data is less than 8 bytes, the remaining byte of the data register is undefined.
Since the transfer to the message object is performed by 4-byte unit of Data A or Data B, a part of 4-byte
data cannot be updated.
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10.4.3
MB91210 Series
Message Object
There are 32 message objects (up to 128 depending on the model) in the message RAM.
To avoid conflicts between CPU access to the message RAM and access from CAN
controller, the CPU cannot directly access the message objects. These accesses are
handled via the IFx message interface registers.
This section explains the configuration and function of the message objects.
■ Configuration of Message Object
Table 10.4-2 Configuration of Message Object
UMask
Msk28 to
Msk0
MsgVal ID28 to ID0
MXtd
MDir
EoB
Xtd
Dir
DLC3 to
DLC0
NewDat
MsgLst
Data0 Data1 Data2
RxIE
TxIE
IntPnd RmtEn TxRqst
Data3
Data4
Data5
Data6
Data7
Note:
Message objects cannot be initialized by Init bit in the CAN control register and hardware reset. For
the hardware reset, the CPU must initialize the message RAM or set MsgVal bit in the message
RAM to "0" after release of hardware reset.
■ Function of Message Object
ID28 to ID0, Xtd and Dir bits are used for ID and the kind of messages when message is transmitted. They
are used in the acceptance filter with Msk28 to Msk0, MXtd and MDir bits when message is received.
Data frame or remote frame that passed the acceptance filter is stored in the message object. Xtd indicates
whether the extended frame or standard frame. When Xtd is "1", 29-bit ID (extended frame) is received,
and when it is "0", 11-bit ID (standard frame) is received.
When the received data frame or the remote frame matches more than one message object, the frame is
stored in the smallest message number of the message object. For detail, see the "■ Acceptance Filter of
Reception Message" in "10.5.3 Message Reception Operation".
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MsgVal: Message valid bit
MsgVal
Function
0
Message object is invalid.
Message is not transmitted/ received.
1
Message object is valid.
Message can be transmitted/ received.
• Make sure that MsgVal bit in all unused message objects are reset by the CPU during the
initialization performed before resetting Init bit in the CAN control register to "0".
• Make sure that MsgVal bit is reset to "0", before changing ID28 to ID0, Xtd, Dir, DLC3 to DLC0, or
when you don't need the message objects.
• When MsgVal bit in the message object is cleared to "0" during the transmission, TxOk bit in the
CAN status register is set to "1" after the transmission is completed. However, because the message
object and TxRqst bit in the CAN transmission request register are not cleared to "0", clear TxRqst
bit to "0" using the message interface register.
UMask: Acceptance mask enable bit
UMask
Function
0
Msk28 to Msk0, MXtd and MDir are not used.
1
Msk28 to Msk0, MXtd and MDir are used.
• Change UMask bit when Init bit in the CAN control register is "1" or MsgVal bit is "0".
• When Dir bit is "1" and RmtEn bit is "0", the operation is different depending on the Umask setting:
- If UMask is "1" when the acceptance filter passed and the remote frame is received, TxRqst bit is
reset to "0". At that time, the received ID, IDE, RTR, and DLC are stored in the message object,
NewDat bit is set to "1", and data remains unchanged (handled like the data frame).
- If Umask is "0", a value of TxRqst bit is kept as it is and the remote frame is ignored due to
reception of the remote frame.
ID28 to ID0: Message ID
ID
CM71-10139-5E
Function
ID28 to ID0
29-bit ID (extended frame) is indicated.
ID28 to ID18
11-bit ID (standard frame) is indicated.
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Msk28 to Msk0: ID mask
Msk
Function
0
The bit corresponding to ID of message object is masked.
1
The bit corresponding to ID of message object is not masked.
If 11-bit ID (standard frame) is set in a message object, ID of received data frame is written to ID28 to
ID18. Msk28 to Msk18 are used for ID mask.
Xtd: Extended ID enable bit
Xtd
Function
0
11-bit ID (standard frame) is used for message object.
1
29-bit ID (extended frame) is used for message object.
MXtd: Extended ID mask bit
MXtd
Function
0
Extended ID bit (IDE) is masked in acceptance filter.
1
Extended ID bit (IDE) is not masked in acceptance filter.
Dir: Message direction bit
282
Dir
Function
0
Indicates the reception direction.
When TxRqst is set to "1", a remote frame is transmitted. When TxRqst is set to "0", a
data frame that has passed the acceptance filter is received.
1
Indicates the transmission direction.
When TxRqst is set to "1", a data frame is transmitted. When TxRqst is set to "0" and
RmtEn is set to "1", the CAN controller sets TxRqst to "1" by receiving the remote
frame that has passed the acceptance filter.
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MDir: Message direction mask bit
MDir
Function
0
Message direction bit (Dir) is masked in acceptance filter.
1
Message direction bit (Dir) is not masked in acceptance filter.
Note:
Mdir bit should always be set to "1".
EoB: End of buffer bit (see "10.5.4 Function of FIFO Buffer" for detail)
EoB
Function
0
Message object is used as FIFO buffer and is not the last message.
1
Single message object or last message object of FIFO buffer.
EoB bit is used to configure the FIFO buffer of 2 to 32 messages.
Single message object (when not using FIFO) should always set EoB bit to "1".
NewDat: Data renewal bit
NewDat
Function
0
There is no valid data.
1
There is valid data.
MsgLst: Message lost
MsgLst
Function
0
Message lost is not generated.
1
Message lost is generated.
MsgLst bit is valid only when Dir bit is "0" (reception direction).
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RxIE: Reception interrupt flag enable bit
RxIE
Function
0
No IntPnd change after the frame is received successfully.
1
IntPnd is set to "1" after the frame is received successfully.
TxIE: Transmission interrupt flag enable bit
TxIE
Function
0
No IntPnd change after the frame is transmitted successfully.
1
IntPnd is set to "1" after the frame is transmitted successfully.
IntPnd: Interrupt pending bit
IntPnd
Function
0
There is no interrupt source.
1
There is interrupt source.
If there is no other interrupt with high priority, IntId bit in the CAN interrupt register
indicates this message object.
RmtEn: Remote enable
RmtEn
Function
0
TxRqst is not changed by receiving remote frame.
1
TxRqst is set to "1" by receiving remote frame when Dir bit is "1".
When Dir bit is "1" and RmtEn bit is "0", the operation is different depending on the Umask setting:
- If UMask is "1" when the acceptance filter passed and the remote frame is received, TxRqst bit is
reset to "0". At that time, the received ID, IDE, RTR, and DLC are stored in the message object,
NewDat bit is set to "1", and data remains unchanged (handled like the data frame).
- If Umask is "0", a value of TxRqst bit is kept as it is and the remote frame is ignored due to reception
of the remote frame.
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TxRqst: Transmission request bit
TxRqst
Function
0
The transmission idle state (neither transmitting nor transmission wait state)
1
Transmitting or transmission wait state
DLC3 to DLC0: Data length code
DLC3 to DLC0
Function
0 to 8
Data frame length is 0 to 8 bytes.
9 to 15
Setting is disabled.
If setting, it becomes 8-byte length.
When the data frame is received, the received DLC is stored in DLC bit.
Data0 to Data7: Data 0 to 7
Data0 to Data7
Function
Data 0
1st data byte of the CAN data frame
Data 1
2nd data byte of the CAN data frame
Data 2
3rd data byte of the CAN data frame
Data 3
4th data byte of the CAN data frame
Data 4
5th data byte of the CAN data frame
Data 5
6th data byte of the CAN data frame
Data 6
7th data byte of the CAN data frame
Data 7
8th data byte of the CAN data frame
• Serial output to the CAN bus is output from MSB (bit7 or bit15).
• When the reception message data is less than 8 bytes, the remaining byte data of the data register is
undefined.
• Since the transfer to the message object is performed by 4-byte unit of Data A or Data B, a part of 4byte data cannot be updated.
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10.4.4
MB91210 Series
Message Handler Register
All message handler registers are read-only. TxRqst, NewDat, IntPnd, MsgVal and IntId
bits in the message object show the status.
■ Message Handler Register
• CAN transmission request resister 1 and 2 (TREQR1, TREQR2)
• CAN new data resister 1 and 2 (NEWDT1, NEWDT2)
• CAN interrupt pending resister 1 and 2 (INTPND1, INTPND2)
• CAN message valid resister 1 and 2(MSGVAL1, MSGVAL2)
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10.4 Functions of CAN Resisters
MB91210 Series
10.4.4.1
CAN Transmission Request Registers
(TREQR1, TREQR2)
CAN transmission request registers (TREQR1, TREQR2) show TxRqst bit in all the
message objects. Reading TxRqst bit can check which transmission request of
message object is pending.
■ Register Configuration
Figure 10.4-14 CAN Transmission Request Registers (TREQR1, TREQR2)
CAN transmission request register 2 (TREQR2) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+80H
bit12
bit11
TxRqst32 to TxRqst25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
Initial value
00000000B
CAN transmission request register 2 (TREQR2) lower byte
Address
bit7
bit6
bit5
Base+81H
R
R
R
bit4
bit3
TxRqst24 to TxRqst17
R
R
Initial value
00000000B
R
R
R
bit10
bit9
bit8
CAN transmission request register 1 (TREQR1) upper byte
Address
bit15
bit14
bit13
Base+82H
R
R
R
bit12
bit11
TxRqst16 to TxRqst9
R
R
Initial value
00000000B
R
R
R
bit2
bit1
bit0
CAN transmission request register 1 (TREQR1) lower byte
Address
bit7
bit6
bit5
Base+83H
R
R:
R
R
bit4
bit3
TxRqst8 to TxRqst1
R
R
Initial value
00000000B
R
R
R
Read only
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MB91210 Series
■ Register Function
TxRqst32 to TxRqst1: Transmission request bits
TxRqst32 to
TxRqst1
Function
0
The transmission idle state (neither transmitting nor transmission wait state)
1
Transmitting or transmission wait state
Set/reset condition of TxRqst bit is shown in the following:
• Set condition
- When WR/RD and TxRqst bits in the IFx command mask register are set to "1", TxRqst of
specific object can be set by writing to the IFx command request register.
- When WR/RD and TxRqst in the IFx command mask register are set to "1" and "0" respectively,
and TxRqst in the IFx message control register is set to "1", TxRqst of specific object can be set
by writing to the IFx command request register.
- When Dir and RmtEn bits are set to "1", receiving the remote frame that has passed the
acceptance filter sets TxRqst bit.
• Reset condition
- When WR/RD and TxRqst in the IFx command mask register are set to "1" and "0" respectively,
and TxRqst in the IFx message control register is set to "1", TxRqst of specific object can be reset
by writing to the IFx command request register.
- When frame transmission is completed successfully, this bit is reset.
- When Dir is "1", RmtEn is "0", and Umask is "1", receiving the remote frame that has passed the
acceptance filter resets this bit.
See the following table for the transmission request bit in the CAN macro loaded more than 32 message
buffers:
addr + 0
addr + 1
addr + 2
addr + 3
TREQR4 &
TREQR3
TxRqst64 to
TxRqst33
(address 84H)
TxRqst64 to
TxRqst57
TxRqst56 to
TxRqst49
TxRqst48 to
TxRqst41
TxRqst40 to
TxRqst33
TREQR6 &
TREQR5
TxRqst96 to
TxRqst65
(address 88H)
TxRqst96 to
TxRqst89
TxRqst88 to
TxRqst81
TxRqst80 to
TxRqst73
TxRqst72 to
TxRqst65
TREQR8 &
TREQR7
TxRqst128 to
TxRqst97
(address 8CH)
TxRqst128 to
TxRqst121
TxRqst120 to
TxRqst113
TxRqst112 to
TxRqst105
TxRqst104 to
TxRqst97
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4.4.2
CAN New Data Resisters (NEWDT1, NEWDT2)
CAN new data resisters (NEWDT1, NEWDT2) show NewDat bit in all the message
objects. Reading NewDat bit can check which data of message object is renewed.
■ Register Configuration
Figure 10.4-15 CAN New Data Resisters (NEWDT1, NEWDT2)
CAN new data resister 2 (NEWDT2) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+90H
bit12
bit11
bit10
bit9
bit8
R
R
bit1
bit0
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
NewDat32 to NewDat25
R
R
R
Initial value
00000000B
CAN new data resister 2 (NEWDT2) lower byte
Address
bit7
bit6
bit5
R
R
R
Base+91H
bit4
bit3
bit2
NewDat24 to NewDat17
R
R
R
Initial value
00000000B
CAN new data resister 1 (NEWDT1) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+92H
bit12
bit11
NewDat16 to NewDat9
R
R
Initial value
00000000B
CAN new data resister 1 (NEWDT1) lower byte
Address
bit7
bit6
bit5
Base+93H
R
R:
R
R
bit4
bit3
NewDat8 to NewDat1
R
R
Initial value
00000000B
R
R
R
Read only
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■ Register Function
NewDat32 to NewDat1: Data renewal bits
NewDat32 to NewDat1
Function
0
There is no renewal data.
1
There is renewal data.
Set/reset condition of NewDat bit is shown in the following:
• Set condition
- When WR/RD bit in the IFx command mask register and NewDat bit in the IFx message control
register are set to "1", specific object of this bit can be set by writing to IFx command request
register.
- This bit is set by receiving the data frame that has passed the acceptance filter.
- When Dir is "1", RmtEn is "0", and Umask is "1", receiving the remote frame that has passed the
acceptance filter sets this bit.
• Reset condition
- When WR/RD and NewDat bits in the IFx command mask register are set to "0" and "1"
respectively, NewDat bit of specific object can be reset by writing to the IFx command request
register.
- When WR/RD bit in the IFx command mask register is set to "1", and NewDat it in the IFx
message control register is set to "0", NewDat of specific object can be reset by writing to the IFx
command request register.
- After data is transferred to transmission shift register (internal register), this bit is reset.
See the following table for the data renewal bit in the CAN macro loaded more than 32 message
buffers:
addr + 0
addr + 1
addr + 2
addr + 3
NEWDT4 &
NEWDT3
NewDat64 to
NewDat33
(address 94H)
NewDat64 to
NewDat57
NewDat56 to
NewDat49
NewDat48 to
NewDat41
NewDat40 to
NewDat33
NEWDT6 &
NEWDT5
NewDat96 to
NewDat65
(address 98H)
NewDat96 to
NewDat89
NewDat88 to
NewDat81
NewDat80 to
NewDat73
NewDat72 to
NewDat65
NEWDT8 &
NEWDT7
NewDat128 to
NewDat97
(address 9CH)
NewDat128 to
NewDat121
NewDat120 to
NewDat113
NewDat112 to
NewDat105
NewDat104 to
NewDat97
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4.4.3
CAN Interrupt Pending Registers (INTPND1, INTPND2)
CAN interrupt pending registers (INTPND1, INTPND2) show IntPnd bit in all the message
objects. Reading IntPnd bit can check which data of message object is interrupt
pending.
■ Register Configuration
Figure 10.4-16 CAN Interrupt Pending Registers (INTPND1, INTPND2)
CAN interrupt pending register 2 (INTPND2) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+A0H
bit12
bit11
IntPnd32 to IntPnd25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
Initial value
00000000B
CAN interrupt pending register 2 (INTPND2) lower byte
Address
bit7
bit6
bit5
R
R
R
Base+A1H
bit4
bit3
IntPnd24 to IntPnd17
R
R
Initial value
00000000B
CAN interrupt pending register 1 (INTPND2) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+A2H
bit12
bit11
IntPnd16 to IntPnd9
R
R
Initial value
00000000B
CAN interrupt pending register 1 (INTPND2) lower byte
Address
bit7
bit6
bit5
Base+A3H
R
R:
R
R
bit4
bit3
IntPnd8 to IntPnd1
R
R
Initial value
00000000B
R
R
R
Read only
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■ Register Function
IntPnd32 to IntPnd 1: Interrupt pending bits
IntPnd 32 to IntPnd1
Function
0
There is no interrupt source.
1
There is interrupt source.
Set/reset conditions of IntPnd bit is shown below:
• Set conditions
- When TxIE is set to "1", this bit is set after transmission of the frame is completed successfully.
- When RxIE is set to "1", this bit is set after reception of the frame that has passed the acceptance
filter is completed successfully.
- When WR/RD of IFx command mask register and IntPnd of IFx message control register are set
to "1" and IFx command request register is written, this bit can be set to IntPnd which is a specific
object.
• Reset conditions
- By setting WR/RD and IntPnd bits to "1" in IFx command mask register, IntPnd of specific object
can be reset by writing to the IFx command request register.
- When "1" is set to WR/RD of IFx command mask register and "0" is set to IntPnd of IFx message
control register, IntPnd which is a specific object, can be reset by writing to IFx command request
register.
See the following table for the interrupt pending bit in the CAN macro loaded more than 32 message
buffers:
addr + 0
addr + 1
addr + 2
addr + 3
INTPND4 &
INTPND3
IntPnd 64 to
IntPnd33
(address A4H)
IntPnd64 to
IntPnd57
IntPnd56 to
IntPnd49
IntPnd48 to
IntPnd41
IntPnd40 to
IntPnd33
INTPND6 &
INTPND5
IntPnd 96 to
IntPnd65
(address A8H)
IntPnd96 to
IntPnd89
IntPnd88 to
IntPnd81
IntPnd80 to
IntPnd73
IntPnd72 to
IntPnd65
INTPND8 &
INTPND7
IntPnd 128 to
IntPnd97
(address ACH)
IntPnd128 to
IntPnd121
IntPnd120 to
IntPnd113
IntPnd112 to
IntPnd105
IntPnd104 to
IntPnd97
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4.4.4
CAN Message Valid Registers (MSGVAL1, MSGVAL2)
CAN message valid registers (MSGVAL1, MSGVAL2) show MsgVal bit in all the
message objects. Reading MsgVal bit can check which data of message object is
enabled.
■ Register Configuration
Figure 10.4-17 CAN Message Valid Registers (MSGVAL1, MSGVAL2)
CAN message valid register 2 (MSGVAL2) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+B0H
bit12
bit11
MsgVal32 to MsgVal25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
Initial value
00000000B
CAN message valid register 2 (MSGVAL2) lower byte
Address
bit7
bit6
bit5
R
R
R
Base+B1H
bit4
bit3
MsgVal24 to MsgVal17
R
R
Initial value
00000000B
CAN message valid register 1 (MSGVAL1) upper byte
Address
bit15
bit14
bit13
R
R
R
Base+B2H
bit12
bit11
MsgVal16 to MsgVal9
R
R
Initial value
00000000B
CAN message valid register 1 (MSGVAL1) lower byte
Address
bit7
bit6
bit5
Base+B3H
R
R:
R
R
bit4
bit3
MsgVal8 to MsgVal1
R
R
Initial value
00000000B
R
R
R
Read only
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■ Register Function
MsgVal32 to MsgVal1: Message valid bits
MsgVal32 to MsgVal1
Function
0
Message object is invalid.
Message is not transmitted/ received.
1
Message object is valid.
Message can be transmitted/ received.
Set/reset condition of MsgVal bit is shown in the following:
• Set condition
When MsgVal bit in the IFx arbitration register 2 is set to "1", MsgVal of specific object can be set
by writing to the IFx command request register.
• Reset condition
When MsgVal bit in the IFx arbitration register 2 is set to "0", MsgVal of specific object can be reset
by writing to the IFx command request register.
See the following table for the message valid bit in the CAN macro loaded more than 32 message
buffers:
addr + 0
addr + 1
addr + 2
addr + 3
MSGVAL4 &
MSGVAL3
MsgVal64 to
MsgVal33
(address B4H)
MsgVal64 to
MsgVal57
MsgVal56 to
MsgVal49
MsgVal48 to
MsgVal41
MsgVal40 to
MsgVal33
MSGVAL6 &
MSGVAL5
MsgVal96 to
MsgVal65
(address B8H)
MsgVal96 to
MsgVal89
MsgVal88 to
MsgVal81
MsgVal80 to
MsgVal73
MsgVal72 to
MsgVal65
MSGVAL8 &
MSGVAL7
MsgVal128 to
MsgVal97
(address BCH)
MsgVal128 to
MsgVal121
MsgVal120 to
MsgVal113
MsgVal112 to
MsgVal105
MsgVal104 to
MsgVal-97
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CHAPTER 10 CAN CONTROLLER
10.4 Functions of CAN Resisters
MB91210 Series
10.4.5
CAN Prescaler Register (CANPRE)
CAN prescaler register (CANPRE) defines the division ratio of the clock supplied to
CAN interface. When changing the value of this register, set the initialization bit (Init) in
the CAN control register (CTRLR) to "1" and stop all the bus operation.
■ Register Configuration
Figure 10.4-18 CAN Prescaler Register (CANPRE)
CANPRE
Address
bit7
bit6
bit5
bit4
0001A8H
R
R
R
R
bit3
bit2
bit1
bit0
CANPRE3 CANPRE2 CANPRE1 CANPRE0
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W: Readable/Writable
R:
Read only
-:
Undefined bit
■ Register Function
[bit7 to bit4] res: Reserved bits
"0000B" is read from these bits.
Writing is not affected on registers.
[bit3 to bit0] CANPRE3 to CANPRE0: CAN prescaler setting bits
CANPRE[3:0]
Function
0000B
Select system clock as CAN clock [Initial value]
0001B
Select 1/2 cycle of system clock as CAN clock
001XB
Select 1/4 cycle of system clock as CAN clock
01XXB
Select 1/8 cycle of system clock as CAN clock
1000B
Select 2/3 cycle of system clock as CAN clock
Duty of clock is 67%
1001B
Select 1/3 cycle of system clock as CAN clock
101XB
Select 1/6 cycle of system clock as CAN clock
11XXB
Select 1/12 cycle of system clock as CAN clock
• Change the CAN prescaler setting bits, after the initialization bit in the CAN control register is set to
"1" and all the bus operation is stopped.
• The clock supplied to CAN interface by setting this resister should be 20 MHz or less.
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10.5 Functions of CAN
10.5
MB91210 Series
Functions of CAN
This section explains the operation and function of CAN controller.
The following functions are explained:
• Message Object
• Message Transmission Operation
• Message Reception Operation
• Function of FIFO Buffer
• Interrupt Function
• Bit Timing
• Test Mode
• Software Initialization
• CAN Clock Prescaler
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CHAPTER 10 CAN CONTROLLER
10.5 Functions of CAN
MB91210 Series
10.5.1
Message Object
This section explains message object and interface of the message RAM.
■ Message Object
Message object setting of the message RAM (except for MsgVal, NewDat, IntPnd and TxRqst bits) is not
initialized by hardware reset. So, initialize the message object by CPU or set MsgVal bit invalid
(MsgVal=0). Also, set the CAN bit timing register when Init bit in the CAN control register is "0".
Message object setting is specified in the message interface registers (IFx mask register, IFx arbitration
register, IFx message control register, and IFx data register). When a message number is written into the
IFx command request register, the data of the corresponding interface register is transferred to the specified
message object.
When Init bit in the CAN control register is cleared to "0", the CAN controller starts operation. The
reception messages that passed through the acceptance filter are stored in the message RAM. The message
which transmission request is pending are transferred from the message RAM to the shift register of the
CAN controller, and then sent to the CAN bus.
The CPU reads the reception messages via the message interface register, and updates the transmission
messages. An interrupt to the CPU occurs according to the settings of the CAN control register and IFx
message control register (message object).
■ Data Transmission/ Reception with Message RAM
When the data transfer between the message interface register and the message RAM starts, Busy bit in the
IFx command request register is set to "1". When the data transfer is completed, the BUSY bit is cleared to
"0" (See Figure 10.5-1).
The IFx command mask register specifies whether to transfer all data of one message object or to transfer
partial data. Due to the structure of the message RAM, it is impossible to write a single bit/ byte of a
message object. All data of a message object is always written to the message RAM. Consequently, the
data transfer from the message interface register to the message RAM requires the execution cycle of readmodify-write (RMW) instructions.
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Figure 10.5-1 Data Transfer between Message Interface Register and Message RAM
Start
NO
Write to IFx command
request register
YES
BUSY = 1
Interrupt = 0
NO
YES
WR/RD = 1
Read from message RAM to
message interface register
Read from message RAM to
message interface register
Write from message interface
register to message RAM
BUSY = 0
Interrupt = 1
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CHAPTER 10 CAN CONTROLLER
10.5 Functions of CAN
MB91210 Series
10.5.2
Message Transmission Operation
This section explains setting procedure and transmission operation of the transmission
message object.
■ Message Transmission
If there is no data transfer between the message interface register and message RAM, MsgVal bit in the
CAN message valid register and TxRqst bit in the CAN transmission request register are evaluated. While
the transmission request is pending, the valid message object with the highest priority is transferred to the
transmission shift register. At this time, NewDat bit in the message object is reset to "0".
After the transmission is completed successfully if there is no new data in the message object (NewDat=0),
TxRqst bit will be reset to "0". If TxIE is set to "1", IntPnd bit is set to "1" after the transmission is
performed successfully. When CAN controller has lost the arbitration on the CAN bus, or when an error
occurred during the transmission, the message will be retransmitted as soon as the CAN bus becomes idle.
■ Transmission Priority
The transmission priority for the message objects is determined by the message number. Message object 1
has the highest priority and message object 32 (or the highest implemented message object number) has the
lowest priority. If more than one transmission request is pending, the transfer is performed in the order of
smallest number for the corresponding message object.
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■ Setting of Transmission Message Object
Table 10.5-1 shows the initialization procedure of the transmission object.
Table 10.5-1 Initialization of Transmission Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
1
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
0
appl.
0
RmtEn TxRqst
appl.
0
IFx arbitration registers (ID28 to ID0 and Xtd bits) are given by the application and define ID of the
transmission message and type of message.
When the standard frame (11-bit ID) is specified, ID28 to ID18 are used, but ID17 to ID0 are invalid.
When the extended frame (29-bit ID) is specified, ID28 to ID0 are used.
When setting TxIE bit to "1", IntPnd bit is set to "1" after successful transmission of the message object.
When setting RmtEn bit to "1", TxRqst bit is set to "1" after reception of matched remote frame, and the
data frame is transmitted automatically.
The settings of the data registers (DLC3 to DLC0 and Data0 to Data7) are given by the application.
When Umask=1, IFx mask register (Msk28 to Msk0, Umask, MXtd, and Mdir bits) receives the remote
frame that has grouped ID due to mask setting, and then it is used to enable the transmission (set TxRqst bit
to "1"). See the remote frame in "10.5.3 Message Reception Operation" for details.
Note:
Setting Dir bit in the IFx mask register to mask enable is disabled.
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MB91210 Series
■ Updating a Transmission Message Object
The CPU can update the data of the transmission message object via the message interface register.
The data of the transmission message object is written in the unit of 4 bytes of the corresponding IFx data
register (IFx data register A or IFx data register B). Therefore, you cannot change only one byte of the
transmission message object.
In order to update 8-byte data only, write 0087H into the IFx command mask register first. Then, write a
message number into the IFx command request register. The data of the transmission message object is
updated (8- byte data) and "1" is written to TxRqst bit at the same time.
In order to transmit the data consecutively by following the message number being transmitted, set TxRqst
and NewDat bits to "1". TxRqst bit is not reset to "0" and continuous transmission is enabled.
When NewDat and TxRqst bits are set to "1", NewDat bit will be reset to "0" as soon as the new
transmission has started.
• To update data, write the data in the unit of 4 bytes of the IFx data register A or IFx data register B.
• To update data only, set NewDat and TxRqst bits to "1".
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10.5.3
MB91210 Series
Message Reception Operation
Setting procedure and reception operation of the reception message object are
explained.
■ Acceptance Filter of Reception Message
When the arbitration/ control field of the message (ID + IDE + RTR + DLC) is completely shifted to the
shift register for the CAN controller reception, the scan of the message RAM starts to compare it with valid
message objects to find a match.
During the scan, the arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are
loaded from the message object of the message RAM, and the arbitration fields of the message object and
the shift register are compared including the mask data.
This operation is repeated until "the match of the arbitration fields of the message object and the shift
register is found" or "the operation reaches the last word of the message RAM". When a match is found, the
scan of the message RAM is stopped, and the CAN controller starts processing according to the type of the
reception frame (data frame or remote frame).
■ Reception Priority
The reception priority level of the message objects is determined from the message numbers. Message
object 1 has the highest priority, and message object 32 (the largest message object number being
implemented) has the lowest priority. Consequently, when two or more messages match at the acceptance
filter, the message object with a smaller message number is received.
■ Data Frame Reception
The CAN controller transfers and stores the reception message from the shift register to the message RAM
of the message object that is found as a match at the acceptance filter. The data to be stored is not only data
bytes, but also all the arbitration fields and data length codes. The same is true even when the IFx mask
register is set for masking (The data is stored to retain the ID and data bytes).
When new data is received, NewDat bit is set to "1". When the CPU starts to read a message object, reset
NewDat bit to "0". If NewDat bit is already set to "1" when a message is received, the preceding data is
regarded as lost, and the MsgLst bit is set to "1".
When RxIE bit is set to "1" and a message buffer is received, IntPnd bit in the CAN interrupt pending
register is set to "1". When this happens, the TxRqst bit in the corresponding message object is reset to "0".
This purpose is to prohibit transmission processing if a request data frame is received during the
transmission processing of a remote frame.
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■ Remote Frame
The following three types of processing are available when a remote frame is received. The processing at
receiving a remote frame is selected according to the setting of the corresponding message object.
1) Dir=1 (Transmission direction), RmtEn=1, UMask=1 or 0
The matched remote frame is received. Only TxRqst bit in this message object is set to "1". The
automatic reply (transmission) of the data frame is performed for the remote frame (The message
objects other than the TxRqst bit are not changed).
2) Dir=1 (Transmission direction), RmtEn=0, UMask=0
The remote frame is not received even when it matches with the message object. The remote frame is
considered to be invalid (TxRqst bit in this message object is not changed).
3) Dir=1 (Transmission direction), RmtEn=0, UMask=1
If the received remote frame matches with the message object, TxRqst bit in the message object is reset
to "0", and the remote frame is processed as if it is a reception data frame. The received arbitration field
and control field (ID + IDE + RTR + DLC) are stored in the message object of the message RAM, and
NewDat bit in this message object is set to "1". The data field of the message object is not changed.
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■ Setting of Reception Message Object
Table 10.5-2 shows how to initialize the reception message object.
Table 10.5-2 Initialization of Reception Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
0
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
appl.
0
0
RmtEn TxRqst
0
0
IFx arbitration register (ID28 to ID0, Xtd bits) is provided by the application and defines the reception
message ID and message type used for the acceptance filter.
When a standard frame (11-bit ID) is set, ID28 to ID18 are used; ID17 to ID0 are invalid. When a standard
frame is received, ID17 to ID0 are reset to "0". When an extended frame (29-bit ID) is set, ID28 to ID0 are
used.
When RxIE bit is set to "1" and a reception data frame is stored in the message object, IntPnd bit is set to
"1".
The data length code (DLC3 to DLC0) is provided by the application. When the CAN controller stores a
reception data frame into the message object, it stores the reception data length code and the 8-byte data. If
the data length code is less than 8, undefined data is written into the rest of the message object data.
When UMask=1, IFx mask register (Msk28 to Msk0, UMask, MXtd, and MDir bits) is used to enable the
reception of the data frame that has the ID grouped by the mask setting. See the data frame reception in
"10.5.3 Message Reception Operation" for details.
Note:
Mask setting of Dir bit in the IFx mask register is disabled.
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■ Process of Reception Message
The CPU can read the reception messages any time via the message interface register.
In general, it writes 007FH into the IFx command mask register. Then, it writes the message number of the
message object into the IFx command request register. With these procedures, the reception message of the
specified message number is transferred from the message RAM to the message interface register. During
this process, NewDat and IntPnd bits in the message object can be cleared to "0" by setting the IFx
command mask register.
For the process of the reception message, the message is received when it is found to be a match by the
acceptance filter. If the message object uses masking by the acceptance filter, the data set to be masked is
removed from the filter, and whether to receive the message or not is determined.
NewDat bit indicates whether a new message is received after the last message object was read.
MsgLst bit indicates that the previous data is lost because the next reception data is received before the
received data was read from the message object. The MsgLst bit is not reset automatically.
When the acceptance filter receives a matching data frame during the transmission processing of a remote
frame, the TxRqst bit is automatically reset to "0".
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10.5.4
MB91210 Series
Function of FIFO Buffer
This section explains configuration and operation of FIFO buffer for message object in
the reception message process.
■ Configuration of FIFO Buffer
Except EoB bit, the configuration of the reception message objects that belong to a FIFO buffer is the same
as the configuration of a reception message object (See the "■ Setting of Reception Message Object" in
"10.5.3 Message Reception Operation").
Use FIFO buffer to concatenate two or more reception message objects. To store the reception message to
this FIFO buffer, setting of ID and mask for the reception message object must be matched if they are used.
First reception message object of FIFO buffer is equal to the lower message number of high priority. Last
reception message object of FIFO buffer needs to indicate the end of FIFO buffer block by setting EoB bit
to "1" (set EoB bit to "0", except last message object of message object that uses the configuration of FIFO
buffer).
• Setting of ID and mask for message object used for FIFO buffer must be the same setting.
• Be sure to set "1" to EoB bit when FIFO buffer is not used.
■ Message Reception by FIFO Buffer
If the reception message matches with ID of FIFO buffer, the message is stored to the reception message
object for FIFO buffer of the smallest message number.
When the message is stored to the reception message object for FIFO buffer, NewDat bit in this reception
message object is set to "1". When EoB bit sets NewDat bit to the reception message object of "0", the
reception message object is protected until it reaches to last reception message object (EoB bit = 1) and
FIFO buffer writing by the CAN controller is not performed.
Unless "0" is written to NewDat bit in the reception message object in the state which valid data is stored
up to last FIFO buffer (release of write protection), next message to be received is written to last message
object and the message is overwritten.
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■ Read from FIFO Buffer
By writing the reception message number to the IFx command request register, the reception message
number is transferred to message interface register and the content of the reception message object can be
read by CPU. At this time, set WR/RD in the IFx command mask register to "0" (read), set TxRqst/
NewDat=1 and IntPnd=1, and reset NewDat and IntPnd bits to "0".
To guarantee the function of FIFO buffer, be sure to read the reception message object of FIFO buffer from
the smallest message number.
Figure 10.5-2 shows procedure for CPU processing of the message object concatenated by FIFO buffer.
Figure 10.5-2 CPU Process of FIFO Buffer
Start
Message interrupt
Read CAN interrupt
register
8000H
0000H
CAN interrupt register value
Other than 8000H and 0000H
Execution of state
interrupt operation
End
(normal operation)
Message number = CAN interrupt
register value
Write IFx command request register
(message number)
Read message interface resister
(reset: NewDat=0, IntPnd=0)
Read IFx message control register
NO
NewDat = 1
YES
Read IFx message data register A,B
YES
EoB = 1
NO
Message number = message number + 1
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10.5.5
MB91210 Series
Interrupt Function
This section explains the interrupt process by status interrupt (IntId=8000H) and
message interrupt (IntId=message number).
When two or more interrupts are pending, the CAN interrupt register indicates the pending interrupt code
of the highest priority. The time order specified the interrupt codes is ignored. The interrupt code of the
highest priority is always indicated. The interrupt code is retained until it is cleared by the CPU.
The status interrupt (IntId bit=8000H) has the highest priority.
The priority of the message interrupt is set higher for the message with a smaller message number, and is
set lower for the message with a larger message number.
The message interrupt is cleared by clearing IntPnd bit in the message object. The status interrupt is cleared
by reading the CAN status register.
IntPnd bit in the CAN interrupt pending register indicates whether an interrupt is present or not. If there is
no pending interrupt, the IntPnd bit indicates "0".
When IntPnd bit is set to "1" while IE bit in the CAN control register and TxIE and RxIE bits in the IFx
message control register are "1", an interrupt signal to the CPU becomes active. The interrupt signal is
retained to be active until the CAN interrupt pending register is cleared to "0" (interrupt factor reset), or
until the IE bit in the CAN control register is reset to "0".
The CAN interrupt register set to 8000H indicates that the CAN status register was updated by the CAN
controller. This interrupt has the highest priority. The interrupt by updating the CAN status register can be
used for the control of enabling or disabling the setting of the CAN interrupt register by using EIE and SIE
bits in the CAN control register. The interrupt signal to the CPU can be controlled with IE bit in the CAN
control register.
RxOk, TxOk, and LEC bits in the CAN status register can be updated (reset) by writing values from the
CPU. The writing, however, cannot set or reset an interrupt.
The CAN interrupt register set to the values other than 8000H or 0000H indicates that the message interrupt
is pending, and shows the pending message interrupt which has a high priority.
The CAN interrupt register is updated even when IE bit is reset.
The source of the message interrupt to the CPU can be identified by checking the CAN interrupt register or
the CAN interrupt pending register (See "10.4.4 Message Handler Register"). When clearing the message
interrupt, you can read the message data simultaneously. If you clear the message interrupt indicated by the
CAN interrupt register, the interrupt with the second highest priority is set in the CAN interrupt register and
waits for the next interrupt processing. If there is no interrupt, the CAN interrupt register indicates 0000H.
• Status interrupt (Intld=8000H) is cleared by read access of the CAN status register.
• Status interrupt (Intld=8000H) by write access of the CAN status register does not occur.
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CHAPTER 10 CAN CONTROLLER
10.5 Functions of CAN
MB91210 Series
10.5.6
Bit Timing
This section explains the overview for the bit timing and the bit timing in the CAN
controller.
Each CAN node of the CAN network has its own clock oscillator (usually a crystal oscillator). The time
parameter of the bit time can be configured individually for each CAN node, creating a common bit rate
even though the CAN nodes' oscillation cycle (fosc) is different.
The frequencies of these oscillators depend on the change in temperature or voltage and deterioration of
components. As long as the variations remain within a specific oscillator tolerance range (df), the CAN
nodes are able to compensate for the different bit rates by resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into 4 segments (see Figure 10.5-3):
Synchronization Segment (Sync-Seg), Propagation Time Segment (Prop-Seg), Phase Buffer Segment 1
(Phase-Seg1), and Phase Buffer Segment 2 (Phase-Seg2). Each segment consists of a specific,
programmable number of time quanta (see Table 10.5-3). The basic time unit of the bit time (tq) is defined
by the CAN controller's system clock fsys and the baud rate prescaler (BRP):
tq = BRP / fsys
The CAN's system clock fsys is the frequency of clock input (see Figure 10.2-1). The Synchronization
Segment Sync_Seg is timing of the bit time where edges of the CAN bus level are expected to occur. The
Propagation Time Segment Prop_Seg is intended to compensate for the physical delay times within the
CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 specify the sampling point.
Resynchronization jump width (SJW) defines move width of sampling point at the time of
resynchronization in order to compensate for edge phase errors.
Figure 10.5-3 Bit Timing
1 bit time (tq)
Sync
_Seg
Prop_Seg
1 time quantum
(tq)
CM71-10139-5E
Phase_Seg1
Phase_Seg2
Sampling point
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Table 10.5-3 Parameter of CAN Bit Time
Parameter
Range
Function
BRP
[1 to 32]
Sync_Seg
1 tq
Prop_Seg
[1 to 8] tq
Compensates for the physical delay times
Phase_Seg1
[1 to 8] tq
Guarantee of edge phase error before sampling point
May be lengthened temporarily by synchronization
Phase_Seg2
[1 to 8] tq
Guarantee of edge phase error after sampling point
May be shortened temporarily by synchronization
SJW
[1 to 4] tq
Resynchronization jump width
May not be longer than either phase buffer segment
Defines the length of the time quantum (tq)
Fixed length, synchronization to system clock
Figure 10.5-4 shows the bit timing of the CAN controller:
Figure 10.5-4 Bit Timing of CAN Controller
1 bit time (BT)
Sync
_Seg
TSEG1
1 time quantum
(tq)
310
TSEG2
Sampling point
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Table 10.5-4 Parameter of CAN Controller
Parameter
Range
Function
BRPE, BRP
[0 to 1023]
Defines the length of the time quantum (tq)
Prescaler can be extended up to 1024 by the bit timing register and the
prescaler extended register.
Sync_Seg
1 tq
TSEG1
[1 to 15] tq
Time segment before sampling point
Equivalent to Prop_Seg and Phase_Seg1
Can be controlled by the bit timing register
TSEG2
[0 to 7] tq
Time segment after sampling point
Equivalent to Phase_Seg2
Can be controlled by the bit timing register
SJW
[0 to 3] tq
Resynchronization jump width
Can be controlled by the bit timing register
Synchronization to system clock
Fixed length
Relationship of each parameter is shown below:
tq =([BRPE, BRP] +1) / fsys
BT =SYNC_SEG
CM71-10139-5E
+ TSEG1
+ TSEG2
=(1
+ (TSEG1 + 1) + (TSEG2 + 1)) × tq
=(3 + TSEG1
+ TSEG2) × tq
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10.5.7
MB91210 Series
Test Mode
This section explains setting procedure and operation of the test mode.
■ Test Mode Setting
The test mode starts by setting Test bit in the CAN control register to "1". In the test mode, Tx1, Tx0,
LBack, Silent and Basic bits in the CAN test register are enabled.
All test register functions are disabled when Test bit in the CAN control register is reset to "0".
■ Silent Mode
The CAN controller can be set in silent mode by setting Silent bit in the CAN test register to "1".
In silent mode, the data frames and remote frames can be received, but only recessive is output on the CAN
bus and the message and ACK are not transmitted.
If the CAN controller is requested to transmit a dominant bit (ACK bit, overload flag, active error flag), it
is transmitted on RX side with loop circuit in the CAN controller. In this operation, the dominant bit
transmitted back in the CAN controller is received on the reception side even in recessive state on the CAN
bus.
The silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of
dominant bits (ACK bits, error flags).
Figure 10.5-5 shows the CAN controller in silent mode.
Figure 10.5-5 CAN Controller in Silent Mode
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
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■ Loop Back Mode
The CAN controller can be set in loop back mode by setting LBack bit in the CAN test register to "1".
Loop back mode can be used for self-test function.
In loop back mode, TX side and RX side are connected in the internal CAN controller, the message
transmitted from the CAN controller is handled as a received message on RX side, and the messages that
passed the acceptance filter are stored into the reception buffer.
Figure 10.5-6 shows the CAN controller in loop back mode.
Figure 10.5-6 CAN Controller in Loop Back Mode
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
To be independent from external signal, the dominant bit in the acknowledge slot of a data/ remote frame is
not sampled. Therefore, CAN controller usually generates acknowledge error, but it ignores acknowledge
errors in this test mode.
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■ Combination of Silent Mode and Loop Back Mode
It is possible to combine loop back mode and silent mode and to operate by setting LBack and Silent bits in
the CAN test register to "1" at the same time.
This mode can be used for a hot self test, which means when the CAN controller tests in loop back mode,
this test has no effect on operation of the CAN system because fixed output of recessive to CAN_TX pin
and input from CAN_RX pin are invalid.
Figure 10.5-7 shows the CAN controller where loop back mode and silent mode are combined.
Figure 10.5-7 CAN Controller Where LOOP Back Mode and Silent Mode are Combined
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
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MB91210 Series
■ Basic Mode
The CAN controller can be set in basic mode by setting Basic bit in the CAN test register to "1".
In basic mode, the CAN controller runs without using the message RAM.
The IF1 message interface registers are used for transmission control.
When transmitting a message, first set the content to transmit to IF1 message interface register. Then,
request the transmission by setting BUSY bit in the IF1 command request register to "1". While BUSY bit
is set to "1", that indicates the IF1 message interface register is locked or the transmission is pending.
When "1" is set to BUSY bit, CAN controller operates as follows:
As soon as the CAN bus becomes bus idle, the content of the IF1 message interface registers are loaded
into the transmission shift register to start the transmission. When the transmission has completed
successfully, BUSY bit is reset to "0" and the locked IF1 message interface registers are released.
A pending transmission can be aborted at any time by resetting BUSY bit in the IF1 command request
register to "0". If the BUSY bit is reset to "0" during transmission, a possible retransmission in case of
arbitration lost or an error is disabled.
The IF2 message interface registers are used for reception control.
All messages are received without using the acceptance filter. The contents of the received message can be
read by setting BUSY bit in the IF2 command request register to "1".
When "1" is set to BUSY bit, CAN controller stores the received message (content of shift register for
reception) to IF2 message interface register without the acceptance filter.
When new message is stored in the IF2 message interface register, the CAN controller sets NewDat bit to
"1". Also, when NewDat bit is "1", the CAN controller sets MsgLst to "1" if another new message is
received.
• In basic mode, the setting of all message objects related to control/ status bits and the setting of the
control mode of the IFx command mask registers are disabled.
• The message number of the command request registers is invalid.
• NewDat and MsgLst bits in the IF2 message control register operates in the same way as the normal
operation; DLC3 to DLC0 will show the received DLC, and the other control bits will be read "0".
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■ Software Control of Pin CAN_TX
CAN_TX; the CAN transmit pin has 4 output functions:
• Serial data output (normal output)
• CAN sampling point signal output to monitor the bit timing of CAN controller
• Dominant fixed output
• Recessive fixed output
Fixed output of dominant and recessive has CAN_RX monitoring function of the CAN reception pin and
can be used to check the CAN bus's physical layer.
The output mode of CAN_TX pin can be controlled by Tx1 and Tx0 bits in the CAN test register.
CAN_TX must be set to serial data output when transmitting CAN message, or using loop back mode,
silent mode, or basic mode.
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10.5.8
Software Initialization
This section explains initialization by software.
The initialization factors in software is shown below:
• Hardware reset
• Setting of Init bit in the CAN control register
• Transmission to bus off state
Hardware reset initializes all message objects other than the message RAM (except for MsgVal, NewDat,
IntPnd and TxRqst bits). After hardware reset, the message RAM should be initialized by the CPU, or
MsgVal bit in the message RAM should be set to "0". Also, when setting the bit timing register, set the
register before clearing Init bit in the CAN control register to "0".
Init bit in the CAN control register is set to "1" with the following conditions:
• Write "1" from CPU
• Hardware reset
• Bus off
When Init bit is set to "1", all the message transmission/ reception from and to the CAN bus is stopped, the
CAN_TX pin of the CAN bus output is recessive output (except for CAN_TX test mode).
When Init bit is set to "1", error counter and register are not changed.
Setting to the bit timing register and to the prescaler extended register for the baud rate control are enabled
when both Init and CCE bits in the CAN control register are set to "1".
Resetting Init bit to "0" finishes the software initialization. Only the access from CPU can set Init bit to "0".
The message is transferred after synchronizing with data transfer on the CAN bus when Init bit is reset to
"0" until occurrence of consecutive 11-bit recessive (=bus idle) is waited.
When changing the mask of a message object, ID, Xtd, EoB, and RmtEm during normal operation, disable
MsgVal first.
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10.5.9
MB91210 Series
CAN Clock Prescaler
This section explains CAN clock switching during PLL operation.
■ Block Diagram
The overview of the CAN clock prescaler is shown in the following block diagram:
The division ratio of clock supplied to the CAN interface is determined according to the setting of
CANPRE bit in the CAN clock prescaler register.
Figure 10.5-8 Block Diagram of CAN Clock Prescaler
PLL
Clock
division
CAN clock
X0
Div by
CANPRE
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MB91210 Series
■ Procedure of Clock Switching
The following procedure is recommended for how to switch the clock using the CAN clock prescaler.
Figure 10.5-9 Procedure of Clock Switching
Switching CAN clock :
OSCILLATOR -> PLL
Switching CAN clock :
PLL -> OSCILLATOR
Set bit Init in the CAN
Control Register
Set bit Init in the CAN
Control Register
Enable PLL
Set prescaler value
Wait for PLL Lock Time
CLocK source Select *2
CLocK source Select *1
Disable PLL
Set prescaler value
Reset bit Init in the CAN
Control Register
Reset bit Init in the CAN
Control Register
*1: Set PLL1EN (bit10) in the CLKR (clock source selection resister) before selecting the main PLL
(10B) in the CLKS [1:0] (bit8/bit9).
*2: Deselect the main PLL in the CLKS [1:0] (bit8/bit9) in the CLKR (clock source selection resister)
before disabling using PLL1EN (bit10).
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■ CAN Clock Prescaler Setting
The values that can be set to the CAN clock prescaler are indicated:
Clock supplied to the CAN interface is the one that is divided the system clock according to the setting
value of the CAN clock prescaler.
CANPRE[3:0]
Function
System clock:
at 40MHz
40MHz
(setting disabled)
0000B
Select system clock as CAN clock [Initial value]
0001B
Select 1/2 cycle of system clock as CAN clock
20MHz
001XB
Select 1/4 cycle of system clock as CAN clock
10MHz
01XXB
Select 1/8 cycle of system clock as CAN clock
5MHz
1000B
Select 2/3 cycle of system clock as CAN clock Duty ratio of
the clock is 67%
1001B
Select 1/3 cycle of system clock as CAN clock
13.33MHz
101XB
Select 1/6 cycle of system clock as CAN clock
6.67MHz
11XXB
Select 1/12 cycle of system clock as CAN clock
3.33MHz
26.67MHz
(setting disabled)
• Change the CAN prescaler setting bits, after the initialization bit in the CAN control register is set to "1"
and all the bus operation is stopped.
• The clock supplied to CAN interface by setting this resister should be 20MHz or less.
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CHAPTER 11
LIN-UART
This chapter explains the functions and operations of
the UART with LIN function.
11.1 Overview of UART
11.2 Configuration of UART
11.3 Registers of UART
11.4 Interrupts of UART
11.5 UART Baud Rates
11.6 Operations of UART
11.7 Notes on Using UART
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CHAPTER 11 LIN-UART
11.1 Overview of UART
11.1
MB91210 Series
Overview of UART
LIN (Local Interconnect Network) compliant UART (Universal Asynchronous Receiver
and Transmitter) is a general-purpose serial data communication interface for
asynchronous/synchronous communication with external devices. The LIN-UART
supports bidirectional communication function (normal mode), master/slave
communication function (multiprocessor mode in master system), and LIN bus systems
(working as both master/slave devices).
■ Overview
The LIN-UART is a general-purpose serial data communication interface for transmitting to and receiving
data from other CPUs and peripheral devices, especially LIN devices. The functions of the LIN-UART are
listed in Table 11.1-1.
Table 11.1-1 Functions of LIN-UART (1 / 2)
Item
Function
Data buffer
Full-duplex buffer
Serial input
In asynchronous mode, oversampling is performed 5 times to determine the reception value.
Transfer mode
Transfer rate
Data length
• Clock synchronous (start/stop synchronization, start/stop bit selection)
• Clock asynchronous (using start/stop bits)
• Dedicated 15-bit baud rate generator provided
• An external clock input can be used and is adjusted by the reload counter.
• 7 bits (not applicable in synchronous or LIN mode)
• 8 bits
Signal mode
NRZ
Start bit timing
Clock synchronized with the falling edge of a start bit in asynchronous mode
• Framing error
Reception error detection
• Overrun error
• Parity error
• Reception interrupt (reception completion, reception error detection)
Interrupt request
• Transmission interrupt (transmission completion)
• Bus idle interrupt (belongs to reception interrupt)
• LIN-Synch-Break interrupt (belongs to reception interrupt)
Master/slave communication
function
(Multiprocessor mode)
1-to-many communication (1 master, multiple slaves) is enabled.
(Supported in both master and slave systems)
Synchronization mode
Function as a master or a slave LIN-UART
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CHAPTER 11 LIN-UART
11.1 Overview of UART
MB91210 Series
Table 11.1-1 Functions of LIN-UART (2 / 2)
Item
Function
Transmission and reception
line
Direct access enabled
• Operation as a master device
• Operation as a slave device
LIN bus option
• LIN-Synch-Break generation
• LIN-Synch-Break detection
• Detection of LIN-Synch-Field start/stop edges by ICU
Synchronous serial clock
Continuous output from the SCK pin is possible for synchronous communication using the
start/stop bits.
Clock delay option
Special synchronous clock mode for clock delay (for SPI)
Note:
The LIN function is not provided for ch.4 of LIN-UART in MB91F211B.
■ LIN-UART Operation Modes
The LIN-UART operates in four different modes. The operation mode is selected by the MD0 and MD1
bits in the serial mode register (SMR). Modes 0 and 2 are used for bidirectional serial communication,
mode 1 for master/slave communication, and mode 3 for LIN master/slave communication.
Table 11.1-2 LIN-UART Operation Modes
Data length
Operation mode
Parity disabled
0 Normal mode
1
Multiprocessor
mode
7 bits or 8 bits
7 bits or
8 + 1 bits*2
2 Normal mode
3 LIN mode
Parity enabled
8 bits
8 bits
-
Synchronous
mode
Stop bit length
Data bit
detection*1
Asynchronous
1 bit or 2 bits
LSB first or
MSB first
Asynchronous
1 bit or 2 bits
LSB first or
MSB first
Synchronous
0, 1 bit or 2 bits
LSB first or
MSB first
Asynchronous
1 bit
LSB first
*1: Means the transfer mode: LSB first or MSB first
*2: "+1" indicates address/data switching in multiprocessor mode instead of using a parity bit.
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11.1 Overview of UART
MB91210 Series
Note:
Mode 1 (multiprocessor mode) supports both master and slave operations of the LIN-UART in a
master/slave system. In Mode 3, LIN-UART function is fixed to 8N1-Format, LSB first.
If the mode is changed, LIN-UART stops its transmissions and receptions and waits, and then shifts to a
new operation.
Table 11.1-3 shows the mode bit setting.
Table 11.1-3 Mode Bit Setting
324
MD1
MD0
Mode
Function
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
3
Asynchronous (LIN mode)
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CHAPTER 11 LIN-UART
11.2 Configuration of UART
MB91210 Series
11.2
Configuration of UART
This section explains the LIN-UART configuration.
■ Block Diagram of LIN-UART
LIN-UART consists of the following blocks:
• Reload counter
• Reception control circuit
• Reception shift register
• Reception data register (RDR)
• Transmission control circuit
• Transmission shift register
• Transmission data register (TDR)
• Error detection circuit
• Oversampling unit
• Interrupt generation circuit
• LIN-Synch-Break and Sync-Field detection circuit
• Bus idle detection circuit
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Extended communication control register (ECCR)
• Extended communication status/control register (ESCR)
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CHAPTER 11 LIN-UART
11.2 Configuration of UART
MB91210 Series
■ Block Diagram of LIN-UART
Figure 11.2-1 Block Diagram of LIN-UART
PE
Transmission clock
CLK
ORE
FRE
TIE
Reception clock
Reload
counter
SCK
Reception
control circuit
Reception
control circuit
Interrupt
generation
circuit
Pin
Start bit
detection
SIN
Pin
Reception restart
reload counter
Reception
bit counter
Transmission
start circuit
Transmission
bit counter
RIE
LBIE
LBD
BIE
RBI
TBI
Reception IRQ
TDRE
Transmission IRQ
Reception
parity
counter
Over
sampling
unit
Transmission
parity
counter
SOT
Pin
RDRF
Reception
completed
SIN
Signal
to ICU
Reception
shift
register
LIN-Break,
Synch-Field
detection
SOT
SIN
Transmission
shift
register
LIN-Break
generation
Reception start
Error
detection
RDR
Bus idle
detection
TDR
LBR
LBL1
LBL0
STR
PE
ORE
FRE
RBI
TBI
LBD
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
326
SSR
register
MD1
MD0
(OTO)
(EXT)
(REST)
UPCL
SCKE
SOE
SMR
register
PEN
P
SBL
CL
AD
DRE
RXE
TXE
SCR
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
ESCR
register
FUJITSU MICROELECTRONICS LIMITED
LBR
MS
SCDE
SSM
BIE
RBI
TBI
ECCR
register
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CHAPTER 11 LIN-UART
11.2 Configuration of UART
MB91210 Series
■ Explanation of Each Block
● Reload Counter
The reload counter functions as the dedicated baud rate generator. The transmission/reception clock is
generated from an external or internal clock. The reload counter has a 15-bit register for the reload value.
The actual count value of the transmission reload counter can be read from the BGR0/BGR1 value.
● Reception Control Circuit
The reception control circuit consists of a reception bit counter, a start bit detection circuit, and a reception
parity counter.
The reception bit counter counts the reception data. When reception of one data with a specified data length
is completed, the reception bit counter sets the reception data register full flag.
The start bit detection circuit detects a start bit from a serial input signal and outputs the signal to the reload
counter in synchronization with the falling edge of the start bit.
The reception parity counter calculates the parity of the reception data.
● Reception Shift Register
The reception shift register fetches reception data input from the SIN pin by shifting the data bit by bit.
When the reception is completed, the reception shift register transfers the reception data to the reception
data register (RDR).
● Reception Data Register (RDR)
The reception data register retains reception data. Serial input data is converted and stored in this register.
● Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, a transmission start circuit and a
transmission parity counter.
The transmission bit counter counts transmission data bits. When transmission of one data with a specified
data length is completed, the transmission bit counter sets the transmission data register empty flag.
The transmission start circuit starts transmission when data is written to the TDR.
The transmission parity counter generates a parity bit for transmission data if parity is enabled.
● Transmission Shift Register
The transmission shift register shifts transmission data written in the transmission data register (TDR) and
outputs the data to the SOT pin bit by bit.
● Transmission Data Register (TDR)
Transmission data is set in the transmission data register. Data written to this register is converted to serial
data and then the data is output.
● Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred, it
sets the corresponding error flag.
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CHAPTER 11 LIN-UART
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MB91210 Series
● Oversampling Unit
The oversampling unit oversamples data input from the SIN pin for 5 times. This unit does not operate in
synchronous operation mode.
● Interrupt Generation Circuit
The interrupt generation circuit controls all interrupts. An interrupt is generated immediately if the interrupt
is enabled and the corresponding interrupt source occurs.
● LIN-Break and Sync-Field Detection Circuit
The LIN-Break and LIN-Sync-Break detection circuit detects a LIN-Break if a LIN master node is
outputting a message handler. If a LIN-Break is detected, the LBD flag bit is generated. The 1st and the 5th
falling edge of the Sync-Field is detected by this circuit and it outputs an internal signal to the input capture
to measure accurate serial clock cycle of the transmission master node.
● LIN-Break Generation Circuit
The LIN-Break generation circuit generates a LIN-Synch-Break with a defined length.
● Bus Idle Detection Circuit
The bus idle detection circuit detects the state where no reception/transmission is in execution (bus idle). In
this state, this circuit generates TBI and RBI flag bits.
● Serial Mode Register (SMR)
The serial mode register performs the following operations:
- Selects the LIN-UART operation mode
- Selects a clock input
- Selects between one-to-one connection and reload counter connection for the external clock
- Restarts the dedicated reload timer
- Resets LIN-UART (with register settings saved)
- Enables output of the serial output pin (SOT)
- Switches I/O of the serial clock pin (SCK)
● Serial Control Register (SCR)
The serial control register performs the following operations:
- Specifies whether to provide a parity bit
- Selects a parity bit
- Specifies a stop bit length
- Specifies a data length
- Specifies a frame data format in mode 1
- Clears error flags
- Enables transmission
- Enables reception
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MB91210 Series
● Serial Status Register (SSR)
The serial status register checks transmission/reception status and the error status.
transmission/reception interrupt and sets the transfer direction (LSB first/MSB first).
It also enables
● Extended Status/Control Register (ESCR)
This register can set LIN functions. It can set the direct access to the SIN and SOT pins and the LIN-UART
synchronous clock mode.
● Extended Communication Control Register (ECCR)
This register can set the bus idle detection interrupts and the synchronous clock, and can generate LINBreaks.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
11.3
MB91210 Series
Registers of UART
Figure 11.3-1 shows the registers of LIN-UART.
■ Registers of LIN-UART
Figure 11.3-1 Registers of LIN-UART
SCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000060H
000068H
000070H
0000B0H
0000B8H
0000C0H
0000C8H
PEN
R/W
P
R/W
SBL
R/W
CL
R/W
AD
R/W
CRE
W
RXE
R/W
TXE
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000061H
000069H
000071H
0000B1H
0000B9H
0000C1H
0000C9H
MD1
R/W
MD0
R/W
OTO
R/W
EXT
R/W
REST
W
UPCL
W
SCKE
R/W
SOE
R/W
00000000B
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000062H
00006AH
000072H
0000B2H
0000BAH
0000C2H
0000CAH
PE
R
ORE
R
FRE
R
RDRF
R
TDRE
R
BDS
R/W
RIE
R/W
TIE
R/W
00001000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000063H
D7
00006BH
R/W
000073H
0000B3H
0000BBH
0000C3H
0000CBH
R/W: Readable/writable
R:
Read only
W: Write only
D6
R/W
D5
R/W
D4
R/W
D3
W
D2
W
D1
R/W
D0
R/W
00000000B
SMR
SSR
RDR/TDR
Address
(Continued)
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11.3 Registers of UART
MB91210 Series
(Continued)
ESCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000064H
00006CH
000074H
0000B4H
0000BCH
0000C4H
0000CCH
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
00000100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000065H
00006DH
000075H
0000B5H
0000BDH
0000C5H
0000CDH
res
LBR
MS
SCDE
SSM
BIE
RBI
TBI
000000XXB
-
W
R/W
R/W
R/W
R/W
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000066H
00006EH
000076H
0000B6H
0000BEH
0000C6H
0000CEH
-
B14
B13
B12
B11
B10
B09
B08
10000000B
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000067H
00006FH
000077H
0000B7H
0000BFH
0000C7H
0000CFH
B07
B06
B05
B04
B03
B02
B01
B00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ECCR
BGR1
BGR0
R/W:
R:
W:
X:
-:
Readable/writable
Read only
Write only
Undefined value
Undefined bit
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CHAPTER 11 LIN-UART
11.3 Registers of UART
11.3.1
MB91210 Series
Serial Control Register (SCR)
The serial control register (SCR) is used to set a parity bit, select the stop bit length and
data length, select the frame data format in mode 1, clear reception error flags, and
enable transmission/reception.
■ Serial Control Register (SCR)
Figure 11.3-2 Bit Configuration of Serial Control Register (SCR)
SCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000060H
000068H
000070H
0000B0H
0000B8H
0000C0H
0000C8H
PEN
P
SBL
CL
AD
CRE
RXE
TXE
00000000B
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W: Readable/writable
W: Write only
[bit15] PEN: Parity enable bit
PEN
Parity enable
0
No parity [initial value]
1
Enables parity
This bit selects whether to add a parity bit to transmission data in serial asynchronous mode. It performs
parity detection during the reception.
Parity is added in mode 0, and also in mode 2 if SSM bit in ECCR is set. This bit is fixed to "0" (no
parity) in mode 3 (LIN mode).
[bit14] P: Parity selection bit
P
Parity selection
0
Even parity [initial value]
1
Odd parity
When parity is valid, this bit selects even parity (0) or odd parity (1).
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11.3 Registers of UART
MB91210 Series
[bit13] SBL: Stop bit length selection bit
SBL
Stop bit length
0
1 bit [initial value]
1
2 bits
This bit selects the length of a stop bit for an asynchronous data frame, and also for a synchronous
frame. If SSM bit in ECCR is set, it even selects the bit length for a synchronous data frame. This bit is
fixed to "0" (1 bit) in mode 3 (LIN mode).
[bit12] CL: Data length selection bit
CL
Character (data frame) length
0
7 bits [initial value]
1
8 bits
This bit specifies the length of transmission/reception data. This bit is fixed to "1" (8 bits) in modes 2
and 3.
[bit11] AD: Address/data selection bit
AD
Address/data bit
0
Data bit [initial value]
1
Address bit
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is provided for a master
CPU and reading from it is provided for a slave CPU. The "1" indicates address frame and the "0"
indicates data frame.
Note:
See "11.7 Notes on Using UART" for the use of AD bit.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
[bit10] CRE: Reception error flag clear bit
Reception error clear
CRE
Write
0
Ignored [initial value]
1
Clears all reception errors
(PE, FRE, ORE).
Read
Read value is always "0"
This bit clears FRE, ORE, and PE flags in the serial status register (SSR).
- Writing "1" to this bit clears the reception error flag.
- Writing "0" to this bit has no effect on operation. Reading this bit always returns "0".
Note:
Disable reception (RXE=0) and then clear reception error flags.
If the reception error flag is cleared without disabling reception, the reception is interrupted once and
then the reception is resumed.
By this operation, some data may not be received normally at the resume.
[bit9] RXE: Reception enable bit
RXE
Reception enable
0
Disables reception [initial value]
1
Enables reception
This bit enables LIN-UART reception. When this bit is set to "0", LIN-UART stops receiving data
frame. This bit is invalid for detecting LIN-Break in the mode 0 and 3.
[bit8] TXE: Transmission enable bit
TXE
Transmission enable
0
Disables transmission [initial value]
1
Enables transmission
This bit enables LIN-UART transmission. When this bit is set to "0", LIN-UART stops transmitting
data frame.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
11.3.2
Serial Mode Register (SMR)
The serial mode register (SMR) is used to select the operation mode and baud rate
clock. It is also used to specify the input and output direction of the serial clock (SCK)
and to set the serial output enable setting.
■ Serial Mode Register (SMR)
Figure 11.3-3 Bit Configuration of Serial Mode Register (SMR)
SMR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000061H
000069H
000071H
0000B1H
0000B9H
0000C1H
0000C9H
MD1
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
00000000B
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W: Readable/writable
W: Write only
[bit7, bit6] MD1, MD0: Operation mode selection bits
MD0
MD1
Operation mode setting
0
0
Mode 0: Asynchronous normal mode [initial value]
1
0
Mode 1: Asynchronous multiprocessor mode
0
1
Mode 2: Synchronous mode
1
1
Mode 3: Asynchronous LIN mode
These bits set the LIN-UART operation mode.
[bit5] OTO: 1 to 1 external clock selection bit
OTO
External clock selection
0
Uses an external clock for the baud rate generator (reload counter) [initial value]
1
Uses an external clock as the serial clock
If this bit is set, an external clock is used directly as the LIN-UART serial clock. This function is used
for synchronous slave mode operation.
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11.3 Registers of UART
MB91210 Series
[bit4] EXT: External clock selection bit
EXT
External serial clock enable
0
Uses the internal baud rate generator (reload counter) [initial value]
1
Uses an external clock as the serial clock
This bit can select the clock for the reload counter.
[bit3] REST: Transmission reload counter restart bit
Reload counter restart
REST
Write
0
Ignored [initial value]
1
Restarts counter
Read
Read value is always "0"
Writing "1" to this bit restarts the reload counter. Writing "0" is ignored.
Reading this bit always returns "0".
[bit2] UPCL: LIN-UART clear bit (software reset)
LIN-UART clear (software reset)
UPCL
Write
0
Ignored [initial value]
1
LIN-UART reset
Read
Read value is always "0"
Writing "1" to this bit resets LIN-UART immediately, however, the register setting values are saved.
Transmission/Reception is suspended.
All error flags are cleared and the reception data register (RDR) becomes 00H.
Writing "0" to this bit is ignored.
Reading this bit always returns "0".
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11.3 Registers of UART
MB91210 Series
[bit1] SCKE: Serial clock output enable
SCKE
Serial clock output enable
0
External clock input [initial value]
1
Internal clock output
This bit controls the I/O of the serial clock pin (SCK).
When this bit is "0", the SCK pin functions as a general-purpose port/serial clock input pin. When "1",
it becomes a serial clock output pin.
Note:
When using the SCK pin as a serial clock input (SCKE=0), set the port as an input port. When using
it as a serial clock output, settings of the SCKE bit and the port function register (PFR)
corresponding to the SCK pin are required. For details on the port function register settings, see
"CHAPTER 5 I/O PORTS". Also, select the external clock by using the external clock selection bit
(EXT=1).
[bit0] SOE: Serial data output enable bit
SOE
Serial data output
0
Disables SOT output [initial value]
1
Enables SOT output
This bit enables serial output.
When this bit is "1", serial data output is enabled.
Note:
When using the SOT pin as a serial output, settings of the SOE bit and the port function register
(PFR) corresponding to it are required. For details on the port function register settings, see
"CHAPTER 5 I/O PORTS".
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CHAPTER 11 LIN-UART
11.3 Registers of UART
11.3.3
MB91210 Series
Serial Status Register (SSR)
The serial status register (SSR) is used to check transmission/reception status and the
error status. In addition, it controls transmission/reception interrupts.
■ Serial Status Register (SSR)
Figure 11.3-4 Bit Configuration of Serial Status Register (SSR)
SSR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000062H
00006AH
000072H
0000B2H
0000BAH
0000C2H
0000CAH
PE
R
ORE
R
FRE
R
RDRF
R
TDRE
R
BDS
R/W
RIE
R/W
TIE
R/W
00001000B
R/W: Readable/writable
R:
Read only
[bit15] PE: Parity error flag bit
PE
Parity error
0
No parity error [initial value]
1
A parity error occurred during reception
This bit is set to "1" when a parity error occurs during reception. This bit is cleared when "1" is written
to CRE bit in the serial control register (SCR).
A reception interrupt request is output when this bit and the RIE bit are "1".
Data in the reception data register (RDR) is invalid if this flag is set.
[bit14] ORE: Overrun error flag bit
ORE
Overrun error
0
No overrun error [initial value]
1
An overrun error occurred during reception
This bit is set to "1" when an overrun error occurs during reception. This bit is cleared when "1" is
written to CRE bit in the serial control register (SCR).
A reception interrupt request is output when this bit and the RIE bit are "1".
Data in the reception data register (RDR) is invalid if this flag is set.
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11.3 Registers of UART
MB91210 Series
[bit13] FRE: Framing error flag bit
FRE
Framing error
0
No framing error [initial value]
1
A framing error occurred during reception
This bit is set to "1" when a framing error occurs during reception. This bit is cleared when "1" is
written to CRE bit in the serial control register (SCR).
A reception interrupt request is output when this bit and the RIE bit are "1".
Data in the reception data register (RDR) is invalid if this flag is set.
[bit12] RDRF: Reception data full flag bit
RDRF
Reception data register full
0
No data in the reception data register [initial value]
1
Data exists in the reception data register
This flag indicates the status of the reception data register (RDR).
This bit is set to "1" when reception data is stored in RDR. It is cleared to "0" only when RDR is read.
A reception interrupt request is output when this bit and the RIE bit are "1".
[bit11] TDRE: Transmission data empty flag bit
TDRF
Transmission data register empty
0
Data exists in the transmission data register
1
No data in the transmission data register [initial value]
This flag indicates the status of the transmission data register (TDR).
This bit is cleared to "0" when transmission data is written to TDR. It is set to "1" when data is stored in
the transmission shift register and transmission starts.
A transmission interrupt request is output when this bit and the TIE bit are "1".
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
[bit10] BDS: Transfer direction selection bit
BDS
Bit direction setting
0
Transmission/Reception is LSB first [initial value]
1
Transmission/Reception is MSB first
This bit selects whether to transfer serial transfer data from the LSB first (BDS=0) or the MSB first
(BDS=1).
This bit is fixed to "0" in mode 3 (LIN mode).
Note:
The upper side and lower side of the serial data will be interchanged while the serial data register is
read/written. The data will be invalid if the value of this bit is changed after the data was written to
RDR.
[bit9] RIE: Reception interrupt request enable bit
RIE
Reception interrupt enable
0
Disables reception interrupt [initial value]
1
Enables reception interrupt
This bit controls reception interrupt requests to CPU.
If this bit is set, a reception interrupt request will be output when the reception data flag bit (RDRF) is
"1" or when an error flag (PE, ORE, FRE) is set.
[bit8] TIE: Transmission interrupt request enable bit
TIE
Transmission interrupt enable
0
Disables transmission interrupt [initial value]
1
Enables transmission interrupt
This bit controls transmission interrupt requests to CPU.
If this bit is set, a transmission interrupt request will be output when TDRE bit is "1".
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
11.3.4
Reception/Transmission Data Register (RDR/TDR)
The reception data register (RDR) holds reception data and the transmission data
register holds transmission data. RDR and TDR are located at the same address.
■ Reception/Transmission Data Register (RDR/TDR)
Figure 11.3-5 Reception/Transmission Data Register (RDR/TDR)
RDR/TDR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000063H
00006BH
000073H
0000B3H
0000BBH
0000C3H
0000CBH
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
00000000B
R/W: Readable/writable
[bit7 to bit0] Data register
Access
Data register
Read
Reads from the reception data register
Write
Writes to the transmission data register
● Reception
RDR is the register that stores reception data. A serial data signal transmitted from the SIN pin is converted
at the shift register and then stored in this register. When the data length is 7 bits, the highest bit (D7)
becomes "0". When reception is completed, the data is stored in this register and the reception data full flag
bit (RDRF bit in SSR) is set to "1". Then, if reception interrupt request is enabled, a reception interrupt will
occur.
Read RDR when RDRF bit in SSR is "1". The RDRF bit is cleared automatically to "0" when RDR is read.
The reception interrupt is also cleared if it is enabled and no error has occurred.
● Transmission
When data to be transmitted is written to the transmission data register in transmission enabled state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output pin (SOT). If the data length is 7 bits, the highest bit (D7) is not sent.
When transmission data is written to this register, the transmission data empty flag bit (TDRE bit in SSR) is
cleared to "0". When transfer to the transmission shift register is completed, the bit is set to "1". When the
TDRE bit is "1", the next transmission data can be written to this register. If transmission interrupt request
has been enabled, a transmission interrupt occurs. Write the next data when a transmission interrupt occurs
or the TDRE bit is "1".
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11.3 Registers of UART
MB91210 Series
Note:
TDR is a write-only register and RDR is a read-only register. Because these registers are located at
the same address, the read value is different from the write value. Therefore, do not access them
using read-modify-write (RMW) instructions.
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11.3 Registers of UART
MB91210 Series
11.3.5
Extended Status/Control Register (ESCR)
The extended status/control register is used to set LIN functions. It also sets the setting
for direct access to the SIN and SOT pins and the setting for LIN-UART synchronous
clock mode.
■ Extended Status/Control Register (ESCR)
Figure 11.3-6 Bit Configuration of Extended Status/Control Register (ESCR)
ESCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000064H
00006CH
000074H
0000B4H
0000BCH
0000C4H
0000CCH
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
00000100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
[bit15] LBIE: LIN-Break detection interrupt enable bit
LBIE
LIN-Break detection interrupt enable
0
Disables LIN-Break interrupt [initial value]
1
Enables LIN-Break interrupt
This bit enables the interrupt that is generated when a LIN-Break is detected.
[bit14] LBD: LIN-Break detection flag bit
LIN-Break detection
LBD
Write
Read
0
Clears LIN-Break detection flag
No LIN-Break detected [initial value]
1
Ignored
LIN-Break detected
This bit is set to "1" when a LIN-Break is detected. Writing "0" clears this flag bit, and if LIN-Break
detection interrupt is enabled, it also clears the interrupt.
Although "1" is always returned when a read-modify-write (RMW) instruction is executed, this does not
mean a LIN-Break is detected.
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11.3 Registers of UART
MB91210 Series
[bit13, bit12] LBL1, LBL0: LIN-Break length selection bits
LBL0
LBL1
LIN-Break length
0
0
LIN-Break length is 13 bits [initial value]
1
0
LIN-Break length is 14 bits
0
1
LIN-Break length is 15 bits
1
1
LIN-Break length is 16 bits
These bits define the serial bit length of a LIN-Break generated in LIN-UART. The LIN-Break length
for reception is always 11 bits.
[bit11] SOPE: Serial output pin direct access enable bit
SOPE
Serial output pin direct access
0
Disables serial output pin direct access [initial value]
1
Enables serial output pin direct access
Setting this bit to "1" enables direct writing to the SOT pin.
For details, see Table 11.3-1.
[bit10] SIOP: Serial I/O pin direct access enable bit
Serial I/O pin access
SIOP
Write (when SOPE is "1")
0
SOT outputs "0"
1
SOT outputs "1" [initial value]
Read
Reads SIN value
Normal read instructions always return the value of the SIN pin. Writing sets the value of the SOT pin.
The value of the SOT is returned when a read-modify-write (RMW) instruction is executed.
For details, see Table 11.3-1.
Note:
Only when the TXE bit of serial control register (SCR) is "0", the set value to SIOP bit is valid.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
Table 11.3-1 Functions of SOPE and SIOP
SOPE
SIOP
Writing to SIOP
Reading from SIOP
0
R/W
No effect on SOT pin
Holds the written value
Reads the SIN value
1
R/W
Outputs the written value to SOT
pin
Reads the SIN value
1
RMW
Reads and writes the value of the SOT pin
[bit9] CCO: Continuous clock output enable bit
CCO
Continuous clock output (Mode 2)
0
Disables continuous clock output [initial value]
1
Enables continuous clock output
This bit enables a continuous serial clock output at the SCK pin if LIN-UART operates in master mode
2 (synchronous mode) and the SCK pin is set as output.
[bit8] SCES: Serial clock edge selection bit
SCES
Serial clock edge selection
0
Sampling on clock rising edge (normal) [initial value]
1
Sampling on clock falling edge (inverted clock)
This bit inverts the internal serial clock in the mode 2 (synchronous mode). The output clock is also
inverted if LIN-UART operates in the master mode 2 (synchronous mode) and the SCK pin is set as
output.
In slave mode 2, the sampling edge is switched from the rising edge to the falling edge.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
Extended Communication Control Register (ECCR)
11.3.6
The extended communication control register (ECCR) is used to set the bus idle
detection interrupt, set the synchronous clock and generate the LIN-Break.
■ Extended Communication Control Register (ECCR)
Figure 11.3-7 Bit Configuration of Extended Communication Control Register (ECCR)
ECCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000065H
00006DH
000075H
0000B5H
0000BDH
0000C5H
0000CDH
res
LBR
MS
SCDE
SSM
BIE
RBI
TBI
000000XXB
-
W
R/W
R/W
R/W
R/W
R
R
R/W:
R:
W:
X:
-:
Readable/writable
Read only
Write only
Undefined value
Undefined bit
[bit7] res: Reserved bit
This bit is a reserved bit. Always write "0".
[bit6] LBR: LIN-Break setting bit
LIN-Break setting
LBR
Write
0
Ignored [initial value]
1
Generates LIN-Break
Read
Read value is always "0"
Setting this bit to "1" in operation mode 0 or 3 generates a LIN-Break with the length specified by
LBL1 and LBL0 in ESCR.
[bit5] MS: Master/Slave mode selection bit
MS
Master/Slave function in mode 2
0
Master mode (serial clock generation) [initial value]
1
Slave mode (external serial clock reception)
This bit sets master or slave mode of LIN-UART in synchronous mode 2. If master is selected, LINUART generates a synchronous clock. If slave mode is selected, LIN-UART receives an external serial
clock.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
Note:
If slave mode is set, the clock source must be set to 1 to 1 external clock input (SCKE=0, EXT=1,
OTO=1 in SMR) as the external clock.
[bit4] SCDE: Serial clock delay enable bit
SCDE
Serial clock delay enable in mode 2
0
Disables clock delay [initial value]
1
Enables clock delay
If this bit is set when LIN-UART operates in mode 2, a serial output clock is delayed by 1 machine
cycle.
[bit3] SSM: Start/Stop bit mode enable
SSM
Asynchronous in mode 2
0
Disables start/stop bit mode in mode 2 [initial value]
1
Enables start/stop bit mode in mode 2
This bit is used to add a start bit and a stop bit for synchronization when LIN-UART operates in mode
2. This bit is fixed to "0" in other modes (modes 0, 1, and 3).
[bit2] BIE: Bus idle interrupt enable
BIE
Bus idle interrupt enable
0
Disables bus idle interrupt [initial value]
1
Enables bus idle interrupt
If neither reception nor transmission is being executed (RBI=1, TBI=1), this bit enables reception
interrupt.
Do not use this bit when SSM bit is "0" in the mode 2.
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11.3 Registers of UART
MB91210 Series
[bit1] RBI: Reception bus idle flag bit
RBI
Reception bus idle
0
Reception is active
1
Reception is stopped
This bit is set to "1" when no reception is done at the SIN pin.
Do not use this bit when SSM bit is "0" in mode 2.
[bit0] TBI: Transmission bus idle flag bit
TBI
Transmission bus idle
0
Transmission is active
1
Transmission is stopped
This bit is set to "1" when no reception is done at the SOT pin.
Do not use this bit when SSM bit is "0" in mode 2.
Note:
Do not use BIE, RBI and TBI bits when SSM bit is "0", if LIN-UART operation mode is set to mode 2.
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
11.3.7
Baud Rate/Reload Counter Register (BGR)
The baud rate/reload counter register (BGR) sets the division ratio for the serial clock.
Also accurate values of the transmission reload counter can be read.
■ Baud Rate/Reload Counter Register (BGR)
Figure 11.3-8 Baud Rate/Reload Counter Register (BGR)
BGR1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000066H
00006EH
000076H
0000B6H
0000BEH
0000C6H
0000CEH
-
B14
B13
B12
B11
B10
B09
B08
10000000B
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000067H
00006FH
000077H
0000B7H
0000BFH
0000C7H
0000CFH
B07
B06
B05
B04
B03
B02
B01
B00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BGR0
R/W: Readable/writable
-:
Undefined bit
[bit15] Reserved: Reserved bit
This bit is a reserved bit. Read value is always "1".
[bit14 to bit8] B14 to B08: Baud rate generator register 1
B14 to B08
Baud rate generator register 1
Write
Writes bit14 to bit8 of reload value to the counter
Read
Reads count bit14 to bit8
[bit7 to bit0] B07 to B00: Baud rate generator register 0
B07 to B00
CM71-10139-5E
Baud rate generator register 0
Write
Writes bit7 to bit0 of reload value to the counter
Read
Reads count bit7 to bit0
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CHAPTER 11 LIN-UART
11.3 Registers of UART
MB91210 Series
■ Baud Rate/Reload Counter Register
The baud rate reload counter register (BGR) sets the division ratio for the serial clock.
The register can be read/written by byte access or half-word access.
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
11.4
Interrupts of UART
LIN-UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the following causes:
• Reception data is stored in the reception data register (RDR), or a reception error
occurs.
• Transmission data is transferred from the transmission data register (TDR) to the
transmission shift register.
• A LIN-Break is detected
• Bus idle (no transmission/reception operations)
■ Interrupts of LIN-UART
Table 11.4-1 shows the interrupt control bits and interrupt sources.
Table 11.4-1 LIN-UART Interrupt Control Bit and Interrupt Source
Reception/ Interrupt
Transmis- request flag
sion/ICU
bit
Reception
Transmission
Operation mode
Flag
register
Interrupt source
0
1
2
3
Reception data is
written to RDR
RDRF
SSR
❍
❍
❍
❍
ORE
SSR
❍
❍
❍
❍ Overrun error
FRE
SSR
❍
❍
❍ Framing error
PE
SSR
❍
×
×
Parity error
LBD
ESCR
❍
×
❍
LIN-Synch-Break
detection
TBI & RBI
ESCR
❍
❍
TDRE
SSR
❍
❍
❍
❍
ICP
ICS
❍
×
×
ICP
ICS
❍
×
×
×
Interrupt
source
enable bit
How to clear the
interrupt request
Read reception data
SSR: RIE
Write "1" to the
reception error clear
bit (SCR: CRE)
ESCR: LBIE
Write "1" to LBD bit
in ESCR
ECCR: BIE
Transmit reception
data/transmission data
Transmission register
empty
SSR: TIE
Write transmission
data
❍
First falling edge of
LIN-Synch-Field
ICS: ICP
Disable ICP
temporarily
❍
5th falling edge of
LIN-Synch-Field
ICS: ICP
Disable ICP
❍ Bus idle
ICU
❍ : Available
: Available if SSM bit in ECCR is "1"
× : Not available
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
■ Reception Interrupts
If one of the following cases occurs in the reception mode, the corresponding flag bit in the serial status
register (SSR) is set to "1".
• Data reception completed: RDRF
When the reception data is transferred from the serial input shift register to the reception data register
(RDR) and therefore, reading is enabled.
• Overrun error: ORE
When RDRF=1 and RDR is not read from CPU.
• Framing error: FRE
When "0" is received while receiving a stop bit.
• Parity error: PE
When a wrong parity bit is detected.
If any of the above flags become "1" when the reception interrupt is enabled (SSR:RIE = 1), a reception
interrupt request is generated.
If the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". This is the only
way to clear the RDRF flag.
All error flags are cleared to "0" if "1" is written to the reception error flag clear bit (CRE) in the serial
control register (SCR).
Note:
Disable reception (RXE=0) and then clear reception error flags in CRE bit.
If the reception error flag is cleared without disabling reception, the reception is interrupted once and
then the reception is resumed.
By this operation, some data may not be received normally at the resume.
■ Transmission Interrupts
If transmission data is transferred from the transmission data register (TDR) to the transmission shift
register (it occurs when the shift register is empty and transmission data exists), the transmission data
register empty flag bit (TDRE) of the serial status register (SSR) is set to "1". In this case, an interrupt
request is generated if the transmission interrupt enable bit (TIE) in the SSR is set to "1".
Note:
Because the initial value of TDRE is "1", a transmission interrupt will be generated immediately after
the TIE bit is set to "1". The TDRE flag is reset only by writing to the transmit data register (TDR).
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
■ LIN-Synch-Break Interrupts
These interrupts are available when LIN-UART operates as a LIN slave in mode 0 or 3.
If the serial input bus becomes "0" (dominant) for more than 11-bit time, the LIN-Break detection flag bit
(LBD) in the extended status/control register (ESCR) is set to "1". In this case, the reception error flag is set
to "1" after 9-bit time. Therefore, set the RIE flag or the RXE flag to "0" if only LIN-Synch-Break
detection is desired. For other cases, wait until a reception error interrupt is generated first and LBD=1 is
set by interrupt process routine.
The interrupt and the LBD flag are cleared after "1" is written to the LBD flag. Then, CPU certainly detects
a LIN-Synch-Break for the following adjustment procedures of the serial clock to the LIN master.
■ LIN-Synch-Field Edge Detection Interrupts
These interrupts are available when LIN-UART operates as a LIN slave in the mode 0 or 3.
The falling edge of the reception bus after LIN-Break detection is indicated by LIN-UART. Simultaneously
an interrupt signal connected to the ICU is set to "1". This signal will be reset after the 5th falling edge of
the LIN-Synch-Field. In either case, the ICU generates an interrupt, if the both edge detection and the ICU
interrupt are enabled. The difference of the counter values detected by ICU is 8 times as the serial clock.
The baud rate for the dedicated reload counter can be calculated using this result.
There is no need to restart the reload counter, because it is automatically reset if a falling edge of a start bit
is detected.
■ Bus Idle Interrupts
When no reception operation is performed at the SIN pin, the RBI flag bit in ECCR is set to "1". Similarly,
when no transmission operation is performed at the SOT pin, the TBI flag bit is set to "1". An interrupt will
be generated when both bus idle flags (TBI and RBI) are "1" if the bus idle enable bit (BIR) in ECCR is set.
Note:
If "0" is written to the SIOP bit when the SOPE is "1", the TBI flag becomes "0" even if no bus
operation exists. TBI bit and RBI bit cannot be used if SSM bit in ECCR register is "0" in
synchronous mode 2.
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
Figure 11.4-1 shows a bus idle interrupt generation.
Figure 11.4-1 Bus Idle Interrupt Generation
Transmission
data
Reception
data
TBI
RBI
Reception IRQ
: Start bit
354
: Stop bit
: Data bit
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
11.4.1
Reception Interrupt Generation and Flag Set Timing
This section explains the reception interrupt sources, reception completion (RDRF bit in
SSR) and reception errors (PE, ORE, FRE bits in SSR).
■ Reception Interrupt Generation and Flag Set Timing
A reception interrupt is generated when data reception is completed (RDRF=1) if the reception interrupt
enable flag bit (RIE) in the serial status register (SSR) is set to "1". This interrupt is generated when a stop
bit is detected in mode 0, mode 1, mode 2 (if SSM is "1"), mode 3, or the last data bit is read in mode 2 (if
SSM is "0").
Note:
If a reception error has occurred, contents of the reception data register become invalid in each
mode.
Figure 11.4-2 Reception Operation and Flag Set Timing
Reception data
(mode 0/mode 3)
ST
D0
D1
D2
D5
D6
D7/
P
SP
ST
Reception data
(mode 1)
ST
D0
D1
D2
D6
D7
A/D
SP
ST
D0
D1
D2
D4
D5
D6
D7
D0
Reception data
(mode 2)
PE*1, FRE
RDRF
ORE*2
(When RDRF=1)
Reception interrupt occurred
*1: PE flag is always "0" in modes 1 and 3.
*2: ORE occurs if the reception data is not read by CPU and another data is received.
ST: Start bit SP: Stop bit
A/D: Mode 1 (multiprocessor) address data selection bit
Note:
Not all reception options for mode0 and mode 3 are shown in Figure 11.4-2.
It shows "7p1" and "8N1" (p="E"[even], or "O"[odd]).
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
Figure 11.4-3 ORE Setting Timing
Reception
data
RDRF
ORE
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
11.4.2
Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the next transmission data is ready to be
written to the transmission data register (TDR).
■ Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the next data is ready to be written to the transmission data
register (TDR). A transmission interrupt is generated when the TDR becomes empty, if the transmission
interrupt enable bit (TIE) in the serial status register (SSR) is set to "1" to enable transmission interrupt.
The transmission register empty (TDRE) flag bit in SSR indicates that TDR is empty. The TDRE bit is for
read only. The flag can be cleared only by writing data into TDR.
Figure 11.4-4 shows a transmission operation and flag set timing.
Figure 11.4-4 Transmission Operation and Flag Set Timing
Mode 0, mode 1,
mode 3:
Write to TDR
Transmission interrupt
occurred
Transmission interrupt
occurred
TDRE
Serial output
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmission interrupt
occurred
P
P
SP ST D0 D1 D2 D3 D4 D5 D6 D7
SP
AD
AD
Transmission interrupt
occurred
Mode 2 (SSM = 0):
Write to TDR
TDRE
Serial output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
ST: Start bit D0 to D7: Data bits P: Parity
AD: Address data selection bit (mode 1)
SP: Stop bit
Note:
Not all transmission options in mode 0 are shown in the example shown in Figure 11.4-4.
It shows "8p1" (p="E"[even] or "O"[odd]). No parity is added when SSM bit is the "0" in modes 3 and
2.
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CHAPTER 11 LIN-UART
11.4 Interrupts of UART
MB91210 Series
■ Transmission Interrupt Request Generation Timing
A transmission interrupt request is generated when TDRE flag becomes "1" if transmission interrupt is
enabled (TIE bit in SSR is "1").
Note:
The initial value of TDRE bit is "1". Therefore, a transmit interrupt is generated immediately after the
transmit interrupt is enabled (TIE = 1). TDRE is read-only. The TDRE flag can be cleared only by
writing data into the transmission data register (TDR). Be sure to carefully specify the timing for
enabling transmission interrupt.
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CHAPTER 11 LIN-UART
11.5 UART Baud Rates
MB91210 Series
11.5
UART Baud Rates
One of the following can be selected for the LIN-UART serial clock:
• Dedicated baud rate generator (reload counter)
• External clock (clock input from SCK pin)
• Using external clock for baud rate generator (reload counter)
■ LIN-UART Baud Rate Selection
Figure 11.5-1 shows the baud rate selection circuit (reload counter). One of the following three types of
baud rates can be selected:
● Using Dedicated Baud Rate Generator (Reload Counter)
LIN-UART has an independent reload counter for each transmission and reception serial clock. The baud
rate is set using the 15-bit reload value of the baud rate generator register (BGR).
The reload counter divides the machine clock by the value set in the baud rate generator register.
● Using External Clock (1 to 1 mode)
A clock input from the LIN-UART clock input pin (SCK) is used directly as the baud rate.
● Using External Clock for Dedicated Baud Rate Generator
An external clock can be connected to the reload counter inside the device. In this mode, the external clock
is used instead of the internal machine clock.
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CHAPTER 11 LIN-UART
11.5 UART Baud Rates
MB91210 Series
Figure 11.5-1 Baud Rate Selection Circuit (Reload Counter)
REST
Start bit
Falling edge detection
Reload value: v
Set
Rxc = 0?
Reception
15-bit reload counter
Reload
0
F/F
Reception
clock
Reset
Rxc = v/2?
1
Reload value: v
EXT
Set
Txc = 0?
CLK
SCK
(External
clock
input)
0
1
Transmission
15-bit reload counter
Counter value: TXC
Reload
0
F/F
Reset
Txc = v/2?
1
OTO
Transmission
clock
Internal data bus
EXT
REST
OTO
360
SMRn
register
B14
B13
B12
B11
B10
B09
B08
BGRn1
register
B07
B06
B05
B04
B03
B02
B01
B00
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BGRn0
register
CM71-10139-5E
CHAPTER 11 LIN-UART
11.5 UART Baud Rates
MB91210 Series
11.5.1
Baud Rate Setting
This section shows baud rate settings and the calculation result of serial clock
frequency.
■ Baud Rate Calculation
The baud rate generator (BGR) sets the 15-bit reload counter.
Use the following formula for the baud rate calculation.
v = [φ/b] - 1
"φ" is a machine clock frequency and "b" is a baud rate.
● Example of Calculation
If the machine clock is 16 MHz and the desired baud rate is 19200 bps, then the reload value "v" is:
v = [16 × 106 / 19200] - 1 = 832
For the actual baud rate, recalculate it as follows:
bexact = φ / (v + 1) = 16 × 106 / 833 = 19207.6831 bps
Note:
If the reload value set is to "0", the reload counter will stop. For this reason, the minimum division
ratio is 2.
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CHAPTER 11 LIN-UART
11.5 UART Baud Rates
MB91210 Series
■ Examples of Baud Rate Settings for Each Machine Clock Frequency
Table 11.5-1 shows examples of baud rate settings for each machine clock.
Table 11.5-1 Examples of Baud Rate Settings for Each Machine Clock
Baud
rate
(bps)
8MHz
16MHz
20MHz
24MHz
32MHz
value
dev.
value
dev.
value
dev.
value
dev.
value
dev.
4M
-
-
-
-
4
0
5
0
7
0
2M
-
-
7
0
9
0
11
0
15
0
1M
7
0
15
0
19
0
23
0
31
0
500000
15
0
31
0
39
0
47
0
63
0
460800
-
-
-
-
-
-
51
-0.16
68
-0.64
250000
31
0
63
0
79
0
95
0
127
0
230400
-
-
-
-
-
-
103
-0.16
138
0.08
153600
51
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
127
0
159
0
191
0
255
0
115200
68
-0.64
138
0.08
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
277
0.08
346
-0.06
416
0.08
555
0.08
38400
207
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
0
1535
0
1919
0
2303
0
3071
0
9600
832
-0.04
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
-0.01
2221
-0.01
2777
0.01
3332
-0.01
4443
-0.01
4800
1666
0.02
3332
-0.01
4166
0.01
4999
0
6666
0
2400
3332
-0.01
6666
0
8332
0
9999
0
13332
0
1200
6666
0
13332
0
16666
0
19999
0
26666
0
600
13332
0
26666
0
-
-
-
-
-
-
300
26666
0
-
-
-
-
-
-
-
-
Note:
Deviations are given in %.
The maximum synchronous baud rate is the machine clock divided by 5.
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11.5 UART Baud Rates
MB91210 Series
■ Using External Clock
If EXT bit in SMR is set, the external pin SCK is selected as a clock. The external clock signal is used in
the same way as the internal MCU clock. It is designed to use the reload counter for selecting all the baud
rates of PC-16550-UART by connecting, for example, the 1.8432 MHz crystal oscillator to the SCK pin.
If "1to1" external clock input mode (OTO bit in SMR) is selected, the SCK signal is directly connected to
the LIN-UART serial clock input. This is needed for the LIN-UART synchronous mode 2 operating as
slave device.
Note:
In each case, the clock signal is synchronized with MCU clock inside the LIN-UART. This means that
indivisible clock ratio will result in unstable signals.
■ Counting Example
Figure 11.5-2 shows a counting example of transmission/reception reload counter. Assume that the reload
value is 832.
Figure 11.5-2 Counting Example of Reload Counter
Transmission reception
clock
Reload count
001
000
832
831
830
829
828
827
412
411
410
Reload count value
Transmission reception
clock
Reload count
417
416
415
414
413
Note:
The falling edge of a serial clock signal always occurs after |(v + 1) / 2|.
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CHAPTER 11 LIN-UART
11.5 UART Baud Rates
11.5.2
MB91210 Series
Restart of Reload Counter
The reload counters can be restarted for the following reasons:
(For both transmission/reception reload counters)
• MCU reset
• LIN-UART software clear (UPCL bit in SMR)
• LIN-UART software restart (REST bit in SMR)
(For reception reload counter only)
• Start bit falling edge detection in asynchronous mode
■ Software Restart
If REST bit in the serial mode register (SMR) is set, both transmission/reception reload counters will be
restarted at the next clock cycle. This feature is intended to use the transmission reload counter as a timer.
Figure 11.5-3 shows an example of the reload counter restart. Assume that the reload value is 100.
Figure 11.5-3 Example of Reload Counter Restart
Operating clock
Reload counter
clock output
REST
Reload value
37
36 35 100 99
98
97
96
95
94
93
92
91
90
89 88
87
Read BGR0/BGR1
Data bus
90
: don’t care
In this example, the number of MCU clock cycles (cyc) after REST is as follows:
cyc = v - c + 1 = 100 - 90 + 1 = 11
In this case "v" is a reload value and "c" is a read counter value.
Note:
If LIN-UART is reset by UPCL bit in SMR, the reload counters will also be restarted.
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CHAPTER 11 LIN-UART
11.5 UART Baud Rates
MB91210 Series
■ Automatic Restart
If a falling edge of a start bit is detected in asynchronous LIN-UART mode, the reception reload counter is
restarted. This is intended to synchronize the serial input shift register with the input serial data.
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CHAPTER 11 LIN-UART
11.6 Operations of UART
11.6
MB91210 Series
Operations of UART
LIN-UART operates as normal bidirectional serial communication in the operation mode
0. In the mode 2 and mode 3, it performs bidirectional communication as master or
slave. In the mode 1, it performs multiprocessor communication as master or slave.
■ Operations of LIN-UART
● Operation Mode
There are four LIN-UART operation modes: mode 0 to mode 3. Table 11.6-1 shows the LIN-UART
operation modes.
Table 11.6-1 LIN-UART Operation Modes
Data length
Operation mode
No parity
0 Normal mode
7 bits or 8 bits
1 Multiprocessor mode
7 bits or
8 + 1 bits *2
2 Normal mode
3 LIN mode
With parity
-
8 bits
8 bits
-
SynchronizaStop bit length
tion
Data
direction*1
Asynchronous
1 bit or 2 bits
LSB first/
MSB first
Asynchronous
1 bit or 2 bits
LSB first/
MSB first
Synchronous
0, 1 bit or 2 bits
LSB first/
MSB first
Asynchronous
1 bit
LSB first
*1: This indicates transfer data format (LSB first, MSB first).
*2: "+1" means the indicator bit of the address/data part given instead of parity in the multiprocessor
mode.
Note:
Mode 1 supports both for master and slave operations of LIN-UART in a master/slave connection
system. In the mode 3, the LIN-UART function is fixed to 8N1-format, LSB first.
If the mode is changed, LIN-UART stops all transmission and reception operations, and then starts
the next operation.
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11.6 Operations of UART
MB91210 Series
■ Inter-CPU Connection Method
External clock "1to1" connection (normal mode) and master/slave connection (multiprocessor mode) can
be selected. Data length, parity setting, synchronization type must be the same among all CPUs in all the
connections.
The operation mode must be selected as follows:
• For "1to1" connection method, operation mode 0 for asynchronous transfer mode or operation mode 2
for synchronous transfer mode must be set in the two CPUs. A CPU has to be set as master and the other
as slave in the synchronous mode 2.
• Select operation mode 1 for the master/slave connection method and use it as either master or slave
system.
■ Synchronization Method
In the asynchronous operation mode, LIN-UART reception clock is automatically synchronized with a
falling edge of the reception start bit.
In the synchronous operation mode, the synchronization is performed either by the clock signal of the
master device or by LIN-UART itself if operating as master.
■ Signal Mode
LIN-UART handles data as NRZ format.
■ Operation Enable Bit
LIN-UART controls transmission and reception using the operation enable bit for transmission (TXE bit in
SCR) and reception (RXE bit in SCR). If the operation is disabled, it stops at the following status:
• If reception operation is disabled during reception (data input to the reception shift register), the
reception operation will stop immediately.
• If transmission operation is disabled during transmission (data output from the transmission shift
register), the transmission operation will stop immediately.
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CHAPTER 11 LIN-UART
11.6 Operations of UART
11.6.1
MB91210 Series
Operation in Asynchronous Mode (Operation Mode 0 and
Mode 1)
When LIN-UART is used in the operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), asynchronous transfer mode is selected.
■ Transfer Data Format
Data transfer in asynchronous operation mode starts with a start bit ("L" level) and ends with a stop bit
(bit1 at minimum, "H" level). The direction of the bit stream (LSB first or MSB first) is determined by
BDS bit in the serial status register (SSR). If parity is enabled, a parity bit is placed between the last data bit
and the stop bit.
In operation mode 0, the length of the data frame is 7 or 8 bits including an address/data delimiter bit used
instead of a parity bit. The stop bit length can be selected between 1 bit and 2 bits.
The calculation formula for the bit length of a transfer frame is:
Bit length = 1 + d + p + s
(d = data bit [7bits or 8bits], p = parity bit [0bit or 1bit], s = stop bit [1bit or 2bits])
Figure 11.6-1 Transfer Data Format (Operation Mode 0, 1)
*1
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
*2
SP
AD
SP
SP
*1: D7 (bit7): If data length is 8 bits with no parity
P (bit7): If data length is 8 bits with parity
*2: If SBL bit in SCR is 1
ST: Start bit
SP: Stop bit
AD: Address data selection bit (mode 1)
Note:
If BDS bit in the serial status register (SSR) is set to "1" (MSB first), the bit stream is processed as
D7, D6, ..., D1, D0, (P).
If 2 bits is selected for stop bit, both bits will be detected during reception, however, the reception data full
flag (RDRF) will be set to "1" at the 1st stop bit. The bus idle flag (RBI bit in ECCR) will be set to "1" after
the 2nd stop bit if no further start bit is detected. (The 2nd stop bit indicates bus activity.)
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
■ Transmission Operation
If the transmission data register empty flag (TDRE) bit in the serial status register (SSR) is set to "1", it is
enabled to write data to the transmission data register (TDR). Once data is written, TDRE flag becomes
"0". Once the transmission operation is enabled by TXE bit in the serial control register (SCR), data is
written to the transmission shift register and the transmission starts at the next serial clock cycle, beginning
with the start bit. Thereby TDRE flag becomes "1", so that the next data can be written to TDR.
If transmission interrupt is enabled (TIE=1), an interrupt is generated by TDRE flag. Because the initial
value of TDRE flag is "1", an interrupt will occur immediately once the TIE bit is set to "1".
When the bit length is set to 7 bits (CL=0), the highest bit in TDR (MSB) becomes an unused bit regardless
of the bit direction (LSB first or MSB first) set by BDS bit.
■ Reception Operation
Reception is operated when it is enabled by RXE flag bit in SCR. If a start bit is detected, a data frame is
received according to the format specified by SCR. If an error occurs, the corresponding error flag is set
(PE, ORE, FRE). After receiving the data frame, the data is transferred from the serial shift register to the
reception data register (RDR) and the reception data register full flag (RDRF) bit in SSR is set. The data
has to be read by CPU to clear RDRF flag. If reception interrupt is enabled (RIE=1), an interrupt is will be
generated by RDRF.
When the bit length is set to 7 bits (CL=0), the highest bit in RDR (MSB) becomes an unused bit regardless
of the bit direction (LSB first or MSB first) set by BDS bit.
Note:
If RDRF flag is set and no error has occurred, the data in the reception data register (RDR) is valid.
For the period when the reception bus level is at "H", set the reception enable flag (RXE) to "1".
■ Stop Bit
In transmission, the stop bit can be selected between 1 bit and 2 bits. When it is set to 2 bits, both bits will
be detected. This is because the stop bit is used to set properly the reception bus idle flag (RBI) in ECCR
after the second stop bit.
■ Error Detection
In mode 0, parity, overrun, and framing errors can be detected.
In mode 1, overrun and framing errors can be detected. Parity is not supported in this mode.
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11.6 Operations of UART
MB91210 Series
■ Parity
In mode 0 (and in mode 2, in case SSM bit in ECCR is set), LIN-UART performs parity calculation (when
transmission) and parity detection and check (when receiving) using the parity enable (PEN) bit in the
serial control register (SCR).
P bit in SCR sets odd parity or even parity.
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11.6 Operations of UART
MB91210 Series
11.6.2
Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used in LIN-UART operation mode 2 (normal
mode).
■ Transfer Data Format
In synchronous mode, 8-bit data is transferred without start/stop bits if SSM bit in the extended
communication control register (ECCR) is "0". The data format in mode 2 depends on the clock signal.
Figure 11.6-2 shows the transfer data format (operation mode 2).
Figure 11.6-2 Transfer Data Format (Operation Mode 2)
Transfer and reception data
(ECCR:SSM=0, SCR:PEN=0)
D0
D1
D2
D3
D4
D5
D6
D7
Transfer and reception data
(ECCR:SSM=1, SCR:PEN=0)
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
*
SP
Transfer and reception data
(ECCR:SSM=1, SCR:PEN=1)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
*
SP
*: If stop bit setting is 2 bits (SCR: SBL bit =1)
ST: Start bit
SP: Stop bit
P: Parity bit
■ Clock Inversion and Start/Stop Bits in Mode 2
If SCES bit in the extended status/control register (ESCR) is set, the serial clock is inverted. Therefore, in
slave mode LIN-UART, data is fetched at a falling edge of the reception serial clock. The mark level of the
clock signal becomes "0" when SCES bit is set to "1" in master mode. If SSM bit in the extended
communication control register (ECCR) is set, start and stop bits is added in the same way as asynchronous
mode.
Figure 11.6-3 Transfer Data Format with Clock Inversion
Mark level
Transmission and reception clock
(SCES = 0, CCO = 0):
Transmission and reception clock
(SCES = 1, CCO = 0):
Transmission and reception data
(SSM=1)
(No parity, with 1 stop bit)
Mark level
ST
SP
Data frame
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
■ Clock Supply
In clock synchronous mode (normal), the number of transmission bits and the number of reception bits is
equal to the number of the clock cycles. If asynchronous communication is set, the number of the clock
cycles is equal to the one with start/stop bits added.
When the internal clock is selected (dedicated reload timer), data received in synchronization with the
clock will be generated after automatically after data is transmitted.
When the external clock is selected, data is stored in the transmission data register and the clock cycle for
each bit to be output is supplied from the outside and generated. If SCES is "0", the mark level ("H") is
retained before starting transmission and after completing transmission.
The transmission clock signal is delayed by one machine cycle by setting SCDE bit in ECCR to enable and
stabilize transmission data at any falling edge of the clock (it is required when a receiving device fetches
data at the rising or falling edge of the clock). This function will be stopped by setting CCO.
Figure 11.6-4 Delayed Transmission Clock Signal (SCDE=1)
Transmission and
reception data writing
Reception data sampling point (SCES=0)
Mark level
Transmission and
reception clock (normal)
Mark level
Transmission and
reception clock
(SCDE = 1)
Transmission and
reception data
Mark level
0
1
LSB
1
0
1
0
0
1
MSB
Data
When the serial clock edge selection (SCES) bit of ESCR is set, LIN-UART clock signal is inverted and
reception data is fetched at a falling edge of the serial clock. In this case, the serial data must be valid at the
timing of the clock falling edge.
In master mode, when CCO bit in the extended status/control register (ESCR) is set, the serial clock is
output from SCK pin continuously. In this mode, use start and stop bits in order to specify the beginning
and end of the data frame for the reception side. Figure 11.6-5 shows the continuous clock output in mode
2.
Figure 11.6-5 Continuous Clock Output in Mode 2
Transmission and reception clock
(SCES = 0, CCO = 1):
Transmission and reception clock
(SCES =1, CCO = 1):
Transmission and reception data
(SSM=1)
(No parity, with 1 stop bit)
ST
SP
Data frame
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11.6 Operations of UART
MB91210 Series
■ Error Detection
If no start/stop bits are used (SSM = 0 in ECCR), only overrun errors are detected.
■ Communication
To initialize the synchronous communication mode, the following settings are required:
• Baud rate generator register (BGR)
Set a reload value for the dedicated baud rate reload counter
• Serial mode register (SMR)
MD1, MD0: 10B (mode 2)
SCKE: "1" (uses the dedicated baud rate reload counter)
"0" (external clock input)
• Serial control register (SCR)
RXE, TXE: Set the flags bit to "1"
SBL, AD: No stop bit, no address/data delimiter, the value is invalid.
CL: 8-bit fixed automatically, the value is invalid.
CRE: "1" (Error flags are cleared for initialization, and transmission/reception stop.)
If SSM=0: No parity, setting values of PEN and P are invalid.
If SSM=1: PEN, P settings are valid.
• Serial status register (SSR)
BDS: "0" (LSB first), "1" (MSB first)
RIE: "1" (interrupt enabled) , "0" (interrupt disabled)
TIE: "1" (interrupt enabled) , "0" (interrupt disabled)
• Extended communication control register (ECCR)
SSM: "0" (no start/stop bit, normal)
"1" (with start/stop bit, special)
MS: "0" (master mode, LIN-UART generates a serial clock.)
"1" (slave mode, LIN-UART receives a serial clock from outside.)
To start communication, write data into the transmission data register (TDR). To perform only reception,
stop the output using the serial output enable (SOE) bit in SMR, and then write dummy data into TDR.
Note:
Continuous clock and start/stop bit and bidirectional communication are enabled as in the
asynchronous mode.
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CHAPTER 11 LIN-UART
11.6 Operations of UART
11.6.3
MB91210 Series
Operation with LIN Function (Operation Mode 3)
LIN-UART can be used as either LIN master device or LIN slave device. The LIN function
is assigned as mode 3. If LIN-UART is set to mode 3, the data format is set to 8N1, LSB
first format.
■ LIN-UART as LIN Master
In LIN master mode, because the master determines the baud rate of the whole bus, slave devices
synchronizes with the master. Therefore the baud rate set by the master operation after initialization will be
retained.
When "1" is written to LBR bit in the extended communication control register (ECCR), "L" level is output
for a 13-bit to 16-bit time to SOT pin. This is the start of LIN-Sync-Break and a LIN message.
Thereby TDRE flag in the serial status register (SSR) becomes "0". After the break, this bit is initialized to
"1" and if TIE bit in SSR bit is "1", a transmission interrupt is output to CPU.
The length of a Sync-Break to be sent can be determined by the LBL1 and LBL0 bits of ESCR as shown in
Table 11.6-2.
Table 11.6-2 LIN-Break Length
LBL1
LBL0
Break length
0
0
13-bit time
0
1
14-bit time
1
0
15-bit time
1
1
16-bit time
Synch-Field can be transmitted as 1 byte 55H after LIN-Break. To avoid a transmission interrupt, 55H can
be written to TDR by writing "1" to LBR even if TDRE flag is "0". The transmission shift register waits
until LIN-Break ends and the shift the TDR value. In this case, no interrupt will be generated after a LINBreak and before a start bit.
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11.6 Operations of UART
MB91210 Series
■ LIN-UART as LIN Slave
In LIN slave mode, LIN-UART synchronizes with the baud rate of its master. The LIN-UART generates a
reception interrupt when a Synch-Break of the LIN master is detected and LBD flag in ESCR indicates it, if
reception is disabled (RXE=0) and LIN-Break interrupt is enabled (LBIE=1). Writing "0" to this bit clears
the interrupt.
Then, LIN-UART analyzes the baud rate of the LIN master. The LIN-UART detects the first falling edge
of the Synch-Field. The LIN-UART reports it to the input capture (ICU) via internal signal and resets the
signal sent to ICU at the 5th falling edge. Therefore, ICU must be set as a LIN input capture to enable ICU
interrupts. The correct baud rate of the LIN master is calculated by dividing by 8 a period of time that the
signal to ICU is "1".
The baud rate setting value is calculated as follows.
• Without timer overflow: BGR value = (b - a) / 8
• With timer overflow
: BGR value = (Max + b - a) / 8
"Max" means the maximum value of timer, "a" means the ICU counter register value after the first
interrupt, and "b" means the ICU counter register value after the second interrupt.
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11.6 Operations of UART
MB91210 Series
■ LIN-Synch-Break Detection Interrupt and Flag
If a LIN-Synch-Break is detected in slave mode, the LIN-Break detection (LBD) flag in ESCR is set to "1".
This causes an interrupt if LIN-Break interrupt enable (LBIE) bit is set.
Figure 11.6-6 LIN-Synch-Break Detection and Flag Set Timing
Serial clock
number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial clock
Serial input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
If RXE=1, a reception interrupt occurs.
If RXE=0, a reception interrupt occurs.
Figure 11.6-6 shows LIN-Synch-Break detection and the flag set timing.
Set RXE to "0" when using a LIN-Break since the reception data framing error (FRE) flag bit in SSR
generates a reception interrupt 2-bit time ("8N1") earlier than a LIN-Break interrupt, if reception interrupt
is enabled (RIE=1) in reception enabled state (RXE=1).
LBD is available in operation modes 0 and 3.
Figure 11.6-7 LIN-UART Operation in LIN Slave Mode
Serial clock
Serial input
(LIN bus)
LBR clear
by CPU
LBD
ICU input
Synch-Break (if 14-bit setting)
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11.6 Operations of UART
MB91210 Series
■ LIN Bus Timing
Figure 11.6-8 LIN Bus Timing and LIN-UART Signal
Old serial clock
No clock
(calculation frame)
Newly calculated
serial clock
ICU count
LIN bus
(LSYN)
RXE
LBD
(IRQ0)
LBIE
ICU input
IRQ (ICU)
RDRF
(IRQ0)
RIE
RDR read
by CPU
Reception interrupt is
enabled
LIN break starts
LIN break is detected, interrupt occurs
IRQ is clear by CPU (LBD->0)
IRQ (ICU)
IRQ clear: ICU start
IRQ (ICU)
IRQ clear: baud rate is calculated and set
LBIE disable
Reception enable
Start bit falling edge
1 byte of reception data is stored in RDR
RDR is read by CPU
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CHAPTER 11 LIN-UART
11.6 Operations of UART
11.6.4
MB91210 Series
Direct Access to Serial Pins
LIN-UART can access directly to values of the transmission pin (SOT) and reception pin
(SIN).
■ LIN-UART Pin Direct Access
The LIN-UART has the function to access directly to values of the serial input pin/serial output pin using
software. Serial input data can be monitored by reading SIOP bit in ESCR. If the serial output pin direct
access enable (SOPE) bit in ESCR is set, the software can fix the output value of SOT pin. This access is
available only when the transmission shift register is empty, for example, no transmission operation is
performed.
In LIN mode, this function is used for reading back the own transmission data. It is also used for error
handling if any physical failure exists on the single-wire LIN bus.
Note:
SIOP holds the last written value. Write a value to SIOP pin before setting for the access to output
pin to prevent undesired edge output.
When an access of a read-modify-write (RMW) instruction to SIOP bit is performed, the value of SOT
pin is returned. With a normal read instruction, the value of SIN pin is returned.
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
11.6.5
Bidirectional Communication Function (Normal Mode)
In operation mode 0 and mode 2, normal serial bidirectional communication is available.
Select operation mode 0 for asynchronous communication and operation mode 2 for
synchronous communication.
■ Bidirectional Communication Function
Figure 11.6-9 shows the settings of LIN-UART for normal mode (operation mode 0, 2).
Figure 11.6-9 LIN-UART Settings for Operation Mode 0 and 2
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR, SMR
PEN
P
SBL
CL
Mode 0 →
Mode 2 →
SSR, TDR/
RDR
+
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
×
0
0
0
×
0
1
0
PE ORE FRE RDRF TDRE BDS RIE
0
0
0
0
0
0
1
Conversion data is set (when write)
Reception data is retained (when read)
TIE
Mode 0 →
Mode 2 →
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 0 →
Mode 2 →
×
1
0
+
×
×
×
×
×
-
LBR MS SCDE SSM BIE
×
×
×
RBI
TBI
×
×
: Used bit
: Unused bit
: Set "1"
: Set "0"
: Used when SSM=1 (synchronous start/stop bits)
: Bit automatically set correctly
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
■ Inter-CPU Connection
Figure 11.6-10 shows an example of the bidirectional communication connection in LIN-UART operation
mode 2.
Figure 11.6-10 Example of Bidirectional Communication Connection in LIN-UART Mode 2
SOT
SOT
SIN
SIN
SCK
Output
Input
CPU-1 (master)
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SCK
CPU-2 (slave)
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
11.6.6
Master/Slave Communication Function (Multiprocessor
Mode)
In master/slave mode, LIN-UART enables to communicate with multiple CPUs for both
master and slave systems.
■ Master/Slave Communication Function
Figure 11.6-11 shows the settings of LIN-UART for operation mode 1.
Figure 11.6-11 LIN-UART Settings for Operation Mode 1
bit 15
SCR, SMR
Mode 1 →
SSR,
TDR/RDR
14
13
12
11
10
9
PEN
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
+
×
0
×
1
0
+
6
1
5
0
4
0
3
0
2
0
1
0
1
Conversion data is set (when write)
Reception data is retained (when read)
TIE
×
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 1 →
7
0
PE ORE FRE RDRF TDRE BDS RIE
Mode 1 →
8
×
×
×
×
×
-
LBR MS SCDE SSM BIE
×
×
×
×
RBI
TBI
×
: Used bit
: Unused bit
: Set "1"
: Set "0"
: Bit automatically set correctly
■ Inter-CPU Connection
Figure 11.6-12 shows a communication system consisting of one master CPU and multiple slave CPUs
connected by two communication lines. LIN-UART can be used for the master or slave.
Figure 11.6-12 Example of LIN-UART Master/Slave Communication Connection
SOT
SIN
Master CPU
SOT
SIN
Slave CPU #0
CM71-10139-5E
SOT
SIN
Slave CPU #1
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
■ Function Part
For master/slave communication, set the operation mode and data transfer mode as shown in Table 11.6-3.
Table 11.6-3 Master/Slave Communication Function Settings
Operation mode
Master
CPU
Address
Mode 1
transmission and (AD bit
reception
issuance)
Data
Parity
Slave CPU
Mode 1
(AD bit
reception)
AD=1 + 7-bit or
8-bit address
Synchronization method
-
-
AD=0 + 7-bit or
8-bit data
Bit direction
None
Asynchronous
Data
transmission and
reception
Stop bit
1 bit or
2 bits
LSB first or
MSB first
-
■ Communication Procedure
The communication starts when the master CPU transmits address data. The AD bit in the address data is
set to "1", and the CPU applicable for communication is selected. Each slave CPU checks the address data.
When the address data indicates the address assigned to a slave CPU, the slave CPU communicates with
the master CPU (normal mode).
Figure 11.6-13 shows a flowchart for master/slave communication (multiprocessor mode).
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
Figure 11.6-13 Master/Slave Communication Flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set to operation mode 1
Set to operation mode 1
Set SIN pin as serial data
input
Set SOTn pin as serial data
output
Set SIN pin as serial data
input
Set SOTn pin as port input
Set 7 or 8 data bits
Set 1 or 2 stop bits
Set 7 or 8 data bits
Set 1 or 2 stop bits
Set AD bit to "1"
Enable transmission reception
operation
Enable transmission reception
operation
Receive byte
Transmit address to slave
AD bit = 1?
NO
Wait
YES
Bus idle
interrupt
Slave address
matched?
NO
Set AD bit to "0"
YES
Communicate with master
CPU
Communicate with slave
CPU
Terminate
communication?
NO
YES
Terminate
communication?
NO
YES
Communicate with
another CPU?
NO
YES
Disable transmission reception
operation
End
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CHAPTER 11 LIN-UART
11.6 Operations of UART
11.6.7
MB91210 Series
LIN Communication Function
LIN-UART communication with LIN devices is available for both LIN master and LIN
slave systems.
■ LIN Master/Slave Communication Function
Figure 11.6-14 shows the settings of LIN-UART for operation mode 3 (LIN).
Figure 11.6-14 LIN-UART Settings for Operation Mode 3 (LIN)
bit 15
SCR, SMR
14
13
12
11
PEN
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
+
×
+
+
Mode 3 →
SSR,
TDR/RDR
×
10
9
0
×
6
1
5
0
4
0
3
0
2
0
1
0
1
Conversion data is set (when write)
Reception data is retained (when read)
TIE
+
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 3 →
×
1
0
+
7
1
PE ORE FRE RDRF TDRE BDS RIE
Mode 3 →
8
×
0
-
LBR MS SCDE SSM BIE
×
×
RBI
TBI
×
: Used bit
: Unused bit
: Set "1"
: Set "0"
: Bit automatically set correctly
■ LIN Device Connection
Figure 11.6-15 shows a connection between a LIN master device and a LIN slave device.
UART can be set as LIN master or LIN slave.
Figure 11.6-15 Example of LIN Bus System Connection
SOT
SOT
LIN bus
SIN
LIN master
384
SIN
Single-wire transceiver
Single-wire transceiver
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LIN slave
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
11.6.8
LIN Communication Mode (Operation Mode 3)
LIN-UART Sample Flowchart
This section shows examples of LIN-UART flowchart in LIN communication mode.
■ LIN-UART as Master Device
Figure 11.6-16 LIN-UART Flowchart for LIN Master Mode
Start
Initialize: set to operation mode 3
(Data length 8 bits, no parity,
with 1 stop bit)
TIE = 0, RIE = 0
NO
Send message?
YES
Transmit Synch Break:
Write "1" to ECCR:
LBR, TIE = 1;
Transmit sleep data
TDR = 80H
TIE = 0
Transmit Synch Field:
TDR = 55H
Transmit wakeup code
Wakeup from CPU?
NO
Sleep mode
transmission?
RIE = 1
YES
NO
Transmit ID Field: TDR = Id
NO
Write to slave?
YES
NO
TIE = 0
RIE = 1
Read data from slave
RIE = 0
CM71-10139-5E
RIE = 0
YES TIE = 1
TDR = 80H
00H,
80H or C0H
reception?
TIE = 1
Write data from
slave
TIE = 0
RIE = 0
YES
Error occurred?
NO
YES
Error handler
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
■ LIN-UART as Slave Device
Figure 11.6-17 LIN-UART Flowchart for LIN Slave Mode
Start
A
B
Initialize:
Set to operation mode 3
(8N1 data format)
C
Error occurred?
RIE = 0; LBIE = 1;
RXE = 0
NO
NO
Slave address
matched?
E
C
YES
YES
Wait for
slave
operation
NO
Transmission
request from
master?
LBD = 1
LIN Break interrupt
YES
Wait for message from
LIN master
Write "0" to ESCR:LBD
Disable interrupt
Enable ICU interrupt
Receive data
+ checksum
80H received?
(sleep mode)
NO
S
RIE = 0
TIE = 1
Calculate
checksum
Transmit data
(To the next page)
Wait for
slave
operation
TIE = 0
YES
B
ICU interrupt
Read ICU data
Clear ICU interrupt flag
C
Transmission
request from
master?
Wait for
slave
operation
NO
YES
C
ICU interrupt
Read ICU data
Calculate new baud rate
Clear ICU interrupt flag
Clear interrupt
Wait for
slave
operation
E
Error handler
Bus idle
interrupt
C
Receive ID
RIE = 1; RXE = 1
A
(Continued)
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CHAPTER 11 LIN-UART
11.6 Operations of UART
MB91210 Series
(Continued)
Continued from the previous page
S
Wakeup
from CPU?
NO
Transmit wakeup code
RIE = 0
TIE = 1
TDR = 80H
YES
RIE = 1
NO
CM71-10139-5E
Receive
00H, 80H or
C0H?
TIE = 0
YES
RIE = 0
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CHAPTER 11 LIN-UART
11.7 Notes on Using UART
11.7
MB91210 Series
Notes on Using UART
This section shows notes on using LIN-UART.
■ Operation Setting
The serial control register (SCR) of LIN-UART has TXE (transmission) and RXE (reception) operation
enable bits. Both transmission and reception operations must be enabled before transfer starts because they
have been disabled as the default value (initial value). The transfer operation can be canceled by setting
these bits to disable state.
Do not set these two bits at the same time in a single-bus system such as ISO9141 (LIN bus system)
because its communication is unidirectional. As reception is automatically performed, data sent by LINUART will be received also by LIN-UART itself.
■ Communication Mode Setting
Set the communication mode while the system is not operating. If the mode is changed during transmission/
reception, the transmission/reception is stopped and the transfer data will be lost.
■ Transmission Interrupt Enabling Timing
The initial value of the transmission data empty flag bit (TDRE bit in SSR) is "1" (no transmission data,
transmission data write enabled state). A transmission interrupt request will be generated immediately after
the transmission interrupt request is enabled (TIE bit in SSR is "1"). Be sure to set the TIE flag to "1" after
setting the transmission data in TDR register to prevent this interrupt from occurring.
■ Using LIN in Operation Mode 3
Although LIN functions can be used in mode 0 (transmission, reception break), if the operation mode is set
to mode 3, the LIN-UART data format is set automatically to LIN format (8N1, LSB first). Set the
operation mode to mode 3 to apply LIN-UART to LIN bus protocol. The transmitting time for break is
variable but at least 11 serial bit time is required.
■ Changing Operation Settings
Be sure to reset LIN-UART after changing any operation settings. Especially keep attention on the
presence of start/stop bit in synchronous mode 2.
When setting the serial mode register (SMR), do not perform UPCL bit setting and LIN-UART resetting at
the same time. In such case, LIN-UART may not operate correctly. Thus, it is recommended to set the bits
in SMR first and then UPCL bit.
■ LIN Slave Settings
If LIN-UART is initialized as LIN slave, be sure to set the baud rate before receiving the first LIN
synchronous break. This makes sure that the minimum 13-bit time of the LIN synchronous break is
detected.
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CHAPTER 11 LIN-UART
11.7 Notes on Using UART
MB91210 Series
■ Software Compatibility
Although this LIN-UART is similar to other LIN-UARTs installed in conventional MCUs, the software is
incompatible. The programming models are almost the same, but the structure of the registers is different.
Furthermore, the setting of the baud rate is now determined by a reload value instead of selecting a
predefined value.
■ Bus Idle Function
The bus idle function cannot be used in synchronous mode 2.
■ AD Bit in Serial Control Register (SCR)
When using AD bit (address/data bit in multiprocessor mode) in the serial control register (SCR), consider
the following points:
When reading from this bit, it returns the last received AD bit, however when writing to it, it sets the AD
bit for transmission. Therefore, this bit is a control bit and also a flag bit. Inside the device, reception data
and transmission data are stored in different registers. However, the transmission data is read when a readmodify-write (RMW) instruction is used, and the data is written as reception data after data manipulation.
Therefore, an incorrect value may be set in AD bit when another bit in the same register is accessed using
this type of instruction.
For the reason above, an access for writing to this bit must be performed before transmission, or set all the
bits correctly by byte access at a time. In addition, AD bit does not retain data like the transmission data
register does.
If this bit is changed during transmission, the AD bit of the data in the transmission is changed.
■ Notes on Using DMA Transfer
In a data transfer of the UART, unnecessary transfers will occur if a DMA transfer is performed after a
program transfer is performed by CPU. To avoid them, set the transmission enable bit (TIE) and the
reception enable bit (RIE) in the serial status register (SSR) to disable ("0" write) once before starting a
DMA transfer.
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CHAPTER 11 LIN-UART
11.7 Notes on Using UART
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CM71-10139-5E
CHAPTER 12
16-BIT RELOAD TIMER
This chapter explains the register configuration/
function and timer operation of the 16-bit reload timer.
12.1 Overview of 16-Bit Reload Timer
12.2 Registers of 16-Bit Reload Timer
12.3 Operations of 16-Bit Reload Timer
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CHAPTER 12 16-BIT RELOAD TIMER
12.1 Overview of 16-Bit Reload Timer
12.1
MB91210 Series
Overview of 16-Bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an
internal count, a prescaler for creating clock, and a control register.
■ Overview of 16-Bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an internal count, a
prescaler for creating clock, and a control register.
The clock source can be selected from three internal clocks (machine clock divided by 2, 8, and 32) and an
external event.
■ Block Diagram of 16-Bit Reload Timer
Figure 12.1-1 shows a block diagram of the 16-bit reload timer.
Figure 12.1-1 Block Diagram of 16-Bit Reload Timer
16-bit reload register
(TMRLR)
Reload
INTE
16-bit down counter
(TMR)
IRQ
UF
R-bus
RELD
OUT CTL
Count
enable
CNTE
TRG
CSL1
CSL0
Clock
selector
EXCK
Prescaler
392
OUTL
TOT output
PORT
IN CTL
CSL1
CSL0
External
trigger select
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
MB91210 Series
12.2
Registers of 16-Bit Reload Timer
This section explains the configurations and functions of the registers used by the 16bit
reload timer.
■ Register List of 16-Bit Reload Timer
TMCSR upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00004EH
000056H
00005EH
-
-
-
-
CSL1
R/W
CSL0
R/W
MOD1
R/W
MOD0
R/W
----0000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00004FH
000057H
00005FH
MOD0
R/W
R
OUTL
R/W
RELD
R/W
INTE
R/W
UF
R/W
CNTE
R/W
TRG
R/W
00000000B
bit0
Initial value
TMCSR lower byte
TMR
Address
bit15
XXXXH
00004AH
000052H
00005AH
R
TMRLR
Address
bit15
000048H
000050H
000058H
R/W:
R:
W:
X:
-:
bit0
Initial value
XXXXH
W
Readable/Writable
Read only
Write only
Undefined
Undefined bit
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
12.2.1
MB91210 Series
Control Status Register (TMCSR)
The control status register (TMCSR) controls the operating modes and interrupts of the
16-bit reload timer.
■ Bit Configuration of Control Status Register (TMCSR)
TMCSR upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00004EH
000056H
00005EH
-
-
-
-
CSL1
R/W
CSL0
R/W
MOD1
R/W
MOD0
R/W
----0000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00004FH
000057H
00005FH
MOD0
R/W
R
OUTL
R/W
RELD
R/W
INTE
R/W
UF
R/W
CNTE
R/W
TRG
R/W
00000000B
TMCSR lower byte
R/W: Readable/Writable
R:
Read only
-:
Undefined bit
[bit15 to bit12] Reserved: Reserved bits
These bits are reserved bits.
The read value is always 0000B.
[bit11, bit10] CSL1, CSL0: Count Source Select Bits
These bits are the count source select bits. Count sources can be selected from the internal clock or the
external event. The selectable count sources are shown in the following:
Count source
(φ:Machine clock)
φ=40MHz
φ=32MHz
φ=16MHz
φ/21 [Initial value]
50 ns
62.5 ns
125 ns
Internal clock
φ/23
200 ns
250 ns
500 ns
0
Internal clock
φ/25
800 ns
1.0 µs
2.0 µs
1
External event
-
-
-
CSL1
CSL0
0
0
Internal clock
0
1
1
1
-
Countable edges used when external event is set as the count source are set by the MOD1 and MOD0
bits.
The minimum pulse width required for an external clock is 2 × T (T: Machine clock cycle).
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
MB91210 Series
[bit9 to bit7] MOD2, MOD1, MOD0: Mode Bits
These bits set the operating modes. The functions depend on the count source: "internal clock" or
"external clock".
• Internal clock mode …… setting reload trigger
• External clock mode …… setting count enable edge
Be sure to set MOD2 to "0".
[Reload Trigger Setting at Selecting Internal Clock]
When an internal clock is selected as count source, the contents of reload register are loaded after a
valid edge is input by setting MOD2 to MOD0 bits, and the count operation is continued.
MOD2
MOD1
MOD0
Valid edge
0
0
0
Software trigger [Initial value]
0
0
1
External trigger (rising edge)
0
1
0
External trigger (falling edge)
0
1
1
External trigger (both edges)
1
X
X
Setting prohibited
[Valid Edge Setting at Selecting External Clock]
When an external clock event is selected as count source, the event is counted after a valid edge is input
by setting MOD2 to MOD0 bits.
MOD2
MOD1
MOD0
Valid edge
X
0
0
- [Initial value]
X
0
1
External trigger (rising edge)
X
1
0
External trigger (falling edge)
X
1
1
External trigger (both edges)
Reload of external event is generated with underflow and software trigger.
[bit6] Reserved: Reserved Bit
This bit is a reserved bit.
The read value is always "0".
[bit5] OUTL: Output Level
This bit sets the external timer output level. The output level is reversed depending on whether this bit
is "0" or "1".
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
MB91210 Series
[bit4] RELD: Reload Enable Bit
This bit is the reload enable bit. "1" turns on the reload mode. As soon as the counter value underflows
from 0000H → FFFFH, the contents of the reload register are loaded into the counter and the count
operation is continued.
"0" turns on the one shot mode, and the count operation is stopped when the counter value underflows
from 0000H → FFFFH.
PFRxy
OUTL
RELD
Output waveform
0
X
X
Output disabled [Initial state]
1
0
0
Rectangular wave of "H" during counting
1
1
0
Rectangular wave of "L" during counting
1
0
1
Toggle output of "L" at count start
1
1
1
Toggle output of "H" at count start
PFRxy means the PFR register value of the corresponding pin.
[bit3] INTE: Interrupt Enable Bit
This bit is the interrupt request enable bit. If the bit is set to "1", an interrupt request is generated when
the UF bit is set to "1". If it is set to "0", no interrupt request is generated.
[bit2] UF: Underflow Interrupt Flag
This bit is the timer interrupt request flag. This bit is set to "1" when the counter value underflows from
0000H→ FFFFH. Writing "0" clears the flag.
Writing "1" to this bit has no effect.
For a read-modify-write (RMW) instruction, "1" is always read.
[bit1] CNTE: Count Enable Bit
This bit is the count enable bit of the timer. Write "1" to this bit to enter the activation trigger wait state.
Writing "0" stops the count operation.
[bit0] TRG: Trigger Bit
This bit is the software trigger bit. Writing "1" to this bit generates a software trigger, loads the contents
of the reload register into the counter, and starts the count operation.
Writing "0" has no effect. The read value is always "0".
The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0.
Note:
Rewrite the bit other than UF, CNTE, and TRG bits if CNTE=0.
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
MB91210 Series
12.2.2
16-Bit Timer Register (TMR)
The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer.
■ Bit Configuration of 16-Bit Timer Register (TMR)
TMR
Address
00004AH
000052H
00005AH
R:
X:
bit15
bit0
Initial value
XXXXH
R
Read only
Undefined
This register can read the count value of the 16-bit timer. The initial value is undefined. Be sure to read this
register using a 16-bit data transfer instruction.
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CHAPTER 12 16-BIT RELOAD TIMER
12.2 Registers of 16-Bit Reload Timer
12.2.3
MB91210 Series
16-Bit Reload Register (TMRLR)
The 16-bit reload register (TMRLR) holds the initial value of a counter.
■ Bit Configuration of 16-Bit Reload Register (TMRLR)
TMRLR
Address
000048H
000050H
000058H
W:
X:
bit15
bit0
Initial value
XXXXH
W
Write only
Undefined
This register is used to hold the initial value of a counter. The initial value is undefined. Be sure to write
this register using a 16-bit data transfer instruction.
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CHAPTER 12 16-BIT RELOAD TIMER
12.3 Operations of 16-Bit Reload Timer
MB91210 Series
12.3
Operations of 16-Bit Reload Timer
This section explains the following operations of the 16-bit reload timer:
• Internal clock operation
• Underflow operation
• Output pin function
■ Internal Clock Operation
If the timer operates with a division clock of the internal clock, one of the clocks created by dividing the
machine clock by 2, 8, or 32 can be selected as the count source.
To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bits of the
control status register.
Trigger input due to the TRG bit is always valid regardless of the operating mode, when the timer is
running (CNTE=1).
Time as long as T (T: peripheral clock machine cycle) is required after the counter activation trigger is
input and before the data of the reload register is actually loaded into the counter.
Figure 12.3-1 Activation and Operations of the Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE
TRG
T
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CHAPTER 12 16-BIT RELOAD TIMER
12.3 Operations of 16-Bit Reload Timer
MB91210 Series
■ Underflow Operation
Underflow is an event in which the counter value changes from 0000H to FFFFH. Thus, an underflow
occurs at the count of [Reload register setting value + 1].
If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of the reload
register are loaded into the counter and the count operation is continued. If the RELD bit is set to "0", the
counter stops at FFFFH.
Figure 12.3-2 Underflow Operation
[RELD=1]
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
[RELD=0]
Count clock
Counter
0000H
FFFFH
Underflow set
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CHAPTER 12 16-BIT RELOAD TIMER
12.3 Operations of 16-Bit Reload Timer
MB91210 Series
■ Output Pin Function
The TOT output pin provides a toggle output that is inverted by an underflow (in reload mode), or a pulse
output that indicates that counting is in progress (in one shot mode). The output polarity can be set using
the OUTL bit of the register. If OUTL=0, toggle output is "0" for the initial value, and the one-shot pulse
output is "1" while the count operation is in progress. If OUTL=1, the output waveform is reversed.
Figure 12.3-3 Output Pin Function [RELD=1, OUTL=0]
Count activation
Underflow
TOT0 to TOT2
CNTE
General-purpose
port
Inverted at
OUTL=1
Activation trigger
Figure 12.3-4 Output Pin Function [RELD=0, OUTL=0]
Count activation
Underflow
TOT0 to TOT2
CNTE
Inverted at
OUTL=1
General-purpose
port
Activation trigger
Activation trigger waiting state
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CHAPTER 12 16-BIT RELOAD TIMER
12.3 Operations of 16-Bit Reload Timer
MB91210 Series
■ Operating Status of Counter
The counter state is determined by the CNTE bit of the control register and the WAIT signal, which is an
internal signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state);
the activation trigger wait state, when CNTE=1 and WAIT=1 (WAIT state); and the operation state, when
CNTE=1 and WAIT=0 (RUN state).
Figure 12.3-5 Counter State Transition
State transition by hardware
Reset
State transition by register access
STOP CNTE=0,WAIT=1
Counter:Holds the value when it
stops
Undefined just after
reset
CNTE=1
TRG=0
CNTE=1
TRG=1
WAIT CNTE=1, WAIT=1
RUN CNTE=1,WAIT=0
Counter: Holds the value when it
stops
Undefined just after reset
and until data is loaded
TRG=1
Counter: operation
RELD UF
TRG=1
LOAD CNTE=1,WAIT=0
Loads contents of reload
register into counter
RELD UF
Completed with load
■ Notes
• The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1 (timer
enable: CNTE) of the control status register is set to "1".
• If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the
clear operation becomes ineffective.
• If the device attempts to write to the 16-bit timer reload register and reload the data into the 16-bit timer
reload register at the same time, old data is loaded into the counter. New data is loaded into the counter
only in the next reload timing.
• If the device attempts to load and count the 16-bit timer register at the same time, the load (reload)
operation takes precedence.
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CHAPTER 13
16-BIT FREE-RUN TIMER
This section explains the functions and operations of
the 16-bit free-run timer.
13.1 Overview of 16-Bit Free-Run Timer
13.2 Registers of 16-Bit Free-Run Timer
13.3 Operations of 16-Bit Free-Run Timer
13.4 Notes on Using 16-Bit Free-Run Timer
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.1 Overview of 16-Bit Free-Run Timer
13.1
MB91210 Series
Overview of 16-Bit Free-Run Timer
The 16-bit free-run timer consists of a 16-bit timer (up counter) and control circuit. The
16-bit free-run timer can be used with combination of the input capture and the output
compare.
■ Overview of 16-Bit Free-Run Timer
The 16-bit free-run timer consists of a 16-bit up counter and control status register. The count value from
the 16-bit free-run timer is used as the base time for the output compare and input capture.
• The count clock can be selected from four different clocks.
• An interrupt can be generated when a counter overflow occurs.
• The counter can be initialized with the mode setting when there is a match with the value in compare
register (in the output compare unit).
■ Block Diagram of 16-Bit Free-Run Timer
Figure 13.1-1 Block Diagram of 16-Bit Free-Run Timer
Interrupt
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Division
frequency
R-bus
FRCK
Clock select
16-Bit Free-Run Timer
(TCDT)
Clock
To internal circuit (T15 to T00)
Comparator
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.2 Registers of 16-Bit Free-Run Timer
MB91210 Series
13.2
Registers of 16-Bit Free-Run Timer
This section explains the registers of the 16-bit free-run timer.
■ Register List of 16-Bit Free-Run Timer
Figure 13.2-1 Register List of 16-Bit Free-Run Timer
TCDT upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000D4H
0000D8H
0000DCH
0000E0H
T15
R/W
T14
R/W
T13
R/W
T12
R/W
T11
R/W
T10
R/W
T09
R/W
T08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D5H
0000D9H
0000DDH
0000E1H
T07
R/W
T06
R/W
T05
R/W
T04
R/W
T03
R/W
T02
R/W
T01
R/W
T00
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D7H
0000DBH
0000DFH
0000E3H
ECLK
R/W
IVF
R/W
IVFE
R/W
STOP
R/W
MODE
R/W
CLR
R/W
CLK1
R/W
CLK0
R/W
00000000B
TCDT lower byte
TCCS
R/W: Readable/Writable
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.2 Registers of 16-Bit Free-Run Timer
13.2.1
MB91210 Series
Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of the 16-bit free-run
timer.
■ Timer Data Register (TCDT)
Figure 13.2-2 Timer Data Register (TCDT)
TCDT upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000D4H
0000D8H
0000DCH
0000E0H
T15
R/W
T14
R/W
T13
R/W
T12
R/W
T11
R/W
T10
R/W
T09
R/W
T08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D5H
0000D9H
0000DDH
0000E1H
T07
R/W
T06
R/W
T05
R/W
T04
R/W
T03
R/W
T02
R/W
T01
R/W
T00
R/W
00000000B
TCDT lower byte
R/W: Readable/Writable
The counter value of the timer data register is initialized to 0000H by a reset. Writing to this register sets the
timer value.
Note that this register must be written to while the 16-bit free-run timer is stopped (STOP in TCCS
register=1).
The 16-bit free-run timer is initialized with the following sources:
• Initialization by a reset
• Initialization by writing "1" to the CLR bit of the timer control status register
• Initialization due to a match of the compare clear register value in the output compare and the timer
counter value (Mode setting is required).
Note:
Access to this register must be half word (16-bit) access.
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.2 Registers of 16-Bit Free-Run Timer
MB91210 Series
13.2.2
Timer Control Status Register (TCCS)
The timer control status register (TCCS) is used to control the count value of the 16-bit
free-run timer.
■ Timer Control Status Register (TCCS)
Figure 13.2-3 Timer Control Status Register (TCCS)
TCCS
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D7H
0000DBH
0000DFH
0000E3H
ECLK
R/W
IVF
R/W
IVFE
R/W
STOP
R/W
MODE
R/W
CLR
R/W
CLK1
R/W
CLK0
R/W
00000000B
R/W: Readable/Writable
[bit7] ECLK: Clock Select bit
This bit selects either the internal or external clock as count clock source for the 16-bit free-run timer.
Select the clock source when output compare and input capture are stopped.
ECLK
Clock select
0
Selects the internal clock source (CLKP) [Initial value]
1
Selects the external pin (FRCK)
Note:
If the internal clock is selected, set the count clock in bits 1 and 0 (CLK1 and CLK0) of the TCCS
register. This count clock is handled as the base clock. If a clock is input from FRCK, set the
corresponding DDR bit to "0" (input port).
The minimum pulse width required for the external clock is 2 × T (T: Peripheral clock cycle).
If the external clock is specified and output compare is used, a compare match or interrupt occurs at
the next clock cycle. For a compare match to be output and an interrupt to occur, at least one clock
cycle must be input after the compare match.
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.2 Registers of 16-Bit Free-Run Timer
MB91210 Series
[bit6] IVF: Interrupt Request Flag
IVF is the interrupt request flag of the 16-bit free-run timer.
When the 16-bit free-run timer overflows or when, as a result of the mode setting, a match with
compare register clears the counter, this bit is set to "1".
An interrupt occurs when the interrupt request enable bit (IVFE) is set.
Writing "0" clears this bit. For a read-modify-write (RMW) instruction, "1" is always read.
IVF
Interrupt request flag
0
No interrupt request [Initial value]
1
Interrupt request
Reference:
While the IVF bit is initialized to "0" by a reset, "1" is set after the time an overflow occurs has
elapsed, as the free-run timer is running.
[bit5] IVFE: Interrupt Enable bit
IVFE is the interrupt enable bit of the 16-bit free-run timer.
If this bit is set to "1", an interrupt occurs when the interrupt flag (IVF) is set to "1".
IVFE
Interrupt enable
0
Interrupt disabled [Initial value]
1
Interrupt enabled
[bit4] STOP: Stop bit
The STOP bit is used to stop counting by the 16-bit free-run timer.
STOP
Count operation
0
Count enabled (operation) [Initial value]
1
Count disabled (stop)
Note:
When the 16-bit free-run timer stops, the output compare operation also stops.
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.2 Registers of 16-Bit Free-Run Timer
MB91210 Series
[bit3] MODE: Mode Setting bit
The MODE bit is used to set the initialization conditions of the 16-bit free-run timer.
When this bit is set to "0", the counter value can be initialized by a reset and the clear bit (bit2: CLR).
When this bit is set to "1", the counter value can be initialized as the result of a match with the value of
compare register in the output compare unit as well as by a reset and the clear bit (bit2: CLR).
MODE
Timer initialization condition
0
Reset, clear bit [Initial value]
1
Reset, clear bit, compare register
[bit2] CLR: Timer Clear bit
This bit is used to initialize the value of the operating 16-bit free-run timer to 0000H.
Writing "1" to this bit initializes the timer value to 0000H.
"0" is always read from this bit.
Note:
The initialization of the counter value takes place at the point of the count value change. After "1" is
written to the CLR bit, the counter clear request is canceled when "0" is written before the counter is
cleared.
To initialize the counter value while the timer is stopped, write 0000H to the data register.
[bit1, bit0] CLK1, CLK0: Count Clock Selection Bits
These bits are used to select the count clock of the 16-bit free-run timer.
The count clock is updated immediately after a value is written to these bits. Therefore, change a value
to these bits when the output compare and input capture are stopped.
CLK1
CLK0
Count clock (φ)
φ=40 MHz
φ=32 MHz
φ=16 MHz
0
0
22/φ
100 ns
125 ns
250 ns
0
1
24/φ
400 ns
500 ns
1.0 µs
1
0
25/φ
800 ns
1.0 µs
2.0 µs
1
1
26/φ
1.6 µs
2.0 µs
4.0 µs
φ: Resource clock (CLKP)
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.3 Operations of 16-Bit Free-Run Timer
13.3
MB91210 Series
Operations of 16-Bit Free-Run Timer
The 16-bit free-run timer starts counting at the counter value of 0000H when a reset has
been released. This counter value is a reference time for the 16-bit output compare and
16-bit input capture.
■ Explanation of Operation of 16-Bit Free-Run Timer
The counter value is cleared if:
• An overflow occurs.
• A compare match is performed with the compare clear register (output compare register) value (A mode
setting is required).
• "1" is written to the CLR bit of the TCCS register during the operation.
• 0000H is written to the TCDT register while the timer is stopped.
• A reset occurs.
An interrupt can occur when an overflow occurs or when the counter is cleared because a compare match
with the compare clear register value occurs (A mode setting is required for a compare match interrupt).
Figure 13.3-1 Clearing of Counter Due to an Overflow
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Interrupt
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.3 Operations of 16-Bit Free-Run Timer
MB91210 Series
Figure 13.3-2 Clearing of Counter Due to a Compare Match with the Compare Clear Register Value
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
BFFFH
Compare register
Interrupt
■ Clear Timing of 16-Bit Free-Run Timer
The counter can be cleared by a reset, software, or a match with the compare clear register.
A reset and software clear the counter as soon as the clear occurs. A match with the compare clear register,
however, clears the counter in synchronization with the count timing.
Figure 13.3-3 Clear Timing of 16-Bit Free-Run Timer
Compare clear
Register value
N
Counter clear
Counter value
N
0000H
■ Count Timing of 16-Bit Free-Run Timer
The 16-bit free-run timer counts up according to an input clock (internal or external clock). When an
external clock is selected, the clock's falling edge is synchronized with the system clock, then the falling
edge of the internal count clock is counted.
Figure 13.3-4 Count Timing of 16-Bit Free-Run Timer
External clock input
Internal clock
Counter value
CM71-10139-5E
N
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N+1
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CHAPTER 13 16-BIT FREE-RUN TIMER
13.4 Notes on Using 16-Bit Free-Run Timer
13.4
MB91210 Series
Notes on Using 16-Bit Free-Run Timer
This section contains notes on using the 16-bit free-run timer.
■ About Connection with Input Capture/Output Compare
The free-run timer/input capture/output compare are connected as follows:
Free-run timer
Input capture
Output compare
0
0, 1
0, 1
1
2, 3
2, 3
2
4, 5
4, 5
3
6, 7
6, 7
■ Notes on Using 16-Bit Free-Run Timer
• If the interrupt request flag set timing and clear timing occur simultaneously, the flag setting operation
overrides the flag clearing operation.
• When bit2 (counter initialize bit: CLR) in the control status register is set to "1", it holds the value until
the internal counter clear timing and clears itself at that timing. If the clear timing and writing "1" occur
simultaneously, the write operation overrides the clear operation and the CLR bit remains "1" until next
clear timing.
• The counter clear operation is valid only when the internal counter and internal prescaler are running.
To clear the counter when stopped, write 0000H to the timer count data register.
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CHAPTER 14
INPUT CAPTURE
This chapter explains the functions and operations of
the input capture.
14.1 Overview of Input Capture
14.2 Registers of Input Capture
14.3 Operations of Input Capture
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CHAPTER 14 INPUT CAPTURE
14.1 Overview of Input Capture
14.1
MB91210 Series
Overview of Input Capture
The input capture has the functions to detect a rising edge, a falling edge or both edges
of an external input signal and store a 16-bit free-run timer value at that time in the
register. In addition, the input capture can generate an interrupt upon detection of an
edge.
The input capture consists of an input capture data register and a control register.
■ Overview of Input Capture
Each input capture has a corresponding external input pin.
• The valid edge of an external input can be selected from the following three types:
- Rising edge
- Falling edge
- Both edges
• An interrupt can be generated upon detection of the valid edge of an external input.
■ Block Diagram of Input Capture
Figure 14.1-1 Block Diagram of Input Capture
16-bit timer count value (T15 to T00)
R-bus
IN0
input pin
Edge
detection
Capture data register ch.0
EG11
EG10
EG01
EG00
16-bit timer count value (T15 to T00)
IN1
input pin
Edge
detection
Capture data register ch.1
ICP1
ICP0
ICE1
ICE0
Interrupt
Interrupt
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CHAPTER 14 INPUT CAPTURE
14.2 Registers of Input Capture
MB91210 Series
14.2
Registers of Input Capture
The input capture has the following registers:
• Input capture register (IPCP)
• Input capture control register (ICS)
The details of these registers are explained below.
■ List of Input Capture Registers
Figure 14.2-1 List of Input Capture Registers
IPCP upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000E4H
0000E6H
0000ECH
0000EEH
0000F4H
0000F6H
0000FCH
0000FEH
CP15
R
CP14
R
CP13
R
CP12
R
CP11
R
CP10
R
CP09
R
CP08
R
XXXXXXXXB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000E5H
0000E7H
0000EDH
0000EFH
0000F5H
0000F7H
0000FDH
0000FFH
CP07
R
CP06
R
CP05
R
CP04
R
CP03
R
CP02
R
CP01
R
CP00
R
XXXXXXXXB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000EBH
0000F3H
0000FBH
000103H
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
EG11
R/W
EG10
R/W
EG01
R/W
EG00
R/W
00000000B
IPCP lower byte
ICS
R/W: Readable/Writable
R:
Read only
X:
Undefined
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CHAPTER 14 INPUT CAPTURE
14.2 Registers of Input Capture
14.2.1
MB91210 Series
Input Capture Register (IPCP)
The input capture register (IPCP) is a register to store the value of the 16-bit free-run
timer when the valid edge of a waveform input from the corresponding external pin is
detected.
■ Bit Configuration of the Input Capture Register (IPCP)
Figure 14.2-2 Input Capture Register (IPCP)
IPCP upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000E4H
0000E6H
0000ECH
0000EEH
0000F4H
0000F6H
0000FCH
0000FEH
CP15
R
CP14
R
CP13
R
CP12
R
CP11
R
CP10
R
CP09
R
CP08
R
XXXXXXXXB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000E5H
0000E7H
0000EDH
0000EFH
0000F5H
0000F7H
0000FDH
0000FFH
CP07
R
CP06
R
CP05
R
CP04
R
CP03
R
CP02
R
CP01
R
CP00
R
XXXXXXXXB
IPCP lower byte
R:
X:
Read only
Undefined
This register is used to store the value of the 16-bit free-run timer when the valid edge of a waveform input
from the corresponding external pin is detected. The register value is undefined after reset.
This register must be accessed using 16-bit data or 32-bit data. Writing to this register is not allowed.
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CHAPTER 14 INPUT CAPTURE
14.2 Registers of Input Capture
MB91210 Series
14.2.2
Input Capture Control Register (ICS)
The input capture control register (ICS) is used to control the interrupts and edge
detections of the input capture.
■ Bit Configuration of the Input Capture Register (ICS)
Figure 14.2-3 Input Capture Register (ICS)
ICS
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000EBH
0000F3H
0000FBH
000103H
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
EG11
R/W
EG10
R/W
EG01
R/W
EG00
R/W
00000000B
R/W: Readable/Writable
[bit7, bit6] ICP1, ICP0: Interrupt flags
These are input capture interrupt flags. This bit is set to "1" upon detection of the valid edge of an
external input pin. If the interrupt enable bits (ICE1, ICE0) are set, an interrupt can be generated upon
detection of the valid edge. Writing "0" clears this bit. Writing "1" is ignored. "1" can be read by a readmodify-write (RMW) instruction.
ICP1/ICP0
Interrupt flag
0
No valid edge detected [initial value]
1
Valid edge detected
[bit5, bit4] ICE1, ICE0: Interrupt enable bits
These are input capture interrupt enable bits. When this bit is "1", an input capture interrupt occurs if
the interrupt flags (ICP1, ICP0) are set to "1".
ICE1/ICE0
CM71-10139-5E
Interrupt enable
0
Disables interrupt [initial value]
1
Enables interrupt
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CHAPTER 14 INPUT CAPTURE
14.2 Registers of Input Capture
MB91210 Series
[bit3 to bit0] EG11, EG10, EG01, EG00: Edge selection bits
These bits are used to select the valid edge polarity of an external input. They are also used to control
the input capture operation.
EGn1
EGn0
Edge polarity detection
0
0
No edge detection (stop state) [initial value]
0
1
Rising edge detection ↑
1
0
Falling edge detection ↓
1
1
Both edges detection ↑ & ↓
EGn1/EGn0: n number corresponds to the channel number of the input capture.
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CHAPTER 14 INPUT CAPTURE
14.3 Operations of Input Capture
MB91210 Series
14.3
Operations of Input Capture
The 16-bit input capture can generate an interrupt after fetching a 16-bit free-run timer
value into the capture register upon detection of the specified valid edge.
■ Operations of the 16-bit Input Capture
Figure 14.3-1 Example of Input Capture Fetch Timing
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IN0
IN1
IN2
Data register 0
Undefined
3FFFH
Undefined
Data register 1
Data register 2
Undefined
BFFFH
BFFFH
7FFFH
Input capture 0 interrupt
Input capture 1 interrupt
Input capture 2 interrupt
Input capture 0: Rising edge
Input capture 1: Falling edge
Input capture 2: Both edges
CM71-10139-5E
An interrupt occurred again by valid edge
Interrupt clear by software
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CHAPTER 14 INPUT CAPTURE
14.3 Operations of Input Capture
MB91210 Series
■ Input Timing of 16-bit Input Capture
Counter value
Input capture input
N
N+1
Valid edge
Input capture signal
N+1
Input capture register value
Interrupt
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CHAPTER 15
OUTPUT COMPARE UNIT
This chapter describes the operations and functions of
the output compare unit.
15.1 Overview of the Output Compare Unit
15.2 Resisters of the Output Compare Unit
15.3 Operations of the Output Compare Unit
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CHAPTER 15 OUTPUT COMPARE UNIT
15.1 Overview of the Output Compare Unit
15.1
MB91210 Series
Overview of the Output Compare Unit
The output compare module consists of the bit compare registers, compare output
latches, and control registers.
■ Features of the Output Compare Unit
• Compare registers can be used independently.
An output pin and an interrupt flag are assigned to each compare register.
• Two compare registers can be paired to control an output pin.
The output pin can be inverted using the compare registers.
• An initial value can be set for each output pin.
• An interrupt can be generated for a match when values are compared.
■ Block Diagram of the Output Compare Unit
Figure 15.1-1 Block Diagram of the Output Compare Unit
OTD1 OTD0
Compare register
Compare circuit
R-bus
Compare register
CMOD
Compare circuit
Latch for
compare output
PORT
Output
Latch for
compare output
PORT
Output
CST1 CST0
ICP1 ICP0 ICE1 ICE0
16-bit free-run timer
Interrupt
Interrupt
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CHAPTER 15 OUTPUT COMPARE UNIT
15.2 Resisters of the Output Compare Unit
MB91210 Series
15.2
Resisters of the Output Compare Unit
Output compare unit has the compare resisters and control resisters.
■ Registers of the Output Compare Unit
Figure 15.2-1 List of the Registers of the Output Compare Unit
OCCP upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000108H
00010AH
00010CH
00010EH
000114H
000116H
000118H
00011AH
C15
R/W
C14
R/W
C13
R/W
C12
R/W
C11
R/W
C10
R/W
C09
R/W
C08
R/W
XXXXXXXXB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000109H
00010BH
00010DH
00010FH
000115H
000117H
000119H
00011BH
C07
R/W
C06
R/W
C05
R/W
C04
R/W
C03
R/W
C02
R/W
C01
R/W
C00
R/W
XXXXXXXXB
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000110H
000112H
00011CH
00011EH
-
-
-
CMOD
R/W
-
-
OTD1
R/W
OTD0
R/W
11101100B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000111H
000113H
00011DH
00011FH
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
-
-
CST1
R/W
CST0
R/W
00001100B
OCCP lower byte
OCS upper byte
OCS lower byte
R/W: Readable/Writable
X:
Undefined
-:
Undefined bit
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CHAPTER 15 OUTPUT COMPARE UNIT
15.2 Resisters of the Output Compare Unit
15.2.1
MB91210 Series
Compare Resister (OCCP)
This section describes the details of the compare resister (OCCP).
■ Bit Configuration of the Compare Register (OCCP)
Figure 15.2-2 Compare Register (OCCP)
OCCP upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000108H
00010AH
00010CH
00010EH
000114H
000116H
000118H
00011AH
C15
R/W
C14
R/W
C13
R/W
C12
R/W
C11
R/W
C10
R/W
C09
R/W
C08
R/W
XXXXXXXXB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000109H
00010BH
00010DH
00010FH
000115H
000117H
000119H
00011BH
C07
R/W
C06
R/W
C05
R/W
C04
R/W
C03
R/W
C02
R/W
C01
R/W
C00
R/W
XXXXXXXXB
OCCP lower byte
R/W: Readable/Writable
X:
Undefined
■ Functions of the Compare Register (OCCP)
The 16-bit length compare register of which value is compared with the 16-bit free-run timer. Because the
initial value of this register is undefined, be sure to set a compare value in it before enabling to start.
The output compare register must be accessed in 16-bit or 32-bit units. If the value of the compare register
matches the value of the 16-bit free-run timer, a compare signal is generated and the output compare
interrupt flag is set. If the corresponding bit of the port function register (PFR) is set to enable output, the
output level corresponding to the compare register is inverted.
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CHAPTER 15 OUTPUT COMPARE UNIT
15.2 Resisters of the Output Compare Unit
MB91210 Series
15.2.2
Control Register (OCS)
This section describes the details of the control resister (OCS).
■ Bit Configuration of the Control Register (OCS)
Figure 15.2-3 Control Register (OCS)
OCS upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000110H
000112H
00011CH
00011EH
-
-
-
CMOD
R/W
-
-
OTD1
R/W
OTD0
R/W
11101100B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000111H
000113H
00011DH
00011FH
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
-
-
CST1
R/W
CST0
R/W
00001100B
OCS lower byte
R/W: Readable/Writable
-:
Undefined bit
[bit15 to bit13] Reserved: Reserved bits
They are reserved bits from which 111B is always read from these bits.
[bit12] CMOD: Mode bit
This bit specifies the pin output level invert operation upon a match while the output pin is enabled.
• When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is
inverted.
- Inverts the level upon a match with compare register 0.
- Inverts the level upon a match with compare register 1.
• When CMOD=1:
- Inverts the level upon a match with compare register 0.
- Inverts the level upon a match with compare register 0 and 1.
[bit11, bit10] Reserved: Reserved bits
They are reserved bits from which 11B is always read from these bits.
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CHAPTER 15 OUTPUT COMPARE UNIT
15.2 Resisters of the Output Compare Unit
MB91210 Series
[bit9, bit8] OTD1, OTD0: Compare pin output level change bits
These bits are used to specify the pin output level when the output pin in the output compare resister is
enabled. Make sure that the compare operation is stopped before specifying a value. When reading
operation, the output compare pin output value is read.
OTD1, OTD0
Compare pin output level
0
Sets the compare pin output to "0". [Initial value]
1
Sets the compare pin output to "1".
[bit7, bit6] ICP1, ICP0: Interrupt flags
These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register
value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are
enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set to "1". These bits are
cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write (RMW)
instruction.
ICP1, ICP0
Interrupt flag
0
There is no output compare match. [Initial value]
1
There is a compare match.
If an external clock is specified for the free-run timer, a compare match and interrupt occur in the next
clock cycle. Therefore, to generate a compare match output and an interrupt, at least one clock pulse
must be input for the external clock specified for the free-run timer after the matching occurs.
[bit5, bit4] ICE1, ICE0: Interrupt enable bits
These bits enable the output compare to interrupt. If "1" is set to these bits, an output compare interrupt
occurs when an interrupt flag (ICP1 or ICP0) is set to "1".
ICE1, ICE0
Interrupt enable
0
Disables the output compare interrupt. [Initial value]
1
Enables the output compare interrupt.
[bit3, bit2] Reserved: Reserved bits
They are reserved bits from which 11B is always read from these bits.
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CHAPTER 15 OUTPUT COMPARE UNIT
15.2 Resisters of the Output Compare Unit
MB91210 Series
[bit1, bit0] CST1, CST0: Matching operation enable bits
These bits are used to enable the matching operation with 16-bit free-run timer. Ensure that values are
set to the compare register and output control resister before the compare operation is enabled.
CST1, CST0
Matching operation enable
0
Disables compare operation. [Initial value]
1
Enables compare operation.
Since the output compare is synchronized with 16-bit free-run timer, stopping the 16-bit free-run timer
stops compare operation.
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CHAPTER 15 OUTPUT COMPARE UNIT
15.3 Operations of the Output Compare Unit
15.3
MB91210 Series
Operations of the Output Compare Unit
16-bit output compare can compare the specified compare register value with the 16-bit
free-run timer value, and set an interrupt flag and invert the output level when they are
found to match.
■ Operation of the 16-bit Output Compare
• The compare operation can be performed for each channel independently (when CMOD=0).
Figure 15.3-1 Sample of Output Waveform When Compare Registers 0 and 1 Used (Initial Output Value is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Output compare register 0 value
BFFFH
Output compare register 1 value
7FFFH
OP0 output
OP1 output
Output compare 0 interrupt
Output compare 1 interrupt
• The output level can be changed using two pairs of compare registers (when CMOD=1).
Figure 15.3-2 Sample of Output Waveform When Compare Registers 0 and 1 Used (Initial Output Value is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Output compare register 0 value
BFFFH
Output compare register 1 value
7FFFH
OP0 output
OP1 output
Output compare 0 interrupt
Output compare 1 interrupt
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CHAPTER 15 OUTPUT COMPARE UNIT
15.3 Operations of the Output Compare Unit
MB91210 Series
■ Timing of 16-bit Output Compare Operation
The output level can be changed using two pairs of compare registers (when CMOD=1). In output compare
operation, a compare match signal is generated when the free-run timer value matches the specified
compare register value. The output value can be inverted and an interrupt can be issued. The output invert
timing upon a compare match is synchronized with the counter count timing.
● Compare register write timing
When rewriting the compare register, the value is not compared with the counter value.
Counter value
N
N+1
N+2
N+3
No match signal is generated.
Compare clear register 0 value
N+1
N
Compare register 0 write
Compare clear register 1 value
N+3
L
Compare register 1 write
Compare 0 stop
Compare 1 stop
● Compare match, Interrupt timing
Count clock
Counter value
N
Compare register value
N+1
N+2
N+3
N
Compare match
Pin output
Interrupt
● Pin output timing
Counter value
Compare register value
N
N+1
N+1
N+1
N
Compare match
Pin output
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CHAPTER 15 OUTPUT COMPARE UNIT
15.3 Operations of the Output Compare Unit
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CHAPTER 16
PPG TIMER
This chapter explains about the PPG timer.
16.1 Overview of PPG Timer
16.2 Block Diagram of PPG Timer
16.3 Registers of PPG Timer
16.4 Operating Explanation of PPG Timer
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CHAPTER 16 PPG TIMER
16.1 Overview of PPG Timer
16.1
MB91210 Series
Overview of PPG Timer
The PPG is an 8-bit reload timer module that performs a PPG output by controlling the
pulse output in response to the timer operation.
The hardware consists of 8-bit down counters, 8-bit reload registers, control register,
external pulse outputs, and interrupt output.
■ PPG Functions
● 8-bit PPG output independent operation mode
Can operate an independent PPG output.
● 16-bit PPG output operation mode
Can operate 16-bit PPG output.
● 8+8 bit PPG output operation mode
Can operate 8-bit PPG output in any cycle with setting the ch. (2n+1) output as the ch. (2n) clock input.
● 16+16 bit PPG output operation mode
Sets the 16-bit prescaler output for the ch. (4n+3) + ch. (4n+2) as a 16-bit PPG clock input for the ch.
(4n+1) + ch. (4n).
● PPG output operation
Outputs the pulse wave of any cycle/ duty ratio.
Can also be used as a D/A converter with the external circuit.
● Output reverse function
Can reverse the PPG output value.
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CHAPTER 16 PPG TIMER
16.2 Block Diagram of PPG Timer
MB91210 Series
16.2
Block Diagram of PPG Timer
This section shows the block diagram of the PPG.
■ Block Diagram of the 8-bit PPG ch.0 and ch.2
Figure 16.2-1 Block Diagram of the 8-bit PPG ch.0 and ch.2
ch.3, ch.1 borrow
Machine clock 64-divided
Machine clock 16-divided
Machine clock 4-divided
Machine clock
To port
PPG output
latch
Inversion
clear
PEN1, PEN3
Count clock
selection
S
R Q
PCNT (down counter)
IRQ0
IRQ2
Reload
"H"/"L" select
"H"/"L" selector
PRLL0
PRLL2
PUF0
PUF2
PIE0
PIE2
PRLH0
PRLH2
"L" side data bus
"H" side data bus
PPGC0
PPGC2 / TRG
Operation mode (control)
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CHAPTER 16 PPG TIMER
16.2 Block Diagram of PPG Timer
MB91210 Series
■ Block Diagram of the 8-bit PPG ch.1
Figure 16.2-2 Block Diagram of the 8-bit PPG ch.1
ch.2 borrow
Machine clock 64-divided
Machine clock 16-divided
Machine clock 4-divided
Machine clock
To port
PPG output
latch
Inversion
clear
PEN1
S
R Q
Count clock
selection
IRQ1
PCNT (down counter)
ch.0
borrow
Reload
"H"/"L" select
"H"/"L" selector
PUF1
PRLL1
PIE1
PRLH1
"L" side data bus
"H" side data bus
PPGC3 / TRG
Operation mode (control)
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CHAPTER 16 PPG TIMER
16.2 Block Diagram of PPG Timer
MB91210 Series
■ Block Diagram of the 8-bit PPG ch.3
Figure 16.2-3 Block Diagram of the 8-bit PPG ch.3
To port
Machine clock 64-divided
Machine clock 16-divided
Machine clock 4-divided
Machine clock
PPG output
latch
Inversion
clear
PEN3
S
R Q
Count clock
selection
PCNT (down counter)
ch.2
borrow
Reload
"H"/"L" select
"H"/"L" selector
PUF3
PRLL3
PIE3
PRLH3
"L" side data bus
"H" side data bus
PPGC1 / TRG
Operation mode (control)
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
16.3
MB91210 Series
Registers of PPG Timer
This section describes the details of the PPG timer.
■ List of the Registers of the PPG Timer
Figure 16.3-1 List of the Registers of the PPG Timer
PPGC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001B8H
0001B9H
0001BAH
0001BBH
0001C8H
0001C9H
0001CAH
0001CBH
0001D8H
0001D9H
0001DAH
0001DBH
0001E8H
0001E9H
0001EAH
0001EBH
PIE
R/W
PUF
R/W
INTM
R/W
PCS1
R/W
PCS0
R/W
MD1
R/W
MD0
R/W
-
0000000XB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PRLH
Address
0001B0H
0001B2H
0001B4H
0001B6H
0001C0H
0001C2H
0001C4H
0001C6H
0001D0H
0001D2H
0001D4H
0001D6H
0001E0H
0001E2H
0001E4H
0001E6H
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
-:
Undefined bit
X:
Undefined
(Continued)
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
(Continued)
PRLL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0001F0H
PEN15
R/W
PEN14
R/W
PEN13
R/W
PEN12
R/W
PEN11
R/W
PEN10
R/W
PEN09
R/W
PEN08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001F1H
PEN07
R/W
PEN06
R/W
PEN05
R/W
PEN04
R/W
PEN03
R/W
PEN02
R/W
PEN01
R/W
PEN00
R/W
00000000B
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0001F2H
REV15
R/W
REV14
R/W
REV13
R/W
REV12
R/W
REV11
R/W
REV10
R/W
REV09
R/W
REV08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001F3H
REV07
R/W
REV06
R/W
REV05
R/W
REV04
R/W
REV03
R/W
REV02
R/W
REV01
R/W
REV00
R/W
00000000B
0001B1H
0001B3H
0001B5H
0001B7H
0001C1H
0001C3H
0001C5H
0001C7H
0001D1H
0001D3H
0001D5H
0001D7H
0001E1H
0001E3H
0001E5H
0001E7H
Initial value
XXXXXXXXB
TRG1
TRG0
REVC1
REVC0
R/W: Readable/Writable
X:
Undefined
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
16.3.1
MB91210 Series
PPG Operating Mode Control Register (PPGC)
The PPG operating mode control register (PPGC) controls the PPG interrupt, operating
clock, and operating mode.
■ PPG Operating Mode Control Register (PPGC)
Figure 16.3-2 PPG Operating Mode Control Register (PPGC)
PPGC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001B8H
0001B9H
0001BAH
0001BBH
0001C8H
0001C9H
0001CAH
0001CBH
0001D8H
0001D9H
0001DAH
0001DBH
0001E8H
0001E9H
0001EAH
0001EBH
PIE
R/W
PUF
R/W
INTM
R/W
PCS1
R/W
PCS0
R/W
MD1
R/W
MD0
R/W
-
0000000XB
R/W: Readable/Writable
-:
Undefined bit
X:
Undefined
[bit7] PIE: PPG Interrupt enable bit
Controls to enable a PPG interrupt as described below:
PIE
PPG interrupt enable
0
Disables the interrupt. [Initial value]
1
Enables the interrupt.
• If this bit is set to "1", an interrupt request is generated when the PUF is set to "1".
• If this bit is set to "0", no interrupt request is generated.
• Initialized to "0" by resetting.
• Readable and writable.
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
[bit6] PUF: PPG counter underflow bit
Controls PPG counter underflow bit as described below:
PUF
PPG counter underflow
0
PPG counter underflow has not been detected. [Initial value]
1
PPG counter underflow has been detected.
• In 8-bit PPG 2 channels mode and 8-bit prescaler + 8-bit PPG mode, the bit is set to "1" when the
ch.0 count value underflows from 00H to FFH.
• In 16-bit PPG 1 channel mode, the bit is set to "1" when the ch.1/ ch.0 count value underflows from
0000H to FFFFH.
• Writing "0" clears the bit to "0".
• Writing "1" to this bit is meaningless.
• When this bit is read to a read-modify-write (RMW) instructions, "1" is always read.
• Initialized to "0" by resetting.
• Readable and writable.
[bit5] INTM: Interrupt mode bit
Can restrict the detection of PUF bit to the underflow timing from the PRLH only.
INTM
Interrupt mode
0
Sets PUF bit to "1" at an underflow. [Initial value]
1
Sets PUF bit to "1" at an underflow from PRLH only.
• Initialized to "0" by resetting.
• Readable and writable.
• If this bit is set to "1", an interrupt is enabled at one cycle output of PPG waveform.
• Do not rewrite this bit when the interrupt is enabled.
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
[bit4, bit3] PCS1/PCS0: Count clock select bits
Selects the down counter operating clock as shown below:
PCS1
PCS0
Count clock
0
0
Machine clock [Initial value]
0
1
Machine clock/ 4
1
0
Machine clock/ 16
1
1
Machine clock/ 64
• Initialized to 00B by resetting.
• Readable and writable.
[bit2, bit1] MD1/MD0: Operating mode select bits
MD1
MD0
Operating mode
0
0
8-bit PPG 2 channels [Initial value]
0
1
8-bit prescaler + 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler + 16-bit PPG mode
• Initialized to 00B by resetting.
• Readable and writable.
• These bits exist only in even-numbered channels.
[bit0] Reserved: Reserved bit
It is a reserved bit. Write "0" on writing (writing "1" is disabled).
Read value is undefined.
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
16.3.2
Reload Register (PRLL/PRLH)
Reload registers (PRLL/PRLH) retain the reload values of the PPG.
■ Reload Register (PRLL/PRLH)
Figure 16.3-3 Reload Register (PRLL/PRLH)
PRLH
Address
0001B0H
0001B2H
0001B4H
0001B6H
0001C0H
0001C2H
0001C4H
0001C6H
0001D0H
0001D2H
0001D4H
0001D6H
0001E0H
0001E2H
0001E4H
0001E6H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PRLL
Address
0001B1H
0001B3H
0001B5H
0001B7H
0001C1H
0001C3H
0001C5H
0001C7H
0001D1H
0001D3H
0001D5H
0001D7H
0001E1H
0001E3H
0001E5H
0001E7H
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
X:
Undefined
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
Reload registers (PRLL/PRLH) retain the reload values for a down counter PCNT. Each register has own
role as shown below:
Register
Name
Function
PRLL
Retains the reload value on "L" side.
PRLH
Retains the reload value on "H" side.
Both registers are readable and writable.
Note:
In the 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, setting the same
value to the PRLL and PRLH in the prescaler side is recommended because the PPG waveform
may be different for each cycle when the different value is set to the PRLL and PRLH in the
prescaler side.
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
MB91210 Series
16.3.3
PPG Start Register (TRG)
PPG start register (TRG) enables the PPG operation.
■ PPG Start Register (TRG)
Figure 16.3-4 PPG Start Register (TRG)
TRG1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0001F0H
PEN15
R/W
PEN14
R/W
PEN13
R/W
PEN12
R/W
PEN11
R/W
PEN10
R/W
PEN09
R/W
PEN08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001F1H
PEN07
R/W
PEN06
R/W
PEN05
R/W
PEN04
R/W
PEN03
R/W
PEN02
R/W
PEN01
R/W
PEN00
R/W
00000000B
TRG0
R/W: Readable/Writable
[bit15 to bit0] PEN15 to PEN00: PPG operation enable bits
Selects the PPG operation start and the operating mode as shown below:
PEN
Operation state
0
Stops the operation (retains "L" level output). [Initial value]
1
Enables the PPG operation.
• Initialized to "0" by resetting.
• Readable and writable.
• When using in 16-bit PPG, you must set the same value to PEN bits that correspond to both even and
odd numbers. Enable/ stop both even and odd numbers at the same time on setting the resister.
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CHAPTER 16 PPG TIMER
16.3 Registers of PPG Timer
16.3.4
MB91210 Series
Output Reverse Register (REVC)
The Output Reverse Register (REVC) reverses the output value of the PPG.
■ Output Reverse Register (REVC)
Figure 16.3-5 Output Reverse Register (REVC)
REVC1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0001F2H
REV15
R/W
REV14
R/W
REV13
R/W
REV12
R/W
REV11
R/W
REV10
R/W
REV09
R/W
REV08
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0001F3H
REV07
R/W
REV06
R/W
REV05
R/W
REV04
R/W
REV03
R/W
REV02
R/W
REV01
R/W
REV00
R/W
00000000B
REVC0
R/W: Readable/Writable
X:
Undefined
[bit15 to bit0] REV15 to REV00: Output reverse bits
Reverses the PPG output values including the initial levels.
REV
Output level
0
Normal [Initial value]
1
Inversion
• Initialized to "0" by resetting.
• Readable and writable.
• Since these bits merely invert the PPG outputs, they also invert the initial levels.
• The relationship between the reload register "L" and "H" is reversed as well.
• When using in 16-bit PPG, setting REV bit of the pins to be used provides the reversed outputs, for
the same wave forms are output from both PPG (m) and PPG (m+1) pins. You can also set the same
value to both outputs.
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CM71-10139-5E
CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
MB91210 Series
16.4
Operating Explanation of PPG Timer
The PPG has 8-bit length PPG units and can be used in 4 different modes by linking the
operations: 8-bit prescaler + 8-bit PPG mode, 16-bit PPG 1 channel mode, 16-bit
prescaler + 16-bit PPG mode, and the independent mode.
■ PPG Operation
Each of 8-bit length PPG units has two of 8-bit-length reload registers on the "L" and "H" sides (PRLL,
PRLH). The "L" side and "H" side values written to this register are alternately reloaded to the 8-bit down
counter (PCNT) that counts down on each cycle of the count clock. The value of the pin output (PPG) is
toggled each time a counter borrow occurs to trigger another reload. With this operation, the pin output
(PPG) becomes a pulse output, which has "L"/ "H" width corresponding to the value of reload register.
The operation starts/ restarts when the bit in the register is written.
The relationship between the reload operation and the pulse output is shown below:
Reload operation
Pin output change
PRLH → PCNT
PPGn [0 → 1]
PRLL → PCNT
PPGn [1 → 0]
n: PPG channel number
When bit7 (PIE) in the PPGC register is "1", an interrupt request is output by a borrow from 00H to FFH of
the counter (or a borrow from 0000H to FFFFH in 16-bit PPG mode).
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CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
MB91210 Series
■ Operating Mode
There are 4 operating modes: independent mode, 8-bit prescaler + 8-bit PPG mode, 16-bit PPG 1 channel
mode, and 16-bit prescaler + 16-bit PPG mode.
• In the independent mode, a channel can operate as 8-bit PPG independently. The PPG output of ch.n is
connected to PPGn pin.
• The 8-bit prescaler + 8-bit PPG mode makes 1 channel operate as an 8-bit prescaler, counts its borrow
output, and then allows the 8-bit PPG wave form in any cycle to be output. For example, the prescaler
output of ch.1 is connected to the PPG1 pin; the PPG output of ch.0 is connected to the PPG0 pin.
• In the 16-bit PPG 1 channel mode, two channels are combined to operate as 16-bit PPG. For example, if
ch.0 and ch.1 are combined, 16-bit PPG outputs are connected to both PPG0 pin and PPG1 pin.
■ PPG Output Operation
The PPG is activated and starts counting when the bit corresponding to each channel in the TRG register
(PPG start register) is set to "1". After operation starts, the count operation is stopped when each channel
bit in the TRG register is set to "0". After having stopped, the pulse output retains "L" level.
Do not set the PPG channel as the operating state with the prescaler channel in the stopped state during the
8-bit prescaler + 8-bit PPG and the 16-bit prescaler + 16-bit PPG mode.
In 16-bit PPG mode, use the PEN bits for each channel in the TRG register to simultaneously start and stop
operation.
PPG output operation is explained below:
While PPG operating, the pulse wave with any frequency/duty ratio (the ratio between "H" level period and
"L" level period in pulse wave) is output continuously. Once the pulse wave output is started, PPG will not
stop it until operation stop is set.
Figure 16.4-1 PPG Output Operation Output Waveform
PENn
Operation
start by PENn
(from "L" side)
Output pin
T × (L+1)
PPG
n=00 to 15
Start
T × (H+1)
L : PRLL value
H : PRLH value
T : Machine clock(φ, φ/4, φ/16)
or input from time-base counter
(by PPGC clock select)
PPG output operation output waveform
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CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
MB91210 Series
■ Relationship between Reload Value and Pulse Width
The pulse width to be output is the product of the cycle of the count clock and the value written in the
reload register plus 1. Note that the pulse width will be one cycle of the count clock when the reload
register value is set to 00H at operating the 8-bit PPG and when the reload register value is set to 0000H at
operating the 16-bit PPG. Note that the pulse width will be 256 cycles of the count clock when the reload
register value is set to FFH at operating the 8-bit PPG, and the pulse width will be 65536 cycles of the count
clock when the reload register value is set to FFFFH at operating the 16-bit PPG.
The equations for calculating the pulse width are shown below:
L : PRLL value
Pl = T × (L+1)
H : PRLH value
Ph = T × (H+1)
T : Cycle of input clock
Ph : "H" pulse width
Pl : "L" pulse width
■ Count Clock Selection
The count clock to be used for this block operation uses the peripheral, and can be selected from one of the
following 4 types of count clock inputs.
The count clock operates as shown below:
PPGC register
Count clock operation
PCS1
PCS0
0
0
Count clock is counted for each peripheral clock
0
1
Count clock is counted for 4 cycles of peripheral clock
1
0
Count clock is counted for 16 cycles of peripheral clock
1
1
Count clock is counted for 64 cycles of peripheral clock
In 8-bit prescaler + 8-bit PPG mode, 16-bit PPG mode, and 16-bit prescaler + 16-bit PPG mode however,
the values for bit4 and bit3 (PCS1, PCS0) in the PPGC resister of the PPG other than the first PPG becomes
invalid.
Note that, in 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, the first count
period may vary when the PPG is started with prescaler side operating state and the PPG side halted state.
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CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
MB91210 Series
■ Control of Pulse Pin Output
The pulse output generated by operating this module can be output from external pins (PPGn).
As both PPG (m) and PPG (m+1) output the same wave form in 16-bit PPG mode, the same output can be
obtained whichever of these is enabled as an external output pin.
In the 8-bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, the 8-bit prescaler
toggle waveform is output on the prescaler side, and the 8-bit PPG waveform is output on the PPG side.
The following shows an example of the output waveform in this mode:
Ph1
Pl1
PPG1
PPG0
Ph0
Pl0
L1: ch.1 PRLL value and
ch.1 PRLH value
L0: ch.0 PRLL value
Pl1 = T × (L1 + 1)
H0: ch.0 PRLH value
Ph1 = T × (L1 + 1)
T: Period of input clock
Pl0 = T × (L1 + 1) × (L0 + 1)
Ph0: "H" pulse width of PPG0
Ph0 = T × (L1 + 1) × (H0 + 1)
Pl0: "L" pulse width of PPG0
Ph1: "H" pulse width of PPG1
Pl1: "L" pulse width of PPG1
Setting the same value to PRLL and PRLH for ch.1 is recommended.
■ Interrupt
The interrupt on this module becomes active when a reload value is counted out and a borrow occurs.
However, if the INTM bit is "1", the interrupt goes to active only when an underflow (borrow) occurs from
PRLH. The interrupt occurs when "H" width pulse ends.
In the 8-bit PPG mode and the 8-bit prescaler + 8-bit PPG mode, an interrupt request is performed by the
relevant counter borrow. However, in 16-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, PUF (m)
and PUF (m+1) are concurrently set by the borrow of the 16-bit counter. For this reason, it is recommended
that either PIE (m) or PIE (m+1) is enabled in order to unify the interrupt sources. Similarly, it is
recommended that you write to PUF (m) and PUF (m+1) simultaneously when clearing the interrupt
source.
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CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
MB91210 Series
■ Initial Values for Each Hardware
Each hardware of this block is initialized by a reset as shown below:
< Register >
PPGC → 0000000XB
< Pulse output >
PPG
→ "L"
< Interruption request >
IRQ
→ "L"
Any hardware other than those above is not initialized.
■ PPG Combinations
ch.0: PPGC
ch.2: PPGC
MD1
MD0
MD1
MD0
0
0
0
0
0
0
ch.0
ch.1
ch.2
ch.3
0
8-bit PPG
8-bit PPG
8-bit PPG
8-bit PPG
0
1
8-bit PPG
8-bit PPG
8-bit PPG
8-bit prescaler
0
1
0
8-bit PPG
8-bit PPG
0
0
1
1
0
1
0
0
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit PPG
0
1
0
1
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit prescaler
0
1
1
0
8-bit PPG
8-bit prescaler
0
1
1
1
1
0
0
0
16-bit PPG
8-bit PPG
8-bit PPG
1
0
0
1
16-bit PPG
8-bit PPG
8-bit prescaler
1
0
1
0
16-bit PPG
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
16-bit PPG
Setting is prohibited
16-bit PPG
Setting is prohibited
16-bit PPG
Setting is prohibited
CM71-10139-5E
16-bit PPG
FUJITSU MICROELECTRONICS LIMITED
16-bit prescaler
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CHAPTER 16 PPG TIMER
16.4 Operating Explanation of PPG Timer
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MB91210 Series
CM71-10139-5E
CHAPTER 17
REAL TIME CLOCK
This chapter explains the register configuration and the
functions of the real time clock (hereinafter referred to
as RTC) and the operation of RTC module.
17.1 Configuration of Real Time Clock Registers
17.2 Block Diagram of Real Time Clock
17.3 Details of Real Time Clock Registers
17.4 Clock Calibration Unit of Real Time Clock
17.5 Clock Calibration Unit Registers of Real Time Clock
17.6 About the Use for Clock Calibration Unit of Real Time Clock
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CHAPTER 17 REAL TIME CLOCK
17.1 Configuration of Real Time Clock Registers
17.1
MB91210 Series
Configuration of Real Time Clock Registers
This section shows the register configuration of the real time clock.
■ List of Real Time Clock Registers
Figure 17.1-1 List of Real Time Clock Registers
WTCR upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000146H
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000147H
-
-
-
-
RUN
UPDT
-
ST
000-00-0B
R/W
R/W
R/W
-
R/W
R/W
-
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000149H
-
-
-
D20
D19
D18
D17
D16
---XXXXXB
-
-
-
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
WTCR lower byte
WTBR2
WTBR1
Address
00014AH
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00014BH
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTBR0
R/W: Readable/writable
-:
Undefined bit
X:
Undefined
(Continued)
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CHAPTER 17 REAL TIME CLOCK
17.1 Configuration of Real Time Clock Registers
MB91210 Series
(Continued)
WTHR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00014CH
-
-
-
H4
H3
H2
H1
H0
---XXXXXB
-
-
-
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00014DH
-
-
M5
M4
M3
M2
M1
M0
--XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00014EH
-
-
S5
S4
S3
S2
S1
S0
--XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000145H
-
-
-
-
-
-
WTCK
DBL
------00B
-
-
-
-
-
-
R/W
R/W
WTMR
WTSR
WTDBL
R/W: Readable/writable
-:
Undefined bit
X:
Undefined
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CHAPTER 17 REAL TIME CLOCK
17.2 Block Diagram of Real Time Clock
17.2
MB91210 Series
Block Diagram of Real Time Clock
This section shows the block diagram of the real time clock.
■ Block Diagram of Real Time Clock
Figure 17.2-1 Block Diagram of Real Time Clock
X0 (main)
X0A (sub)
0
1
1/2 clock
divider
WTCK
UPDT
21-bit
prescaler
Subsecond
register
ST
Second
counter
Minute
counter
Hour
counter
6 bits
6 bits
5 bits
Second/Minute/Hour register
INTE0 INT0
INTE1 INT1
INTE2 INT2
INTE3 INT3
IRQ
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CHAPTER 17 REAL TIME CLOCK
17.3 Details of Real Time Clock Registers
MB91210 Series
17.3
Details of Real Time Clock Registers
This section explains details of register configuration for real time clock.
■ Timer Control Register (WTCR)
Figure 17.3-1 Timer Control Register (WTCR)
WTCR upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000146H
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000147H
-
-
-
-
RUN
UPDT
-
ST
000-00-0B
R/W
R/W
R/W
-
R/W
R/W
-
R/W
WTCR lower byte
R/W: Readable/writable
-:
Undefined bit
X:
Undefined
[bit15 to bit8] INT3 to INT0, INTE3 to INTE0: Interrupt flags and interrupt enable flags
INT0 to INT3 are interrupt flags. They are set when the second counter, minute counter and hour
counter overflow respectively. If an INT bit is set while the corresponding INTE bit is "1", it generates
an interrupt signal. These flags are designed to generate an interrupt signal by the second/minute/hour/
day. Writing "0" to an INT bit clears the flag and writing "1" does not have any effect. All read-modifywrite (RMW) instructions operable on the INT bit will read "1".
Interrupt
Source
Interrupt enable bit
Interrupt flag
Second interrupt
Prescaler underflow
INTE0
INT0
Minute interrupt
Second counter overflow
INTE1
INT1
Hour interrupt
Minute counter overflow
INTE2
INT2
Day interrupt
Hour counter overflow
INTE3
INT3
[bit7 to bit5] Reserved bits
These are reserved bits.
Be sure to set these bits to 000B.
[bit3] RUN: Flag
This bit is read only. If the reading value is "1", it indicates that the RTC module is operating.
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CHAPTER 17 REAL TIME CLOCK
17.3 Details of Real Time Clock Registers
MB91210 Series
[bit2] UPDT: Update bit
The UPDT bit is used to modify the second/minute/hour counter value.
To modify the counter value, write the modified data in the second/minute/hour register. Then, set the
UPDT bit to "1". The register value is loaded to the counter at the next cycle by CO signal (written)
from the 21-bit prescaler. The UPDT bit is reset by hardware when the counter value is updated.
However, if a setting operation by software and a resetting operation by hardware occur at the same
time, the UPDT bit will not be reset.
This occurs only if the peripheral clock (CLKP) has a higher frequency than the RTC clock (oscillation
clock).
Writing "0" to the UPDT bit has no effect. "0" is read by a read-modify-write (RMW) instruction.
[bit0] ST: Start bit
When the ST bit is set to "1", the watch timer loads a value of second/minute/hour from the register and
starts its operation. When it is reset to "0", all the counters and the prescaler are reset to "0" and halt.
This bit can also be used for updating the counter value. Set the ST bit to "0", wait for RUN to become
"0", update the counter value and set the ST bit to "1".
Notes:
• Always wait one second interrupt when transferring to RTC mode after setting UPDT bit.
• Use UPDT bit to update time/minute/hour only in RTC operation. Do not use it to update time/
minute/hour when RTC is stopped (ST=0).
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CHAPTER 17 REAL TIME CLOCK
17.3 Details of Real Time Clock Registers
MB91210 Series
■ Subsecond Register
Figure 17.3-2 Subsecond Register (WTBR)
WTBR2
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000149H
-
-
-
D20
D19
D18
D17
D16
---XXXXXB
-
-
-
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00014AH
D15
D14
D13
D12
D11
D10
D9
D8
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00014BH
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTBR1
WTBR0
R/W: Readable/writable
-:
Undefined bit
X:
Undefined
[bit4 to bit0, bit15 to bit0] D20 to D0
The subsecond register stores a reload value for the 21-bit prescaler. This value is reloaded after the
reload counter reaches "0". When modifying all the three bytes, make sure that the reload operation is
not being performed during a write instruction. Otherwise, the 21-bit prescaler loads the combined
value of new data and old data bytes. Update the subsecond register while the ST bit is "0". While the
subsecond register is set to "0", the 21-bit prescaler stops its operation.
A clock signal of 1 second can be supplied precisely by combining these two prescalers.
An example of the setting values for the subsecond register is shown below.
Input clock frequency
WTBR setting value
(decimal)
WTBR setting value
(hexadecimal)
4 MHz
1999999
1E847FH
100 kHz
49999
00C34FH
32 kHz
15999
003E7FH
Note:
Since the subsecond register is 21 bits long, the upper limit of the frequency that can generate 1
second is 4.19 MHz. If selecting the main clock as the clock supplying to the RTC module, set the
main clock frequency to 4 MHz.
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CHAPTER 17 REAL TIME CLOCK
17.3 Details of Real Time Clock Registers
MB91210 Series
■ Hour/Minute/Second Register
Figure 17.3-3 Hour/Minute/Second Register (WTHR, WTMR, WTSR)
WTHR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00014CH
-
-
-
H4
H3
H2
H1
H0
---XXXXXB
-
-
-
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
--XXXXXXB
WTMR
Address
00014DH
-
-
M5
M4
M3
M2
M1
M0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00014EH
-
-
S5
S4
S3
S2
S1
S0
--XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
WTSR
R/W: Readable/writable
-:
Undefined bit
X:
Undefined
The second/minute/hour register stores time information. It is a binary representation of second/minute/
hour.
Reading this register returns the counter value only. The register is combined with a written value and the
written data is loaded into the counter after the UPDT bit is set to "1".
Since the register holds 3 bytes, make sure that the output value is consistent. This means the output value
"1 hour, 59 minutes, 59 seconds" could be "0 hours, 59 minutes, 59 seconds" or "2 hours, 59 minutes, 59
seconds".
If reading is done when the counter overflow occurs, a wrong value could be read. Therefore, reading must
be performed using RTC interrupts or following the procedure below.
• Clear RTC interrupt flag (INT).
• Read the register.
• Read it again if overflow occurs during reading and the flag is set after the reading.
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CHAPTER 17 REAL TIME CLOCK
17.3 Details of Real Time Clock Registers
MB91210 Series
■ Clock Disable Register
Figure 17.3-4 Clock Disable Register (WTDBL)
WTDBL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000145H
-
-
-
-
-
-
WTCK
DBL
------00B
-
-
-
-
-
-
R/W
R/W
R/W: Readable/writable
-:
Undefined bit
[bit1] WTCK: Clock selection
This bit can select the input clock for the subsecond register. The initial value is "0" and selects the
main clock oscillation as the clock source. When setting this bit to "1", the sub clock oscillation is
selected as the clock source.
This bit can be read and written.
Note:
For products not supporting 32 kHz oscillation, be sure to set the WTCK bit to "0".
If the main clock frequency is higher than 4 MHz, set this bit to "1" to select the sub clock.
[bit0] DBL: Clock disable
When this bit is set to "1", the clock of the RTC module is disabled. For normal operation, set this bit to
"0". This bit is initialized to "0". Read and write are enabled.
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CHAPTER 17 REAL TIME CLOCK
17.4 Clock Calibration Unit of Real Time Clock
17.4
MB91210 Series
Clock Calibration Unit of Real Time Clock
By using the clock calibration unit, the sub oscillation clock supplied to the RTC
module can be calibrated based on the main oscillation clock.
■ Clock Calibration Unit of Real Time Clock
By using the clock calibration unit, the signal generated by the sub clock oscillation can be measured by the
main clock oscillation using software.
The accuracy of the sub clock oscillation can be improved to that of the main clock oscillation by software
process and the use of this unit. The measurement result of the clock calibration unit can be processed by
software and obtained the required setting for the RTC module.
This unit has a timer that operates in the sub clock and another in the main clock, and the value of the main
timer is stored in the register when the sub timer triggers the main timer. The value stored in the register is
processed by software, and the required setting for the RTC module can be calculated.
■ Measurement Process Timing
Figure 17.4-1 Measurement Process Timing
Sub clock
STRT (CLKP)
STRTS (sub)
RUN (sub)
RUNS (main)
Sub counter (16-bit)
Main counter (24-bit)
CUTD
CUTD-1
2
1
Old CUTR 0
0
CUTD
New CUTR
READY (sub)
READYPULSE (CLKP)
INT (CLKP)
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CHAPTER 17 REAL TIME CLOCK
17.4 Clock Calibration Unit of Real Time Clock
MB91210 Series
■ Clock
The clock calibration unit operates using three clocks: main clock OSC4, sub clock OSC32, and peripheral
clock CLKP. Each clock area is synchronized by the synchronization circuit.
These clocks must satisfy the following conditions:
• Clock ratio
TOSC32 > 2 × TOSC4 + 3 × TCLKP
TOSC4 < 1/2 × TOSC32 - 3/2 × TCLKP
TCLKP < 1/3 × TOSC32 - 2/3 × TOSC4
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
17.5
MB91210 Series
Clock Calibration Unit Registers of Real Time Clock
This section shows a list of the clock calibration unit registers and explains the function
of each register in detail.
■ Clock Calibration Unit Registers List of Real Time Clock
Figure 17.5-1 Clock Calibration Unit Registers List of Real Time Clock
CUCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015DH
-
-
-
STRT
-
-
INT
INTEN
00000000B
R
R
R
R/W
R
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00015EH
TDD15
TDD14
TDD13
TDD12
TDD11
TDD10
TDD9
TDD8
10000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015FH
TDD7
TDD6
TDD5
TDD4
TDD3
TDD2
TDD1
TDD0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CUTD upper byte
CUTD lower byte
CUTR1 upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000160H
-
-
-
-
-
-
-
-
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000161H
TDR23
TDR22
TDR21
TDR20
TDR19
TDR18
TDR17
TDR16
00000000B
R
R
R
R
R
R
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000162H
TDR15
TDR14
TDR3
TDR12
TDR11
TDR10
TDR9
TDR8
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000163H
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
00000000B
R
R
R
R
R
R
R
R
CUTR1 lower byte
CUTR2 upper byte
CUTR2 lower byte
R/W: Readable/writable
R:
Read only
-:
Undefined bit
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
MB91210 Series
17.5.1
Calibration Unit Control Register (CUCR)
The calibration unit control register (CUCR) has the following functions:
• Starting/Stopping calibration measurement
• Enabling/Disabling interrupt
• Displaying the end of calibration measurement
■ Calibration Unit Control Register (CUCR)
Figure 17.5-2 Calibration Unit Control Register (CUCR)
CUCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015DH
-
-
-
STRT
-
-
INT
INTEN
00000000B
R
R
R
R/W
R
R/W
R/W
R/W
R/W: Readable/writable
R:
Read only
-:
Undefined bit
[bit7 to bit5] Reserved: Reserved bits
These are reserved bits.
Reading value is always "0".
[bit4] STRT: Calibration start bit
0
Stops calibration, stops the calibration unit [initial value]
1
Start calibration
When the STRT bit is set to "1" by software, a calibration is started. The sub timer starts counting down
from the value set in the sub timer data register, and the main timer starts counting up from "0".
When the sub timer reaches "0", this bit is reset to "0" automatically.
When "0" is written to this bit by software during calibration processing, the calibration stops
immediately. If writing "0" by software and resetting to "0" by hardware occur at the same time, the
operation by hardware is preferred. That is, the calibration is completed and the INT bit which indicates
the completion is set to "1". Writing "1" to this bit during calibration has no effect on operation.
[bit3] Reserved: Reserved bit
This is a reserved bit.
Reading value is always "0".
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
MB91210 Series
[bit2] Reserved: Reserved bit
This is a reserved bit.
Be sure to set this bit to "0".
[bit1] INT: Interrupt flag bit
0
In calibration process or the calibration unit suspended [initial value]
1
Calibration completed
This bit indicates the end of calibration. When the sub timer reaches "0" after a calibration starts, the
main timer data register stores the last value of the main timer and the INT bit is set to "1".
When a read-modify-write (RMW) instruction is executed for this bit, "1" is read. The INT flag is
cleared by writing "0". Writing "1" is ignored.
Because the interrupt flag (INT) is not reset by hardware, reset it by software before starting a new
calibration.
[bit0] INTEN: Interrupt enable bit
0
Disables interrupt [initial value]
1
Enables interrupt
This bit is an interrupt enable bit. If this bit is set to "1" when the INT bit (bit1) is set at the completion
of a calibration, the calibration unit sends an interrupt signal to CPU. The INT bit is automatically set
when a calibration is completed even if the interrupt is disabled (INTEN=0) regardless of the setting
value for the INTEN bit.
This bit can be read and written.
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
MB91210 Series
17.5.2
Sub Timer Data Register (CUTD)
The sub timer data register (CUTD) retains the value which determines the calibration
period (sub reload value).
■ Sub Timer Data Register (CUTD)
Figure 17.5-3 Sub Timer Data Register (CUTD)
CUTD upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00015EH
TDD15
TDD14
TDD13
TDD12
TDD11
TDD10
TDD9
TDD8
10000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015FH
TDD7
TDD6
TDD5
TDD4
TDD3
TDD2
TDD1
TDD0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CUTD lower byte
R/W: Readable/writable
The initial value of the sub timer data register is 8000H, and it corresponds to the measurement time of 1
second at 32.768 kHz.
Write to this register while calibration is stopping (STRT=0).
The sub timer data register stores the value specified for the calibration time. When a calibration starts, the
set valve is loaded to the sub timer, and counting down is performed until the timer reaches "0".
When 0000H is set to the sub timer data register, an underflow occurs and the measurement value becomes
(FFFFH+1) × TOSC32.
To set the measurement time to 1 second, set the value to 8000H. Table 17.5-1 shows the ideal values of a
measurement result (if OSC32=32.768 kHz, OSC4=4.00 MHz).
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
MB91210 Series
Table 17.5-1 Ideal Measurement Result
Calibration time
CUTD value
CUTR value
2.00 s
0000H
7A1200H
1.75 s
E000H
6ACFC0H
1.50 s
C000H
5B8D80H
1.25 s
A000H
4C4B40H
1.00 s
8000H
3D0900H
0.75 s
6000H
2DC6C0H
0.50 s
4000H
1E8480H
0.25 s
2000H
0F4240H
The processing time from writing "1" into the STRT bit to resetting of the STRT bit by hardware due to the
completion of a calibration is longer than the actual calibrating time. This is because the calibration unit
uses multiple clocks requiring synchronization with them.
• Processing time < (CUTD + 3) × TOSC32
• Calibrating time = CUTD × TOSC32
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CHAPTER 17 REAL TIME CLOCK
17.5 Clock Calibration Unit Registers of Real Time Clock
MB91210 Series
17.5.3
Main Timer Data Register (CUTR)
The main timer data register (CUTR) retains the value of calibration result (main
counter).
■ Main Timer Data Register (CUTR)
The end of calibration is shown by the INT bit and STRT bit of CUCR register.
When the INT bit is set to "1" and the STRT bit is set to "0" at the end of a calibration, the CUTR value is
enabled.
Reference:
The CUTR register value also continues to be updated during a calibration (STRT=1), and the
reading value of the CUTR register becomes the data in the calibration process as well.
Figure 17.5-4 Main Timer Data Register (CUTR)
CUTR1 upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000160H
-
-
-
-
-
-
-
-
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000161H
TDR23
TDR22
TDR21
TDR20
TDR19
TDR18
TDR17
TDR16
00000000B
R
R
R
R
R
R
R
R
CUTR1 lower byte
CUTR2 upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000162H
TDR15
TDR14
TDR3
TDR12
TDR11
TDR10
TDR9
TDR8
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000163H
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
00000000B
R
R
R
R
R
R
R
R
CUTR2 lower byte
R:
-:
Read only
Undefined bit
The main timer data register stores a calibration result. When a calibration starts, the main timer starts
counting up from "0". When the sub timer reaches "0", the main timer stops the counting, and the register
retains the calibration result until the next calibration is triggered by software (STRT=1).
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CHAPTER 17 REAL TIME CLOCK
17.6 About the Use for Clock Calibration Unit of Real Time Clock
17.6
MB91210 Series
About the Use for Clock Calibration Unit of Real Time
Clock
This section explains the accuracy of calibration and measurement time.
■ Sub Timer Data Register Setting
The setting of the sub timer data register can be calculated by the following method.
For this example, the main oscillation frequency is 4 MHz and the sub oscillation frequency is 32.768 kHz.
To set the calibration time to 1 second, set the sub timer data register to 8000H (=32768D). This indicates
32768 cycles of the sub oscillation clock.
By this setting, the value of approximately 3D0900H is stored to the main timer data register as the
calibration result. This indicates 4000000 cycles of 4 MHz oscillation.
■ Accuracy of Calibration
The calibration accuracy depends on the input clock frequency and the calibration time of the main timer.
The maximum error of the main timer is ±1. The calibration accuracy is calculated by the following method
when the input clock frequency is 4 MHz and the calibration time is 1 second.
0.25 s (input clock cycle) /1 s (calibration time) = 0.25 ppm
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CHAPTER 18
A/D CONVERTER
This chapter explains the overview of the A/D converter,
the configuration/function of the registers, and the
operation of the A/D converter.
18.1 Overview of A/D Converter
18.2 Block Diagram of A/D Converter
18.3 Registers of A/D Converter
18.4 Operation of A/D Converter
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CHAPTER 18 A/D CONVERTER
18.1 Overview of A/D Converter
18.1
MB91210 Series
Overview of A/D Converter
The A/D converter converts an analog input voltage to a digital value.
This section explains the overview of the A/D converter.
■ Features of A/D Converter
The A/D converter has the following features:
• Conversion time: Minimum of 3.0 μs per channel
• Adoption of the successive approximation conversion method with sample & hold circuit
• 10-bit resolution (switchable between 8-bit and 10-bit)
• Selection of analog input from 32 channels with MB91213A/F213A/F218S, 16 channels with
MB91F211B by software
• Conversion Mode
- Single conversion mode
: Selects and converts one channel.
- Scan conversion mode
: Converts consecutive multiple channels.
- Continuous conversion mode : Repetitiously converts a specified channel.
- Stop conversion mode
: Converts a specified channel, pauses, and waits until the next
activation occurs (conversion start can be synchronized).
• Interrupt request
When the A/D conversion ends, an interrupt request for the A/D conversion end can be generated to
CPU.
• Selectable start source
Start source is selected from software, external trigger (falling edge), or timer (rising edge).
■ Input Impedance
The sampling circuit of the A/D converter is shown as the following equivalent circuit.
Figure 18.1-1 Input Impedance
Analog signal
source
Rin
3.13 kΩ (AVCC ≥ 4.0 V)
2.54 kΩ (AVCC ≥ 4.5 V)
Rext
ANx
Analog
switch
Cin: Max
8.5pF
ADC
Set Rext not exceeding the maximum sampling time (Tsamp).
Rext = Tsamp/(7 × Cin) - Rin
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CHAPTER 18 A/D CONVERTER
18.2 Block Diagram of A/D Converter
MB91210 Series
18.2
Block Diagram of A/D Converter
Figure 18.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of A/D Converter
Figure 18.2-1 Block Diagram of A/D Converter
AVRH/
AV CC AVRL AV SS
D/A converter
MPX
Input circuit
AN0
MB91F211B: AN0 to AN15
Internal data bus
)
Comparator
Sample &
hold circuit
Decoder
(
AN31
MB91213A,
MB91F213A,
MB91F218S: AN0 to AN31
Successive approximation register
Data register
A/D control register 0
A/D control register 1
ATGX pin
16-bit reload timer 2
CLKP
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Operation
clock
Prescaler
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
18.3
MB91210 Series
Registers of A/D Converter
This section explains the configuration and function of the registers used by the A/D
converter.
■ Overview of A/D Converter Registers
The A/D converter has the following six types of registers.
• Analog input enable register (ADER)
• Control status register (ADCS)
• Data register (ADCR)
• Conversion time setting register (ADCT)
• Start channel setting register (ADSCH)
• End channel setting register (ADECH)
■ Register List
Figure 18.3-1 Register List of A/D Converter
ADERH upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000150H
ADE31
ADE30
ADE29
ADE28
ADE27
ADE26
ADE25
ADE24
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERH lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000151H
ADE23
ADE22
ADE21
ADE20
ADE19
ADE18
ADE17
ADE16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERL upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000152H
ADE15
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERL lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000153H
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
(Continued)
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
MB91210 Series
(Continued)
ADCS1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000154H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
-
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000155H
MD1
MD0
S10
ACH4
ACH3
ACH2
ACH1
ACH0
00000000B
R/W
R/W
R/W
R
R
R
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000156H
-
-
-
-
-
-
D9
D8
------XXB
-
-
-
-
-
-
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000157H
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000158H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000159H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
00101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00015AH
-
-
-
ANS4
ANS3
ANS2
ANS1
ANS0
---00000B
-
-
-
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015BH
-
-
-
ANE4
ANE3
ANE2
ANE1
ANE0
---00000B
-
-
-
R/W
R/W
R/W
R/W
R/W
ADCS0
ADCR1
ADCR0
ADCT1
ADCT0
ADSCH
ADECH
R/W:
R:
-:
X:
Readable/writable
Read only
Undefined bit
Undefined value
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
18.3.1
MB91210 Series
Analog Input Enable Register (ADER)
Always write "1" to the bit of ADER register corresponding to the pin used for analog
input.
■ A/D Enable Register (ADER)
Figure 18.3-2 A/D Enable Register (ADER)
ADERH upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000150H
ADE31
ADE30
ADE29
ADE28
ADE27
ADE26
ADE25
ADE24
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERH lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000151H
ADE23
ADE22
ADE21
ADE20
ADE19
ADE18
ADE17
ADE16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERL upper byte
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000152H
ADE15
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERL lower byte
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000153H
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
[bit15 to bit0] ADE31 to ADE0: A/D input enable
ADE
Function
0
General-purpose port [initial value]
1
Analog input
These bits are initialized to 00000000H at reset.
Be sure to write "1" to the analog input enable register of a start channel and an end channel.
Note:
Please set "0" to ADE16 to ADE31 for MB91F211B.
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
MB91210 Series
18.3.2
A/D Control Status Register (ADCS)
The A/D control status register (ADCS) controls the A/D converter and indicates the
status. Do not update the ADCS register during A/D conversion.
■ A/D Control Status Register 1 (ADCS1)
Figure 18.3-3 A/D Control Status Register 1 (ADCS1)
ADCS1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000154H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
-
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
-:
Undefined bit
[bit15] BUSY (busy flag and stop)
BUSY
Function
Read
This bit is used to indicate A/D converter operation.
This bit is set when A/D conversion starts and cleared when A/D conversion of last
channel ends.
Write
If "0" is written to this bit during A/D operation, the bit is forcibly cleared.
This bit is used to forcibly stop the operation in continuous and stop modes.
The bit for indicating the operation cannot be set to "1".
A read-modify-write (RMW) instruction always reads "1".
In single mode, the bit is cleared after completion of the A/D conversion of the last set channel.
In continuous and stop modes, the bit is not cleared until it is set to "0" to stop the operation.
This bit is initialized to "0" at reset.
Note:
Do not execute forced stop and software activation at the same time (BUSY=0, STRT=1).
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18.3 Registers of A/D Converter
MB91210 Series
[bit14] INT (interrupt)
This bit is set when conversion data is written to the ADCR.
When INTE (bit5) is "1", setting this bit generates an interrupt request.
Writing "0" clears this bit.
This bit is initialized to "0" at reset.
When using the DMA, this bit is cleared at end of the DMA transfer.
Note:
Write "0" to clear the INT bit while the A/D converter is stopped.
[bit13] INTE (interrupt enable)
This bit specifies whether to enable or disable interrupt at the end of conversion.
INTE
Function
0
Disables interrupt [initial value]
1
Enables interrupt
This bit is initialized to "0" at reset.
[bit12] PAUS (A/D converter pause)
This bit is set when an A/D conversion operation stops temporarily.
Because there is only one register to store an A/D conversion result, the conversion result must be
transferred by the DMA when conversions are performed continuously, otherwise the previous data will
be overwritten.
To protect the previous data, the next conversion data will not be stored until the data register content is
transferred by the DMA. A/D conversion operation is suspended during this time. A/D conversion
restarts when the DMA transfer ends.
• This bit is valid only when the DMA is used.
• This bit can be cleared only by writing "0" to it. (This bit is not cleared at the end of the DMA
transfer.)
However, this bit cannot be cleared in DMA transfer wait state.
• This bit is initialized to "0" at reset.
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18.3 Registers of A/D Converter
MB91210 Series
[bit11, bit10] STS1, STS0 (Start source select)
These bits are initialized to 00B at reset.
A/D start source is selected by setting these bits.
STS1
STS0
Function
0
0
Software activation [initial value]
0
1
External pin trigger activation and software activation
1
0
Timer activation and software activation
1
1
External pin trigger activation, timer activation and software activation
In a mode that enables multiple start sources, the A/D converter is activated by the first generated
source.
Since the start source setting will be changed immediately after rewriting, exercise caution when
changing a start source during A/D converter operation.
• The external pin trigger detects a falling edge. If the external trigger input level is "L", the A/D
converter can be activated when this bit is rewritten to set external pin trigger activation.
• When selecting the timer, 16-bit reload timer 2 is selected.
[bit9] STRT (Start)
Writing "1" to this bit restarts the A/D converter (software activation).
To restart, write "1" to this bit again.
This bit is initialized to "0" at a reset.
In continuous mode and stop mode, restart cannot be used due to its operation function. Check the
BUSY bit before writing "1" to this bit. (Activate it after clearing the BUSY bit.)
Do not execute forced stop and software activation at the same time (BUSY=0, STRT=1).
[bit8] Reserved bit
Be sure to set this bit to "0".
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18.3 Registers of A/D Converter
MB91210 Series
■ A/D Control Status Register 0 (ADCS0)
Figure 18.3-4 A/D Control Status Register 0 (ADCS0)
ADCS0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000155H
MD1
MD0
S10
ACH4
ACH3
ACH2
ACH1
ACH0
00000000B
R/W
R/W
R/W
R
R
R
R
R
R/W: Readable/writable
R:
Read only
[bit7, bit6] MD1, MD0 (A/D converter mode set)
These bits are used to set the operation mode.
These bits are initialized to 00B at reset.
MD1
MD0
Operation mode
0
0
Single mode [initial value]
0
1
Single mode
1
0
Continuous mode
1
1
Stop mode
• Single mode
A/D conversion is continuously performed for the channels set by ANS4 to ANS0 up to the channels
set by ANE4 to ANE0, and the conversion stops when the conversion of all channel ends.
• Continuous mode
A/D conversion is performed repeatedly for the channels set by ANS4 to ANS0 up to the channels
set by ANE4 to ANE0.
• Stop mode
A/D conversion is performed for the channels set by ANS4 to ANS0 up to the channels set by ANE4
to ANE0, but operation stops temporarily for each channel. The A/D conversion is restarted by the
start source generation.
• When A/D conversion is activated in continuous and stop modes, the conversion operation continues
until it is stopped forcibly by the BUSY bit.
• To stop the conversion operation forcibly, set the BUSY bit to "0".
• The A/D conversion is performed from the channels set by ANS4 to ANS0 at the activation after
forced stop.
• When A/D conversion cannot be restarted in single, continuous or stop mode, it will be applied to all
the activations by timer, external trigger and software.
[bit5] S10
This bit specifies the resolution of the conversion. When this bit is set to "0", a 10-bit A/D conversion is
performed. Otherwise, an 8-bit A/D conversion is performed, and the result is stored in the ADCR0.
This bit is initialized to "0" at reset.
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18.3 Registers of A/D Converter
MB91210 Series
[bit4 to bit0] ACH4 to ACH0 (Analog convert select channel)
These bits indicate the channel where an A/D conversion is in progress.
These bits are initialized to 00000B at a reset.
CM71-10139-5E
ACH4
ACH3
ACH2
ACH1
ACH0
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
1
1
0
0
0
AN24
1
1
0
0
1
AN25
1
1
0
1
0
AN26
1
1
0
1
1
AN27
1
1
1
0
0
AN28
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
MB91210 Series
ACH
Function
Read
During an A/D conversion (BUSY bit=1), the current conversion channel is indicated
by these bits.
When stopped by forced stop (BUSY bit=0), the channel where the conversion is
stopped is indicated.
Write
Writing to these bits is ignored.
Note:
Writing a value other than the set value described in the table to the register is prohibited.
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CHAPTER 18 A/D CONVERTER
18.3 Registers of A/D Converter
MB91210 Series
18.3.3
Data Register (ADCR1, ADCR0)
The data register (ADCR1, ADCR0) is used to store a digital value generated as a result
of conversion. The ADCR0 stores the lower 8 bits, and ADCR1 stores the most
significant 2 bits of the conversion result. These register values are rewritten every time
a conversion ends. Generally, the last converted value is stored in this register.
■ Data Register (ADCR1, ADCR0)
Figure 18.3-5 Data Register (ADCR1, ADCR0)
ADCR1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000156H
-
-
-
-
-
-
D9
D8
------XXB
-
-
-
-
-
-
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000157H
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
ADCR0
R:
-:
X:
Read only
Undefined bit
Undefined value
000000B is always read from bit15 to bit10 of the ADCR1.
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18.3 Registers of A/D Converter
MB91210 Series
Conversion Time Setting Register (ADCT)
18.3.4
The A/D conversion time setting register (ADCT) controls the sampling time and
comparison time of analog input. The A/D conversion time is set by setting the ADCT
register.
Do not rewrite the ADCT register during an A/D conversion.
■ Conversion Time Setting Register (ADCT)
Figure 18.3-6 Conversion Time Setting Register (ADCT)
ADCT1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000158H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000159H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
00101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCT0
R/W: Readable/writable
[bit15 to bit10] CT5 to CT0 (A/D comparison time set)
Setting these bits specifies the clock division value of the comparison operation time.
When set the CT5 to CT0 to 000001B, it becomes no division = CLKP.
Do not set the CT5 to CT0 to 000000B.
These bits are initialized to 000100B at reset.
Comparison operation time (Compare Time) =
CT set value × CLKP cycle × 10 + (4 × CLKP cycle)
Note:
Set comparison operation time not exceeding 500 μs.
The minimum value for comparison operation time is 1.1 μs.
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18.3 Registers of A/D Converter
MB91210 Series
[bit9 to bit0] ST9 to ST0 (A/D input sampling time set)
Setting these bits specifies the sampling time of analog input.
These bits are initialized to 0000101100B at reset.
Sampling time (Sampling Time) = ST set value × CLKP cycle
Calculate the required sampling time and ST set time using the following formula:
Required sampling time (Tsamp) = (Rext + Rin) × Cin × 7
ST9 to ST0 set value = Required sampling time (Tsamp) / CLKP cycle
Set the ST set value so that A/D sampling time is greater than the required sampling time.
Example: If CLKP=40MHz, AVCC ≥ 4.5V, Rext = 200 kΩ
Tsamp = (200 × 103 + 2.54 × 103) × 8.5 × 10-12 × 7 = 12.05 μs
ST = 12.05-6 / 25-9 = 482.01 → Set 483 (0111100011B) or higher.
Note:
When AVCC is less than 4.5V, do not set the sampling time to 1.1 μs or less.
The required sampling time is determined by the Rext value so the Rext should be determined by
taking the conversion time into consideration.
Please do not set the ST9 to ST0 to 0000000000B, 0000000001B, and 0000000010B.
■ Recommended Set Value
It is recommended to use the following set value to obtain an appropriate conversion time.
(AVCC ≥ 4.5V, Rext ≤ 15kΩ)
CM71-10139-5E
CLKP
(MHz)
Comparison operation
time (CT5 to CT0)
Sampling time
(ST9 to ST0)
ADCT set
value
Conversion time
(μs)
16
000010B
0000010001B
0811H
1.1 + 1.500 = 2.600
24
000011B
0000011010B
0C1AH
1.1 + 1.417 = 2.517
32
000100B
0000100010B
1022H
1.1 + 1.375 = 2.475
40
000100B
0000101010B
102AH
1.1 + 1.100 = 2.200
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18.3 Registers of A/D Converter
18.3.5
MB91210 Series
Start Channel Setting Register (ADSCH)
End Channel Setting Register (ADECH)
These registers set the start channel and end channel of an A/D conversion.
Do not rewrite the ADSCH and ADECH during an A/D conversion.
■ Start Channel Setting Register (ADSCH) /End Channel Setting Register (ADECH)
Figure 18.3-7 Start Channel Setting Register (ADSCH), End Channel Setting Register (ADECH)
ADSCH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00015AH
-
-
-
ANS4
ANS3
ANS2
ANS1
ANS0
---00000B
-
-
-
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00015BH
-
-
-
ANE4
ANE3
ANE2
ANE1
ANE0
---00000B
-
-
-
R/W
R/W
R/W
R/W
R/W
ADECH
R/W: Readable/writable
-:
Undefined bit
These bits set the start channel and end channel of an A/D conversion.
When the same channels are written to the ANS4 to ANS0 and ANE4 to ANE0, the conversion is
performed for one channel (single channel conversion).
When continuous mode or stop mode is being set, it returns to the start channel set by the ANS4 to ANS0
after the conversion of the channels set by these bits ends.
When the set channel is ANS > ANE, the conversion starts from ANS. If the conversion is performed up to
31 channels, it returns to 0 channel and is performed up to ANE.
These bits are initialized to ANS=00000B and ANE=00000B at reset.
For example, if the channel setting is ANS=6 channels and ANE=3 channels in single mode, the conversion
will be performed in the following order:
6 channels → 7 channels → 8 channels → ... → 30 channels → 31 channels → 0 channel →
1 channel → 2 channels → 3 channels
Note:
Do not set the bits in this register by a read-modify-write (RMW) instruction after setting the start
channel in the A/D conversion start channel selection bits.
If the bits in this register are set by a read-modify-write (RMW) instruction after setting the start
channel in the ANS0 to ANS4 bits, the value of these bits may be rewritten since the previous
conversion channel is read from the ANS0 to ANS4 bits until an A/D conversion operation starts.
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18.3 Registers of A/D Converter
MB91210 Series
[bit12 to bit8] ANS4 to ANS0 (A/D start channel set)
[bit4 to bit0] ANE4 to ANE0 (A/D end channel set)
CM71-10139-5E
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
Start/End channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
1
1
0
0
0
AN24
1
1
0
0
1
AN25
1
1
0
1
0
AN26
1
1
0
1
1
AN27
1
1
1
0
0
AN28
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
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CHAPTER 18 A/D CONVERTER
18.4 Operation of A/D Converter
18.4
MB91210 Series
Operation of A/D Converter
The A/D converter operates using the successive approximation method and can select
a 10-bit or 8-bit resolution. This section explains the operation modes of the A/D
converter.
■ A/D Conversion Data
The conversion data register (ADCR0 and ADCR1) is rewritten each time a conversion is completed
because this A/D converter has only one register for storing a conversion result (16-bit). Therefore, it is
recommended to convert by transferring the conversion data to memory using DMA since the A/D
converter is not suitable for the continuous conversion process by itself.
■ Single Mode
This mode sequentially converts the analog input specified by the ANS and ANE bits and the A/D stops its
operation after completing the conversion up to the end channel specified by the ANE bit. A conversion
operation is performed for either of the channels if the start and end channels are the same (ANS=ANE).
[Examples]
• ANS=00000B, ANE=00011B
Start → AN0 → AN1 → AN2 → AN3 → End
• ANS=00010B, ANE=00010B
Start → AN2 → End
■ Continuous Mode
This mode sequentially converts the analog input specified by the ANS and ANE bits, returns to the analog
input of ANS after completing the conversion up to the end channel specified by the ANE bit, and
continues the conversion operation. A conversion operation is continued for either of the channels if the
start and end channels are the same (ANS=ANE).
[Examples]
• ANS=00000B, ANE=00011B
Start → AN0 → AN1 → AN2 → AN3 → AN0 → AN1 (repeated)
• ANS=00010B, ANE=00010B
Start → AN2 → AN2 → AN2 (repeated)
A conversion in continuous mode continues repeatedly until "0" is written to the BUSY bit (writing "0" to
the BUSY bit → forced termination). Note that a conversion is stopped before it is completed when
forcibly terminate the operation. (If operation is forcibly terminated, the conversion register holds the
previous data that the conversion has been completed.)
■ Stop Mode
This mode sequentially converts the analog input specified by the ANS and ANE bits and temporarily stops
the operation each time a conversion has been performed for one channel. To clear the temporary stop,
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18.4 Operation of A/D Converter
MB91210 Series
restart the A/D converter.
This mode returns to the analog input of ANS after performing a conversion up to the end channel specified
by the ANE bit and then continues the conversion operation. A conversion operation is performed for either
of the channels if the start and end channels are the same (ANS=ANE).
[Examples]
• ANS=00000B, ANE=00011B
Start → AN0 → Stop → Start → AN1 → Stop → Start → AN2 → Stop → Start → AN3 → Stop →
Start → AN0 → Stop → Start → AN1 (repeated)
• ANS=00010B, ANE=00010B
Start → AN2 → Stop → Start → AN2 → Stop → Start → AN2 (repeated)
Only start sources specified by STS1 and STS0 are used in this case.
This mode can be used to synchronize the conversion start.
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18.4 Operation of A/D Converter
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CHAPTER 19
FLASH MEMORY
This chapters gives an overview of flash memory and
describes the register configuration/functions and the
operations.
19.1 Overview of Flash Memory
19.2 Flash Memory Registers
19.3 Operations of Flash Memory
19.4 Flash Memory Automatic Algorithms
19.5 Details of Programming and Erasing Flash Memory
19.6 Restrictions on Data Polling Flag (DQ7) and How to Avoid
Problems
19.7 Notes on Flash Memory Programming
Code: CM71-00501-2E
Page: 490
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CHAPTER 19 FLASH MEMORY
19.1 Overview of Flash Memory
19.1
MB91210 Series
Overview of Flash Memory
The MB91210 series contains 288 Kbytes (MB91F211B) /544 Kbytes (MB91F213A/F218S)
of flash memory.
The built-in flash memory enables to erase either by sector or in all of the sectors
collectively, and program data in halfwords (16-bit units), via the FR-CPU.
Overview of Flash Memory
When used as internal ROM for the FR-CPU, the flash memory allows instructions and data to be read
from in words (32 bits), contributing to high-speed operation of the device.
This series provides the following features using the combination of the internal flash memory and FRCPU interface circuit:
• Serving as the CPU's memory for storing programs and data
(Hereafter referred to as CPU mode)
- Accessible at a bus width of 32 bits when used as ROM
- Capable of being read/programmed/erased by the CPU instruction
(Automatic algorithm*)
• Functions as discrete flash memory
(Hereafter referred to as FLASH mode)
- Capable of being read/programmed/erased by a ROM programmer
(Automatic algorithm*)
The following describes the use of the flash memory from the FR-CPU.
For details on using this flash memory with a ROM programmer, refer to the instruction manual for the
ROM programmer.
*: Automatic algorithm = Embedded Algorithm
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CHAPTER 19 FLASH MEMORY
19.1 Overview of Flash Memory
MB91210 Series
■ Block Diagram of Flash Memory
Figure 19.1-1 is a block diagram of the flash memory.
Figure 19.1-1 Block Diagram of Flash Memory
RDY/BUSYX
Rising edge detection
Control signal
generation
RESETX
BYEX
OEX
Flash memory
RDY
WE
Bus control signal
WEX
CEX
FA18 to FA0 DI15 to DI0 DO31 to DO0
Address buffer
FA18 to FA0
Data buffer
FD31 to FD0
FR F-bus (instruction/data)
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CHAPTER 19 FLASH MEMORY
19.1 Overview of Flash Memory
MB91210 Series
■ Memory Map of Flash Memory
Figure 19.1-2 and Figure 19.1-3 shows the memory map of flash memory in each mode.
Figure 19.1-2 Memory Map of Flash Memory (544K bytes)
CPU mode
Flash memory mode
0000 0000 H
I/O, etc
0007 8000 H
0007 8000 H
32 bits
8/16 bits
544K bytes
Flash memory
544K bytes
Flash memory
000F FFFF H
000F FFFF H
FFFF FFFF H
Figure 19.1-3 Memory Map of Flash Memory (288K bytes)
CPU mode
Flash memory mode
0000 0000 H
I/O, etc
000B 8000 H
000B 8000 H
32 bits
8/16 bits
288K bytes
Flash memory
000F FFFF H
288K bytes
Flash memory
000F FFFF H
FFFF FFFF H
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CHAPTER 19 FLASH MEMORY
19.1 Overview of Flash Memory
MB91210 Series
■ Sector Address Table of Flash Memory
● Flash memory sector map (544K bytes)
078000H
SA4 (64 K bytes)
088000H
SA5 (64 K bytes)
098000H
SA6 (64 K bytes)
0A8000H
SA7 (64 K bytes)
0B8000H
SA8 (64 K bytes)
0C8000H
SA9 (64 K bytes)
0D8000H
SA10 (64 K bytes)
0E8000H
SA11 (64 K bytes)
0F8000H
0FA000H
0FC000H
0FE000H
100000H
SA0 (8 K bytes)
SA1 (8 K bytes)
SA2 (8 K bytes)
SA3 (8 K bytes)
32 bits
● Flash memory sector map (288K bytes)
0B8000H
SA4 (64 K bytes)
0C8000H
SA5 (64 K bytes)
0D8000H
SA6 (64 K bytes)
0E8000H
SA7 (64 K bytes)
0F8000H
0FA000H
0FC000H
0FE000H
100000H
SA0 (8 K bytes)
SA1 (8 K bytes)
SA2 (8 K bytes)
SA3 (8 K bytes)
32 bits
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
19.2
MB91210 Series
Flash Memory Registers
This section describes the configuration and functions of the registers used for flash
memory.
■ Overview of Flash Memory Registers
The flash memory has the following two registers:
• FLCR: Flash memory control/status register (CPU mode)
• FLWC: Flash memory wait register
Figure 19.2-1 Register List of Flash Memory Registers
FLCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007000H
R
R
R
R
RDY
R
R/W
WE
R/W
R/W
0000X101B
FLWC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007004H
FAC1
R/W
FAC0
R/W
WTW2
R/W
WTW1
R/W
WTW0
R/W
WTR2
R/W
WTR1
R/W
WTR0
R/W
01011011B
R/W:
R:
-:
X:
494
Readable/writable
Read only
Undefined bit
Undefined value
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
MB91210 Series
19.2.1
Flash Memory Control/Status Register (FLCR)
The flash memory control/status register (FLCR) indicates the operating status of the
flash memory. It also controls the writing to the flash memory.
Do not use any read-modify-write (RMW) instruction to access this register.
■ Bit Configuration of Flash Memory Control/Status Register (FLCR)
The flash memory control/status register (FLCR) consists of the following bits:
Figure 19.2-2 Flash Memory Control/Status Register (FLCR)
FLCR
Address
007000H
bit7
R
bit6
R
bit5
R
bit4
R
bit3
RDY
R
bit2
R/W
bit1
WE
R/W
bit0
Initial value
R/W
0000X101B
R/W: Readable/writable
R:
Read only
X:
Undefined value
This register controls the writing to the flash memory.
Do not use any read-modify-write (RMW) instruction to access the register.
[bit7 to bit4] Reserved: Reserved bits
These bits are reserved bits.
The value read is 0000B.
[bit3] RDY: Ready
This bit indicates the operating status of an automatic algorithm (data write/erase).
When this bit is "0", data is written to or erased from the flash memory with the automatic algorithm,
unable to accept another data write or erase command. In addition, no data can be read from a flash
memory area.
The data read from this bit indicates the current status of the flash memory.
RDY
Function
0
Indicates that flash memory is being data written to or erased from, not ready to accept
a data write, read, or erase command.
1
Indicates that flash memory is ready to accept a data read, data write, or erase
command.
• This bit is not initialized at the time of reset (the bit value depends on the state of the flash memory
at that point).
• The bit is for read -only; an attempt to write to it has no effect on its value.
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[bit2] Reserved: Reserved bit
This bit is a reserved bit.
Be sure to set this bit to "0".
[bit1] WE: Write enable
This bit controls the writing (programming) of data and commands into flash memory.
While this bit contains "0", any attempt to program data or a command into flash memory is ignored.
While the bit contains "1", the programming of data and commands into flash memory is valid, where
the automatic algorithm can be started.
Before updating the WE bit, be sure to check the RDY bit to make sure that the automatic algorithm
(data write/erase) has been stopped. The WE bit value cannot be updated with the RDY bit set to "0".
WE
Function
0
Disables write access to flash memory. [Initial value]
1
Enables write access to flash memory.
• This bit is initialized to "0" at a reset.
• The bit is readable and writable.
[bit0] Reserved: Reserved bit
This bit is a reserved bit.
Be sure to set the bit to "0".
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
MB91210 Series
19.2.2
Flash Memory Wait Register (FLWC)
The flash memory wait register (FLWC) controls the wait state for flash memory access.
■ Bit Configuration of Flash Memory Wait Register (FLWC)
The flash memory wait register (FLWC) consists of the following bits:
Figure 19.2-3 Flash Memory Wait Register (FLWC)
FLWC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007004H
FAC1
R/W
FAC0
R/W
WTW2
R/W
WTW1
R/W
WTW0
R/W
WTR2
R/W
WTR1
R/W
WTR0
R/W
01011011B
R/W: Readable/writable
The value of this register is not updated only by write access to the register. Reading the register after write
access reflects the value and updates the register value.
[bit7, bit6] FAC1, FAC0: Access control bits
These bits are set to control internal pulse generation for flash memory control. The ATDIN/EQIN
pulse width can be set by setting these bits.
Be sure to set the bits to a value that matches the wait cycle setting (WTR2 to WTR0).
CM71-10139-5E
FAC1
FAC0
ATDIN
EQIN
Remarks
0
0
0.5 clock
1.0 clock
1 wait cycle for read
0
1
1.0 clock
1.0 clock
2 or 3 wait cycles for read [Initial value]
1
0
0.5 clock
1.5 clock
Setting prohibited
1
1
1.0 clock
1.5 clock
Setting prohibited
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19.2 Flash Memory Registers
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[bit5 to bit3] WTW2 to WTW0: Write wait cycle bits
WTW2
WTW1
WTCW0
Wait cycle
Remarks
0
0
0
—
Setting prohibited
0
0
1
1
Setting prohibited
0
1
0
2
Setting prohibited
0
1
1
3
Initial value
1
0
0
4
Setting prohibited
1
0
1
5
Setting prohibited
1
1
0
6
Setting prohibited
1
1
1
7
Setting prohibited
• These bits are initialized to 011B at a reset.
• Do not set the bits to other than 011B.
[bit2 to bit0] WTR2 to WTR0: Read wait cycle bits
WTR2
WTR1
WTR0
Wait cycle
Remarks
0
0
0
—
Setting prohibited
0
0
1
1
0
1
0
2
0
1
1
3
Initial value
1
0
0
4
Setting prohibited
1
0
1
5
Setting prohibited
1
1
0
6
Setting prohibited
1
1
1
7
Setting prohibited
• These bits are initialized to 011B at a reset.
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CHAPTER 19 FLASH MEMORY
19.3 Operations of Flash Memory
MB91210 Series
19.3
Operations of Flash Memory
This section describes the operations of flash memory.
■ Flash Memory Access Modes
The following two types of access modes are available to the FR-CPU to access flash memory:
• ROM mode
The CPU can fetch instructions from flash memory. It can read word (32-bit) data collectively but
cannot write data.
• Programming mode
The CPU cannot fetch instructions from flash memory but can write halfword (16-bit) data.
■ FR-CPU ROM Mode (Read-only in 32/16/8 Bits)
In this mode, the flash memory serves as internal ROM for the FR-CPU. The CPU can read a word (32
bits) of data collectively but can neither program data into flash memory nor start the automatic algorithm.
• Specifying the access mode
- Setting the WE bit in the flash memory control/status register (FLCR) to "0" places the flash memory
in this mode.
- The flash memory enters this mode whenever a reset is cleared during CPU operation.
• Operation
When reading a flash memory area, the CPU can read a word (32 bits) of data collectively from
memory.
• Restrictions
In this mode, you cannot program a command or data into flash memory.
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■ FR-CPU Programming Mode (Read/Write Enabled in 16 Bits)
In this mode, the CPU can erase/ program data from/into flash memory. The program in flash memory
cannot be executed during operation in this mode.
• Specifying the access mode
- Setting the WE bit in the flash memory control/status register (FLCR) to "1" places the flash memory
in this mode.
- The WE bit is set to "0" after a reset is cleared during CPU operation. To specify this mode, write "1"
to the bit. The flash memory returns to ROM mode when the WE bit is set to "0" by writing "0" to the
bit or causing a reset.
- When the RDY bit in the flash memory control/status register (FLCR) is "0", the WE bit cannot be
updated. Make sure that the RDY bit is set to "1" before updating the WE bit.
• Operation
- When reading a flash memory area, the CPU reads a halfword (16 bits) of data collectively from
memory.
- You can start an automatic algorithm by programming the command into flash memory. You can
erase data from or program data into flash memory by starting the automatic algorithm. For details on
the automatic algorithm, see "19.4 Flash Memory Automatic Algorithms".
• Restrictions
This mode prohibits access except in halfwords (16 bits).
■ Automatic Algorithm Execution Status
When you start an automatic execution algorithm in FR-CPU programming mode, you can see the
operating the status of the automatic algorithm by the RDY bit in the flash memory control/status register
(FLCR).
When the RDY bit is "0", a data write or erase operation is being performed by the automatic algorithm,
preventing another data write or erase command from being accepted. In addition, no data can be read from
any flash memory area.
The data read when the RDY bit is "0" serves as the hardware sequence flag that indicates the status of the
flash memory.
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CHAPTER 19 FLASH MEMORY
19.4 Flash Memory Automatic Algorithms
MB91210 Series
19.4
Flash Memory Automatic Algorithms
This section details the command sequence for flash memory automatic algorithms, the
method of checking their execution status, and programming/erasing flash memory.
■ Overview of Flash Memory Automatic Algorithms
There are four types of commands to invoke their respective flash memory automatic algorithms: Reset,
Data Program, Chip Erase, and Sector Erase. For the Sector Erase command, it is possible to control the
suspending and resuming of its execution.
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19.4 Flash Memory Automatic Algorithms
19.4.1
MB91210 Series
Command Sequence
This section explains the command sequence to start each automatic algorithm.
■ Command Sequences for Automatic Algorithms
To start an automatic algorithm, program halfword (16-bit) data into flash memory once to six times
consecutively. That is called a command.
The flash memory is reset to the read mode if invalid addresses and data are programmed or if addresses
and data are programmed in a wrong order. Table 19.4-1 lists command sequences.
For data write access from the FR-CPU, program data into flash memory in units of halfword (16-bit)
(addresses are those assigned in CPU mode).
Table 19.4-1 Command Sequence Table
Command sequence
Access
count
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
6th cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Reset
1
XXXXH
XXF0H
—
—
—
—
—
—
—
—
—
—
Reset
3
DAAA8H
XXAAH
D5554H
XX55H
DAAA8H
XXF0H
—
—
—
—
—
—
Data program
4
DAAA8H
XXAAH
D5554H
XX55H
DAAA8H
XXA0H
PA
PD
—
—
—
—
Chip erase
6
DAAA8H
XXAAH
D5554H
VV55H
DAAA8H
XX80H
DAAA8H
XXAAH
D5554H
XX55H
DAAA8H
XX10H
Sector erase
6
DAAA8H
XXAAH
D5554H
XX55H
DAAA8H
XX80H
DAAA8H
XXAAH
D5554H
XX55H
SA
XX30H
Sector erase suspend
Sector erasure is suspended when address = XXXXXH and data = XXB0H are programmed.
Sector erase resume
Suspended sector erasure is resumed when address = XXXXXH and data = XX30H are programmed.
PA : Program (write) address
SA : Sector address (Specify one arbitrary address in a sector.)
PD : Programmed (written) data
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CHAPTER 19 FLASH MEMORY
19.4 Flash Memory Automatic Algorithms
■ Reset Command
The reset command places the flash memory in read/reset mode. The flash memory remains in the read
state until another command is input. The flash memory enters the read/reset mode automatically when the
power is turned on. In this case, no data read command is required.
To return to the read mode after the timing limit is exceeded, issue the reset command sequence. Data is
read from flash memory in the read cycle.
■ Program (Data Write)
In CPU programming mode, data is programmed into flash memory in units of halfword. Data program is
performed by programming 4 cycles of the command sequence. Programming data is started by the last
write cycle of the command sequence.
Once the data program command sequence is executed, the flash memory does not require further external
control.
The flash memory starts the automatic algorithm, sets the data polling flag(DQ7) to a value that inverts the
written value of bit7, and generates an internally produced appropriate programming pulse to verify the
margins of programmed cells. When the automatic algorithm has terminated, the data polling flag(DQ7)
becomes the same value as the value programmed into bit7. Then the flash memory returns to the read
mode. In this way, data polling flag (DQ7) indicates that data is being programmed into the flash memory.
During executing data program automatic algorithm, any command programmed into flash memory is
ignored. If a hardware reset is activated during programming data at an address, the data at that address is
not guaranteed.
Programming data is allowed in any order of addresses or beyond the boundaries of sectors.
Data "0" that has already programmed into the flash memory cannot be returned to data "1" by writing data.
If data "1" is programmed over data "0", either the data polling algorithm determines that the element is
defective or data "1" apparently looks as if it were programmed. When the data is read in reset/read mode,
however, it remains as "0". Data "0" can be updated to data "1" only through an erase operation.
■ Chip Erase
Chip erasure (erasing all of the sectors collectively) of the command sequence is executed in six program
operations. Chip erase is started by entering the chip erase command.
Before chip erasing, the user need not perform programming data into flash memory. During execution of
the chip erase automatic algorithm, the flash memory automatically verifies its cells by programming
patterns of "0" (preprogramming) before erasing all the cells. During preprogramming, the flash memory
requires no external control.
Chip erase automatic algorithm is started by programming in the command sequence and terminates when
the data polling flag (DQ7) is set to "1", the flash memory returns to the read mode. The chip erase time is
"sector erase time × the number of all sectors + chip program (preprogram) time".
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19.4 Flash Memory Automatic Algorithms
MB91210 Series
■ Sector Erase
Sector erasure is performed by programming 6 cycles of the command sequence. The sector erase
command is programmed in the sixth cycle to start erasing a sector.
During a minimum of 50 μs sector erase time-out period after the last sector erase command is
programmed, the next sector erase command can be accepted.
The erasing of multiple sectors can be accepted at the same time of programming is the sixth cycle of the
command sequence. This sequence is executed by programming the sector erase command (XX30H)
continuously at the addresses of the sectors to be erased at the same time.
When a minimum of 50 μs sector erase time-out period after the last sector erase command is programmed
expires, the flash memory starts erasing the sectors. To erase multiple sectors at the same time, therefore,
the sector erase command for each of the sectors must be input within a time-out period of 50 μs, or the
command may not be accepted if it expires. You can check whether the successive sector erase command is
valid by monitoring the sector erase timer flag (DQ3) (see "■ Hardware Sequence Flag" in "19.4.2
Confirming Automatic Algorithm Execution States").
If any command other than the sector erase command and erase suspend command is input in a sector erase
time-out period, the flash memory is reset to the read mode and invalidates the preceding command
sequence. In this case, the relevant sector is erased completely by erasing it again. Sector addresses can be
input to the sector erase buffer for any number of sectors in any combination.
Sector erase is started after a minimum of 50 μs sector erase time-out period since the last sector erase
command is programmed, and terminates when data polling flag (DQ7) is set to "1". The flash memory
returns to the read mode.
Data polling flag (DQ7) works for any address in the sectors erased. The multiple-sector erase
time is "(sector erase time + sector program (preprogram) time) × the number of sectors erased".
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CHAPTER 19 FLASH MEMORY
19.4 Flash Memory Automatic Algorithms
■ Erase Suspend
The erase suspend command allows the user to suspend the flash memory automatic algorithm during
erasure of sectors in order to read data from or program data into other sectors. This command is valid only
during sector erasure; it is ignored during chip erasure or programming data.
The erase suspend command (B0H) is valid only during the period of sector erasure, including the sector
erasure time-out period after the sector erase command (XX30H). When this command is input during the
sector erase time-out period, the flash memory terminates the time-out immediately to suspend erasure. The
flash memory restarts erasure when the erase resume command is programmed. The erase suspend and
resume commands can be programmed with any address.
When the erase suspend command is input during sector erasure, it takes a maximum of 20 μs for the flash
memory to suspend erasure. When the flash memory enters the erase suspend mode, the RDY bit in the
flash memory control/status register (FLCR) and the data polling flag (DQ7) output "1", and toggle bit flag
(DQ6) stops toggling. You can check whether erasure is suspended by inputting the sector address being
erased to monitor the values read from the toggle bit flag (DQ6) and data polling flag(DQ7). An attempt to
program another erase suspend command is ignored.
When erasure is suspended, the flash memory enters the erase-suspend read mode. Data reading in this
mode is the same as typical data reading, except that it is effective for sectors not being erase-suspended. In
erase-suspend read mode, the toggle bit 2 (DQ2) toggles for continuous reading from the sector being
erase-suspended.
In erase-suspend read mode, the user can program data into flash memory by programming the data
program command sequence. This program mode is the erase-suspend program mode. Programming data in
this mode is the same as normal data writing, except that it is effective for sectors containing data not being
erase-suspended. In erase-suspend program mode, the toggle bit 2 (DQ2) toggles for continuous reading
from the sector being erase-suspended. The erase suspend state can be detected by checking the erase
suspend bit (bit6).
Note that the data polling flag (DQ7) must be read for the address being programmed while the toggle bit
flag (DQ6) can be read for any address.
To restart sector erasure, input the sector erase resume command (XX30H). Another resume command is
ignored if input when sector erasure is restarted. In contrast, the erase suspend command can be input after
the flash memory resumes erasure.
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19.4 Flash Memory Automatic Algorithms
19.4.2
MB91210 Series
Confirming Automatic Algorithm Execution States
This flash memory executes the automatic algorithm for data program/erase flow.
This automatic algorithm enables confirmation of the operating state of the internal
flash memory using the following hardware sequence flag.
■ RDY Bit
Besides the hardware sequence flag, the flash memory has the RDY bit in the flash memory status register
(FLCR). As a method of indicating whether an internal automatic algorithm is now executing or ended.
When the read value of the RDY bit is "0", data is being programmed or erased into the flash memory, not
ready to accept the data program or erase command. When the read value of the RDY bit is "1", the flash
memory is ready for a read/data program or erase operation.
■ Hardware Sequence Flag
Figure 19.4-1 shows the bit configuration of the hardware sequence flag.
Figure 19.4-1 Bit Configuration of Hardware Sequence Flag
bit15
For halfword read
bit8 bit7
(undefined value)
For byte read
Odd-numbered
addresses only
bit7
DPOLL
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Hardware
sequence flag
Hardware
sequence flag
bit0
TOGGLE TLOVER undefined SETIMR TOGGL2 undefined undefined
The hardware sequence flag can be obtained as data by reading an arbitrary address (an odd-numbered
address during byte access) in flash memory during execution of the automatic algorithm. The obtained
data contains five effective bits, each of which indicates a state of the automatic algorithm.
Note that these flag bits are meaningless in FR-CPU ROM mode. Be sure to read them in FR-CPU
programming mode.
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19.4 Flash Memory Automatic Algorithms
MB91210 Series
Table 19.4-2 lists hardware sequence flag states.
Table 19.4-2 Hardware Sequence Flag State List
State
DPOLL
Inverted
data
Toggle
0
0
1
0
Toggle
0
1
Toggle
Time-out period
1
Toggle
0
1
Toggle
Erase period
0
Toggle
0
1
Toggle
Reading (Sector being erased)
1
1
0
0
Toggle
Data
Data
Data
Data
Data
Inverted
data
Toggle
0
0
1 *1
Inverted
data
Toggle
1
0
1
0
Toggle
1
1
*2
Data program
Chip erase
Executing
Sector erase
Erase suspend
Reading (Sector not being erased)
Data programming
(Sector not being erased)
Time limit
over
TOGGLE TLOVER SETIMR TOGGL2
Data program
Chip/sector erase
*1: In the erase-suspended programming state, the TOGGL2 bit is "1" during a read from the address being programmed.
The TOGGL2 bit toggles during a continuous read from the sector being erase-suspended.
*2: When the TLOVER bit is "1" (time limit over), the TOGGL2 bit toggles for continuous read access to the sector being
programmed/erased; it does not toggle for read access to other sectors.
The individual bits listed above are designated as follows:
CM71-10139-5E
[bit7] : DPOLL
: Data polling flag (DQ7)
[bit6] : TOGGLE
: Toggle bit flag (DQ6)
[bit5] : TLOVER
: Timing limit over flag (DQ5)
[bit3] : SETIMR
: Sector erase timer flag (DQ3)
[bit2] : TOGGL2
: Toggle bit2 flag (DQ2)
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The following summarizes each of the flag bits:
[bit7] DPOLL: Data polling flag (DQ7)
The data polling flag uses a data polling function to indicate that the execution of the automatic
algorithm is currently in progress or completed.
• During a data program operation:
When the flash memory is read-accessed during execution of the automatic algorithm, it outputs the
inverted version of data finally written to bit7 without accessing the address located by the address
signal.
When the flash memory is read-accessed upon completion of the automatic algorithm, it outputs bit7
of the value read from the address located by the address signal.
• During a chip erase operation:
When the flush memory is read-accessed during execution of the chip erase automatic algorithm, it
outputs "0" irrespective of the address located by the address signal. In the same way, the flash
memory outputs "1 " when the algorithm is completed.
• During a sector erase operation:
When the flash memory is read-accessed from the sector being erased during execution of the sector
erase automatic algorithm, it outputs "0". Due to restrictions on the function in this series, the flash
memory outputs "1" for 50 to 160 μs after the sector erase command is issued, and then outputs "0".
After the sector erase is terminated, the flash memory outputs "1".
For restrictions on the data polling flag (DQ7) and how to avoid problems at sector erase, see section
"25.9 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems".
• During sector erasure suspended:
When the flash memory is read-accessed during suspended sector erasure, it outputs "1" if the
address located by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, the flash memory outputs bit7 of the value read from the address
located by the address signal.
By referencing this bit along with the toggle bit, you can check whether sector erasure is currently
being suspended and which sector is being erased.
Note:
Any read access to the specified address is ignored with the automatic algorithm running. For
reading data, the data polling flag must be completed before data can be output from any other bit. A
data read after completion of the automatic algorithm should therefore follow the read access which
confirms the completion of data polling.
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[bit6] TOGGLE: Toggle bit flag (DQ6)
Like the data polling flag (DQ7), the toggle bit flag uses a toggle bit function mainly to indicate that the
execution of the automatic algorithm is currently in progress or completed.
• During data programming or chip/sector erasure:
When the flash memory is continuously read-accessed during execution of the data program or chip/
sector erase automatic algorithm, it outputs the result of toggling between "1" and "0" for each read
operation not bit6 of the value read from the address located by the address signal.
When the flash memory is read-accessed upon completion of the automatic algorithm, it stops
toggling toggle bit flag (DQ6) and outputs bit6 (DATA:6) of the value read from the address located
by the address signal.
• During sector erasure suspended:
When the flash memory is read-accessed during suspended sector erasure, it outputs "1" if the
address located by the address signal belongs to the sector being erased.
If the address does not belong to the sector being erased, the flash memory outputs bit6 (DATA:6) of
the value read from the address located by the address signal.
[bit5] TLOVER: Timing limit over flag (DQ5)
The timing limit excess flag indicates that the automatic algorithm has been executed beyond the time
(internal pulse count) specified inside the flash memory.
During data programming or chip/sector erasure:
When the flash memory is read-accessed after the data program or chip/sector erase automatic
algorithm is started, this flag outputs "0" if the specified time (time required for program/erase
operation) has not been exceeded, or "1" if the time has been exceeded.
As this is not affected by whether the automatic algorithm is currently being executed or has been
completed, you can determine if the data program/erase operation has been successful. In other
words, you can determine that data program has been unsuccessful, if the automatic algorithm is still
being executed by the data polling or toggle bit function when this flag has output "1".
For example, a failure will occur if an attempt is made to write "1" to a flash memory address which
contains "0". In this case, the flash memory will be locked; therefore, the automatic algorithm will
not be completed. On rare occasions, it can be completed properly as if "1" had been written
successfully. As a consequence, valid data cannot be output from the data polling flag. Also, the
toggle bit flag does not stop toggling, resulting in a time limit over. Then, the timing limit over flag
outputs "1". Note that this indicates that the flash memory was not used correctly rather than any
defect with the flash memory. If this event occurs, execute the reset command.
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19.4 Flash Memory Automatic Algorithms
MB91210 Series
[bit3] SETIMR: Sector erase timer flag (DQ3)
The sector erase timer flag indicates whether the sector erase time-out period has passed after the sector
erase command is started.
• During a sector erase operation:
When read-accessed after a sector erase command is started, the flash memory outputs "0" within the
sector erase time-out period, or "1" after that period, without accessing the address located by the
address signal of the sector for which the command has been issued.
If this flag is "1" when the data polling or toggle bit function is indicating that the sector erase
automatic algorithm is currently executed, it means that internally controlled erasure has started.
Until the erasure is completed, any command other than the ones for programming the sector erase
code or suspending the erasure is ignored.
If this flag is "0", the flash memory accepts an additional sector erase code to be programmed. To
confirm this, it is recommended to check the state of this flag before programming the succeeding
sector erase code. If the flag is "1" at the second status check, the additional sector erase code may
not have been accepted.
• During sector erasure suspended:
When the flash memory is read-accessed during suspended sector erasure, it outputs "1" if the
address located by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, the flash memory outputs bit3 (DATA:3) of the value read from
the address located by the address signal.
[bit2] TOGGL2: Toggle bit2 flag (DQ2)
This toggle bit flag is used, along with the toggle bit flag (DQ6) of bit6, to detect whether the flash
memory is executing automatic erasure or erasure is currently being suspended, using the toggle bit
function.
• During data programming or chip/sector erasure:
This flag toggles in the same way as the toggle bit flag (DQ6).
• During sector erasure suspended:
If the flash memory is in erase-suspend read mode, the toggle bit2 flag (DQ2) toggles during
continuous read from the erase-suspended sector.
If the flash memory is in erase-suspend state and during execution of data program automatic
algorithm, "1" is read from the toggle bit2 flag (DQ2) during continuous read from addresses of the
sector which is not erase-suspended.
Unlike the toggle bit2 flag (DQ2), the toggle bit flag (DQ6) toggles only during normal programming,
erasure, or erase-suspend programming.
Reference:
The bit2 and bit6 are simultaneously used to detect the erase-suspend read mode (the bit6 does not
toggle while the bit2 toggles). In addition, the bit2 is used to detect the sector being erased. When
the flash memory is performing an erase operation, the bit2 toggles during a read from the sector
being erased.
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CHAPTER 19 FLASH MEMORY
19.5 Details of Programming and Erasing Flash Memory
MB91210 Series
19.5
Details of Programming and Erasing Flash Memory
This section describes the procedures to issue the Reset, Data Program, Chip Erase,
Sector Erase, Sector Erase Suspend, and Sector Erase Resume commands to the flash
memory for invoking their respective automatic algorithms to execute their operations.
■ Overview of Programming and Erasing Flash Memory
The flash memory can execute the following the automatic algorithms by writing to the command
sequences:
• Reset
• Data program
• Chip erase
• Sector erase
• Sector erase suspend
• Erase resume
Each series of bus write cycles must be executed continuously. The completion of each automatic
algorithm can be checked, for example, by the data polling function. When the automatic algorithm
terminates normally, the flash memory returns to the read/reset state.
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CHAPTER 19 FLASH MEMORY
19.5 Details of Programming and Erasing Flash Memory
19.5.1
MB91210 Series
Read/Reset State
This section describes the procedure for issuing the reset command to place the flash
memory in the read/reset state.
■ Placing the Flash Memory in the Reset State
To place the flash memory in the read/reset state, issue the Reset command in the command sequence table
continuously to the target sector in flash memory.
There are two different command sequences available to the Reset command: one for a single programming
and the other for three programming. The two command sequences are basically the same.
The read/reset state is the initial state of the flash memory. The flash memory always enters the read/reset
state when the power is turned on and upon normal termination of a command. In the read/reset state, the
flash memory is waiting for input of another command.
In the read/reset state, data can be read by normal read access. Like masked ROM, flash memory is
program-accessible from the CPU. Usually, the Reset command is not required for reading data. Use the
command to initialize an automatic algorithm, for example, when the command has failed to terminate
normally for some reason.
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19.5 Details of Programming and Erasing Flash Memory
MB91210 Series
19.5.2
Programming Data
This section describes the procedure for issuing the Program command to program
data into flash memory.
■ Programming Data into Flash Memory
To invoke the automatic algorithm for programming data into flash memory, issue the Data Program
command in the command sequence table continuously to the target sector in flash memory.
Upon completion of a data write to the target address in the fourth cycle, the automatic algorithm is
activated to start data programming.
■ Addressing
Although programming can be performed in any order of addresses and beyond a sector boundary, each
Data Program command can write only halfword (16 bits) of data.
■ Notes on Programming Data
Programming data cannot restore data from "0" to "1".
If you attempt to write data "1" to data "0", the data polling algorithm or toggle operation does not
terminate, the flash memory device is regarded as defective, and the specified programming time is
exceeded, resulting in an error detected by the timing limit over flag. Otherwise, the data "1" appears to
have been written normally. If the data is then read in the read/reset state, however, the value will still be
"0". Only erasing data "0" can set it to "1".
During execution of data program automatic algorithm, all commands are ignored. Note that, if a hardware
reset occurs during programming data, the data at the address currently being programmed is not
guaranteed.
■ Flash Memory Programming Procedure
Figure 19.5-1 shows an example of the flash memory programming procedure.
The states of the automatic algorithm in flash memory can be checked by referencing the hardware
sequence flags. In the example, the data polling flag (DQ7) is used to determine whether programming data
has been completed.
The data to be used for checking the flag is read from the last address programmed.
Since the data polling flag (DQ7) might changes almost at the same time with the timing limit over flag
(DQ5), the data polling flag (DQ7) must be checked again even when the timing limit over flag (DQ5)
contains "1".
Similarly, the toggle bit flag (DQ6) might stops toggle operation almost at the same time with the timing
limit over flag (DQ5) set to "1". The toggle bit flag (DQ6) must therefore be checked again.
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19.5 Details of Programming and Erasing Flash Memory
MB91210 Series
Figure 19.5-1 Example of Flash Memory Programming Procedure
Writing start
Enable writing to Flash memory
with WE (bit1) in FLCR .
Write command sequence
DAAA8H
D5554H
DAAA8H
Write address
XXAAH
XX55H
XXA0H
Write data
Next address
Read internal address.
Data polling
(DPOLL)
Data
Data
0
Time limit
(TLOVER)
1
Read internal address.
Data
Data polling
(DPOLL)
Data
Write error
Last address
NO
YES
Disable writing to Flash memory
with WE (bit1) in FLCR.
Check hardware
sequence flag
DPOLL: Data polling flag (DQ7)
TLOVER: Timing limit over flag (DQ5)
514
Writing completion
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19.5.3
CHAPTER 19 FLASH MEMORY
19.5 Details of Programming and Erasing Flash Memory
Erasing Data (Chip Erase)
This section describes the procedure for issuing the Chip Erase command to erase all
data from flash memory.
■ Erasing All Data from Flash Memory (Chip Erase)
To erase all data from flash memory, issue the Chip Erase command in the command sequence table (see
Table 19.4-1) continuously to the target sectors in flash memory.
The Chip Erase command is executed in six program operations.
The chip erase operation starts upon the completion of the write in the sixth cycle. The user does not have
to program data into flash memory before performing chip erasure. During execution of the chip erase
automatic algorithm, the flash memory performs verification by automatically writing "0"s to all cells
before erasing them.
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CHAPTER 19 FLASH MEMORY
19.5 Details of Programming and Erasing Flash Memory
19.5.4
MB91210 Series
Erasing Data (Sector Erase)
This section describes the procedure for issuing the Sector Erase command to erase
one or more arbitrary sectors in flash memory. The Sector Erase command can erase
data from flash memory in sector units. It allows two or more sectors to be specified at
the same time.
To erase an arbitrary sector in flash memory, issue the Sector Erase command in the
command sequence table continuously to the target sector in flash memory.
■ Specifying One or More Sectors
The Sector Erase command is executed in six program operations. A minimum of 50 μs sector erase timeout period is started by writing the sector erase code (XX30H) to an arbitrary address accessible in the
target sector in the sixth cycle.
To erase more than one sector, continue the above sequence by writing further sector erase codes (XX30H)
to the addresses in the sectors to be erased.
■ Notes on Specifying Multiple Sectors
Erasing sectors starts at the end of a minimum of 50 μs sector erase time-out period after writing the last
sector erase code. In other words, in order to erase more than one sector at a time, the address in each sector
to be erased and the sector erase code (in the sixth cycle of the command sequence) must be input within 50
μs after writing the sector erase code for the previous sector. Sectors specified after this time may not be
accepted.
The sector erase timer flag (DQ3) can monitor whether writing subsequent sector erase code is effective or
not. Note that the address to read the Sector Erase command must point to the sector to be erased.
■ Sector Erasing Procedure
The state of the automatic algorithm in flash memory can be checked by referencing hardware sequence
flags. Figure 19.5-2 shows an example of the flash memory sector erasing procedure.
In the example, the toggle bit flag (DQ6) is used to determine whether sector erasure automatic algorithm
has been completed.
Note that the data to be used for checking the flag is read from the sector to be erased.
Because the toggle bit flag (DQ6) might stops toggle operation almost at the same time with the timing
limit over flag (DQ5) set to "1", the toggle bit flag (DQ6) must be checked again even when the timing
limit over flag (DQ5) contains "1".
Similarly, as the data polling flag (DQ7) might changes almost at the same time with the timing limit over
flag (DQ5), the data polling flag (DQ7) must also be checked again.
■ Restrictions on Data Polling Flag (DQ7)
Due to restrictions on the function in this series, the data polling flag(DQ7) outputs "1" for 50 to 160 μs
after the sector erase command is issued, and then outputs "0". After the sector erase is terminated, the flash
memory outputs "1".
For restrictions on the data polling flag (DQ7) and how to avoid problems at sector erase, see section "19.6
Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems".
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19.5 Details of Programming and Erasing Flash Memory
MB91210 Series
Figure 19.5-2 Example of Sector Erasing Procedure
Erase start
FLCR : WE(bit1)
Flash memory erase
enabled
Erase command sequence
DAAA8H
D5554H
DAAA8H
DAAA8H
D5554H
Input to erase sector (XX30H)
YES
Internal address read
XXAAH
XX55H
XX80H
XXAAH
XX55H
Is there any
other sector?
NO
Internal address read 1
Sector
erase timer (DQ3)
Internal address read 2
Toggle bit (TOGGLE)
YES
Data 1 = Data 2 ?
No erasing specification
occurs within 50 μs
additionally.
Set the flag for starting
again from the remainder
andsuspend the erasing.
NO
Timing limit
(TLOVER)
Internal address read 1
Internal address read 2
: Check by hardware sequtnce flag
NO
Toggle bit (TOGGLE)
Data 1 = Data 2 ?
YES
Erase error
Set the flag
for starting again from
the remainder ?
YES
NO
FLCR : WE(bit1)
Flash memory erase
disabled
TOGGLE: Toggle bit flag (DQ6)
TLOVER: Timing limit over flag (DQ5)
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Erase complete
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19.5 Details of Programming and Erasing Flash Memory
19.5.5
MB91210 Series
Suspending Sector Erasure
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing one or more sectors. The command allows data to be read from
sectors currently not being erased.
■ Suspending Sector Erasure in Flash Memory
To suspend erasing sectors in flash memory, issue the Sector Erase Suspend command in the table in Table
19.4-1 to the flash memory.
The Sector Erase Suspend command allows to read data from sectors which is not in the erase state by
suspending sector erasure. When sector erasure is being suspended, such sectors can only be read from;
they cannot be written to. The command is valid only during the period of sector erasure including the
sector erase time-out period; it is ignored during chip erasure or data programming.
If the Sector Erase Suspend command is input during a sector erase time-out period, the flash memory
terminates the time-out period immediately to halt erasure and enters the erase suspended state. If the
command is input during a sector erase operation after a sector erase time-out period, the flash memory
enters the erase suspended state after a maximum of 20 μs. Issue the Sector Erase Suspend command at
least 20 μs after issuing the Sector Erase command or Sector Erase Resume command.
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19.5.6
CHAPTER 19 FLASH MEMORY
19.5 Details of Programming and Erasing Flash Memory
Resuming Sector Erasure
This section describes the procedure for issuing the Sector Erase Resume command to
resume suspended erasure of one or more sectors.
■ Resuming Sector Erasure in Flash Memory
To resume suspend sector erasure, issue the Sector Erase Resume command in Table 19.4-1 to the flash
memory.
The Sector Erase Resume command resumes sector erasure suspended by the Sector Erase Suspend
command. The Sector Erase Resume command is executed by writing the erase resume code (XX30H) to
any address in the flash memory area.
Note that the Sector Erase Resume command is ignored if issued during sector erasure in progress.
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CHAPTER 19 FLASH MEMORY
19.6 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems
19.6
MB91210 Series
Restrictions on Data Polling Flag (DQ7) and How to Avoid
Problems
This series has some restrictions on how to use the data polling flag (DQ7) during
execution of the automatic sector erase algorithm. This section describes such
restrictions and how to avoid related problems.
■ Description of Problems due to Restrictions
The data polling flag (DQ7) is used to indicate that the execution of the automatic algorithm is currently in
progress or completed, by using the data polling function. In its original operation, as shown in Figure 19.61, DQ7 outputs "0" after the sector erase command is issued when the automatic algorithm is being started,
and returns to "1" upon the completion of the erase operation. Therefore, the DQ7 polling algorithm
indicates the completion of the erase operation by outputting "1".
In this series, DQ7 continues to output "1" for 50 to 160μs, after the Sector Erase command is issued, and
then it outputs "0". When the erase operation is completed, it then returns to "1". For this reason, if the
sector erase polling is started while "1" is still being output immediately after the sector erase command is
issued, the erroneous judgment that the erase operation has been completed may occur, although the erase
operation has not actually started.
The timing for DQ7 to change from "1" to "0" after the sector erase command is accepted is the same as the
timing for the sector erase timer flag (DQ3), which indicates the sector erase timeout period, to change
from "0" to "1".
Figure 19.6-1 Actual Operation of Data Polling Flag (DQ7)
Writing the last XX30H by
sector erase command
Erase completed
Signal of internal
interruption
DQ7 (Normal)
DQ7(Problems)
First reading
50 to 160 μs
DQ3
The following or other problems may occur, as a result of the erroneous judgment that the erase operation
has been completed,
(1) Runaway or abnormal operation may occur, because the value of the sequence flag is read from the
flash memory even when the CPU attempts to fetch instruction/data; therefore, the value of the program
cannot be read properly.
(2) If the next command is issued after the erroneous judgment that the sector erase operation has been
completed occurs, the first command may be cancelled, resulting in a return to the read state, or the next
command may not be accepted.
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19.6 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems
MB91210 Series
■ How to Avoid Problems
Use one of the following methods to avoid the problems.
● Polling using the toggle bit flag (DQ6)
Determine the state of the automatic algorithm using DQ6, as shown in Figure 19.5-2 in "19.5.4 Erasing
Data (Sector Erase)".
In the same manner as the data polling flag (DQ7), the toggle bit flag (DQ6) indicates that the automatic
algorithm is being executed or has terminated by the toggle bit function.
● Starting polling of DQ7 after the sector erase timeout period elapses
Before starting the polling of DQ7, wait for 160μs or more by software after the sector erase command is
issued, or wait until DQ3 is set to "1" (end of the sector erase timeout period). Figure 19.6-2 shows the
judgment method using DQ3 after the sector erase command is issued.
Figure 19.6-2 How to Avoid Problems by Sector Erase Timer Flag (DQ3)
P
Internal address read
0
Sector erase timer flag
(DQ3)
1
Internal address read
Data polling flag (DQ7)
1
0
0
Timing limit over flag (DQ5)
1
Internal address read
0
Data polling flag (DQ7)
1
Erase error
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Sector erase
completed
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19.6 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems
MB91210 Series
● Data polling using the 8 bits of hardware sequence flags
Make a judgment by data polling using the 8 bits of hardware sequence flags, rather than using only the
polling of DQ7.
Figure 19.6-3 shows the judgment method using the data polling of the 8 bits after the sector erase
command is issued.
Figure 19.6-3 How to Avoid Problems by Data Polling of 8 Bits
P
Internal address read
Data (DQ0 to DQ7)?
FFH
other
0
Timing limit over flag (DQ5)
1
Internal address read
other
Data (DQ0 to DQ7)?
FFH
Erase error
522
Sector erase
completed
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CHAPTER 19 FLASH MEMORY
19.7 Notes on Flash Memory Programming
MB91210 Series
19.7
Notes on Flash Memory Programming
This section provides notes on programming into flash memory.
■ Notes on Flash Memory Programming
Take the following operations when reprogramming flash memory using a program:
• If a reset occurs during programming data into flash memory, the data being written is not guaranteed.
• In FR-CPU programming mode (WE = 1 in the FLCR register), do not run any program in flash
memory. If an interrupt vector table resides in flash memory in that mode, do not generate an interrupt.
Either case causes the program to run out of control as it fails to fetch normal values from flash
memory.
• To check whether programming data into flash memory has been completed, reference the toggle bit
flag (TOGGLE, DQ6) as well as the RDY flag.
If the flash memory is defective, the RDY flag that indicates the completion of data program automatic
algorithm is not set. If referencing only the RDY flag, therefore, the program will enter an infinite loop.
• In FR-CPU programming mode (WE = 1 in the FLCR register), do not enter sub-run mode or lowpower consumption mode.
• Do not perform write access to FLASH memory while WE=0 in the FLCR register.
• Do not perform continuous write access to the FLASH memory while WE=1 in the FLCR register. In
this case, always insert two or more NOP instructions.
ldi
ldi
ldi
ldi
ldi
ldi
ldi
sth
nop
nop
sth
nop
nop
sth
nop
nop
sth
nop
nop
#0xAAAA,
#0x5555,
#0xDAAA8,
#0xD5554,
#0xA0A0,
#PA,
#PD,
r0, @r6
r0
r1
r6
r7
r8
r2
r3
// Always insert two or more "NOP" instructions.
// Always insert two or more "NOP" instructions.
r1, @r7
// Always insert two or more "NOP" instructions.
// Always insert two or more "NOP" instructions.
r8, @r6
// Always insert two or more "NOP" instructions.
// Always insert two or more "NOP" instructions.
r3, @r2
// Always insert two or more "NOP" instructions.
// Always insert two or more "NOP" instructions.
• In CPU mode, write access to FLASH memory can only be performed using half words. Do not perform
byte write access.
• The value read immediately after writing to flash memory is unpredictable. When reading after writing,
be sure to read after inserting a dummy read.
sth r0,
lduh
lduh
CM71-10139-5E
@r1
@r2, r4
@r3, r4
// Write to FLASH
// Dummy read
// Read polling data
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19.7 Notes on Flash Memory Programming
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CHAPTER 20
EXAMPLES OF SERIAL
PROGRAMMING
CONNECTION
This chapters gives an overview of flash memory
product for examples of serial programming connection.
20.1 Serial Programming Connection Examples
20.2 Serial (Asynchronous) Programming Example
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CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
20.1
MB91210 Series
Serial Programming Connection Examples
The MB91210 series supports serial on-board programming (Fujitsu standard) into flash
ROM. This section summarizes the specifications.
■ Basic Configuration
Fujitsu-standard serial on-board programming uses the AF200 flash microcontroller programmer
manufactured by Yokogawa Digital Computer Corporation.
Figure 20.1-1 Serial Programming Connection Examples
Host interface cable (AZ201)
AF200
RS232C
Flash
microcontroller
programmer
+
memory card
General-purpose common cable (AZ210)
CLK synchronous
serial connection FLASH memory
integrated
user system
Operable in stand-alone mode
Note:
Contact Yokogawa Digital Computer Corporation for the functions and use of the AF200 flash
microcontroller programmer and for information on the general-purpose common cable (AZ210) for
connection and relevant connectors.
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CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
■ Pins Used for Fujitsu-standard Serial On-board Programming
Pin
Function
Supplement
MD3,
MD2,
MD1,
MD0
Mode pins
Controls the flash memory to enter program mode from the flash
microcontroller programmer.
Flash serial programming mode:
MD3, MD2, MD1, MD0=0, 1, 0, 0
X0, X1
Oscillation pins
In program mode, the CPU's internal operation clock is a frequency-halved
version of the oscillation clock. Note that the PLL cannot be set.
Note also that the resonator used for serial reprogramming is limited to be 4
MHz.
P10,
P11
Writing program start pins
Set P10 to the "L" level and P11 to the "H" level.
INITX
Reset pin
—
SIN0
Serial data input pin
—
SOT0
Serial data output pin
SCK0
Serial clock input pin
VCC
Supply-voltage feeder pin
When the programming voltage is supplied from the user system, you do not
have to connect the flash microcontroller programmer.
When plugging the pin, do not connect it with the power supply on the user
side.
VSS
GND pin
Use this pin also to ground the flash microcontroller programmer.
Uses the UART in clock synchronous mode.
Note:
If P10, P11, SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcomputer programmer's
/TICS signal. See the connection example)
AF200
Write control pin
MB91F211B, MB91F213A, MB91F218S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
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CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
■ Serial Programming Connection Examples
This section provides connection examples for serial programming for your reference.
• Serial programming connection example (using a user power supply)
• Serial programming connection example (with power supply from the flash microcontroller programmer)
• Sample minimum connection with flash microcontroller programmer (using a user power supply)
• Sample minimum connection with flash microcontroller programmer (with power supply from the
programmer)
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CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
● Serial programming connection example (using a user power supply)
This section provides a connection example for serial programming using a user power supply.
Note that the MD2 and MD0 mode pins input MD2=1 and MD0=0 from TAUX3 and TMODE on the flash
microcontroller programmer (AF200). (Serial reprogramming mode: MD3, MD2, MD1, MD0=0100B)
Figure 20.1-2 Connection Example for Serial Programming into MB91F211B, MB91F213A, MB91F218S in
Internal Vector Mode (Using a User Power Supply)
AF200 flash
microcontroller
programmer
TAUX3
TMODE
User system
MB91F211B, MB91F213A, MB91F218S
Connector
DX10-28S
(19)
MD3
MD2
MD1
MD0
(12)
X0
4MHz
X1
(23)
TAUX
/TICS
P10
(10)
User circuit
/TRES
INITX
(5)
P11
User circuit
TTXD
(13)
SIN0
TRXD
(27)
SOT0
TCK
(6)
SCK0
TVcc
(2)
GND
(7,8,
14,15,
21,22,
1,28)
Leave pins 3, 4, 9, 11,
16, 17, 18, 20, 24, 25,
and 26 open.
DX10-28S : Right-angle type
CM71-10139-5E
VCC
User power
supply
VSS
14 pin
1 pin
DX10-28S
28 pin
15 pin
Connector (manufactured by
HIROSE ELECTRIC) pinout
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CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
Notes:
• If P10, P11, SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in
the figure below is necessary.
(During the serial writing, the user circuit can be disconnected by the Flash microcomputer
programmer's /TICS signal).
AF200
Write control pin
MB91F211B, MB91F213A, MB91F218S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
530
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
● Serial programming connection example (with power supply from the flash microcontroller programmer)
The following gives a connection example for serial programming using power supply from the flash
microcontroller programmer (AF200).
Note that the MD2 and MD0 mode pins input MD2=1 and MD0=0 from TAUX3 and TMODE on the flash
microcontroller programmer (AF200). (Serial reprogramming mode: MD3, MD2, MD1, MD0=0100B)
Figure 20.1-3 Connection Example for Serial Programming into MB91F211B, MB91F213A, MB91F218S in
Internal Vector Mode (With Power Supply from the Programmer)
AF200 flash
microcontroller
programmer
User system
MB91F211B, MB91F213A, MB91F218S
Connector
DX10-28S
TAUX3
(19)
MD3
MD2
MD1
TMODE
(12)
MD0
X0
4MHz
X1
(23)
TAUX
P10
(10)
/TICS
User circuit
/TRES
INITX
(5)
P11
User circuit
TTXD
(13)
SIN0
TRXD
(27)
SOT0
TCK
(6)
SCK0
Vcc
(3)
(7,8,
14,15,
21,22,
1,28)
GND
VCC
User power
supply
VSS
14 pin
Supply-voltage
regulator AZ264
Leave pins 2, 4, 9, 11,
16, 17, 18, 20, 24, 25,
and 26 open.
DX10-28S : Right-angle type
CM71-10139-5E
1 pin
DX10-28S
28 pin
15 pin
Connector (manufactured by
HIROSE ELECTRIC) pinout
FUJITSU MICROELECTRONICS LIMITED
531
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
Notes:
• If P10, P11, SIN0, SOT0, and SCK0 pins are used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcomputer programmer's
/TICS signal).
AF200
Write control pin
MB91F211B, MB91F213A, MB91F218S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
• Do not make a short-circuit with the user power supply when the writing power supply is supplied
from AF200.
532
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
MB91210 Series
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
● Sample minimum connection with flash microcontroller programmer (using a user power supply)
The following gives an example of minimum connection with the flash microcontroller programmer
(AF200) using a user power supply. Set each pin as shown below when programming into flash memory,
so that you do not have to connect MD3, MD2, MD1, MD0, P10, and P11 to the flash microcontroller
programmer (serial reprogramming mode: MD3, MD2, MD1, MD0=0100B).
Figure 20.1-4 Using a User Power Supply
MB91F211B, MB91F213A, MB91F218S
MD3
AF200 flash
microcontroller
programmer
User system
For serial
reprogramming: 1
MD2
For serial
reprogramming: 0
MD1
MD0
For serial
reprogramming: 0
X0
4MHz
X1
For serial
reprogramming: 0
User circuit
P10
P11
For serial reprogramming: 1
User circuit
Connector
DX10-28S
/TRES
(5)
INITX
TTXD
(13)
SIN0
TRXD
(27)
SOT0
TCK
TVcc
(6)
SCK0
GND
(2)
VCC
(7,8,
14,15,
21,22,
1,28)
User power
supply
14 pin
Leave pins 3, 4, 9, 10, 11, 12,
16, 17, 18, 19, 20, 23, 24, 25,
and 26 open.
CM71-10139-5E
1 pin
DX10-28S
28 pin
DX10-28S: Right-angle type
VSS
15 pin
Connector (manufactured by
HIROSE ELECTRIC) pinout
FUJITSU MICROELECTRONICS LIMITED
533
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
Notes:
• If the SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcomputer
programmer's/TICS signal).
AF200
Write control pin
MB91F211B, MB91F213A, MB91F218S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
534
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
● Sample minimum connection with flash microcontroller programmer (with power supply from the
programmer)
The following gives an example of minimum connection with the flash microcontroller programmer
(AF200) with power supply from the AF200.
Set each pin as shown below when programming into flash memory, so that you do not have to connect
MD3, MD2, MD1, MD0, P10, and P11 to the flash microcontroller programmer (serial reprogramming
mode: MD3, MD2, MD1, MD0=0100B).
Figure 20.1-5 With Power Supply from Flash Microcontroller Programmer
MB91F211B, MB91F213A, MB91F218S
MD3
AF200 flash
microcontroller
programmer
User system
For serial
reprogramming: 1
MD2
For serial
reprogramming: 0
MD1
MD0
For serial
reprogramming: 0
X0
4MHz
X1
P10
For serial
User circuit
reprogramming: 0
For serial reprogramming: 1
P11
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
(5)
(13)
(27)
(6)
Vcc
(3)
(7,8,
14,15,
21,22,
1,28)
GND
Supply-voltage
regulator AZ264
INITX
SIN0
SOT0
SCK0
VCC
User power
supply
VSS
14 pin
1 pin
Leave pins 2, 4, 9, 10, 11,
DX10-28S
12, 16, 17, 18, 19, 20,
23, 24, 25, and 26 open.
28 pin
15 pin
Connector (manufactured by
DX10-28S : Right-angle type
HIROSE ELECTRIC) pinout
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
535
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
Notes:
• If SIN0, SOT0, and SCK0 pins are used by the user system, the control circuit in the figure below
is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcomputer programmer's
/TICS signal).
AF200
Write control pin
MB91F211B, MB91F213A, MB91F218S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
• Do not cause short-circuit with the user power supply when the writing power is supplied from
AF200.
536
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.1 Serial Programming Connection Examples
MB91210 Series
■ System Configuration for AF200 Flash Microcontroller Programmer (Manufactured by
Yokogawa Digital Computer Corporation)
Model
Main
unit
Function
AF220
/AC4P
Ethernet interface model
/100V to 220V power adapter
AF210
/AC4P
Standard model
/100V to 220V power adapter
AF120
/AC4P
Single-key Ethernet interface model
/100V to 220V power adapter
AF110
/AC4P
Single-key model
/100V to 220V power adapter
AZ221
Programmer-dedicated RS-232C cable for PC-AT
AZ210
Standard target probe (a) Length: 1 m
FF003
Control module for Fujitsu FR flash microcontroller
AZ290
Remote controller
/P2
2M-byte PC Card (Option): Flash memory size of up to 128K bytes
/P4
4M-byte PC Card (Option): Flash memory size of up to 512K bytes
Contact: Yokogawa Digital Computer Corporation
Phone: +81-42-333-6224
■ Oscillation Clock Frequency
The oscillation clock frequency usable for programming into flash memory is from 4.0 MHz.
■ Additional Notes
The port state during flash memory programming by the serial programmer is the same as the reset state,
except for the pin used for programming.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
537
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.2 Serial (Asynchronous) Programming Example
20.2
MB91210 Series
Serial (Asynchronous) Programming Example
This section summaries the serial (asynchronous) programing examples.
■ Basic Configuration
Figure 20.2-1 Serial (Asynchronous) Programming Example
RS-232C driver
User system
RS232C
Communication via UART
MB91F211B, MB91F213A, MB91F218S
You can use a personal computer to reprogram flash memory in the flash built-in
microcontroller on your user system via the PC's RS-232C interface.
Note that this assumes that the user system has an RS-232C driver that can communicate with
the UART in the microcontroller.
538
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.2 Serial (Asynchronous) Programming Example
MB91210 Series
■ Connection Example for On-board Reprogramming Using a Programmer
Figure 20.2-2 Connection Example for On-board Reprogramming Using a Programmer
User system
MB91F211B, MB91F213A, MB91F218S
MD3
1
For serial reprogramming: 1
MD2
0
For serial reprogramming: 0
1
MD1
0
1
For serial reprogramming: 0
MD0
0
1
P10
0
1
For serial reprogramming: 0
User circuit
P11
0
For serial reprogramming: 0
P12
User
circuit
X0
4MHz
X1
RS-232C
driver
INITX
SIN
SOT
Communication via UART
RS232C
As the MD3, MD2, MD1, MD0, P10, P11, and P12 pins cannot be controlled from the PC side, set them on
the user system. During serial reprogramming, Changing INITX from "L" to "H" after setting the MD3,
MD2, MD1, MD0, P10, P11, and P12 pins during serial reprogramming causes a transition to serial
reprogramming mode, enabling serial reprogramming from the PC.
When serial reprogramming is completed, the user program is executed by placing the MD2, MD1, and
MD0 pins in regular mode, switching the P10, P11, and P12 pins to the user circuit side, and setting INITX
from "L" to "H".
Note:
For programming into mass-produced products using a serial programmer manufactured by
Yokogawa Digital Computer Corporation in the future, it is advisable to draw serial clock pin patterns
on the board according to the serial programming connection examples in the hardware manual for
each model as references.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
539
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.2 Serial (Asynchronous) Programming Example
MB91210 Series
■ Pins Used by the Programmer for On-board Reprogramming
Pin
Function
Supplement
MD3,
MD2,
MD1,
MD0
Mode pins
Control these pins for flash reprogramming.
Setting MD3="L", MD2="H", and MD1=MD0="L" establishes the flash
reprogramming mode.
P10,
P11,
P12
Write program start pin
Set P10=P11="L" in flash reprogramming mode.
Set P12 to "L" when the source oscillation is 4 MHz and to "H" for 5 MHz.
INITX
Reset pin
Set the MD3, MD2, MD1, MD0, P10, P11 and P12 pins to flash
reprogramming mode before clearing a reset.
SIN0
Serial data input pin
Uses the UART.
SOT0
Serial data output pin
Uses the UART.
X0, X1
Oscillation pins
In program mode, the CPU's internal operation clock is a frequency-halved
version of the oscillation clock. Note that the PLL cannot be used.
VCC
Supply voltage
VSS
GND pin
540
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.2 Serial (Asynchronous) Programming Example
MB91210 Series
■ Pin Timing Chart
Input to each pin on the microcontroller as follows, with the input to the INITX pin as a reference.
Min setup time and hold time of each signal relative to the rise of INITX.
P10, P11, P12 and SIN represent the write program start pins and the serial data input pin, respectively.
Figure 20.2-3 Pin Timing Chart
"H"
INITX
5tcp
"L"
MD0
"H"
tcp
"L"
MD1
"H"
tcp
"L"
MD2
"H"
tcp
"L"
MD3
"H"
tcp
"L"
"H"
P10, P11,
P12
"L"
SIN
"H"
tcp
tcp × 250
tcp × 3500(Min)
Data
"L"
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
541
CHAPTER 20 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
20.2 Serial (Asynchronous) Programming Example
542
FUJITSU MICROELECTRONICS LIMITED
MB91210 Series
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
APPENDIX B Vector Table
APPENDIX C Status of Each Pin in Each CPU state
APPENDIX D INSTRUCTION LISTS
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
543
APPENDIX
APPENDIX A I/O Map
MB91210 Series
APPENDIX A I/O Map
This section shows the correspondence between memory space and each register of
peripheral resources.
[How to read]
Address
000000H
Register
Block
+0
+1
+2
+3
PDR0 [R/W]B PDR1 [R/W]B PDR2 [R/W]B PDR3 [R/W]B T-unit
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Port Data Register
Read/Write attribute, access unit
(B: Byte, H: Half-word, W: Word)
Initial register value after reset
Register name (Registers in column 1 are located at 4n addresses,
registers in column 2 are located at 4n + 1 addresses, and so on)
The leftmost register address
(When word access is used, the register in the first column becomes
the MSB side of data.)
Note:
Register bit values indicate initial values as shown below:
"1" :Initial value "1"
"0" :Initial value "0"
"X" :Undefined initial value
"-" :No physical register exists at that location.
The access by the data access attribute not described is disabled.
544
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (1 / 17)
Address
000000H
000004H
000008H
00000CH
Register
+0
PDR0
(R/W) B, H, W
XXXXXXXX
PDR4
(R/W) B, H, W
XXXXXXXX
PDR8
(R/W) B, H, W
--XXXXXX
PDRC
(R/W) B, H, W
XXXXXXXX
+1
PDR1
(R/W) B, H, W
XXXXXXXX
PDR5
(R/W) B, H, W
XXXXXXXX
PDR9
(R/W) B, H, W
XXXXXXXX
PDRD
(R/W) B, H, W
XXXXXXXX
+2
PDR2
(R/W) B, H, W
XXXXXXXX
PDR6
(R/W) B, H, W
---XXXXX
PDRA
(R/W) B, H, W
XXXXXXXX
PDRE
(R/W) B, H, W
-----XXX
+3
PDR3
(R/W) B, H, W
XXXXXXXX
PDR7
(R/W) B, H, W
XXXXXXXX
PDRB
(R/W) B, H, W
XXXXXXXX
PDRF
(R/W) B, H, W
XXXXXXXX
—
—
—
—
000010H
to
00003CH
000040H
000044H
000048H
EIRR0
ENIR0
(R/W) B, H, W
(R/W) B, H, W
00000000
00000000
DICR
HRCL
(R/W) B, H, W
(R/W, R) B
-------0
0--11111
TMRLR0
(W) H, W
XXXXXXXX XXXXXXXX
00004CH
—
—
TMRLR1
(W) H, W
XXXXXXXX XXXXXXXX
000050H
000054H
—
—
TMRLR2
(W) H, W
XXXXXXXX XXXXXXXX
000058H
00005CH
—
—
000060H
SCR0
(R/W, W) B, H, W
00000000
000064H
ESCR0
(R/W) B, H, W
00000100
SMR0
(R/W, W) B, H, W
00000000
ECCR0
(R/W, R, W)
B, H, W
000000XX
CM71-10139-5E
ELVR0
(R/W) B, H, W
00000000 00000000
—
TMR0
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR0
(R/W, R) B, H, W
----0000 00000000
TMR1
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR1
(R/W, R) B, H, W
----0000 00000000
TMR2
(R) H, W
XXXXXXXX XXXXXXXX
TMCSR2
(R/W, R) B, H, W
----0000 00000000
SSR0
RDR0/TDR0
(R/W, R) B, H, W
(R/W) B, H, W
00001000
00000000
BGR10
(R/W) B, H, W
10000000
FUJITSU MICROELECTRONICS LIMITED
BGR00
(R/W) B, H, W
00000000
Block
Port Data
Register
Reserved
External
Interrupt
(INT0 to INT7)
Delay Interrupt
Module/
Hold Request
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART 0
545
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (2 / 17)
Address
000068H
Register
+0
SCR5
(R/W, W) B, H, W
00000000
+1
SMR5
(R/W, W) B, H, W
00000000
ECCR5
(R/W, R, W)
B, H, W
000000XX
SMR6
(R/W, W) B, H, W
00000000
ECCR6
(R/W, R, W)
B, H, W
000000XX
+2
SSR5
(R/W, R) B, H, W
00001000
+3
RDR5/TDR5
(R/W) B, H, W
00000000
BGR15
(R/W) B, H, W
10000000
BGR05
(R/W) B, H, W
00000000
SSR6
(R/W, R) B, H, W
00001000
RDR6/TDR6
(R/W) B, H, W
00000000
BGR16
(R/W) B, H, W
10000000
BGR06
(R/W) B, H, W
00000000
00006CH
ESCR5
(R/W) B, H, W
00000100
000070H
SCR6
(R/W, W) B, H, W
00000000
000074H
ESCR6
(R/W) B, H, W
00000100
000078H
to
0000ACH
—
—
—
—
0000B0H
SCR1
(R/W, W) B, H, W
00000000
SSR1
(R/W, R) B, H, W
00001000
RDR1/TDR1
(R/W) B, H, W
00000000
0000B4H
ESCR1
(R/W) B, H, W
00000100
BGR11
(R/W) B, H, W
10000000
BGR01
(R/W) B, H, W
00000000
0000B8H
SCR2
(R/W, W) B, H, W
00000000
SSR2
(R/W, R) B, H, W
00001000
RDR2/TDR2
(R/W) B, H, W
00000000
0000BCH
ESCR2
(R/W) B, H, W
00000100
BGR12
(R/W) B, H, W
10000000
BGR02
(R/W)B, H, W
00000000
0000C0H
SCR3
(R/W, W) B, H, W
00000000
SSR3
(R/W, R) B, H, W
00001000
RDR3/TDR3
(R/W) B, H, W
00000000
0000C4H
ESCR3
(R/W) B, H, W
00000100
BGR13
(R/W) B, H, W
10000000
BGR03
(R/W) B, H, W
00000000
0000C8H
SCR4
(R/W, W) B, H, W
00000000
SSR4
(R/W, R) B, H, W
00001000
RDR4/TDR4
(R/W) B, H, W
00000000
0000CCH
ESCR4
(R/W) B, H, W
00000100
BGR14
(R/W) B, H, W
10000000
BGR04
(R/W) B, H, W
00000000
0000D0H
EIRR1
(R/W) B, H, W
00000000
SMR1
(R/W, W) B, H, W
00000000
ECCR1
(R/W, R, W)
B, H, W
000000XX
SMR2
(R/W, W) B, H, W
00000000
ECCR2
(R/W, R, W)
B, H, W
000000XX
SMR3
(R/W, W) B, H, W
00000000
ECCR3
(R/W, R, W)
B, H, W
000000XX
SMR4
(R/W, W) B, H, W
00000000
ECCR4
(R/W, R, W)
B, H, W
000000XX
ENIR1
(R/W) B, H, W
00000000
546
ELVR1
(R/W) B, H, W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
Block
UART 5
UART 6
Reserved
UART 1
UART 2
UART 3
UART 4
External
Interrupt
(INT8 to INT15)
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (3 / 17)
Address
0000D4H
0000D8H
0000DCH
0000E0H
0000E4H
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
Register
+0
+1
TCDT0
(R/W) H, W
00000000 00000000
TCDT1
(R/W) H, W
00000000 00000000
TCDT2
(R/W) H, W
00000000 00000000
TCDT3
(R/W) H, W
00000000 00000000
IPCP1
(R) H, W
XXXXXXXX XXXXXXXX
—
—
IPCP3
(R) H, W
XXXXXXXX XXXXXXXX
—
—
IPCP5
(R) H, W
XXXXXXXX XXXXXXXX
—
—
IPCP7
(R) H, W
XXXXXXXX XXXXXXXX
000100H
—
—
000104H
—
—
000108H
00010CH
000110H
000114H
CM71-10139-5E
OCCP1
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP3
(R/W) H, W
XXXXXXXX XXXXXXXX
OCS23
(R/W) B, H, W
11101100 00001100
OCCP5
(R/W) H, W
XXXXXXXX XXXXXXXX
+2
—
—
—
—
+3
TCCS0
(R/W) B, H, W
00000000
TCCS1
(R/W) B, H, W
00000000
TCCS2
(R/W) B, H, W
00000000
TCCS3
(R/W) B, H, W
00000000
IPCP0
(R) H, W
XXXXXXXX XXXXXXXX
ICS01
—
(R/W) B, H, W
00000000
IPCP2
(R) H, W
XXXXXXXX XXXXXXXX
ICS23
—
(R/W) B, H, W
00000000
IPCP4
(R) H, W
XXXXXXXX XXXXXXXX
ICS45
—
(R/W) B, H, W
00000000
IPCP6
(R) H, W
XXXXXXXX XXXXXXXX
ICS67
—
(R/W) B, H, W
00000000
—
—
OCCP0
(R/W) H, W
XXXXXXXX XXXXXXXX
OCCP2
(R/W) H, W
XXXXXXXX XXXXXXXX
OCS01
(R/W) B, H, W
11101100 00001100
OCCP4
(R/W) H, W
XXXXXXXX XXXXXXXX
FUJITSU MICROELECTRONICS LIMITED
Block
Free-run
Timer 0
Free-run
Timer 1
Free-run
Timer 2
Free-run
Timer 3
Input Capture
0, 1
Input Capture
2, 3
Input Capture
4, 5
Input Capture
6, 7
Reserved
Output
Compare 0, 1
Output
Compare 2, 3
Output Compare
Control 0 to 3
Output
Compare 4, 5
547
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (4 / 17)
Address
000118H
00011CH
Register
+0
OCCP7
(R/W) H, W
XXXXXXXX XXXXXXXX
OCS67
(R/W) B, H, W
11101100 00001100
000120H
to
000140H
—
000144H
—
000148H
—
00014CH
WTHR
(R/W) B, H
---XXXXX
000150H
000154H
000158H
00015CH
000160H
+1
—
WTDBL
(R/W) B
------00
WTBR2
(R/W) B
---XXXXX
WTMR
(R/W) B, H
--XXXXXX
ADERH
(R/W) B, H, W
00000000 00000000
ADCS1
ADCS0
(R/W) B, H, W
(R/W, R) B, H, W
00000000
00000000
ADCT1
ADCT0
(R/W) B, H, W
(R/W) B, H, W
00010000
00101100
CUCR
—
(R/W, R) B, H, W
00000000
CUTR1
(R) B, H, W
00000000 00000000
000164H
to
0001A4H
—
0001A8H
CANPRE
(R/W, R) B, H, W
00000000
—
0001ACH
—
—
548
—
+2
+3
OCCP6
(R/W) H, W
XXXXXXXX XXXXXXXX
OCS45
(R/W) B, H, W
11101100 00001100
—
—
WTCR
(R/W, R) B, H
00000000 000-00-0
WTBR1
WTBR0
(R/W) B
(R/W) B
XXXXXXXX
XXXXXXXX
WTSR
(R/W) B
—
--XXXXXX
ADERL
(R/W) B, H, W
00000000 00000000
ADCR1
ADCR0
(R) B, H, W
(R) B, H, W
------XX
XXXXXXXX
ADSCH
ADECH
(R/W) B, H, W
(R/W) B, H, W
---00000
---00000
CUTD
(R/W) B, H, W
10000000 00000000
CUTR2
(R) B, H, W
00000000 00000000
—
FUJITSU MICROELECTRONICS LIMITED
Output
Compare 6, 7
Output Compare
Control 4 to 7
Reserved
Real-Time
Clock
A/D Converter
Sub clock
Calibration unit
—
Reserved
—
Select CAN
Clock
Prescaler/
External
Interrupt
Reserved
EISSR
(R/W) B, H, W
00000000 00000000
—
Block
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (5 / 17)
Address
0001B0H
0001B4H
0001B8H
0001BCH
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
0001D8H
0001DCH
0001E0H
0001E4H
0001E8H
0001ECH
0001F0H
Register
+0
PRLH0
(R/W) B, H, W
XXXXXXXX
PRLH2
(R/W) B, H, W
XXXXXXXX
PPGC0
(R/W) B, H, W
0000000X
—
PRLH4
(R/W) B, H, W
XXXXXXXX
PRLH6
(R/W) B, H, W
XXXXXXXX
PPGC4
(R/W) B, H, W
0000000X
—
PRLH8
(R/W) B, H, W
XXXXXXXX
PRLHA
(R/W) B, H, W
XXXXXXXX
PPGC8
(R/W) B, H, W
0000000X
—
PRLHC
(R/W) B, H, W
XXXXXXXX
PRLHE
(R/W) B, H, W
XXXXXXXX
PPGCC
(R/W) B, H, W
0000000X
—
TRG1
(R/W) B, H, W
00000000
+1
PRLL0
(R/W) B, H, W
XXXXXXXX
PRLL2
(R/W) B, H, W
XXXXXXXX
PPGC1
(R/W) B, H, W
0000000X
—
PRLL4
(R/W) B, H, W
XXXXXXXX
PRLL6
(R/W) B, H, W
XXXXXXXX
PPGC5
(R/W) B, H, W
0000000X
—
PRLL8
(R/W) B, H, W
XXXXXXXX
PRLLA
(R/W) B, H, W
XXXXXXXX
PPGC9
(R/W) B, H, W
0000000X
—
PRLLC
(R/W) B, H, W
XXXXXXXX
PRLLE
(R/W) B, H, W
XXXXXXXX
PPGCD
(R/W) B, H, W
0000000X
—
TRG0
(R/W) B, H, W
00000000
+2
PRLH1
(R/W) B, H, W
XXXXXXXX
PRLH3
(R/W) B, H, W
XXXXXXXX
PPGC2
(R/W) B, H, W
0000000X
—
PRLH5
(R/W) B, H, W
XXXXXXXX
PRLH7
(R/W) B, H, W
XXXXXXXX
PPGC6
(R/W) B, H, W
0000000X
—
PRLH9
(R/W) B, H, W
XXXXXXXX
PRLHB
(R/W) B, H, W
XXXXXXXX
PPGCA
(R/W) B, H, W
0000000X
—
PRLHD
(R/W) B, H, W
XXXXXXXX
PRLHF
(R/W) B, H, W
XXXXXXXX
PPGCE
(R/W) B, H, W
0000000X
—
REVC1
(R/W) B, H, W
00000000
+3
PRLL1
(R/W) B, H, W
XXXXXXXX
PRLL3
(R/W) B, H, W
XXXXXXXX
PPGC3
(R/W) B, H, W
0000000X
—
PRLL5
(R/W) B, H, W
XXXXXXXX
PRLL7
(R/W) B, H, W
XXXXXXXX
PPGC7
(R/W) B, H, W
0000000X
—
PRLL9
(R/W) B, H, W
XXXXXXXX
PRLLB
(R/W) B, H, W
XXXXXXXX
PPGCB
(R/W) B, H, W
0000000X
—
PRLLD
(R/W) B, H, W
XXXXXXXX
PRLLF
(R/W) B, H, W
XXXXXXXX
PPGCF
(R/W) B, H, W
0000000X
—
REVC0
(R/W) B, H, W
00000000
—
—
—
—
0001F4H
to
0001FCH
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
Block
PPG 0 to PPG 3
Reserved
PPG 4 to PPG 7
Reserved
PPG 8 to PPG B
Reserved
PPG C to PPG F
Reserved
PPG 0 to PPG F
AP/INV
Reserved
549
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (6 / 17)
Address
Register
+0
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
—
550
+3
—
—
—
—
—
FUJITSU MICROELECTRONICS LIMITED
Block
DMAC
—
DMACR
(R/W, R) B, H, W
00000000 00000000 00000000 00000000
000240H
000244H
to
0003ECH
+2
DMACA0
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
DMACB0
(R/W) B, H, W
00000000 00000000 00000000 00000000
DMACA1
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
DMACB1
(R/W) B, H, W
00000000 00000000 00000000 00000000
DMACA2
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
DMACB2
(R/W) B, H, W
00000000 00000000 00000000 00000000
DMACA3
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
DMACB3
(R/W) B, H, W
00000000 00000000 00000000 00000000
DMACA4
(R/W, R) B, H, W *1
00000000 00000000 00000000 00000000
DMACB4
(R/W) B, H, W
00000000 00000000 00000000 00000000
000200H
000228H
to
00023CH
+1
Reserved
DMAC
—
Reserved
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (7 / 17)
Register
Address
0003F0H
0003F4H
0003F8H
0003FCH
000400H
000404H
000408H
00040CH
+0
000424H
000428H
00042CH
+2
+3
BSD0
(W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1
(R/W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSDC
(W) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR
(R) W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0
DDR1
DDR2
DDR3
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
00000000
00000000
00000000
00000000
DDR4
DDR5
DDR6
DDR7
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
00000000
00000000
---00000
00000000
DDR8
DDR9
DDRA
DDRB
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
--000000
00000000
00000000
00000000
DDRC
DDRD
DDRE
DDRF
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
(R/W) B, H, W
00000000
00000000
-----000
00000000
000410H
to
00041CH
000420H
+1
Block
Bit Search
Module
Data Direction
Register
—
—
—
—
Reserved
PFR0
(R/W) B, H, W
0000-00PFR4
(R/W) B, H, W
00000000
PFR8
(R/W) B, H, W
000----PFRC
(R/W) B, H, W
--------
PFR1
(R/W) B, H, W
00-00-0PFR5
(R/W) B, H, W
-0000000
PFR9
(R/W) B, H, W
00000000
PFRD
(R/W) B, H, W
00-00-0-
PFR2
(R/W) B, H, W
00000000
PFR6
(R/W) B, H, W
------00
PFRA
(R/W) B, H, W
-----000
PFRE
(R/W) B, H, W
-----00-
PFR3
(R/W) B, H, W
------00
PFR7
(R/W) B, H, W
00000-0PFRB
(R/W) B, H, W
-------PFRF
(R/W) B, H, W
--------
Port Function
Register
—
—
—
—
Reserved
000430H
to
00043CH
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
551
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (8 / 17)
Address
Register
+0
ICR00
(R, R/W) B, H, W
---11111
ICR04
(R, R/W) B, H, W
---11111
ICR08
(R, R/W) B, H, W
---11111
ICR12
(R, R/W) B, H, W
---11111
ICR16
(R, R/W) B, H, W
---11111
ICR20
(R, R/W) B, H, W
---11111
ICR24
(R, R/W) B, H, W
---11111
ICR28
(R, R/W) B, H, W
---11111
ICR32
(R, R/W) B, H, W
---11111
ICR36
(R, R/W) B, H, W
---11111
ICR40
(R, R/W) B, H, W
---11111
ICR44
(R, R/W) B, H, W
---11111
+1
ICR01
(R, R/W) B, H, W
---11111
ICR05
(R, R/W) B, H, W
---11111
ICR09
(R, R/W) B, H, W
---11111
ICR13
(R, R/W) B, H, W
---11111
ICR17
(R, R/W) B, H, W
---11111
ICR21
(R, R/W) B, H, W
---11111
ICR25
(R, R/W) B, H, W
---11111
ICR29
(R, R/W) B, H, W
---11111
ICR33
(R, R/W) B, H, W
---11111
ICR37
(R, R/W) B, H, W
---11111
ICR41
(R, R/W) B, H, W
---11111
ICR45
(R, R/W) B, H, W
---11111
+2
ICR02
(R, R/W) B, H, W
---11111
ICR06
(R, R/W) B, H, W
---11111
ICR10
(R, R/W) B, H, W
---11111
ICR14
(R, R/W) B, H, W
---11111
ICR18
(R, R/W) B, H, W
---11111
ICR22
(R, R/W) B, H, W
---11111
ICR26
(R, R/W) B, H, W
---11111
ICR30
(R, R/W) B, H, W
---11111
ICR34
(R, R/W) B, H, W
---11111
ICR38
(R, R/W) B, H, W
---11111
ICR42
(R, R/W) B, H, W
---11111
ICR46
(R, R/W) B, H, W
---11111
+3
ICR03
(R, R/W) B, H, W
---11111
ICR07
(R, R/W) B, H, W
---11111
ICR11
(R, R/W) B, H, W
---11111
ICR15
(R, R/W) B, H, W
---11111
ICR19
(R, R/W) B, H, W
---11111
ICR23
(R, R/W) B, H, W
---11111
ICR27
(R, R/W) B, H, W
---11111
ICR31
(R, R/W) B, H, W
---11111
ICR35
(R, R/W) B, H, W
---11111
ICR39
(R, R/W) B, H, W
---11111
ICR43
(R, R/W) B, H, W
---11111
ICR47
(R, R/W) B, H, W
---11111
—
—
—
—
RSRR
(R, R/W) B, H, W
X-***-00*2
CLKR
(R/W) B, H, W
00000000
STCR
(R/W) B, H, W
00110011
WPR
(W) B, H, W
XXXXXXXX
CTBR
(W) B, H, W
XXXXXXXX
DIVR1
(R/W) B, H, W
00000000
000488H
—
—
00048CH
—
—
TBCR
(R/W, R) B, H, W
00XXXX11
DIVR0
(R/W) B, H, W
00000011
OSCCR
(R/W) B
XXXXXXX0
—
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
000470H
to
00047CH
000480H
000484H
552
FUJITSU MICROELECTRONICS LIMITED
Block
Interrupt Control
Unit
Reserved
Clock Control
Unit
—
—
Reserved
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (9 / 17)
Register
Address
+0
+1
+2
+3
Block
000490H
OSCR
(R/W, W) B
000XX000
—
—
—
Main
Oscillation
Stabilization
Wait Register
000494H
PLLC
(R/W, R) B, H, W
X1000101
—
—
—
PLL Controller
000498H
to
0004FCH
—
—
—
—
Reserved
PPER0
(R/W) B, H, W
00000000
PPER4
(R/W) B, H, W
00000000
PPER8
(R/W) B, H, W
--000000
PPERC
(R/W) B, H, W
00000000
PPER1
(R/W) B, H, W
00000000
PPER5
(R/W) B, H, W
00000000
PPER9
(R/W) B, H, W
00000000
PPERD
(R/W) B, H, W
00000000
PPER2
(R/W) B, H, W
00000000
PPER6
(R/W) B, H, W
---00000
PPERA
(R/W) B, H, W
00000000
PPERE
(R/W) B, H, W
-----000
PPER3
(R/W) B, H, W
00000000
PPER7
(R/W) B, H, W
00000000
PPERB
(R/W) B, H, W
00000000
PPERF
(R/W) B, H, W
00000000
Port Pull-up/
Pull-down
Enable Register
—
—
—
—
Reserved
PPCR0
(R/W) B, H, W
11111111
PPCR4
(R/W) B, H, W
11111111
PPCR8
(R/W) B, H, W
--111111
PPCRC
(R/W) B, H, W
11111111
PPCR1
(R/W) B, H, W
11111111
PPCR5
(R/W) B, H, W
11111111
PPCR9
(R/W) B, H, W
11111111
PPCRD
(R/W) B, H, W
11111111
PPCR2
(R/W) B, H, W
11111111
PPCR6
(R/W) B, H, W
---11111
PPCRA
(R/W) B, H, W
11111111
PPCRE
(R/W) B, H, W
-----111
PPCR3
(R/W) B, H, W
11111111
PPCR7
(R/W) B, H, W
11111111
PPCRB
(R/W) B, H, W
11111111
PPCRF
(R/W) B, H, W
11111111
Port Pull-up/
Pull-down
Control Register
—
—
—
—
Reserved
PILR0
(R/W) B, H, W
00000000
PILR4
(R/W) B, H, W
00000000
PILR1
(R/W) B, H, W
00000000
PILR5
(R/W) B, H, W
00000000
PILR2
(R/W) B, H, W
00000000
PILR6
(R/W) B, H, W
---00000
PILR3
(R/W) B, H, W
00000000
PILR7
(R/W) B, H, W
00000000
Port Input Level
Select Register
000500H
000504H
000508H
00050CH
000510H
to
00051CH
000520H
000524H
000528H
00052CH
000530H
to
00053CH
000540H
000544H
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
553
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (10 / 17)
Address
000548H
00054CH
000550H
to
00061CH
000620H
000624H
000628H
00062CH
000630H
to
000FFCH
001000H
001004H
001008H
00100CH
001010H
001014H
001018H
00101CH
554
Register
Block
+0
PILR8
(R/W) B, H, W
--000000
PILRC
(R/W) B, H, W
00000000
+1
PILR9
(R/W) B, H, W
00000000
PILRD
(R/W) B, H, W
00000000
+2
PILRA
(R/W) B, H, W
00000000
PILRE
(R/W) B, H, W
-----000
+3
PILRB
(R/W) B, H, W
00000000
PILRF
(R/W) B, H, W
00000000
—
—
—
—
Reserved
PIDR0
(R) B, H, W
XXXXXXXX
PIDR4
(R) B, H, W
XXXXXXXX
PIDR8
(R) B, H, W
--XXXXXX
PIDRC
(R) B, H, W
XXXXXXXX
PIDR1
(R) B, H, W
XXXXXXXX
PIDR5
(R) B, H, W
XXXXXXXX
PIDR9
(R) B, H, W
XXXXXXXX
PIDRD
(R) B, H, W
XXXXXXXX
PIDR2
(R) B, H, W
XXXXXXXX
PIDR6
(R) B, H, W
---XXXXX
PIDRA
(R) B, H, W
XXXXXXXX
PIDRE
(R) B, H, W
-----XXX
PIDR3
(R) B, H, W
XXXXXXXX
PIDR7
(R) B, H, W
XXXXXXXX
PIDRB
(R) B, H, W
XXXXXXXX
PIDRF
(R) B, H, W
XXXXXXXX
Input Data
Direct Read
Register
—
—
—
—
Reserved
DMASA0
(R/W) W
00000000 00000000 00000000 00000000
DMADA0
(R/W) W
00000000 00000000 00000000 00000000
DMASA1
(R/W) W
00000000 00000000 00000000 00000000
DMADA1
(R/W) W
00000000 00000000 00000000 00000000
DMASA2
(R/W) W
00000000 00000000 00000000 00000000
DMADA2
(R/W) W
00000000 00000000 00000000 00000000
DMASA3
(R/W) W
00000000 00000000 00000000 00000000
DMADA3
(R/W) W
00000000 00000000 00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
Port Input Level
Select Register
DMAC
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (11 / 17)
Register
Address
+0
+1
001024H
001028H
to
006FFCH
007004H
+3
DMASA4
(R/W) W
00000000 00000000 00000000 00000000
DMADA4
(R/W) W
00000000 00000000 00000000 00000000
001020H
007000H
+2
—
FLCR
(R/W, R) B, H, W
0000X101
FLWC
(R/W) B, H, W
01011011
007008H
to
01FFFCH
020000H
020004H
020008H
02000CH
020010H
020014H
020018H
02001CH
020020H
020024H
CM71-10139-5E
Block
DMAC
—
—
—
—
—
—
Reserved
Flash Interface
—
CTRLR0
(R/W, R) B, H, W
00000000 00000001
ERRCNT0
(R) B, H, W
00000000 00000000
INTR0
(R) B, H, W
00000000 00000000
BRPER0
(R, R/W) B, H, W
00000000 00000000
IF1CREQ0
(R/W, R) B, H, W
00000000 00000001
IF1MSK20
(R/W, R) B, H, W
11111111 11111111
IF1ARB20
(R/W) B, H, W
00000000 00000000
IF1MCTR0
(R/W, R) B, H, W
00000000 00000000
IF1DTA10
(R/W) B, H, W
00000000 00000000
IF1DTB10
(R/W) B, H, W
00000000 00000000
—
—
—
—
—
—
STATR0
(R/W, R) B, H, W
00000000 00000000
BTR0
(R/W, R) B, H, W
00100011 00000001
TESTR0
(R/W, R) B, H, W
00000000 r0000000*3
—
Reserved
CAN Controller
0
—
IF1CMSK0
(R/W, R) B, H, W
00000000 00000000
IF1MSK10
(R/W) B, H, W
11111111 11111111
IF1ARB10
(R/W) B, H, W
00000000 00000000
—
CAN Controller
0
—
IF1DTA20
(R/W) B, H, W
00000000 00000000
IF1DTB20
(R/W) B, H, W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
555
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (12 / 17)
Address
020028H
to
02002CH
Register
+0
+1
+2
+3
—
—
—
—
IF1DTA20
(R/W) B, H, W
00000000 00000000
IF1DTB10
(R/W) B, H, W
00000000 00000000
020030H
020034H
020038H
to
02003CH
—
020044H
020048H
02004CH
020050H
020054H
—
020064H
556
Reserved
CAN Controller
0
—
IF2DTA20
(R/W) B, H, W
00000000 00000000
IF2DTB20
(R/W) B, H, W
00000000 00000000
—
—
IF2DTA10
(R/W) B, H, W
00000000 00000000
IF2DTB10
(R/W) B, H, W
00000000 00000000
—
—
TREQR20
(R) B, H, W
00000000 00000000
—
—
—
Reserved
CAN Controller
0
IF2CMSK0
(R/W, R) B, H, W
00000000 00000000
IF2MSK10
(R/W) B, H, W
11111111 11111111
IF2ARB10
(R/W) B, H, W
00000000 00000000
—
—
020080H
020084H
to
02008CH
—
IF2DTA20
(R/W) B, H, W
00000000 00000000
IF2DTB20
(R/W) B, H, W
00000000 00000000
020060H
020068H
to
02007CH
—
IF2CREQ0
(R/W, R) B, H, W
00000000 00000001
IF2MSK20
(R/W, R) B, H, W
11111111 11111111
IF2ARB20
(R/W) B, H, W
00000000 00000000
IF2MCTR0
(R/W, R) B, H, W
00000000 00000000
IF2DTA10
(R/W) B, H, W
00000000 00000000
IF2DTB10
(R/W) B, H, W
00000000 00000000
020040H
020058H
to
02005CH
IF1DTA10
(R/W) B, H, W
00000000 00000000
IF1DTB20
(R/W) B, H, W
00000000 00000000
Block
CAN Controller
0
—
TREQR10
(R) B, H, W
00000000 00000000
—
—
FUJITSU MICROELECTRONICS LIMITED
Reserved
Reserved
CAN Controller
0
—
Reserved
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (13 / 17)
Address
Register
+0
—
020100H
020104H
020108H
02010CH
020110H
020114H
020118H
02011CH
020120H
020124H
CM71-10139-5E
—
—
—
—
—
Reserved
CAN Controller
0
MSGVAL10
(R) B, H, W
00000000 00000000
—
CTRLR1
(R/W, R) B, H, W
00000000 00000001
ERRCNT1
(R) B, H, W
00000000 00000000
INTR1
(R) B, H, W
00000000 00000000
BRPER1
(R, R/W) B, H, W
00000000 00000000
IF1CREQ1
(R/W, R) B, H, W
00000000 00000001
IF1MSK21
(R/W, R) B, H, W
11111111 11111111
IF1ARB21
(R/W) B, H, W
00000000 00000000
IF1MCTR1
(R/W, R) B, H, W
00000000 00000000
IF1DTA11
(R/W) B, H, W
00000000 00000000
IF1DTB11
(R/W) B, H, W
00000000 00000000
—
—
Block
CAN Controller
0
INTPND10
(R) B, H, W
00000000 00000000
MSGVAL20
(R) B, H, W
00000000 00000000
0200B0H
0200B4H
to
0200FCH
—
—
+3
NEWDT10
(R) B, H, W
00000000 00000000
INTPND20
(R) B, H, W
00000000 00000000
0200A0H
0200A4H
to
0200ACH
+2
NEWDT20
(R) B, H, W
00000000 00000000
020090H
020094H
to
02009CH
+1
Reserved
CAN Controller
0
—
Reserved
STATR1
(R/W, R) B, H, W
00000000 00000000
BTR1
(R/W, R) B, H, W
00100011 00000001
TESTR1
(R/W, R) B, H, W
00000000 r0000000*3
—
—
IF1CMSK1
(R/W, R) B, H, W
00000000 00000000
IF1MSK11
(R/W) B, H, W
11111111 11111111
IF1ARB11
(R/W) B, H, W
00000000 00000000
—
CAN Controller
1
—
IF1DTA21
(R/W) B, H, W
00000000 00000000
IF1DTB21
(R/W) B, H, W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
557
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (14 / 17)
Address
020128H
to
02012CH
Register
+0
+1
+2
+3
—
—
—
—
IF1DTA21
(R/W) B, H, W
00000000 00000000
IF1DTB11
(R/W) B, H, W
00000000 00000000
020130H
020134H
020138H
to
02013CH
—
020144H
020148H
02014CH
020150H
020154H
—
020164H
558
Reserved
CAN Controller
1
—
IF2DTA21
(R/W) B, H, W
00000000 00000000
IF2DTB21
(R/W) B, H, W
00000000 00000000
—
—
IF2DTA11
(R/W) B, H, W
00000000 00000000
IF2DTB11
(R/W) B, H, W
00000000 00000000
—
—
TREQR21
(R) B, H, W
00000000 00000000
—
—
—
Reserved
CAN Controller
1
IF2CMSK1
(R/W, R) B, H, W
00000000 00000000
IF2MSK11
(R/W) B, H, W
11111111 11111111
IF2ARB11
(R/W) B, H, W
00000000 00000000
—
—
020180H
020184H
to
02018CH
—
IF2DTA21
(R/W) B, H, W
00000000 00000000
IF2DTB21
(R/W) B, H, W
00000000 00000000
020160H
020168H
to
02017CH
—
IF2CREQ1
(R/W, R) B, H, W
00000000 00000001
IF2MSK21
(R/W, R) B, H, W
11111111 11111111
IF2ARB21
(R/W) B, H, W
00000000 00000000
IF2MCTR1
(R/W, R) B, H, W
00000000 00000000
IF2DTA11
(R/W) B, H, W
00000000 00000000
IF2DTB11
(R/W) B, H, W
00000000 00000000
020140H
020158H
to
02015CH
IF1DTA11
(R/W) B, H, W
00000000 00000000
IF1DTB21
(R/W) B, H, W
00000000 00000000
Block
CAN Controller
1
—
TREQR11
(R) B, H, W
00000000 00000000
—
—
FUJITSU MICROELECTRONICS LIMITED
Reserved
Reserved
CAN Controller
1
—
Reserved
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (15 / 17)
Address
Register
+0
—
020200H
020204H
020208H
02020CH
020210H
020214H
020218H
02021CH
020220H
020224H
CM71-10139-5E
—
—
—
INTR2 (R) B, H, W
00000000 00000000
BRPER2
(R, R/W) B, H, W
00000000 00000000
IF1CREQ2
(R/W, R) B, H, W
00000000 00000001
IF1MSK22
(R/W, R) B, H, W
11111111 11111111
IF1ARB22
(R/W) B, H, W
00000000 00000000
IF1MCTR2
(R/W, R) B, H, W
00000000 00000000
IF1DTA12
(R/W) B, H, W
00000000 00000000
IF1DTB12
(R/W) B, H, W
00000000 00000000
—
—
Reserved
CAN Controller
1
MSGVAL11
(R) B, H, W
00000000 00000000
—
CTRLR2
(R/W, R) B, H, W
00000000 00000001
ERRCNT2
(R) B, H, W
00000000 00000000
—
—
Block
CAN Controller
1
INTPND11
(R) B, H, W
00000000 00000000
MSGVAL21
(R) B, H, W
00000000 00000000
0201B0H
0200B4H
to
0200FCH
—
—
+3
NEWDT11
(R) B, H, W
00000000 00000000
INTPND21
(R) B, H, W
00000000 00000000
0201A0H
0201A4H
to
0201ACH
+2
NEWDT21
(R) B, H, W
00000000 00000000
020190H
020194H
to
02019CH
+1
Reserved
CAN Controller
1
—
Reserved
STATR2
(R/W, R) B, H, W
00000000 00000000
BTR2
(R/W, R) B, H, W
00100011 00000001
TESTR2
(R/W, R) B, H, W
00000000 r0000000*3
—
—
IF1CMSK2
(R/W, R) B, H, W
00000000 00000000
IF1MSK12
(R/W) B, H, W
11111111 11111111
IF1ARB12
(R/W) B, H, W
00000000 00000000
—
CAN Controller
2
—
IF1DTA22
(R/W) B, H, W
00000000 00000000
IF1DTB22
(R/W) B, H, W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
559
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (16 / 17)
Address
020228H
to
02022CH
Register
+0
+1
+2
+3
—
—
—
—
IF1DTA22
(R/W) B, H, W
00000000 00000000
IF1DTB22
(R/W) B, H, W
00000000 00000000
020230H
020234H
020238H
to
02023CH
—
020244H
020248H
02024CH
020250H
020254H
—
020264H
020280H
560
—
CAN Controller
2
—
—
—
IF2DTA12
(R/W) B, H, W
00000000 00000000
IF2DTB12
(R/W) B, H, W
00000000 00000000
—
TREQR22
(R) B, H, W
00000000 00000000
Reserved
IF2DTA22
(R/W) B, H, W
00000000 00000000
IF2DTB22
(R/W) B, H, W
00000000 00000000
—
—
—
—
Reserved
CAN Controller
2
IF2CMSK2
(R/W, R) B, H, W
00000000 00000000
IF2MSK12
(R/W) B, H, W
11111111 11111111
IF2ARB12
(R/W) B, H, W
00000000 00000000
IF2DTA22
(R/W) B, H, W
00000000 00000000
IF2DTB22
(R/W) B, H, W
00000000 00000000
020260H
020268H
to
02027CH
—
IF2CREQ2
(R/W, R) B, H, W
00000000 00000001
IF2MSK22
(R/W, R) B, H, W
11111111 11111111
IF2ARB22
(R/W) B, H, W
00000000 00000000
IF2MCTR2
(R/W, R) B, H, W
00000000 00000000
IF2DTA12
(R/W) B, H, W
00000000 00000000
IF2DTB12
(R/W) B, H, W
00000000 00000000
020240H
020258H
to
02025CH
IF1DTA12
(R/W) B, H, W
00000000 00000000
IF1DTB12
(R/W) B, H, W
00000000 00000000
Block
—
CAN Controller
2
—
TREQR12
(R) B, H, W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
Reserved
Reserved
CAN Controller
2
CM71-10139-5E
APPENDIX
APPENDIX A I/O Map
MB91210 Series
Appendix Table A-1 I/O Map (17 / 17)
Address
020284H
to
02028CH
Register
+0
+1
+2
+3
—
—
—
—
NEWDT22
(R) B, H, W
00000000 00000000
020290H
020294H
to
02029CH
—
0202B0H
—
—
INTPND22
(R) B, H, W
00000000 00000000
0202A0H
0202A4H
to
0202ACH
NEWDT12
(R) B, H, W
00000000 00000000
—
—
MSGVAL22
(R) B, H, W
00000000 00000000
—
Reserved
CAN Controller
2
—
MSGVAL12
(R) B, H, W
00000000 00000000
Reserved
CAN Controller
2
INTPND12
(R) B, H, W
00000000 00000000
—
Block
Reserved
CAN Controller
2
*1 : The lower 16 bits (DTC[15:0]) cannot be accessed in bytes.
*2 : It differs depending on the source.
*3 : As for bit7, the level of the RX pin is read.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
561
APPENDIX
APPENDIX B Vector Table
MB91210 Series
APPENDIX B Vector Table
Table B-1 contains an interrupt vector table. This table shows interrupt sources used in
MB91210 series as well as assigned interrupt vectors and interrupt control registers.
■ Vector Table
ICR:
This sets the interrupt level for each interrupt request by the registers provided in the interrupt
controller. ICR is available for each corresponding interrupt request.
TBR:
This is the register that indicates the start address of the EIT vector table.
The vector address is calculated by adding TBR to the offset value determined for each EIT source.
The EIT vector area is a 1Kbyte area starting from the address indicated by TBR.
Each vector consists of 4 bytes. The relationship between vector numbers and vector addresses is as
follows:
vctadr
= TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct:
562
Vector number
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX B Vector Table
MB91210 Series
Appendix Table B-1 Vector Table (1 / 3)
Interrupt number
Interrupt cause
Interrupt level
Offset
TBR default
address
Decimal Hexadecimal
Reset*
0
00
−
3FCH
000FFFFCH
Mode vector*
1
01
−
3F8H
000FFFF8H
System reserved
2
02
−
3F4H
000FFFF4H
System reserved
3
03
−
3F0H
000FFFF0H
System reserved
4
04
−
3ECH
000FFFECH
System reserved
5
05
−
3E8H
000FFFE8H
System reserved
6
06
−
3E4H
000FFFE4H
Coprocessor absent trap
7
07
−
3E0H
000FFFE0H
Coprocessor error trap
8
08
−
3DCH
000FFFDCH
INTE instruction
9
09
−
3D8H
000FFFD8H
System reserved
10
0A
−
3D4H
000FFFD4H
System reserved
11
0B
−
3D0H
000FFFD0H
Step trace trap
12
0C
−
3CCH
000FFFCCH
NMI request (ICE)
13
0D
−
3C8H
000FFFC8H
Undefined-instruction exception
14
0E
−
3C4H
000FFFC4H
NMI request
15
0F
Fixed 15 (FH)
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART 0 (reception)
27
1B
ICR11
390H
000FFF90H
UART 0 (transmission)
28
1C
ICR12
38CH
000FFF8CH
UART 1 (reception)
29
1D
ICR13
388H
000FFF88H
UART 1 (transmission)
30
1E
ICR14
384H
000FFF84H
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
563
APPENDIX
APPENDIX B Vector Table
MB91210 Series
Appendix Table B-1 Vector Table (2 / 3)
Interrupt number
Interrupt cause
Interrupt level
Offset
TBR default
address
Decimal Hexadecimal
UART 2 (reception)
31
1F
ICR15
380H
000FFF80H
UART 2 (transmission)
32
20
ICR16
37CH
000FFF7CH
CAN 0
33
21
ICR17
378H
000FFF78H
CAN 1
34
22
ICR18
374H
000FFF74H
UART 3/5 (reception)
35
23
ICR19
370H
000FFF70H
UART 3/5 (transmission)
36
24
ICR20
36CH
000FFF6CH
UART 4/6 (reception)
37
25
ICR21
368H
000FFF68H
UART 4/6 (transmission)
38
26
ICR22
364H
000FFF64H
AD convertor
39
27
ICR23
360H
000FFF60H
RTC/CAN 2
40
28
ICR24
35CH
000FFF5CH
ICU 0
41
29
ICR25
358H
000FFF58H
ICU 1
42
2A
ICR26
354H
000FFF54H
ICU 2/3
43
2B
ICR27
350H
000FFF50H
ICU 4/5/6/7
44
2C
ICR28
34CH
000FFF4CH
FRT 0/1/2/3
45
2D
ICR29
348H
000FFF48H
Main oscillation stabilization wait timer
46
2E
ICR30
344H
000FFF44H
Overflow of time-base timer
47
2F
ICR31
340H
000FFF40H
OCU 0/1/2/3
48
30
ICR32
33CH
000FFF3CH
OCU 4/5/6/7
49
31
ICR33
338H
000FFF38H
PPG 0
50
32
ICR34
334H
000FFF34H
PPG 1
51
33
ICR35
330H
000FFF30H
PPG 2/3
52
34
ICR36
32CH
000FFF2CH
PPG 4/5/6/7
53
35
ICR37
328H
000FFF28H
PPG 8/9/A/B
54
36
ICR38
324H
000FFF24H
PPG C/D/E/F
55
37
ICR39
320H
000FFF20H
External interrupt 8
56
38
ICR40
31CH
000FFF1CH
External interrupt 9
57
39
ICR41
318H
000FFF18H
External interrupt 10
58
3A
ICR42
314H
000FFF14H
External interrupt 11
59
3B
ICR43
310H
000FFF10H
External interrupt 12/13
60
3C
ICR44
30CH
000FFF0CH
External interrupt 14/15
61
3D
ICR45
308H
000FFF08H
DMA (termination, error)
62
3E
ICR46
304H
000FFF04H
564
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX B Vector Table
MB91210 Series
Appendix Table B-1 Vector Table (3 / 3)
Interrupt number
Interrupt cause
Interrupt level
Offset
TBR default
address
Decimal Hexadecimal
Delayed interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved
(Used by REALOS))
64
40
—
2FCH
000FFEFCH
System reserved
(Used by REALOS))
65
41
—
2F8H
000FFEF8H
System reserved
66
42
—
2F4H
000FFEF4H
System reserved
67
43
—
2F0H
000FFEF0H
System reserved
68
44
—
2ECH
000FFEECH
System reserved
69
45
—
2E8H
000FFEE8H
System reserved
70
46
—
2E4H
000FFEE4H
System reserved
71
47
—
2E0H
000FFEE0H
System reserved
72
48
—
2DCH
000FFEDCH
System reserved
73
49
—
2D8H
000FFED8H
System reserved
74
4A
—
2D4H
000FFED4H
System reserved
75
4B
—
2D0H
000FFED0H
System reserved
76
4C
—
2CCH
000FFECCH
System reserved
77
4D
—
2C8H
000FFEC8H
System reserved
78
4E
—
2C4H
000FFEC4H
System reserved
79
4F
—
2C0H
000FFEC0H
Used by INT instruction
80 to 255
50 to FF
—
2BCH to
000H
000FFEBCH to
000FFC00H
* : Even if changing the value of TBR, the fixed address, 000FFFFCH and 000FFFF8H are always used for reset vector and
mode vector.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
565
APPENDIX
APPENDIX C Status of Each Pin in Each CPU state
APPENDIX C
MB91210 Series
Status of Each Pin in Each CPU state
This appendix defines the following terms related to pin states:
■ Pin States in Each CPU State
• Input enabled
Means that an input function can be used.
• Input fixed to "0"
A state of a pin, in which "0" is transmitted to internal circuitry, with the external input shut off by the input
gate adjacent to the pin.
• Output Hi-Z
Means to place a pin in a high impedance state by disabling the pin driving transistor from driving.
• Output storage
Means to output the state existing immediately prior to entering this mode.
That is, to output according to an internal resource with an output when it is operating or to preserve an
output when the output is provided, for example, as a port.
• Preserving the previous state
Means to be able to output or input the state existing immediately prior to entering this mode.
• Pull-down
Means that an built-in pull-down resistor is enabled.
566
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX C Status of Each Pin in Each CPU state
MB91210 Series
Appendix Table C-1 Single Chip Mode (1 / 4)
Pin name
Function name
INITX
INITX
X0
X0
X1
X1
X0A
X0A
X1A
X1A
MD0
MD0
MD1
MD1
MD2
MD2
MD3
MD3
P00
P00/SIN5/INT8R
P01
P01/SOT5/INT9R
P02
P02/SCK5/INT10R
P03
P03/SIN6/INT11R
P04
P04/SOT6/INT12R
P05
P05/SCK6/INT13R
P06
P06/OUT4/INT14R
P07
P07/OUT5/INT15R
P10
P10/TIN1
P11
P11/TOT1
P12
P12/SIN3
P13
P13/SOT3
P14
P14/SCK3
P15
P15/SIN4
P16
P16/SOT4
P17
P17/SCK4
Initial value
INITX = “L” INITX = “H”
Input
enabled
Input
enabled
In stop state
In sleep state
HIZ = 0
HIZ = 1
Input enabled
Input enabled
Pull-down
Pull-down
Input enabled
Input enabled
Input
enabled
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding
status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z/
internal input held
P20 to P27/
P20 to P27 PPG0, 2, 4, 6, 8, A,
C, E
CM71-10139-5E
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APPENDIX
APPENDIX C Status of Each Pin in Each CPU state
MB91210 Series
Appendix Table C-1 Single Chip Mode (2 / 4)
Pin name
Function name
Initial value
INITX = “L” INITX = “H”
In stop state
In sleep state
HIZ = 0
HIZ = 1
P30
P30/ (RX2) /
(INT10C)
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
P31
P31/ (TX2)
Output Hi-Z/
internal input held
P32
P32/INT10
P33 to P37
P33 to P37/
INT11 to INT15
P40 to P43
P40 to P43/
PPG9, B, D, F
P44 to P47
P44 to P47/
IN0 to IN3
P50 to P53
P50 to P53/
PPG1, 3, 5, 7
P54
P54/IN4
P55
P55/IN5
P56
P56/IN6
P57
P57/IN7
P60
P60/OUT6
P61
P61/OUT7
P62
P62
P63
P63
P64
P64
568
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding
status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z/
internal input held
P70
P70/RX0/INT8
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
P71
P71/TX0
Output Hi-Z/
internal input held
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CM71-10139-5E
APPENDIX
APPENDIX C Status of Each Pin in Each CPU state
MB91210 Series
Appendix Table C-1 Single Chip Mode (3 / 4)
Pin name
Function name
P72
P72/RX1/INT9
P73
P73/TX1
P74 to P77
P74 to P77/
OUT0 to OUT3
P80 to P83
P80 to P83/
FRCK0 to FRCK3
P84
P84/TIN2
P85
P85/TOT2
P90 to P97/PPG0R,
P90 to P97 2R, 4R, 6R, 8R, AR,
CR, ER/AN0 to AN7
PA0
PA0/SIN2R/AN8
PA1
PA1/SOT2R/AN9
PA2
PA2/SCK2R/AN10
PA3 to
PA7
PA3 to PA7/
AN11 to AN15
Initial value
INITX = “L” INITX = “H”
In stop state
In sleep state
HIZ = 0
HIZ = 1
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
Output Hi-Z/
internal input held
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
P:
Immediately
preceding status held
F:
Normal
operation
performed
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
Output Hi-Z/
internal input held
PB0 to
PB7
PB0 to PB7/
INT0R to INT7R/
AN16 to AN23
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
PC0 to
PC7
PC0 to PC7/
AN24 to AN31
Output Hi-Z/
internal input held
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APPENDIX
APPENDIX C Status of Each Pin in Each CPU state
MB91210 Series
Appendix Table C-1 Single Chip Mode (4 / 4)
Pin name
Function name
PD0
PD0/TIN0/ATGX
PD1
PD1/TOT0
PD2
PD2/SIN0
PD3
PD3/SOT0
PD4
PD4/SCK0
PD5
PD5/SIN1
PD6
PD6/SOT1
PD7
PD7/SCK1
PE0
PE0/SIN2
PE1
PE1/SOT2
PE2
PE2/SCK2
PF0 to
PF7
570
Initial value
INITX = “L” INITX = “H”
Output
Hi-Z input
enabled
Output
Hi-Z input
enabled
In stop state
In sleep state
P:
Immediately
preceding status held
F:
Normal
operation
performed
HIZ = 0
P:
Immediately
preceding
status held
F:
Output held or
Hi-Z ,
input enabled
HIZ = 1
Output Hi-Z/
internal input held
Output Hi-Z/
selecting interrupt
function, and input
enabled when
interrupt is allowed
during ENIR
internal input held
PF0 to PF7/
INT0 to INT7
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
APPENDIX D INSTRUCTION LISTS
This section provides lists of the FR family instructions.
Before the lists are presented, the following items are explained to make the lists easier
to understand:
• How to read the instruction lists
• Addressing mode symbols
• Instruction format
■ How to Read the Instruction Lists
Mnemonic
Type
OP
CYCLE
NZVC
Operation
ADD
*ADD
Rj, Rj
#s5, Rj
,
,
A
C
,
,
AG
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj --> Rj
Ri + s5 --> Ri
,
,
↓
1.
↓
2.
↓
3.
↓
4.
↓
5.
↓
6.
↓
7.
Remarks
1. Instruction name.
•
An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications and
is obtained by extension of or addition of the instruction with the assembler.
2. Symbols indicating addressing modes that can be specified for the operand.
•
For the meaning of symbols, see "■ Addressing Mode Symbols".
3. Instruction format.
4. Instruction code in hexadecimal notation.
Code: CM71-00103-3E
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APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
5. Number of instruction execution cycles.
•
a: Memory access cycle that may be extended by the wait cycle.
•
b: Memory access cycle that may be extended by the wait cycle. However, the cycle is interlocked if
a next instruction references a register intended for an LD operation, increasing the number of
execution cycles by 1.
•
c: Interlocked if the next instruction is an instruction that reads or writes to R15, SSP, or USP, or an
instruction in instruction format A. The number of execution cycles increases by 1 to become 2.
•
d: Interlocked if the next instruction references MDH/MDL. The number of execution cycles
increases to 2.
Always interlocked, when the special register (TBR, RP, USP, SSP, MDH, and MDL) is accessed
by "ST Rs, @-R15" instruction immediately after the DIV1 instruction. The number of execution
cycles increases to 2.
•
The minimum cycle for a, b, c, and d is 1.
6. Indicates a flag change.
Flag change
Flag meaning
C: Change
N: Negative flag
- : No change
Z: Zero flag
0: Clear
V: Overflow flag
1: Set
C: Carry flag
7. Instruction operation.
572
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CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Addressing Mode Symbols
Table D-1 Explanation of Addressing Mode Symbols (1/2)
Symbol
Meaning
Ri
Register direct (R0 to R15, AC, FP, SP)
Rj
Register direct (R0 to R15, AC, FP, SP)
R13
Register direct (R13, AC)
PS
Register direct (program status register)
Rs
Register direct (TBR, RP, SSP, USP, MDH, MDL)
CRi
Register direct (CR0 to CR15)
CRj
Register direct (CR0 to CR15)
#i4
Unsigned 4-bit immediate data
(0 to 15 or -16 to -1 depending on types of instruction)
#i8
Unsigned 8-bit immediate data (-128 to 255)
Note: -128 to -1 are handled as 128 to 255.
#i20
Unsigned 20-bit immediate data (-0x80000 to 0xFFFFF)
Note: -0x7FFFF to -1 are handled as 0x7FFFF to 0xFFFFF.
#i32
Unsigned 32-bit immediate data (-0X80000000 to 0XFFFFFFFF)
Note: -0x80000000 to -1 are handled as 0x80000000 to 0xFFFFFFFF.
#s5
Signed 5-bit immediate data (-16 to 15)
#s10
Signed 10-bit immediate data (-512 to 508, multiples of 4 only)
#u4
Unsigned 4-bit immediate data (0 to 15)
#u5
Unsigned 5-bit immediate data (0 to 31)
#u8
Unsigned 8-bit immediate data (0 to 255)
#u10
Unsigned 10-bit immediate data (0 to 1020, multiples of 4 only)
@dir8
Unsigned 8-bit direct address (0 to 0xFF)
@dir9
Unsigned 9-bit direct address (0 to 0x1FE, multiple of 2 only)
@dir10
Unsigned 10-bit direct address (0 to 0x3FC, multiples of 4 only)
label9
Signed 9-bit branch address (-0x100 to 0xFC, multiples of 2 only)
label12
Signed 12-bit branch address (-0x800 to 0x7FC, multiples of 2 only)
label20
Signed 20-bit branch address (-0x80000 to 0x7FFFF)
label32
Signed 32-bit branch address (-0x80000000 to 0x7FFFFFFF)
@Ri
Register indirect (R0 to R15, AC, FP, SP)
@Rj
Register indirect (R0 to R15, AC, FP, SP)
@(R13,Rj)
Register relative indirect (Rj: R0 to R15, AC, FP, SP)
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APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
Table D-1 Explanation of Addressing Mode Symbols (1/2)
Symbol
Meaning
@(R14,disp10)
Register relative indirect (disp10: -0x200 to 0x1FC, multiples of 4 only)
@(R14,disp9)
Register relative indirect (disp9: -0x100 to 0xFE, multiples of 2 only)
@(R14,disp8)
Register relative indirect (disp8: -0x80 to 0x7F)
@(R15,udisp6)
Register relative indirect (udisp6: 0 to 60, multiples of 4 only)
@Ri+
Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
Register indirect with post-increment (R13, AC)
@SP+
Stack pop
@-SP
Stack push
(reglist)
Register list
• extu()....... indicates a zero extension operation, in which values lacking high-order bits are
complemented by adding "0" as necessary.
• extn()....... indicates a minus extension operation, in which values lacking high-order bits are
complemented by adding "1" as necessary.
• exts() ....... indicates a sign extension operation in which a zero extension is performed for the data within
( ) in which the MSB is "0" and a minus extension is performed for the data in which the MSB
is "1".
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CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Instruction Format
Table D-2 Instruction Format
Type
Instruction format
MSB
LSB
16 bits
A
B
OP
Rj
Ri
8
4
4
OP
i8/o8
Ri
4
8
4
OP
u4/m4/i4
Ri
8
4
4
C
ADD, ADDN, CMP, LSL, LSR, ASR instructions only
*C’
OP
s5/u5
Ri
7
5
4
D
E
F
CM71-10139-5E
OP
u8/rel8/dir/
reglist
8
8
OP
SUB-OP
Ri
8
4
4
OP
rel11
5
11
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APPENDIX
APPENDIX D INSTRUCTION LISTS
D.1
MB91210 Series
FR Family Instruction Lists
The FR family instruction lists are presented in the order listed below.
■ FR Family Instruction Lists
Table D-3 Add-Subtract Instructions
Table D-4 Compare Operation Instructions
Table D-5 Logic Operation Instructions
Table D-6 Bit Manipulation Instructions
Table D-7 Multiply/Divide Instructions
Table D-8 Shift Instructions
Table D-9 Immediate Set/16-bit/32-bit Immediate Transfer Instructions
Table D-10 Memory Load Instructions
Table D-11 Memory Store Instructions
Table D-12 Register-to-Register Transfer Instructions
Table D-13 Normal Branch (No Delay) Instructions
Table D-14 Delayed Branch Instructions
Table D-15 Other Instructions
Table D-16 20-Bit Normal Branch Macro Instructions
Table D-17 20-Bit Delayed Branch Macro Instructions
Table D-18 32-Bit Normal Branch Macro Instructions
Table D-19 32-Bit Delayed Branch Macro Instructions
Table D-20 Direct Addressing Instructions
Table D-21 Resource Instructions
Table D-22 Coprocessor Control Instructions
576
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CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Add-Subtract Instructions
Table D-3 Add-Subtract Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ADD Rj, Ri
A
A6
1
CCCC
Ri + Rj → Ri
*ADD #s5, Ri
C’
A4
1
CCCC
Ri + s5 → Ri
The assembler treats the
highest-order bit as the sign.
ADD #i4, Ri
C
A4
1
CCCC
Ri + extu(i4) → Ri
Zero extension
ADD2 #i4, Ri
C
A5
1
CCCC
Ri + extn(i4) → Ri
Minus extension
ADDC Rj, Ri
A
A7
1
CCCC
Ri + Rj + c → Ri
Addition with carry
ADDN Rj, Ri
A
A2
1
----
Ri + Rj → Ri
*ADDN #s5, Ri
C’
A0
1
----
Ri + s5 → Ri
The assembler treats the
highest-order bit as the sign.
ADDN #i4, Ri
C
A0
1
----
Ri + extu(i4) → Ri
Zero extension
ADDN2 #i4, Ri
C
A1
1
----
Ri + extn(i4) → Ri
Minus extension
SUB
Rj, Ri
A
AC
1
CCCC
Ri - Rj → Ri
SUBC Rj, Ri
A
AD
1
CCCC
Ri - Rj - c → Ri
SUBN Rj, Ri
A
AE
1
----
Addition with carry
Ri - Rj → Ri
■ Compare Operation Instructions
Table D-4 Compare Operation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
CMP Rj, Ri
A
AA
1
CCCC
Ri - Rj
*CMP #s5, Ri
C’
A8
1
CCCC
Ri - s5
The assembler treats the
highest-order bit as the sign.
CMP
#i4, Ri
C
A8
1
CCCC
Ri - extu(i4)
Zero extension
CMP2 #i4, Ri
C
A9
1
CCCC
Ri - extn(i4)
Minus extension
CM71-10139-5E
Operation
FUJITSU MICROELECTRONICS LIMITED
Remarks
577
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Logic Operation Instructions
Table D-5 Logic Operation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
AND Rj, Ri
A
82
1
CC--
Ri &= Rj
Word
AND Rj, @Ri*
A
84
1+2a
CC--
(Ri) &= Rj
Word
ANDH Rj, @R*
A
85
1+2a
CC--
(Ri) &= Rj
Halfword
ANDB Rj, @Ri*
A
86
1+2a
CC--
(Ri) &= Rj
Byte
OR
Rj, Ri
A
92
1
CC--
Ri
|= Rj
Word
OR
Rj, @Ri*
A
94
1+2a
CC--
(Ri) |= Rj
Word
ORH Rj, @Ri*
A
95
1+2a
CC--
(Ri) |= Rj
Halfword
ORB Rj, @Ri*
A
96
1+2a
CC--
(Ri) |= Rj
Byte
EOR Rj, Ri
A
9A
1
CC--
Ri ^= Rj
Word
EOR Rj, @Ri*
A
9C
1+2a
CC--
(Ri) ^= Rj
Word
EORH Rj, @Ri*
A
9D
1+2a
CC--
(Ri) ^= Rj
Halfword
EORB Rj, @Ri*
A
9E
1+2a
CC--
(Ri) ^= Rj
Byte
*: If these instructions are written in the assembler, the general-purpose registers other than R15 is specified to Rj.
578
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Bit Manipulation Instructions
Table D-6 Bit Manipulation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
BANDL #u4, @Ri
C
80
1+2a
----
(Ri) &= (0xF0+u4)
Low-order 4 bits are
manipulated.
BANDH #u4, @Ri
C
81
1+2a
----
(Ri) &= ((u4<<4)+0x0F)
High-order 4 bits are
manipulated.
----
(Ri) &= u8
*BAND #u8, @Ri*1
BORL
#u4, @Ri
BORH #u4, @Ri
*BOR
Operation
Remarks
C
90
1+2a
----
(Ri) |= u4
Low-order 4 bits are
manipulated.
C
91
1+2a
----
(Ri) |= (u4<<4)
High-order 4 bits are
manipulated.
----
(Ri) |= u8
#u8, @Ri*2
BEORL #u4, @Ri
C
98
1+2a
----
(Ri) ^= u4
Low-order 4 bits are
manipulated.
BEORH #u4, @Ri
C
99
1+2a
----
(Ri) ^= (u4<<4)
High-order 4 bits are
manipulated.
----
(Ri) ^= u8
*BEOR #u8, @Ri*3
BTSTL #u4, @Ri
C
88
2+a
0C--
(Ri) & u4
Low-order 4-bit test.
BTSTH #u4, @Ri
C
89
2+a
CC--
(Ri) & (u4<<4)
High-order 4-bit test.
*1: The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some
cases, both BANDL and BANDH may be generated.
*2: The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases,
both BORL and BORH are generated.
*3: The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases,
both BEORL and BEORH are generated.
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APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Multiply/Divide Instructions
Table D-7 Multiply/Divide Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Rj,Ri
A
AF
5
CCC-
Ri * Rj → MDH,MDL
32 bits × 32 bits=64 bits
MULU Rj,Ri
A
AB
5
CCC-
Ri * Rj → MDH,MDL
No sign
MULH Rj,Ri
A
BF
3
CC--
Ri * Rj → MDL
16 bits × 16 bits=32 bits
MULUH Rj,Ri
A
BB
3
CC--
Ri * Rj → MDL
No sign
DIV0S Ri
E
97-4
1
----
Step operation
DIV0U
Ri
E
97-5
1
----
32 bits/32 bits=32 bits
DIV1
Ri
E
97-6
d
-C-C
DIV2
Ri*3
E
97-7
1
-C-C
DIV3
E
9F-6
1
----
DIV4S
E
9F-7
1
----
Ri*1
36
-C-C
MDL / Ri → MDL,
MDL % Ri → MDH*4
*DIVU Ri*2
33
-C-C
MDL / Ri → MDL,
MDL % Ri → MDH*4
MUL
*DIV
Operation
Remarks
No sign
*1: DIV0S, DIV1 x 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes.
*2: DIV0U or DIV1 x 32 is generated. The instruction code length becomes 66 bytes.
*3: Be sure to place a DIV3 instruction after a DIV2 instruction.
*4: % is remainder operator.
580
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Shift Instructions
Table D-8 Shift Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
LSL Rj, Ri
A
B6
1
CC-C
Ri << Rj → Ri
*LSL #u5, Ri (u5:0 to 31)
C’
B4
1
CC-C
Ri << u5 → Ri
LSL #u4, Ri
C
B4
1
CC-C
Ri << u4 → Ri
LSL2 #u4, Ri
C
B5
1
CC-C
Ri << (u4+16) → Ri
LSR Rj, Ri
A
B2
1
CC-C
Ri >> Rj → Ri
*LSR #u5, Ri (u5:0 to 31)
C’
B0
1
CC-C
Ri >> u5 → Ri
LSR #u4, Ri
C
B0
1
CC-C
Ri >> u4 → Ri
LSR2 #u4, Ri
C
B1
1
CC-C
Ri >> (u4+16) → Ri
ASR Rj, Ri
A
BA
1
CC-C
Ri >> Rj → Ri
*ASR #u5, Ri (u5:0 to 31)
C’
B8
1
CC-C
Ri >> u5 → Ri
ASR #u4, Ri
C
B8
1
CC-C
Ri >> u4 → Ri
ASR2 #u4, Ri
C
B9
1
CC-C
Ri >> (u4+16) → Ri
Remarks
Logical shift
Logical shift
Arithmetic shift
■ Immediate Set/16-bit/32-bit Immediate Transfer Instructions
Table D-9 Immediate Set/16-bit/32-bit Immediate Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
LDI:32 #i32, Ri
E
9F-8
3
----
i32 → Ri
LDI:20 #i20, Ri
C
9B
2
----
i20 → Ri
High-order 12 bits are
zero-extended.
LDI:8
B
C0
1
----
i8 → Ri
High-order 24 bits
are zero-extended.
#i8, Ri
*LDI # {i8 | i20 | i32} ,Ri*
Operation
Remarks
{i8 | i20 | i32} → Ri
*: If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32.
If immediate data contains a relative value or external reference symbol, i32 is selected.
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581
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Memory Load Instructions
Table D-10 Memory Load Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
LD
@Rj, Ri
A
04
b
----
(Rj) → Ri
LD
@(R13,Rj), Ri
A
00
b
----
(R13+Rj) → Ri
LD
@(R14,disp10), Ri
B
20
b
----
(R14+disp10) → Ri
LD
@(R15,udisp6), Ri
C
03
b
----
(R15+udisp6) → Ri
LD
@R15+, Ri
E
07-0
b
----
(R15) → Ri,R15+=4
LD
@R15+, Rs
E
07-8
b
----
(R15) → Rs, R15+=4
LD
@R15+, PS
E
07-9
1+a+c
CCCC
(R15) → PS, R15+=4
LDUH @Rj, Ri
A
05
b
----
(Rj) → Ri
Zero extension
LDUH @(R13,Rj), Ri
A
01
b
----
(R13+Rj) → Ri
Zero extension
LDUH @(R14,disp9), Ri
B
40
b
----
(R14+disp9) → Ri
Zero extension
LDUB @Rj, Ri
A
06
b
----
(Rj) → Ri
Zero extension
LDUB @(R13,Rj), Ri
A
02
b
----
(R13+Rj) → Ri
Zero extension
LDUB @(R14,disp8), Ri
B
60
b
----
(R14+disp8) → Ri
Zero extension
Rs: Special register *
*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
Note:
In the o8 and u4 fields of a Instruction Format, the assembler calculates values and sets them as
shown below:
- disp10/4 --> o8, disp9/2 --> o8, disp8 --> o8 (disp10, disp9, and disp8 have a sign.)
- udisp6/4 --> u4 (udisp6 has no sign.)
582
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Memory Store Instructions
Table D-11 Memory Store Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ST
Ri, @Rj
A
14
a
----
Ri → (Rj)
Word
ST
Ri, @(R13,Rj)
A
10
a
----
Ri → (R13+Rj)
Word
ST
Ri, @(R14,disp10)
B
30
a
----
Ri → (R14+disp10)
Word
ST
Ri, @(R15,udisp6)
C
13
a
----
Ri → (R15+udisp6)
ST
Ri, @-R15
E
17-0
a
----
R15-=4,Ri → (R15)
ST
Rs, @-R15
E
17-8
a
----
R15-=4, Rs → (R15)
ST
PS, @-R15
E
17-9
a
----
R15-=4, PS → (R15)
STH Ri, @Rj
A
15
a
----
Ri → (Rj)
Halfword
STH Ri, @(R13,Rj)
A
11
a
----
Ri → (R13+Rj)
Halfword
STH Ri, @(R14,disp9)
B
50
a
----
Ri → (R14+disp9)
Halfword
STB Ri, @Rj
A
16
a
----
Ri → (Rj)
Byte
STB Ri, @(R13,Rj)
A
12
a
----
Ri → (R13+Rj)
Byte
STB Ri, @(R14,disp8)
B
70
a
----
Ri → (R14+disp8)
Byte
Rs: Special register *
*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
Note:
In the o8 and u4 fields of a Instruction Format, the assembler calculates values and sets them as
shown below:
- disp10/4 --> o8, disp9/2 --> o8, disp8 --> o8 (disp10, disp9, and disp8 have a sign.)
- udisp6/4 --> u4 (udisp6 has no sign.)
■ Register-to-Register Transfer Instructions
Table D-12 Register-to-Register Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
MOV Rj, Ri
A
8B
1
----
Rj → Ri
Transfer between general-purpose
registers
MOV Rs, Ri
A
B7
1
----
Rs → Ri
Rs: Special register *
MOV Ri, Rs
A
B3
1
----
Ri → Rs
Rs: Special register *
MOV PS, Ri
E
17-1
1
----
PS → Ri
MOV Ri, PS
E
07-1
c
CCCC
Ri → PS
*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
583
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Normal Branch (No Delay) Instructions
Table D-13 Normal Branch (No Delay) Instructions
Mnemonic
JMP
@Ri
CALL label12
Type
OP
CYCLE
NZVC
E
97-0
2
----
Ri → PC
Operation
F
D0
2
----
PC+2→ RP ,
PC+2+(label12-PC-2)→PC
CALL @Ri
E
97-1
2
----
PC+2→RP ,Ri→PC
RET
E
97-2
2
----
RP → PC
D
1F
3+3a
----
SSP-=4,PS → (SSP),
SSP-=4,PC+2 → (SSP),
0→ I flag, 0 → S flag,
(TBR+0x3FC-u8x4) → PC
INTE
E
9F-3
3+3a
----
SSP-=4,PS → (SSP),
SSP-=4,PC+2 → (SSP),
0 → S flag,
(TBR+0x3D8) →PC
RETI
E
97-3
2+2a
CCCC
INT
#u8
Return
For emulator
(R15) → PC,R15+=4,
(R15) → PS,R15+=4
label9
D
E0
2
----
PC+2+(label9-PC-2) → PC
BNO label9
D
E1
1
----
No branch
BEQ label9
D
E2
2/1
----
if(Z==1) then
PC+2+(label9-PC-2) → PC
BNE label9
D
E3
2/1
----
if(Z==0) then
PC+2+(label9-PC-2) → PC
BC
label9
D
E4
2/1
----
if(C==1) then
PC+2+(label9-PC-2) → PC
BNC label9
D
E5
2/1
----
if(C==0) then
PC+2+(label9-PC-2) → PC
BN
label9
D
E6
2/1
----
if(N==1) then
PC+2+(label9-PC-2) → PC
BP
label9
D
E7
2/1
----
if(N==0) then
PC+2+(label9-PC-2) → PC
BV
label9
D
E8
2/1
----
if(V==1) then
PC+2+(label9-PC-2) → PC
BNV label9
D
E9
2/1
----
if(V==0) then
PC+2+(label9-PC-2) → PC
BLT
label9
D
EA
2/1
----
if(V xor N==1) then
PC+2+(label9-PC-2) → PC
BGE label9
D
EB
2/1
----
if(V xor N==0) then
PC+2+(label9-PC-2) → PC
BLE
label9
D
EC
2/1
----
if((V xor N) or Z==1) then
PC+2+(label9-PC-2) → PC
BGT label9
D
ED
2/1
----
if((V xor N) or Z==0) then
PC+2+(label9-PC-2) → PC
BLS
label9
D
EE
2/1
----
if(C or Z==1) then
PC+2+(label9-PC-2) → PC
BHI
label9
D
EF
2/1
----
if(C or Z==0) then
PC+2+(label9-PC-2) → PC
BRA
Remarks
Notes:
• "2/1" in CYCLE indicates 2 when branching occurs and 1 when branching does not occur.
• In the rel11 and rel8 fields of a Instruction Format, the assembler calculates values and sets them as shown below:
(label12-PC-2)/2 --> rel11, (label9-PC-2)/2 --> rel8 (label12 and label9 have a sign.)
• To execute the RETI instruction, the Stack flag (S) must be 0.
584
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Delayed Branch Instructions
Table D-14 Delayed Branch Instructions
Type
OP
CYCLE
NZVC
JMP:D @Ri
Mnemonic
E
9F-0
1
----
Operation
Ri → PC
CALL:D label12
F
D8
1
----
PC+4 → RP ,
PC+2+(label12-PC-2) → PC
CALL:D @Ri
E
9F-1
1
----
PC+4 → RP ,Ri → PC
RET:D
E
9F-2
1
----
BRA:D label9
D
F0
1
----
RP→ PC
PC+2+(label9-PC-2) → PC
BNO:D label9
D
F1
1
----
No branch
BEQ:D label9
D
F2
1
----
BNE:D label9
D
F3
1
----
BC:D
label9
D
F4
1
----
BNC:D label9
D
F5
1
----
BN:D
label9
D
F6
1
----
BP:D
label9
D
F7
1
----
BV:D
label9
D
F8
1
----
BNV:D label9
D
F9
1
----
BLT:D
label9
D
FA
1
----
BGE:D label9
D
FB
1
----
BLE:D
label9
D
FC
1
----
BGT:D label9
D
FD
1
----
BLS:D
label9
D
FE
1
----
BHI:D
label9
D
FF
1
----
if(Z==1) then
PC+2+(label9-PC-2) → PC
if(Z==0) then
PC+2+(label9-PC-2) → PC
if(C==1) then
PC+2+(label9-PC-2) → PC
if(C==0) then
PC+2+(label9-PC-2) → PC
if(N==1) then
PC+2+(label9-PC-2) → PC
if(N==0) then
PC+2+(label9-PC-2) → PC
if(V==1) then
PC+2+(label9-PC-2) → PC
if(V==0) then
PC+2+(label9-PC-2) → PC
if(V xor N==1) then
PC+2+(label9-PC-2) → PC
if(V xor N==0) then
PC+2+(label9-PC-2) → PC
if((V xor N) or Z==1) then
PC+2+(label9-PC-2) → PC
if((V xor N) or Z==0) then
PC+2+(label9-PC-2) → PC
if(C or Z==1) then
PC+2+(label9-PC-2) → PC
if(C or Z==0) then
PC+2+(label9-PC-2) → PC
Remarks
Return
Notes:
• In the rel11 and rel8 fields of a Instruction Format, the assembler calculates values and sets them as
shown below:
(label12-PC-2)/2 --> rel11, (label9-PC-2)/2 --> rel8 (label12 and label9 have a sign.)
• A delayed branch always occurs after the next instruction (delay slot) is executed.
• Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions.
Multicycle instructions cannot be placed in the delay slot.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
585
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Other Instructions
Table D-15 Other Instructions
Mnemonic
Type
OP
CYCLE
NOP
E
9F-A
1
----
ANDCCR #u8
D
83
c
CCCC
CCR and u8 → CCR
ORCCR #u8
D
93
c
CCCC
CCR or u8 → CCR
STILM
D
87
1
----
u8 → ILM
ILM immediate set
ADDSP #s10*1
D
A3
1
----
R15 += s10
ADD SP instruction
EXTSB Ri
E
97-8
1
----
Sign extension 8 bits → 32
bits
EXTUB Ri
E
97-9
1
----
Zero extension 8 bits → 32
bits
EXTSH Ri
E
97-A
1
----
Sign extension 16 bits → 32
bits
EXTUH Ri
E
97-B
1
----
Zero extension 16 bits → 32
bits
LDM0 (reglist)
D
8C
----
(R15) → reglist,
R15 increment
Load multi R0 to R7
LDM1 (reglist)
D
8D
----
(R15) → reglist,
R15 increment
Load multi R8 to R15
----
(R15) → reglist,
R15 increment
Load multi R0 to R15
#u8
*LDM (reglist)*2
NZVC
Operation
Remarks
No change
STM0 (reglist)
D
8E
----
R15 decrement,
reglist → (R15)
Store multi R0 to R7
STM1 (reglist)
D
8F
----
R15 decrement,
reglist → (R15)
Store multi R8 to R15
----
R15 decrement,
reglist → (R15)
Store multi R0 to R15
*STM (reglist)*3
ENTER #u10*4
D
0F
1+a
----
R14 → (R15 - 4),
R15 - 4 → R14,
R15 - u10 → R15
Entry processing of a function
LEAVE
E
9F-9
b
----
R14 + 4 → R15,
(R15 - 4) → R14
Exit processing of a function
XCHB @Rj, Ri*5
A
8A
2a
----
Ri → TEMP
(Rj) → Ri
TEMP → (Rj)
For semaphore management
Byte data
*1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign.
*2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In some cases,
both LDM0 and LDM1 are generated.
*3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In some cases,
both STM0 and STM1 are generated.
*4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has no sign.
*5: If this instruction is written in the assembler, the general-purpose registers other than R15 is specified to Ri.
Notes:
• The number of execution cycles for LDM0(reglist) and LDM1(reglist) can be calculated as a × (n-1)+b+1 cycles
if the number of specified registers is n.
• The number of execution cycles for STM0(reglist) and STM1(reglist) can be calculated as a × n+1 cycles
if the number of specified registers is n.
586
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ 20-Bit Normal Branch Macro Instructions
Table D-16 20-Bit Normal Branch Macro Instructions
Mnemonic
Operation
Remarks
*CALL20 label20,Ri
Address of the next instruction → RP,
label20 → PC
Ri: Temporary register (See Reference 1)
*BRA20 label20,Ri
label20 → PC
Ri: Temporary register (See Reference 2)
*BEQ20
label20,Ri
if(Z==1) then label20 → PC
Ri: Temporary register (See Reference 3)
*BNE20
label20,Ri
if(Z==0) then label20 → PC
↑
*BC20
label20,Ri
if(C==1) then label20 → PC
↑
*BNC20 label20,Ri
if(C==0) then label20 → PC
↑
*BN20
label20,Ri
if(N==1) then label20 → PC
↑
*BP20
label20,Ri
if(N==0) then label20 → PC
↑
*BV20
label20,Ri
if(V==1) then label20 → PC
↑
*BNV20 label20,Ri
if(V==0) then label20 → PC
↑
*BLT20
label20,Ri
if(V xor N==1) then label20 → PC
↑
*BGE20
label20,Ri
if(V xor N==0) then label20 → PC
↑
*BLE20
label20,Ri
if((V xor N) or Z==1) then label20 → PC
↑
*BGT20
label20,Ri
if((V xor N) or Z==0) then label20 → PC
↑
*BLS20
label20,Ri
if(C or Z==1) then label20 → PC
↑
*BHI20
label20,Ri
if(C or Z==0) then label20 → PC
↑
Reference 1:
CALL20
1) If label20-PC-2 is between -0x800 and +0x7FE, create an instruction as shown below:
CALL
label12
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:20 #label20,Ri
CALL
@Ri
Reference 2:
BRA20
1) If label20-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
BRA
label9
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:20 #label20,Ri
JMP
@Ri
Reference 3:
Bcc20
1) If label20-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
Bcc
label9
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
Bxcc
false
; xcc is the opposite condition of cc.
LDI:20 #label20,Ri
JMP
@Ri
false:
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
587
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ 20-Bit Delayed Branch Macro Instructions
Table D-17 20-Bit Delayed Branch Macro Instructions
Mnemonic
Operation
Remarks
*CALL20:D label20,Ri
Address of the next instruction +2 → RP,
label20 → PC
Ri: Temporary register (See Reference 1)
*BRA20:D
label20 → PC
Ri: Temporary register (See Reference 2)
*BEQ20:D label20,Ri
if(Z==1) then label20 → PC
Ri: Temporary register (See Reference 3)
*BNE20:D
label20,Ri
if(Z==0) then label20 → PC
↑
*BC20:D
label20,Ri
if(C==1) then label20 → PC
↑
*BNC20:D
label20,Ri
if(C==0) then label20 → PC
↑
*BN20:D
label20,Ri
if(N==1) then label20 → PC
↑
*BP20:D
label20,Ri
if(N==0) then label20 → PC
↑
*BV20:D
label20,Ri
if(V==1) then label20 → PC
↑
*BNV20:D label20,Ri
if(V==0) then label20 → PC
↑
*BLT20:D
label20,Ri
if(V xor N==1) then label20 → PC
↑
*BGE20:D
label20,Ri
if(V xor N==0) then label20 → PC
↑
*BLE20:D
label20,Ri
if((V xor N) or Z==1) then label20 → PC
↑
*BGT20:D label20,Ri
if((V xor N) or Z==0) then label20 → PC
↑
*BLS20:D
label20,Ri
if(C or Z==1) then label20 → PC
↑
*BHI20:D
label20,Ri
if(C or Z==0) then label20 → PC
↑
label20,Ri
Reference 1:
CALL20:D
1) If label20-PC-2 is between -0x800 and +0x7FE, create an instruction as shown below:
CALL:D label12
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:20 #label20,Ri
CALL:D @Ri
Reference 2:
BRA20:D
1) If label20-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
BRA :D label9
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:20 #label20,Ri
JMP:D @Ri
Reference 3:
Bcc20:D
1) If label20-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
Bcc:D
label9
2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
Bxcc
false
; xcc is the opposite condition of cc.
LDI:20 #label20,Ri
JMP:D @Ri
false:
588
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CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ 32-Bit Normal Branch Macro Instructions
Table D-18 32-Bit Normal Branch Macro Instructions
Mnemonic
Operation
Remarks
*CALL32 label32,Ri
Address of the next instruction → RP,
label32 → PC
Ri: Temporary register (See Reference 1)
*BRA32 label32,Ri
label32 → PC
Ri: Temporary register (See Reference 2)
*BEQ32
label32,Ri
if(Z==1) then label32 → PC
Ri: Temporary register (See Reference 3)
*BNE32
label32,Ri
if(Z==0) then label32 → PC
↑
*BC32
label32,Ri
if(C==1) then label32 → PC
↑
*BNC32 label32,Ri
if(C==0) then label32 → PC
↑
*BN32
label32,Ri
if(N==1) then label32 → PC
↑
*BP32
label32,Ri
if(N==0) then label32 → PC
↑
*BV32
label32,Ri
if(V==1) then label32 → PC
↑
*BNV32 label32,Ri
if(V==0) then label32 → PC
↑
*BLT32
label32,Ri
if(V xor N==1) then label32 → PC
↑
*BGE32
label32,Ri
if(V xor N==0) then label32 → PC
↑
*BLE32
label32,Ri
if((V xor N) or Z==1) then label32 → PC
↑
*BGT32
label32,Ri
if((V xor N) or Z==0) then label32 → PC
↑
*BLS32
label32,Ri
if(C or Z==1) then label32 → PC
↑
*BHI32
label32,Ri
if(C or Z==0) then label32 → PC
↑
Reference 1:
CALL32
1) If label32-PC-2 is between -0x800 and +0x7FE, create an instruction as shown below:
CALL
label12
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:
LDI:32 #label32,Ri
CALL
@Ri
Reference 2:
BRA32
1) If label32-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
BRA
label9
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:
LDI:32 #label32,Ri
JMP
@Ri
Reference 3:
Bcc32
1) If label32-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
Bcc
label9
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:
Bxcc
false
; xcc is the opposite condition of cc.
LDI:32 #label32,Ri
JMP
@Ri
false:
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
589
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ 32-Bit Delayed Branch Macro Instructions
Table D-19 32-Bit Delayed Branch Macro Instructions
Mnemonic
Operation
Remarks
*CALL32:D label32,Ri
Address of the next instruction +2 → RP,
label32 → PC
Ri: Temporary register (See Reference 1)
*BRA32:D
label32,Ri
label32 → PC
Ri: Temporary register (See Reference 2)
*BEQ32:D
label32,Ri
if(Z==1) then label32 → PC
Ri: Temporary register (See Reference 3)
*BNE32:D
label32,Ri
if(Z==0) then label32 → PC
↑
*BC32:D
label32,Ri
if(C==1) then label32 → PC
↑
*BNC32:D
label32,Ri
if(C==0) then label32 → PC
↑
*BN32:D
label32,Ri
if(N==1) then label32 → PC
↑
*BP32:D
label32,Ri
if(N==0) then label32 → PC
↑
*BV32:D
label32,Ri
if(V==1) then label32 → PC
↑
*BNV32:D label32,Ri
if(V==0) then label32 → PC
↑
*BLT32:D
label32,Ri
if(V xor N==1) then label32 → PC
↑
*BGE32:D
label32,Ri
if(V xor N==0) then label32 → PC
↑
*BLE32:D
label32,Ri
if((V xor N) or Z==1) then label32 → PC
↑
*BGT32:D label32,Ri
if((V xor N) or Z==0) then label32 → PC
↑
*BLS32:D
label32,Ri
if(C or Z==1) then label32 → PC
↑
*BHI32:D
label32,Ri
if(C or Z==0) then label32 → PC
↑
Reference 1:
CALL32:D
1) If label32-PC-2 is between -0x800 and +0x7FE, create an instruction as shown below:
CALL:D label12
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:32 #label32,Ri
CALL:D @Ri
Reference 2:
BRA32:D
1) If label32-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
BRA:D label9
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
LDI:32 #label32,Ri
JMP:D @Ri
Reference 3:
Bcc32:D
1) If label32-PC-2 is between -0x100 and +0xFE, create an instruction as shown below:
Bcc:D
label9
2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown
below:
Bxcc
false
; xcc is the opposite condition of cc.
LDI:32 #label32,Ri
JMP:D @Ri
false:
590
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Direct Addressing Instructions
Table D-20 Direct Addressing Instructions
Mnemonic
Type
OP
CYCLE
NZVC
DMOV @dir10, R13
D
08
b
----
(dir10) → R13
Word
DMOV R13,
D
18
a
----
R13 → (dir10)
Word
DMOV @dir10, @R13+
D
0C
2a
----
(dir10) → (R13),R13+=4
Word
DMOV @R13+, @dir10
D
1C
2a
----
(R13) → (dir10),R13+=4
Word
DMOV @dir10, @-R15
D
0B
2a
----
R15-=4,(R15) → (dir10)
Word
DMOV @R15+, @dir10
D
1B
2a
----
(R15) → (dir10),R15+=4
Word
DMOVH @dir9, R13
D
09
b
----
(dir9) → R13
Halfword
DMOVH R13,
D
19
a
----
R13 → (dir9)
Halfword
DMOVH @dir9, @R13+
D
0D
2a
----
(dir9) → (R13),R13+=2
Halfword
DMOVH @R13+, @dir9
D
1D
2a
----
(R13) → (dir9),R13+=2
Halfword
DMOVB @dir8, R13
D
0A
b
----
(dir8) → R13
Byte
DMOVB R13,
D
1A
a
----
R13 → (dir8)
Byte
DMOVB @dir8, @R13+
D
0E
2a
----
(dir8) → (R13),R13++
Byte
DMOVB @R13+, @dir8
D
1E
2a
----
(R13) → (dir8),R13++
Byte
@dir10
@dir9
@dir8
Operation
Remarks
Note:
In the dir8, dir9, and dir10 fields of a Instruction Format, values and sets them as shown below:
dir8 --> dir, dir9/2 --> dir, dir10/4 --> dir (dir8, dir9, and dir10 have no sign.)
■ Resource Instructions
Table D-21 Resource Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
LDRES @Ri+, #u4
C
BC
a
----
(Ri) → u4 resource
Ri+=4
u4: Channel number
STRES #u4, @Ri+
C
BD
a
----
u4 resource → (Ri)
Ri+=4
u4: Channel number
Note:
This series cannot use these instructions because it has no resource with the channel number used for
the resource instructions.
CM71-10139-5E
FUJITSU MICROELECTRONICS LIMITED
591
APPENDIX
APPENDIX D INSTRUCTION LISTS
MB91210 Series
■ Coprocessor Control Instructions
Table D-22 Coprocessor Control Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
COPOP #u4, #u8, CRj, CRi
E
9F-C
2+a
----
Operation instruction
COPLD
#u4, #u8, Rj, CRi
E
9F-D
1+2a
----
Rj → CRi
COPST
#u4, #u8, CRj, Ri
E
9F-E
1+2a
----
CRj → Ri
COPSV #u4, #u8, CRj, Ri
E
9F-F
1+2a
----
CRj → Ri
Remarks
No error trap
Notes:
• {CRi | CRj}:= CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 |
CR13 |CR14 | CR15
u4:= Channel specified
u8:= Command specified
• Since this series has no coprocessor, these instructions cannot be used.
592
FUJITSU MICROELECTRONICS LIMITED
CM71-10139-5E
INDEX
INDEX
Numerics
0 Detection
0 Detection...................................................... 191
0 Detection Data Register (BSD0) ..................... 189
0 Detection Data Register
0 Detection Data Register (BSD0) ..................... 189
1 Detection
1 Detection...................................................... 191
1 Detection Data Register (BSD1) ..................... 189
1 Detection Data Register
1 Detection Data Register (BSD1) ..................... 189
16-bit
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions......................................... 581
16-Bit Free-Run Timer
Block Diagram of 16-Bit Free-Run Timer .......... 404
Clear Timing of 16-Bit Free-Run Timer ............. 411
Count Timing of 16-Bit Free-Run Timer ............ 411
Explanation of Operation of 16-Bit Free-Run
Timer................................................. 410
Notes on Using 16-Bit Free-Run Timer .............. 412
Overview of 16-Bit Free-Run Timer .................. 404
Register List of 16-Bit Free-Run Timer .............. 405
16-bit Input Capture
Input Timing of 16-bit Input Capture ................. 420
Operations of the 16-bit Input Capture ............... 419
16-bit Output Compare
Operation of the 16-bit Output Compare ............ 428
Timing of 16-bit Output Compare
Operation ........................................... 429
16-Bit Reload Register
Bit Configuration of 16-Bit Reload Register
(TMRLR)........................................... 398
16-Bit Reload Timer
Block Diagram of 16-Bit Reload Timer.............. 392
Overview of 16-Bit Reload Timer...................... 392
Register List of 16-Bit Reload Timer ................. 393
16-Bit Timer Register
Bit Configuration of 16-Bit Timer Register
(TMR) ............................................... 397
20-Bit Delayed Branch Macro Instructions
20-Bit Delayed Branch Macro Instructions ......... 588
20-Bit Normal Branch Macro Instructions
20-Bit Normal Branch Macro Instructions .......... 587
32-bit
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions......................................... 581
32-bit ←→ 16-bit Bus Converter
32-bit ←→ 16-bit Bus Converter......................... 31
32-Bit Delayed Branch Macro Instructions
32-Bit Delayed Branch Macro Instructions..........590
32-Bit Normal Branch Macro Instructions
32-Bit Normal Branch Macro Instructions...........589
8-bit PPG
Block Diagram of the 8-bit PPG ch.0 and
ch.2 ....................................................433
Block Diagram of the 8-bit PPG ch.1..................434
Block Diagram of the 8-bit PPG ch.3..................435
593
INDEX
A
A/D
A/D Control Status Register 0 (ADCS0)............. 478
A/D Control Status Register 1 (ADCS1)............. 475
A/D Conversion Data ....................................... 486
A/D Enable Register (ADER)............................ 474
Block Diagram of A/D Converter ...................... 471
Features of A/D Converter ................................ 470
Overview of A/D Converter Registers ................ 472
A/D Control Status Register
A/D Control Status Register 0 (ADCS0)............. 478
A/D Control Status Register 1 (ADCS1)............. 475
A/D Conversion
A/D Conversion Data ....................................... 486
A/D Converter
A/D Converter (32 Channels) ................................ 3
Block Diagram of A/D Converter ...................... 471
Features of A/D Converter ................................ 470
Overview of A/D Converter Registers ................ 472
A/D Converter Registers
Overview of A/D Converter Registers ................ 472
About Connection
About Connection with Input Capture/Output
Compare............................................. 412
Acceptance
Acceptance and Transfer of Transfer
Request .............................................. 230
Acceptance Filter
Acceptance Filter of Reception Message ............ 302
Access
Access Address ................................................ 226
Access Mode ..................................................... 66
Flash Memory Access Modes ............................ 499
LIN-UART Pin Direct Access ........................... 378
Accuracy
Accuracy of Calibration .................................... 468
Activation
Activation from Pausing State ........................... 229
Transfer Activation........................................... 229
AD
AD Bit in Serial Control Register (SCR) ............ 389
ADCR
Data Register (ADCR1,ADCR0) ....................... 481
ADCS
A/D Control Status Register 0 (ADCS0)............. 478
A/D Control Status Register 1 (ADCS1)............. 475
Additional
Additional Notes .............................................. 537
Address Register
Address Register Specification .......................... 225
Addressing
Addressing ...................................................... 513
Direct Addressing............................................... 34
Direct Addressing Area....................................... 28
594
Direct Addressing Instructions .......................... 591
Addressing Mode
Addressing Mode Symbols ............................... 573
Add-Subtract Instructions
Add-Subtract Instructions ................................. 577
ADER
A/D Enable Register (ADER) ........................... 474
ADSCH
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH)................... 484
AF200
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
All the Channels’ Operation
All the Channels’ Operation Disabled ................ 233
All the Channels’ Operation Enabled ................. 229
Arithmetic Operation
Arithmetic Operation.......................................... 33
Arithmetic Operation and Bit Manipulation .......... 34
Automatic Algorithm
Automatic Algorithm Execution Status .............. 500
Command Sequences for Automatic
Algorithms ......................................... 502
Overview of Flash Memory Automatic
Algorithms ......................................... 501
Automatic Restart
Automatic Restart ............................................ 365
B
Basic Block Diagram
Basic Block Diagram of Ports ........................... 134
Basic Clock Division Setting Register
DIVR0: Basic Clock Division Setting
Register 0............................................. 92
DIVR1: Basic Clock Division Setting
Register 1............................................. 95
Basic Configuration
Basic Configuration ................................. 526, 538
Basic Mode
Basic Mode ..................................................... 315
Basic Programming Model
Basic Programming Model ................................. 35
Baud Rate
Baud Rate Calculation...................................... 361
Baud Rate/Reload Counter Register................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
Examples of Baud Rate Settings for Each Machine
Clock Frequency................................. 362
LIN-UART Baud Rate Selection ....................... 359
Baud Rate/Reload Counter Register
Baud Rate/Reload Counter Register................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
INDEX
BGR
Baud Rate/Reload Counter Register (BGR) ........ 349
Bidirectional Communication
Bidirectional Communication Function .............. 379
Bit Configuration
Bit Configuration of 16-Bit Reload Register
(TMRLR)........................................... 398
Bit Configuration of 16-Bit Timer Register
(TMR) ............................................... 397
Bit Configuration of Control Status Register
(TMCSR) ........................................... 394
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR)...................... 173
Bit Configuration of External Interrupt Source
Register (EIRR) .................................. 172
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ................................. 495
Bit Configuration of Flash Memory Wait Register
(FLWC) ............................................. 497
Bit Configuration of Hold Request Cancel Request
Register (HRCL)................................. 159
Bit Configuration of ICR .................................... 54
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 158
Bit Configuration of Interrupt Enable Register
(ENIR)............................................... 171
Bit Configuration of the Compare Register
(OCCP).............................................. 424
Bit Configuration of the Control Register
(OCS) ................................................ 425
Bit Configuration of the Input Capture Register
(ICS).................................................. 417
Bit Configuration of the Input Capture Register
(IPCP)................................................ 416
Bit Function
Bit Function of DMACA0 to DMACA4............. 200
Bit Function of DMACB0 to DMACB4 ............. 205
Bit Function of DMACR .................................. 215
Bit Function of DMASA0 to DMASA4/DMADA0 to
DMADA4 .......................................... 212
Bit Manipulation Instructions
Bit Manipulation Instructions ............................ 579
Bit Ordering
Bit Ordering ...................................................... 45
Bit Search Module
Bit Search Module (Used by REALOS) ................. 2
Block Diagram of Bit Search Module ................ 188
Overview of Bit Search Module ........................ 186
Register List of Bit Search Module .................... 187
Block
Step/Block Two-Cycle Transfer ........................ 223
Block Diagram
Basic Block Diagram of Ports ........................... 134
Block Diagram ................................................ 318
Block Diagram of 16-Bit Free-Run Timer .......... 404
Block Diagram of 16-Bit Reload Timer ..............392
Block Diagram of A/D Converter.......................471
Block Diagram of Bit Search Module .................188
Block Diagram of CAN.....................................245
Block Diagram of Clock Generation Control
Block....................................................78
Block Diagram of Delay Interrupt Module ..........183
Block Diagram of DMAC .................................198
Block Diagram of External Interrupt Control
Unit....................................................169
Block Diagram of External Reset Pin .................128
Block Diagram of Input Capture ........................414
Block Diagram of LIN-UART ...................325, 326
Block Diagram of MB91210 Series ........................5
Block Diagram of Pseudo Sub Clock ..................120
Block Diagram of Real Time Clock....................454
Block Diagram of the 8-bit PPG ch.0 and
ch.2 ....................................................433
Block Diagram of the 8-bit PPG ch.1..................434
Block Diagram of the 8-bit PPG ch.3..................435
Block Diagram of the Main Oscillation Stabilization
Wait Timer..........................................114
Block Diagram of the Output Compare Unit........422
Flash Memory Block Diagram ...........................491
Interrupt Controller Block Diagram ....................156
Block Size
Block Size .......................................................224
Block Transfer
Block Transfer .................................................223
Operation Flow of Block Transfer ......................239
Branch
Delayed Branch Instructions ..............................585
Normal Branch (No Delay) Instructions..............584
Branching
Branching ..........................................................33
BSD
0 Detection Data Register (BSD0)......................189
1 Detection Data Register (BSD1)......................189
BSDC
Change Point Detection Data Register
(BSDC) ..............................................190
BSRR
Detection Result Register (BSRR)......................190
Built-in Peripheral Request
Built-in Peripheral Request................................221
Burst
Burst Two-Cycle Transfer .................................222
Burst Transfer
Operation Flow of Burst Transfer.......................240
Bus Converter
32-bit ←→ 16-bit Bus Converter .........................31
Harvard ←→ Princeton Bus Converter .................32
Bus Idle
Bus Idle Function .............................................389
Bus Idle Interrupts ............................................353
595
INDEX
Bus Mode
Bus Mode .......................................................... 66
Bus Mode 0 (Single-chip Mode) .......................... 67
Bus Mode 1
(Internal ROM/External Bus Mode) ........ 67
Bus Mode 2
(External ROM/External Bus Mode) ....... 67
Byte Ordering
Byte Ordering .................................................... 45
C
Calculation
Baud Rate Calculation ...................................... 361
Calibration Unit Control Register
Calibration Unit Control Register (CUCR) ......... 463
CAN
Block Diagram of CAN .................................... 245
CAN Clock Prescaler Setting............................. 320
Features of CAN .............................................. 244
Registers of CAN ............................................. 253
CAN Controller
CAN Controller (3 Channels) ................................ 3
CAN_TX
Software Control of Pin CAN_TX ..................... 316
Caution
Caution for Operation during PLL Clock
Mode ................................................... 25
CCR
CCR (Condition Code Register)........................... 38
Change Point Detection
Change Point Detection .................................... 192
Change Point Detection Data Register
(BSDC) .............................................. 190
Change Point Detection Data Register
Change Point Detection Data Register
(BSDC) .............................................. 190
Changing
Changing Operation Settings ............................. 388
Wait Time after Changing PLL Multiplication
Rate ..................................................... 73
Channel
All the Channels’ Operation Disabled ................ 233
All the Channels’ Operation Enabled ................. 229
Channel Group................................................. 238
Priority Among Channels.................................. 237
Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the
Channels Simultaneously) .................... 232
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH) ................... 484
Chip Erase
Chip Erase ....................................................... 503
Erasing All Data from Flash Memory
(Chip Erase)........................................ 515
596
Clear
Clear Timing of 16-Bit Free-Run Timer ............. 411
CTBR: Time-base Counter Clear Register ............ 87
Timing of Occurrence for Interrupt Clear
by DMA............................................. 231
CLKB
CPU Clock (CLKB) ........................................... 75
CLKP
Peripheral Clock (CLKP).................................... 75
CLKR
CLKR: Clock Source Control Register................. 88
Clock
Block Diagram of Clock Generation Control
Block ................................................... 78
Block Diagram of Pseudo Sub Clock ................. 120
Block Diagram of Real Time Clock ................... 454
CAN Clock Prescaler Setting ............................ 320
Caution for Operation during PLL Clock
Mode ................................................... 25
CLKR: Clock Source Control Register................. 88
Clock.............................................................. 461
Clock Calibration Unit of Real Time Clock ........ 460
Clock Calibration Unit Registers List of Real Time
Clock ................................................. 462
Clock Disable Register ..................................... 459
Clock Inversion and Start/Stop Bits
in Mode 2........................................... 371
Clock Prescaler Register ................................... 252
Clock Supply................................................... 372
Count Clock Selection...................................... 447
CPU Clock (CLKB) ........................................... 75
DIVR0: Basic Clock Division Setting
Register 0............................................. 92
DIVR1: Basic Clock Division Setting
Register 1............................................. 95
Examples of Baud Rate Settings for Each Machine
Clock Frequency................................. 362
Generating Internal Operating Clock.................... 70
Internal Clock Operation .................................. 399
List of Real Time Clock Registers ..................... 452
Note on Using an External Clock......................... 25
Operation of Clock Supply Function .................. 118
Oscillation Clock Frequency ............................. 537
Peripheral Clock (CLKP).................................... 75
Procedure of Clock Switching ........................... 319
Selecting the Source Clock ................................. 70
Using External Clock ....................................... 363
Wait Time after Switching from the Sub Clock to the
Main Clock .......................................... 74
Clock Calibration Unit Registers
Clock Calibration Unit Registers List of Real Time
Clock ................................................. 462
Clock Disable Register
Clock Disable Register ..................................... 459
INDEX
Clock Frequency
Examples of Baud Rate Settings for Each Machine
Clock Frequency ................................. 362
Oscillation Clock Frequency ............................. 537
Clock Generation
Block Diagram of Clock Generation Control
Block ................................................... 78
Clock Prescaler Register
Clock Prescaler Register ................................... 252
Clock Selection
Count Clock Selection ...................................... 447
Clock Source Control Register
CLKR: Clock Source Control Register................. 88
Clock Supply
Clock Supply................................................... 372
Operation of Clock Supply Function .................. 118
Combination
Combination of Silent Mode and Loop Back
Mode ................................................. 314
PPG Combinations........................................... 449
Command
Command Sequences for Automatic
Algorithms ......................................... 502
Reset Command............................................... 503
Communication
Bidirectional Communication Function .............. 379
Communication ............................................... 373
Communication Mode Setting ........................... 388
Communication Procedure ................................ 382
Extended Communication Control Register
(ECCR).............................................. 346
LIN Master/Slave Communication Function ....... 384
Master/Slave Communication Function.............. 381
Compare
About Connection with Input Capture/Output
Compare ............................................ 412
Bit Configuration of the Compare Register
(OCCP).............................................. 424
Block Diagram of the Output Compare Unit ....... 422
Features of the Output Compare Unit ................. 422
Functions of the Compare Register (OCCP) ....... 424
Operation of the 16-bit Output Compare ............ 428
Registers of the Output Compare Unit................ 423
Timing of 16-bit Output Compare
Operation ........................................... 429
Compare Instructions
Compare Instructions ....................................... 577
Compare Register
Bit Configuration of the Compare Register
(OCCP).............................................. 424
Functions of the Compare Register (OCCP) ....... 424
Comparison
Function Comparison ........................................... 4
Condition Code Register
CCR (Condition Code Register) .......................... 38
Configuration
Basic Configuration ..................................526, 538
Bit Configuration of 16-Bit Reload Register
(TMRLR) ...........................................398
Bit Configuration of 16-Bit Timer Register
(TMR) ................................................397
Bit Configuration of Control Status Register
(TMCSR)............................................394
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ......................173
Bit Configuration of External Interrupt Source
Register (EIRR)...................................172
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ..................................495
Bit Configuration of Flash Memory Wait Register
(FLWC)..............................................497
Bit Configuration of Hold Request Cancel Request
Register (HRCL) .................................159
Bit Configuration of ICR .....................................54
Bit Configuration of Interrupt Control Register
(ICR)..................................................158
Bit Configuration of Interrupt Enable Register
(ENIR) ...............................................171
Bit Configuration of the Compare Register
(OCCP) ..............................................424
Bit Configuration of the Control Register
(OCS).................................................425
Bit Configuration of the Input Capture Register
(ICS) ..................................................417
Bit Configuration of the Input Capture Register
(IPCP) ................................................416
Configuration of FIFO Buffer ............................306
Configuration of Message Object .......................280
Hardware Configuration of DMAC ....................196
Hardware Configuration of the Interrupt
Controller ...........................................154
Register Configuration .....255, 258, 261, 262, 263,
265, 267, 269, 272, 276, 277, 278, 279,
287, 289, 291, 293, 295
Sector Configuration of Flash Memory .................11
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation)........................................537
Connection
About Connection with Input Capture/Output
Compare .............................................412
Connection Example for On-board Reprogramming
Using a Programmer ............................539
Inter-CPU Connection...............................380, 381
Inter-CPU Connection Method...........................367
LIN Device Connection.....................................384
Serial Programming Connection Examples .........528
Continuous Mode
Continuous Mode .............................................486
597
INDEX
Control
Control of Pulse Pin Output............................... 448
Control Register
Bit Configuration of the Control Register
(OCS) ................................................ 425
Overall Control Register ................................... 254
Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the
Channels Simultaneously) .................... 232
Control Status Register
Bit Configuration of Control Status Register
(TMCSR) ........................................... 394
Conversion
A/D Conversion Data ....................................... 486
Conversion Time Setting Register (ADCT)......... 482
Conversion Time Setting Register
Conversion Time Setting Register (ADCT)......... 482
Coprocessor Absent Trap
Coprocessor Absent Trap .................................... 65
Coprocessor Control Instructions
Coprocessor Control Instructions ....................... 592
Coprocessor Error Trap
Coprocessor Error Trap....................................... 65
Count Clock
Count Clock Selection ...................................... 447
Count Timing
Count Timing of 16-Bit Free-Run Timer ............ 411
Counter
Baud Rate/Reload Counter Register ................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
CTBR: Time-base Counter Clear Register ............ 87
Operating Status of Counter .............................. 402
Other Interval Timer/Counter ................................ 3
PC (Program Counter) ........................................ 42
TBCR: Time-base Counter Control Register ......... 85
Time-base Counter ........................................... 100
Counting Example
Counting Example............................................ 363
CPU
CPU.................................................................. 31
CPU Clock (CLKB) ........................................... 75
Features of the FR CPU ........................................ 2
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
FR-CPU ROM Mode
(Read-only in 32/16/8 Bits) .................. 499
Inter-CPU Connection .............................. 380, 381
Inter-CPU Connection Method .......................... 367
CPU State
Pin States in Each CPU State............................. 566
Crystal Oscillation Circuit
Crystal Oscillation Circuit................................... 24
CTBR
CTBR: Time-base Counter Clear Register ............ 87
598
CUCR
Calibration Unit Control Register (CUCR) ......... 463
CUTD
Sub Timer Data Register (CUTD) ..................... 465
CUTR
Main Timer Data Register (CUTR).................... 467
D
Data Direction Registers
Data Direction Registers (DDRs)....................... 137
Data Format
Transfer Data Format ............................... 368, 371
Data Frame
Data Frame Reception ...................................... 302
Data Polling Flag
Restrictions on Data Polling Flag (DQ7) ............ 516
Data Register
Data Register (ADCR1,ADCR0) ....................... 481
Reception/Transmission Data Register
(RDR/TDR) ....................................... 341
Data Transmission/Reception
Data Transmission/Reception
with Message RAM ............................ 297
Data Write
Program (Data Write)....................................... 503
DDRs
Data Direction Registers (DDRs)....................... 137
Delay
Block Diagram of Delay Interrupt Module ......... 183
Delay Interrupt Module Register (DICR) ........... 184
Operation with a Delay Slot ................................ 48
Operation without a Delay Slot ........................... 50
Overview of Delay Interrupt Module ................. 182
Register List of Delay Interrupt Module ............. 183
Restrictions on the Operation
with a Delay Slot .................................. 49
Delay Interrupt Module Register
Delay Interrupt Module Register (DICR) ........... 184
Delayed Branch
20-Bit Delayed Branch Macro Instructions ......... 588
32-Bit Delayed Branch Macro Instructions ......... 590
Delayed Branch Instructions
Delayed Branch Instructions ............................. 585
Description ........................................................... 520
Details
Details of Interrupt Controller Registers ............. 157
Details of Registers of External Interrupt Control
Unit ................................................... 170
Detection Result Register
Detection Result Register (BSRR) ..................... 190
Determining the Priority
Determining the Priority ................................... 160
INDEX
Device
Device States................................................... 105
LIN Device Connection .................................... 384
LIN-UART as Master Device............................ 385
LIN-UART as Slave Device.............................. 386
Operational States of Device ............................. 106
Overview of Device State Control ..................... 104
DICR
Delay Interrupt Module Register (DICR)............ 184
DLYI Bit of DICR ........................................... 185
Direct Access
LIN-UART Pin Direct Access ........................... 378
Direct Addressing
Direct Addressing .............................................. 34
Direct Addressing Area ...................................... 28
Direct Addressing Instructions
Direct Addressing Instructions .......................... 591
Division
DIVR0: Basic Clock Division Setting
Register 0 ............................................. 92
DIVR1: Basic Clock Division Setting
Register 1 ............................................. 95
Initializing the Division Ratio Setting .................. 77
Setting Division Ratio ........................................ 77
DIVR
DIVR0: Basic Clock Division Setting
Register 0 ............................................. 92
DIVR1: Basic Clock Division Setting
Register 1 ............................................. 95
DLYI
DLYI Bit of DICR ........................................... 185
DMA
DMA Controller .................................................. 2
DMA Suppression............................................ 228
DMA Transfer and Interrupt ............................. 228
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Notes on Using DMA Transfer.......................... 389
Timing of Occurrence for Interrupt Clear
by DMA............................................. 231
DMA Transfer
DMA Transfer and Interrupt ............................. 228
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Notes on Using DMA Transfer.......................... 389
DMAC
Block Diagram of DMAC ................................. 198
Hardware Configuration of DMAC.................... 196
Interrupt That can Output the DMAC Interrupt
Control............................................... 235
Overview of DMAC......................................... 218
Overview of the DMAC Register....................... 197
Primary Functions of DMAC ............................ 196
Primary Operations of DMAC........................... 219
DMACA
Bit Function of DMACA0 to DMACA4 .............200
DMACB
Bit Function of DMACB0 to DMACB4..............205
DMACR
Bit Function of DMACR ...................................215
DMADA
Bit Function of DMASA0 to DMASA4/DMADA0 to
DMADA4...........................................212
DMASA
Bit Function of DMASA0 to DMASA4/DMADA0 to
DMADA4...........................................212
DQ7
Restrictions on Data Polling Flag (DQ7) .............516
E
ECCR
Extended Communication Control Register
(ECCR) ..............................................346
EIRR
Bit Configuration of External Interrupt Source
Register (EIRR)...................................172
EISSR
External Interrupt Input Pin Select Register
(EISSR) ..............................................174
EIT
EIT Interrupt Levels............................................52
EIT Sources .......................................................51
EIT Vector Table................................................56
Features of EIT...................................................51
Priority Levels for Accepting EIT Sources ............60
Returning from EIT ............................................51
ELVR
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ......................173
Enabling PLL Operation
Enabling PLL Operation......................................71
ENIR
Bit Configuration of Interrupt Enable Register
(ENIR) ...............................................171
Erase
Erase Suspend ..................................................505
Erasing
Erasing All Data from Flash Memory
(Chip Erase) ........................................515
Overview of Programming and Erasing Flash
Memory..............................................511
Sector Erasing Procedure...................................516
Erasing All Data
Erasing all Data from Flash Memory
(Chip Erase) ........................................515
Error
Coprocessor Error Trap .......................................65
Error Detection.........................................369, 373
599
INDEX
Occurrence of Address Error ............................. 234
ESCR
Extended Status/Control Register (ESCR) .......... 343
Example
Connection Example for On-board Reprogramming
Using a Programmer ............................ 539
Counting Example............................................ 363
Example of Using the Function to Generate a Request
to Cancel a Hold Request (HRCR) ........ 165
Examples of Baud Rate Settings for Each Machine
Clock Frequency ................................. 362
Serial Programming Connection Examples ......... 528
Exception
Operation of Undefined Instruction
Exception ............................................. 64
Execution Status
Automatic Algorithm Execution Status............... 500
Explanation
Explanation of Each Block ................................ 327
Explanation of Operation of 16-Bit Free-Run
Timer ................................................. 410
Explanation of the Main Oscillation Stabilization Wait
Timer Register .................................... 115
Extended Communication Control Register
Extended Communication Control Register
(ECCR) .............................................. 346
Extended Status/Control Register
Extended Status/Control Register (ESCR) .......... 343
External Bus Mode
Bus Mode 1
(Internal ROM/External Bus Mode) ........ 67
Bus Mode 2
(External ROM/External Bus Mode) ....... 67
External Clock
Note on Using an External Clock ......................... 25
Using External Clock........................................ 363
External Interrupt
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ...................... 173
Bit Configuration of External Interrupt Source
Register (EIRR) .................................. 172
Block Diagram of External Interrupt Control
Unit ................................................... 169
Details of Registers of External Interrupt Control
Unit ................................................... 170
External Interrupt Input Pin Select Register
(EISSR).............................................. 174
External Interrupt Request Level........................ 177
External Interrupts (16 Channels)........................... 3
List of Registers of External Interrupt Control
Unit ................................................... 168
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Operating Procedure for an External
Interrupt ............................................. 176
600
Operations of an External Interrupt .................... 176
Return Via the External Interrupt
in STOP Mode.................................... 125
External Interrupt Control
Block Diagram of External Interrupt Control
Unit ................................................... 169
Details of Registers of External Interrupt Control
Unit ................................................... 170
List of Registers of External Interrupt Control
Unit ................................................... 168
External Interrupt Input Pin Select Register
External Interrupt Input Pin Select Register
(EISSR) ............................................. 174
External Interrupt Request Level Setting Register
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR)...................... 173
External Interrupt Source Register
Bit Configuration of External Interrupt Source
Register (EIRR) .................................. 172
External Pin Reset Timing
External Pin Reset Timing ................................ 128
External Reset
Block Diagram of External Reset Pin................. 128
F
Features
Features of A/D Converter ................................ 470
Features of CAN .............................................. 244
Features of EIT .................................................. 51
Features of Internal Architecture ......................... 29
Features of the FR CPU ........................................ 2
Features of the Output Compare Unit................. 422
Other Features ..................................................... 4
Fetch
Mode Fetch ..................................................... 129
FIFO
Configuration of FIFO Buffer ........................... 306
Message Reception by FIFO Buffer ................... 306
Read from FIFO Buffer .................................... 307
Flag
Hardware Sequence Flag .................................. 506
I Flag ................................................................ 53
LIN-Synch-Break Detection Interrupt
and Flag ............................................. 376
Reception Interrupt Generation and Flag Set
Timing............................................... 355
Transmission Interrupt Generation and Flag Set
Timing............................................... 357
Flash
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ................................. 495
Bit Configuration of Flash Memory Wait Register
(FLWC) ............................................. 497
INDEX
Erasing All Data from Flash Memory
(Chip Erase) ....................................... 515
Flash Memory Access Modes............................ 499
Flash Memory Block Diagram .......................... 491
Flash Memory Programming Procedure ............. 513
Memory Map of Flash Memory......................... 492
Notes on Flash Memory Programming ............... 523
Overview of Flash Memory .............................. 490
Overview of Flash Memory Automatic
Algorithms ......................................... 501
Overview of Flash Memory Registers ................ 494
Overview of Programming and Erasing Flash
Memory ............................................. 511
Programming Data into Flash Memory............... 513
Resuming Sector Erasure in Flash Memory ........ 519
Sector Address Table of Flash Memory.............. 493
Suspending Sector Erasure in Flash Memory ...... 518
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
Writing to Flash ................................................. 25
Flash Memory
Placing the Flash Memory in the Reset
State .................................................. 512
Flash Memory Control/Status Register
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ................................. 495
Flash Memory Wait Register
Bit Configuration of Flash Memory Wait Register
(FLWC) ............................................. 497
Flash Microcontroller
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
Flash Microcontroller Programmer
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
Flow
Operation Flow of Block Transfer ..................... 239
Operation Flow of Burst Transfer ...................... 240
Format
Transfer Data Format ............................... 368, 371
FR
Features of the FR CPU ........................................ 2
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
FR-CPU ROM Mode
(Read-only in 32/16/8 Bits) .................. 499
FR Family Instruction Lists
FR Family Instruction Lists............................... 576
Free-Run Timer
Block Diagram of 16-Bit Free-Run Timer ...........404
Clear Timing of 16-Bit Free-Run Timer..............411
Count Timing of 16-Bit Free-Run Timer.............411
Explanation of Operation of 16-Bit Free-Run
Timer .................................................410
Notes on Using 16-Bit Free-Run Timer ..............412
Overview of 16-Bit Free-Run Timer...................404
Register List of 16-Bit Free-Run Timer ..............405
Function
Bidirectional Communication Function...............379
Bit Function of DMACA0 to DMACA4 .............200
Bit Function of DMACB0 to DMACB4..............205
Bit Function of DMACR ...................................215
Bit Function of DMASA0 to DMASA4/DMADA0 to
DMADA4...........................................212
Bus Idle Function .............................................389
Example of Using the Function to Generate a Request
to Cancel a Hold Request (HRCR) ........165
Function Comparison ............................................4
Function of Message Object ..............................280
Function Part....................................................382
Functions of the Compare Register (OCCP) ........424
LIN Master/Slave Communication Function .......384
List of Pin Functions ...........................................12
Main Functions of the Interrupt Controller ..........154
Master/Slave Communication Function ..............381
Operation of Clock Supply Function...................118
Operation of Interval Timer Function .................117
Output Pin Function..........................................401
PPG Functions .................................................432
Primary Functions of DMAC .............................196
Register Function ....255, 258, 261, 262, 263, 265,
267, 269, 272, 279, 288, 290, 292, 294,
295
G
General Specifications
General Specifications of Ports ..........................135
General-purpose Register
General-purpose Register ....................................36
Generating Internal Operating Clock
Generating Internal Operating Clock ....................70
Generation
Block Diagram of Clock Generation Control
Block....................................................78
Reception Interrupt Generation and Flag Set
Timing................................................355
Transmission Interrupt Generation and Flag Set
Timing................................................357
Transmission Interrupt Request Generation
Timing................................................358
WPR: Watchdog Reset Generation Postpone
Register ................................................91
601
INDEX
H
Hardware Configuration
Hardware Configuration of DMAC .................... 196
Hardware Configuration of the Interrupt
Controller ........................................... 154
Hardware Sequence Flag
Hardware Sequence Flag................................... 506
Harvard ←→ Princeton
Harvard ←→ Princeton Bus Converter................. 32
Hold Request
Bit Configuration of Hold Request Cancel Request
Register (HRCL) ................................. 159
Example of Using the Function to Generate a Request
to Cancel a Hold Request (HRCR) ........ 165
Hold Request Cancel Request............................ 163
Hold Request Cancel Request
Hold Request Cancel Request............................ 163
Hold Request Cancel Request Register
Bit Configuration of Hold Request Cancel Request
Register (HRCL) ................................. 159
Hold Suppression
NMI/Hold Suppression Level Interrupt
Process............................................... 232
Hour
Hour/Minute/Second Register............................ 458
How to Avoid
How to Avoid Problems.................................... 521
How to Read the Instruction Lists
How to Read the Instruction Lists ...................... 571
HRCL
Bit Configuration of Hold Request Cancel Request
Register (HRCL) ................................. 159
HRCR
Example of Using the Function to Generate a Request
to Cancel a Hold Request (HRCR) ........ 165
I
I Flag
I Flag ................................................................ 53
I/O Circuit
I/O Circuit Types ............................................... 21
ICR
Bit Configuration of ICR..................................... 54
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 158
ICR Mapping ..................................................... 54
ICS
Bit Configuration of the Input Capture Register
(ICS).................................................. 417
ILM
ILM ............................................................ 41, 53
602
Immediate Set
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions ........................................ 581
Immediate Transfer Instructions
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions ........................................ 581
INIT
Settings Initialization Reset (INIT) .................... 126
Initial Values
Initial Values for Each Hardware....................... 449
Initialization
Operation Initialization Reset (RST) .................. 127
Settings Initialization Reset (INIT) .................... 126
Wait Time after Setting Initialization ................... 73
Initializing
Initializing the Division Ratio Setting .................. 77
INITX
Return Via the INITX Pin in STOP Mode .......... 125
Input
About Connection with Input Capture/Output
Compare ............................................ 412
Bit Configuration of the Input Capture Register
(ICS) ................................................. 417
Bit Configuration of the Input Capture Register
(IPCP) ............................................... 416
Block Diagram of Input Capture........................ 414
External Interrupt Input Pin Select Register
(EISSR) ............................................. 174
Input Data Direct Read Registers (PIDRs).......... 152
Input Impedance .............................................. 470
Input Timing of 16-bit Input Capture ................. 420
List of Input Capture Registers .......................... 415
Operations of the 16-bit Input Capture ............... 419
Overview of Input Capture................................ 414
Pin Input Levels............................................... 148
Processing Unused Input Pins ............................. 24
Selecting a Pin Input Level ............................... 148
Source Oscillation Input on Power-up .................. 25
Input Capture
About Connection with Input Capture/Output
Compare ............................................ 412
Bit Configuration of the Input Capture Register
(ICS) ................................................. 417
Bit Configuration of the Input Capture Register
(IPCP) ............................................... 416
Block Diagram of Input Capture........................ 414
Input Timing of 16-bit Input Capture ................. 420
List of Input Capture Registers .......................... 415
Operations of the 16-bit Input Capture ............... 419
Overview of Input Capture................................ 414
Input Capture Register
Bit Configuration of the Input Capture Register
(ICS) ................................................. 417
Bit Configuration of the Input Capture Register
(IPCP) ............................................... 416
INDEX
List of Input Capture Registers .......................... 415
Input Data Direct Read Registers
Input Data Direct Read Registers (PIDRs) .......... 152
Input Impedance
Input Impedance .............................................. 470
Input Timing
Input Timing of 16-bit Input Capture ................. 420
Instruction
20-Bit Delayed Branch Macro Instructions ......... 588
20-Bit Normal Branch Macro Instructions .......... 587
32-Bit Delayed Branch Macro Instructions ......... 590
32-Bit Normal Branch Macro Instructions .......... 589
Add-Subtract Instructions ................................. 577
Bit Manipulation Instructions ............................ 579
Compare Instructions ....................................... 577
Coprocessor Control Instructions....................... 592
Delayed Branch Instructions ............................. 585
Direct Addressing Instructions .......................... 591
FR Family Instruction Lists............................... 576
How to Read the Instruction Lists...................... 571
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions......................................... 581
Instruction Format............................................ 575
Logic Instructions ............................................ 578
Memory Load Instructions ................................ 582
Memory Store Instructions................................ 583
Multiply Instructions ........................................ 580
Normal Branch (No Delay) Instructions ............. 584
Operation of INT Instruction ............................... 63
Operation of INTE Instruction............................. 63
Operation of RETI Instruction ............................. 65
Operation of Undefined Instruction
Exception ............................................. 64
Other Instructions ............................................ 586
Overview of Other Instructions ........................... 34
Register-to-Register Transfer Instructions .......... 583
Resource Instructions ....................................... 591
Shift Instructions.............................................. 581
Instruction Format
Instruction Format............................................ 575
INT
Operation of INT Instruction ............................... 63
INTE
Operation of INTE Instruction............................. 63
Inter-CPU Connection
Inter-CPU Connection .............................. 380, 381
Inter-CPU Connection Method .......................... 367
Interface
List of Message Interface Register ..................... 248
Internal
Bus Mode 1
(Internal ROM/External Bus Mode) ........ 67
Generating Internal Operating Clock.................... 70
Internal Clock Operation................................... 399
Internal Architecture
Features of Internal Architecture ..........................29
Overview of Internal Architecture ........................29
Structure of Internal Architecture .........................30
Internal Clock
Internal Clock Operation ...................................399
Internal Memory
Internal Memory...................................................2
Interrupt
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ......................173
Bit Configuration of External Interrupt Source
Register (EIRR)...................................172
Bit Configuration of Interrupt Control Register
(ICR)..................................................158
Bit Configuration of Interrupt Enable Register
(ENIR) ...............................................171
Block Diagram of Delay Interrupt Module ..........183
Block Diagram of External Interrupt Control
Unit....................................................169
Bus Idle Interrupts ............................................353
Delay Interrupt Module Register (DICR) ............184
Details of Interrupt Controller Registers..............157
Details of Registers of External Interrupt Control
Unit....................................................170
DMA Transfer and Interrupt ..............................228
EIT Interrupt Levels............................................52
External Interrupt Input Pin Select Register
(EISSR) ..............................................174
External Interrupt Request Level ........................177
External Interrupts (16 Channels) ...........................3
Hardware Configuration of the Interrupt
Controller ...........................................154
Interrupt...........................................................448
Interrupt Controller ...............................................3
Interrupt Controller Block Diagram ....................156
Interrupt Number ..............................................185
Interrupt Stack....................................................55
Interrupt That can Output the DMAC Interrupt
Control ...............................................235
Interrupts of LIN-UART ...................................351
Level Masking for Interrupt/NMI .........................53
LIN-Synch-Break Detection Interrupt
and Flag..............................................376
LIN-Synch-Break Interrupts ..............................353
LIN-Synch-Field Edge Detection Interrupts ........353
List of Interrupt Controller Registers ..................155
List of Registers of External Interrupt Control
Unit....................................................168
Main Functions of the Interrupt Controller ..........154
Main Oscillation Stabilization Wait
Interrupt..............................................117
NMI (Non Maskable Interrupt) ..........................163
NMI/Hold Suppression Level Interrupt
Process ...............................................232
603
INDEX
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Operating Procedure for an External
Interrupt ............................................. 176
Operation of User Interrupt and NMI ................... 62
Operations of an External Interrupt .................... 176
Overview of Delay Interrupt Module.................. 182
Reception Interrupt Generation and Flag Set
Timing ............................................... 355
Reception Interrupts ......................................... 352
Register List of Delay Interrupt Module ............. 183
Return Via the External Interrupt
in STOP Mode .................................... 125
Timing of Occurrence for Interrupt Clear
by DMA ............................................. 231
Transmission Interrupt Enabling Timing............. 388
Transmission Interrupt Generation and Flag Set
Timing ............................................... 357
Transmission Interrupt Request Generation
Timing ............................................... 358
Transmission Interrupts..................................... 352
Interrupt Control
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 158
Block Diagram of External Interrupt Control
Unit ................................................... 169
Details of Registers of External Interrupt Control
Unit ................................................... 170
Interrupt That can Output the DMAC Interrupt
Control............................................... 235
List of Registers of External Interrupt Control
Unit ................................................... 168
Interrupt Control Register
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 158
Interrupt Controller
Details of Interrupt Controller Registers ............. 157
Hardware Configuration of the Interrupt
Controller ........................................... 154
Interrupt Controller............................................... 3
Interrupt Controller Block Diagram.................... 156
List of Interrupt Controller Registers .................. 155
Main Functions of the Interrupt Controller.......... 154
Interrupt Controller Registers
Details of Interrupt Controller Registers ............. 157
List of Interrupt Controller Registers .................. 155
Interrupt Enable Register
Bit Configuration of Interrupt Enable Register
(ENIR) ............................................... 171
Interrupt Request
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ...................... 173
External Interrupt Request Level........................ 177
Transmission Interrupt Request Generation
Timing ............................................... 358
604
Interval Time
Interval Times of the Main Oscillation Stabilization
Wait Timer......................................... 113
Interval Timer
Operation of Interval Timer Function................. 117
Other Interval Timer/Counter................................ 3
IPCP
Bit Configuration of the Input Capture Register
(IPCP) ............................................... 416
L
Latch-up
Preventing Latch-up ........................................... 24
Level Masking
Level Masking for Interrupt/NMI ........................ 53
Levels
EIT Interrupt Levels........................................... 52
Pin Input Levels............................................... 148
Priority Levels for Accepting EIT Sources ........... 60
LIN
LIN Bus Timing .............................................. 377
LIN Device Connection .................................... 384
LIN Master/Slave Communication Function....... 384
LIN Slave Settings ........................................... 388
LIN-Synch-Break Interrupts.............................. 353
LIN-Synch-Field Edge Detection Interrupts........ 353
UART with LIN Function (7 Channels) ................. 3
Using LIN in Operation Mode 3 ........................ 388
LIN-UART
Block Diagram of LIN-UART................... 325, 326
Interrupts of LIN-UART................................... 351
LIN-UART as LIN Master................................ 374
LIN-UART as LIN Slave.................................. 375
LIN-UART as Master Device............................ 385
LIN-UART as Slave Device.............................. 386
LIN-UART Baud Rate Selection ....................... 359
LIN-UART Operation Modes ........................... 323
LIN-UART Pin Direct Access........................... 378
Operations of LIN-UART ................................. 366
Registers of LIN-UART ................................... 330
List
Clock Calibration Unit Registers List of Real Time
Clock ................................................. 462
List of Input Capture Registers .......................... 415
List of Interrupt Controller Registers ................. 155
List of Message Handler Register ...................... 251
List of Message Interface Register ..................... 248
List of Overall Control Register ........................ 247
List of Pin Functions .......................................... 12
List of Real Time Clock Registers ..................... 452
List of Registers of External Interrupt Control
Unit ................................................... 168
List of the Registers of the PPG Timer ............... 436
Register List .................................................... 472
Register List of 16-Bit Free-Run Timer.............. 405
INDEX
Register List of 16-Bit Reload Timer ................. 393
Register List of Bit Search Module .................... 187
Register List of Delay Interrupt Module ............. 183
Load
Load and Store................................................... 33
Logic Instructions
Logic Instructions ............................................ 578
Loop
Loop Back Mode ............................................. 313
LQFP-100
LQFP-100 ........................................................... 6
LQFP-144
LQFP-144 ........................................................... 7
M
Machine Clock
Examples of Baud Rate Settings for Each Machine
Clock Frequency ................................. 362
Macro
20-Bit Delayed Branch Macro Instructions ......... 588
20-Bit Normal Branch Macro Instructions .......... 587
32-Bit Delayed Branch Macro Instructions ......... 590
32-Bit Normal Branch Macro Instructions .......... 589
Main
Main Oscillation Stabilization Wait
Interrupt ............................................. 117
Main Timer Data Register (CUTR).................... 467
Main Clock
Wait Time after Switching from the Sub Clock to the
Main Clock .......................................... 74
Main Functions
Major Functions of the Interrupt Controller ........ 154
Main Oscillation Stabilization Wait Timer
Block Diagram of the Main Oscillation Stabilization
Wait Timer ......................................... 114
Interval Times of the Main Oscillation Stabilization
Wait Timer ......................................... 113
Notes on Using the Main Oscillation Stabilization
Wait Timer ......................................... 119
Operation of the Main Oscillation Stabilization Wait
Timer................................................. 118
Main Oscillation Stabilization Wait Timer Register
Explanation of the Main Oscillation Stabilization Wait
Timer Register .................................... 115
Main Timer Data Register
Main Timer Data Register (CUTR).................... 467
Manipulation
Arithmetic Operation and Bit Manipulation .......... 34
Mapping
ICR Mapping..................................................... 54
Master
LIN Master/Slave Communication Function ....... 384
LIN-UART as LIN Master ................................ 374
LIN-UART as Master Device............................ 385
Master/Slave Communication Function ..............381
MB91210 Series
Block Diagram of MB91210 Series ........................5
Memory Maps of MB91210 Series.......................10
MD
Mode Pins (MD0 to MD3)...................................25
Measurement
Measurement Process Timing ............................460
Memory
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ..................................495
Bit Configuration of Flash Memory Wait Register
(FLWC)..............................................497
Erasing All Data from Flash Memory
(Chip Erase) ........................................515
Flash Memory Access Modes ............................499
Flash Memory Block Diagram ...........................491
Flash Memory Programming Procedure ..............513
Internal Memory...................................................2
Memory Map of Flash Memory .........................492
Notes on Flash Memory Programming................523
Overview of Flash Memory ...............................490
Overview of Flash Memory Automatic
Algorithms..........................................501
Overview of Flash Memory Registers.................494
Overview of Programming and Erasing Flash
Memory..............................................511
Programming Data into Flash Memory ...............513
Resuming Sector Erasure in Flash Memory .........519
Sector Address Table of Flash Memory ..............493
Sector Configuration of Flash Memory .................11
Suspending Sector Erasure in Flash Memory.......518
Memory Access Modes
Flash Memory Access Modes ............................499
Memory Load Instructions
Memory Load Instructions.................................582
Memory Map
Memory Map ...............................................28, 47
Memory Map of Flash Memory .........................492
Memory Maps of MB91210 Series.......................10
Memory Store Instructions
Memory Store Instructions ................................583
Message
Acceptance Filter of Reception Message.............302
Configuration of Message Object .......................280
Data Transmission/Reception
with Message RAM .............................297
Function of Message Object ..............................280
List of Message Handler Register.......................251
List of Message Interface Register......................248
Message Handler Register .................................286
Message Object ................................................297
Message Reception by FIFO Buffer....................306
Message Transmission ......................................299
Process of Reception Message ...........................305
605
INDEX
Setting of Reception Message Object ................. 304
Setting of Transmission Message Object ............ 300
Updating a Transmission Message Object........... 301
Message Handler Register
List of Message Handler Register ...................... 251
Message Handler Register ................................. 286
Message Interface Register
List of Message Interface Register ..................... 248
Microcontroller
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
Minute
Hour/Minute/Second Register............................ 458
Mode
Access Mode ..................................................... 66
Basic Mode...................................................... 315
Bus Mode .......................................................... 66
Bus Mode 0 (Single-chip Mode) .......................... 67
Bus Mode 1
(Internal ROM/External Bus Mode) ........ 67
Bus Mode 2
(External ROM/External Bus Mode) ....... 67
Caution for Operation during PLL Clock
Mode ................................................... 25
Clock Inversion and Start/Stop Bits
in Mode 2 ........................................... 371
Combination of Silent Mode and Loop Back
Mode ................................................. 314
Communication Mode Setting ........................... 388
Continuous Mode ............................................. 486
Flash Memory Access Modes ............................ 499
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
FR-CPU ROM Mode
(Read-only in 32/16/8 Bits) .................. 499
LIN-UART Operation Modes............................ 323
Loop Back Mode.............................................. 313
Mode Fetch...................................................... 129
Mode Pins ................................................. 68, 129
Mode Pins (MD0 to MD3) .................................. 25
Mode Register (MODR) ..................................... 69
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Operating Mode ............................................... 446
Overview of Operating Modes............................. 66
Pin States after Mode Data is Read .................... 132
PPG Operating Mode Control Register
(PPGC) .............................................. 438
Return Via the External Interrupt
in STOP Mode .................................... 125
Return Via the INITX Pin in STOP Mode........... 125
Returning from Standby (Stop or Sleep)
Mode ................................................. 164
Serial Mode Register (SMR) ............................. 335
606
Signal Mode .................................................... 367
Silent Mode..................................................... 312
Single Mode .................................................... 486
Sleep Mode ..................................................... 108
Stop Mode............................................... 110, 486
Test Mode Setting............................................ 312
Transfer Mode ................................................. 219
Using LIN in Operation Mode 3 ........................ 388
Wait Time after Returning from Stop Mode ......... 74
Mode Data
Pin States after Mode Data is Read .................... 132
Mode Fetch
Mode Fetch ..................................................... 129
Mode Pins
Mode Pins ................................................. 68, 129
Mode Pins (MD0 to MD3) .................................. 25
Mode Register
Mode Register (MODR) ..................................... 69
MODR
Mode Register (MODR) ..................................... 69
Module
Bit Search Module (Used by REALOS) ................. 2
Block Diagram of Bit Search Module ................ 188
Block Diagram of Delay Interrupt Module ......... 183
Delay Interrupt Module Register (DICR) ........... 184
Overview of Bit Search Module ........................ 186
Overview of Delay Interrupt Module ................. 182
Register List of Bit Search Module .................... 187
Register List of Delay Interrupt Module ............. 183
Multiplication
PLL Multiplication Rate ..................................... 72
Wait Time after Changing PLL Multiplication
Rate ..................................................... 73
Multiply & Divide Register
Multiply & Divide Register (Multiply & Divide
Register) .............................................. 44
Multiply Instructions
Multiply Instructions ........................................ 580
N
NMI
Level Masking for Interrupt/NMI ........................ 53
NMI (Non Maskable Interrupt).......................... 163
NMI/Hold Suppression Level Interrupt
Process .............................................. 232
Operation of User Interrupt and NMI ................... 62
No Delay
Normal Branch (No Delay) Instructions ............. 584
Normal Branch
20-Bit Normal Branch Macro Instructions .......... 587
32-Bit Normal Branch Macro Instructions .......... 589
Normal Branch (No Delay) Instructions ............. 584
Note
Additional Notes.............................................. 537
INDEX
Note on Using an External Clock......................... 25
Notes .............................................................. 402
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Notes on Flash Memory Programming ............... 523
Notes on Programming Data ............................. 513
Notes on Reset Source Bits ............................... 131
Notes on Setting Register.................................. 199
Notes on Specifying Multiple Sectors ................ 516
Notes on Using 16-Bit Free-Run Timer .............. 412
Notes on Using DMA Transfer.......................... 389
Notes on Using the Main Oscillation Stabilization
Wait Timer ......................................... 119
Number
Interrupt Number ............................................. 185
O
Object
Configuration of Message Object ...................... 280
Function of Message Object .............................. 280
Message Object ............................................... 297
Setting of Reception Message Object ................. 304
Setting of Transmission Message Object ............ 300
Updating a Transmission Message Object .......... 301
OCCP
Bit Configuration of the Compare Register
(OCCP).............................................. 424
Functions of the Compare Register (OCCP) ....... 424
Occurrence
Occurrence of Address Error ............................. 234
Occurrence of Transfer Stop Request from Peripheral
Circuit................................................ 234
Timing of Occurrence for Interrupt Clear
by DMA............................................. 231
OCS
Bit Configuration of the Control Register
(OCS) ................................................ 425
On-board
Connection Example for On-board Reprogramming
Using a Programmer............................ 539
Pins Used by the Programmer for On-board
Reprogramming .................................. 540
Operating
Generating Internal Operating Clock.................... 70
Operating Mode ............................................... 446
Operating Procedure for an External
Interrupt ............................................. 176
Operating Status of Counter .............................. 402
Overview of Operating Modes ............................ 66
PPG Operating Mode Control Register
(PPGC) .............................................. 438
Operating Modes
Overview of Operating Modes ............................ 66
Operating Status
Operating Status of Counter...............................402
Operation
All the Channels' Operation Disabled .................233
All the Channels' Operation Enabled ..................229
Arithmetic Operation ..........................................33
Arithmetic Operation and Bit Manipulation...........34
Caution for Operation during PLL Clock
Mode....................................................25
Changing Operation Settings .............................388
Enabling PLL Operation......................................71
Explanation of Operation of 16-Bit Free-Run
Timer .................................................410
Internal Clock Operation ...................................399
LIN-UART Operation Modes ............................323
Operation Enable Bit.........................................367
Operation Flow of Block Transfer ......................239
Operation Flow of Burst Transfer.......................240
Operation Initialization Reset (RST)...................127
Operation of Clock Supply Function...................118
Operation of Data in Two-cycle Transfer ............241
Operation of INT Instruction ...............................63
Operation of INTE Instruction .............................63
Operation of Interval Timer Function .................117
Operation of RETI Instruction .............................65
Operation of Step Trace Trap...............................64
Operation of the 16-bit Output Compare .............428
Operation of the Main Oscillation Stabilization Wait
Timer .................................................118
Operation of Undefined Instruction
Exception..............................................64
Operation of User Interrupt and NMI....................62
Operation on Power-up .......................................25
Operation Setting..............................................388
Operation with a Delay Slot.................................48
Operation without a Delay Slot ............................50
Operations of an External Interrupt.....................176
Operations of LIN-UART..................................366
Operations of the 16-bit Input Capture ................419
Outline of Reset Operation ................................129
PPG Operation .................................................445
PPG Output Operation ......................................446
Primary Operations of DMAC ...........................219
Reception Operation .........................................369
Recovery Operations from STOP Status .............179
Reload Operation..............................................224
Restrictions on the Operation
with a Delay Slot ...................................49
Synchronous Standby Operation ........................112
Timing of 16-bit Output Compare
Operation............................................429
Transfer Count Register and Reload
Operation............................................227
Transmission Operation ....................................369
Underflow Operation ........................................400
Using LIN in Operation Mode 3.........................388
Wait Time after Enabling PLL Operation..............73
607
INDEX
Operation Enable Bit
Operation Enable Bit ........................................ 367
Operation Flow
Operation Flow of Block Transfer...................... 239
Operation Flow of Burst Transfer ...................... 240
Operation Mode
LIN-UART Operation Modes............................ 323
Using LIN in Operation Mode 3 ........................ 388
Operational States
Operational States of Device ............................. 106
OSCCR
OSCCR: Oscillation Control Register................... 97
Oscillation Clock Frequency
Oscillation Clock Frequency ............................. 537
Oscillation Control Register
OSCCR: Oscillation Control Register................... 97
Oscillation Stabilization Wait Interrupt
Main Oscillation Stabilization Wait
Interrupt ............................................. 117
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time When the Power
is Turned On ....................................... 125
Reset Factors and Oscillation Stabilization Wait
Time .................................................. 124
Other
Other Features...................................................... 4
Other Interval Timer/Counter ................................ 3
Overview of Other Instructions............................ 34
Other Instructions
Other Instructions............................................. 586
Outline
Outline of Reset Operation ................................ 129
Output
About Connection with Input Capture/Output
Compare............................................. 412
Block Diagram of the Output Compare Unit ....... 422
Control of Pulse Pin Output............................... 448
Features of the Output Compare Unit ................. 422
Interrupt That can Output the DMAC Interrupt
Control............................................... 235
Operation of the 16-bit Output Compare............. 428
Output Pin Function ......................................... 401
Output Reverse Register (REVC)....................... 444
PPG Output Operation ...................................... 446
Registers of the Output Compare Unit ................ 423
Timing of 16-bit Output Compare
Operation ........................................... 429
Output Compare
About Connection with Input Capture/Output
Compare............................................. 412
Block Diagram of the Output Compare Unit ....... 422
Features of the Output Compare Unit ................. 422
Operation of the 16-bit Output Compare............. 428
Registers of the Output Compare Unit ................ 423
608
Timing of 16-bit Output Compare
Operation ........................................... 429
Output Pin
Output Pin Function ......................................... 401
Output Reverse Register
Output Reverse Register (REVC) ...................... 444
Overall Control Register
List of Overall Control Register ........................ 247
Overall Control Register................................... 254
Overview
Overview ........................................................ 322
Overview of 16-Bit Free-Run Timer .................. 404
Overview of 16-Bit Reload Timer ..................... 392
Overview of A/D Converter Registers................ 472
Overview of Bit Search Module ........................ 186
Overview of Delay Interrupt Module ................. 182
Overview of Device State Control ..................... 104
Overview of DMAC......................................... 218
Overview of Flash Memory .............................. 490
Overview of Flash Memory Automatic
Algorithms ......................................... 501
Overview of Flash Memory Registers ................ 494
Overview of Input Capture................................ 414
Overview of Internal Architecture ....................... 29
Overview of Operating Modes ............................ 66
Overview of Other Instructions ........................... 34
Overview of Programming and Erasing Flash
Memory ............................................. 511
Overview of the DMAC Register ...................... 197
P
Parity
Parity.............................................................. 370
PC
PC (Program Counter) ........................................ 42
PDRs
Port Data Registers (PDRs)............................... 136
Peripheral Clock
Peripheral Clock (CLKP).................................... 75
PIDRs
Input Data Direct Read Registers (PIDRs).......... 152
Pin
Block Diagram of External Reset Pin................. 128
Control of Pulse Pin Output .............................. 448
External Interrupt Input Pin Select Register
(EISSR) ............................................. 174
External Pin Reset Timing ................................ 128
LIN-UART Pin Direct Access........................... 378
Mode Pins ................................................. 68, 129
Mode Pins (MD0 to MD3) .................................. 25
Output Pin Function ......................................... 401
Pin Input Levels............................................... 148
Pin States after Mode Data is Read .................... 132
Pin States during a Reset .................................. 132
Pin Timing Chart ............................................. 541
INDEX
Pins Used by the Programmer for On-board
Reprogramming .................................. 540
Pins Used for Fujitsu-standard Serial On-board
Programming...................................... 527
Power Supply Pins ............................................. 24
Processing Unused Input Pins ............................. 24
Return Via the INITX Pin in STOP Mode .......... 125
Selecting a Pin Input Level ............................... 148
Software Control of Pin CAN_TX ..................... 316
Pin Assignment
Pin Assignment of MB91213A/F213A/F218S ........ 9
Pin Assignment of MB91F211B ............................ 8
Pin Function
List of Pin Functions .......................................... 12
Output Pin Function ......................................... 401
Pin State
Pin States in Each CPU State ............................ 566
Pin States
Pin States after Mode Data is Read .................... 132
Pin States during a Reset................................... 132
Placing
Placing the Flash Memory in the Reset
State .................................................. 512
PLL
Caution for Operation during PLL Clock
Mode ................................................... 25
Enabling PLL Operation ..................................... 71
PLL Multiplication Rate ..................................... 72
PLLC: PLL Control Register............................... 98
Wait Time after Changing PLL Multiplication
Rate ..................................................... 73
Wait Time after Enabling PLL Operation ............. 73
PLL Clock Mode
Caution for Operation during PLL Clock
Mode ................................................... 25
PLL Control Register
PLLC: PLL Control Register............................... 98
PLLC
PLLC: PLL Control Register............................... 98
Port
Basic Block Diagram of Ports ........................... 134
General Specifications of Ports.......................... 135
Port 0.............................................................. 138
Port 1.............................................................. 139
Port 2.............................................................. 140
Port 3.............................................................. 140
Port 4.............................................................. 141
Port 5.............................................................. 142
Port 6.............................................................. 142
Port 7.............................................................. 143
Port 8.............................................................. 143
Port 9.............................................................. 144
Port A ............................................................. 145
Port B ............................................................. 145
Port C ............................................................. 145
Port D..............................................................146
Port Data Registers (PDRs) ...............................136
Port E ..............................................................146
Port F ..............................................................147
Port Pull-up/Pull-down Control Registers ...........151
Port Pull-up/Pull-down Enable Registers ............150
Port 0
Port 0 ..............................................................138
Port 1
Port 1 ..............................................................139
Port 2
Port 2 ..............................................................140
Port 3
Port 3 ..............................................................140
Port 4
Port 4 ..............................................................141
Port 5
Port 5 ..............................................................142
Port 6
Port 6 ..............................................................142
Port 7
Port 7 ..............................................................143
Port 8
Port 8 ..............................................................143
Port 9
Port 9 ..............................................................144
Port A
Port A..............................................................145
Port B
Port B..............................................................145
Port C
Port C..............................................................145
Port D
Port D..............................................................146
Port Data Registers
Port Data Registers (PDRs) ...............................136
Port E
Port E ..............................................................146
Port F
Port F ..............................................................147
Port Pull-up/Pull-down Control Registers
Port Pull-up/Pull-down Control Registers ...........151
Port Pull-up/Pull-down Enable Registers
Port Pull-up/Pull-down Enable Registers ............150
Power Supply Pins
Power Supply Pins..............................................24
Power-on
Wait Time after Power-on ...................................73
Power-up
Operation on Power-up .......................................25
Source Oscillation Input on Power-up...................25
609
INDEX
PPG
Block Diagram of the 8-bit PPG ch.0 and
ch.2.................................................... 433
Block Diagram of the 8-bit PPG ch.1 ................. 434
Block Diagram of the 8-bit PPG ch.3 ................. 435
List of the Registers of the PPG Timer ............... 436
PPG Combinations ........................................... 449
PPG Functions ................................................. 432
PPG Operating Mode Control Register
(PPGC) .............................................. 438
PPG Operation ................................................. 445
PPG Output Operation ...................................... 446
PPG Start Register (TRG) ................................. 443
PPG Operating Mode Control Register
PPG Operating Mode Control Register
(PPGC) .............................................. 438
PPG Start Register
PPG Start Register (TRG) ................................. 443
PPG Timer
List of the Registers of the PPG Timer ............... 436
PPGC
PPG Operating Mode Control Register
(PPGC) .............................................. 438
Prescaler
CAN Clock Prescaler Setting............................. 320
Clock Prescaler Register ................................... 252
Preventing Latch-up
Preventing Latch-up ........................................... 24
Primary Functions
Primary Functions of DMAC............................. 196
Primary Operations
Primary Operations of DMAC ........................... 219
Priority
Determining the Priority ................................... 160
Priority Among Channels.................................. 237
Reception Priority ............................................ 302
Transmission Priority........................................ 299
Priority Levels
Priority Levels for Accepting EIT Sources............ 60
PRLL/PRLH
Reload Register (PRLL/PRLH) ......................... 441
Problem
Description of Problems due to Restrictions........ 520
How to Avoid Problems.................................... 521
Procedure
Communication Procedure ................................ 382
Flash Memory Programming Procedure.............. 513
Operating Procedure for an External
Interrupt ............................................. 176
Procedure of Clock Switching ........................... 319
Sector Erasing Procedure .................................. 516
Process
Process of Reception Message ........................... 305
Process of Save/Restore .................................... 193
610
Processing Unused Input Pins
Processing Unused Input Pins ............................. 24
Program
Program (Data Write)....................................... 503
Program Counter
PC (Program Counter) ........................................ 42
Program Status
PS (Program Status) ........................................... 37
Programmer
Connection Example for On-board Reprogramming
Using a Programmer............................ 539
Pins Used by the Programmer for On-board
Reprogramming .................................. 540
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation) ....................................... 537
Programming
Basic Programming Model ................................. 35
Flash Memory Programming Procedure ............. 513
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
Notes on Flash Memory Programming ............... 523
Notes on Programming Data ............................. 513
Overview of Programming and Erasing Flash
Memory ............................................. 511
Pins Used for Fujitsu-standard Serial On-board
Programming...................................... 527
Programming Data into Flash Memory .............. 513
Serial Programming Connection Examples......... 528
PS
PS (Program Status) ........................................... 37
Pull-up/Pull-down
Port Pull-up/Pull-down Control Registers........... 151
Port Pull-up/Pull-down Enable Registers............ 150
Pull-up/Pull-down Control ................................ 150
Pulse
Control of Pulse Pin Output .............................. 448
Relationship between Reload Value and Pulse
Width ................................................ 447
Pulse Width
Relationship between Reload Value and Pulse
Width ................................................ 447
R
RAM
Data Transmission/Reception
with Message RAM ............................ 297
RDR
Reception/Transmission Data Register
(RDR/TDR) ....................................... 341
RDY
RDY Bit.......................................................... 506
INDEX
Read
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
FR-CPU ROM Mode
(Read-only in 32/16/8 Bits) .................. 499
Input Data Direct Read Registers (PIDRs) .......... 152
Pin States after Mode Data is Read .................... 132
Read from FIFO Buffer .................................... 307
Read/Write
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
Real Time Clock
Clock Calibration Unit of Real Time Clock ........ 460
Clock Calibration Unit Registers List of Real Time
Clock ................................................. 462
Real Time Clock Registers
List of Real Time Clock Registers ..................... 452
REALOS
Bit Search Module (Used by REALOS) ................. 2
Reception
Acceptance Filter of Reception Message ............ 302
Data Frame Reception ...................................... 302
Data Transmission/Reception
with Message RAM............................. 297
Message Reception by FIFO Buffer ................... 306
Process of Reception Message........................... 305
Reception Interrupt Generation and Flag Set
Timing ............................................... 355
Reception Interrupts ......................................... 352
Reception Operation......................................... 369
Reception Priority ............................................ 302
Reception/Transmission Data Register
(RDR/TDR)........................................ 341
Setting of Reception Message Object ................. 304
Reception Interrupt
Reception Interrupt Generation and Flag Set
Timing ............................................... 355
Reception/Transmission Data Register
Reception/Transmission Data Register
(RDR/TDR)........................................ 341
Recommended Set Value
Recommended Set Value .................................. 483
Recovery Operations
Recovery Operations from STOP Status............. 179
Register
0 Detection Data Register (BSD0) ..................... 189
1 Detection Data Register (BSD1) ..................... 189
A/D Control Status Register 0 (ADCS0) ............ 478
A/D Control Status Register 1 (ADCS1) ............ 475
A/D Enable Register (ADER) ........................... 474
AD Bit in Serial Control Register (SCR) ............ 389
Address Register Specification .......................... 225
Baud Rate/Reload Counter Register ................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
Bit Configuration of 16-Bit Reload Register
(TMRLR) ...........................................398
Bit Configuration of 16-Bit Timer Register
(TMR) ................................................397
Bit Configuration of Control Status Register
(TMCSR)............................................394
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ......................173
Bit Configuration of External Interrupt Source
Register (EIRR)...................................172
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ..................................495
Bit Configuration of Flash Memory Wait Register
(FLWC)..............................................497
Bit Configuration of Hold Request Cancel Request
Register (HRCL) .................................159
Bit Configuration of Interrupt Control Register
(ICR)..................................................158
Bit Configuration of Interrupt Enable Register
(ENIR) ...............................................171
Bit Configuration of the Compare Register
(OCCP) ..............................................424
Bit Configuration of the Control Register
(OCS).................................................425
Bit Configuration of the Input Capture Register
(ICS) ..................................................417
Bit Configuration of the Input Capture Register
(IPCP) ................................................416
Calibration Unit Control Register (CUCR)..........463
CCR (Condition Code Register) ...........................38
Change Point Detection Data Register
(BSDC) ..............................................190
CLKR: Clock Source Control Register .................88
Clock Calibration Unit Registers List of Real Time
Clock..................................................462
Clock Disable Register......................................459
Clock Prescaler Register....................................252
Conversion Time Setting Register (ADCT) .........482
CTBR: Time-base Counter Clear Register.............87
Data Direction Registers (DDRs) .......................137
Data Register (ADCR1,ADCR0)........................481
Delay Interrupt Module Register (DICR) ............184
Details of Interrupt Controller Registers..............157
Details of Registers of External Interrupt Control
Unit....................................................170
Detection Result Register (BSRR)......................190
DIVR0: Basic Clock Division Setting
Register 0..............................................92
DIVR1: Basic Clock Division Setting
Register 1..............................................95
Explanation of the Main Oscillation Stabilization Wait
Timer Register.....................................115
Extended Communication Control Register
(ECCR) ..............................................346
Extended Status/Control Register (ESCR)...........343
External Interrupt Input Pin Select Register
(EISSR) ..............................................174
611
INDEX
Functions of the Compare Register (OCCP)........ 424
General-purpose Register .................................... 36
Hour/Minute/Second Register............................ 458
Input Data Direct Read Registers (PIDRs) .......... 152
List of Input Capture Registers .......................... 415
List of Interrupt Controller Registers .................. 155
List of Message Handler Register ...................... 251
List of Message Interface Register ..................... 248
List of Overall Control Register......................... 247
List of Real Time Clock Registers...................... 452
List of Registers of External Interrupt Control
Unit ................................................... 168
List of the Registers of the PPG Timer ............... 436
Main Timer Data Register (CUTR) .................... 467
Message Handler Register ................................. 286
Mode Register (MODR) ..................................... 69
Multiply & Divide Register (Multiply & Divide
Register)............................................... 44
Notes on Setting Register .................................. 199
OSCCR: Oscillation Control Register................... 97
Output Reverse Register (REVC)....................... 444
Overall Control Register ................................... 254
Overview of A/D Converter Registers ................ 472
Overview of Flash Memory Registers ................ 494
Overview of the DMAC Register ....................... 197
PLLC: PLL Control Register ............................... 98
Port Data Registers (PDRs) ............................... 136
Port Pull-up/Pull-down Control Registers ........... 151
Port Pull-up/Pull-down Enable Registers ............ 150
PPG Operating Mode Control Register
(PPGC) .............................................. 438
PPG Start Register (TRG) ................................. 443
Reception/Transmission Data Register
(RDR/TDR) ........................................ 341
Register Configuration..... 255, 258, 261, 262, 263,
265, 267, 269, 272, 276, 277, 278, 279,
287, 289, 291, 293, 295
Register Function .... 255, 258, 261, 262, 263, 265,
267, 269, 272, 279, 288, 290, 292, 294,
295
Register List .................................................... 472
Register List of 16-Bit Free-Run Timer .............. 405
Register List of 16-Bit Reload Timer.................. 393
Register List of Bit Search Module .................... 187
Register List of Delay Interrupt Module ............. 183
Registers of CAN ............................................. 253
Registers of LIN-UART.................................... 330
Registers of the Output Compare Unit ................ 423
Reload Register (PRLL/PRLH) ......................... 441
RSRR: Reset Source Register/Watchdog Timer
Control Register .................................... 79
SCR (System Condition Code Register) ............... 40
Serial Control Register (SCR)............................ 332
Serial Mode Register (SMR) ............................. 335
Serial Status Register (SSR) .............................. 338
612
Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the
Channels Simultaneously).................... 232
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH)................... 484
STCR: Standby Control Register ......................... 82
Sub Timer Data Register (CUTD) ..................... 465
Sub Timer Data Register Setting ....................... 468
Subsecond Register .......................................... 457
TBCR: Time-base Counter Control Register......... 85
TBR (Table Base Register) ........................... 42, 56
Timer Control Register (WTCR) ....................... 455
Timer Control Status Register (TCCS) ............... 407
Timer Data Register (TCDT) ............................ 406
Transfer Count Register and Reload
Operation ........................................... 227
WPR: Watchdog Reset Generation Postpone
Register ............................................... 91
Register-to-Register Transfer Instructions
Register-to-Register Transfer Instructions .......... 583
Relationship
Relationship between Reload Value and Pulse
Width ................................................ 447
Reload
Baud Rate/Reload Counter Register................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
Bit Configuration of 16-Bit Reload Register
(TMRLR)........................................... 398
Block Diagram of 16-Bit Reload Timer.............. 392
Overview of 16-Bit Reload Timer ..................... 392
Register List of 16-Bit Reload Timer ................. 393
Relationship between Reload Value and Pulse
Width ................................................ 447
Reload Operation ............................................. 224
Reload Register (PRLL/PRLH) ......................... 441
Transfer Count Register and Reload
Operation ........................................... 227
Reload Counter
Baud Rate/Reload Counter Register................... 350
Baud Rate/Reload Counter Register (BGR) ........ 349
Reload Register
Bit Configuration of 16-Bit Reload Register
(TMRLR)........................................... 398
Reload Register (PRLL/PRLH) ......................... 441
Reload Timer
Block Diagram of 16-Bit Reload Timer.............. 392
Overview of 16-Bit Reload Timer ..................... 392
Register List of 16-Bit Reload Timer ................. 393
Reload Value
Relationship between Reload Value and Pulse
Width ................................................ 447
Remote Frame
Remote Frame ................................................. 303
Reset
Block Diagram of External Reset Pin................. 128
INDEX
External Pin Reset Timing ................................ 128
Notes on Reset Source Bits ............................... 131
Operation Initialization Reset (RST) .................. 127
Outline of Reset Operation................................ 129
Pin States during a Reset................................... 132
Placing the Flash Memory in the Read/Reset
State .................................................. 512
Reset............................................................... 130
Reset Command............................................... 503
Reset Factors ................................................... 122
Reset Factors and Oscillation Stabilization Wait
Time .................................................. 124
Reset Source Bits and Reset Factors .................. 131
RSRR: Reset Source Register/Watchdog Timer
Control Register.................................... 79
Settings Initialization Reset (INIT) .................... 126
WPR: Watchdog Reset Generation Postpone
Register................................................ 91
Reset Operation
Outline of Reset Operation................................ 129
Reset Source Register
RSRR: Reset Source Register/Watchdog Timer
Control Register.................................... 79
Resource Instructions
Resource Instructions ....................................... 591
Restore
Process of Save/Restore.................................... 193
Restoring
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Restriction
Description of Problems due to Restrictions ....... 520
Restrictions
Restrictions on Data Polling Flag (DQ7) ............ 516
Restrictions on the Operation
with a Delay Slot .................................. 49
Result
Detection Result Register (BSRR) ..................... 190
Resuming
Resuming Sector Erasure in Flash Memory ........ 519
RETI
Operation of RETI Instruction ............................. 65
Return
Return Via the External Interrupt
in STOP Mode.................................... 125
Return Via the INITX Pin in STOP Mode .......... 125
Return Pointer
RP (Return Pointer)............................................ 42
Returning
Returning from EIT............................................ 51
Returning from Standby (Stop or Sleep)
Mode ................................................. 164
Wait Time after Returning from Stop Mode.......... 74
REVC
Output Reverse Register (REVC) .......................444
ROM
Bus Mode 1
(Internal ROM/External Bus Mode).........67
Bus Mode 2
(External ROM/External Bus Mode)........67
FR-CPU ROM Mode
(Read-only in 32/16/8 Bits)...................499
RP
RP (Return Pointer) ............................................42
RSRR
RSRR: Reset Source Register/Watchdog Timer
Control Register ....................................79
RST
Operation Initialization Reset (RST)...................127
Run
Block Diagram of 16-Bit Free-Run Timer ...........404
Clear Timing of 16-Bit Free-Run Timer..............411
Count Timing of 16-Bit Free-Run Timer.............411
Explanation of Operation of 16-Bit Free-Run
Timer .................................................410
Notes on Using 16-Bit Free-Run Timer ..............412
Overview of 16-Bit Free-Run Timer...................404
Register List of 16-Bit Free-Run Timer ..............405
S
Save
Process of Save/Restore ....................................193
SCR
AD Bit in Serial Control Register (SCR).............389
SCR (System Condition Code Register)................40
Serial Control Register (SCR) ............................332
Second
Hour/Minute/Second Register ............................458
Sector
Notes on Specifying Multiple Sectors .................516
Resuming Sector Erasure in Flash Memory .........519
Sector Address Table of Flash Memory ..............493
Sector Erase .....................................................504
Sector Erasing Procedure...................................516
Specifying One or More Sectors.........................516
Suspending Sector Erasure in Flash Memory.......518
Sector Address Table
Sector Address Table of Flash Memory ..............493
Sector Configuration
Sector Configuration of Flash Memory .................11
Sector Erase
Sector Erase .....................................................504
Sector Erasing
Sector Erasing Procedure...................................516
Selecting
Selecting a Pin Input Level ................................148
Selecting the Source Clock ..................................70
613
INDEX
Selecting the Transfer Sequence ........................ 222
Selection
Count Clock Selection ...................................... 447
LIN-UART Baud Rate Selection........................ 359
Serial Communication
Serial Communication ........................................ 24
Serial Control Register
AD Bit in Serial Control Register (SCR) ............ 389
Serial Control Register (SCR)............................ 332
Serial Mode Register
Serial Mode Register (SMR) ............................. 335
Serial Programming Connection
Serial Programming Connection Examples ......... 528
Serial Status Register
Serial Status Register (SSR) .............................. 338
Setting
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR) ...................... 173
CAN Clock Prescaler Setting............................. 320
Changing Operation Settings ............................. 388
Communication Mode Setting ........................... 388
Conversion Time Setting Register (ADCT)......... 482
DIVR0: Basic Clock Division Setting
Register 0 ............................................. 92
DIVR1: Basic Clock Division Setting
Register 1 ............................................. 95
Examples of Baud Rate Settings for Each Machine
Clock Frequency ................................. 362
Initializing the Division Ratio Setting................... 77
LIN Slave Settings ........................................... 388
Notes on Setting Register .................................. 199
Operation Setting ............................................. 388
Setting Division Ratio......................................... 77
Setting of Reception Message Object ................. 304
Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the
Channels Simultaneously) .................... 232
Setting of Transmission Message Object ............ 300
Settings Initialization Reset (INIT)..................... 126
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH) ................... 484
Sub Timer Data Register Setting........................ 468
Test Mode Setting ............................................ 312
Wait Time after Setting Initialization ................... 73
Setting Register
Notes on Setting Register .................................. 199
Shift Instructions
Shift Instructions .............................................. 581
Signal Mode
Signal Mode .................................................... 367
Silent Mode
Silent Mode ..................................................... 312
Single Mode
Single Mode .................................................... 486
614
Single-chip Mode
Bus Mode 0 (Single-chip Mode).......................... 67
Slave
LIN Master/Slave Communication Function....... 384
LIN Slave Settings ........................................... 388
LIN-UART as LIN Slave.................................. 375
LIN-UART as Slave Device.............................. 386
Master/Slave Communication Function.............. 381
Sleep
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Returning from Standby (Stop or Sleep)
Mode ................................................. 164
Sleep Mode ..................................................... 108
Sleep Mode
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Sleep Mode ..................................................... 108
SMR
Serial Mode Register (SMR) ............................. 335
Software
Software Compatibility..................................... 389
Software Control of Pin CAN_TX ..................... 316
Software Request ............................................. 221
Software Restart .............................................. 364
Source
Bit Configuration of External Interrupt Source
Register (EIRR) .................................. 172
CLKR: Clock Source Control Register................. 88
EIT Sources....................................................... 51
Priority Levels for Accepting EIT Sources ........... 60
RSRR: Reset Source Register/Watchdog Timer
Control Register.................................... 79
Selecting the Source Clock ................................. 70
Source Oscillation
Source Oscillation Input on Power-up .................. 25
Specification
Address Register Specification .......................... 225
Specifying
Notes on Specifying Multiple Sectors ................ 516
Specifying One or More Sectors ........................ 516
SSP
SSP (System Stack Pointer) .......................... 43, 55
SSR
Serial Status Register (SSR).............................. 338
Stack
Interrupt Stack ................................................... 55
SSP (System Stack Pointer) .......................... 43, 55
USP (User Stack Pointer).................................... 43
Standby
Returning from Standby (Stop or Sleep)
Mode ................................................. 164
STCR: Standby Control Register ......................... 82
Synchronous Standby Operation........................ 112
INDEX
Standby Control Register
STCR: Standby Control Register ......................... 82
Start
Clock Inversion and Start/Stop Bits
in Mode 2........................................... 371
PPG Start Register (TRG)................................. 443
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH)................... 484
Start Channel Setting Register
Start Channel Setting Register (ADSCH) End Channel
Setting Register (ADECH)................... 484
Start/Stop
Clock Inversion and Start/Stop Bits
in Mode 2........................................... 371
State
Activation from Pausing State ........................... 229
Overview of Device State Control ..................... 104
Placing the Flash Memory in the Reset
State .................................................. 512
Status
A/D Control Status Register 0 (ADCS0) ............ 478
A/D Control Status Register 1 (ADCS1) ............ 475
Automatic Algorithm Execution Status .............. 500
Bit Configuration of Control Status Register
(TMCSR) ........................................... 394
Bit Configuration of Flash Memory Control/Status
Register (FLCR) ................................. 495
Extended Status/Control Register (ESCR) .......... 343
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Operating Status of Counter .............................. 402
PS (Program Status) ........................................... 37
Recovery Operations from STOP Status............. 179
Serial Status Register (SSR).............................. 338
Timer Control Status Register (TCCS) ............... 407
STCR
STCR: Standby Control Register ......................... 82
Step
Step/Block Two-Cycle Transfer ........................ 223
Step Trace Trap
Operation of Step Trace Trap .............................. 64
Step Transfer
Step Transfer ................................................... 223
Stop
Clock Inversion and Start/Stop Bits
in Mode 2........................................... 371
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 178
Occurrence of Transfer Stop Request from Peripheral
Circuit................................................ 234
Recovery Operations from STOP Status............. 179
Return Via the External Interrupt
in STOP Mode.................................... 125
Return Via the INITX Pin in STOP Mode .......... 125
Returning from Standby (Stop or Sleep)
Mode..................................................164
Stop Bit ...........................................................369
Stop Mode ...............................................110, 486
Wait Time after Returning from Stop Mode ..........74
Stop Mode
Return Via the External Interrupt
in STOP Mode ....................................125
Return Via the INITX Pin in STOP Mode ...........125
Stop Mode ...............................................110, 486
Wait Time after Returning from Stop Mode ..........74
Store
Load and Store ...................................................33
Structure
Structure of Internal Architecture .........................30
Sub Clock
Block Diagram of Pseudo Sub Clock ..................120
Wait Time after Switching from the Sub Clock to the
Main Clock ...........................................74
Sub Timer Data Register
Sub Timer Data Register (CUTD) ......................465
Sub Timer Data Register Setting ........................468
Subsecond
Subsecond Register...........................................457
Supply
Clock Supply ...................................................372
Operation of Clock Supply Function...................118
Suppression
DMA Suppression ............................................228
NMI/Hold Suppression Level Interrupt
Process ...............................................232
Suspending
Suspending Sector Erasure in Flash Memory.......518
Switching
Procedure of Clock Switching............................319
Wait Time after Switching from the Sub Clock to the
Main Clock ...........................................74
Synchronization
Synchronization Method ...................................367
Synchronous Standby Operation
Synchronous Standby Operation ........................112
System
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation)........................................537
System Condition Code Register
SCR (System Condition Code Register)................40
System Configuration
System Configuration for AF200 Flash
Microcontroller Programmer (Manufactured
by Yokogawa Digital Computer
Corporation)........................................537
615
INDEX
System Stack Pointer
SSP (System Stack Pointer)........................... 43, 55
T
Table
EIT Vector Table ............................................... 56
Sector Address Table of Flash Memory .............. 493
Table Base Register
TBR (Table Base Register)............................ 42, 56
TBCR
TBCR: Time-base Counter Control Register ......... 85
TBR
TBR (Table Base Register)............................ 42, 56
TCCS
Timer Control Status Register (TCCS) ............... 407
TCDT
Timer Data Register (TCDT)............................. 406
TDR
Reception/Transmission Data Register
(RDR/TDR) ........................................ 341
Test
Test Mode Setting ............................................ 312
Time-base Counter
Time-base Counter ........................................... 100
Time-base Counter Clear Register
CTBR: Time-base Counter Clear Register ............ 87
Time-base Counter Control Register
TBCR: Time-base Counter Control Register ......... 85
Timer
Bit Configuration of 16-Bit Timer Register
(TMR)................................................ 397
Block Diagram of 16-Bit Free-Run Timer........... 404
Block Diagram of 16-Bit Reload Timer .............. 392
Block Diagram of the Main Oscillation Stabilization
Wait Timer ......................................... 114
Clear Timing of 16-Bit Free-Run Timer ............. 411
Count Timing of 16-Bit Free-Run Timer ............ 411
Explanation of Operation of 16-Bit Free-Run
Timer ................................................. 410
Explanation of the Main Oscillation Stabilization Wait
Timer Register .................................... 115
Interval Times of the Main Oscillation Stabilization
Wait Timer ......................................... 113
List of the Registers of the PPG Timer ............... 436
Main Timer Data Register (CUTR) .................... 467
Notes on Using 16-Bit Free-Run Timer .............. 412
Notes on Using the Main Oscillation Stabilization
Wait Timer ......................................... 119
Operation of Interval Timer Function ................. 117
Operation of the Main Oscillation Stabilization Wait
Timer ................................................. 118
Other Interval Timer/Counter ................................ 3
Overview of 16-Bit Free-Run Timer .................. 404
Overview of 16-Bit Reload Timer...................... 392
616
Register List of 16-Bit Free-Run Timer.............. 405
Register List of 16-Bit Reload Timer ................. 393
Sub Timer Data Register (CUTD) ..................... 465
Sub Timer Data Register Setting ....................... 468
Timer Control Register (WTCR) ....................... 455
Timer Control Status Register (TCCS) ............... 407
Timer Data Register (TCDT) ............................ 406
Timer Control Register
Timer Control Register (WTCR) ....................... 455
Timer Control Status Register
Timer Control Status Register (TCCS) ............... 407
Timer Data Register
Timer Data Register (TCDT) ............................ 406
Timer Register
Bit Configuration of 16-Bit Timer Register
(TMR) ............................................... 397
Timing
Clear Timing of 16-Bit Free-Run Timer ............. 411
Count Timing of 16-Bit Free-Run Timer ............ 411
External Pin Reset Timing ................................ 128
Input Timing of 16-bit Input Capture ................. 420
LIN Bus Timing .............................................. 377
Measurement Process Timing ........................... 460
Pin Timing Chart ............................................. 541
Reception Interrupt Generation and Flag Set
Timing............................................... 355
Timing of 16-bit Output Compare
Operation ........................................... 429
Timing of Occurrence for Interrupt Clear
by DMA............................................. 231
Transmission Interrupt Enabling Timing ............ 388
Transmission Interrupt Generation and Flag Set
Timing............................................... 357
Transmission Interrupt Request Generation
Timing............................................... 358
Timing Chart
Pin Timing Chart ............................................. 541
TMCSR
Bit Configuration of Control Status Register
(TMCSR) ........................................... 394
TMR
Bit Configuration of 16-Bit Timer Register
(TMR) ............................................... 397
TMRLR
Bit Configuration of 16-Bit Reload Register
(TMRLR)........................................... 398
Transfer
Acceptance and Transfer of Transfer
Request .............................................. 230
Block Transfer................................................. 223
Burst Two-Cycle Transfer ................................ 222
DMA Transfer and Interrupt ............................. 228
Notes on DMA Transfer During the Sleep
Mode ................................................. 236
Notes on Using DMA Transfer.......................... 389
INDEX
Occurrence of Transfer Stop Request from Peripheral
Circuit................................................ 234
Operation Flow of Block Transfer ..................... 239
Operation Flow of Burst Transfer ...................... 240
Operation of Data in Two-cycle Transfer ........... 241
Selecting the Transfer Sequence ........................ 222
Step Transfer ................................................... 223
Step/Block Two-Cycle Transfer ........................ 223
Transfer Activation .......................................... 229
Transfer Address.............................................. 220
Transfer Count and Transfer Termination........... 220
Transfer Count Register and Reload
Operation ........................................... 227
Transfer Data Format ............................... 368, 371
Transfer Mode ................................................. 219
Transfer Termination........................................ 233
Transfer Type .................................................. 219
Transfer Count Register
Transfer Count Register and Reload
Operation ........................................... 227
Transfer Data Format
Transfer Data Format ............................... 368, 371
Transfer Request
Acceptance and Transfer of Transfer
Request .............................................. 230
Transfer Termination
Transfer Count and Transfer Termination........... 220
Transfer Termination........................................ 233
Transmission
Data Transmission/Reception
with Message RAM............................. 297
Message Transmission...................................... 299
Reception/Transmission Data Register
(RDR/TDR)........................................ 341
Setting of Transmission Message Object ............ 300
Transmission Interrupt Enabling Timing ............ 388
Transmission Interrupt Generation and Flag Set
Timing ............................................... 357
Transmission Interrupt Request Generation
Timing ............................................... 358
Transmission Interrupts .................................... 352
Transmission Operation .................................... 369
Transmission Priority ....................................... 299
Updating a Transmission Message Object .......... 301
Transmission Interrupt
Transmission Interrupt Enabling Timing ............ 388
Transmission Interrupt Generation and Flag Set
Timing ............................................... 357
Transmission Interrupt Request Generation
Timing ............................................... 358
Trap
Coprocessor Absent Trap.................................... 65
Coprocessor Error Trap ...................................... 65
Operation of Step Trace Trap .............................. 64
TRG
PPG Start Register (TRG) .................................443
Two-cycle Transfer
Burst Two-Cycle Transfer .................................222
Operation of Data in Two-cycle Transfer ............241
Step/Block Two-Cycle Transfer .........................223
Types
I/O Circuit Types................................................21
U
UART
Block Diagram of LIN-UART ...................325, 326
Interrupts of LIN-UART ...................................351
LIN-UART as LIN Master ................................374
LIN-UART as LIN Slave ..................................375
LIN-UART as Master Device ............................385
LIN-UART as Slave Device ..............................386
LIN-UART Baud Rate Selection ........................359
LIN-UART Operation Modes ............................323
LIN-UART Pin Direct Access ...........................378
Operations of LIN-UART..................................366
Registers of LIN-UART ....................................330
UART with LIN Function (7 Channels) ..................3
Undefined Instruction Exception
Operation of Undefined Instruction
Exception..............................................64
Underflow
Underflow Operation ........................................400
Underflow Operation
Underflow Operation ........................................400
Unused Input Pins
Processing Unused Input Pins ..............................24
Updating
Updating a Transmission Message Object ...........301
User Stack Pointer
USP (User Stack Pointer) ....................................43
USP
USP (User Stack Pointer) ....................................43
V
Various Timers
Various Timers.....................................................3
Vector Table
EIT Vector Table................................................56
W
Wait Time
Wait Time after Changing PLL Multiplication
Rate......................................................73
Wait Time after Enabling PLL Operation..............73
Wait Time after Power-on ...................................73
Wait Time after Returning from Stop Mode ..........74
Wait Time after Setting Initialization....................73
617
INDEX
Wait Time after Switching from the Sub Clock to the
Main Clock........................................... 74
Watchdog Reset Generation Postpone Register
WPR: Watchdog Reset Generation Postpone
Register ................................................ 91
Watchdog Timer Control Register
RSRR: Reset Source Register/Watchdog Timer
Control Register .................................... 79
Word Alignment
Word Alignment ................................................ 46
WPR
WPR: Watchdog Reset Generation Postpone
Register ................................................ 91
618
Write
FR-CPU Programming Mode (Read/Write Enabled in
16 Bits) .............................................. 500
Writing
Setting of the Pause by Writing to the Control Register
(Set Each Channel Independently or All the
Channels Simultaneously).................... 232
Writing to Flash ................................................. 25
WTCR
Timer Control Register (WTCR) ....................... 455
CM71-10139-5E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91210 Series
HARDWARE MANUAL
March 2010 the fifth edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Sales Promotion Dept.
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