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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM71-10149-2E
FR60
32-BIT MICROCONTROLLER
MB91460N Series
HARDWARE MANUAL
FR60
32-BIT MICROCONTROLLER
MB91460N Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
MB91460N series is a line of the FUJITSU MICROELECTRONICS's general-purpose 32-bit RISC
microcontrollers designed for embedded control applications such as consumer devices and vehicle system,
which require high-speed real-time processing. MB91460N series uses the FR60 CPU compatible with the
FR family CPUs.
MB91460N series contains the LIN-USART and CAN controller.
■ Trademark
FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU MICROELECTRONICS
Limited.
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
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•
•
•
•
•
•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device;
FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such
information. When you develop equipment incorporating the device based on such information, you must assume any
responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any
damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement
of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright © 2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
ii
CONTENTS
Chapter 1
1.1
1.2
1.3
1.4
Chapter 2
2.1
2.2
2.3
2.4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.1
5.2
59
60
61
61
61
62
63
64
65
CPU Registers ............................................................................................ 67
General-purpose Registers................................................................................................................ 67
Dedicated Registers .......................................................................................................................... 67
Chapter 6
6.1
6.2
6.3
6.4
19
21
40
45
46
47
50
56
CPU Architecture ....................................................................................... 59
Overview............................................................................................................................................
Features.............................................................................................................................................
CPU ...................................................................................................................................................
32-bit/16-bit Bus Converter................................................................................................................
Harvard/Princeton Bus Converter......................................................................................................
Instruction Overview ..........................................................................................................................
Data Structure....................................................................................................................................
Word Alignment .................................................................................................................................
Addressing.........................................................................................................................................
Chapter 5
13
13
15
17
MB91460N Series Basic Information........................................................ 19
Memory space ...................................................................................................................................
I/O Map ..............................................................................................................................................
INTERRUPT SOURCE TABLE .........................................................................................................
PACKAGE DIMENSION ....................................................................................................................
PIN ASSIGNMENT ............................................................................................................................
PIN DESCRIPTION ...........................................................................................................................
I/O CIRCUIT TYPE ............................................................................................................................
Pin State Table ..................................................................................................................................
Chapter 4
1
5
7
8
MB91460N Series Overview ...................................................................... 13
DESCRIPTION ..................................................................................................................................
FEATURES........................................................................................................................................
MB91460N Series Product Lineup ....................................................................................................
Block Diagram ...................................................................................................................................
Chapter 3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Introduction .................................................................................................. 1
PRECAUTIONS FOR HANDLING THE DEVICES..............................................................................
HANDLING DEVICES .........................................................................................................................
NOTES ON DEBUGGER ....................................................................................................................
How to Use This Document .................................................................................................................
EIT: Exceptions, Interrupts and Traps ..................................................... 75
Overview............................................................................................................................................
Features.............................................................................................................................................
EIT Trigger.........................................................................................................................................
Context saving ...................................................................................................................................
iii
75
75
75
76
6.5
6.6
6.7
6.8
6.9
6.10
Recovery from EIT handler................................................................................................................
EIT Interrupt Level .............................................................................................................................
EIT Vector Table................................................................................................................................
Multiple EIT Processing .....................................................................................................................
Operation ...........................................................................................................................................
Caution ..............................................................................................................................................
Chapter 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.1
8.2
8.3
Reset ........................................................................................................... 93
Standby..................................................................................................... 107
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Settings............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 11
11.1
11.2
11.3
Device State Transition ............................................................................. 89
Overview............................................................................................................................................ 93
Features............................................................................................................................................. 93
Configuration ..................................................................................................................................... 94
Registers............................................................................................................................................ 95
INITX Pin Input (INIT: Settings Initialization Reset) ......................................................................... 100
Watchdog Reset (INIT: Settings Initialization Reset)....................................................................... 102
Software Reset (RST: Operation Initialization Reset)..................................................................... 103
Reset Operation Modes................................................................................................................... 104
MCU Operation Mode...................................................................................................................... 105
Caution ............................................................................................................................................ 106
Chapter 10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
85
85
85
86
87
88
88
Overview............................................................................................................................................ 89
Features............................................................................................................................................. 89
State Transition Diagram ................................................................................................................... 90
Chapter 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Branch Instruction ..................................................................................... 85
Overview............................................................................................................................................
List of Delayed Branching instructions...............................................................................................
Operation of Delayed Branching Instructions ....................................................................................
Some Examples of Delayed Branching Instructions..........................................................................
Restrictions on Branch Instruction with Delay Slot ............................................................................
Branch Instruction without Delay Slot ................................................................................................
List of Non-Delayed Branch Instructions ...........................................................................................
Chapter 8
76
77
77
78
80
83
107
107
108
109
111
113
113
116
Memory Controller ................................................................................... 117
Overview.......................................................................................................................................... 117
FLASH Interface .............................................................................................................................. 117
General-purpose RAM..................................................................................................................... 118
iv
11.4
11.5
11.6
instruction cache while writing to the FLASH memory..................................................................... 118
FLASH Access Timing Setting......................................................................................................... 120
Registers.......................................................................................................................................... 121
Chapter 12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Settings............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 13
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Clock Modulator....................................................................................... 157
Timebase Counter.................................................................................... 171
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Settings............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 17
17.1
17.2
17.3
CAN Clock Prescaler ............................................................................... 153
Overview.......................................................................................................................................... 157
Clock Modulator Registers............................................................................................................... 158
Application Note............................................................................................................................... 169
Chapter 16
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
143
143
143
144
148
149
151
Overview.......................................................................................................................................... 153
Features........................................................................................................................................... 153
Registers.......................................................................................................................................... 154
Chapter 15
15.1
15.2
15.3
129
129
130
131
136
138
139
141
Main PLL Interface ................................................................................... 143
Overview..........................................................................................................................................
Features...........................................................................................................................................
Frequency calculation......................................................................................................................
Registers..........................................................................................................................................
Recommended Settings ..................................................................................................................
Clock Auto-Gear Up/Down ..............................................................................................................
Caution ............................................................................................................................................
Chapter 14
14.1
14.2
14.3
Clock Control ........................................................................................... 129
171
171
173
174
176
180
181
183
Timebase Timer........................................................................................ 185
Overview.......................................................................................................................................... 185
Features........................................................................................................................................... 185
Configuration ................................................................................................................................... 186
v
17.4
17.5
17.6
17.7
17.8
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 18
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
19.1
19.2
19.3
19.4
19.5
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
22.1
22.2
22.3
211
211
212
213
214
215
216
218
Interrupt Control ...................................................................................... 219
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 22
205
206
207
209
210
Main Oscillation Stabilization Timer ...................................................... 211
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 21
195
195
196
197
200
202
203
204
Hardware Watchdog Timer ..................................................................... 205
Overview..........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Functions .........................................................................................................................................
Caution ............................................................................................................................................
Chapter 20
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
Software Watchdog Timer....................................................................... 195
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 19
187
189
190
191
193
219
219
220
221
226
227
227
228
External Interrupt ..................................................................................... 229
Overview.......................................................................................................................................... 229
Features........................................................................................................................................... 229
Configuration ................................................................................................................................... 230
vi
22.4
22.5
22.6
22.7
22.8
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 23
23.1
23.2
23.3
23.4
23.5
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
26.1
26.2
26.3
26.4
26.5
27.1
27.2
293
295
296
304
324
I/O Ports .................................................................................................... 325
I/O Ports Functions .......................................................................................................................... 325
Port Register Settings...................................................................................................................... 328
Chapter 28
28.1
28.2
283
283
284
285
287
289
290
291
MPU / EDSU .............................................................................................. 293
Overview..........................................................................................................................................
Features...........................................................................................................................................
Break Functions...............................................................................................................................
Registers..........................................................................................................................................
Quick Reference ..............................................................................................................................
Chapter 27
279
279
279
280
280
281
281
281
Bit Search ................................................................................................. 283
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 26
241
243
261
275
277
Delayed Interrupt ..................................................................................... 279
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 25
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
DMA Controller......................................................................................... 241
Overview of the DMA Controller (DMAC) ........................................................................................
DMA Controller (DMAC) Registers ..................................................................................................
DMA Controller (DMAC) Operation .................................................................................................
Operation Flowcharts.......................................................................................................................
Data Bus ..........................................................................................................................................
Chapter 24
233
235
236
236
239
LIN-USART................................................................................................ 345
Overview.......................................................................................................................................... 345
LIN-USART Configuration ............................................................................................................... 348
vii
28.3
28.4
28.5
28.6
28.7
28.8
LIN-USART Pins..............................................................................................................................
LIN-USART Registers......................................................................................................................
LIN-USART Interrupts......................................................................................................................
LIN-USART Baud Rates ..................................................................................................................
LIN-USART Operation .....................................................................................................................
Notes on using LIN-USART.............................................................................................................
Chapter 29
29.1
29.2
29.3
29.4
30.1
30.2
30.3
30.4
30.5
32.1
32.2
32.3
32.4
32.5
32.6
32.7
32.8
33.1
33.2
33.3
33.4
33.5
33.6
491
491
492
493
496
498
499
502
Input Capture Unit (ICU) .......................................................................... 503
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Settings............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 33
429
430
431
436
474
Free-Run Timer (FRT) .............................................................................. 491
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration Diagram.....................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 32
405
407
423
425
CAN Controller ......................................................................................... 429
Overview..........................................................................................................................................
Block diagram of the CAN Controller...............................................................................................
CAN Registers .................................................................................................................................
CAN register function.......................................................................................................................
Functional Description .....................................................................................................................
Chapter 31
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
I2C Controller............................................................................................ 405
Overview..........................................................................................................................................
I2C Interface Registers ....................................................................................................................
I2C Interface Operation....................................................................................................................
Programming Flow Charts ...............................................................................................................
Chapter 30
352
353
370
375
382
401
503
503
504
505
508
510
511
514
Output Compare Unit (OCU) ................................................................... 515
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration Diagram.....................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Settings............................................................................................................................................
viii
515
515
516
517
521
523
33.7
33.8
Q & A ............................................................................................................................................... 524
Caution ............................................................................................................................................ 527
Chapter 34
34.1
34.2
34.3
34.4
34.5
34.6
34.7
34.8
Chapter 35
35.1
35.2
35.3
35.4
35.5
35.6
35.7
35.8
37.1
37.2
37.3
37.4
37.5
37.6
37.7
38.1
38.2
38.3
38.4
575
575
576
580
587
594
596
601
A/D Converter (ADC)................................................................................ 603
Overview of A/D Converter ..............................................................................................................
Block Diagram of A/D Converter......................................................................................................
Registers of A/D Converter..............................................................................................................
Operation of A/D Converter .............................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 38
549
549
551
553
561
565
566
573
Up/Down Counter (UDC) ......................................................................... 575
Overview..........................................................................................................................................
Feature ............................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 37
529
529
530
532
536
541
543
547
Programmable Pulse Generator (PPG) .................................................. 549
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
Chapter 36
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
Reload Timer (RLT).................................................................................. 529
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q & A ...............................................................................................................................................
Caution ............................................................................................................................................
603
605
606
615
618
620
624
Clock Monitor ........................................................................................... 627
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Register ...........................................................................................................................................
ix
627
627
628
629
38.5
38.6
38.7
38.8
Operation .........................................................................................................................................
Settings............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 39
39.1
39.2
39.3
39.4
39.5
39.6
39.7
39.8
40.1
40.2
40.3
Fixed Mode-Reset Vector / BOOT-ROM ................................................. 653
Flash Memory........................................................................................... 655
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Access Modes .................................................................................................................................
Flash Memory Mode ........................................................................................................................
Auto Program Algorithms.................................................................................................................
Caution ............................................................................................................................................
Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems ............................................
Chapter 43
43.1
43.2
43.3
43.4
Low Voltage Reset/Interrupt ................................................................... 649
Overview.......................................................................................................................................... 653
Chapter 42
42.1
42.2
42.3
42.4
42.5
42.6
42.7
42.8
42.9
635
635
636
637
642
644
645
647
Overview.......................................................................................................................................... 649
Features........................................................................................................................................... 649
Registers.......................................................................................................................................... 650
Chapter 41
41.1
Real-Time Clock (RTC) ............................................................................ 635
Overview..........................................................................................................................................
Features...........................................................................................................................................
Configuration ...................................................................................................................................
Registers..........................................................................................................................................
Operation .........................................................................................................................................
Setting..............................................................................................................................................
Q&A .................................................................................................................................................
Caution ............................................................................................................................................
Chapter 40
631
632
632
633
655
655
656
664
664
665
666
675
676
Flash Security .......................................................................................... 679
Overview..........................................................................................................................................
Flash Security Vectors.....................................................................................................................
Refetching Security Vectors ............................................................................................................
Register ...........................................................................................................................................
x
679
680
684
685
Main changes in this edition
Page
652
Changes (For details, refer to main body.)
Chapter 40 Low Voltage Reset/Interrupt
40.3.1 LV Detection Control Registers
Changed the trigger level on table of [bit7 to bit4].
(+/- 0.1V→ +/- 0.15V)
Changed the table of [bit3 to bit0].
(added the column for MB91F463NC)
655
Chapter 42 Flash Memory
42.2 Features
Corrected "(1) 32-bit CPU mode".
CPU reads, writes and executes → CPU reads and executes
658
Chapter 42 Flash Memory
42.3.1 Constitution with the CPU mode
Added Table 42.3-2.
(added the address map for MB91F463NC)
Added Figure 42.3-3.
(added the address map for MB91F463NC)
660
663
Chapter 42 Flash Memory
42.3.2 Address conversion from CPU
Mode to Flash Programming Mode
Added " • MB91F463NC".
(added address conversion formula for MB91F463NC)
664
Chapter 42 Flash Memory
42.5.1 Access from the CPU
■ 32-bit CPU mode (read/execute)
Corrected title and explanation.
(read/write/execute) → (read/execute)
Deleted "This mode allows data erase/write.".
"Programs cannot be executed in Flash memory while the Flash is
being written/erased."
→
"Programs cannot write to Flash memory, and cannot erase to
Flash memory."
Deleted explanation about auto algorithms.
667
Chapter 42 Flash Memory
42.7.1 Command Operation
Added Table 42.7-2.
(added list of commands for MB91F463NC)
675
Chapter 42 Flash Memory
42.8 Caution
Added "• Restrictions on Data Polling Flag (DQ7)".
Chapter 42 Flash Memory
42.9 Restrictions on Data Polling Flag
(DQ7) and How to Avoid Problems
Added "42.9 Restrictions on Data Polling Flag (DQ7) and How to
Avoid Problems".
Chapter 43 Flash Security
43.2.1 Vector addresses
Added Figure 43.2-2.
(Added security vector address of MB91F463NC)
676 to 678
680
The vertical lines marked in the left side of the page show the changes.
xi
xii
Chapter 1 Introduction
1.1
MB91460N series
Chapter 1
Introduction
1.1 PRECAUTIONS FOR HANDLING THE DEVICES
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected
by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page
describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability
from your FUJITSU semiconductor devices.
■ Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
• Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
• Recommended Operating Conditions
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the
data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to
power supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such over voltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause
large current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such
pins should be connected through an appropriate resistance to a power supply pin or ground pin.
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
1
Chapter 1 Introduction
1.1
MB91460N series
• Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
Note: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(a) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(b) Be sure that abnormal current flows do not occur during the power-on sequence.
• Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and
standards in the design of products.
• Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
• Precautions Related to Usage of Devices
FUJITSU semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, submarine
repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with
FUJITSU sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
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Chapter 1 Introduction
1.1
MB91460N series
■ Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mounting type. In either case, quality
assurance of heat resistance are applied for mounting under the Fujitsu's recommended conditions only at the
soldering stage. For detailed information on mount conditions, contact the sales representative.
• Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder.
In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the
absolute ratings for storage temperature. Mounting processes should conform to FUJITSU recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface
treatment of socket contacts and IC leads be verified before mounting.
• Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch
results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder
bridges.
You must use appropriate mounting techniques. FUJITSU recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with FUJITSU ranking of recommended conditions.
• Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental
conditions will cause absorption of moisture. During mounting, the application of heat to a package that has
absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to
crack. To prevent, do the following:
(a) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(b) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between +5 °C to +30 °C.
(c) When necessary, FUJITSU packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for
storage.
(d) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
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Chapter 1 Introduction
1.1
MB91460N series
• Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the
FUJITSU recommended conditions for baking.
• Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(a) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion
generation may be needed to remove electricity.
(b) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(c) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the
level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other
measures to minimize shock loads is recommended.
(d) Ground all fixtures and instruments, or protect with anti-static measures.
(e) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
■ Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely
affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to
protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users
should provide shielding as appropriate.
(5) Smoke, Flame
Note: Plastic molded devices are flammable, and therefore should not be used near combustible substances.
If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU products in other special environmental conditions should consult
with FUJITSU sales representatives.
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Chapter 1 Introduction
1.2
MB91460N series
1.2 HANDLING DEVICES
• Power supply pins
Because there are multiple VCC and VSS pins, respective pins at the same potential are interconnected to
prevent malfunctions such as latch-up. However, you must connect the pins externally to the power supply
and ground lines to reduce the electro-magnetic emission levels, to prevent abnormal operation of strobe
signals caused by the rise in the ground level, and to conform to the total output current rating. Furthermore,
the current supply source should be connected to the VCC and VSS pins of the device at a low impedance.
It is recommended to connect a ceramic bypass capacitor of approximately 0.1 μF as a bypass capacitor
between the VCC and VSS near this device.
• Crystal oscillator circuit
Noise in proximity to the X0 and X1 pins can cause the device to malfunction. Printed circuit boards should
be designed so that the X0 and X1 pins, crystal oscillator (or ceramic oscillator), and bypass capacitors
connected to ground are located near the device and ground.
It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins are
surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
• Mode pins (MOD0 to MOD3)
Connect them directly to VCC or VSS. To prevent the device from entering test mode accidentally due to
noise, minimize the lengths of the patterns between each mode pin and VCC or VSS on the printed circuit
board as much as possible and connect them at a low impedance. When used pulling down, design your
circuit not to generate noises with a resistance 1 kΩ or less. Test your circuit and confirm that there is no
problem.
• Operation at power-on
At power-on, it is necessary to make the pin INITX “L” level.
Maintain the “L” level input to the INITX pin for the duration of the stabilization wait time immediately after the
power on to ensure the stabilization wait time as required by the oscillator circuit.
• Note on oscillator input at power-on
At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed.
• Built-in regulator
As this series includes built-in step-down regulators, always connect a bypass capacitor of 4.7 μF or more to
the C pin for use by the regulator.
• Notes on power on/off
Connect/disconnect the power supply pins when power on/off, or turn on/off in the following order.
Power on : VCC → AVCC, AVRH
Power off : AVCC, AVRH → VCC
• Precautions for the STOP mode
Set 1 to the bit 0 (OSCD1) of STCR register. When shifting to the STOP mode, a regulator switches to the
stand-by regulator (for low-consumption current).
Due to the limited drive current, stop the (programming/erasing) access to the A/D converter and Flash
before shifting to the STOP mode.
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MB91460N series
• Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
• Notes on using external clock
When using the external clock, as a general rule you should simultaneously supply X0 and X1 pins. And
also, the clock signal to X0 should be supplied a clock signal with the reverse phase to X1 pins. However, in
this case the stop mode (oscillation stop mode) must not be used.
• Example of using external clock (normal)
X0
X1
Note : Stop mode (oscillation stop mode) cannot be used.
• Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller
may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this
self-running operation cannot be guaranteed.
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Chapter 1 Introduction
1.3
MB91460N series
1.3 NOTES ON DEBUGGER
• Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent
the main routine and the handlers for low priority level interrupts from being executed (For example, if the
time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of
the time-base timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs
debugging.
• Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as
the target of the hardware break (including an event breaks).
• Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not
set the access to the areas containing the address of system stack pointer as a target of data event break.
• Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the
following exception handling may result in execution breaking in an interrupt handling routine or the
displayed values of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1) The following behavior may occur if any of the following occurs in the instruction immediately after a
DIVOU/DIVOS instruction:
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks
due to a data event or from the emulator menu.
- D0 and D1 flags are updated in advance.
- An EIT handling routine (user interrupt/NMI or emulator) is executed.
- Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as those in 1).
2) The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to
enable a user interrupt or NMI source while that interrupt is in the active state.
- The PS register is updated in advance.
- An EIT handling routine (user interrupt/NMI or emulator) is executed.
- Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in 1).
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Chapter 1 Introduction
1.4
MB91460N series
1.4 How to Use This Document
■ Main terminology: This table shows main terminology used for FR-family CPU.
Term
I-bus
D-bus
F-bus
R-bus
X-bus
Main clock
(CLKMAIN)
Sub clock
(CLKSUB)
RC Clock
(CLKRC 100kHz)
Base clock
(Φ)
CPU clock
(CLKB)
Peripheral clock
(CLKP)
External bus clock
(CLKT)
CAN clock
(CLKCAN)
Main clock mode
Sub clock mode
Main-RUN
Main-SLEEP
Main-STOP
Sub-RUN
Oscillation
stabilization time
Main clock
oscillation
stabilization wait
8
Meaning
32-bit-wide bus for internal instruction.
Since FR-family CPU series employ internal Harvard architecture, instruction and data are independent
busses. For I-bus, Harvard/Princeton-bus-converter is connected. Also connected to I-bus is EDSU/MPU.
Internal 32-bit-wide data bus.
For D-bus, bit search module, Harvard/Princeton-bus-converter, R-bus interface (32-bit⇔16-bit Busconverter), CAN modules and EDSU/MPU are connected.
Internal 32-bit-wide bus.
F-bus is connected to embedded Flash/ROM and embedded RAM.
Internal 16-bit-wide data bus.
R-bus is connected to D-bus via R-bus-converter. For R-bus, peripheral function, I/O, clock generator and
interrupt controller are connected.
32-bit-wide address and data bus. Via bus-converter for external bus, it accesses to external bus.
This is a clock which acts as a benchmark for LSI operation triggered by high-speed-side oscillation.
This is connected to Main clock oscillation stabilization timer and it can be source for base clock.
This is a clock which acts as a benchmark for LSI operation triggered by low-speed-side oscillation.
This is connected to sub oscillation stabilization timer, real-time clock and it can be source for base clock.
This cannot use in the MB91460N series.
This is a clock which is connected to the RC Oscillator (Typical value 100kHz).
This is connected to Real time clock, watchdog and it can be source for base clock.
At the maximum speed, base clock has the same cycle as source oscillation. Clock source can be
CLKMAINPLL, Main clock divided by 2 or CLKCSV.
Base clock is basis clock which generates CLKB, CLKP and CKLT in the clock generator.
CPU clock is the clock which is referred by CPU, embedded ROM, embedded RAM, bit search module and
internal bus (I-bus, D-bus, F-bus and X-bus) operations. Generated from the base clock in the clock generator.
Peripheral clock is the clock which is referred by each peripheral function (peripheral functions other than bit
search module and CAN) connected to R-bus and R-bus, clock control, interrupt controller, I/O port and
external interrupt input operations. Generated from the base clock in the clock generator.
External bus clock is the clock which is referred by external expansion bus interface connected to X-BUS and
external clock output operations. Generated from the base clock in the clock generator.
CAN clock is the clock which is referred by the CAN modules. Generated from the non modulated PLL
output clock to ensure operation within CAN network oscillation tolerances.
Mode which runs based on Main clock. This Main clock mode has status such as Main-RUN, Main-SLEEP,
Main-STOP, oscillation stabilization wait RUN, oscillation stabilization wait reset and program reset.
Mode which runs based on Sub clock. This Sub clock mode has status such as Sub-RUN, Sub-SLEEP, SubSTOP, Sub clock oscillation stabilization wait RUN and program reset.
This cannot use in the MB91460N series.
Main-RUN is the state which is in Main clock mode and also all circuits are operable.
Main-SLEEP is the state which is in Main clock mode and just the peripherals are operable.
Main-STOP is the state which is in Main clock mode and all circuits are stopped.
Sub-RUN is the state which is in Sub clock mode and also all circuits are operable.
This cannot use in the MB91460N series.
Upon the reset (INITX, RST), return from STOP, return from PLL abnormal operation, generation of
watchdog and during Main clock stop, it takes oscillation stabilization time for Main clock. Time base timer
counts the time.
Wait time until Main clock oscillates after Main clock stops in Sub clock mode.
Main clock oscillation stabilization timer counts the time.
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Chapter 1 Introduction
1.4
MB91460N series
■ Access size and address position
Offset
Address
+0
RCR1 [W]
B,H,W
00000000
CCRH0 [R/W]
B,H,W
00000000
CCRH1 [R/W]
B,H,W
00000000
0000B0H
0000B8H
0000B8H
Register name
Write-only
Read-only
Address offset value/Register name
+1
+2
RCR0 [W]
B,H,W
00000000
CCRL0 [R/W]
B,H,W
00001000
CCRL1 [R/W]
B,H,W
00001000
UDCR1 [R]
B,H,W
00000000
-
+3
UDCR0 [R]
B,H,W
00000000
CSR0 [R/W]
B,H,W
00000000
CSR1 [R/W]
B,H,W
00000000
Read/write
Block
Up/down
counter 0,1
Initial value
Byte access, Half-word access, and Word access are allowed.
There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note
that some registers have restricted access. For more information, see "3.3.2 I/O Map (Page No.21)" or "Detail
Description of Register" in each chapter.
B,H,W
B
H
W
B, H
H,W
: Byte access, Half-word access, and Wordaccess are allowed.
: Byte access (Be sure to access by Byte.)
: Half-word access (Be sure to access by Half-word.)
: Word access (Be sure to access by Word.)
: Byte access, Half-word access only (Word access is not allowed.)
: Half-word access, Word access only (Byte access is not allowed.)
Reference
The following describes address position to access.
• In Word access, address becomes multiple of 4. (Lowest order 2 bits mandatorily become "00".)
• In Half-word access, address becomes multiple of 2. (Lowest order 1 bit mandatorily becomes "0".)
• In Byte access, address will not be changed.
Therefore, for example, make RCR0 register to use Half-word access,
For address 0B0H, RCR1+RCR0 register is accessed.
(When address offset is +1 and +2, (Example: RCR0+UDCR1) Half-word access is not allowed.)
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Chapter 1 Introduction
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MB91460N series
■ About access size and bit position
Register name Register mark Target peripheral device Address
Access size
Bit position
(1) Counter control register (Higher byte)
This is the register (higher byte) which controls up/down counter operation.
CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word)
CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word)
15
M16E/Reserved
0
R/W *
14
CDCF
0
R/W
13
CFIE
0
R/W
12
CLKS
0
R/W
11
CMS1
0
R/W
10
CMS0
0
R/W
8
CES0
0
R/W
9
CES1
0
R/W
bit
Initial value
Attribute
bit15: Enable 16-bit mode
Enable 16-bit mode
M16E (CCRH0 only)
0
8-bit x 2-channel mode (8-bit mode)
1
16-bit x 1-channel mode (16-bit mode)
*: CCRH1: Reserved (Always write 0 for writing. The read value is indeterminate).
When access size changes, bit position changes.
• In the case that address offset value is +0 (Example: CCRH0 register)
Access size
Byte
Address
0B4H+0H
07
06
05
04
03
02
01
00
Half-word
0B4H+0H
15
14
13
12
11
10
09
08
Word
0B4H+0H
31
30
29
28
27
26
25
24
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
Bit name
Bit position
• In the case that address offset value is +1 (Example: CCRL0 register)
Access size
Byte
Address
0B4H+1H
07
06
05
04
03
02
01
00
Half-word
0B4H+0H
07
06
05
04
03
02
01
00
Word
0B4H+0H
23
22
21
20
19
18
17
16
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
Bit name
Bit position
• In the case that address offset value is +2 (Example: UDCR1 register)
Access size
Byte
Address
0B0H+2H
07
06
05
04
03
02
01
00
Half-word
0B0H+2H
15
14
13
12
11
10
09
08
Word
0B0H+0H
15
14
13
12
11
10
09
08
D15
D14
D13
D12
D11
D10
D9
D8
Bit name
Bit position
• In the case that address offset value is +3 (Example: UDCR 1 register)
Access size
Byte
Address
0B0H+3H
07
06
05
04
03
02
01
00
Half-word
0B0H+2H
07
06
05
04
03
02
01
00
Word
0B0H+0H
07
06
05
04
03
02
01
00
D7
D6
D5
D4
D3
D2
D1
D0
Bit name
10
Bit position
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Chapter 1 Introduction
1.4
MB91460N series
■ Meaning of Bit Attribute Symbols
R
W
RM
R0
R1
W0
W1
(RM0)
(RM1)
RX
WX
X
-
: Readable
: Writable
: Reading operation during read/modify/write operation.
"/" (Slash) R/W: Readable and writable. (The read value is the value written.)
"," (comma) R,W: Values are different between read and write. (The read value is different from
the value written.)
: The read value is "0".
: The read value is "1".
: Always write "0".
: Always write "1".
: read/modify/write operation reads "0".
: read/modify/write operation reads "1".
: The read value is indeterminate. (Reserved bit or undefined bit)
: Writing does not affect the operation. (Undefined bit)
: Don’t care
: Holds it’s value
• Example of how R/W is used
• R/W
: Readable and writable. (The read value is the value written.)
• R,W
: Readable and writable. (The read value and written value are different.)
• R,RM/W
: Readable and writable. (The read value and written value are different. Read/modify/write
command reads the value written.) Example: port data register
• R(RM1),W
: Readable and writable. (The read value and written value are different. Read/modify/write
command reads 1.) Example: interrupt flag
• R/WX
: Read-only (Read-only. Writing does not affect the operation.)
• R1,W
: Write-only (Write-only. The read value is 1.)
• R0,W
: Write-only (Write-only. The read value is 0.)
• RX,W
: Write-only (Write-only. The read value is indeterminate.)
• R/W0
: Reserved bit (The written value is 0. The read value is the value written.)
• R0/W0
: Reserved bit (The written value is 0. The read value is 0.)
• R1,W0
: Reserved bit (The written value is 0. The read value is 1.)
• RX,W0
: Reserved bit (The written value is 0. The read value is indeterminate.)
• R/W1
: Reserved bit (The written value is 1. The read value is the value written.)
• R1/W1
: Reserved bit (The written value is 1. The read value is 1.)
• R0,W1
: Reserved bit (The written value is 1. The read value is 0.)
• RX,W1
: Reserved bit (The written value is 1. The read value is indeterminate.)
• RX/WX
: Undefined bit (The read value is indeterminate. Writing does not affect the operation.)
• R0/WX
: Undefined bit (The read value is 0. Writing does not affect the operation.)
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Chapter 1 Introduction
1.4
12
MB91460N series
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 2 MB91460N Series Overview
2.1
MB91460N series
Chapter 2
MB91460N Series Overview
2.1 DESCRIPTION
MB91460N series is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. MB91460N series uses the FR60 CPU which is compatible with the FR* CPUs.
MB91460N series contains the LIN-USART and CAN controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
Note: MB91F463NB includes the improved features of MB91F463NA.
Please select MB91F463NB for the future development.
2.2 FEATURES
■ FR60 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• Maximum operating frequency: 80 MHz (oscillator frequency: 4 MHz; oscillator frequency multiplier: 20 (PLL
clock multiplication method))
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed: 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions:
Instructions suitable for embedded applications
• Function entry/exit instructions and register data multi load store instructions: Instructions supporting C
language
• Register interlock function: Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS saving): 6 cycles (16 priority levels)
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instructions compatible with the FR family
■ Internal peripheral resources
•
•
•
•
Flash memory capacity: 288 Kbytes
Internal RAM capacity: 8 Kbytes (Data RAM) + 2 Kbytes (Instruction/data RAM)
General-purpose port: Maximum 48 ports
DMAC (DMA Controller)
Maximum of 5 channels for able to operate simultaneously
2 transfer sources (internal peripheral/software)
Activation source can be selected by programs
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (burst transfer/step transfer/block transfer)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer capable (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
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Chapter 2 MB91460N Series Overview
2.2
MB91460N series
• A/D converter (sequential comparison)
10-bit resolution: 8 channels
Conversion time: 1 μs (using at 5 V) , 3 μs (using at 3.3 V)
• External interrupt inputs: 10 channels
• Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first "0", "1" or changed bit in a word
• LIN-USART (full duplex double buffer): 4 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C bus interface (Supports 400 kbps): 2 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): 2 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• 16-bit PPG timer: 8 channels
• 16-bit reload timer: 4 channels+1 channel (exclusive A/D converter)
• 16-bit free-run timer: 4 channels
• Input capture: 4 channels
• Output compare: 4 channels
• 8/16-bit up/down counter: 2 channels (8-bit)/1channel (16-bit)
• Watchdog timer
• Real-time clock
• Low-power consumption mode: Sleep/stop mode function
• Package: LQFP-64 (FPT-64P-M23)
• CMOS 0.18 μm technology
• 3.3 V only power supplies or 5 V only power supplies
• Operating temperature range: - 40°C to + 85°C (using at 5 V)
- 40°C to + 105°C (using at 3.3 V)
14
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 2 MB91460N Series Overview
2.3
MB91460N series
2.3 MB91460N Series Product Lineup
Table 2.3-1 MB91460N Series Product Lineup (1 / 2)
Feature
Core frequency
MB91V460A
MB91F463N
80MHz
80MHz
Resource frequency
40MHz
40MHz
Technology
0.35μm
0.18μm
yes
yes
yes (disengageable)
yes
Watchdog
Watchdog (RC osc. based)
Bit Search
yes
yes
Reset input (INITX)
yes
yes
Clock Modulator
yes
yes
Low Power Mode
yes
yes
DMA
5 ch
5 ch
MAC (DSP)
no
no
MMU/MPU
MPU* (16 ch)
MPU* (4 ch)
Emulation SRAM 32bit read data
256K + 32KByte
n.a.
yes
D-bus RAM
64 KByte
8 KByte
I/D-bus RAM
64 KByte
2 KByte
Flash (Instruction) Cache
16 KByte
4 KByte
Boot-ROM / BI-ROM
4 KByte
4 KByte (BI-ROM)
Real-Time Clock (RTC)
1 ch
1 ch
Free-Run Timer
8 ch
4 ch
ICU
8 ch
4 ch
OCU
8 ch
4 ch
Flash
Flash Protection
Reload Timer
8 ch
5 ch
PPG 16-bit
16 ch
8 ch
PFM 16-bit
1 ch
no
Sound Generator
1 ch
no
4 ch (8-bit) / 2 ch (16-bit)
2 ch (8-bit) / 1 ch (16-bit)
Up/Down Counter (8/16-bit)
C_CAN
LIN-USART
2
I C (400k)
FR external bus
6 ch (128msg)
2 ch (32msg)
4 ch + 4 ch FIFO + 8 ch
4 ch
4 ch
2 ch
yes (32bit addr, 32bit data)
no
External Interrupts
16 ch
10 ch
NMI Interrupts
1 ch
no
SMC
6 ch
no
LCD controller (40x4)
1 ch
no
ADC (10 bit)
32 ch
8 ch
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
15
Chapter 2 MB91460N Series Overview
2.3
MB91460N series
Table 2.3-1 MB91460N Series Product Lineup (2 / 2)
Feature
MB91V460A
MB91F463N
Alarm Comparator
2 ch
no
Supply Supervisor
yes
no
Clock Supervisor
yes
no
4MHz
4MHz
Main clock oscillator
Sub clock oscillator
32kHz
no
RC Oscillator
100kHz
100KHz / 2MHz
x 25
x 16
PLL
DSU4
yes
no
EDSU
yes (32 BP)
yes (16 BP)
3V / 5V
3V / 5V
Supply Voltage
Regulator
yes
yes
Power Consumption
n.a.
< 1W
Package
PGA/BGA
LQFP64
0 to + 70°C
- 40 to + 105°C (85°C using at 5.0 V)
I2S
no
no
Media LB (MOST interface)
no
no
USB
no
no
Flex Ray
no
no
Temperature Range (Ta)
*: The Memory protection Unit (MPU) is a part of the EDSU functionality
16
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 2 MB91460N Series Overview
2.4
MB91460N series
2.4 Block Diagram
Figure 2.4-1 Block Diagram
FR60 CPU
core
Data RAM
8 Kbytes
Flash-instruction
cache
4 Kbytes
Bit search
I-bus
32
Flash
memory
288 Kbytes
Instruction
RAM
8 Kbytes
D-bus
32
CAN
2 channels
RX4,RX5
TX4,TX5
32 ↔ 16
bus adapter
Bus converter
DMAC
5 channels
R-bus
16
Interrupt controller
Clock control
TTG0 to TTG3
PPG0 to PPG7
PPG
8 channels
TIN0 to TIN3
TOT0 to TOT3
Reload timer
4 channels + 1 channel
(exclusive A/D converter)
CK0 to CK3
ICU0 to ICU3
OCU0 to OCU3
AIN0,AIN1
BIN0,BIN1
ZIN0,ZIN1
CM44-10149-1E
Free-run timer
4 channels
Input capture
4 channels
Output compare
4 channels
External interrupt
10 channels
LIN-USART
4 channels
INT0 to INT7
INT12,INT13
SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3
I 2C
2 channels
SDA2,SDA3
SCL2,SCL3
A/D converter
8 channels
AN0 to AN7
Up/down counter
2 channels
FUJITSU MICROELECTRONICS LIMITED
17
Chapter 2 MB91460N Series Overview
2.4
18
FUJITSU MICROELECTRONICS LIMITED
MB91460N series
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.1
MB91460N series
Chapter 3
MB91460N Series Basic Information
This chapter describes MB91460N series basic information including Memory- and I/O map, interrupt vector table, pin function list, circuit type and pin state table for each device mode.
3.1 Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data to be accessed as shown below.
Byte data access
: 000H to 0FFH
Half word access
: 000H to 1FFH
Word data access
: 000H to 3FFH
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
19
Chapter 3 MB91460N Series Basic Information
3.1
MB91460N series
■ Memory Map
Figure 3.1-1 Memory Map
00000000H
I/O
Direct addressing area
Refer to “■ I/O MAP”.
00000400H
I/O
00001000H
0002E000H
Data RAM (8 Kbytes)
00030000H
Instruction/data RAM
(2 Kbytes)
00030800H
000C0000H
Flash memory
256 Kbytes
00100000H
00148000H
Flash memory
32 Kbytes
00150000H
FFFFFFFFH
20
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
3.2 I/O Map
Register
Address
000000H
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Initial value of register after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1 is
the MSB side of the data.)
Note: Initial values of register bits are represented as follows:
•"1" : Initial value "1"
•"0" : Initial value "0"
•"X" : Initial value "undefined"
•"-" : No physical register at this location
Access is prohibited to areas where the data access attributes are undefined.
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
21
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
I/O Map
Register
Address
Block
+0
+1
000000H
to
000008H
+2
+3
PDR14 [R/W]
- - - - XXXX
PDR15 [R/W]
- - - - XXXX
Reserved
00000CH
Reserved
000010H
Reserved
PDR17 [R/W]
XXXXXXXX
000014H
PDR20 [R/W]
-XXX-XXX
PDR21 [R/W]
-XXX-XXX
000018H
PDR24 [R/W]
XXXXXXXX
00001CH
Reserved
Reserved
PDR22 [R/W]
- - - - XXXX
Reserved
R-bus
Port Data
Register
Reserved
PDR29 [R/W]
XXXXXXXX
Reserved
000020H
Reserved
000024H
to
00002CH
Reserved
Reserved
000030H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
0 to 7
000034H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
12, 13
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
Reserved
Delayed interrupt
00003CH
Reserved
SCR00 [R/W, W]
00000000
SMR00 [R/W, W]
00000000
000044H
ESCR00 [R/W]
00000X00
ECCR00
[R/W, R, W]
000000XX
000048H
SCR01 [R/W, W]
00000000
SMR01 [R/W, W]
00000000
00004CH
ESCR01 [R/W]
00000X00
ECCR01
[R/W, R, W]
000000XX
000050H
SCR02 [R/W, W]
00000000
SMR02 [R/W, W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W, R, W]
000000XX
000040H
22
Reserved
SSR00 [R/W, R]
00001000
RDR00/TDR00
[R/W]
00000000
LIN-USART0
Reserved
SSR01 [R/W, R]
00001000
RDR01/TDR01
[R/W]
00000000
LIN-USART1
Reserved
SSR02 [R/W, R]
00001000
RDR02/TDR02
[R/W]
00000000
LIN-USART2
Reserved
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
000058H
SCR03 [R/W, W]
00000000
SMR03 [R/W, W]
00000000
SSR03 [R/W, R]
00001000
RDR03/TDR03
[R/W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W, R, W]
000000XX
000060H
to
00007CH
LIN-USART3
Reserved
Reserved
Reserved
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H,
00008CH
Reserved
000090H
to 0000FCH
Reserved
Baud rate
Generator
LIN-USART0 to 3
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
- - - - 0000
PPG Control
0 to 3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108H
Reserved
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
CM44-10149-1E
Reserved
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
FUJITSU MICROELECTRONICS LIMITED
PPG 0
PPG 1
PPG 2
PPG 3
PPG 4
PPG 5
23
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
to 00017CH
000180H
+2
+3
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
Reserved
ICS01 [R/W]
00000000
Reserved
Reserved
ICS23 [R/W]
00000000
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
0001A0H
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
Reserved
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
24
Output
Compare
0 to 3
ADERL [R/W]
00000000
0001A4H
0001B0H
Input
Capture
0 to 3
Reserved
Reserved
0001ACH
PPG 7
Reserved
000184H
000198H,
00019CH
PPG 6
A/D
Converter
Reserved
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
FUJITSU MICROELECTRONICS LIMITED
TMCSRL2
[R/W]
0 - 000000
Reload Timer 0
(PPG0, PPG1)
Reload Timer 1
(PPG2, PPG3)
Reload Timer 2
(PPG4, PPG5)
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
to 0001E7H
+2
+3
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
Reserved
TMRLR7 [W]
XXXXXXXX XXXXXXXX
0001E8H
Reload Timer 3
(PPG6, PPG7)
Reserved
TMR7 [R]
XXXXXXXX XXXXXXXX
0001ECH
Reserved
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free-run Timer 0
(ICU0, ICU1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free-run Timer 1
(ICU2, ICU3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free-run Timer 2
(OCU0, OCU1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free-run Timer 3
(OCU2, OCU3)
000200H
DMACA0 [R/W] *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] *
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] *
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
0- - - 0000
CM44-10149-1E
TMCSRL7
[R/W]
0 - 000000
Reload Timer 7
(A/D converter)
TMCSRH7
[R/W]
- - - 00000
DMAC
Reserved
FUJITSU MICROELECTRONICS LIMITED
25
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
000244H
to
0002FCH
+2
+3
Reserved
Reserved
000300H
UDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00001000
Reserved
UDCS0 [R/W]
00000000
000308H
UDCCH1 [R/W]
00000000
UDCCL1 [R/W]
00001000
Reserved
UDCS1 [R/W]
00000000
00030CH
to
000364H
Reserved
Reserved
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370H
Reserved
IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111
Reserved
000374H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
- - - - - - 00
ITBAL3 [R/W]
00000000
000378H
ITMKH3 [R/W]
00 - - - - 11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
- 0000000
00037CH
Reserved
IDAR3 [R/W]
00000000
ICCR3 [R/W]
- 0011111
Reserved
000380H
to
00038CH
000390H
Reserved
ROMS [R]
11111111 01001111
I2C 2
I2C 3
Reserved
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
26
Up/Down
Counter
0, 1
FUJITSU MICROELECTRONICS LIMITED
ROM Select
Register
Reserved
Bit Search
Module
Reserved
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
000440H
ICR00 [R/W]
- - - 11111
ICR01 [R/W]
- - - 11111
ICR02 [R/W]
- - - 11111
ICR03 [R/W]
- - - 11111
000444H
ICR04[R/W]
- - - 11111
ICR05 [R/W]
- - - 11111
ICR06 [R/W]
- - - 11111
ICR07 [R/W]
- - - 11111
000448H
ICR08 [R/W]
- - - 11111
ICR09 [R/W]
- - - 11111
ICR10[R/W]
- - - 11111
ICR11 [R/W]
- - - 11111
00044CH
ICR12 [R/W]
- - - 11111
ICR13[R/W]
- - - 11111
ICR14[R/W]
- - - 11111
ICR15[R/W]
- - - 11111
000450H
ICR16[R/W]
- - - 11111
ICR17[R/W]
- - - 11111
ICR18 [R/W]
- - - 11111
ICR19 [R/W]
- - - 11111
000454H
ICR20 [R/W]
- - - 11111
ICR21 [R/W]
- - - 11111
ICR22 [R/W]
- - - 11111
ICR23 [R/W]
- - - 11111
000458H
ICR24[R/W]
- - - 11111
ICR25[R/W]
- - - 11111
ICR26[R/W]
- - - 11111
ICR27[R/W]
- - - 11111
00045CH
ICR28[R/W]
- - - 11111
ICR29 [R/W]
- - - 11111
ICR30[R/W]
- - - 11111
ICR31[R/W]
- - - 11111
000460H
ICR32[R/W]
- - - 11111
ICR33[R/W]
- - - 11111
ICR34[R/W]
- - - 11111
ICR35[R/W]
- - - 11111
000464H
ICR36[R/W]
- - - 11111
ICR37[R/W]
- - - 11111
ICR38 [R/W]
- - - 11111
ICR39 [R/W]
- - - 11111
000468H
ICR40[R/W]
- - - 11111
ICR41[R/W]
- - - 11111
ICR42 [R/W]
- - - 11111
ICR43 [R/W]
- - - 11111
00046CH
ICR44[R/W]
- - - 11111
ICR45[R/W]
- - - 11111
ICR46[R/W]
- - - 11111
ICR47[R/W]
- - - 11111
000470H
ICR48 [R/W]
- - - 11111
ICR49 [R/W]
- - - 11111
ICR50 [R/W]
- - - 11111
ICR51 [R/W]
- - - 11111
000474H
ICR52[R/W]
- - - 11111
ICR53[R/W]
- - - 11111
ICR54[R/W]
- - - 11111
ICR55[R/W]
- - - 11111
000478H
ICR56 [R/W]
- - - 11111
ICR57[R/W]
- - - 11111
ICR58 [R/W]
- - - 11111
ICR59 [R/W]
- - - 11111
00047CH
ICR60[R/W]
- - - 11111
ICR61 [R/W]
- - - 11111
ICR62 [R/W]
- - - 11111
ICR63 [R/W]
- - - 11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
001100-1
TBCR [R/W]
00XXXX00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
- - - - - 000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488H
Reserved
00048CH
PLLDIVM [R/W]
- - - - 0000
000490H
PLLCTRL [R/W]
- - - - 0000
000494H
000498H
PLLDIVN [R/W]
- - 000000
PLLMULG [R/W]
00000000
Reserved
Reserved
00049CH
CM44-10149-1E
Interrupt
Control
Unit
Clock
Control
Unit
Reserved
PLLDIVG [R/W]
- - - - 0000
PORTEN [R/W]
- - - - - - 00
Interrupt
Control
Unit
PLL Clock
Gear Unit
Reserved
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
Port Input Enable
Control
Reserved
27
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
0004A0H
Reserved
WTCER [R/W]
- - - - - - 00
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
0004ACH
+2
+3
WTCR [R/W]
00000000 000 - 00 - 0
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
WTMR [R/W]
- - 000000
Reserved
0004B0H,
0004B4H
WTSR [R/W]
- - 000000
Reserved
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
Reserved
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
CANPRE [R/W]
00000000
CANCKD [R/W]
- - 00 - - - -
0004C4H
Reserved
LVDET [R/W]
00000 - 00
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
Clock Monitor
Reserved
Reserved
0004C0H
Real Time Clock
(Watch Timer)
CAN Clock
Control
Reserved
HWWDE [R/W]
- - - - - - 00
Clock
Modulator
HWWD [R/W, W]
00011000
Low-voltage
Detection
0004CCH
Reserved
MainOscillation
Stabilization
Timer
0004D0H
to
0007F8H
Reserved
Reserved
0007FCH
MODR [W]
XXXXXXXX
Reserved
Reserved
000800H
to
000CFCH
Reserved
000D00H
to
000D08H
Reserved
000D0CH
Reserved
PDRD17 [R]
XXXXXXXX
000D14H
PDRD20 [R]
- XXX- XXX
PDRD21 [R]
- XXX- XXX
000D18H
PDRD24 [R]
XXXXXXXX
000D1CH
Reserved
28
Mode Register
Reserved
PDRD14 [R]
- - - - XXXX
Reserved
000D10H
000D20H
Reserved
PDRD15 [R]
- - - - XXXX
Reserved
PDRD22 [R]
- - - - XXXX
Reserved
R-bus
Port Data
Direct Read
Register
Reserved
PDRD29 [R]
XXXXXXXX
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
000D24H
to
000D3CH
Reserved
000D40H
to
000D48H
Reserved
000D4CH
Reserved
DDR14 [R/W]
- - - - 0000
Reserved
000D50H
Reserved
DDR17 [R/W]
00000000
000D54H
DDR20 [R/W]
-000- 000
DDR21 [R/W]
-000- 000
000D58H
DDR24 [R/W]
00000000
000D5CH
Reserved
DDR15 [R/W]
- - - - 0000
Reserved
DDR22 [R/W]
- - - - 0000
Reserved
R-bus
Port Direction
Register
Reserved
DDR29 [R/W]
00000000
Reserved
000D60H
Reserved
000D64H
to
000D7CH
Reserved
000D80H
to
000D88H
Reserved
000D8CH
+3
Reserved
PFR14 [R/W]
- - - - 0000
Reserved
000D90H
Reserved
PFR17 [R/W]
00000000
000D94H
PFR20 [R/W]
-000- 000
PFR21 [R/W]
-000- 000
000D98H
PFR24 [R/W]
00000000
000D9CH
Reserved
PFR15 [R/W]
- - - - 0000
Reserved
PFR22 [R/W]
- - - - 0000
Reserved
R-bus
Port Function
Register
Reserved
PFR29 [R/W]
00000000
Reserved
000DA0H
Reserved
000DA4H
to
000DBCH
Reserved
Reserved
000DC0H
to 000DC8H
Reserved
R-bus Extension
Port
Function
Register
000DCCH
CM44-10149-1E
Reserved
EPFR14 [R/W]
- - - - 0000
EPFR15 [R/W]
- - - - 0000
FUJITSU MICROELECTRONICS LIMITED
29
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
000DD0H
+2
+3
EPFR22 [R/W]
--------
Reserved
Reserved
000DD4H
EPFR20 [R/W]
- 000- 000
000DD8H
EPFR24 [R/W]
--------
000DDCH
Reserved
EPFR21 [R/W]
- 0- - - 0- -
Reserved
EPFR29 [R/W]
--------
Reserved
000DE0H
Reserved
000DE4H
to
000DFCH
Reserved
000E00H
to
000E08H
Reserved
000E0CH
000E10H
Reserved
PODR17 [R/W]
00000000
000E14H
PODR20 [R/W]
- 000- 000
PODR21 [R/W]
- 000- 000
000E18H
PODR24 [R/W]
00000000
000E1CH
Reserved
PODR15 [R/W]
- - - - 0000
Reserved
PODR22 [R/W]
- - - - 0000
Reserved
R-bus Port
Output Drive
Select
Register
Reserved
PODR29 [R/W]
00000000
Reserved
000E20H
Reserved
000E24H
to
000E3CH
Reserved
000E40H
to
000E48H
Reserved
Reserved
PILR14 [R/W]
- - - - 0000
Reserved
000E50H
Reserved
PILR17 [R/W]
00000000
000E54H
PILR20 [R/W]
- 000- 000
PILR21 [R/W]
-000- 000
000E58H
PILR24 [R/W]
00000000
000E5CH
Reserved
PILR15 [R/W]
- - - - 0000
Reserved
PILR22 [R/W]
- - - - 0000
Reserved
R-bus Pin
Input Level Select
Register
Reserved
PILR29 [R/W]
00000000
000E60H
Reserved
000E64H
to
000E7CH
Reserved
30
Reserved
PODR14 [R/W]
- - - - 0000
Reserved
000E4CH
R-bus Extension
Port
Function
Register
Reserved
FUJITSU MICROELECTRONICS LIMITED
Reserved
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
000E80H
to
000E88H
+2
+3
EPILR14 [R/W]
- - - - 0000
EPILR15 [R/W]
- - - - 0000
Reserved
000E8CH
Reserved
000E90H
Reserved
EPILR17 [R/W]
00000000
000E94H
EPILR20 [R/W]
- 000- 000
EPILR21 [R/W]
- 000- 000
000E98H
EPILR24 [R/W]
00000000
Reserved
EPILR22 [R/W]
- - - - 0000
Reserved
000E9CH,
000EA0H
Reserved
000EA4H
to
000EBCH
Reserved
000EC0H
to
000EC8H
Reserved
000ECCH
Reserved
R-bus Port
Extra Input Level
Select
Register
Reserved
PPER14 [R/W]
- - - - 0000
Reserved
000ED0H
Reserved
PPER17 [R/W]
00000000
000ED4H
PPER20 [R/W]
-000- 000
PPER21 [R/W]
-000- 000
000ED8H
PPER24 [R/W]
00000000
000EDCH
Reserved
PPER15 [R/W]
- - - - 0000
Reserved
PPER22 [R/W]
- - - - 0000
Reserved
R-bus Port
Pull-up/down
Enable
Register
Reserved
PPER29 [R/W]
00000000
Reserved
000EE0H
Reserved
000EE4H
to
000EFCH
Reserved
Reserved
000F00H
to
000F08H
Reserved
R-bus Port
Pull-up/down Control
Register
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
31
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
000F0CH
+1
Reserved
000F10H
Reserved
PPCR17 [R/W]
11111111
000F14H
PPCR20 [R/W]
-111-111
PPCR21 [R/W]
-111-111
000F18H
PPCR24 [R/W]
11111111
000F1CH
Reserved
+2
+3
PPCR14 [R/W]
- - - - 1111
PPCR15 [R/W]
- - - - 1111
Reserved
PPCR22 [R/W]
- - - - 1111
Reserved
PPCR29 [R/W]
11111111
Reserved
000F24H
to
000F3CH
Reserved
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
006FFCH
Reserved
007004H
007008H
32
FMCS [R/W]
01101000
FMCR [R/W]
- - - -0000
FMWT [R/W]
11111111 01011101
R-bus Port
Pull-up/down Control
Register
Reserved
000F20H
007000H
Reserved
Reserved
DMAC
Reserved
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R/W]
- 101 - - - -
FMPS [R/W]
- - - - - 000
FMAC [R]
- - - - - - - - - - - 00000 00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
Flash Memory/
I-Cache
Control
Register
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
00700CH
FCHA0 [R/W]
- - - - - - - - - 0000000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - 0000000 00000000 00000000
007014H
to
00AFFCH
Reserved
Reserved
00B000H
to
00BFFCH
MB91F463NA BI-ROM size is 4 Kbytes : 00B000H to 00BFFFH
BI-ROM
4 Kbytes
00C000H
to
00C3FCH
Reserved
Reserved
00C400H
CTRLR4 [R/W]
00000000 00000001
STATR4 [R/W]
00000000 00000000
00C404H
ERRCNT4 [R]
00000000 00000000
BTR4 [R/W]
00100011 00000001
00C408H
INTR4 [R]
00000000 00000000
TESTR4 [R/W]
00000000 X0000000
00C40CH
BRPE4 [R/W]
00000000 00000000
Reserved
00C410H
IF1CREQ4 [R/W]
00000000 00000001
IF1CMSK4 [R/W]
00000000 00000000
00C414H
IF1MSK24 [R/W]
11111111 11111111
IF1MSK14 [R/W]
11111111 11111111
00C418H
IF1ARB24 [R/W]
00000000 00000000
IF1ARB14 [R/W]
00000000 00000000
00C41CH
IF1MCTR4 [R/W]
00000000 00000000
Reserved
00C420H
IF1DTA14 [R/W]
00000000 00000000
IF1DTA24 [R/W]
00000000 00000000
00C424H
IF1DTB14 [R/W]
00000000 00000000
IF1DTB24 [R/W]
00000000 00000000
00C428H,
00C42CH
IF1DTA24 [R/W]
00000000 00000000
IF1DTA14 [R/W]
00000000 00000000
00C434H
IF1DTB24 [R/W]
00000000 00000000
IF1DTB14 [R/W]
00000000 00000000
CM44-10149-1E
CAN 4
Control
Register
CAN 4
IF1 Register
Reserved
00C430H
00C438H,
00C43CH
I-Cache
Non-cacheable area
setting
Register
CAN 4
IF1 Register
Reserved
FUJITSU MICROELECTRONICS LIMITED
33
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
00C440H
IF2CREQ4 [R/W]
00000000 00000001
IF2CMSK4 [R/W]
00000000 00000000
00C444H
IF2MSK24 [R/W]
11111111 11111111
IF2MSK14 [R/W]
11111111 11111111
00C448H
IF2ARB24 [R/W]
00000000 00000000
IF2ARB14 [R/W]
00000000 00000000
00C44CH
IF2MCTR4 [R/W]
00000000 00000000
Reserved
00C450H
IF2DTA14 [R/W]
00000000 00000000
IF2DTA24 [R/W]
00000000 00000000
00C454H
IF2DTB14 [R/W]
00000000 00000000
IF2DTB24 [R/W]
00000000 00000000
00C458H,
00C45CH
Reserved
00C460H
IF2DTA24 [R/W]
00000000 00000000
IF2DTA14 [R/W]
00000000 00000000
00C464H
IF2DTB24 [R/W]
00000000 00000000
IF2DTB14 [R/W]
00000000 00000000
00C468H
to
00C47CH
Reserved
00C480H
TREQR24 [R]
00000000 00000000
TREQR14 [R]
00000000 00000000
00C484H
TREQR44 [R]
00000000 00000000
TREQR34 [R]
00000000 00000000
00C488H
TREQR64 [R]
00000000 00000000
TREQR54 [R]
00000000 00000000
00C48CH
TREQR84 [R]
00000000 00000000
TREQR74 [R]
00000000 00000000
00C490H
NEWDT24 [R]
00000000 00000000
NEWDT14 [R]
00000000 00000000
00C494H
NEWDT44 [R]
00000000 00000000
NEWDT34 [R]
00000000 00000000
34
CAN 4
IF2 Register
FUJITSU MICROELECTRONICS LIMITED
CAN 4
Status Flags
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
00C498H
NEWDT64 [R]
00000000 00000000
NEWDT54 [R]
00000000 00000000
00C49CH
NEWDT84 [R]
00000000 00000000
NEWDT74 [R]
00000000 00000000
00C4A0H
INTPND24 [R]
00000000 00000000
INTPND14 [R]
00000000 00000000
00C4A4H
INTPND44 [R]
00000000 00000000
INTPND34 [R]
00000000 00000000
00C4A8H
INTPND64 [R]
00000000 00000000
INTPND54 [R]
00000000 00000000
00C4ACH
INTPND84 [R]
00000000 00000000
INTPND74 [R]
00000000 00000000
00C4B0H
MSGVAL24 [R]
00000000 00000000
MSGVAL14 [R]
00000000 00000000
00C4B4H
MSGVAL44 [R]
00000000 00000000
MSGVAL34 [R]
00000000 00000000
00C4B8H
MSGVAL64 [R]
00000000 00000000
MSGVAL54 [R]
00000000 00000000
00C4BCH
MSGVAL84 [R]
00000000 00000000
MSGVAL74 [R]
00000000 00000000
00C4C0H
to
00C4FCH
Reserved
00C500H
CTRLR5 [R/W]
00000000 00000001
STATR5 [R/W]
00000000 00000000
00C504H
ERRCNT5 [R]
00000000 00000000
BTR5 [R/W]
00100011 00000001
00C508H
INTR5 [R]
00000000 00000000
TESTR5 [R/W]
00000000 X0000000
00C50CH
BRPE5 [R/W]
00000000 00000000
Reserved
00C510H
IF1CREQ5 [R/W]
00000000 00000001
IF1CMSK5 [R/W]
00000000 00000000
00C514H
IF1MSK25 [R/W]
11111111 11111111
IF1MSK15 [R/W]
11111111 11111111
00C518H
IF1ARB25 [R/W]
00000000 00000000
IF1ARB15 [R/W]
00000000 00000000
00C51CH
IF1MCTR5 [R/W]
00000000 00000000
Reserved
00C520H
IF1DTA15 [R/W]
00000000 00000000
IF1DTA25 [R/W]
00000000 00000000
CM44-10149-1E
CAN 4
Status Flags
FUJITSU MICROELECTRONICS LIMITED
CAN 5
Control
Register
CAN 5
IF1 Register
35
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
00C524H
+1
+2
IF1DTB15 [R/W]
00000000 00000000
00C528H,
00C52CH
+3
IF1DTB25 [R/W]
00000000 00000000
Reserved
00C530H
IF1DTA25 [R/W]
00000000 00000000
IF1DTA15 [R/W]
00000000 00000000
00C534H
IF1DTB25 [R/W]
00000000 00000000
IF1DTB15 [R/W]
00000000 00000000
00C538H,
00C53CH
Reserved
00C540H
IF2CREQ5 [R/W]
00000000 00000001
IF2CMSK5 [R/W]
00000000 00000000
00C544H
IF2MSK25 [R/W]
11111111 11111111
IF2MSK15 [R/W]
11111111 11111111
00C548H
IF2ARB25 [R/W]
00000000 00000000
IF2ARB15 [R/W]
00000000 00000000
00C54CH
IF2MCTR5 [R/W]
00000000 00000000
Reserved
00C550H
IF2DTA15 [R/W]
00000000 00000000
IF2DTA25 [R/W]
00000000 00000000
00C554H
IF2DTB15 [R/W]
00000000 00000000
IF2DTB25 [R/W]
00000000 00000000
00C558H,
00C55CH
CAN 5
IF2 Register
Reserved
00C560H
IF2DTA25 [R/W]
00000000 00000000
IF2DTA15 [R/W]
00000000 00000000
00C564H
IF2DTB25 [R/W]
00000000 00000000
IF2DTB15 [R/W]
00000000 00000000
00C568H
to
00C57CH
Reserved
00C580H
TREQR25 [R]
00000000 00000000
TREQR15 [R]
00000000 00000000
00C584H
TREQR45 [R]
00000000 00000000
TREQR35 [R]
00000000 00000000
00C588H
TREQR65 [R]
00000000 00000000
TREQR55 [R]
00000000 00000000
36
CAN 5
IF1 Register
FUJITSU MICROELECTRONICS LIMITED
CAN 5
Status Flags
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
00C58CH
TREQR85 [R]
00000000 00000000
TREQR75 [R]
00000000 00000000
00C590H
NEWDT25 [R]
00000000 00000000
NEWDT15 [R]
00000000 00000000
00C594H
NEWDT45 [R]
00000000 00000000
NEWDT35 [R]
00000000 00000000
00C598H
NEWDT65 [R]
00000000 00000000
NEWDT55 [R]
00000000 00000000
00C59CH
NEWDT85 [R]
00000000 00000000
NEWDT75 [R]
00000000 00000000
00C5A0H
INTPND25 [R]
00000000 00000000
INTPND15 [R]
00000000 00000000
00C5A4H
INTPND45 [R]
00000000 00000000
INTPND35 [R]
00000000 00000000
00C5A8H
INTPND65 [R]
00000000 00000000
INTPND55 [R]
00000000 00000000
00C5ACH
INTPND85 [R]
00000000 00000000
INTPND75 [R]
00000000 00000000
00C5B0H
MSGVAL25 [R]
00000000 00000000
MSGVAL15 [R]
00000000 00000000
00C5B4H
MSGVAL45 [R]
00000000 00000000
MSGVAL35 [R]
00000000 00000000
00C5B8H
MSGVAL65 [R]
00000000 00000000
MSGVAL55 [R]
00000000 00000000
00C5BCH
MSGVAL85 [R]
00000000 00000000
MSGVAL75 [R]
00000000 00000000
00C5C0H
to
00EFFCH
Reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
00000000 00000000 00000000 00000000
00F00CH
BOAC [R]
00000000 00000000 00000000 00000000
00F010H
BIRQ [R/W]
00000000 00000000 00000000 00000000
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
CAN 5
Status Flags
EDSU / MPU
37
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F03CH
Reserved
00F040H
to
00F07CH
Reserved
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
38
FUJITSU MICROELECTRONICS LIMITED
+3
EDSU / MPU
Reserved
EDSU / MPU
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.2
MB91460N series
Register
Address
Block
+0
+1
+2
+3
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
00F0FCH
Reserved
00F100H
to
02DFFCH
Reserved
Reserved
02E000H
to
02FFFCH
MB91F463NA Data RAM size is 8 Kbytes: 02E000H to 02FFFFH
(data access is 0 wait cycle)
D-RAM
8 Kbytes
030000H
to
0307FCH
MB91F463NA Instruction/data RAM size is 2 Kbytes: 030000H to 0307FFH
(instruction access is 0 wait cycle, data access is 1 wait cycle)
I/D-RAM
2 Kbytes
030800H
to
0BFFFCH
Reserved
Reserved
0C0000H
to
0DFFFCH
ROMS04 area (128 Kbytes)
0E0000H
to
0FFFF4H
ROMS05 area (128 Kbytes)
0FFFF8H
FMV [R]
XXXXXXXXH
0FFFFCH
FRV [R]
XXXXXXXXH
100000H
to
147FFCH
Reserved
148000H
to
14FFFCH
ROMS07 area (32 Kbytes)
148000H
to
4FFFFCH
Reserved
EDSU / MPU
Flash memory
256 Kbytes
Reset/Mode
Vector
Reserved
Flash memory
32 Kbytes
Reserved
* : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
39
Chapter 3 MB91460N Series Basic Information
3.3
MB91460N series
3.3 INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
number
Interrupt level
HexaDecimal
decimal
Setting
register
Interrupt vector
Register
address
Offset
Default vector
address
Resource
number*1
Reset
0
00
⎯
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
⎯
3ECH
000FFFECH
⎯
CPU supervisor mode
(INT #5 instruction) *2
5
05
⎯
⎯
3E8H
000FFFE8H
⎯
Memory protection exception *2
6
06
⎯
⎯
3E4H
000FFFE4H
⎯
System reserved
7
07
⎯
⎯
3E0H
000FFFE0H
⎯
System reserved
8
08
⎯
⎯
3DCH
000FFFDCH
⎯
System reserved
9
09
⎯
⎯
3D8H
000FFFD8H
⎯
System reserved
10
0A
⎯
⎯
3D4H
000FFFD4H
⎯
System reserved
11
0B
⎯
⎯
3D0H
000FFFD0H
⎯
System reserved
12
0C
⎯
⎯
3CCH
000FFFCCH
⎯
System reserved
13
0D
⎯
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
3BCH
000FFFBCH
0, 16
External interrupt 1
17
11
3B8H
000FFFB8H
1, 17
External interrupt 2
18
12
3B4H
000FFFB4H
2, 18
External interrupt 3
19
13
3B0H
000FFFB0H
3, 19
External interrupt 4
20
14
3ACH
000FFFACH
20
External interrupt 5
21
15
3A8H
000FFFA8H
21
External interrupt 6
22
16
3A4H
000FFFA4H
22
External interrupt 7
23
17
3A0H
000FFFA0H
23
System reserved
24
18
39CH
000FFF9CH
⎯
System reserved
25
19
398H
000FFF98H
⎯
System reserved
26
1A
394H
000FFF94H
⎯
System reserved
27
1B
390H
000FFF90H
⎯
External interrupt 12
28
1C
38CH
000FFF8CH
⎯
External interrupt 13
29
1D
388H
000FFF88H
⎯
System reserved
30
1E
384H
000FFF84H
⎯
System reserved
31
1F
380H
000FFF80H
⎯
Reload timer 0
32
20
37CH
000FFF7CH
4, 32
Reload timer 1
33
21
378H
000FFF78H
5, 33
Reload timer 2
34
22
374H
000FFF74H
34
Reload timer 3
35
23
370H
000FFF70H
35
40
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
ICR07
447H
ICR08
448H
ICR09
449H
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.3
MB91460N series
Interrupt
number
Interrupt source
Decimal
Hexadecimal
System reserved
36
24
System reserved
37
25
System reserved
38
26
Reload timer 7
39
27
Free-run timer 0
40
28
Free-run timer 1
41
29
Free-run timer 2
42
2A
Free-run timer 3
43
2B
System reserved
44
2C
System reserved
45
2D
System reserved
46
2E
System reserved
47
2F
System reserved
48
30
System reserved
49
31
System reserved
50
32
System reserved
51
33
CAN 4
52
34
CAN 5
53
35
LIN-USART0 RX
54
36
LIN-USART0 TX
55
37
LIN-USART1 RX
56
38
LIN-USART1 TX
57
39
LIN-USART2 RX
58
3A
LIN-USART2 TX
59
3B
LIN-USART3 RX
60
3C
LIN-USART3 TX
61
3D
System reserved
62
3E
63
3F
64
40
65
41
System reserved
66
42
System reserved
67
43
System reserved
68
44
System reserved
69
45
Delayed interrupt
System reserved
*4
System reserved
*4
System reserved
70
46
System reserved
71
47
System reserved
72
48
System reserved
73
49
CM44-10149-1E
Interrupt level
Interrupt vector
Setting
register
Offset
Register
address
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23 *3
457H
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
Default vector
address
Resource
number*1
36CH
000FFF6CH
36
368H
000FFF68H
37
364H
000FFF64H
38
360H
000FFF60H
39
35CH
000FFF5CH
40
358H
000FFF58H
41
354H
000FFF54H
42
350H
000FFF50H
43
34CH
000FFF4CH
44
348H
000FFF48H
45
344H
000FFF44H
46
340H
000FFF40H
47
33CH
000FFF3CH
æ
338H
000FFF38H
æ
334H
000FFF34H
æ
330H
000FFF30H
æ
32CH
000FFF2CH
æ
328H
000FFF28H
æ
324H
000FFF24H
6, 48
320H
000FFF20H
7, 49
31CH
000FFF1CH
8, 50
318H
000FFF18H
9, 51
314H
000FFF14H
52
310H
000FFF10H
53
30CH
000FFF0CH
54
308H
000FFF08H
55
304H
000FFF04H
⎯
300H
000FFF00H
⎯
2FCH
000FFEFCH
⎯
2F8H
000FFEF8H
⎯
2F4H
000FFEF4H
10, 56
2F0H
000FFEF0H
11, 57
2ECH
000FFEECH
12, 58
2E8H
000FFEE8H
13, 59
2E4H
000FFEE4H
60
2E0H
000FFEE0H
61
2DCH
000FFEDCH
62
2D8H
000FFED8H
63
FUJITSU MICROELECTRONICS LIMITED
41
Chapter 3 MB91460N Series Basic Information
3.3
Interrupt source
Interrupt
number
Decimal
Hexadecimal
I2C 2
74
4A
I2
75
4B
System reserved
76
4C
System reserved
77
4D
System reserved
78
4E
System reserved
79
4F
System reserved
80
50
System reserved
81
51
System reserved
82
52
System reserved
83
53
System reserved
84
54
System reserved
85
55
System reserved
86
56
System reserved
87
57
C3
System reserved
88
58
System reserved
89
59
System reserved
90
5A
System reserved
91
5B
Input capture 0
92
5C
Input capture 1
93
5D
Input capture 2
94
5E
Input capture 3
95
5F
System reserved
96
60
System reserved
97
61
System reserved
98
62
System reserved
99
63
Output compare 0
100
64
Output compare 1
101
65
Output compare 2
102
66
Output compare 3
103
67
System reserved
104
68
System reserved
105
69
System reserved
106
6A
System reserved
107
6B
System reserved
108
6C
Phase Frequency modulator
109
6D
System reserved
110
6E
System reserved
111
6F
42
MB91460N series
Interrupt level
Interrupt vector
Setting
register
Offset
Register
address
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 *4
46FH
Default vector
address
Resource
number*1
2D4H
000FFED4H
⎯
2D0H
000FFED0H
⎯
2CCH
000FFECCH
64
2C8H
000FFEC8H
65
2C4H
000FFEC4H
66
2C0H
000FFEC0H
67
2BCH
000FFEBCH
68
2B8H
000FFEB8H
69
2B4H
000FFEB4H
70
2B0H
000FFEB0H
71
2ACH
000FFEACH
72
2A8H
000FFEA8H
73
2A4H
000FFEA4H
74
2A0H
000FFEA0H
75
29CH
000FFE9CH
76
298H
000FFE98H
77
294H
000FFE94H
78
290H
000FFE90H
79
28CH
000FFE8CH
80
288H
000FFE88H
81
284H
000FFE84H
82
280H
000FFE80H
83
27CH
000FFE7CH
84
278H
000FFE78H
85
274H
000FFE74H
86
270H
000FFE70H
87
26CH
000FFE6CH
88
268H
000FFE68H
89
264H
000FFE64H
90
260H
000FFE60H
91
25CH
000FFE5CH
92
258H
000FFE58H
93
254H
000FFE54H
94
250H
000FFE50H
95
24CH
000FFE4CH
⎯
248H
000FFE48H
⎯
244H
000FFE44H
⎯
240H
000FFE40H
⎯
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.3
MB91460N series
Interrupt source
Interrupt
number
Decimal
Hexadecimal
PPG0
112
70
PPG1
113
71
PPG2
114
72
PPG3
115
73
PPG4
116
74
PPG5
117
75
PPG6
118
76
PPG7
119
77
System reserved
120
78
System reserved
121
79
System reserved
122
7A
System reserved
123
7B
System reserved
124
7C
System reserved
125
7D
System reserved
126
7E
System reserved
127
7F
Up/down counter 0
128
80
Up/down counter 1
129
81
System reserved
130
82
System reserved
131
83
Real time clock
132
84
Calibration unit
133
85
A/D converter 0
134
86
System reserved
135
87
System reserved
136
88
System reserved
137
89
Low voltage detection
138
8A
System reserved
139
8B
Time-base overflow
140
8C
PLL clock gear
141
8D
DMA controller
142
8E
Main OSC stability wait
143
8F
System reserved
144
Used by the INT instruction
145
to
255
Interrupt level
Interrupt vector
Setting
register
Offset
Register
address
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90
⎯
91
to
FF
⎯
Default vector
address
Resource
number*1
23CH
000FFE3CH
15, 96
238H
000FFE38H
97
234H
000FFE34H
98
230H
000FFE30H
99
22CH
000FFE2CH
100
228H
000FFE28H
101
224H
000FFE24H
102
220H
000FFE20H
103
21CH
000FFE1CH
104
218H
000FFE18H
105
214H
000FFE14H
106
210H
000FFE10H
107
20CH
000FFE0CH
108
208H
000FFE08H
109
204H
000FFE04H
110
200H
000FFE00H
111
1FCH
000FFDFCH
⎯
1F8H
000FFDF8H
⎯
1F4H
000FFDF4H
⎯
1F0H
000FFDF0H
⎯
1ECH
000FFDECH
⎯
1E8H
000FFDE8H
⎯
1E4H
000FFDE4H
14, 112
1E0H
000FFDE0H
⎯
1DCH
000FFDDCH
⎯
1D8H
000FFDD8H
⎯
1D4H
000FFDD4H
⎯
1D0H
000FFDD0H
⎯
1CCH
000FFDCCH
⎯
1C8H
000FFDC8H
⎯
1C4H
000FFDC4H
⎯
1C0H
000FFDC0H
⎯
⎯
1BCH
000FFDBCH
⎯
⎯
1B8H
to
000H
000FFDB8H
to
000FFC00H
⎯
*1: The peripheral resources to which RN (Resource Number) is assigned are capable of being DMA transfer activation sources.
In addition, RN respectively corresponds to an IS (Input Source) of the DMAC channel control register A(DMACA0 to DMACA4),
and the IS (Input Source) can be obtained by representing RN in a binary number and adding "1" to the head of it.
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
43
Chapter 3 MB91460N Series Basic Information
3.3
MB91460N series
*2: Memory Protection Unit (MPU) support
*3: ICR23 can be switched to ICR47 by setting REALOS compatibility bit (address 0C03H ISO[0]).
*4: Used by REALOS
44
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.4
MB91460N series
3.4 PACKAGE DIMENSION
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
64
17
1
16
0.65(.026)
0.32±0.05
(.013±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"A"
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
©2003-2008
FUJITSU
LIMITED F64034S-c-1-2
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F64034S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
CM44-10149-1E
FUJITSU MICROELECTRONICS LIMITED
45
Chapter 3 MB91460N Series Basic Information
3.5
MB91460N series
3.5 PIN ASSIGNMENT
AVSS
AVRH
P14_0/ICU0/TIN0/TTG0
P14_1/ICU1/TIN1/TTG1
P14_2/ICU2/TIN2/TTG2
P14_3/ICU3/TIN3/TTG3
P21_0/SIN0
P21_1/SOT0
P21_2/SCK0/CK0
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P17_0/PPG0
P17_1/PPG1
P17_2/PPG2
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
AVCC
1
48
VCC
P29_0/AN0
2
47
P17_3/PPG3
P29_1/AN1
3
46
P17_4/PPG4
P29_2/AN2
4
45
P17_5/PPG5
P29_3/AN3
5
44
P17_6/PPG6
P29_4/AN4
6
43
P17_7/PPG7
P29_5/AN5
7
42
P15_3/OCU3/TOT3
P29_6/AN6
8
41
P15_2/OCU2/TOT2
LQFP-64
28
29
30
31
32
P20_4/SIN3/AIN1
P20_5/SOT3/BIN1
P20_6/SCK3/CK3/ZIN1
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
VSS
27
VSS
26
33
P20_1/SOT2/BIN0
16
P20_2/SCK2/CK2/ZIN0
X0
VCC
25
X1
34
P20_0/SIN2/AIN0
35
15
24
14
P24_5/INT5/SCL2
23
P24_4/INT4/SDA2
P22_3/TX5
MD3
P22_2/RX5/INT13
36
22
13
P22_1/TX4
MD2
P24_3/INT3/MONCLK
21
MD1
37
20
38
12
P22_0/RX4/INT12
11
P24_2/INT2
P24_7/INT7/SCL3
P24_1/INT1
19
MD0
18
INITX
39
C
40
P24_6/INT6/SDA3
9
10
17
P29_7/AN7
P24_0/INT0
(FPT-64P-M23)
46
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.6
MB91460N series
3.6 PIN DESCRIPTION
Pin no.
2 to 9
10 to 12
Pin name
P29_0 to P29_7
AN0 to AN7
P24_0 to P24_2
INT0 to INT2
I/O
I/O circuit
type*
I/O
B
I/O
A
P24_3
13
INT3
I/O
A
15
I/O
C
21
General-purpose input/output port
INT5
I/O
C
INT6
General-purpose input/output port
I/O
C
I2C bus data input/output pin
P24_7
General-purpose input/output port
INT7
I/O
C
I2C bus clock input/output pin
P22_0
General-purpose input/output port
RX4
I/O
A
P22_1
TX4
RX5
P22_3
TX5
SIN2
SOT2
I/O
A
I/O
A
CK2
CM44-10149-1E
TX output pin of CAN4
RX input pin of CAN5
External interrupt input pin
I/O
A
I/O
A
General-purpose input/output port
TX output pin of CAN5
General-purpose input/output port
Data input pin of LIN-USART2
Up/down counter input pin
General-purpose input/output port
I/O
A
Data output pin of LIN-USART2
Up/down counter input pin
P20_2
ZIN0
General-purpose input/output port
General-purpose input/output port
BIN0
SCK2
RX input pin of CAN4
External interrupt input pin
P20_1
27
External interrupt input pin
SCL3
AIN0
26
External interrupt input pin
SDA3
P20_0
25
External interrupt input pin
I2C bus clock input/output pin
INT13
24
External interrupt input pin
P24_5
P22_2
23
External interrupt input pin
I2C bus data input/output pin
INT12
22
External interrupt input pins
SDA2
P24_6
20
General-purpose input/output ports
General-purpose input/output port
SCL2
19
Analog input pins for A/D converter
Clock monitor output pin
P24_4
INT4
General-purpose input/output ports
General-purpose input/output port
MONCLK
14
Function
General-purpose input/output port
I/O
A
Clock input/output pin of LIN-USART2
Free-run timer input pin
Up/down counter input pin
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Chapter 3 MB91460N Series Basic Information
3.6
Pin no.
Pin name
MB91460N series
I/O
I/O circuit
type*
I/O
A
P20_4
28
SIN3
General-purpose input/output port
AIN1
SOT3
General-purpose input/output port
I/O
A
BIN1
SCK3
CK3
General-purpose input/output port
I/O
A
ZIN1
32
OCU0
Free-run timer input pin
General-purpose input/output port
I/O
A
Output compare output pin
TOT0
Reload timer output pin
P15_1
General-purpose input/output port
OCU1
I/O
A
TOT1
Output compare output pin
Reload timer output pin
34
X0
⎯
J
Clock (oscillation) input
35
X1
⎯
J
Clock (oscillation) output
36
MD3
I
I
Mode setting pin
37
MD2
I
G
Mode setting pin
38
MD1
I
G
Mode setting pin
39
MD0
I
G
Mode setting pin
40
INITX
I
H
External reset input
P15_2
41
OCU2
General-purpose input/output port
I/O
A
Reload timer output pin
P15_3
General-purpose input/output port
OCU3
43 to 47,
50 to 52
P17_7 to P17_0
I/O
A
TOT3
PPG7 to PPG0
SCK1
I/O
A
55
P21_5
SOT1
P21_4
SIN1
I/O
A
SCK0
CK0
PPG timer output pins
Clock input/output pin of LIN-USART1
Free-run timer input pin
I/O
A
I/O
A
P21_2
56
General-purpose input/output ports
General-purpose input/output port
CK1
54
Output compare output pin
Reload timer output pin
P21_6
53
Output compare output pin
TOT2
42
48
Clock input/output pin of LIN-USART3
Up/down counter input pin
P15_0
31
Data output pin of LIN-USART3
Up/down counter input pin
P20_6
30
Data input pin of LIN-USART3
Up/down counter input pin
P20_5
29
Function
General-purpose input/output port
Data output pin of LIN-USART1
General-purpose input/output port
Data input pin of LIN-USART1
General-purpose input/output port
I/O
A
Clock input/output pin of LIN-USART0
Free-run timer input pin
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Chapter 3 MB91460N Series Basic Information
3.6
MB91460N series
Pin no.
Pin name
P21_1
57
SOT0
P21_0
58
SIN0
I/O
I/O circuit
type*
I/O
A
I/O
A
P14_3
I/O
TIN3
Data input pin of LIN-USART0
A
Input capture input pin
External trigger input pin of reload timer
P14_2
General-purpose input/output port
I/O
A
Input capture input pin
External trigger input pin of reload timer
TTG2
PPG timer input pin
P14_1
General-purpose input/output port
ICU1
I/O
TIN1
A
Input capture input pin
External trigger input pin of reload timer
TTG1
PPG timer input pin
P14_0
General-purpose input/output port
ICU0
62
General-purpose input/output port
PPG timer input pin
TIN2
61
Data output pin of LIN-USART0
TTG3
ICU2
60
General-purpose input/output port
General-purpose input/output port
ICU3
59
Function
I/O
TIN0
A
TTG0
Input capture input pin
External trigger input pin of reload timer
PPG timer input pin
*: For I/O circuit type, refer to “ 3.7 I/O CIRCUIT TYPE”.
[Power supply/GND pins]
Pin no.
Pin name
I/O
Function
17, 33, 49
VSS
⎯
GND pins
16, 48
VCC
⎯
3.3 V/5 V power supply pins
64
AVSS
⎯
Analog GND pin for A/D converter
1
AVCC
⎯
3.3 V/5 V power supply pin for A/D converter
63
AVRH
⎯
Reference power supply pin for A/D converter
18
C
⎯
Capacitor connection pin for internal regulator
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Chapter 3 MB91460N Series Basic Information
3.7
MB91460N series
3.7 I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Pull-up control
P-ch
P-ch
N-ch
N-ch
Driver strength
control
Data line
• CMOS level output
(programmable IOL = 5mA, IOH = − 5mA,
IOL = 2mA, IOH = − 2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
Pull-down control
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
B
Pull-up control
P-ch
P-ch
N-ch
N-ch
Driver strength
control
Data line
Pull-down control
• CMOS level output
(programmable IOL = 5 mA, IOH = − 5 mA,
IOL = 2 mA, IOH = − 2 mA)
• 2 different CMOS hysteresis inputs with
input shutdown function
• Automotive input with input shutdown
function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
• Analog input
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
Analog input
50
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CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.7
MB91460N series
Type
Circuit
Remarks
C
Pull-up control
P-ch
P-ch
Data line
N-ch
• CMOS level output (IOL = 3 mA, IOH = − 3 mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
N-ch
Pull-down control
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for input shutdown
D
Pull-up control
P-ch
P-ch
Data line
N-ch
N-ch
• CMOS level output (IOL = 3 mA, IOH = − 3 mA)
• 2 different CMOS hysteresis inputs with
input shutdown function
• Automotive input with input shutdown
function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
• Analog input
Pull-down control
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
Analog input
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Chapter 3 MB91460N Series Basic Information
3.7
Type
MB91460N series
Circuit
Remarks
E
Pull-up control
P-ch
P-ch
Driver strength
control
Data line
N-ch
N-ch
• CMOS level output
(programmable IOL = 5 mA, IOH = − 5 mA,
IOL = 2 mA, IOH = − 2 mA, IOL = 30 mA,
IOH = − 30 mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
Pull-down control
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
F
Pull-up control
P-ch
P-ch
N-ch
N-ch
Driver strength
control
Data line
Pull-down control
• CMOS level output
(programmable IOL = 5 mA, IOH = − 5 mA,
IOL = 2 mA, IOH = − 2 mA,IOL = 30 mA,
IOH = − 30 mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
• Analog input
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
Analog input
52
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CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.7
MB91460N series
Type
Circuit
Remarks
G
R
CMOS input
H
• MASK ROM and evaluation device:
CMOS input pin
• Flash device:
- CMOS input pin
- 12 V resistant (for MD [2:0])
• CMOS hysteresis input pin
• Pull-up resistor value: approx.50 kΩ
Pull-up resistor
R
Hysteresis
input
I
• CMOS hysteresis input pin
• Pull-down resistor value: approx.50 kΩ
R
Hysteresis
input
Pull-down resistor
J
Oscillation circuit
X1
Xout
X0
Standby control signal
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Chapter 3 MB91460N Series Basic Information
3.7
Type
MB91460N series
Circuit
Remarks
K
Pull-up control
P-ch
Driver strength
control
Data line
P-ch
N-ch
N-ch
• CMOS level output
(programmable IOL = 5 mA, IOH = − 5 mA,
IOL = 2 mA, IOH = − 2 mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
• LCD SEG/COM output
Pull-down control
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
LCD SEG/COM
L
Pull-up control
P-ch
Driver strength
control
Data line
P-ch
N-ch
N-ch
Pull-down control
• CMOS level output
(programmable IOL = 5 mA, IOH = − 5 mA,
IOL = 2 mA, IOH = − 2 mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor:
approx.50 kΩ
• Analog input
• LCD voltage input
R
CMOS hysteresis
type1
CMOS hysteresis
type2
Automotive input
TTL input
Standby control for
input shutdown
VLCD
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CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.7
MB91460N series
Type
Circuit
Remarks
M
CMOS level TRI-STATE output
(IOL = 5 mA, IOH = − 5 mA)
Tri-state control
P-ch
Data line
N-ch
N
Analog input pin with protection
P-ch
Analog input line
N-ch
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Chapter 3 MB91460N Series Basic Information
3.8
MB91460N series
3.8 Pin State Table
Below are the meanings of the expressions used in the List of the Pin State which corresponds to each
selected mode:
• input enable: A signal can be input to the device.
• input fixed: The input level is internally fixed to Åg0Åh in order to prevent any leakage due to input variation.
• Hi-Z: The pin is in high impedance state.
• Maintain previous state: Maintains the pin state (input/output) immediately before the state changes. In the
case of output, the output value of the pin is maintained.
Table 3.8-1 List of the Pin State (1 / 3)
Pin No.
Pin Name
I/O
I/O
Circuit
Type
P29_0 to
P29_7
2 to 9
I/O
B
I/O
A
I/O
C
AN0 to AN7
10 to 13
14
15
19
20
P24_0 to
P24_3
INT0 to INT3
P24_4
INT4
SDA2
P24_5
INT5
SCL2
P24_6
INT6
SDA3
P24_7
INT7
I/O
C
I/O
C
I/O
C
At Reset
(INIT, RST)
After
Reset and
Vector
Fetch
At SLEEP
mode
At STOP
HIZ=0
At STOP
HIZ=1
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
STOP: When
setting INT*,
Output Hi-Z,
input enable
input fixed
(for external
interrupt)
SCL3
P22_0
RX4
21
I/O
A
I/O
A
I/O
A
I/O
A
STOP: When
setting INT*,
input enable
(for external
interrupt)
INT12
22
P22_1
TX4
P22_2
RX5
23
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
INT13
24
56
P22_3
TX5
Remark
FUJITSU MICROELECTRONICS LIMITED
Output Hi-Z,
input fixed STOP: When
setting INT*,
input enable
(for external
interrupt)
CM44-10149-1E
Chapter 3 MB91460N Series Basic Information
3.8
MB91460N series
Table 3.8-1 List of the Pin State (2 / 3)
Pin No.
I/O
I/O
Circuit
Type
SIN2
AIN0
P20_1
SOT2
BIN0
P20_2
SCK2
CK2
ZIN0
P20_4
SIN3
AIN1
P20_5
SOT3
BIN1
P20_6
SCK3
CK3
ZIN1
P15_0
I/O
A
I/O
A
I/O
A
OCU0
TOT0
P15_1
OCU1
TOT1
X0
Pin Name
At Reset
(INIT, RST)
After
Reset and
Vector
Fetch
At SLEEP
mode
At STOP
HIZ=0
At STOP
HIZ=1
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Remark
P20_0
25
26
27
28
29
30
31
32
34
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
-
J
35
X1
-
J
36
37
38
39
40
MD3
MD2
MD1
MD0
INITX
P15_2
OCU2
TOT2
P15_3
OCU3
TOT3
P17_7 to
P17_0
I
I
I
I
I
I
G
G
G
H
I/O
A
41
42
43 to 47,
50 to 52
PPG7 to
PPG0
CM44-10149-1E
I/O
I/O
Oscillator
ON
Oscillator
ON
Oscillator
ON
Input enabled
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
A
A
When setting When setting
OSCD1,
OSCD1,
oscillator in oscillator in
STOP state STOP state
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Chapter 3 MB91460N Series Basic Information
3.8
MB91460N series
Table 3.8-1 List of the Pin State (3 / 3)
Pin No.
Pin Name
I/O
I/O
Circuit
Type
I/O
A
I/O
A
I/O
A
At Reset
(INIT, RST)
After
Reset and
Vector
Fetch
At SLEEP
mode
At STOP
HIZ=0
At STOP
HIZ=1
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Output Hi-Z, Output Hi-Z,
input fixed
input fixed
Maintain
previous
state
Output:
Maintain
previous
state, input
fixed
Output Hi-Z,
input fixed
Remark
P21_6
53
54
55
56
57
58
59
60
61
62
58
SCK1
CK1
P21_5
SOT1
P21_4
SIN1
P21_2
SCK0
CK0
P21_1
SOT0
P21_0
SIN0
P14_3
ICU3
TIN3
TTG3
P14_2
ICU2
TIN2
TTG2
P14_1
ICU1
TIN1
TTG1
P14_0
ICU0
TIN0
TTG0
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 4 CPU Architecture
4.1
MB91460N series
Chapter 4
CPU Architecture
This chapter describes the architecture of FR-family CPU.
4.1 Overview
The CPUs of the FR-family series employ RISC architecture and advanced function instructions for embedded
application.
CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. "32bit/16-bit bus converter" realizes the interface between CPU and peripheral functions. "Harvard/Princeton bus
converter" connects both of I-bus and D-bus and realizes the interface between CPU and Princeton Bus.
Figure 4.1-1 Connection Diagram of Internal Architecture (Core Group)
FR-family CPU
Extbus - I-Cache
External Bus
Address Space
Prefetch
Queue
Flash-I-Cache
(16 kByte)
Embedded
ID-RAM
(64 kByte)
Bus Converter
I-Bus
D-Bus
Embedded
Flash
32 bit <-> 16 bit
Embedded
(R-Unit)
D-RAM
(64 kByte)
R-Bus
(Only Flash
Device)
Embedded
ROM
(Only ROM
Data
Buffer
16 bit
Resources
32 bit
Resources
Device)
External
SRAM
(Only
EVA Chip)
Harvard/Princeton
Bus Converter
(B-Unit)
F-Bus
M-Bus
X-Bus
DMA
Controller
Bus Converter
(T-Unit)
CM44-10149-1E
T-Bus
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External Bus
59
Chapter 4 CPU Architecture
4.2
MB91460N series
4.2 Features
■ Features of internal architecture
• RISC architecture
• Base instruction: 1 instruction/1 cycle
• 32-bit architecture
• General-purpose register: 32-bit x 16
• 4GB of linear memory space
• Equipped with multiplier.
•32-bit x 32-bit multiplication: 5 cycles
•16-bit x 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
•High-speed respond (6 cycles)
•Support of multiple interrupts
•Level mask function (16 levels)
• Enhanced instruction for I/O operation
•Transfer instruction between memories
•Bit-processing instruction
• Highly efficient code
• Length of base instruction words: 16 bits
• Standby states (Low power consumption states): SLEEP/STOP
• Setting function of clock division ratios
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Chapter 4 CPU Architecture
4.3
MB91460N series
4.3 CPU
The CPU realizes the compact implementation of a 32-bit RISC FR architecture.
It employs a 5-stage instruction pipeline method to execute 1 instruction per 1 cycle.
This pipeline consists of the following stages.
•
Instruction fetch (IF): outputs instruction address to fetch instruction.
•
Instruction decode (ID): decodes fetched instruction and reads register.
•
Execution (EX): executes operation.
•
Memory access (MA): loads data for memory or accesses stored data.
•
Write back to register (WB): writes back data to registers.
Figure 4.3-1 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
No instruction is executed in random order. If instruction A enters into pipeline before instruction B, instruction
A always reaches to write-back stage before instruction B.
1 instruction is executed per 1 cycle.
However, to execute the instruction, multiple cycles are required for load/store instruction with memory wait,
branch instruction without delay slot and multi-cycle instruction. In addition, a slow instruction degrades
instruction execution speed.
4.4 32-bit/16-bit Bus Converter
This converter generates the interface between D-bus which executes 32-bit high-speed access and R-bus
which executes 16-bit access in order to realize data access from CPU to peripheral functions.
If 32-bit access comes from CPU, this converter converts the access into two 16-bit accesses to access to R
bus. Some peripheral functions have restrictions of access width.
4.5 Harvard/Princeton Bus Converter
This converter realizes interface between instruction access and data access of CPU, to realize smooth
interface with external bus.
The CPU employs the Harvard architecture whose instruction bus and data bus are independent while it
employs single-bus Princeton architecture for bus controller to control external bus. This bus converter
prioritizes instruction accesses and data accesses of CPU, and executes access control to bus controller. This
always optimizes access sequence to external bus.
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Chapter 4 CPU Architecture
4.6
MB91460N series
4.6 Instruction Overview
The FR-family supports logic operation, bit operation and direct addressing instruction optimized for
embedded application as well as general RISC instruction system. Instruction-set list is shown in the appendix.
Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it is possible to generate
compact program code.
Instruction sets are grouped into the following function groups.
■ Arithmetic Operation
This group consists of standard arithmetic operation instructions (addition, subtraction and comparison) and
shift instruction (logic shift and arithmetic shift). For addition and subtraction, the operation with carry used for
multiple word length operation and the operation useful for address calculation without changing flag value are
allowed.
In addition, it includes 32-bit x 32-bit and 16-bit x 16-bit multiplication instruction as well as 32-bit/32-bit step
division instruction.
It provides transfer instruction of immediate value which sets immediate value to register, and transfer
instruction between registers.
All arithmetic instructions are operated using general-purpose register and multiply & divide register within
CPU.
■ Load and Store
Load/store is the instruction to read and write to memory. This is also used for read and write to peripheral
functions (I/O) within chip.
Load and store consist of 3 type access lengths including byte, half-word and word. In addition to general
register-indirect memory addressing, some instructions allow register-indirect memory addressing with
displacement or with register increment/decrement.
■ Branch
This is the instruction for branch, call, interrupt and return. Branch instruction consists of instructions with and
without delay slot. For more information of branch instruction, see "Chapter 7 Branch Instruction (Page
No.85)".
■ Logical Operation and Bit Operation
Logical operation instruction allows the logical operation of AND, OR and EOR between general-purpose
registers or general-purpose register and memory (and I/O). Bit operation instruction allows the direct
operation of data of memory (and I/O). Memory addressing is general register indirect.
■ Direct Addressing
Direct addressing instruction is the instruction to access between I/O and general-purpose register, or
between I/O and memory. By directly instructing I/O address rather than register indirect, it enables highspeed and high-efficient access. Some instructions allow register-indirect memory addressing with register
increment/decrement.
■ Others
This is the instruction which executes flag setting, stack operation, sign extension and zero extension within
PS register. It provides the function entrance/exit which supports high-level language, and register multi-load/
store instruction.
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CM44-10149-1E
Chapter 4 CPU Architecture
4.7
MB91460N series
4.7 Data Structure
FR-family CPU has two data allocations as follows.
■ Bit Ordering
FR60 family CPU uses little endian as bit ordering.
Figure 4.7-1 Bit Structure of Bit Ordering
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
MSB
■ Byte Ordering
FR60 family CPU uses big endian as byte ordering.
Figure 4.7-2 Bit Structure of Byte Ordering
Memory
MSB
bit31
23
15
7
LSB
0
10101010 11001100 11111111 00010001
bit
7
CM44-10149-1E
0
n address
10101010
(n+1) address
11001100
(n+2) address
11111111
(n+3) address
00010001
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Chapter 4 CPU Architecture
4.8
MB91460N series
4.8 Word Alignment
Since instructions and data are accessed by byte, allocated addresses vary by instruction length or data width.
■ Program Access
FR60 family CPU program is required to be allocated in addresses multiplied by 2.
PC's bit0 is cleared for instruction execution upon the PC update.
(PC bit 0 may be set when odd address is specified for branching address, however, it is invalid. Since the instruction is
required to be allocated in addresses multiplied by 2, there is no odd address exception.)
■ Data Access
FR60 family CPU provides the following alignment for addresses depending on data width when executing data
access.
• Word access
: Address is multiplied by 4. (Lowest order 2 bits are mandatorily 00.)
• Half-word access : Address is multiplied by 2. (Lowest order bit is mandatorily 0.)
• Byte access:
: Address is multiplied by 1.
Upon the word and half-word data accesses, some bits mandatorily become 0 for computing results of effective
address. For example, in the case of addressing mode of @(R13, Ri), register value before addition is used as
is (even if lowest order bit is 1), and lower bits of addition results are masked. Register values before computing
are not masked.
Figure 4.8-1 [Example] LD @(R13, R2), R0
R13
00002222
R2
00000003
Addition results
00002225H
+)
Address pin
64
00002224H
Lower 2 bits are
mandatorily masked.
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4.9 Addressing
Address space is 32-bit linear.
■ Map of address space
Figure 4.9-1 Address Map
0000 0000H
Byte data
0000 0100H
Half-word data
Direct addressing area
0000 0200H
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
FFFF FFFFH
FR60 family CPU has logical address space of 4GB (232 addresses), CPU accesses the data linearly.
■ Direct Addressing Area
The following areas are used for I/O.
These spaces are referred to as direct addressing area where direct operand address can be specified by the
instruction.
These direct areas vary by data size to be accessed.
• Byte access
: 000H to 0FFH
•
Half-word access : 000H to 1FFH
•
Word access
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Chapter 5 CPU Registers
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Chapter 5
CPU Registers
5.1 General-purpose Registers
Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and
memory access pointers on various operations.
Figure 5.1-1 General-purpose Registers
32 bit
[Initial value]
R0
R1
XXXX XXXXH
...
...
...
...
...
...
R12
R13
R14
R15
...
...
XXXX XXXXH
0000 0000H
AC
FP
SP
Of 16 registers, the following registers are reserved for special application.(In addition to functioning as
general-purpose registers)
• R13: Virtual accumulator
• R14: Frame pointer
• R15: Stack pointer
Initial values by reset are indeterminate for R0 through R14. Initial value by reset is 00000000H (SSP value)
for R15.
5.2 Dedicated Registers
Dedicated registers consist of program counter (PC), program status (PS), table-base register (TBR), return
pointer (RP), system stack pointer (SSP), user stack pointer (USP) and multiply & divide register (MDH/MDL).
Figure 5.2-1 Dedicated Registers List
Program Counter
(PC)
Program status
(PS)
Table-base register
(TBR)
Return pointer
(RP)
System stack pointer
(SSP)
User stack pointer
(USP)
-
ILM
-
SCR CCR
Multiply & divide registers (MDH)
(MDL)
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5.2.1 PC: Program Counter
Program Counter (PC) consists of 32 bits.
Figure 5.2-2 Bit Structure of Program Counter (PC)
0
bit 31
PC
[Initial value]
XXXXXXXXH
This register indicates the address of the instruction that is currently executing. After a reset, the initial value of the PC
is the reset entry address contained in the vector table.
5.2.2 PS: Program Status Register
Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR
and CCR.
All undefined bits are reserved bit. Upon the reading, "0" is always read. Writing is invalid.
Program status register (PS) consists of condition code register (CCR), system condition code register (SCR) and
interrupt level mask register (ILM).
Figure 5.2-3 Bit Structure of Program Status (PS)
bit
31
20
16
10
87
SCR
ILM
0
CCR
■ CCR: Condition Code Register
Figure 5.2-4 Structure of Condition Code Register (CCR)
bit
7
6
5
4
3
2
1
0
-
SV
S
I
N
Z
V
C
Initial value
--00XXXXB
• [Bit 6] SV: Super Visor flag
This bit indicates supervisor mode of the CPU/MPU
SV
Description
0
CPU/MPU is in User Mode
1
CPU/MPU is in Supervisor Mode
This bit becomes "0" by reset.
The SVMODE signal is sent to EDSU/MPU(set the SV flag and execute INT#5 ISR). the CPU/MPU is triggered by the
INT#5 instruction or by ORCCR and ANDCCR to clear the SV flag can be set. Hardware operation by the INT#5
instruction execution is the same as other interrupt instruction except when the SV flag is set.
For the Memory Protection Unit (MPU), please refer to "Chapter 26 MPU / EDSU".
• [Bit 5] S: Stack flag
This bit specifies stack pointer.
S
0
1
68
Description
Uses R15 as SSP. Upon generating EIT, this bit automatically becomes "0".
(Note that the value saved in stack is the value before clear.)
Uses R15 as USP.
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This bit becomes "0" by reset.
After using R15 as USP, write "0" before executing RETI instruction.
• [Bit 4] I: Interrupt enable bit
This bit enables and disables user interrupt request.
I
0
1
Description
Disables user interrupt.
Upon executing INT instruction, this bit becomes "0".
(Note that the value saved in stack is the value before clear.)
Enables user interrupt.1
Mask processing of user interrupt request is controlled by the value which is held in ILM.
1. For more information about user interrupt refer to "Chapter 6 EIT: Exceptions, Interrupts and
Traps (Page No.75)"
This bit becomes "0" by reset.
• [Bit 3] N: Negative flag
This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers.
N
0
1
Description
It indicates that operation result is positive value.
It indicates that operation result is negative value.
• [Bit 2] Z: Zero flag
This bit indicates whether operation result is 0 or not.
Z
0
1
Description
It indicates that operation result is other than 0.
It indicates that operation result is 0.
• [Bit 1] V: Overflow flag
This bit deems that operand used for operation as integer represented by two’s-complement numbers, and indicates
whether overflow was generated or not as the result of operation results.
V
0
1
Description
It indicates that overflow was not generated as the result of operation.
It indicates that overflow was generated as the result of operation.
• [Bit 0] C: Carry flag
This bit indicates whether carry or borrow from highest-order bit was generated or not as the result of operation.
Value
0
1
Description
It indicates that neither carry nor borrow is generated.
It indicates that either carry or borrow is generated.
■ SCR: System Condition Code Register
Figure 5.2-5 Structure of System Condition Code Register (SCR)
10
SCR
9
D1 D0
8
T
[Initial value]
XX0 B
This section describes each bit structure of system condition code register (SCR).
• [Bit 10, bit 9] D1 and D0: Step division flag
D1 and D0 bits hold intermediate data during the execution of step division.
Do not modify data during the execution of division processing.
If other processes are executed during the execution of step division, step division is assured to be restarted by saving
and returning PS register value.
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Initial status by reset is indeterminate for D1 and D0 bits.
Upon executing DIV0S instruction, these bits are set by referring to dividend and divisor.
Upon executing DIV0U instruction, these bits mandatorily become "00".
• [Bit 8] T: Step trace trap flag
This bit is the flag to enable step trace trap or not.
T value
0
1
Description
Disables step trace trap.
Enables step trace trap.
In this case, all user interrupts are disabled.
This bit is initialized to "0" by reset.
The function of step trace trap is used for emulator. During the use of emulator, this bit cannot be used for user
program.
■ ILM: Interrupt Level Mask Register
Figure 5.2-6 Register Structure of Interrupt Level Mask Register (ILM)
20
19
18
17
16
ILM4 ILM3 ILM2 ILM1 ILM0
[Initial value]
01111 B
• This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask.
• ILM indicates corresponding interrupt level from interrupt requests entered in CPU.
• Interrupt requests are accepted only if it’s priority is higher than the level.
• For level value, the highest priority is 0 (00000B), and the lowest priority is 31 (11111B).
• Program has some restrictions on configurable data.
•
When original value is between 16 and 31,
Configurable new values are the value between 16 and 31.
If the value to be set is specified between 0 and 15, "specified value +16" is set.
•
When original value is between 0 and 15,
Any value between 0 and 31 can be set.
These values are initialized to 15 (01111B) by reset.
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■ Caution: PS Register
Since some instructions have already processed PS register in advance, the following exception operations may break
interrupt processing routine during the use of debugger, or update PS flag data.
In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and
after EIT will be processed in accordance with specification.
• At instruction right before DIV0U/DIV0S instruction, the following 1. to 3. operation may be executed.
• If user interrupt request is received,
• If step execution is executed,
• If data event or emulator menu is broken,
1. D0 or D1 flag is updated in first.
2. EIT processing routine (user interrupt or emulator) is executed.
3. After returning from EIT, it executes DIV0U/DIV0S instruction and updates D0/D1 flag to the same value
as 1.
• When user interrupt request is generated, if any instruction of ORCCR, STILM, MOV Ri or PS is
executed to enable interrupt, the following operations are generated.
1. Updates PS register in first.
2. Executes EIT processing routine (user interrupt).
3. After returning from EIT, executes the instruction above and updates PS register to the same value as
1.
Note: For EIT, See "Chapter 6 EIT: Exceptions, Interrupts and Traps (Page No.75)".
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5.2.3 TBR: Table-base Register
Table-base register (TBR) consists of 32 bits.
Figure 5.2-7 Bit Structure of Table-base Register (TBR)
31
0
TBR
[Initial value]
000FFC00H
The Table-base register holds the first address of the vector table to be used during EIT processing.
The initial value upon reset is 000FFC00H.
5.2.4 RP: Return Pointer
Return pointer (RP) consists of 32 bits.
Figure 5.2-8 Bit Structure of Return Pointer (RP)
31
0
RP
[Initial value]
XXXXXXXXH
The return pointer holds the return address from a subroutine.
When the CALL instruction is executed, the value of the PC is transferred to the RP.
When the RET instruction is executed, the contents of the RP are transferred to the PC.
The initial value upon reset is undefined.
5.2.5 SSP: System Stack Pointer
System stack pointer (SSP) is used for the pointer which receives EIT and indicates stack to save/return data for return
operation.
System stack pointer (SSP) consists of 32 bits.
Figure 5.2-9 Bit Structure of System Stack Pointer (SSP)
31
SSP
0 [Initial value]
00000000H
When S flag is "0", it works as R15. SSP can explicitly specified.
Upon generating EIT, it is used for the pointer which specifies the stack to save PS and PC.
During the EIT process, this pointer reduces the value by 8, and adds 8 to the value during the return from EIT by
executing RETI instruction.
System stack pointer (SSP) works as general-purpose register R15 when S flag within CCR is "0".
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5.2.6 USP: User Stack Pointer
User Stack Pointer (USP) consists of 32 bits.
Figure 5.2-10 Bit Structure of User Stack Pointer (USP)
31
0
USP
[Initial value]
00000000H
When S flag is "1", this pointer works as R15.
USP can be explicitly specified.
RETI instruction cannot be used
This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates. After
interrupt, it stores PC in address where SSP indicates, and PS in (SSP+4) address.
Figure 5.2-11 Interrupt Stack
[Example]
SSP
[Before interrupt]
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
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7FFFFFFCH
7FFFFFF8H
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PC
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5.2.7 MDH, MDL: Multiply & Divide Register
Multiply & Divide register (MDH/MDL) consists of 32 bits.
Figure 5.2-12 Bit Structure of Multiply & Divide Register (MDH/MDL)
31
0
MDH
MDL
This is the register for multiplication and division and consists of 32 bits.
Initial value by reset is indeterminate.
■ At the executing multiplication
When 32 bits x 32 bits multiplication, operation results of 64 bits are stored in multiplication/division store register as
the following allocation.
• MDH: Upper 32 bits
• MDL: Lower 32 bits
When 16 bits x 16 bits multiplication, results are stored as follows.
• MDH: Indeterminate.
• MDL: Results of 32 bits
■ At the executing division
Upon starting operation, dividend is stored in MDL.
By computing division by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, results are stored in MDL
and MDH.
• MDH: Remainder
• MDL: Quotient
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MB91460N series
Chapter 6
EIT: Exceptions, Interrupts and Traps
6.1 Overview
EIT stands for Exception, Interrupt and Trap.
Interrupts, exceptions and traps are similar operations applied under partially differing conditions. Each "EIT"
event involves terminating execution of instructions, saving information for restarting, and branching to a
designated processing program. "EIT" processing programs can return to the prior program by use of the
"RETI" instruction.
"EIT" processing operates in essentially the same manner for exceptions, interrupts and traps, with the
following minor differences:
• Interrupts
originate independently of the instruction sequence. Processing is designed to resume from the instruction
immediately following the acceptance of the interrupt.
• Exceptions
are related to the instruction sequence, and processing is designed to resume from the instruction in which the
exception occurred.
• Traps
are also related to the instruction sequence, and processing is designed to resume from the instruction
immediately following the instruction in which the trap occurred.
6.2 Features
• Support of nested EITs:
• (multiple and simultaneous EITs)
• Both maskable and non-maskable interrupts
• The priority of all maskable interrupts is lower than the non-maskable ones
• Assignment of maskable interrupt priority levels by user
• Execution instructions
• Trap instructions
• Emulator operation support
• The priority of all EIT operations is lower than the Reset one
6.3 EIT Trigger
• Reset (highest priority of all)
• Interrupts
• Maskable interrupts
• Non-maskable interrupts
• Delayed interrupt
• Undefined-instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absent trap (only on devices with mounted coprocessor)
• Coprocessor error trap (only on devices with mounted coprocessor)
• CPU supervisor mode
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• Memory protection violation
6.4 Context saving
In the case of EITs processing, the values of the "PS" and "PC" are saved to the stack as designated by the
"SSP", regardless of the value of the "S" flag in the "CCR".
6.5 Recovery from EIT handler
RETI instruction is used for recovery from the EIT handler.
In order to guarantee the program execution results after recovery, it is required that all the contents of the
CPU register are saved.
It is important to note that the PC and PS values in the stack are not overwritten unless needed because those
values, saved in the stack at the occurrence of EIT, are recovered from the stack during the recovery
sequence using the RETI instruction. Be sure to set the "S" flag to 0 when the RETI instruction is executed.
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MB91460N series
6.6 EIT Interrupt Level
When multiple "EIT" requests occur at the same time, priority levels are used to select one source and
execute the corresponding "EIT" sequence. After the "EIT" sequence is completed, "EIT" request detection is
applied again to enable processing of multiple "EIT" requests. Acceptance of certain types of "EIT" requests
can mask other events. In such cases the priority applied by the "EIT" processing handler may not match the
priority of the requests.
Table 6.6-1 Interrupt Level of EIT
Binary
00000
...
...
00011
Level
Decimal
0
...
...
3
Description
Remarks
(Reserved for system)
...
...
(Reserved for system)
00100
4
INTE instruction
Step trace trap
If original value of ILM is between 16 and 31, these
values are not configurable to ILM by program.
00101
...
...
01110
01111
10000
10001
...
...
11110
11111
5
...
...
14
15
16
17
...
...
30
31
(Reserved for system)
...
...
(Reserved for system)
NMI (for users)
Interrupt
Interrupt
...
...
Interrupt
N/A
When ILM is set, user Interrupt is disabled.
When ICR is set, Interrupt is disabled.
The non-maskable interrupt priority cannot be configured by user. This priority is 15.
The maskable interrupt priority can be set by user. The priority of each maskable interrupt can be set in the
range from 16 to 31.
If the priority is equal to 31, then interrupt is disabled. This means that it will not be assigned.
Undefined-instruction exception, coprocessor absent trap, coprocessor error trap and INT instruction are not
affected by interrupt level. Also, ILM is not changed by interrupt level.
6.7 EIT Vector Table
The vector table is located in the main memory, occupying an area of 1K bytes beginning with the address
contained in the TBR. Vectors are 4 bytes in length. Therefore, 255 vectors are located in this area in the main
memory.
These areas are intended for use as a table of entry addresses for "EIT" processing. However in applications
where vector tables are not required, this area can be used as a normal instruction or data area.
The vector address is calculated as follows:
Vector address = [TBR] + Offset value = [TBR] + (03FCH - 4 × Vector number)
Lower two bits as the result of addition are always used for "00".
The initial value of the TBR register after a reset is equal to 000FFC00H. Therefore, the initial location of the
vector table after a reset is 000FFC00H through 000FFFFFH.
Both the mode and reset vector have a fixed addresses 000FFFF8H and 000FFFFCH respectively. These
addresses remain fix, although the TBR register is rewritten.
For more information about the EIT vector table, refer to the chapter of "3.3 INTERRUPT SOURCE TABLE
(Page No.40)".
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6.8 Multiple EIT Processing
If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to
accept, and then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting
EIT, CPU executes instruction of the last accepted EIT handler. Therefore, if multiple EITs are generated at
the same time, execution sequence of each EIT handler is determined by the following two parameters.
■ Basic Operations in "EIT" Processing
The FR family device processes "EIT" events as follows:
(1) The vector table indicated by the table base register (TBR) and the number corresponding to the particular
"EIT" event are used to determine the entry address for the processing program for the "EIT".
(2) For restarting purposes, the contents of the old program counter (PC) and the old program status (PS) are
saved to the stack area designated by the system stack pointer (SSP).
(3) After the processing flow is completed, the presence of new "EIT" sources is determined.
■ Priority Level of EIT Triggers
Priority level of EIT triggers defines the sequence to select which EIT triggers to execute by saving PS and PC
in order to update PC and masking other triggers where appropriate.
EIT does not always mean first-in first-out handler.
Table 6.8-1 Priority Level of Receipt of EIT Triggers and Mask for Other Triggers
Priority for accepting EITs
1
2
3
4
5
6
7
8
9
10
11
EIT
Masking of other EITs
Reset
All EITs are cleared
Instruction Break
Other EITs are canceled (ILM = 4)
INTE instruction
Other EITs are canceled (ILM = 4)
Undefined instruction exception
Other EITs are canceled (I-flag = 0)
INT instruction / Coprocessor exceptions I-flag = 0
Memory protection violation
I-flag = 0
User interrupt
ILM = level of accepted INT
NMI (user)
ILM = 15
NMI (emulator)
Other EITs are canceled (ILM = 4)
Step Trace trap
Other EITs are canceled (ILM = 4)
Operand Break
Other EITs are canceled (ILM = 4)
■ How to Mask Other Triggers upon acceptance
Table below shows the execution sequence of each handler when multiple EIT requests are generated at the
same time considering mask processes.
Table 6.8-2 Execution Sequence of EIT Handlers
Handler execution Priority
1
2
3
4
5
6
7
8
9
10
11
78
EIT
Reset
Undefined instruction exception
Instruction Break
INTE instruction
NMI (emulator)
Step Trace trap
Operand Break
NMI (user)
Memory protection violation
INT instruction / Coprocessor exceptions
User interrupt
Masking of other EITs
All EITs are cleared
Other EITs are canceled (I-flag = 0)
Other EITs are canceled (ILM = 4)
Other EITs are canceled (ILM = 4)
Other EITs are canceled (ILM = 4)
Other EITs are canceled (ILM = 4)
Other EITs are canceled (ILM = 4)
ILM = 15
I-flag = 0
I-flag = 0
ILM = level of accepted INT
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Figure 6.8-1 Multiple EITs Process
NMI handler
Main routine
INT instruction
handler
(1) First execution
User interrupt
handler
Priority
(High) Generation of NMI
(2) Second execution
(Middle) Execution of INT instruction
(Low) Execution of user interrupt
(3) Third execution
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6.9 Operation
In this section, the following nomenclature is used:
Source "PC" is the address of the current instruction which is executing at the time when an EIT request takes
place.
"Address of next instruction" is the next address from the current instruction which is executing at the time
when an EIT request takes place.
• When LDI is 32: PC+6
• When LDI is 20, and it is COPOP, COPLD, COPST or COPSV: PC+4
• For other instructions: PC+2
6.9.1 User Interrupt operation
If user interrupt request occurs, it determines whether to accept its request or not in the following sequence.
■ How to determine whether to accept interrupt request or not
1. Selects the interrupt which holds the highest priority level (the smallest number) by comparing interrupt
request levels generated at the same time.
For the level to be compared, it uses the value which ICR holds corresponding to maskable interrupt.
2. Selects the interrupt request which has the lowest interrupt number if multiple interrupt requests with the
same priority level are generated.
3. Where "Interrupt level >
= Level mask value", the interrupt request is masked without acceptance. Where
"Interrupt level < Level mask value", it goes forward to Step 4.
4. When selected interrupt request is maskable interrupt, if I flag is 0, its Interrupt request is masked without
acceptance and if I flag is 1, it goes forward to Step 5.
5. If the conditions above are satisfied, interrupt requests are accepted between instruction processes.
If user interrupt requests are accepted upon detecting EIT requests, CPU executes the following operations
according to the Interrupt number for the interrupt request accepted.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the next instruction is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value (level) of the accepted interrupt is stored in the "ILM".
5. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
6. The vector address of the accepted interrupt is stored in the program counter (PC).
After the interrupt sequence, EIT is checked again before executing the main program handler’s instruction. If
any EIT is generated at this time, the CPU goes to EIT process sequence.
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6.9.2 Operation of INT Instruction
INT #u8 instruction is operated as follows.
Branches to interrupt handler of vector specified in INT #u8.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the next instruction is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value "0" is written to the "I" flag in the condition code register (CCR) in the program status (PS).
5. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
6. The value "TBR+3FCH-4 × u8" is stored in the program counter (PC).
6.9.3 Operation of INTE Instruction
INTE instruction is operated as follows.
Branches to vector interrupt handler of vector #9.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the next instruction is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value (level) "4" is stored in the "ILM".
5. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
6. The value "TBR+3D8H" is stored in the program counter (PC).
During the execution of step, EIT is not generated by INTE.
Since INTE instruction is used for the debug support unit (DSU), do not use it.
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6.9.4 Operation of Step Trace Trap
If T flag is set in SCR within PS and enable step trace trap function, step trace trap is generated with each
following executing instruction.
■ Condition for detecting step trace trap
T flag = 1
Instructions are other than delayed branch command.
During the execution of instructions other than INTE instructions or step trace trap process routines.
If conditions above are satisfied, it is broken between instruction operations.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the next instruction is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value (level) "4" is stored in the "ILM".
5. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
6. The value "TBR+3CCH" is stored in the program counter (PC).
If T flag is set to enable step trace trap, user interrupt is disabled.
In addition, EIT will not be generated by INTE instruction.
FR-family CPU generates traps from next instruction to instruction which set T flag.
6.9.5 Operation of Undefined-instruction Exception
If any undefined instruction is detected upon decoding instruction, an undefined-instruction exception is
generated.
■ Condition for detecting an undefined-instruction exception
• Upon the decoding instruction an undefined instruction is detected.
• It is out of delayed slot. (It is not the instruction which is right after delay branch instruction.)
If conditions above are satisfied, undefined-instruction exception will be generated.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
5. The value "TBR+3C4H" is stored in the program counter (PC).
The address of the instruction which has detected an undefined-instruction exception is saved as PC.
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6.9.6 Coprocessor Absent Trap
If coprocessor instruction for unmounted coprocessor is executed, a coprocessor absent trap is generated.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the instruction following the one which caused the undefined instruction exception is saved
to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
5. The value "TBR+3E0H" is stored in the program counter (PC).
6.9.7 Coprocessor Error Trap
If an error occurs during the use of a coprocessor, a coprocessor error trap is generated when coprocessor
instruction is executed in order to operate the coprocessor next time.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the instruction following the one which caused the undefined instruction exception is saved
to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
5. The value "TBR+3DCH" is stored in the program counter (PC).
6.9.8 Operation of RETI Instruction
The RETI instruction is the instruction which returns from EIT process routine.
■ Operation
1. Load data from stack indicated by (R15)* to the program counter (PC).
2. Increment R15+4 and store to R15.
3. Load data from stack indicated by (R15)* to the program status (PS).
4. Increment R15+4 and store to R15.
The RETI instruction should be executed with S flag "0".
6.10 Caution
• Since the INTE instruction is used for the Debug Support Unit (DSU), do not use it in any application.
• The delay slot for branch instruction has restrictions on EIT.
See "Chapter 7 Branch Instruction (Page No.85)".
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Chapter 7 Branch Instruction
7.1
MB91460N series
Chapter 7
Branch Instruction
7.1 Overview
The FR-family CPU can execute both delayed and non-delayed branching instructions.
The position of an instruction immediately following a branching instruction which is already loaded by the
pipeline operation is called the delay slot.
In pipeline operation, by the time the CPU recognizes an instruction as a branching instruction the next
instruction has already been loaded. To process the program as written, the instruction following the branching
instruction must be canceled in the middle of execution. Branching instructions that are handled in this manner
are non-delayed branching instructions. As a result, the program is processed in the order in which it is written,
and the branching instruction requires an apparent processing time of two cycles.
A delayed branching instruction is a branching instruction that executes the instruction in the delay slot
regardless of whether the branching conditions are satisfied or not satisfied. This means that the apparent
order of instruction processing is changed.
The FR family CPU processes delayed branching instructions with an apparent execution speed of 1 cycle,
regardless of whether branching conditions are satisfied or not. When branching occurs, this is one cycle
faster than using non-delayed branching instructions.
7.2 List of Delayed Branching instructions
• The following branching instructions are delayed
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D
BNE:D label9
BC:D label9
BNC:D label9
BN:D
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
label9
label9
BP:D
label9
7.3 Operation of Delayed Branching Instructions
In pipeline operation, the instruction located in the next position of a branching instruction is executed before.
This means that just after the instruction located in the delay slot is executed, the branching instruction is
processed. So that the apparent order of instruction processing is changed in cases where delayed branching
occurs.
If a delay slot contains a not valid instruction, then a NOP instruction is executed.
Below the example shows how a delayed branching instruction is executed:
Figure 7.3-1 Example (Branch instruction with delay slot)
;
Sequence of instruction
ADD
R1,
R2
BRA:D LABEL
MOV
R2,
R3
...
LABEL : ST
R3,
@R4
;
; Branch instruction
; Delay slot ...... To be executed before the branch.
; Branched instruction
In case of conditional delayed branching instructions, the instruction located in the delay slot is executed
regardless of whether the branching conditions are satisfied or not.
In delay branch instruction, execution sequence of some instructions seems opposite, however, it only applies
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to updating process on the PC. Any other operation (register update/look-up) is executed in the order of
description.
7.4 Some Examples of Delayed Branching Instructions
7.4.1 JMP:D @Ri / CALL:D @Ri
Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay slot update
Ri.
Figure 7.4-1 Example
LDI:32
JMP:D
LDI:8
...
#Label,
@R0
#0,
R0
R0
; Branches to Label.
; Not affect any branched address.
7.4.2 RET:D Instruction
RP referred in RET:D instruction remains intact even if instructions within delay slot update RP.
Figure 7.4-2 Example
RET:D
MOV
...
R8,
RP
; Branches to the address previously specified in RP.
; Not affect any return operation.
7.4.3 Bcc:D rel Instruction
Flag referred in Bcc:D rel instruction also remains unaffected by instructions within delay slot.
Figure 7.4-3 Example
ADD
#1,
R0
BC:D
Overflow
ANDCCR #0
...
; Change of flag
; Branches in accordance with the execution result of instructions above.
; This flag update is not referred in branch instruction above.
7.4.4 CALL:D Instruction
When RP is referred using the instruction within delay slot of CALL:D instruction, the data updated by CALL:D
instruction is read out.
Figure 7.4-4 Example
CALL:D Label
MOV
RP,
...
86
R0
; Branches by updating RP.
; Transfers RP based on the execution results of CALL: D above.
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MB91460N series
7.5 Restrictions on Branch Instruction with Delay Slot
7.5.1 Available Instructions for Delay Slot
Only the instructions located at the delay slot which meet the following requirements can be executed:
• 1-cycle instruction;
• Non-branch instruction; and
• Instruction which does not affect any operation even if its sequence is changed.
"1-cycle instruction" indicates instructions whose number of cycles column in the instruction list table is
described with "1", "a", "b", "c" or "d".
7.5.2 Step Trace Trap
The step trace trap is not generated at the time between the execution of a delayed branching instruction and
the execution of the instruction located at the delay slot.
7.5.3 Interrupt
Interrupts are not accepted at the time between the execution of delayed branching instruction and the
instruction located at the delay slot.
7.5.4 Undefined-instruction Exception
If an undefined instruction exists in delay slot, then the undefined instruction-exception is not generated. In this
case, undefined instruction works as NOP instruction.
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7.6 Branch Instruction without Delay Slot
• The following branching instructions are non-delayed:
JMP @Ri
CALL label12
CALL @Ri
RET
BRA label9
BNO label9
BEQ label9
BNE label9
BC label9
BNC label9
BN
BP
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
label9
label9
7.7 List of Non-Delayed Branch Instructions
In pipeline operation, the instruction located in the next position of a non-delayed branching instruction is
never executed.
The example below shows how a non-delayed branching instruction is executed:
Figure 7.7-1 Example (Branch Instruction without Delay Slot)
;
Sequence of instruction
ADD
R1,
R2
BRA:D LABEL
MOV
R2,
R3
...
LABEL ST
R3,
@R4
;
; Branch instruction (without delay slot)
; Not to be executed.
; Branched instruction
The number of execution cycles of non-delayed conditional branching instruction is equal to 2 cycles if the
branching conditions are satisfied and only equal to 1 cycle if the branching conditions are not satisfied.
Therefore, select the delayed branching instruction when a valid instruction can be set at the delay slot.
Otherwise select a non-delayed one in order to avoid an additional processing cycle regarding the execution of
a NOP instruction instead of a non-valid instruction. This selection enables FR-family CPU to satisfy both of
execution rate and code efficiency.
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8.1
MB91460N series
Chapter 8
Device State Transition
8.1 Overview
MB91460N series basically has devices state and flow as shown below.
For more information, see "8.3 State Transition Diagram (Page No.90)".
Figure 8.1-1 Overview Diagram of Device State Transition
State transition
Power-on
Watchdog reset
INITX-pin input
Setting-initialization
reset (INIT)
Oscillation-stabilization
wait reset
Operation-initialization
reset (RST)
Software-reset instruction
RUN
Interrupt request
Oscillation-stabilization-wait RUN
STOP
Interrupt request
SLEEP
8.2 Features
■ Device state
•
•
•
•
RUN (Normal operation): State where the program is executed.
SLEEP: State where the program is stopped (peripheral circuits are operating).
STOP: State where the device is stopped.
Oscillation-stabilization-wait RUN: State to return from the STOP to the RUN state (waiting until clock
oscillation is stabilized).
• Oscillation-stabilization-wait reset: State for waiting until the clock oscillation is stabilized after INIT.
• Operation-initialization reset (RST): State where the program is initialized.
• Setting-initialization reset (INIT): State where all settings are initialized.
■ Standby mode (Low-power-consumption mode)
SLEEP and STOP above are standby modes.
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8.3 State Transition Diagram
This section describes state transition.
Figure 8.3-1 State Transition of MB91460N Series
1
2
3
4
5
6
7
8
9
10
INITX pin = 0 (INIT)
INITX pin = 1 (Cancel of INIT)
Termination of oscillation-stabilization wait
Cancel of reset (RST)
Software reset (RST)
SLEEP (Writing instruction)
STOP (Writing instruction)
Interrupt
External interrupt requiring no clock
Watchdog reset (INIT)
Highest Priority of transition request
priority Setting-initialization reset (INIT)
Termination of oscillation-stabilization wait
Operation-initialization reset (RST)
Interrupt request
Lowest STOP
priority SLEEP
Power-on
1
Setting-initialization
reset (INIT)
2
Main clock mode
1
Oscillation stabilization
wait reset
Main-STOP
9
1
1
3
Oscillation stabilization
wait RUN
1
Program reset
(RST)
3
4
7
5
10
1
6
Main-SLEEP
Main-RUN
1
8
8.3.1 RUN (Normal Operation)
This is the state where program is executed with all clocks and all circuits are enabled.
This state has various paths for a state transition. However, if the synchronous reset mode is selected the
state transition operations for some requests are different from normal reset mode. For more information, see
the chapter of "Chapter 9 Reset".
8.3.2 SLEEP
This is the state where only the CPU's program execution is stopped and the peripheral circuits are operating.
Embedded memories and internal bus are stopped unless the DMA controller requests them. This state is
invoked by the program.
• Upon generation of valid interrupt requests the SLEEP state is cancelled and the RUN state (Normal
operation) is entered.
• Upon generation of the external reset request by INITX pin the setting-initialization reset state (INIT) is
entered.
• Upon generation of the operation-initialization reset request (by the software reset) the operationinitialization reset state (RST) is entered.
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8.3.3 STOP
This is the state where all internal circuits, all internal clocks and the PLL are stopped. Main oscillation and RC
oscillation (which can be connected to the Real Time Clock (RTC) can be stopped by setting the related
registers). This state is invoked by the program.
Additionally high impedance for external pins can be enabled by setting the related register.
• Upon generation of specific valid interrupt requests (requiring no clock), active oscillation timer interrupt or
Main clock oscillation stabilization timer interrupt request the oscillation stabilization wait RUN state is entered.
• Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization
reset state (INIT) is entered.
• Upon generation of the operation-initialization reset request (by the software reset) the operationinitialization reset state (RST) is entered.
The Real Time Clock (RTC) can be supplied in the STOP state with main oscillation clock, if the control bits for
oscillation disable (OSCDx of the STCR register) are not set to disable.
8.3.4 Oscillation-stabilization-wait RUN
All internal circuits are stopped except for clock generation control parts (timebase counter and device state
control parts). All internal clocks are stopped while oscillation circuits and enabled Main PLL is operated. This
state is entered automatically after the return from STOP.
•
High-impedance control of external pins by STOP is cancelled.
•
After the configured oscillation-stabilization-wait time has passed, the RUN (Normal operation) state is
entered.
• Upon generation of the setting-initialization reset request by the external INITX pin, the setting-initialization
reset state (INIT) is entered.
• Upon generation of the operation-initialization reset request (by the software reset), the operationinitialization reset state (RST) is entered.
8.3.5 Oscillation-stabilization-wait Reset
This is the state where the device is stopped. This state is entered upon a setting-initialization reset (INIT).
All internal circuits are stopped except for clock generation control parts (timebase counter and device state
control parts). All internal clocks are stopped while oscillation circuits and Main PLL (if enabled) are operating.
• High-impedance control of external pins by STOP is cancelled.
•
For internal circuits this state outputs operation-initialization reset (RST).
• After configured oscillation-stabilization-wait time has passed the oscillation-stabilization-wait reset state is
entered.
• Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization
reset state (INIT) is entered.
•
See "Chapter 17 Timebase Timer" for the oscillation stabilization wait time.
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8.3.6 Operation-initialization Reset (RST)
This is the state where the program execution is initialized. Upon receipt of the operation-initialization reset
(software reset) request or the termination of the oscillation-stabilization-wait reset (RST) this state is active.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized except for
some peripheral circuits. All internal clocks, oscillation circuits and enabled Main PLL are operating.
•
For internal circuits this state asserts operation-initialization reset (RST).
• Upon clear of request of operation-initialization reset (RST) this state transits to the RUN (normal
operation) state and executes the operation-initialization reset sequence. Upon returning from settinginitialization reset (INIT) this state executes the setting-initialization reset sequence.
• Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization
reset state (INIT) is entered.
8.3.7 Setting-initialization Reset (INIT)
This is the state where all settings are initialized. Upon receipt of request of setting-initialization reset (INIT)
this state is active.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized. Oscillation
circuits are operating while the Main PLL is stopped. All internal clocks are operating except while "L" level is
input to the external INITX pin.
• For internal circuits this state asserts the setting-initialization reset (INIT) and the operation-initialization
reset (RST).
• Upon clear of the setting-initialization reset (INIT) request this state cancels the setting-initialization reset
state and then enters to the oscillation-stabilization-wait reset. After that it executes the operation-initialization
reset sequence.
8.3.8 Priority of Each Request of State Transition
In any state, each request of the state transition is subject to the following priority:
[Highest
priority]
[Lowest
priority]
92
Request of setting-initialization reset (INIT)
Termination of oscillation-stabilization-wait time (This is generated only in state of
oscillation-stabilization-wait reset and oscillation-stabilization-wait RUN.)
Request of operation-initialization reset (RST)
Request of valid interrupt (This is generated only in RUN, sleep or stop state.)
Request of stop mode (Writing in register) (This is generated only in RUN state.)
Request of sleep mode (Writing in register) (This is generated only in RUN state.)
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9.1
MB91460N series
Chapter 9
Reset
9.1 Overview
When a reset is triggered, the device halts the program and all hardware operation, and then initializes all
states. This state is called a reset.
When the reset trigger condition is removed, the device changes from this initialized state to restart the
program and hardware operation. The series of steps from removal of the reset condition until operation starts
is called the reset cancellation sequence.
Figure 9.1-1 Flow of Reset Operation
Power ON
INITX pin input
From any state
Settings initialization reset (INIT)
Watchdog timeout
Oscillation stabilization
wait reset
Operation initialization
reset (RST)
RUN
Software reset instruction
9.2 Features
• Types of reset
• INITX pin input: Settings initialization reset (INIT)
• Watchdog reset: Settings initialization reset (INIT)*
• Software reset: Operation initialization reset (RST)
• Low Voltage reset: Settings initialization reset (INIT)
*: Although a watchdog reset triggers the same settings initialization reset (INIT) as the INITX pin input, it does
not initialize the oscillation stabilization time selection bits (OS[1:0]) and reset cause flags (INIT, WDOG, SRST and
LINIT).
• Cause of reset can be determined
• The cause of the previous reset is stored in a series of flags (INIT, WDOG, SRST and LINIT) in the
RSRR register.
• Operation after reset conditions are removed
• Operating mode: Determined by the mode pins and mode data.
• After a setting-initialization reset (INIT), an operation reset (RST) occurs when the oscillation stabilization
wait time has elapsed.
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9.3 Configuration
Figure 9.3-1 Configuration Diagram of Reset operation
MD0
State transition control circuit (reset related)
MD1
MD2
SLEEP
STCR:
STCR:bit7
bit6
0
1
OSCD1
0
1
Do not change to sleep mode
Change to sleep mode
Sleep signal
STOP
STCR:
STCR:bit7
bit7
Stop signal
0
1
Do not change to stop mode
Change to stop mode
STCR:STCR:
bit1 bit0
Main clock continues to operate during stop mode
State
transition
control
circuit
Main clock halts during stop mode
HIZ
STCR:
STCR:bit0
bit5
0
1
Maintain pin states during stop mode
Set pins to high impedance during stop mode
Clock control
Pin control
Internal interrupts, external interrupts
SRST
0
1
STCR: bit4
Initialization reset (INIT)
Trigger software reset
Do not trigger software reset
INITX
Operation reset (RST)
INIT
RSRR:
RSRR: bit7
bit7
0
1
No INIT pin input
INIT pin input occurred
SRST
Oscillation stabilization wait ended
Clear counter and
start oscillation
stabilization wait
RSRR: bit3
bit
0
1
No software reset RS
(RST)
T)
Software reset (RST) occurred
RS T)
Time-base counter
(oscillation stabilization wait)
Watchdog timer
WDOG
RSRR:
RSRR:bit5
bit5
0
1
No watchdog timeout
Watchdog timeout(INIT)
(INIT) occurred
Figure 9.3-2 Register List
RSRR/STCR
Address
94
Bit 7
INIT
6
00480H
00481H
Bit 7
STOP
6
SLEEP
5
WDOG
4
5
HIZ
4
SRST
3
SRST
2
LINIT
1
WT1
0
WT0
RSRR
(Reset cause)
3
OS1
2
OS0
1
0
OSCD1
STCR
(Standby control)
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9.4
MB91460N series
9.4 Registers
9.4.1 RSRR: Reset Cause Register
Stores the cause of the previous reset, and sets the watchdog interval time for the watchdog timer.
• RSRR: Address 000480H (Access: Byte, Half-word)
7
INIT
6
-
5
WDOG
4
-
3
SRST
2
LINIT
1
WT1
0
WT0
1
0
0
0
0
0
0
0
-
-
-
X
X
-
0
0
X
X
X
-
-
X
0
0
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/W
R/W
bit
Initial value
(INITX pin input)
Initial value
(Watchdog reset)
Initial value
(Software reset)
Attribute
Note: See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.
Reading the reset request cause returns the reset cause flags and then clears the flag values to "0".
If multiple resets occur prior to reading the register, the resulting flag values contain the bitwise OR of the flags
for each reset. That is, more than one flag may be set to "1".
• Bit7: Initialization reset occurred flag
Indicates whether a reset (INIT) was triggered by INITX pin input.
INIT
0
1
Meaning
No INIT has been triggered by the INITX pin input.
INIT has been triggered by the INITX pin input or by the hardware watchdog.
The initialization reset occurred flag (INIT) is cleared to "0" after reading.
See "Chapter 19 Hardware Watchdog Timer (Page No.205)" for details.
• Bit6: Reserved bit
• Bit5: Watchdog reset occurred flag
Indicates whether a reset (INIT) was triggered by the watchdog timer.
WDOG
0
1
Meaning
No INIT has been triggered by the watchdog timer.
INIT has been triggered by the watchdog timer.
The watchdog reset occurred flag (WDOG) is cleared to "0" after reading.
• Bit4: Reserved bit
• Bit3: Software reset occurred flag
Indicates whether a software reset has been triggered by writing to the software reset bit (STCR:SRST).
SRST
0
1
Meaning
No RST has been triggered by a software reset.
RST has been triggered by a software reset.
The software reset occurred flag (SRST) is cleared to "0" after reading.
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• Bit2: Low voltage reset occurred flag
Indicates whether a reset (INIT) was triggered by the low voltage detection.
LINIT
0
1
Meaning
No INIT has been triggered by the low voltage detection.
INIT has been triggered by the low voltage detection.
The low voltage reset occurred flag (LINIT) is cleared to "0" after reading.
• Bit1, bit0: Watchdog interval time selection
The watchdog period selection bits (WT[1:0]) can set the period of the watchdog timer to the following:
(φ × 220 to 221, φ × 222 to 223, φ × 224 to 225, φ × 226 to 227)
See "Chapter 18 Software Watchdog Timer (Page No.195)" for details.
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9.4.2 STCR: Standby Control Register
This register is used for software reset control (changing to standby mode, pin control in STOP state, and
clock oscillation halted in STOP state), and specifies the oscillation stabilization wait time.
Note: See also "Chapter 10 Standby (Page No.107)".
• STCR: Address 000481H (Access: Byte, Half-word)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
-
0
OSCD1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
1
1
0
0
X
1
X
X
X
X
R/W
R/W
R/W
R1,W
R/W
R/W
RX/WX
R/W
bit
Initial value
(INITX pin input)
Initial value
(Watchdog reset)
Initial value
(Software reset)
Attribute
Note: See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.
• Bit7: STOP state
Writing "1" to the STOP state bit (STOP) changes to STOP state.
See "Chapter 10 Standby (Page No.107)" for details.
• Bit6: SLEEP state
Writing "1" to the SLEEP state bit (SLEEP) changes to SLEEP state.
See "Chapter 10 Standby (Page No.107)" for details.
• Bit5: High impedance mode
Writing "1" to the high impedance mode bit (HIZ) sets pin to high impedance (Hi-Z) during STOP state.
See "Chapter 10 Standby (Page No.107)" for details.
• Bit4: Software reset
Writing "0" to the software reset bit triggers a software reset.
SRST
0
1
Operation
A software reset is issued.
No software reset is issued.
• Note that negative logic is used.
• The read value is always "1".
• Bit3, bit2: Oscillation stabilization time
The oscillation stabilization time selection bits (OS[1:0]) set the oscillation stabilization time as follows:
(φ × 21, φ × 211, φ × 216, φ × 222)
The count is supplied by the timebase counter.
Initialized to "00" (φ × 21, Main clock) by a reset triggered by INITX pin input.
See "Chapter 17 Timebase Timer (Page No.185)" for details.
• Bit1: Reserved bit
Writing to this bit does not affect the operation.
• Bit0: Halt Main clock oscillation
Writing "1" to the halt Main clock oscillation bit (OSCD1) halts the oscillation of the Main clock during STOP state.
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9.4.3 MD: Mode Pins
These pins specify the location of the mode vector and reset vector that are read after the MCU is reset. The
MD pins are validated by INITX pin = 0, other MD pins are not involved in the mode vector fetch.
Mode pins
MD2 MD1 MD0
0
0
0
0
0
1
Mode name
Reset vector
Access area
Internal ROM mode
vector
External ROM mode
vector
Remarks
Internal
External
Setting disabled
9.4.4 Mode Vector
The data written to the mode register (MODR) by the mode vector fetch operation is called the mode data.
(The mode register is an internal register and cannot be written to or read from directly.)
After the mode register is set, the MCU operates in accordance with the modes (bus mode and access mode)
set in this register.
The mode data is set by all types of reset. Setting the mode data from the user program is not possible.
Be sure to write "00000111B". If a value other than "00000111B" is set, the operation is not guaranteed.
• Mode Vector: Address 0FFFF8H (Access: Byte, Half-word, Word)
31
0
30
0
29
0
28
0
27
0
26
ROMA
25
WTH1
24
WTH0
Bit
Operation mode setting bits
• Bit31 to bit27: Reserved bits
Always set these bits to "00000B".
If a value other than "00000B" is set, the operation of the MCU is not guaranteed.
• Bit26: Internal ROM enable
Specifies whether to enable the internal ROM area.
ROMA
0
1
Function
External ROM mode
Internal ROM mode
Remarks
Enables the external ROM area.
Enables the internal ROM area.
Always set to "1".
• Bit25, bit24: Bus width setting
This sets the bus width for external bus mode.
WTH1
0
0
1
1
WTH0
0
1
0
1
Function
8-bit bus width
16-bit bus width
32-bit bus width
Single chip mode
Remarks
• Bit23 to bit0: Undefined bits
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9.4.5 Reset Vector
The MCU starts program execution from the address specified by the reset vector.
Initial value to load into PC.
Address
0007FDH
MODR
000FFFF8 H Mode
Vector
000FFFFC H Reset
Vector
XXXXXXXX XXXXXXXX XXXXXXXX
PC
9.4.6 Device Mode Overview
The following table gives a combination of supported device modes on the MB91460N series:
Mode pins
MD2 MD1 MD0
0
0
0
0
0
1
Mode/Reset
Vector
access area
ROMA
ROM
access
area
0
External
1
Internal
Internal
0
External
1
Internal
External
WTH[1:0]
Bus
width
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
8bit
16bit
32bit
Single
8bit
16bit
32bit
Single
8bit
16bit
32bit
Single
8bit
16bit
32bit
Single
Remarks
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Setting not supported
Remarks:
• On the MB91460N series the ROM area is from 000C0000H up to 000FFFFFH, and from 00148000H up to
0014FFFFH.
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MB91460N series
9.5 INITX Pin Input (INIT: Settings Initialization Reset)
9.5.1 Trigger
The INITX pin is used to trigger a settings initialization reset.
A settings initialization reset (INIT) request remains active while the pin remains at the "L" level. Keep the "L"
level for the main oscillation stabilization wait time.
9.5.2 Releasing the Reset Request
Inputting an "H" level to the pin after the main oscillation stabilization wait time releases the settings
initialization reset (INIT) request.
9.5.3 Flag
When an pin request triggers a settings initialization reset (INIT), the settings initialization reset flag
(RSRR.INIT) is set to "1".
9.5.4 Reset Level
This reset has the maximum reset level and initializes all settings. This type of reset is called the settings
initialization reset (INIT)
A settings initialization reset (INIT) triggered by INITX pin input has the highest priority of all resets and has
priority over all other inputs, operations, and states.
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the oscillation
stabilization time elapses.
9.5.5 Initialization Triggered by INITX Pin Input (INIT)
•
•
•
•
Device operation mode (bus mode and external bus width setting)
All internal clock related settings (clock source selection, Main PLL control, division setting)
All other settings related to pin states
All areas initialized by an operation reset (RST)
• Program operation
• CPU and internal bus
• Peripheral circuit register contents
• I/O port settings
• Device operation mode (bus mode and external bus width setting)
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9.5.6 Reset Cancellation Sequence
After the cancellation (removal) of the settings initialization reset (external INITX pin) request the device
performs the following operations in the sequence listed.
1. Removal of settings initialization reset (INIT)
2. Set operation reset (RST) state and start internal clock
3. Clear operation reset (RST) state and change to normal operation (RUN)
4. Read mode vector from address 000FFFF8H
5. Write mode vector to MODR (mode register)
6. Read reset vector from address 000FFFFCH
7. Write reset vector in PC (program counter)
Start program execution from the address specified by PC (program counter)
Note: See explanation in "16.5 Operation (Page No.176)".
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MB91460N series
9.6 Watchdog Reset (INIT: Settings Initialization Reset)
9.6.1 Trigger
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a watchdog
reset request is generated unless "A5H" and "5AH" are written to the watchdog reset delay register (WPR)
within the time specified by the watchdog period selection bits (RSRR:WT[1:0]).
9.6.2 Releasing the Reset Request
The watchdog reset request invokes a settings initialization reset (INIT). The watchdog reset request is
released after the request is received and the settings initialization reset (INIT) generated, or when an
operation reset (RST) occurs.
9.6.3 Flag
When watchdog reset request is triggered, the watchdog timeout flag (RSRR:WDOG) is set to "1".(SWWD and
HWWD)
In addition the HWWD sets cpu reset flag (HWWD:CPUF) to "1", and a settings initialization reset (RSRR:
INIT) is triggered.
9.6.4 Reset Level
This reset has the maximum reset level and initializes all settings. This type of reset is called the settings
initialization reset (INIT).
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the oscillation
stabilization time elapses.
9.6.5 Initialization Triggered by Watchdog Reset (INIT)
Same as for a reset triggered by an INITX pin input.
However, the oscillation stabilization time selection bits (STCR:OS[1:0]) and reset cause flags (INIT, WDOG,
SRST) are not initialized and retain their existing values.
9.6.6 Reset Cancellation Sequence
Same as for INITX pin input.
(See "Chapter 18 Software Watchdog Timer (Page No.195)" for details.)
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9.7
MB91460N series
9.7 Software Reset (RST: Operation Initialization Reset)
9.7.1 Trigger
Writing "0" to the software reset bit (STCR:SRST) generates a software reset request.
A software reset requests an operation reset (RST).
9.7.2 Releasing the Reset Request
The software reset request is released after the request is received and the operation reset (RST) generated.
9.7.3 Flag
When software reset request triggers an operation reset (RST), the software reset flag (RSRR:SRST) is set to
"1".
9.7.4 Reset Level
This is a normal level reset which only initializes the program and is called an operation reset (RST).
The following section lists the main items initialized by an operation reset (RST):
9.7.5 Items Initialized by Operation Reset (RST)
•
•
•
•
•
Program operation
CPU and internal bus
Content of registers in peripheral circuits
I/O port settings
Device operation mode (bus mode and external bus width setting)
9.7.6 Reset Cancellation Sequence
After cancellation (removal) of the operation reset (RST) request, the device performs the following operations
in the sequence listed.
1. Removal of operation reset (RST) and change to RUN state
2. Read mode vector from address 000FFFF8H
3. Write mode vector to MODR (mode register)
4. Read reset vector from address 000FFFFCH
5. Write reset vector to the PC (program counter)
6. Start program execution from the address specified by the PC (program counter)
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MB91460N series
9.8 Reset Operation Modes
The following two different modes can be used for an operation reset (RST):
• Normal (asynchronous) reset mode
• Synchronous reset mode
Which mode to use is specified by the synchronous reset operation enable bit (TBCR:SYNCR).
Pin input resets and watchdog resets always use normal reset mode.
For software resets, either normal reset mode or synchronous reset mode can be selected.
9.8.1 Normal (Asynchronous) Reset Mode
Normal reset operation refers to the mode when the device goes to the operation reset (RST) state
immediately after an operation reset (RST) request occurs.
For a normal reset, the device changes to the reset (RST) state immediately after a reset (RST) request is
received regardless of the current state of internal bus access.
In normal reset mode, the result on any bus operation that is in progress at the time the device changes state
is not guaranteed. However, acceptance of the operation reset (RST) request is guaranteed.
Setting the synchronous reset operation enable bit (TBCR:SYNCR) to "0" specifies normal reset mode.
Normal reset mode is the default setting after a settings initialization reset (INIT).
9.8.2 Synchronous Reset Operation
Synchronous reset operation refers to the mode when the device does not go to the operation reset (RST)
state after a operation reset (RST) request until after all bus access has halted.
In synchronous reset mode, the device does not go to the reset (RST) state when a reset (RST) request is
received if internal bus access is still in progress.
When such a reset request is received, a sleep request is issued to the internal bus. The device does not
change to the operation reset (RST) state until all buses have shutdown operation and changed to SLEEP
state.
In synchronous reset mode, the results of bus operations are guaranteed because the device does not change
state until all bus access has halted.
However, if bus access should not halt for some reason, no requests can be received while bus operation
continues. In such a case, the settings initialization reset (INIT) remains available at any time.
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MB91460N series
9.9 MCU Operation Mode
After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data.
The MB91460N series is compliant with single chip mode only. FR60 supports the modes shown below.
Operation mode
Bus mode
Single chip mode
Internal ROM/external bus mode
External ROM/external bus mode
Access mode
32-bit bus width
16-bit bus width
8-bit bus width
9.9.1 Bus Modes and Access Modes
Normal reset operation refers to the mode when the device goes to the operation reset (RST) state
immediately after an operation reset (RST) request occurs.
■ Bus mode
The bus mode controls internal ROM operation and the external access function. The bus mode is specified
by the mode setting pins (MD2, MD1, MD0) and internal ROM enable bit (ROMA of Mode-Vector).
The FR-family CPU has the following three bus modes.
● Single chip mode
In this mode, internal I/O, internal RAM, and internal ROM are available but access to other areas is
disabled. External pins are used either by the peripheral functions or as general-purpose ports. Pins cannot
be used as bus pins.
● Internal ROM, external bus mode
In this mode, internal I/O, internal RAM, and internal ROM are available, and access to areas for which
external access is enabled results in access to the external area. Some external pins function as bus pins.
● External ROM, external bus mode
In this mode, internal I/O and internal RAM are available but access to internal ROM is prohibited. Access
to internal ROM areas and areas for which external access is enabled results in access to the external
area. Some external pins function as bus pins.
■ Access mode
The access mode controls the width of the external data bus and is set by the WTH[1:0] bits in the mode data.
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9.10 Caution
• INITX pin input
Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also, after turning on
the power, ensure a sufficient oscillation stabilization wait time is provided for the oscillation circuit by holding the input
to the pin at the "L" level for the required time.
Note: The INIT reset triggered by INITX pin input initializes the oscillation stabilization wait time to its minimum
value.
• Watchdog reset
When a settings initialization reset (INIT) is triggered by a watchdog reset request, the oscillation stabilization time is
not initialized. Also, in Main-RUN state, no oscillation stabilization wait occurs in response to a watchdog reset request
if the Main clock is not halted.
• Software reset
If "1" (synchronous reset mode) is set to the synchronous reset operation enable bit (TBCR.SYNCR) when an
operation reset (RST) is triggered by a software reset request, the operation reset (RST) does not occur until all bus
access halts. Accordingly, there may be a long delay before the operation reset (RST) occurs, depending on the bus
usage.
• Settings initialization reset (INIT)
A settings initialization reset (INIT) invokes an operation reset (RST) after the oscillation stabilization wait time elapses.
• Reset cause flags (INIT, WDOG, SRST and LINIT)
• Reading the reset cause register clears all the reset cause flags to "0".
• If more than one reset occurs before the reset cause register is read, the flag values are combined
(logical OR) and more than one flag may be set to "1".
• Reset mode
A settings initialization reset (INIT) initializes the reset mode to normal reset mode.
• DMA controller
As the DMA controller halts any transfer when a request is received, it does not cause any delay in changing device
state.
• Pin states during a reset
See "3.8 Pin State Table (Page No.56)" for details about pin states during a reset.
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10.1
MB91460N series
Chapter 10 Standby
10.1 Overview
Two standby modes (low power consumption modes) are available.
•
SLEEP state: Stops the program
•
STOP state: Shuts down the device
Note: It is possible to keep the Real Time Clock active in STOP state (see chapter RTC).
10.2 Features
■ SLEEP state
• Device state in SLEEP state:
• Halts the program.
• CPU program execution only stops. Peripheral functions can continue to operate.
• The internal memory and internal bus halt, until they are requested by DMA.
• Transition to SLEEP state:
• SLEEP state is invoked by the program.
• Recovery from SLEEP state:
• Generation of a valid interrupt request ends SLEEP state (returns to normal operation)
• An INITX pin input invokes an initialization reset (INIT) followed by an operation reset (RST).
■ STOP state
• Device state in STOP state:
• The overall device halts.
• Internal circuits halt (with some exceptions)
• Internal clock signals halt (with some exceptions)
• Whether or not the oscillation circuit halts can be controlled by a setting (programmable).
• All external pins can be set to high impedance (programmable, excludes some pins)
• Transition to STOP state:
• STOP state is invoked by the program.
• Recovery from STOP state:
• The following three interrupt requests change the device to the oscillation stabilization wait state.
•External level-detect or edge-detect interrupt
•Interrupt generated by oscillation stabilization wait timer for the Main clock when oscillation not halted.
•Real time clock interrupt when clk source to RTC is active.
• Input to the INITX pin invokes an initialization reset (INIT) and then an operation reset (RST).
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10.3 Configuration
Figure 10.3-1 Configuration Diagram of Standby operation
State transition control circuit
(for standby modes)
SYNCS
TB CR: bit0
Setting prohibited
Synchronous standby
0
1
SLEEP
0
1
OSCD1
0
1
STCR: bit6
Do not change to sleep mode.
Change to sleep mode.
Sleep signal
STOP
STCR: bit7
Stop signal
0
1
Do not change to stop mode.
STCR: bit0
Change to stop mode.
Do not halt main clock oscillation during stop mode.
Clock control
Halt main clock oscillation during stop mode.
HIZ
STCR: bit5
0
1
Set pins to high impedance during stop mode.
Maintain same states during stop mode.
SRST
0
1
State
transition
control
circuit
Internal interrupts,
external interrupts
STCR: bit4
Pin control
Initialize settings (INIT)
Generate software reset.
Do not generate software reset.
INITX
Initialize operation (RST)
RSRR: bit7
INIT
0
1
No INIT pin input
SRST
0
1
Counter cleared,
oscillation
stabilization
wait
INIT pin input occurred (INIT)
RSRR: bit3
No software reset (RST)
Software reset (RST) occurred
Oscillation stabilization
wait finished
Time-base counter
(oscillation stabilization wait)
Watchdog timer
WDOG
RSRR: bit5
0
1
No watchdog timeout
Watchdog timeout (INIT) occurred
Figure 10.3-2 Register List
Standby Control
Address
000480H
7
INIT
6
HSTB
5
WDOG
4
ERST
3
SRST
2
LINIT
1
WT1
000481H
STOP
SLEEP
HIZ
SRST
OS1
OS0
---
OSCD1 STCR
(Standby control)
000482H
TBIF
TBIE
TBC2
TBC1
TBC0
---
SYNCR
SYNCS TBCR
(Time-base counter control)
108
Bit
0
WT0
RSRR
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10.4
MB91460N series
10.4 Registers
10.4.1 STCR: Standby Control Register
Used to control transition to the STOP and SLEEP standby states, and to specify the pin states and whether to
halt the oscillation during STOP state.
Note: See "Chapter 9 Reset (Page No.93)" also.
• STCR: Address 000481H (Access: Byte)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
-
0
OSCD1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
1
1
0
0
X
1
X
X
X
X
R/W
R/W
R/W
R1, W
R/W
R/W
R/W
R/W
bit
Initial value
(INITX pin input)
Initial value
(Watchdog reset)
Initial value after RST
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7: STOP state
STOP
0
1
Operation
Does not change to STOP state.
Changes to STOP state.
• Goes to "0" when a reset (INITX pin input or software reset) occurs or on recovery from STOP state.
• When going directly from Main PLL operation to STOP state, the PLL operation should be disabled
before the STOP state is invoked. (See "10.8 Caution (Page No.116)".)
• Bit6: SLEEP state
SLEEP
0
1
Operation
Device does not change to SLEEP state.
Device changes to SLEEP state.
• If this bit and the STOP state bit (STOP) bit are set to "1" at the same time, the device goes to STOP
state.
• Goes to "0" when a reset (INITX pin input or software reset) occurs or on recovery from SLEEP state.
• Bit5: High impedance mode
HIZ
0
1
Operation
Maintain same pin states when changing to STOP state.
Set pin outputs to high impedance (Hi-Z) during STOP state.
• The default setting is high impedance.
• Bit4: Software reset (SRST)
• Setting this bit to "0" invokes a software reset.
• Bit3, bit2: Oscillation stabilization time selection (OS[1:0])
• Setting these bits in the range "00"-"11" sets the oscillation stabilization time to use after recovering from
STOP state.
An INITX pin input reset or watchdog reset initialize this setting to its initial value.
(See "Chapter 16 Timebase Counter (Page No.171)".)
• Bit1: Reserved bit
• Writing does not affect the operation.
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• Bit0: Main clock oscillation halt
OSCD1
0
1
Operation of Main clock during STOP state
Continue oscillation
Halt oscillation
10.4.2 TBCR: Timebase timer control register
This register controls the timebase timer interrupts and the options for resets and standby operation.
Note: See also "Chapter 17 Timebase Timer (Page No.185)".
• TBCR: Address 000482H (Access: Byte)
7
TBIF
6
TBIE
5
TBC2
4
TBC1
3
TBC0
2
---
1
SYNCR
0
SYNCS
0
0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R1,W
R/W
RX/WX
R/W
R/W
bit
Initial value
(INITX pin, watchdog)
Initial value after RST
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7: Interrupt flag for timebase timer
• This flag goes to "1" when a timebase timer interrupt occurs
• Bit6: Interrupt request enable for the timebase timer
• Writing "1" to this bit enables timebase timer interrupt requests.
• Bit5 to bit3: Interval time selection for timebase timer
• Writing a value in the range "000"-"111" to these bits selects the interval time for the timebase timer.
(φ × 211, φ × 212, φ × 213, φ × 222, φ × 223, φ × 224, φ × 225, φ × 226)
• Bit2: Reserved Writing does not affect the operation. The read value is undefined.
• Bit1: Enable synchronous reset operation
• Selects a normal reset "0" or a synchronous reset "1".
• Bit0: Enable synchronous standby operation
SYNCS
0
1
Operation
Asynchronous reset operation (Not permitted on this model).
Enable synchronous standby operation (always set this before changing to a standby mode).
During synchronous standby operation, writing to the STOP bit alone does not cause mode transition. The
transition only occurs when data is read from the STCR register.
• Synchronous standby operation
Data is written to the standby control register via multiple buses.
Therefore, after a write instruction is issued to the standby control register, succeeding instructions may be
executed while the write instruction is still going through the multiple buses.
To prevent this, use synchronous standby mode.
In synchronous standby mode, the device goes to standby state by reading from the standby control
register, after writing to the same register.
Read operation is also performed via multiple buses. In the case of a read instruction, however, succeeding
instructions are not executed until the data returns to the CPU.
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MB91460N series
10.5 Operation
10.5.1 SLEEP state
■ Entering SLEEP state
Writing "1" to the SLEEP state bit (STCR:SLEEP) changes to SLEEP state. The device remains in this mode
until an event occurs to wakeup the device from SLEEP state.
(See "10.8 Caution (Page No.116)".)
■ Device state in SLEEP state
• CPU program execution stops. (Peripheral functions continue to operate.)
• The internal memory and internal bus halt, until they are requested by DMA.
• Circuits that halt during SLEEP state
• Bit search module
• All internal memory (inclusive I-cache)
• Internal/external bus
• Circuits that do not halt during SLEEP state
• Oscillation circuit, Main PLL (if enabled)
• Clock generation control circuit
• Interrupt controller
• External interrupts
• DMA
• Peripherals
■ Recovery and other items
• Generation of an interrupt request that is currently enabled changes the device back to RUN state. (Restores
normal operation.)
• An INITX pin input invokes an initialization reset (INIT) followed by an operation reset (RST).
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10.5.2 STOP state
■ Entering STOP state
Writing "1" to the STOP state bit (STCR:STOP) changes to STOP state.
The device remains in this mode until an event occurs to wakeup the device from STOP state.
(See "10.8 Caution (Page No.116)".)
■ Device state in STOP state
• The overall device halts (internal circuits halt and the internal clock signals halt).
• Circuits that halt during STOP state
All internal circuits except those listed below.
• Circuits that do not halt during STOP state
• Oscillation circuits that are not specified to be halted
•
Oscillation circuit for Main clock (if not disabled)
•
Main PLL circuit if oscillation circuit for Main clock is enabled and PLL circuit is enabled and main
regulator is kept enabled. But the PLL circuit must be disabled before going to STOP state.
• Peripheral functions that are driven directly by the oscillation and which have not been specified to be
halted.
•
Real Time Clock (if not disabled) is used to enable RTC clock source.
• Pin states (High impedance or maintain previous state)
• When pin outputs are set to go to high impedance during STOP state
•
High impedance output: Pins that are set as general purpose ports and pins that have been selected
for use by peripheral functions.
• When pin outputs are set to maintain their previous states during STOP state
•
Maintain previous state: Pins that are set as general purpose ports and pins that have been selected
for use by peripheral functions.
• When set as external interrupts
•
Input available state:
Pins set as external interrupt inputs using level detection or edge detection.
(Whether the pin output during STOP state has been set to either high impedance or maintain
previous state.)
■ Recovery and other items
• Any of the following interrupt requests cause the device to go to the oscillation stabilization wait RUN state
and then to change back to RUN state after the oscillation stabilization time elapses (return to normal
operation).
• External interrupts set to level detection or edge detection and that do not require a specific clock.
• Real Time Clock interrupt (if operating)
• An INITX pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by an
operation reset (RST) after the oscillation stabilization time.
• After stopping the oscillation of the main clock when returning by the INITX input, "L" must be input to INITX
until the oscillation stabilization wait time is elapsed.
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10.6
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10.6 Settings
Table 10.6-1 Settings Required to Change to SLEEP state
Setting
Setting
procedure*
Setting register
Interrupt settings
(See the chapter for each peripheral function.)
—
Synchronous standby settings
Timebase timer control register (TBCR)
See 10.7.1
Change to SLEEP state
Standby control register (STCR)
See 10.7.1
Operational restrictions
(See "10.8 Caution (Page No.116)".)
—
*:For the setting procedure, refer to the section indicated by the number.
Table 10.6-2 Settings Required to Change to STOP state
Setting
Setting
procedure*
Setting register
Selects the oscillation stabilization
wait time
(See "Chapter 16 Timebase Counter (Page No.171)".)
—
Interrupt settings
(See the chapter for each peripheral function.)
—
Synchronous standby settings
Timebase timer control register (TBCR)
See 10.7.2
Change to STOP state
Standby control register (STCR)
See 10.7.2
Operational restrictions
(See "10.8 Caution (Page No.116)".)
—
*: For the setting procedure, refer to the section indicated by the number.
10.7 Q&A
10.7.1 How to change to SLEEP state
Before a change to SLEEP state, first the synchronous standby operation enable bit (TBCR:SYNCS) must be
set.
Operation
To enable synchronous standby operation
Synchronous standby operation enable bit (SYNCS)
Set to "1".
Note: Setting (SYSNCS=0) is prohibited.
Set using the SLEEP state bit (STCR: SLEEP).
Operation
Change not to SLEEP state
Change to SLEEP state
SLEEP state bit (SLEEP)
Set to "0".
Set to "1".
Note: Some restrictions apply when changing to SLEEP state. See "10.8 Caution (Page No.116)" for details.
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10.7.2 How to change to STOP state
• When operating on the Main PLL clock, the operating clock must be set to the Main clock divided by two.
See "12.7.3 How to select the operating clock source (Page No.139)" for details about changing the
operating clock.
• Before a change to STOP state, at first the synchronous standby operation enable bit (TBCR:SYNCS) must
be set. See section 10.7.1.
• Set using the STOP state bit (STCR:STOP).
Operation
Change not to STOP state
Change to STOP state
STOP state bit (STOP)
Set to "0".
Set to "1".
Note: Some restrictions apply when changing to STOP state. See "10.8 Caution (Page No.116)" for details.
10.7.3 How to set pins to high impedance (Hi-Z) during STOP state
Set using the high impedance mode bit (STCR:HIZ).
Operation
Pins are not set to high impedance during STOP state
Pins are set to high impedance during STOP state
High impedance mode bit (HIZ)
Set to "0".
Set to "1".
Note: Some ports do not go to high impedance in some circumstances. (See "10.5.2
No.112)".)
STOP state (Page
10.7.4 How to halt the Main clock oscillation during STOP state
Use the Main clock oscillation stop bit (STCR:OSCD1).
Operation
Main clock oscillation is not stopped during STOP state
Main clock oscillation is stopped during STOP state
Main clock oscillation stop bit (OSCD1)
Set to "0".
Set to "1".
10.7.5 How to recover from SLEEP state
Two methods are available to recover from SLEEP state.
• Generation of a valid interrupt request changes to RUN state (restores normal operation).
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM), and interrupt
control register (ICR).
• An INITX pin input invokes an initialization reset (INIT) followed by an operation reset (RST).
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10.7.6 How to recover from STOP state
The following events end STOP state:
• The following three interrupts change the device to the oscillation stabilization wait state.
• External level-detect interrupt or edge-detect interrupt.
• Oscillation stabilization wait timer for the Main clock when oscillation not halted.
• Real time clock when RTD clock source (Main Clock, Sub Clock or RC Oscillation) is active.
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM), and interrupt
control register (ICR).
• Input to the INITX pin invokes an initialization reset (INIT) followed by an oscillation stabilization delay and
then an operation reset (RST).
In the case of an INITX pin input, an oscillation stabilization wait is required, depending on the width of the
INITX pin input.
See also "Chapter 12 Clock Control (Page No.129)" and "Chapter 16 Timebase Counter (Page No.171)".
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10.8 Caution
• Points to note when changing to SLEEP state
When changing to SLEEP state, set the synchronous standby operation enable bit (TBCR:SYNCS=1).
Also, in order to change to SLEEP state with synchronous standby operation enabled, the STCR register
must be read after writing to the SLEEP bit. Always use the following sequence.
(LDI
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
#value_of_sleep, R0) ; value_of_sleep contains the write data for STCR.
#_STCR, R12)
; _STCR is the address of STCR (481H).
R0, @R12 ; Write to standby control register (STCR).
@R12, R0 ; STCR read required for synchronous standby.
@R12, R0 ; Second dummy read to STCR.
; NOP x 5 required (for flushing the pipeline)
• Points to note when changing to STOP state
When changing to SLEEP state, set the synchronous standby operation enable bit (TBCR:SYNCS=1).
Also, in order to change to STOP state with synchronous standby operation enabled, the STCR register
must be read after writing to the STOP bit. Always use the following sequence.
(LDI
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
#value_of_stop, R0)
#_STCR, R12)
R0, @R12
@R12, R0
@R12, R0
; value_of_stop contains the write data for STCR.
; _STCR is the address of STCR (481H).
; Write to standby control register (STCR).
; STCR read required for synchronous standby.
; Second dummy read to STCR.
; NOP x 5 required (for flushing the pipeline)
• When the Main PLL is selected as the operation clock source
When the Main PLL is selected as the operation clock source, change the operation clock source selection
to Main clock divided by two before changing to STOP state.
See "Chapter 12 Clock Control (Page No.129)" for details.
The restrictions that apply to the clock divide ratio setting are the same as for normal operation. The PLL
oscillation has also not to be halted.
• If interrupts are disabled in the interrupt control register (ICR=00011111B), the device will not recover from STOP
or SLEEP state when an interrupt occurs.
• Pin high impedance control in STOP state
Setting the high impedance bit (STCR:HIZ) to "1" sets pin outputs to high impedance during STOP state. If
the high impedance bit (STCR:HIZ) is set to "0", pins retain the states they have prior to entering STOP
state.
See Chapter 3.8 "Pin State Table" on P. 56 for details such as the operation of specific pins
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Chapter 11 Memory Controller
11.1 Overview
This module controls, FLASH and General Purpose RAM (also referenced as ID-RAM).
Code fetches from the FLASH memory and general-purpose RAM is performed via I-bus.
Data access from the FLASH memory and general-purpose RAM is performed via F-bus.
The FLASH memory has an instruction cache designed for the FLASH memory.
The FLASH memory can be accessed by using the prefetch function, which reduces a code fetch delay at
code linear access.
11.2 FLASH Interface
• Timing control
The wait timing for FLASH access can be controlled.
The control signal for FLASH access can be controlled independently.
The above features enable the optimal FLASH memory access according to the clock frequency of the CPU.
For details, see "11.5 FLASH Access Timing Setting".
• Access mode
Read mode can be changed to the 16-bit or 32-bit mode.
Write mode can be changed to the 16-bit or 32-bit mode.
The 16-bit read mode cannot be used to execute a program.
It is prohibited to change these modes when an instruction or data is being read from the FLASH memory.
Always expand a program in I-RAM beforehand.
Note:
The FLASH memory requires 100ns as the transition time after access mode is changed.
When the mode has been changed, wait for 100ns before reading data.
• Prefetch
The prefetch function reduces a fetch delay at linear code execution.
Whether a prefetch is successful or not is determined by whether the prefetch address matches with the
address of instruction access from the CPU or not.
Even if there is a time gap between instruction fetches, the prefetched instruction is stored in the prefetch
buffer.
Since the prefetch buffer uses cache memory, it cannot be used if the cache is disabled.
If a prefetch is unsuccessful, the prefetch operation is cancelled immediately.
There is no distinction between the instruction fetch and data fetch.
Even during linear code execution, it is still cancelled if data access occurs to a different address in the middle
of the operation.
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11.3 General-purpose RAM
This 2KB RAM can be used for both codes and data.
Code access is enabled in 0 wait cycle. Data access is performed in 1 wait cycle.
11.4 instruction cache while writing to the FLASH memory
This 4KB instruction cache is designed for the FLASH memory.
Note:
To maintain data consistency, disable the instruction cache while writing or erasing data from the FLASH
memory. Once the data has been written to or erased from the FLASH memory, flush the cache.
11.4.1 Algorithm
This is a direct map cache based on word entry.
The instruction cache for FLASH memory is based on a standard cache algorithm that stores code fetches
consecutively from the FLASH memory.
Whether a cache hit is occurring or not is determined at the same time as FLASH memory access. Therefore,
even if a cache miss occurs, no penalty applies, unlike when the cache is disabled.
11.4.2 Prefetch miss cache
The cache algorithm can be changed to an algorithm that performs cache operation only when a prefetch miss
has occurred.
If FLASH memory access is completed within 2 cycles of the CPU clock, the CPU only uses the prefetch function
upon linear code execution, which enables code fetches without waiting for the FLASH memory.
In this case, the cache function does not affect the operation.
It should be noted that the performance drops if a prefetch miss occurs due to branching or other reasons.
Therefore, such performance drop due to branching or other reasons can be improved independently by caching
only the code immediately after the prefetch miss.
This algorithm allows the cache memory with a limited capacity to be used efficiently.
Whether FLASH memory access can be completed within 2 cycles depends on the CPU clock and FMWT
register settings. For details, see the section regarding the FMWT register.
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11.4.3 Specifying Non-cacheable Area
An area to be excluded from cache operation can be set by the FCHA0/1 register. The initial value is no area
excluded from cache operation.
There are two ways to specify this area: the address mask method and the address range method.
• Address mask method
This method can be used by setting the FCHCR:REN bit to "0".
In this case, the area at the address specified by the FCHA0 register becomes excluded from cache operation.
The area can be specified this way, because address comparison is performed by masking the bits specified
by FCHA1.
Example) FCHA0
= 000FA300H
FCHA1
= 0000FFFFH
In the above case, the non-cacheable area is 000F0000H to 000FFFFFH.
As the lower 16 bits are masked, only the upper 16 bits are compared and judged.
• Address range method
This method can be used by setting the FCHCR:REN bit to "1".
The non-cacheable area is an area from the address specified by FCHA0 to the address specified by FCHA1.
Example) FCHA0
= 000FA300H
FCHA1
= 000FF7FFH
In the above case, the non-cacheable area is 000FA300H to 000FF7FFH.
11.4.4 Cache Flash
The entry flush of instruction cache is started by writing "1" to the FCHCR:FLUSH bit.
Cache operation is disabled during flushing.
Execution of initialization requires one cycle of the CPU clock per entry.
Once all entries are flushed, the FCHCR:FLUSH bit is cleared to "0". This indicates that the cache flush is
complete.
As the initial value of the FCHCR:FLUSH bit is "1", cache entries are always flushed when the first cache is
enabled after a reset.
For cache flush, the cache capacity must be set correctly. Therefore, set FCHCR: SIZE1/0 correctly, before
enabling the cache.
Note:
Do not flush the cache by writing "1" to FCHCR:FLUSH at the same time as rewriting FCHCR:SIZE1/0.
Always set FCHCR:SIZE1/0 before activation.
11.4.5 Global Lock
Entry write/update operation can be disabled by locking cached entries.
This locking applies to all cached entries.
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11.5 FLASH Access Timing Setting
11.5.1 FLASH Write Access Cycle
The following figure shows an example of FLASH access cycles.
tATD, tALEH, tEQ, and tWTC can be set separately by register setting.
flash_start
FMA
valid
ATDIN
EQIN
flash_wait
DO
valid
tATD
tALEH
tEQ
tWTC
tRC
Examples of setting values of the above waveforms are shown below.
Length
Setup
tATD
1.5 CPU cycles
FMWT:ATD = 2
tALEH
1.5 CPU cycles
FMWT2:ALEH = 2
tEQ
3 CPU cycles
FMWT:EQ = 2
tWTC
6 CPU cycles
FMWT:WTC = 2
tRC
7 CPU cycles
FMWT:WTC + 1 = 3
For read/write timing settings, see the appropriate datasheet for each model.
11.5.2 Specifications of Read Control Signal
The real time of each control signal is set by the FMWT register and calculated in the following way.
120
tATD
:
(FMWT:ATD + 1) × 0.5
[CPU cycle]
tALEH
:
(FMWT2:ALEH + 1) × 0.5
[CPU cycle]
tEQ
:
(FMWT:EQ + 1) × 0.5
[CPU cycle]
tWTC
:
FMWT:WTC
[CPU cycle]
tRC
:
FMWT:WTC + 1
[CPU cycle]
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MB91460N series
11.6 Registers
11.6.1 List and Notes
11.6.1.1 List
Table 11.6-1 List of Registers
Address
007000H
Register
+0
+1
FMCS [R/W]
01101000
FMCR [R/W]
----0000
007004H
Block
+2
+3
Flash memory cache
control register
FCHCR
[R/W]
------00 1000011
FMWT[R/W]
11111111 01011101
FMWT2[R/W]
-101----
FMPS[R/W]
-----000
007008H
FMAC [R]
-------- ---00000 00000000 00000000
00700CH
FCHA0
-------- -0000000 00000000 00000000
007010H
FCHA1
-------- -0000000 00000000 00000000
I-cache non-capable
area setting register
11.6.1.2 Notes
Read and write access to all registers is byte, halfword and word.
11.6.2 FLASH Memory Control and Status Register (FMCS)
FMCS
bit 31
Address: 007000H
Read/Write →
Initial value →
30
29
Reserved
Reserved Reserved
R/W
0
R/W
1
R/W
1
28
27
26
25
24
RDYEG
RDY
Reserved
RW16
Reserved
R
0
R
1
R/W
0
R/W
0
R/W
0
• BIT[31 to 29]:Reserved
Always write "011" to these bits. "011" is always read.
• BIT[28]: RDYEG - RDY status hold/end register
RDYEG
Description
0
Auto Algorithm not completed (default)
1
Auto Algorithm has been completed.
The initial value of this bit is "0".
The bit set to "1" after 0->1 transition of FMCS:RDY.
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Reading this bit clears it to "0".
This bit indicates that the FLASH memory is ready or was ready (the Auto Algorithm has been completed).
It must be noted that it is set when FMCS:RDY changes from "0" to "1".
This bit does not return to "0", even when the Auto Algorithm is reactivated before it is read and cleared to "0".
• BIT[27]: RDY - FLASH RDY status of Auto Algorithm
If Auto Algorithm is started such as writing to/erasing from FLASH, FLASH becomes the busy state. Use this bit to
read the ready/busy state of FLASH. If RDY returns to "1", the Auto Algorithm has been completed.
The RDY bit is read-only status information.
• BIT[26]: Reserved
Always write "0" to this bit. "0" is always read.
• BIT[25]: RW16 - 16 bit access enable bit
RW16
Description
0
32 bit access is enabled (default)
1
16 bit access is enabled
The initial value of this bit is "0".
Note: In MB91F463N, if writing to the FLASH memory, set the RW16 bit to "1".
• BIT[24] : Reserved
Always write "0" to this bit. The readout value is "0".
11.6.3 FLASH Memory Control Register (FMCR)
FMCR
Address: 007001H
Read/Write →
Initial value →
bit 23
22
21
20
19
−
−
−
−
LOCK
R/W
0
−
−
−
−
X
X
X
X
18
17
16
Reserved
PF2I
RD64
R/W
0
R/W
0
R/W
0
• BIT[23] to BIT[20]: Reserved
The readout value is undefined. Writing has no effect on operation.
• BIT[19]: LOCK - ALEH auto-update lock
LOCK
Description
0
ALEH setting auto update is enabled (default)
1
ALEH setting auto update is disabled
The initial value of this bit is "0".
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If setting this bit to "0", write to the FMWT:ATD bit to automatically update the FMWT2:ALEH bit to the same setting.
If setting this bit to "1", auto update is automatically disabled.
• BIT[18]: Reserved
Always write "0" to this bit. "0" is always read.
• BIT[17]: PF2I - 32-bit prefetch setting bit
PF2I
Description
0
Prefetch 64 bit (default)
1
Prefetch 32 bit only
The initial value of this bit is "0".
In the 64-bit read mode, if setting this bit to "1", prefetch is performed in 32 bits.
In the MB91F463N, this setting cannot used.
• BIT[16]: RD64 - 64-bit read mode enable bit
RD64
Description
0
64 bit read mode is disabled (default)
1
64 bit read mode is enabled
The initial value of this bit is "0".
If setting this bit to "1", reading from the FLASH memory is performed in 64 bits.
In the MB91F463N, this setting cannot used.
11.6.4 FLASH Cache Control Register (FCHCR)
FCHCR
Address: 007002H
Read/Write →
Initial value →
Address: 007003H
Read/Write →
Initial value →
bit 15
14
13
12
11
10
9
8
−
−
−
−
−
−
REN
Reserved
X
−
X
X
X
X
−
−
X
R/W
0
R/W
0
bit 7
6
5
4
3
2
1
0
FLSH
R(RM0)/W
1
−
−
−
Reserved
PFEN PFMC
LOCK
ENAB
SIZE1 SIZE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
• BIT[15] to BIT[10]:Reserved
The undefined value is read. Writing is ignored.
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• BIT[9]: REN - Non-cacheable area Range Enable
REN
Description
0
Non-cacheable area is specified using the address mask. (default)
1
Non-cacheable area is specified using the address range.
The initial value of this bit is "0".
• BIT[8]:Reserved
Always write "0" to this bit. "0" is always read.
• BIT[7]: FLUSH - Flush instruction cache entries
FLUSH
Description
0
Flushing the instruction cache entries has been completed
1
Actually flushing the instruction cache entries (default)
The initial value of this bit is "1".
Do not activate the flush simultaneously with rewriting FCHCR:SIZE1/0.
Be sure to flush after setting FCHCR:SIZE1/0.
After completing flush, this bit is cleared to "0".
Writing "0" is ignored.
"0" is read when a read-modify-write instruction is used.
• BIT[6]:Reserved
Always write "0" to this bit. "0" is always read.
• BIT[5]: PFEN - PreFetch ENable
PFEN
Description
0
Prefetch of instructions is disabled (default)
1
Prefetch of instructions is enabled
The initial value of this bit is "0".
• BIT[4]: PFMC - Prefetch Miss Cache enable
FLUSH
Description
0
Prefetch miss cache is disabled (default)
1
Prefetch miss cache is enabled
The initial value of this bit is "0".
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• BIT[3]: LOCK - Global lock of cache entries
LOCK
Description
0
Write of cache entries is enabled (default)
1
Writing of cache entries is disabled
The initial value of this bit is "0".
• BIT[2]: ENAB - Instruction cache enable
ENAB
Description
0
The instruction cache is disabled (default)
1
Enable the instruction cache
The initial value of this bit is "0".
• BIT[1:0]: SIZE1/0 - Cache size configuration
SIZE1/0
Description
00
0kByte - Cache disabled
01
4kByte (1024 entries)
10
8kByte (2048 entries)
11
16kByte (4096 entries) (default)
The initial value of this bit is "11".
Be sure to set this bit before enabling cache.
Do not activate the cache flush simultaneously with rewriting the bit.
Because the instruction cache is 4KB in MB91F463N, set the bit to "01".
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11.6.5 FLASH Memory Wait Timing Register (FMWT)
FMWT
bit 31
Address: 007004H
Read/Write →
Initial value →
R/W
1
bit 23
Address: 007005H
Reserved
Read/Write →
Initial value →
FMWT2
30
Reserved Reserved
R/W
0
bit 15
Address: 007006H
Read/Write →
Initial value →
FMPS
Address: 007007H
Read/Write →
Initial value →
−
−
R/W
1
29
28
27
26
WEXH1 WEXH0 WTC3 WTC2
R/W
1
R/W
1
R/W
1
R/W
1
25
24
WTC1
WTC0
R/W
1
R/W
1
22
21
20
19
18
17
16
ATD2
ATD1
ATD0
EQ3
EQ2
EQ1
EQ0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
14
13
12
11
10
9
8
−
−
−
−
ALEH2 ALEH1 ALEH0
R/W
1
R/W
0
R/W
1
−
−
−
−
X
X
X
X
bit 7
6
5
4
3
2
−
−
−
−
−
X
−
−
−
−
−
X
X
X
X
X
Reserved
R/W
0
1
0
Reserved Reserved
R/W
0
R/W
0
• BIT[31:30]:Reserved
Always write "11" to these bits. "11" is always read.
• BIT[29:28]: WEXH[1:0] - WEX Hi width setting bit
The initial value of these bits is 3.
Since the Hi width of WEX is the register value + 2, the initial value is 5 cycles.
• BIT[27:24]: WTC[3:0] - Wait cycles for FLASH memory access
The initial value of these bits is 15.
Total access cycle of FLASH is WTC+1.
• BIT[23]:Reserved
Always write "0" to this bit. "0" is always read.
• BIT[22:20]: ATD[2:0] - ATDIN cycle of FLASH memory access control signal
The initial value of these bits is 5 in MB91460N series. It is 7 in MB91V460A.
• BIT[19:16]: EQ[3:0] - EQIN cycle of FLASH memory access control signal
The initial value of these bits is 13 in MB91460N series. It is 15 in MB91V460A.
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• BIT[15]:Reserved
The undefined value is read. Writing is ignored.
• BIT[14:12]: ALEH[2:0] - ALEH cycle of FLASH memory access control signal
The initial value of these bits is 5 in MB91460N series. It cannot be used in MB91V460A.
• BIT[11:3]:Reserved
The undefined value is read. Writing is ignored.
• BIT[2:0]:Reserved
Always write "000" to these bits. "000" is always read.
Note:
ATD and EQ bits
In MB91V460A, setting these bits has no effect on operation. Set and use these bits in accordance with the
operating frequency of MB91460N series.
11.6.6 FLASH Memory Address Check Register (FMAC)
FMAC
bit 31
0
FMAC
Address: 007008H
Read/Write →
Initial value →
R
-------- -0000000 00000000 00000000
This register is used for testing purposes. It always captures the address at which the FLASH access cycle
has started.
11.6.7 Non-cacheable Area Setting Register (FCHA1/0)
FCHA0
bit 31
FCHA0
Address: 00700CH
Read/Write →
Initial value →
FCHA1
R
-------- -0000000 00000000 00000000
bit 31
Address: 007010H
Read/Write →
Initial value →
CM44-10149-1E
0
0
FCHA1
R
-------- -0000000 00000000 00000000
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Chapter 11 Memory Controller
11.6
MB91460N series
This register sets an area to be excluded from FLASH cache operation.
The initial value has no excluded area.
Note:
In MB91V460A, setting the ATD and EQ bits does not affect the operation. However, set them according to the
operating frequency of the MB91460N series for use.
11.6.8 Setting of Flash memory controller
• Setting of flash access timing
For executing programs with a Flash memory, follow the settings below according to the frequency of CPU clock
(CLKB). This setting is the most suitable for a high-speed access to the Flash memory.
Table 11.6-2 At Flash memory read operating
CPU clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
To 24 MHz
0
0
0
0
1
To 48 MHz
0
0
1
0
2
To 96 MHz
1
1
3
0
4
Table 11.6-3 At Flash memory write operating
128
CPU clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
To 32 MHz
1
0
1
0
4
To 48 MHz
1
0
3
0
5
To 64 MHz
1
1
3
0
6
To 96 MHz
1
1
3
0
7
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CM44-10149-1E
Chapter 12 Clock Control
12.1
MB91460N series
Chapter 12 Clock Control
12.1 Overview
The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator.
The clock control circuit supports broad clock speeds from high-speed clock (80MHz at the maximum) to low
speed clock (2MHz).
Figure 12.1-1 Block Diagram of Clock Distribution
Main clock
source
oscillation
Divide-by-2
Selector
Divider
CPU clock (CLKB)
Divider
Peripheral clock (CLKP)
PLL
Base clock
Selector
Divider
CAN clock
Explanation to PLL Interface: 1/G means 1/(PLLDIVG + 1)
1/M means 1/(PLLDIVM + 1)
1/N means 1/(PLLDIVN + 1)
12.2 Features
■ Source oscillation
• Main clock (CLKMAIN): 4MHz (typical value)
Input from the X0/X1 pins and used as the high speed clock
■ Base clock (φ): Selectable from 2 different clocks
• Main PLL (programmable) : CLKMAIN × (MxN)/M (either modulated or unmodulated)
• CLKMAIN divided by 2
■ Operating clocks: Selectable from 16 different speeds
• CPU clock (CLKB): φ/1, /2, /3, /4, /5, /6, /7, /8, ..., /16
The clock used by the CPU, internal memory, and internal buses. The circuits that use this clock are as
follows.
•
CPU, internal RAM, internal ROM, bit search module,
•
I-bus, D-bus, F-bus, X-bus
• Peripheral clock (CLKP): φ/1, /2, /3, /4, /5, /6, /7, /8, ..., /16
This clock is used by the peripheral functions and peripheral bus. The circuits that use this clock are as
follows.
•
Peripheral bus
•
Clock controller (bus interface unit only)
•
Interrupt controller
•
I/O ports
•
External interrupt inputs, UART, 16-bit timer, and similar peripheral functions
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Chapter 12 Clock Control
12.3
MB91460N series
12.3 Configuration
Figure 12.3-1 Configuration Diagram of the clock controller
PLL1EN
CLKR: bit2
0
1
0
1
STCR: bit0
Continue oscillation
in stop mode
Halt oscillation
in stop mode
X0
Halt PLL
Enable (start) PLL
X1
Set PLL autogear
OSCDS1
OSCCR: bit0
0
Main clock continues to
run in subclock mode
1
Main clock halts in
subclock mode
Main clock
source
(FCLK-MAIN)
PLLDIVM: bit3 to bit0
PLLDIVN: bit5 to bit0
PLLDIVG: bit3 to bit0
PLLMULG: bit7 to bit0
CPU Clock
(FCLKB)
Divider
PLL
Selector
OSCD1
B3 to B0 DIVR0: bit7 to bit4
0000
No division
0001
Divide by 2
0010
Divide by 3
Divide by 4
0011
Divide by 5
0100
Divide by 6
0101
Divide by 7
0110
Divide by 8
0111
1000 to 1110 Divide by 9 to 15
1111
Divide by 16
Set PLL multiplier
Divide-by-2
Peripheral clock
(FCLKP)
Divider
Base
clock
(φ)
Base clock (φ)
OSCD1
0
1
CLKS1,
CLKS0
STCR: bit0
Continue oscillation
in stop mode
Halt oscillation
in stop mode
Permitted
change
CLKR: bit1, bit0
Main clock divided by 2
(main clock mode)
Main clock divided by 2
(main clock mode)
Main PLL
(main clock mode)
00
01
10
11
00=>01, 10
01=>00
10=>00
Setting
disabled
Setting disabled
P3 to P0 DIVR1: bit3 to bit0
0000
No division
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100
Divide by 5
0101
Divide by 6
0110
Divide by 7
0111
Divide by 8
1000 to 1110 Divide by 9 to 15
1111
Divide by 16
Figure 12.3-2 Register List
Clock Control
Address Bit
000486H
7
B3
6
B2
5
B1
4
B0
3
P3
2
P2
1
P1
0
P0
DIVR0
(Operating clock division setting register 0)
000487H
---
---
---
---
---
---
---
---
DIVR1
(Operating clock division setting register 1)
000484H
---
---
---
---
---
PLL1EN
CLKS1
CLKS0
CLKR
(Clock source control register)
00048AH
---
---
---
---
---
---
---
HIZ
SRST
OS1
OS0
---
000481H
130
STOP SLEEP
OSCDS1 OSCCR (Oscillation control register)
OSCD1 STCR
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(Standby control register)
CM44-10149-1E
Chapter 12 Clock Control
12.4
MB91460N series
12.4 Registers
12.4.1 CLKR: Clock Source Control Register
Selects the clock source for the base clock used to run the MCU and controls the PLL.
• CLKR: Address 000484H (Access: Byte)
7
-
6
-
5
-
4
-
3
-
2
PLL1EN
1
CLKS1
0
CLKS0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
R/W0
R/W0
R/W0
R/W0
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bit.
• Always write "0" to this bit. The read value is the value written.
• Bit3: Reserved bit.
• Always write "0" to this bit.
• Bit2: Enable Main PLL operation
PLL1EN
0
1
Function
Halt Main PLL (Initial value)
Enable Main PLL operation
• Modifying the Main PLL operation enable bit (PLL1EN) while the Main PLL is selected as the clock
source (CLKS[1:0]=10) is prohibited.
• Modifying the Main PLL operation enable bit (PLL1EN) while the clock autogear function is active (gear
up or gear down) is prohibited. Always check the gear status flags before changing the PLL state (see
chapter "Clock Auto-Gear Up/Down" on P. 149 ).
• If the Main clock oscillation is halted (STCR.OSCD1=1), the Main PLL halts during STOP state even if
the PLL enable bit (PLL1EN) is set to "1". If Main PLL operation is enabled (PLL1EN=1), the Main clock
operates using the PLL after recovering from STOP state.
(See the explanation for the clock source selection bits (bit1, bit0:) for details of changing the clock
source.)
• Bit1, bit0: Clock source selection
CLKS1
0
0
1
1
CLKS0
Clock source setting
0
Main clock input from X0/X1 divided by 2 (Initial value)
1
Main clock input from X0/X1 divided by 2
0
Main PLL
1
Mode
Main clock mode
Main clock mode
Main clock mode
-
Setting Disabled
• When changing the clock mode, the value of CLKS0 must not be modified while CLKS1 is "1".
The table below lists the cases in which the CLKS1, CLKS0 bits may be modified.
Table 12.4-1 Allowed transitions from CLKS1 and CLKS0
CM44-10149-1E
Modify permitted
"00B" → "01B" or "10B"
Modify prohibited
"00B" → "11B"
"01B" → "00B"
"01B" → "10B" or "11B"
"10B" → "00B"
"10B" → "01B" or "11B"
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Chapter 12 Clock Control
12.4
MB91460N series
12.4.2 DIVR0: Clock Division Setting Register 0
Sets the division ratio for the clocks used for internal device operation.
• DIVR0: Address 000486H (Access: Byte, Half-word)
7
B3
6
B2
5
B1
4
B0
3
P3
2
P2
1
P1
0
P0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input,
watchdog reset)
Initial value
(software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and
peripheral bus (CLKP).
• Bit7 to bit4: CLKB division selection
B3 to B0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
CPU clock (CLKB) division ratio
φ/1 (initial value)
φ/2
φ/3
φ/4
φ/5
φ/6
φ/7
φ/8
φ/9
φ/10
φ/11
φ/12
φ/13
φ/14
φ/15
φ/16
• Do not change the division ratio with B3 to B0 if current CLKB frequency is equal or above
80MHz!
• Sets the clock division ratio for the clock used by the CPU, internal memory, and internal buses (CLKB).
The 16 options listed in the table are available.
• Do not set a division ratio that exceeds the maximum operating frequency of the device.
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Chapter 12 Clock Control
12.4
MB91460N series
• Bit3 to bit0: CLKP division selection
P3 to P0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
Peripheral clock (CLKP) division ratio
φ/1
φ/2
φ/3
φ/4 (initial value)
φ/5
φ/6
φ/7
φ/8
φ/9
φ/10
φ/11
φ/12
φ/13
φ/14
φ/15
φ/16
• Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP).
The 16 options listed in the table are available.
• Do not set a division ratio that exceeds the maximum operating frequency of the MCU.
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Chapter 12 Clock Control
12.4
MB91460N series
12.4.3 DIVR1: Clock Division Setting Register 1
Sets the division ratio for the clocks used for internal device operation.
• DIVR1: Address 000487H (Access: Byte, Half-word)
7
0
X
R/W
6
0
X
R/W
5
0
X
R/W
4
0
X
R/W
3
–
0
X
R/W
2
–
0
X
R/W
1
–
0
X
R/W
0
–
0
X
R/W
bit
Initial value (INITX pin input, watchdog reset)
Initial value (software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bit.
• Always write "0" to this bit. The read value is the value written.
• Bit3 to bit0: Reserved bit
• Always write "0" to this bit. The read value is the value written.
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CM44-10149-1E
Chapter 12 Clock Control
12.4
MB91460N series
12.4.4 CSCFG: Clock Source Configuration Register
This register sets the clock source.
• CSCFG: Address 0004AEH (Access: Byte)
7
6
EDSUEN PLLLOCK
5
RCSEL
4
MONCKI
3
-
2
-
1
CSC1
0
CSC0
0
X
0
0
0
0
0
0
X
X
X
X
X
X
X
X
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• bit7: EDSU/MPU Enable
EDSUEN
0
1
Function
EDSU/MPU is (clock) disabled [Initial value]
EDSU/MPU is (clock) enabled
• bit6: PLL Lock
PLLLOCK
0
1
Function
PLL is in the un-locked state
PLL is in the locked state
• bit5: CLKRC Selector
RCSEL
0
1
Function
CLKRC is set to 100kHz [Initial value]
CLKRC is set to 2MHz
The selected oscillation frequency is supplied to Real Time Clock and Flash Security Unit (change the oscillation to
2MHz for faster CRC generation). Hardware Watchdog (CR based Watchdog), is always supplied with 100kHz
independent of this setting.
• bit4: Clock Monitor MONCLK inverted
MONCKI
0
1
output
Function
MONCLK mark level is low [Initial value]
MONCLK mark level is high
See chapter "Clock Monitor (Page No.627)" about information about this function.
• bit3, bit2: Reserved bit
• Always write "0" to this bit. The read value is the value written.
• bit1, bit0: Clock Source Selection for RTC
CSC1, CSC0
00
01
10
11
CM44-10149-1E
Function
Real Time Clock is sourced by Main Oscillator
Setting prohibited
Real Time Clock is sourced by RC Oscillator(100kHz)
Setting prohibited
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Chapter 12 Clock Control
12.5
MB91460N series
12.5 Operation
This section describes how to setup and switch between clocks.
12.5.1 Clock Setup Sequence (Example)
Figure 12.5-1 Clock Setup Sequence (Example)
(1) Main clock oscillation stabilization
(2) Operate using initial values (main clock divided by 2).
Setup
operating
clocks.
(2) Set divide ratios for operating clocks. (CLKB, CLKP)
(3) Select PLL multiplier. ( PLLS[2:0] )
(4) Enable main PLL operation (PLL1EN).
(4) Wait for main PLL to lock (See oscillation stabilization wait chapter).
Setup
base
clock.
(5) Select clock source. (CLKS[1:0] )
Main clock mode (divided by 2)
(“00”)
Main clock mode (divided by 2)
(“01”)
Main PLL mode
(“10”)
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Chapter 12 Clock Control
12.5
MB91460N series
12.5.2 Notes
■ Main PLL control
After settings initialization reset (INIT) initialization, the Main PLL oscillation is stopped. While it is stopped, the
output of the Main PLL cannot be selected as the clock source.
When the program operation starts, set the multiplier of the PLL to be used as the clock source, enable it, and
switch the source clock after the PLL lock wait time elapses. For the PLL lock wait time, use of a time base
timer interrupt is recommended.
The Main PLL cannot be stopped while the output of the Main PLL is selected as the clock source (writing to
the register has no effect). To stop the Main PLL upon transition to STOP state, reselect the Main clock
divided by two as source clock before stopping the PLL.
If STCR:OSCD1 or STCR:OSCD2 of the standby control register is set to "1" to stop oscillation in STOP state,
the Main PLL automatically stops when the device enters STOP state. There is no need to stop the Main PLL
(CLKR:PLL1EN=0) explicitly beforehand.
The Main PLL also restarts automatically when recovering from STOP state. When the oscillation is not set to
stop during STOP state (STCR:OSCD1=0), the Main PLL does not stop automatically. In this case, stop the
Main PLL explicitly (CLKR:PLL1EN=0) before changing to STOP state.
■ Main PLL multiplier
To change the Main PLL multiplier setting, change it before or as soon as the Main PLL is enabled after
program execution starts. After changing the multiplier setting, wait for the Main PLL lock time before switching
the clock source. For the Main PLL lock wait time, it is recommended to use a time base timer interrupt.
To change the Main PLL multiplier setting during operation, first change the clock source to a clock other than
the Main PLL. As described above, after changing the multiplier setting, wait for the Main PLL lock time before
changing the clock source.
It is also a safety feature implemented, so the Main PLL multiplier setting can also be changed while the Main
PLL is in use. In this case, the program stops running and the MCU automatically goes to the oscillation
stabilization wait state after the multiplier setting is modified. Therefore this procedure is not recommended.
The program execution is continued, when the specified oscillation stabilization wait time has elapsed.
The program execution does not stop when changing to a clock source other than the Main PLL.
■ Clock division
The clocks used to drive the internal operation of the device allow division ratios relative to the base clock to
be set independently for each clock. This function allows the optimum operating frequency to be selected for
each circuit.
The division ratios are set in the operating clock division setting registers (DIVR0 and DIVR1). These registers
contain 4-bit settings that specify the ratio for each clock. The division ratio relative to the base clock equals
(register value+1). The duty ratio is always 50%, even if an odd numbered division ratio is set.
If the setting is modified, the new setting becomes valid at the next rising edge of the clock.
The division ratio setting is not initialized if an operation initialization reset (RST) occurs, but the settings from
before the reset are retained. The ratio setting is only initialized by a settings initialization reset (INIT). When
changing the clock source from its initial setting to a high speed clock, always set the division ratio first.
An upper-limit frequency for the operation is set for each clock.
Device operation is not guaranteed if the combination of clock source selection, Main PLL multiplier setting,
and division ratio setting results in a frequency higher than the maximum permitted frequency.
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Chapter 12 Clock Control
12.6
MB91460N series
12.6 Settings
Table 12.6-1 Settings for Operating at 1/2 of the Main Clock
Setting
Setting register
Clock source selection
Clock source control register (CLKR)
Setting
procedure*
See 12.7.3
*: For the setting procedure, refer to the section indicated by the number.
Table 12.6-2 Settings for Operating Using the Main PLL
Setting
Setting register
Main PLL operation enable
Clock source selection
Clock source control register (CLKR)
Setting
procedure*
See 12.7.1
See 12.7.3
*: For the setting procedure, refer to the section indicated by the number.
Table 12.6-3 Settings for Selecting the Division Ratio for the Operating Clocks
Setting
Setting register
Clock source selection
Operating clock division ratio selection
Clock source control register (CLKR)
Operating clock division setting registers
(DIVR0, DIVR1)
Setting
procedure*
See 12.7.3
See 12.7.4
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 12 Clock Control
12.7
MB91460N series
12.7 Q & A
12.7.1 How to enable or disable the clock operation
• There is no operation enable bit for the Main clock.
(Halting the oscillation in STOP state is handled separately.)
• Main PLL operation is enabled by the Main PLL operation enable bit (CLKR:PLL1EN).
Operation
To halt the Main PLL
To enable operation of the Main PLL
Main PLL operation enable bit (PLL1EN)
Set to "0".
Set to "1".
Initially, the PLL is halted and therefore PLL operation must be enabled and the PLL started after setting the PLL
multiplier ratio.
12.7.2 How to select the Main PLL multiplier ratio
• The PLL multiplier can be set by using the PLL interface registers PLLDIVM and PLLDIVN (see chapter
"Main PLL Interface" on P. 143 ).
12.7.3 How to select the operating clock source
Use the clock source selection bits (CLKR:CLKS[1:0]) to select Main clock divided by 2, Main PLL as the
operating clock source.
Operating clock source
Clock source selection bits (CLKS[1:0])
Set
initial
values "00B" or "01B".
To change from the initial value to the Main clock divided by 2
To change from the initial value to the Main PLL
Change from the initial values "00B" to "10B".
To change from Main PLL to the Main clock divided by 2
Change from "10B" to "00B".
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Chapter 12 Clock Control
12.7
MB91460N series
12.7.4 How to set the operation clock division ratios
• CPU clock setting
The CPU clock setting is set using the CLKB division ratio selection bits (DIVR0:B[3:0]).
Example frequency
When φ = 32MHz
When φ = 16MHz
Base clock (φ) division ratio
CLKB division ratio selection
bits(B[3:0])
no division
Set to "0000B".
CLKB = 32.0MHz
CLKB = 16.0MHz
2
Set to "0001B".
CLKB = 16.0MHz
CLKB = 8.00MHz
3
Set to "0010B".
CLKB = 10.6MHz
CLKB = 5.33MHz
4
Set to "0011B".
CLKB = 8.00MHz
CLKB = 4.00MHz
5
Set to "0100B".
CLKB = 6.40MHz
CLKB = 3.20MHz
6
Set to "0101B".
CLKB = 5.33MHz
CLKB = 2.66MHz
7
Set to "0110B".
CLKB = 4.57MHz
CLKB = 2.28MHz
8
Set to "0111B".
CLKB = 4.00MHz
CLKB = 2.00MHz
16
Set to "1111B".
CLKB = 2.00MHz
CLKB = 1.00MHz
• Peripheral clock setting
The peripheral clock setting is set using the CLKP division ratio selection bits (DIVR0:P[3:0]).
140
Example frequency
When φ = 32MHz
When φ = 16MHz
Base clock (φ) division ratio
CLKP division ratio selection bits
(P[3:0])
no division
Set to "0000B".
CLKP = 32.0MHz
CLKP = 16.0MHz
2
Set to "0001B".
CLKP = 16.0MHz
CLKP = 8.00MHz
3
Set to "0010B".
CLKP = 10.6MHz
CLKP = 5.33MHz
4
Set to "0011B".
CLKP = 8.00MHz
CLKP = 4.00MHz
5
Set to "0100B".
CLKP = 6.40MHz
CLKP = 3.20MHz
6
Set to "0101B".
CLKP = 5.33MHz
CLKP = 2.66MHz
7
Set to "0110B".
CLKP = 4.57MHz
CLKP = 2.28MHz
8
Set to "0111B".
CLKP = 4.00MHz
CLKP = 2.00MHz
16
Set to "1111B".
CLKP = 2.00MHz
CLKP = 1.00MHz
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CM44-10149-1E
Chapter 12 Clock Control
12.8
MB91460N series
12.8 Caution
• Operation is not guaranteed if the clock source selection, Main PLL multiplier setting, and division ratio
setting result in a frequency that exceeds the maximum.
• It is necessary to follow the sequence in which the clock source selection is set or modified.
• When the Main clock oscillation is halted (OSCDS1 = 1) an oscillation stabilization wait time (for Main clock)
is also required if a reset (INIT) occurs that switches the clock source to the Main clock. In this case,
operation after the reset is not guaranteed if the wait time set in the oscillation stabilization time selection bits
(STCR:OS[1:0]) does not satisfy the oscillation stabilization time requirement for the Main clock.
Always set the oscillation stabilization time selection bits (STCR:OS[1:0]) to a value that provides an
adequate oscillation stabilization time for the Main clock.
In the case of an INIT reset triggered by the INITX pin, the "L" level input must be maintained for long
enough for the Main clock oscillation to stabilize.
See "Chapter 16 Timebase Counter (Page No.171)" and "Chapter 20 Main Oscillation Stabilization Timer
(Page No.211)" for details of the oscillation stabilization wait.
• When changing to STOP state, the Main PLL must either be halted or de-selected. Either set the Main clock
oscillation halt bit (STCR:OSCD1 = 1) to halt automatically or change the operating clock to Main clock
divided by two before changing to STOP state.
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12.8
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Chapter 13 Main PLL Interface
13.1
MB91460N series
Chapter 13 Main PLL Interface
13.1 Overview
• This block diagram (simplified) shows the integration of the PLL and the PLL Interface with the multiplier
control logic (PLLDIVM (1/M), PLLDIVN (1/N) for basic frequency multiplication and PLLDIVG (1/G) for clock
auto gear).
Figure 13.1-1 Block diagram of PLL interface
CLKMAIN/2
divide-by-2
PLL Interface x1, x2, ... x25
Auto-Gear
CLKMAIN
1/G
PLL
CLKPLL
Clock
Modulator
CMCR, CMPR
CLKMOD
1
CLKMAINPLL
0
X
FB
CLKVCO
1/M
CLKPLLFB
1/N
CMCR_
FMOD
Multiplier
PLLDIVM, PLLDIVN,
PLLDIVG, PLLMULG,
PLLCTRL
13.2 Features
• Free programmable divide-by-M counter (1/M) in the range of 1..16
• Free programmable divide-by-N counter (1/N) in the range of 1..64
• Clock auto gear up/down function to prevent voltage drops and surges
13.3 Frequency calculation
• CLKB frequency is determined by :
CLKB = [ CLKMAIN * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR0_B+1) ]
• CLKP frequency is determined by :
CLKP = [ CLKMAIN * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR0_P+1) ]
• CLKT frequency is determined by :
CLKT = [ CLKMAIN * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR1_T+1) ]
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13.4 Registers
13.4.1 PLL Control Registers
Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function.
• PLLDIVM: Address 00048CH (Access: Byte, Halfword, Word)
7
-
6
-
5
-
4
-
3
DVM3
2
DVM2
1
DVM1
0
DVM0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
R0/W0
R0/W0
R0/W0
R0/W0
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bits.
Always write "0" to these bits.
• Bit3 to bit0: PLL divide-by-M selection
DVM3 to DVM0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
......
1111B
(Notes)
PLL output (CLKPLL)
CLKVCO : 1 (no division)
CLKVCO : 2 (division by 2)
CLKVCO : 3 (division by 3)
CLKVCO : 4 (division by 4)
CLKVCO : 5 (division by 5)
CLKVCO : 6 (division by 6)
CLKVCO : 7 (division by 7)
CLKVCO : 8 (division by 8)
.....
CLKVCO : 16 (division by 16)
• Even though it is possible to select no division ratio (:1) for the divide-by-M counter it is not
recommended. The resulting output clock will have an odd clock duty ratio (direct PLL output).
Always select at least a division ratio > 1 and an even division ratio (:2, :4, :6, etc.).
• Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-M counter it
is not recommended. The resulting output clock will have an odd clock duty ratio. Always select an
even division ratio (:2, :4, :6, etc.).
• The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=10).
• It is strongly recommended to disable the PLL (CLKR:PLL1EN=0) while or after changing the
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR:PLL1EN=1) afterwards.
• PLLDIVN: Address 00048DH (Access: Byte, Halfword, Word)x
7
-
6
-
5
DVN5
4
DVN4
3
DVN3
2
DVN2
1
DVN1
0
DVN0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
R0/WX
R0/WX
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
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• Bit7, bit6: Reserved bits. The read value is always "0".
• Bit5 to bit0: PLL divide-by-N selection
DVN5 to DVN0
000000B
000001B
000010B
000011B
000100B
000101B
000110B
000111B
......
111111B
(Notes)
feedback to PLL (CLKPLLFB)
CLKPLL : 1 (no division)
CLKPLL : 2 (division by 2)
CLKPLL : 3 (division by 3)
CLKPLL : 4 (division by 4)
CLKPLL : 5 (division by 5)
CLKPLL : 6 (division by 6)
CLKPLL : 7 (division by 7)
CLKPLL : 8 (division by 8)
.....
CLKPLL : 64 (division by 64)
• The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=10).
• It is strongly recommended to disable the PLL (CLKR:PLL1EN=0) while or after changing the
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR:PLL1EN=1) afterwards.
• PLLDIVG: Address 00048EH (Access: Byte, Halfword, Word)
7
-
6
-
5
-
4
-
3
DVG3
2
DVG2
1
DVG1
0
DVG0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
R0/W0
R0/W0
R0/W0
R0/W0
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bits.Always write "0" to these bits.
• Bit3 to bit0: PLL auto gear start/end divide-by-G selection
DVG3 to DVG0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
......
1111B
(Notes)
PLL output start/end frequency (CLKPLL with Auto-gear function)
Auto gear disabled (initial value)
CLKVCO : 2 (division by 2)
CLKVCO : 3 (division by 3)
CLKVCO : 4 (division by 4)
CLKVCO : 5 (division by 5)
CLKVCO : 6 (division by 6)
CLKVCO : 7 (division by 7)
CLKVCO : 8 (division by 8)
.....
CLKVCO : 16 (division by 16)
• See section 13.6 Clock Auto-Gear Up/Down for detailed information on how to use this function.
• Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-G counter it
is not recommended. Always select an even division ratio (:2, :4, :6, etc.).
• The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=10).
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• PLLMULG: Address 00048FH (Access: Byte, Halfword, Word)
7
MLG7
6
MLG6
5
MLG5
4
MLG4
3
MLG3
2
MLG2
1
MLG1
0
MLG0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit0: MLG7 to MLG0 PLL auto gear divide-by-G step multiplier selection
MLG7 to MLG0
00000000B
00000001B
00000010B
00000011B
00000100B
00000101B
00000110B
00000111B
......
11111111B
(Notes)
Divide-by-G step multiplier
Divide-by-G step × 1 (multiply by 1)
Divide-by-G step × 2 (multiply by 2)
Divide-by-G step × 3 (multiply by 3)
Divide-by-G step × 4 (multiply by 4)
Divide-by-G step × 5 (multiply by 5)
Divide-by-G step × 6 (multiply by 6)
Divide-by-G step × 7 (multiply by 7)
Divide-by-G step × 8 (multiply by 8)
.....
Divide-by-G step × 256 (multiply by 256)
• See chapter 13.6 Clock Auto-Gear Up/Down for detailed information on how to use this function.
• The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=10).
• PLLCTRL: Address 000490H (Access: Byte, Halfword, Word)
7
-
6
-
5
-
4
-
3
IEDN
2
GRDN
1
IEUP
0
GRUP
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
R/W
R/W
R/W
R/W
R/W
RM1/W
R/W
RM1/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bit. The read value is always "0000B".
• Bit3: Interrupt Request Enable Gear DOWN.
IEDN
0
1
Function
Gear DOWN interrupt request disabled [Initial value]
Gear DOWN interrupt request enabled
• Bit2: Interrupt Flag Gear DOWN.
GRDN
0
1
Function
Gear DOWN interrupt not active [Initial value]
Gear DOWN interrupt active
• While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G
counter reaches the programmed end value.
• This bit is read as "1" at a Read-Modify-Write instructions. Writing "1" has no effect.
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13.4
MB91460N series
• Bit1: Interrupt Request Enable Gear UP.
IEUP
0
1
Function
Gear UP interrupt request disabled [Initial value]
Gear UP interrupt request enabled
• Bit0: Interrupt Flag Gear UP.
GRUP
0
1
Function
Gear UP interrupt not active [Initial value]
Gear UP interrupt active
• While switching from clock source oscillator to clock source PLL this flag is set when the divide-by-G
counter reaches the end value defined by the divide-by-M counter.
• This bit is read as "1" at a Read-Modify-Write instructions. Writing "1" has no effect.
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13.5
MB91460N series
13.5 Recommended Settings
PLL Input
(CLKMAIN)
[MHz]
Multiplier Parameter
Auto-Gear Parameter
DIVM
DIVN
DIVG
MULG
PLL Output
(CLKVCO)
[MHz]
CLKPLL
[MHz]
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
• Please consult the available datasheet for the maximum allowed frequency of each clock domain (CLKB,
CLKP) respectively.
Note:
When using MB91V460A, PLL output is used in the range between 80MHz and 170MHz.
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13.6
MB91460N series
13.6 Clock Auto-Gear Up/Down
To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/
DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL
interface.
The main functionality is implemented using two divide-by counters (divide-by-M and divide-by-G
counter), where one supplies the PLL feedback always with the target frequency (divide-by-M counter),
and the other (divide-by-G counter) which increases the frequency from a programmable frequency division given by the divide-by-G setting (DIVG) up to the target frequency given by the divide-by-M setting
(DIVM), or decreases the frequency from the divide-by-M setting (DIVM) down to the programmable end
frequency (DIVG).
In this sense only a setting of DIVG > DIVM is a valid clock gear specification to scale the system clock
from slower frequencies to faster frequencies (when gearing up) and from faster frequencies to slower
ones (when gearing down).
The frequency steps are performed in multiple of the PLL output frequency, e.g. the setting of: Oscillator =
4MHz, M = 2, N = 20 (which is a frequency multiplication of M * N = 40 with PLL output = 160MHz and
frequency output to C-Unit = 80MHz).
The gear divider can be set to any even divider, in this example it is G = 20, which causes the following
gear-up when switching from oscillator to PLL:
1. step : 1 cycle of 8.0MHz (8.0MHz equals 20 cycles of the PLL output)
2. step : 2 cycles of 8.4MHz (8.4MHz equals 19 cycles of the PLL output)
3. step : 3 cycles of 8.8MHz (8.8MHz equals 18 cycles of the PLL output)
:
17. step : 17 cycles of 40.0MHz (40.0MHz equals 4 cycles of the PLL output)
18. step : 18 cycles of 53.3MHz (53.3MHz equals 3 cycles of the PLL output)
19. step : 19 cycles of 80.0MHz (80.0MHz equals 2 cycles of the PLL output)
-> Target frequency reached by transition to last step (here from 18. to 19.)
Each step can be multiplied by setting a multiplication value in the gear multiplier register. The duration
from generating the start frequency up to reaching the target frequency can be calculated by the following
formula:
i
duration = mul t
i
k ( i – k + 1) –
k=1
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k = j +1
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this equals to (resolved closed arithmetic series of the first sum term):
duration = mul t
i ( i + 1) ( i + 2 -)
--------------------------------------------–
6
i
k ( i – k + 1)
k = j +1
with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout)
For the above given setting this equals 1483 PLL output clock cycles with a duration from the start frequency to the target frequency of 9262500 ps (about 9.3 us).
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13.7
MB91460N series
13.7 Caution
When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear
down flags (PLLCTRL:GRUP, PLLCTRL:GRDN) to evaluate the current state of this function to avoid
malfunctions in the clock system due to setting changes prior to completion.
Procedure example:
• Set the PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the selected
frequency and gear duration
• Switch on the PLL (CLKR:PLL1EN=1)
• If interrupts should be received after gearing up or down, also enable the corresponding interrupt
enables (PLLCTRL:IEUP, PLLCTRL:IEDN)
• Wait for the PLL stabilization time
• Set the base clock division registers (DIVR0, DIVR1)
• Switch the clock source to the PLL (CLKR:CLKS "00"-> "10")
• Wait for the PLLCTRL:GRUP gear up flag (either by polling or by interrupt) before switching the
clock source back to oscillation or confirm the setting of PLLCTRL:GRUP=1 before changing bits in
the CLKR register
• Switch the clock source to Oscillator (CLKR:CLKS "10"-> "00")
• Wait for PLLCTRL:GRDN gear down flag (either by polling or by interrupt) before switching the clock
source back to PLL or confirm the setting of PLLCTRL:GRDN=1 before changing bits in the CLKR
register
• Switch off the PLL (CLKR:PLL1EN=0)
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Chapter 14 CAN Clock Prescaler
14.1
MB91460N series
Chapter 14 CAN Clock Prescaler
14.1 Overview
• This block diagram (simplified) shows the integration of the CAN Controller and the D-Bus Interface with the
CAN clock prescaler logic (divide-by-c) and clock source selector.
Figure 14.1-1 Combination of CAN Clock prescaler and CAN interface
CAN Clock Prescaler
CLKMAIN
CLKVCO
1
MUX
3
0
divide-by-c
CLKCAN CAN
Controller
CANPRE_DVC[3:0]
RX/TX
CANPRE_CPCKS[1:0]
CLKCAN
D-Bus
CLKB
CLKB Interface1)
D-Bus
1)
The D-Bus Interface is an interface between CLKB domain (D-BUS) and CLKCAN domain (CAN Controller)
• Remark: PLL clock used with CAN clock prescaler is sharing with PLL that generates the base clock.
Therefore, switch the clock of CAN prescaler to PLL clock after permitting the oscillation of PLL and
the oscillation stability waiting time passes (See Chapter 13/Chapter 14).
• Remark: PLL clock used with CAN clock prescaler is sharing with PLL that generates the base clock.
Therefore, do neither PLL oscillation stop nor multiple change for the base clock generation with
PLL clock selected as a clock of CAN prescaler (See Chapter 13/Chapter 14).
• Remark: Do not change the supply clock by CAN clock prescaler while CAN is operating.
Therefore, change the setting of the supply clock with the INIT bit of the CAN control register set to
"1" (Refer to Chapter 34).
14.2 Features
• CAN clock source selectable out of CLKMAIN, CPU Clock (CLKB) and PLL output
• Free programmable divide-by-c counter in the range of 1..16
• Individual clock disable function for each CAN controller
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14.3
MB91460N series
14.3 Registers
14.3.1 CAN Clock Control Register
Controls the CAN clock source, the clock division ratio and the clock disable.
• CANPRE: Address 0004C0H (Access: Byte)
7
-
6
-
5
CPCKS1
4
CPCKS0
3
DVC3
2
DVC2
1
DVC1
0
DVC0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
R0/W0
R0/W0
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7, bit6: Reserved bit
Always write "0" to these register bits.
• Bit5, bit4: CAN Prescaler ClocK Selection
CPCKS1 to CPCKS0
00B
01B
10B
11B
Prescaler clock source
CLKB, core clock (initial value)
CLKVCO
reserved
CLKMAIN
• Bit3 to bit0: Source clock Divide-by-C selection
DVC3 to DVC0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
......
1111B
(Notes)
154
Source clock divided-by-C (generates CLKCAN)
Source clock : 1 (no division)
Source clock : 2 (division by 2)
Source clock : 3 (division by 3)
Source clock : 4 (division by 4)
Source clock : 5 (division by 5)
Source clock : 6 (division by 6)
Source clock : 7 (division by 7)
Source clock : 8 (division by 8)
.....
Source clock : 16 (division by 16)
• Do not exceed the specified upper frequency limit of CLKCAN (20MHz) by setting prescaler values
exceeding this limit, or by switching the prescaler clock source to a higher frequency clock without
switching previously the prescaler values to higher division rates.
• If prescaler source is selected to CLKVCO: Even though it is possible to select no division ratio (:1)
for the divide-by-C counter it is not recommended. The resulting output clock will have an odd clock
duty ratio (direct PLL output can have up to 90:10 duty). Always select at least a division ratio >
1.To set the duty ratio to 50%, select an even-numbered division ratio (source clock: 2, : 4, : 6, etc).
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Chapter 14 CAN Clock Prescaler
14.3
MB91460N series
• CANCKD: Address 0004C1H (Access: Byte)
7
-
6
-
5
4
CANCKD5 CANCKD4
3
-
2
-
1
-
0
-
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
R/W0
R/W0
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7, bit6: Reserved bit
Always write "0" to these register bits.
• Bit5, bit4: CANCKD5,CANCKD4
Function
CANCKD5
0
Clock supply to CAN controller 5 is enabled
1
Clock supply to CAN controller 5 is disabled
CANCKD4
0
1
Function
Clock supply to CAN controller 4 is enabled
Clock supply to CAN controller 4 is disabled
• Bit3 to bit0: Reserved bit
Always write "0" to these register bits.
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14.3
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Chapter 15 Clock Modulator
15.1
MB91460N series
Chapter 15 Clock Modulator
This chapter provides an overview of the Clock Modulator and its features. It describes the register structure and operation of the Clock Modulator.
15.1 Overview
The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the
spectrum of the clock signal over a wide range of frequencies.
The module is fed with an unmodulated reference clock with frequency F0, provided by the Main PLL circuit. This
reference clock is frequency modulated, controlled by a random signal.
The mean frequency of the modulated clock is equal to the reference clock frequency F0.
Figure 15.1-1 Frequency spectrum of the modulated clock
modulation range
frequency
Fmin
F0
Fmax
● Modulation degree and frequency resolution in frequency modulation mode
Maximum and minimum frequencies (Fmax and Fmin) of the modulated clock are defined by the modulation
degree parameter. Furthermore the resolution of the modulation range is selectable in 7 steps from low (1) to high
(7). Higher resolution implies a finer granularity of discrete frequencies in the spectrum of the modulated clock but
less possible modulation degrees.
In general the highest possible frequency resolution combined with the highest possible modulation degree
results in the highest EMI reduction. But for some cases lower modulation degrees may result in a better EMI
behavior. Refer to the table of possible settings in datasheet.
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Chapter 15 Clock Modulator
15.2
MB91460N series
15.2 Clock Modulator Registers
This section lists the clock modulator registers and describes the function of each register in detail.
● Clock modulator registers
Figure 15.2-1 Clock modulator registers
Address:
0004B9H
7
6
5
4
3
2
1
0
MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
CMPRL (lower)
Initial value
1 1 1 1 1 1 0 1B
R/W R/W R/W R/W R/W R/W R/W R/W
0004B8H
0004BBH
158
15
14
13
-
-
MP13 MP12 MP11 MP10 MP9 MP8
-
-
R/W R/W R/W R/W R/W R/W
7
6
5
12
4
11
3
10
2
9
1
8
0
-
FMOD
Re- ReReserved served served RUN
-
FMOD PDX
-
R/W R/W R/W R
-
R/W R/W
CMPRH (upper)
Initial value
X X 0 0 0 0 0 1 0B
CMCR
Initial value
X 0 0 1 0 X 0 0B
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Chapter 15 Clock Modulator
15.2
MB91460N series
● Clock Modulator Control Register (CMCR)
The Control Register (CMCR) has the following functions:
Set the modulator to power down mode
Modulator enable/disable in frequency modulation mode
Indicates the status of the modulator
Figure 15.2-2 Configuration of the clock modulator control register (CMCR)
7
0004BB H
6
5
4
3
2
1
0
-
FMOD
ReRe- Reserved served served RUN
-
FMOD PDX
-
R/W R/W R/W R
-
R/W R/W
CMCR
Initial value
X 0 0 1 0 X 0 0B
bit 0
PDX
Power down bit
0
power down mode
1
power up
bit 1
FMOD
Frequency modulation enable bit
0
Frequency modulation mode disabled
1
Frequency modulation mode enabled
bit 3
FMOD
RUN
Modulator status in frequency modulation mode
0
Clock frequency unmodulated
1
Clock frequency modulated
bit 4,5,6
Reserved
R/W
R
X
-
:
:
:
:
Readable and writable
Read only
Undefined value
Undefined
:
Initial value
bit 4
Always write 1 to this bit
bit 5,6
Always write 0 to this bit
The bits FMODRUN, FMOD, PDX control or indicate the status of the frequency modulation mode. Frequency
modulation mode needs some additional configuration (CMPR register).
● Clock modulator control register contents
Table 15.2-1 Function of each bit of the clock modulator control register (1 / 3)
Bit name
Function
bit7
undefined
bit 6 to bit5
Reserved
Always write 0 to this bit.
bit 4
Reserved
Always write 1 to this bit.
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Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-1 Function of each bit of the clock modulator control register (2 / 3)
Bit name
bit 3
FMOD RUN:
Modulator status
in frequency
modulation mode
bit
bit 2
Undefined
bit 1
FMOD:
Frequency
modulation
enable bit
160
Function
"0": MCU is running with unmodulated clock
"1": MCU is running with frequency modulated clock
• FMODRUN indicates the status of the modulator output clock in frequency
modulation mode (FMOD=1). If the output clock is frequency modulated,
MODRUN is set to 1, otherwise MODRUN is set to 0.
• After enabling the frequency modulation mode by setting FMOD to 1, the
modulator is calibrated. During this time, the clock is unmodulated. Therefore it
takes several μs before the output clock switches to modulated clock and the
FMODRUN bit is set to 1. The calibration time depends on the frequency of the
oscillator.
• During normal operation, after calibration is finished, the clock is not switched to
unmodulated clock anymore.
• Due to the synchronization of the FMOD signal and the synchronized switching
to unmodulated clock, it takes less than 9 × T0 (input clock period) before
FMODRUN changes to 0 and the clock switches to unmodulated clock after the
modulator is disabled.
• The FMODRUN bit is read only. Writing to FMODRUN has no effect.
• Before changing the parameter register CMPR, the modulator must be disabled > FMOD=0 and FMODRUN=0.
"0": Frequency modulation disabled.
"1": Frequency modulation enabled.
• To enable the modulator in frequency modulation mode, FMOD must be set to 1.
• Before the modulator can be enabled, the PLL must deliver a stable reference
clock (PLL lock time must be elapsed).
• Each PLL output frequency offers a set of possible modulation parameters. The
selected setting (CMPR register) and the PLL frequency must match.
For more information refer to the CMPR register description.
• Whenever the PLL output frequency is changed or the PLL is switched off e.g. in
power down modes, the modulator must be disabled before -> FMOD=0 and
FMODRUN=0.
• Before the modulator can be enabled, it must be switched from power down to
active mode by setting PDX to 1. And the startup time must be awaited.
Refer to the application note for a description of the recommended startup
sequence.
• Before the modulator can be enabled in frequency modulation mode, a proper
setting must be selected via the parameter register CMPR.
• After enabling the frequency modulation mode by setting FMOD to 1, the
modulator is calibrated. During this time, the clock is unmodulated. Therefore
the output clock does not switch immediately to modulated clock. The status of
the clock (frequency modulated / unmodulated) is indicated by the FMODRUN
status bit. Refer to the FMODRUN bit description.
• Due to the synchronization of the FMOD signal and the synchronized switching
to unmodulated clock, it takes less than 9 × T0 (input clock period) before the
clock switches to unmodulated clock after the modulator is disabled. The
modulator can be disabled at any time.
• Before changing the parameter register CMPR, the modulator must be disabled > FMOD=0 and FMODRUN=0.
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Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-1 Function of each bit of the clock modulator control register (3 / 3)
Bit name
bit 0
CM44-10149-1E
PDX:
Power down bit
Function
"0": Power down mode
"1": Power up
• PDX is the power down signal for the modulator. Before the frequency
modulation mode can be enabled, this bit must be set to 1 and the startup time
must be awaited for 6 μs. For more information refer to the application note for a
description of the recommended startup sequence.
• Before switching to power down mode (PDX=0), the modulator must be disabled
-> FMOD=0 and FMODRUN=0.
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MB91460N series
In the Table below the modulator states are summarized:
Table 15.2-2 States of the modulator
FMOD
PDX
FMODRUN
(read only)
modulator disabled
0
0
0
modulator power on,
waiting modulator startup time (> 6 μs)
(modulation calibration time + modulation startup time)
0
1
0
modulator enabled in frequency modulation mode,
modulator is calibrating, modulation not active
1
1
0
modulator is running in frequency modulation mode
modulation is active
1
1
1
others not allowed
● Clock Modulation Parameter Register (CMPR)
The Clock Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation
mode.
Figure 15.2-3 Clock Modulation parameter register
Address:
0004B9H
7
6
5
4
3
2
1
0
MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
CMPRL (lower)
Initial value
1 1 1 1 1 1 0 1B
R/W R/W R/W R/W R/W R/W R/W R/W
15
0004B8H
14
13
12
11
10
9
8
MP13 MP12 MP11 MP10 MP9 MP8
R/W R/W R/W R/W R/W R/W
R/W
X
CMPRH (upper)
Initial value
XX0000010B
: Readable and writable
: Undefined value
: Undefined
• The modulation parameter determines the degree of modulation and the maximal and minimal occurring
frequencies in the modulated clock. Refer to the application note for a description of an approach to select the
optimal setting.
• Each set of possible modulation parameters refers to a particular PLL frequency. The PLL frequency and the
selected parameter must match. Refer to the following table of possible settings.
• The modulation parameter affects only the frequency modulation mode.
Note:
The modulation parameter must be changed only when the modulator is disabled and the RUN flag is 0
(FMOD=0, FMODRUN=0).
When using the clock modulator, the operating frequency is up to 24MHz in MB91V460A.
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Chapter 15 Clock Modulator
15.2
MB91460N series
● Modulation parameter register contents
Table 15.2-3 Function of each bit of the modulation parameter register (CMPR)
Bit name
Function
bit 15, bit 14
Undefined
bit 13 to bit 0
MP13 to MP0:
Modulation
Parameter bits
Depending on the PLL frequency the following modulation parameter settings are
possible. The corresponding CMPR register value is stated in the most right
column.
F0:
Frequency of unmodulated input clock (PLL frequency)
T0:
Period of unmodulated input clock (PLL clock period)
resolution:
Resolution of frequencies in the modulated clock. low (1) to high (7)
Fmin:
Minimal frequency occurring in the frequency modulated clock
Fmax:
Maximal frequency occurring in the frequency modulated clock
phase skew:
The maximal phase shift of the modulated clock relative to the unmodulated
reference clock in terms of clock periods of the unmodulated clock.
Example: Phase skew = 1.44
In worst cases, the sequence of n periods of the modulated clock may be shorter or
longer than the sequence of the n periods of the unmodulated standard clock by
1.44 × T0.
phase skew 50:
Phase skew for sequences with n<= 50 periods
CMPR:
Register setting of the CMPR register
Figure 15.2-4 Skew of modulated clock vs. unmodulated clock
n periods
CLKPLL (reference clock)
+ phase skew
n periods
CLKMOD (modulated clock)
n periods
For values about the modulation see the datasheet.
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Chapter 15 Clock Modulator
15.2
MB91460N series
Note:
Consider the actual maximal allowed clock frequency of the MCU (refer to the data sheet).
Refer to the datasheet of each device about modulation parameter settings.
Table 15.2-4 Setting of clock modulator (1 / 5)
Modulation
(k)
Internal parameter
(N)
CMPR
[hex]
Base clock
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
3
026F
80
72.6
89.1
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
2
3
046E
76
65.3
90.8
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
2
3
046E
64
55.3
75.9
2
5
04AC
64
49.9
89.1
3
3
066D
64
52.5
82
4
3
086C
64
49.9
89.1
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
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CM44-10149-1E
Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-4 Setting of clock modulator (2 / 5)
Modulation
(k)
Internal parameter
(N)
CMPR
[hex]
Base clock
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
2
3
046E
52
45.2
61.2
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
5
3
0A6B
52
38.8
78.6
6
3
0C6A
52
37.1
86.8
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
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Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-4 Setting of clock modulator (3 / 5)
Modulation
(k)
Internal parameter
(N)
CMPR
[hex]
Base clock
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
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CM44-10149-1E
Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-4 Setting of clock modulator (4 / 5)
Modulation
(k)
Internal parameter
(N)
CMPR
[hex]
Base clock
[MHz]
Fmin
[MHz]
Fmax
[MHz]
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
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Chapter 15 Clock Modulator
15.2
MB91460N series
Table 15.2-4 Setting of clock modulator (5 / 5)
Modulation
(k)
Internal parameter
(N)
CMPR
[hex]
Base clock
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
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CM44-10149-1E
Chapter 15 Clock Modulator
15.3
MB91460N series
15.3 Application Note
Startup/stop sequence for frequency modulation mode.
Modulation parameter for frequency modulation mode.
● Recommended startup sequence for frequency modulation mode
start
1.
Switch modulator from power down to power up mode PDX=1
2.
Switch on PLL
3.
Wait PLL lock time (refer to the MCM flag description in "Chapter 12 Clock Control").
At the same time the modulator starts up.
4.
Set CMPR register to a proper setting
5.
Enable frequency modulation mode FMOD=1
After the calibration is finished, the clock switches from unmodulated to modulated clock and
the FMODRUN flag changes to 1
... running...
stop
6.
Disable modulator FMOD=0
7.
Wait until FMODRUN changes to 0
8.
Switch to power down mode PDX=0
9.
Disable PLL, switch to power down mode, etc.
Note:
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the
modulator is running.
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Chapter 15 Clock Modulator
15.3
MB91460N series
● Modulation parameter for frequency modulation mode
It is not possible to recommend a particular modulation parameter setting to achieve a particular reduction in EMI.
The best setting depends much on the actual application, the whole system and the requirements.
In order to find the optimal modulation parameter setting in frequency modulation mode, the following approach is
recommended.
1.
Define the required PLL frequency based on performance needs
Example: 16MHz
2.
Determine the maximal allowed clock frequency of the MCU
Example: 32MHz
3.
Choose the setting with the highest resolution and the highest modulation
degree, whose maximal frequency is below the maximal allowed clock
frequency of the MCU.
Example: Resolution: 7,
Modulation degree: 2,
CMPR=05F2H (Fmax=
30.34MHz)
4.
Perform EMI measurements
5.
If the EMI measurements do not fulfill the requirements, either
6.
170
The modulation degree at the same frequency resolution should be
reduced
(this may improve the reduction in the upper frequency band > 100MHz,
but decrease the reduction of the fundamental < 100MHz)
Example: Resolution: 7,
Modulation degree:1,
CMPR=03F9H
or
Increase the modulation degree at a lower frequency resolution
(this may improve the reduction of the fundamental < 100MHz, but
worsen the reduction in the upper frequency band > 100MHz)
Or,
Example: Resolution: 5,
Modulation degree: 3,
CMPR=0771H
Repeat item 3) with the new setting and continue until the best settings is
identified
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 16 Timebase Counter
16.1
MB91460N series
Chapter 16 Timebase Counter
16.1 Overview
The timebase counter is a 26-bit up-counter that counts the base clock.
When recovering from a state in which the selected clock source for the MCU has been, or may have been,
halted, the MCU automatically changes to the oscillation stabilization wait state to avoid any unstable output
from the oscillator.
During the oscillation stabilization wait time, supply of internal and external clocks is halted and only the
timebase counter continues to operate until the time set by the oscillation stabilization wait time setting has
elapsed.
The Timebase Counter and the Timebase Timer (See "Timebase Timer" on P. 185) are based on the same
hardware module. The Timebase counter is used in this chapter to generate the oscillation stabilization wait
time.
Later, when the software is running, the Timebase counter is used as a timer (Timebase Timer).
Figure 16.1-1 Timebase Counter (overview diagram)
Temporary Stop Causes
Base clock φ
Timebase counter
Watchdog Time
Selection
Watchdog reset
Timebase Time
Selection
Timebase Timer
Interrupt
Oscillation Stabilization
Wait Time Selection
Oscillation Stabilization
Wait control signal
26-bit up counter
This diagram is just an overview. Each part is explained in detail in the respective chapter.
The timebase counter, timebase timer, and watchdog timer are collectively called the watchdog control unit.
Figure 16.1-2 Timebase counter when used to generate the oscillation stabilization wait
Timebase counter
Base clock φ
Oscillation stabilization wait time selection
26-bit up counter
Selector
Edge detection
Oscillation
stabilization
wait control
signal
16.2 Features
16.2.1 Timebase Counter (when used to generate the oscillation stabilization wait)
Type
Clock source
Clear
CM44-10149-1E
: 26-bit up-counter
: Base clock (just CLKMAIN / 2, because PLL is not running)
: Cleared automatically when changing to oscillation stabilization wait state.
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Chapter 16 Timebase Counter
16.2
MB91460N series
16.2.2 Events that Invoke an Oscillation Stabilization Wait
■ Events that invoke an oscillation stabilization wait using the timebase counter
● Wait time after a settings initialization: Invoked automatically (timebase counter)
• INITX Initial oscillation stabilization wait after pin input
• Watchdog reset (SWWD and HWWD)
• If the Main clock oscillation has not been halted: Oscillation stabilization wait not required
• If the Main clock oscillation has halted: Oscillation stabilization wait is required
● Wait time after recovering from STOP state: Invoked automatically (timebase counter)
• STOP state cases when clock oscillation circuit is halted:
• The oscillation stabilization wait time for the intended oscillation circuit is required
• Wait time for Main PLL to lock is required (if Main PLL is used)
• STOP state cases when clock oscillation circuit is not halted:
• Wait time for Main PLL to lock is required (if Main PLL is used)
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CM44-10149-1E
Chapter 16 Timebase Counter
16.3
MB91460N series
■ Events that invoke an oscillation stabilization wait using other than the timebase counter
● Wait time after power on: Provided by INITX pin input
● When recovering from Main clock oscillation halted: Enabling the Main clock oscillation and
waiting for oscillation to stabilize is required.
● Main PLL lock wait time (for Main clock operation): Using the timebase timer interrupt to generate
this time is recommended.
• A wait time is required after the Main PLL operation is enabled.
• A wait time is required after the Main PLL multiplier setting is changed.
16.3 Configuration
Figure 16.3-1
Configuration Diagram of the timebase counter used to generate the oscillation
stabilization wait time
Oscillation Stabilization Wait Time Section
0
1
0
1
1
1
0
0
1
1
0
1
1
φ
φ
φ
φ
CLKMAIN-divided-by-2
Edge detection
0
0
ST CR:bit3, bit2
0
Selector
CLKR :bit1, bit0
CLKS1, CLKS0
OS1, OS0
×
×
×
×
21
211
216
222
Oscillation stabilization
wait control signal
Main PLL
Setting disabled
Time-base counter
(26-bit counter)
CLKMAIN -divided-by-2
Main PLL
0
1
2
3
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
21
22
23
24
210
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
Base clock (φ)
Clear the timer
(Auto control)
- INITX pin input
- Watchdog reset
- STOP
Figure 16.3-2 Register List
Time-base counter
Address Bit
7
6
000481H
STOP SLEEP
Clock control
Address Bit
000484H
CM44-10149-1E
7
---
6
---
5
HIZ
4
SRST
3
OS1
5
---
4
---
3
---
2
OS0
1
---
0
OSCD1 STCR
2
1
0
PLL1EN CLKS1 CLKS0 CLKR
FUJITSU MICROELECTRONICS LIMITED
(Standby control register)
(Clock source control register)
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16.4
MB91460N series
16.4 Registers
16.4.1 STCR: Standby Control Register
Controls transition to standby modes, pin states during STOP state, whether to halt the clock during STOP
state, the oscillation stabilization wait time, and software reset.
Note: See also "Chapter 10 Standby (Page No.107)" and "Chapter 18 Software Watchdog Timer (Page No.195)"
chapters.
• STCR: Address 000481H (Access: Byte)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
-
0
OSCD1
0
0
1
1
0
0
1
1
0
0
R/W
0
0
R/W
1
X
R/W
1
1
R1,W
X
X
R/W
X
X
R/W
1
X
RX,W
1
X
R/W
bit
Initial value
(INITX pin input)
Initial value (Watchdog)
Initial value (Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• bit7: STOP state (STOP)
• Setting "1" changes to STOP state.
• bit6: SLEEP state (SLEEP)
• Setting "1" changes to SLEEP state.
• If this bit and the STOP state bit (STOP) bit are set to "1" at the same time, the device goes to STOP
state.
• bit5: High impedance mode (HIZ)
• Setting "0" specifies that pins maintain the same states they have on entering STOP state.
• Setting "1" specifies that pin outputs go to high impedance (Hi-Z) during STOP state.
• bit4: Software reset (SRST)
• Setting "0" triggers a software reset.
• Note that negative logic is used.
• bit3, bit2: Oscillation stabilization time selection
OS[1:0]
00
01
10
11
The oscillation stabilization wait time after a reset (INIT) or on recovering
from STOP state.
Oscillation stabilization
When using Main clock
wait time
(For a 4.0MHz Main clock)
1.00μs
φ × 21
1.0ms
φ × 211
32ms
φ × 216
2s
φ × 222
• φ: Main clock divided by two
• In the case of a reset triggered by an INITX pin input, operation defaults to "00" (φ × 21, Main clock).
• In the case of other resets or on recovering from STOP state, the specified clock (Main) and oscillation
stabilization wait time (OS[1:0]) are used.
• The count is performed by the timebase counter.
• bit1: Reserved Bit
Always write "0" to this bit.
• bit0: Main clock oscillation halt (OSCD1)
Setting "1" specifies that the Main clock oscillation halts in STOP state.
(See "16.8 Caution (Page No.183)".)
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16.4.2 CLKR: Clock Source Control Register
Selects the clock source for the base clock used to run the MCU and controls the PLL.
Note: See also the "Chapter 12 Clock Control (Page No.129)".
• CLKR: Address 000484H (Access: Byte)
7
-
6
-
5
-
4
-
3
-
2
PLL1EN
1
CLKS1
0
CLKS0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
R/W0
R/W0
R/W0
R/W0
R/W
R/W
R/W
R/W
bit
Initial value
(INITX pin input)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit4: Reserved bit
Always write "0" to these bits. The read value is the value written.
• Bit3: Reserved Bit
• Always write "0" to this bit.
• Bit2: Main PLL operation enable (PLL1EN)
• Setting this bit to "1" starts Main PLL operation. Main PLL can be selected as the operating clock after
the Main PLL has locked.
• Bit1, bit0: Clock source selection
CLKS1
0
0
1
1
CLKS0
0
1
0
1
Clock source setting
The Main clock input from X0/X1 divided by 2 (initial value)
The Main clock input from X0/X1 divided by 2
Main PLL
Setting Disabled
Mode
Main clock mode
Main clock mode
Main clock mode
Setting Disabled
When changing the clock mode, the value of CLKS0 cannot be modified if CLKS1 is "1"
The table below lists the cases when the CLKS1, CLKS0 bits may or may not be modified.
Table 16.4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified
Modify permitted
"00B" -> "01B" or "10B"
Modify not permitted
"00B" -> "11B"
"01B" -> "00B"
"01B" -> "10B" or "11B"
"10B" -> "00B"
"10B" -> "01B" or "11B"
The clock source for the timebase counter during the oscillation stabilization wait time is set by the clock source
selection bits.
Clock source for timebase
counter during oscillation stabilization wait time
CLKS1
CLKS0
0
0
0
1
The Main clock input from X0/X1 divided by 2 (initial value)
Main clock mode
1
0*
1
Setting Disabled
Setting Disabled
1
Mode
* : The PLL is not active during oscillation stabilization time, therefore the setting "01" also selects Main clock divided by 2.
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16.5
MB91460N series
16.5 Operation
This section describes the events that trigger an oscillation stabilization wait and the operation in each case.
16.5.1 INITX Pin Input
An oscillation stabilization wait is required after power on. As the wait time provided by the initialized timebase
counter is too short, the INITX pin input must be held at the "L" level.
Figure 16.5-1 Using the Width of the Pin Input to Provide the Oscillation Stabilization Wait Time
Using the INIT pin input to trigger
a reset and provide the oscillation
stabilization wait time for the
main clock
Example power-on Vcc
(1)
(3)
Example main clock startup
Time-base
counter count
Provide a sufficient oscillation
(5)
stabilization wait time
21
Time
000H
2 1 (Bit 0 output)
INITX pin input
(4)
(5)
(2)
State transition
Undefined
Initial value of oscillation
stabilization wait time is too short
(6)
(2)
(7)
Main-RUN
Oscillation stabilization wait reset
Settings initialization
(INIT)
(8)
Operation initialization (SRST)
Reset cancellation sequence
(1) Power turned on
(2) Start INITX pin input (Settings initialization reset)
(3) Main clock oscillation starting
(4) INITX pin input (to provide a sufficient time for the Main clock oscillation to stabilize)
(5) INITX pin input removed. The timebase counter is initialized and starts counting.
(6) Oscillation stabilization wait time provided by timebase timer/counter (Initial value = minimum value)
(If the INITX pin input (4) is not maintained, the wait time is too short.)
(7) Operation initialization reset, reset cancellation sequence
(8) Main-RUN
■ INITX Pin input when Main clock running
The device goes to the operation initialization reset (RST) state automatically after the minimum oscillation
stabilization wait time elapses.
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16.5.2 Watchdog Reset - HWWD and SWWD (The specified oscillation stabilization wait
time is generated automatically)
■ Watchdog reset when Main clock operating
Although no oscillation stabilization wait is required in this case, the specified wait time is generated
automatically.
16.5.3 Recovering from STOP state via an Interrupt
■ When changing from Main PLL operation to STOP state with the Main clock oscillation halted
(STCR:OSCD[2:1]=11B):
The Main oscillation circuit generates the selected oscillation stabilization time automatically.
Figure 16.5-2 Recovering from STOP state with the Main Clock Halted to
Main PLL Operation via an Interrupt
Usint the time-base counter to generate oscillation stabilization wait
Main clock/Main PLL
(2)
Example main clock startup
Example main PLL lock
Provide a sufficient oscillation
stabilization wait time
(4)
Time-base
counter 2 22
count
(2)
Time
000H
2 22 (Bit 21 output)
External interrupt (level detect)
Clock timer interrupt
Realtime clock interrupt
(4)
(1)
(5)
Internal reset signal
(3)
State transition
Main stop mode with main clock
oscillation stabilization halted
Oscillation stabilization
wait/PLL lock wait
Main PLL operation
(1) Enabled interrupt is generated (end STOP state)
(2) The timebase counter is cleared automatically and then starts counting.
(3) Oscillation stabilization wait time (specified value)
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)
(4) Interval time for timebase counter
(5) Main PLL operation
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■ When changing to STOP state without halting the clock oscillation circuit (Main PLL/Main):
Although no oscillation stabilization wait is required in this case, a wait is generated automatically. Accordingly,
it is recommended that the interval time is set to its minimum value before changing to STOP state.
• When recovering from STOP state, the device goes to the oscillation stabilization wait state immediately
after STOP state is released.
• The next state after the oscillation stabilization wait completes depends on what triggered recovery from
STOP state.
• If recovery was triggered by an enabled external interrupt, or main oscillation stabilization wait timer
interrupt, the device goes to the normal operating state (RUN).
Note: If the Main PLL continues to operate in STOP state, changing to STOP state with the Main PLL clock set
as the active clock is not permitted. Always set the active clock to the Main clock divided by two
beforehand.)
16.5.4 The lock wait time for the Main PLL must be generated by software.
■ Wait time after Main PLL operation enabled:
Using the timebase timer interrupt is recommended
However, the Main PLL must not be selected as the clock source.
■ Wait time after Main PLL multiplier modified:
Using the timebase timer interrupt is recommended
However, the Main PLL must not be selected as the clock source.
See "Chapter 17 Timebase Timer (Page No.185)" for details.
16.5.5 When Recovering from an Abnormal State with the Main PLL Selected
When the Main PLL is set as the clock source and a problem of some sort occurs in Main PLL control (such as
the multiplier setting being changed or the Main PLL enable bit modified during Main PLL operation), the
device goes to the oscillation stabilization wait state automatically to provide the Main PLL lock time. The
device then goes to normal operating mode after the oscillation stabilization wait elapses.
16.5.6 Types of Oscillation Stabilization Wait
■ Timebase counter
Automatically provides a count for the oscillation stabilization wait time.
When a trigger occurs to change the device to the oscillation stabilization wait state, the timebase counter is
cleared and then starts counting the specified oscillation stabilization wait time.
■ "L" level input to INITX pin
When device operation is restarted by inputting an "L" level to the INITX pin while the oscillation is halted (the
three cases listed below), the width of the "L" level input provides the stabilization time required by the
oscillation circuit.
• INITX pin input after power turned on.
• INITX pin input when oscillation halted during STOP state
■ Timebase timer
Using the timebase timer to generate the Main PLL lock time is recommended.
See "Chapter 17 Timebase Timer (Page No.185)" for details.
■ Main oscillation stabilization wait timer
See "Chapter 20 Main Oscillation Stabilization Timer (Page No.211)" for details.
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16.5
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16.5.7 Whether or not a Stabilization Wait is Required for Each State Transition
Figure 16.5-3 Stabilization Wait for each state transition (necessary or not)
Reset due to INIT pin input
State
PLL
Main
Wait time after power on
X
X
Main clock running
(= main clock oscillation running)
X
0
0
0
Main PLL running
(= main PLL oscillation running)
Main stop (main clock/main PLL
oscillation running)
0/X
Operation after
INIT signal input
Is oscillation stabilization
wait required ?
Operate using initial Must be provided by
value (CLKMAIN/2) width of INIT oin input
Operate using initial
value (CLKMAIN/2)
Oscillation stabilization
wait not required
0
From main clock (1/2) running to
main stop (main clock halted)
X
X
From main PLL running to main stop
(Main clock halted)
X
X
Main clock oscillation stabilization
wait in progress
X
X
Remarks
The automatic oscillation stabilization
wait (minimum value) is too short
Uses the automatic oscillation
stabilization wait
(initial value = minimum value)
Operate using initial
value (CLKMAIN/2)
Must be provided by
width of INIT oin input
The automatic oscillation stabilization
wait (minimum value) is too short
Watchdog reset
State
PLL
Main
Main clock running
(= main clock oscillation running)
X
0
Main PLL running
(= main PLL oscillation running)
0
0
Operation after
INIT signal input
Is oscillation stabilization
wait required ?
Operate using
initial value
(CLKMAIN/2)
Oscillation stabilization
wait not required
Remarks
Uses the automatic oscillation
stabilization wait.
(The oscillation stabilization wait time
is not initialized)
Recovery from STOP state via an Interrupt
State
PLL
Main-STOP
(CLKMAIN continues during
STOP state, main PLL running)1)
Main-STOP
(CLKMAIN continues during
STOP state, main PLL halted)
Main-STOP
(CLKMAIN halted during
STOP state (automatic))
Main
Op. State after recovering
from STOP state via
Interrupt
Is oscillation stabilization
wait required ?
Remarks
Previous operation state
(CLKMAIN/2)
When changing to main PLL Uses the automatic oscillation
after recovering, a main PLL stabilization wait. Set wait time setting
lock wait time is required
to OS[1:0]= 11 to provide the main
PLL lock time.
0
0
X
0
Previous operation state
(CLKMAIN/2)
Oscillation stabilization
wait not required
X
X
Previous operation state
(CLKMAIN/2)
Uses the automatic oscillation
Main clock oscillation and
stabilization wait. Set an appropriate
main PLL lock wait required wait time setting.
Uses the automatic oscillation
stabilization wait. Set wait time setting
to minimum value.
1) The active clock must be set to CLKMAIN/2 before changing to STOP state.
Main PLL oscillation enable
State
PLL
Main
Main PLL oscillation enabled
Is oscillation stabilization wait
required ?
CLKMAIN/2
running
X
0
Start Main clock oscillation/
Change PLL multiplier
setting
Main PLL lock wait required
Remarks
It is recommended to use the time-base
timer to generate the Main PLL lock
wait time.
0: Oscillation running, X: Oscillation halted
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16.6
MB91460N series
16.6 Settings
Table 16.6-1 Settings Required to Specify the Oscillation Stabilization Wait Time
Setting
Setting register
Oscillation stabilization wait time setting
Standby control register (STCR)
Setting
procedure*
See 16.7.1
*: For the setting procedure, refer to the section indicated by the number.
Table 16.6-2 Settings Required to Setup an INITX Pin Reset
Setting
INITX pin input
Setting item
Setting procedure
Refer to the oscillator parameters and the reset
parameters in the Data Sheet.
–
• Settings required to specify the oscillation stabilization wait time for the Main clock
See "Chapter 20 Main Oscillation Stabilization Timer (Page No.211)".
• Settings required to specify the PLL lock wait time
See "Chapter 17 Timebase Timer (Page No.185)".
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16.7
MB91460N series
16.7 Q&A
16.7.1 How to setup the oscillation stabilization wait time that is generated automatically
Use the oscillation stabilization wait time selection bits (STCR:OS[1:0]). (The following lists likely scenarios
and the required settings.)
Oscillation stabilization
wait time selection bits
(OS[1:0])
Scenario
To not halt the Main PLL or oscillator during STOP state
(No oscillation stabilization wait time required)
To not stop the oscillator during external clock input or STOP
state
(Main PLL lock wait time)
When using an oscillator with a fast stabilization time such as a
ceramic resonator
(Oscillation stabilization wait time (medium))
When using a standard quartz oscillator
(Oscillation stabilization wait time (long))
Example oscillation stabilization
wait time
after a reset (INIT) or on
recovering from STOP state
Oscillation
4.0MHz
stabilization
Main clock
wait time
running
Set "00".
φ × 21
1.00μs
Set "01".
φ × 211
1.0ms
Set to "10".
φ × 216
32ms
Set to "11".
φ × 222
2s
• φ: Main clock divided by 2
• In the case of an INITX pin input, operation defaults to "00" (φ × 21= Main clock divided by 4).
• For other resets and when recovering from STOP state, the operation is in accordance with the specified
clock (Main) and oscillation stabilization wait time (OS[1:0]) setting.
• The count is performed by the timebase counter.
• Once the time is selected, it is not initialized except by a settings initialization triggered by the external
INITX pin.
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16.7.2 How to set the oscillation stabilization wait time without generating it
automatically
The settings described below for various cases are required.
Oscillation
State (before transition)
PLL
Main
Wait time after power on
×
×
Main clock oscillation
stabilization wait
×
×
Oscillation
State (before transition)
Main clock (1/2) running
PLL
×
Main
O
Condition (after
transition)
Is oscillation
stabilization wait
required?
To set the oscillation
stabilization wait time
Operation after INITX
pin input defaults to
Main clock (1/2) (Initial
value)
Main clock
oscillation
stabilization wait is
required
As the automatic oscillation
stabilization wait (minimum value)
is too short, the width of the
INITX pin must be sufficient to
provide the stabilization time.
Main PLL running and
enabled
Is oscillation
stabilization wait
required?
To set the oscillation
stabilization wait time
Start Main PLL
oscillation/
Change PLL multiplier
setting
Using the timebase timer to
Main PLL lock wait
generate the Main PLL lock wait
required
time is recommended.
O: Oscillation running, ×: Oscillation halted
16.7.3 What is the clear timing for the timebase counter?
• The timebase counter is only cleared automatically by INITX pin input, and by watchdog reset (SWWD and
HWWD)
The timebase counter automatically starts counting after being cleared.
• The timebase counter can also be cleared by software.
See "Chapter 17 Timebase Timer (Page No.185)" for details.
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Chapter 16 Timebase Counter
16.8
MB91460N series
16.8 Caution
• Clock source
If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required.
• Oscillation stabilization wait time
The wait time set in the oscillation stabilization time selection bits (STCR:OS[1:0]) is not initialized by any
reset except a reset triggered by the external INITX pin input or the RC based watchdog. For other resets
including settings initialization resets (timebase counter based watchdog reset) and operation initialization
resets (RST), the wait time set prior to the reset is used.
• Watchdog reset (Timebase Counter based watchdog)
Although an oscillation stabilization wait time is not required if a watchdog reset occurs while the Main clock
is running (Main), a wait time is generated automatically. In this case, the oscillation stabilization wait time
(STCR:OS[1:0]) is not initialized.
• "L" level input to INITX pin
As the oscillation stabilization wait time is initialized to its minimum value when an initialization is triggered
by an INITX pin input, the wait time in this case is too short. Ensure the INITX pin input width is long enough
to provide the oscillation stabilization wait time.
In the following three cases, maintain the INITX pin input at the "L" level for long enough to provide the
oscillation stabilization wait time required by the oscillation circuit.
• INITX pin input after turning on the power
• INITX pin input after oscillation halted in STOP state
• Main PLL lock wait
If enabling the Main PLL from the halted state after program execution starts, the Main PLL must not be
used until after sufficient time has elapsed for the Main PLL to lock.
Similarly, when changing the multiplier setting for the Main PLL when the PLL is running, the new Main PLL
clock must not be used until sufficient time has elapsed for the Main PLL to lock.
Using the timebase timer interrupt to generate the Main PLL lock wait time is recommended.
• Cases when oscillation stabilization wait is not required
Although no oscillation stabilization wait is required when recovering via an interrupt from Main-STOP state
when the Main clock oscillation has not been halted, the oscillation stabilization wait is generated
automatically. Setting the wait time to its minimum value prior to entering STOP state is recommended.
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Chapter 17 Timebase Timer
17.1
MB91460N series
Chapter 17 Timebase Timer
17.1 Overview
The Timebase Timer and the Timebase Counter (Chapter 16 Timebase Counter (Page No.171)) are based
on the same hardware module. The Timebase counter is used in this chapter as an Timebase timer.
The timebase timer is an interval-interrupt generating timer that is used to acquire Main PLL lock wait time and
to count a long time.
Figure 17.1-1 Timebase Counter (overview diagram)
Temporary Stop Causes
Base clock φ
Timebase counter
Watchdog Time
Selection
Watchdog reset
Timebase Time
Selection
Timebase Timer
Interrupt
Oscillation Stabilization
Wait Time Selection
Oscillation Stabilization
Wait control signal
26-bit up counter
This diagram is just an overview. Each part is explained in detail in the respective chapter.
The timebase counter, timebase timer, and watchdog timer are collectively called the watchdog control unit.
Figure 17.1-2 Timebase Counter used to generate the Timebase Timer Interrupt
Timebase counter
Timebase Time selection
Base clock φ
26-bit up counter
Selector
Timebase
timer control
Timebase timer
interrupt (#140)
17.2 Features
■ Timebase timer (TBT)
• Type
: Detects timebase timer bit output and generates an interval interrupt.
• Quantity
:1
• Interval time: 8 types (Timebase timer bit output)
Period = φ × 211,φ × 212, φ × 213, φ × 222, φ × 223, φ × 224, φ × 225, φ × 226
• Operation start/stop: Always in operation (Can be replaced by interrupt request enable control)
• Timebase counter clear: Continuously writes "A5" or "5A" in the timebase counter clear register CTBR using
the software.
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MB91460N series
17.3 Configuration
Figure 17.3-1 Configuration Diagram of the Timebase Timer
Interval time
Timebase time selection
TBCR: bit 5, bit 3
TBC2 to TBC0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
φ × 2 11
φ × 2 12
φ × 2 13
φ × 2 22
φ × 2 23
φ × 2 24
φ × 2 25
φ × 2 26
Timebase Timer control
TBIE
0
1
TBCR: bit 6
Interrupt request disable
Interrupt request enable
0
Edge detection
Selector
TBIF
TBCR: bit 7
0
1
No interrupt
With interrupt
WRITE; 0: Flag clear
1
Timebase
Timer interrupt
(#140)
Timebase counter
(26-bit counter)
Base clock φ
0
1
2
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
21
22
23
24
2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26
Timer clear
CTBR
Clears the counter
after writing "A5H"
and then "5AH".
Figure 17.3-2 List of Registers
Timebase timer
Address
000482H
7
TBIF
6
TBIE
5
TBC2
4
TBC1
3
TBC0
2
---
000483H
D7
D6
D5
D4
D3
D2
D1
D0
CTBR
(Timebase counter clear register)
00045FH
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0
ICR62
(Interrupt level register)
Address
0FFDCCH
186
Bit
1
0
SYNCR SYNCS TBCR
32Bits
FUJITSU MICROELECTRONICS LIMITED
(Timebase counter control register)
(Interrupt vector #140)
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Chapter 17 Timebase Timer
17.4
MB91460N series
17.4 Register
17.4.1 TBCR: Timebase Timer Control Register
This register is used to set timebase timer interrupt control, reset/ standby operation option etc.
Note: Refer also to "Chapter 10 Standby (Page No.107)".
• TBCR: Address 000482H (Access: Byte)
7
TBIF
6
TBIE
5
TBC2
4
TBC1
3
TBC0
2
---
1
SYNCR
0
SYNCS
0
0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R/W
R/W
RX/WX
RX/WX
R/W
bit
Initial value
(INITX pin input,
watchdog reset)
Initial value
(the software reset)
Attribute
(Refer to "Meaning of Bit Attribute Symbols (Page No.11)" for the attributes.)
• Bit7: Timebase timer interrupt flag
Operation
TBIF
Read
With no interrupt
Write
Flag is cleared
With interrupt
(The interval time set by the timebase timer
has elapsed)
Writing does not affect operation
0
1
• An interrupt request is generated if the timebase timer interrupt request enable bit is "1", and if the
timebase timer interrupt flag is "1".
• Bit6: Timebase timer interrupt request enable
TBIE
0
1
Operation
Disabling the timebase timer interrupt request
Enabling the timebase timer interrupt request
• Bit5 to bit3: Selecting the timebase timer interval time
TBC2 to TBC0
Interval time
Example
(32.0MHz, base clock)
000B
φ × 211
64.0μs
001B
φ×
128μs
010B
212
φ×2
13
256μs
011B
φ×2
22
131ms
100B
φ×2
23
262ms
101B
φ × 224
524ms
110B
φ × 225
1048ms
111B
φ×
2097ms
226
• Be sure to set the interval time before an interrupt.
(Oscillation stability wait time used when returning to STOP caused by an interrupt)
• Bit2: Reserved bit
Writing does not affect the operation. The read value is indefinite.
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• Bit1: Enabling the synchronous reset operation
SYNCR
0
1
Operation
Asynchronous reset operation
Synchronous reset operation enable
• Ordinary operation reset: Immediately resets the operation initialization when the operation initialization
reset (RST) request is generated.
Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped.
Refer to "9.8.2 Synchronous Reset Operation" for details.
• Bit0: Synchronous standby operation enable
SYNCS
0
1
Operation
Asynchronous reset operation (Not permitted on this model).
Enable synchronous standby operation (always set this before changing to a standby mode).
Refer to "10.4.2 TBCR: Timebase timer control register" for details of synchronous standby operation.
17.4.2 CTBR: Timebase Counter Clear Register
This register is used to initialize the timebase counter.
• CTBR: Address 000483H (Access: Byte)
7
D7
X
RX/W
6
D6
X
RX/W
5
D5
X
RX/W
4
D4
X
RX/W
3
D3
X
RX/W
2
D2
X
RX/W
1
D1
X
RX/W
0
D0
X
RX/W
bit
Initial value
Attribute
(Refer to "Meaning of Bit Attribute Symbols (Page No.11)" for the attributes)
• Continuously writing "A5H", "5AH" in the timebase counter clear register clears the timebase counter
immediately after writing "5AH". (All bits are "0")
There is no time restrictions between "A5H" and "5AH", but if "A5H" is written followed by the one other than
"5AH", it must be written "A5H" again. If not, the timebase counter cannot be cleared even if "5AH" is written.
• The read value is indefinite.
• Clearing the timebase counter using the timebase counter clear register temporarily modifies the relevant
items shown below.
• Oscillation stability wait interval
• Watchdog timer period
• Timebase timer period
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17.5 Operation
Timebase timer operation is described.
17.5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)
Figure 17.5-1 Example for Timebase Timer Interrupt (Main PLL Lock Wait)
Main PLL lock wait
by the timebase timer
(8)
(5)
Example of
the Main PLL
oscillation
600 μs or more
(1)
(1)
2 11
Timebase
counter
count
(4)
Time
000H
(3)
““A5”
A5” “5A”
”
Clears the
(CTBR)
timebase counter
Main PLL enable (PLL1EN)
(5)
Timebase timer interrupt
request enable (PLL1EN)
(7)
Timebase timer interrupt flag
(PLL1EN)
(2)
( Main PLL value
setting/switching
(PLLDIVM[3:0],
PLLDIVN[5:0])
(6)
(9)
“1111B” “111111B”
(10B)
Clock switching (CLKS[1:0]) “00
“00B”
Operation with the 2-dividing main clock
“10
“10B””
Operation with the PLL clock
(1) Selecting the interval value in the timebase timer
(2) Selecting the Main PLL value (Setting / Switching)
(3) Writing data in the timebase counter clear register in the order of "A5H" and "5AH"
(4) Writing "5AH" clears the timebase counter and causes the count to start from"0"
(5) Enables the Main PLL to operate
(6) Clears the timebase timer interrupt flag using the software
(7) Setting the timebase timer interrupt request enable bit to "1"
(8) The Main PLL locks
(9) A timebase timer interrupt occurs when the timebase timer interval time has elapsed
(10) Setting the Main PLL to the operation clock
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17.6 Setting
Table 17.6-1 Setting Required for the Timebase Timer
Setting
Setting register
Timebase timer control register
control register (TBCR)
Timebase counter clear register
(CTBR)
Setting the interval time
Timebase counter clear
Setting
method*
Refer to 17.7.1
Refer to 17.7.5
*: Refer to the number for more information on the setting method.
Table 17.6-2 Setting Required for Interrupting the Timebase Timer
Setting
Setting register
Setting the timebase timer interrupt vector and
interrupt level
Setting the Main clock oscillation stability wait timer interrupt
Interrupt request clear
Interrupt request enable
Setting
method*
Refer to "Chapter 21 Interrupt
Control (Page No.219)"
Refer to 17.7.6
Timebase timer control register
control register (TBCR)
Refer to 17.7.7
*: Refer to the number for more information on the setting method.
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17.7 Q & A
17.7.1 What are the types of interval time used in the timebase timer (and the timebase
counter used by the timebase timer) and how to select them?
There are eight types of interval time, and they are set using the interval selection bit (TBCR:TBC[2:0]).
Timebase timer
Interval time
Interval selection bit
(TBC[2:0])
Example Interval time
φ =2MHz
φ = 32MHz
How to select φ × 211
Set the value to "000B"
1.024ms
64μs
12
Set the value to "001B"
2.048ms
128μs
13
Set the value to "010B"
4.096ms
256μs
How to select φ × 222
Set the value to "011B"
2.097s
131ms
How to select φ × 223
Set the value to "100B"
4.194s
262ms
How to select φ × 224
Set the value to "101B"
8.388s
524ms
How to select φ × 225
Set the value to "110B"
16.77s
1.04s
How to select φ × 226
Set the value to "111B"
33.55s
2.09s
How to select φ × 2
How to select φ × 2
φ: This is the base clock. (Refer to "Chapter 12 Clock Control (Page No.129)".)
17.7.2 What Is the count clock of the timebase counter?
The count clock is a base clock. Refer to "Chapter 12 Clock Control (Page No.129)".
17.7.3 How to operate the timebase timer
The timebase timer is always operating. (Setting is unnecessary.)
However, to use interval interrupt, interrupt setting is required.
17.7.4 How is the timebase timer (=timebase counter) operation stopped?
It cannot be stopped.
17.7.5 How is the timebase counter (=timebase timer) cleared?
If {A5H} and {5AH} is written successively in the timebase counter clear register CTBR, the timebase counter is
cleared immediately after {5AH}. (All bits are "0".)
However, if the timebase counter is cleared, the watchdog timer is affected. (Refer to "17.8 Caution (Page
No.193)")
17.7.6 How about the interrupt-associated registers?
Setting timebase timer’s interrupt vector and interrupt level
The relationship between the interrupt level and vector is shown in the following table.
Refer to "Chapter 21 Interrupt Control (Page No.219)" for more information on the interrupt level and interrupt
vector.
Interrupt vector (default)
#140
Address: 0FFDCCH
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR62)
Address: 00047EH
The interrupt flag (TBCR:TBIF) cannot automatically be cleared. As a result, clear it by the software before
returning from an interrupt service. (Write "0" in the interrupt flag (TBIF).)
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17.7.7 What are the interrupt types?
One type of interrupt is available, and an interrupt is generated when the interval time that is set using the
interval selection bit (TBCR:TBC[2:0]) has elapsed. (Selection is unnecessary.)
17.7.8 How is an interrupt enabled?
Interrupt request enable bit and interrupt flag
To enable the interrupt request the interrupt request enable bit is used (TBCR:TBIE).
Interrupt disable
Interrupt enable
Interrupt request enable bit (TBIE)
Set the value to "0"
Set the value to "1"
Clearing the interrupt request is performed using the interrupt flag (TBCR:TBIF).
Interrupt flag clear
192
Interrupt flag (TBIF)
Write "0"
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17.8 Caution
• The Main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply.
We recommend that this Main PLL lock wait time be acquired using the timebase interrupt.
Because the lock waiting time of PLL is about 600μs, it is necessary to set PLL lock wait time in 600μs or
more and to set it to the value.
• Regarding the interval setting
• When modifying the timebase timer interval time, set the interrupt request enable bit (TBIE) to "0" in
advance to disable an interrupt.
• The timebase counter is always counting. Clear the timebase counter before enabling an interrupt to
acquire an accurate interval interrupt time using the timebase timer.
(If not, an interrupt request may be generated immediately after an interrupt request enable.)
• About clearing the timebase counter using a program
• If there is data written in the timebase counter clear register CTBR in the order of "A5H" and "5AH" the
timebase counter is cleared immediately after writing "5AH". (All bits are "0".)
• Although there are no restrictions on the write timings for "A5H" and "5AH" writing "A5H" followed by a one
other than "5AH" the clearing operation is not performed if "A5H" is not written again even if "5AH" is
written.
• If the timebase counter is cleared, the reset signal to the watchdog is generated with a delay once.
• About clearing the timebase counter by the hardware
The timebase counter is cleared by the STOP state and the setting initialization reset (INITX pin input,
watchdog reset). (All bits are "0".)
• In the STOP state
When returning to the interrupt from a STOP, the timebase counter is used to acquire the clock oscillation
stability wait time. As a result, there is a possibility to unintentionally generate timebase timer’s interval
interrupt. Therefore, disable the timebase timer interrupt not to use the timebase timer before the STOP is
set.
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Chapter 18 Software Watchdog Timer
18.1 Overview
The software watchdog timer consists of a selector that uses the output from the 26-bit Timebase counter
(Chapter 16 Timebase Counter (Page No.171)) and a one-bit counter.
When delayed operation reset (interval watchdog reset) is not disabled due to a problem such as program
runaway, the watchdog timer generates a watchdog reset initialization reset).
Figure 18.1-1 Timebase Counter (overview diagram)
Temporary Stop Causes
Timebase counter
Base clock φ
Watchdog Time
Selection
Watchdog reset
Timebase Time
Selection
Timebase Timer
Interrupt
Oscillation Stabilization
Wait Time Selection
Oscillation Stabilization
Wait control signal
26-bit up counter
This diagram is just an overview. Each part is explained in detail in the respective chapter.
The timebase counter, timebase timer, and watchdog timer are collectively called the watchdog control unit.
Figure 18.1-2 Timebase Counter used to generate the Watchdog Reset
writing “A5H” or “5AH”
to WPR
Temporary
Stop Causes
clear
Selector
Timebase counter
Base clock φ
1-bit
counter
Watchdog
Detection Control
Watchdog
Reset
26-bit up counter
Watchdog Time Selection
18.2 Features
■ Watchdog timer
• Type
•
•
•
•
: Generates the watchdog reset (INIT) with the overflow from one-bit counter
(See "RSRR: Reset Cause Register" on P. 95)
Quantity : 1
Count clock (interval time): Bit output from the timebase timer
4 types
φ × 220, φ × 222, φ × 224, φ × 226
(Can be set only once after the reset (RST).)
Clearing 1-bit counter:
Successively writes "A5H" or "5AH" to watchdog reset generation delay register WPR by the software. This
operation does not influence the Timebase counter.
Operation start/stop: This timer starts to operate once it writes data to the watchdog control register RSRR
for the first time after the reset (RST). This timer stops by reset (RST, INIT, SWWD reset, HWWD reset).
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18.3 Configuration
Figure 18.3-1 Configuration Diagram of the Watchdog Timer
Temporary stop causes:
-SLEEP state
-STOP state
-Oscillation stability
wait RUN
Timebase counter
(26-bit up counter)
0
Base clock φ
3
13 14 15 16 17 18 19 20 21 22 23 24 25
21 22 23 24
1
2
214 215 216 217 218 219 220 221 222 223 224 225 226
Watchdog time selection
For watchdog detection
WT1,WT0
0
0
0
1
1
0
1
1
CT BR
Clears the counter
after writing “A5H”
and then “5AH”.
WIF
Edge detection
Selector
Timer clear
1-bit
counter
RSRR: bit2, bit1
φ × 220
φ × 222
φ × 224
φ × 226
Watchdog reset
OSCR: bit 7
0 Without interrupt request
1 With interrupt request
WRITE; 0: Flag clear
To the reset
circuit
WPR
Clears the counter
after writing “A5H”
and then “5AH”.
Watchdog
detection control
Figure 18.3-2 List of Registers
Watchdog timer
Address
000480H
7
INIT
6
−
5
WDOG
4
−
3
SRST
2
LINIT
1
WT1
0
WT0
000485H
D7
D6
D5
D4
D3
D2
D1
D0
WPR (Watchdog reset generation delay register)
000483H
D7
D6
D5
D4
D3
D2
D1
D0
CTBR (Time-base counter clear register)
196
Bit
RSRR (Watchdog timer control register)
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18.4
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18.4 Register
18.4.1 RSRR: Watchdog Timer Control Register
This register is used to set watchdog timer periods, and execute the startup control.
(This register also functions as the reset cause register that stores previously generated reset causes.)
Note: Refer also to "Chapter 9 Reset (Page No.93)".
• RSRR: Address 000480H (Access: Byte, Half-word)
7
INIT
6
-
5
WDOG
4
-
3
SRST
2
LINIT
1
WT1
0
WT0
1
0
0
0
0
0
0
0
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
0
0
R/W
0
0
R/W
bit
Initial value
(INITX pin input)
Initial value (Watchdog reset)
Initial value (Software reset)
Attribute
(For the attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
The watchdog timer starts once it writes the watchdog timer control register.
• Bit7: Initialization reset occurred flag
Indicates whether a reset (INIT) was triggered by INITX pin input.
INIT
0
1
Meaning
No INIT has been triggered by the INITX pin input.
INIT has been triggered by the INITX pin input.
The initialization reset occurred flag (INIT) is cleared to "0" after reading.
• Bit6: Reserved Bit
• Bit5: Watchdog reset occurred flag
Indicates whether a reset (INIT) was triggered by the watchdog timer.
WDOG
0
1
Meaning
No INIT has been triggered by the watchdog timer.
INIT has been triggered by the watchdog timer.
The watchdog reset occurred flag (WDOG) is cleared to "0" after reading.
• Bit4: Reserved Bit
• Bit3: Software reset occurred flag
Indicates whether a software reset has been triggered by writing to the software reset bit (STCR:SRST).
SRST
0
1
Meaning
No RST has been triggered by a software reset.
RST has been triggered by a software reset.
The software reset occurred flag (SRST) is cleared to "0" after reading.
• Bit2: Low voltage reset occurred flag
Indicates whether a reset (INIT) was triggered by the low voltage detection.
LINIT
0
1
Meaning
No INIT has been triggered by the low voltage detection.
INIT has been triggered by the low voltage detection.
The low voltage reset occurred flag (LINIT) is cleared to "0" after reading.
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• Bit1, bit0: Watchdog interval time selection
WT1
WT0
The minimum writing interval required for WPR
so that the watchdog timer may not be reset
Interval between the time when WPR is last
written with 5AH and when the watchdog is
reset
(Interval time of the timebase counter
selection bit)
(Watchdog interval time)
0
φ × 220 (Initial value)
φ × 220 to φ × 221
0
1
φ×
222
φ × 222 to φ × 223
1
0
φ × 224
φ × 224 to φ × 225
1
1
φ × 226
φ × 226 to φ × 227
0
(φ: Base clock)
• A total of four watchdog interval times are available to be selected.
• Only the data firstly written after a reset is valid, and the other data sets are invalid.
• Watchdog interval time selection bit can be read to know the set value.
Note: For more information on bits used for timers other than the watchdog timer, refer to "Chapter 9 Reset
(Page No.93)".
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18.4.2 WPR: Watchdog Reset Generation Postponement Register
This register is used to postpone the generation of watchdog reset.
• WPR: Address 000485H (Access: Byte)
7
D7
X
X
RX,W
6
D6
X
X
RX,W
5
D5
X
X
RX,W
4
D4
X
X
RX,W
3
D3
X
X
RX,W
2
D2
X
X
RX,W
1
D1
X
X
RX,W
0
D0
X
X
RX,W
bit
Initial value (INIT)
Initial value (RST)
Attribute
(Refer to "Meaning of Bit Attribute Symbols (Page No.11)" for the attributes.)
• If "A5H" and "5AH" are successively written in the watchdog reset generation postponement register and
immediately after writing "5AH" the 1-bit counter used to detect the watchdog is set to "0" to postpone the
generation of a watchdog reset.
Although there are no restrictions on the write timings for "A5H" and "5AH", if "A5H" and a value other
than "5AH" are written, "A5H" must be written again. If not, writing "5AH" does not set the 1-bit counter to
"0".
• The read value is indefinite.
• Both "A5H" and "5AH" must be written within the specified interval as shown below to prevent the
watchdog reset from being generated. The intervals are shown in the following table according to the
watchdog interval time selection bit (RSRR:WT[1:0]).
WT1
WT0
Minimum interval required for writing data in WPR
0
0
Within φ × 220 (Initial value)
0
1
Within φ × 222
1
0
Within φ × 224
1
1
Within φ × 226
18.4.3 CTBR: Timebase Counter Clear Register
This register is used to initialize the timebase counter.
• CTBR: Address 000483H (Access: Byte)
For more information, refer to "Chapter 17 Timebase Timer (Page No.185)".
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18.5 Operation
This section describes the watchdog operation.
18.5.1 Watchdog (Detecting Runaway)
Figure 18.5-1 Example of Watchdog operation (Detecting Runaway)
Count value of
the timer counter
(11)
(8)
(1)
(6)
Interval period
selection
(3)
(3)
(8)
(6)
Bit output of
the timer counter
(Bits 19, 21, 23 or 25)
Watchdog timer
Reading from the RSRR
register
Periodically writing
“A5H” and “5AH” in
the WPR register
Watchdog
startup
(12) Runaway
(3) (4)
(7) (8)
(5) (6)
detection
(2)
(4)
(5)
Clear by
software
Clear by
software
(7)
Clear by
software
WDOG bit
(10)
With
no clear
Setting initialization reset
(INIT)
(13)
Normal operation
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(12)
(9) Runaway
Reset
Setting interval time
Watchdog startup (Watchdog timer clear)
Interval signal output from the timebase counter. The watchdog timer counts.
Within the interval time, by software periodic writing to the WPR register with "A5H" and "5AH" has been
performed. The watchdog timer clears.
Within the interval time, by software periodic writing to the WPR register with "A5H" and "5AH" has been
performed. The watchdog timer clears.
Interval signal output from the timebase counter. The watchdog timer counts.
Within the interval time, by software periodic writing to the WPR register with "A5H" and "5AH" has been
performed. Watchdog timer clears.
Interval signal output from the timebase counter. The watchdog timer counts.
MCU runs away (the runaway of MCU is assumed).
Within interval time, by software writing to the WPR register with "A5H" and "5AH" has not been performed.
(11) Interval signal output from the timebase counter. The watchdog timer counts.
(12) Runaway is detected, WDOG flag has been changed to "1".
(13) Watchdog reset (INIT) has been generated.
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18.5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period
The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control
register) after the reset (RST). At this time, Bits 1 and 0 (WT1 and WT0 bits) set the watchdog timer interval
time. Only the setting for the interval time executed first after the reset is valid, and the other settings executed
at a later time are invalid.
18.5.3 Postponing the Generation of a Watchdog Reset
Once watchdog timer is started, it is necessary that the WPR (watchdog reset generation postponement
register) should be written periodically with "A5H" and "5AH" in this order by software. This operation is used to
set the 1-bit counter for detecting the watchdog reset to "0".
18.5.4 Generation of the watchdog reset
The 1-bit counter for detecting the watchdog reset is set at the falling edge of the output of the timebase
counter where an interval is set. In addition, if the second falling edge is detected while the 1-bit counter is set,
the request for the setting initialization reset (INIT) is generated as the watchdog reset.
18.5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)
The watchdog timer resets the 1-bit counter used for detecting the watchdog reset to "0" as initialization while
CPU program operation is stopped. In this state, the generation of the watchdog reset is postponed. The
states where programs stop running are concretely shown below.
• SLEEP state
• STOP state
• Oscillation stability wait RUN
• Is in break when using the embedded debug support unit (only if EDSU and EMMODE is enabled)
In addition, clearing the timebase counter simultaneously initializes the 1-bit counter used for detecting the
watchdog reset, thus causing the reset timing of the watchdog to be postponed.
18.5.6 Stopping the Watchdog Timer
Once the watchdog timer is started, the watchdog timer operation cannot be stopped until the initialization
reset (RST) is generated.
The watchdog timer is stopped under these states shown below where the operation initialization reset (RST)
is generated until it is restarted by software.
• Operation initialization reset (RST)
• Setting initialization reset (INIT)
• Oscillation stabilization wait reset
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18.6 Setting
Table 18.6-1 Setting Required for Using the Watchdog Timer
Setting
Interval time setting
Startup of the watchdog
Setting register
Watchdog timer control register (RSRR)
Setting method
Refer to 18.7.1
Refer to 18.7.2
*: Refer to the number for more information on the setting method.
Table 18.6-2 Setting Required for Delaying the Generation of the Watchdog
Setting
Setting required for delay the generation of the
watchdog reset
Setting register
Watchdog reset generation delay register
(WPR)
Setting method
Refer to 18.7.3
*: Refer to the number for more information on the setting method.
Table 18.6-3 Setting Required for Checking the Generation of the Watchdog
Setting
Watchdog generation check
Setting register
Watchdog timer control register (RSRR)
Setting method
Refer to 18.7.5
*: Refer to the number for more information on the setting method.
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18.7 Q & A
18.7.1 What are the types of watchdog interval time and how are they selected?
There are four types of the interval period, and they are set using the interval selection bit (RSRR:WT[1:0]).
To select φ × 220
Interval
Selection bit
(WT[1:0])
Set the value to
"00B"
To select φ × 222
Set the value to
"01B"
52.4 ms
2.097 s
To select φ × 224
Set the value to
"10B"
209.7 ms
8.388 s
To select φ × 226
Set the value to
"11B"
838.8 ms
33.554 s
Watchdog
Interval time
(Notes)
Example) Interval Time
φ =80.0MHz
φ = 2.00MHz
13.1 ms
0.524 s
• φ: Base clock. (Refer to "Chapter 12 Clock Control (Page No.129)".)
• Only the data sets first written after the reset (INITX pin input, watchdog reset, software reset) are
valid, and the other data sets are invalid.
18.7.2 How is the watchdog operation started (set to valid)?
Writing data in the watchdog timer control register RSRR causes the watchdog timer to be started (set
RSRR:WT to valid data at the first write access).
18.7.3 How to check that the watchdog reset has been generated
If the watchdog reset flag (RSRR:WDOG) is set to "1", the watchdog reset has been generated.
18.7.4 How is the watchdog stopped?
The watchdog cannot be stopped by the software.
The watchdog can be stopped with the reset (INIT, RST, HWWD reset, SWWD reset).
18.7.5 How to clear the watchdog timer (1-bit counter)
Successively writing "A5H" and "5AH" in the watchdog reset generation postponement register WPR causes
the 1-bit counter used for detecting the watchdog to be cleared immediately after writing "5AH". In this state,
the reset timing of the watchdog can be postponed.
In addition, if the timebase timer is cleared, the 1-bit counter used for detecting the watchdog is simultaneously
reset.
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MB91460N series
18.8 Caution
• Although the watchdog interval time corresponds to the one twice as long as the watchdog 1-bit counter, the
watchdog timer clear operation only clears the 1-bit counter used for detecting the watchdog. As a result, the
time margin to clear the watchdog timer is different from the interval time.
Table 18.8-1 Watchdog interval time selection
Time margin to clear the watchdog timer
Interval time during which the watchdog
reset is generated
00B
φ × 220 (Initial value)
φ × 220 to φ × 221
01B
φ × 222
φ × 222 to φ × 223
10B
φ×2
24
φ × 224 to φ × 225
11B
φ × 226
φ × 226 to φ × 227
WT1, WT0
Figure 18.8-1 One bit counter reset
(1) without CLEAR
Timebase Counter
...
n
2 -1
0
...
1
n
2 -1
0
...
1
n
2 -1
0
...
1
n
2 -1
0
clock for 1-bit counter
1-bit counter
0
0
1
1
0
overflow 1-bit counter
Reset
(2) with CLEAR
watchdog CLEAR
1-bit counter
0
1
0
1
0
1
overflow 1-bit counter
Reset
• The watchdog timer is started once data is written in the watchdog timer control register.
• The watchdog timer control register is also the reset cause register and the status (INIT, WDOG, SRST and
LINIT) is set to "0" when it is read.
• The watchdog reset holds the oscillation stability wait time.
(Refer to "Chapter 16 Timebase Counter (Page No.171)".)
• When watchdog reset occurs in Main-RUN, and the Main clock is running, there will be no oscillation
stabilization time.
• Refer to "Chapter 17 Timebase Timer (Page No.185)" for the method of clearing the timebase counter that is the
count source for the watchdog timer.
• Clearing the timebase counter causes the watchdog reset timing to be postponed once.
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Chapter 19 Hardware Watchdog Timer
19.1
MB91460N series
Chapter 19 Hardware Watchdog Timer
19.1 Overview
The hardware watchdog timer (CR oscillation based (CLKRC 100kHz)) provides a system reset
if an internal watchdog timer is not cleared within the postponement duration.
● Hardware watchdog timer
This watchdog timer starts counting after the setting initialization reset (INIT) automatically. Clearing the
counter in the postponement duration is necessary to continue running an application. Otherwise if the counter
is not cleared within the postponement duration, e.g. due to infinite loop in the application, this module
provides a reset signal (initialization reset, INIT). The width of this signal is normally 20μs (in general,
equivalent of 2 cycles of the CR clock at 100kHz).
If the CPU is in a standby mode as described below, this watchdog timer stops:
• SLEEP state: the CPU stops, the peripherals run.
• STOP state: the CPU and the peripherals stop.
• STOP state but the RTC module and the oscillator run.
If one of the below condition occurs, the watchdog counter is cleared:
• Writing "0" to CL bit in the HWWD register
• Initialization Reset (INIT)
• Operational Reset (RST)
• Oscillation stops
• Transition to the SLEEP state, STOP state or "STOP with RTC running" state
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19.2
MB91460N series
19.2 Configuration
Hardware watchdog timer consists of two sub-blocks:
• Watchdog timer
• Timer control and status register
● Block diagram of the hardware watchdog timer
Figure 19.2-1 Block Diagram of hardware watchdog timer
Internal Bus
reserved reserved reserved reserved reserved reserved
ED1
Selector
ED0
Reset signal
CLKRC 100kHz
19-bit counter
clear
reserved reserved reserved reserved
CL
reserved reserved
CPUF
Internal Bus
Watchdog timer
This is a timer to supervise CPU operation. The counter needs to be cleared periodically after releasing the
reset.
Hardware watchdog timer control status register
This register has the reset flag and clear bit for the counter.
Occurring of the watchdog reset
If the counter has not been cleared periodically, this module provides a setting initialization reset (INIT). After
the watchdog reset the normal system reset procedure starts. For more details about this procedure, see the
corresponding section in the device state description.
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19.3
MB91460N series
19.3 Register
19.3.1 Hardware watchdog timer control and status register
Hardware watchdog timer control status register (with reset flag and clear bit).
• HWWD: Address 0004C7H (Access: Byte)
7
-
6
-
5
-
4
-
3
CL
2
-
1
-
0
CPUF
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
X
R/W0
R/W0
R/W0
R/W1
W
R/W0
R/W0
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit5: Reserved bits.
Always write "0" to these bits.
• Bit4: Reserved bit.
Always write "1" to this bit.
• Bit3: CL (counter clear).
CL
0
1
Function
By writing "0" the watchdog timer is cleared
Writing "1" has no effect
This bit is write only, it is always read as "1".
• Bit2, bit1: Reserved bits.
Always write "0" to these bits.
• Bit0: CPUF (CPU reset Flag).
CPUF
0
1
Function
Watchdog reset not triggered
Watchdog reset triggered (overflow of watchdog timer occurred)
This bit is initialized by external reset input (INITX), but not by internal reset.
Writing "0" clears this bit, writing "1" has no effect.
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19.3.2 Hardware watchdog timer duration register
Hardware watchdog timer duration register (elongation of the trigger duration).
• HWWDE: Address 0004C6H (Access: Byte)
7
-
6
-
5
-
4
-
3
-
2
-
1
ED1
0
ED0
-
-
-
-
-
-
0
0
-
-
-
-
-
-
0
0
RX/W0
RX/W0
RX/W0
RX/W0
RX/W0
RX/W0
R/W
R/W
bit
Initial value (INITX pin
input, watchdog reset)
Initial value
(Software reset)
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit7 to bit2: Reserved bits.
Always write "0" to these bits.
• Bit1, bit0: ED1, ED0 (Elongate watchdog duration).
ED1, ED0
00B
Function
The watchdog period is
216
CLKRC cycles [initial setting]
CLKRC cycles
CLKRC cycles
The watchdog period is
217
10B
The watchdog period is
218
11B
The watchdog period is 219 CLKRC cycles
01B
Note:
MB91V460A cannot change the watchdog period.
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19.4
MB91460N series
19.4 Functions
If the watchdog timer is not cleared periodically, a setting initialization reset (INIT) occurs. In this case the
value of registers in CPU is not guaranteed.
● Function of the hardware watchdog timer
After releasing INITX the hardware watchdog timer starts immediately without stabilization time. If the timer is
not cleared periodically, setting initialization (INIT) reset occurs.
● Period of the hardware watchdog timer
The timer width is 19-bit. Since the CR oscillator is used as clock source of the hardware watchdog timer, the
duration of the timer deviates with the CR oscillator accuracy:
ED1, 0
CR oscillation cycle (µs)
Watchdog term (ms)
CM44-10149-1E
00B
01B
10B
11B
Min.
5
327.68
655.36
1310.72
2621.44
Typ.
10
655.36
1310.72
2621.44
5242.88
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Max.
20
1310.72
2621.44
5242.88
10485.76
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Chapter 19 Hardware Watchdog Timer
19.5
MB91460N series
19.5 Caution
● Software disabling is not possible
The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop the counting.
● Postponement of reset
In order to postpone the watchdog reset, the clearing of the watchdog timer is necessary. Whenever the CL bit
of register is set to "0" (there is no minimum writing limitation), the timer is cleared and the occurrence of reset
is postponed. Just writing to the register without setting CL to "0" does not clear the timer.
● Timer stop and clear
In modes where the CPU does not work (SLEEP state, STOP state or STOP with RTC active state), the timer
is cleared first then the counting is stopped.
● During DMA transfer
During DMA transfer between D-bus modules, the writing "0" to CL bit is not possible. Thus, if the transfer time
is more than 328ms (calculated from the fastest frequency of the CR oscillator as minimum period), a reset
occurs.
● CLKRC frequency
You can change the CR clock frequency to 2 MHz. However, the watchdog timer always operates at the
frequency of 100kHz (10μs).
● Difference between watchdog reset and Power-on reset
In case of a clock supervisor reset (the device is running on CLKRC then), it is necessary to have an external
reset or a power-on reset to start the device on CLKMAIN again. A watchdog reset does not have this effect.
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Chapter 20 Main Oscillation Stabilization Timer
20.1
MB91460N series
Chapter 20 Main Oscillation Stabilization Timer
20.1 Overview
The Main clock oscillation stabilization timer is a 23-bit counter that counts the CLKMAIN. This timer does not
affect the selection of clock source operated by MCU/dividing setting.
This is equipped as a timer for main clock oscillation stabilization when the main clock oscillation has halted
during the sub clock operating. However, you cannot use this function because MB91460N series does not
equip the sub clock. Even so, this timer is suitable for the interval time or the system clock of real time OS.
Figure 20.1-1 Counter used to generate Main clock oscillation stabilization wait interrupt
CLKMAIN
23-bit up counter
Main Clock oscillation stabilization wait time selection
Selector
Detection
Control
Main Clock
oscillation
stabilization
wait interrupt
(#143)
20.2 Features
•
•
•
•
•
•
•
•
Type
Quantity
Clock source
Interval time
: 23-bit Free-Run counter
:1
: Main clock (source oscillation) --- Period = 1/CLKMAIN
: 3 types
Period =212/CLKMAIN, 217/CLKMAIN, 223/CLKMAIN,
(1.0ms, 32.7ms, 2s / CLKMAIN 4MHz)
Cause of timer clear: (Software, overflow, reset (INIT))
Operation start/stop : Can be operated/stopped by the software.
Interrupt
: Main clock oscillation stability wait interrupt (Interval interrupt)
Count value
: Cannot read/write. (Clear only)
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MB91460N series
20.3 Configuration
Figure 20.3-1 Configuration Diagram of the Main clock oscillation stability wait time selection
Main clock oscillation stabilization wait timer
Main clock oscillation stability wait time selection
Selector
Detection Control
Interval time
0
0
1
1
WS1,0
0
1
0
1
0
1
Edge detection
Selector
Timer operation enable
WEN
OSCR: bit 2, bit 1
Setting disable
2 12 × CLKMAIN
2 17 × CLKMAIN
2 23 × CLKMAIN
OSCR: bit 5
Operation stop
Operation enable
WIE
0
1
OSCR: bit 6
Interrupt request disable
Interrupt request enable
0
WIF
OSCR: bit 7
Main clock
READ:
0
1
0
1
Without interrupt
With interrupt
WRITE:
Flag clear
1
Oscillation stability
wait interrupt (#143)
Not affected
23-bit Free-Run timer
CLKMAIN
0
1
2
3
4
5
6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
21
22
23
24
25
26
27
29
2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23
28
Timer clear
WCL
0
1
OSCR: bit 2
Does not affect the operation
Timer clear
Figure 20.3-2 List of Registers
Mainclock oscillation stability wait timer
Address
0004C8H
00047FH
Address
0FFDC0H
Bit
7
WIF
6
WIE
5
WEN
4
---
3
---
2
WS1
1
WS0
0
WCL
OSCRH (Wait control status for the main clock oscillation stability register)
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0
ICR63
(Interrupt level register)
32Bits
(Interrupt vector #143)
*Refer to Chapter "INTERRUPT CONTROL" for the IC register and the interrupt vector.
Note: Refer to "Chapter 21 Interrupt Control (Page No.219)" for the ICR register and the interrupt vector.
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20.4
MB91460N series
20.4 Register
20.4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer
This register is used to select the interval time, clear the timer, control the interrupt, control the timer such as
stop, and confirm the state of the timer.
• OSCRH: Address 0004C8H (Access: Byte)
7
WIF
6
WIE
5
WEN
4
–
3
–
2
WS1
1
WS0
0
WCL
0
0
0
X
X
0
0
1
X
X
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R/W
R/W
R1,W
RX/W0 RX/W0
bit
Initial value
(INITX pin input,
watchdog reset)
Initial value
(Software reset)
Attribute
(For the attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• Bit7: Timer interrupt flag
WIF
0
1
Read Operation
No interrupt
With interrupt
Write Operation
Clears interrupt flag
Writing does not affect operation
• The timer interrupt flag is set to "1" at the falling edge of the selected interval period output.
• Bit6: Interrupt request enable
WIE
0
1
Operation
Interrupt request disable
Interrupt request enable
• If the timer interrupt flag (WIF) is set to "1" while the interrupt request enable (WIE) is "1" an interrupt
request is immediately generated.
• Bit5: Timer operation enable
WEN
0
1
Operation
Stops timer operation
Enables timer operation
• Bit4, bit3: Reserved bit
Be sure to write "0". The read value is "0".
• Bit2, bit1: Interval period selection
WS1
0
WS0
0
Interval period (At 4MHz)
0
1
212/CLKMAIN (2.0ms)
1
0
217/CLKMAIN (65.4ms)
1
1
223/CLKMAIN (4.0s)
Setting prohibited
• The reset does not initialize. Be sure to set it after the startup.
• Bit0: Timer clear
WCL
0
1
Operation
Clears the Main clock oscillation stability wait timer
Writing does not affect operation
• The timer is also cleared by INITX pin input and watchdog reset.
(Refer to "20.8 Caution (Page No.218)".)
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20.5
MB91460N series
20.5 Operation
This section describes the Main clock oscillation stability wait timer operation.
20.5.1 Interval Interrupt
Figure 20.5-1 Example of generating an interval interrupt
H
H
H
(1) Selects the interval time (WS[1:0]). (In this example, 217/CLKMAIN is selected.)
(2) Clears the timer (WCL=0), clears flags (WIF=0), enables interrupt request (WIE=1), enables timer count (WEN=1)
by the software.
(3) The timer counts up using the Main clock (source oscillation).
(4) Generates interval interrupt at the selected interval time (Falling of the dividing 217).
(5) Processing caused by an interrupt (Software): Clears interrupt flag (WIF=0).
(6) Repeats Items (3) to (5)
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20.6
MB91460N series
20.6 Setting
Table 20.6-1 Settings Required for Using the Main Clock Oscillation Stability Wait Timer
Setting
Setting register
Setting interval time
Count clear
Counting operation start
Main clock oscillation stability wait
timer control register (OSCRH)
Setting
method*
20.7.1
20.7.4
20.7.3
*: Refer to the number for more information on the setting method.
Table 20.6-2 Settings Required for Enabling the Main Clock Oscillation Stability Wait Timer Interrupt
Setting
Sets the Main clock oscillation stability wait timer
interrupt vector and
Sets Free-Run timer interrupt level
Sets the Main clock oscillation stability wait timer interrupt
Clears interrupt flag
Enables interrupt request
Setting register
Setting
method*
Refer to "Chapter 21 Interrupt Control (Page No.219)".
20.7.5
The Main clock oscillation stability
wait timer control register (OSCRH)
20.7.7
*: Refer to the number for more information on the setting method.
Table 20.6-3 Settings Required for Stopping the Main Clock Oscillation Stability Wait Timer
Setting
Sets the Main clock oscillation stability wait timer stop
Setting register
Setting
method*
The Main clock oscillation stability
wait timer control register (OSCRH)
20.7.8
*: Refer to the number for more information on the setting method.
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20.7
MB91460N series
20.7 Q & A
20.7.1 What are the types of interval time (wait time) and how are they selected?
There are 3 types of interval time, and they are set with the interval selection bit (OSCRH:WS[0:1]).
Count period
Interval selection bit (WS[1:0])
Set the value to "01B"
Interval (Wait time) Example
At CLKMAIN = 4.00MHz
217
/CLKMAIN
Set the value to "10B"
32.7ms
to223
/CLKMAIN
Set the value to "11B"
2.0s
Interval time
To set the value to 212/CLKMAIN
To set the value to
To set the value
1.0ms
Note: Setting (WS[1:0]=00) is prohibited.
20.7.2 How to select the count clock
The count clock is the Main clock (source oscillation). (Cannot be selected.)
20.7.3 How is the Main clock oscillation stabilization wait timer count operation enabled/
disabled?
Sets with the timer operation enable bit (OSCRH:WEN).
Operation
To stop the Main clock oscillation stabilization wait timer
To start the Main clock oscillation stabilization wait timer
Timer operation enable bit (WEN)
Set the value to "0"
Set the value to "1"
20.7.4 How is the Main clock oscillation stabilization wait timer cleared?
The following methods are used to clear the Main clock oscillation stabilization wait timer.
• Sets with the clear bit (OSCRH:WCL).
Operation
To clear the Main clock oscillation stabilization wait timer
Clear bit (WCL)
Writes "1"
• Performs a reset.
Clears the Free-Run timer with the operation initialization reset (INITX pin input, watchdog reset).
(Value is held without being cleared even if a software reset is performed.)
• The overflow (Next of "7FFFFFH") of the Main clock oscillation stability wait timer causes the count value to
be reset to "000000 H".
20.7.5 What happens with the interrupt-associated registers?
Setting the interrupt vector and interrupt level of the Main clock oscillation stability wait timer
The relationship between the interrupt level and the interrupt vector is shown in the following table.
Refer to "Chapter 21 Interrupt Control (Page No.219)" for the interrupt level and interrupt vector.
Interrupt vector (Default)
#143
Address: 0FFDC0H
Interrupt level setting bit (ICR4 to ICR0)
Interrupt level register (ICR63)
Address: 00047FH
As the interrupt flag (OSCRH:WIF) is not automatically cleared, clear it before returning to interrupt processing
by the software. (Writes "0" in the WIF bit.)
20.7.6 What are the types of interrupt?
There is one type of interrupt called the Main clock oscillation stability wait timer interrupt.
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MB91460N series
(Selection is unnecessary.)
20.7.7 How is an interrupt enabled?
Interrupt request enable and interrupt flag
Setting the interrupt request enable is performed with the interrupt request enable bit (OSCRH:WIE).
Interrupt request disable
Interrupt request enable
Interrupt request enable bit (WIE)
Set the value to "0"
Set the value to "1"
Clearing an interrupt is performed with the interrupt flag (OSCRH:WIF).
Interrupt clear
Interrupt flag (WIF)
Writes "0"
20.7.8 How is the Main clock oscillation stability wait timer stopped counting?
Sets with the timer operation enable bit (OSCRH:WEN). Refer to 20.7.3.
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20.8
MB91460N series
20.8 Caution
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the
Main clock oscillation is unstable for the beginning immediately after the oscillation has started.
• If the Main clock oscillation stops, the Main clock oscillation stability wait interrupt (interval interrupt) is not
generated either because the Main clock oscillation stability wait timer stops. The Main clock oscillation
should be enabled for processing that uses the Main clock oscillation stability wait interrupt (interval
interrupt).
• The flag is set to "1" (flag setting preference) if the timer interrupt (WIF=1) and the writing operation where
"0" is written by software in the flag occur simultaneously.
• The Main clock oscillation stability wait timer is counted up with the Main clock. As a result, in the following
state, the counting of the timer used to stop the Main clock oscillation also stops.
• If the timer operation enable bit (OSCRH:WEN) is "0", the timer stops counting.
• If the Main clock is stopped in the STOP state (STCR:OSCD1=1), the timer stops counting from the
moment the STOP state is activated.
• If the interrupt request should be enabled (WIE=1) after the reset is released, and the interval time to be
modified, be sure to simultaneously set the interrupt flag (WIF) and the clear bit (WCL) to "0" beforehand.
• The timer interrupt flag (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and timer
clear bit (WCL) are initialized using the setting initialization reset (INITX pin input, watchdog reset).
• Be sure to set the interval selection bit (WS[1:0]) after startup (after setting initialization reset) by the
software.
• The Main clock oscillation stability wait timer control register should be initialized (to set the initial value) only
with the setting initialization reset (INITX pin input, watchdog reset) because the software reset does not
initialize the register and the current value is held.
• If the counter clear (WPCR:WCL=0) and the overflow for the selected bit occur simultaneously, the interrupt
flag (WIF) is not set to "1".
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Chapter 21 Interrupt Control
21.1
MB91460N series
Chapter 21 Interrupt Control
21.1 Overview
Interrupt control manages interrupt reception and arbitration.
Figure 21.1-1 Block diagram of Interrupt Control
Wakeup
NMI
Priority judging circuit
Interrupt level/
interrupt vector
generator
NMI processing
Interrupt requests
(peripheral function,
INT instruction,
delayed interrupt,
and REALOS)
Level
HLDREQ
cancel
request
Interrupt
priority
judging circuit
HALT
To the CPU
Vector number
21.2 Features
• Functions
• Detection of interrupt requests
• The interrupt priority is determined by interrupt level and interrupt number. The first criteria is the interrupt
level. For more than one interrupt with the same interrupt level at the same time, the interrupt number is
determinant.
• The interrupt level from the event with the highest priority is propagated to the CPU.
• The interrupt number from the event with the highest priority is propagated to the CPU.
• Request (to the CPU) to return from STOP state by a valid interrupt (Wakeup)
• Interrupt level
• Reserved for System: level 0 to 14
• NMI
: level 15 (Not available for MB91460N series.)
• Interrupt
: level 16 to 31
• Interrupt disable
: level 31
(As the interrupt level goes up, the interrupt priority goes down.)
• Number of interrupt triggers
• NMI
: 1 (Not available for MB91460N series.)
• Interrupt from peripheral functions: 128 (63 reserved for System)
• Delayed interrupt
:1
• Reserved for system (for REALOS): 2
• INT instruction
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: 111
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MB91460N series
21.3 Configuration
Figure 21.3-1 Configuration Diagram of Interrupt Control
Interrupt Controller
Priority judging circuit
The enabled interrupt request
Interrupt
request
enable bit
Interrupt
cause
NMI
Wakeup
NMIX
pin
NMI processing
Interrupt
request
flag
Interrupt priority
judging circuit
External interrupt ( 16)
Reload timer ( 4)
UART receive ( 4)
UART transmit ( 4)
A/D ( 2)
Real-time clock ( 1)
Main clock oscillation
stabilization timer ( 1)
Timebase timer ( 1)
Clock timer ( 1)
Up/down counter ( 2)
PPG ( 3)
Free-run Timer ( 2)
Input capture ( 2)
Output compare ( 4)
Delayed interrupt ( 1)
Level
Interrupt level
/interrupt
number
generator
HLDREQ
cancel
request
To the CPU
MHALTI
(Hold request cancel
to DMAC)
Number
Interrupt control register
ICR(4 to 0)
00000
Cannot be set.
01111
10000
Higher interrupt
11110
Lower interrupt
11111
Disable interrupts
Reserved for system [REALOS] ( 2)
INT instruction ( 176)
Figure 21.3-2 Configuration Diagram of Interrupt Control (CPU side)
RAM
Interrupt control (CPU side)
(PS, PC)
The inside of the CPU
Interrupt level mask register
00000
l
01111
System processing
I flag
Prioritization
10000
l
11110
Interrupt processing
11111
Initial level
Interrupt leve [ICRxx: ICR(4 to 0)]
Interrupt
control
circuit
SSP
Rewrite
ILM(4 to 0) ILM register in CPU
0
Disable
1
Enable
PS
PC
Table base register
TBR
Interrupt number (#)
Initial value: FFC00H
Interrupt number (#) × 4 + TBR
Address
220
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Vector table
(1k Bytes)
CM44-10149-1E
Chapter 21 Interrupt Control
21.4
MB91460N series
21.4 Registers
21.4.1 ICR00 to ICR63: Interrupt Control Register
The 64 ICR registers specify the interrupt level of each interrupt request.
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
#43
#44
#45
#46
#47
#48
#49
#50
#51
#52
#53
#54
#55
#56
#57
#58
#59
#60
#61
#62
#63
#64
#65
CM44-10149-1E
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
System reserved
System reserved
System reserved
System reserved
External Interrupt 12
External Interrupt 13
System reserved
System reserved
Reload Timer 0
Reload Timer 1
Reload Timer 2
Reload Timer 3
System reserved
System reserved
System reserved
Reload Timer 7
Free-run Timer 0
Free-run Timer 1
Free-run Timer 2
Free-run Timer 3
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
CAN 4
CAN 5
LIN-USART 0 RX
LIN-USART 0 TX
LIN-USART 1 RX
LIN-USART 1 TX
LIN-USART 2 RX
LIN-USART 2 TX
LIN-USART 3 RX
LIN-USART 3 TX
System reserved
Delayed Interrupt
System reserved (*1)
System reserved (*1)
Address: 0440H
(Access: Byte)
Address: 0441H
(Access: Byte)
Address: 0442H
(Access: Byte)
Address: 0443H
(Access: Byte)
Address: 0444H
(Access: Byte)
Address: 0445H
(Access: Byte)
Address: 0446H
(Access: Byte)
Address: 0447H
(Access: Byte)
Address: 0448H
(Access: Byte)
Address: 0449H
(Access: Byte)
Address: 044AH
(Access: Byte)
Address: 044BH
(Access: Byte)
Address: 044CH
(Access: Byte)
Address: 044DH
(Access: Byte)
Address: 044EH
(Access: Byte)
Address: 044FH
(Access: Byte)
Address: 0450H
(Access: Byte)
Address: 0451H
(Access: Byte)
Address: 0452H
(Access: Byte)
Address: 0453H
(Access: Byte)
Address: 0454H
(Access: Byte)
Address: 0455H
(Access: Byte)
Address: 0456H
(Access: Byte)
Address: 0457H (*2)
(Access: Byte)
Address: 0458H
(Access: Byte)
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21.4
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
ICR48
ICR49
ICR50
ICR51
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MB91460N series
#66
#67
#68
#69
#70
#71
#72
#73
#74
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
#75
#76
#77
#78
#79
#80
#81
#82
#83
#84
#85
#86
#87
#88
#89
#90
#91
#92
#93
#94
#95
#96
#97
#98
#99
#100
#101
#102
#103
#104
#105
#106
#107
#108
#109
#110
#111
#112
#113
#114
#115
#116
#117
#118
#119
I2C 3
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
Input Capture 0
Input Capture 1
Input Capture 2
Input Capture 3
System reserved
System reserved
System reserved
System reserved
Output Compare 0
Output Compare 1
Output Compare 2
Output Compare 3
System reserved
System reserved
System reserved
System reserved
System reserved
Phase Frequ. Modulator
System reserved
System reserved
Prog. Pulse Gen. 0
Prog. Pulse Gen. 1
Prog. Pulse Gen. 2
Prog. Pulse Gen. 3
Prog. Pulse Gen. 4
Prog. Pulse Gen. 5
Prog. Pulse Gen. 6
Prog. Pulse Gen. 7
I2C 2
Address: 0459H
(Access: Byte)
Address: 045AH
(Access: Byte)
Address: 045BH
(Access: Byte)
Address: 045CH
(Access: Byte)
Address: 045DH
(Access: Byte)
Address: 045EH
(Access: Byte)
Address: 045FH
(Access: Byte)
Address: 0460H
(Access: Byte)
Address: 0461H
(Access: Byte)
Address: 0462H
(Access: Byte)
Address: 0463H
(Access: Byte)
Address: 0464H
(Access: Byte)
Address: 0465H
(Access: Byte)
Address: 0466H
(Access: Byte)
Address: 0467H
(Access: Byte)
Address: 0468H
(Access: Byte)
Address: 0469H
(Access: Byte)
Address: 046AH
(Access: Byte)
Address: 046BH
(Access: Byte)
Address: 046CH
(Access: Byte)
Address: 046DH
(Access: Byte)
Address: 046EH
(Access: Byte)
Address: 046FH (*2)
(Access: Byte)
Address: 0470H
(Access: Byte)
Address: 0471H
(Access: Byte)
Address: 0472H
(Access: Byte)
Address: 0473H
(Access: Byte)
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CM44-10149-1E
Chapter 21 Interrupt Control
21.4
MB91460N series
ICR52
ICR53
ICR54
ICR55
ICR56
ICR57
ICR58
ICR59
ICR60
ICR61
ICR62
ICR63
#120
#121
#122
#123
#124
#125
#126
#127
#128
#129
#130
#131
#132
#133
#134
#135
#136
#137
#138
#139
#140
#141
#142
#143
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
Up/Down Counter 0
Up/Down Counter 1
System reserved
System reserved
Real Time Clock
Calibration Unit
A/D Converter 0
System reserved
System reserved
Low Voltage Detection
System reserved
Timebase Overflow
PLL Clock Gear
DMA Controller
Main OSC stability wait
Address: 0474H
(Access: Byte)
Address: 0475H
(Access: Byte)
Address: 0476H
(Access: Byte)
Address: 0477H
(Access: Byte)
Address: 0478H
(Access: Byte)
Address: 0479H
(Access: Byte)
Address: 047AH
(Access: Byte)
Address: 047BH
(Access: Byte)
Address: 047CH
(Access: Byte)
Address: 047DH
(Access: Byte)
Address: 047EH
(Access: Byte)
Address: 047FH
(Access: Byte)
(*1): It is used by REALOS.
(*2): ICR23 and ICR47 are exchangeable mutually by setting REALOS bits (address: 0C03H: IOS[0]).
ICR (interrupt control register) is a register contained in the interrupt controller, which sets an interrupt level for
each interrupt request. ICR supports the input of interrupt requests. ICR is also mapped to the I/O space.
• ICR00 to ICR63
7
–
6
–
5
–
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
–
–
–
1
1
1
1
1
RX/WX
RX/WX
RX/WX
R/WX
R/W
R/W
R/W
R/W
bit
Initial
value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• Bit7 to bit5: Undefined. Writing does not affect the operation. The read value is undefined.
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MB91460N series
• Bit4 to bit0: Interrupt level setting bits
ICR4 to ICR0 bits
0000B to 01110B
01111B
10000B
10001B
10010B
10011B
10100B
10101B
10110B
10111B
11000B
11001B
11010B
11011B
Interrupt level
0 to 14
15
16
17
18
19
20
21
22
23
24
25
26
27
11100B
28
11101B
11110B
11111B
29
30
31
Description
Reserved for system (cannot be set by user)
NMI
The highest level
(High)
(Low)
The lowest level
Disable interrupts
• The interrupt level setting bit specifies the interrupt level of the corresponding interrupt request.
• When the interrupt level set to the interrupt control register is the same as, or higher than the level mask
value set to the ILM register of the CPU (See "ILM: Interrupt Level Mask Register" on P. 70), the interrupt
request is masked by the CPU side.
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Chapter 21 Interrupt Control
21.4
MB91460N series
21.4.2 Interrupt Vector
Interrupt vector that corresponds to a vector number (#) with TBR register set to 0FFC00H (initial value):
#00
: Address
0FFFFCH
#01
: Address
0FFFF8H
~
~
~
#07
: Address
0FFFE0H
~
~
~
#63
: Address
0FFF00H
~
~
~
#143
: Address
0FFDC0H
32 bits
• Set the address of each interruption handling routine to the corresponding vector.
• The address of a vector = TBR (table vector register) + {3FCH - 4 × vector number (#)}
• EIT used by system (#0 to #14) (See "EIT Interrupt Level" on P. 77)
Interrupt number
#0
#1
#2 to #4
#5
#6
#7
#8
#9
#10
#11
#12
#13
#14
#15
CM44-10149-1E
Interrupt level (fixed)
0
1
–
5
6
7
8
9
10
11
12
13
14
15
interrupt event
Reset vector
Mode vector
Reserved for system
CPU Supervisor Mode
Memory Protection Exception
Coprocessor absence trap
Coprocessor error trap
INTE instruction
Instruction break exception
Operand break trap
Step trace trap
NMI request (TOOL)
Undefined-instruction exception
NMI request
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Chapter 21 Interrupt Control
21.5
MB91460N series
21.5 Operation
The following section explains priority determination operation of interrupt control.
Figure 21.5-1 Priority determination operation of interrupt control
The Flow of the Interrupt Process
Interrupt cause generated
The interrupt request flag is set to “1”.
CPU processing
Is the interrupt level higher than
the interrupt mask level?
NO
NO
(ICR) < (ILM)
Are interrupt requests enabled?
YES
YES
The interrupt request is transmitted to
the interrupt control circuit.
Priority determination
NO
Are interrupts enabled?
I flag = 1
Interrupt control circuit
NO
YES
Is the corresponding interrupt enabled?
(ICR) < 31?
Wait until the executed instructions finish
YES
Interrupt level = 31
Interrupt number
has no influence
Which interrupt has the lowest level
among the interrupt requests?
The lowest interrupts
Which interrupt has the lowest
number (#) among the lowest
interrupt requests?
Transition processing to interrupts
- Save to the system stack (PS and PC)
- Set an interrupt level to ILM
- System stack enabled
- Branch to the interrupt routine
(PC <= interrupt vector)
The interrupt with
the lowest number
The interrupt level and the interrupt number
are transmitted to the CPU.
■ Priority determination
• The interrupt control circuit selects the highest priority event from those that have been generated
simultaneously, and outputs the event's interrupt level (ICR) and interrupt number (#) to the CPU.
• The priority level criteria of an interrupt cause are the following conditions.
• The value of the interrupt level is not 31. (31 is "interrupt disable")
• The events with the smallest interrupt level.
• Among these, the event that has the smallest interrupt number.
• If nothing is applicable by the above-mentioned criteria, interrupt level 31 (11111B) is sent to the CPU. In this
case, the interrupt number has no influence.
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Chapter 21 Interrupt Control
21.6
MB91460N series
21.6 Setting
Table 21.6-1 Setting Required to Use Interrupts
Setting
Setting Registers
Setting the interrupt level
Clearing the interrupt request flags
Enabling interrupt requests
I flag setting
Interrupt control registers (ICR00 to ICR63)
See the corresponding chapter for each peripheral function.
See the corresponding chapter for each peripheral function.
CCR register
Setting
Procedure
See 21.7.1
–
–
See 21.7.4
*: For the setting procedure, refer to the section indicated by the number.
Table 21.6-2 Setting that Requires the Setting within Interrupt Processing
Setting
Setting Registers
Clearing the interrupt request flags
See the corresponding chapter for each peripheral function.
Setting
Procedure
–
*: For details of the setting procedure, see the section stated in Setting Procedure.
21.7 Q & A
21.7.1 How to set interrupt levels
Set by Interrupt control registers (ICR00 to ICR63).
It is necessary to set interrupt levels in advance to the control registers of the applicable interrupts.
How to configure to the highest level
How to configure to a level
How to configure to the lowest level
When is the interrupt not used
Interrupt control registers ICR00 to ICR63
Set 16.
Set any level (from 16 to 30).
Set 30.
Set 31 (interrupt disable).
• Since the bit of the interrupt control register (ICR[4]) is fixed to "1", 0 to 15 cannot be set to a register.
21.7.2 How to enable interrupts
To enable interrupts, all of the following three settings should be set:
• Set the value 16 to 30 to the applicable register in the interrupt control registers (ICR00 to ICR63).
• Set the interrupt request enable bit of the applicable peripheral function to "1" (enable) (See the chapter
for the corresponding peripheral function).
• Set the interrupt enable bit (I) to "1."
21.7.3 How to disable interrupts
To disable interrupts, at least one of the following three settings should be set:
• Set the value 31 to the applicable register in the interrupt control registers (ICR00 to ICR63).
• Set the interrupt request enable bit of the applicable peripheral function to "0" (disable).
• Set the interrupt enable bit (I) to "0" (disable all interrupts.)
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Chapter 21 Interrupt Control
21.8
MB91460N series
21.7.4 How to set an I flag
−>Using C programming language:
I flag is set to "1" (interrupt enable) by writing __EI(); (EI() is a macro function).
I flag is set to "0" (interrupt disable) by writing __DI(); (DI() is a macro function).
Two underscores
21.8 Caution
Interrupt flags are not cleared automatically. Make sure to clear them in the interrupt process.
(They are usually cleared by writing "0" to the interrupt flag, however, there are some exceptions depending
on the type of peripheral functions. See the chapter for the corresponding peripheral function.)
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CM44-10149-1E
Chapter 22 External Interrupt
22.1
MB91460N series
Chapter 22 External Interrupt
22.1 Overview
An external interrupt is generated whenever an external interrupt request level is applied to an external
interrupt input pin, and the respective interrupt request is enabled.
Figure 22.1-1 Block diagram of external interrupt
INT input pin
Edge / Level
detection
circuit
enable
Interrupt flag
Interrupt request
The output of the above figure (P. 229) is an input to the Interrupt control (See "Block diagram of Interrupt Control" on P.
219)
22.2 Features
• Quantity
: 10(INT input --10 channels: INT0 to INT7, INT12, INT13)
• External interrupt request level: 4 levels
• "L" level
• "H" level
• Rising edge
• Falling edge
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Chapter 22 External Interrupt
22.3
MB91460N series
22.3 Configuration
Figure 22.3-1 Configuration Diagram for external interrupts 0 to 7
External interrupts 0 to 7
Detect level setting
External interrupt request enable flag
LB0,
LB1,
LB2,
LB3,
LB4,
LB5,
LB6,
LB7,
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
ELVR0 : bit 1, bit 0,
ELVR0 : bit 3, bit2,
ELVR0 : bit 5, bit 4,
ELVR0 : bit 7, bit 6,
ELVR0 : bit 9, bit 8,
ELVR0 : bit 11, bit 10,
ELVR0 : bit 13, bit 12,
ELVR0 : bit 15, bit 14
0
0
Detect at “L” level
0
1
1
0
Detect at “H” level
Detect at the rising edge
1
1
Detect at the falling edge
External interrupt flag
ER0,
ER1,
ER2,
ER3,
ER4,
ER5,
ER6,
ER7
INT input pins
INT0/P24.0
INT1/P24.1
INT2/P24.2
INT3/P24.3
INT4/SDA2/P24.4
INT5/SCL2/P24.5
INT6/SDA3/P24.6
INT7/SCL3/P24.7
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
n0
n1
n2
n3
n4
n5
n6
n7
EN0,
EN1,
EN2,
EN3,
EN4,
EN5,
EN6,
EN7
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
0
Disable interrupt request
1
Enable interrupt request
0
Edge / Level detection circuit
0
No interrupt
1
Interrupt present
WRITE 0: Flag clear
(Inputs of other peripheral
function macros)
0
1
2
3
4
5
6
7
1
Interrupt request
(#16, #17, #18, #19,
#20, #21, #22, #23)
Read of the port
1
(Outputs of other peripheral function macros)
From the port data register
0
Register number
SDA2 PFR24: bit4
SCL2 PFR24: bit5
SDA3 PFR24: bit6
SCL3 PFR24: bit7
0
1
230
General-purpose port
Peripheral
P24.0
P24.1
P24.2
P24.3
P24.4
P24.5
P24.6
P24.7
0
1
DDR24: bit0
DDR24: bit1
DDR24: bit2
DDR24: bit3
DDR24: bit4
DDR24: bit5
DDR24: bit6
DDR24: bit7
Input only
Enable output
2
3
4
5
External interrupt
request level
setting bit
LB0, LA0
LB1, LA1
LB2, LA2
LB3, LA3
LB4, LA4
LB5, LA5
6
7
LB6, LA6
LB7, LA7
External
interrupt
0
1
External Enable external Interrupt
interrupt
interrupt
number
request bit
requests
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
EN0
EN1
EN2
EN3
EN4
EN5
EN6
EN7
FUJITSU MICROELECTRONICS LIMITED
#16
#17
#18
#19
#20
#21
#22
#23
The data
direction bit
P24.0
P24.1
P24.2
P24.3
P24.4
P24.5
P24.6
P24.7
Port
function
--------SDA2
SCL2
SDA3
SCL3
Pins
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
CM44-10149-1E
Chapter 22 External Interrupt
22.3
MB91460N series
Figure 22.3-2 Configuration Diagram for external interrupts 8 to 15
External interrupts 12, 13
Detect level setting
LB12, LA12
LB13, LA13
ELVR1 : bit 9, bit 8,
ELVR1 : bit 11, bit 10
0
Detect at “L” level
0
1
1
0
Detect at “H” level
Detect at the rising edge
1
1
Detect at the falling edge
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
ER4,
ER5
INT input pins
INT12/RX4/P22.0
INT13/RX5/P22.2
External interrupt request enable flag
External interrupt flag
0
Edge / Level detection circuit
EN4,
EN5
n0
n1
n2
n3
n4
n5
n6
n7
ENIR1 : bit 4
ENIR1 : bit 5
0
Disable interrupt request
1
Enable interrupt request
Interrupt request
(#24, #25, #26, #27
#28, #29, #30, #31)
0
No interrupt
1
Interrupt present
WRITE 0: Flag clear
(Inputs of other peripheral
function macros)
Read of the port
1
(Outputs of other peripheral function macros)
From the port data register
0
Register number
RX4
RX5
PFR22: bit0
PFR22: bit2
0
1
General-purpose port
P22.0 DDR22: bit0
P22.2 DDR22: bit2
Input only
0
Enable output
1
Pepheral
External
interrupt
External interrupt
request level
setting bit
12
13
LB12, LA12
LB13, LA13
External Enable external Interrupt
interrupt
interrupt
number
request bit
requests
ER12
ER13
EN12
EN13
#28
#29
The data
direction bit
P22.0
P22.2
Port
function
Pins
RX4
RX5
INT12
INT13
Figure 22.3-3 Register List
External interrupt (0 to 7)
Address Bit
00030H
7
ER7
6
ER6
5
ER5
4
ER4
3
ER3
2
ER2
1
ER1
0
ER0
EIRR0
00031H
(External interrupt cause 0)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
ENIR0
Bit
15
LB7
14
LA7
13
LB6
12
LA6
11
LB5
10
LA5
9
LB4
8
LA4
7
LB3
Bit
00D58H
7
P24.7
6
P24.6
5
P24.5
4
P24.4
3
P24.3
2
P24.2
1
P24.1
0
P24.0 DDR24
(Data direction)
00D98H
P24.7
P24.6
P24.5
P24.4
P24.3
P24.2
P24.1
P24.0 PFR24
(Port function)
00440H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR00
(Interrupt level #16/#17)
00441H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR01
(Interrupt level #18/#19)
00442H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR02
(Interrupt level #20/#21)
00443H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR03
(Interrupt level #22/#23)
00032H
(External interrupt enable 0)
6
LA3
5
LB2
4
LA2
3
LB1
2
LA1
1
LB0
0
LA0
ELVR0
(External interrupt request level 0)
0FFFBCH
32Bits
(Interrupt vector #16)
0FFFB8H
32Bits
(Interrupt vector #17)
0FFFB4H
32Bits
(Interrupt vector #18)
0FFFB0H
32Bits
(Interrupt vector #19)
0FFFACH
32Bits
(Interrupt vector #20)
0FFFA8H
32Bits
(Interrupt vector #21)
0FFFA4H
32Bits
(Interrupt vector #22)
0FFFA0H
32Bits
(Interrupt vector #23)
* See the chapter of "Interrupt Control" about ICR register and interrupt vectors.
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Figure 22.3-4 Register List
External interrupt (12,13)
Address Bit
000030H
7
ER7
6
ER6
5
ER5
4
ER4
3
ER3
2
ER2
1
ER1
0
ER0
000031H
EIRR0
(External interrupt cause 0)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0 ENIR0
(External interrupt enable 0)
Address Bit
000034H
7
---
6
---
5
ER13
4
ER12
3
---
2
---
1
---
0
---
EIRR1
(External interrupt cause 1)
000035H
---
---
EN13
EN12
---
---
---
---
ENIR1
(External interrupt enable 1)
Address Bit
000036H
15
---
14
---
13
---
12
---
11
LB13
10
LA13
9
LB12
8
LA12
Address Bit
000D56H
7
---
6
---
5
---
4
---
3
---
2
P22.2
1
---
0
P22.0 DDR22
(Data direction)
000D96H
---
---
---
---
---
P22.2
---
P22.0 PFR22
(Port function)
000446H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR06
(Interrupt level #28/#29)
7
---
6
---
5
---
4
---
3
---
2
---
1
---
0
--ELVR1
(External Interrupt request level 1)
Address
00FFF8CH
32Bits
(Interrupt vector #28)
00FFF88H
32Bits
(Interrupt vector #29)
* See the chapter of "Interrupt Control" about ICR register and interrupt vectors.
Note: See "Chapter 21 Interrupt Control (Page No.219)" about ICR register and interrupt vectors.
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22.4
MB91460N series
22.4 Registers
22.4.1 ELVR: Interrupt Request Level Register
The register selects the interrupt request level of the INT input pins (rising edge, falling edge, high level or low
level).
• ELVR0 (INT0 to INT7): Address 000032H (access: Half-word, Word)
15
14
13
12
11
10
9
8
Bit
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
7
6
5
4
3
2
1
0
Bit
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
Bit
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• ELVR1 (INT12,INT13): Address 000036H (access: Half-word, Word)
15
14
13
12
11
10
9
8
-
-
-
-
LB13
LA13
LB12
LA12
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
7
6
5
4
3
2
1
0
Bit
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
Interrupt request level bits (LBn, LAn) are registers that configures the Edge / Level detection circuit of
external interrupt.
2 bits (LBn, LAn) are assigned to each external interrupt INTn.
LBn
0
0
1
1
LAn
0
1
0
1
Description
Detection of "L" level and generation of an interrupt request.
Detection of "H" level and generation of an interrupt request.
Detection of the rising edge and generation of an interrupt request.
Detection of the falling edge and generation of an interrupt request.
When the interrupt request level is "H" level or "L" level (LAn, LBn = 00 or 01), and when the INTn pin input is
the valid level, the corresponding flag (ERn) will be re-set to "1" even if the external interrupt flag (ERn) is set
to "0" by software simultaneously.
Note: n = 0 to 15
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22.4.2 EIRR: External Interrupt Request Register
Status flag of an external interrupt.
• EIRR0 (INT0 to INT7): Address 000030H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
0
0
0
0
0
R (RM1), W
0
R (RM1), W
Initial value
Attribute
Bit
0
0
R (RM1), W
R (RM1), W
R (RM1), W R (RM1), W R (RM1), W R (RM1), W
Bit
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• EIRR1 (INT12,INT13): Address 000034H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
-
-
ER13
ER12
-
-
-
-
0
0
0
0
0
0
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
0
0
R (RM1), W R (RM1), W
Initial value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
An external interrupt flag (ERn) indicates the corresponding external interrupt.
Description
ERn
Read value
No external interrupt present
External interrupt present
0
1
Write value
Clear external interrupt flag
No effect on operation
Note: n = 0 to 15
22.4.3 ENIR: Enable Interrupt Request Register
Enable bit of external interrupt requests.
• ENIR0 (INT0 to INT7): Address 000031H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
Bit
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
Bit
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• ENIR1 (INT12, INT13): Address 000035H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
-
-
EN13
EN12
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
An external interrupt request enable bit (ENn) enables the corresponding external interrupt.
ERn
0
1
Description
External interrupt request output disable
External interrupt request output enable
Note: n = 0 to 15
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22.5
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22.5 Operation
Figure 22.5-1 Example Operation for occurrence of external interrupt
Level detection
(2)
(1)
INT (“H”)
(“L”)
(1)
(2)
(3)
Valid edge
Clear by software
(4)
Interrupt flag (ER)
(5)
Edge detection
Peripheral clock
(CLKP)
(2)
INT (rising)
(fallling)
Required to maintain the level more than
before and after the edge (2 × CLKP)
(1)
(1)
(2)
(3)
Valid edge
Clear by software
(4)
Interrupt flag (ER)
(5)
(1) External interrupt signal (INT) input
(2) Detect interrupt signals (level/edge).
(3) Valid edge signal (2 × CLKP above required)
(4) An interrupt is generated.
(5) The interrupt flag is cleared by software.
Remark: When waking up from STOP state with edge detection enabled a minimum pulse width (> 50ns) of
the INT signal trigger must be fulfilled.
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22.6 Setting
Table 226-1 Setting Required in Order to Use External Interrupts
Setting
Setting of external interrupt request level
Set INT pin as the input.
External interrupt
Setting
Procedures*
Setting Registers
External interrupt request level setting register
(ELVR0, ELVR1)
Data direction register (DDR22, DDR24)
Port function register (PFR22, PFR24)
External inputs
→Inputs the signal to INT0 to INT7,INT12,INT13 pins.
See 22.7.1
See 22.7.2
–
Note: For the setting procedure, refer to the section indicated by the number.
22.7 Q & A
22.7.1 What are the types and setting procedures of external interrupt request levels?
There are 4 types of external interrupt request levels: "L" level, "H" level, rising edge, and falling edge
Carry out in Detection level bit (ELVR0:LBx, LAx) x = 0 to 7, and (ELVR1:LBx, LAx) x = 12,13.
Detection level bit (LBn, LAn) n = 0 to 15
Sets to "00B"
External interrupt request levels
"L" level
Sets to "01B"
"H" level
Sets to "10B"
rising edge
Sets to "11B"
falling edge
22.7.2 How to set INT pin as the input
Use data direction registers (DDR22, DDR24).
Use port function register (PFR22, PFR24).
Operation
To use INT0 pin input
To use INT1 pin input
To use INT2 pin input
To use INT3 pin input
To use INT4 pin input
To use INT5 pin input
To use INT6 pin input
To use INT7 pin input
To use INT12 pin input
To use INT13 pin input
Data Direction bits
DDR24.0
DDR24.1
DDR24.2
DDR24.3
DDR24.4
DDR24.5
DDR24.6
DDR24.7
DDR22.0
DDR22.2
Setting
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Port Function bit
PFR24.0
PFR24.1
PFR24.2
PFR24.3
PFR24.4
PFR24.5
PFR24.6
PFR24.7
PFR22.0
PFR22.2
Setting
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Remark: Even though the external interrupt can be even used with setting DDR=0 and PFR=0 (general
purpose port input mode), the input line will be disabled when setting STOP state with HIZ.
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22.7.3 What interrupt registers are used?
Setting of interrupt vectors of external interrupts, and interrupt levels
The relationship among external interrupt numbers, interrupt levels, and vectors is shown in the table below.
See "Chapter 21 Interrupt Control (Page No.219)" about the details of interrupt levels and interrupt vectors.
INT0
Interrupt vectors (default)
#16
Address: 0FFFBCH
INT1
#17
Address: 0FFFB8H
INT2
#18
Address: 0FFFB4H
INT3
#19
Address: 0FFFB0H
INT4
#20
Address: 0FFFACH
INT5
#21
Address: 0FFFA8H
INT6
#22
Address: 0FFFA4H
INT7
#23
Address: 0FFFA0H
INT12
#28
Address: 0FFF8CH
INT13
#29
Address: 0FFF88H
Interrupt level setting bits (ICR[4:0])
Interrupt level register (ICR00)
Address: 000440H
Interrupt level register (ICR01)
Address: 000441H
Interrupt level register (ICR02)
Address: 000442H
Interrupt level register (ICR03)
Address: 000443H
Interrupt level register (ICR06)
Address: 000446H
22.7.4 Interrupt types
Interrupt causes are limited to external interrupts. There is no bit for selection.
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22.7.5 How to enable, disable, and clear interrupts
Interrupt request enable bit, interrupt flag
Use interrupt request enable bits (ENIR0:ENx. x = 0 to 7) and (ENIR1:ENx. x = 12,13) to enable interrupts.
To disable interrupt requests
To enable interrupt requests
Interrupt request enable bit (ENn [n = 0 to 7,12,13])
Set to "0"
Set to "1"
Use interrupt flags (EIRR0:ERx. x = 0 to 7) and (EIRR1:ERx. x = 12,13) to clear interrupt requests.
To clear interrupts
238
Interrupt flag (ERn [n = 0 to 7,12,13])
Write "0"
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Chapter 22 External Interrupt
22.8
MB91460N series
22.8 Caution
• When the External interrupt request level is set to "H" level or "L" level (LAn, LBn = 00 or 01) and when the
INT pin input becomes activated, the corresponding flag (ERn) will be re-set to "1" even if the external
interrupt flag (ERn) is set to "0" by software simultaneously.
Note: n = 0 to 15
• Before enabling the external interrupt request with ENn = 1 it is recommended to clear the external interrupt
flag (set ERn to "0") to avoid interrupts caused by previous matches of the input trigger (the ERn flag is set
independently of the setting of ENn).
Note: n = 0 to 15
• Before going into standby (STOP state), make sure to disable unused external interrupts (ENn = 0).
Note: n = 0 to 15
• Minimum 3 × CLKP (peripheral clock) is required for the pulse width to detect the edge presence when the
request level is set to the edge request.
• When waking up from STOP state with edge detection enabled a minimum pulse width (> 50ns) of the INT
signal trigger must be fulfilled.
• The interrupt request to the interrupt controller remains active, even if an external interrupt is input from the
external interrupt pin INTn and canceled afterward, since the interrupt flag (ERn) is present. To cancel the
interrupt request to the interrupt controller, the interrupt flag must be cleared (ERn = 0) by software. (See the
diagram in "22.5 Operation (Page No.235)")
Note: n = 0 to 7,12,13
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Chapter 23 DMA Controller
23.1
MB91460N series
Chapter 23 DMA Controller
23.1 Overview of the DMA Controller (DMAC)
The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer
on FR family devices. When this module is used to control DMA transfer, various kinds of data
can be transferred at high speed by bypassing the CPU, enhancing system performance.
■ Hardware Configuration
The DMA controller (DMAC) consists mainly of the following blocks:
Five independent DMA channels
•
5-channel independent access control circuit
•
32-bit address registers (reload specifiable, two registers for each channel)
•
16-bit transfer count register (reload specifiable, one register for each channel)
•
4-bit block count register (one for each channel)
•
Up to 128 internal transfer request sources
•
External transfer request input pins: Not equipped
•
External transfer request acknowledgement output pins: Not equipped
•
DMA end output pins: Not equipped
•
Fly-by transfer (external memory to external I/O and external I/O to external memory) : Not supported
•
2-cycle transfer
■ Main Functions
The following are the main functions related to data transfer by the DMA controller (DMAC):
Data can be transferred independently over multiple channels (5 channels)
● Priority (ch.0>ch.1>ch.2>ch.3>ch.4)
● The priority order can be rotated between ch.0 and ch.1.
● Transfer request sources
•
Built-in peripheral requests (shared interrupt requests, including external interrupts)
•
Software request (register write)
● Transfer mode
•
Burst transfer, step transfer, and block transfer
•
Addressing mode: 32-bit full addressing (increment/decrement/fixed)
The address increment/decrement range is from -255 to +255.
•
Data types: Byte, halfword, and word length
•
Single shot/reload selectable
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■ Block Diagram
Figure 23.1-1"Block Diagram of the DMA Controller (DMAC)" is a block diagram of the DMA controller (DMAC).
Figure 23.1-1 Block Diagram of the DMA Controller (DMAC)
Counter
Selector
Write back
Buffer
DMA transfer request to
the bus controller
DTC 2-stage register DTCR
DMA activation
source
selection circuit
& request
acceptance
control
Peripheral activation request/stop input
External pin activation request/stop input:
Not supported
Counter
DSS[3:0]
Read
Write
Priority circuit
ERIR,EDIR
Selector
Read/write
control
BLK register
242
MCLREQ
Bus control unit
Selector
Counter buffer
Peripheral interrupt clear
SADM,SASZ[7:0] SADR
Write back
Selector
address
Counter buffer
Access
DSAD 2-stage register
IRQ[4:0]
TYPE.MOD,WS
DMA control
Address counter
To Harvard/
Princeton
bus converter
Bus control unit
M-bus
State
transition
circuit
To interrupt controller
X-bus
Buffer
DDAD 2-stage register
DADM,DASZ[7:0] DADR
Write back
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23.2
MB91460N series
23.2 DMA Controller (DMAC) Registers
This section describes the configuration and functions of the registers used by the DMA controller (DMAC).
■ DMA Controller (DMAC) registers
Figure 23.2-1"DMA Controller (DMAC) Registers" shows the registers of the DMA controller (DMAC).
Figure 23.2-1 DMA Controller (DMAC) Registers
(bit)
31 24 23 16 15 08 07 00
ch.0
Control/status register A
(DMACA0)
ch.0
Control/status register B
(DMACB0)
ch.1
Control/status register A
(DMACA1)
ch.1
Control/status register B
(DMACB1)
ch.2
Control/status register A
(DMACA2)
ch.2
Control/status register B
(DMACB2)
ch.3
Control/status register A
(DMACA3)
ch.3
Control/status register B
(DMACB3)
ch.4
Control/status register A
(DMACA4)
ch.4
Control/status register B
(DMACB4)
All-channel control register
(DMACR)
ch.0
Transfer source address register
(DMASA0)
ch.0
Transfer destination address register
(DMADA0)
ch.1
Transfer source address register
(DMASA1)
ch.1
Transfer destination address register
(DMADA1)
ch.2
Transfer source address register
(DMASA2)
ch.2
Transfer destination address register
(DMADA2)
ch.3
Transfer source address register
(DMASA3)
ch.3
Transfer destination address register
(DMADA3)
ch.4
Transfer source address register
(DMASA4)
ch.4
Transfer destination address register
(DMADA4)
■ Notes on Setting Registers
When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while
DMA is in progress (during transfer), correct operation cannot be guaranteed.
An asterisk following a bit when its function is described later indicates that the operation of the bit is affected if it
is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped (start is disabled or temporarily
stopped).
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If such a bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the
setting takes effect when start is enabled.
If such a bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMACR not equal to 0000B or PAUS
of DMACA=1), the setting takes effect when temporary stopping is canceled.
23.2.1 Control/Status Registers A (DMACA0 to 4)
Control/status registers A (DMACA0 to 4) control the operation of the DMAC channels. There is
a separate register for each channel.
This section describes the configuration and functions of control/status registers A (DMACA0 to
4).
■ Bit Configuration of Control/Status Registers A (DMACA0 to 4)
Figure 23.2-2"Bit Configuration of Control/Status Registers A (DMACA0 to 4)" shows the bit configuration of
control/status registers A (DMACA0 to 4).
Figure 23.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to 4)
bit
Address
000200H (ch0)
000208H (ch1)
000210H (ch2)
000218H (ch3)
000220H (ch4)
31
30
29
28
27
bit
15
14
13
26
25
24
23
IS[4:0]
DENB PAUS STRG
12
11
10
22
21
20
19
EIS[3:0]
9
8
7
6
5
18
17
16
BLK[3:0]
4
3
2
1
Initial value
000000000000XXXX
0
DTC[15:0]
XXXXXXXXXXXXXXXXB
■ Detailed Bit of Control/Status Registers A (DMACA0 to 4)
The following describes the functions of the bits of control/status registers A (DMACA0 to 4).
[Bit 31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to 0 and transfer stops.
The transfer can be forced to stop by writing 0 to this bit. Be sure to stop a transfer forcibly (0 write) only after
temporarily stopping DMA using the PAUS bit (Bit30 of DMACA). If the transfer is forced to stop without first
temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is
stopped using the DSS[2:0] bits [Bit18 to bit16 of DMACB].
DENB
Function
0
Disables operation of DMA on the corresponding channel (initial value).
1
Enables operation of DMA on the corresponding channel.
•
If a stop request is accepted during reset: Initialized to 0.
•
This bit is readable and writable.
•
If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register
(DMACR), writing 1 to this bit is disabled and the stopped state is maintained. If the operation is disabled by
the above bit while it is enabled by this bit, 0 is written to this bit and the transfer is stopped (forced stop).
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[Bit 30] PAUS (PAUSe)*: Temporary stop instruction
This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set to "1", DMA transfer is
not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xxB).
If this bit is set to "1" before starting, DMA transfer continues to be temporarily stopped.
New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is
cleared (See 23.3.8"Operation from Starting to End/Stopping").
PAUS
Function
0
Enables operation of the corresponding channel DMA (initial value)
1
Temporarily stops DMA on the corresponding channel.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 29] STRG (Software TRiGger): Transfer request
This bit generates a DMA transfer request for the corresponding channel. If 1 is written to this bit, a transfer
request is generated when write operation to the register is completed and transfer on the corresponding
channel is started.
However, if the corresponding channel is not activated, operations on this bit are disabled.
If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are
simultaneous, the transfer request is enabled and transfer is started. If writing of 1 to the PAUS bit and a
transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but DMA transfer is
not started before 0 is written to the PAUS bit.
STRG
Function
0
Disabled
1
DMA starting request
•
When reset: Initialized to 0.
•
The read value is always 0.
•
Only a write value of 1 is valid. If 0 is written, operation is not affected.
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[Bit 28 to bit 24] IS4 to 0 (Input Select)*: Transfer source selection
These bits select the source of a transfer request. Note that the software transfer request by the STRG bit
function is always valid regardless of the setting of these bits. As listed in Table 23.2-1 "Settings for Transfer
Request Sources".
Table 23.2-1 Settings for Transfer Request Sources
IS
EIS
RN
Function
Transfer stop request
00000B
-
-
Activation by hardware prohibited
00001B
01101B
-
-
Setting prohibited
Setting prohibited
01110B
-
-
Rerserved
01111B
-
-
Rerserved
10000B
0000B
0
External Interrupt 0
-
10001B
0000B
1
External Interrupt 1
-
10010B
0000B
2
External Interrupt 2
-
10011B
0000B
3
External Interrupt 3
-
10100B
0000B
4
Reload Timer 0
-
10101B
0000B
5
Reload Timer 1
-
10110B
0000B
6
LIN-USART 0 RX
available
10111B
0000B
7
LIN-USART 0 TX
-
11000B
0000B
8
LIN-USART 1 RX
available
11001B
0000B
9
LIN-USART 1 TX
-
11010B
0000B
10
Rerserved
-
11011B
0000B
11
Rerserved
-
11100B
0000B
12
Rerserved
-
11101B
0000B
13
Rerserved
-
11110B
0000B
14
A/D Converter
-
11111B
0000B
15
Programmable Pulse Generator (PPG) 0
-
•
When reset: IS4 to IS0 is initialized to 00000B.
•
When reset: EIS3 to EIS0 is initialized to 0000B.
•
These bits are readable and writable.
not available
Note:
If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxxB), disable interrupts from
the selected peripheral function with the ICR register.
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[Bit23 to bit20] EIS3 to 0 (Extended Input Select)*: Extended Transfer Source Selection
These bits select the source of a transfer request note that the software transfer request by the STRG bit
function is always valid regardless of the setting of these bits. As listed in Table 23.2-2 "Settings for Extended
Transfer Source Selection".
Table 23.2-2 Settings for Extended Transfer Source Selection
IS
EIS
RN
Function
Transfer stop request
10000B
0001B
16
External Interrupt 0
-
10001B
0001B
17
External Interrupt 1
-
10010B
0001B
18
External Interrupt 2
-
10011B
0001B
19
External Interrupt 3
-
10100B
0001B
20
External Interrupt 4
-
10101B
0001B
21
External Interrupt 5
-
10110B
0001B
22
External Interrupt 6
-
10111B
0001B
23
External Interrupt 7
-
11000B
0001B
24
Reserved
-
11001B
0001B
25
Reserved
-
11010B
0001B
26
Reserved
-
11011B
0001B
27
Reserved
-
11100B
0001B
28
Reserved
-
11101B
0001B
29
Reserved
-
11110B
0001B
30
Reserved
-
11111B
0001B
31
Reserved
-
10000B
0010B
32
Reload Timer 0
-
10001B
0010B
33
Reload Timer 1
-
10010B
0010B
34
Reload Timer 2
-
10011B
0010B
35
Reload Timer 3
-
10100B
0010B
36
Reserved
-
10101B
0010B
37
Reserved
-
10110B
0010B
38
Reserved
-
10111B
0010B
39
Reload Timer 7
-
11000B
0010B
40
Free-Run Timer 0
-
11001B
0010B
41
Free-Run Timer 1
-
11010B
0010B
42
Free-Run Timer 2
-
11011B
0010B
43
Free-Run Timer 3
-
11100B
0010B
44
Reserved
-
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Table 23.2-2 Settings for Extended Transfer Source Selection
IS
EIS
RN
Function
Transfer stop request
11101B
0010B
45
Reserved
-
11110B
0010B
46
Reserved
-
11111B
0010B
47
Reserved
-
10000B
0011B
48
LIN-USART 0 RX
available
10001B
0011B
49
LIN-USART 0 TX
-
10010B
0011B
50
LIN-USART 1 RX
available
10011B
0011B
51
LIN-USART 1 TX
-
10100B
0011B
52
LIN-USART 2 RX
available
10101B
0011B
53
LIN-USART 2 TX
-
10110B
0011B
54
LIN-USART 3 RX
available
10111B
0011B
55
LIN-USART 3 TX
-
11000B
0011B
56
Reserved
-
11001B
0011B
57
Reserved
-
11010B
0011B
58
Reserved
-
11011B
0011B
59
Reserved
-
11100B
0011B
60
Reserved
-
11101B
0011B
61
Reserved
-
11110B
0011B
62
Reserved
-
11111B
0011B
63
Reserved
-
10000B
0100B
64
Reserved
-
10001B
0100B
65
Reserved
-
10010B
0100B
66
Reserved
-
10011B
0100B
67
Reserved
-
10100B
0100B
68
Reserved
-
10101B
0100B
69
Reserved
-
10110B
0100B
70
Reserved
-
10111B
0100B
71
Reserved
-
11000B
0100B
72
Reserved
-
11001B
0100B
73
Reserved
-
11010B
0100B
74
Reserved
-
11011B
0100B
75
Reserved
-
11100B
0100B
76
Reserved
-
11101B
0100B
77
Reserved
-
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Table 23.2-2 Settings for Extended Transfer Source Selection
IS
EIS
RN
Function
Transfer stop request
11110B
0100B
78
Reserved
-
11111B
0100B
79
Reserved
-
10000B
0101B
80
Input Capture 0
-
10001B
0101B
81
Input Capture 1
-
10010B
0101B
82
Input Capture 2
-
10011B
0101B
83
Input Capture 3
-
10100B
0101B
84
Reserved
-
10101B
0101B
85
Reserved
-
10110B
0101B
86
Reserved
-
10111B
0101B
87
Reserved
-
11000B
0101B
88
Output Compare 0
-
11001B
0101B
89
Output Compare 1
-
11010B
0101B
90
Output Compare 2
-
11011B
0101B
91
Output Compare 3
-
11100B
0101B
92
Reserved
-
11101B
0101B
93
Reserved
-
11110B
0101B
94
Reserved
-
11111B
0101B
95
Reserved
-
10000B
0110B
96
Programmable Pulse Generator 0
-
10001B
0110B
97
Programmable Pulse Generator 1
-
10010B
0110B
98
Programmable Pulse Generator 2
-
10011B
0110B
99
Programmable Pulse Generator 3
-
10100B
0110B
100
Programmable Pulse Generator 4
-
10101B
0110B
101
Programmable Pulse Generator 5
-
10110B
0110B
102
Programmable Pulse Generator 6
-
10111B
0110B
103
Programmable Pulse Generator 7
-
11000B
0110B
104
Reserved
-
11001B
0110B
105
Reserved
-
11010B
0110B
106
Reserved
-
11011B
0110B
107
Reserved
-
11100B
0110B
108
Reserved
-
11101B
0110B
109
Reserved
-
11110B
0110B
110
Reserved
-
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Table 23.2-2 Settings for Extended Transfer Source Selection
IS
EIS
RN
Function
11111B
0110B
111
Reserved
-
10000B
0111B
112
ADC 0
-
10001B
0111B
113
Reserved
-
10010B
0111B
114
Reserved
-
•
When reset: IS4 to IS0 is initialized to 00000B.
•
When reset: EIS3 to EIS0 is initialized to 0000B.
•
These bits are readable and writable.
Transfer stop request
[Bit 19 to bit 16] BLK3 to 0 (BLocK size): Block size specification
These bits specify the block size for block transfer on the corresponding channel. The value specified by these
bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width
setting). If block transfer will not be performed, set 01H (size 1).
BLK
XXXXB
Function
Block size of the corresponding channel
•
When reset: Not initialized.
•
These bits are readable and writable.
•
If 0 is specified for all bits, the block size becomes 16 words.
•
During reading, the block size is always read (reload value).
[Bit 15 to bit 0] DTC (Dma Terminal Count register)*: Transfer count register
The DTC register stores the transfer count. Each register has 16-bit length.
All registers have a dedicated reload register. When the register is used for a channel that is enabled to reload
the transfer count register, the initial value is automatically written back to the register when the transfer is
completed.
DTC
XXXXH
Function
Transfer count for the corresponding channel
When DMA transfer is started, the data from this register is stored in the counter buffer of the DMA-dedicated
transfer counter and is decremented by 1 (subtraction) after each transfer unit. When DMA transfer is completed,
the contents of the counter buffer are written back to this register and then DMA ends. Thus, the transfer count
value during DMA operation cannot be read.
•
When reset: Not initialized.
•
These bits are readable and writable. Always access DTC using halfword length or word length.
•
During reading, the count value is read. The reload value cannot be read.
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23.2.2 Control/Status Registers B (DMACB0 to 4)
Control/status registers B (DMACB0 to 4) control the operation of each DMAC channel and exist
separately for each channel.
This section describes the configuration of control/status registers B (DMACB0 to 4) and their
functions.
■ Bit Configuration of Control/Status Register B (DMACB0 to 4)
Figure 23.2-3"Bit Configuration of Control/Status Registers B (DMACB0 to 4)" shows the bit configuration of
control/status registers B (DMACB0 to 4).
Figure 23.2-3 Bit Configuration of Control/Status Registers B (DMACB0 to 4)
bit
Address
000204H (ch0)
00020CH (ch1)
000214H (ch2) bit
00021CH (ch3)
000224H (ch4)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
TYPE[1:0] MOD[1:0] WS[1:0] SADM DADM DTCR SADR DADR ERIE EDIE
15
14
13
12
11
10
9
8
7
6
5
SASZ[7:0]
4
3
17
16
DSS[2:0]
2
1
Initial value
0000000000000000B
0
DASZ[7:0]
XXXXXXXXXXXXXXXXB
■ Detailed Bit of Control/Status Register B (DMACB0 to 4)
The following describes the functions of the bits of control status register B (DMACB0 to 4).
[Bit 31 to bit 30] TYPE1, TYPE0: Transfer type setting
These bits are the transfer type setting bits and set the type of operation for the corresponding channel.
•
2-cycle transfer type: In this type, the transfer source address (DMASA) and transfer destination address
(DMADA) are set and transfer is performed by repeating the read operation and write operation for the number
of times specified by the transfer counter buffer. All areas can be specified as a transfer source or transfer
destination (32-bit address).
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Table 23.2-3 Settings for the Transfer Types
TYPE
Function
00B
2-cycle transfer (initial value)
01B
Setting disabled
10B
Setting disabled
11B
Setting disabled
•
When reset: Initialized to 00B.
•
These bits are readable and writable.
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[Bit 29, bit28] MOD1, MOD0: Transfer mode setting
These bits are the transfer mode setting bits and set the operating mode of the corresponding channel.
Table 23.2-4 Settings for Transfer Modes
MOD
Function
00B
Block/step transfer mode (initial value)
01B
Burst transfer mode
10B
Setting disabled
11B
Setting disabled
•
When reset: Initialized to 00B.
•
These bits are readable and writable.
[Bit 27, bit 26] WS1, WS0: Transfer data width selection
These bits are the transfer data width selection bits and are used to select the transfer data width of the
corresponding channel. Transfer operations are repeated in units of the data width specified in this register for
as many times as the specified count.
Table 23.2-5 Selection of the Transfer Data Width
WS
Function
00B
Byte-width transfer
01B
Halfword-width transfer
10B
Word-width transfer
11B
Setting disabled
(initial value)
•
When reset: Initialized to 00B.
•
These bits are readable and writable.
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[Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification
This bit specifies the address processing of the transfer source address of the corresponding channel in each
transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation according
to the specified transfer source address count width (SASZ). When the transfer is completed, the next access
address is written to the corresponding address register (DMASA).
As a result, the transfer source address register is not updated until DMA transfer is completed.
To make the address always the same, specify 0 or 1 for this register and make the address count width
(SASZ and DASZ) equal to 0.
SADM
Function
0
Increments transfer source address. (initial value)
1
Decrements the transfer source address.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode
specification
This bit specifies the address processing for the transfer destination address of the corresponding channel in
each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation according
to the specified transfer destination address count width (DASZ). When the transfer is completed, the next
access address is written to the corresponding address register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is completed.
To make the address always the same, specify 0 or 1 for this register and make the address count width
(SASZ, DASZ) equal to 0.
DADM
Function
0
Increments the transfer source address. (initial value)
1
Decrements the transfer source address.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
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[Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification
This bit controls reloading of the transfer count register for the corresponding channel.
If reload operation is enabled by this bit, the count register value is restored to its initial value after the transfer
is completed then DMAC stops and then waiting starts for new transfer requests (an activation request by
STRG or IS setting). If this bit is 1, the DENB bit is not cleared.
DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops
after the transfer is completed even if reload is specified in the address register. The DENB bit is also cleared
in this case.
DTCR
Function
0
Disables transfer count register reloading (initial value)
1
Enables transfer count register reloading.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification
This bit controls reloading of the transfer source address register for the corresponding channel.
If this bit enables the reload operation, the transfer source address register value is restored to its initial value
after the transfer is completed.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops
after the transfer is completed even if reload is specified in the address register. The address register value
also stops in this case while the initial value is being reloaded.
If this bit disables the reload operation, the address register value when the transfer is completed is the
address to be accessed next to the final address. When address increment is specified, the next address is an
incremented address.
SADR
Function
0
Disables transfer source address register reloading. (initial value)
1
Enables transfer source address register reloading.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
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[Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification
This bit controls reloading of the transfer destination address register for the corresponding channel.
If this bit enables reloading, the transfer destination address register value is restored to its initial value after
the transfer is completed.
The details of other functions are the same as those described for bit 22 (SADR).
DADR
Function
0
Disables transfer destination address register reloading. (initial value)
1
Enables transfer destination address register reloading.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 20] ERIE (ERror Interrupt Request Enable)*: Error interrupt Request output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error that
occurred is indicated by DSS2 to 0. Note that an interrupt occurs only for specific termination causes and not
for all termination causes (Refer to bits DSS2 to 0, which are bit 18 to bit 16).
ERIE
Function
0
Disables error interrupt request output. (initial value)
1
Enables error interrupt request output.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 19] EDIE (EnD Interrupt Request Enable)*: End interrupt request output enable
This bit controls the occurrence of an interrupt for normal termination.
EDIE
Function
0
Disables end interrupt request output. (initial value)
1
Enables end interrupt request output.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
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[Bit 18 to bit 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication
These bits indicate code (end code) of 3 bits that indicates the source of stopping or termination of DMA
transfer on the corresponding channel. For a list of end codes, see Table 23.2-6 and Table 23.2-7 "End
Codes".
Table 23.2-6 End Codes-1
DSS[2]
Function
0B
Initial value
1B
DMA stopped temporarily (for example, due to DMAH, PAUS bit, and an interrupt)
Table 23.2-7 End Codes-2
DSS[1:0]
Function
Interrupt
00B
Initial value
None
01B
Address error (underflow/overflow)
Error interrupt (ERIE)
10B
Transfer stop request
Error interrupt (ERIE)
11B
Normal end
End interrupt (EDIE)
A transfer stop request is set only when it is requested by a peripheral device or the external pin DSTP function is
used.
The Interrupt column indicates the type of interrupts that can occur.
•
When reset: Initialized to 000B.
•
These bits can be cleared by writing 000B to them.
•
These bits are readable and writable. Note that the only valid written value is 000B.
[Bit 15 to bit 8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification
These bits specify the increment or decrement width for the transfer source address (DMASA) of the
corresponding channel in each transfer operation. The value set by these bits becomes the address
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in
the transfer source address count mode (SADM).
SASZ
XXH
Function
Specify the increment/decrement width of the transfer source address. 0 to 255
•
When reset: Not initialized
•
These bits are readable and writable.
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[Bit 7 to bit 0] DASZ (Des Addr count SiZe)*: Transfer destination address count size specification
These bits specify the increment or decrement width for the transfer destination address (DMADA) of the
corresponding channel in each transfer operation. The value set by these bits becomes the address
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in
the transfer destination address count mode (DADM).
DASZ
Function
XXH
Specify the increment/decrement width of the transfer destination address. 0 to 255
•
When reset: Not initialized
•
These bits are readable and writable.
23.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/
DMADA0 to 4)
The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4)
control the operation of the DMAC channels. These registers are separately existent for each
channel.
This section describes the configuration and functions of the transfer source/transfer destination
address setting registers (DMASA0 to 4/DMADA0 to 4).
■ Bit Configuration of Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to 4/DMADA0 to 4)
The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4) are a group of
registers that store the transfer source/transfer destination addresses. Each register is 32 bits length.
Figure 23.2-4"Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers (DMASA0
to 4/DMADA0 to 4)" shows the bit configuration of the transfer source/transfer destination address setting
registers (DMASA0 to 4/DMADA0 to 4).
Figure 23.2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to 4/DMADA0 to 4)
Address
001000H
001008H
001010H
001018H
001020H
(ch0)
(ch1)
(ch2)
(ch3)
(ch4)
Address
001004H (ch0)
00100CH (ch1)
001014H (ch2)
00101CH (ch3)
001024H (ch4)
bit
bit
31
15
30
14
29
13
28
12
27
11
26
10
25
9
bit
31
30
29
28
27
26
25
bit
15
14
13
12
11
10
9
24 23 22
DMASA[31:16]
8
7
6
DMASA[15:0]
21
20
19
18
17
16
24 23 22
DMADA[31:16]
8
7
6
DMADA[15:0]
21
20
19
18
17
16
5
4
3
2
1
0
Initial value
XXXXXXXXXXXXXXXXB
5
4
3
2
1
0
XXXXXXXXXXXXXXXXB
Initial value
XXXXXXXXXXXXXXXXB
XXXXXXXXXXXXXXXXB
Detailed Bit of Transfer Source/Transfer
Destination Address Setting Register (DMASA0 to 4/DMADA0 to 4)
The following describes the functions of the bits of each transfer source/transfer destination address setting
register (DMASA0 to 4/DMADA0 to 4).
[Bit 31 to bit 0] DMASA (DMA Source Addr)*: Transfer source address setting
These bits set the transfer source address.
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[Bit 31 to bit 0] DMADA (DMA Destination Addr)*: Transfer destination address setting
These bits set the transfer destination address.
If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address
counter and then the address is calculated according to the settings for the transfer operation. When the DMA
transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends.
Thus, the address counter value during DMA operation cannot be read.
All registers have a dedicated reload register. When the register is used for a channel that is enabled for
reloading of the transfer source/transfer destination address register, the initial value is automatically written
back to the register when the transfer is completed. Other address registers are not affected.
•
When reset: Not initialized.
•
These bits are readable and writable. For this register, be sure to access these bits as 32-bit data.
•
If these bits are read during transfer, the address before the transfer is read. If they are read after transfer, the
next access address is read. Because the reload value cannot be read, it is not possible to read the transfer
address in real time.
Note:
Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the DMAC’s
registers themselves.
23.2.4 DMAC All-Channel Control Register (DMACR)
The DMAC all-channel control register (DMACR) controls the operation of the all five DMAC
channels. Be sure to access this register using byte length.
This section describes the configuration and functions of the DMAC all-channel control register
(DMACR).
■ Bit Configuration of DMAC All-Channel Control Register (DMACR)
Figure 23.2-5"Bit Configuration of the DMAC All-Channel Control Register (DMACR)" shows the bit configuration
of the DMAC all-channel control register (DMACR).
Figure 23.2-5 Bit Configuration of the DMAC All-Channel Control Register (DMACR)
bit
Address
000240H
31
DMAE
bit
15
-
30
14
-
29 28
- PM01
13 12
-
27
26 25
DMAH[3:0]
11 10 9
-
24
8
-
23
7
-
22
6
-
21
5
-
20
4
-
19
3
-
18
2
-
17
1
-
16
0
-
Initial value
0XX00000XXXXXXXXB
XXXXXXXXXXXXXXXXB
■ Detailed Bit of DMAC All-Channel Control Register (DMACR)
The following describes the bit functions of the DMAC all-channel control register (DMACR) bits.
[Bit 31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of the
start/stop settings for each channel and the operating status. Any channel carrying out transfer cancels the
requests and stops transfer at a block boundary. All start operations on each channel in a disabled state are
disabled.
If this bit enables DMA operation, start/stop operations are enabled for each channel. Simply enabling DMA
operation with this bit does not activate each channel.
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DMA operation can be forced to stop by writing 0 to this bit. However, be sure to force stopping (0 write) only
after temporarily stopping DMA using the DMAH[3:0] bits [Bit27 to bit24 of DMACR]. If forced stopping is
carried out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed.
Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to bit16 of DMACB].
DMAE
Function
0
Disables DMA transfer on all channels. (initial value)
1
Enables DMA transfer on all channels.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 28] PM01 (Priority mode ch0,ch1): Channel priority rotation
This bit is set to alternate priority for each transfer between Channel0 and Channel1.
PM01
Function
0
Fixes the priority. (ch0 > ch1)(initial value)
1
Alternates priority. (ch1 > ch0)
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[Bit 27 to bit 24] DMAH (DMA Halt): DMA temporary stop
These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not performed
on any channel before these bits are cleared.
When DMA transfer is activated after these bits are set, all channels remain temporarily stopped.
Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits are set
are all enabled. The transfer can be started by clearing all these bits.
DMAH
0000B
Other than 0000B
Function
Enables the DMA operation on all channels. (initial value)
Temporarily stops DMA operation on all channels.
•
When reset: Initialized to 0.
•
These bits are readable and writable.
[Bit 30, bit 29, and bit 23 to bit 0] (Reserved): Unused bits
•
These bits are unused.
•
A read value is undefined.
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23.3 DMA Controller (DMAC) Operation
A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions.
This section describes the operation of the DMAC.
■ Principal Operations
•
Functions can be set for each transfer channel independently.
•
Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has
been detected.
•
After a transfer request is detected, a DMA transfer request is output to the bus controller and the bus right is
acquired by the bus controller before the transfer is started.
•
The transfer is carried out as a sequence conforming to the mode settings made independently for the channel
being used.
■ Transfer Mode
Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its DMACB
register.
● Block/step transfer
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the
bus controller for transfer until the next transfer request is received.
The block transfer unit is the specified block size (BLK[3:0] of DMACA).
● Burst transfer
Transfer in response to one transfer request is carried out continuously for the number of times in the specified
transfer count is reached.
The specified transfer count is the transfer count (BLK[3:0] of DMACA × DTC[15:0] of DMACA) × block size.
■ Transfer Type
● 2-cycle transfer (normal transfer)
The DMA controller operates using a read operation and a write operation as its unit of operation.
Data is read from an address in the transfer source register and then written to another address in the transfer
destination register.
■ Transfer Address
The following types of addressing are available and can be set independently for each channel transfer source
and transfer destination.
The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transfer and the method for
a fly-by transfer are different.
● Specifying the address for a 2-cycle transfer
The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as the
address for access. After receiving a transfer request, DMA stores the address from the register in the temporary
storage buffer and then starts transfer.
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed
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selectable) by the address counter and then written to the temporary storage buffer. Because the contents of the
temporary storage buffer are written back to the register (DMASA/DMADA) after each block transfer unit is
completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed,
making it impossible to determine the address in real time during transfer.
■ Transfer Count and Transfer End
● Transfer count
The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer
count register becomes 0, counting for the specified transfer ends, and the transfer stops with the end code
displayed or is reactivated *.
Like the address register, the transfer count register value is updated only after each block transfer unit.
*: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register value is
initialized and then waits for transfer (DTCR of DMACB)
● Transfer end
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code
(DSS[2:0] of DMACB).
•
End of the specified transfer count (DMACA:BLK[3:0] × DMACA:DTC[15:0]) => Normal end
•
A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error
•
An address error occurred => Error
•
A reset occurred => Reset
The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is
generated.
23.3.1 Setting a Transfer Request
The following two types of transfer requests are provided to activate DMA transfer:
• Built-in peripheral request
• Software request
Software requests can always be used regardless of the settings of other requests.
■ Built-in Peripheral Request
A transfer request is generated by an interrupt from the built-in peripheral circuit.
For each channel, set the peripheral’s interrupt by which a transfer request is generated (When IS[4:0] of
DMACA=1xxxxB.)
The built-in peripheral request cannot be used together with an external transfer request.
Note:
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU, disable
interrupts from the interrupt controller (ICR register).
■ Software Request
A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).
The software request is independent of the external transfer request pin and built-in peripheral request and can
always be caused.
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If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate
output of a DMA transfer request to the bus controller.
23.3.2 Transfer Sequence
The transfer type and the transfer mode that determine, for example, the operation sequence
after DMA transfer has started can be set independently for each channel (Settings for
TYPE[1:0] and MOD[1:0] of DMACB).
■ Selection of the Transfer Sequence
The following sequence can be selected with a register setting:
•
Burst 2-cycle transfer
•
Block/step 2-cycle transfer
● Burst 2-cycle transfer
In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously for
one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/transfer
destination address.
A peripheral transfer request or software transfer request can be selected as the transfer source.
Table 23.3-1 Specifiable transfer addresses (burst 2-cycle transfer)
Transfer source addressing
Direction
Transfer destination addressing
All 32-bit areas specifiable
=>
All 32-bit areas specifiable
The following are some features of a burst transfer:
When one transfer request is received, transfer is performed continuously until the transfer count register reaches
0.
The transfer count is the transfer count × block size (BLK[3:0] of DMACA × DTC[15:0] of DMACA).
Another request occurring during transfer is ignored.
If the reload function of the transfer count register is enabled, the next request is accepted after transfer ends.
If a transfer request for another channel with a higher priority is received during transfer, the channel is switched
at the boundary of the block transfer unit. Processing resumes only after the transfer request for the other
channel is cleared.
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Figure 23.3-1 Example of burst transfer for a start on an external pin rising edge, number of blocks =1,
and transfer count = 4
Transfer request ( edge)
Bus operation
CPU
SA
Transfer count
DA
SA
4
DA
3
SA
DA
SA
2
DA
CPU
0
1
Transfer end
Figure 23.3-2 Example of demand transfer for a start with the external pin at H level, number of blocks =
1, and transfer count = 3
Transfer request (H level)
Bus operation
Transfer count
CPU
SA
DA
3
SA
DA
CPU
2
SA
DA
1
0
Transfer end
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● Step/block transfer 2-cycle transfer
For a step/block transfer (Transfer for each transfer request is performed as many times as the specified block
count), all 32-bit areas can be specified as the transfer source/transfer destination address.
Table 23.3-2 Specifiable transfer addresses (step/block transfer 2-cycle transfer)
Transfer source addressing
Direction
Transfer destination addressing
All 32-bit areas specifiable
=>
All 32-bit areas specifiable
[Step transfer]
If 1 is set as the block size, a step transfer sequence is generated.
The following are some features of a step transfer:
•
If a transfer request is received, the transfer request is cleared after one transfer operation and then the
transfer is stopped (The DMA transfer request to the bus controller is canceled).
•
Another request occurring during transfer is ignored.
•
If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched after the running transfer is stopped. After finishing the higher priority transfer the stopped transfer is
restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously.
[Block transfer]
If any value other than 1 is specified as the block size, a block transfer sequence is generated.
The following are some features of a block transfer:
•
The block transfer has the same features as those of a step transfer except that one transfer unit consists of
multiple transfer cycle counts (number of blocks).
Figure 23.3-3 Example of block transfer for a start for an external pin on a rising edge, number of blocks
= 2, and transfer count = 2
Transfer request
( rising edge)
Bus operation
Number of blocks
Transfer count
CPU
SA
DA
SA
2
DA
1
CPU
0
2
SA
DA
SA
2
DA
1
1
Transfer end
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23.3.3 General Aspects of DMA Transfer
This section describes the block size for DMA transfers and the reload operation.
■ Block Size
•
The unit and increment for transfer data is a set of (the number set in the block size specification register ×
data width) data.
•
Since the amount of data transferred in one transfer cycle is determined by the value specified as the data
width, one transfer unit is consists of the number of transfer cycles for the specified block size.
•
If a transfer request with a higher priority is received during transfer or if a temporary stop request for a
transfer occurs, the transfer stops only at the transfer unit boundary, whether or not the transfer is a block
transfer. This arrangement makes it possible to protect data for which division or temporary stopping is not
desirable. However, if the block size is large, response time decreases.
•
Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be
guaranteed.
■ Reload Operation
In this module, the following three types of reloading can be set for each channel:
● Transfer count register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer count register again
and waiting for a start request starts.
Set this type of reloading when the entire transfer sequence is to be performed repeatedly.
If reload is not specified, the count register value remains 0 after the transfer is performed the specified number of
times and no further transfer is performed.
● Transfer source address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer source address
register again.
Set this type of reloading when transfer is to be repeated from a fixed area in the transfer source address area.
If reload is not specified, the transfer source address register value after the transfer is performed the specified
number of times becomes the next address. Use this type when the address area is not fixed.
● Transfer destination address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer destination address
register again.
Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destination address area.
(The processing hereafter is the same as described in "Transfer source address register reloading" above.)
•
If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is
performed the specified number of times is not implemented and only the values of each address register are
set.
● Special examples of operating mode and the reload operation
•
If it is preferable that processing stops when data transfer ends and starts after input is detected again, do not
specify reload.
•
For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reload when data transfer
ends. Transfer does not start until new transfer request input is detected.
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23.3.4 Addressing Mode
Specify the transfer destination/transfer source address independently for each transfer channel.
■ Address Register Specifications
The following two methods are provided to specify an address register. The method specified depends on the
transfer sequence.
•
In 2-cycle transfer type, set the transfer source address in the transfer source address setting register
(DMASA) and the transfer destination address in the transfer destination address setting register (DMADA).
■ Features of the Address Register
This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed.
■ Function of the Address Register
•
The address register is read in each access operation and the read value is sent to the address bus.
•
At the same time, the address for the next access is calculated by the address counter and the address
register is updated using the calculated address.
•
For address calculation, increment or decrement is selected independently for each channel, transfer
destination, and transfer source. The address increment/decrement width is specified by the address count
size register (SASZ/DASZ of DMACB).
•
If reloading is not enabled, the address resulting from the address calculation of the last address remains in
the address register when the transfer ends.
•
If reloading is enabled, the initial value of the address is reloaded.
Notes:
•
If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address error is
detected and transfer on the relevant channel is stopped. Refer to the description for the items related to the
end code.
•
Do not set any of the DMAC’s registers as the address register.
•
Do not let the DMAC transfer data to any of the DMAC’s registers.
23.3.5 Data Types
Select the data width transferred in one transfer operation from the following:
• Byte
• Halfword
• Word
■ Data Length (Data width)
Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an
address with a different data length is specified for the transfer destination/transfer source address.
•
Byte: The actual access address and the addressing match.
•
Halfword: The actual access address has 2-byte length starting with 0 as the lowest-order bit.
•
Word: The actual access address has a 4-byte length starting with 00 as the lowest-order 2 bits.
If the lowest-order bits in the transfer source address and transfer destination address are different, the
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addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed
after the addresses are corrected according to the above rules.
23.3.6 Transfer Count Control
Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).
■ Transfer Count Control
Set the transfer count value in the transfer count register (DTC of DMACA).
The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the
transfer counter. When the counter value becomes 0, end of transfer end for the specified count is detected, and
the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).
The following are some features of the group of transfer count registers:
•
Each register has 16-bit length.
•
All registers have a dedicated reload register.
•
If transfer is activated when the register value is 0, transfer is performed 65536 times.
■ Reload Operation
•
The reload operation can be used only if reloading is enabled in a register that allows reloading.
•
When transfer is activated, the initial value of the count register is saved in the reload register.
•
If the transfer counter counts down to 0, end of transfer is reported and the initial value is read from the reload
register and written to the count register.
23.3.7 CPU Control
When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus operation
and DMA transfer starts.
■ DMA Transfer and Interrupts
•
During DMA transfer, interrupts are generally not accepted until the transfer ends.
•
If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt
processing is stopped until the transfer is completed.
•
If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level set
by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller at a
transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared. In the
meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC reissues a
transfer request to the bus controller to acquire the right to use the bus and then restarts DMA transfer.
■ Suppressing DMA
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the
DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt
requests. When all interrupt sources are cleared, the suppression feature no longer works and the DMA transfer
is restarted by the interrupt processing routine. Thus, if the restart of DMA transfer should be suppressed after
clearing interrupt sources in the interrupt source processing routine at a level that interrupts DMA transfer, the
DMA suppress function should be used. The DMA suppress function can be activated by writing any value other
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than 0 to the DMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing 0 to these bits.
This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt
processing routine are cleared, the DMA suppress register is incremented by 1. If this is done, then no DMA
transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by 1 before returning. If multiple
interrupts have occurred, DMA transfer continues to be suppressed since the DMAH[3:0] bits are not 0 yet. If a
single interrupt has occurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately.
Notes:
•
Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels.
•
Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt
levels.
23.3.8 Operation from Starting to End/Stopping
Starting of DMA transfer is controlled independently for each channel, but before transfer starts,
the operation of all channels needs to be enabled. This section describes operation from starting
to end/stopping.
■ Operation Start
● Enabling operation for all channels
Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the DMA
operation enable bit (DMAE of DMACR). All start settings and transfer requests that occurred before operation is
enabled are invalid.
● Starting transfer
The transfer operation can be started by the operation enable bit of the control register for each channel. If a
transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified mode.
● Starting from a temporary stop
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary stopped
state is maintained even though the transfer operation is started. If transfer requests occur in the meantime, they
are accepted and retained. When temporary stopping is released, transfer is started.
■ Transfer Request Acceptance and Transfer
Sampling for transfer requests set for each channel starts after starting.
If edge detection is selected for the external pin start source and a transfer request is detected, the request is
retained within DMAC until the clear conditions are met (when the external pin start source is selected for block,
step, or burst transfer).
If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the
transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer
unit (peripheral interrupt start).
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the interrupts.
Transfer requests are always accepted while other channel requests are being accepted and transfer performed.
The channel that will be used for transfer is determined for each transfer unit after priority has been checked.
■ Clearing Peripheral Interrupts by DMA
This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is
selected as the DMA start source (when IS[4:0]=1xxxxB).
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Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0]
are cleared.
The timing for clearing an interrupt depends on the transfer mode (See Section 23.4"Operation Flowcharts").
•
Block/step transfer: If block transfer is selected, a clear signal is generated after one block (step) transfer.
•
Burst transfer: If burst transfer is selected, a clear signal is generated after transfer is performed the specified
number of times.
■ Temporary Stopping
DMA transfer is stopped temporary in the following cases:
● Setting of temporary stopping by writing to the control register (Set independently for each channel
or all channels simultaneously)
If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until
release of temporary stopping is set again. The DSS bits for temporary stopping can be checked.
● Hold suppress level interrupt processing
If an interrupt request with a higher level than the hold suppress level occurs, all channels on which transfer is in
progress are temporarily stopped at the boundary of the transfer unit and the bus right is returned to give priority
to interrupt processing. Transfer request accepted during interrupt processing are retained, initiating a wait for
completion of interrupt processing.
Channels for which requests are retained restart transfer after interrupt processing is completed.
■ Operation End/Stopping
The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for
all channels at once.
● Transfer end
If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests
are disabled after the transfer count register becomes 0 (Clear the DENB bit of DMACA).
If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait for
transfer requests starts after the transfer count register becomes 0 (Do not clear the DENB bit of DMACA).
● Disabling all channels
If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations,
including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again,
no transfer is performed unless a channel is restarted. In this case, no interrupt whatever occurs.
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■ Stopping Due To an Error
In addition to normal end after transfer for the number of times specified, stopping as the result of various types of
errors and the forced stopping are provided. (See "[Bit 18 to bit 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop
source indication" on P. 257)
● Transfer stop requests from peripheral circuits
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an
error is detected (Example: Error when data is received at or sent from a communications system peripheral).
The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the end code and
stops the transfer on the corresponding channel.
Table 23.3-3 Stopping due to an Error
IS
EIS
Function
Transfer stop request
10110B
11000B
0000B
0000B
LIN-USART 0 RX *1
LIN-USART 1 RX *1
Yes
Yes
10000B
10010B
10100B
10110B
0011B
0011B
0011B
0011B
LIN-USART 0 RX *1
LIN-USART 1 RX *1
LIN-USART 2 RX *1
LIN-USART 3 RX *1
Yes
Yes
Yes
Yes
others
others
None
*1 : A transfer stop request is issued when an error is detected
For details of the conditions under which a transfer stop request is generated, see the specifications for each
peripheral circuit.
■ Occurrence of an Address Error
If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is
detected (if an overflow or underflow occurs in the address counter when a 32-bit address is specified).
If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the
corresponding channel is stopped. (See "[Bit 18 to bit 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source
indication" on P. 257)
23.3.9 DMAC Interrupt Control
Independent of peripheral interrupts that become transfer requests, interrupts can also be output
for each DMAC channel.
■ DMAC Interrupt Control
The following interrupts can be output for each DMAC channel:
•
Transfer end interrupt: Occurs only when operation ends normally.
•
Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral)
•
Error interrupt: Occurrence of address error (error due to software)
All of these interrupts are output according to the meaning of the end code.
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An interrupt request can be cleared by writing 000B to DSS2 to 0 (end code) of DMACS. Be sure to clear the end
code by writing 000B before restarting.
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not cleared
and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the order of priority is
displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to the
displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
•
Reset
•
Clearing by writing 000B
•
Peripheral stop request
•
Normal end
•
Stopping when address error detected
•
Channel selection and control
■ DMA Transfer during SLEEP
•
The DMAC can also operate in SLEEP state.
•
If there are operations during SLEEP state anticipated, the following should be noticed:
Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before SLEEP state is entered.
The SLEEP state is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start
source, interrupts must be disabled by the interrupt controller.
•
If the SLEEP state should not be released with a DMAC end interrupt, disable these interrupts.
23.3.10 Channel Selection and Control
Up to five channels can be simultaneously set as transfer channels. In general, an independent
function can be set for each channel.
■ Priority Among Channels
Since DMA transfer is possible only on one channel at a time, priority must be set for the channels.
Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group
(described later).
● Fixed mode
The order of priority is fixed by channel number, with priority decreasing from channel 0 to channel 4:
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the channel
with the higher priority when the transfer for the transfer unit (number set in the block size specification register ×
data width) ends.
When higher priority transfer is completed, transfer is restarted on the previous channel.
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Figure 23.3-4 Timing Example in Fixed Mode
ch0 transfer request
ch1 transfer request
Bus operation
CPU
SA
Transfer ch
DA
SA
ch1
DA
ch0
SA
DA
ch0
SA
DA
CPU
ch1
ch0 transfer end
ch1 transfer end
● Rotation mode (ch.0 to ch.1 only)
When operation is enabled, the initial states have the same order that they would have in fixed mode, but at the
end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer request is
output at the same time, the channel is switched after each transfer unit.
This mode is effective when continuous or burst transfer is set.
Figure 23.3-5 Timing Example in Rotation Mode
ch0 transfer request
ch1 transfer request
Bus operation
CPU
Transfer ch
SA
DA
SA
ch1
DA
ch0
SA
DA
ch1
SA
DA
CPU
ch0
ch0 transfer end
ch1 transfer end
■ Channel Group
The order of priority is set as shown in the following table.
MODE
Priority
Remarks
Fixed
ch0 > ch1
−
ch0 > ch1
Rotation
ch0 < ch1
CM44-10149-1E
The initial state is the top row.
If transfer occurs for the top row, the priority
is reversed.
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MB91460N series
23.3.11 Supplement on Internal Operation Timing
This section provides supplementary information about internal operation timing.
■ If Another Transfer Request Occurs During Block Transfer
No request is detected before the transfer of the specified blocks is completed. At the block boundaries, transfer
requests accepted at that time are evaluated and then transfer on the channel with the highest priority is
performed.
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Chapter 23 DMA Controller
23.4
MB91460N series
23.4 Operation Flowcharts
This section contains operation flowcharts for the following transfer modes:
• Block transfer
• Burst transfer
■ Block Transfer
Figure 23.4-1"Operation Flowchart for Block Transfer" shows the flowchart for block transfer.
Figure 23.4-1 Operation Flowchart for Block Transfer
DMA stop
DENB=>0
DENB=1
Reload enable
Activation request
wait
Activation request
Load the initial address,
transfer count, and number
of blocks
Calculate the address for
transfer source address access
One-time access for fly-by
Calculate the address for transfer
destination address access
Number of blocks - 1
BLK=0
Transfer count - 1
Write back the address,
transfer count, and
number of blocks
Only when the peripheral
interrupt activation source
is selected
Interrupt clear
Interrupt cleared
DTC=0
DMA transfer end
DMA interrupted
Block transfer
- Can be activated by all activation sources (selection).
- Can access to all areas.
- The number of blocks can be set.
- Interrupt clear is issued when transfer of the specified
number of blocks is completed.
- The DMA interrupt is issued when transfer for the number
of times specified is completed.
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■ Burst Transfer
Figure 23.4-2"Operation Flowchart for Burst Transfer" shows the operation flowchart for burst transfer.
Figure 23.4-2 Operation Flowchart for Burst Transfer
DMA stop
DENB=>0
DENB=1
Reload enable
Activation request
wait
Load the initial address,
transfer count, and
number of blocks
Calculate the address for
transfer source address access
One-time access for fly-by
Calculate the address for transfer
destination address access
Number of blocks - 1
BLK=0
Transfer count - 1
DTC=0
Write back the address,
transfer count, and number
of blocks
Only when the peripheral interrupt
activation source is selected
Interrupt clear
Interrupt cleared
DMA transfer end
DMA interrupted
Burst transfer
- Can be activated by all activation sources (selection).
- Can access to all areas.
- The number of blocks can be set.
- Interrupt clear and the DMA interrupt are issued when
transfer for the number of times specified is completed.
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Chapter 23 DMA Controller
23.5
MB91460N series
23.5 Data Bus
This section shows the flow of data during 2-cycle transfer and fly-by transfer.
■ Flow of Data During 2-Cycle Transfer
Figure 23.5-1 shows examples of six types of transfer during 2-cycle transfer.
Figure 23.5-1 Examples of 2-Cycle Transfer (Continued on next page)
Built-in I/O area => internal RAM area transfer
MB91460N series
MB91460N series
DMAC
D-bus
Data buffer
RAM
M-bus
I-bus
Harvard/Princeton
bus converter
CPU
CPU
I-bus
DMAC
Read cycle
M-bus
Read cycle
Harvard/Princeton
bus converter
D-bus
Data buffer
I/O
RAM
I/O
Internal RAM area => built-in I/O area transfer
MB91460N series
MB91460N series
DMAC
DMAC
D-bus
Data buffer
RAM
CM44-10149-1E
M-bus
I-bus
Harvard/Princeton
bus converter
CPU
CPU
I-bus
Read cycle
M-bus
Read cycle
Harvard/Princeton
bus converter
D-bus
I/O
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Data buffer
RAM
I/O
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Chapter 24 Delayed Interrupt
24.1
MB91460N series
Chapter 24 Delayed Interrupt
24.1 Overview
The delayed interrupt, or the delayed interrupt module is used to generate an interrupt for task switching.
Figure 24.1-1 Block diagram of delayed Interrupt
Delay interrupt
control circuit
Software request
Interrupt request (#63)
24.2 Features
• Type: Interrupt request bit (There is no interrupt request enable bit)
• Quantity: 1
• Other:
• The software generates/releases interrupt request.
• Real time OS (REALOS) uses the delayed interrupt for task switching.
24.3 Configuration
Figure 24.3-1 Configuration diagram of delayed interrupt
Delay interrupt
Delay interrupt control bit
DLYI
DICR: bit 0
Read
Write
0
Without interrupt
0
Delay interrupt release
1
With interrupt
1
Delay interrupt request
Interrupt request (#63)
Delay interrupt control circuit
Figure 24.3-2 List of Registers
Delayed interrupt
Address
000038H
Bit
7
---
6
---
5
---
4
---
3
---
2
---
1
---
000457H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR23
(Interrupt level)
00046FH
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR47
(Interrupt level)
Address
0FFF00H
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0
DLYI
DICR
32Bits
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(Delayed interrupt control)
(Interrupt vector #63)
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24.4
MB91460N series
24.4 Register
24.4.1 DICR: Delayed Interrupt Control Register
This register controls to generate/clear the delayed interrupt.
• DICR: Address 000038H (Access: Byte)
7
–
–
RX/WX
6
–
–
RX/WX
5
–
–
RX/WX
4
–
–
RX/WX
3
–
–
RX/WX
2
–
–
RX/WX
1
–
–
RX/WX
0
DLYI
0
R/W
bit
Initial value
Attribute
(Refer to "Meaning of Bit Attribute Symbols (Page No.11)" for the attributes.)
• Bit7 to bit1: Undefined:
Writing does not affect operation. The read value is undefined.
• Bit0: Delayed interrupt control bit
DLYI
0
1
Read operation
No delayed interrupt request
Delayed interrupt request
Write operation
Delayed interrupt request clear
Delayed interrupt request generation
24.5 Operation
Figure 24.5-1 Delayed interrupt service
Preference interrupt
(4)
Delay
(5)
Delayed interrupt
(6) (7)
Task A
OS
Task B
(1) A task dispatch request is generated.
(2) Setting for the dispatch destination (Delay return destination)
(3) Setting for the delayed interrupt request (Generating)
(1)
(2)
(3)
(4)
In OS, a request for task B dispatch is generated
OS sets the delayed interrupt return destination (dispatch destination)
OS sets the delayed interrupt (delayed interrupt request generation)
When OS returns, the interrupt with the highest priority sequence takes place, because an interrupt service is
prohibited in OS
(5) When the interrupt with the highest priority is completed, delayed interrupt takes place
(6) In delayed interrupt, delayed interrupt is released
(7) Returned from the delayed interrupt (dispatched to task B)
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24.6
MB91460N series
24.6 Setting
Table Setting required for the delayed interrupt generation/clear
Table 24.6-1 Setting required for the delayed interrupt generation/clear
Setting
Vector for delayed interrupt
Delayed interrupt setting.
Generating interrupt request/Releasing interrupt request
Setting register
Refer to "Chapter 21 Interrupt Control (Page No.219)"
Delayed interrupt control register
(DICR)
Setting method*
Refer to 24.7.1
Refer to 24.7.2
*: Refer to the number for the setting method.
24.7 Q & A
24.7.1 What are interrupt-associated registers?
Setting for the delayed interrupt vector and interrupt level
The relationship between the delayed interrupt level and the delayed interrupt vector is shown in the following
table.
Refer to "Chapter 21 Interrupt Control (Page No.219)" for more information on the interrupt level and interrupt
vector.
Interrupt vector (default)
#63
Address: 0FFF00H
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR23)
Address: 000457H
The interrupt request bit (DICR:DLYI) cannot automatically be released, and it should be released by the
software before returning from an interrupt service. ("0" is written for DLYI bit)
Remark: For REALOS compatibility reasons, ICR23 and ICR47 can be exchanged by setting the REALOS
compatibility bit (addr 000C03H : IOS[0]) if necessary.
24.7.2 How is the interrupt request generated/cleared?
The delayed interrupt request bit (DICR:DLYI) performs this function.
Clearing an interrupt request
Generating an interrupt request
Delayed interrupt control bit (DLYI)
Sets the value to "0"
Sets the value to "1"
The delayed interrupt does not have an interrupt request enable bit.
24.8 Caution
• The delayed interrupt request bit is the same as general interrupt flags. It should be used to clear delayed
interrupt request bit in an interrupt routine in addition to switching tasks.
• The delayed interrupt function is used by real time OS (REALOS). As a result, the delayed interrupt function
is prohibited in a piece of user software when using real time OS.
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Chapter 25 Bit Search
25.1
MB91460N series
Chapter 25 Bit Search
25.1 Overview
The bit search module is used to detect the first "0" position, the first "1" position or the first changing position
for data written in specific registers.
Figure 25.1-1 Block diagram of the Bit search module
Detection
circuit
(0-position,
1-pos. and
changing
position)
0-position register
1-position register
Result register
Changing-pos. register
25.2 Features
• Function: Detects the first position ("1"-position, "0"-position or changing position) by scanning data written in
data register from MSB to LSB.
• 0 detection :
Detects the first "0" position.
• 1 detection :
Detects the first "1" position.
• Changing position detection :
Detects the first position where data changes from "0" to "1" or vice
versa.
• Quantity: 1
• Other: Internal data can be read.
(This function can be used to restore the previous state, when it is used in bit search during an
interrupt service or interrupt processing routine.)
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25.3
MB91460N series
25.3 Configuration
Figure 25.3-1 Configuration Diagram of the bit search module
Detection mode selection
Bit search
Address decoder
0-/1-/Changing-position-detection
data register
Write only
Lowest four bits
of the address
Operation selection
for BSD0/BSD1/BSDC
0000
0100
0-detection
1000
Changing-position-detection
1-detection
BSD0/ BSD1/ BSDC
Detection result
Run only
Detection data (BSD1)
Detection circuit
(0-/1-/Changing-positions)
BSRR
Figure 25.3-2 List of Registers
Bit search
Address
0003F0H
32Bits
BSD0
(0 detection data)
0003F4H
32Bits
BSD1
(1 detection data)
0003F8H
32Bits
BSDC
(Changing point detection data)
0003FCH
32Bits
BSRR
(Detection result)
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Chapter 25 Bit Search
25.4
MB91460N series
25.4 Register
25.4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing
position Detection Data Register
This is a register for setting the bit search detection data.
• BSD0: Address 0003F0H (Access: Word)
• BSD1: Address 0003F4H (Access: Word)
• BSDC: Address 0003F8H (Access: Word)
31
0
BSD0
Indefinite
W
31
Initial value
Attribute
0
BSD1
Indefinite
R,W
31
bit
Initial value
Attribute
0
BSDC
Indefinite
W
bit
bit
Initial value
Attribute
(For the attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• Write data used to detect 0, 1 and changing position in each of the registers BSD0, BSD1 and BSDC.
• The result is stored in the detection result register BSRR.
• During 0 detection, the position where "0" is first detected is stored for data written in the order of
MSB(bit31) to LSB(bit0).
• During 1 detection, the position where "1" is first detected is stored for data written in the order of
MSB(bit31) to LSB(bit0).
• During change position detection, the position where a value different from MSB(bit31) is first detected is
stored for data written in the order of bit31 to LSB(bit0).
• The register BSD0 used for 0 detection and the BSRC register used for changing position detection are
write-only. The value during read operation is indefinite.
• Data saved in the bit search can be read if the register BSR1 used to detect 1 is read.
Previous detection result can be restored by re-writing previously read data in the BSR1 used for detecting
1. This applies to the processes for the 0 detection and the changing position detection.This function can be
used to restore a specific state when using a bit search in processing such as interrupt handler.
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MB91460N series
25.4.2 BSRR: Detection Result Register
This register is used to read a bit search result.
• BSRR: Address 0003FCH (Access: Word)
31
0
BSRR
Indefinite
R
bit
Initial value
Attribute
(For the attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• Detection result for data written in the 0 detection register BSD0, the 1-detection register BSD1 and the
changing-position-detection register BSDC can be read. Data last written can be read. However, the type of
result cannot be identified: Information on 0 detection,1 detection or changing position detection is not
included.
A 0 can be read at detection position bit31(MSB), and continues reading 31 at detection position bit0(LSB)
by adding 1 at the next position toward bit0(LSB). A value of 32 is read when not detected.
• The detection result register is read-only, and a write operation has no effect.
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Chapter 25 Bit Search
25.5
MB91460N series
25.5 Operation
25.5.1 Zero detection
Figure 25.5-1 Example of zero detection
Bit position from MSB
11111111111111112
0123456789ABCDEF0123456789AB CDEF0
Data
11111111110000000000000000000000
Scan
>>>>>>>>>>0
AH (10 Decimal)
Detection result
(1) Bit position from MSB
(2) Written data (Starts to search once data is written.)
(3) Detects "0" by scanning from MSB.
(4) Detected bit position
(5) Detection result
If "0" does not exist (That is, numeric value is FFFFFFFFH), "32" is returned as detection result.
• Execution example
Write data
11111111111111111111000000000000B (FFFFF000H)
11111000010010011110000010101010B (F849E0AAH)
10000000000000101010101010101010B (8002AAAAH)
11111111111111111111111111111111B (FFFFFFFFH)
→
→
→
→
Read value (Decimal notation)
20
5
1
32
25.5.2 One Detection
Figure 25.5-2 Example of one detection
Bit position from MSB
11111111111 111112
0123456789AB CDEF0123456789ABCDEF0
00000000000000000011111111111111
Data
Scan
>>>>>>>>>>>>>>>>>>1
Detection result
12 H (18Decimal)
(1) Bit position from MSB
(2) Written data (Detection operation starts once data is written.)
(3) Detect "1" scan starting with the MSB.
(4) Detected bit position
(5) Detection result
If "1" does not exist (That is, if numeric value is 00000000H), value of "32" is returned as detection result.
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MB91460N series
• Execution example
Write data
00100000000000000000000000000000B (20000000H)
00000001001000110100010101100111B (01234567H)
00000000000000111111111111111111B (0003FFFFH)
00000000000000000000000000000001B (00000001H)
00000000000000000000000000000000B (00000000H)
→
→
→
→
→
Read value (Decimal notation)
2
7
14
31
32
25.5.3 Changing Position Detection
Figure 25.5-3 Example of changing position detection
Bit position from MSB
11111111111111112
0123456789AB CDEF0123456789ABCDEF0
00000000000000011100000000000000
Data
Scan
>>>>>>>>>>>>>>>*
Detection result
F H (15Decimal)
(1) Bit position from MSB
(2) Written data (Detection starts once data is written.)
(3) Detects the changing position by scanning from MSB.
(4) Detected bit position
(5) Detection result
A value of "32" is returned as detection result if changing position does not exist.
A value of "0" is not returned as detection result for changing position detection.
• Execution example
Write data
00100000000000000000000000000000B (20000000H)
00000001001000110100010101100111B (01234567H)
00000000000000111111111111111111B (0003FFFFH)
00000000000000000000000000000001B (00000001H)
00000000000000000000000000000000B (00000000H)
11111111111111111111000000000000B (FFFFF000H)
11111000010010011110000010101010B (F849E0AAH)
10000000000000101010101010101010B (8002AAAAH)
11111111111111111111111111111111B (FFFFFFFFH)
→
→
→
→
→
→
→
→
→
Read value (Decimal notation)
2
7
14
31
32
20
5
1
32
Table 25.5-1 The Relationship Between the Bit Position and the Value to be Returned (Decimal Notation)
Detected
bit position
31
30
29
28
27
26
25
24
288
Return
value
0
1
2
3
4
5
6
7
Detected
bit position
23
22
21
20
19
18
17
16
Return
value
8
9
10
11
12
13
14
15
Detected
bit position
15
14
13
12
11
10
9
8
Return value
16
17
18
19
20
21
22
23
Detected
bit position
7
6
5
4
3
2
1
0
Nonexistent
FUJITSU MICROELECTRONICS LIMITED
Return value
24
25
26
27
28
29
30
31
32
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Chapter 25 Bit Search
25.6
MB91460N series
25.6 Setting
Table 25.6-1 Settings Required for "Zero" Position Detection
Setting
Data write & scan start
Converted value read
Setting register
"Zero" position detection data register (BSD0)
Detection result register (BSRR)
Setting method *
Refer to 25.7.1
Refer to 25.7.2
*: For detailed description contents, refer to the reference destination number.
Table 25.6-2 Setting Required for Using "One" Position Detection
Setting
Data write & scan start
Converted value read
Setting register
"One" position detection data register (BSD1)
Detection result register (BSRR)
Setting method *
Refer to 25.7.1
Refer to 25.7.2
*: For detailed description contents, refer to the reference destination number.
Table 25.6-3 Setting Required for Using Changing Position Detection
Setting
Data write & scan start
Converted value read
Setting register
Changing position detection data register (BSDC)
Detection result register (BSRR)
Setting method *
Refer to 25.7.1
Refer to 25.7.2
*: For detailed description contents, refer to the reference destination number.
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25.7
MB91460N series
25.7 Q & A
25.7.1 How is data written?
Writes data with the detection data registers (BSD0, BSD1, BSDC).
Operation mode
"Zero" position detection write
"One" position detection write
Changing position detection write
Detection data register
Writes data in (BSD0)
Writes data in (BSD1)
Writes data in (BSDC)
25.7.2 How is scanning started?
Scanning is started once data is written in the detection data registers (BSD0, BSD1, BSDC).
25.7.3 How is a result read?
The detection result register (BSRR) is read.
25.7.4 How is the previous bit search state restored?
The following restoration processes are performed.
If the previous bit search state should be restored after a bit search has been executed in an interrupt handler.
1) Reads data from the one detection data register, and saves the contents. (evacuation)
2) The Bit search is used.
3) Writes data evacuated in Item 1) in the one detection data register. (restoration)
Using the above procedures, the value to be read next from the detection result register is the one that was
written in the bit search executed in 1) or before.
The bit search state can be correctly restored using the above procedures even if the 0-detection, 1-detection
or changing-position-detection data register has been written last.
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Chapter 25 Bit Search
25.8
MB91460N series
25.8 Caution
The following are the remarks on using the bit search module.
• The macros are for REALOS(OS), and the user cannot use them when using REALOS.
• If the relevant detection is not found, a detection result of 32(decimal) is returned.
• A value of "0" is not returned for the changing position detection.
• The data registers (0-detection/1-detection/ changing-position-detection) is a write-only, and accessed by
word.
However, the 1-detection read address is assigned to an internal data register for restoration so that
restoring previous bit search state is possible. (Refer to "25.7.3 How is a result read? (Page No.290)".)
• The 0-detection register BSD0, 1-detection register BSD1 and changing-position-detection register BSDC
are included in one register in terms of the structure. The operation is selected with the lowest four bits of the
accessing address.
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Chapter 26 MPU / EDSU
26.1
MB91460N series
Chapter 26 MPU / EDSU
26.1 Overview
Memory Protection Unit (MPU) and Embedded Debug Support Unit (EDSU) for MB91460N series.
Remark: The MPU/EDSU module features a clock disable function. For enabling the MPU/EDSU module it
is necessary to set the EDSUEN bit in the CSCFG register. See chapter "CSCFG: Clock Source Configuration Register (Page No.135)" for further information.
The features are scalable in units of "Comparator Groups". The number of this Groups can be defined from one to
two. Features of one Comparator Group are listed below:
•
A total number of 4 Breakpoints, could be programmed to:
— 4 Instruction Address Breakpoints
— 4 Operand Address Breakpoints (programmable on datasize and access type)
— 2 Operand Address Breakpoints and 2 Instruction Address Breakpoints
— 2 Operand Address Breakpoints and 2 Data Value Breakpoints
•
2 Masks possible to assign (reduces the number of breakpoints)
•
2 Range Functions
•
Break Trigger programmable on resource interrupts
•
MPU functionality
— User and Supervisor permission for read/write/execute
— Default permissions for the whole MCU address range
— Permission definition for two address ranges per Comparator Group
(2 Groups result in 4 MPU Channels)
— Can detect DMA accesses on the D-Bus and Resource address regions
— Register set is locked in User mode
— Dynamic configuration possible, privileged configuration with INT #5 is not interruptible
— A permission violation causes an MPUPV trap
•
Capture register for Instruction Address and Operand Address (for MPU and Operand Break)
•
Capture information for MPU channel index, DMA flag, Operand Size and Access Type
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26.1
MB91460N series
Figure 26.1-1 EDSU block diagram
BCR1
BCR1
OBS1
OBS−Match
BAD7
Point 3
BAD6
Point 2
IA/OA
BD3
BD7
Mask 1
CMP1
BD2
BD6
CTC
IA
OA
Value
BAD5
Point 1
BAD4
Point 0
IA/OA/DT
BD1
BD5
Mask 0
CMP0
BD0
BD4
CTC
IA
OA
DT
Value
BCR0
BCR0
OBS0
OBS−Match
BAD3
Point 3
BAD2
Point 2
IA/OA
BD3
BD3
Mask 1
CMP1
BD2
BD2
CTC
IA
OA
Break Detection Evaluation
Comparator GROUP 1
Value
Comparator GROUP 0
294
Point 1
BAD0
Point 0
IA/OA/DT
BD1
BD1
Mask 0
CMP0
BD0
BD0
CTC
IA
OA
DT
BAD1
Value
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Chapter 26 MPU / EDSU
26.2
MB91460N series
26.2 Features
One Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparators with
the option to use two point registers as mask information. The following features could be partially mixed-up:
4 Instruction Address Breakpoints
Up to 4 instruction address breakpoints can be defined.
Two instruction breakpoints can be masked. The other two registers can operate as mask registers then. Also maskable is a break address range made with two points and one mask register.
Two absolute address ranges for instruction breakpoints can be defined where 2 or 4 out of 4 instruction breakpoint
registers are assigned for the range.
4 Operand Address Breakpoints
Up to 4 operand address breakpoints can be defined.
Two operand breakpoints can be masked. The other two registers can operate as mask registers then. Also maskable is a break address range made with two points and one mask register.
Two absolute address ranges for operand breakpoints can be defined where 2 or 4 out of 4 operand breakpoint
registers are assigned for the range.
Operand breaks can be selected for datasizes: byte, halfword and word on access types: read, read-modify-write
and write.
2 Operand Data Value Breakpoints
Up to 2 operand data value breakpoints can be defined.
The definition of one data value range is possible.
One data value breakpoint can be masked by defining the other point as mask register.
The Operand Address and Data Value Breakpoints can be switched to a combined trigger condition.
Memory protection
Two channels/ranges could be defined to operate in memory protection mode.
Possible is the protection of two Operand Address ranges, two Instruction Address Ranges or a combination of one
Operand and one Instruction Address range.
Read/write or execute permission could be defined for each channel, both for the normal User and the Supervisor
mode.
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26.3 Break Functions
26.3.1 Instruction address break
The instruction address point break is the most basic break that occurs when an instruction is fetched at the address
specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to
"00" provides this mode. The bits EP[3:0] in BCR0 enable the break points.
Up to 4 instruction breakpoints from channels 0 to 3 can be set. All instruction break events are combined ( logical
OR) into instruction break exception requests to the CPU.
2 of the break address registers can operate as mask registers (BAD0, BAD2) for masking the instruction address
which is being fetched. Mask register BAD0 can be assigned either to BAD1 (same channel) or BAD2/3 (opposite
channel), mask register BAD2 can be assigned either to BAD3 or BAD0/1.
Normally Instruction break address and mask information reside in the same channel. So BAD3 contains the instruction break address and BAD2 the address mask information. The channel is enabled with EP3. The same applies for channel BAD1 (address), BAD0 (mask) and EP1 (enable).
But some cases require enabling point 2 (EP2) or the range function (ER1). Then BAD2 holds Instruction Address
information and could not carry the address mask. In that cases (when EP2 or ER1 are set) the mask information
is taken from the opposite BAD0 register. The same applies for EP0 and ER0 - which enables the use of the opposite BAD2 register for the mask information.
Example:
CTC
00
Type: Instruction Address Break
EP1
1
Enable break point address BAD1
EM0
1
Set mask BAD0 for break address BAD1
BAD1
12345678H
Set break address
BAD0
00000FFFH
Set break mask
Break occurs at 12345000H to 12345FFFH
On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt register BIRQ will be set to "1". They have
to be reset by software in the instruction break routine.
Channels 0 and 1 (BAD0, BAD1) can be set up to function as address range match. Setting the ER0 bit of the control
register BCR0 to "1" provides this mode. BAD0 is the lower address and BAD1 is the upper address for address
comparison. In this mode the mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled
by EM0 = 1.
Alternatively channels 2 and 3 (BAD2, BAD3) can be set up to function as address range match. Setting the ER1
bit of the control register BCR0 to "1" provides this mode. BAD2 is the lower address and BAD3 is the upper address
for address comparison. In this mode the mask register BAD0 will mask both channels 2 and 3, if the mask feature
is enabled by EM1 = 1.
Example:
CTC
00
Type: Instruction Address Break
EP0
1
Enable break point on BAD0
EP1
1
Enable break point on BAD1
ER0
1
Enable address range function on BAD0, BAD1
EM0
1
Enable address mask function on BAD0, BAD1
BAD0
12345200H
Set lower break address
BAD1
12345300H
Set upper break address
BAD2
F0000000H
Set break mask
Break occurs at 02345200H to 02345300H,or
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at 12345200H to 12345300H,or
at 22345200H to 22345300H, etc.
The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has occured.
Table 26.3-1 Instruction Break Detection Status Bits (BD)
BD1
BD0
0
1
Match on point (instruction address == 12345200H), or
Match on point (instruction address == 22345200H), etc
1
0
Match on point (instruction address == 12345300H), or
Match on point (instruction address == 22345300H), etc
1
1
Match on range (12345200H < instruction address < 12345300H), or
Match on range (22345200H < instruction address < 22345300H), etc
In the instruction address break mode the following important point has to be considered:
To precisely determine the instruction address where a break occurs, use the PC value saved on the stack during
entry to the instruction break interrupt service routine.
26.3.2 Operand address break
The operand break function causes a break for the data access address which can be specified by the operand
address break registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to "01" provides this mode.
The bits EP[3:0] in BCR0 enable the break points.
Up to 4 breakpoints from channels 0 to 3 can be set. All operand break events are combined (logical OR) into a
operand break exception interrupt request to the CPU.
For the address mask function the same applies, what is stated in section 26.3.1 for the Instruction Address Break.
Example:
CTC
01
Type: Operand Address Break
EP1
1
Enable break point address BAD1
EM0
1
Set mask BAD0 for break address BAD1
BAD1
12345678H
Set break address
BAD0
00000FFFH
Set break mask
Break occurs at 12345000H to 12345FFFH
On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt register BIRQ will be set to "1". They have
to be reset by software in the operand break exception routine.
Channels 0 and 1 (BAD0, BAD1) can be set up to function as address range match. Setting the ER0 bit of the control
register BCR0 to "1" provides this mode. BAD0 is the lower address and BAD1 is the upper address for address
comparison. In this mode the mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled
by EM0 = 1.
Alternatively channels 2 and 3 (BAD2, BAD3) can be set up to function as address range match. Setting the ER1
bit of the control register BCR0 to "1" provides this mode. BAD2 is the lower address and BAD3 is the upper address
for address comparison. In this mode the mask register BAD0 will mask both channels 2 and 3, if the mask feature
is enabled by EM1 = 1.
Example:
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CTC
01
Type: Operand Address Break
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EP0
1
Enable break point on BAD0
EP1
1
Enable break point on BAD1
ER0
1
Enable address range function on BAD0, BAD1
EM0
1
Enable address mask function on BAD0, BAD1
BAD0
12345200H
Set lower break address
BAD1
12345300H
Set upper break address
BAD2
F0000000H
Set break mask
Break occurs at 02345200H to 02345300H,or
at 12345200H to 12345300H,or
at 22345200H to 22345300H, etc.
The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has occured.
Table 26.3-2 Operand Break Detection Status Bits (BD)
BD1
BD0
0
1
Match on point (operand address == 12345200H), or
Match on point (operand address == 22345200H), etc
1
0
Match on point (operand address == 12345300H), or
Match on point (operand address == 22345300H), etc
1
1
Match on range (12345200H < operand address < 12345300H), or
Match on range (22345200H < operand address < 22345300H), etc
The access data length and read/write break attributes can also be specified by the control register BCR0, bits
OBS[1:0] and OBT[1:0]. When the mask function is disabled by setting EM1 = EM0 = 0 (all bits effective), the relationship between breakpoint setting, and break by access address is shown below:
Table 26.3-3 Operand size and operand address relations
Access data
length
8 bit
16 bit
298
Access
address
Address set in BOA0, BOA1
4n + 0
4n + 1
4n + 2
4n + 3
4n + 0
Hit
-
-
-
4n + 1
-
Hit
-
-
4n + 2
-
-
Hit
-
4n + 3
-
-
-
Hit
4n + 0
Hit
Hit
-
-
4n + 1
Hit
Hit
-
-
4n + 2
-
-
Hit
Hit
4n + 3
-
-
Hit
Hit
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Table 26.3-3 Operand size and operand address relations
Access data
length
32 bit
Access
address
Address set in BOA0, BOA1
4n + 0
4n + 1
4n + 2
4n + 3
4n + 0
Hit
Hit
Hit
Hit
4n + 1
Hit
Hit
Hit
Hit
4n + 2
Hit
Hit
Hit
Hit
4n + 3
Hit
Hit
Hit
Hit
In Operand address break mode the Operand Address, causing the break is captured in the BOAC register. Additional BIAC holds the instruction address of the instruction, which was executed one cycle before the break causing
data operation. This is normally the instruction, which has caused the data transfer.
In the operand address break mode the following important points have to be considered:
1) In the FR family architecture, if data access is performed with misalignment, the lower address bit 0 will be ignored
for halfword and the lower address bits 0 and 1 for word access. The mask register could be programmed accordingly.
2) The EDSU operand break does not always occur immediately after completion of execution of the instruction
causing the break event.
3) Please see also information at chapter 26.3.4 Using operand with data break
26.3.3 Data value break
The data value break causes a break if specified data is read or written at a data access to an address specified by
the CPU. The data can be specified by the data value break registers BAD0 and BAD1. Setting the CTC[1:0] bits
of the control register BCR0 to "11" provides this mode. The bits EP0 and EP1 in BCR0 enable the break condition.
Up to 2 break points from channels 0 to 1 can be set. All data value break events are combined (logical OR) into a
operand break exception to the CPU.
1 mask register (BAD0) is available for masking the data value (stored in BAD1) and 1 mask register (BAD2) is available for masking the operand address (BAD3) which is being accessed. Mask registers BAD2 and BAD0 can be
enabled with EM1 and EM0.
The data on which a break should be executed must be masked by a data-mask on the bus, requiring 32-bit setting
considering the address and data length (see table below). This is required due to the byte position of the operand
is dependent from the operand address. The setting of data length of the control register BCR0 OBS[1:0] could be
configured to all ignored. The data length is controllable by mask setting to the BAD0 register implicitly.
On break at BAD[1:0] the respective flags BD[1:0] in the break interrupt register BIRQ will be set to "1". They have
to be reset by software in the operand break exception routine.
In Operand data value break mode the Operand Address, causing the break is captured in the BOAC register. Additional BIAC holds the instruction address of the instruction, which was executed one cycle before the break causing data operation. This is normally the instruction, which has caused the data transfer.
In the data value break mode the following important points have to be considered:
1) The data value break is also executed for matching DMA transfers. This could lead to unexpected behaviour due
to parallel processes. The filter bits FDMA and FCPU could be set for dedicated investigations.
2) The EDSU data break does not always occur immediately after completion of execution of the instruction causing
the break event.
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3) Please see also information at chapter 26.3.4 Using operand with data break
Table 26.3-4
Access data
length
8 bit
16 bit
32 bit
Address set
to BAD3/2
MASK set to BAD0
Position of valid
data in BAD1/0
(indicated by *)
4n + 0
00FFFFFFH
**-- ----
4n + 1
FF00FFFFH
--** ----
4n + 2
FFFF00FFH
---- **--
4n + 3
FFFFFF00H
---- --**
4n + 0
0000FFFFH
**** ----
4n + 1
0000FFFFH
**** ----
4n + 2
FFFF0000H
---- ****
4n + 3
FFFF0000H
---- ****
4n + 0
00000000H
**** ****
4n + 1
00000000H
**** ****
4n + 2
00000000H
**** ****
4n + 3
00000000H
**** ****
Remarks
Possibly intended to
use address mask in
BAD3 for address
bit 0
Possibly intended to
use address mask in
BAD3 for address
bits 1 and 0;
Data mask not
required, two channels could be used
Notes:
1) The mask values for the BAD0 register in the table are a minimum set of bits. Setting more masking bits permits
masking bits not needed to be compared with transfer data.
2) "Position of valid data in BAD1, BAD0" provides an 8-bit hexadecimal image for MSB on the left and LSB on the
right. Data at bit positions indicated by * in the BAD1, BAD0 registers is compared with data on the data bus, according to the access data length and access address.
26.3.4 Using operand with data break
Using operand address with data value break together is enabled with setting both EP3 and EP1, and/or both EP2
and EP0 together with setting the bit COMB = 1 for the data value break mode set with CTC = 11.
In other words: a break in channel 0 will occur at a match on operand address in BAD2 and a match on data value
in BAD0. A break in channel 1 will occur at a match on operand address in BAD3 and a match on data value in
BAD1. It is not possible to mix them vice versa.
On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand
break exception routine.
Table 26.3-5 Operand address and data value break combinations
300
EP3/2
EP1/0
COMB
Function
0
0
0
No break detection
0
1
0
Independent data break (match value on any operand address)
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Table 26.3-5 Operand address and data value break combinations
EP3/2
EP1/0
COMB
Function
1
0
0
Independent Operand break (match operand address)
1
1
0
Independent Data break and Operand break
0
0
1
No break detection
0
1
1
No break detection
1
0
1
No break detection
1
1
1
Data value break (match both operand address and value)
26.3.5 Memory Protection
Due to the availability of address range comparators for the operand and instruction addresses the wish is obvious,
to use the same comparator hardware as a memory protection unit (MPU).
Following table list the possible type configurations and its feasibility to be used for memory protection. The number
of break points and MPU channels is valid for 2 comparator groups implemented.
Table 26.3-6 Comparator Type Configuration
CTC
CMP1 Input
CMP0 Input
Max. Break Points
(MPE=0)
Max. MPU Channels
(MPE=1)
00
IA
IA
8 Instruction breaks
4 ranges with execute
permissions
01
OA
OA
8 Operand breaks
4 ranges with read/
write permissions
10
OA
IA
4 + 4 IA/OA breaks
2 ranges with read/
write and execute permissions or 2+2 independent ranges
11
OA
DT
8 data value breaks
-
Additional to the given hardware there were made some extensions to provide the user with a more likely configuration of read, write and execute permissions instead of the more bus applicable definition of the operand break size
and type definitions OBS/OBT, including read-modify-write. With the introduction of the Supervisor mode a definition
of User and Supervisor permissions is possible.
Permissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index.
Table 26.3-7 Meaning of the permission config bits
Symbol
Data Mode (OA)
Instruction Mode (IA)
SRX[1:0]
Supervisor Read permission
Supervisor eXecute permission
SW[1:0]
Supervisor Write permission
-
URX[1:0]
User Read permission
User eXecute permission
UW[1:0]
User Write permission
-
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At each time an instruction is executed or an operand is accessed, the actual valid permissions were evaluated.
This evaluation is divided into operand access (OA-based) and code execution (IA-based).
For each part the highest priority region hit is searched for. The highest channel number has the highest priority
(strict priority scheme). If a channel hit was found, the permissions defined for this channel will apply. If no channel
hit was detected, the default permissions apply.
After the actual permissions are evaluated (valid for actual data access, if any, and actual instruction) the permissions were checked. If the execute permission is not set or if the read or write permissions do not fit to the type of
the actual access, a protection violation will be indicated. This causes a CPU trap to the memory protection violation
MPUPV handler routine. The CPU switches directly to Supervisor mode in this case.
The config register space of the EDSU is protected against random access in User mode. Only in Supervisor mode
or Emulation mode the register file enables write access. For configuration a system interrupt INT #5 was defined,
which switches in Supervisor mode (SV bit remains set during the execution of the INT #5-ISR). Except debugger
interrupts by the emulator and NMI the Supervisor ISR is not interruptible.
Exceptions caused by the memory protection and the break unit for debugging are separated. In that way the memory protection functionality can be debugged itself.
26.3.6 Break Factors
Summary of the internal break factors and the executed events:
Break on instruction address
->
Causes Instruction Break
Break on operand address
->
Causes Operand Break
Break on data value
->
Causes Operand Break
Resource Interrupt (BREAK)
->
Causes Tool NMI
Step Trace Trap
->
Causes Step Trace Trap
Execution of the INTE instr.
->
Causes INTE
Execution of INT #5
->
CPU Supervisor Mode
Memory protection exception
->
Causes MPUPV Trap
Break factors and corresponding interrupt numbers and vectors:
Table 26.3-8 Interrupt numbers and vectors of break factors
Interrupt
302
Interrupt number
Interrupt level
Interrupt vector
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
CPU supervisor mode
(INT #5 instruction)
5
05
-
-
3E8H
000FFFE8H
Memory protection
exception
6
06
-
-
3E4H
000FFFE4H
INTE instruction
9
09
-
-
3D8H
000FFFD8H
Instruction break
exception
10
0A
-
-
3D4H
000FFFD4H
Operand break
exception
11
0B
-
-
3D0H
000FFFD0H
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Default Vector
address
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26.3
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Table 26.3-8 Interrupt numbers and vectors of break factors
Interrupt
Interrupt number
Interrupt level
Interrupt vector
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Step trace trap
12
0C
-
-
3CCH
000FFFCCH
NMI interrupt (tool)
13
0D
-
-
3C8H
000FFFC8H
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Default Vector
address
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26.4 Registers
26.4.1 List of EDSU Registers
Table 26.4-1 EDSU Registers Summary
Address
Register
Block
+0
+1
+2
+3
--------
BCTRL
--------
[R/W]
11111100
00000000
--------
BSTAT
-----000
[R/W0]1
00000000
10--0000
00000000
BIAC
00000000
[R]
00000000
00000000
00000000
BOAC
00000000
[R]
00000000
00000000
00000000
BIRQ
00000000
[R/W]
00000000
00000000
0000F000H
0000F004H
0000F008H
0000F00CH
0000F010H
0000F014H...0000F01FH
EDSU
reserved
0000F020H
--------
BCR0
00000000
[R/W]
00000000
00000000
--------
BCR1
00000000
[R/W]
00000000
00000000
--------
BCR2
00000000
[R/W]
00000000
00000000
--------
BCR3
00000000
[R/W]
00000000
00000000
0000F024H
0000F028H
0000F02CH
0000F030H
0000F034H
0000F038H
reserved
0000F03CH
0000F040H...0000F07FH
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Table 26.4-1 EDSU Registers Summary
Address
Register
+0
+1
+2
+3
XXXXXXXX
BAD0
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD1
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD2
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD3
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD4
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD5
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD6
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD7
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD8
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD9
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD10
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD11
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD12
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD13
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD14
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
BAD15
XXXXXXXX
[R/W]
XXXXXXXX
XXXXXXXX
0000F080H
0000F084H
0000F088H
0000F08CH
0000F090H
0000F094H
0000F098H
0000F09CH
0000F0A0H
0000F0A4H
0000F0A8H
0000F0ACH
0000F0B0H
0000F0B4H
0000F0B8H
0000F0BCH
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Table 26.4-1 EDSU Registers Summary
Address
Register
+0
+1
Block
+2
+3
EDSU
0000F0C0H
0000F0C4H
0000F0C8H
0000F0CCH
0000F0D0H
0000F0D4H
0000F0D8H
0000F0DCH
reserved
0000F0E0H
0000F0E4H
0000F0E8H
0000F0ECH
0000F0F0H
0000F0F4H
0000F0F8H
0000F0FCH
1.RMW - read returns "1" for each flag, for write only "0" (clear) is supported.
Remark: Read and write access to all registers is byte, halfword and word.
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26.4.2 Explanations of Registers
● BCTRL (EDSU Control Register)
BCTRL byte 2
Address : 00F002H
15
14
13
12
11
10
9
8
SR
SW
SX
UR
UW
UX
FCPU
FDMA
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(0)
(0)
Initial value⇒
BCTRL byte 3
Address : 00F003H
Read/write ⇒
Initial value⇒
7
6
EEMM
PFD
5
4
SINT1 SINT0
3
2
EINT1
EINT0
1
0
⇐ Bit no.
EINTT EINTR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default Permission Register
The default permission register defines the lowest priority access permission for the whole memory and I/O address
range of the MCU. Lowest priority means, that the default permission take effect for all address regions, which are
NOT covered by any dedicated channel configuration, operating in MPU mode. Default read, write and execute permission could be defined for the supervisor mode (SV=1) and the normal user mode (SV=0). The supervisor mode
(SV) is indicated by bit 6 of the CCR in the program status word of the CPU. After the INIT condition all permissions
are set (access allowed).
BIT[15]: SR - Supervisor default Read permission register
0
Supervisor is not permitted to read data
1
Supervisor is permitted to read data (default)
BIT[14]: SW - Supervisor default Write permission register
0
Supervisor is not permitted to write data
1
Supervisor is permitted to write data (default)
BIT[13]: SX - Supervisor default eXecute permission register
0
Supervisor is not permitted to execute code
1
Supervisor is permitted to execute code (default)
BIT[12]: UR - User default Read permission register
0
User is not permitted to read data
1
User is permitted to read data (default)
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BIT[11]: UW - User default Write permission register
0
User is not permitted to write data
1
User is permitted to write data (default)
BIT[10]: UX - User default eXecute permission register
0
User is not permitted to execute code
1
User is permitted to execute code (default)
CPU and DMA Filter Option Register
BIT[9]: FCPU - Filter CPU access
0
Trigger on CPU accesses (default)
1
Do not trigger on CPU accesses
FCPU controls the filter operation for CPU accesses triggered by operand compare channels (Operand address
break, data value break and memory data protection).
If FCPU is set to "1", all CPU accesses are masked out. If set to "0" CPU accesses can cause break function.
BIT[8]: FDMA - Filter DMA access
0
Trigger on DMA accesses (default)
1
Do not trigger on DMA accesses
FDMA controls the filter operation for DMA accesses triggered by operand compare channels (Operand address
break, data value break and memory data protection).
If FDMA is set to "1", all DMA accesses are masked out. If set to "0", DMA accesses can cause break function.
Important Note for FDMA: Only DMA accesses over D-Bus were detected. The operands for an explicit DMA trigger
condition have to be located in the D-Bus address area (This is the case for D-bus RAM, CAN and all R-Bus resources in the MB91460 family). Otherwise the DMA transfer could not be recognized by the EDSU. This function
was mainly intended to disable the trigger on DMA accesses (filter out the operand change condition by DMA), complete address range DMA trigger conditions are not supported.
Enable Interrupt Register
BIT[7]: EEMM - Enable Emulation Mode
308
0
Disable emulation mode (default)
1
Enable emulation mode
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If EEMM is set to "1" then the emulation mode is entered during Step Trace Mode and EDSU exceptions Instruction
Break, Operand Break and Tool NMI. During emulation mode, the Watchdog Timer (WDT) is disabled. EDSU triggered emulation mode is left with the RETI instruction.
Set to "0" disables emulation mode function. The WDT is not stopped during Step Trace and EDSU exceptions.
BIT[6]: PFD - Phantom Filter Disable
0
Instruction break detection uses phantom filter (default)
1
Phantom Filter disabled
The default (PFD=0) is to use policies to filter out phantom interrupts and wrong status bits, which may be set in
addition.
•
The instruction fetched, after RETI was executed, is normally the instruction on which the break point was set.
Fetch is repeated after processing the breakpoint handler ISR before executing the instruction at the break
point. The filter avoids that the trigger of the break condition will be repeated.
•
Not granted Instruction Break exceptions are timed out
— Pre-fetched, but not executed commands
— Commands after delayed slot instruction
•
Consecutive break conditions which are pre-fetched are not allowed to set flags. Only the instruction at which
the break condition occurs at first time can set status bits accordingly.
•
Nested Instruction breaks are not allowed (break within the break handler ISR)
BIT[5:4]: SINT[1:0] - Select resource INTerrupt source
SINT[1:0]
MB91F463N
Resource
00B
Tool NMI by interrupt on source 0 selected (default)
LIN-USART 0 RX / LIN-USART 0 TX
01B
Tool NMI by interrupt on source 1 selected
LIN-USART 1 RX / LIN-USART 1 TX
10B
Tool NMI by interrupt on source 2 selected
LIN-USART 3 RX / LIN-USART 3 TX
11B
Tool NMI by interrupt on source 3 selected
CAN4 / I2C 2
SINT1 and SINT0 select the active resource interrupt source.
BIT[3]: EINT1 - Enable extended INTerrupt 1
0
Disable extended interrupt source 1 (default)
1
Enable extended interrupt source 1
If EINT1 is set to "1" then a Tool NMI will be generated on an extended interrupt event at source channel 1. Set to
"0" disables this function.
Remark: EINT1 interrupt source is not available for the MB91F463N series.
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BIT[2]: EINT0 - Enable extended INTerrupt 0
0
Disable extended interrupt source 0 (default)
1
Enable extended interrupt source 0
If EINT0 is set to "1" then a Tool NMI will be generated on an extended interrupt event at source channel 0. Set to
"0" disables this function.
Remark: EINT1 and EINT0 can be used for indicating a signal line event which can be used for generating a BREAK
function. The sources of these interrupts are hardwired in the MCU and can be for example: external interrupt ports,
general purpose I/O port pins, other resources, etc. This has to be defined in the device specification.
BIT[1]: EINTT - Enable INTerrupt on Transmit
0
Disable transmit interrupt source channels 0 to 3 (default)
1
Enable transmit interrupt source channels 0 to 3
If EINTT is set to "1" then a Tool NMI will be generated on a transmit interrupt event at source channels 0 to 3 set
by TXINT[1:0]. Setting EINTT to "0" disables this function.
Remark: If SINT[1:0] is set to "11" this bit enables the interrupt of CAN channel 1 (CAN has one interrupt
request for both reception and transmission).
BIT[0]: EINTR - Enable INTerrupt on Receive
0
Disable receive interrupt source channels 0 to 3 (default)
1
Enable receive interrupt source channels 0 to 3
If EINTR is set to "1" then a Tool NMI will be generated on a receive interrupt event at source channels 0 to 3 set
by RXINT[1:0]. Setting EINTR to "0" disables this function.
Remark: If SINT[1:0] is set to "11", this bit enables the interrupt of CAN channel 0 (CAN has one interrupt
request for both reception and transmission).
● BSTAT (EDSU Status Register)
BSTAT byte 2
Address : 00F006H
Read/write ⇒
Initial value⇒
BSTAT byte 3
Address : 00F007H
14
13
12
11
10
9
8
IDX4
IDX3
IDX2
IDX1
IDX0
CDMA
CSZ1
CSZ0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
PV
RST
INT1
INT0
INTT
INTR
(R)
(0)
(R)
(0)
CRW1 CRW0
Read/write ⇒
Initial value⇒
310
15
(R )
(0)
(R )
(0)
(R/W) (R/W) (R/W) (R/W)
(0)
(1)
(0)
(0)
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⇐ Bit no.
⇐ Bit no.
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BIT[15:11]: IDX[4:0] - Channel Index Indication of MPUPV Trigger
In the case of triggering a memory protection violation (MPUPV), the index of the channel pair 0...15 is saved in The
IDX register, which caused the trigger. The channel pairs are normally used as range comparators.
If no MPU channel has detected a hit on its address range, the default permissions apply. If the default permissions
are violated, IDX is set to the value 16 (overrun). If the permissions of a matching MPU channel are violated, IDX
shows the index of the appropriate break detection bits BIRQ_BD[31:0]. The break detection bits belonging to this
comparator are BD[2*IDX] and BD[2*IDX+1].
In case of multiple range hits and/or trigger conditions, the channel with the highest priority trigger condition is indicated by IDX[4:0]. The priority raises with the channel index.
IDX
Description
0 to 15
Points to the channel number of the last protection violation
16
The last protection violation was caused by the violation of the default permissions
The channel index indication register can be read only.
Access Type Capture Register
In case of a trap caused by a memory protection violation or an operand/data value break condition, the status bits
[12:8] capture type information about the break causing operand access. In case of a memory protection fault due
to the violation of execution permissions, this information is also captured, regardless if there was an active operand
access or not.
Access type capture register are read only.
BIT[10]: CDMA - Capture DMA Indication
0
The operand access was executed by the CPU
1
The operand access was executed by the DMA controller
BIT[9:8]: CSZ[1:0] - Capture Operand Size
00
The operand has a bit size of 8
01
The operand has a bit size of 16
10
The operand has a bit size of 32
11
reserved
BIT[7:6]: CRW[1:0] - Capture Operand Access Type
00
The operand has been read
01
The operand has been read by read-modify-write indicated
10
The operand has been written
11
no operand access
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BIT[5]: PV - Protection Violation Detection
0
There was no protection violation on read, write and execute permissions
1
A protection violation (MPUPV) has been occurred
If this bit is set after a protection violation, a MPUPV trap is indicated to the CPU. The occurrence of a protection
violation means, that there was a read or write access to a defined address region, which was not permitted or code
was executed without execute permissions for this address region. As consequence the CPU switches to supervisor
mode (SV=1) and calls the handler routine for interrupt number #6 (see table 26.3-8).
This bit should be cleared by writing "0" in the MPUPV trap handler routine.
BIT[4]: RST - Operation Initialization Reset (RST) Detection
The reset operation of FR family is divided into two levels, setting initialization reset (INIT) and operation initialization
reset (RST). When INIT occurs, RST occurs at the same time implicitly.
0
Operation Reset was not triggered since last BSTAT read or clear
1
Operation Reset was triggered since last BSTAT read or clear
The RST bit is read only, any write access to this bit will be ignored. RST is cleared after BSTAT is read (read from
any byte address within the 32 bit word). RST has same behaviour for read and read-modify-write access.
The RST bit can be used for reset detection. It is set in any case of operation initialization reset is triggered. Debug
monitor software can use this to detect if the communication device to the debugger front end needs to be re-configured after an operation reset. This is important for debugging of boot procedures and soft reset handling. After
reading the EDSU status word the RST bit is cleared automatically.
Break Interrupt Register
BIT[3]: INT1 - INTerrupt on extended source 1
0
Interrupt on extended source channel 1 not detected (default)
1
Interrupt on extended source channel 1 detected
INT1 reflects the status of the extended interrupt source channel 1. It is set to "1" if a high level on the extended
interrupt signal line has been occurred. The status of "1" is stored until cleared by software.
Writing "0" resets the INT1 bit to "0". Writing "1" to this bit is ignored. On a Read Modify Write instruction INT1 is
read as "1".
BIT[2]: INT0 - INTerrupt on extended source 0
0
Interrupt on extended source channel 0 not detected (default)
1
Interrupt on extended source channel 0 detected
INT0 reflects the status of the extended interrupt source channel 0. It is set to "1" if a high level on the extended
interrupt signal line has been occurred. The status of "1" is stored until cleared by software.
Writing "0" resets the INT0 bit to "0". Writing "1" to this bit is ignored. On a Read Modify Write instruction INT0 is
read as "1".
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BIT[1]: INTT - INTerrupt on Transmit source
0
Interrupt on transmit source not detected (default)
1
Interrupt on transmit source channel detected
INTT reflects the status of the transmit interrupt source channels 0 to 3 (can be selected by TXINT[1:0]). It is set to
"1" on a high level on the transmit interrupt signal line and "0" on a low level on the signal line.
This bit is read-only. It can be set to "0" by clearing the appropriate interrupt bit in the selected resource.
Remark: If SINT[1:0] is set to "11" this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt
request for both reception and transmission).
BIT[0]: INTR - INTerrupt on Receive source
0
Interrupt on receive source not detected (default)
1
Interrupt on receive source channel detected
INTR reflects the status of the receive interrupt source channels 0 to 3 (can be selected by RXINT[1:0]). It is set to
"1" on a high level on the receive interrupt signal line and "0" on a low level on the signal line.
This bit is read-only. It can be set to "0" by clearing the appropriate interrupt flag in the selected resource.
Remark: If SINT[1:0] is set to "11" this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt
request for both reception and transmission).
● BIAC (EDSU Instruction Address Capture Register)
BIAC
Address
00F008H
+0
00000000
[R]
+1
+2
00000000
00000000
+3
00000000
This register captures the address of the instruction (IA), which has caused the protection violation or the operand/
data value break. This register could be read only.
● BOAC (EDSU Operand Address Capture Register)
BOAC
Address
00F00CH
+0
00000000
+1
00000000
[R]
+2
00000000
+3
00000000
This register captures the address of the operand access (OA), which has caused the protection violation or the
operand/data value break. This register could be read only.
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● BIRQ (EDSU Break Detection Interrupt Request Register)
BIRQ
Address
00F010H
+0
00000000
[R/W]
+1
00000000
+2
00000000
+3
00000000
BIRQ collects all break detection bits of all channels, regardless of the type configuration of each channel. The actual implementation consists of 8 groups of channels, that are 32 single point channels totally.
Each group of channels consists of 4 channels and 4 bits for break detection in the BIRQ register. Each group has
two comparator pairs. Each pair consists of two point comparators which could build a range comparator by setting
the range enable bit. Such a range comparator pair is connected to the instruction address, operand address or the
data value information - selected by the comparator type configuration.
For detection of combined operand address and data value breaks two of such comparator pairs are combined together. Than the break detection (BD) bits are set only if both conditions are matching simultaneously.
BIT[31:0]: BD[31:0] - Break Detection register
0
Break factor not detected (default)
1
Break factor detected on channel according the bit position [31:0]
BD[31:0] reflects the status of the break detection. It is set to "1" at match with BAD31...BAD0 accordingly (and if
the mask condition is satisfied, if enabled by EM1/0). For bit pairs [31:30], [29:28], ..., [1:0] range matches could
apply, if the range function using two points is enabled by ER1/0.
Break factors could be
•
instruction address break,
•
operand address break,
•
data value break,
•
combined operand address and data value break and
•
memory protection violation.
Writing "0" resets the BD[31:0] bits to "0". Writing "1" to these bits is ignored. On a Read Modify Write instruction all
BD bits are read as "1".
BD1/BD0 setting at enabled address range function (also valid for the other pairs of BD bits in neighbourhood):
If the operand address range function is enabled with ER0 in addition to the point enables EP1 and EP0, then the
BD1 and BD0 detection bits are set in the following manner:
Table 26.4-2 BD Coding for Match on Start/Endpoint or Range
BD1
314
BD0
Compare value: Instruction, Operand Address, Data Value
0
0
No match (Default)
0
1
Match on point (compare value == BAD0)
1
0
Match on point (compare value == BAD1)
1
1
Match on range (BAD0 < compare value < BAD1)
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● BCR0, BCR1 (EDSU Channel Configuration Register0, EDSU Channel Configuration Register1)
BCR 0, byte 0
Address : 00F020H
Read/write ⇒
Initial value⇒
BCR 0, byte 1
Address : 00F021H
Read/write ⇒
Initial value⇒
BCR 0, byte 2
Address : 00F022H
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
23
22
21
20
19
18
17
16
SRX1
SW1
SRX0
SW0
URX1
UW1
URX0
UW0
⇐ Bit no.
⇐ Bit no.
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
MPE
COMB
CTC1
CTC0
OBS1
OBS0
OBT1
OBT0
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value⇒
BCR 0, byte 3
Address : 00F023H
Read/write ⇒
Initial value⇒
7
6
5
4
3
2
1
0
EP3
EP2
EP1
EP0
EM1
EM0
ER1
ER0
⇐ Bit no.
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
For each group of four channels one channel configuration register (BCR0...BCR7) is implemented. It holds the configuration set for the according group of channels. The following table shows the relationship, which channel configuration, break point address/data registers and break detection bits belong together.
Table 26.4-3 Relationship of BCR, BAD and BIRQ registers
Group Config
Address/Data
BADx Usage
BCR0
BAD0
Point0, Mask0
EP0
BAD1
Point1
EP1
BAD2
Point2, Mask1
EP2
BAD3
Point3
EP3
BAD4
Point0, Mask0
EP0
BAD5
Point1
EP1
BAD6
Point2, Mask1
EP2
BAD7
Point3
EP3
BCR1
Point
Mask
EM0
EM1
EM0
EM1
Combination
range 0
ER0
range 1
ER1
range 0
ER0
range 1
ER1
BIRQ
OA0
BD0
OA1
BD1
DT0
BD2
DT1
BD3
OA0
BD4
OA1
BD5
DT0
BD6
DT1
BD7
Group of Channels, Permission Definition Register
The permission definition registers are valid only for the group of channels operating in MPU mode. This is the case
if MPE is set to "1". If the group does not operate in MPU mode, the permission configuration is not required (don’t
care).
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Normally MPU channels operate in range mode for the address definitions.
The type of the permission, which could be set-up, depends on the comparator type configuration (CTC) for each
comparator pair. MPU channels could be configured either to check instruction addresses (IA) or operand addresses (OA). IA ranges could be used to define execute permissions. OA ranges could be used to define read and write
permissions.
The comparator type for MPU usage could be set to
•
CTC=0: both IA ranges define execute permissions,
•
CTC=1: both OA ranges define read/write permissions and
•
CTC=2: IA range 0 defines execute permissions and OA range 1 defines read/write permissions.
Data value (DT) detection by setting CTC=3 is not possible to use in MPU mode.
Permission configurations exist for read, write and execute for two CPU modes, the supervisor mode and the user
mode. Supervisor permissions are valid for SV=1 and user permissions are valid for SV=0.
BIT[23]: SRX1 - Supervisor Read/eXecute permission register for range 1
Setting valid for CTC == 0 (Instruction address range comparator):
0
Supervisor has no execute permission on address range 1(default)
1
Supervisor has execute permission on address range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
Supervisor has no read permission on address range 1 (default)
1
Supervisor has read permission on address range 1
BIT[22]: SW1 - Supervisor Write permission register for range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
Supervisor has no write permission on address range 1 (default)
1
Supervisor has write permission on address range 1
BIT[21]: SRX0 - Supervisor Read/eXecute permission register for range 0
Setting valid for CTC == 0 or CTC == 2 (Instruction address range comparator):
0
Supervisor has no execute permission on address range 0 (default)
1
Supervisor has execute permission on address range 0
Setting valid for CTC == 1 (Operand address range comparator):
316
0
Supervisor has no read permission on address range 0 (default)
1
Supervisor has read permission on address range 0
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BIT[20]: SW0 - Supervisor Write permission register for range 0
Setting valid for CTC == 1 (Operand address range comparator):
0
Supervisor has no write permission on address range 0 (default)
1
Supervisor has write permission on address range 0
BIT[19]: URX1 - User Read/eXecute permission register for range 1
Setting valid for CTC == 0 (Instruction address range comparator):
0
User has no execute permission on address range 1(default)
1
User has execute permission on address range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
User has no read permission on address range 1 (default)
1
User has read permission on address range 1
BIT[18]: UW1 - User Write permission register for range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
User has no write permission on address range 1 (default)
1
User has write permission on address range 1
BIT[17]: URX0 - User Read/eXecute permission register for range 0
Setting valid for CTC == 0 or CTC == 2 (Instruction address range comparator):
0
User has no execute permission on address range 0 (default)
1
User has execute permission on address range 0
Setting valid for CTC == 1 (Operand address range comparator):
0
User has no read permission on address range 0 (default)
1
User has read permission on address range 0
BIT[16]: UW0 - User Write permission register for range 0
Setting valid for CTC == 1 (Operand address range comparator):
0
User has no write permission on address range 0 (default)
1
User has write permission on address range 0
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Group of Channels, Mode Configuration Register
BIT[15]: MPE - Memory Protection Enable
0
The group of channels operates as debug interface and defines breakpoints (default)
1
The group of channels operates in memory protection mode
Some restrictions apply with the setting of the MPE bit.
MPE=0 (break unit):
•
permission registers are don’t care (BCRx bits [23:16])
MPE=1 (memory protection unit):
•
OBS and OBT should be set to "3" (BCRx bits [11:8], any size and any type)
•
CTC should not be set to "3" (BCRx bits [13:12], data value check not supported in this mode)
BIT[14]: COMB - Channel Combination Enable
0
No combination between channels (default)
1
Combination between channels is effective
Depending on the MPE configuration bit the COMB feature has different meaning.
(A) COMB=1 and MPE=0 (break unit, combined operand address and data value break):
The break detection conditions are combined before setting the BIRQ_BD bits and signalise an operand break condition. Setting the COMB bit is required for defining a data value break on a specific operand address. If the COMB
bit is set to "1", both conditions, matching operand address (OA) and matching data value (DT), are required to be
true. Setting the COMB bit makes only sense in the OA/DT mode, defined by CTC=3.
The AND-combination is effective between channels 3 (OA1) and 1 (DT1) and between channels 2 (OA0) and 0
(DT0). It is assumed that no range operation is defined (ER1=ER0=0).
BIRQ_BD3 = BIRQ_BD1 = BD3 && BD1;
BIRQ_BD2 = BIRQ_BD0 = BD2 && BD0;
If channels 3 and 2 define an operand address range (OA1:OA0) by setting ER1=1 and/or channels 1 and 0 define
a data value range (DT1:DT0) by setting ER0=1, the break detection bits of each channel are AND-combined with
the combined ( logical OR) channels of the opposite range comparator break detection outputs.
BIRQ_BD3 = BD3 && (BD1 || BD0);
BIRQ_BD2 = BD2 && (BD1 || BD0);
BIRQ_BD1 = BD1 && (BD3 || BD2);
BIRQ_BD0 = BD0 && (BD3 || BD2);
This offers the same interpretation of the BIRQ break detection bits (see table 26.4-2 for coding of match on start
point, range or end point) as it would be the case for range detection with COMB=0. BD3 and BD2 hold the coding
for the operand address (OA) match, whereas BD1 and BD0 hold the coding for the data value (DT) match. The
COMB bit set to "1" ensures that both conditions, the OA match and the DT match must be true to set the appropriate BD bit in the end.
If the COMB bit is set to "0" all break detection bits are passed to the BIRQ register in it’s original form. The comparator channels match conditions are independent from each other.
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(B) COMB=1 and MPE=1 (memory protection unit, combined rwx permissions on single range):
In memory protection mode the COMB bit has the meaning of combined data read/write and code execute permissions, set for the same address range. The setting is only meaningful for the combination of operand address (OA)
comparators on channels 3 and 2 and instruction address (IA) comparators on channels 1 and 2 in the mode
CTC=2.
The COMB bit set to "1" causes the IA comparator CMP0 to use the same BADx point definitions as the OA comparator CMP1. Point 3 and Point 2 define the address range for both comparators CMP0 and CMP1. This has the
effect that the entry of Point 0/Mask 0 is not allocated for the Point set-up and could be used for masking either one
or both comparators. The Point 1 entry is not useable in this case.
If the COMB bit is set to "0" both comparators have independent address configurations. The comparators can either define read/write permissions for data protection or define execute permissions for code protection. Each comparator can define an address region by a range between two points (ER=1) or by one point with a mask (EM=1).
BIT[13:12]: CTC[1:0] - Comparator Type Config
CTC
CMP1
CMP0
Break Function
MPU Function
0
IA
IA
4 instruction break points
2 regions for code protection
(x permissions)
1
OA
OA
4 operand break points
2 regions for data protection
(rw permissions)
2
OA
IA
2 instruction break points +
2 operand break points
1 region for code protection
(x permissions) and
1 region for data protection
(rw permissions) or
1 region for combined code
and data protection
(rwx permissions)
3
OA
DT
2 operand break points +
2 data value breaks,
normally with combination
not applicable
One group of channels contains 2 range comparator blocks. Each comparator block can detect a range hit between
two points or two independent point hits. The point configuration is stored in dedicated BADx registers for each
channel (4 BADx registers for each group of channels).
The comparator type configuration (CTC) controls the input multiplexing of the compare value for each of the two
range comparator blocks CMP1 and CMP0. CMP1 combines the break detection channels 3 and 2. The compare
value for CMP1 can be assigned either to the instruction address (IA) or to the operand address (OA). CMP0 combines the break detection channels 1 and 0. The compare value for CMP0 can be assigned to the instruction address (IA), to the operand address (OA) or to the data value (DT). The table above defines the input compare values
for CMP1 and CMP0, depending on the CTC setting.
In addition a mask for each comparator block could be defined (see the definition of the EM bits later). In this case
the BADx register, which contains the mask information, is not available for the point configuration. Thus the usage
of the mask feature restricts the number of points or channels, which are available in total.
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MB91460N series
BIT[11:8]: OBS[1:0], OBT[1:0] - Operand Break Size / Operand Break Type register 1
Datasize
OBS1
OBS0
Access type
OBT1
OBT0
0
0
Byte (Default)
0
0
Read (Default)
0
1
Halfword
0
1
Read-Modify-Write
1
0
Word
1
0
Write
1
1
All (Byte, Hword, Word)
1
1
All (Read, RMW, Write)
The operand break size register OBS configures the datasize and the operand break type register OBT configures
the access type if the channel is configured to operand address break or data value break detection.
Setting to "all" in datasize will cause detection of byte, halfword and word data sizes. Setting to "all" in access type
will cause detection of Read, Read-Modify-Write and Write access types.
Enable Break Point Register
BIT[7]: EP3 - Enable break Point 3 register
0
Break point 3 register is disabled (default)
1
Break point 3 register is enabled
If EP3 is enabled then the input value of CMP1 will be compared with the point 3 register content (BAD index =
3+group offset, BAD3 for group 0 channel 3, BAD7 for group 1 channel 3, ...).
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception.
BIT[6]: EP2 - Enable break Point 2 register
0
Break point 2 register is disabled (default)
1
Break point 2 register is enabled
If EP2 is enabled then the input value of CMP1 will be compared with the point 2 register content (BAD index =
2+group offset, BAD2 for group 0 channel 2, BAD6 for group 1 channel 2, ...).
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception.
EP2 controls in addition to enabling and allocating point 2 the selection of the mask register. Point 2 is also the default place for storing the CMP1 mask value. But, if point 2 is enabled, the mask could not be stored there and the
mask input of CMP1 switches to point 0 (to the opposite comparator).
BIT[5]: EP1 - Enable break Point 1 register
320
0
Break point 1 register is disabled (default)
1
Break point 1 register is enabled
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If EP1 is enabled then the input value of CMP0 will be compared with the point 1 register content (BAD index =
1+group offset, BAD1 for group 0 channel 1, BAD5 for group 1 channel 1, ...).
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception.
BIT[4]: EP0 - Enable break Point 0 register
0
Break point 0 register is disabled (default)
1
Break point 0 register is enabled
If EP0 is enabled then the input value of CMP0 will be compared with the point 0 register content (BAD index =
0+group offset, BAD0 for group 0 channel 0, BAD4 for group 1 channel 0, ...).
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception.
EP0 controls in addition to enabling and allocating point 0 the selection of the mask register. Point 0 is also the default place for storing the CMP0 mask value. But, if point 0 is enabled, the mask could not be stored there and the
mask input of CMP0 switches to point 2 (to the opposite comparator).
If memory protection is enabled (MPE=1) in conjunction with the combination bit set (COMB=1), the address range
is defined by point 3 and point 2 and is valid for both comparators COMB1 and COMB0. So the points 1 and 0 are
not required for the range definition of CMP0, independent from the point enable EP0 and EP1, which normally are
set in this case. Thus point 0 could be used for storing the mask value for both comparators CMP1 and CMP0 and
the exception described in the paragraph above did not apply for this case.
Enable Mask And Range Register
BIT[3]: EM1 - Enable Mask for CMP1
0
Mask function for CMP1 is disabled (default)
1
Mask function for CMP1 is enabled
If EM1 is enabled the comparator CMP1 matches only these bit positions, which are set to "0" and are not masked
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the
mask register. The compare operations point match or range detection are derived based on these OR-masked values.
The selection of the appropriate BADx register (point 2 or 0) for the mask value depends on EP2 and ER1. If at least
one of both bits are enabled, the mask usage switches to point 0 due to the allocation of point 2. Otherwise the
default mask stored in point 2 applies for CMP1.
BIT[2]: EM0 - Enable Mask for CMP0
0
Mask function for CMP0 is disabled (default)
1
Mask function for CMP0 is enabled
If EM0 is enabled the comparator CMP0 matches only these bit positions, which are set to "0" and are not masked
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the
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mask register. The compare operations point match or range detection are derived based on these OR-masked values.
The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least
one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the
default mask stored in point 0 applies for CMP0. If MPE=1 and COMB=1 the mask is taken from point 0, regardless
of the setting of EP0 and ER0.
BIT[1]: ER1 - Enable Range for CMP1
0
Range detection CMP1 (channels 2, 3) is disabled (default)
1
Range detection CMP1 (channels 2, 3) is enabled
If ER1 is enabled then the registers BADx, point 3 and point 2 will be used for range comparison:
Point 2 <
= Compare Value <
= Point 3.
If a mask is set with EM1 then both point registers will be masked with the mask register content.
Point 3 and Point 2 are taken from BAD[x+3] and BAD[x+2], the mask is stored in Point 0, BAD[x+0].
The "x" is the group offset and calculates by the group index multiplied with 4.
BIT[0]: ER0 - Enable Range for CMP0
0
Range detection CMP0 (channels 0, 1) is disabled (default)
1
Range detection CMP0 (channels 0, 1) is enabled
If ER0 is enabled then the registers BADx, point 1 and point 0 will be used for range comparison:
Point 0 <
= Compare Value <
= Point 1.
If a mask is set with EM0 then both point registers will be masked with the mask register content.
In the special case of MPE=1 together with COMB=1, Point 1 and Point 0 are taken from the opposite channel
BAD[x+3] and BAD[x+2] and the mask is stored in Point 0, BAD[x+0]. Otherwise Point 1 and Point 0 are taken from
BAD[x+1] and BAD[x+0], the mask is stored in Point 2, BAD[x+2].
The "x" is the group offset and calculates by the group index multiplied with 4.
● BAD0...BAD31 (Break Address/Data register0...Break Address/Data register31)
The BADx registers define 8 break point addresses, data values or mask information for the 2 groups of channels.
For each group of channels there are 4 dedicated BAD registers. BAD0, BAD1, BAD2 and BAD3 belong to Group
0, BAD4, BAD5, BAD6 and BAD7 belong to Group 1 and so on. The functionality described below for the registers
of group 0 is representative for all the other groups too. The index of the BADx registers has to be incremented by
4 for each of the next group indexes.
BAD0 (BAD4)
Address
00F080H
+0
XXXXXXXX
+1
XXXXXXXX
[R/W]
+2
XXXXXXXX
+3
XXXXXXXX
This register sets the 32 bit comparison value for break point 0 of CMP0. In range mode (set with ER0) the register
value of BAD0 functions as lower address limit. In addition BAD0 could be used as mask register.
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In the special case of MPE=1 and COMB=1 BAD0 is not used for the point definition. CMP0 gets its point configuration then from BAD2.
BAD1 (BAD5)
Address
00F084H
+0
XXXXXXXX
[R/W]
+1
XXXXXXXX
+2
XXXXXXXX
+3
XXXXXXXX
This register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the register
value of BAD1 functions as upper address limit.
In the special case of MPE=1 and COMB=1 BAD1 is not used for the point definition. CMP0 gets its point configuration then from BAD3.
BAD2 (BAD6) [R/W]
Address
00F088H
+0
XXXXXXXX
+1
XXXXXXXX
+2
XXXXXXXX
+3
XXXXXXXX
This register sets the 32 bit comparison value for break point 2 of CMP1. In range mode (set with ER1) the register
value of BAD2 functions as lower address limit. In addition BAD2 could be used as mask register.
BAD3 (BAD7) [R/W]
Address
00F08CH
+0
XXXXXXXX
+1
XXXXXXXX
+2
XXXXXXXX
+3
XXXXXXXX
This register sets the 32 bit comparison value for break point 3 of CMP1. In range mode (set with ER1) the register
value of BAD3 functions as upper address limit.
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F0BCH
BAD15
F0B8H
BAD14
F0B4H
BAD13
F0B0H
BAD12
...
F08CH
BAD3
F088H
BAD2
F084H
BAD1
F080H
BAD0
F02CH
BCR3
...
F020H
BCR0
F010H
BIRQ
F00CH
BOAC
F008H
BIAC
16
IDX3
ro
ro
SW
IDX4
SR
15
ro
IDX2
SX
ro
IDX1
UR
UW
point 3
point 2 / mask 1
point 1
point 0 / mask 0
point 3
point 2 / mask 1
point 1
point 0 / mask 0
SRX1 SW1
SRX1 SW1
SRX0 SW0 URX1 UW1 URX0 UW0
SRX0 SW0 URX1 UW1 URX0 UW0
7
ro
ro
0
BD8
ro
MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0
CMP1: IA, OA, OA, OA8, 16, 32, alll r, rmw, w, all
CMP0: IA, OA, IA, DT
MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0
BD9
ro
EP3
EP3
BD7
ro
EP2
EP2
BD6
ro
EP1
EP1
BD5
PV
EP0
EP0
BD4
ro/ac
RST
EM1
EM1
BD3
INT1
EM0
EM0
BD2
INT0
LIN-USART0, 1, 2, CAN
Device select (Rst) (Breakx)
ER1
ER1
BD1
ro
INTT
ER0
ER0
BD0
ro
INTR
FCPU FDMA EEMM PFD SINT1 SINT0 EINT1 EINT0 EINTT EINTR
8
IDX0 CDMA CSZ1 CSZ0 CRW1 CRW0
UW
BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10
ro
ro: read only
23
ac: auto clear
24
F004H
ro
31
BSTAT
F000H
BCTRL
Chapter 26 MPU / EDSU
26.5
MB91460N series
26.5 Quick Reference
Figure 26.5-1 Quick Reference of Registers
CM44-10149-1E
Chapter 27 I/O Ports
27.1
MB91460N series
Chapter 27 I/O Ports
27.1 I/O Ports Functions
For enabling the resource functions, please refer to section 30.27.2.4 Port Function Register Setup (Page
No.332).
Table 27.1-1 I/O Ports Functions (1 / 3)
Pin no.
2 to 9
10 to 12
Pin name
P29_0 to P29_7
AN0 to AN7
P24_0 to P24_2
INT0 to INT2
I/O
I/O
I/O
P24_3
13
INT3
I/O
15
I/O
21
22
General-purpose input/output port
INT5
I/O
INT6
General-purpose input/output port
I/O
I2C bus data input/output pin
P24_7
General-purpose input/output port
INT7
I/O
External interrupt input pin
SCL3
I2C bus clock input/output pin
P22_0
General-purpose input/output port
RX4
I/O
RX input pin of CAN4
INT12
External interrupt input pin
P22_1
General-purpose input/output port
TX4
I/O
RX5
P22_3
TX5
SIN2
SOT2
BIN0
TX output pin of CAN4
General-purpose input/output port
I/O
RX input pin of CAN5
External interrupt input pin
I/O
General-purpose input/output port
TX output pin of CAN5
General-purpose input/output port
I/O
Data input pin of LIN-USART2
Up/down counter input pin
P20_1
CM44-10149-1E
External interrupt input pin
SDA3
AIN0
26
External interrupt input pin
I2C bus clock input/output pin
P20_0
25
External interrupt input pin
P24_5
INT13
24
External interrupt input pin
I2C bus data input/output pin
P22_2
23
External interrupt input pins
SDA2
P24_6
20
General-purpose input/output ports
General-purpose input/output port
SCL2
19
Analog input pins for A/D converter
Clock monitor output pin
P24_4
INT4
General-purpose input/output ports
General-purpose input/output port
MONCLK
14
Function
General-purpose input/output port
I/O
Data output pin of LIN-USART2
Up/down counter input pin
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Table 27.1-1 I/O Ports Functions (2 / 3)
Pin no.
Pin name
I/O
P20_2
27
SCK2
CK2
General-purpose input/output port
I/O
ZIN0
SIN3
I/O
General-purpose input/output port
I/O
BIN1
SCK3
CK3
General-purpose input/output port
I/O
ZIN1
OCU0
I/O
General-purpose input/output port
I/O
TOT1
34
Output compare output pin
Reload timer output pin
X0
⎯
Clock (oscillation) input
Clock (oscillation) output
35
X1
⎯
36
MD3
I
Mode setting pin
37
MD2
I
Mode setting pin
38
MD1
I
Mode setting pin
39
MD0
I
Mode setting pin
40
INITX
I
External reset input
P15_2
41
42
OCU2
General-purpose input/output port
I/O
43 to 47,
50 to 52
TOT2
Reload timer output pin
General-purpose input/output port
OCU3
I/O
P17_7 to P17_0
PPG7 to PPG0
SCK1
I/O
54
55
SOT1
P21_4
SIN1
General-purpose input/output ports
PPG timer output pins
General-purpose input/output port
I/O
CK1
P21_5
Output compare output pin
Reload timer output pin
P21_6
53
Output compare output pin
P15_3
TOT3
326
Output compare output pin
Reload timer output pin
P15_1
OCU1
Free-run timer input pin
General-purpose input/output port
TOT0
32
Clock input/output pin of LIN-USART3
Up/down counter input pin
P15_0
31
Data output pin of LIN-USART3
Up/down counter input pin
P20_6
30
Data input pin of LIN-USART3
Up/down counter input pin
P20_5
SOT3
Free-run timer input pin
General-purpose input/output port
AIN1
29
Clock input/output pin of LIN-USART2
Up/down counter input pin
P20_4
28
Function
Clock input/output pin of LIN-USART1
Free-run timer input pin
I/O
I/O
General-purpose input/output port
Data output pin of LIN-USART1
General-purpose input/output port
Data input pin of LIN-USART1
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27.1
MB91460N series
Table 27.1-1 I/O Ports Functions (3 / 3)
Pin no.
Pin name
I/O
P21_2
56
SCK0
General-purpose input/output port
I/O
CK0
57
58
P21_1
SOT0
P21_0
SIN0
60
61
62
ICU3
TIN3
I/O
I/O
General-purpose input/output port
Data output pin of LIN-USART0
General-purpose input/output port
Data input pin of LIN-USART0
General-purpose input/output port
I/O
Input capture input pin
External trigger input pin of reload timer
TTG3
PPG timer input pin
P14_2
General-purpose input/output port
ICU2
TIN2
I/O
Input capture input pin
External trigger input pin of reload timer
TTG2
PPG timer input pin
P14_1
General-purpose input/output port
ICU1
TIN1
I/O
Input capture input pin
External trigger input pin of reload timer
TTG1
PPG timer input pin
P14_0
General-purpose input/output port
ICU0
TIN0
TTG0
CM44-10149-1E
Clock input/output pin of LIN-USART0
Free-run timer input pin
P14_3
59
Function
I/O
Input capture input pin
External trigger input pin of reload timer
PPG timer input pin
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MB91460N series
27.2 Port Register Settings
27.2.1 General Rules
For all ports, the following rules are valid:
1. All port inputs are disabled by default to avoid transverse current floating before the ports are configured
by software. After configuring each port pin according to its function it is necessary to enable the port inputs
with the global port enable (PORTEN:GPORTEN). See section "27.2.3 Port Input Enable".
2. Each port has a Port Data Register direct read (PDRD) to sample the pin data with CLKP. This register is
read-only.
3. Each port has a Data Direction Register (DDR) to switch the port's input/output direction. After reset, all
ports are input (DDR=00H).
• Port Input mode (PFR = 0 and DDR = 0)
PDRD read : Reads the sampled pin data.
PDR read
: Reads the sampled pin data.
PDR write : Writes the PDR setting value, has no effect on the pin value.
• Port Output mode (PFR = 0 and DDR = 1)
PDRD read : Reads the sampled pin data.
PDR read
: Reads the PDR register value.
PDR write : Writes the PDR setting value to the corresponding external pins.
4. On a Read-Modify-Write instruction (bit operations) always the PDR register is read independent of the
Data Direction Register (DDR) settings.
5. Certain ports have a Port Function Register (PFR) and an Extra Port Function Register (EPFR). To enable
the function determined by EPFR=1 it is necessary to also set PFR=1. On MB91V460A the behaviour of
setting EPFR=1 and PFR=0 equals the port input/output mode (reserved for future use).
6. Each port has a Port Input Level Register (PILR) to bit-wise select the input level (CMOS-Hysteresis /
Automotive [/ TTL]). The default value depends on the function of the port.
The input level can be set in every device mode. See section "27.2.5 Port Input Level Selection".
7. Certain ports have programmable Pull-Ups/Pull-Downs (50 kΩ) which are enabled bit-wise by their Pull-Up/
Pull-Down Enable Registers (PPER) and Pull-Up/Pull-Down Control Registers (PPCR). See section "27.2.6
Programmable Pull-Up/Pull Down Resistors".
8. Each port has one or two Port Function Registers: PFR and, if necessary, Extra PFR (EPFR). Together,
they can serve up to 3 resource I/O’s per pin. See section "27.2.4 Port Function Register Setup".
9. Port setup controlled by the MD[2:0] pins and the mode register MODR overwrites the setup in the port
registers. E.g. External Bus Mode overwrites port register setup. The external bus signal output can be
disabled by setting the PFR of the pin to port mode (PFR=0).
10.Resource input lines are generally connected to the pin and are enabled by setting the appropriate
functionality inside the resource. There are exceptions which are listed in "27.2.4 Port Function Register
Setup".
11.External Interrupt input lines are always connected to the pin and are enabled in the External Interrupt
unit.
12.In STOP state (STCR:STOP set and STCR:HIZ not set) all pins keep their state (input or output depending
on the configuration before entering the STOP state) and the input stages and lines are internally fixed to
avoid transverse current. External interrupt input pins are not fixed if the corresponding pin is selected by
using the PFR=1 setting and the corresponding external interrupt request is enabled with the ENIR0, resp.
ENIR1 registers. Pull-Ups and Pull-Downs are enabled.
13.In STOP-HIZ state (STCR:STOP and STCR:HIZ set) all pins are switching to input (high impedance state)
and all input stages and lines are internally fixed to avoid floating. External interrupt input pins are not fixed
if the corresponding pin is selected by using the PFR=1 setting and the corresponding external interrupt
request is enabled with the ENIR0, resp. ENIR1 registers. Pull-Ups and Pull-Downs are disabled.
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14.Resource output lines are enabled by setting the corresponding PFR and/or EPFR bit in the port. Details
see section "27.2.4 Port Function Register Setup". LIN-USART outputs (SOT) must be enabled
additionally by setting the SOE bit in the LIN-USART control.
15.Resource bidirectional signals (e.g. SCK of the LIN-USART) are enabled by setting the corresponding
PFR and/or EPFR bit in the port. The signal direction is controlled by the setup of the resource, e.g. via the
output enable bits. Details see section "27.2.4 Port Function Register Setup".
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27.2.2 I/O Port Block Diagram
Figure 27.2-1 Block diagram of an I/O port
Port Bus
PILR
EPILR
External bus interface inputs
Peripheral inputs
TTL
PDRD read
&
Automotive
Hysteresis
0
CLKP
PDRD
CMOS
Hysteresis
&
&
1
STOP or
GPORTEN
PDR read
PPER
PPCR
Out Driver
1. Peripheral output
2. Peripheral output
50 kΩ
P-ch
Pull Up/
Down
Control
Pin
Output
MUX
PDR
50 kΩ
N-ch
DDR
Port
Direction
Control
PFR
EPFR
PODR
PDR:
PDRD:
DDR:
PFR:
EPFR:
PODR:
PILR:
EPILR:
PPER:
PPCR:
330
Port Data Register
Port Data Direct Register
Data Direction Register
Port Function Register
Extra PFR Port Function Register
Port Output Drive Register
Port Input Level selection Register
Port Input Level selection Register
Port Pull up/down Enable Register
Port Pull up/down Control Register
Address 0x000H + #port (Port00: 000H, Port01: 001H,...)
Address = PDR + D00H
Address = PDR + D40H
Address = PDR + D80H
Address = PDR + DC0H
optional
Address = PDR + E00H
optional
optional
Address = PDR + E40H
optional
Address = PDR + E80H
Address = PDR + EC0H
optional
optional
Address = PDR + F00H
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Chapter 27 I/O Ports
27.2
MB91460N series
27.2.3 Port Input Enable
This section describes the Port Input Enable function.
■ PORTEN: Port Input Enable.
PORTEN
Addr
7
6
5
4
3
2
1
0
initial
000498H
-
-
-
-
-
-
CPORTEN
GPORTEN
---- --00B
-
-
-
-
-
-
R/W
R/W
All port inputs are disabled by default to avoid transverse current floating in the IO input stages and the
subsequent logic. After configuring all ports according to their functional specification (input level, output drive,
pull-up or pull-down resistor, etc.) it is mandatory to globally enable the inputs by setting the port input enable bit.
GPORTEN
0 - The inputs of all ports are disabled.
1 - The inputs of all ports are enabled.
CPORTEN
0 - The inputs of the bootloader communication ports are disabled.
1 - The inputs of the bootloader communication ports are enabled.
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Chapter 27 I/O Ports
27.2
MB91460N series
27.2.4 Port Function Register Setup
This section describes the Port Function Registers of each port.
■ P14: The functions of Port 14 are controlled by PFR14 and EPFR14
Addr
7
6
5
4
3
2
1
0
initial
PFR14
000D8EH
-
-
-
-
PFR14.3
PFR14.2
PFR14.1
PFR14.0
0000 0000B
EPFR14
000DCEH
-
-
-
-
EPFR14.3
EPFR14.2
EPFR14.1
EPFR14.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P14[3:0] is input/output for Input Capture inputs ICU[3:0], Reload Timer triggers TIN[3:0] and PWM inputs
TTG[3:0]. Otherwise, the port can be used as general purpose port.
PFR14.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TIN3 and TTG3 input, and
EPFR14.3 0 - Resource function is ICU3 input
1 - ICU3 is internally connected to LSYN of LIN-USART 3
PFR14.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TIN2 and TTG2 input, and
EPFR14.2 0 - Resource function is ICU2 input
1 - ICU2 is internally connected to LSYN of LIN-USART 2
PFR14.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TIN1 and TTG1 input, and
EPFR14.1 0 - Resource function is ICU1 input
1 - ICU1 is internally connected to LSYN of LIN-USART 1
PFR14.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TIN0 and TTG0 input, and
EPFR14.0 0 - Resource function is ICU0 input
1 - ICU0 is internally connected to LSYN of LIN-USART 0
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■ P15: The functions of Port 15 are controlled by PFR15 and EPFR15
Addr
7
6
5
4
3
2
1
0
initial
PFR15
000D8FH
-
-
-
-
PFR15.3
PFR15.2
PFR15.1
PFR15.0
0000 0000B
EPFR15
000DCFH
-
-
-
-
EPFR15.3
EPFR15.2
EPFR15.1
EPFR15.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P15[3:0] is input/output for Output Compare outputs OCU[3:0] and Reload Timer outputs TOT[3:0]. Otherwise,
the port can be used as general purpose port.
PFR15.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR15.3 0 - Resource function is OCU3 output
1 - Resource function is TOT3 output
PFR15.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR15.2 0 - Resource function is OCU2 output
1 - Resource function is TOT2 output
PFR15.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR15.1 0 - Resource function is OCU1 output
1 - Resource function is TOT1 output
PFR15.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR15.0 0 - Resource function is OCU0 output
1 - Resource function is TOT0 output
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■ P17: The functions of Port 17 are controlled by PFR17
PFR17
Addr
7
6
5
4
3
2
1
0
initial
000D91H
PFR17.7
PFR17.6
PFR17.5
PFR17.4
PFR17.3
PFR17.2
PFR17.1
PFR17.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P17[7:0] is input/output for Programmable Pulse Generator outputs PPG[7:0]. Otherwise, the port can be used
as general purpose port.
PFR17.7
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG7 output
PFR17.6
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG6 output
PFR17.5
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG5 output
PFR17.4
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG4 output
PFR17.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG3 output
PFR17.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG2 output
PFR17.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG1 output
PFR17.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is PPG0 output
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27.2
MB91460N series
■ P20: The functions of Port 20 are controlled by PFR20 and EPFR20
Addr
7
6
5
4
3
2
1
0
initial
PFR20
000D94H
-
PFR20.6
PFR20.5
PFR20.4
-
PFR20.2
PFR20.1
PFR20.0
-000 -000B
EPFR20
000DD4H
-
EPFR20.6
EPFR20.5
-
-
EPFR20.2
EPFR20.1
-
-00- -00-B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P20_6 to P20_4, P20_2 to P20_0 pins are input/output for LIN-UART serial communication signals SCK, SOT,
SIN of channels 2 and 3, Up-/Down-Counter inputs ZIN, BIN, AIN of channels 0 and 1, and Free-Run Timer FRT
inputs CK of channels 2 and 3. Otherwise, the port can be used as general purpose port.
PFR20.6
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR20.6 0 - Resource function is SCK3 input/output
1 - Resource function is ZIN1 and CK3 input
PFR20.5
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR20.5 0 - Resource function is SOT3 output
1 - Resource function is BIN1 input
PFR20.4
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SIN3 and AIN1 input
PFR20.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR20.2 0 - Resource function is SCK2 input/output
1 - Resource function is ZIN0 and CK2 input
PFR20.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR20.1 0 - Resource function is SOT2 output
1 - Resource function is BIN0 input
PFR20.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SIN2 and AIN0 input
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MB91460N series
■ P21: The functions of Port 21 are controlled by PFR21 and EPFR21
Addr
7
6
5
4
3
2
1
0
initial
PFR21
000D95H
-
PFR21.6
PFR21.5
PFR21.4
-
PFR21.2
PFR21.1
PFR21.0
-000 -000B
EPFR21
000DD5H
-
EPFR21.6
-
-
-
EPFR21.2
-
-
-0-- -0--B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P21_6 to P21_4, P21_2 to P21_0 are input/output for LIN-USART serial communication signals SCK, SOT, SIN
of channels 0 and 1, and Free-Run Timer FRT inputs CK of channels 0 and 1. Otherwise, the port can be used as
general purpose port.
PFR21.6
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR21.6 0 - Resource function is SCK1 input/output
1 - Resource function is CK1 input
PFR21.5
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SOT1 output
PFR21.4
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SIN1 input
PFR21.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
EPFR21.2 0 - Resource function is SCK0 input/output
1 - Resource function is CK0 input
PFR21.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SOT0 output
PFR21.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SIN0 input
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MB91460N series
■ P22: The functions of Port 22 are controlled by PFR22
PFR22
Addr
7
6
5
4
3
2
1
0
initial
000D96H
-
-
-
-
PFR22.3
PFR22.2
PFR22.1
PFR22.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P22[3:0] is input/output for CAN serial communication signals TX, RX of channels 4 and 5, and External Interrupt
Triggers INT[13:12]. Otherwise, the port can be used as general purpose port.
PFR22.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TX5 output
PFR22.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is RX5 input, and INT13 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR1:EN13 set to "1".
PFR22.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is TX4 output
PFR22.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is RX4 input, and INT12 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR1:EN12 set to "1".
Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, LINUSART.SIN) also in the Port I/O input mode (PFR=0 and DDR=0). In that case the internal input line is forced to
low in STOP-HIZ state.
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MB91460N series
■ P24: The functions of Port 24 are controlled by PFR24
PFR24
Addr
7
6
5
4
3
2
1
0
initial
000D98H
PFR24.7
PFR24.6
PFR24.5
PFR24.4
PFR24.3
PFR24.2
PFR24.1
PFR24.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P24[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 2 and 3, and External
Interrupt Triggers INT[7:0]. Otherwise, the port can be used as general purpose port.
PFR24.7
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SCL3 open drain, and INT7 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN7 set to "1".
PFR24.6
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SDA3 open drain, and INT6 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN6 set to "1".
PFR24.5
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SCL2 open drain, and INT5 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN5 set to "1".
PFR24.4
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is SDA2 open drain, and INT4 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN4 set to "1".
PFR24.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is INT3 input, and MONCLK output when the clock monitor is available.
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN3 set to "1".
PFR24.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is INT2 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
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27.2
MB91460N series
interrupt request is enabled with ENIR0.EN2 set to "1".
PFR24.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is INT1 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN1 set to "1".
PFR24.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is INT0 input
Remark: This pin supports external interrupt wake up from STOP-HIZ state. Because of this
the internal input line is not forced to low in STOP-HIZ state if the PFR is set to "1" and
interrupt request is enabled with ENIR0.EN0 set to "1".
Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN)
also in the Port I/O input mode (PFR=0 and DDR=0). In that case the internal input line is forced to low in STOPHIZ state.
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Chapter 27 I/O Ports
27.2
MB91460N series
■ P29: The functions of Port 29 are controlled by PFR29
PFR29
Addr
7
6
5
4
3
2
1
0
initial
000D9DH
PFR29.7
PFR29.6
PFR29.5
PFR29.4
PFR29.3
PFR29.2
PFR29.1
PFR29.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P29[7:0] is input/output for A/D converter analogue inputs AN[7:0]. Otherwise, the port can be used as general
purpose port.
PFR29.7
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN7 input
PFR29.6
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN6 input
PFR29.5
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN5 input
PFR29.4
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN4 input
PFR29.3
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN3 input
PFR29.2
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN2 input
PFR29.1
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN1 input
PFR29.0
0 - Port is in general purpose port mode.
1 - Port is in resource function mode:
Resource function is AN0 input
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27.2
MB91460N series
27.2.5 Port Input Level Selection
The input levels of each port can be programmed bit-wise between CMOS Hysteresis type 1 and 2, Automotive
Hysteresis and TTL level.
Table 27.2-1 Input Level VIL/VIH
Input Level
VIL
VIH
CMOS input
0.3 × VDD
0.7 × VDD
CMOS Hysteresis type1 input
0.3 × VDD
0.7 × VDD
CMOS Hysteresis type2 input
0.2 × VDD
0.8 × VDD
Automotive Hysteresis input
0.5 × VDD
0.8 × VDD
0.8
2.0
TTL input
For setup, the Port Input Level Registers (PILR, EPILR) of each port are used.
Table 27.2-2 Settings of the MB91460N Series (GP14 to GP29)
PILRx.y
EPILRx.y
Port Input Level
0 (default)
0 (default)
CMOS Hysteresis A
1
0
Automotive Hysteresis
0
1
TTL
1
1
CMOS Hysteresis B
Addr
7
6
5
4
3
2
1
0
initial
PILR14
000E4EH
-
-
-
-
PILR14.3
PILR14.2
PILR14.1
PILR14.0
---- 0000B
PILR15
000E4FH
-
-
-
-
PILR15.3
PILR15.2
PILR15.1
PILR15.0
---- 0000B
PILR17
000E51H
PILR17.7
PILR17.6
PILR17.5
PILR17.4
PILR17.3
PILR17.2
PILR17.1
PILR17.0
0000 0000B
PILR20
000E54H
-
PILR20.6
PILR20.5
PILR20.4
-
PILR20.2
PILR20.1
PILR20.0
-000 -000B
PILR21
000E55H
-
PILR21.6
PILR21.5
PILR21.4
-
PILR21.2
PILR21.1
PILR21.0
-000 -000B
PILR22
000E56H
-
-
-
-
PILR22.3
PILR22.2
PILR22.1
PILR22.0
---- 0000B
PILR24
000E58H
PILR24.7
PILR24.6
PILR24.5
PILR24.4
PILR24.3
PILR24.2
PILR24.1
PILR24.0
0000 0000B
PILR29
000E5DH
PILR29.7
PILR29.6
PILR29.5
PILR29.4
PILR29.3
PILR29.2
PILR29.1
PILR29.0
0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 27 I/O Ports
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Addr
MB91460N series
7
6
5
4
3
2
1
0
initial
EPILR14 000E8EH
-
-
-
-
EPILR14_3 EPILR14_2 EPILR14_1 EPILR14_0
---- 0000B
EPILR15 000E8FH
-
-
-
-
EPILR15_3 EPILR15_2 EPILR15_1 EPILR15_0
---- 0000B
EPILR17 000E91H EPILR17_7 EPILR17_6 EPILR17_5 EPILR17_4 EPILR17_3 EPILR17_2 EPILR17_1 EPILR17_0 0000 0000B
EPILR20 000E94H
-
EPILR20_6 EPILR20_5 EPILR20_4
-
EPILR20_2 EPILR20_1 EPILR20_0 -000 -000B
EPILR21 000E95H
-
EPILR21_6 EPILR21_5 EPILR21_4
-
EPILR21_2 EPILR21_1 EPILR21_0 -000 -000B
EPILR22 000E96H
-
-
-
-
EPILR22_3 EPILR22_2 EPILR22_1 EPILR22_0
---- -000B
EPILR24 000E98H EPILR24_7 EPILR24_6 EPILR24_5 EPILR24_4 EPILR24_3 EPILR24_2 EPILR24_1 EPILR24_0 0000 0000B
EPILR29 000E9DH EPILR29_7 EPILR29_6 EPILR29_5 EPILR29_4 EPILR29_3 EPILR29_2 EPILR29_1 EPILR29_0 0000 0000B
R/W
342
R/W
R/W
R/W
R/W
R/W
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R/W
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27.2
MB91460N series
27.2.6 Programmable Pull-Up/Pull Down Resistors
The Ports listed in the following table have 50 kΩ Pull-Up resistors, which can be enabled bit-wise. The function is
enabled by the Port Pull Enable Registers (PPER) and controlled by the Port Pull Control Register (PPCR). The
PPCR selects Pull-Up or Pull-Down. The Pull-Up/Pull-Down are disabled automatically in the STOP-HiZ state
(STCR:STOP and STCR:HIZ set).
Port Pull-Up/Pull-Down Enable Registers
Bit
PPERx.y
0 (default)
1
Pull-Up/Pull-Down disabled
Pull-Up/Pull-Down enabled
Addr
7
6
5
4
3
2
1
0
initial
PPER14
000ECEH
-
-
-
-
PPER14.3
PPER14.2
PPER14.1
PPER14.0
---- 0000B
PPER15
000ECFH
-
-
-
-
PPER15.3
PPER15.2
PPER15.1
PPER15.0
---- 0000B
PPER17
000ED1H
PPER17.7
PPER17.6
PPER17.5
PPER17.4
PPER17.3
PPER17.2
PPER17.1
PPER17.0 0000 0000B
PPER20
000ED4H
-
PPER20.6
PPER20.5
PPER20.4
-
PPER20.2
PPER20.1
PPER20.0
-000 -000B
PPER21
000ED5H
-
PPER21.6
PPER21.5
PPER21.4
-
PPER21.2
PPER21.1
PPER21.0
-000 -000B
PPER22
000ED6H
-
-
-
-
PPER22.3
PPER22.2
PPER22.1
PPER22.0
---- 0000B
PPER24
000ED8H
PPER24.7
PPER24.6
PPER24.5
PPER24.4
PPER24.3
PPER24.2
PPER24.1
PPER24.0 0000 0000B
PPER29
000EDDH
PPER29.7
PPER29.6
PPER29.5
PPER29.4
PPER29.3
PPER29.2
PPER29.1
PPER29.0 0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
It is necessary to disable the Pull-Up/Pull Downs first (See "Programmable Pull-Up/Pull Down Resistors" on P.
343), before changing the setting of the PPCRx.y bit. After changing this bit you have to reenable the Pull-Up/
Pull Downs.
Port Pull-Up/Pull-Down Control Registers
Bit
PPCRx.y
Addr
0
1 (default)
Pull Down is selected
Pull-Up is selected
7
6
5
4
3
2
1
0
initial
PPCR14 000F0EH
-
-
-
-
PPCR14.3
PPCR14.2
PPCR14.1
PPCR14.0
---- 1111B
PPCR15 000F0FH
-
-
-
-
PPCR15.3
PPCR15.2
PPCR15.1
PPCR15.0
---- 1111B
PPCR17 000F11H PPCR17.7
PPCR17.6
PPCR17.5
PPCR17.4
PPCR17.3
PPCR17.2
PPCR17.1
PPCR17.0
1111 1111B
PPCR20 000F14H
-
PPCR20.6
PPCR20.5
PPCR20.4
-
PPCR20.2
PPCR20.1
PPCR20.0
-111 -111B
PPCR21 000F15H
-
PPCR21.6
PPCR21.5
PPCR21.4
-
PPCR21.2
PPCR21.1
PPCR21.0
-111 -111B
PPCR22 000F16H
-
-
-
-
PPCR22.3
PPCR22.2
PPCR22.1
PPCR22.0
---- 1111B
PPCR24 000F18H PPCR24.7
PPCR24.6
PPCR24.5
PPCR24.4
PPCR24.3
PPCR24.2
PPCR24.1
PPCR24.0
1111 1111B
PPCR29 000F1DH PPCR29.7
PPCR29.6
PPCR29.5
PPCR29.4
PPCR29.3
PPCR29.2
PPCR29.1
PPCR29.0
1111 1111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
PPCR Register bits can only be written, if the attached PPER register bit is low (resistors disabled).
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Chapter 27 I/O Ports
27.2
MB91460N series
27.2.7 Programmable Port Output Drive
The Ports listed in the following table have a programmable output drive option, which can be enabled bit-wise.
The function is enabled by the Port Output Drive Registers (PODR).
Port Output Drive Registers
Bit
PODRx.y
Addr
0 (default)
1
5 mA output drive
2 mA output drive
7
6
5
4
3
2
1
0
initial
PODR14 000E0EH
-
-
-
-
PODR14.3
PODR14.2
PODR14.1
PODR14.0
---- 0000B
PODR15 000E0FH
-
-
-
-
PODR15.3
PODR15.2
PODR15.1
PODR15.0
---- 0000B
PODR17 000E11H
PODR17.7
PODR17.6
PODR17.5
PODR17.4
PODR17.3
PODR17.2
PODR17.1
PODR17.0 0000 0000B
PODR20 000E14H
-
PODR20.6
PODR20.5
PODR20.4
-
PODR20.2
PODR20.1
PODR20.0 -000 -000B
PODR21 000E15H
-
PODR21.6
PODR21.5
PODR21.4
-
PODR21.2
PODR21.1
PODR21.0 -000 -000B
PODR22 000E16H
-
-
-
-
PODR22.3
PODR22.2
PODR22.1
PODR22.0
PODR24 000E18H
PODR24.7
PODR24.6
PODR24.5
PODR24.4
PODR24.3
PODR24.2
PODR24.1
PODR24.0 0000 0000B
PODR29 000E1DH PODR29.7
PODR29.6
PODR29.5
PODR29.4
PODR29.3
PODR29.2
PODR29.1
PODR29.0 0000 0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
344
FUJITSU MICROELECTRONICS LIMITED
---- 0000B
R/W
CM44-10149-1E
Chapter 28 LIN-USART
28.1
MB91460N series
Chapter 28 LIN-USART
28.1 Overview
This chapter explains the function and operation of the LIN-USART. The LIN-USART with LIN (Local
Interconnect Network) - Function is a general-purpose serial data communication interface for performing
synchronous or asynchronous communication with external devices.
The LIN-USART provides bidirectional communication function (normal mode), master-slave communication
function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working
both as master or as slave device).
■ LIN-USART Functions
LIN-USART is a general-purpose serial data communication interface for transmitting serial data to and
receiving data from another CPU or peripheral devices. It has the functions listed in
table 28.1-1.
Table 28.1-1 LIN-USART functions
Function
Item
Channel
4 channels
Data buffer
Full-duplex
Serial Input
5 times oversampling in asynchronous mode
Transfer mode
- Clock synchronous (start-stop synchronization and
start-stop-bit-option)
- Clock asynchronous (using start-, stop-bits)
Baud rate
- A dedicated baud rate generator is provided, which
consists of a 15-bit-reload counter
- An external clock can be input and also be adjusted
by the reload counter
Data length
- 7 bits (not in synchronous or LIN mode)
- 8 bits
Signal mode
Non-return to zero (NRZ) and return to zero (RZ)
Start bit timing
Clock synchronization to the falling edge of the start bit
in asynchronous mode
Reception error
detection
- Framing error
- Overrun error
- Parity error
Interrupt request
- Reception interrupt (reception complete, reception
error detect, Bus-Idle, LIN-Synch-break detect)
- Transmission interrupt (transmission complete)
Master-slave communication
function
(multiprocessor mode)
One-to-n communication (one master to n slaves)
(This function is supported both for master and slave
system).
Synchronous mode
Function as Master- or Slave-USART
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Chapter 28 LIN-USART
28.1
MB91460N series
Table 28.1-1 LIN-USART functions (Continued)
Transceiving pins
Direct access possible
LIN bus options
- Operation as master device
- Operation as slave device
- Generation of LIN-Sync-break
- Detection of LIN-Sync-break
- Detection of start/stop edges in LIN-Sync-field
connected to ICU 0 and 2
Synchronous serial clock
The synchronous serial clock can be output
continuously on the SCK pin for synchronous
communication with start & stop bits
Clock delay option
Special synchronous Clock Mode for delaying clock
(useful for SPI-compliance)
■ LIN-USART operation modes
The LIN-USART operates in four different modes, which are determined by the MD0- and the MD1-bit of the
Serial mode register (SMR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/
slave communication and mode 3 for LIN master/slave communication.
Table 28.1-2 LIN-USART operation modes
Operation
mode
0
normal mode
1
multiprocessor
2
normal mode
3
LIN mode
Data length
parity
disabled
parity
enabled
7 or 8
7 or 8 + 1**
8
8
-
Synchronization of mode
Length
of
stop bit
data bit
directio
n*
asynchronous
1 or 2
L/M
asynchronous
1 or 2
L/M
synchronous
0, 1 or 2
L/M
asynchronous
1
L
* means the data bit transfer format: LSB or MSB first.
** "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.
Mode 1 operation is supported both for master or slave operation of LIN-USART in a master-slave connection
system. In Mode 3 the LIN-USART function is locked to 8N1-Format, LSB first.
If the mode is changed, LIN-USART cuts off all possible transmission or reception and then awaits new action.
The MD1 and MD0 bits of the Serial Mode Register (SMR) determine the operation mode of LIN-USART as
shown in the following table:
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CM44-10149-1E
Chapter 28 LIN-USART
28.1
MB91460N series
Table 28.1-3 Mode Bit Setting
MD1
MD0
Mode
Description
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
3
Asynchronous (LIN mode)
■ LIN-USART Interrupts
Table 28.1-4 LIN-USART interrupts
Interrupt cause
Interrupt
number
Interrupt control register
Interrupt Vector
Register name
Address
Offset
Default address
LIN-USART0 reception interrupt
#54(36H)
ICR19
000453H
324H
0FFF24H
LIN-USART0 transmission
interrupt
#55(37H)
ICR19
000453H
320H
0FFF20H
LIN-USART1 reception interrupt
#56(38H)
ICR20
000454H
31CH
0FFF1CH
LIN-USART1 transmission
interrupt
#57(39H)
ICR20
000454H
318H
0FFF18H
LIN-USART2 reception interrupt
#58(3AH)
ICR21
000455H
314H
0FFF14H
LIN-USART2 transmission
interrupt
#59(3BH)
ICR21
000455H
310H
0FFF10H
LIN-USART3 reception interrupt
#60(3CH)
ICR22
000456H
30CH
0FFF0CH
LIN-USART3 transmission
interrupt
#61(3DH)
ICR22
000456H
308H
0FFF08H
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Chapter 28 LIN-USART
28.2
MB91460N series
28.2 LIN-USART Configuration
■ LIN-USART consists of the following blocks:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
348
Reload Counter
Reception Control Circuit
Reception Shift Register
Reception Data Register (RDR)
Transmission Control Circuit
Transmission Shift Register
Transmission Data Register (TDR)
Error Detection Circuit
Oversampling Unit
Interrupt Generation Circuit
LIN Break Generation
LIN Break and Synch Field Detection
Bus Idle Detection Circuit
Serial Mode Register (SMR)
Serial Control Register (SCR)
Serial Status Register (SSR)
Extended Com. Contr. Reg. (ECCR)
Extended Status/Contr. Reg. (ESCR)
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 28 LIN-USART
28.2
MB91460N series
Figure 28.2-1 LIN-USART Block Diagram
(OTO,
EXT,
REST)
CLKP
PE
ORE FRE
TIE
RIE
LBIE
LBD
BIE
RBI
TBI
transmission clock
Reload
Counter
TRANSMISSION
CONTROL
CIRCUIT
RECEPTION
CONTROL
CIRCUIT
Pin
Reception Restart
Reload Counter
SIN
Interrupt
Generation
circuit
reception clock
SCK
Pin
Start bit
Detection
circuit
Transmission
Start circuit
Received
Bit counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
reception
IRQ
transm.
IRQ
TDRE
SOT
Oversampling
Unit
Pin
RDRF
LIN break
and Synch
Field
Detection
circuit
Signal
to ICU
reception
complete
SOT
SIN
SIN
Reception
shift register
Transmission
shift register
transmission
start
Bus idle
Detection
circuit
Error
Detection
RDR (FIFO)
PE
ORE
FRE
LIN
break
generation
circuit
LBR
LBL1
LBL0
TDR (FIFO)
RBI
TBI
LBD
R-bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSR
register
CM44-10149-1E
MD1
MD0
(OTO)
(EXT)
(REST)
UPCL
SCKE
SOE
SMR
register
PEN
P
SBL
CL
A/D
CRE
RXE
TXE
SCR
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
ESCR
register
FUJITSU MICROELECTRONICS LIMITED
LBR
MS
SCDE
SSM
BIE
RBI
TBI
ECCR
register
349
Chapter 28 LIN-USART
28.2
MB91460N series
■ Explanation of the different blocks
• Reload Counter
The reload counter functions as the dedicated baud rate generator. It can select external input clock or CLKP
for the transmitting and receiving clocks. The reload counter has a 15 bit register for the reload value. The
actual count of the transmission reload counter can be read via the BGR0/1 registers.
• Reception Control Circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity
counter. The received bit counter counts reception data bits. When reception of one data item for the specified
data length is complete, the received bit counter sets the Reception data register full flag. When the FIFO is
enabled, the flag is set if the triggerlevel is reached. The start bit detection circuit detects start bits from the
serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start
bits. The reception parity counter calculates the parity of the reception data.
• Reception Shift Register
The reception shift register fetches reception data input from the SIN pin, shifting the data bit by bit. When
reception is complete, the reception shift register transfers receive data to the RDR register.
• Reception Data Register
This register retains reception data. Serial input data is converted and stored in this register.
• Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter.The transmission bit counter counts transmission data bits. When the transmission
of one data item of the specified data length is complete, the transmission bit counter sets the Transmission
data register full flag. The transmission start circuit starts transmission when data is written to TDR. The
transmission parity counter generates a parity bit for data to be transmitted if parity is enabled.
• Transmission Shift Register
The transmission shift register transfers data written to the TDR register to itself and outputs the data to the
SOT pin, shifting the data bit by bit.
• Transmission Data Register
This register sets transmission data. Data written to this register is converted to serial data and output.
• Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
• Oversampling Unit
The oversampling unit oversamples the incoming data at the SIN pin for five times. It is switched off in
synchronous operation mode.
• Interrupt Generation Circuit
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a
corresponding request enable bit is set and an interrupt case occurs the interrupt request will be generated
immediately.
• LIN Break and Synchronization Field Detection Circuit
The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is
sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth
falling edge of the synchronization field is recognized by this circuit by generating an internal signal for the
Input Capture Unit to measure the actual serial clock time of the transmitting master node.
• LIN Break Generation Circuit
The LIN break generation circuit generates a LIN break of a determined length.
• Bus Idle Detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case the
circuit generates a special flag bit.
• Serial Mode Register
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CM44-10149-1E
Chapter 28 LIN-USART
28.2
MB91460N series
This register performs the following operations:
• Selecting the LIN-USART operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting the LIN-USART (preserving the settings of the registers)
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
• Serial Control Register
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable transmission
• Specifying whether to enable reception
• Serial Status Register
This register indicates the transmission and reception status and error status, and enables/disables
transmission and reception interrupt requests.
• Extended Status/Control Register
This register provides several LIN functions, direct access to the SIN and SOT pin and setting for the LINUSART synchronous clock mode.
• Extended Communication Control Register
The extended communication control register provides bus idle recognition interrupt settings, synchronous
clock settings, and the LIN break generation.
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Chapter 28 LIN-USART
28.3
MB91460N series
28.3 LIN-USART Pins
■ LIN-USART Pins
The LIN-USART pins also serve as general ports. Table 28.3-1 lists the pin functions, I/O formats, and settings
required to use LIN-USART.
Table 28.3-1 LIN-USART Pins
Standby
control
Setting required to use
pin
Pin function
SIN
Port I/O or serial
data input
Set port function mode:
PFR: bit0 = 1,
EPFR: bit0 = 0
Port I/O or serial
data output
Set to output enable mode:
SMR: SOE = 1,
Set port function mode:
PFR: bit1 = 1
EPFR: bit1 = 0
SOT
SCK
I/O format
Pull-up
Pull-down
Pin name
CMOS output and
CMOS hysteresis, CMOS Automotive hysteresis,
TTL input
Programmable
Provided
Set port function mode:
PFR: bit2 = 1
EPFR: bit2 = 0
Set to output enable mode
when a clock is output
SMR: SCKE = 1
Port I/O or serial
clock input/output
Figure 28.3-1 Block Diagram of LIN-USART pins
Port Bus
PDR read
Peripheral input
Peripheral output
PDR
Pin
PFR
DDR
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CM44-10149-1E
Chapter 28 LIN-USART
28.4
MB91460N series
28.4 LIN-USART Registers
The following table defines the LIN-USART0 to 3 registers:
Table 28.4-1 LIN-USART0 to 3 Registers
Address
000040H
000041H
000042H
000043H
000044H
000045H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
000050H
000051H
000052H
000053H
000054H
000055H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
bit15
bit8
bit7
bit0
SCR0(Serial Control Register 0)
SMR0(Serial Mode Register 0)
SSR0(Serial Status Register 0)
RDR0/TDR0(Rx, Tx Data Register 0)
ESCR0(Extended Status/Control Register 0)
ECCR0(Extended Communication Control
Register 0)
SCR1(Serial Control Register 1)
SMR1(Serial Mode Register 1)
SSR1(Serial Status Register 1)
RDR1/TDR1(Rx, Tx Data Register 1)
ESCR1(Extended Status/Control Register 1)
ECCR1(Extended Communication Control
Register 1)
SCR2(Serial Control Register 2)
SMR2(Serial Mode Register 2)
SSR2(Serial Status Register 2)
RDR2/TDR2(Rx, Tx Data Register 2)
ESCR2(Extended Status/Control Register 2)
ECCR2(Extended Communication Control
Register 2)
SCR3(Serial Control Register 3)
SMR3(Serial Mode Register 3)
SSR3(Serial Status Register 3)
RDR3/TDR3(Rx, Tx Data Register 3)
ESCR3(Extended Status/Control Register 3)
ECCR3(Extended Communication Control
Register 3)
BGR100(Baud Rate Generator Register 1 00)
BGR000(Baud Rate Generator Register 0 00)
BGR101(Baud Rate Generator Register 1 01)
BGR001(Baud Rate Generator Register 0 01)
BGR102(Baud Rate Generator Register 1 02)
BGR002(Baud Rate Generator Register 0 02)
BGR103(Baud Rate Generator Register 1 03)
BGR003(Baud Rate Generator Register 0 03)
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Chapter 28 LIN-USART
28.4
MB91460N series
28.4.1 Serial Control Register (SCR)
This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1,
clears the reception error flag, and specifies whether to enable transmission and reception.
Figure 28.4-1 Serial Control Register (SCR)
15
14
13
12
11
10
9
Initial value
00000000B
8
R/W R/W R/W R/W R/W W R/W R/W
bit8
TXE
Transmission enable
0
Disable Transmission
1
Enable Transmission
bit9
RXE
Reception enable
0
Disable Reception
1
Enable Reception
bit10
Clear Reception errors
CRE
write
read
0
ignored
1
Clear all reception
errors (PE, FRE, ORE)
read always returns 0
bit11
AD
Address / Data bit
0
Data bit
1
Address bit
bit12
CL
Character (Data frame) Length
0
7 bits
1
8 bits
bit13
SBL
Stop bit length
0
1 stop bit
1
2 stop bits
bit14
P
Parity setting
0
Even Parity enabled
1
Odd Parity enabled
bit15
PEN
354
R/W
:
Readable and writable
W
:
Write only
:
Initial value
Parity Enable
0
Parity disabled
1
Parity enabled
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CM44-10149-1E
Chapter 28 LIN-USART
28.4
MB91460N series
Table 28.4-2 Functions of each bit of serial control register (SCR)
Bit name
Function
bit15
PEN: Parity enable
bit
This bit selects whether to add a parity bit during transmission in
serial asynchronous mode or detect it during reception.
Parity is only provided in mode 0 and in mode 2 if SSM of the
ECCR is selected. This bit is fixed to 0 (no parity) in mode 3 (LIN).
bit14
P: Parity selection bit
When parity is provided and enabled this bit selects even (0) or
odd (1) parity
bit13
SBL: Stop bit length
selection bit
This bit selects the length of the stop bit of an asynchronous data
frame or a synchronous frame if SSM of the ECCR is selected.
This bit is fixed to 0 (1 stop bit) in mode 3 (LIN).
bit12
CL: Data length
selection bit
This bit specifies the length of transmission or reception data. This
bit is fixed to 1 (8 bits) in mode 2 and 3.
bit11
AD: Address/Data
selection bit *
This bit specifies the data format in multiprocessor mode 1. Writing
to this bit determines an address or data frame to be sent next,
reading from it returns the last received kind of frame. "1" indicates
an address frame, "0" indicates a usual data frame.
Note:
During a RMW-Read cycle the AD bit returns the value to be
sent instead of the last received AD bit.
see table below*
bit10
CRE: Clear reception
error flags bit
This bit clears the FRE, ORE, and PE flag of the Serial Status
Register (SSR). This bit also clears a possible reception interrupt
caused by errors.
Writing "1" to this bit clears the error flag.
Writing "0" has no effect.
Reading from it always returns 0.
Note:
Clear the reception error flag after disabling reception (RXE=0).
As soon as "1" is written to this bit, the reception operation stops
temporarily, and immediately after that, it resumes. For this
reason, unless the reception operation is disabled, correct data
may not be received.
bit9
RXE: Reception
enable bit
This bit enables LIN-USART reception.
If this bit is set to 0, LIN-USART disables the reception of data
frames. The LIN break detection in mode 0 or 3 remains
unaffected.
bit8
TXE: Transmission
enable bit
This bit enables LIN-USART transmission. If this bit is set to 0, LINUSART disables the transmission of data frames.
* see table 28.4-3 for R/W options
Table 28.4-3 * Read/Write options of AD-Bit
Cycle
Write
CM44-10149-1E
Action
Write data to be sent to AD-Bit
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Chapter 28 LIN-USART
28.4
MB91460N series
Table 28.4-3 * Read/Write options of AD-Bit
Cycle
Action
Normal Read
RMW-Read
Read received AD-Bit
Read data to be sent from AD-Bit
28.4.2 Serial Mode Register (SMR)
This register selects an operation mode and baud rate clock and specifies whether to enable output of serial
data and clocks to the corresponding pin.
Figure 28.4-2 Configuration of the Serial Mode register (SMR)
7
6
5
4
3
R/W R/W R/W R/W W
2
1
0
W R/W R/W
Initial value
00000000B
bit0
SOE
Serial Output enable
0
disable SOT pin (high Z)
1
enable SOT pin (TxData)
bit1
SCKE
Serial Clock Output enable
0
External Serial Clock Input
1
Internal Serial Clock Output
bit2
UPCL
LIN-USART programmable clear (Software Reset)
write
read
0
ignored
1
Reset LIN-USART
always 0
bit3
Restart dedicated Reload Counter
REST
write
read
0
ignored
1
Restart Counter
always 0
bit4
EXT
External Serial Clock Source enable
0
Use internal Baud Rate Generator (Reload Counter)
1
Use external Serial Clock Source
bit5
OTO
One-to-one external clock Input enable
0
Use ext. Clock with Baud Rate Generator (Reload C.)
1
Use external Clock as is
bit6
356
bit7
MD0
MD1
Readable and writable
0
0
Operation Mode Setting
R/W
:
W
:
Write only
1
0
Mode 1: Asynchronous Multiprocessor
:
Initial value
0
1
Mode 2: Synchronous
1
1
Mode 3: Asynchronous LIN
Mode 0: Asynchronous normal
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 28 LIN-USART
28.4
MB91460N series
Table 28.4-4 Bit function of the Serial Mode register (SMR) (1 / 2)
Bit name
Function
bit7
bit6
MD1 and MD0:
Operation mode
selection bits
These two bits sets the LIN-USART operation mode.
<Caution>
Set the operating mode while the operation of LIN-USART is
stopped.
If the operating mode is set during transmission or reception of
data, the transmitted or received data cannot be guaranteed.
bit5
OTO: One-to-one
external clock
selection bit
This bit is used to select slave mode in mode 2 (ECCR:MS=1).
It selects between the direct use of the external clock and the use
of the clock generated from the internal baud rate generator, for
the transmission/reception clock.
•Setting this bit to "0" selects the clock generated from the internal
baud rate generator.
•Setting this bit to "1" selects the external serial clock (SCK).
When the EXT bit (bit 4) of the register is set to "0", this bit is set to
"0", ignoring any writing.
Note:
Set it to "0" for any mode other than slave mode in mode 2.
bit4
EXT: External clock
selection bit
This bit selects the clock of the internal baud rate generator (reload
counter).
•Setting this bit to "0" selects the operating clock of the resource.
•Setting this bit to "1" selects the external serial clock (SCK).
Note:
Set it to "1" for slave mode in mode 2.
bit3
REST: Restart of
transmission reload
counter bit
This bit restarts the internal baud rate generator (reload counter).
•When "1" is written to this bit, the reload counter is reset and
restarted.
•Writing "0" to this bit does not affect the operation.
"0" is always read.
bit2
UPCL: LIN-USART
programmable clear
bit (Software reset)
Writing a 1 to this bit resets LIN-USART immediately. The register
settings are preserved. Possible reception or transmission will cut
off.
All error flags are cleared and the Reception Data Register (RDR)
contains 00H. Writing 0 to this bit has no effect. Reading from it
always returns 0.
bit1
SCKE: Serial clock
output enable
This bit controls the serial clock input-output ports.
• When this bit is 0, the SCK pin operates as serial clock input pin.
• When this bit is 1, the SCK pin operates as serial clock output
pin. In mode 2, the serial clock is output.
When slave mode in mode 2 (ECCR: MS=1) is selected, this bit
is set to "0", ignoring any writing and maintaining the "0" status.
<Caution>
• When using the SCK pin as an input/output pin of the serial
clock, always select SCK for the corresponding PFR/EPFR
setting.
Also, select external clock (EXT = 1) using the external clock
selection bit.
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Table 28.4-4 Bit function of the Serial Mode register (SMR) (2 / 2)
Bit name
bit0
358
SOE: Serial data
output enable bit
Function
• This bit enables or disables the output of serial data.
• When this bit is 0, the SOT pin outputs the default mark level.
When this bit is 1, the SOT pin outputs the transmission data.
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28.4
MB91460N series
28.4.3 Serial Status Register (SSR)
This register checks the transmission status, reception status and error status, and enables and disables the
transmission and reception interrupt requests.
Figure 28.4-3 Configuration of the Serial Status register (SSR)
15
R
14
R
13
R
12
R
11
10
9
Initial value
00001000
8
B
R R/W R/W R/W
bit8
TIE
Transmission Interrupt request enable
0
Disables Transmission Interrupt request
1
Enables Transmission Interrupt request
bit9
RIE
Reception Interrupt request enable
0
Disables Reception Interrupt request
1
Enables Reception Interrupt request
bit10
BDS
Bit direction setting
0
send / receive LSB first
1
send / receive MSB first
bit11
TDRE
Transmission data register empty
0
Transmission data register is full
1
Transmission data register is empty
bit12
RDRF
Reception data register full
0
Reception data register is empty
1
Reception data register is full
bit13
FRE
Framing error
0
No framing error occurred
1
A framing error occurred during reception
bit14
ORE
Overrun error
0
No overrun error occurred
1
An overrun error occurred during reception
bit15
PE
Parity error
R/W
:
Readable and writable
0
No parity error occurred
R
:
Flag is read only, writing to it
has no effect
1
A parity error occurred during reception
:
Initial value
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Table 28.4-5 Functions of each bit of serial status register (SSR) (1 / 2)
Bit name
360
Function
bit15
PE: Parity error
flag
•This bit is set to "1", if a reception parity error occurs when the parity is
enabled (SCR:PEN=1).
•This bit is cleared to "0", when "1" is written to the clear reception error bit
of the serial control register (SCR:CRE).
•If this bit is set to "1" when the RIE bit (bit 9) of the register is "1", a
reception interrupt request is output.
•When this flag is set, the data in the reception data register (RDR) is
invalid.
bit14
ORE: Overrun
error flag
•This bit is set to "1", when an overrun occurs during reception.
•This bit is cleared to "0", when "1" is written to the clear reception error bit
of the serial control register (SCR:CRE).
•If this bit is set to "1" when the RIE bit (bit 9) of the register is "1", a
reception interrupt request is output.
•When this flag is set, the data in the reception data register (RDR) is
invalid.
bit13
FRE: Framing
error flag
•This bit Is set to "1", when an framing error occurs during reception.
•This bit is cleared to "0", when "1" is written to the clear reception error bit
of the serial control register (SCR:CRE).
• Data in the reception data register (RDR) is invalid when this flag is set.
• A reception interrupt request is output when this flag and the RIE bit are 1.
Note: If the stop bit is set to 2 by the stop bit length selection
bit(SCR:SBL=1), "1" is set to this bit by either of the stop bits. Therefore,
use the 2nd stop bit to determine whether the received data is valid.
bit12
RDRF: Receive
data full flag
• This flag indicates the status of the reception data register (RDR).
• This flag is set to 1 when reception data is loaded into RDR and can only
be cleared to 0 when the reception data register (RDR) is read.
• When FIFO is used, this bit is set to "1" once the valid data count stored in
FIFO reaches the trigger level. And when it falls below the level, this bit is
cleared to "0".
• A reception interrupt request is output when this flag and the RIE bit are 1.
bit11
TDRE:
Transmission
data empty flag
• This flag indicates the status of the transmission data register (TDR).
• This flag is cleared to 0 when transmission data is written to TDR and is
set to 1 when data is loaded into the transmission shift register and
transmission starts.
• A transmission interrupt request is generated if this flag and the RIE bit
are 1.
• When this bit is set to "1", setting "1" to the set LIN break bit in the
extended communication control register(ECCR:LBR) changes the bit to
"0", and the LIN Break field is generated. Then, if the valid data does not
exist to TDR, the bit is set to "1".
<Caution>
This flag is set to 1 (TDR empty) as its initial value.
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28.4
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Table 28.4-5 Functions of each bit of serial status register (SSR) (2 / 2)
Bit name
Function
bit10
BDS: Transfer
direction selection
bit
This bit selects either the lowest-order bit side (LSB first) or the highestorder bit side (MSB first) from which transfer serial data is transferred.
When mode 3 is selected, this bit is set to "0", ignoring any writing and
maintaining the "0" status.
•Setting this bit to "0" selects LSB first.
•Setting this bit to "1" selects MSB first.
Note:
When writing the reception data to the reception data register (RDR), the
data in RDR becomes invalid, if the BDS bit is rewritten after the reception
data is written to RDR in order to switch between the highest and lowest
side of the data.
bit9
RIE: Reception
interrupt request
enable bit
• This bit enables or disables input of a interrupt request for transmission to
the CPU.
• A reception interrupt request is output when this bit and the reception data
flag (RDRF) are 1 or this bit and one or more error flags (PE, ORE, and
FRE) are 1.
bit8
TIE: Transmission
interrupt request
enable bit
• This bit enables or disables output of a request for transmission interrupt
to the CPU.
• A transmission interrupt request is output when this bit and the TDRE bit
are 1.
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28.4.4 Reception Data Register/Transmission Data Register (RDR / TDR)
The reception data register (RDR) holds the received data. The transmission data register (TDR) holds the
transmission data. Both RDR and TDR registers are located at the same address.
(Note)
TDR is a write-only register and RDR is a read-only register. These registers are located in the same
address, so the read value is different from the write value. Therefore, instructions that perform a
read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used.
Figure 28.4-4 Reception Data Register/Transmission Data Register (RDR / TDR)
7
6
5
4
3
2
1
0
Initial value
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 to bit0
R/W
R/W
:
Data Registers
Read
Read from Reception Data Register
Write
Write to Transmission Data Register
Readable and writable
■ Reception:
RDR is the register that contains reception data. The serial data signal transmitted to the SIN pin is converted
in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7) contains 0. When
reception is complete the data is stored in this register and the reception data full flag (SSR: RDRF) is set to 1.
If a reception interrupt request is enabled at this point, a reception interrupt request occurs.
Read RDR when the RDRF flag of the status register (SSR) is 1. The RDRF flag is cleared automatically to 0
when RDR is read. Also the reception interrupt is cleared if it is enabled and no error has occurred.
Data in RDR is invalid when a reception error occurs (SSR: PE, ORE, or FRE = 1).
■ Transmission:
When data to be transmitted is written to the transmission data register (TDR04) in transmission enable state,
it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output pin (SOT pin). If the data length is 7 bits, the uppermost bit (D7) is not sent.
When transmission data is written to this register, the transmission data empty flag (SSR: TDRE) is cleared to
0. When transfer to the transmission shift register is complete, the flag is set to 1. When the TDRE flag is 1,
the next part of transmission data can be written. If output transmission interrupt requests have been enabled,
a transmission interrupt request is generated. Write the next part of transmission data when a transmission
interrupt is generated or the TDRE flag is 1.
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28.4
MB91460N series
28.4.5 Extended Status/Control Register (ESCR)
This register provides several LIN functions, direct access to the SIN and SOT pin and setting for LIN-USART
synchronous clock mode.
Figure 28.4-5 Configuration of the Extended Status/Control Register (ESCR)
15
14
13
12
11
10
9
Initial value
00000100
8
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit8
SCES
Sampling Clock Edge Selection (Mode 2)
0
Sampling on rising clock edge (normal)
1
Sampling on falling clock edge (inverted clock)
bit9
CCO
Continuous Clock Output (Mode 2)
0
Continuous Clock Output disabled
1
Continuous Clock Output enabled
bit10
Serial Input / Output Pin Access
SIOP
write (if SOPE = 1)
read
0
SOT is forced to "0"
1
SOT is forced to "1"
reading the actual value of
SIN
bit11
SOPE
Enable Serial Output pin direct Access
0
Serial Output pin direct access disable
1
Serial Output pin direct access enable
bit12
bit 13
LBL0
LBL1
0
0
LIN break length 13 bit times
LIN break length
1
0
LIN break length 14 bit times
0
1
LIN break length 15 bit times
1
1
LIN break length 16 bit times
bit14
LIN break detected
LBD
write
read *
0
Clear LIN break
detected flag
No LIN break detected
1
ignored
LIN break detected
bit15
LBIE
R/W
LIN break detection Interrupt request enable
:
Readable and writable
0
LIN break interrupt request disable
:
Initial value
1
LIN break interrupt request enable
* see table 28.4-6 for RMW access!
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Table 28.4-6 Function of each bit of the Extended Status/Control Register (ESCR) (1 / 2)
Bit name
364
Function
bit15
LBIE: LIN break
detection interrupt
request enable bit
This bit enables a reception interrupt request, if a LIN break was
detected.
An interrupt occurs, when this bit is "1" (interrupt enabled) and the
LIN break field detected flag bit (bit 14: LBD) of the register is set to
"1".
When mode 1 or 2 is selected, this bit is set to "0", ignoring any
writing.
bit14
LBD: LIN break
detected flag
This flag goes 1 if a LIN break was detected. Writing a 0 to it clears
this flag and the corresponding interrupt request, if it is enabled.
Note: RMW instructions always return "1". In this case, the value "1"
does not indicate a LIN-Break. LIN break field detection is performed
even when reception is disabled (SCR4:RXE=0).
bit13
bit12
LBL1/0: LIN break
length selection
These bits set the generation time of the LIN break field to be
transmitted. The unit used is serial bits.
The LIN break field is always detected at an 11-bit length.
LBL1
LBL0
LIN Break Field Length selection Bit
0
0
13 bits
0
1
14 bits
1
0
15 bits
1
1
16 bits
bit11
SOPE: Serial Output
pin direct access
enable*
Setting this bit to 1 enables the direct write to the SOT pin, if SOE = 1
(SMR).*
Note:
When SCR:TXE is set to "1" and transmission is in progress or slave
mode in mode 2 is selected, direct access to the SOT pin cannot be
made, regardless of the setting of this bit.
See Table 28.4-6 for its specifications along with the SIOP bit (bit 10)
of the register.
bit10
SIOP: Serial Input/
Output Pin direct
access*
Normal read instructions always return the actual value of the SIN
pin. Writing to it sets the bit value to the SOT pin, if SOPE = 1. During
a Read-Modify-Write instruction the bit returns the SOT value in the
read cycle.*
Note:
When a read-modify-write (RMW) instruction is used, the fixed output
value from SOT which is written to the register is read.
This prevents the output value from the SOT4 pin from being
changed unintentionally by an instruction such as bit operation
instruction.
See Table 28.4-6 for its specifications along with the SIOP bit (bit 10)
of the register.
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28.4
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Table 28.4-6 Function of each bit of the Extended Status/Control Register (ESCR) (2 / 2)
Bit name
Function
bit9
CCO: Continuos
Clock Output enable
bit
This bit enables the serial clock to be always output from the SCK pin
during synchronous communication.
When this bit is set to "0", the serial clock is not output continuously.
Instead, it is only output during communication.
When this bit is set to "1", the serial clock is output continuously even
during a non- communication period.
Notes:
Set the SCK pin to the output of clock (SMR:SCKE=1).
When setting this bit to "1", set the start/stop bits to be added
(ECCR4:SSM=1). As clock is always output, normal communication
cannot be performed without the start/stop bits.
Set this bit to "0", when mode 0, 1, 3, or slave mode in mode 2 is
selected.
bit8
SCES: Serial clock
edge selection bit
If this bit is set to "1" when slave mode in mode 2 is selected
(ECCR4:MS=1), the sampling edge is switched from the rising edge
to the falling edge.
When master mode in mode 2 is selected (ECCR4:MS=0) and the
SCK pin is set to the output of clock, the internal serial clock and the
output clock signal are reversed.
When mode 0, 1 or 3 is selected, this bit is set to "0", ignoring any
writing.
* see table 28.4-7 for SOPE and SIOP interaction
Table 28.4-7 Description of the interaction of SOPE and SIOP:
SOPE setting
value
Output to SOT4 pin
0
no
SIOP Access type
When write
Read SIN pin
state
Read/write at normal
1
yes
0
no
1
yes
When read
Normal write
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value
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Chapter 28 LIN-USART
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MB91460N series
28.4.6 Extended Communication Control Register (ECCR)
The extended communication control register provides bus idle recognition, interrupt settings, synchronous
clock settings, and the LIN break generation.
Figure 28.4-6 Configuration of the Extended Communication Control Register (ECCR)
7
6
5
4
3
2
1
0
R/W W R/W R/W R/W R/W R
R
Initial value
0 0 0 0 0 0 X XB
bit0
TBI *
Transmission bus idle
0
Transmission is ongoing
1
no transmission activity
bit1
RBI *
Reception bus idle
0
Reception is ongoing
1
no reception activity
bit2
BIE *
Bus idle interrupt request enable
0
disable Bus idle interrupt request
1
enable Bus idle interrupt request
bit3
SSM
Synchronous start/stop bits in mode 2
0
No start/stop bits in synchronous mode 2
1
Enable start/stop bits in synchronous mode 2
bit4
SCDE
Serial Clock Delay enable in mode 2
0
disable clock delay
1
enable clock delay
bit5
MS
Master / Slave function in mode 2
0
Master mode (generating serial clock)
1
Slave mode (receiving external serial clock)
bit6
Set LIN break
LBR
write
read
0
ignored
1
Generate LIN break
always read 0
bit7
INV
R/W
Readable and writable
0
Serial data is not inverted (NRZ format)
R
:
Flag is read only
1
Serial data is inverted (RZ format)
W
:
Flag is write only
X
366
Invert Serial Data
:
:
Indeterminate
:
Initial value
* not useable in mode 2
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28.4
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Table 28.4-8 Function of each bit of the Extended Communication Control Register (ECCR) (1 / 2)
Bit name
Function
bit7
INV: Invert serial
data
When this bit is set to "1", the serial data output from the SOT pin
is reversed.
Also, it treats the serial data input from the SIN pin as being
reversed.
It does not affect the SCK4 pin.
bit6
LBR: Set LIN break
bit
Writing a 1 to this bit generates a LIN break of the length selected
by the LBL0/1 bits of the ESCR, if operation mode 0 or 3 is
selected.
When mode 0 is selected, set this bit to "0".
Reading from this bit always returns "0".
bit5
MS: Master/Slave
mode selection bit
This bit allows either master or slave mode to be selected in mode
2.
• When this bit is set to "0", master mode is selected to generate
synchronous clock.
• When this bit is set to "1", slave mode is selected to operate with
the external serial clock.
When mode 0, 1 or 3 is selected, this bit is set to "0", ignoring any
writing.
When changing this bit, do it while transmission is disabled
(SCR:TXE=0).
Note:
When slave mode is selected, it is necessary to set the clock
source to the external clock and enable the input of the external
clock (SMR:SCKE=0,EXT=1,OTO=1).
bit4
SCDE: Serial clock
delay enable bit
When the SCDE bit is set to "1" during the master mode operation in
mode 2, the delayed serial clock, as shown in Figure 28.7-2/Figure
28.7-3, is output. This bit is valid to the SPI operation.
When mode 0, 1 or 3 is selected, this bit is set to "0", ignoring any
writing.
Note:
In slave mode, set this bit to "0" for use.
bit3
SSM: Start/Stop bit
mode enable
When this bit is set to "1" in mode 2, the start/stop bits are added
to the synchronous data format.
• When this bit is set to "0", the start/stop bits are not added.
• When this bit is set to "1", the start/stop bits are added during
transmission, and the start bit is detected during reception to start
the reception. The stop bit is used to detect a framing error.
When mode 0, 1 or 3 is selected, this bit is set to "0", ignoring any
writing.
bit2
BIE: Bus idle
interrupt request
enable
This bit enables/disables bus idle interrupts.
A bus idle interrupt occurs, if this bit is set to "1" when the
reception/transmission bus idle flags (bit 1/0) of the register are
both set to "1".
Note:
Do not set this bit to "1" in mode 2.
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Table 28.4-8 Function of each bit of the Extended Communication Control Register (ECCR) (2 / 2)
Bit name
Function
bit1
RBI: Reception bus
idle flag
This flag is "1" if there is no reception activity on the SIN pin.
Note: Do not use this flag in mode 2 when MS = 1.
bit0
TBI: Transmission
bus idle flag
This flag is "1" if there is no transmission activity on the SOT pin.
Note: Do not use this flag in mode 2 when MS = 1.
(Note)The RBI and TBI flags can be cleared through an interrupt. Then the interrupt request is cleared, while the
interrupt service routine is active.
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28.4
MB91460N series
28.4.7 Baud Rate / Reload Counter Registers 0 and 1 (BGR0 / BGR1)
The baud rate / reload counter registers set the division ratio for the serial clock. Also the actual count of the
transmission reload counter can be read.
Figure 28.4-7 Baud Rate/Reload Counter Registers 0 and 1 (BGR0 / BGR1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
00000000B
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit 0 to bit 7
BGR0
Baud rate Generator Register 1
write
Write bit 0 to bit7 of reload value to counter
read
Read bit 0 to bit7 of actual count
bit 8 to bit 5
BGR1
R/W
:
Baud rate Generator Register 0
write
Write bit 8 to bit 15 of reload value to counter
read
Read bit 8 to bit 15 of actual count
Readable and writable
The Baud Rate / Reload Counter Registers determine the division ratio for the serial clock.
Both registers can be read or written via byte or word access.
(Note)
There are two independent reload counters available. One for transmission serial clock, the other
one for reception serial clock.
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MB91460N series
28.5 LIN-USART Interrupts
The LIN-USART uses both reception and transmission interrupts. An interrupt request can be generated for
either of the following causes:
• Receive data is set in the Reception Data Register (RDR), or a reception error occurs.
• Transmission data is transferred from the Transmission Data Register (TDR) to the transmission shift
register.
• A LIN break is detected
• No bus activity (neither reception nor transmission)
■ LIN-USART Interrupts
Table 28.5-1 Interrupt control bits and interrupt causes of LIN-USART
Reception/
transmission/
ICU
Interrupt
request
flag
Flag
Register
RDRF
Operation
mode
Interrupt
cause
0
1
2
3
SSR
x
x
x
x
receive data is
written to RDR
ORE
SSR
x
x
x
x
Overrun error
FRE
SSR
x
x
*
x
Framing error
PE
SSR
x
LBD
ESCR
x
TBI &
RBI
ESCR
x
x
Transmission
TDRE
SSR
x
x
Input
Capture Unit
ICP
ICS
ICP
ICS
Reception
x
*
370
*
Interrupt
cause
enable bit
SSR : RIE
How to clear
the Interrupt
Request
Receive data
is read
"1" is written to
clear rec. error
bit (SCR: CRE)
Parity error
x
LIN synch break
detected
ESCR :
LBIE
"0" is written to
ESCR : LBD
x
no bus activity
ESCR :
BIE
Receive data /
Send data
x
Empty transmission
register
SSR : TIE
Transfer data is
written
x
x
1st falling edge of
LIN synch field
ICS : ICE
disable ICE
temporary
x
x
5th falling edge of
LIN synch field
ICS : ICE
disable ICE
x
: Used
: Only available if ECCR/SSM = 1
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28.5
MB91460N series
■ Reception Interrupt
If one of the following events occur in reception mode, the corresponding flag of the Serial Status Register
(SSR) is set to "1":
• - Data reception is complete, i. e. the received data was transferred from the serial input shift register to the
Reception Data Register (RDR) and data can be read: RDRF
• - Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU: ORE
• - Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE
• - Parity error, i. e. a wrong parity bit was detected: PE
If at least one of these flags above go "1" and the reception interrupt request is enabled
(SSR: RIE = 1), a reception interrupt request is generated.
If the Reception Data Register (RDR) is read, the RDRF flag is automatically cleared to "0". Note that this is
the only way to reset the RDRF flag. The error flags are cleared to "0", if a "1" is written to the Clear Reception
Error (CRE) flag bit of the Serial Control Register (SCR). The RDR04 contains only valid data if the RDRF flag
is "1" and no error bits are set.
Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one CPU clock
cycle.
■ Transmission Interrupt
If transmission data is transferred from the Transmission Data Register (TDR) to the transfer shift register (this
happens, if the shift register is empty and transmission data exists), the Transmission Data Register Empty
flag (TDRE) of the Serial Status Register (SSR) is set to "1". In this case an interrupt request is generated, if
the Transmission Interrupt request Enable bit (TIE) of the SSR was set to "1" before.
Note, that the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately then, if the TIE bit is set to "1". Also note, that the only way to reset the TDRE flag is writing data
to the Transmission Data Register (TDR).
■ LIN Synchronization Break Interrupt
This paragraph is only relevant, if LIN-USART operates in mode 0 or 3 as a LIN slave.
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag of
the Extended Status/Control Register (ESCR) is set to "1". Note, that in this case after 9 bit times the reception
error flags are set to "1", therefore the RIE flag has to be set to "0" or the RXE flag has to be set to "0", if only
a LIN synch break detect is desired. In the other case a reception error interrupt would be generated first, and
the interrupt handler routine has then to wait for LBD = 1.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This makes sure, that the CPU
has detected the LIN synch break, because of the following procedure of adjusting the serial clock to the LIN
master.
■ LIN Synchronization Field Edge Detection Interrupts
This paragraph is only relevant, if LIN-USART operates in mode 0 or 3 as a LIN slave. After a LIN break
detection the next falling edge of the reception bus is indicated by LIN-USART. Simultaneously an internal
signal connected to the ICU is set to "1". This signal is reset to "0" after the fifth falling edge of the LIN
Synchronization Field. In both cases the ICU generates an interrupt request, if "both edge detection" and the
ICU interrupt request are enabled. The difference of the ICU counter values is the serial clock multiplied by 8.
Dividing it by 8 results in the new detected and calculated baud rate for the dedicated reload counter. This
value - 1 has then to be written to the Baud Rate Generator Registers (BGR1/0). There is no need to restart
LIN-USART after the dedicated baud rate generator register is updated because the reload counter is
automatically reset if a falling edge of a start bit is detected.
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■ Bus Idle Interrupt
If there is no reception activity on the SIN pin, the RBI flag of the ECCR goes "1". The TBI flag respectively
goes "1", when no data is transmitted. If the Bus Idle Interrupt request Enable bit (BIE) of the ECCR is set and
both bus idle flags (TBI and RBI) are "1", an interrupt request is generated.
(Note)
The TBI flag goes also "0" if there is no bus activity, but a "0" is written to the SIOP bit, if SOPE is
"1".
(Note)
TBI and RBI cannot be used in mode 2 (synchronous communication).
Figure 28.5-1 illustrates how the bus idle interrupt is generated
Figure 28.5-1 Bus idle interrupt generation
Transmission
data
Reception
data
TBI
RBI
Reception IRQ
: Start bit
372
: Stop bit
: Data bit
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28.5.1 Reception Interrupt Request Generation and Flag Set Timing
The following are the reception interrupt causes: Completion of reception (SSR: RDRF) and occurrence of a
reception error (SSR: PE, ORE, or FRE).
■ Reception Interrupt Request Generation and Flag Set Timing
A reception interrupt request is generated, if the received data is complete (RDRF = 1) and the Reception
Interrupt request Enable bit (RIE) of the Serial Status Register (SSR) was set to "1". This interrupt is
generated if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2
(if SSM = 0).
(Note)
If a reception error has occurred, the Reception Data Register (RDR) contains invalid data in each
mode.
Figure 28.5-2 Reception operation and flag set timing
Receive data
(mode 0/3)
ST
D0
D1
D2
....
D5
D6
D7/P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
....
D6
D7
A/D
SP
ST
D2
....
D5
D6
D7
D0
Receive data
(mode 2)
D0
D1
D4
PE*, FRE
RDRF
ORE**
(if RDRF = 1)
* The PE flag will always remain "0" in mode 1 or 3
reception interrupt occurs
* An overrun error only occurs, if next data is transferred before the reception data is read.
ST: Start Bit
SP: Stop Bit
A/D: Mode 1 (multi processor) address/data selection bit
(Note)
The example in figure 28.5-2 does not show all possible reception options for mode 0 and 3. Here it
is: "7p1" and "8N1" (p = E [even] or O [odd]), all in NRZ data format (ECCR: INV = 0).
(Note)
**ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame
is read.
Figure 28.5-3 ORE set timing
Receive
data
RDRF
ORE
* An overrun error only occurs, if next data is transferred before the reception data is read.
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28.5.2 Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the transmission data is transferred to the transmission data
register (TDR) and the register becomes empty.
■ Transmission Interrupt Generation and Flag Set Timing
When data written to the transmission data register (TDR) is transferred to the transmission shift register and
the transmission starts, data becomes empty(SSR:TDRE=1). In this case, when the transmission interrupt is
enabled(SSR:TIE=1), the transmission interrupt occurs. Because the TDRE flag is "read only", it only can be
cleared by writing data into TDR.
The following figure demonstrates the transmission operation and flag set timing for the four modes of LINUSART.
Figure 28.5-4 Transmission operation and flag set timing
transmission interrupt occurs
transmission interrupt occurs
Mode 0, 1 or 3:
write to TDR
TDRE
serial output
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A/D
A/D
transmission interrupt occurs
transmission interrupt occurs
Mode 2 (SSM = 0):
write to TDR
TDRE
serial output
ST: Start bit
(Note)
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits
P: Parity
SP: Stop bit
A/D: Address/data selection bit (mode1)
The example in figure 28.5-4 does not show all possible transmission options for mode 0. Here it is:
"8p1" (p = E [even] or O [odd]), ECCR: INV = 0. Parity is not provided in mode 3 or 2, if SSM = 0.
■ Transmission Interrupt Request Generation Timing
If the TDRE flag is set to 1 when a transmission interrupt request is enabled (SSR: TIE=1) a transmission
interrupt request is generated.
A transmission completion interrupt request is generated immediately after the transmission interrupt request
is enabled (TIE=1) because the TDRE flag is set to 1 as its initial value. TDRE is a read-only flag that can be
cleared only by writing new data to the output data register (TDR). Carefully specify the transmission interrupt
enable timing.
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28.6 LIN-USART Baud Rates
One of the following can be selected for the LIN-USART serial clock source:
• Dedicated baud rate generator (Reload Counter)
• External clock as it is (clock input to the SCK pin)
• External clock connected to the baud rate generator (Reload Counter)
■ LIN-USART Baud Rate Selection
The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can
be selected:
• Baud Rates Determined Using the Dedicated Baud Rate Generator (Reload Counter)
LIN-USART has two independent internal reload counters for transmission and reception serial clock. The baud rate
can be selected via the 16-bit reload value determined by the Baud Rate Generator Register 0 and 1 (BGR0/BGR1).
The reload counter divides the peripheral clock by the value set in the Baud Rate Generator Register 0 and 1.
• Baud Rates determined using external clock (one-to-one mode)
The clock input from LIN-USART clock pulse input pins (SCK) is used as it is (synchronous). Any baud rate less than
the peripheral clock divided by 4 and is divisible can be set externally
It is used in synchronous mode (slave).
External clock and direct use of external clock are selected for the setting of clock source (SMR: EXT=1, OTO=1).
• Baud Rates determined using the dedicated baud rate generator with external clock
An external clock source can also be connected internally to the reload counter. In this mode it is used instead of the
internal peripheral clock. This was designed to use quartz oscillators with special frequencies and having the possibility
to divide them.
It is used in asynchronous mode.
External clock and baud rate generator clock are selected for the setting of the clock source (SMR: EXT=1, OTO=0).
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Figure 28.6-1 Baud rate selection circuit (reload counter)
REST
Start bit falling
edge detected
Reload Value: v
Rxc = 0?
Reception
16-bit Reload Counter
set
FF
Reload
Rxc = v/2?
0
Reception
Clock
reset
1
Reload Value: v
CLKP
0
SCK
EXT
Txc = 0?
Transmission
16-bit Reload Counter
Count Value: Txc
Txc = v/2?
OTO
FF
Reload
1
(external
clock
input)
set
0
reset
1
Transmission
Clock
Internal data bus
EXT
REST
OTO
376
SMR
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR9
BGR8
BGR1
register
BGR7
BGR6
BGR5
BGR4
BGR3
BGR2
BGR1
BGR0
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BGR0
register
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28.6.1 Setting the Baud Rate
This section describes how the baud rates are set and the resulting serial clock frequency is calculated.
■ Calculating the baud rate
The both 15-bit Reload Counters are programmed by the Baud Rate Generator Registers 1 and 0 (BGR1/
BGR0). The following calculation formula should be used to set the wanted baud rate:
Reload Value:
v = [F / b] - 1 ,
where F is the resource clock (CLKP), b the baud rate and [ ] gaussian brackets (mathematical rounding
function).
■ Example of Calculation
If the CPU clock is 16MHz and the desired baud rate is 19200 baud then the reload value v is:
v = [16*106 / 19200] - 1 = 832
The exact baud rate can then be recalculated: bexact = F / (v + 1), here it is: 16*106 / 833 = 19207.6831
(Notes)
• Setting the reload value to 0 stops the reload counter.
• The minimum recommended division ratio is 4 (i.e. reload value is 3) due to RX oversampling filter
in asynchronous communication modes (mode 0,1 and 3).
■ Suggested Division Ratios for different machine speeds and baud rates
The following settings are suggested for different MCU clock speeds and baud rates:
Table 28.6-1 Suggested Baud Rates and reload values at different machine speeds (1 / 2)
8MHz
Baud
rate
10MHz
16MHz
Setting
value
Error
(%)
Setting
value
Error
(%)
2M
3
0
4
0
7
1M
7
0
9
0
500000
15
0
19
460800
-
-
250000
31
230400
20MHz
32MHz
Setting
value
Error
(%)
Setting
value
Error
(%)
Setting
value
Error
(%)
0
9
0
11
0
15
0
15
0
19
0
23
0
31
0
0
31
0
39
0
47
0
63
0
-
-
-
-
-
-
51
-0.16
-
-
0
39
0
63
0
79
0
95
0
127
0
-
-
-
-
-
-
86
0.22
103
-0.16
138
-0.08
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
207
0.16
125000
63
0
79
0
127
0
159
0
191
0
255
0
115200
-
-
86
0.22
138
0.08
173
0.22
207
-0.16
278
-0.08
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
173
0.22
277
0.08
346
-0.06
416
0.08
555
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
3071
<0.01
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Setting Error
value
(%)
24MHz
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Table 28.6-1 Suggested Baud Rates and reload values at different machine speeds (2 / 2)
8MHz
Baud
rate
10MHz
16MHz
Setting
value
Error
(%)
Setting
value
Error
(%)
9600
832
0.04
1041
0.03
1666
7200
1110
<0.01
1388
<0.01
4800
1666
0.02
2082
2400
3332
<0.01
1200
6666
600
300
20MHz
Setting Error
value
(%)
24MHz
32MHz
Setting
value
Error
(%)
Setting
value
Error
(%)
Setting
value
Error
(%)
0.02
2083
0.03
2499
0
3332
0.01
2221
<0.01
2777
<0.01
3332
<0.01
4443
-0.01
-0.02
3332
<0.01
4166
<0.01
4999
0
6666
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
13332
<0.01
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
26666
<0.01
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
26666
<0.01
-
-
-
-
-
-
-
-
The unit of frequency deviation (dev.) is %.
<Note>
The maximum baud rate for synchronous mode is 1/6 of the LIN-USART operation clock (value=5).
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■ Counting Example
Assume the reload value is 832. The figure 28.6-2 demonstrates the behavior of the both Reload Counters:
Figure 28.6-2 Counting example of the reload counters
Transmission/
Reception Clock
Reload
Count
001
000
832
831
830
829
828
827
413
412
411
410
reload count value
Transmission/
Reception Clock
Reload
Count
(Note)
417
416
415
414
The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |.
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28.6.2 Restarting the Reload Counter
This section describes reload counter.
■ Function of Reload Counter
The reload counter has the transmission and reception reload counters and functions as dedicated baud rate
generator. It consists of a 15-bit register for the reload value and generates the transmission/reception clocks
by the external or internal clock. Also, the count value of the transmission reload counter can be read by the
baud rate generator register (BGR1, BGR0).
● Count start
When the reload value other than "0" is written to the baud rate generator register (BGR1, BGR0), the reload
counter starts counting.
● Restart
The Reload Counter can be restarted because of the following reasons:
Transmission and Reception Reload Counter:
• Global MCU Reset
• LIN-USART programmable clear (SMR:UPCL bit)
• User programmable restart (SMR: REST bit)
Reception Reload Counter:
• Start bit falling edge detection in asynchronous mode
■ Programmable Restart
If the REST bit of the Serial Mode Register (SMR) is set by the user, both Reload Counters are restarted at
the next clock cycle. This feature is intended to use the Transmission Reload Counter as a small timer.
The following figure illustrates a possible usage of this feature (assume that the reload value is 100.)
Figure 28.6-3 Reload Counter Restart example
MCU
Clock
Reload
Counter
Clock
Outputs
REST
Reload
Value
37
36
35
100
99
98
97
96
95
94
93
92
91
90
89
88
87
Read
BGR0/1
Data
Bus
90
: don’t care
In this example the number of MCU clock cycles (cyc) after REST is then:
cyc = v - c + 1 = 100 - 90 + 1 = 11,
where v is the reload value and c is the read counter value.
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(Note)
If LIN-USART is reset by setting SMR:UPCL, the Reload Counters will restart too.
(Note)
Do not restart the reload counter during transmission/reception.
■ Automatic Restart
In asynchronous UART mode if a falling edge of a start bit is detected the Reception Reload Counter is
restarted. This is intended to synchronize the serial input shifter to the incoming serial data stream.
● Clearing reload counters
When a reset occurs, the reload values in the baud rate generator registers (BRG14, BGR04) and the reload
counter are cleared to "00H".
Although the counter value is temporarily cleared to "00H" by the programmable reset (writing "1" to
SMR:UPCL), the reload counter restarts since the reload value is retained.
The counter value is not cleared to "00H" by the restart setting (writing "1" to SMR:REST), and the reload
counter restarts.
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28.7 LIN-USART Operation
LIN-USART operates in operation mode 0 for normal bidirectional serial communication, in mode
2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in
multiprocessor communication.
■ Operation of LIN-USART
• Operation modes
There are four LIN-USART operation modes: modes 0 to 3. As listed in table 28.7-1, an operation mode can
be selected according to the inter-CPU connection method and data transfer mode.
Table 28.7-1 LIN-USART operation mode
Operation
mode
0
normal mode
1
multiprocessor
2
normal mode
3
LIN mode
Data length
parity
disabled
parity
enabled
7 or 8
7 or 8 + 1**
8
8
-
Synchronization of mode
Length
of
stop bit
data bit
directio
n*
asynchronous
1 or 2
L/M
asynchronous
1 or 2
L/M
synchronous
0, 1 or 2
L/M
asynchronous
1
L
* means the data bit transfer format: LSB or MSB first
** "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.
(Note)
Mode 1 operation is supported both for master or slave operation of LIN-USART in a master-slave
connection system. In Mode 3 the LIN-USART function is locked to 8N1-Format, LSB first.
If the mode is changed, LIN-USART cuts off all possible transmission or reception and awaits then new action.
■ Inter-CPU Connection Method
External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can
be selected. For either connection method, the data length, whether to enable parity, and the synchronization
method must be common to all CPUs. Select an operation mode as follows:
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select
operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode.
Note, that one CPU has to set to the master and one to the slave in synchronous mode 2.
• Select operation mode 1 for the master-slave connection method and use it either for the master or slave
system.
■ Synchronization Methods
In asynchronous operation LIN-USART reception clock is automatically synchronized to the falling edge of a
received start bit.
In synchronous mode the synchronization is performed either by the clock signal of the master device or by
LIN-USART itself if operating as master.
■ Signal Mode
LIN-USART can treat data in non-return to zero (NRZ) and return to zero (RZ) format. For this option the
ECCR: INV bit is provided.
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■ Operation Enable Bit
LIN-USART controls both transmission and reception using the operation enable bit for transmission (SCR:
TXE) and reception (SCR: RXE). If each of the operations is disabled, stop it as follows:
• If reception operation is disabled during reception (data is input to the reception shift register), finish frame
reception and read the received data of the reception data register (RDR). Then stop the reception
operation.
• If the transmission operation is disabled during transmission (data is output from the transmission shift
register), wait until there is no data in the transmission data register (TDR) before stopping the transmission
operation.
28.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1)
When LIN-USART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode),
the asynchronous transfer mode is selected.
■ Transfer data format
Each data transfer in the asynchronous mode operation begins with the start bit (low-level on bus) and ends
with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is determined by
the BDS-Bit of the Serial Status Register (SSR). The parity bit (if enabled) is always placed between the last
data bit and the (first) stop bit.
In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop bits.
In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection bit
instead of a parity bit. 1 or 2 stop bits can be selected.
The calculation formula for the bit length of a transfer frame is:
Length = 1 + d + p + s
(d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2]
Figure 28.7-1 Transfer data format (operation modes 0 and 1)
*
**
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
SP SP
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7 A/D
SP
* D7 (bit 7) if parity is not provided and data length is 8 bits
P (parity) if parity is provided and data length is 7 bits
** only if SBL-Bit of SCR is set to 1
ST: Start Bit
(Note)
SP: Stop Bit
A/D: Address/data selection bit in mode 1 (multiprocessor mode)
If BDS-Bit of the Serial Status Register (SSR) is set to "1" (MSB first), the bit stream processes as:
D7, D6, ... , D1, D0, (P).
During Reception both stop bits are detected, if selected. But the Reception data register full (RDRF) flag will
go "1" at the first stop bit. The bus idle flag (RBI of ECCR) goes "1" after the second stop bit if no further start
bit is detected. (The second stop bit belongs to "bus activity", although it is just mark level.)
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■ Transmission Operation
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1",
transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, the
TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control Register
(SCR), the data is written next to the transmission shift register and the transmission starts at the next clock
cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes "1", so that new data can be
written to the TDR04.
If transmission interrupt request is enabled (TIE = 1), the interrupt request is generated by the TDRE flag.
Note, that the initial value of the TDRE flag is "1", so that in this case if TIE is set to "1", an interrupt request
will occur immediately. When the data length is set to 7 bits (CL=0), the unused bit of the TDR4 is always the
MSB, independently from the transfer direction selection bit (BDS) setting (LSB first or MSB first).
■ Reception Operation
Reception operation is performed every time it is enabled by the Reception Enable (RXE) flag of the SCR. If a
start bit is detected, a data frame is received according to the format specified by the SCR. By occurring
errors, the corresponding error flags are set (PE, ORE, FRE). However after the reception of the data frame,
the data is transferred from the serial shift register to the Reception Data Register (RDR) and the Receive
Data Register Full (RDRF) flag of the SSR is set. The data then has to be read by the CPU. By doing so, the
RDRF flag is cleared. If reception interrupt request is enabled (RIE = 1), the interrupt request is simply
generated by the RDRF. When reading data after reception of one frame data, check the error flag state and
read reception data from the Reception Data Register (RDR4) if the reception is performed normally.
If the reception error occurs, perform error processing.
If the data length is set to 7 bits (CL=0), MSB of RDR4 is set to "0", regardless of the setting of the transfer
direction selection bit (BDS) (i.e. LSB first or MSB first).
Note: Only when the RDRF flag is set and no errors have occurred the Reception Data Register (RDR)
contains valid data.
● Used clock
Use the internal clock or external clock (SMR4:EXT="1" or "0").
Select the baud rate generator (SMR4:OTO="0") for desired baud rate.
● Stop bit
1- or 2-stop bit can be selected at the transmission.
When the first stop bit is detected, the reception is judged as complete. If no start bit is detected after that,
the reception bus idle flag (ECCR:RBI) is set to "1", indicating that there is no reception operation.
● Error detection
In mode 0, the parity, overrun, and framing errors can be detected.
In mode 1, the overrun and framing errors can be detected, and the parity error cannot be detected.
● Parity
Parity can set to add (transmission) or detect (reception) the parity bit.
The parity enable bit (SCR: PEN) is used to specify whether there is parity or not, and parity selection bit
(SCR: P) is selected the even/odd parity.
In operation mode 1, the parity cannot be used.
Figure 28.7-2 shows the Configuration of the Transmission Data When Parity Enabled.
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Figure 28.7-2 Transmission Data When Parity Enabled (Operation mode 0)
SIN
ST
SP
1
SOT
1
1
0
0
0
0
0
ST
1
SOT
0
0
1
1
0
0
0
0
0
1
1
0
Data
0
0
SP
Even parity transmitting
(SCR:P=0)
SP
Odd parity transmitting
(SCR:P=1)
1
ST
1
Parity error generating
at received even parity
(SCR:P=0)
0
0
Parity
ST: Start bit, SP: Stop bit at parity ON (PEN=1)
Note: Parity cannot be used at operation mode 1.
● Data signal type
The data signal type is NRZ data format.
● Data transition method
The data bit transfer method can be selected by LSB first or MSB first.
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28.7.2 Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for LIN-USART operation mode 2 (normal mode).
■ Transfer data format (standard synchronous)
In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended
Communication Control Register (ECCR) is 0. A special clock signal belongs to the data format in mode 2.
The figure below illustrates the data format during a transmission in the synchronous operation mode
Figure 28.7-3 Transfer data format (operation mode 2)
Transmission data
writing
Reception data sample edge (SCES = 0)
Transmitting or
receiving clock
(normal)
Mark level
Mark level
Transmitting
clock (SCDE = 1)
Transmission and
reception data
Mark level
0
1
1
0
LSB
1
0
0
1
MSB
Data
■ Transfer data format
In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended
Communication Control Register (ECCR) is 0. A special clock signal belongs to the data format in mode 2.
The figure below illustrates the data format during a transmission in the synchronous operation mode.
Figure 28.7-4 SPI Transfer data format (operation mode 2)
Transmission data
writing
Reception data sample edge (SCES = 0)
Transmitting or
receiving clock
(normal)
Mark level
Mark level
Transmitting
clock (SCDE = 1)
Transmission and
reception data
Mark level
0
1
1
LSB
0
1
Data
0
0
1
MSB
■ Clock inversion and start/stop bits in mode 2
If the SCES bit of the Extended Status/Control Register (ESCR) is set the serial clock is inverted. Therefore in
slave mode LIN-USART samples the data bits at the falling edge of the received serial clock. Note, that in
master mode if SCES is set to "1", the clock signal’s mark level is "0".
● Start/stop bits
If the SSM04 bit of the Extended Communication Control Register (ECCR) is set the data format gets
additional start and stop bits like in asynchronous mode.
386
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Figure 28.7-5 Transfer data format with clock inversion
mark level
reception or transmission clock
(SCES = 0, CCO = 0):
reception or transmission clock
(SCES = 1, CCO = 0):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
mark level
ST
SP
data frame
■ Clock Supply
In clock synchronous (normal) mode (I/O extended serial), the number of the transmission and reception bits
has to be equal to the number of clock cycles. Note, that if start/stop bits communication is enabled, the
number of clock cycles has to match with the quantity for the additional start and stop bit(s).
If the internal clock (dedicated reload counter) is selected, the data receiving synchronous clock is generated
automatically if data is transmitted.
If external clock is selected, be sure, that the transmission side of the Transmission Data Register contains
data and then clock cycles for each bit to sent have to be generated and supplied from outside. The mark level
("H") must be retained before transmission starts and after it is complete if SCES is "0".
Setting the SCDE bit of ECCR delays the transmitting clock signal by 1 CLKP cycle (or half a clock period in
SPI). This will make sure, that the transmission data is valid and stable at any falling clock edge. (Necessary, if
the receiving device samples the data at falling clock edge). This function is disabled when CCO is enabled.
If the Serial Clock Edge Select (SCES) bit of the ESCR is set, the LIN-USARTs clock is inverted and thus
samples the reception data at the falling clock edge. In this case, the sending device must make sure that the
serial data is valid at the falling serial clock edge.
When both the SCES and the SCDE bit are set, data is stable at the rising clock edge, as in the case of SCES
= SCDE = 0. However, the marker value for idle state is inverted (low).
If the CCO bit of the Extended Status/Control Register (ESCR) is set, the serial clock on the SCK pin in master
mode is continuously clocked out. It is strongly recommended to use start and stop bits in this mode to
signalize the receiver, when a data frame begins and when it stops. Figure 28.7-6 illustrates this.
Figure 28.7-6 Continuous clock output in mode 2
reception or transmission clock
(SCES = 0, CCO = 1):
reception or transmission clock
(SCES = 1, CCO = 1):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
ST
SP
data frame
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■ Data signal mode
NRZ data format is selected, if ECCR: INV = 0, otherwise the signal mode for the serial data input and output
pin is RZ.
■ Error Detection
If no Start/Stop bits are selected (ECCR: SSM = 0) only overrun errors are detected.
■ Communication
For initialization of the synchronous slave mode, the following settings have to be done:
• Baud Rate Generator Registers (BGR0/1):
Set the desired reload value for the dedicated Baud Rate Reload Counter
• Serial Control Register (SCR):
• RXE, TXE: set both of these flags to "0"
• PEN: no parity provided - Value: don’t care
• P, SBL, A/D: no parity, no stop bit(s), no Address/Data selection - Value: don’t care
• CL: automatically fixed to 8-bit data - Value: don’t care
• CRE: "1" (the error flag is cleared for initialization, possible transmission or reception will cut off)
• Serial Mode Control Register (SMR):
• MD1, MD0: "10b" (Mode 2)
• SCKE: "1" for dedicated Baud Rate Reload Counter
"0" for external clock input
• SOE:
"1" for transmission and reception
"0" for reception only
• Serial Status Register (SSR):
• BDS: "0" for LSB first, "1" for MSB first
• RIE: "1" if interrupts are used; "0" if not
• TIE: "1" if interrupts are used; "0" if not
• Extended Communication Control Register (ECCR):
• SSM: "0" if no start/stop bits are desired (normal)
"1" for adding start/stop bits (special)
• MS:
"0" for master mode (LIN-USART generates the serial clock);
"1" for slave mode (LIN-USART receives serial clock from the master device)
• Serial Control Register (SCR):
• RXE, TXE: set one or both of these control bits to "1" to begin communication.
To start the communication, write data into the Transmission Data Register (TDR).
To receive data, disable the Serial Output Enable (SOE) bit of the SMR and write dummy data to TDR.
(Note)
388
Setting continuous clock and start-/stop-bit mode, duplex transfer is possible like in asynchronous
modes.
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28.7.3 Operation with LIN Function (Operation Mode 3)
LIN-USART can be used either for LIN-Master devices or LIN-Slave devices. For this LIN function a special
mode (3) is provided. When LIN-USART is set to mode 3, the data format is set to 8-bit data, no parity, one
stop bit, and LSB first.
The transfer method is asynchronous clock.
■ LIN-USART as LIN master
In LIN master mode, the master determines the baud rate of the whole sub bus. Therefore, slave devices have
to synchronize to the master and the desired baud rate remains fixed in master operation after initialization.
Writing "1" to the LBR bit of the Extended Status/Communication Register (ECCR) generates a 13bit to 16 bit
times low-level on the SOT pin, which is the LIN synchronization break and the start of a LIN message.
Thereby the TDRE flag of the Serial Status Register (SSR) goes "0" and is reset to "1" after the break, and
generates a transmission interrupt request for the CPU (if TIE of SSR is "1").
The length of the Synchronization break to be sent can be determined by the LBL1/0 bits of the ESCR as
follows:
Table 28.7-2 LIN break length
LBL1
LBL0
Length of
Break
0
0
13 Bit times
0
1
14 Bit times
1
0
15 Bit times
1
1
16 Bit times
The Synch Field can be sent as a simple 55H-Byte after the LIN break. To prevent a transmission interrupt, the
55H can be written to the TDR just after writing the "1" to the LBR bit, although the TDRE flag is "0". The
internal transmission shifter waits until the LIN break has finished and shifts the TDR value out afterwards. In
this case no interrupt is generated after the LIN break and before the start bit.
■ LIN-USART as LIN slave
In LIN slave mode LIN-USART has to synchronize to the master’s baud rate. If Reception is disabled (RXE = 0)
but LIN break Interrupt request is enabled (LBIE = 1) LIN-USART will generate a reception interrupt request, if a
synchronization break of the LIN master is detected, and indicates it with the LBD flag of the ESCR. Writing a "0"
to this flag clears the interrupt. The next step is to analyze the baud rate of the LIN master. The first falling edge
of the Synch Field is detected by LIN-USART. The LIN-USART signals it then to the Input Capture Unit (ICU) via
a rising edge of an internal connection. The fifth falling edge resets the ICU signal. Therefore the ICU has to be
configured for the LIN input capture (PFR=1, EPFR=1) and its interrupt requests have to be enabled (ICS). The
values of the ICU counter register after the first Interrupt (a) and after the second interrupt (b) yield the BGR
value:
without timer overflow:BGR value = (b - a) / 8 ,
with timer overflow: BGR value = (max - b + a) / 8 ,
where max is the timer maximum value at which the overflow occurs.
The figure 28.7-8 shows a typical start of a LIN message frame and the behavior of the LIN-USART.
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Figure 28.7-7 LIN Synch Break Detection and Flag Set Timing
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Serial clock cycle
Serial input
(LIN bus)
FRE(RXE=1)
LBD
Note:
The data framing error flag bit (FRE) of the SSR 4 will cause a reception interrupt 2 bit times ("8N1") earlier
than the LIN break interrupt, so it is recommended to RXE=0, if a LIN Break field is expected.
LIN synch break detection is only supported in operation mode 3.
Figure 28.7-8 LIN-USART behavior as slave in LIN mode
Serial
clock
Serial
Input
(LIN bus)
LBR cleared
by CPU
LBD
Internal
ICU
Signal
390
Synch break (e. g. 14T bit)
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■ LIN bus timing
Figure 28.7-9 LIN bus timing and LIN-USART signals
old serial clock
no clock used
(calibration frame)
new (calibrated) serial clock
ICU count
LIN
bus
(SIN)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal
to ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR
by CPU
Reception Interrupt enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD -> 0)
IRQ from ICU
IRQ cleared: Begin of Input Capture
IRQ from ICU
IRQ cleared: Calculate & set new baud rate
LBIE disable
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR
RDR read by CPU
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28.7.4 Direct Access to Serial Pins
LIN-USART allows the user to access directly the transmission pin (SOT) or the reception pin (SIN).
■ LIN-USART Direct Pin Access
The LIN-UART provides the ability for the programmer to access directly to serial input or output pin. Software
can be used to read from the SIOP bit of ESCR to monitor reception serial data at all times. Software can also be
used to maintain the SOT pin to a required value level by setting the serial output pin direct access enable bit
(SOPE) of ESCR to "1". This access is enabled only when the transmission shift register is empty (i.e. no
transmission is being processed).
In LIN mode, this function can be used for reading back the own transmission and is used for error handling if
something is physically wrong with the single-wire LIN-bus.
<Notes>
392
•
Direct access is enabled only when the transmission is not ongoing (transmission shift register is
empty).
•
Write a value to the serial output pin direct access bit (ESCR:SIOP) before setting the SOPE bit to "1".
As the SIOP bit maintains the previous value, this step is necessary to prevent any signal at an
unexpected level from being output.
•
While the value of the SIN pin is read in normal read operation, the value of the SOT pin is read for the
SIOP bit by a read-modify-write instruction (RMW). This prevents any unexpected value from being
written to the SIOP bit during the execution of the RMW instruction.
•
When SCR4:TXE is set to "1", the direct access to the SOT pin is disabled during transmission or slave
mode in operating mode 2, regardless of the setting of this bit.
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28.7.5 Bidirectional Communication Function (Normal Mode)
In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for
asynchronous communication and operation mode 2 for synchronous communication.
■ Bidirectional Communication Function
The settings shown in figure 28.7-10 are required to operate LIN-USART in normal mode (operation mode 0 or
2).
Figure 28.7-10 Settings for LIN-USART operation mode 0 and 2
bit
SCR, SMR
15
14
13
12
11
PEN
P
SBL
CL
AD
Mode 0
10
9
8
7
6
x
0
0
0
0
1
0
1
0
Mode 2 (MS=0)
x
x
Mode 2 (MS=1)
+
x
5
4
3
2
1
0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
SSR, TDR/RDR PE ORE FRE RDRF TDRE BDS RIE
x
1
0
0
0
0
0
1
0
Set transmission data (during writing)
Retain reception data (during reading)
TIE
Mode 0
Mode 2 (MS=0)
Mode 2 (MS=1)
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
Mode 0 x
x
x
x
x
x
x
x
Mode 2
x
x
x
x
Mode 2
+
x
x
x
x
Reserved
x
LBR MS SCDE SSM
x
x
x
x
x
0
0
+
1
0
BIE
x
RBI
x
TBI
x
x
x
x
x
x
Bit is used
x Bit is not used
0 / 1 Set bit to 0 / 1
Bit is used if SSM = 1 (Synchronous start-/stop-bit mode)
+ Bit is automatically set to the correct value
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■ Inter-CPU Connection
As shown in figure 28.7-11, interconnect two CPUs in LIN-USART mode 2
Figure 28.7-11 Connection example of LIN-USART mode 2 bidirectional communication
SOT
SOT
SIN
SIN
Input
Output
SCK
CPU-1 (Master)
SCK
CPU-2 (Slave)
■ Communication procedure
Communication starts at arbitrary timing from the transmission side when the transmission data is provided.
When the transmission data is received at the reception side, ANS (per one byte in example) is returned
periodically. Figure 28.7-12 shows an example of the bi-directional communication flowchart.
Figure 28.7-12 Example of Bi-directional Communication Flowchart
(Transmission side)
(Reception side)
Start
Start
Operating mode setting
(either "0" or "2")
(match the transmission side)
Set 1 byte data to TDR1
and communicate
Operating mode setting
Data transmission
NO
NO
With reception
data
YES
With reception
data
Read reception data
and process
YES
Read reception data
and process
394
Data transmission
(ANS)
1 byte data transmission
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28.7.6 Master-Slave Communication Function (Multiprocessor Mode)
LIN-USART communication with multiple CPUs connected in master-slave mode is available for both master
or slave systems.
■ Master-slave Communication Function
The settings shown in figure 28.7-13 are required to operate LIN-USART in multiprocessor mode (operation
mode 1).
Figure 28.7-13 Settings for LIN-USART operation mode 1
bit
SCR, SMR
Mode 1
SSR,
TDR/RDR
15
14
13
12
11
PEN
P
SBL
CL
AD
x
x
10
9
0
PE ORE FRE RDRF TDRE BDS RIE
Mode 1
8
7
6
5
4
3
2
1
0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
0
1
x
0
0
0
1
Set transmission data (during writing)
Retain reception data (during reading)
TIE
x
ESCR,ECCR
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 1 +
x
x
x
x
+
Reserved
0
LBR MS SCDE SSM
x
+
+
BIE
RBI
TBI
+
Bit is used
x Bit is not used
0 / 1 Set bit to 0 / 1
Bit is used if SSM = 1 (Synchronous start-/stop-bit mode)
+ Bit is automatically set to the correct value
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■ Inter-CPU Connection
As shown in figure 28.7-14, a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. LIN-USART can be used for the master or slave CPU.
Figure 28.7-14 Connection example of LIN-USART master-slave communication
SIN
SOT
Master CPU
SIN
SOT
SIN
Slave CPU #1
SOT
Slave CPU #2
■ Function Selection
Select the operation mode and data transfer mode for master-slave communication as shown in table 28.7-3.
Table 28.7-3 Selection of the master-slave communication function
Operation mode
Master
CPU
Address
transmission and
reception
Data transmission
and reception
Mode 1
(send A/Dbit)
Data
Parity
Synchronization
method
Stop bit
Bit
direction
None
Asynchronous
1 or 2
bits
LSB
or
MSB
first
Slave CPU
Mode 1
(receive
A/D-bit)
A/D=1 +
7-bit or 8-bit
address
A/D=0 +
7-bit or 8-bit
data
■ Communication Procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to
1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using
a program. When the address data indicates the address assigned to a slave CPU, the slave CPU
communicates with the master CPU (ordinary data). Figure 28.7-15 shows a flowchart of master-slave
communication (multiprocessor mode)
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Figure 28.7-15 Master-slave communication flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set operation mode 1
Set operation mode 1
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set "1" in A/D bit
Set TXE = RXE = 1.
Set TXE = RXE = 1.
Receive Byte
Send Slave Address
Is
A/D bit = 1 ?
Set "0" in A/D bit.
NO
YES
Does
Slave Address
match?
Communicate with
slave CPU
NO
YES
Is
communication
complete?
NO
Communicate with
master CPU
NO
Is
communication
complete?
YES
Communicate
with another
slave CPU?
NO
YES
YES
Set TXE = RXE = 0.
End
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28.7.7 LIN Communication Function
LIN-USART communication with LIN devices is available for both LIN master or LIN slave systems.
■ LIN-Master-Slave Communication Function
The settings shown in the figure below are required to operate LIN-USART in LIN communication mode
(operation mode 3).
Figure 28.7-16 Settings for LIN-USART
bit
SCR, SMR
Mode 3
SSR,
TDR/RDR
15
14
13
12
11
PEN
P
SBL
CL
AD
x
x
+
+
x
10
9
ESCR, ECCR
x
7
0
1
PE ORE FRE RDRF TDRE BDS RIE
Mode 3
8
6
5
4
3
2
1
0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
1
x
0
0
0
1
Set transmission data (during writing)
Retain reception data (during reading)
TIE
+
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
Mode 3
x
x
x
-
LBR MS SCDE SSM
x
x
x
x
BIE
RBI
TBI
x
x
Bit is used
x Bit is not used
0 / 1 Set bit to 0 / 1
Bit is used if SSM = 1 (Synchronous start-/stop-bit mode)
+ Bit is automatically set to the correct value
■ LIN device connection
As shown in the Figure below, a communication system of one LIN-Master device and a LIN-Slave device.
LIN-USART can operate both as LIN-Master or LIN-Slave.
Figure 28.7-17 Connection example of a small LIN-Bus system
SOT
SOT
LIN bus
SIN
LIN-Master
398
SIN
Single-WireTransceiver
Single-WireTransceiver
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28.7.8 Sample Flowcharts for LIN-USART in LIN Communication (Operation Mode 3)
This section contains sample flowcharts for LIN-USART in LIN communication.
■ LIN-USART as master device
Figure 28.7-18 LIN-USART LIN master flow chart
Start
Initial setting:
Set operation mode 3
Serial data output enabled, Baud rate setting,
Synch break length setting
TXE = 1, TIE = 0, RXE = 1, RIE = 1
NO
Send
Message?
(Reception) YES
YES
NO
Wake up ?
(80H reception)
Data Field
reception ?
(Transmission) NO
Reception
interrupt
Transmission data 1 set:
TDR = Data 1
Transmission interrupt
enabled
Data 1 reception *1
Reception interrupt
TDRE=1
Transmission interrupt
YES
Data N reception *1
RXE = 0
Synch break interrupt enabled
Synch break transmission:
ECCR: LBR = 1
Synch field transmission:
Transmission data N set:
TDR = Data N
Transmission interrupt
disabled
RDRF=1
Transmission interrupt
LBD = 1
Synch Break interrupt
Data 1 reception *1
Data 1 reading
Reception enabled
Lin Break field detection clear
Lin Break field interrupt disable
RDRF=1
Transmission interrupt
RDRF=1
Reception interrupt
Data N reception *1
Data N reading
Lin Synch field Reception *1
PID transmission
Reception interrupt
PID Reception *1
Without
error?
NO
Error processing*2
YES
*1: If an error occurs, perform the error processing.
*2: • When FRE and ORE are "1", write "1" to SCR: CRE bit and clear the error flag.
• When ESCR: LBD bit is "1", execute UART reset.
Note: The error is detected in each processing and take appropriate measures.
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■ LIN-USART as slave device
Figure 28.7-19 LIN-USART LIN slave flow chart (part1)
Start
Initial setting:
Set operation mode 3
Serial data output enabled
TXE = 1, TIE = 0, RXE = 0, RIE = 1
Connection with UART and ICU
ICU interrupt enabled
Synch break interrupt
enabled
(reception) YES
Lin Break reception
Synch break interrupt
(transmission) NO
Data Field
reception ?
Reception
interrupt
Transmission data 1 set
TDR = Data 1
Transmission interrupt
enabled
Data 1 reception*1
Synch break field detection clear
Synch break field interrupt
prohibited
RDRF=1
Reception interrupt
Lin Synch Byte reception
ICU interrupt
Transmission interrupt
Transmission data N set
TDR = Data N
Transmission interrupt
disabled
Data N reception*1
ICU data read
ICU interrupt flag clear
Reception interrupt
Reception prohibited
Reception interrupt
enabled
Data 1 reception*1
Data 1 read
ICU data read
ICU interrupt flag clear
Baud rate regulation
ICU interrupt prohibited
Reception enabled
Reception interrupt enabled
Reception interrupt
Data N reception*1
Data N read
Reception prohibited,
Reception interrupt enabled
PID reception
Reception interrupt
NO
PID Field reception *1
Without error?
Error processing*2
YES
Sleep
mode?
NO
YES
Wake up
reception?
YES
*1: If an error occurs, perform the error processing.
*2: • When FRE and ORE are "1", write "1" to SCR: CRE bit and
clear the error flag.
• When ESCR: LBD bit is "1", execute UART reset.
Note: The error is detected in each processing and take appropriate
measures.
400
NO
NO
Wake up
transmission?
YES
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MB91460N series
28.8 Notes on using LIN-USART
Notes on using LIN-USART are given below.
■ Enabling Operations
In LIN-USART, the control register (SCR) has TXE (transmission) and RXE (reception) operation enable bits.
Both, transmission and reception operations, must be enabled before the transfer starts because they have
been disabled as the default value (initial value).
■ Cancelling Transfers
Transfers can be cancelled by clearing their operation enable bits TXE / RXE. If RXE is cleared during an
ongoing reception, then the LIN-USART state machines must be reset (set UPCL=1). If a transmission is
ongoing at the same time, it will be cancelled too! In this case, wait until TDRE=1 and TBI=1 before setting
UPCL.
■ Software reset of LIN-USART
Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "0".
■ Clearing reception errors
Please set SCR:CRE in synchronous slave mode only, if SCR:RXE = 0.
■ Communication Mode Setting
Set the communication mode while the LIN-USART is not operating. If the mode is changed during transmission
or reception, the transmission or reception is stopped and possible data will be get lost.
■ Transmission Interrupt Enabling Timing
The default (initial value) of the transmission data empty flag (SSR: TDRE) is "1" (no transmission data and
transmission data write enable state). A transmission interrupt request is generated as soon as the
transmission interrupt request is enabled (SSR: TIE=1). Be sure to set the TIE bit to "1" after setting the
transmission data to avoid an immediate interrupt.
■ Changing Operation Settings
It is recommended to disable the communication (RXE = 0, TXE = 0), if the LIN-USART setting or mode is
changed or LIN-USART is initialized.
It is strongly recommended to reset LIN-USART after changing operation settings.
Particularly in synchronous mode 2 if (for example) start-/stop-bits are added to or removed from the data
format.
<Caution>
If settings in the Serial Mode Register (SMR) are desired, it is not useful to set the UPCL bit at the same time
to reset LIN-USART. The correct operation settings are not guaranteed in this case. Thus it is recommended
to set the bits of the SMR and then to set them again plus the UPCL bit.
■ LIN slave settings
To initiate LIN-USART for LIN slave make sure to set the baudrate before receiving the first LIN
synchronization break. This is needed to detect safely the minimum of 11 bit times of a LIN synch break.
■ Bus Idle Function
The Bus Idle Function cannot be used in synchronous mode 2. Also, the transmission bus idle detection
function cannot be used when slave mode is selected.
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■ Baud Rate Detection Using the Input Capture Units
The LIN-USARTs provide the signal LSYN that can be connected to the ICU so that LSYN’s pulse length can
be measured to derive the baud rate. In LIN-USART4, the connection of the LSYN signals to the ICUs is
controlled by the Port 14 function register PFR and EPFR. For other channels, see the chapter in I/O Ports.
Figure 28.8-1 Baud Rate Detection Using the Input Capture Units
10
11
S
Pin IN0
LIN-USART0
LSYN
ICU0
PFR[0] & EPFR[0]
FREE RUN TIMER0
10
11
S
Pin IN1
LIN-USART1
LSYN
IN
IN
ICU1
PFR[1] & EPFR[1]
If the PFR bit equals "1" and the EPFR bits equals "0", the ICU is connected to its corresponding input pin IN.
If the PFR bit equals "1" and the EPFR bits equals "1", the LIN-USARTs are connected to the ICU.
The user has to take into account that:
• ICU0 and ICU1 share one free running timer (prescaler).
■ Break field Detection
If the serial input remains to be "0" over 11 bits in mode 3 (LIN mode), the LBD bit of the extended status/
control register (ESCR4) is set to "1" (LIN break field detected), LIN-USART waits for the Synch field.
Consequently, when the serial input remains to be "0" over 11 bits somewhere other than the LIN break field,
LIN-USART recognizes that the LIN break field has been input (LBD=1) and waits for the Synch field.
In this case, execute a programmable reset (SMR4: UPCL = 1).
■ AD bit Serial Control Register (SCR4:AD)
• This bit selects transmission address/data in write operation and returns the last received value of the AD
bit in read operation.
The value of the AD bit for transmission/reception is stored in a different register. When a read-modifywrite (RMW) instruction is used, the value of the AD bit for transmission is read. In other read operation,
the received AD data is read.
• When the TDRE bit changes from "0" to "1" during transmission operation, the AD bit for transmission is
loaded to the transmission shift register along with the data in the transmission data register (TDR4).
Therefore, set the AD bit for transmission before writing to the transmission data register (TDR4).
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■ Effects of reception errors and CRE bit
CRE resets reception state machine and next falling edge at SINn starts reception of new byte. Therefore
either set CRE bit immediately (within half bit time) after receiving errors to prevent data stream
desynchronization or wait an application dependent time after receiving errors and set CRE, when SINn is idle.
Figure 28.8-2 Timing of the CRE bit
CRE bit timing within 1/2 Bit Time of Stop Bit
CRE bit timing out of 1/2 Bit Time of Stop Bit
Last Data Bit
Last Data Bit
Stop Bit
Start Bit
1/2 Bit Time
SIN
Stop Bit
Start Bit
1/2 Bit Time
SIN
Sample
Point
Sample
Point
Error
Flags
Error
Flags
CRE
CRE
Falling edge detected: Receive new Frame
Reception State Machine is reset
Reception State Machine is reset, Start Bit Condition
is reset, actal Reception is desznchronized
Falling edge detected: Receive new Frame
Figure 28.8-3 Data Stream Synchronization
Example for Desynchronisation
SIN
CRE during Start bit
CRE
Reception is reset
RX read
Next falling Edge is
treated as Start bit
1st Frame
2nd Frame
1st desynchronized
frame
Begin of 2nd
desynchronized
frame
Missed bits
Missed bits
Please note, that in case a framing error occurred (stop bit: SINn = 0) and next start bit (SINn = 0) follows
immediately, this start bit is recognized regardless of no falling edge before. This is used to remain UART
synchronized to the data stream and to determine bus always dominant errors ("Fig. 28.8-4 on P. 404" upper
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figure) by producing next framing errors, if a recessive stop bit is expected. If this behaviour is not wanted,
please disable the reception temporarily (RXE = 1 -> 0 -> 1) after framing error. In this case, reception goes on
at next falling edge on SINn. ("Fig. 28.8-4 on P. 404" lower figure).
Figure 28.8-4 LIN-USART Dominant Bus Behaviour
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Chapter 29 I2C Controller
29.1 Overview
The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C
bus.
■ Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Master/slave transmitting and receiving functions
Arbitration function
Clock synchronization function
General call addressing support
Transfer direction detection function
Repeated start condition generation and detection function
Bus error detection function
7 bit addressing as master and slave
10 bit addressing as master and slave
Possibility to give the interface a seven and a ten bit slave address
Acknowledging upon slave address reception can be disabled (Master-only operation)
Address masking to give interface several slave addresses (in 7 bit and 10 bit mode)
Up to 400 kbps transfer rate
Possibility to use built-in noise filters for SDA and SCL
Reception of data at 400 kbps if peripheral clock (CLKP) is higher than 6MHz regardless of prescaler setting
Generation MCU interrupts on transmission and bus error events
Can be slowed down by a slave on bit and byte level
Quantity : 2 channels
The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400 kbps
datarate if the peripheral clock (CLKP) is higher than 6MHz regardless of the prescaler setting. However, clock
stretching on byte level is performed since SCL is pulled low during an interrupt (INT=1 in IBCR2 register).
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■ Block Diagram
Figure 29.1-1 Block diagram of I2C Controller
ICCR
I2C enable
EN
Peripheral Clock (CLKP)
ICCR
Clock Divider 1
2 3 4 5 ... 32
CS4
CS3
5
CS2
5
Clock Selector
Sync
CS1
CS0
Clock Divider 2 (by 12)
SCL Duty Cycle Generator
Shift Clock Generator
IBSR
BB
Bus busy
RSC
Repeated start
LRB
Last Bit
TRX
Send/receive
Bus Observer
Bus Error
ADT
Address Data
AL
Arbitration Loss Detector
SDA
IBCR
SDA
BER
BEIE
Interrupt Request
INTE
R-bus
MCU
IRQ
INT
ICCR
NSF
enable
Noise
Filter
SDA
SCL
IBCR
SCC
MSS
ACK
GCAA
Start
Start-Stop Condition
Generator
Master
ACK enable
GC-ACK enable
8
GCA
ISMK
ENSB
ITMK
ENTB
RAL
SCL
IDAR
IBSR
AAS
SCL
ACK Generator
8
Slave
General call
enable 7 bit mode
Slave Address
Comparator
enable 10 bit mode
received ad. length
7
10
10
ITBA
ITMK
7
ISBA
ISMK
10
10
7
7
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29.2 I2C Interface Registers
This section describes the function of the I2C interface registers in detail.
Figure 29.2-1 Bus Control Register (IBCR)
Bus control register
15
Address : 000368H, 000374H
14
13
12
BER BEIE SCC MSS
11
10
9
ACK GCAA INTE
8
INT
⇐ Bit no.
IBCR2, 3
Read/write ⇒ (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default value⇒
Figure 29.2-2 Bus Status Register (IBSR)
Bus status register
Address : 000369H, 000375H
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
BB
RSC
AL
LRB
TRX
AAS GCA ADT
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
0
⇐ Bit no.
IBSR2, 3
(R)
(0)
Figure 29.2-3 Ten Bit slave Address register (ITBA)
Ten Bit Address high byte
Address : 00036AH, 000376H
Read/write ⇒
Default value⇒
Ten Bit Address low byte
Address : 00036BH, 000377H
Read/write ⇒
Default value⇒
15
14
13
12
11
10
9
8
---
---
---
---
---
---
TA9
TA8
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
⇐ Bit no.
ITBAH2, 3
(R/W) (R/W)
(0)
(0)
⇐ Bit no.
ITBAL2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Figure 29.2-4 Ten bit slave address MasK register (ITMK)
Ten Bit Address Mask high byte
Address : 00036CH, 000378H
15
ENTB RAL
Read/write ⇒ (R/W)
(0)
Default value⇒
Ten Bit Address Mask low byte
Address : 00036DH, 000379H
Read/write ⇒
Default value⇒
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(0)
7
6
TM7
TM6
13
12
11
10
9
8
---
---
---
---
TM9
TM8
(-)
(1)
(-)
(1)
(-)
(1)
(-)
(1)
5
4
TM5 TM4
3
2
TM3
TM2
⇐ Bit no.
ITMKH2, 3
(R/W) (R/W)
(1)
(1)
1
0
TM1 TM0
⇐ Bit no.
ITMKL2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
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Figure 29.2-5 Seven bit slave address MasK register (ISMK)
Seven Bit Address Mask register
15
14
13
12
ENSB SM6 SM5 SM4
Address : 00036EH, 00037AH
11
10
9
8
SM3 SM2 SM1 SM0
⇐ Bit no.
ISMK2, 3
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Default value⇒
Figure 29.2-6 Seven Bit slave Address register (ISBA)
Seven Bit Address register
Address : 00036FH, 00037BH
Read/write ⇒
Default value⇒
7
6
---
SA6
(-)
(0)
5
4
SA5 SA4
3
2
SA3
SA2
1
0
SA1 SA0
⇐ Bit no.
ISBA2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Figure 29.2-7 Data Register (IDAR)
Data register
Address : 000371H, 00037DH
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
⇐ Bit no.
IDAR2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Figure 29.2-8 Clock control register (ICCR)
Clock Control register
Address : 000372H, 00037EH
Read/write ⇒
Default value⇒
408
15
14
13
12
---
NSF
EN
CS4
(-)
(0)
11
10
CS3 CS2
9
8
CS1
CS0
⇐ Bit no.
ICCR2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(1)
(1)
(1)
(1)
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29.2.1 Bus Control Register (IBCR)
The bus control register (IBCR0) has the following functions:
• Interrupt request enable bits
• Interrupt generation flag
• Bus error detection flag
• Repeated start condition generation
• Master / slave mode selection
• General call acknowledge generation enabling
• Data byte acknowledge generation enabling
Write access to this register should only occur while the INT=1 or if a transfer is to be started. The user should
not write to this register during an ongoing transfer since changes to the ACK or GCAA bits could result in bus
errors. All bits in this register except the BER and the BEIE bit are cleared if the interface is not enabled (EN=0
in ICCR).
Figure 29.2-9 Bus Control Register (IBCR)
Bus control register
15
Address : 000368H, 000374H
14
13
12
BER BEIE SCC MSS
11
10
9
ACK GCAA INTE
8
INT
⇐ Bit no.
IBCR2, 3
Read/write ⇒ (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default value⇒
[bit 15] BER (Bus ERror)
This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. It is always read as "1"
in a Read-Modify-Write access.
(Write access)
0
Clear bus error interrupt flag.
1
No effect.
(Read access)
0
No bus error detected.
1
One of the error conditions described below detected.
When this flag is set, the EN bit in the ICCR register is cleared, the I2C interface goes to pause status, data
transfer is interrupted and all bits in the IBSR and the IBCR registers except BER, BEIE and INT are cleared.
The BER flag must be cleared before the interface may be reenabled.
This bit is set to "1" if:
• start or stop conditions are detected at wrong places: during an address data transfer or during the transfer
of the bits two to nine (acknowledge bit)
• a ten bit address header with read access is received before a ten bit write access
• a stop condition is detected while the interface is in master mode
The detection of the first two of the above conditions is enabled after the reception of the first stop condition to
prevent false bus error reports if the interface is being enabled during an ongoing transfer.
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[bit 14] BEIE (Bus Error Interrupt request Enable)
This bit enables the bus error interrupt request. It can only be changed by the user.
0
Bus error interrupt request disabled.
1
Bus error interrupt request enabled.
Setting this bit to "1" enables MCU interrupt request generation when the BER flag is set to "1".
[bit 13] SCC (Start Condition Continue)
This bit is used to generate a repeated start condition. It is write only - it is always read as "0".
0
No effect.
1
Generate repeated start condition during master transfer.
A repeated start condition is generated if a "1" is written to this bit while an interrupt in master mode (MSS=1
and INT=1) and the INT bit is cleared automatically.
[bit 12] MSS (Master Slave Select)
This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user
and the hardware.
0
Go to slave mode.
1
Go to master mode, generate start condition and send address data byte in
IDAR0 register.
It is cleared if an arbitration loss event occurs during master sending.
If a "0" is written to it during a master interrupt (MSS=1 and INT=1), the INT bit is cleared automatically, a stop
condition will be generated and the data transfer ends. Note that the MSS bit is reset immediately, the
generation of the stop condition can be checked by polling the BB bit in the IBSR register.
If a "1" is written to it while the bus is idle (MSS=0 and BB=0), a start condition is generated and the contents
of the IDAR register (which should be address data) is sent.
If a "1" is written to the MSS bit while the bus is in use (BB=1 and TRX=0 in IBSR; MSS=0 in IBCR), the
interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime
(AAS=1 and TRX=1 in IBSR), it will not start sending data if the bus is free again. It is important to check
whether the interface was addressed as slave (AAS=1 in IBSR), sent the data byte successfully (MSS=1 in
IBCR) or failed to send the data byte (AL=1 in IBSR) at the next interrupt!
[bit 11] ACK (ACKnowledge)
This is the acknowledge generation on data byte reception enable bit. It can only be changed by the user.
410
0
The interface will not acknowledge on data byte reception.
1
The interface will acknowledge on data byte reception.
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This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave
address, it will acknowledge if the corresponding enable bit (ENTB in ITMK or ENSB in ISMK) is set.
Write access to this bit should occur during an interrupt (INT=1) or if the bus is idle (BB=0 in the IBSR
register). In addition the interface must be enabled (EN=1 in ICCR) and there has to be no bus error (BER=0
in IBCR).
[bit 10] GCAA (General Call Address Acknowledge)
This bit enables acknowledge generation when a general call address is received. It can only be changed by
the user.
0
The interface will not acknowledge on general call address byte reception.
1
The interface will acknowledge on general call address byte reception.
Write access to this bit should occur during an interrupt (INT=1) or if the bus is idle (BB=0 in IBSR register),
write access to this bit is only possible if the interface is enabled (EN=1 in ICCR) and if there is no bus error
(BER=0 in IBCR).
[bit 9] INTE (INTerrupt request Enable)
This bit enables the MCU interrupt request generation. It can only be changed by the user.
0
Interrupt request disabled.
1
Interrupt request enabled.
Setting this bit to "1" enables MCU interrupt request generation when the INT bit is set to "1" (by the
hardware).
[bit 8]: INT (INTerrupt)
This bit is the transfer end interrupt flag. It is changed by the hardware and can be cleared by the user. It is
always read as "1" in a Read-Modify-Write access.
(Write access)
0
Clear transfer end interrupt flag.
1
No effect.
(Read access)
0
Transfer not ended or not involved in current transfer or bus is idle.
1
Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
• Device is bus master.
• Device is addressed as slave.
• General call address received.
• Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address
received, after second byte if ten bit address received) including the acknowledge
bit if the device is addressed as slave.
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While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit clears the setting, releases
the SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated.
Additionally, this bit is cleared if a "1" is written to the SCC bit or the MSS bit is being cleared.
SCC, MSS And INT Bit Competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
• Next byte transfer and stop condition generation.
When "0" is written to the INT bit and "0" is written to the MSS bit, the MSS bit takes priority and a stop
condition is generated.
• Next byte transfer and start condition generation.
When "0" is written to the INT bit and "1" is written to the SCC bit, the SCC bit takes priority. A repeated start
condition is generated and the content of the IDAR0 register is sent.
• Repeated start condition generation and stop condition generation.
When "1" is written to the SCC bit and "0" to the MSS bit, the MSS bit clearing takes priority. A stop
condition is generated and the interface enters slave mode.
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29.2.2 Bus Status Register (IBSR)
The bus status register (IBSR) has the following functions:
• Bus busy detection
• Repeated start condition detection
• Arbitration loss detection
• Acknowledge detection
• Data transfer direction indication
• Addressing as slave detection
• General call address detection
• Address data transfer detection
This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not
enabled (EN=0 in ICCR).
Figure 29.2-10 Bus Status Register (IBSR)
Bus status register
Address : 000369H, 000375H
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
BB
RSC
AL
LRB
TRX
AAS GCA ADT
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
0
⇐ Bit no.
IBSR2, 3
(R)
(0)
[bit 7] BB (Bus Busy)
This bit indicates the status of the I2C bus.
0
Stop condition detected (bus idle).
1
Start condition detected (bus in use).
This bit is set to "1" if a start condition is detected. It is reset upon a stop condition.
[bit 6] RSC (Repeated Start Condition)
This bit indicates detection of a repeated start condition.
0
Repeated start condition not detected.
1
Bus in use, repeated start condition detected.
This bit is cleared at the end of an address data transfer (ADT=0) or detection of a stop condition.
[bit 5] AL (Arbitration Loss)
This bit indicates an arbitration loss.
0
No arbitration loss detected.
1
Arbitration loss occurred during master sending.
This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR register.
An arbitration loss occurs if:
• the data sent does not match the data read on the SDA line at the rising SCL edge
• a repeated start condition is generated by another master in the first bit of a data byte
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• the interface could not generate a start or stop condition because another slave pulled the SCL line low
before
[bit 4] LRB (Last Received Bit)
This bit is used to store the acknowledge message from the receiving side at the transmitter side.
0
Receiver acknowledged.
1
Receiver did not acknowledge.
It is changed by the hardware upon reception of bit 9 (acknowledge bit) and is also cleared by a start or stop
condition.
[bit 3] TRX (Transmitting data)
This bit indicates data sending operation during data transmission.
0
Not transmitting data.
1
Transmitting data.
It is set to "1":
• if a start condition was generated in master mode at the end of a first byte transfer and read access as slave
or sending data as master
It is set to "0" if:
• the bus is idle (BB=0 in IBCR)
• an arbitration loss occurred
• a "1" is written to the SCC bit during master interrupt (MSS=1 and INT=1)
• the MSS bit is cleared during master interrupt (MSS=1 and INT=1)
• the interface is in slave mode and the last transferred byte was not acknowledged
• the interface is in slave mode and it is receiving data
• the interface is in master mode and is reading data from a slave
[bit 2] AAS (Addressed As Slave)
This bit indicates detection of a slave addressing.
0
Not addressed as slave.
1
Addressed as slave.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its seven and/or ten
bit slave address.
[bit 1] GCA (General Call Address)
This bit indicates detection of a general call address (00H).
414
0
General call address not received as slave.
1
General call address received as slave.
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This bit is cleared by a (repeated-) start or stop condition.
[bit 0] ADT (Address Data Transfer)
This bit indicates the detection of an address data transfer.
0
Incoming data is not address data (or bus is not in use).
1
Incoming data is address data.
This bit is set to "1" by a start condition. It is cleared after the second byte if a ten bit slave address header
with write access is detected, else it is cleared after the first byte.
"After" the first/second byte means:
• a "0" is written to the MSS bit during a master interrupt (MSS=1 and INT=1 in IBCR)
• a "1" is written to the SCC bit during a master interrupt (MSS=1 and INT=1 in IBCR)
• the INT bit is being cleared
• the beginning of every byte transfer if the interface is not involved in the current transfer as master or slave
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29.2.3 Ten Bit Slave Address Register (ITBA)
This register (ITBAH/ITBAL) designates the ten bit slave address.
Write access to this register is only possible if the interface is disabled (EN=0 in ICCR).
Figure 29.2-11 Ten Bit Slave Address Register (ITBA)
Ten Bit Address high byte
Address : 00036AH, 000376H
Read/write ⇒
Default value⇒
Ten Bit Address low byte
Address : 00036BH, 000377H
Read/write ⇒
Default value⇒
15
14
13
12
11
10
9
8
---
---
---
---
---
---
TA9
TA8
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
⇐ Bit no.
ITBAH2, 3
(R/W) (R/W)
(0)
(0)
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
⇐ Bit no.
ITBAL2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
[bit 15 to bit 10] Not used.
These bits always read "0".
[bit 9 to bit 0] TBA - Ten Bit slave Address (TA9 to TA0)
When address data is received in slave mode, it is compared to the ITBA register if the ten bit address is
enabled (ENTB=1 in the ITMK register). An acknowledge is sent to the master after reception of a ten bit
address header with write access*1. Then, the second incoming byte is compared to the ITBA register. If a
match is detected, an acknowledge signal is sent to the master device and the AAS bit is set.
Additionally, the interface acknowledges upon the reception of a ten bit header with read access*2 after a
repeated start condition.
All bits of the slave address may be masked using the ITMK register. The received ten bit slave address is
written back to the ITBA register, it is only valid while the AAS bit in the IBSR register is "1".
*1 : A ten bit header (write access) consists of the following bit sequence: 11110B, TA9, TA8, 0.
*2 : A ten bit header (read access) consists of the following bit sequence: 11110B, TA9, TA8, 1.
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29.2.4 Ten Bit Address Mask Register (ITMK)
This register contains the ten bit slave address mask and the ten bit slave address enable bit.
Figure 29.2-12 Ten Bit Address Mask Register (ITMK)
Ten Bit Address Mask high byte
Address : 00036CH, 000378H
15
13
12
11
10
9
8
---
---
---
---
TM9
TM8
(R)
(0)
(-)
(1)
(-)
(1)
(-)
(1)
(-)
(1)
7
6
5
4
3
2
TM7
TM6
TM3
TM2
Read/write ⇒ (R/W)
(0)
Default value⇒
Ten Bit Address Mask low byte
Address : 00036DH, 000379H
Read/write ⇒
Default value⇒
14
ENTB RAL
TM5 TM4
⇐ Bit no.
ITMKH2, 3
(R/W) (R/W)
(1)
(1)
1
0
TM1 TM0
⇐ Bit no.
ITMKL2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
[bit 15] ENTB - EnaBle Ten Bit slave address
This bit enables the ten bit slave address (and the acknowledging upon its reception). Write access to this bit
is only possible if the interface is disabled (EN=0 in ICCR0).
0
Ten bit slave address disabled.
1
Ten bit slave address enabled.
[bit 14] RAL - Received slave Address Length
This bit indicates whether the interface was addressed as a seven or ten bit slave. It is read-only.
0
Addressed as seven bit slave.
1
Addressed as ten bit slave.
This bit can be used to determine whether the interface was addressed as a seven or ten bit slave if both
slave addresses are enabled (ENTB=1 and ENSB=1). Its contents is only valid if the AAS bit in the IBSR
register is "1". This bit is also reset if the interface is disabled (EN=0 in ICCR).
[bit 13 to bit 10] Not used.
These bits always read "1".
[bit 9 to bit 0] TMK - Ten bit slave address MasK (TM9 to TM0).
This register is used to mask the ten bit slave address of the interface. Write access to these bits is only
possible if the interface is disabled (EN=0 in ICCR).
0
Bit is not used in slave address comparison.
1
Bit is used in slave address comparison.
This can be used to make the interface acknowledge on multiple ten bit slave addresses. Only the bits set to
"1" in this register are used in the ten bit slave address comparison. The received slave address is written
back to the ITBA register and thus may be determined by reading the ITBA register if the AAS bit in the IBSR
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register is "1".
Note: If the address mask is changed after the interface had been enabled, the slave address should also be
set again since it could have been overwritten by a previously received slave address.
29.2.5 Seven Bit Slave Address Register (ISBA)
This register designates the seven bit slave address.
Write access to this register is only possible if the interface is disabled (EN=0 in ICCR).
Figure 29.2-13 Seven Bit Slave Address Register (ISBA)
Seven Bit Address register
Address : 00036FH, 00037BH
Read/write ⇒
Default value⇒
7
6
---
SA6
(-)
(0)
5
4
SA5 SA4
3
2
SA3
SA2
1
0
SA1 SA0
⇐ Bit no.
ISBA2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
[bit 7] Not used.
This bit always reads "0".
[bit 6 to bit 0] Seven Bit slave Address (SA6 to SA0)
When address data is received in slave mode, it is compared to the ISBA register if the seven bit address is
enabled (ENSB=1 in the ISMK register). If a match is detected, an acknowledge signal is sent to the master
device and the AAS bit is set.
All bits of the slave address may be masked using the ISMK register. The received seven bit slave address is
written back to the ISBA register, it is only valid while the AAS bit in the IBSR register is "1".
The interface does not compare the contents of this register to the incoming data if a ten bit header or a
general call is received.
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29.2.6 Seven Bit Slave Address Mask Register (ISMK)
This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to
this register is only possible if the interface is disabled (EN=0 in ICCR).
Figure 29.2-14 Seven Bit Slave Address Mask Register (ISMK)
Seven Bit Address Mask register
Address : 00036EH, 00037AH
15
14
13
12
ENSB SM6 SM5 SM4
11
10
9
8
SM3 SM2 SM1 SM0
⇐ Bit no.
ISMK2, 3
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Default value⇒
[bit 15] ENSB - EnaBle Seven Bit slave address
This bit enables the seven bit slave address (and the acknowledge upon its reception).
0
Seven bit slave address disabled.
1
Seven bit slave address enabled.
[bit 14 to bit 8] SMK - Seven bit slave address MasK (SM6 to SM0)
This register is used to mask the seven bit slave address of the interface.
0
Bit is not used in slave address comparison.
1
Bit is used in slave address comparison.
This can be used to make the interface acknowledge on multiple seven bit slave addresses. Only the bits set
to "1" in this register are used in the seven bit slave address comparison. The received slave address is
written back to the ISBA register and thus may be determined by reading the ISBA register if the AAS bit in the
IBSR register is "1".
Note: If the address mask is changed after the interface had been enabled, the slave address should also be
set again since it could have been overwritten by a previously received slave address.
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29.2.7 Data Register (IDAR)
Figure 29.2-15 Data Register (IDAR)
Data register
Address : 000371H, 00037DH
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
⇐ Bit no.
IDAR2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
[bit 7 to bit 0] Data bits (D7 to D0)
The data register is used in serial data transfer, and transfers data MSB-first. This register is double buffered
on the write side, so that when the bus is in use (BB=1), write data can be loaded to the register for serial
transfer. The data byte is loaded into the internal transfer register if the INT bit in the IBCR register is being
cleared or the bus is idle (BB=0 in IBSR). In a read access, the internal register is read directly, therefore
received data values in this register are only valid if INT=1 in the IBCR register.
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29.2.8 Clock Control Register (ICCR)
The clock control register (ICCR0) has the following functions:
• Enable IO pad noise filters
• Enable I2C interface operation
• Setting the serial clock frequency
Figure 29.2-16 Clock Control Register (ICCR)
Clock Control register
Address : 000372H, 00037EH
Read/write ⇒
Default value⇒
15
14
13
12
---
NSF
EN
CS4
(-)
(0)
11
10
CS3 CS2
9
8
CS1
CS0
⇐ Bit no.
ICCR2, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(1)
(1)
(1)
(1)
(1)
[bit 15] Not used.
This bit always reads "0".
[bit 14] IO pad NoiSe Filter enable.
This bit enables the noise filters built into the SDA and SCL IO pads.
The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and between 1 and 1.5 cycles
of R-bus (maximum). The maximum depends on the phase relationship between I2C signals (SDA, SCL) and
Peripheral clock.
It should be set to "1" if the interface is transmitting or receiving at datarates above 100 kbps.
[bit 13] EN (ENable)
This bit enables the I2C interface operation. It can only be set by the user but may be cleared by the user and
the hardware.
0
Interface disabled.
1
Interface enabled.
When this bit is set to "0" all bits in the IBSR register and IBCR register (except the BER and BEIE bits) are
cleared, the module is disabled and the I2C lines are left open. It is cleared by the hardware if a bus error
occurs (BER=1 in IBCR).
Warning: The interface immediately stops transmitting or receiving if is it is being disabled. This might leave
the I2C bus in an undesired state!
[bit 12 to bit 8] CS4 to 0 (Clock preScaler)
These bits select the serial bitrate. They can only be changed if the interface is disabled (EN=0) or the EN bit
is being cleared in the same write access.
It is determined by the following formula:
(Note)
Bitrate =
φ
Noise filter disabled
n × 12 + 18 n>0; φ : Peripheral clock CLKP (set by DIVR0 register)
Bitrate =
φ
n × 12 + 19 (+1)
Noise filter enabled
n>0; φ : Peripheral clock CLKP (set by DIVR0 register)
(+1): Inaccuracy caused by noise filter operation
Because of the noise filter (depending on relationship between external signal and internal clock it
will cause different delays ) the divider in the second formula can vary between (12n + 19) and (12n
+ 20).
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■ Prescaler settings:
Table 29.2-1 I2C Prescaler Settings
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
1
1
1
...
31
1
1
Do not use n=0 prescaler setting, it violates SDA/SCL timings!
The table below shows SCL frequency measurement results for the most common peripheral clock settings
and the recommended related pre-scaler settings for 100 kbps and 400 kbps operation.
Peripheral
Clock (CLKP)
[MHz]
100 kbps (Noise filter disabled)
n
400 kbps (Noise filter enabled)
Bitrate [kbps]
32
n
Bitrate [kbps]
5
387.5
24
19
97.5
4
352.5
16
12
98
2
372
8
6
89
1
266.5
It should be noted that the measured values have been determined by examining the last 8 cycles of a
transfer. This was done because the first cycle of all address or data transfers is longer than the other cycles.
To be more precise: In case of an address transfer this first cycle is 3 prescaler periods longer than the other
cycles, in case of a data transfer it is 4 prescaler periods longer (see figure below).
■ SCL Waveforms
Figure 29.2-17 SCL Waveforms
Address sending
9
6
7
5
7
5
Data sending
9
7
5
7
5
7
Time unit: Prescaler cycles
Figure 29.2-17 shows the SCL waveform for sending of address and data bits. The timings given
in the figure are prescaler periods (e.g. "9" means 9 times the prescaler count based on the
Peripheral clock). The timings in the figure are only valid if no other device on the I2C bus
influences the SCL timing.
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29.3 I2C Interface Operation
The I2C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial
clock line (SCL). The I2C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines,
enabling wired logic applications.
■ Start Conditions
When the bus is free (BB=0 in IBSR, MSS=0 in IBCR), writing "1" to the MSS bit places the I2C interface in
master mode and generates a start condition.
If "1" is written to it while the bus is idle (MSS=0 and BB=0), a start condition is generated and the contents of
the IDAR register (which should be address data) is sent.
Repeated start conditions can be generated by writing "1" to the SCC bit when in bus master mode and
interrupt status (MSS=1 and INT=1 in IBCR).
If a "1" is written to the MSS bit while the bus is in use (BB=1 and TRX=0 in IBSR; MSS=0 and INT=0 in
IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus of free again. It is important to check whether the interface was addressed
as slave (MSS=0 in IBCR and AAS=1 in IBSR), sent the data byte successfully (MSS=1 in IBCR) or failed to
send the data byte (AL=1 in IBSR) at the next interrupt!
Writing "1" to the MSS bit or SCC bit in any other situation has no significance.
■ Stop Conditions
Writing "0" to the MSS bit in master mode (MSS=1 and INT=1 in IBCR) generates a stop condition and places
the device in slave mode. Writing "0" to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another master
pulls the SCL line low before the stop condition has been generated. This will generate an interrupt after the
next byte has been transferred!
■ Slave Address Detection
In slave mode, after a start condition is generated the BB is set to "1" and data sent from the master device is
received into the IDAR register.
After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using the
bit mask stored in ISMK if the ENSB bit in the ISMK register is "1". If a match results, the AAS bit is set to "1"
and an acknowledge signal is sent to the master. Then bit 0 of the received data (bit 0 of the IDAR register) is
inverted and stored in the TRX bit.
If the ENTB bit in the ITMK register is "1" and a ten bit address header (11110, TA1, TA0, write access) is
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask stored
in ITMK) to the lower byte of the ITBA register. If a match is found, an acknowledge signal is sent to the
master, the AAS bit is set and an interrupt is generated.
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after
reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.
Since there are separate registers for the ten and seven bit address and their bitmasks, it is possible to make
the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits. The
received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK
register (this bit is valid if the AAS bit is set only).
It is also possible to give the interface no slave address by setting both bits to "0" if it is only used as a master.
All slave address bits may be masked with their corresponding mask register (ITMK or ISMK).
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■ Slave Address Masking
Only the bits set to "1" in the mask registers (ITMK/ISMK) are used for address comparison, all other bits are
ignored. The received slave address can be read from the ITBA (if ten bit address received, RAL=1) or ISBA
(if seven bit address received, RAL=0) register if the AAS bit in the IBSR register is "1".
If the bitmasks are cleared, the interface can be used as a bus monitor since it will always be addressed as
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception,
even if there is no other slave listening.
■ Addressing Slaves
In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of the
IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was received
from the slave device, bit 0 of the sent data (bit 0 of the IDAR register after sending) is inverted and stored in
the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR register. This
procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 to A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start 1 1 1 1 0 A9 A8 1.
■ Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the
device is considered to have lost arbitration, and the AL bit is set to "1". Also, the AL bit is set to "1" if a start
condition is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave mode
so it is able to acknowledge if its own slave address is being sent.
■ Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be used
to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received from
the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave may be checked by reading the LRB bit in the IBSR register.
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29.4 Programming Flow Charts
■ Example Of Slave Addressing And Sending Data
Figure 29.4-1 Example Of Slave Addressing And Sending Data
Addressing a 7 bit slave
Sending data
Start
Start
Address slave for write
Clear BER bit (if set);
Enable Interface EN:=1;
IDAR := Data Byte;
INT := 0
IDAR := sl.address<<1+RW;
MSS := 1; INT := 0
N
INT=1?
N
INT=1?
Y
Y
Y
BER=1?
Y
Bus error
BER=1?
N
N
AL=1?
Restart
transfer
Check
if AAS
Y
AL=1?
Y
Restart
transfer
Check
if AAS
N
N
ACK?
ACK?
N
N
(LRB=0?)
(LRB=0?)
Y
Y
Ready to send data
Last byte
Y
transferred?
N
Slave did not ACK
Generate
repeated start
or stop condition
Transfer End
Generate
repeated start or
stop condition
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■ Example Of Receiving Data
Figure 29.4-2 Example of Receiving Data
Start
Address slave for read
Clear ACK bit in IBCR if it’s the
last byte to read from slave;
INT := 0
N
INT=1?
Y
BER=1?
Y
Bus error
reenable IF
N
N
Last byte
transferred?
Y
Transfer End
Generate
repeated start or
stop condition
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■ Example Of An Interrupt Handler
Figure 29.4-3 Example Of An Interrupt Handler
Start
INT=1?
N
Interrupt
from other
module
received
Y
BER=1?
Y
Bus error
reenable IF
GCA=1? Y
N
N
Y
General call
as slave
AAS=1? Y
AL=1?
AL=1?
N
N
Transfer failed
remember to retry
LRB=1?
Y
Y
Y
ADT=1?
N
New data transfer
starts at next INT
Change ACK bit
if necessary
Arbitration
lost
Restart
transfer
Slave did
not ACK
Generate
stop or
repeated
start
N
TRX=1?
TRX=1?
Y
Y
N
N
Read received byte
from IDAR register
Change ACK bit if
necessary
Put next byte to be
sent in IDAR
register
Read received byte
from IDAR register
Change ACK bit if
necessary
Put next byte
to be sent in
IDAR register
or clear MSS
Clear INT bit
End ISR
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Chapter 30 CAN Controller
30.1
MB91460N series
Chapter 30 CAN Controller
30.1 Overview
The CAN performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be
programmed to values up to 1MBit/s. For the connection to the physical layer additional transceiver hardware
is required.
■ The CAN implements the following features:
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 (up to 128) Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Programmable loop-back mode for self-test operation
• Read/write to message buffer with interface register
• Quantity : 2 channels
■ This chapter uses the following terms and abbreviations.
Term
CAN
BSP
BTL
CRC
DLC
EML
FSM
TTCAN
Meaning
Controller Area Network
Bit Stream Processor
Bit Timing Logic
Cyclic Redundancy Check
Data Length Code
Error Management Logic
Finite State Machine
Time Triggered CAN
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MB91460N series
30.2 Block diagram of the CAN Controller
Figure 30.2-1 Block diagram of the CAN Controller
TX
RX
CAN Controller
CAN Core
Registers
Message Handler
Message RAM
Interrupt
D-Bus
CLKB
CLKCAN
Module Interface
● CAN controller
CAN controller controls the serial register for the serial/parallel conversion for CAN protocol and transfer of
reception/transmission messages.
● Message RAM
Stores a message object.
● Registers
All registers when using in CAN.
● Message handler
Controls message RAM and CAN controller.
● CPU interface
Controls the interface of FR family internal bus.
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30.3
MB91460N series
30.3 CAN Registers
CAN has the following registers:
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler extension register (BRPER)
• IFx command request register (IFxCREQ)
• IFx command mask register (IFxCMSK)
• IFx mask register 1, 2 (IFxMSK1, IFxMSK2)
• IFx arbitration 1, 2 (IFxARB1, IFxARB2)
• IFx message control register (IFxMCTR)
• IFx data register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• CAN transmission request register 1, 2 (TREQR1, TREQR2)
• CAN new data register 1, 2 (NEWDT1, NEWDT2)
• CAN interrupt pending register 1, 2 (INTPND1, INTPND2)
• CAN message valid register 1, 2 (MSGVAL1, MSGVAL2)
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Table 30.3-1 CAN Register Summary
Register
Address
Note
+0
Base-addr +
00H
Base-addr +
04H
Base-addr +
08H
+1
+2
+3
Control Register
Status Register
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
reserved
see descr. CTRLR
reserved
see descr. STATR
Reset: 00H
Reset: 01H
Reset: 00H
Reset: 00H
Error Counter
Bit Timing Register
Error Counter is read
only.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
RP,REC[6:0]
TEC[7:0]
TSeg2[2:0],TSeg1[3:0]
SJW[1:0],BRP[5:0]
Reset: 00H
Reset: 00H
Reset: 23H
Reset: 01H
Interrupt Register
Test Register
Bit Timing Register is
write enabled by
CCE
Interrupt Register is
read only.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Int-Id[15:8]
Int-Id[7:0]
reserved
see descr. TESTR
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H &
Test Register is write
enabled by Test.
r signifies the actual
value of the RX pin.
0br0000000
Base-addr +
0CH
Base-addr +
10H
Base-addr +
14H
Base-addr +
18H
Base-addr +
1CH
432
Prescaler Extension Register
Reserved
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
reserved
BRP[3:0]
reserved
reserved
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 Command Request
BRP Extension Register is write enabled
by CCE.
IF1 Command Mask
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Busy
Mess. No. [5:0]
reserved
see descr. IF1CMSK
Reset: 00H
Reset: 01H
Reset: 00H
Reset: 00H
IF1 Mask 2
IF1 Mask 1
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MXtd,MDir,Msk[28:24]
Msk[23:16]
Msk[15:8]
Msk[7:0]
Reset: FFH
Reset: FFH
Reset: FFH
Reset: FFH
IF1 Arbitration 2
IF1 Arbitration 1
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal,Xtd,Dir,ID[28:24]
ID[23:16]
ID[15:8]
ID[7:0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 Message Control
Reserved
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
see descr. IF1MCTR
see descr. IF1MCTR
reserved
reserved
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
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30.3
MB91460N series
Register
Address
Note
+0
Base-addr +
20H
+1
+2
+3
IF1 Data A1
Base-addr +
24H
IF1 Data A2
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[0]
Data[1]
Data[2]
Data[3]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 Data B1
Base-addr +
30H
IF1 Data B2
bit[15:8]
bit[7:0]
bit[15:8]
Data[4]
Data[5]
Data[6]
Data[7]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 Data A1
bit[7:0]
bit[15:8]
bit[7:0]
Data[3]
Data[2]
Data[1]
Data[0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 Data B1
bit[7:0]
bit[15:8]
bit[7:0]
Data[7]
Data[6]
Data[5]
Data[4]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 Command Mask
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Busy
Mess. No. [5:0]
reserved
see descr. IF2CMSK
Reset: 00H
Reset: 01H
Reset: 00H
Reset: 00H
IF2 Mask 2
Base-addr +
48H
Little Endian byte
ordering.
bit[15:8]
IF2 Command Request
Base-addr +
44H
Little Endian byte
ordering.
bit[15:8]
IF1 Data B2
Base-addr +
40H
Big Endian byte
ordering.
bit[7:0]
IF1 Data A2
Base-addr +
34H
Big Endian byte
ordering.
IF2 Mask 1
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MXtd,MDir,Msk[28:24]
Msk[23:16]
Msk[15:8]
Msk[7:0]
Reset: FFH
Reset: FFH
Reset: FFH
Reset: FFH
IF2 Arbitration 2
IF2 Arbitration 1
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal,Xtd,Dir,ID[28:24]
ID[23:16]
ID[15:8]
ID[7:0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Base-addr +
4CH
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IF2 Message Control
Reserved
bit[15:8]
bit[7:0]
bit[7:0]
bit[15:8]
see descr. IF2MCTR
see descr. IF2MCTR
reserved
reserved
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
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Register
Address
Note
+0
Base-addr +
50H
Base-addr +
54H
Base-addr +
60H
Base-addr +
64H
Base-addr +
80H
+1
Base-addr +
A4H
434
IF2 Data A2
Big Endian byte
ordering.
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[0]
Data[1]
Data[2]
Data[3]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 Data B1
IF2 Data B2
Big Endian byte
ordering.
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[4]
Data[5]
Data[6]
Data[7]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 Data A2
IF2 Data A1
Little Endian byte
ordering.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[3]
Data[2]
Data[1]
Data[0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 Data B2
IF2 Data B1
Little Endian byte
ordering.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[7]
Data[6]
Data[5]
Data[4]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Transmission Request Register 2
Transmission Request Register 1
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
TxRqst[32 to 25]
TxRqst[24 to 17]
TxRqst[1 to 9]
TxRqst[8 to 1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Transmission
Request Register is
read only.
Reserved ( >32..128 Message buffer)
New Data 2
New Data 1
New Data is read
only.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
NewDat[32 to 25]
NewDat[24 to 17]
NewDat[16 to 9]
NewDat[8 to 1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Base-addr +
94H
Base-addr +
A0H
+3
IF2 Data A1
Base-addr +
84H
Base-addr +
90H
+2
Reserved ( >32..128 Message buffer)
Interrupt Pending 2
Interrupt Pending 1
Interrupt Pending is
read only.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
IntPnd[32 to 25]
IntPnd[24 to 17]
IntPnd[16 to 9]
IntPnd[8 to 1]
Reset: 00H
Reset: 00H
RReset: 00H
Reset: 00H
Reserved ( >32..128 Message buffer)
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30.3
MB91460N series
Register
Address
Note
+0
Base-addr +
B0H
+1
+2
Message Valid 2
+3
Message Valid 1
Message Valid is
read only.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal[32 to 25]
MsgVal[24 to 17]
MsgVal[16 to 9]
MsgVal[8 to 1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Base-addr +
B4H
Reserved ( >32..128 Message buffer)
Table 30.3-2 CAN Prescaler Register Summary
Address
0004C0H
CM44-10149-1E
Register
+0
+1
+2
+3
CANPRE
CANCKD
-
-
bit[3:0]
bit[5:0]
-
-
CANPRE[3:0]
CANCKD[5:0]
-
-
Reset: 00H
Reset: 00H
-
-
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CAN Prescaler
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30.4
MB91460N series
30.4 CAN register function
The CAN register is assigned with a 256-byte (64 words) address space. The CPU access to the message
RAM is made via the message interface register.
This section describes the CAN register and detailed functions of each register.
■ CAN register
• Overall control register
- CAN control register (CTRLR)
- CAN status register (STATR)
- CAN error counter (ERRCNT)
- CAN bit timing register (BTR)
- CAN interrupt register (INTR)
- CAN test register (TESTR)
- CAN prescaler extension register (BRPER)
• Message interface register
- IFx command request register (IFxCREQ)
- IFx command mask register (IFxCMSK)
- IFx mask register 1, 2 (IFxMSK1, IFxMSK2)
- IFx arbitration register 1, 2 (IFxARB1, IFxARB2)
- IFx message control register (IFxMCTR)
- IFx data register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• Message handler register
- CAN transmission request register 1, 2 (TREQR1, TREQR2)
- CAN data update register 1, 2 (NEWDT1, NEWDT2)
- CAN interrupt pending register 1, 2 (INTPND1, INTPND2)
- CAN message valid register 1, 2 (MSGVAL1, MSGVAL2)
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30.4.1 Overall Control Register
Overall control register controls the CAN protocol control and operation mode and provides status information.
■ Overall Control Register
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler extension register (BRPER)
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30.4.1.1 CAN Control Register (CTRLR)
CAN control register (CTRLR) controls the operating mode of the CAN controller.
■ Register Configuration
Figure 30.4-1 CAN Control Register (CTRLR)
CAN Control Register high byte
Address : Base + 00H
Read/write ⇒
Default value⇒
CAN Control Register low byte
Address : Base + 01H
Read/write ⇒
Default value⇒
15
14
13
12
11
10
9
8
res
res
res
res
res
res
res
res
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
7
4
3
2
1
0
CCE DAR
res
EIE
SIE
IE
Init
(R/W) (R/W) (R/W)
(0)
(0)
(0)
(R)
(0)
Test
⇐ Bit no.
CTRLRH
⇐ Bit no.
CTRLRL
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(1)
■ Register Function
[bit15 to bit8]
[bit7]
Reserved Bits
Always read "00000000B".
Set it to "00000000B" when writing.
Test
Test Mode Enable
0
1
Normal Operation.
Test Mode.
Note:
Set the Test bit to "1" when the INIT bit is "1".
[bit6]
CCE
0
1
[bit5]
DAR
0
1
(Notes)
Configuration Change Enable
The CPU has no write access to the Bit Timing Register.
The CPU has write access to the Bit Timing Register (while Init = 1)
Disable Automatic Retransmission
Automatic Retransmission of disturbed messages enabled.
Automatic Retransmission disabled.
Operations of TxRqst and NewDat bits of the message object are different in a mode in which DAR bit
has been set to "1" (see "30.5.1 Message Object" for details on the message object).
• When the frame transmission is started, TxRqst of the message object will be reset to "0", but
NewDat bit will remain set to "1".
• NewDat bit will be reset to "0" when the frame transmission ends successfully.
NewDat will remain set when the transmission loses the arbitration or when an error is detected. In
order to resume the transmission, TxRqst bit must be set to "1" by the CPU.
• If the DAR bit of the CAN control register (CTRLR) is changed from "0" to "1" during frame
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transmission (TxRqst = 1), the currently transmitted frame will be retransmitted. Therefore,
change the DAR bit when the INIT bit is "1".
• Only two messages are sent, if the host requests transmission of several messages at the same
time, when the DAR bit is set to "1" in CAN. While the TxRqst bit of any other message buffer
requested for transmission is reset, the transmission does not start. NewDat and IntPnd remain
unchanged. For the two transmitted messages, the TxRqst and NewDat bits are reset. And if TxIE
is enabled, IntPnd will be set.
[bit4]
res
[bit3]
EIE
0
1
[bit2]
SIE
0
1
[bit1]
[bit0]
Setting of interrupt code to the CAN interrupt register (INTR) is prohibited by a
change in BOff or EWarn bit of the CAN status register (STATR). [Initial value]
Setting of interrupt code to the CAN interrupt register (INTR) is allowed by a
change in BOff or EWarn bit of the CAN status register (STATR).
Status Change Interrupt request Enable
Setting of interrupt code to the CAN interrupt register (INTR) is prohibited by a
change in TxOk, RxOk or LEC bit of the CAN status register (STATR). [Initial value]
Setting of interrupt code to the CAN interrupt register (INTR) is allowed by a
change in TxOk, RxOk or LEC bit of the CAN status register (STATR).
A change that has occurred in TxOk, RxOk or LEC bit by a write from the CPU will
not be set to the CAN interrupt register (INTR).
IE
Module Interrupt request Enable
0
1
Prohibits the generation of interrupts. [Initial value]
Allows the generation of interrupts.
Init
Initialization
0
1
(Notes)
reserved bit
Always read "0".
Set it to "0" when writing.
Error Interrupt request Enable
Allows the operation of CAN controller..
initialized [Initial value]
• The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or
resetting Init. If the device goes busoff, it will set Init of its own accord, stopping all bus activities.
Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle
(129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the busoff
recovery sequence, the Error Management Counters will be reset.
• If Init bit is set to "1" then back to "0" during the bus-off recovery sequence, the sequence will be
performed again from the beginning (performed 129 times again with an 11 bit recessive counted as
1 bus-idle).
• Perform a write to the CAN bit timing register (BTR) after setting Init and CCE bits to "1".
• Transmission/reception will halt immediately when Init bit is set to "1" while transmission/reception
is in progress.
• When using low-power consumption mode (stop mode, clock mode), initialize CAN controller by
writing "1" to Init bit before the transition to low-power consumption mode is made.
• When changing the division ratio of the clock to be provided to the CAN interface using the CAN
prescaler register (BRTER), change the CAN prescaler after setting Init bit to "1".
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MB91460N series
30.4.1.2 CAN Status Register (STATR)
CAN status register (STATR) displays the CAN status and the state of the CAN bus.
■ Register Configuration
Figure 30.4-2 Status Register (STATR)
Status Register high byte
Address : Base + 02H
Read/write ⇒
Default value⇒
Status Register low byte
Address : Base + 03H
Read/write ⇒
Default value⇒
15
14
13
12
11
10
9
8
res
res
res
res
res
res
res
res
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
BOff EWarnEPassRxOK TxOK
(R)
(0)
(R)
(0)
(R)
(0)
LEC
⇐ Bit no.
STATRH
⇐ Bit no.
STATRL
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
■ Register Function
[bit15 to bit8]
[bit7]
Reserved Bits
Always read "0".
Set it to "0" when writing.
BOff
0
1
[bit6]
EWarn
0
1
[bit5]
EPass
0
1
[bit4]
RxOk
0
1
[bit3]
TxOk
0
1
440
Busoff Status
The CAN module is not busoff.
The CAN module is in busoff state.
Warning Status
Both error counters are below the error warning limit of 96.
At least one of the error counters in the EML has reached the error warning limit
of 96.
Error Passive
Transmission and reception counters are both less than 128 (error-active state)
[Initial value]
Reception counter is RP bit=1; Transmission counter is greater than 128 (error
passive state)
Received a Message Successfully
Message reception is error or bus-idle state [Initial value]
Message reception is normal
Transmitted a Message Successfully
Message transmission is error or bus-idle state [Initial value]
Message transmission is normal
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MB91460N series
[bit2 to bit0]
LEC
0
1
2
Last Error Code (Type of the last error to occur on the CAN bus)
No Error
Stuff Error
More than 5 equal bits in a sequence have occurred in a part of a
received message where this is not allowed.
A fixed format part of a received frame has the wrong format.
3
Form Error
AckError
4
Bit1Error
During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value "1"), but the monitored bus value was dominant.
5
Bit0Error
6
CRCError
7
Undetected
Indicates that recessive was detected in the message transmission
data even though dominant had been transmitted.
During bus recovery, it is set for every 11 bits of recessive that are
detected. Bus recovery sequence can be monitored by reading this
bit.
Indicates that the CRC data of the received message and the calculated CRC result did not match.
If the value read from LEC bit after "7" was written to it by the CPU is
still "7", it indicates that no transmission or reception has occurred
during this period (bus-idle state).
The message this CAN Core transmitted was not acknowledged by
another node.
LEC bit holds the code indicating the last error that occurred in the CAN bus. It will be set to "0H" when the
message transfer (reception/transmission) completes without error. Set undetected code "7H" by the CPU
to check for code updates.
- Status interrupt code ("8000H") will be set to the CAN interrupt register (INTR) when BOff or EWarn bit is
changed while EIE bit is "1" or when RxOk, TxOk or LEC bit is changed while SIE bit is "1".
- RxOk and TxOk bits set by the CAN controller will not be held as they will be updated by a write from the
CPU. When using RxOk and TxOk bits, clear them within (45 × BT) hours from when RxOk or TxOk bit
was set to "1". BT indicates 1-bit time.
- Do not write to CAN status register (STATR) when an interrupt due to a change in LEC bit occurs while
SIE bit is "1".
- Do not write to CAN status register (STATR) when an interrupt due to a change in LEC bit occurs while
SIE bit is "1".
- It does not occur by a change in the EPass bit or writing to the RxOk, TxOk or LEC bit from the CPU.
- Status interrupt (8000H) of the CAN interrupt register (INTR) will be cleared when CAN status register
(STATR) is read.
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30.4.1.3 Error Counter (ERRCNT)
CAN error counter (ERRCNT) indicates the passive display of reception error, reception error counter and
transmission error counter.
■ Register Configuration
Figure 30.4-3 Error Counter (ERRCNT)
Error Counter high byte
15
14
13
RP
Address : Base + 04H
Read/write ⇒
Default value⇒
Error Counter low byte
Address : Base + 05H
12
11
10
9
8
ERRCNTH
REC6 to 0
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
ERRCNTL
TEC7 to 0
Read/write ⇒
Default value⇒
⇐ Bit no.
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
■ Register Functions
[bit15]
RP
0
1
[bit14 to bit8] REC6 to 0
Receive Error Passive
Reception error counter is not in error passive state [Initial value]
The Receive Error Counter has reached the error passive level as defined in the
CAN Specification.
Receive Error Counter
Actual state of the Receive Error Counter. Values between 0 and 127.
Example: REC6-0 = 127, +8 due to a reception error results in RP = 1, and
REC6-0 = 127
REC6-0 = 126, +8 due to a reception error results in RP = 1, REC6-0
= 126
REC6-0 = 119, +8 due to a reception error results in RP = 0, REC6-0
= 127
[bit7 to bit0]
TEC7 to 0
Transmit Error Counter
Actual state of the Transmit Error Counter. Values between 0 and 255.
Example: TEC7-0 = 255, +8 due to a reception error results in Init = 1, TEC7-0
= 255
TEC7-0 = 254, +8 due to a reception error results in Init = 1, TEC7-0
= 254
TEC7-0 = 247, +8 due to a reception error results in Init = 0, TEC7-0
= 255
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30.4
MB91460N series
30.4.1.4 Bit Timing Register (BTR)
CAN bit timing register (BTR) sets the prescaler and bit timing.
■ Register Configuration
Figure 30.4-4 Bit Timing Register (BTR)
Bit Timing Register high byte
15
Address : Base + 06H
Read/write ⇒
Default value⇒
Bit Timing Register low byte
Address : Base + 07H
Read/write ⇒
Default value⇒
14
res
(R)
(0)
7
13
12
11
10
9
8
BTRH
TSeg1
TSeg2
⇐ Bit no.
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(1)
(0)
(0)
(0)
(1)
(1)
6
SJW
5
4
3
2
1
0
BRP
⇐ Bit no.
BTRL
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
Set the CAN bit timing register and the CAN prescaler extension register when the CCE and Init bits are set to
"1".
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■ Register Function
[bit15]
res
[bit14 to bit12]
TSeg2
Reserved bit
Always read "0".
Set it to "0 when writing.
The time segment after the sample point
The valid value range is from 0 to 7. The value of TSeg2+1 will be time segment 2.
Time segment 2 corresponds to phase buffer segment (PHASE_SEG2) in
the CAN specification.
[bit11 to bit8]
TSeg1
The time segment before the sample point
The valid value range is from 1 to 15. It cannot be set to "0". The value of
TSeg1+1 will be time segment 1.
Time segment 1 corresponds to propagation segment (PROP_SEG) and
phase buffer segment 1 (PHASE_SEG1) in the CAN specification.
[bit7, bit6]
SJW
(Re)Synchronization Jump Width
The valid value range is from 0 to 3. The value of SJW+1 will be the resynchronization jump width.
[bit5 to bit0]
BRP
Baud Rate Prescaler
The valid value range is from 0 to 63. The value of BRP+1 will be baud rate
prescaler.
Basic unit time (tq) of the CAN controller is determined by dividing the system clock (fsys).
(Note)
444
With a module clock CLKCAN of 8MHz, the reset value of 2301H configures the CAN for a bit rate of
500 kbps. The registers are only writable if bits CCE and Init in the CAN Control Register are set.
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Chapter 30 CAN Controller
30.4
MB91460N series
30.4.1.5 CAN Interrupt Register (INTR)
CAN interrupt register (INTR) displays the message interrupt and status interrupt codes.
■ Register Configuration
Figure 30.4-5 CAN Interrupt Register (INTR)
INTR high byte
Address:
bit15
bit14
bit13
Base+08H
R
R
R
bit7
bit6
bit5
bit12
bit11
IntId15 to IntId8
R
R
bit10
bit9
bit8
Initial value
00000000B
R
R
R
bit2
bit1
bit0
INTR low byte
Address:
Base+09H
R
R
R
bit4
bit3
IntId7 to IntId0
R
R
Initial value
00000000B
R
R
R
■ Register Function
• 32 message buffer CAN
IntId
Function
0000H
No interrupt
0001H to 0020H
Message interrupt code
0021H to 7FFFH
Unused
8000H
Status interrupt code
8001H to FFFFH
Unused
• 128 message buffer CAN
IntId
Function
0000H
No interrupt
0001H to 0080H
Message interrupt code
0081H to 7FFFH
Unused
8000H
Status interrupt code
8001H to FFFFH
Unused
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If 2 or more interrupt codes are pending, CAN interrupt register (INTR) will indicate the high priority
interrupt code. When a high priority interrupt code is generated, CAN interrupt register (INTR) will be
updated by the high priority interrupt code even if interrupt code is already set in the register.
Status interrupt code ("8000H") has the highest priority, followed by message interrupts ("0001H", "0002H",
"0003H", ……, "0020H").
Interrupt signal to the CPU will become active when IE bit of the CAN control register (CTRLR) is set to "1"
while IntId bit is other than "0000H". Interrupt signal will become inactive when the value of IntId becomes
"0000H" (interrupt factor is reset) or when IE bit of the CAN control register (CTRLR) is reset to "0".
As for the targeted message object (see "30.5.1 Message Object" for details of message object), message
interrupt code will be cleared when IntPnd bit is cleared to "0".
Status interrupt code will be cleared when CAN status register (STATR) is read.
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30.4
MB91460N series
30.4.1.6 CAN Test Register (TESTR)
CAN test register (TESTR) sets the test mode and monitors the RX pin. See "30.5.7 Test Mode" for details of
its operation.
■ Register Configuration
Figure 30.4-6 Test Register (TESTR)
Test Register high byte
15
14
13
12
11
10
9
8
res
res
res
res
res
res
res
res
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Rx
Tx1
Tx0 LBack Silent Basic
res
res
(R) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(R)
(0)
(R)
(0)
Address : Base + 0AH
Read/write ⇒
Default value⇒
Test Register low byte
Address : Base + 0BH
Read/write ⇒
Default value⇒
⇐ Bit no.
TESTRH
⇐ Bit no.
TESTRL
Initial value of Rx in bit7 (r) displays the level on the CAN bus.
Write to the CAN test register (TESTR) after setting the Test bit of the CAN control register (CTRLR) to "1".
Test mode is enabled when the Test bit of the CAN control register is "1". If the Test bit of the CAN control
register is changed to "0" in the middle of test mode, it will change to normal mode.
■ Register Function
[bit15 to bit8]
res
Reserved bits
Always read "00000000B".
Set it to "00000000B" when writing.
[bit7]
Rx
0
1
[bit6, bit5]
Tx1,0
Monitors the actual value of the RX Pin
Indicates that CAN bus is dominant.
Indicates that CAN bus is recessive.
Control of TX pin
00
Normal operation [Initial value]
01
Outputs a sampling point to the TX pin.
10
Outputs dominant to the TX pin.
11
Outputs recessive to the TX pin.
Message cannot be transmitted if Tx bit is set to other than "00B".
[bit4]
LBack
0
1
CM44-10149-1E
Loop Back Mode
Prohibits the loopback mode. [Initial value]
Allows the loopback mode.
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[bit3]
Silent
0
1
[bit2]
[bit1, bit0]
Basic
MB91460N series
Silent Mode
Prohibits the silent mode. [Initial value]
Allows the silent mode.
Basic Mode
0
Prohibits the basic mode. [Initial value]
Allows the basic mode.
1
IF1 register will be used as a transmission message, and IF 2 register will be used
as a reception message.
res
Reserved Bits
Always read "00B".
Set it to "00"B when writing.
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30.4.1.7 Prescaler Extension Register (BRPER)
CAN prescaler extension register (BRPER) extends the prescaler to be used in the CAN controller by
combining it with the prescaler set in the CAN bit timing.
■ Register Configuration
Figure 30.4-7 Prescaler Extension Register (BRPER)
BRP Extension Register high byte
Address : Base + 0CH
Read/write ⇒
Default value⇒
BRP Extension Register low byte
Address : Base + 0DH
Read/write ⇒
Default value⇒
15
14
13
12
11
10
9
8
res
res
res
res
res
res
res
res
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
res
res
res
res
BRPE
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
⇐ Bit no.
BRPERH
⇐ Bit no.
BRPERL
■ Register Function
[bit15 to bit4]
res
[bit3 to bit0]
BRPE
Reserved Bits
Always read "00000000 0000B".
Set it to "00000000 0000B" when writing.
Baud Rate Prescaler Extension
By programming BRPE the Baud Rate Prescaler can be extended to values up to
1023. The actual interpretation by the hardware is that one more than the value
programmed by BRPE (MSBs) and BRP (LSBs) is used.
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30.4.2 Message Interface Register Sets
There are two sets of Interface Registers which are used to control the CPU access to the Message RAM. The
Interface Registers avoid conflicts between CPU access to the Message RAM and CAN message reception
and transmission by buffering the data to be transferred. A complete Message Object (see chapter 30.4.3
“Message Object in the Message Memory” on page 461.) or parts of the Message Object may be transferred
between the Message RAM and the IFx Message Buffer registers in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic). They can be used the
way that one set of registers is used for data transfer to the Message RAM while the other set of registers is
used for the data transfer from the Message RAM, allowing both processes to be interrupted by each other.
Figure 30.4-8 gives an overview of the two Interface Register sets.
Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command
Registers. The Command Mask Register specifies the direction of the data transfer and which parts of a
Message Object will be transferred. The Command Request Register is used to select a Message Object in
the Message RAM as target or source for the transfer and to start the action specified in the Command Mask
Register.
Figure 30.4-8 IF1 and IF2 Message Interface Register Sets
450
Address
IF1 Register Set
Address
IF2 Register Set
CAN Base + 10H
IF1 Command Request
CAN Base + 40H
IF2 Command Request
CAN Base + 12H
IF1 Command Mask
CAN Base + 42H
IF2 Command Mask
CAN Base + 14H
IF1 Mask 2
CAN Base + 44H
IF2 Mask 2
CAN Base + 16H
IF1 Mask 1
CAN Base + 46H
IF2 Mask 1
CAN Base + 18H
IF1 Arbitration 2
CAN Base + 48H
IF2 Arbitration 2
CAN Base + 1AH
IF1 Arbitration 1
CAN Base + 4AH
IF2 Arbitration 1
CAN Base + 1CH
IF1 Message Control
CAN Base + 4CH
IF2 Message Control
CAN Base + 20H
CAN Base + 32H
IF1 Data A1
CAN Base + 50H
CAN Base + 62H
IF2 Data A1
CAN Base + 22H
CAN Base + 30H
IF1 Data A2
CAN Base + 52H
CAN Base + 60H
IF2 Data A2
CAN Base + 24H
CAN Base + 36H
IF1 Data B1
CAN Base + 54H
CAN Base + 66H
IF2 Data B1
CAN Base + 26H
CAN Base + 34H
IF1 Data B2
CAN Base + 56H
CAN Base + 64H
IF2 Data B2
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30.4
MB91460N series
30.4.2.1 IFx Command Request Registers (IFxCREQ)
IFx command request register (IFxCREQ) selects a message number in message RAM and transfers data
between message RAM and the message buffer register. In test basic mode, IF1 is used for transmission
control and IF2 is used for reception control.
■ Register Configuration
Figure 30.4-9 IFx Command Request Registers (IFxCREQ)
IFx Command Request Register high byte
14
13
12
11
10
9
8
BUSY res
res
res
res
res
res
res
Read/write ⇒ (R/(W)) (R)
(0)
(0)
Default value⇒
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
Address : Base + 10H & Base + 40H
IFx Command Request Register low byte
Address : Base + 11H & Base + 41H
Read/write ⇒
Default value⇒
15
7
6
Message Number
⇐ Bit no.
IFxCREQH
⇐ Bit no.
IFxCREQL
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
■ Register Function
When a message number is written to the IFx command request register (IFxCREQ), message transfer
between message RAM and the message buffer register (mask, arbitration, message control and data
registers) will be started immediately. This write operation will set BUSY bit to "1", indicating that message
transfer is currently being processed. BUSY bit will be reset to "0" when the transfer ends.
When an access to the message interface register from the CPU occurs while BUSY bit is "1", CPU will wait
until BUSY bit becomes "0" (3 to 6 clock cycle periods after a write to the command request register).
BUSY bit is used differently in test basic mode. IF1 command request register is used as a transmission
message, and instructs message transmission to be started by setting BUSY bit to "1". BUSY bit will be reset
to "0" when the message transfer ends successfully. Furthermore, message transfer can be aborted at any
time by resetting BUSY bit to "0".
IF2 command request register is used as a reception message, and stores the received message to the IF2
message interface register by setting BUSY bit to "1".
[bit15]
Busy Flag
Other than test basic mode
Indicates that there is no data transfer between the message interface register and
0
message RAM. [Initial value]
Indicates that data transfer between the message interface register and message
1
RAM is currently being processed.
Test basic mode
IF1 command request register
0
Prohibits message transmission.
1
Allows message transmission.
IF2 command request register
0
Prohibits message reception.
1
Allows message reception.
BUSY bit is readable and writable. Whatever value written to this bit will not affect the operation unless while
in test basic mode (see "30.5.7 Test Mode" for details of basic mode).
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[bit14 to bit5]
res
[bit4 to bit0]
MB91460N series
Reserved Bits
Always read "0000000000B".
Set it to "0000000000B" when writing.
Message Number (for 32 message buffer CANs)
00H
Setting is prohibited.
If set, it will be interpreted as "20H" and "20H" will be read.
01H to 20H
Sets the message number to be processed.
21H to 3FH
Setting is prohibited.
If set, it will be interpreted as "01H" to "1FH" and the interpreted value will be read.
[bit4 to bit0]
Message Number (for 128 message buffer CANs)
00H
01H to 80H
81H to FFH
Setting is prohibited.
If set, it will be interpreted as "20H" and "20H" will be read.
Sets the message number to be processed.
Setting is prohibited.
If set, it will be interpreted as "01H" to "7FH" and the interpreted value will be read.
(Note)
Note: The Busy Flag can only be used in BASIC mode (see chapter ). When using the Message
RAM (BASIC=0) the hardware interface controls the access for read and write and this flag is always
read as "0".
(Note)
When a Message Number that is not valid is written into the Command Request Register, the
Message Number will be transformed into a valid value and that Message Object will be transferred.
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30.4
MB91460N series
30.4.2.2 IFx Command Mask Register (IFxCMSK)
The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx
Message Buffer Registers are source or target of the data transfer.
■ Register Configuration
Figure 30.4-10 IFx Command Mask Register (IFxCMSK)
IFx Command Mask Register high byte 15
14
13
12
11
10
9
8
res
res
res
res
res
res
res
res
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Address : Base + 12H & Base + 42H
Read/write ⇒
Default value⇒
IFx Command Mask Register low byte
Address : Base + 13H & Base + 43H
Read/write ⇒
Default value⇒
7
6
WR/RD Mask
(R/W) (R/W)
(0)
(0)
⇐ Bit no.
IFxCMSKH
1
2
0 ⇐ Bit no.
TxReq/
Arb Control CIP NewDat Data A Data B IFxCMSKL
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
5
4
3
■ Register functions
[bit 15 to bit8] res: Reserved bits
"00000000B" will be read from these bits.
Set it to "00000000B" when writing.
[bit7] WR/RD: Write/Read control bit
WR/RD
Function
0
Indicates that data will be read from message RAM.A read from message RAM is performed by
a write to the IFx command request register. Data that is read from message RAM depends on
the settings of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A and Data B bits. [Initial value]
1
Indicates that data will be written to message RAM. A write to message RAM is performed by a
write to the IFx command request register. Data that is written to message RAM depends on the
settings of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A and Data B bits.
Data on message RAM will be undefined after the reset. Reading data from message RAM is prohibited while
the data on message RAM is in undefined state.
Meanings of bit6 to bit0 of the IFx command mask register differ depending on the transfer direction (WR/RD
bit) setting.
● If the transfer direction is write (WR/RD=1)
[bit6] Mask: Mask data update bit
Mask
Function
0
Does not update the mask data (ID mask + MDir + MXtd) of the message object [Initial value]
1
Updates the mask data (ID mask + MDir + MXtd) of the message object
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[bit5] Arb: Arbitration data update bit
Arb
Function
0
Does not update the arbitration data (ID + Dir + Xtd + MsgVal) of the message object [Initial
value]
1
Updates the arbitration data (ID + Dir + Xtd + MsgVal) of the message object
[bit4] Control: Control data update bit
Control
Function
0
Does not update the control data (IFx message control register) of the message object
[Initial value]
1
Updates the control data (IFx message control register) of the message object
[bit3] CIP: Interrupt clear bit
Setting this bit to "0" or "1" will not affect the operation of the CAN controller.
[bit2] TxRqst/NewDat: Message transmission request bit
TxRqst/NewDat
Function
0
Sets the message object and TxRqst bit of the CAN transmission request register to "0"
[Initial value]
1
Sets the message object and TxRqst bit of the CAN transmission request register to "1"
(Transmission request)
Setting of TxRqst bit of the IFx message control register will be disabled when TxRqst/NewDat bit of the IFx
command mask register is set to "1".
[bit1] Data A: Data 0 to 3 update bit
Data A
Function
0
Does not update data 0 to 3 of the message object [Initial value]
1
Updates data 0 to 3 of the message object
[bit0] Data B: Data 4 to 7 update bit
Data B
Function
0
Does not update data 4 to 7 of the message object [Initial value]
1
Updates data 4 to 7 of the message object
See "30.4.3 Message Object in the Message Memory".
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● If the transfer direction is read (WR/RD=0)
IntPnd and NewDat bits can be reset to "0" by a write access to the message object. However, IntPnd and
NewDat bits before they have been reset by a read access will be stored to the IFx message control
register.
They will be disabled in test basic mode.
[bit6] Mask: Mask data update bit
Mask
Function
0
Does not transfer data (ID mask + MDir + MXtd ) to IFx mask register 1, 2 from the message
object [Initial value]
1
Transfers data (ID mask + MDir + MXtd ) to IFx mask register 1, 2 from the message object
[bit5] Arb: Arbitration data update bit
Arb
Function
0
Does not transfer data (ID+ Dir + Xtd + MsgVal) to IFx arbitration 1, 2 from the message object
[Initial value]
1
Transfers data (ID+ Dir + Xtd + MsgVal) to IFx arbitration 1, 2 from the message object
[bit4] Control: Control data update bit
Control
Function
0
Does not transfer data to IFx message control register from the message object [Initial value]
1
Transfers data to the IFx message control register from the message object
[bit3] CIP: Interrupt clear bit
CIP
Function
0
Holds the message object and IntPnd bit of the CAN interrupt pending register [Initial value]
1
Clears the message object and IntPnd bit of the CAN interrupt pending register to "0"
[bit2] TxRqst/NewDat: Data update bit
TxRqst/NewDat
Function
0
Holds the message object and NewDat bit of the CAN data update register [Initial value]
1
Clears the message object and NewDat bit of the CAN data update register to "0"
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[bit1] Data A: Data 0 to 3 update bit
Data A
Function
0
Holds the message object and the data of the CAN data register A1 and A2 [Initial value]
1
Updates the message object and the data of the CAN data register A1 and A2
[bit0] Data B: Data 4 to 7 update bit
Data B
Function
0
Holds the message object and the data of the CAN data register B1 and B2 [Initial value]
1
Updates the message object and the data of the CAN data register B1 and B2
See "30.4.3 Message Object in the Message Memory".
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30.4
MB91460N series
30.4.2.3 IFx Mask Register 1, 2 (IFxMSK1, IFxMSK2)
IFx mask register (IFxMSK1, IFxMSK2) is used to write/read the message object mask data of message RAM.
The set mask data will be disabled in test basic mode.
See "30.5.1 Message Object" for details of the function of each bit.
■ Register Configuration
Figure 30.4-11 IFx Mask 2 Register (IFxMSK2)
IFx Mask 2 Register high byte
15
14
13
12
11
10
9
8
res
Msk28 to 24
Read/write ⇒ (R/W) (R/W)
(1)
(1)
Default value⇒
(R)
(1)
(R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
IFx Mask 2 Register low byte
Address : Base + 15H & Base + 45H
Read/write ⇒
Default value⇒
7
6
5
4
3
2
⇐ Bit no.
IFxMSK2H
MXtd MDir
Address : Base + 14H & Base + 44H
1
0
⇐ Bit no.
IFxMSK2L
Msk23 to 16
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Figure 30.4-12 IFx Mask 1 Register (IFxMSK1)
IFx Mask 1 Register high byte
15
14
13
12
11
10
9
8
IFxMSK1H
Msk15 to 8
Address : Base + 16H & Base + 46H
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Default value⇒
IFx Mask 1 Register low byte
Address : Base + 17H & Base + 47H
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
0
Msk7 to 0
⇐ Bit no.
IFxMSK1L
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
See "30.5.1 Message Object" for descriptions of the IFx mask register bits.
"1" will be read from the reserved bit (bit 13 of IFx mask register 2). Set it to "1" when writing.
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30.4.2.4 IFxArbitration Register 1, 2 (IFxARB1, IFxARB2)
IFx arbitration register (IFxARB1, IFxARB2) is used to write/read the message object arbitration data of
message RAM. It will be disabled in test basic mode.
See "30.5.1 Message Object" for details of the function of each bit.
■ Register Configuration
Figure 30.4-13 IFx Arbitration 2 Register (IFxARB2)
IFx Arbitration 2 Register high byte
Address : Base + 18H & Base + 48H
14
13
MsgVal Xtd
15
Dir
12
11
10
9
⇐ Bit no.
8
IFxARB2H
ID28 to 24
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default value⇒
IFx Arbitration 2 Register low byte
Address : Base + 19H & Base + 49H
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
0
⇐ Bit no.
IFxARB2L
ID23 to 16
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Figure 30.4-14 IFx Arbitration 1 Register (IFxARB1)
IFx Arbitration 1 Register high byte
15
14
13
12
11
10
9
8
IFxARB1H
ID15 to 8
Address : Base + 1AH & Base + 4AH
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default value⇒
IFx Arbitration 1 Register low byte
Address : Base + 1BH & Base + 4BH
Read/write ⇒
Default value⇒
7
6
5
4
3
2
1
0
ID7 to 0
⇐ Bit no.
IFxARB1L
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
See "30.4.3 Message Object in the Message Memory" for the bit explanation of the IFx arbitration register.
The TxRqst bit of the message object and the CAN transmission request register is not cleared to "0" though
the TxOk bit of the CAN status register becomes "1" when the transmission is completed when the MsgVal bit
of the message object is cleared to "0" while transmitting. Clear the TxRqst bit to "0" according to the message
interface register.
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30.4.2.5 IFx Message Control Register (IFxMCTR)
IFx message control register (IFxMCTR) is used to write/read the message object control data of message
RAM. Furthermore, IF1 message control register will be disabled in test basic mode. NewDat and MsgLst of
the IF2 message control register will operate normally; and DLC bit will display DLC of the received message.
Other control bits will operate as disabled ("0").
See "30.5.1 Message Object" for details of the function of each bit.
■ Register Configuration
Figure 30.4-15 IFx Message Control Register (IFxMCTR)
IFx Message Control Register high byte 15
Address : Base + 1CH & Base + 4CH
14
13
12
NewDat MsgLst IntPnd UMask
11
10
TxIE
RxIE
9
8
⇐ Bit no.
IFxMCTRH
RmtEn TxRqst
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Default value⇒
IFx Message Control Register low byte
Address : Base + 1DH & Base + 4DH
Read/write ⇒
Default value⇒
7
EoB
6
5
4
res
res
res
(R/W) (R)
(0)
(0)
(R)
(0)
(R)
(0)
3
2
1
0
⇐ Bit no.
DLC3 to 0
IFxMCTRL
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
See "30.5.1 Message Object" for descriptions of the IFx message control register bits.
TxRqst, NewDat and IntPnd bits operate as described below, depending on the WR/RD bit setting of the IFx
command mask register (IFxCMSK):
● If the transfer direction is "write" (IFx command mask register (IFxCMSK): WR/RD=1)
TxRqst bit of this register will only be enabled when TxRqst/NewDat in the IFx command mask register
(IFxCMSK) is set to "0".
● If the transfer direction is "read" (IFx command mask register (IFxCMSK): WR/RD=0)
IntPnd bit before it has been reset will be set to this register when the message object and IntPnd bit of the
CAN interrupt pending register (INTPND) are reset by a write operation to the IFx command request
register (IFxCREQ) after setting CIP bit of the IFx command mask register (IFxCMSK) to "1".
NewDat bit before it has been reset will be set to this register when the message object and NewDat bit of
the CAN data update register are reset by a write operation to the IFx command request register
(IFxCREQ) after setting TxRqst/NewDat bit of the IFx command mask register (IFxCMSK) to "1".
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30.4.2.6 IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
IFx data register (IFxDTA1, IFxDTA2, IFxDTAB1, IFxDTB2) is used to write/read the message object
transmission/reception data of message RAM. It is only used for transmitting/receiving data frames, and not
for transmitting/receiving remote frames.
■ Register Configuration
IFx Message Data A1 (addresses 20H & 50H)
addr+0
addr+1
Data(0)
Data(1)
IFx Message Data A2 (addresses 22H & 52H)
IFx Message Data B1 (addresses 24H & 54H)
Data(4)
Data(3)
Data(2)
Data(3)
Data(6)
Data(7)
Data(1)
Data(0)
Data(5)
Data(4)
Data(2)
IFx Message Data A1 (addresses 32H & 62H)
IFx Message Data B2 (addresses 34H & 64H)
addr+3
Data(5)
IFx Message Data B2 (addresses 26H & 56H)
IFx Message Data A2 (addresses 30H & 60H)
addr+2
Data(7)
Data(6)
IFx Message Data B1 (addresses 36H & 66H)
Figure 30.4-16 IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
IFxDTA1, IFxDTA2 IFxDTB1, IFxDTB2
bit15
bit7
R/W
bit14
bit6
R/W
bit13
bit5
bit12
bit4
bit11
bit3
R/W
Data
R/W R/W
bit10
bit2
bit9
bit1
bit8
bit0
Initial value
00000000B
R/W
R/W
R/W
■ Register Function
● Transmission message data setting
The set data starts from MSB (bit7, bit15) and is transmitted in the order of Data(0), Data(1), ... , Data(7).
● Reception message data
Reception message data starts from MSB (bit7, bit15) and is stored in the order of Data(0), Data(1), ... ,
Data(7).
If the reception message data is less than 8 bytes, the remaining bytes of the data register will be
undefined.
Data transfer to the message object will be in units of 4 bytes of Data A or Data B. It is therefore not
possible to update only a part of the 4 byte data.
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30.4.3 Message Object in the Message Memory
There are 32 Message Objects (up to 128 depending on the implementation) in the Message RAM. To avoid
conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.
Table 30.4-1 gives an overview of the two structures of a Message Object.
■ Message object configuration
Table 30.4-1 Configuration of the Message Object
UMask
Msk28 to
Msk0
MsgVal
ID28 to ID0
MXtd MDir
Xtd
Dir
EoB
DLC3 to
DLC0
NewDat
MsgLst RxIE
TxIE IntPnd RmtEn TxRqst
Data0 Data1 Data2 Data3 Data4 Data5
Data6
Data7
<Note>
Message object will not be initialized by Init bit of CAN control register or hardware reset. In the case of
hardware reset, after its release, initialize message RAM by the CPU or set MsgVal of message RAM to
"0".
■ Message object functions
When transmitting a message, ID28 to ID0, Xtd and Dir bits will be used as the message ID and type. When
receiving a message, Msk28 to Msk0, MXtd and MDir bits will be used in the acceptance filter.
ID, IDE, RTR, DLC and DATA of the data frame or remote frame that has passed the acceptance filter will be
stored to ID28-ID0, Xtd, Dir, DLC3-DLC0 and Data7-Data0 of the message object. Xtd indicates whether the
message object is an extension frame or standard frame. A 29-bit ID (extension frame) will be received if Xtd is "1",
and an 11-bit ID (standard frame) will be received if Xtd is "0".
If the received data frame or remote frame matches one or more message objects, it will be stored to the
lowest matched message number. See "■ Acceptance Filtering of Received Messages" in "30.5.3 Message
Reception Operation" for details.
MsgVal: Valid message bit
MsgVal
Function
0
Message object is disabled.
Message transmission/reception will not be performed.
1
Message object is enabled.
Message transmission/reception will become possible.
• Reset MsgVal bit of all unused message objects by the CPU during the initialization process before resetting
Init bit of the CAN control register to "0".
• Always reset MsgVal bit to "0" before changing ID28 to ID0, Xtd, Dir and DLC3 to DLC0 or if message object
is not required.
• If MsgVal bit is cleared to "0" while the transmission is in progress, TxOk bit of the CAN status register will
become "1" as soon as the transmission ends. However, the message object and TxRqst bit of the CAN
transmission request register will not be cleared to "0" Clear TxRqst bit to "0" by the message interface
register.
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UMask: Acceptance mask enable bit
UMask
Function
0
Does not use Msk28 to Msk0, MXtd and MDir.
1
Uses Msk28 to Msk0, MXtd and MDir.
• Change UMask bit while Init bit of the CAN control register is "1" or while MsgVal bit is "0".
• When Dir bit is "1" and RmtEn bit is "0", it will operate differently depending on the UMask setting.
- If UMask is "1", TxRqst bit will be reset to "0" when the remote frame is received through the acceptance
filter. At this time, the received ID, IDE, RTR and DLC will be stored to the message object, NewDat bit
will be set to "1", and the data will remain unchanged (treated as a data frame).
- If UMask is "0", TxRqst bit will remain unchanged by the remote frame reception; and it will ignore the
remote frame.
ID28 to ID0: Message ID
ID
Function
ID28 to ID0
Instructs a 29-bit ID (Extended frame).
ID28 to ID18
Instructs an 11-bit ID (Standard frame).
Msk28 to Msk0: ID mask
Msk
Function
0
Mask of the bit corresponding to the message object ID exists.
1
Mask of the bit corresponding to the message object ID does not exist.
If an 11-bit ID (standard frame) is set to the message object, ID of the received data frame will be written to
ID28 to ID18. Msk28 to Msk18 will be used as ID mask.
Xtd: Extended ID enable bit
Xtd
Function
0
Message object is an 11-bit ID (Standard frame).
1
Message object is a 29-bit ID (Extended frame).
MXtd: Extended ID mask bit
462
MXtd
Function
0
Does not compare the value that has been set to Xtd of the message object with the IDE value
of the received frame. It will determine whether to compare it as a standard frame ID or
extension frame ID, according to IDE bit of the received frame.
1
Compares the value that has been set to Xtd of the message object with the IDE value of the
received frame.
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<Note>
If an 11 bit ID (standard frame) is set to the message object, ID of the received data frame will be written to
from ID28 to ID18. Msk28 to Msk18 will be used as ID mask.
Dir: Message direction bit
Dir
Function
0
Indicates the reception direction.
The remote frame will be transmitted when TxRqst is set to "1", and the data frame that has
passed through the acceptance filter will be received when it is set to "0".
1
Indicates the transmission direction.
Data frame will be transmitted when TxRqst is set to "1". If TxRqst is "0" and RmtEn is set to "1",
CAN controller sets its TxRqst to "1" by receiving the remote frame that has passed through
the acceptance filter.
MDir: Message direction mask bit
MDir
Function
0
Mask of the message direction bit (Dir) in the acceptance filter exists.
1
Mask of the message direction bit (Dir) in the acceptance filter does not exist.
<Note>
Always set MDir bit to "1".
EoB: End of Buffer bit (see "30.5.4 FIFO Buffer Function" for details)
EoB
Function
0
Message object is used as FIFO buffer and is not the final message.
1
Single message object or the final message object of FIFO buffer.
EoB bit is used to configure the FIFO buffer of 2 to 32 messages.
Always set EoB bit to "1" in the case of a single message object (when FIFO is not used).
NewDat: Data update bit
NewDat
Function
0
Valid data does not exist.
1
Valid data exists.
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MsgLst: Message lost
MsgLst
Function
0
No message lost occurs.
1
Message lost occurs.
MsgLst bit is only enabled when Dir bit is "0" (reception direction).
RxIE: Reception interrupt flag enable bit
RxIE
Function
0
IntPnd remains unchanged after successful frame reception.
1
IntPnd is set to "1" after successful frame reception.
TxIE: Transmission interrupt flag enable bit
TxIE
Function
0
IntPnd remains unchanged after successful frame transmission.
1
IntPnd is set to "1" after successful frame transmission.
IntPnd: Interrupt pending bit
IntPnd
Function
0
No interrupt factor
1
Interrupt factor
If no other high priority interrupt exists, IntId bit of the CAN interrupt register will indicate this
message object.
RmtEn: Remote enable
RmtEn
Function
0
TxRqst remains unchanged by remote frame reception.
1
TxRqst will be set to "1" if a remote frame is received while Dir bit is "1".
When Dir bit is "1" and RmtEn bit is "0", it will operate differently depending on the UMask setting.
- If UMask is "1", TxRqst bit will be reset to "0" when the remote frame is received through the acceptance
filter. At this time, the received ID, IDE, RTR and DLC will be stored to the message object, NewDat bit
will be set to "1", and the data will remain unchanged (treated as a data frame).
- If UMask is "0", TxRqst bit will remain unchanged by the remote frame reception; and it will ignore the
remote frame.
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TxRqst: Transmission request bit
TxRqst
Function
0
Transmission is in idle state (transmission is neither in progress nor in wait state).
1
Transmission is in progress or in wait state.
DLC3 to DLC0: Data length code
DLC3 to DLC0
Function
0 to 8
Data frame length is 0 to 8 bytes.
9 to 15
Setting prohibited.
If set, it will be 8 bytes in length.
The received DLC will be stored to DLC bit when the data frame is received.
Data0 to Data7: Data 0 to 7
Data0 to Data7
Function
Data 0
First data byte of the CAN data frame
Data 1
Second data byte of the CAN data frame
Data 2
Third data byte of the CAN data frame
Data 3
Fourth data byte of the CAN data frame
Data 4
Fifth data byte of the CAN data frame
Data 5
Sixth data byte of the CAN data frame
Data 6
Seventh data byte of the CAN data frame
Data 7
Eighth data byte of the CAN data frame
• Serial output to the CAN bus is output from MSB (bit7 or bit15).
• If the received message data is less than 8 bytes, the remaining byte data of the data register will be
undefined.
• Data transfer to the message object will be in units of 4 bytes of Data A or Data B. It is therefore not possible
to update only a part of the 4 byte data.
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30.4.4 Message Handler Registers
All Message Handler registers are read-only. Their contents (TxRqst, NewDat, IntPnd, and MsgVal bits of
each Message Object and the Interrupt Identifier) is status information provided by the Message Handler FSM.
■ Message Handler Registers
• CAN transmission request register 1, 2 (TREQR1, TREQR2)
• CAN data update register 1, 2 (NEWDT1, NEWDT2)
• CAN interrupt pending register 1, 2 (INTPND1, INTPND2)
• CAN message valid register 1, 2 (MSGVAL1, MSGVAL2)
30.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2)
CAN transmission request register (TREQR1, TREQR2) displays the TxRqst bit of all message objects. It is possible to
check transmission request of which message object is currently pending by reading TxRqst bit.
■ Register Configuration
Figure 30.4-17 Transmission Request Register 2 (TREQR2)
Transmission Req Register 2 high byte
15
14
Transmission Req Register 2 low byte
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
TREQR2L
TxRqst24 to 17
(R)
(0)
⇐ Bit no.
TREQR2H
(R)
(0)
Address : Base + 81H
Read/write ⇒
Default value⇒
12
TxRqst32 to 25
Address : Base + 80H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
Figure 30.4-18 Transmission Request Register 1 (TREQR1)
Transmission Req Register 1 high byte
15
14
Transmission Req Register 1 low byte
466
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
TREQR1L
TxRqst8 to 1
(R)
(0)
⇐ Bit no.
TREQR1H
(R)
(0)
Address : Base + 83H
Read/write ⇒
Default value⇒
12
TxRqst16 to 9
Address : Base + 82H
Read/write ⇒
Default value⇒
13
(R)
(0)
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(R)
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■ Register functions
TxRqst32 to TxRqst1: Transmission request bit
TxRqst32 to TxRqst1
Function
0
Transmission is in idle state (transmission is neither in progress nor in wait state).
1
Transmission is in progress or in wait state.
The following shows the set/reset conditions of the TxRqst bit:
• Set conditions
- It can be set to TxRqst of a specific object by setting WR/RD to "1" and TxRqst to "1" in the IFx command
mask register and writing to the IFx command request register.
- If WR/RD is set to "1", TxRqst is set to "0" and Control is set to "1" in the IFx command mask register and
TxRqst of the IFx message control register is set to "0", it can be set to TxRqst of a specific object by
writing to the IFx command request register.
- It is set by setting Dir and RmtEn bits to "1" and receiving the remote frame that has passed through the
acceptance filter.
• Reset conditions
- If WR/RD is set to "1", TxRqst is set to "0" and Control is set to "1" in the IFx command mask register and
TxRqst of the IFx message control register is set to "0", TxRqst of a specific object can be reset by
writing to the IFx command request register.
- It will be reset when the frame transmission ends successfully.
- If Dir bit is "1", RmtEn is "0" and UMask is "1", it is reset by receiving the remote frame that has passed
through the acceptance filter.
<Notes>
• If TxRqst is set to "1" and then set to "0" to stop the transmission in the case where the lowest priority
message buffer is being used for the transmission, the message may not be transmitted when TxRqst is set
to "1" again until one of the following events occurs (depends on the timing).
- A valid message flows through the CAN bus
- A transmission request is issued to another message buffer
- C_CAN is initialized by INIT bit
If it will become necessary to stop the transmission on the system, either avoid using the lowest priority
message buffer for the transmission, or set TxRqst to "1" again after generating one of the above events.
• If the message object with ID28-0, DLC3-0, Xtd and Data7-0 is changed while TxRqst bit is set to "1", the
message object before and after the change may get transmitted in mixture or the message object after the
change may not be transmitted at all. Therefore, change them while TxRqst bit is "0".
If more than 32 message buffers are implemented, the following table gives an overview about the additional
flags:
Table 30.4-2 Additional flags when more than 32 message buffers exist
addr+0
addr+1
addr+2
addr+3
TREQR 4 & 3
TxRqst 64 to 33 (address 0x84)
TxRqst64 to 57
TxRqst56 to 49
TxRqst48 to 41
TxRqst40 to 33
TREQR 6 & 5
TxRqst 96 to 65 (address 0x88)
TxRqst96 to 89
TxRqst88 to 81
TxRqst80 to 73
TxRqst72 to 65
TREQR 8 & 7 TxRqst 128 to 97 (address 0x8C) TxRqst128 to 121 TxRqst120 to 113 TxRqst112 to 105 TxRqst104 to 97
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30.4.4.2 CAN New Data Registers (NEWDT1, NEWDT2)
CAN data update register (NEWDT1, NEWDT2) displays NewDat bit of all message objects. It is possible to
check data of which message object has been updated by reading NewDat bit.
■ Register Configuration
Figure 30.4-19 New Data Register 2 (NEWDT2)
New Data Register 2 high byte
15
14
New Data Register 2 low byte
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
NEWDT2L
NewDat24 to 17
(R)
(0)
⇐ Bit no.
NEWDT2H
(R)
(0)
Address : Base + 91H
Read/write ⇒
Default value⇒
12
NewDat32 to 25
Address : Base + 90H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
Figure 30.4-20 New Data Register 1 (NEWDT1)
New Data Register 1 high byte
15
14
Read/write ⇒
Default value⇒
New Data Register 1 low byte
12
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
NEWDT1L
NewDat8 to 1
(R)
(0)
⇐ Bit no.
NEWDT1H
(R)
(0)
Address : Base + 93H
Read/write ⇒
Default value⇒
13
NewDat16 to 9
Address : Base + 92H
(R)
(0)
(R)
(0)
(R)
(0)
■ Register functions
NewDat32 to NewDat1: Data update bit
NewDat32 to NewDat1
Function
0
No update data
1
Update data exists.
The following shows the set/reset conditions of the NewDat bit:
• Set conditions
- It can be set to a specific object by setting WR/RD to "1" and Control to "1" in the IFx command mask
register, setting NewDat to "1" in the IFx message control register and then writing to the IFx command
request register.
- It will be set by receiving the data frame that has passed through the acceptance filter.
- If Dir bit is "1", RmtEn is "0" and UMask is "1", it is set by receiving the remote frame that has passed
through the acceptance filter.
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• Reset conditions
- NewDat of a specific object can be reset by setting WR/RD to "0" and NewDat to "1" in the IFx command
mask register and writing to the IFx command request register.
- NewDat of a specific object can be reset by setting WR/RD to "1" and Control to "1" in the IFx command
mask register, setting NewDat to "0" in theIFx message control register, and then writing to the IFx
command request register.
- It will be reset after transferring the data to the transmission shift register (internal register).
See the following table for the data update bits in CAN macro with over 32 message buffers.
Table 30.4-3 Additional flags when more than 32 message buffers exist
addr+0
addr+1
addr+2
addr+3
NEWDT 4 & 3
NewDat 64 to 33 (address 0x94)
NewDat64 to 57
NewDat56 to 49
NewDat48 to 41
NewDat40 to 33
NEWDT 6 & 5
NewDat 96 to 65 (address 0x98)
NewDat96 to 89
NewDat88 to 81
NewDat80 to 73
NewDat72 to 65
NEWDT 8 & 7 NewDat 128 to 97 (address 0x9C) NewDat128 to 121 NewDat120 to 113 NewDat112 to 105 NewDat104 to 97
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30.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2)
CAN interrupt pending register (INTPND1, INTPND2) displays the IntPnd bit of all message objects. It is
possible to check the interrupt of which message object is currently pending by reading IntPnd bit.
■ Register Configuration
Figure 30.4-21 Interrupt Pending Register 2 (INTPND2)
Int Pending Register 2 high byte
15
14
Int Pending Register 2 low byte
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
INTPND2L
IntPnd24 to 17
(R)
(0)
⇐ Bit no.
INTPND2H
(R)
(0)
Address : Base + A1H
Read/write ⇒
Default value⇒
12
IntPnd32 to 25
Address : Base + A0H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
Figure 30.4-22 Interrupt Pending Register 1 (INTPND1)
Int Pending Register 1 high byte
15
14
Int Pending Register 1 low byte
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
INTPND1L
IntPnd8 to 1
(R)
(0)
⇐ Bit no.
INTPND1H
(R)
(0)
Address : Base + A3H
Read/write ⇒
Default value⇒
12
IntPnd16 to 9
Address : Base + A2H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
■ Register functions
IntPnd32 to IntPnd1: Interrupt pending bit
IntPnd 32 to IntPnd1
Function
0
No interrupt factor
1
Interrupt factor
The following shows the set/reset conditions of the IntPnd bit:
• Set conditions
- If TxIE is set to "1", IntPnd bit will be set to "1" when the frame transmission ends successfully.
- If RxIE is set to "1", IntPnd bit will be set to "1" when the reception of the frame that has passed through
the acceptance filter ends successfully.
- IntPnd of a specific object can be reset by setting WR/RD to "1" and Control to "1" in the IFx command
mask register, setting IntPnd to "1" in the IFx message control register, and then writing to the IFx
command request register.
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• Reset conditions
- If WR/RD is set to "1" and IntPnd is set to "1" in the IFx command mask register, IntPnd of a specific object
can be reset by writing to the IFx command request register.
- If WR/RD is set to "1" and Control is set to "1" in the IFx command mask register and IntPnd of the IFx
message control register is set to "0", IntPnd of a specific object can be set by writing to the IFx
command request register.
See the following table for the interrupt pending bits in CAN macro with over 32 message buffers.
Table 30.4-4 Additional flags when more than 32 message buffers exist
addr+0
addr+1
addr+2
addr+3
INTPND 4 & 3 IntPnd 64 to 33 (address 0xA4) IntPnd64 to 57
IntPnd56 to 49
IntPnd48 to 41
IntPnd40 to 33
INTPND 6 & 5 IntPnd 96 to 65 (address 0xA8) IntPnd96 to 89
IntPnd88 to 81
IntPnd80 to 73
IntPnd72 to 65
INTPND 8 & 7 IntPd 128 to 97 (address 0xAC) IntPnd128 to 121 IntPnd120 to 113 IntPnd112 to 105 IntPnd104 to 97
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30.4.4.4 CAN Message Valid Register (MSGVAL1, MSGVAL2)
CAN message valid register (MSGVAL1, MSGVAL2) displays the MsgVal bit of all message objects. It is
possible to check which message object is valid by reading MsgVal bit.
■ Register Configuration
Figure 30.4-23 Message Valid Register 2 (MSGVAL2)
Message Valid Register 2 high byte
15
14
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Address : Base + B1H
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
MSGVAL2L
MsgVal24 to 17
(R)
(0)
⇐ Bit no.
MSGVAL2H
(R)
(0)
Message Valid Register 2 low byte
Read/write ⇒
Default value⇒
12
MsgVal32 to 25
Address : Base + B0H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
Figure 30.4-24 Message Valid Register 1 (MSGVAL1)
Message Valid Register 1 high byte
15
14
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Address : Base + B3H
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
⇐ Bit no.
MSGVAL1L
MsgVal8 to 1
(R)
(0)
⇐ Bit no.
MSGVAL1H
(R)
(0)
Message Valid Register 1 low byte
Read/write ⇒
Default value⇒
12
MsgVal16 to 9
Address : Base + B2H
Read/write ⇒
Default value⇒
13
(R)
(0)
(R)
(0)
(R)
(0)
■ Register functions
MsgVal32 to MsgVal1: Message valid bit
MsgVal32 to MsgVal1
Function
0
Message object is disabled.
Message transmission/reception will not be performed.
1
Message object is enabled.
Message transmission/reception will become possible.
The following shows the set/reset conditions of the MsgVal bit:
• Set conditions
MsgVal of a specific object can be set by setting WR/RD to "1" and Arb to "1" in the IFx command mask
register, setting MsgVal of the IFx arbitration register 2 to "1", and then writing to the IFx command request
register.
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• Reset conditions
MsgVal of a specific object can be set by setting WR/RD to "1" and Arb to "1" in the IFx command mask
register, setting MsgVal of the IFx arbitration register 2 to "0", and then writing to the IFx command request
register.
See the following table for the message valid bits in CAN macro with over 32 message buffers.
Table 30.4-5 Additional flags when more than 32 message buffers exist
addr+0
addr+1
addr+2
addr+3
MSGVAL 4 & 3
MsgVal 64 to 33 (address 0xB4)
MsgVal64 to 57
MsgVal56 to 49
MsgVal48 to 41
MsgVal40 to 33
MSGVAL 6 & 5
MsgVal 96 to 65 (address 0xB8)
MsgVal96 to 89
MsgVal88 to 81
MsgVal80 to 73
MsgVal72 to 65
MSGVAL 8 & 7 MsgVal 128 to 97 (address 0xBC) MsgVal128 to 121 MsgVal120 to 113 MsgVal112 to 105 MsgVal104 to 97
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30.5 Functional Description
This chapter provides an overview of the CAN module’s operating modes and how to use them.
CAN has the following functions:
• Message object
• Message Transmission Operation
• Message Reception Operation
• FIFO Buffer Function
• Interrupt Function
• Bit Timing
• Test Mode
• Software Initialization
30.5.1 Message Object
This section explains the message object and interface of message RAM.
■ Management of Message Objects
The configuration of the Message Objects in the Message RAM will (with the exception of the bits MsgVal,
NewDat, IntPnd, and TxRqst) not be affected by resetting the chip. All the Message Objects must be
initialized by the CPU or they must be not valid (MsgVal = 0) and the bit timing must be configured before the
CPU clears the Init bit in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of
one of the two interface register sets to the desired values. By writing to the corresponding IFx Command
Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the
Message RAM.
When the Init bit in the CAN Control Register is cleared, the CAN Protocol Controller state machine of the
CAN_Core and the Message Handler State Machine control the CAN’s internal data flow. Received messages
that pass the acceptance filtering are stored into the Message RAM, messages with pending transmission
request are loaded into the CAN_Core’s Shift Register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx Interface Registers.
Depending on the configuration, the CPU is interrupted on certain CAN message and CAN error events.
■ Data Transfer from/to Message RAM
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the Message Handler
sets an internal busy signal which delays a consecutive access. After the transfer has completed, the busy
signal is set back and the consecutive access is executed.
The respective Command Mask Register specifies whether a complete Message Object or only parts of it will
be transferred. Due to the structure of the Message RAM it is not possible to write single bits/bytes of one
Message Object, it is always necessary to write a complete Message Object into the Message RAM.
Therefore the data transfer from the IFx Registers to the Message RAM requires a read-modify-write cycle.
First parts of the Message Object that are not to be changes are read from the Message RAM and then the
complete contents of the Message Buffer Registers are written into the Message Object.
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Figure 30.5-1 Data Transfer between IFx Registers and Message RAM
Start
NO
Write to Ifx command
request register
YES
BUSY = 1
Interrupt = 0
NO
YES
WR/RD = 1
Read from message RAM to message interface
Read from message RAM to message interface
Write from message interface to message RAM
BUSY = 0
Interrupt = 1
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30.5.2 Message Transmission Operation
This section explains the setting method and transmission operation of the transmission message object.
■ Transmission of Messages
If the shift register of the CAN Core cell is ready for loading and if there is no data transfer between the IFx
Registers and Message RAM, the MsgVal bits in the Message Valid Register and the TxRqst bits in the
Transmission Request Register are evaluated. The valid Message Object with the highest priority pending
transmission request is loaded into the shift register by the Message Handler and the transmission is started.
The Message Object’s NewDat bit is reset.
After a successful transmission and if no new data was written to the Message Object (NewDat = 0) since the
start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful
transmission. If the CAN has lost the arbitration or if an error occurred during the transmission, the message
will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a message with
higher priority has been requested, the messages will be transmitted in the order of their priority.
■ Receive / Transmit Priority
The receive/transmit priority for the Message Objects is attached to the message number. Message Object 1
has the highest priority, while Message Object 32 (the highest implemented message object number) has the
lowest priority. If more than one transmission request is pending, they are serviced due to the priority of the
corresponding Message Object.
<Notes>
• If TxRqst is set to "1" and then set to "0" to stop the transmission in the case where the lowest priority
message buffer is being used for the transmission, the message may not be transmitted when TxRqst is set
to "1" again until one of the following events occurs (depends on the timing).
- A valid message flows through the CAN bus
- A transmission request is issued to another message buffer
- C_CAN is initialized by INIT bit
If it will become necessary to stop the transmission on the system, either avoid using the lowest priority
message buffer for the transmission, or set TxRqst to "1" again after generating one of the above events.
• If the message object with ID28-0, DLC3-0, Xtd and Data7-0 is changed while TxRqst bit is set to "1", the
message object before and after the change may get transmitted in mixture or the message object after the
change may not be transmitted at all. Therefore, change them while TxRqst bit is "0".
■ Configuration of a Transmit Object
Figure 30.5-2 shows how a Transmit Object should be initialised.
Figure 30.5-2 Initialization of a Transmit Object
MsgVal
Arb
Data
Mask
EoB
Dir
NewDat
MsgLst
RxIE
TxIE
IntPnd
RmtEn
TxRqst
1
appl.
appl.
appl.
1
1
0
0
0
appl.
0
appl.
0
The Arbitration Registers (ID28 to 0 and Xtd bit) are given by the application. They define the identifier and
type of the outgoing message. If an 11-bit Identifier ("Standard Frame") is used, it is programmed to ID28 to
ID18, ID17 to ID0 can then be disregarded.
If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the Message Object.
If the RmtEn bit is set, a matching received Remote Frame will cause the TxRqst bit to be set; the Remote
Frame will autonomously be answered by a Data Frame.
The Data Registers (DLC3 to 0, Data0 to 7) are given by the application, TxRqst and RmtEn may not be set
before the data is valid.
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The Mask Registers (Msk28 to 0, UMask, MXtd, and MDir bits) may be used (UMask=1) to allow groups of
Remote Frames with similar identifiers to set the TxRqst bit. For details see section ■"Transmission of
Messages" on P. 476 , handle with care. The Dir bit should not be masked.
■ Update of transmission message object
CPU can update the data of the transmission message object via the message interface register.
Data of the transmission message object will be written in units of 4 bytes of the corresponding IFx data
register (in unit of the IFx data register A or IFx data register B). Therefore, it is not possible to change only 1
byte of the transmission message object.
"0087H" will be written to the IFx command mask register first when only updating an 8 byte data. Then, data
of the transmission message object (8 byte data) will be updated and "1" will be written to TxRqst bit at the
same time when a message number is written to the IFx command request register.
If NewDat bit and TxRqst bit are both "1", NewDat bit will be reset to "0" when the transmission starts.
• When updating data, perform it in units of 4 bytes of the IFx data register A or IFx data register B.
• If the message object with ID28-0, DLC3-0, Xtd and Data7-0 is changed while TxRqst bit is set to "1", the
message object before and after the change may get transmitted in mixture or the message object after the
change may not be transmitted at all. Therefore, change them while TxRqst bit is "0".
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30.5.3 Message Reception Operation
This section explains the setting method and reception operation of the reception message object.
■ Acceptance Filtering of Received Messages
When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely
shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the
Message RAM for a matching valid Message Object.
To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the
arbitration bits from the CAN Core shift register. Then the arbitration and mask fields (including MsgVal,
UMask, NewDat, and EoB) of Message Object 1 are loaded into the Acceptance Filtering unit and compared
with the arbitration field from the shift register. This is repeated with each following Message Object until a
matching Message Object is found or until the end of the Message RAM is reached.
If a match occurs, the scanning is stopped and the Message Handler FSM proceeds depending on the type of
frame (Data Frame or Remote Frame) received.
■ Reception priority
Reception priority of a message object is determined by its message number. Message object 1 has the
highest priority; and message object 32 (ch.0) / 64 (ch.1) has the lowest priority. If 2 or more message objects
match the acceptance filter, the one having the smaller message number will be the reception message
object.
■ Reception of Data Frame
The Message Handler FSM stores the message from the CAN Core shift register into the respective Message
Object in the Message RAM. Not only the data bytes, but all arbitration bits and the Data Length Code are
stored into the corresponding Message Object. This is implemented to keep the data bytes connected with the
identifier even if arbitration mask registers are used.
The NewDat bit is set to indicate that new data (not yet seen by the CPU) has been received. The CPU should
reset NewDat when it reads the Message Object. If at the time of the reception the NewDat bit was already
set, MsgLst is set to indicate that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is
set, the IntPnd bit is set, causing the Interrupt Register to point to this Message Object.
The TxRqst bit of this Message Object is reset to prevent the transmission of a Remote Frame, while the
requested Data Frame has just been received.
■ Reception of Remote Frame
When a Remote Frame is received, three different configurations of the matching Message Object have to be
considered:
1) Dir = 1 (direction = transmit), RmtEn = 1, UMask = 1 or 0
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object is set. The rest of the
Message Object remains unchanged.
2) Dir = 1 (direction = transmit), RmtEn = 0, UMask = 0
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object remains unchanged; the
Remote Frame is ignored.
3) Dir = 1 (direction = transmit), RmtEn = 0, UMask = 1
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object is reset. The arbitration
and control field (Identifier + IDE + RTR + DLC) from the shift register is stored into the Message Object in the
Message RAM and the NewDat bit of this Message Object is set. The data field of the Message Object
remains unchanged; the Remote Frame is treated similar to a received Data Frame.
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■ Remote frame
The following three processes are performed when the remote frame is received. The appropriate process will
be selected from the setting of the matching message object.
1) Dir=1 (Transmission direction) , RmtEn=1, UMask=1 or 0
The matched remote frame will be received, only TxRqst bit of this message object will be set to "1", and
the automatic reply (transmission) of the data frame in response to the received remote frame will be
performed (the message object will remain unchanged except for TxRqst bit).
2) Dir=1 (Transmission direction) , RmtEn=0, UMask=0
Remote frame will be disabled without receiving the message, even if the received remote frame matches
the message object (TxRqst bit of this message object will remain unchanged).
3) Dir=1 (Transmission direction) , RmtEn=0, UMask=1
If the received remote frame matches the message object, TxRqst bit of this message object will be reset to
"0", and the remote frame will be processed as a reception data frame. The received arbitration field and
control field (ID + IDE + RTR + DLC) will be stored to the message object in message RAM, and NewDat
bit of this message object will be set to "1". Data field of the message object will be unchanged.
■ Configuration of a Receive Object
Figure 30.5-3 shows how a Transmit Object should be initialised.
Figure 30.5-3 Initialization of a Receive Object
MsgVal
Arb
Data
Mask
EoB
Dir
NewDat
MsgLst
RxIE
TxIE
IntPnd
RmtEn
TxRqst
1
appl.
appl.
appl.
1
0
0
0
appl.
0
0
0
0
The Arbitration Registers (ID28 to 0 and Xtd bit) are given by the application. They define the identifier and
type of accepted received messages. If an 11-bit Identifier ("Standard Frame") is used, it is programmed to
ID28 toID18, ID17 to ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received,
ID17 to ID0 will be set to "0".
If the RxIE bit is set, the IntPnd bit will be set when a received Data Frame is accepted and stored in the
Message Object.
The Data Length Code (DLC3 to 0) is given by the application. When the Message Handler stores a Data
Frame in the Message Object, it will store the received Data Length Code and eight data bytes. If the Data
Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by non specified
values.
The Mask Registers (Msk28 to 0, UMask, MXtd, and MDir bits) may be used (UMask=1) to allow groups of
Data Frames with similar identifiers to be accepted. For details see section ■"Reception of Data Frame" on P.
478 . The Dir bit should not be masked in typical applications.
(Note)
Dir bit of the IFx mask register cannot be set as a mask.
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■ Handling of Received Messages
The CPU may read a received message any time via the IFx Interface registers, the data consistency is
guaranteed by the Message Handler state machine.
Typically the CPU will write first 0x007F to the Command Mask Register and then the number of the Message
Object to the Command Request Register. That combination will transfer the whole received message from
the Message RAM into the Message Buffer Register. Additionally, the bits NewDat and IntPnd are cleared in
the Message RAM (not in the Message Buffer).
If the Message Object uses masks for acceptance filtering, the arbitration bits show which of the matching
messages have been received.
The actual value of NewDat shows whether a new message has been received since last time this Message
Object was read. The actual value of MsgLst shows whether more than one message has been received
since last time this Message Object was read. MsgLst will not be automatically reset.
By means of a Remote Frame, the CPU may request another CAN node to provide new data for a receive
object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the
receive object’s identifier. This Remote Frame triggers the other CAN node to start the transmission of the
matching Data Frame. If the matching Data Frame is received before the Remote Frame could be transmitted,
the TxRqst bit is automatically reset.
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30.5.4 FIFO Buffer Function
This section explains the configuration and operation of the FIFO buffer of the message object in the reception message
processing.
■ Configuration of a FIFO Buffer
With the exception of the EoB bit, the configuration of Receive Objects belonging to a FIFO Buffer is the same
as the configuration of a (single) Receive Object, see section ■"Configuration of a Receive Object" on P. 479
To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and masks (if used) of these
Message Objects have to be programmed to matching values. Due to the implicit priority of the Message
Objects, the Message Object with the lowest number will be the first Message Object of the FIFO Buffer. The
EoB bit of all Message Objects of a FIFO Buffer except the last have to be programmed to zero. The EoB bits
of the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the Block.
■ Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO Buffer are stored into a Message Object of this FIFO
Buffer starting with the Message Object with the lowest message number.
When a message is stored into a Message Object of a FIFO Buffer the NewDat bit of this Message Object is
set. By setting NewDat while EoB is 0 the Message Object is locked for further write accesses by the
Message Handler until the CPU has written the NewDat bit back to 0.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached. If none of
the preceding Message Objects is released by writing NewDat to 0, all further messages for this FIFO Buffer
will be written into the last Message Object of the FIFO Buffer and therefore overwrite previous messages.
■ Reading from a FIFO Buffer
When the CPU transfers the contents of Message Object to the IFx Message Buffer registers by writing its
number to the IFx Command Request Register, the corresponding Command Mask Register should be
programmed the way that bits NewDat and IntPnd are reset to zero (TxRqst/NewDat = 1 and ClrIntPnd = 1).
The values of these bits in the Message Control Register always reflect the status before resetting the bits.
To assure the correct function of a FIFO Buffer, the CPU should read out the Message Objects starting at the
FIFO Object with the lowest message number.
Figure 30.5-4 shows how a set of Message Objects which are concatenated to a FIFO Buffer can be handled
by the CPU.
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Figure 30.5-4 CPU Handling of a FIFO Buffer
Start
Message interrupt
Read from CAN
interrupt register
8000H
0000H
CAN interrupt register value
Neither 8000H nor 0000H
Execute status
interrupt process
Message number =
CAN interrupt register value
End
(normal process)
Write (message number) to
Ifx command request register
Read from message interface register
(reset: NewDat=0, IntPnd=0)
Read from Ifx message control register
NO
NewDat = 1
YES
Read from Ifx message data register A/B
YES
EoB = 1
NO
Message number = Message number + 1
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30.5.5 Handling of Interrupts
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest
priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt
priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by
reading the Status Register.
The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is
pending, the register will hold the value zero. If the value of the Interrupt Register is different from zero, then
there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active. The interrupt line remains
active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily
changed) the Status Register (Error Interrupt or Status Interrupt). This interrupt has the highest priority. The
CPU can update (reset) the status bits RxOk, TxOk and LEC, but a write access of the CPU to the Status
Register can never generate or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects, IntId points to the
pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE and SIE in the
CAN Control Register) and whether the interrupt line becomes active when the Interrupt Register is different
from zero (bit IE in the CAN Control Register). The Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt. First it can follow the IntId in the
Interrupt Register and second it can poll the Interrupt Pending Register (see section 30.4.4 Message Handler
Registers (Page No.466).
An interrupt service routine reading the message that is the source of the interrupt may read the message and
reset the Message Object’s IntPnd at the same time (through setting bit CIP = 1 (clear interrupt pending) in
the Command Mask Register). When IntPnd is cleared, the Interrupt Register will point to the next Message
Object with a pending interrupt.
30.5.6 Bit Time and Bit Rate
The timing parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually for each
CAN node, creating a common bit rate even though the CAN nodes’ oscillator periods (fosc) may be different.
The frequencies of these oscillators are not absolutely stable, small variations are caused by changes in
temperature or voltage and by deteriorating components. As long as the variations remain inside a specific
oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by
resynchronising to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure 30.5-5). The
Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase Buffer
Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 1). The
length of the time quantum (tq) , which is the basic time unit of the bit time, is defined by the CAN controller’s
system clock fsys and the Baud Rate Prescaler (BRP) : tq = BRP / fsys. The CAN’s system clock fsys is the
frequency of its CLKCAN input.
The Synchronization Segment Sync_Seg is that part of the bit time where edges of the CAN bus level are
expected to occur; the distance between an edge that occurs outside of Sync_Seg and the Sync_Seg is called
the phase error of that edge. The Propagation Time Segment Prop_Seg is intended to compensate for the
physical delay times within the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2
surround the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization
may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge
phase errors.
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Figure 30.5-5 Bit Timing
Nominal CAN Bit Time
Sync_
Seg
Phase_Seg1
Prop_Seg
1 Time Quantum
(tq)
Phase_Seg2
Sample Point
Table 30.5-1 Parameters of the CAN Bit Time
(Note)
484
Parameter
Range
Remark
BRP
[1..32]
defines the length of the time quantum tq
Sync_Seg
1 tq
Prop_Seg
[1..8] tq
compensates for the physical delay times
Phase_Seg1
[1..8] tq
may be lengthened temporarily by synchronization
Phase_Seg2
[1..8] tq
may be shortened temporarily by synchronization
SJW
[1..4] tq
may not be longer than either Phase Buffer Segment
fixed length, synchronization of us into system clock
This table describes the minimum programmable ranges required by the CAN protocol.
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Figure 30.5-6 shows the bit timing in the CAN controller.
Figure 30.5-6 Bit Timing in the CAN Controller
1 bit time (BT)
Sync
_Seg
TEG1
TEG2
1 unit of time
(tq)
Sampling point
Table 30.5-2 CAN Controller Parameters
Parameter
Range
Function
BRPE,BRP
[0-1023]
Sync_Seg
1 tq
TSEG1
[1-15] tq
Time segment before the sampling point.
It corresponds to Prop_Seg and Phase_Seg1.
It can be controlled using a bit timing register.
TSEG2
[0-7] tq
Time segment after the sampling point.
It corresponds to Phase_Seg2.
It can be controlled using a bit timing register.
SJW
[0-3] tq
It is the resynchronization jump width.
It can be controlled using a bit timing register.
Definition of time quantum length (tq)
Prescaler can be extended up to 1024 by the bit timing register and
prescaler extension register.
Synchronization to the system clock
Fixed length
The following shows the relationship between each parameter:
tq
=([BRPE,BRP]+1) / fsys
BT =SYNC_SEG + TEG1 + TEG2
=(1 + (TSEG1 + 1) + (TSEG2 + 1)) × tq
=(3 + TSEG1 + TSEG2) × tq
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30.5.7 Test Mode
This section explains the setting method and operation of the test mode.
■ Test Mode
The Test Mode is entered by setting bit Test in the CAN Control Register to one. In Test Mode the bits Tx1,
Tx0, LBack, Silent and Basic in the Test Register are writable. Bit Rx monitor the state of pin RX and
therefore is only readable. All Test Register functions are disabled when bit Test is reset to zero.
■ Silent Mode
The CAN Core can be set in Silent Mode by programming the Test Register bit Silent to "1".
In Silent Mode, the CAN is able to receive valid data frames and valid remote frames, but it sends only
recessive bits on the CAN bus and it cannot start a transmission. If the CAN Core is required to send a
dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN Core
monitors this dominant bit, although the CAN bus may remain in recessive state. The Silent Mode can be used
to analyse the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits,
Error Frames). Figure 30.5-7 shows the connection of signals TX and RX to the CAN Core in Silent Mode.
Figure 30.5-7 CAN Core in Silent Mode
TX
RX
C_CAN
=1
Tx
Rx
CAN_Core
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■ Loop Back Mode
The CAN Core can be set in Loop Back Mode by programming the Test Register bit LBack to one. In Loop
Back Mode, the CAN Core treats its own transmitted messages as received messages and stores them (if
they pass acceptance filtering) into a Receive Buffer. Figure 30.5-8 shows the connection of signals TX and
RX to the CAN Core in Loop Back Mode.
Figure 30.5-8 CAN Core in Loop Back Mode
TX
RX
Tx
Rx
C_CAN
CAN Core
This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core
ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop
Back Mode. In this mode the CAN Core performs an internal feedback from its Tx output to its Rx input. The
actual value of the RX input pin is disregarded by the CAN Core. The transmitted messages can be monitored
at the TX pin.
■ Loop Back combined with Silent Mode
It is also possible to combine Loop Back Mode and Silent Mode by programming bits LBack and Silent to "1"
at the same time. This mode can be used for a "Hot Selftest", meaning the CAN can be tested without
affecting a running CAN system connected to the pins TX and RX. In this mode the RX pin is disconnected
from the CAN Core and the TX pin is held recessive. Figure 30.5-9shows the connection of signals TX and RX
to the CAN Core in case of the combination of Loop Back Mode with Silent Mode.
Figure 30.5-9 CAN Core in Loop Back combined with Silent Mode
RX
TX
C_CAN
=1
Tx
Rx
CAN Core
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■ Basic Mode
The CAN Core can be set in Basic Mode by programming the Test Register bit Basic to "1". In this mode the
CAN module runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is
requested by writing the Busy bit of the IF1 Command Request Register to "1". The IF1 Registers are locked
while the Busy bit is set. The Busy bit indicates that the transmission is pending.
As soon as the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN Core and the
transmission is started. When the transmission has completed, the Busy bit is reset and the locked IF1
Registers are released.
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request
Register while the IF1 Registers are locked. If the CPU has reset the Busy bit, a possible retransmission in
case of lost arbitration or in case of an error is disabled.
The IF2 Registers are used as Receive Buffer. After the reception of a message the content of the shift
register is stored into the IF2 Registers, without any acceptance filtering.
Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time
a read Message Object is initiated by writing the Busy bit of the IF2 Command Request Register to "1", the
content of the shift register is stored in the IF2 Registers.
In Basic Mode the evaluation of all Message Object related control and status bits and of the control bits of the
IFx Command Mask Registers is turned off. The message number of the Command request registers is not
evaluated. The NewDat and MsgLst bits of the IF2 Message Control Register retain their function, DLC3 to 0
will show the received DLC, the other control bits will be read as "0".
■ Software control of CAN_TX pin
CAN_TX, the CAN transmission pin, has the following four output functions:
• Serial data output (Normal output)
• CAN sampling point signal output for monitoring the bit timing of the CAN controller
• Fixed dominant output
• Fixed recessive output
Fixed dominant and recessive outputs can be used for the CAN_RX monitoring function of the CAN reception
pin and for checking the physical layer of the CAN bus.
Output mode of the CAN_TX pin can be controlled using Tx1 and Tx0 bits of the CAN test register.
CAN_TX needs to be set to serial data output when using CAN message transmission, loopback mode, silent
mode or basic mode.
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30.5.8 Software Initialization
This section explains the initialization by software.
The following shows the software initialization factors:
• Hardware reset
• Init bit setting of the CAN control register (CTRLR)
• A transition to the bus-off state
A hardware reset initializes everthing except message RAM (excluding MsgVal, NewDat, IntPnd and TxRqst
bits). After a hardware reset, initialize message RAM by the CPU or set MsgVal of message RAM to "0". Set
bit timing register before clearing Init bit of the CAN control register (CTRLR) to "0".
Init bit of the CAN control register will be set in the following conditions:
• When "1" is written from the CPU
• Hardware reset
• Bus-off
When Init bit is set to "1", all message transmissions/receptions of the CAN bus will be stopped and the
CAN_TX pin of the CAN bus output will become a recessive output (excluding the CAN_TX test mode).
When Init bit is set to "1", error counter and register will both remain unchanged.
Settings of the bit timing register for baud rate control and the prescaler extension register will become
possible when Init and CCE bits of the CAN control register (CTRLR) is set to "1".
Software initialization will be terminated by resetting Init bit to "0". Init bit can only be set to "0" by an access
from the CPU.
Message will be transferred after synchronizing with the data transfer on the CAN bus, by waiting for a
consecutive 11-bit recessive (= bus-idle) to occur after Init bit has been reset to "1".
During normal operation, change the mask, ID, Xtd, EoB and RmtEn of the message object after disabling MsgVal.
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Chapter 31 Free-Run Timer (FRT)
31.1
MB91460N series
Chapter 31 Free-Run Timer (FRT)
31.1 Overview
The Free-Run timer consists of a 16-bit timer (up counter) and control circuits.
The Free-Run timer can be used by the input capture or by the output compare.
Figure 31.1-1 Block diagram of Free-Run Timer
Output compare [0-1],[2-3]
16-bit up counter [2],[3]
Overflow
Interrupt
Free-Run Timer
Clear
Internal clock
Clear
External clock
Overflow
16-bit up counter [0],[1]
Input capture [0-1],[2-3]
Interrupt
Free-Run Timer
31.2 Features
•
•
•
•
•
Format: 16-bit up counter
Quantity: 4 (Free-Run timer 0 to Free-Run timer 3)
Clock source: 4 internal clocks (1/4, 1/16, 1/32, and 1/64 of CLKP)
External clock (CK pin)
Clear factor of the counter:
• Software
• Reset
• Compare-match (match of the compare-register value and the count value of the Free-Run timer)
• Operation start/stop: operations can be started/stopped by software.
• Interrupt:
• Overflow interrupt
• An interrupt generated when the compare clear register value and the count value of the Free-Run timer
match.
• Count value: Readable/writable (write is only possible when the counting stops)
• Others: Operates from immediately after reset.
• Free-Run Timer and ICU/OCU:
• Free-Run timer 0 can be used by input capture unit 0/1
• Free-Run timer 1 can be used by input capture unit 2/3
• Free-Run timer 2 can be used by output compare unit 0/1
• Free-Run timer 3 can be used by output compare unit 2/3
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MB91460N series
31.3 Configuration Diagram
Figure 31.3-1 Configuration Diagram of Free-Run Timer
Free-Run Timer
Count clock
0
0
1
1
CLK1,0
0
1
0
1
TCCS: bit 1, bit 0
CLKP / 4
CLKP / 16
CLKP / 32
CLKP / 64
STOP
0
1
Input capture
TCCS: bit 4
IVFE
Count operation
Stop the count operation
0
1
Count value
0
Overflow flag
0
Peripheral clock
Timer data register
Divider
C LKP
IVF
TCDT
Synchronization
circuit
CK /SCK/ Pxy.z
1
Free-Run Timer
interrupt
TCCS: bit 6
0
No interrupt
1
Interrupt present
WRITE 0: Flag clear
External clock
External clock
T CCS: bit 5
Disable interrupt requests
Enable interrupt requests
Clear
1
The clock selection
ECLK
0
1
OR
TCCS:bit 7
Count value
From the divider
From the outside
Output compare
1
Read of the port
The timer clear request by the
compare value match of the
output compare
0
From the port
data register
0
1 (Resource
output)
CLR
PFR/EPFR
Function
0 0 General-purpose port
1 0 SCK (LIN-USART shift clock)
1 1 CK (FRT clock input)
GP
DDRxy.z
0
Input only
1 Enable output
0
1
TCCS:bit 2
TCCS: bit 3
MODE
No effect
Clears the timer
0
Disable the clear by the compare-match
1
Enable the clear by the compare-match
Notes: When using the input/output (SCK), the external clock (CK) cannot be used because the port is shared.
Figure 31.3-2 Register List
F ree-run T imer 0
Addres s B it
0001F 0 H
B it
15
T 15
14
T 14
13
T 13
12
T 12
11
T 11
10
T 10
8
T8
2
CLR
7
T7
0001F 3 H
7
E CLK
6
IV F
5
IV F E
000D95 H
000DD5 H
-----
-----
-----
-----
-----
S CK
CK
-----
00044C H
---
---
---
IC R 4
IC R 3
IC R 2
IC R 1
0F F F 5C H
4
3
S T OP MODE
9
T9
6
T6
5
T5
4
T4
1
0
CLK 1 CLK 0 TCCS 0
-----
P F R 21
E P F R 21
IC R 0 IC R 12
3
T3
2
T2
1
T1
0
T0
T C DT 0 (F ree-run T imer 0)
(F ree-run timer c ontrol 0)
(P ort func tion)
(E x tra port func tion)
(Interrupt level
32B its
(Interrupt vec tor #40)
* S ee the c hapter of " Interrupt C ontrol" about IC R regis ter and interrupt vec tors .
Note: See "Chapter 21 Interrupt Control (Page No.219)" about ICR register and interrupt vectors.
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Chapter 31 Free-Run Timer (FRT)
31.4
MB91460N series
31.4 Registers
31.4.1 TCCS: Timer Control Register
A register for controlling the operation of the Free-Run timer.
•
•
•
•
TCCS0 (Free-Run timer 0): Address 0001F3H (access: Byte, Half-word, Word)
TCCS1 (Free-Run timer 1): Address 0001F7H (access: Byte, Half-word, Word)
TCCS2 (Free-Run timer 2): Address 0001FBH (access: Byte, Half-word, Word)
TCCS3 (Free-Run timer 3): Address 0001FFH (access: Byte, Half-word, Word)
7
ECLK
0
R/W
6
IVF
0
R (RM1), W
5
IVFE
0
R/W
4
STOP
0
R/W
3
MODE
0
R/W
2
CLR
0
R/W
1
CLK1
0
R/W
0
CLK0
0
R/W
bit
Initial value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit7: Select the count clock
ECLK
0
1
Select the count clock
Internal clock (the peripheral clock divided by n)
External clock (CK pin)
• The setting of the count clock selection bit should be changed only when other peripheral modules (the
output compare, input capture, etc.) using the output of the Free-Run timer are stopped.
• When using the external clock, the period of the external clock must be more than double of the
peripheral clock (CLKP). When using the output compare, in order to allow the compare-match output
and interrupt generation, the external clock input of at least 1 clock is required after the compare-match.
• bit6: Interrupt flag
Status
IVF
Read
Write
0
No interrupt present
Clear the flag (IVF).
1
Interrupt present
(Overflow or compare-match)
No effect on operation
• When the count value of the Free-Run timer overflows, or the clear mode bit (MODE) is "1", the interrupt
flag is set to "1" if the count values of the Free-Run timer and the compare register (OCCP) match and
the counter is cleared.
• To enable the interrupt request, the interrupt enable bit must be set to do so (IVFE=1).
• When the interrupt flag is set to "1", and "0" is written at the same time, the interrupt flag is set to "1".
(Setting the flag has priority.)
• bit5: Enable interrupt requests
IVFE
0
1
Operation
Disable interrupt requests
Enable interrupt requests
• When the interrupt request enable bit is set to "1", the interrupt request (IVF) is enabled.
• bit4: Stop counting
STOP
0
1
Operation
Enable counting
Disable count (stop)
• When the count stop bit is set to "1", the Free-Run timer stops.
• When the output compare is being used, if the Free-Run timer stops, the output compare also stops.
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• bit3: Clear mode
MODE
Clear mode
0
Clear the Free-Run timer by the reset and the clear bit (CLR).
1
Clear the free-run timer by the match with the reset, the clear bit (CLR), and the compare register value
of the output compare (OCCP).
• Set the clear mode of the Free-Run timer.
• If the clear mode bit is set to "1", when the count value of the Free-Run timer and the compare-register
value (OCCP) match, the count value of the Free-Run timer is cleared to "0000H".
• The reset and writing "1" to the clear bit (CLR) cause to clear the count value of the Free-Run timer to
"0000H", regardless of the setting of the clear mode bit.
• The count value of the Free-Run timer is only cleared when the Free-Run timer is running. When the
Free-Run timer is stopped, clear it by writing "0000H" to the timer data register (TCDT).
• bit2: Clear
CLR
0
1
Operation
No effect on operation
Clear the Free-Run timer.
• When the clear bit is set to "1", the count value of the Free-Run timer is cleared to "0000H". The clear bit
is read as "1" until the Free-Run timer is completely cleared.
When the Free-Run timer is completely cleared, the clear bit is also cleared to "0".
• When the clear operation of the Free-Run timer and writing "1" to the clear bit occurs at the same time,
the clear bit keeps "1", and after the next time the Free-Run timer is cleared, it is cleared.
• bit1, bit0: Count clock division ratio selection (when the internal clock is selected)
CLK1
0
0
1
1
CLK0
0
1
0
1
The division ratio of the count clock
Peripheral clock (CLKP) divided by 4
Peripheral clock (CLKP) divided by 16
Peripheral clock (CLKP) divided by 32
Peripheral clock (CLKP) divided by 64
• Select the division ratio of the count clock of the Free-Run timer.
• Change the division ratio when the setting of the count clock division ratio selection bit is changed. When
the internal clock is selected as the count clock of the Free-Run timer (count clock selection bit ECLK=0),
change the setting when other peripheral modules (output compare, input capture, etc.) using the output
of the Free-Run timer are stopped.
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31.4
MB91460N series
31.4.2 TCDT: Timer Data Register
This register can read 16-bit Free-Run timer count values.
•
•
•
•
TCDT0 (Free-Run timer 0): Address 0001F0H (access: Half-word, Word)
TCDT1 (Free-Run timer 1): Address 0001F4H (access: Half-word, Word)
TCDT2 (Free-Run timer 2): Address 0001F8H (access: Half-word, Word)
TCDT3 (Free-Run timer 3): Address 0001FCH (access: Half-word, Word)
15
T15
14
T14
13
T13
12
T12
11
T11
10
T10
9
T9
8
T8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
T7
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial
value
Attribute
bit
Initial
value
Attribute
(About attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• When the timer data register is read, the count value of the Free-Run timer is also obtained.
• By writing to the timer data register, the timer value can be written in the Free-Run timer. When it is
written, make sure that the Free-Run timer is in the idle state (the count stop bit (TCCS:STOP= 1)).
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31.5 Operation
31.5.1 Count Operation of the Free-Run Timer
Figure 31.5-1 Count Operation of the Free-Run Timer
(Internal clock)
(External clock
CLKP/2)
External pin
(CKI)
Peripheral
clock (CLKP)
Internal clock
(CLKP/2)
Count
timing
Count
timing
The count of the
Free-Run timer
(7 )
The count of the
Free-Run timer
(8)
FFFFH
The count of
the Free-Run
timer
(3)
0000H
Reset
(2)
(1)
The overflow and the
interrupt request
Clearing the
Free-Run timer
(5)
(2)
Time
Clear by software
Clear by software
(4)
(5)
(1) Reset
(2) Clearing of the Free-Run timer by reset. (Count value "0000H")
(3) Count-up of the Free-Run timer
(4) Overflow and interrupt of the Free-Run timer.
(5) Clearing of the Free-Run timer by overflow. (Count value "0000H")
(6) Repeat (3) to (5)
(7) The Free-Run timer counts up at the count clock (the internal clock divided by n).
(8) The Free-Run timer counts up at the count clock (the external clock synchronized with the internal clock).
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Chapter 31 Free-Run Timer (FRT)
31.5
MB91460N series
31.5.2 Various Clear Operations of the Free-Run Timer
Figure 31.5-2 Various Clear Operations of the Free-Run Timer
The count of
the Free-Run
timer
0000H
(2)
(3)
(1)
(4)
Time
Reset
Write "0000H"
Clear
Clear by software or the
compare-match.
The enable/disable
of the operation
(software)
Operation
stop
Operation stop
Timing of the clear by the compare-match
(Internal clock)
Peripheral
clock (CLKP)
Count
timing
Count value N-1
-
N
Compare value
"0000"
"0001"
Compare value = N
Compare-match
Clearing the Free-Run timer
The request of interrupt
Clear operations of the Free-Run timer (4 types)
(1) Reset
(2) Clear by software
(3) Clear by the compare-match
(4) Writing "0000H"
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31.6
MB91460N series
31.6 Setting
Table 31.6-1 Setting Required in Order to Use the Free-Run Timer
Setting
Setting Registers
Setting of the initialization conditions of the timer
Setting of the count clock
Selection of the internal clock
Selection of the external clock
Start the count operation
In the case of the external clock
Set the clock input pin (CK) as the input.
Timer control register
(TCCS0 to TCCS3)
Port function register (PFRxy.z)
Extra port function register (EPFRxy.z)
Setting
Procedures *
See 31.7.4
See 31.7.1
See 31.7.2
See 31.7.3
See 31.7.2
*: For the setting procedure, refer to the section indicated by the number.
Table 31.6-2 Setting Required to Enable the Free-Run Timer Interrupt
Setting
Setting of the Free-Run timer interrupt vector,
and the Free-Run timer interrupt level
Setting of the Free-Run timer interrupt
Clearing interrupt flags
Enabling interrupt requests
Setting Registers
Setting
Procedures *
See "Chapter 21 Interrupt Control (Page
No.219)".
See 31.7.5
Timer control register (TCCS0 to TCCS3)
See 31.7.7
*: For the setting procedure, refer to the section indicated by the number.
Table 31.6-3 Setting Required to Stop the Free-Run Timer
Setting
Setting of the Free-Run timer stop bit
Setting Registers
Timer control register (TCCS0 to TCCS3)
Setting
Procedures *
See 31.7.8
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 31 Free-Run Timer (FRT)
31.7
MB91460N series
31.7 Q & A
31.7.1 What are the types of the internal clock, and how to select?
There are 4 types of internal clocks, and these are set by the clock selection bit (TCCS:ECLK) and the count
clock bit (TCCS:CLK [1:0]).
Internal clock
To select CLKP/4
Setting
Clock selection
Count clock bit
Bit (ECLK)
(CLK [1:0])
Set to "0"
Sets to "00"
Count period
CLKP = 32MHz CLKP = 16MHz
125 ns
250 ns
To select CLKP/16
Set to "0"
Set to "01"
0.5 μs
1 μs
To select CLKP/32
Set to "0"
Set to "10"
1 μs
2 μs
To select CLKP/64
Set to "0"
Set to "11"
2 μs
4 μs
31.7.2 How to select the external clock
Set with clock selection bits (TCCS:ECLK), data direction bits, and (extra) port function bits.
To use the external
clock input
Free-Run Timer 0 to 3
Setting
The clock
selection
bit (ECLK)
to "1"
Pins
The port function bit The extra port
(PFRxy.z)
function bit
to "1"
(EPFRxy.z}
to "1"
CK0 to
CK3
Count
Cycle
Over 2/CLKP
31.7.3 How to enable / disable the count operation of the Free-Run timer
Set with count operation bits (TCCS:STOP).
Operation
To enable the Free-Run timer
To stop the Free-Run timer
CM44-10149-1E
Count operation bit (STOP)
Set to "0"
Set to "1"
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31.7
MB91460N series
31.7.4 How to clear the Free-Run timer
The Free-Run timer can be cleared by performing the following operations:
• Set with clear bit (TCCS:CLR).
Operation
Clear bit (CLR)
To clear the Free-Run timer
Write "1"
• How to clear the Free-Run timer when the Free-Run timer value and the compare-register value match
Set with the timer initialization condition bit (TCCS:MODE).
Operation
To clear the Free-Run timer at the compare-match
Timer initialization condition bit (MODE)
Set to "1"
The setting of the output compare is also required. (See "Chapter 33 Output Compare Unit (OCU) (Page No.515)".)
• Reset.
When a reset occurs (the INITX pin input, the watchdog reset, the software reset), the Free-Run timer is cleared.
• Write "0000H" while the Free-Run timer is stopped.
The count value will be set to "0000 H", when "0000 H" is written while the Free-Run timer is stopped.
• With the overflow of the Free-Run timer, the count value returns to "0000 H".
31.7.5 What interrupt registers are used?
Setting of the Free-Run timer interrupt vector and the Free-Run timer interrupt level
The relationship among the Free-Run timer number, interrupt levels and vectors is shown in the table below.
See "Chapter 21 Interrupt Control (Page No.219)" about the details of interrupt levels and interrupt vectors.
Number
Free-Run Timer 0
Interrupt Vectors (default)
#40
Address: 0FFF5CH
Free-Run Timer 1
#41
Address: 0FFF58H
Free-Run Timer 2
#42
Address: 0FFF54H
Free-Run Timer 3
#43
Address: 0FFF50H
Interrupt level setting bits (ICR[4:0])
Interrupt level register (ICR12)
Address: 00044CH
Interrupt level register (ICR13)
Address: 00044DH
Since the interrupt request flag (TCCS:IVF) is not cleared automatically, make sure to clear it with software
before returning from the interrupt process. (Write "0" in the IVF bit)
31.7.6 Interrupt Types
There is only one type of interrupt, and it is generated at the overflow of the free-run timer. (Selection is not
required)
31.7.7 How to enable interrupts
Enable interrupt request bit, interrupt flag
Use interrupt request enable bit (TCCS:IVFE) to enable interrupts.
Interrupt request enable bit (IVFE)
Disable interrupt requests
Enable interrupt requests
Set to "0"
Set to "1"
Use interrupt flag (TCCS:IVF) to clear interrupt requests.
Clear interrupt requests
500
Interrupt flag (IVF)
Write "0"
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Chapter 31 Free-Run Timer (FRT)
31.7
MB91460N series
31.7.8 How to stop the Free-Run timer
Set with count operation bit (TCCS: STOP).
See "31.7.3 How to enable / disable the count operation of the Free-Run timer (Page No.499)".
31.7.9 How are the Free-Run timer assigned to ICU and OCU?
• The value of Free-Run timer 0 can be used as capture data by ICU0 and ICU1
• The value of Free-Run timer 1 can be used as capture data by ICU2 and ICU3
• The value of Free-Run timer 2 can be used as compare data by OCU0 and OCU1
• The value of Free-Run timer 3 can be used as compare data by OCU2 and OCU3
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31.8
MB91460N series
31.8 Caution
• Clearing the Free-Run timer
• When a reset occurs (the INITX pin input, the watchdog reset, the software reset), the counter is
initialized to "0000H" and the counting is running.
• When the Free-Run timer is cleared by software, the counter is cleared and the clear request is
generated almost at the same time. If the counter is cleared by the compare-match, it is cleared when it
is counted up.
• After writing "1" in the clear bit (CLR), this request (CLR=1) is cleared at the same clear timing of the
Free-Run timer. When the clear operation of this CLR and writing "1" to the clear bit occurs at the same
time, the clear bit (CLR) keeps "1", and after the next time the timer is cleared, it is cleared. (As a result,
the Free-Run timer is cleared twice.)
• The counter clear operation (the software, the overflow, and the compare-match) of the Free-Run timer is
enabled while the Free-Run timer is counting. To clear while the Free-Run timer is stopped, write 0000H
in the timer count data register.
• Write to the timer data register
When writing the value in the Free-Run timer, make sure to do so while the Free-Run timer is stopped
(STOP=0), and with word access.
• External clock operation
• The pulse width required for the external clock is 2/CLKP minimum.
• When using an external clock, the timing of the compare-match output and the interrupt occurrence is the
same as the next count clock timing after the compare-match. Therefore, to allow the compare-match
output and interrupt generation, an external clock input of at least 1 clock is required after the comparematch.
• Read/modify/write
The interrupt flag (IVF) is always read as "1" in read/modify/write.
• Interrupt flag
If the interrupt flag set to "1" and cleared to "0" by software simultaneously, the flag setting operation
overrides the flag clearing operation.
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Chapter 32 Input Capture Unit (ICU)
32.1
MB91460N series
Chapter 32 Input Capture Unit (ICU)
32.1 Overview
The input capture unit (ICU) stores the free-run timer value if an edge is detected at an ICU input pin. Using
this stored value it is possible to calculate the time between edges from the external signal.
This unit can be configured to detect rising and/or falling edges.
Figure 32.1-1 Block diagram of Input Capture (Example of channels 0/1)
Buffer 0
ICU0
Edge
detection
circuit
Capture
Interrupt
Input Capture 0
Free-Run timer 0
ICU1
Edge
detection
circuit
Capture
Interrupt
Input Capture 1
Buffer 1
32.2 Features
• Format: Edge detection circuit + 16 bit buffer (capture register)
• Quantity: 2 groups = 4 channels (input capture channels 0/1, 2/3)
• Compatible timers:
Input capture channels 0/1 use Free-Run timer 0
Input capture channels 2/3 use Free-Run timer 1
• Edge Detection: Rising/falling/both edges
• Interrupt: Edge detection
• Capture value: Timer value (0000H-FFFFH)
• Timer: Uses Free-Run timer 0
• Precision: 4/CLKP, 16/CLKP, 32/CLKP, 64/CLKP (Free-Run timer count clock)
Figure 32.2-1 Functionality of Input Capture
External signal
Free-Run
timer value
A
t
Buffer value
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Chapter 32 Input Capture Unit (ICU)
32.3
MB91460N series
32.3 Configuration
Figure 32.3-1 Configuration Diagram for Input Capture
Input capture 0,1
Edge detection polarity
From port
data register
EG01,00
ICS01: bit 1, bit 0
0 0
No edge detection
0 1
Rising edge detection
1 0
Falling edge detection
1 1
Both edges detection
ICE0
Capture data register 0
P14 PFR: bit 0
GP Port
0
ICU input
1
ICS01:bit 4
0 Disable interrupt requests
1 Enable interrupt requests
IPCP0 (CP15 to CP0)
Edge detection circuit
ICU0 / P14.0
ICP0
Capture
Port read
0
ICS01:bit 6
0
Interrupt not present
1
Interrupt present
WRITE 0: Flag clear
Free-Run timer 0
Input capture 0
Interrupt (#92)
1
TCDT
Port read
Edge detection circuit
ICU1 / P14.1
P14 PFR: bit 1
GP Port
0
ICU input
1
ICP1
Capture
0
Interrupt not present
1
Interrupt present
WRITE 0: Flag clear
IPCP1 (CP15 to CP0)
0
1
Capture data register 1
EG11,10
ICS01: bit 3, bit 2
0 0
No edge detection
Rising edge detection
0 1
1 0
Falling edge detection
1 1
Both edges detection
Input capture 1
Interrupt (#93)
1
ICE1
Edge detection polarity
From port
data register
0
ICS01:bit 7
ICS01:bit 5
Disable interrupts
Enable interrupts
Figure 32.3-2 Register List
Input C apture 0
Addres s
000184 H
B it 15
14
11
9
13
12
10
C P 15 C P 14 C P 13 C P 12 C P 11 C P 10 C P 9
B it
8
CP8
7
CP7
6
CP6
5
4
CP5 CP4
3
2
CP3 CP2
1
CP1
0
C P 0 IP C P 0
000181 H
7
IC P 1
6
IC P 0
5
IC E 1
4
IC E 0
3
E G 11
2
E G 10
1
E G 01
0
E G 00 IC S 01
(C apture c ontrol 01)
000402 H
IC U7
IC U6
IC U5
IC U4
IC U3
IC U2
IC U1
IC U0 P F R 14
(P ort func tion 14)
000466 H
---
---
---
IC R 4
IC R 3
IC R 2
IC R 1
IC R 0 IC R 38
(Interrupt level)
0F F E 8C H
(Input c apture data 0)
(Interrupt vec tor #92)
32B its
* F or information on IC R regis ter and interrupt vec tor, s ee the s ec tion entitled " Interrupt C ontrol" .
Input C apture 1
Addres s
000186 H
10
B it 15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
C P 15 C P 14 C P 13 C P 12 C P 11 C P 10 C P 9 C P 8 C P 7 C P 6 C P 5 C P 4 C P 3 C P 2 C P 1 C P 0 IP C P 1
000181 H
B it
7
IC P 1
6
IC P 0
5
IC E 1
4
IC E 0
3
E G 11
2
E G 10
1
E G 01
0
E G 00 IC S 01
(C apture c ontrol 01)
000402 H
IC U7
IC U6
IC U5
IC U4
IC U3
IC U2
IC U1
IC U0 P F R 14
(P ort func tion 14)
000466 H
---
---
---
IC R 4
IC R 3
IC R 2
IC R 1
IC R 0 IC R 38
(Interrupt level)
0F F E 88 H
32B its
(Input c apture data 1)
(Interrupt vec tor #93)
* F or information on IC R regis ter and interrupt vec tor, s ee the s ec tion entitled " Interrupt C ontrol" .
Note: For information about ICR registers and interrupt vectors, see "Chapter 21
No.219)".
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Interrupt Control (Page
CM44-10149-1E
Chapter 32 Input Capture Unit (ICU)
32.4
MB91460N series
32.4 Register
32.4.1 IPCP: Input Capture Data Register
These registers store the Free-Run timer content after detecting an external signal edge (rising and/or falling)
on a pin.
The IPCP0 and IPCP1 store the content of the Free-Run timer 0.
The IPCP2 and IPCP3 store the content of the Free-Run timer 1.
•
•
•
•
IPCP0
IPCP1
IPCP2
IPCP3
(Input capture 0): Address 000184H (Access: Half-word, Word)
(Input capture 1): Address 000186H (Access: Half-word, Word)
(Input capture 2): Address 000188H (Access: Half-word, Word)
(Input capture 3): Address 00018AH (Access: Half-word, Word)
15
CP15
X
R/WX
14
CP14
X
R/WX
13
CP13
X
R/WX
12
CP12
X
R/WX
11
CP11
X
R/WX
10
CP10
X
R/WX
9
CP9
X
R/WX
8
CP8
X
R/WX
7
CP7
X
R/WX
6
CP6
X
R/WX
5
CP5
X
R/WX
4
CP4
X
R/WX
3
CP3
X
R/WX
2
CP2
X
R/WX
1
CP1
X
R/WX
0
CP0
X
R/WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• The count value of the Free-Run timer 0 is stored in the input signal from the external pin (ICU0, ICU1), using a
change (edge) in the signal selected by the active edge selection bit (ICS01:EG[01:00]), (ICS01:EG[11:10]).
• Input capture 0 and input capture 1 store the count value of the Free-Run timer.
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Chapter 32 Input Capture Unit (ICU)
32.4
MB91460N series
32.4.2 ICS: Input Capture Control Register
A register for controlling input capture
• ICS01 (Input capture 0, 1): Address 000181H (Access: Byte)
• ICS23 (Input capture 2, 3): Address 000183H (Access: Byte)
7
ICP1
0
R(RM1),W
6
ICP0
0
R(RM1),W
5
ICE1
0
R/W
4
ICE0
0
R/W
3
EG11
0
R/W
2
EG10
0
R/W
1
EG01
0
R/W
0
EG00
0
R/W
bit
Initial value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit7: Input capture 1 interrupt flag
Status
ICP1
0
1
Read
Write
No interrupt present
Interrupt present (edge detection present)
Clear flag
No effect on operation
• When the signal change (edge) selected by the active capture edge selection bit (EG[11:10]) is detected
on the input from an external pin, the flag is set to "1".
• To activate the interrupt request it is necessary to set the interrupt request enable bit (ICE1=1).
• If the interrupt flag (ICP1) is set to "1" and is cleared to "0" by software simultaneously, the interrupt flag
will be set to "1".
• bit6: Input capture 0 interrupt flag
Status
ICP0
0
1
Read
Write
No interrupt present
Interrupt present
Clear flag
No effect on operation
• When the signal change selected by the active capture edge selection bit (EG[01:00]) is detected on the
input from an external pin (CS0), the flag is set to "1".
• To activate the interrupt request, the interrupt request enable setting (ICE1=1) is necessary.
• If the interrupt flag (ICP0) is set to "1" and is cleared to "0" by software simultaneously, the interrupt flag
will be set to "1".
• bit5: Input capture 1 interrupt request enable
ICE1
0
1
Operation
Interrupt request disabled
Interrupt request enabled
• If input capture 1 interrupt request enable bit is set to "1", input capture 1 interrupt request ICP1 will be
enabled.
• bit4: Input capture 0 interrupt request enable
ICE0
0
1
Operation
Interrupt request disabled
Interrupt request enabled
• If input capture 0 interrupt request enable bit is set to "1", input capture 0 interrupt request ICP0 will be
enabled.
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Chapter 32 Input Capture Unit (ICU)
32.4
MB91460N series
• bit3, bit2: Input capture 1 active edge selection
EG11
0
0
1
1
EG10
0
1
0
1
Edge selection
Input capture unit is stopped
Rising edge
Falling edge
Both edges (rising edge and falling edge)
• Select the active capture edge for the input capture signal from external pin (ICU1)
• If the active edge selection bit is "00", input capture 1 is stopped.
• bit1, bit0: Input capture 0 active edge selection
EG01
0
0
1
1
EG00
0
1
0
1
Edge selection
Input capture unit is stopped
Rising edge
Falling edge
Both edges (rising edge and falling edge)
• Select the active capture edge for the input capture signal for external pin (ICU0).
• When the active edge selection bit is "00", input capture 0 is stopped.
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Chapter 32 Input Capture Unit (ICU)
32.5
MB91460N series
32.5 Operation
The input capture operation is described below.
32.5.1 Capture Timing, Interrupt Timing
Figure 32.5-1 Operation of Input Capture (Capture Timing, Interrupt Timing)
External Pin (ICUn)
(1)
Peripheral
clock (CLKP)
(2)
Active edge
Free-run timer 0
N
N+1
(3)
Capture register
Interrupt
request
N+1
(4)
FFFFH
Free-Run
timer 0
count
0000H
Time
Reset
Input
capture
Interrupt
request
(1)
(2)
(3)
(4)
508
Rising edge of input signal
Internal signal generated by edge detection (synchronous with peripheral clock)
Store Free-Run timer value in capture register (capture)
Input capture interrupt generation (ICU0, ICU1=1)
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Chapter 32 Input Capture Unit (ICU)
32.5
MB91460N series
32.5.2 Input Capture Edge Specification and Operation
Figure 32.5-2 Input Capture Edge Specification and Operation
Overflow
(IVF)
FFFFH
Count value C
Free-Run
timer 0
count value
Count value B
Count value A
Count value D
Time
0000H
Reset
Input capture
Rising
edge
Capture data
register
(1)
(2)
Indeterminate
Interrupt
request
Count value A
(3)
Input capture
Falling
edge
(4)
Capture data
register
(5)
Count value C
Indeterminate
Interrupt
request
(6)
7)
(7)
Input capture
Both
edges
Capture data
register
(11)
(8)
Indeterminate
Interrupt
request
Count value B
The flag is reset by software
(9)
(12)
Count value D
(13)
(10)
• When specifying rising edge
(1) Detection of rising edge of input signal
(2) Storage of Free-Run timer value in capture register (capture)
(3) Input capture interrupt generation
• When specifying falling edge
(4) Detection of input signal falling edge
(5) Storage of Free-Run timer value in capture register (capture)
(6) Input capture interrupt generation
• Both edges
(7)
(8)
(9)
(10)
(11)
(12)
Detection of input signal rising edge
Storage of Free-Run timer value in capture register (capture)
Input capture interrupt generation
Clear interrupt flag (ICS01.ICP0), (ICS01.ICP1) in software
Detection of input signal falling edge
Storage of Free-Run timer value in capture register (capture)
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Chapter 32 Input Capture Unit (ICU)
32.6
MB91460N series
(13) Input capture interrupt generation
32.6 Settings
Table 32.6-1 Settings Necessary for Using Input Capture
Settings
Setting register
Free-Run timer settings
Free-Run timer activation
See "Chapter 31 Free-Run Timer (FRT) (Page No.491)"
Input pin ICU0 to ICU3 settings
Active edge polarity selection for external input
Port function register (PFR14.0 to PFR14.3)
Extra port function register (EPFR14.0 to EPFR14.3)
Input capture control register (ICS01, ICS23, ICS45, ICS67)
Setting
procedure*
–
32.7.2
32.7.1
*: For the setting procedure, refer to the section indicated by the number.
Table 32.6-2 Required Settings for ICU Interrupt
Settings
Input Capture interrupt vector,
Input capture interrupt level settings
Input capture interrupt settings
Interrupt request clear
Interrupt request enable
Settings register
Setting
procedure*
See "Chapter 21 Interrupt Control (Page No.219)"
32.7.3
Input capture control register (ICS01, ICS23)
32.7.5
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 32 Input Capture Unit (ICU)
32.7
MB91460N series
32.7 Q&A
32.7.1 What are the types of active edge polarity for external input, and how to select
them?
The active edge polarity types consist of rising, falling, and both, for a total of 3, and are set using the external
input active edge selection bit (ICS01:EG[01:00]) and (ICS01:EG[11:10]), (ICS23:EG[01:00]) and
(ICS23:EG[11:10]).
External input active edge polarity bit
(EG[01:00]), (EG[11:10])
Select "00"
Select "10"
Select "11"
Operation
To select rising edge
To select falling edge
To select both edges
32.7.2 What about setting the external input pins (ICU0 to ICU3)?
Use the port function register and extra port function bits (PFR14.x/EPFR14.x).
Operation
To set it to the external input pins (ICU0)
To set it to the external input pins (ICU1)
To set it to the external input pins (ICU2)
To set it to the external input pins (ICU3)
Port function (PFR14.x)
Set PFR14.0 to "1"
Set PFR14.1 to "1"
Set PFR14.2 to "1"
Set PFR14.3 to "1"
Extra Port function (EPFR14.x)
Set EPFR14.0 to "0"
Set EPFR14.1 to "0"
Set EPFR14.2 to "0"
Set EPFR14.3 to "0"
Remark: When setting the Extra port function register EPFR14.x to "1" the corresponding input capture macro
is internally connected to the corresponding LIN-USART for LIN Sync Field measurement. Hence, with this
setting the corresponding ICU channel is not available as external input.
32.7.3 What about interrupt-related registers?
Input capture interrupt vector and input capture interrupt level settings
The relationship among input capture number, interrupt level, and vector is explained in the following table.
For more information on interrupt level and interrupt vectors, see "Chapter 21 Interrupt Control (Page
No.219)".
Number
Input Capture 0
Interrupt vector (Default)
#92
Address: 0FFE8CH
Input Capture 1
#93
Address: 0FFE88H
Input Capture 2
#94
Address: 0FFE84H
Input Capture 3
#95
Address: 0FFE80H
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR38)
Address: 000466H
Interrupt level register (ICR39)
Address: 000467H
Interrupt flags (ICS01:ICP0), (ICS01:ICP1), (ICS23:ICP0), (ICS23:ICP1) are not automatically cleared, so
please set the input capture interrupt flag (ICP1, ICP0) to "0" to clear them before returning from interrupt
processing.
32.7.4 What are the types of interrupts?
There is only one type of interrupt, and it is generated by input signal edge detection.
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32.7
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32.7.5 How to enable interrupts
Interrupt request enable bit, interrupt flag
Interrupts are enabled via interrupt request enable bit (ICS01:ICE0), (ICS01:ICE1), (ICS23:ICE0),
(ICS23:ICE1).
Disable interrupt requests
Enable interrupt requests
Interrupt request enable bit (ICE0), (ICE1)
Set to "0"
Set to "1"
Clearing of interrupts is done using interrupt flag (ICS01:ICP0), (ICS01:ICP1), (ICS23:ICP0), (ICS23:ICP1).
Interrupt clear
512
Interrupt flag (ICP0), (ICP1)
Write "0"
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32.7
MB91460N series
32.7.6 How to measure the pulse width of the input signal
• "H" Width measurement:
Specify both edges for edge detection.
First detect the rising edge, then detect the falling edge.
Pulse width = {value stored during falling (input capture register value)
+ "10000H" × Overflow frequency
– value stored during rising (input capture register value)}
× Count clock width of Free-Run timer
Example: value stored during falling = 2320H, Value stored during rising = A635H,
Overflow frequency = 1, count clock = 125ns
==> pulse width = (2320H+10000H-A635H) × 125ns = 3997.375μs
• Cycle measurement:
Specify rising (or falling) for edge detection.
Detect edge 2 times.
Cycle = {Second stored value (input capture register value)
+ "10000H" × Overflow frequency
– First stored value (input capture register value)}
× Count clock width of Free-Run timer
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32.8
MB91460N series
32.8 Caution
• Input capture data register
The value of the input capture data register during reset is indeterminate.
Read out of the input capture data register must always be done using 16 or 32 bit access.
• Read modify write
Input capture interrupt flag (ICP0), (ICP1) will be read as "1" when read with read modify write.
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Chapter 33 Output Compare Unit (OCU)
33.1
MB91460N series
Chapter 33 Output Compare Unit (OCU)
33.1 Overview
The Output compare unit reverses the level of the output pin (OCUn), if the compare register value matches
the timer value of the Free-Run timer.
Figure 33.1-1 Structure of output compare (Example of channels 0/1)
Interrupt
Output compare 0
OCU0
Compare 0
Latch
=
Toggle
Output
Clear
Free-Run Timer 2
Latch
=
OCU1
Compare 1
Interrupt
Output compare 1
33.2 Features
Figure 33.2-1 Output waveform: Toggle output 4 channel
Trigger output 4 channel
T1 or T(max.)
T1
(OCU0 Pin/OCU2 Pin)
(OCU1 Pin/OCU3 Pin)
T2
PWM Output
(OCU1/OCU3)
2 channel
T2
T1
• Format:
16 bit compare register + Compare circuit
• Quantity:
2 groups = 4 channels (output compare ch.0/ch.1, ch.2/ch.3)
• Compatible timers:Output compare channels 0/1 use Free-Run timer 2
Output compare channels 2/3 use Free-Run timer 3
• Operation on compare match:
• Reversal of pin output value (toggle output)
• Free-Run timer clear
• Interrupt generation
• Count precision: 4/CLKP, 16/CLKP, 32/ CLKP, 64/ CLKP (dependent on Free-Run timer)
• Toggle change width (T): 1 × count precision - 10000H × count precision
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33.3
• Interrupt:
• Others:
MB91460N series
Compare-match interrupt
Setting of initial output level value is possible ("H"/"L")
Pins not used for OCU output can be used as general-purpose ports
33.3 Configuration Diagram
Figure 33.3-1 Configuration Diagram for Output compare
Output Compare 0,1
ICE0 OCS01: bit4
0 Disable interrupts
1 Enable interrupts
ICP0 OCS01: bit6
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
CST 0 OCS01: bit0
0 Disable compare operation
1 Enable compare operation
Compare register 0
OT D0 OCS01: bit8
Low fixed
0
High fixed
1
* Compare operation only
writable when stopped
OCCP0
IVF
TCCS2: bit6
0 Overflow not present
Overflow present
1
OCU0 Interrupt (#100)
External clock (for Free-Run timer 2)
General-use port read
PFR15.0
0 General-use Port
1
OUT0
From general-use
port register
Compare
0
Match -> Latch
reversal
0
Free-Run timer 2
TCDT2
1
1
CLR TCCS2:bit2
0
No effect
1
Clear
0
Compare
1
Latch
CMOD
OCS01: bit12
0
OCCP1 match alone inverts OP1 latch.
1
OCCP0 or OCCP1 match inverts OP1 latch.
OCU1/TOT1/P15.1
Latch
From general-use
port register
CST 1 OCS01: bit1
0 Disable compare operation
1 Enable compare operation
0
PFR15.1
0 General-use Port
1
OUT1
OT D1 OCS01: bit9
0 Low fixed 1c
1
High fixed
* Compare operation only
writable when stopped
OCCP1
OCU0/TOT0/P15.0
1
Match -> Latch reversal
OR
Compare register 0
0
General-use port read
External clock (for Free-Run timer 2)
0
T CCS2 : bit 3
MODE
0
No clear on compare-match
1
Clear on compare-match
ICP1 OCS01: bit 7
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
1
OCU1 Interrupt (#100)
ICE1 OCS01: bit5
0 Disable interrupts
1 Enable interrupts
Figure 33.3-2 Register List
Note: For information about ICR registers and interrupt vectors, see "Chapter 21
No.219)".
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33.4
MB91460N series
33.4 Registers
33.4.1 OCS: Output Control Register
A register for controlling the operation of output compare.
• OCS01 (Output compare 0, 1): Address 00018CH (Access: Byte, Half-word, Word)
• OCS23 (Output compare 2, 3): Address 00018EH (Access: Byte, Half-word, Word)
15
–
1
R1/W1
14
–
1
R1/W1
13
–
1
R1/W1
12
CMOD
0
R/W
11
–
1
R1/W1
10
–
1
R1/W1
9
OTD1
0
R/W
8
OTD0
0
R/W
7
ICP1
0
R(RM1),W
6
ICP0
0
R(RM1),W
5
ICE1
0
R/W
4
ICE0
0
R/W
3
–
1
R1/W1
2
–
1
R1/W1
1
CST1
0
R/W
0
CST0
0
R/W
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit15 to bit13: undefined
Writing does not affect the operation. The read out value is "1".
• bit12: Reverse Mode
CMOD
0
1
Operation Mode
Independent operation (the output level reversal operation of pins OCU0, OCU1 is independent)
Combined operation
(OCU1 output pin level is inverted when output compare 0 or output compare 1 is matched in the
compare operation.)
• Specifies the output level reversal operation of pin OCU1 when Free-Run timer count value TCDT2
matches compare registers OCCP0, OCCP1.
• When the reverse mode bit is set to "1", the operation is as follows:
OCU0 pin: output reverses when Free-Run timer TCDT2 matches compare register 0 (OCCP0)
OCU1 pin: output reverses when Free-Run timer TCDT2 matches compare register 1 (OCCP1)
• When the reverse mode bit is set to "0", the operation is as follows:
OCU0 pin: output reverses when Free-Run timer TCDT2 matches compare register 0(OCCP0)
OCU1 pin: output reverses when Free-Run timer TCDT2 matches compare register 0 (OCCP0) or
compare register 1 (OCCP1)
Note: Reversal mode does not allow interrupts, even with cooperative operation (CMOD=1).
• For output from pins OCU0, OCU1, registers PFR15.0, PFR15.1 must be set.
• bit11, bit10: Undefined
Writing does not affect the operation. The read value is "1".
• bit9: Pin-level settings (output compare 1)
OTD1
0
1
Operation
Set the output level of pin OCU1 to "L"
Set the output level of pin OCU1 to "H"
To perform output on pin OCU1, general-purpose port settings must be performed.
• bit8: Pin-level settings (output compare 0)
OTD0
0
1
Operation
Set the output level of pin OCU0 to "L"
Set the output level of pin OCU0 to "H"
• To perform output on pin OCU0, general-purpose port settings must be performed.
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• bit7: Interrupt flag (output compare 1)
Status
ICP1
0
1
Read
No Interrupt present
Interrupt present
Write
Clear flag (ICP1)
No effect on operation
• If Free-Run timer count value TCDT2 matches the output compare register OCCP1, ICP1 becomes "1".
• Interrupt request is enabled when the interrupt enable bit (ICP1) is set to "1".
• If the interrupt request and the flag resetting occur simultaneously, the flag is set to "1" (The flag setting
has higher priority than clearing the flag).
• When using an external clock as the Free-Run timer operation clock, at least one external clock input is
necessary after compare match for output compare-match output and interrupt generation.
• bit6: Interrupt flag (output compare 0)
Status
ICP0
0
1
Read
No Interrupt present
Interrupt present
Write
Clear flag (ICP0)
No effect on operation
• If Free-Run timer count value TCDT2 matches output compare register OCCP0, ICP0 becomes "1".
• Interrupt request is enabled when the interrupt enable bit (ICP0) is "1".
• If the interrupt request and the flag resetting occur simultaneously, the flag is set to "1" (The flag setting
has higher priority than clearing the flag).
• When using an external clock as the Free-Run timer operation clock, at least one external clock input is
necessary after compare match for output compare-match output and interrupt generation.
• bit5: Interrupt request enable (output compare 1)
ICE1
0
1
Status
Disable output compare 1 interrupt requests
Enable output compare 1 interrupt requests
• bit4: Interrupt request enable (output compare 0)
ICE0
0
1
Status
Disable output compare 0 interrupt requests
Enable output compare 0 interrupt requests
• bit3, bit2: Undefined
Writing does not affect the operation. The read value is always "1".
• bit1: Enable operation requests (output compare 1)
CST1
0
1
Operation
Stop operation of output compare 1
Enable operation of output compare 1
• A bit that enables a comparison operation between the Free-Run timer count value and the output
compare register (TCDT2 and OCCP1).
• Before enabling the operation, always set a value to compare register OCCP1.
• If the Free-Run timer is stopped, output compare also stops.
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• bit0: Enable operation requests (output compare 0)
CST0
0
1
Operation
Disable output compare 0 operation
Enable output compare 0 operation
• A bit that enables a comparison operation between the Free-Run timer count value and the output
compare register (TCDT2 and OCCP0).
• Before enabling the operation, always set a value to compare register OCCP0.
• If the Free-Run timer is stopped, output compare also stops.
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33.4.2 OCCP: Compare Register
Register that sets the value to be compared to the 16 bit Free-Run timer count value.
•
•
•
•
OCCP0 (OCU0): Address 000190H (Access: Half-word, Word)
OCCP1 (OCU1): Address 000192H (Access: Half-word, Word)
OCCP2 (OCU2): Address 000194H (Access: Half-word, Word)
OCCP3 (OCU3): Address 000196H (Access: Half-word, Word)
15
C15
X
R/W
14
C14
X
R/W
13
C13
X
R/W
12
C12
X
R/W
11
C11
X
R/W
10
C10
X
R/W
9
C9
X
R/W
8
C8
X
R/W
7
C7
X
R/W
6
C6
X
R/W
5
C5
X
R/W
4
C4
X
R/W
3
C3
X
R/W
2
C2
X
R/W
1
C1
X
R/W
0
C0
X
R/W
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• The values of the OCCP0 and OCCP1 compare registers are compared with the TCD2 value of the FreeRun timer2.
• The values of the OCCP2 and OCCP3 compare registers are compared with the TCD3 value of the FreeRun timer3.
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33.5
MB91460N series
33.5 Operation
33.5.1 Output Compare Output (Independent Reversal) CMOD=0
Figure 33.5-1 Output Compare Output (CMOD=0)
Peripheral
clock (CLKP)
(6)
Free-Run timer 2
Compare register value
BFFEH
BFFFH
0000H
0001H
BFFFH
(5)
Compare-match signal
(7)
OCU pin output
(8)
Interrupt
request
BFFFH
Free-Run
timer 2
count
(4)
0000H
(6)
Free-Run timer 2 clear (1)
Time
Compare-match clear
Compare-match clear
(2)
Compare register value
CST
OCU Output
Interrupt request
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
BFFFH
(3)
(7)
(8)
Clear by
software
Free-Run timer clear/reset
Compare value setting
Enable compare operation (CST=1)
Free-Run timer count up (example of 1 clock in 4)
Compare Free-Run timer value and compare value and match (compare match).
Free-Run timer clear from compare match (Free-Run timer 2)
OCU output level reversal
Compare match interrupt request generation
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33.5.2 Output Compare Output (Cooperative Reversal) CMOD=1
Figure 33.5-2 Output Compare Output (CMOD=1)
(9)
BFFFH
Free-Run
timer 2
count
(8)
(5)
4000H
(4)
0000H
Free-Run timer 2 clear
Compare-match clear
(1)
Compare-match clear
Time
(10)
(2)
Compare register 0
BFFFH
(2)
Compare register 1
4000H
CST 0
(3)
CST 1
(3)
(11)
OCU0 output
CMOD=0
OCU1 output
(6)
(11)
OCU0 output
CMOD=1
OCU1 output
(6)
(11)
Interrupt request 0
Interrupt request 1
(7)
Cleared by software
Cleared by software
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Free-Run timers clear/reset (only through Compare 0, not through Compare 1)
Compare 0 and compare 1 value settings
Enable compare operation
Free-Run timer count up
Compare 1 match
OCU1 output level reversal
Compare 1 match interrupt
Free-Run timer count up
Compare 0 match
Free-Run timer is cleared (just if Compare 0 match occurs, not for compare 1 match)
(10) OCU0 output level reversal
When CMOD=1, OCU1 output level also reverses
(11) Compare 0 match interrupt
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33.6
MB91460N series
33.6 Settings
Table 33.6-1 Settings Necessary for Using Output Compare
Settings
Setting Register
See "Chapter 31 Free-Run Timer (FRT) (Page
No.491)"
Compare register (OCCP0 to OCCP3)
Free-Run timer setting
Compare value setting
Compare mode setting
Output control register
(OCS01, OCS23)
Stop compare operation
Set initial level of compare pin output
Port function register (PFR15.0 to PFR15.3)
Extra port function register (EPFR15.0 to
EPFR15.3)
Timer control register
(TCCS2, TCCS3)
See "Chapter 31 Free-Run Timer (FRT) (Page
No.491)"
Output control register
(OCS01, OCS23)
Set OCU0 to OCU3 pins to output
Clear Free-Run timer
Enable compare operation (activate)
Setting
Procedure*
--See 33.7.1
See 33.7.2
See 33.7.3
See 33.7.4
See 33.7.5
See 33.7.6
See 33.7.7
*: For the setting procedure, refer to the section indicated by the number.
Table 33.6-2 Item Necessary to Clear the Free-Run Timer upon Compare-match.
Setting
Setting Register
Setting
Procedure*
Select Free-Run timer clear mode
Timer control register
(TCCS2, TCCS3)
See "Chapter 31 Free-Run Timer (FRT) (Page
No.491)"
See 33.7.8
*: For the setting procedure, refer to the section indicated by the number.
Table 33.6-3 Item Necessary for Performing Interrupts
Setting
Output compare interrupt vector,
output compare interrupt level setting
Output compare interrupt setting
Clear interrupts
Enable interrupt requests
Setting register
Setting
Procedure*
See "Chapter 21 Interrupt Control (Page No.219)"
See 33.7.9
Output control register
(OCS01, OCS23)
See 33.7.11
*: For the setting procedure, refer to the section indicated by the number.
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33.7 Q & A
33.7.1 How to set the compare value
Write the compare value to compare registers OCCP0 to OCCP3.
33.7.2 How to set the compare mode (for OCU1, OCU3 output)
It is set using the corresponding compare mode bits (OCS01:CMOD), (OCS23:CMOD).
Operation
To reverse OCU1 output using a compare-match from only Free-Run timer
2 and compare register 1
To reverse OCU3 output using a compare-match from only Free-Run timer
3 and compare register 3
To reverse OCU1 output using a compare-match from Free-Fun timer 2
and compare register 0, as well as Rree-Run timer 0 and compare register 1
To reverse OCU3 output using a compare-match from Free-Run timer 3
and compare register 2, as well as Free-Run timer 1 and compare register 3
Compare mode bit
Set OCS01:CMOD bit to "0"
Set OCS23:CMOD bit to "0"
Set OCS01:CMOD bit to "1"
Set OCS23:CMOD bit to "1"
With no relation to CMOD bit,
OCU0 output is reversed by a compare-match between Free-Run timer 2 and compare register 0 only.
OCU2 output is reversed by a compare-match between Free-Run timer 3 and compare register 2 only.
33.7.3 How to enable/disable the compare operation
It is enabled/disabled via the compare operation enable bit (OCS01:CST[1:0]), (OCS23:CST[1:0]).
Operation
To stop (disable) the compare operation
To enable compare operation
Compare
Compare 0
Compare 1
Compare 2
Compare 3
Compare 0
Compare 1
Compare 2
Compare 3
Compare operation permission bit
Set OCS01:CST[0] to "0"
Set OCS01:CST[1] to "0"
Set OCS23:CST[0] to "0"
Set OCS23:CST[1] to "0"
Set OCS01:CST[0] to "1"
Set OCS01:CST[1] to "1"
Set OCS23:CST[0] to "1"
Set OCS23:CST[1] to "1"
33.7.4 How to set the initial level of the compare pin output
Set it with compare pin output specification bit (OCS01:OTD[1:0]), (OCS23:OTD[1:0]).
Operation
To set compare 0 pin to "L"
To set compare 0 pin to "H"
To set compare 1 pin to "L"
To set compare 1 pin to "H"
To set compare 2 pin to "L"
To set compare 2 pin to "H"
To set compare 3 pin to "L"
To set compare 3 pin to "H"
524
Compare pin output specification bit
Set OCS01:OTD0 to "0"
Set OCS01:OTD0 to "1"
Set OCS01:OTD1 to "0"
Set OCS01:OTD1 to "1"
Set OCS23:OTD0 to "0"
Set OCS23:OTD0 to "1"
Set OCS23:OTD1 to "0"
Set OCS23:OTD1 to "1"
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MB91460N series
33.7.5 How to set the output for compare pins OCU0 to OCU3
The pin is configured as output from the OCU through the PFR15[3:0].
Operation
To set compare 0 pin (OCU0) to output
To set compare 1 pin (OCU1) to output
To set compare 2 pin (OCU2) to output
To set compare 3 pin (OCU3) to output
Port function bit
Set PFR15.0 bit to "1"
Set PFR15.1 bit to "1"
Set PFR15.2 bit to "1"
Set PFR15.3 bit to "1"
Extra port function bit
Set EPFR15.0 bit to "0"
Set EPFR15.1 bit to "0"
Set EPFR15.2 bit to "0"
Set EPFR15.3 bit to "0"
33.7.6 How to clear the Free-Run timer
The Free-Run timer is cleared through clear bits (TCCS2:CLR), (TCCS3:CLR).
Operation
To clear the Free-Run timer
Clear Bit (CLR)
Write "1"
For other methods, see "Chapter 31 Free-Run Timer (FRT) (Page No.491)".
33.7.7 How to enable the compare operation
Enable it through compare operation enable bit (OCS01:CST[1:0]), (OCS23:CST[1:0]).
See "33.7.4 How to set the initial level of the compare pin output (Page No.524)".
33.7.8 How to compare the Free-Run timer value with the compare register value and
clear the Free-Run timer when they match
It is compared and cleared through timer initialization condition bit (TCCS2:MODE), (TCCS3:MODE).
Operation
To clear Free-Run timer upon compare 0 match
To clear Free-Run timer upon compare 2 match
Timer initialization condition bit (MODE)
Set TCCS2:MODE to "1"
Set TCCS3:MODE to "1"
33.7.9 What are the interrupt-related registers?
Set the output compare interrupt vector and output compare interrupt level.
The relationship between output compare number, interrupt level, and vector is shown in the following table.
For detailed information on interrupt levels and interrupt vectors, see "Chapter 21 Interrupt Control (Page
No.219)".
Number
Output
Compare 0
Interrupt vector (default)
#100
Address: 0FFE6CH
Output
Compare 1
#101
Address: 0FFE68H
Output
Compare 2
#102
Address: 0FFE64H
Output
Compare 3
#103
Address: 0FFE60H
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR42)
Address: 00046AH
Interrupt level register (ICR43)
Address: 00046BH
Interrupt flags (OCS01:ICP[1:0]), (OCS23:ICP[1:0]), are not automatically cleared, so write "0" to the ICP[7:0]
bit before returning from interrupt processing to clear them.
33.7.10 What are the types of interrupts?
There is only one type of interrupt, generated upon a compare-match.
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33.7.11 How to enable interrupts
Enabling of interrupts is done with interrupt request enable bit (OCS01:ICE[1:0]), (OCS23:ICE[1:0]).
Interrupt request enable bit (ICE0, ICE1)
Set to "0"
Set to "1"
Interrupt request disabled
Interrupt request enabled
Interrupts are cleared with interrupt flags (OCS01:ICP[1:0]), (OCS23:ICP[1:0]).
Interrupt flag (ICP0, ICP1)
Write "0"
Interrupt clear
33.7.12 Compare value calculation procedure
• Toggle output pulse
Figure 33.7-1 (Example) To output a period: A, phase difference 1/4 phase pulse
A
OCU0
OP0
OCU1
OP1
Phase difference
1/4 1/4
Formula: Compare 0 value = (A/2) / count clock
Compare 1 value = (A/4) / count clock
(Count clock: time set with Free-Run timer)
Note: To clear Free-Run timer 2 on compare 0 match setting (TCCS2:MODE=1) and CMOD=0 setting are necessary.
Calculation example: A=1024us, count clock =125ns
Compare 0 value = (1024000 / 2) / 125 - 1 = 4095 = FFFH
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFH
• PWM output
Figure 33.7-2 (Example) To output a period: A, duty 1/4 to 3/4 ("L") PWM,
A
OCU1
OP1
1/4-3/4
Formula: Compare 0 value = A / count clock
Compare 1 value = (A/4) / count clock (when duty 1/4)
(A × 3/4) / count clock (when duty 3/4)
(count clock: time set with Free-Run timer)
Note: To clear Free-Run timer 0 on compare 0 match setting (TCCS0:MODE=1) and CMOD=1 setting are necessary.
Calculation example: A=1024us, count clock =125ns
Compare 0 value = 1024000 / 125 - 1 = 8191 = 1FFFH
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFH (when duty 1/4)
(1024000 × 3 / 4) / 125 - 1 = 1023 = BFFH (when duty 3/4)
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Chapter 33 Output Compare Unit (OCU)
33.8
MB91460N series
33.8 Caution
• Compare stop space during compare operation
As shown below, for one count directly after the compare value is written to the compare register, the
compare operation cannot be used.
Figure 33.8-1 Compare stop space
Compare
timing
Free-Run timer count value
N-2
N-1
N
N+1
N+2
N+3
Write to compare register
Compare register value
X
N
Compare stop space
In this case, a match signal
will not be generated!
• When CMOD=1 and OCCP0=OCCP1 setting, if a compare match is generated, the port will only reverse
once.
• Compare registers (OCCP0 to OCCP3) are set to the initial values. Always set a value before activating
them.
• The output compare operation needs to be disabled during the configuration of the output level.
• Output compare is synchronous with the Free-Run timer, so if the Free-Run timer is stopped the compare
operation also stops.
• Even when reversal mode specification (CMOD) is set to "1" and the compare operation is in cooperative
mode, interrupts are generated independently.
• When using an external clock as the Free-Run timer, compare-matches and interrupts are generated with
the following clock edge. To generate compare match output and interrupts, at least 1 clock cycle from
prescaled clock must be input to the external clock pin from the Free-Run timer after the compare-match.
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Chapter 33 Output Compare Unit (OCU)
33.8
528
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MB91460N series
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Chapter 34 Reload Timer (RLT)
34.1
MB91460N series
Chapter 34 Reload Timer (RLT)
34.1 Overview
The reload timer basically consists of a 16 bit down counter. This counter is decremented either by an external
trigger or by software. There is an external output pin associated to this module whose polarity level changes if
an underflow condition occurs.
Figure 34.1-1 Block diagram of the Reload Timer
Reload value
Software trigger
Interrupt
Reload Timer
Reload
External event
Internal clock
16-bit down counter
Underflow
Latch
TOT (n)
External event
Reversal
To PPG
To A/D
34.2 Features
Figure 34.2-1 Operation: 2 types of operation are possible
• One-shot Operation
Initial output level
Reversed output level
• Reload Operation
Initial output level
Reversed output level
Format: 16 bit down counter with reload register
Quantity: 4 (Output: 4 channels TOT[0:3])
Clock mode: Select from two modes
• Internal clock mode
Count clock: CLKP/2, CLKP/8, CLKP/32, CLKP/64, CLKP/128
Activation triggers (4 types)
• External event clock mode
Count clock
: External event (TIN[3:0] pins)
Count active edge: Rising/falling/both edges of external event
Activation trigger: Software trigger
Cycle
: Cycle = count clock × (reload value + 1)
(Example) When count clock = 16MHz, reload value = 15999
Cycle = 62.5ns × (15999+1) = 1.0ms
Count active edge: When in external event mode, choose from 3 types.
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Chapter 34 Reload Timer (RLT)
34.3
MB91460N series
• External trigger (rising /falling/both edges)
Interrupt: Interrupt generated by underflow
• PPG activation trigger source:
Reload timer 0 : PPG0, PPG1
Reload timer 1 : PPG2, PPG3
Reload timer 2 : PPG4, PPG5
Reload timer 3 : PPG6, PPG7
• A/D converter activation trigger source (Reload timer 7 : A/D)
34.3 Configuration
Figure 34.3-1 Configuration Diagram of the Reload Timer (Internal Clock Count)
Reload Timer 0 (Internal clock count)
TIN0
PFR14.0
GP Port
0
1 Reload Timer Input
From general-purpose
port output
Trigger selection
MOD2 to 0 TMCSRx: bit9 to bit7
Software trigger
0 0 0
0 0 1 External trigger rising edge
0 1 0 External trigger falling edge
0 1 1 External trigger both edges
Disabled
1 X X
TMRLR0
0
0
1
1
Trigger (load + counter activation)
Reload/activation/stop
control circuit
0
1
0
1
One-shot mode
Reload mode
"H" square wave during count
"L" square wave during count
"L" toggle output on count start
"H" toggle output on count start
Reload
Stop
CNTE
TMCSRx:bit1
0 Stop count (disable output)
1
Enable count
Counter
activation
.
Ch01 -> PPG0-PPG1
Stop
TOT0
Reload
Clock source
CLKP /25
CLKP /26
Selector
CLKP /23
0
1
Underflow
CLKP /2
TMR0
16 bit down counter (=timer)
CLKP /27
Latch,
output
change
From general-purpose
port output
EPFR15.0
OCU0 output
TOT0 output
1
TO T0/OCU0/P15.0
To general-purpose
port input
CSL2 to 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
TMCSRx: bit12 to bit10
Internal clock CLKP/2
Internal clock CLKP/23
Internal clock CLKP /25
(External event) *
Disabled
Internal clock CLKP /26
Internal clock CLKP /27
Disabled
INTE TMCSRx:bit3
0 Disable interrupts
1 Enable interrupts
UF
TMCSRx:bit2
0 Underflow not present
1 Underflow generation
WRITE 0: Flag clear
* For external events, see the next chart.
530
TMCSR:bit4, bit5
RELD OUTL
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1
Timer interrupt
(underflow)
0
TRG TMCSRx:bit0
No effect
0
1
Soft trigger
Selector
TIN0/ICU0/P14.0
16 bit reload register
0
To general-purpose
port input
CM44-10149-1E
Chapter 34 Reload Timer (RLT)
34.3
MB91460N series
Figure 34.3-2 Configuration Diagram of the Reload Timer (External event count)
Reload timer 0 (External event count)
16 bit reload register
TMRLR0
TRG TMCSR:bit0 Trigger (reload + counter activation)
No effect
0
1
Soft trigger
RELDOUTL
TMCSR: bit4, bit5
0
0
"H" square wave during count
One-shot mode
"L" square wave during count
0
1
"L" toggle output on count start
0
1
Reload mode
"H" toggle output on count start
1
1
Reload/activation/stop
control circuit
Stop
PFR14.0
To general-purpose
port input
Reload
Stop
GP Port
0
1 Reload Timer Input
Ch01 -> PPG0-PPG1
From general-purpose
port output
TOT0
0
1
Reload
Underflow
Selector
TIN0/ICU0/P14.0
Event source
TMR0
16 bit down counter
CSL2 to 0 TMCSR bit12 to bit10
Latch,
output
change
From general-purpose
port output
EPFR15.0
OCU0 output
TOT0 output
1
TO T0/OCU0/P15.0
0
TIN0
Counter
activation
.
CNTE TMCSR:bit1
0
Stop count
1 Enable count
To general-purpose
port input
0 1 1 External event *
* For internal clock, see the previous chart.
INTE TMCSR:bit3
0 Disable interrupts
1 Enable interrupts
Active edge
MOD2 to 0 TMCSR bit9 to bit7
0
0
1
1
X
0
1
0
1
X
---------Rising edge
Falling edge
Both edges
Disabled
UF
TMCSRx:bit2
0 Underflow not present
1 Underflow generation
WRITE 0: Flag clear
1
Timer interrupt
(underflow)
0
0
0
0
0
1
Figure 34.3-3 Register List
Note: For information about ICR registers and interrupt vectors, see "Chapter 21
No.219)".
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Interrupt Control (Page
531
Chapter 34 Reload Timer (RLT)
34.4
MB91460N series
34.4 Registers
34.4.1 TMCSR: Reload Timer Control Status Register
The TMCSR controls the module operation and the interrupts. It also indicates the status of the reload timer.
•
•
•
•
•
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR7
(Reload timer 0): Address: 0001B6H
(Reload timer 1): Address: 0001BEH
(Reload timer 2): Address: 0001C6H
(Reload timer 3): Address: 0001CEH
(Reload timer 7): Address: 0001EEH
15
14
–
–
RX/WX RX/WX
×
×
7
MOD0
0
R/W
×
(Access: Byte, Half-word)
(Access: Byte, Half-word)
(Access: Byte, Half-word)
(Access: Byte, Half-word)
(Access: Byte, Half-word)
13
–
RX/WX
×
12
CSL2
0
R0/WX
×
11
CSL1
0
R/W
×
10
CSL0
0
R/W
×
9
MOD2
0
R/W0
×
8
MOD1
0
R/W
×
5
OUTL
0
R/W
×
4
RELD
0
R/W
×
3
INTE
0
R/W
×
2
UF
0
R(RM1),W
Ο
1
CNTE
0
R/W
Ο
0
TRG
0
R0/W
Ο
6
–
RX/WX
–
bit
Initial Value
Attribute
Rewrite during operation
bit
Initial Value
Attribute
Rewrite during operation
(O: can be rewritten, x: cannot be rewritten)
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit15, bit14: Undefined
Writing has no effect on the operation. The read value is "0".
• bit13: Undefined (reload timer 0 to reload timer 2)
Always write "0". The read value is "0".
• bit12 to bit10: Count clock selection
CSL2
0
0
0
0
1
1
Note:
532
CSL1
0
0
1
1
0
1
CSL0
0
1
0
1
1
0
CLKP: peripheral clock
Count clock
Internal clock CLKP/2
Internal clock CLKP/8
Internal clock CLKP/32
External event (external clock)
Internal clock CLKP/64
Internal clock CLKP/128
Remarks
Depending on whether an internal clock or an external event is selected, the meaning of
the operation mode selection bit (MOD[2:0]) changes.
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Chapter 34 Reload Timer (RLT)
34.4
MB91460N series
• bit9 to bit7: Operation mode selection
Reload trigger when internal clock is selected
MOD2
0
0
0
0
MOD1
0
0
1
1
MOD0
0
1
0
1
Reload trigger
Software trigger
External trigger (rising edge)
External trigger (falling edge)
External trigger (both edges)
When the selected reload trigger is input, the value of reload register TMRLR is loaded to the down counter and the
count operation is started.
Count trigger when external event is selected
MOD2
0
0
0
0
MOD1
0
0
1
1
MOD0
0
1
0
1
Count trigger
-------External trigger (rising edge)
External trigger (falling edge)
External trigger (both edges)
Counts an external event using the selected count trigger.
Always set MOD2 to "0". The read value is the written value.
• bit6: Undefined
Writing has no effect on the operation. The read value is "0".
• bit5: Output level setting
OUTL
0
1
One-shot mode (RELD=0)
During count "H" square wave
During count "L" square wave
Reload mode (RELD=1)
During count start "L" toggle output
During count start "H" toggle output
• During one-shot mode, a pulse is output during the count, and during reload mode a toggle is output.
• For output level setting bit "0" and "1" the output level is reversed.
• bit4: Enable reload
RELD
0
1
Enable reload
One-shot mode (reload disabled)
Reload mode (reload enabled)
• In reload mode, down counter underflow (0000H -> FFFFH) causes the value set to reload register
(TMRLR) to be loaded to the down counter, and the count operation continues.
• In one-shot mode, down counter underflow (0000H -> FFFFH) causes the count operation to stop.
• bit3: Enable Reload timer interrupt requests
INTE
0
1
Enable timer interrupt requests
Disable interrupt requests
Enable interrupt requests
When timer interrupt requests are enabled, and the timer interrupt flag (UF) becomes "1" an interrupt request is
generated.
• bit2: Timer interrupt flag
UF
0
1
Timer interrupt request flag
When read
Underflow not present
Underflow present
When write
Clear interrupt requests
No effect
Upon a down counter underflow (0000H -> FFFFH) generation, the timer interrupt flag is set to "1". If the interrupt
request is enabled (INTE=1) an interrupt request is generated.
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Chapter 34 Reload Timer (RLT)
34.4
MB91460N series
• bit1: Enable timer count
CNTE
0
1
Enable timer count
Stop count operation
Enable count operation (waiting for activation trigger)
If timer count is enabled and an activation trigger is generated, the count operation starts. The activation trigger can be
a software trigger or an external trigger.
• bit0: Software trigger
TRG
0
1
Software trigger
No effect. (The read value is "0".)
Start count operation after data load.
If the count operation is enabled (CNTE=1) and the software trigger bit is set to "1", the value of the reload register
(TMRLR) is loaded to the down counter and the count operation starts.
If the count operation is not enabled (CNTE=0), the software trigger has no effect.
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Chapter 34 Reload Timer (RLT)
34.4
MB91460N series
34.4.2 TMR: Timer Register
•
•
•
•
•
TMR0
TMR1
TMR2
TMR3
TMR7
(Reload timer 0): Address: 0001B2H
(Reload timer 1): Address: 0001BAH
(Reload timer 2): Address: 0001C2H
(Reload timer 3): Address: 0001CAH
(Reload timer 7): Address: 0001EAH
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
15
D15
X
R/WX
14
D14
X
R/WX
13
D13
X
R/WX
12
D12
X
R/WX
11
D11
X
R/WX
10
D10
X
R/WX
9
D9
X
R/WX
8
D8
X
R/WX
7
D7
X
R/WX
6
D6
X
R/WX
5
D5
X
R/WX
4
D4
X
R/WX
3
D3
X
R/WX
2
D2
X
R/WX
1
D1
X
R/WX
0
D0
X
R/WX
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
The reload timer count value can be read out through the timer register TMR.
Please perform the read out using half-word access.
34.4.3 TMRLR: Reload register
•
•
•
•
•
TMRLR0
TMRLR1
TMRLR2
TMRLR3
TMRLR7
(Reload timer 0): Address: 0001B0H
(Reload timer 1): Address: 0001B8H
(Reload timer 2): Address: 0001C0H
(Reload timer 3): Address: 0001C8H
(Reload timer 7): Address: 0001E8H
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
(Access: Half-word)
15
D15
X
RX/W
14
D14
X
RX/W
13
D13
X
RX/W
12
D12
X
RX/W
11
D11
X
RX/W
10
D10
X
RX/W
9
D9
X
RX/W
8
D8
X
RX/W
7
D7
X
RX/W
6
D6
X
RX/W
5
D5
X
RX/W
4
D4
X
RX/W
3
D3
X
RX/W
2
D2
X
RX/W
1
D1
X
RX/W
0
D0
X
RX/W
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see "Meaning of Bit Attribute Symbols (Page No.11)".)
The reload value for the down counter is stored in reload register TMRLR.
Please write using half-word access.
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Chapter 34 Reload Timer (RLT)
34.5
MB91460N series
34.5 Operation
34.5.1 Internal Clock/Reload Mode
Figure 34.5-1 Operation of Reload Timer in reload mode (pulse with a 50% duty ratio is output)
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
Count clock
(5)
Load
data
FFFF
Down counter
Count start
(7) -1
0000
(10)
Reload
data
-1
0000
Reload
data
-1
(2)
CNTE bit
0 (Min)
Activation trigger
(Soft or external event)
(4)
T = CLKP
(10)
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(3)
(6)
Toggle output
(9)
OUTL=1
When RELD=1
Repeat
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): soft trigger or external event trigger
(5)
Load reload value
(6)
TOT toggle output start
(7)
Counter count down (internal clock synchronous)
(8)
Generate counter underflow
(9)
TOT pin output level reversal (toggle output)
(10)
Reload reload value
(11)
Repeat steps (7) to (10)
(See "34.8 Caution (Page No.547)".)
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Chapter 34 Reload Timer (RLT)
34.5
MB91460N series
34.5.2 Internal Clock/One-shot Mode
Figure 34.5-2 Operation of Reload Timer in one-shot mode (one-shot pulse is output)
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
Count clock
FFFF
Counter
(5)
Count start
Reload
data (7) -1
0000
(10) FFFF
Reload
data
-1
(2)
CNTE bit
(4)
Activation trigger
(Soft or external event)
T = CLKP
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(6)
(9)
(3)
(10)
OUTL=1
Output only once
When RELD=0
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): soft trigger or external event trigger
(5)
Load reload value
(6)
Square wave output (during count, "H" output/OUTL=0)
(7)
Counter count down (internal clock synchronous)
(8)
Generate counter underflow
(9)
Return TOT pin output level
(10)
Count stop, wait for next activation trigger
(See "34.8 Caution (Page No.547)".)
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Chapter 34 Reload Timer (RLT)
34.5
MB91460N series
34.5.3 External Event Clock Reload Mode
Figure 34.5-3 Operation in external event clock reload mode (outputs a pulse with a 50% duty ratio)
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
External event (clock)
(5)
Counter
FFFF
Count start
Reload (7)
-1
data
(10)
Load
data
0000
-1
0000
Reload
data
-1
(2)
CNTE bit
0 (Min)
Activation trigger
(Soft only)
(4)
T = CLKP
(10)
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(3)
(6)
Toggle output
(9)
OUTL=1
Repeat
When RELD=1
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): software trigger only
(5)
Load reload value
(6)
TOT pin output (initial value)
(7)
Counter count down (external event synchronous)
(9)
TOT pin output level reversal
(10)
Reload reload value
(11)
Repeat steps (6) to (9)
(See "34.8 Caution (Page No.547)".)
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Chapter 34 Reload Timer (RLT)
34.5
MB91460N series
34.5.4 External Event Clock/One-shot Mode
Figure 34.5-4 Operation in external event clock one-shot mode, (one-shot pulse is output)
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
External event clock
(5)
Counter
CNTE bit
Count start
Reload
data (7) -1
FFFF
0000
(10) FFFF
Reload
data
-1
(2)
(4)
Activation trigger
(Soft only)
T = CLKP
(5)
Data load
(8)
Underflow
(6)
TOT output waveform
OUTL=0
(9)
(3)
(10)
OUTL=1
When RELD=0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Output only once
Set reload value to reload register
Enable reload timer count operation
TOT pin output
Generate reload trigger (activation): soft trigger only
Load reload value
TOT pin output (during count, output "H"/OUTL=0)
Counter count down (via external events)
Generate counter underflow
TOT pin output reversal
Stop counter, wait for next activation trigger
Note: The first reload is delayed by a maximum of 1 T (T: count clock cycle).
34.5.5 Operation during Reset
A reset (reset on INITX signal, watchdog reset, software reset) will cause the registers in the reload timer to be
initialized. The initial value of reload registers is indeterminate.
For detailed information on initial values, see the explanation of registers.
34.5.6 Operation during SLEEP state
Even after entering SLEEP state, the reload timer operation will continue.
34.5.7 Operation during STOP state
After entering STOP state, the operation of the reload timer stops.
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Chapter 34 Reload Timer (RLT)
34.5
MB91460N series
34.5.8 Operation when Returning from STOP state
When returning from STOP state due to an external interrupt, the reload timer will continue with the state it
had before the transition to STOP state.
When returning from STOP state due to a reset (INITX), the reload timer will return to the initial state (down
counter stopped, no TOT pin output).
34.5.9 State Transition
The state of the counter is determined by the CNTE bit of the reload timer control register and the internal
WAIT signal.
Valid states are:
STOP state: Stopped (CNTE=0, WAIT=1)
WAIT state: Waiting for activation trigger (CNTE=1, WAIT=1)
RUN state : Count operation running (CNTE=1, WAIT=0)
LOAD state: Loading value to counter (CNTE=1, WAIT=0)
Figure 34.5-5 State Transition Diagram of the Reload Timer
State Transition from Hardware
Reset
State Transition from Register Access
STOP CNTE=0,WAIT=1
Counter: Retains value
when stopped
Indeterminate after reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
WAIT CNTE=1,WAIT=1
Counter: Retains value
when stopped
Indeterminate until load
after reset
CNTE=1
TRG=1
RUN CNTE=1,WAIT=0
RELD . UF
TRG=1
Counter: Running
TRG=1
LOAD CNTE=1,WAIT=0
Trigger from TIN
RELD . UF
Load reload register
content to counter
Finish load
540
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CM44-10149-1E
Chapter 34 Reload Timer (RLT)
34.6
MB91460N series
34.6 Setting
Table 34.6-1 Settings necessary for internal clock operation
Setting
Setting Registers
Reload (TMRLR0 to TMRLR3,
TMRLR7)
Reload value settings
Setting
Procedure
See 34.7.1
Count clock selection (internal clock selection)
See 34.7.2
Enable reload timer count operation
See 34.7.3
Mode selection (reload /one-shot)
See 34.7.4
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
Output reversal specification
Reload trigger selection (activation selection)
Soft trigger
External trigger
(Rising edge/falling edge/both edges)
See 34.7.5
See 34.7.6
TOT0 to TOT3 pin output
(Extra) port function register
(PFR15.0 to PFR15.3 and EPFR15.0
to EPFR15.3)
Generate activation trigger
–
Software trigger
-> Software trigger bit setting
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
External trigger
-> Input trigger to TIN pin
External input
See 34.7.8
See 34.7.10
Table 34.6-2 Settings necessary for external event operation
Setting
Setting Registers
Reload (TMRLR0 to TMRLR3,
TMRLR7)
Reload value setting
Setting
Procedure
See 34.7.1
Count clock selection (external event clock selection)
See 34.7.2
Enable reload timer count operation
See 34.7.3
Mode selection (reload /one-shot)
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
Output reversal specification
External event clock active edge selection
(Rising edge/falling edge/both edges)
See 34.7.4
See 34.7.5
See 34.7.7
TOT0 to TOT3 pin output
(Extra) port function register
(PFR15.0 to PFR15.3 and EPFR15.0
to EPFR15.3)
See 34.7.8
TIN0 to TIN3 pin external event input
Port function register (PFR14.0 to
PFR14.3)
See 34.7.9
Generate activation trigger
Software trigger
-> Software trigger bit setting
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
See 34.7.10
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Chapter 34 Reload Timer (RLT)
34.6
MB91460N series
Table 34.6-3 Items Necessary for Performing Reload Timer Interrupts
Setting
Setting Registers
Setting
Procedure
Reload timer interrupt vector
Reload timer interrupt level setting
See "Chapter 21 Interrupt Control
(Page No.219)"
See 34.7.11
Reload timer interrupt settings
Interrupt clear
Enable interrupt requests
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
See 34.7.12
Table 34.6-4 Settings Necessary for Stopping the Reload Timer
Setting
Reload timer stop bit setting
542
Setting Registers
Reload timer control status
(TMCSR0 to TMCSR3, TMCSR7)
FUJITSU MICROELECTRONICS LIMITED
Setting
Procedure
See 34.7.13
CM44-10149-1E
Chapter 34 Reload Timer (RLT)
34.7
MB91460N series
34.7 Q & A
34.7.1 How to set the reload value
The reload value is set by the 16 bit reload registers (TMRLR0 to TMRLR3, TMRLR7).
The equation for the values to be set is as follows.
• Formula
TMRLR register value = {reload interval/count clock}-1
• Allowed Range
TMRLR register value = 0000H to FFFFH (65535)
34.7.2 How to select the count clock
The count clock is chosen from the possibilities in the table below.
Selection is done via the count clock selection bit.
Table 34.7-1 TMCSR:CSL[2:0]
Count
Clock
CLKP/2
CLKP/8
CLKP/32
External event
CLKP/64
CLKP/128
Disabled *
Counter clock selection bit
CSL2
CSL1
CSL0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
When CLKP=
32MHz
62.5ns
250ns
1.0μs
2.0μs
4.0μs
Count clock example
When CLKP=
When CLKP= 8MHz
16MHz
125ns
250ns
500ns
1.0μs
2.0μs
4.0μs
Pulse width: 2/CLKP min
4.0μs
8.0μs
8.0μs
16.0μs
---------
(*: See "34.8 Caution (Page No.547)".)
34.7.3 How to enable/disable the reload timer count operation
Use the reload timer count enable bit (TMCSR:CNTE).
Control Details
To stop the reload timer
To enable the reload timer’s count operation
RLT operation enable bit (CNTE)
Set to "0"
Set to "1"
If the timer should change from STOP state to RUN state, first set CNTE = 1 before setting TRG = 1. Setting TRG =1
without setting CNTE first (or simultaneous) has no effect.
34.7.4 How to set the reload timer mode (reload/one-shot)
Use mode selection bit (TMCSR:RELD).
Operation Mode
To set to one-shot mode
To set to reload
CM44-10149-1E
Mode selection bit (RELD)
Set to "0"
Set to "1"
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Chapter 34 Reload Timer (RLT)
34.7
MB91460N series
34.7.5 How to reverse the output level
The settings for the output level are detailed in the following table.
The setting is done via timer output level bit (TMCSR:OUTL).
Output level
Reload mode, Initial value "L" level output
Timer output level bit (OUTL)
Set to "0"
Reload mode, initial value "H" level output (reversed)
Set to "1"
One-shot mode, counting "H" level output
Set to "0"
One-shot mode, counting "L" level output (reversed)
Set to "1"
34.7.6 What are the types of triggers, and how to select them?
• Selection is done via the trigger selection bit (TMCSR:MOD[2:0]).
There are 4 types of reload triggers when an internal clock is selected.
Trigger
Software trigger (TRG bit set)
External trigger from TINx pin (rising edge)
External trigger from TINx pin (falling edge)
External trigger from TINx pin (both edges)
——————
Trigger specification bit (MOD[2:0])
Set to "000"
Set to "001"
Set to "010"
Set to "011"
"100", "101", "110", "111" are disabled *
Reload is repeated on down counter underflow.
(*: See "34.8 Caution (Page No.547)".)
• The reload trigger (activation) when no external event is selected is a software trigger.
34.7.7 What are the types of external event clock active edges and how to select them?
The setting is done via the trigger selection bit (TMCSR:MOD[1:0]).
There are three types of active edges.
Active edge
Rising edge
Falling edge
Both edges
Trigger selection bit (MOD1, MOD0)
Set to "01"
Set to "10"
Set to "11"
MOD2 settings have no meaning, no matter if they are set to "0" or "1".
544
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CM44-10149-1E
Chapter 34 Reload Timer (RLT)
34.7
MB91460N series
34.7.8 How to make a pin a TOT output pin?
Write "1" to the TOT output selection bits (PFR15/EPFR15) to change the port to a TOT pin output.
Pin
TOT0 pin
TOT1 pin
TOT2 pin
TOT3 pin
Control bit
PFR15.0 = 1
PFR15.1 = 1
PFR15.2 = 1
PFR15.3 = 1
EPFR15.0 = 1
EPFR15.1 = 1
EPFR15.2 = 1
EPFR15.3 = 1
34.7.9 How to make the TIN pin into an external event input pin, or an external trigger
input pin?
Write "1" to the TIN input selection bits (PFR14) to change the port to a TIN pin input.
Pin
TIN0 pin
TIN1 pin
TIN2 pin
TIN3 pin
Control bit
PFR14.0 = 1
PFR14.1 = 1
PFR14.2 = 1
PFR14.3 = 1
-
34.7.10 How to generate an activation trigger
• Generating a software trigger
The setting is done via the software trigger bit (TMCSR:TRG).
When the software trigger bit (TGR) is set to"1", a trigger is generated.
To enable operation and activate at the same time, set the count permission bit (TMCSR:CNTE) and the soft trigger bit
(TMCSR:TRG) simultaneously.
• Generating an external trigger
By inputting the edge specified by the trigger selection bit to the trigger pin corresponding to each reload timer, a trigger
is generated.
Timer
Reload timer 0
Reload timer 1
Reload timer 2
Reload timer 3
CM44-10149-1E
Trigger pin
TIN0
TIN1
TIN2
TIN3
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Chapter 34 Reload Timer (RLT)
34.7
MB91460N series
34.7.11 What are the interrupt-related registers?
The relationship between reload timer numbers, interrupt level, vector, control register, etc is outlined in the
following table.
For details on interrupt level and interrupt vectors, see "Chapter 21 Interrupt Control (Page No.219)".
Interrupt vector (default)
Reload timer 0
#32
Address: 0FFF7CH
Reload timer 1
#33
Address: 0FFF78H
Reload timer 2
#34
Address: 0FFF74H
Reload timer 3
#35
Address: 0FFF70H
Reload timer 7
#39
Address: 0FFF60H
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR08)
Address: 000448H
Interrupt level register (ICR09)
Address: 000449H
Interrupt level register (ICR11)
Address: 00044BH
Interrupt flag (TMCSR0:UF) to (TMCSR3:UF), (TMCSR7:UF) is not automatically cleared, so before returning
from interrupt processing, set the UF bit to "0" to reset it.
34.7.12 How to enable interrupts
Interrupt enable bit, interrupt flag
Enabling of interrupts is done via the interrupt request enable bit (TMCSR0:INTE) to (TMCSR3:INTE),
(TMCSR7:INTE).
Interrupt request enable bit (INTE)
Set to "0"
Set to "1"
To disable interrupt requests
To enable interrupt requests
Clearing of interrupts is done via the interrupt flag (TMCSR0:UF) to (TMCSR3:UF), (TMCSR7:UF).
Interrupt flag (UF)
Set to "0"
To clear interrupts
34.7.13 How to stop the reload timer?
This setting is done via the reload timer stop bit.
See "34.7.3 How to enable/disable the reload timer count operation (Page No.543)".
546
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CM44-10149-1E
Chapter 34 Reload Timer (RLT)
34.8
MB91460N series
34.8 Caution
• Count source select bit (TMCSR:CSL[2:0]) settings not in the table: "100B", "111B" are disabled.
If they are set, disable the reload timer operation before resetting the count source select bit.
• Operation mode bit (TMCSR:MOD2) must be set to "0". If it is set to "1", disable the reload timer count
operation before resetting it. Also the value written during read/modify/write access may be read.
• Control bits (Count source select, operation mode, reload permission) must not be rewritten during
operation.
If they are set during operation, disable the reload timer count operation before resetting them.
• From activation timing, it takes T cycle for the reload value to be loaded to the down counter. (Cycle = 1/
CLKP, CLKP = peripheral clock)
• About output signal internal connections
• Reload timer TOT0 to TOT3 outputs are connected to the PPG0 to PPG3 internal trigger inputs.
• Reload timer TOT7 output is connected to the A/D converter 0 trigger input.
• Rewriting of the count clock selection bit (CSL[2:0]), operation mode selection bit (MOD[2:0]), output level
setting bit (OUTL), reload permission bit (RELD), and timer interrupt request enable bit (INTE) should be
done when the reload timer is stopped (TMCSR:CNTE=0).
• The internal prescaler should be already set when the timer count permission bit (TMCSR:CNTE) is set to
"1".
• If the setting of the interrupt flag and clearing the interrupt flag occur at the same time, the flag setting has
higher priority and the clear operation will be made invalid.
• When writing to the reload register and a reload operation occur at the same time, the old data will be loaded
to the counter. The new data will be loaded during the next reload operation.
• If the loading and counting of the timer register occur at the same time, the load (reload) operation has
higher priority.
• If the counting should be enabled at the same time as the count operation should be started, the timer count
enable bit (TMCSR:CNTE) and the software trigger bit (TMCSR:TRG) should both be set to "1".
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547
Chapter 34 Reload Timer (RLT)
34.8
548
MB91460N series
FUJITSU MICROELECTRONICS LIMITED
CM44-10149-1E
Chapter 35 Programmable Pulse Generator (PPG)
35.1
MB91460N series
Chapter 35 Programmable Pulse Generator (PPG)
35.1 Overview
Programmable Pulse Generators (PPGs) are used to generate one-shot (rectangular wave) or pulse width
modulation (PWM) output. The period and duty cycle of the PWM output and the duration of the one shot
output are programmable by software.
Figure 35.1-1 Block diagram of PPG (Programmable Pulse Generator)
Period value
16-bit down counter
Count clock
Interrupt:
- Trigger
- Duty Cycle
- Period
Reload
Borrow
internal trigger
=
Latch
PPG(n)
external trigger
Buffer
TTG(n)
Invert
Duty cycle value
35.2 Features
Figure 35.2-1 Output waveforms: The PPGs can generate the following six types of output signals
• PWM waveform
Normal polarity:
Inverted polarity:
L
H
L
L
H
H
L
H
H
L
Figure 35.2-2 One-shot waveform (Rectangular wave)
Normal polarity:
L
H
L
Inverted polarity:
H
L
H
• Clamped output
Normal polarity: "L" Clamped output
Inverted polarity: "H" Clamped output
• Quantity: 2 groups (Output: 8 channels PPG0 to PPG7)
• Count clock: CLKP, CLKP/4, CLKP/16 or CLKP/64
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Chapter 35 Programmable Pulse Generator (PPG)
35.2
MB91460N series
• Period: Setting range = Duty cycle value ~ 65535 (specified with a 16-bit register)
Period = Count clock × (PCSR register value + 1)
(Example) Count clock = 32MHz(31.25ns), PCSR value = 63999
Period = 31.25ns × (63999+1) = 2ms
• Duty cycle: Setting range = 0 ~ Period value (specified with a 16-bit register)
Duty cycle = Count clock × (PDUT register value + 1)
• Interrupt:
• Software trigger
• Counter borrow (period match)
• Duty cycle match
• Counter borrow (period match) or duty cycle match
• Activation trigger:
• Software trigger
• Internal triggers
Reload timer output ×0 (TOT0) available as trigger for PPG0 to PPG3
Reload timer output ×1 (TOT1) available as trigger for PPG0 to PPG3
Reload timer output ×2 (TOT2) available as trigger for PPG4 to PPG7
Reload timer output ×3 (TOT3) available as trigger for PPG4 to PPG7
• External triggers
Port GP14_0 (ICU0, RLT0 ext-trig, TTG0) available as trigger for PPG0 to PPG3
Port GP14_1 (ICU1, RLT1 ext-trig, TTG1) available as trigger for PPG0 to PPG3
Port GP14_2 (ICU2, RLT2 ext-trig, TTG2) available as trigger for PPG0 to PPG3
Port GP14_3 (ICU3, RLT3 ext-trig, TTG3) available as trigger for PPG0 to PPG3
550
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Chapter 35 Programmable Pulse Generator (PPG)
35.3
MB91460N series
35.3 Configuration
Figure 35.3-1 Configuration Diagram of PPG 0 to 3
PPG (0 to 3)
MDSE
Only write
enabled
PCNH: bit13
0
PWM operation
1
One shot
Period value
PCSR
PDUT
Buffers
Buffer
Count clock
CKS1,0
0
0
0
1
1
0
1
1
PGMS OSEL
0
0
0
1
1
0
1
1
From Port
Data register
Duty cycle match
OR
Output level
(Latch)
Compare
Read-only
down counter
1
Enable operation/Stop
Trigger selection
TSEL03 to 00
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
-
0
1
0
1
0
1
-
Trigger
Trigger
OR
Selector
Reload timer ch0
Reload timer ch1
External Trigger
interrupt 0
request
Edge selection
EGS1,0
PCNL: bit7,bit6
0
0 Operation unaffected
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
Register number
PPG
Timer
0
1
2
3
PTMR0
PTMR1
PTMR2
PTMR3
Period
setting
PCSR0
PCSR1
PCSR2
PCSR3
OR
PPG0/1
interrupt
(#112/#113)
OR
PPG2/3
interrupt
(#114/#115)
PPG1
interrupt
request
IRS1,0
PCNL: bit3,bit2
0 0 Software trigger, or trigger input available
0 1
Counter borrow
Duty match
1 0
1 1
Counter borrow or duty match
STGR PCNH: bit14
0 Operation unaffected
1 Software trigger
Read: Always '0'
IREN PCNL: bit5
0 Interrupt disabled
1 Interrupt enabled
IRQF PCNL: bit4
1
0 No interrupt request
1 Interrupt request
Write 0: Flag clear PPG0
Interrupt cause selection
Edge
selection
EN0 GCN20: bit0
EN2 GCN20: bit2
EN3 GCN20: bit3
Duty
match
RTRG PCNH: bit12
0 Restart disabled
1 Restart enabled
Borrow
GCN10: bit3 to bit0
GCN20 EN0 bit
GCN20 EN1 bit
GCN20 EN2 bit
GCN20 EN3 bit
16-bit reload timer ch0
16-bit reload timer ch1
Disabled
External trigger (TTG)
Disabled
EN1 GCN20: bit1
Control
circuit
Selector
CNTE PCNH: bit15
Stop
0
1 Enable operation
PPG0/P17.0
PPG1/P17.1
PPG2/P17.2
PPG3/P17.3
0
PPG0 PFR4: bit0
PPG1 PFR4: bit1
PPG2 PFR4: bit2
PPG3 PFR4: bit3
0 General-purpose port
1
PPG output
Borrow
PTMR
Prescaler
PCNH: bit9,PCNL:bit0
Normal output
Inverted output
Clamped L output
Clamped H output
Port read
Reload
PCNH: bit11,bit10
CLKP
CLKP/4
CLKP/16
CLKP/64
Peripheral
clock
(CLKP)
Only write
Duty cycle value enabled
Duty cycle Control
status H
setting
PDUT0
PCNH0
PDUT1
PCNH1
PDUT2
PCNH2
PDUT3
PCNH3
Controls
status L
PCNL0
PCNL1
PCNL2
PCNL3
PPG2
interrupt
request
PPG3
interrupt
request
Pin
PPG0
PPG1
PPG2
PPG3
TTG0/P14.0
TTG1/P14.1
TTG2/P14.2
TTG3/P14.3
Figure 35.3-2 Register List
PPG0
Address
000110H
Bit
15
14
13
12
11
10
9
8
16 bits (Read Only)
7
6
5
4
3
2
1
0
PTMR00
(PPG timer 0)
000112H
16 bits (Write Only)
PCSR00
(PPG period setting 0)
000114H
16 bits (Write Only)
PDUT00
(PPG duty setting 0)
CNTE
000116H
STGR
MDSE
RTRG
CKS1
CKS0
PGMS
---
EGS1
EGS0
IREN
IRQF
IRS1
IRS0
---
OSEL PCNH00,PCNL00
TSEL33 TSEL32 TSEL31 TSEL30 TSEL23 TSEL22 TSEL21 TSEL20 TSEL13 TSEL12 TSEL11 TSEL10 TSEL03 TSEL02 TSEL01 TSEL00 GCN10
000100H
Bit
000103H
7
---
000D91H
PPG7
000470H
---
6
---
5
---
4
---
3
EN3
2
EN2
1
EN1
0
EN0
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR48
0FFE3CH
GCN20
(General control 10)
(General control 20)
(Interrupt level PPG 0/1)
32 bits
PPG0
Interrupt vector (#112)
For more information about the ICR register and interrupt vector, see the chapter entitled "Interrupt Control."
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Chapter 35 Programmable Pulse Generator (PPG)
35.3
MB91460N series
PPG1
Address
000118H
Bit
15
14
13
12
11
00011AH
10
9
8
16 bits (Read Only)
7
6
5
4
3
2
1
0
16 bits (Write Only)
00011CH
16 bits (Write Only)
CNTE
00011EH
STGR
MDSE
RTRG
CKS1
CKS0
PGMS
---
EGS1
EGS0
IREN
IRQF
IRS1
IRS0
---
PTMR01
(PPG timer 1)
PCSR01
(PPG period setting 1)
PDUT01
(PPG duty setting 1)
OSEL PCNH01,PCNL01 (PPG control status 1)
TSEL33 TSEL32 TSEL31 TSEL30 TSEL23 TSEL22 TSEL21 TSEL20 TSEL13 TSEL12 TSEL11 TSEL10 TSEL03 TSEL02 TSEL01 TSEL00 GCN10
000100H
000103H
Bit
7
---
6
---
5
---
4
---
3
EN3
2
EN2
1
EN1
0
EN0
000D91H
PPG7
PPG6
PPG5
PPG4
PPG3
PPG2
PPG1
PPG0 PFR17
(Port function 17)
000470H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR48
(Interrupt level PPG 0/1)
0FFE38H
GCN20
(General control 10)
(General control 20)
PPG1
32 bits
Interrupt vector (#113)
For more information about the ICR register and interrupt vector, see the chapter entitled "Interrupt Control."
PPG2
Address
000120H
Bit
15
14
13
12
11
10
9
8
16 bits (Read Only)
7
6
5
4
3
2
1
0
PTMR02
(PPG timer 2)
000122H
16 bits (Write Only)
PCSR02
(PPG period setting 2)
000124H
16 bits (Write Only)
PDUT02
(PPG duty setting 2)
CNTE
000126H
STGR
MDSE
RTRG
CKS1
CKS0
PGMS
---
EGS1
EGS0
IREN
IRQF
IRS1
IRS0
---
OSEL PCNH02,PCNL02 (PPG control status 2)
TSEL33 TSEL32 TSEL31 TSEL30 TSEL23 TSEL22 TSEL21 TSEL20 TSEL13 TSEL12 TSEL11 TSEL10 TSEL03 TSEL02 TSEL01 TSEL00 GCN10
000100H
000103H
Bit
7
---
6
---
5
---
4
---
3
EN3
2
EN2
1
EN1
0
EN0
000D91H
PPG7
PPG6
PPG5
PPG4
PPG3
PPG2
PPG1
PPG0 PFR17
(Port function 17)
000471H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR49
(Interrupt level PPG 2/3)
0FFE34H
GCN20
(General control 10)
(General control 20)
PPG2
32 bits
Interrupt vector (#114)
For more information about the ICR register and interrupt vector, see the chapter entitled "Interrupt Control."
PPG3
Address
000128H
Bit
15
14
13
12
11
10
9
8
16 bits (Read Only)
7
6
5
4
3
2
1
0
PTMR03
(PPG timer 3)
00012AH
16 bits (Write Only)
PCSR03
(PPG period setting 3)
00012CH
16 bits (Write Only)
PDUT03
(PPG duty setting 3)
CNTE
00012EH
STGR
MDSE
RTRG
CKS1
CKS0
PGMS
---
EGS1
EGS0
IREN
IRQF
IRS1
000103H
Bit
7
---
6
---
5
---
4
---
3
EN3
2
EN2
1
EN1
000D91H
PPG7
PPG6
PPG5
PPG4
PPG3
PPG2
PPG1
PPG0 PFR17
(Port function 17)
000471H
---
---
---
ICR4
ICR3
ICR2
ICR1
ICR0 ICR49
(Interrupt level PPG 2/3)
0FFE30H
IRS0
---
OSEL PCNH03,PCNL03 (PPG control status 3)
TSEL33 TSEL32 TSEL31 TSEL30 TSEL23 TSEL22 TSEL21 TSEL20 TSEL13 TSEL12 TSEL11 TSEL10 TSEL03 TSEL02 TSEL01 TSEL00 GCN10
000100H
0
EN0
GCN20
(General control 10)
(General control 20)
32 bits
PPG3
Interrupt vector (#115)
For more information about the ICR register and interrupt vector, see the chapter entitled "Interrupt Control."
Note: For more information about the ICR register and interrupt vector, see "Chapter 21 Interrupt Control (Page
No.219)".
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Chapter 35 Programmable Pulse Generator (PPG)
35.4
MB91460N series
35.4 Registers
35.4.1 PCSR: PPG Period Setting Register
Controls the period of the PPG.
•
•
•
•
•
•
•
•
PCSR0 (PPG0): Address 000112H (Access: Half-word)
PCSR1 (PPG1): Address 00011AH (Access: Half-word)
PCSR2 (PPG2): Address 000122H (Access: Half-word)
PCSR3 (PPG3): Address 00012AH (Access: Half-word)
PCSR4 (PPG4): Address 000132H (Access: Half-word)
PCSR5 (PPG5): Address 00013AH (Access: Half-word)
PCSR6 (PPG6): Address 000142H (Access: Half-word)
PCSR7 (PPG7): Address 00014AH (Access: Half-word)
15
D15
X
RX, W
14
D14
X
RX, W
13
D13
X
RX, W
12
D12
X
RX, W
11
D11
X
RX, W
10
D10
X
RX, W
9
D9
X
RX, W
8
D8
X
RX, W
7
D7
X
RX, W
6
D6
X
RX, W
5
D5
X
RX, W
4
D4
X
RX, W
3
D3
X
RX, W
2
D2
X
RX, W
1
D1
X
RX, W
0
D0
X
RX, W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• The PPG Period Setting registers are buffered. Transfers from the corresponding buffers to the 16-bit
down counter take place automatically at counter underflow.
• After the PPG Period Setting registers have been written, be sure to set PPG Duty cycle Setting registers
PDUT.
• Always access the PPG Period Setting registers in a half-word (16-bit) format.
(See "35.8 Caution (Page No.573)".)
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35.4.2 PDUT: PPG Duty cycle Setting Register
Sets the duty cycle of the PPG output waveform.
•
•
•
•
•
•
•
•
PDUT0 (PPG0): Address 000114H (Access: Half-word)
PDUT1 (PPG1): Address 00011CH (Access: Half-word)
PDUT2 (PPG2): Address 000124H (Access: Half-word)
PDUT3 (PPG3): Address 00012CH (Access: Half-word)
PDUT4 (PPG4): Address 000134H (Access: Half-word)
PDUT5 (PPG5): Address 00013CH (Access: Half-word)
PDUT6 (PPG6): Address 000144H (Access: Half-word)
PDUT7 (PPG7): Address 00014CH (Access: Half-word)
15
D15
X
RX, W
14
D14
X
RX, W
13
D13
X
RX, W
12
D12
X
RX, W
11
D11
X
RX, W
10
D10
X
RX, W
9
D9
X
RX, W
8
D8
X
RX, W
7
D7
X
RX, W
6
D6
X
RX, W
5
D5
X
RX, W
4
D4
X
RX, W
3
D3
X
RX, W
2
D2
X
RX, W
1
D1
X
RX, W
0
D0
X
RX, W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• The PPG Duty cycle Setting registers are buffered.
• Set a value smaller than the setting of PPG Period Setting register PCSR in a PPG Duty cycle Setting
register. (See "35.8 Caution (Page No.573)".)
• If the same value as set in PPG Period Setting register PCSR is set in a PPG Duty cycle Setting register,
• The output pin level is always "H" at normal polarity time. (OSEL=0)
• The output pin level is always "L" at inverted polarity time. (OSEL=1)
(The OSEL bit is an output polarity specification bit of the PPG control register PCN.)
• Always access the PPG Duty cycle Setting registers in a half-word (16-bit) format.
(See "35.8 Caution (Page No.573)".)
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Chapter 35 Programmable Pulse Generator (PPG)
35.4
MB91460N series
35.4.3 PCN: PPG Control Status register
Controls the operations and status of PPGs.
•
•
•
•
•
•
•
•
PCN0 (PPG0): Address 000116H (Access: Byte, Half-word)
PCN1 (PPG1): Address 00011EH (Access: Byte, Half-word)
PCN2 (PPG2): Address 000126H (Access: Byte, Half-word)
PCN3 (PPG3): Address 00012EH (Access: Byte, Half-word)
PCN4 (PPG4): Address 000136H (Access: Byte, Half-word)
PCN5 (PPG5): Address 00013EH (Access: Byte, Half-word)
PCN6 (PPG6): Address 000146H (Access: Byte, Half-word)
PCN7 (PPG7): Address 00014EH (Access: Byte, Half-word)
15
CNTE
0
R/W
O
14
STGR
0
R0/W
O
13
MDSE
0
R/W
×
12
RTRG
0
R/W
×
11
CKS1
0
R/W
×
10
CKS0
0
R/W
×
9
PGMS
0
R/W
×
8
–
X
RX/WX
–
7
EGS1
0
R/W
×
6
EGS0
0
R/W
×
5
IREN
0
R/W
O
4
IRQF
0
R(RM1), W
O
3
IRS1
0
R/W
×
2
IRS0
0
R/W
×
1
–
X
RX/WX
–
0
OSEL
0
R/W
×
Bit
Initial value
Attribute
Rewrite during operation
Bit
Initial value
Attribute
Rewrite during operation
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
O: Rewritable, x: Not writable (See "35.8 Caution (Page No.573)".)
• Bit 15: Timer enable operation
CNTE
0
1
Operation
Operation disabled
Operation enabled
This bit enables the operation of the PPG.
• Bit 14: Software trigger
STGR
0
1
Operation
The operation is unaffected by writing (The read value always equals "0").
Software trigger activation
When the Software Trigger bit is set to "1", a software trigger is generated to activate the PPG, separately from the
generation of an internal trigger (EN bit, reload timer output).
• Bit 13: Mode selection
MDSE
0
1
Mode
PWM operation
One-shot operation
• When the Mode Selection bit is set to "0", a PWM operation is enabled to generate pulses in sequence.
• When the Mode Selection bit is set to "1", pulse output takes place only once.
• Bit 12: Restart enable
RTRG
0
1
Operation
Disable restart.
Enable restart.
When the Enable Restart bit is set to "1", a trigger (software/internal) leads to a restart of the PPG, (even if the PPG is
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MB91460N series
enabled (CNTE = 1)). If the Enable Restart bit is set to "0" the trigger has no effect on the function of the PPG.
• Bit 11, bit 10: Counter clock selection
CKS1
0
0
1
1
CKS0
0
1
0
1
Down Counter Count Clock Selection
Peripheral clock (CLKP)
Peripheral clock divided by 4
Peripheral clock divided by 16
Peripheral clock divided by 64
• Bit 9: PPG output mask selection
PGMS
0
1
Operation
No output mask
Output mask (Output "L" level latched:OSEL=0)
• When the PPG Output Mask Selection bit is set to "1", the PPG output can be clamped at "L" or "H"
regardless of the mode, period, and duty cycle settings.
• The output level can be specified using the Output Polarity Specification bit (PCN:OSEL).
• Bit 8: Undefined.
The operation is unaffected by writing. The read value is indeterminate.
• Bit 7, bit 6: Trigger input edge selection
EGS1
0
0
1
1
EGS0
0
1
0
1
Selected Edge
The operation is unaffected by writing.
Rising edge
Falling edge
Both edges (rising edge, or, falling edge)
Select an edge to trigger the activation of the trigger input selected with the Trigger Specification bits
(GCN10[15:12]), (GCN10[11:8]), (GCN10[7:4]), and (GCN10[3:0]) of PPG3 to PPG0,
(GCN11[15:12]), (GCN11[11:8]), (GCN11[7:4]), and (GCN11[3:0]) of PPG7 to PPG4,
using the Trigger Input Edge Selection bit (EGS[1:0]).
• Bit 5: Interrupt request enable
IREN
0
1
Operation
Interrupt request disabled
Interrupt request enabled
• Bit 4: interrupt flag
IRQF
0
1
Read Operation
No interrupt present
Interrupt present
Write Operation
Clear the Interrupt flag.
No effect.
If the Interrupt flag (IRQF) is set to "1" and writing "0" to the flag take place at the same time, the setting of the Interrupt
flag (IRQF=1) has higher priority.
• Bit 3, bit 2: Interrupt cause selection
IRS1
0
0
1
1
IRS0
0
1
0
1
Selection
Software trigger, or, trigger input
Counter borrow
The counter matches the duty cycle value.
Counter borrow, or the counter equals the duty cycle value.
• Select the operation in which to generate an interrupt request.
• Bit 1: Undefined.
The operation is unaffected by writing. The read value is indeterminate.
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35.4
MB91460N series
• Bit 0: PPG output polarity specification
OSEL
0
1
Operation
Normal polarity
Inverted polarity
When the PPG Output Mask Selection bit (PCN:PGMS) has been set to "1", if the Output Polarity Specification bit
(OSEL) is set to "0", the output is clamped at "L"; if the Output Polarity Specification bit is set to "1", the output is
clamped at "H".
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35.4
MB91460N series
35.4.4 GCN1: General Control register 1
Selects a trigger input to PPG0 to PPG3, PPG4 to PPG7.
• GCN10 (PPG0 to PPG3): Address 000100H (Access: Half-word)
• GCN11 (PPG4 to PPG7): Address 000104H (Access: Half-word)
15
TSEL33
0
R/W
14
TSEL32
0
R/W
13
TSEL31
1
R/W
12
TSEL30
1
R/W
11
TSEL23
0
R/W
10
TSEL22
0
R/W
9
TSEL21
1
R/W
8
TSEL20
0
R/W
7
TSEL13
0
R/W
6
TSEL12
0
R/W
5
TSEL11
0
R/W
4
TSEL10
1
R/W
3
TSEL03
0
R/W
2
TSEL02
0
R/W
1
TSEL01
0
R/W
0
TSEL00
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
PPG4 to PPG7:
•GCN11: Bit15 to bit12
•GCN11: Bit11 to bit8
•GCN11: Bit7 to bit4
•GCN11: Bit3 to bit0
PPG0 to PPG3:
•GCN10: Bit15 to bit12
•GCN10: Bit11 to bit8
•GCN10: Bit7 to bit4
•GCN10: Bit3 to bit0
0
0
0
0
0
0
1
1
1
1
(TSEL3[3:0])
(TSEL2[3:0])
(TSEL1[3:0])
(TSEL0[3:0])
PPG7 trigger specification
PPG6 trigger specification
PPG5 trigger specification
PPG4 trigger specification
(TSEL3[3:0])
(TSEL2[3:0])
(TSEL1[3:0])
(TSEL0[3:0])
PPG3 trigger specification
PPG2 trigger specification
PPG1 trigger specification
PPG0 trigger specification
TSEL
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
None of the above
0
1
0
1
0
1
0
1
0
1
Activation trigger specification
EN0 bit (GCN2 register)
EN1 bit (GCN2 register)
EN2 bit (GCN2 register)
EN3 bit (GCN2 register)
16-bit reload timer 0/2
16-bit reload timer 1/3/7
External trigger 0
External trigger 1
External trigger 2
External trigger 3
Disabled (See "35.8 Caution (Page No.573)".)
• PPG0 to PPG7 as selected are activated when the edge specified by the Trigger Input Edge Selection
bits (PCN:EGS[1:0]) are detected during the specified activation trigger.
• For detailed setting of each channel see chapter 35.7.7 What activation triggers are available and how
are they selected? (Page No.568)
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Chapter 35 Programmable Pulse Generator (PPG)
35.4
MB91460N series
35.4.5 GCN2: General Control Register 2
Generates PPG0 to PPG3 and PPG4 to PPG7 internal trigger levels using software.
• GCN20 (PPG0 to PPG3): Address 000103H (Access: Byte)
• GCN21 (PPG4 to PPG7): Address 000107H (Access: Byte)
7
–
0
R/W0
6
–
0
R/W0
5
–
0
R/W0
4
–
0
R/W0
3
EN3
0
R/W
2
EN2
0
R/W
1
EN1
0
R/W
0
EN0
0
R/W
bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• Bit 7 to bit 4: Undefined.Always write "0". The read value is the value as written. (See "35.8 Caution (Page
No.573)".)
• Bit 3: EN3 trigger input
• Bit 2: EN2 trigger input
• Bit 1: EN1 trigger input
• Bit 0: EN0 trigger input
EN0, EN1, EN2, and EN3
Internal Triggers EN0, EN1, EN2, and EN3
0
Set the level to "L".
1
Set the level to "H".
• Set the levels of internal triggers EN0, EN1, EN2, and EN3.
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits
(GCN10:TSEL0[3:0], GCN10:TSEL1[3:0], GCN10:TSEL2[3:0], and GCN10:TSEL3[3:0]) of PPG0, PPG1,
PPG2, PPG3, then the selected EN serves as a PPG trigger input bit.
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits
(GCN11:TSEL0[3:0], GCN11:TSEL1[3:0], GCN11:TSEL2[3:0], and GCN11:TSEL3[3:0]) of PPG4, PPG5,
PPG6, PPG7, then the selected EN serves as a PPG trigger input bit.
• If the state selected with the trigger input edge selection bit (EGS[1:0]) is generated by software using the
trigger input bit (selected EN0, EN1, EN2, or EN3), the choice serves as an activation trigger to activate
the PPG.
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35.4
MB91460N series
35.4.6 PTMR: PPG Timer Register
Reads the counts of PPG0 to PPG3 and PPG4 to PPG7.
•
•
•
•
•
•
•
•
PTMR0 (PPG0): Address 000110H (Access: Half-word)
PTMR1 (PPG1): Address 000118H (Access: Half-word)
PTMR2 (PPG2): Address 000120H (Access: Half-word)
PTMR3 (PPG3): Address 000128H (Access: Half-word)
PTMR4 (PPG4): Address 000130H (Access: Half-word)
PTMR5 (PPG5): Address 000138H (Access: Half-word)
PTMR6 (PPG6): Address 000140H (Access: Half-word)
PTMR7 (PPG7): Address 000148H (Access: Half-word)
15
D15
1
R/WX
14
D14
1
R/WX
13
D13
1
R/WX
12
D12
1
R/WX
11
D11
1
R/WX
10
D10
1
R/WX
9
D9
1
R/WX
8
D8
1
R/WX
7
D7
1
R/WX
6
D6
1
R/WX
5
D5
1
R/WX
4
D4
1
R/WX
3
D3
1
R/WX
2
D2
1
R/WX
1
D1
1
R/WX
0
D0
1
R/WX
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• The count of the 16-bit down counter can be read.
• Be sure to access the PPG Timer register PTMR in half words (16 bits).
• The register is not be read correctly if it is byte-accessed.
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Chapter 35 Programmable Pulse Generator (PPG)
35.5
MB91460N series
35.5 Operation
The MB91460N series features 8 channels of programmable pulse generators (PPGs), which provide
programmable pulse output independently or jointly.
The individual modes of operation are described below.
35.5.1 PWM Operation
Figure 35.5-1 In PWM operation, variable duty cycle pulses are generated from the PPG pin
(3)
Enable count
CNTE
Activation trigger
(4)
(1)
PCSR 8000H
PDUT
8000H
0005H
(6) Rewrite
0007H
(2) Write
8000H
(Period value)
8000H
(13) Load
(5) Load
0007H
Reload
0005H
(Duty cycle value)
Down count
value
(PTMR)
0007H
Reload
(13) Lo a d
(5) Lo a d
(7) Down count
(8) Match
Match
0005H
Match
(10) Down count
Borrow
(11) Borrow
PPG pin output
Normal
polarity
Inverted
polarity
Interrupt
cause
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(9) Inve rt
(12) Clear
Inve rt
Clear
Inve rt
Duty cycle
Period
Effective edge
Counter borrow
Counter borrow
Duty cycle match
Duty cycle match
Write a period value.
Write a duty cycle value and transfer the period value to buffers.
Enable PPG operation.
Generate an activation trigger.
Load the period and duty cycle values.
Rewrite the duty cycle value and transfer the period value to buffers.
Counter counts down
The down counter equals the duty cycle value.
Inverses the PPG pin output level.
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35.5
(10)
(11)
(12)
(13)
(14)
(15)
MB91460N series
Counter counts down
Counter borrow (underflow)
Clear the PPG pin output level (return to normal).
Reload the period value.
Reload the duty cycle value.
Steps from (6) to (13) are iterated.
(See "35.8 Caution (Page No.573)".)
• Equation
Period = {Period value (PCSR) + 1} × Count clock
Duty cycle = {Duty cycle value (PDUT) + 1} × Count clock
Width up to pulse output = {Period value (PCSR) – Duty cycle value (PDUT)} × Count clock
35.5.2 One-Shot Operation
In one-shot operation, one-shot pulses are generated from the PPG pin.
(3)
Enable count
CNTE
(4)
Activation trigger
(1)
PCSR 8000H
PDUT
0007H
(2)
8000H
(Period value)
(5) Load
0007H
(Duty cycle value)
Down count
value
(PTMR)
0007H
(5) Load
(6) Down count
(7) Match
(8) Down count
(10) Borrow
PPG pin output
Normal
polarity
Inverted
polarity
Interrupt
cause
(9) Invert
(11) Clear
Duty cycle
Period
Effective edge
Counter borrow
Duty cycle match
(1) Write a period value.
(2) Write a duty cycle value and transfer the period value to buffers.
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35.5
MB91460N series
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
Enable PPG operation.
Generate an activation trigger.
Load the period and duty cycle values.
Counter counts down
Down counter value and duty cycle value matches
Counter counts down
Inverse the PPG pin output level.
Counter borrow (underflow)
Clear the PPG pin output level (return to normal).
The operating sequence is now completed.
(See "35.8 Caution (Page No.573)".)
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35.5.3 Restart Operation
The restart operation is described below.
Figure 35.5-2 Restart available in PWM operation
Rising edge detection
Restarted by the trigger
Trigger
m
n
0
PPG
N
T
N = duty cycle, T = period
Figure 35.5-3 Restart available in one-shot operation
Rising edge detection
Restarted by the trigger
Trigger
m
n
0
PPG
N
T
If a restart is not available, the second and subsequent triggers have no effect in both PWM and one-shot
operations.
(The second and subsequent triggers following a shutdown of the down counter are functional.)
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35.6
MB91460N series
35.6 Setting
Table 35.6-1 Settings Needed to Start the PPG
Setting
Setting Registers
Period and duty cycle value settings
Enable PPG operation.
Operation mode selection (PWM/one-shot)
Enable restart.
Count clock selection
PPG output mask selection
Trigger selection
Software
Internal trigger
External trigger
Output polarity specification
PPG pin output setting
Trigger generation (software trigger)
(Reload timer)
(GCN2:EN bit)
Setting
Procedure*
PPG period settings (PCSR0 to PCSR7)
PPG duty cycle settings (PDUT0 to PDUT7)
35.7.1
PPG control status (PCN0 to PCN7)
35.7.2
35.7.3
35.7.4
35.7.5
35.7.6
General Control 1 (GCN10, GCN11)
Port functions (PFR17)
PPG Control Status (PCN0 to PCN7)
See "Chapter 34 Reload Timer (RLT) (Page
No.529)".
General Control 2 (GCN20, GCN21)
35.7.7
35.7.8
35.7.9
35.7.10
* For refer to the section indicated by the number.
Table 35.6-2 Settings Needed to Stop the PPG
Setting
Setting Registers
PPG stop bit setting
PPG control status (PCN0 to PCN7)
Setting
Procedure*
35.7.11
*For the setting procedure, refer to the section indicated by the number.
Table 35.6-3 Settings Needed to Clamp the Output Level
Setting
Setting Registers
Output polarity specification
PPG output mask selection
Period value = Duty cycle value setting
PPG control status (PCN0 to PCN7)
PPG duty cycle settings (PDUT0 to PDUT7)
Setting
Procedure*
35.7.8
35.7.6
35.7.6
*For the setting procedure, refer to the section indicated by the number.
Table 35.6-4 Settings Needed to Implement PPG Interrupts
Setting
Setting Registers
PPG interrupt vector, PPG interrupt level setting
PPG interrupt cause selection
(Generate an activation trigger, borrow, and duty
cycle match)
PPG interrupt setting
Clear interrupts.
Enable interrupt requests.
See "Chapter 21 Interrupt Control (Page
No.219)".
Setting
Procedure*
35.7.12
35.7.13
PPG control status (PCN0 to PCN7)
35.7.14
*:For the setting procedure, refer to the section indicated by the number.
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35.7 Q & A
35.7.1 How to set (rewrite) a period and a duty cycle
Period and duty cycle value settings
• Set each period value in PPG Period Setting Register PCSR.
• Set each duty cycle value in PPG Duty cycle Setting Register PDUT.
• The PPG Period Setting and the PPG Duty cycle Setting registers each have a buffer to allow the user to
ignore the write timing.
• Equation
PCSR register value = {Period/Count clock} –1
PDUT register value = {"H" width (duty cycle)*/Count clock} –1
*: Normal polarity (OSEL= 0)
• Allowed range
PCSR register value = PCSR register value - FFFFH (65535)
PDUT register value = 0 - PCSR register value
Note: Be sure to set the duty cycle after the setting of the period. (See "35.8 Caution (Page No.573)".)
35.7.2 How to enable or disable PPG operations
Enabling the PPG operation
Use the PPG operation enable bit (PCN:CNTE).
Control
To stop a PPG operation
To enable a PPG operation
PPG Operation Enable Bit (CNTE)
Set "0".
Set "1".
Enable PPG operation before starting the PPG.
(See "35.8 Caution (Page No.573)".)
35.7.3 How to set the PPG operation mode (PWM operation/one-shot operation)?
Operation mode selection
Use the mode selection bit (PCN:MDSE).
Operation Mode
To implement a PWM operation
To implement a one-shot operation
Mode Selection Bit (MDSE)
Set "0".
Set "1".
(See "35.8 Caution (Page No.573)".)
35.7.4 How to get it restarted
Enable restart.
A restart of a PPG can be enabled while the PPG is in operation.
Use the Enable Restart bit (PCN:RTRG) to set.
(See "35.8 Caution (Page No.573)".)
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35.7.5 What count clocks are available and how are they selected?
Count clock selection
The count clock is selectable out of the four choices listed below.
Use the count clock selection bit (PCN:CKS[1:0]).
Count
Clock
CLKP
CLKP/4
CLKP/16
CLKP/64
Count Clock Selection Bit
(Example) CLKP = 32MHz
CKS1
CKS0
Count Clock
Period (1 to FFFFH)
0
0
1
1
0
1
0
1
32MHz
8MHz
2MHz
500kHz
62.5ns to 2.048ms
250ns to 8.192ms
1μs to 32.76ms
4μs to 131.0ms
(See "35.8 Caution (Page No.573)".)
35.7.6 How to clamp the PPG pin output level
PPG output mask selection
The level of PPG pin output can be clamped.
Use the PPG Output Mask Selection bit (PCN:PGMS) and the duty cycle value (PDUT) to set.
PPG Pin Output
PPG Output Polarity
Specification
Bit (OSEL)
To clamp the "L" level under normal polarity
When "0"
To clamp the "H" level under normal polarity
When "0"
To clamp the "H" level under inverted polarity
When "1"
To clamp the "L" level under inverted polarity
When "1"
Setting Procedure
Set the PPG Output Mask Selection bit
(PGMS) to "1".
Period value (PCSR) =
Set a duty cycle value (PDUT).
Set the PPG Output Mask Selection bit
(PGMS) to "1".
Period value (PCSR) =
Set a duty cycle value (PDUT).
Figure 35.7-1 PPG pin output can be set to all "L" (when OSEL=0)
PPG
Reduce
the duty cycle
value
Write "1" to PGMS (mask bit) on occurrence
of an interrupt caused by a borrow.
If "0" is written to PGMS on occurrence of
an interrupt caused by a borrow, a PWM
waveform can be generated without
incurring hazard output.
Figure 35.7-2 PPG pin output can be set to all "H" (when OSEL=0)
PPG
Reduce
the duty cycle
value
Write the same value as the period setting
register value to the duty cycle setting register
on occurrence of an interrupt caused by
a compare match.
PPG output will also equal all "H" if "0" is set in both the PPG Period Setting Register (PCSR) and PPG Duty
cycle Setting Register (PDUT). (when OSEL=0)
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35.7.7 What activation triggers are available and how are they selected?
• Trigger selection
• Activation triggers are broadly grouped into software triggers, internal triggers and external triggers.
• Software triggers work at all times.
• Internal and external trigger availability depends on each device specification.
An trigger is set using the trigger specification
(GCN1:TSEL2[3:0]), and (GCN1:TSEL3[3:0]).
bits
(GCN1:TSEL0[3:0]),
(GCN1:TSEL1[3:0]),
Triggers are selectable for PPG0, PPG1, PPG2, and PPG3 independently.
PPG0
Internal Trigger
PPG1
PPG2
PPG3
Internal Trigger Specification Bit
To select the EN0 bit of the GCN20 register
TSEL0[3:0]
Set "0000B"
TSEL1[3:0]
Set "0000B"
TSEL2[3:0]
Set "0000B"
TSEL3[3:0]
Set "0000B"
To select the EN1 bit of the GCN20 register
Set "0001B"
Set "0001B"
Set "0001B"
Set "0001B"
To select the EN2 bit of the GCN20 register
Set "0010B"
Set "0010B"
Set "0010B"
Set "0010B"
To select the EN3 bit of the GCN20 register
Set "0011B"
Set "0011B"
Set "0011B"
Set "0011B"
To select reload timer 0
Set "0100B"
Set "0100B"
Set "0100B"
Set "0100B"
To select reload timer 1
Set "0101B"
Set "0101B"
Set "0101B"
Set "0101B"
PPG0
PPG1
PPG2
PPG3
External Trigger
External Trigger Specification Bit
To select the external trigger on GP14_0 (TTG0)
TSEL0[3:0]
Set "1000B"
TSEL1[3:0]
Set "1000B"
TSEL2[3:0]
Set "1000B"
TSEL3[3:0]
Set "1000B"
To select the external trigger on GP14_1 (TTG1)
Set "1001B"
Set "1001B"
Set "1001B"
Set "1001B"
To select the external trigger on GP14_2 (TTG2)
Set "1010B"
Set "1010B"
Set "1010B"
Set "1010B"
To select the external trigger on GP14_3 (TTG3)
Set "1011B"
Set "1011B"
Set "1011B"
Set "1011B"
Triggers are selectable for PPG4, PPG5, PPG6, and PPG7 independently.
PPG4
Internal Trigger
PPG5
PPG6
PPG7
Internal Trigger Specification Bit
To select the EN0 bit of the GCN21 register
TSEL0[3:0]
Set "0000B"
TSEL1[3:0]
Set "0000B"
TSEL2[3:0]
Set "0000B"
TSEL3[3:0]
Set "0000B"
To select the EN1 bit of the GCN21 register
Set "0001B"
Set "0001B"
Set "0001B"
Set "0001B"
To select the EN2 bit of the GCN21 register
Set "0010B"
Set "0010B"
Set "0010B"
Set "0010B"
To select the EN3 bit of the GCN21 register
Set "0011B"
Set "0011B"
Set "0011B"
Set "0011B"
To select reload timer 2
Set "0100B"
Set "0100B"
Set "0100B"
Set "0100B"
To select reload timer 3
Set "0101B"
Set "0101B"
Set "0101B"
Set "0101B"
PPG4
PPG5
PPG6
PPG7
External Trigger
External Trigger Specification Bit
To select the external trigger on GP14_4 (TTG4)
TSEL0[3:0]
Set "1000B"
TSEL1[3:0]
Set "1000B"
TSEL2[3:0]
Set "1000B"
TSEL3[3:0]
Set "1000B"
To select the external trigger on GP14_5 (TTG5)
Set "1001B"
Set "1001B"
Set "1001B"
Set "1001B"
To select the external trigger on GP14_6 (TTG6)
Set "1010B"
Set "1010B"
Set "1010B"
Set "1010B"
To select the external trigger on GP14_7 (TTG7)
Set "1011B"
Set "1011B"
Set "1011B"
Set "1011B"
The same trigger can be specified for a group of PPGs to activate all these PPGs simultaneously. (See "35.8
Caution (Page No.573)".)
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• Trigger edge selection
Trigger edges are set using trigger input edge selection bits (PCN:EG[1:0]).
Trigger Edge Selection
When not detected (software trigger only)
Trigger Input Edge Selection Bits (EG1, EG0)
Set "00B".
"L" -> "H" Trigger generated on the rising edge
Set "01B".
"H" -> "L" Trigger generated on the falling edge
Set "10B".
Trigger generated on both edges
Set "11B".
(See "35.8 Caution (Page No.573)".)
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35.7.8 How to invert the output polarity?
Output polarity specification
The polarity in the normal state can be specified as follows:
Use the PPG Output Polarity Specification bit (PCN:OSEL) to set.
("Normal state" means the state in which pulse output is not executed.)
Output Level in Normal State
To enable "L" level output (normal polarity)
To enable "H" level output (inverted polarity)
PPG Output Polarity Specification Bit (OSEL)
Set "0".
Set "1".
(See "35.8 Caution (Page No.573)".)
35.7.9 How to program a pin as a PPG output pin?
-> PPG pin output setting
Software programming allows ports to be switched to PPG pin output.
Pin
PPG0 pin
PPG1 pin
PPG2 pin
PPG3 pin
PPG4 pin
PPG5 pin
PPG6 pin
PPG7 pin
570
Control Bit Location
Port Function register PFR17.0 = 1
PPG0 Output specification bit (PPG0)
Port Function register PFR17.1 = 1
PPG1 Output specification bit (PPG1)
Port Function register PFR17.2 = 1
PPG2 Output specification bit (PPG2)
Port Function register PFR17.3 = 1
PPG3 Output specification bit (PPG3)
Port Function register PFR17.4 = 1
PPG4 Output specification bit (PPG4)
Port Function register PFR17.5 = 1
PPG5 Output specification bit (PPG5)
Port Function register PFR17.6 = 1
PPG6 Output specification bit (PPG6)
Port Function register PFR17.7 = 1
PPG7 Output specification bit (PPG7)
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Chapter 35 Programmable Pulse Generator (PPG)
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35.7.10 How to generate an activation trigger?
Generating a trigger
Methods of generating an activation trigger are described below.
• Activating a software trigger
Use the Software Trigger bit (PCN:STGR) to set.
Write "1" to the Software Trigger bit (STGR) to generate an activation trigger.
Always functional, regardless of the internal trigger.
• Activating PPGs with reload timers
The reload timers need to be set up and activated. For more information, see "Chapter 34 Reload Timer (RLT) (Page
No.529)".
An activation trigger is generated when the edge specified by the reload timer output signal is generated with the reload
timer underflow.
• Activating PPGs with external triggers
An activation trigger is generated when the edge specified on the specified pin appears. There is no need for
configuration of the port registers; the trigger is always connected to the PPGs.
• Activating a PPG with the EN trigger input bits (GCN2:EN0) - (GCN2:EN3)
An activation trigger can be generated by rewriting the level of the EN trigger input bits (GCN2:EN0) - (GCN2:EN3).
Edge
Software-Based Setting Procedure (EN0, EN1, EN2, EN3)
Rising edge
Falling edge
First, set the EN bit to "0", then the EN bit to "1".
First, set the EN bit to "1", then to "0".
• Activating multiple PPGs concurrently
The same trigger (trigger input bit) can be specified with the PPG trigger specification bits to activate all the PPGs
simultaneously when the trigger is generated.
• Even if an activation trigger is generated before the operation of a PPG is enabled, that PPG would not be
activated. Be sure to enable the operation of a PPG before generating a trigger to activate it. (See "35.7.2
How to enable or disable PPG operations (Page No.566)".)
35.7.11 How to stop a PPG operation?
PPG stop bit setting (See "35.7.2 How to enable or disable PPG operations (Page No.566)".)
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35.7.12 What interrupt registers are used?
PPG interrupt vector, PPG interrupt level setting
The table below summarizes the relationships among the PPG number, interrupt level and interrupt vector.
For more information about the interrupt levels and interrupt vectors, see "Chapter 21 Interrupt Control (Page
No.219)".
PPG0
Interrupt Vector (Default)
#112
Address: 0FFE3CH
PPG1
#113
Address: 0FFE38H
PPG2
#114
Address: 0FFE34H
PPG3
#115
Address: 0FFE30H
PPG4
#116
Address: 0FFE2CH
PPG5
#117
Address: 0FFE28H
PPG6
#118
Address: 0FFE24H
PPG7
#119
Address: 0FFE20H
Interrupt Level Setting Bit (ICR[4:0])
Interrupt Level register (ICR48)
Address: 000470H
Interrupt Level register (ICR49)
Address: 000471H
Interrupt Level register (ICR50)
Address: 000472H
Interrupt Level register (ICR51)
Address: 000473H
The Interrupt flag (PCN: IRQF) does not clear itself automatically. Use software to clear it before returning from the
interrupt handler. (Write "0" to the IRQF bit.)
35.7.13 What interrupts are available and how are they selected?
Interrupt cause selection
Four kinds of interrupts are selectable as follows:
Use the Interrupt Cause Setting bit (PCN:IRS[1:0]) to set.
Interrupt Cause
Interrupt Cause Setting Bit (IRS[1:0])
Software trigger or Internal trigger generation (PPG0 to PPG7)
Set "00B".
Down counter borrow (period match)
Set "01B".
Duty cycle match
Set "10B".
Down counter borrow (period match) or Duty cycle match
Set "11B".
35.7.14 How to enable, disable and clear interrupts?
Interrupt Request Enable bit, Interrupt flag
Use the interrupt request enable bit (PCN:IREN) to enable interrupts.
To disable interrupt requests
To enable interrupt requests
Interrupt Request Enable Bit (IREN)
Set "0".
Set "1".
Use the interrupt flag (PCN:IRQF) to clear interrupts.
To clear interrupts
Interrupt flag (IRQF)
Write "0".
(See "35.8 Caution (Page No.573)".)
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35.8 Caution
• If an interrupt occurs (Interrupt flag PCN:IRQF is set to "1") and the Interrupt flag is set to "0" at the same
time, the setting of the Interrupt flag to "1" has higher priority.
• The first load comes with a maximum delay of 2.5T after the activation trigger. (T: Count clock)
If the down counter is loaded and counts at the same time, the load operation overrides.
Trigger
Maximum 2.5T
Load
Clock
Count value
X
0003
0002
0001
0000
0003
0002
PPG
Interrupt
Effective edge
Duty cycle match
Counter borrow
• Be sure to write duty cycle value PDUT after period value PCSR has been initialized and rewritten.
(Always write in the order of (1)PCSR and (2)PDUT.)
Only the PDUT can be written for rewriting the duty cycle.
• Set the duty cycle value PDUT smaller than the period value PCSR. If any larger value has been set,
disable the operation of the PPG before replacing the duty cycle with a smaller value.
• Always access PPG Period Setting registers PCSR and PPG Duty cycle Setting registers in a half-word (16bit) format. If these registers are byte-accessed, no values are written to their upper and lower bit positions.
• To activate a PPG, it is necessary to set the Timer Operation Enable bits (PCN:CNTE) to "1" before or
concurrently with the activation to enable the PPG operation.
• The values of mode (MDSE), restart enable (RTRG), count clock (CKS[1:0]), trigger input edge (EGS[1:0]),
interrupt cause (IRS), internal trigger (TSEL) and output polarity specification (OSEL) may not be changed
while the PPG is operating.
If any of these values has been changed while the PPG was operating, disable the operation of the PPG
before reloading the register.
• Whenever writing a value to GCN2, be sure to write "0" to any undefined part of the upper 4 bits.
If "1" is written, disable the operation of the PPG before reloading the register.
• If any value outside the specified range (0110B, 0111B, 1100B to 1111B) is set in Activation Trigger
Specification bits (TSEL0[3:0]), (TSEL1[3:0]), (TSEL2[3:0]), (TSEL3[3:0]) has been set, disable the operation
of the PPG and then write the specified value to let the register return to normal.
• If the Timer Operation Enable bit (PCN:CNTE) is set to "0" to disable PPGn while it is operating, the PPG
stops and sets its output value to the initial value ("1" if (OSEL "1") else "0"). The PPG timer is latched until
the operation of the timer is enabled by setting the Timer Operation enable bit (PCN:CNTE ) to "1".
• If (PCN:CNTE) is set to "1" to enable the PPG, it restarts (PPG timer is set to initial value).
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Chapter 36 Up/Down Counter (UDC)
36.1
MB91460N series
Chapter 36 Up/Down Counter (UDC)
36.1 Overview
Triggered by an input signal, 16-bit Up/Down Counter counts up or down within the range of 0 to 65535.
Specifically, Up/Down Counter running in the phase difference count mode is suitable for counting the encoder
pulse of motors and other equipment. When encoder's output signals of phase A, phase B and phase Z are
applied, the counter can achieve precise counting of rotation angles or number of revolutions.
Figure 36.1-1 Block diagram of an Up/Down Counter
Reload/Compare value
Edge detection
AIN
BIN
ZIN
Selection
Internal clock
Underflow/
Overflow
Reload
Interrupt:
- Compare
- Overflow/
Underflow
- Counter
direction
change
=
16-bit (or 2 × 8-bit) Up/Down Counter
Clear
Counter Direction
(Up/Down)
36.2 Feature
• Format: 16 bit length or 8 bit × 2
• Quantity: 1 for 16 bits (Inputs: AIN0/BIN0/ZIN0)
2 for 8 bits (Inputs: AIN0/BIN0/ZIN0, AIN1/BIN1/ZIN1)
• Count mode: Four types
• Timer mode
Count down the internal clock.
• Up/down count mode
Counting up is triggered by an AIN pin signal.
Counting down is triggered by a BIN pin signal.
• Phase difference count mode (Multiply by 2)
Counting is triggered by the rising and falling edges of a BIN pin signal. Up/Down Counter counts up or
down, depending on the AIN pin signal level.
• Phase difference count mode (Multiply by 4)
•
•
•
•
Counting is triggered by the rising and falling edges of AIN and BIN pin signals.
If an edge on AIN pin occurs, the Counter counts up or down, depending on the BIN pin signal level.
If an edge on BIN pin occurs, the Counter counts up or down, depending on the AIN pin signal level.
Count Source
Internal clock (Timer mode): Peripheral clock (CLKP) divided by 2 or 8
External trigger (Up/down count mode): Edge detection (Rising/falling/both edges/no detection)
Counting range: Any value between 0 and 65535 can be set.
Interrupt: Select from the following four types:
(1) Compare-match interrupt
(2) Underflow interrupt
(3) Overflow interrupt
(4) Count direction change interrupt
Others:
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MB91460N series
Whether counting is performed or not can be controlled based on the pin input level.
The software can activate or deactivate the counter.
The ZIN pin has two functions: Counter clear and gate.
The count direction flag allows identification of the previous count direction.
36.3 Configuration
Figure 36.3-1 Configuration Diagram of the Up/Down Counter 0 (8 bit mode)
Up/Down Counter 0 (8 Bit Mode)
8 bit mode
CFIE UDCC0: bit 13
0 Disable interrupts
1 Enable interrupts
M16E UDCC0: bit15
0
8 bit mode
CDCF UDCC0: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
CMS1,0
UDCC0: bit11,bit10
0 0 Timer mode (Countdown only)
0 1
Up/down count mode
1 0 Phase difference count mode (Multiply by 2)
1 1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
1
UDF1,0
0
1
0
1
UDC0 interrupt
(#128)
OR
UDCS0: bit1,bit0
Write: Disabled, Read only
No input
Countdown
Countup
Both countdown and countup
Up/Down Counter (Read only)
OVFF UDCS0: bit3
No overflow
0
Overflowed
1
UDIE UDCS0: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
Selector/Count Control
P20 EPFR20.0
Others
0
1 Enable UDC
CLKS UDCC0: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
Read from port
Edge
detection
AIN0/SIN2/P20.0
UDCR0
1
Reload
CTUT UDCC0: bit6
0
No impact
1
Data transfer
* Only 16 bit transfer is enabled
while counting stops.
CES1,0 UDCC0: bit9,bit8
Read 0 0
Disable edge detection
from
0 1 Enable falling edge detection
port
1 0 Enable rising edge detection
1 1 Enable both edge detection
From port data
ZIN0/SCK2/P20.2
P20 EPFR20.2
Others
0
1 Enable UDC
0
RLDE UDCC0: bit4
0 Disable reload
1 Enable reload
OR
1
0
WRITE 0: Flag clear
0
CMPF UDCS0: bit4
0 Compare match
1 No compare match
Compare
1
WRITE 0: Flag clear
OR
CITE UDCS0: bit6
0 Disable interrupts
1 Enable interrupts
UDRC0
Gate
register
UDFF UDCS0: bit2
0 No underflow
1 Underflowed
Counter clear
BIN0/SOT2/P20.1
576
0
0
1
1
CSTR UDCS0: bit7
0 Stop counting
1 Start counting
Activation
Prescaler
From port data
register
P20 EPFR20.1
Others
0
1 Enable UDC
0
Reload/compare register (Write only)
0
1
UCRE
UDCC0:bit5
Disable counter clear
0
Enable counter clear
1
UDCLR UDCC0: bit2
0
1
Read from
port
Edge
detection
From port data
register
Clear
Disabling
UDCC0: bit0 to bit 2
CGSC
CGE1,0 0: Counter clear function
0 0 Disable edge detection
0 1 Enable falling edge detection
1 0 Enable rising edge detection
Disable setting
1 1
1: Gate function
Disable level detection
Enable LOW level detection
Enable HIGH level detection
Disable setting
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Chapter 36 Up/Down Counter (UDC)
36.3
MB91460N series
Figure 36.3-2 Configuration Diagram of the Up/Down counter 1 (8 bit mode)
Up/Down Counter 1 (8 Bit Mode)
8 bit mode
CFIE UDCC1: bit 13
0 Disable interrupts
1 Enable interrupts
M16E UDCC0: bit15
0
8 bit mode
CDCF UDCC1: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
CMS1,0
UDCC1: bit11,bit10
0 0 Timer mode (Countdown only)
0 1
Up/down count mode
1 0 Phase difference count mode (Multiply by 2)
1 1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
1
UDF1,0
0
1
0
1
UDC1 interrupt
(#129)
OR
UDCS1: bit1,bit0
Write: Disabled, Read only
No input
Countdown
Countup
Both countdown and countup
Up/Down Counter (Read only)
OVFF UDCS1: bit3
No overflow
0
Overflowed
1
UDIE UDCS1: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
Selector/Count Control
CLKS UDCC1: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
P20 EPFR20.4
Others
0
1 Enable UDC
Read from port
Edge
detection
AIN1/SIN3/P20.4
UDCR1
1
Reload
CTUT UDCC1: bit6
0
No impact
1
Data transfer
* Only 16 bit transfer is enabled
while counting stops.
From port data
register
ZIN1/SCK3/P20.6
P20 EPFR20.6
Others
0
1 Enable UDC
0
RLDE UDCC1: bit4
0 Disable reload
1 Enable reload
CES1,0 UDCC1: bit9,bit8
0 0 Disable edge detection
0 1 Enable falling edge detection
1 0 Enable rising edge detection
1 1 Enable both edge detection
OR
1
0
WRITE 0: Flag clear
0
CMPF UDCS1: bit4
0 Compare match
1 No compare match
Compare
1
WRITE 0: Flag clear
OR
CITE UDCS1: bit6
0 Disable interrupts
1 Enable interrupts
UDRC1
Gate
Read
from
port
UDFF UDCS1: bit2
0 No underflow
1 Underflowed
Counter clear
BIN1/SOT3/P20.5
CM44-10149-1E
0
0
1
1
CSTR UDCS1: bit7
0 Stop counting
1 Start counting
Activation
Prescaler
From port data
register
P20 EPFR20.5
Others
0
1 Enable UDC
0
Reload/compare register (Write only)
0
1
UCRE
UDCC1:bit5
Disable counter clear
0
Enable counter clear
1
UDCLR UDCC1: bit2
0
1
Read from
port
Edge
detection
From port data
register
Clear
Disabling
UDCC1: bit0 to bit 2
CGSC
CGE1,0 0: Counter clear function 1: Gate function
0 0 Disable edge detection Disable level detection
0 1 Enable falling edge detection Enable LOW level detection
1 0 Enable rising edge detection Enable HIGH level detection
Disable setting
Disable setting
1 1
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Chapter 36 Up/Down Counter (UDC)
36.3
MB91460N series
Figure 36.3-3 Configuration Diagram of the Up/Down Counter (16 bit mode)
Up/Down Counter (16 Bit Mode)
16 bit mode
M16E
1
CFIE
UDCC0: bit 13
0
Disable interrupts
Enable interrupts
1
UDCC0: bit15
16 bit mode
0
1
CDCF UDCC0: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
0
0
1
1
CMS1,0
UDCC0: bit11,bit10
0 Timer mode (Countdown only)
Up/down count mode
1
0 Phase difference count mode (Multiply by 2)
1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
UDF1,0
UDF1
UDCS0: bit1,bit0
Write: Disabled, Read only
No input
0 0
Countdown
0 1
Countup
1 0
1 1 Both countdown and countup
Activation
CSTR UDCS0: bit7
0 Stop counting
1 Start counting
Read from port
AIN0/SIN2/P20.0
UDCR0
CTUT UDCC0: bit6
No impact
0
Data transfer
1
* Only 16 bit transfer is enabled
while counting stops.
OR
BIN0/SOT2/P20.1
RLDE UDCC0: bit4
0
Disable reload
1
Enable reload
UDRC1
OR
1
0
0
WRITE 0: Flag clear
0
Reload
Edge
detection
UDFF UDCS0: bit2
0 No underflow
1 Underflowed
1
Counter clear
Selector
P20 EPFR20.0
Others
0
1 Enable UDC
CLKS UDCC0: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
UDIE UDCS0: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
UDCR1
From port data
register
OVFF UDCS0: bit3
0 No overflow
Overflowed
1
Up/Down Counter (Read only)
Prescaler
UDC0 interrupt
(#128)
OR
CMPF UDCS0: bit4
Compare match
0
1 No compare match
Compare
1
WRITE 0: Flag clear
CITE UDCS0: bit6
0 Disable interrupts
1 Enable interrupts
UDRC0
Reload/compare register (Write only)
P20 EPFR20.1
Others
0
1 Enable UDC
Gate
Read
from
port
From port data
register
ZIN0/SCK2/P20.2
P20 EPFR20.2
0
Others
1 Enable UDC
0
CES1,0 UDCC0: bit9,bit8
Disable edge detection
0 0
0 1 Enable falling edge detection
Enable
rising edge detection
1 0
1 1 Enable both edge detection
Read from
port
0
1
Edge
detection
From port data
register
UCRE
UDCC0:bit5
Disable counter clear
0
Enable counter clear
1
UDCC0: bit2
Counter clear
No impact
CGE1,0
0
0
1
1
1
0
1
0
1
UDCC0: bit0 to bit2
CGSC
0: Counter clear function
1: Gate function
Disable edge detection Disable level detection
Enable falling edge detection Enable LOW level detection
Enable rising edge detection Enable HIGH level detection
Disable setting
Disable setting
Figure 36.3-4 Register List
Note: For ICR registers and interrupt vectors, refer to "Chapter 21 Interrupt Control (Page No.219)".
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Chapter 36 Up/Down Counter (UDC)
36.3
MB91460N series
Figure 36.3-5 Register List
Note: For ICR registers and interrupt vectors, refer to "Chapter 21 Interrupt Control (Page No.219)".
Figure 36.3-6 Register List
Note: For ICR registers and interrupt vectors, refer to "Chapter 21 Interrupt Control (Page No.219)".
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Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
36.4 Register
36.4.1 UDCC: Counter Control Register
This register is used to control behaviors of Up/Down Counter.
• UDCC0 (Up/Down Counter 0): Address 000304H (Access: Byte, Half-word)
• UDCC1 (Up/Down Counter 1): Address 000308H (Access: Byte, Half-word)
15
M16E/
Reserved
0
R/W *
7
Reserved
0
R/W0
14
13
12
11
10
9
8
bit
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
UDCCH
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
4
RLDE
0
R/W
3
UDCLR
1
R1,W
2
CGSC
0
R/W
1
CGE1
0
R/W
0
CGE0
0
R/W
bit
UDCCL
Initial value
Attribute
6
CTUT
0
R/W
5
UCRE
0
R/W
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit15: Enable 16 bit mode (Up/Down Counter 0 and 2 only)
M16E
0
1
Enable 16 bit mode
8 bit × 2 channel operation mode (8 bit mode)
16 bit × 1 channel operation mode (16 bit mode)
* Reserved bit (Up/Down Counter 1 and 3). Be sure to write 0. The read value is the value written.
• bit14: Count direction change flag (Interrupt flag)
CDCF
0
1
Direction change detection
When read:
No direction change occurred.
Clear the flag.
A direction change occurred once or more.
No effect.
When written:
• When the count direction has been changed during count operation, the count direction change flag
(CDCF) is set to "1".
• Since the count direction is set to countdown immediately after a reset, the count direction change flag
(CDCF) is set to "1" on counting up following the reset.
• To enable interrupt requests, the interrupt request enable bit must be set (CFIE=1).
• bit13: Enable count direction change interrupt request
CFIE
0
1
Direction change interrupt request
Disable direction change interrupt requests.
Enable direction change interrupt requests.
When the interrupt request enable bit is set to "1", the interrupt flag (CDCF) is enabled.
• bit12: Select internal prescaler
CLKS
0
1
Internal clock frequency
CLKP/2
CLKP/8
This setting is enabled only in the timer mode, in which only countdown is performed.
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Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
• bit11, bit10: Select count mode
CMS1
0
0
1
1
CMS0
0
1
0
1
Count mode
Timer mode (Countdown)
Up/down count mode
Phase difference count mode (Multiply by 2)
Phase difference count mode (Multiply by 4)
• bit9, bit8: Select count clock edge
CES1
0
0
1
1
CES0
0
1
0
1
Edge selection
Disable edge detection.
Detect a falling edge.
Detect a rising edge.
Detect both rising and falling edges.
This bit is used in the up/down count mode (CMS1,CMS0= 01) to select the edge, to be detected, of an AIN
and BIN pin signal. This setting is disabled in modes other than the up/down count.
• bit7: Reserved.
Be sure to write "0". The read value is the value written.
• bit6: Counter write
CTUT
0
1
Data transfer
No impact on operation
Transfer data from the RCR register to UDCR.
During count operation (CSR:CSTR=1), the counter write bit must not be set to "1".
• bit5: Enable compare-match clear
UCRE
0
1
Compare-match counter clear
Disable counter clear due to compare-match.
Enable counter clear due to compare-match.
This setting does not affect clear operations other than compare-match, such as ZIN pin clear.
• bit4: Enable reload
RLDE
0
1
Reload function
Disable reload function.
Enable reload function.
If the reload enable bit is set to "1", the reload/compare value (RCR) is transferred to Up/Down Counter
(UDCR) when Up/Down Counter is underflowed.
• bit3: Clear UDCR
UDCLR
0
Counter clear
Set (Clear) Up/Down Counter (UDCR) to "0000H".
1
No impact on operation
• bit2: Select counter clear/gate
CGSC
0
1
CM44-10149-1E
ZIN pin function
Counter clear function
Gate function
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Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
• bit1, bit0: Select counter clear/gate edge
582
CGE1
CGE0
0
0
1
1
0
1
0
1
Edge detection/level selection
When the counter clear function is selected
When the gate function is selected
(CGSC=0)
(CGSC=1)
Disable edge detection.
Disable level detection. (Disable count.)
Detect a falling edge.
Detect a "L" level.
Detect a rising edge.
Detect a "H" level.
Disable setting.
Disable setting.
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CM44-10149-1E
Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
36.4.2 UDCS: Count Status Register
This register is used to control Up/Down Counter and to indicate the status of the counter.
• UDCS0 (Up/Down Counter 0): Address 000307H (Access: Byte, Half-Word)
• UDCS1 (Up/Down Counter 1): Address 00030BH (Access: Byte, Half-Word)
7
CSTR
0
R/W
6
CITE
0
R/W
5
UDIE
0
R/W
4
CMPF
0
R/W0
3
OVFF
0
R/W0
2
UDFF
0
R/W0
1
UDF1
0
R/WX
0
UDF0
0
R/WX
bit
Initial value
Attribute
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• bit7: Enable count operation
CSTR
0
1
Count operation
Disable count operation.
Enable count operation. (Activate counter.)
• bit6: Enable compare-match interrupt requests
CITE
0
1
Compare-match interrupt request
Disable compare-match interrupt requests.
Enable compare-match interrupt requests.
Setting the interrupt request enable bit to "1" enables the interrupt flag (CMPF).
• bit5: Enable overflow/underflow interrupt request
UDIE
0
1
Overflow/underflow interrupt request
Disable overflow/underflow interrupt requests.
Enable overflow/underflow interrupt requests.
Setting the interrupt request enable bit to "1" enables the interrupt flag (OVFF or UDFF).
• bit4: Compare-match detection flag
CMPF
0
1
Compare-match detection
When read:
Comparison results do not match.
Comparison results match.
When written:
Clear the flag.
Without effect.
To enable interrupt requests, the interrupt request enable bit must be set (CITE= 1).
• bit3: Overflow detection flag
Overflow detection
OVFF
0
1
When read:
No overflow
An overflow has occurred.
When written:
Clear the flag.
Without effect.
To enable interrupt requests, the interrupt request enable bit must be set (UDIE= 1).
• bit2: Underflow detection flag
Underflow detection
UDFF
0
1
When read:
No Underflow
An underflow has occurred.
When written:
Clear the flag.
Without effect.
To enable interrupt requests, the interrupt request enable bit must be set (UDIE= 1).
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MB91460N series
• bit1,bit0: Up/down flag
UDF1
0
0
1
1
584
UDF0
0
1
0
1
Previous count operation
No input
Count down
Count up
Both of count up and count down
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CM44-10149-1E
Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
36.4.3 UDCR: Up/Down Counter Register
This register is used to read the count value of Up/Down Counter.
• UDCR10 (Up/Down Counter 0/1): Address 000302H (Access: Byte, Half-Word)
Depending on the setting of the 16-bit mode enable bit (CCR:M16E), this register behaves differently.
■ 16 Bit Mode (M16E=1)
In the 16 bit mode, this register functions as 16-bit up/down counter register.
• UDCR10 (Up/Down Counter): Address 000302H (Access: Half-word)
15
D15
0
R/WX
14
D14
0
R/WX
13
D13
0
R/WX
12
D12
0
R/WX
11
D11
0
R/WX
10
D10
0
R/WX
9
D09
0
R/WX
8
D08
0
R/WX
7
D07
0
R/WX
6
D06
0
R/WX
5
D05
0
R/WX
4
D04
0
R/WX
3
D03
0
R/WX
2
D02
0
R/WX
1
D01
0
R/WX
0
D00
0
R/WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
For the 16 bit mode, be sure to read by half-word access.
■ 8 Bit Mode (M16E=0)
In the 8 bit mode, this register functions as a 8-bit up/down counter register 0 and a 8-bit up/down counter
register 1.
• UDCR1 (Up/Down Counter 1): Address 000302H (Access: Byte, Half-word)
• UDCR0 (Up/Down Counter 0): Address 000303H (Access: Byte, Half-word)
7
D07
0
R/WX
6
D06
0
R/WX
5
D05
0
R/WX
4
D04
0
R/WX
3
D03
0
R/WX
2
D02
0
R/WX
1
D01
0
R/WX
0
D00
0
R/WX
bit
Initial value
Attribute
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
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Chapter 36 Up/Down Counter (UDC)
36.4
MB91460N series
36.4.4 UDRC: Up/Down Reload/Compare Register
This register is used to reload a value to Up/Down Counter and to compare the register value with the Counter
value.
This register is also used to write to Up/Down Counter.
• UDRC10 (Up/Down Counter 0/1): Address 000300H (Access: Byte, Half-Word)
Depending on the setting of the 16 bit mode enable bit (CCR:M16E), this register behaves differently.
■ 16 Bit Mode (M16E=1)
In the 16 bit mode, this register functions as 16-bit reload/compare register.
• UDCR10 (Reload compare): Address 000300H (Access: Byte, Half-word)
15
D15
0
RX, W
14
D14
0
RX, W
13
D13
0
RX, W
12
D12
0
RX, W
11
D11
0
RX, W
10
D10
0
RX, W
9
D09
0
RX, W
8
D08
0
RX, W
bit
7
D07
0
6
D06
0
5
D05
0
4
D04
0
3
D03
0
2
D02
0
1
D01
0
0
D00
0
Initial value
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
Attribute
Initial value
Attribute
bit
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• The reload and compare values are same.
When Up/Down Counter counts up, the value in RCR is used as a compare value.
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload
value for reloading.
(Up/Down Counter counts between 0000H and the reload/compare value.)
• In the 16 bit mode, be sure to write by half-word access.
■ 8 Bit Mode (M16E=0)
In the 8 bit mode, this register functions as 8-bit reload/compare register 0 and 8-bit reload/compare register 1.
• UDCR1 (reload compare 1): Address 000300H (Access: Byte, Half-word)
• UDCR0 (reload compare 0): Address 000301H (Access: Byte, Half-word)
7
D07
0
RX, W
6
D06
0
RX, W
5
D05
0
RX, W
4
D04
0
RX, W
3
D03
0
RX, W
2
D02
0
RX, W
1
D01
0
RX, W
0
D00
0
RX, W
bit
Initial value
Attribute
(For attributes, refer to "Meaning of Bit Attribute Symbols (Page No.11)".)
• The reload and compare values are same.
When Up/Down Counter counts up, the value in RCR is used as a compare value.
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload
value for reloading.
(Up/Down Counter counts between 00H and the reload/compare value.)
• Perform the following procedure to write to Up/Down Counter.
(1) Stop counting.
(2) Write a value to the reload/compare register.
(3) Write "1"to the counter write bit (CCR:CTUT).
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Chapter 36 Up/Down Counter (UDC)
36.5
MB91460N series
36.5 Operation
This section describes each operation mode for Up/Down Counter.
36.5.1 Timer Mode CMS[1:0]=00
Figure 36.5-1 Up/Down Counter in Timer Mode CMS[1:0]=00
Reload value
Reload value
CLKP divided by 2
Interrupt
request
Countdown
CLKP divided by 8
(5)
Reload value
(8)
(3)
CLKS,RLDE
CGSC
(9)
(1)
(2)
CSTR
(3)
(6)
Underflow flag
Interrupt request enabled
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(4)
Cleared by
software
(10)
(9)
Cleared by
software
Cleared by
software
(7)
An appropriate bit (Reload enable RLDE) is set.
Up/Down Counter is cleared ("0" is written to CGSC).
The software activates Up/Down Counter.
An underflow occurs.
The reload value is reloaded to Up/Down Counter.
The software clears the underflow flag.
The software enables interrupts.
Up/Down Counter counts down.
An underflow occurs. (An interrupt request has been made.)
The software clears the underflow flag.
Repeat (8) to (10).
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Chapter 36 Up/Down Counter (UDC)
36.5
MB91460N series
36.5.2 Up/Down Count Mode CMS[1:0]=01
Figure 36.5-2 Up/Down Counter in Up/Down Count Mode CMS[1:0]=01
ZIN=Clear control
(14)
(6)
Reload / Compare
value
(2)
Counter
operation
(5)
(8)
(4)
(12)
(7)
CSTR, RLDE, UCRE
(13)
(1)
CGSC
AIN
(9)
(2)
(10)
BIN
CGE[1:0]=10
ZIN (Clear)
Counter direction
change flag (CDCF)
(4)
(3)
(11)
Compare-match
flag (CMPF)
Underflow flag
(UDFF)
(15)
cleared by software
Up/Down Counter clear control using the ZIN pin
(1)
Appropriate bits (Counting enable CSTR, Reload enable RLDE, Clear enable UCRE) are set.
(2)
When pulse input to the AIN pin is detected, Up/Down Counter counts up.
(3)
The count direction change flag is set to "1".
(4)
When an edge is applied to the ZIN pin, Up/Down Counter is cleared.
(5)
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.
(6)
The Up/Down Counter's count value matches with the compare value (compare-match) and the
compare-match flag is set to "1".
(7)
Compare-match clears Up/Down Counter.
(8)
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.
(9)
When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(10) When pulse input to the BIN pin is detected, Up/Down Counter counts down.
(11) The count direction change flag is set to "1".
(12) Continuous pulse input to the BIN pin causes Up/Down Counter to count down.
(13) Up/Down Counter is underflowed and the underflow flag is set to "1".
(14) The underflow causes the reload value to be reloaded to Up/Down Counter.
(15) Next time when Up/Down Counter counts down, the compare-match flag is set to "1".
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Chapter 36 Up/Down Counter (UDC)
36.5
MB91460N series
36.5.3 Up/Down Count Mode CMS[1:0]=01
Figure 36.5-3 Up/Down Counter in Up/Down Count Mode CMS[1:0]=01
ZIN=Gate control
(12)
(6)
(7)
(2)
(5)
CS TR, RLDE, UCRE
UDCC
AIN
(1)
(2)
(3)
(6)
(12)
(9)
(7)
BIN
CGE[1:0]=10
(11)
(8)
(4)
“H”
(8)
(10)
“H”
(13)
ZIN (Gate)
Countgate at the ZIN pin
(1)
Appropriate bits (Counting enable CSTR, Reload enable RLDE and Clear enable UCRE) are set.
(2)
Up/Down Counter is cleared. ("0" is written to CGSC).
(3)
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither
counts up nor down.
(4)
Counting is enabled at the ZIN pin.
(5)
Up/Down Counter counts up.
(6)
When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(7)
When a pulse input to the BIN pin is detected, Up/Down Counter counts down.
(8)
When counting is disabled at the ZIN pin, Up/Down Counter stops counting.
(9)
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither
counts up nor down.
(10) Counting is enabled at the ZIN pin.
(11) Up/Down Counter counts up.
(12) When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(13) Counting is disabled at the ZIN pin.
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Chapter 36 Up/Down Counter (UDC)
36.5
MB91460N series
36.5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=10
Frequency multiplied by 2 in phase difference count mode:
On the rising and falling edges at the BIN count pin, Up/Down Counter counts up or down, depending on the
voltage level at the AIN pin.
Figure 36.5-4 Up/Down Counter in Phase Difference Count Mode (Multiply by 2) CMS[1:0]=10
Count value
Time
AIN
BIN
• Count up Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is "H"
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is "L"
• Count down Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is "L"
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is "H"
When this count mode is selected, selection of the edge to be detected using CES1 or CES0 is disabled.
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MB91460N series
Chapter 36 Up/Down Counter (UDC)
36.5
36.5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=11
Frequency multiplied by 4 in phase difference count mode:
On the rising and falling edges at the BIN pin, Up/Down Counter counts up or down, depending on the voltage
level at the AIN pin, and on the rising and falling edges at the AIN pin, Up/Down Counter counts up or down,
depending on the voltage level at the BIN pin.
Figure 36.5-5 Up/Down Counter in Phase Difference Count Mode (Multiply by 4) CMS[1:0]=11
Count value
Time
AIN
BIN
• Count up Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is "H"
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is "L"
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is "L"
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is "H"
• Count down Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is "L"
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is "H"
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is "H"
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is "L"
When Up/Down Counter is used to count encoder output, high precise counting of rotation angles and number
of revolutions, as well as detecting of rotation directions, can be achieved by applying encoder output signals
of phase A and phase B to the AIN and BIN, respectively.
Note that when this count mode is selected, selection of the edge to be detected using CES1 or CES0 is
disabled.
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Chapter 36 Up/Down Counter (UDC)
36.5
MB91460N series
36.5.6 Clear Timing
(1) When a clear request (Compare-match, ZIN edge detection and writing "0" to the clear bit UDCLR) is
made, clear is performed next time when Up/Down Counter counts up.
Figure 36.5-6 Clear Timing of Up/Down Counter (1)
Compare value
0066H
Count value
0065H
0066H
0000H
0001H
Clear request
Countup
Clear timing
(2) Even if a clear request (Compare-match, ZIN edge detection and writing "0" to the clear bit DCC) is made,
clear is not performed when UP/Down Counter counts neither up nor down.
Figure 36.5-7 Clear Timing of Up/Down Counter (2)
Compare value
0066H
Count value
0065H
0066H
0065H
Clear request
Countup
Countdown
Clear timing (None)
(3) If Up/Down Counter does not count up after a clear request (Compare-match, ZIN edge detection and
writing "0" to the clear bit DCC) is made, the counter is cleared when counting is disabled (CSTR=0).
Figure 36.5-8 Clear Timing of Up/Down Counter (3)
Compare value
0066H
Count value
0065H
0066H
0000H
Clear request
Countup
CSTR or ZIN gate function
Enable count
Disable count
(4) When Up/Down Counter exceeds the maximum count, the overflow flag is set to "1" and the counter value
is returned to "0000H".
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36.5
MB91460N series
Figure 36.5-9 Clear Timing of Up/Down Counter (4)
Count value
FFFEH
FFFFH
0000H
Countup
Overflow
36.5.7 Reload Timing
The next time when Up/Down Counter counts down below "0000", an underflow occurs (an interrupt request is
generated) and then reloading is performed.
Figure 36.5-10 Reload Timing of Up/Down Counter
Compare value
0066H
Count value
0001H
0000H
0066H
0065H
0064H
Countdown
Underflow
Reload timing
Note: If clear and reload operations occur at the same time, clear takes precedence.
36.5.8 Writing a Value to Counter
Figure 36.5-11 Writing value to Up/Down Counter
(2)
RCR
XXH
67H
67H
Up/Down Counter
CSTR
CTUT
(1)
(2)
(3)
(4)
(4)
(1)
(3)
Counting of Up/Down Counter is disabled.
A value is written to PCR.
"1" is written to the count write bit CTUT.
A value is transferred from the reload/compare register RCR to Up/Down Counter.
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Chapter 36 Up/Down Counter (UDC)
36.6
MB91460N series
36.6 Setting
Table 36.6-1 Required Settings to Run Up/Down Counter in Timer Mode
Setting
Setting registers
Setting
procedure*
Set the reload value.
Reload/compare register (UDRC)
See 36.7.16
(Optional)
Set a value to Up/Down Counter
or
Clear the count value of Up/Down Counter.
Reload/compare register (UDRC)
See 36.7.5
Count control register (UDCC)
See 36.7.8
Set a bit length.
See 36.7.1
Set the count mode to timer mode.
See 36.7.2
Select a count source.
See 36.7.3
Count control register (UDCC)
Enable reloading at the time of underflow.
See 36.7.7
See
36.7.9 and 36.7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
Count status register (UDCS)
See 36.7.11
*: For the setting procedure, refer to the section indicated by the number.
Table 36.6-2 Required Settings to Run Up/Down Counter in Up/Down Count Mode
Setting
Setting registers
Setting
procedure*
Set the reload value/compare value.
Reload/compare register (UDRC)
See 36.7.16
(Optional)
Set a value to Up/Down Counter
Or
Clear the count value of Up/Down Counter.
Reload/compare register (UDRC)
See 36.7.5
Count control register (UDCC)
See 36.7.8
Set a bit length.
See 36.7.1
Set the count mode to up/down count mode.
See 36.7.2
Select the edge, to be detected, of a signal (AIN or BIN),
for which counting is performed.
Enable clearing of Up/Down Counter at the time of the
counting following a compare-match.
Enable reloading at the time of underflow.
Count control register (UDCC)
See 36.7.6
See 36.7.7
See
36.7.9 and 36.7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
See 36.7.4
Count status register (UDCS)
See 36.7.11
*: For the setting procedure, refer to the section indicated by the number.
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36.6
MB91460N series
Table 36.6-3 Required Settings to Run Up/Down Counter in Phase Difference Count Mode (Multiply by
2 or 4)
Setting
Setting registers
Setting
procedure*
Set the reload value/compare value.
Reload/compare register (UDRC).
See 36.7.16
(Optional)
Set a value to Up/Down Counter
or
Clear the count value of Up/Down Counter.
Reload/compare register (UDRC)
See 36.7.5
Count control register (UDCC)
See 36.7.8
Set a bit length.
See 36.7.1
Set the count mode to phase difference count mode
(Multiply by 2 or 4).
Enable clearing of Up/Down Counter at the time of the
counting following a compare-match.
Enable reloading at the time of underflow.
See 36.7.2
Count control register (UDCC)
See 36.7.7
See
36.7.9 and 36.7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
See 36.7.6
Count status register (UDCS)
See 36.7.11
*: For the setting procedure, refer to the section indicated by the number.
Table 36.6-4 Required Settings for Up/Down Counter Interrupt
Setting
Set Up/Down Counter interrupt vectors and Up/Down
Counter interrupt levels.
Set Up/Down Counter interrupts.
Clear interrupts.
Enable interrupt requests.
Setting registers
Setting
procedure*
Refer to "Chapter 21 Interrupt Control
(Page No.219)".
See 36.7.17
Count control register (UDCC)
Count status register (UDCS)
See 36.7.19
*: For the setting procedure, refer to the section indicated by the number.
Table 36.6-5 Required Settings to Deactivate Up/Down Counter
Setting
Deactivate Up/Down Counter
(Controlled through the ZIN pin)
Deactivate Up/Down Counter.
Setting registers
Setting
procedure*
Count control register (UDCC)
See 36.7.10
Count status register (UDCS)
See 36.7.11
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 36 Up/Down Counter (UDC)
36.7
MB91460N series
36.7 Q&A
36.7.1 How to select a bit length (8 or 16) of Up/Down Counter
Use the 16 bit mode enable bit (UDCC:M16E).
Up/Down Counter's bit length
To set the bit length to 8
To set the bit length to 16 bit
16 bit mode enable bit (M16E)
Set the bit to "0".
Set the bit to "1".
36.7.2 What types of count modes are available and how are they set?
There are four types of count modes:
Timer, Up/down count, Phase difference count (Multiply by 2 or 4)
Use the count mode selection bits (UDCC:CMS[1:0]) to set a count mode.
Count mode
To set the count mode to timer
Count mode selection bit (CMS[1:0])
Set the bit to "00B".
To set the count mode to up/down count
Set the bit to "01B".
To set the count mode to phase difference count
(Multiply by 2)
To set the count mode to phase difference count mode
(Multiply by 4)
Set the bit to "10B".
Set the bit to "11B".
36.7.3 How to select a count source for Up/Down Counter running in the timer mode
Use the internal prescaler select bit (UDCC:CLKS).
Count source for timer mode
To obtain the CLKP divided by 2
To obtain the CLKP divided by 8
Internal prescaler select bit (CLKS)
Set the bit to "0".
Set the bit to "1".
36.7.4 How to select the edge with which Up/Down Counter running in the Up/down
count mode detects an input signal (AIN or BIN)
Use count clock edge select bits (UDCC:CES[1:0]).
Edge to be detected by counter
To disable detection
Count clock edge select bit (CES[1:0])
Set the bit to "00B".
To enable detection of a falling edge
Set the bit to "01B".
To enable detection of a rising edge
Set the bit to "10B".
To enable detection of both edges
Set the bit to "11B".
36.7.5 How to set a value to Up/Down Counter
A value can be set to Up/Down Counter by writing the value to the reload/compare register (RCR) and then
writing "1" to the counter write bit (UDCC:CTUT).
36.7.6 When the Up/Down Counter's count-up value matches with the compare value
(RCR[0:1]), how to enable clearing of Up/Down Counter the next time when the
counter counts up
Use the up/down counter clear enable bit (UDCC:UCRE).
When the count-up value matches with the compare
value and then Up/Down Counter counts up:
To disable clearing of Up/Down Counter
To enable clearing of Up/Down Counter
596
Up/down counter clear enable bit (UCRE)
Set the bit to "0".
Set the bit to "1".
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Chapter 36 Up/Down Counter (UDC)
36.7
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36.7.7 How to enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when
Up/Down Counter is underflowed
Use the reload enable bit (UDCC:RLDE).
When the count-up value matches with the compare
value:
To disable reloading of the reload value (RCR) to Up/
Down Counter
To enable reloading of the reload value (RCR) to Up/Down
Counter
Reload enable bit (RLDE)
Set the bit to "0".
Set the bit to "1".
36.7.8 How to clear Up/Down Counter
Up/Down Counter can be cleared in any of the following ways:
• Writing "0" to the up/down counter clear bit (UDCC:UDCLR).
• Applying an edge to the ZIN pin (For details, refer to 36.7.9)
• When the compare value matches with the Up/Down Counter's count-up value.
• When Up/Down Counter tries to count up after reaching the maximum count.
• Reset input (INITX pin input, watchdog reset, software reset)
36.7.9 How to clear Up/Down Counter using the ZIN pin
Use counter clear gate bit (UDCC:CGSC) and counter clear gate edge select bits (UDCC:CGE[1:0]). (These
bits are enabled in the up/down count mode.)
To disable edge detection (clear)
Set the bit to "0".
Counter clear gate
edge select bit
(CGE[1:0])
Set the bit to "00B".
To clear Up/Down Counter on the falling edge
Set the bit to "0".
Set the bit to "01B".
To clear Up/Down Counter on the rising edge
Set the bit to "0".
Set the bit to "10B".
Counter clear gate bit
(CGSC)
ZIN pin input
GCE[1:0]=11 indicates that setting is disabled.
36.7.10 How to control Up/Down Counter's count operation using the ZIN pin
Use counter clear gate bit (UDCC:CGSC) and counter clear gate edge select bits (UDCC:CGE[1:0]). (These
settings are enabled for all the count modes.)
ZIN pin input
Counter clear gate bit
(CGSC)
To disable level detection (counting)
Set the bit to "1".
Counter clear gate
edge select bit
(CGE[1:0])
Set the bit to "00B".
Set the bit to "1".
Set the bit to "01B".
Set the bit to "1".
Set the bit to "10B".
To start counting up or down at the "L" level
To stop counting up or down at the "H" level
To stop counting up or down at the "L" level
To start counting up or down at the "H" level
GCE[1:0]= 11 indicates that setting is disabled.
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36.7.11 How to enable/disable Up/Down Counter's count operation
Use the count activate bit (UDCS:CSTR).
When the count-up value matches with the compare value:
To disable Up/Down Counter's count operation
To enable Up/Down Counter's count operation
(To activate count operation)
Count activate bits (UDCS:CSTR)
Set the bit to "0".
Set the bit to "1".
• How to start counting
Timer mode
Up/down count mode
Counting starts using the internal clock (See 36.7.3)
Counting starts when the edge of an AIN or BIN pin input signal is detected.
(See 36.7.4)
Phase difference count mode Counting starts when a phase difference between AIN and BIN pins is
detected.
Note that the count operation enable level must be detected, before the ZIN pin's gate function can be
selected.
36.7.12 How to know the previous count direction (the current rotation direction)
Use the up/down flags (UDCS: UDF[1:0]).
Up/down flag (UDF[1:0])
"00B" indicates that no counting is performed after resetting.
"01B" indicates that counting down is performed.
"10B" indicates that counting up is performed.
"11B" indicates that both counting up and down are performed, resulting in no change in the count value.
This flag has nothing to do with interrupts. So, use the count direction change flag (UDCC:CDCF) for interrupt
processing.
36.7.13 How to know count direction changes
Use the count direction change flag (UDCC:CDCF).
Count direction change flag (CDCF)
"0" indicates that no direction change has been made after clearing the flag.
"1" indicates that a direction change has been made once or more after clearing the flag.
36.7.14 How to know that a compare-match has occurred
Use the compare-match detection flag (UDCS:CMPF).
Compare-match detection flag (CMPF)
"0" indicates that the Up/Down Counter's count value does not match with the compare value.
"1" indicates that the Up/Down Counter's count value matches with the compare value.
Regardless of counter operations (counting up/down, or a value being set or reloaded), the compare-match
detection flags are set to "1" when the count value matches with the compare value.
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36.7.15 How to know that an overflow or underflow has occurred
Use the overflow detection flag (UDCS:OVFF) and the underflow detection flag (UDCS:UDFF).
OVFF =1 indicates that Up/Down Counter has been overflowed.
UDFF =1 indicates that Up/Down Counter has been underflowed.
36.7.16 How to set the reload/compare value
Set a value to the reload/compare registers (UDRC). (This value is used as a compare or reload value.)
36.7.17 What are interrupt-related registers?
Configure the up/down counter interrupt vectors and up/down counter interrupt level settings.
The following table shows the relationship among the up/down counter number, interrupt levels and vectors:
For details on interrupt levels and interrupt vectors, refer to "Chapter 21 Interrupt Control (Page No.219)".
Up/Down Counter 0/1 (16 bit)
Up/Down Counter 0 (8 bit)
Up/Down Counter 1 (8 bit)
Interrupt vector
(Default)
#128
Address: 0FFDFCH
#129
Address: 0FFDF8H
Interrupt level set bit (ICR[4:0])
Interrupt level register (ICR56) Address:
000478H
The following interrupt flags are not automatically cleared:
•
Count direction change: UDCC:CDCF
•
Compare-match detection: UDCS:CMPF
•
Overflow: UDCS:OVFF
•
Underflow: UDCS:UDFF
So, the software must write "0" to the interrupt flag before control is returned from interrupt processing.
36.7.18 What interrupts are available and how are they selected?
There are four interrupt causes:
• Count direction change
• compare-match
• overflow
• underflow
An interrupt request is made by combining (logical OR) these four interrupt causes; each interrupt cause
cannot be isolated.
Use the interrupt request enable bit to enable a desired interrupt request.
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36.7
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36.7.19 How to enable (select), disable or clear interrupts
Interrupt request enable bits and interrupt flags
To enable (select) interrupts, use the following interrupt request enable bits:
• Count direction change interrupt request enable bits : UDCC:CFIE
• Compare-match interrupt request enable bits
: UDCS:CITE
• Overflow/underflow interrupt request enable bits
: UDCS:UDIE
Interrupt request enable bits (CFIE, CITE and UDIE)
Set the bit to "0".
Set the bit to "1".
To disable interrupt requests
To enable interrupt requests
To clear interrupts, use the following interrupt flags:
•
For count direction changes
: UDCC:CDCF
•
For compare-match detection
: UDCS:CMPF
•
For overflow
: UDCS:OVFF
•
For underflow
: UDCS:UDFF
To clear terrupts
600
Interrupt flags (CDCF, CMPF, OVFF and UDFF)
Write "0".
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Chapter 36 Up/Down Counter (UDC)
36.8
MB91460N series
36.8 Caution
• The count direction is set to "countdown" immediately after resetting the counter. So, when the counter
counts up immediately after resetting, the count direction change bit (UDCC:CDCF) is set to "1" to indicate a
direction change has been made.
• When the up/down counter register UDCR has reached the maximum count, the overflow flag is set to 1 and
counting continues. This time UDCR is cleared.
• The minimum pulse width for AIN, BIN and ZIN signals is 2 × T (T=1/CLKP: Period of a peripheral clock)
• If it is determined whether a change has been made to the count direction change interrupt and count
direction flags, it must be taken into consideration that when several direction changes have been made
continuously in a short period of time, the count direction flag may be returned to the original value, which
looks as if no change has been made.
• The compare-match detection flag (UDCS:CMPF) is set to "1" when Up/Down Counter's count value
matches with the compare value during both counting up and down. These flags are also set to 1 when:
• The reload value is reloaded to Up/Down Counter; or
• The Up/Down Counter's count value matches with the compare value when Up/Down Counter is
activated.
• The Up/Down Counter's count value is cleared by a clear request which is generated:
• On the edge of a signal input from the ZIN pin;
• By writing "0" to the up/down counter clear bit (UDCC:UDCLR); or
• When the compare value matches with the count value.
In addition,
• On reset input (INITX pin input, RST and watchdog reset); or
• When the counter counts up from the maximum account,
the count value is also set to "0000H".
• When Up/Down Counter clear and reload requests are made at the same time, the clear operation has
higher priority.
• When Up/Down Counter is counting up, writing to the counter is disabled.
Writing "1" to the counter write bit (UDCC:CTUT) after writing to the UDRC register is disabled. If writing to
the reload register and a reload operation occurs at the same time, the writing to the reload register is not
performed.
• The software cannot clear the up/down flags (UDCS:UDF[1:0]) to "0". Only reset (initialization) can clear the
flag to "0".
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36.8
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Chapter 37 A/D Converter (ADC)
37.1
MB91460N series
Chapter 37 A/D Converter (ADC)
This chapter provides an overview of the A/D converter (ADC), describing the register structure, fuctions and
operation.
37.1 Overview of A/D Converter
The A/D converter converts analog input voltage into digital values and provides the following features.
-
Features of A/D converter:
•
•
•
•
•
•
Conversion time: minimum 3µs per channel.
RC type successive approximation conversion with sample & hold circuit
10-bit or 8-bit resolution
Program section analog input from 8 channels
Single conversion mode: This mode selects and converts 1 channel.
Scan conversion mode: This mode converts the plural channels which continued and programs 8
channels at the maximum.
Single shot conversion mode: Convert the specified channels only once.
Continuous mode:
Repeatedly convert the specified channels.
Stop mode:
Convert one channel then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
• A/D conversion can be followed by an A/D conversion interrupt request to CPU if Interrupt Request
Enable bit (See "[bit 5] INTE (Interrupt enable)" on P. 609) is set. This interrupt, an option that is ideal for
continuous processing, can be used to start a DMA transfer of the results of A/D conversion to memory.
•
Startup may be triggered by software, external trigger (falling edge) or timer (rising edge).
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Chapter 37 A/D Converter (ADC)
37.1
MB91460N series
■ Input impedance
Sampling circuit of A/D converter is expressed in Figure 37.1-1 Input Impedance
Figure 37.1-1 Input Impedance
ADC
Analog
signal
source
Rext
ANx
Rin
Analog SW
Cin
Rext: external resistor
Rin: internal resistor
Cin: sample capacity
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Chapter 37 A/D Converter (ADC)
37.2
MB91460N series
37.2 Block Diagram of A/D Converter
Following figure shows the block diagram of A/D converter.
Figure 37.2-1 Block diagram of A/D converter
AVCC
MPX
AVRH/L AVSS
D/A converter
Sequential
comparison register
Sample & Hold
circuit
Decoder
R - Bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
input circuit
Comparator
A/D data register (ADCR)
Interrupt #134
A/D control register 0
A/D control register 1
ADCS 0/1
Operating
Clock
ATGX
16- bit
Reload Timer
CLKP
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37.3
MB91460N series
37.3 Registers of A/D Converter
The A/D converter has the following registers.
• • A/D enable register (ADER)
• • A/D control status register (ADCS)
• • Data register (ADCR)
• • Sampling timer setting register (ADCT)
• • Start channel setting register (ADSC)
• • End channel setting register (ADEC)
■ Register list
• ADERL (ADC0): Address 0001A2H (Access: Word, Half-word, Byte)
15
Reserved
0
R/W
14
Reserved
0
R/W
13
Reserved
0
R/W
12
Reserved
0
R/W
11
Reserved
0
R/W
10
Reserved
0
R/W
9
Reserved
0
R/W
8
Reserved
0
R/W
7
ADE7
0
R/W
6
ADE6
0
R/W
5
ADE5
0
R/W
4
ADE4
0
R/W
3
ADE3
0
R/W
2
ADE2
0
R/W
1
ADE1
0
R/W
0
ADE0
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• ADCS1 (ADC0): Address 0001A4H (Access: Half-word, Byte)
15
BUSY
0
R/W
14
INT
0
R/W
13
INTE
0
R/W
12
PAUS
0
R/W
11
STS1
0
R/W
10
STS0
0
R/W
9
STRT
0
R/W
8
reserved
0
R/W
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• ADCS0 (ADC0): Address 0001A5H (Access: Half-word, Byte)
7
MD1
0
R/W
6
MD0
0
R/W
5
S10
0
R/W
4
ACH4
0
R
3
ACH3
0
R
2
ACH2
0
R
1
ACH1
0
R
0
ACH0
0
R
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• ADCR1 (ADC0): Address 0001A6H (Access: Word, Half-word, Byte)
15
0
R0
14
0
R0
13
0
R0
12
0
R0
11
0
R0
10
0
R0
9
D9
X
R
8
D8
X
R
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
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MB91460N series
• ADCR0 (ADC0): Address 0001A7H (Access: Word, Half-word, Byte)
7
D7
X
R
6
D6
X
R
5
D5
X
R
4
D4
X
R
3
D3
X
R
2
D2
X
R
1
D1
X
R
0
D0
X
R
Bit
Initial value
Attribute
(See "Meaning of Bit Attribute Symbols (Page No.11)" for details of the attributes.)
• ADCT1 (ADC0): Address 0001A8H (Access: Word, Half-word, Byte)
15
CT5
0
R/W
14