The following document contains information on Cypress products. FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM71-10151-2E FR80 32-BIT MICROCONTROLLER MB91625 Series HARDWARE MANUAL FR80 32-BIT MICROCONTROLLER MB91625 Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED MB91625 Series Preface Thank you for your continued use of Fujitsu microelectronics semiconductor products. Read this manual and "Data Sheet" thoroughly before using products in the MB91625 series. ■ Purpose of this manual and intended readers This manual explains the functions and operations of the MB91625 series and describes how it is used. The manual is intended for engineers engaged in the actual development of products using the MB91625 series. Note: FR is an abbreviation for the FUJITSU RISC controller, which is a product of Fujitsu Microelectronics Limited. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ Sample programs and development environment Fujitsu Microelectronics offers sample programs free of charge for using the peripheral functions of the FR80 family. Fujitsu Microelectronics also makes available descriptions of the development environment required for the MB91625 series. Feel free to use them to verify the operational specifications and usage of this Fujitsu microelectronics microcontroller. • Microcontroller support information: http://edevice.fujitsu.com/micom/en-support/ * Note that the sample programs are subject to change without notice. Since they are offered as a way to demonstrate standard operations and usage, evaluate them sufficiently before running them on your system. Fujitsu microelectronics assumes no responsibility for any damage that may occur as a result of using a sample program. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED i MB91625 Series • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2009-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved. ii FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series Manuals That Make Up the Manuals for This Series The manuals used for this series are listed below. See the manual appropriate to the applicable conditions. The contents of these manuals are subject to change without notice. Contact us to check the latest versions available. ■ Hardware manual • FR80 FAMILY MB91625 SERIES HARDWARE MANUAL (CM71-10151) (this manual) ■ Data sheet • MICROCONTROLLER 32-bit ORIGINAL FR80 FAMILY MB91625 SERIES DATA SHEET (DS07-16908) ■ Programming manual • FR80 FAMILY PROGRAMMING MANUAL (CM71-00104) This manual explains a programming model and instructions for the FR80 family CPUs. ■ Hardware tool-related manual • DSU-FR EMULATOR MB2198-01 HARDWARE MANUAL (CM71-00413) This manual explains emulator handling and specifications, and it explains how to connect and operate the emulator. ■ Software tool-related manuals • SOFTUNETM WORKBENCH OPERATION MANUAL for V6 (CM71-00328) This manual explains how to operate the integrated development environment called SOFTUNE and the development procedures. • SOFTUNETM WORKBENCH USER'S MANUAL for V6 (CM71-00329) This manual explains the basic functions and dependent functions of SOFTUNE Workbench. • SOFTUNETM WORKBENCH COMMAND REFERENCE MANUAL for V6 (CM71-00330) This manual explains the commands and built-in variables/functions of SOFTUNE Workbench. • FR FAMILY 32-BIT MICROCONTROLLER EMBEDDED C PROGRAMMING MANUAL FOR APPLICATION (CM71-00324) This manual describes the know-how for creating built-in systems using the C compiler fcc911 for the FR family. The manual explains how to create efficient C programs using the architecture of the FR family and provides the notes. • FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6 (CM81-00206) Refer to this manual when using SOFTUNE C/C++ compiler to create/develop application programs in C and C++. • FR FAMILY SOFTUNETM ASSEMBLER MANUAL for V6 (CM71-00203) This manual explains the functions of Fujitsu SOFTUNETM Assembler operating in Windows 98, Windows Me, Windows 2000, or Windows XP and how to use it. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED iii MB91625 Series • SOFTUNETM LINKAGE KIT MANUAL for V6 (CM71-00327) This manual explains the functions of Fujitsu SOFTUNETM Linkage Kit operating in Windows 98, Windows Me, Windows 2000, or Windows XP and how to use it. See the manual when developing an application program. • FR Family ABSOLUTE ASSEMBLY LIST GENERATOR TOOL MANUAL (CM71-00305) This manual explains absolute assemble lists. • FR-V/FR FAMILY SOFTUNE C/C++ ANALYZER MANUAL for V5 (CM81-00309) This manual explains the functions of C/C++ Analyzer and how to use it. • FR-V/FR FAMILY SOFTUNE C/C++ CHECKER MANUAL for V5 (CM81-00310) This manual explains the functions of C/C++ Checker and how to use it. ■ REALOS-related manuals ● REALOS μITRON3.0-related manuals • FR/F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNETM REALOSTM/FR/907/896 CONFIGURATOR MANUAL (CM71-00322) This manual explains the functions and operations of SOFTUNE REALOS Configurator. • FR-V/FR/F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNETM REALOSTM/ANALYZER MANUAL (CM81-00315) This manual explains the functions provided by SOFTUNE REALOS Analyzer and how to utilize the functions. • FR FAMILY IN CONFORMANCE WITH μITRON 3.0 SPECIFICATIONS SOFTUNE REALOS/ FR USER'S GUIDE (CM71-00320) This manual explains the configuration/activation of REALOS/FR application systems. See the manual when performing comprehensive work for an entire system. • FR FAMILY IN CONFORMANCE WITH μITRON 3.0 SPECIFICATIONS SOFTUNE REALOS/ FR KERNEL MANUAL (CM71-00321) This manual explains the functions provided by SOFTUNE REALOS/FR and how to utilize the functions. See the manual when creating an application system or user program. ● REALOS μITRON4.0-related manuals • FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM REALOSTM/FR Spec.4 PROGRAMMING MANUAL (CM81-00316) This manual explains the functions provided by SOFTUNE REALOS/FR Spec.4 and how to utilize the functions. • FR-V/FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM REALOSTM KERNEL MANUAL (CM81-00312) This manual explains the functions provided by SOFTUNE REALOS/FRV/FR Spec.4 and how to utilize the functions. • FR-V/FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM REALOSTM CONFIGURATOR MANUAL (CM81-00311) This manual explains the functions provided by SOFTUNE REALOS Configurator (GUI) and how to utilize the functions. iv FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series • FR-V/FR /F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNE REALOSTM ANALYZER MANUAL (CM81-00315) This manual explains the functions provided by SOFTUNE REALOS Analyzer and how to utilize the functions. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED v MB91625 Series How to Use This Manual ■ Finding a function The following methods can be used to search for the explanation of a desired function in this manual: • Search from the table of the contents The table of the contents lists the manual contents in the order of description. • Search from the register list The register list lists all the registers of this device. You can look up the name of a desired register on the list to find the address of its location or the page that explains it. The address where each register is located is not described in the text. To verify the address of a register, see "APPENDIX A I/O Map", and "APPENDIX B List of Registers". • Search from the index You can look up the keyword such as the name of a peripheral function in the index to find the explanation of the function. ■ About the chapters Basically, this manual explains 1 peripheral function per chapter. ■ Terminology This manual uses the following terminology. Term vi Explanation Word Indicates access in units of 32 bits. Half word Indicates access in units of 16 bits. Byte Indicates access in units of 8 bits. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 CHAPTER 2 2.1 2.2 2.3 2.4 Overview ........................................................................................................1 MB91625 Series Overview .....................................................................................................................2 MB91625 Series Product Configuration .................................................................................................7 MB91625 Series Block Diagram .............................................................................................................8 Package Dimensions ..............................................................................................................................9 Pins of the MB91625 Series .......................................................................11 Pin Assignment Diagram ......................................................................................................................12 Pin Functions ........................................................................................................................................13 I/O Circuit Types ...................................................................................................................................27 Setting Method for Pins ........................................................................................................................31 CHAPTER 3 CPU ..............................................................................................................61 3.1 Memory Space ......................................................................................................................................62 3.2 Features of the Internal Architecture ....................................................................................................64 3.3 Operation Modes ..................................................................................................................................65 3.4 Pipeline .................................................................................................................................................66 3.5 Overview of Instructions .......................................................................................................................68 3.5.1 Arithmetic Operation ........................................................................................................................68 3.5.2 Load and Store ................................................................................................................................68 3.5.3 Branch .............................................................................................................................................69 3.5.4 Logical Operation and Bit Operation ...............................................................................................69 3.5.5 Direct Addressing ............................................................................................................................69 3.5.6 Bit Search ........................................................................................................................................69 3.5.7 Other ................................................................................................................................................69 3.6 Basic Programming Model ....................................................................................................................70 3.7 Registers ...............................................................................................................................................71 3.7.1 General-purpose Registers (R0 to R15) ..........................................................................................71 3.7.2 Program Status Register (PS) .........................................................................................................72 3.7.3 Program Counter (PC) .....................................................................................................................77 3.7.4 Table Base Register (TBR) .............................................................................................................78 3.7.5 Return Pointer (RP) .........................................................................................................................79 3.7.6 System Stack Pointer (SSP) ............................................................................................................80 3.7.7 User Stack Pointer (USP) ................................................................................................................81 3.7.8 Multiply & Divide Registers ..............................................................................................................82 3.8 Data Configuration ................................................................................................................................83 3.8.1 Bit Ordering .....................................................................................................................................83 3.8.2 Byte Ordering ..................................................................................................................................84 3.8.3 Word Alignment ...............................................................................................................................85 3.9 Addressing ............................................................................................................................................86 3.9.1 Direct Addressing Areas ..................................................................................................................86 3.9.2 20-bit Addressing Area ....................................................................................................................87 3.9.3 32-bit Addressing Area ....................................................................................................................87 3.9.4 Vector Table Initial Area ..................................................................................................................87 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED vii MB91625 Series 3.10 Branch Instructions .............................................................................................................................. 88 3.10.1 Operation with Delay Slots ............................................................................................................. 88 3.10.2 Operation without Delay Slots ........................................................................................................ 90 3.11 EIT (Exception, Interrupt, Trap) ........................................................................................................... 91 3.11.1 EIT Sources .................................................................................................................................... 91 3.11.2 Return from EIT .............................................................................................................................. 91 3.11.3 Interrupt Level ................................................................................................................................. 92 3.11.4 I Flag ............................................................................................................................................... 93 3.11.5 Interrupt Level Mask Register (ILM) ............................................................................................... 94 3.11.6 Level Mask for Interrupts ................................................................................................................ 94 3.11.7 Interrupt Control Register (ICR) ...................................................................................................... 95 3.11.8 System Stack Pointer (SSP) ........................................................................................................... 95 3.11.9 Interrupt Stack ................................................................................................................................ 95 3.11.10 Table Base Register (TBR) ............................................................................................................. 96 3.11.11 EIT Vector Table ............................................................................................................................. 96 3.11.12 Multi-EIT Processing ....................................................................................................................... 97 3.11.13 Operation ........................................................................................................................................ 98 3.11.14 INT Instruction Operation ................................................................................................................ 99 3.11.15 INTE Instruction Operation ........................................................................................................... 100 3.11.16 Step Trace Trap Operation ........................................................................................................... 100 3.11.17 Undefined Instruction Exception Operation .................................................................................. 101 3.11.18 RETI Instruction Operation ........................................................................................................... 101 3.11.19 Delay Slots and EIT ...................................................................................................................... 101 CHAPTER 4 Clock Generating Parts ............................................................................ 103 4.1 Overview ............................................................................................................................................ 104 4.2 Configuration ..................................................................................................................................... 105 4.2.1 Clock Generating Parts ................................................................................................................. 105 4.2.2 Source Clock (SRCCLK) Selection Block ..................................................................................... 108 4.3 Pins .................................................................................................................................................... 109 4.4 Registers ............................................................................................................................................ 110 4.4.1 Clock Source Select Register (CSELR) ........................................................................................ 111 4.4.2 Clock Source Monitor Register (CMONR) .................................................................................... 115 4.4.3 Clock Stabilization Time Select Register (CSTBR) ...................................................................... 118 4.4.4 PLL Configuration Register (PLLCR) ............................................................................................ 121 4.5 Explanation of Operations ................................................................................................................. 125 4.5.1 Explanation of Clock Source Operations ...................................................................................... 125 4.5.2 Switching the Source Clock (SRCCLK) ....................................................................................... 128 4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK) ................................................................. 131 CHAPTER 5 Clock Division Control Part ..................................................................... 133 5.1 Overview ............................................................................................................................................ 134 5.2 Internal Clocks ................................................................................................................................... 135 5.3 Configuration ..................................................................................................................................... 137 5.4 Registers ............................................................................................................................................ 138 5.4.1 Divide Clock Configuration Register 0 (DIVR0) ............................................................................ 139 5.4.2 Divide Clock Configuration Register 2 (DIVR2) ............................................................................ 141 5.5 Division Rate ...................................................................................................................................... 143 viii FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 6 Main Timer .................................................................................................145 6.1 Overview .............................................................................................................................................146 6.2 Configuration ......................................................................................................................................147 6.3 Registers .............................................................................................................................................148 6.3.1 Main Timer Control Register (MTMCR) .........................................................................................149 6.4 Interrupts ............................................................................................................................................153 6.5 An Explanation of Operations and Setting Procedure Examples .......................................................154 6.5.1 Main Timer Operation ....................................................................................................................154 6.5.2 Transition to Stop Mode ................................................................................................................156 CHAPTER 7 Sub Timer ..................................................................................................157 7.1 Overview .............................................................................................................................................158 7.2 Configuration ......................................................................................................................................159 7.3 Registers .............................................................................................................................................160 7.3.1 Sub Timer Control Register (STMCR) ...........................................................................................161 7.4 Interrupts ............................................................................................................................................165 7.5 An Explanation of Operations and Setting Procedure Examples .......................................................166 7.5.1 Sub timer operation .......................................................................................................................166 7.5.2 Transition to Stop Mode, and Watch Mode ...................................................................................168 CHAPTER 8 Low-power Dissipation Mode ..................................................................169 8.1 Overview .............................................................................................................................................170 8.2 Configuration ......................................................................................................................................171 8.3 Registers .............................................................................................................................................173 8.3.1 Standby Mode Control Register (STBCR) .....................................................................................174 8.3.2 Sleep Rate Configuration Register (SLPRR) .................................................................................177 8.4 An Explanation of Operations and Setting Procedure Examples .......................................................179 8.4.1 Operation When Clock Control Is Set ............................................................................................180 8.4.2 Operation in Doze Mode ................................................................................................................181 8.4.3 Operation in Sleep Mode ...............................................................................................................182 8.4.4 Operation in Main Timer Mode ......................................................................................................184 8.4.5 Operation in Watch Mode ..............................................................................................................186 8.4.6 Operation in Stop Mode .................................................................................................................188 8.5 Notes on Use ......................................................................................................................................191 CHAPTER 9 Reset ..........................................................................................................193 9.1 Overview .............................................................................................................................................194 9.2 Configuration ......................................................................................................................................195 9.3 Pins .....................................................................................................................................................197 9.4 Registers .............................................................................................................................................198 9.4.1 Reset Result Register (RSTRR) ....................................................................................................199 9.4.2 Reset Control Register (RSTCR) ..................................................................................................201 9.5 Explanation of Operations ..................................................................................................................203 9.5.1 Reset Types ..................................................................................................................................203 9.5.2 Reset Resource .............................................................................................................................204 9.5.3 Operation of Reset ........................................................................................................................206 9.5.4 Irregular reset ................................................................................................................................211 9.6 Operating State and Transition ...........................................................................................................212 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED ix MB91625 Series CHAPTER 10 Interrupt Controller .................................................................................. 217 10.1 Overview ............................................................................................................................................ 218 10.2 Configuration ..................................................................................................................................... 219 10.3 Registers ............................................................................................................................................ 220 10.3.1 Interrupt Control Register (ICR00 to ICR47) ................................................................................. 221 10.4 An Explanation of Operations and Setting Procedure Examples ....................................................... 223 10.4.1 Explanation of Operations of Interrupt Controller ......................................................................... 223 10.5 Notes on Use ..................................................................................................................................... 225 CHAPTER 11 Interrupt Request Batch-Read Function ................................................ 227 11.1 Overview ............................................................................................................................................ 228 11.2 Configuration ..................................................................................................................................... 229 11.3 Registers ............................................................................................................................................ 230 11.3.1 Interrupt Request Batch-Read Register 0 Upper (IRPR0H) ......................................................... 231 11.3.2 Interrupt Request Batch-Read Register 1 Upper/Lower (IRPR1H/ IRPR1L) ................................ 233 11.3.3 Interrupt Request Batch-Read Register 2 Upper (IRPR2H) ......................................................... 236 11.3.4 Interrupt Request Batch-Read Register 2 Lower (IRPR2L) .......................................................... 237 11.3.5 Interrupt Request Batch-Read Register 3 Upper (IRPR3H) ......................................................... 238 11.3.6 Interrupt Request Batch-Read Register 3 Lower (IRPR3L) .......................................................... 239 11.3.7 Interrupt Request Batch-Read Register 4 Upper (IRPR4H) ......................................................... 240 11.3.8 Interrupt Request Batch-Read Register 4 Lower (IRPR4L) .......................................................... 241 11.3.9 Interrupt Request Batch-Read Register 5 Upper (IRPR5H) ......................................................... 243 11.3.10 Interrupt Request Batch-Read Register 5 Lower (IRPR5L) .......................................................... 245 11.3.11 Interrupt Request Batch-Read Register 6 Upper (IRPR6H) ......................................................... 247 11.3.12 Interrupt Request Batch-Read Register 6 Lower (IRPR6L) .......................................................... 249 11.3.13 Interrupt Request Batch-Read Register 7 Upper (IRPR7H) ......................................................... 251 11.3.14 Interrupt Request Batch-Read Register 7 Lower (IRPR7L) .......................................................... 253 11.4 Notes on Use ..................................................................................................................................... 254 CHAPTER 12 Delay Interrupt .......................................................................................... 255 12.1 Overview ............................................................................................................................................ 256 12.2 Configuration ..................................................................................................................................... 257 12.3 Registers ............................................................................................................................................ 258 12.3.1 Delayed Interrupt Control Register (DICR) ................................................................................... 259 12.4 An Explanation of Operations and Setting Procedure Examples ....................................................... 260 12.4.1 Explanation of Delay Interrupt Operations .................................................................................... 260 12.5 Notes on Use ..................................................................................................................................... 261 CHAPTER 13 I/O Ports .................................................................................................... 263 13.1 Overview ............................................................................................................................................ 264 13.2 Configuration ..................................................................................................................................... 266 13.3 Pins .................................................................................................................................................... 271 13.4 Registers ............................................................................................................................................ 272 13.4.1 Port Data Direction Registers (DDR0 to DDRK) ........................................................................... 274 13.4.2 Port Function Registers (PFR0 to PFRA) ..................................................................................... 277 13.4.3 Extended Port Function Registers (EPFR0 to EPFR34) .............................................................. 279 13.4.4 Port Data Registers (PDR0 to PDRK) .......................................................................................... 294 13.4.5 Pull-up Resistor Control Registers (PCR0 to PCRK) .................................................................... 295 13.4.6 A/D Channel Enable Register (ADCHE) ....................................................................................... 296 x FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series 13.5 Notes on Use ......................................................................................................................................298 CHAPTER 14 External Interrupt Controllers ..................................................................301 14.1 Overview .............................................................................................................................................302 14.2 Configuration ......................................................................................................................................303 14.3 Pins .....................................................................................................................................................305 14.4 Registers .............................................................................................................................................306 14.4.1 External Interrupt Request Level Registers (ELVR0 to ELVR3) ....................................................307 14.4.2 External Interrupt Request Registers (EIRR0 to EIRR3) ...............................................................310 14.4.3 Enable Interrupt Request Registers (ENIR0 to ENIR3) .................................................................312 14.5 Explanation of Operations and Setting Procedure Examples .............................................................314 14.5.1 Operations of the External Interrupt Controllers ............................................................................314 14.5.2 Return from Standby Mode ...........................................................................................................317 14.5.3 Return from Sleep Mode ...............................................................................................................319 CHAPTER 15 Watchdog Timer ........................................................................................321 15.1 Overview .............................................................................................................................................322 15.2 Configuration ......................................................................................................................................323 15.3 Registers .............................................................................................................................................325 15.3.1 Watchdog Timer Control Register 0 (WDTCR0) ...........................................................................326 15.3.2 Watchdog Timer Clear Pattern Register 0 (WDTCPR0) ...............................................................329 15.4 Explanation of Operations and Setting Procedure Examples .............................................................330 15.4.1 Operations of the Watchdog Timer ................................................................................................330 CHAPTER 16 Watch Counter ..........................................................................................333 16.1 Overview .............................................................................................................................................334 16.2 Configuration ......................................................................................................................................335 16.3 Registers .............................................................................................................................................337 16.3.1 Watch Counter Reload Register (WCRL) ......................................................................................338 16.3.2 Watch Counter Control Register (WCCR) .....................................................................................339 16.3.3 Watch Counter Read Register (WCRD) ........................................................................................342 16.4 Interrupts ............................................................................................................................................343 16.5 Explanation of Operations and Setting Procedure Examples .............................................................344 16.5.1 Operations of the Watch Counter ..................................................................................................344 16.6 Notes on Use ......................................................................................................................................346 CHAPTER 17 32-bit Free-Run Timer ...............................................................................347 17.1 Overview .............................................................................................................................................348 17.2 Configuration ......................................................................................................................................349 17.3 Pins .....................................................................................................................................................353 17.4 Registers .............................................................................................................................................354 17.4.1 Free-Run Timer Select Register (FRTSEL) ...................................................................................355 17.4.2 Compare Clear Register (CPCLR0, CPCLR1) ..............................................................................356 17.4.3 Timer Data Register (TCDT0, TCDT1) ..........................................................................................357 17.4.4 Timer Status Control Register Upper/Lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1) ..................358 17.5 Interrupts ............................................................................................................................................362 17.6 An Explanation of Operations and Setting Procedure Examples .......................................................363 17.6.1 Operation When an Internal Clock (Peripheral Clock) Is Selected ................................................364 17.6.2 Operation When an External Clock Is Selected ............................................................................365 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED xi MB91625 Series CHAPTER 18 32-bit Input Capture ................................................................................. 367 18.1 Overview ............................................................................................................................................ 368 18.2 Configuration ..................................................................................................................................... 369 18.3 Pins .................................................................................................................................................... 371 18.4 Registers ............................................................................................................................................ 372 18.4.1 Input Capture Status Control Registers (ICS01 to ICS67) ............................................................ 373 18.4.2 Input Capture Data Register (IPCP0 to IPCP7) ............................................................................ 377 18.5 Interrupts ............................................................................................................................................ 378 18.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 379 18.6.1 Explanation of 32-bit Input Capture Operation ............................................................................. 379 CHAPTER 19 32-bit Output Compare ............................................................................ 383 19.1 Overview ............................................................................................................................................ 384 19.2 Configuration ..................................................................................................................................... 385 19.3 Pins .................................................................................................................................................... 387 19.4 Registers ............................................................................................................................................ 388 19.4.1 Output Compare Register (OCCP0 to OCCP7) ............................................................................ 389 19.4.2 Compare Control Register Upper (OCSH1, OCSH3, OCSH5, OCSH7) ...................................... 390 19.4.3 Compare Control Register Lower (OCSL0, OCSL2, OCSL4, OCSL6) ......................................... 394 19.5 Interrupts ............................................................................................................................................ 397 19.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 398 19.6.1 When the 2 Channels Are Used Independently of Each Other .................................................... 398 19.6.2 When the 2 Channels Are Used as a Pair .................................................................................... 400 CHAPTER 20 16-bit Reload Timer .................................................................................. 403 20.1 Overview ............................................................................................................................................ 404 20.2 Configuration ..................................................................................................................................... 405 20.3 Pins .................................................................................................................................................... 407 20.4 Registers ............................................................................................................................................ 408 20.4.1 Timer Control Status Register (TMCSR0 to TMCSR2) ................................................................ 409 20.4.2 16-bit Timer Reload Register A (TMRLRA0 to TMRLRA2) .......................................................... 415 20.4.3 16-bit Timer Register (TMR0 to TMR2) ........................................................................................ 416 20.5 Interrupts ............................................................................................................................................ 417 20.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 418 20.6.1 Operation in Interval Timer Mode ................................................................................................. 419 20.6.2 Operations in Event Counter Mode .............................................................................................. 432 20.6.3 Operation in Cascade Mode ......................................................................................................... 437 20.7 Notes on Use ..................................................................................................................................... 439 CHAPTER 21 Base Timer I/O Select Function .............................................................. 441 21.1 Overview ............................................................................................................................................ 442 21.2 Configuration ..................................................................................................................................... 443 21.3 Pins .................................................................................................................................................... 444 21.4 Registers ............................................................................................................................................ 446 21.4.1 Base Timer IO Select Register for Ch.0/1/2/3 (BTSEL0123) ........................................................ 447 21.4.2 Base Timer IO Select Register for Ch.4/5/6/7 (BTSEL4567) ........................................................ 450 21.4.3 Base Timer IO Select Register for Ch.8/9/A/B (BTSEL89AB) ...................................................... 453 21.4.4 Base Timer IO Select Register for Ch.C/D/E/F (BTSELCDEF) .................................................... 456 21.4.5 Base Timer Same Time Soft Start Register (BTSSSR) ................................................................ 459 xii FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series 21.5 I/O Mode .............................................................................................................................................464 21.5.1 I/O Mode 0 (16-bit Timer Standard Mode) .....................................................................................464 21.5.2 I/O Mode 1 (Timer Full Mode) .......................................................................................................466 21.5.3 I/O Mode 2 (External Trigger Shared Mode) .................................................................................468 21.5.4 I/O Mode 3 (Other Channel Trigger Shared Mode) .......................................................................470 21.5.5 Operations in I/O Mode 4 (Timer Activation/Stop Mode) ...............................................................472 21.5.6 Operations in I/O Mode 5 (Same Time Software Activation Mode) ...............................................475 21.5.7 Operations in I/O Mode 6 (Software Activation Timer Activation/Stop Mode) ...............................477 21.5.8 Operations in I/O Mode 7 (Timer Activation Mode) .......................................................................479 21.5.9 Operations in I/O Mode 8 (Other Channel Trigger Shared Timer Activation/Stop Mode) .............481 CHAPTER 22 Base Timer ................................................................................................483 22.1 Overview of the Base Timer ...............................................................................................................484 22.2 Block Diagrams of the Base Timer .....................................................................................................486 22.3 Base Timer's Registers .......................................................................................................................494 22.4 Operations of the Base Timer .............................................................................................................505 22.5 32-bit Mode Operations ......................................................................................................................507 22.6 Notes of Using the Base Timer ...........................................................................................................509 22.7 Base Timer Interrupts .........................................................................................................................511 22.8 Base Timer Description by Function Mode .........................................................................................512 22.8.1 PWM Function ...............................................................................................................................513 22.8.2 PPG Function ................................................................................................................................527 22.8.3 Reload Timer Function ..................................................................................................................542 22.8.4 PWC Function ...............................................................................................................................554 CHAPTER 23 Up/Down Counter .....................................................................................569 23.1 Overview .............................................................................................................................................570 23.2 Configuration ......................................................................................................................................572 23.3 Pins .....................................................................................................................................................574 23.4 Registers .............................................................................................................................................575 23.4.1 Reload Compare Register (RCR0 to RCR3) .................................................................................576 23.4.2 Up-Down Count Register (UDCR0 to UDCR3) .............................................................................578 23.4.3 Counter Control Register (CCR0 to CCR3) ...................................................................................579 23.4.4 Counter Status Register (CSR0 to CSR3) .....................................................................................584 23.5 Interrupt ..............................................................................................................................................587 23.6 An Explanation of Operations and Setting Procedure Examples .......................................................589 23.6.1 Operation in Timer Mode ...............................................................................................................593 23.6.2 Operations in Up/Down Count Mode .............................................................................................595 23.6.3 Operations in Phase Difference Count Mode (Multiplied by 2) ......................................................598 23.6.4 Operations in Phase Difference Count Mode (Multiplied by 4) ......................................................600 CHAPTER 24 10-Bit A/D Converter .................................................................................603 24.1 Overview .............................................................................................................................................604 24.2 Configuration ......................................................................................................................................605 24.3 Pins .....................................................................................................................................................607 24.4 Registers .............................................................................................................................................609 24.4.1 A/DC Control Registers (ADCR0) ..................................................................................................610 24.4.2 A/DC Status Registers (ADSR0) ...................................................................................................613 24.4.3 Scan Conversion Control Registers (SCCR0) ...............................................................................617 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED xiii MB91625 Series 24.4.4 Scan Conversion FIFO Number Setting Register (SFNS0) .......................................................... 621 24.4.5 Scan Conversion FIFO Data Registers (SCFD0) ......................................................................... 623 24.4.6 Scan Conversion Input Select Registers (SCIS10, SCIS00) ........................................................ 626 24.4.7 Priority Conversion Control Registers (PCCR0) ........................................................................... 627 24.4.8 Priority Conversion FIFO Number Setting Registers (PFNS0) ..................................................... 631 24.4.9 Priority Conversion FIFO Data Registers (PCFD0) ...................................................................... 633 24.4.10 Priority Conversion Input Select Registers (PCIS0) ..................................................................... 637 24.4.11 A/D Comparison Data Setting Registers (CMPD0) ...................................................................... 640 24.4.12 A/D Comparison Control Registers (CMPCR0) ............................................................................ 641 24.4.13 Sampling Time Setting Registers (ADST00, ADST10) ................................................................. 645 24.4.14 Sampling Time Select Registers (ADSS10, ADSS00) .................................................................. 648 24.4.15 Compare Time Setting Registers (ADCT0) .................................................................................. 649 24.5 Interrupts ............................................................................................................................................ 651 24.6 Explanation of Operations and Setting Procedure Examples ............................................................ 653 24.6.1 Operation of A/D Scan Conversion ............................................................................................... 663 24.6.2 Operation of A/D Priority Conversion ............................................................................................ 666 24.6.3 FIFO Operations ........................................................................................................................... 669 24.6.4 Activating the DMA Controller (DMAC) ......................................................................................... 675 CHAPTER 25 8-bit D/A Converter ................................................................................... 677 25.1 Overview ............................................................................................................................................ 678 25.2 Configuration ..................................................................................................................................... 679 25.3 Pins .................................................................................................................................................... 681 25.4 Registers ............................................................................................................................................ 682 25.4.1 D/A Data Registers (DADR0, DADR1) ......................................................................................... 683 25.4.2 D/A Control Registers (DACR0, DACR1) ..................................................................................... 684 25.5 Explanation of Operations and Setting Procedure Examples ............................................................ 685 25.5.1 Operations of the 8-bit D/A Converter .......................................................................................... 685 CHAPTER 26 Multi-function Serial Interface ................................................................. 687 26.1 Characteristics of Multi-function Serial Interface ................................................................................ 688 26.2 UART (Asynchronous Serial Interface) .............................................................................................. 689 26.3 Overview of UART (Asynchronous Serial Interface) .......................................................................... 690 26.4 Registers of UART (Asynchronous Serial Interface) .......................................................................... 692 26.4.1 Serial Control Register (SCR) ....................................................................................................... 697 26.4.2 Serial Mode Register (SMR) ......................................................................................................... 699 26.4.3 Serial Status Register (SSR) ........................................................................................................ 702 26.4.4 Extended Serial Control Register (ESCR) .................................................................................... 705 26.4.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................ 707 26.4.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ................................................................... 710 26.4.7 FIFO Control Register 1 (FCR1) ................................................................................................... 712 26.4.8 FIFO Control Register 0 (FCR0) ................................................................................................... 714 26.4.9 FIFO Byte Register (FBYTE1/FBYTE2) ....................................................................................... 717 26.5 Interrupts of UART ............................................................................................................................. 719 26.5.1 Occurrence of Reception Interrupts and Flag Set Timing ............................................................. 721 26.5.2 Occurrence of Interrupts when Reception FIFO is Used and Flag Set Timing ............................. 722 26.5.3 Occurrence of Transmission Interrupts and Flag Set Timing ....................................................... 723 26.5.4 Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing ........................ 724 26.6 Operation of UART ............................................................................................................................ 725 xiv FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series 26.7 Dedicated Baud Rate Generator ........................................................................................................730 26.7.1 Setting Baud Rate .........................................................................................................................731 26.8 Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) ...............735 26.9 Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode) ..737 26.10 Notes on UART Mode .........................................................................................................................741 26.11 CSIO (Clock Synchronous Serial Interface) .......................................................................................742 26.12 Overview of CSIO (Clock Synchronous Serial Interface) ...................................................................743 26.13 Registers of CSIO (Clock Synchronous Serial Interface) ...................................................................744 26.13.1 Serial Control Register (SCR) .......................................................................................................750 26.13.2 Serial Mode Register (SMR) ..........................................................................................................753 26.13.3 Serial Status Register (SSR) .........................................................................................................756 26.13.4 Extended Serial Control Register (ESCR) .....................................................................................758 26.13.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................760 26.13.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ....................................................................763 26.13.7 FIFO Control Register 1 (FCR1) ....................................................................................................764 26.13.8 FIFO Control Register 0 (FCR0) ....................................................................................................766 26.13.9 FIFO Byte Register (FBYTE1/FBYTE2) ........................................................................................769 26.13.10Serial Mode Select Registers (SSEL0123, SSEL4567) ...............................................................771 26.13.11Received Data Mirror Registers/Transmitted Data Mirror Registers (RDRM/TDRM) ..................773 26.14 Interrupts of CSIO (Clock Synchronous Serial Interface) ...................................................................774 26.14.1 Occurrence of Reception Interrupts and Flag Set Timing .............................................................776 26.14.2 Occurrence of Interrupts when Reception FIFO is Used and Flag Set Timing ..............................777 26.14.3 Occurrence of Transmission Interrupts and Flag Set Timing ........................................................779 26.14.4 Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing ........................780 26.15 Operation of CSIO (Clock Synchronous Serial Interface) ...................................................................781 26.16 Dedicated Baud Rate Generator ........................................................................................................800 26.16.1 Setting Baud Rate .........................................................................................................................801 26.17 Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface) ........................804 26.18 Notes on CSIO Mode ..........................................................................................................................806 26.19 I2C Interface .......................................................................................................................................807 26.20 Overview of I2C Interface ....................................................................................................................808 26.21 Registers of I2C Interface ...................................................................................................................809 26.21.1 I2C Bus Control Register (IBCR) ...................................................................................................815 26.21.2 Serial Mode Register (SMR) ..........................................................................................................820 26.21.3 I2C Bus Status Register (IBSR) .....................................................................................................822 26.21.4 Serial Status Register (SSR) .........................................................................................................826 26.21.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................828 26.21.6 7-bit Slave Address Mask Register (ISMK) ...................................................................................830 26.21.7 7-bit Slave Address Register (ISBA) .............................................................................................831 26.21.8 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ....................................................................832 26.21.9 FIFO Control Register 1 (FCR1) ....................................................................................................833 26.21.10FIFO Control Register 0 (FCR0) ..................................................................................................835 26.21.11FIFO Byte Register (FBYTE1/FBYTE2) .......................................................................................839 26.22 Interrupts of I2C Interface ...................................................................................................................841 26.22.1 Operation of I2C Interface Communication ....................................................................................843 26.22.2 Master Mode ..................................................................................................................................844 26.22.3 Slave Mode ....................................................................................................................................861 26.22.4 Bus Error .......................................................................................................................................865 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED xv MB91625 Series 26.23 Dedicated Baud Rate Generator ....................................................................................................... 866 26.23.1 Example of I2C Flowcharts ........................................................................................................... 868 26.24 Notes on I2C Mode ............................................................................................................................ 880 CHAPTER 27 DMA Controller (DMAC) ........................................................................... 883 27.1 Overview ............................................................................................................................................ 884 27.2 Configuration ..................................................................................................................................... 887 27.3 Registers ............................................................................................................................................ 889 27.3.1 DMA Control Register (DMACR) .................................................................................................. 891 27.3.2 DMA Source Address Registers (DSAR0 to DSAR7) ................................................................... 894 27.3.3 DMA Destination Address Registers (DDAR0 to DDAR7) ............................................................ 895 27.3.4 DMA Transfer Count Registers (DTCR0 to DTCR7) .................................................................... 896 27.3.5 DMA Channel Control Registers (DCCR0 to DCCR7) ................................................................. 897 27.3.6 DMA Channel Status Registers (DCSR0 to DCSR7) ................................................................... 907 27.3.7 DMA-Halt by Interrupt Level Register (DILVR) ............................................................................. 910 27.4 Interrupts ............................................................................................................................................ 912 27.5 An Explanation of Operations and Setting Procedure Examples ....................................................... 913 27.5.1 Transfer Settings .......................................................................................................................... 913 27.5.2 Transfer Operations ...................................................................................................................... 916 27.5.3 Transfer Suspension ..................................................................................................................... 924 27.5.4 Operation at the End of Transfer .................................................................................................. 926 27.5.5 Post-transfer Operation ................................................................................................................ 927 27.5.6 DMA Transfer Halt ........................................................................................................................ 931 CHAPTER 28 Select Function for DMA Transfer Request Generation/Clear by a Peripheral Function .................................................................................. 933 28.1 Overview ............................................................................................................................................ 934 28.2 Configuration ..................................................................................................................................... 935 28.3 Registers ............................................................................................................................................ 937 28.3.1 IO-Data Request Registers (IORR0 to IORR7) ............................................................................ 939 28.3.2 Select Register 0 for DMA Transfer Request Clear by a Peripheral Function (ICSEL0) .............. 945 28.3.3 Select Register 1 for DMA Transfer Request Clear by a Peripheral Function (ICSEL1) .............. 947 28.3.4 Select Register 2 for DMA Transfer Request Clear by a Peripheral Function (ICSEL2) .............. 949 28.3.5 Select Register 3 for DMA Transfer Request Clear by a Peripheral Function (ICSEL3) .............. 951 28.3.6 Select Register 4 for DMA Transfer Request Clear by a Peripheral Function (ICSEL4) .............. 953 28.3.7 Select Register 5 for DMA Transfer Request Clear by a Peripheral Function (ICSEL5) .............. 955 28.3.8 Select Register 6 for DMA Transfer Request Clear by a Peripheral Function (ICSEL6) .............. 958 28.3.9 Select Register 7 for DMA Transfer Request Clear by a Peripheral Function (ICSEL7) .............. 960 28.3.10 Select Register 8 for DMA Transfer Request Clear by a Peripheral Function (ICSEL8) .............. 961 28.3.11 Select Register 9 for DMA Transfer Request Clear by a Peripheral Function (ICSEL9) .............. 963 28.3.12 Select Register 10 for DMA Transfer Request Clear by a Peripheral Function (ICSEL10) .......... 965 28.3.13 Select Register 11 for DMA Transfer Request Clear by a Peripheral Function (ICSEL11) .......... 969 28.3.14 Select Register 12 for DMA Transfer Request Clear by a Peripheral Function (ICSEL12) .......... 972 28.3.15 Select Register 13 for DMA Transfer Request Clear by a Peripheral Function (ICSEL13) .......... 975 28.3.16 Select Register 14 for DMA Transfer Request Clear by a Peripheral Function (ICSEL14) .......... 978 28.4 An Explanation of Operations and Setting Procedure Examples ....................................................... 980 28.4.1 Operations upon a DMA Transfer ................................................................................................. 980 xvi FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 29 Control of Built-in Program Memory .......................................................983 29.1 Overview of Built-in Program Memory Controller ...............................................................................984 29.2 Register for Built-in Program Memory Controller ................................................................................985 29.2.1 FLASH Control Register (FCTLR) .................................................................................................986 CHAPTER 30 Flash Memory ............................................................................................989 30.1 Overview of Flash Memory .................................................................................................................990 30.2 Flash Memory Configuration ...............................................................................................................991 30.3 Flash Memory Registers .....................................................................................................................994 30.3.1 FLASH Status Register (FSTR) .....................................................................................................995 30.3.2 FLASH Control Register (FCTLR) .................................................................................................996 30.4 Flash Memory Access Mode ..............................................................................................................997 30.5 Automatic Algorithm ............................................................................................................................998 30.5.1 Command Sequence .....................................................................................................................998 30.5.2 Execution State of Automatic Algorithm ......................................................................................1001 30.6 Explanation of Flash Memory Operation ..........................................................................................1006 30.6.1 Reset Operation ..........................................................................................................................1006 30.6.2 Data Write Operation ...................................................................................................................1007 30.6.3 Chip Erase ...................................................................................................................................1010 30.6.4 Sector Erase ................................................................................................................................1010 30.6.5 Sector Erase Suspending ............................................................................................................1012 30.6.6 Sector Erase Restarting ..............................................................................................................1014 30.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems .............................................1015 30.8 Notes on Using Flash Memory .........................................................................................................1018 CHAPTER 31 Wild Register ...........................................................................................1019 31.1 Overview of Wild Register ................................................................................................................1020 31.2 Configuration of Wild Register ..........................................................................................................1021 31.3 Registers of Wild Register ................................................................................................................1022 31.3.1 Wild Register Address Register (WRAR00 to WRAR15) ............................................................1024 31.3.2 Wild Register Data Register (WRDR00 to WRDR15) .................................................................1025 31.3.3 Wild Register Enable Register (WREN) ......................................................................................1026 31.4 Explanation of Operations and Setting Procedure Examples of the Wild Register ..........................1027 31.4.1 Wild Register Operation ..............................................................................................................1027 31.5 Notes on Using the Wild Register .....................................................................................................1028 CHAPTER 32 Serial Programming Connection ...........................................................1031 32.1 Fujitsu Microelectronics Serial Programmer .....................................................................................1032 32.1.1 Pins Used ....................................................................................................................................1036 CHAPTER 33 Handling the Device ...............................................................................1037 33.1 Notes on Handling the Device ..........................................................................................................1038 APPENDIXES ....................................................................................................................1045 APPENDIX A I/O Map .....................................................................................................1046 APPENDIX B List of Registers ......................................................................................1067 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED xvii MB91625 Series APPENDIX C Interrupt Vectors .................................................................................... 1092 APPENDIX D Pin State in Each CPU State .................................................................. 1096 APPENDIX E E.1 E.2 E.3 Lists of Instructions ............................................................................... 1106 Instruction List .................................................................................................................................. 1106 Instruction Tables ............................................................................................................................ 1110 List of Instructions That Can Be Specified for Delay Slots ............................................................... 1123 Index of Pins ..................................................................................................................... 1125 xviii FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E Main changes in this edition Page Changes (For details, refer to main body.) − Added MB91627, MB91F625 series. 1.3 MB91625 Series Block Diagram Corrected "Figure 1.3-1 MB91625 series block diagram". (Added "/Mask ROM" to "Internal program memory Flash memory".) 2.2 Pin Functions Corrected "I/O Circuit Type" of the pins number 20, 21 and 22. (P → H, P) 29 2.3 I/O Circuit Types Added the type H. 63 3.1 Memory Space ■ Memory map Corrected "Figure 3.1-1 Memory map". 120 4.4.3 Clock Stabilization Time Select Register (CSTBR) Corrected the table of [bit3 to bit0]. (Changed from "1" to "0" of "MOSW0" when "Main Clock 8 15 132 466 4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK) 21.5.2 I/O Mode 1 (Timer Full Mode) (000F 0000H → 000F 8000H) (MCLK) Oscillation Stabilization Wait Time" is "28 × Main clock (MCLK) period".) Corrected <Note>. (Added the line, "Source Clock (when PLL clock is selected)" to the table.) (Deleted "• It is prohibited to set ODS=00 and PMS=0000 (PLL multiply rate=1).".) Corrected "Table 21.5-4 External Pins Used". (Added "Even-numbered Channel".) Corrected "Table 21.5-6 Connections for I/O Mode 1". (TIN signal → ECK signal) (TOUT signal of ch.n+1 → Input signal from the TIOAn+1 pin) 467 (TIOBn+1 pin → Input signal from the TIOBn+1 pin) (ECK signal → TIN signal) 480 489, 491, 492 21.5.8 Operations in I/O Mode 7 (Timer Activation Mode) Corrected "Table 21.5-24 Connection for I/O Mode 7". (TIN/TGIN/ECK/DTRG signal → TIN/TGIN/ECK signal) 22.2 Block Diagrams of the Base Timer Corrected the position of "16-bit mode" and "32-bit mode" in the following figures. • "Figure 22.2-3 Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0)" • "Figure 22.2-4 Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0)" xix Page Changes (For details, refer to main body.) Corrected the table of the CKS2 to CKS0 (Count clock select bits). (CKS2 to CKS0="101" : (both edge event) → (rising edge event)) (CKS2 to CKS0="111" : (rising edge event) → (both edge event)) 514 22.8.1.1 Timer Control Register (BTxTMCR) for PWM Timer 528 22.8.2.1 Timer Control Register (BTxTMCR) for PPG Timer 543 22.8.3.1 Timer Control Register (BTxTMCR) for Reload Timer 559 22.8.4.1 Timer Control Register (BTxTMCR) for PWC Timer ■ Status Control Register (BTxSTC) CHAPTER 23 Up/Down Counter Corrected the table of the EDIR (Measurement end interrupt request bit). (0 : Clears interrupt request → 0 : Reads measurement result (BTxDTBF)) 23.1 Overview Corrected the description. (When counting reaches the previously set value, the value of the counter is cleared to continue counting. 569 to 602 571 582 ( compare function → compare clear function) ( reload compare function → reload compare clear function) → Clears the counter at the next up count timing when the specified value matches the counter value.) 23.4.3 Counter Control Register (CCR0 to CCR3) Corrected the description of [bit5]. 23.5 Interrupt Corrected < Notes>. (Deleted "• If an interrupt request is generated, the up/down counter is suspended until the interrupt request flag is cleared.".) 23.6 An Explanation of Operations and Setting Procedure Examples ● Reload/Compare clear function Corrected "Table 23.6-1 Setting the reload/compare clear function". 588 590 Corrected the terms in the entire chapter. xx Page Changes (For details, refer to main body.) 617 24.4.3 Scan Conversion Control Registers (SCCR0) Corrected < Note>. (Byte access to these registers must be performed independently, or half word access must be performed with a ... register (...). 621 24.4.4 Scan Conversion FIFO Number Setting Register (SFNS0) → Do not perform word access to these registers.) 627 24.4.7 Priority Conversion Control Registers (PCCR0) 631 24.4.8 Priority Conversion FIFO Number Setting Registers (PFNS0) 675 24.6.4 Activating the DMA Controller (DMAC) Corrected "Figure 24.6-7 DMA retransfer operation". Added <Note>. 676 707 Added the description. Corrected "Figure 24.6-6 DMA transfer operation (through scan conversion interrupt requests)". Added <Note>. 26.4.5 Reception Data Register / Transmission Data Register (RDR/TDR) Corrected the initial value of "Figure 26.4-5 Bit Structure of Reception Data Register (RDR)". (00000000B → -------0 00000000B) Corrected the initial value of "Figure 26.4-6 Bit Structure of Transmission Data 708 Register (TDR)". (11111111B → -------1 11111111B) 741 26.10 Notes on UART Mode Added a new section. Corrected the initial value of "Figure 26.13-5 Bit Structure of Reception Data Reg- 760 26.13.5 Reception Data Register / Transmission Data Register (RDR/TDR) ister (RDR)". (00000000B → -------0 00000000B) Corrected the initial value of "Figure 26.13-6 Bit Structure of Transmission Data 761 Register (TDR)". (11111111B → -------1 11111111B) 806 26.18 Notes on CSIO Mode Added a new section. 842 26.22 Interrupts of I2C Interface Corrected "Table 26.22-1 Interrupt Control Bits and Interrupt Sources of I2C Interface". 880, 881 26.24 Notes on I2C Mode Added a new section. 899, 900 27.3.5 DMA Channel Control Registers (DCCR0 to DCCR7) Added the explanation of < Notes> above [bit25]. Added < Notes> to the description of [bit25] and [bit24]. xxi Page Changes (For details, refer to main body.) 27.3.7 DMA-Halt by Interrupt Level Register (DILVR) Corrected the table of [bit4 to bit0]. 911 912 27.4 Interrupts Added the explanation of < Notes>. 918 27.5.2 Transfer Operations Added < Note> below "Table 27.5-2 Detect Condition of Transfer Requests and Transfer Request Source". 27.5.3 Transfer Suspension ■ Transfer Suspension/Restart 27.5.6 DMA Transfer Halt Corrected the description of "• Suspension due to a transfer stop request from transfer request source". (If a transfer error ... → If a reception error ...) 924 931 (Interrupt request of ... or higher → Higher level of interrupt request than ...) Corrected the description. (The DMA transfer restarts when the interrupt level reaches ... → The DMA transfer restarts when the interrupt request is cleared, and the interrupt level reaches ...) Corrected "Table 27.5-9 Interrupt Request Level where DMA Transfers are Halted.". (Interrupt request of ... or higher → Higher level of interrupt request than ... ) Corrected the table of [bit2 to bit0]. 956, 957 28.3.7 Select Register 5 for DMA Transfer Request Clear by a Peripheral Function (ICSEL5) Corrected the table of [bit2 to bit0]. 964 28.3.11 Select Register 9 for DMA Transfer Request Clear by a Peripheral Function (ICSEL9) 28.4.1 Operations upon a DMA Transfer ■ Operation Corrected the description. (Added the description of "4.".) (Deleted "An interrupt request flag of the peripheral functions is cleared with the DMA controller (DMAC).".) 29.2.1 FLASH Control Register (FCTLR) Corrected < Note>. (Added "bit other than FWC1 or FWC0".) CHAPTER 30 Flash Memory Added 256 KB flash memory. Corrected the terms in the entire chapter. (Automatic programming algorithm → Automatic algorithm) (Read/reset command → Reset command) (Read/reset operation → Reset operation) (the target sector → the flash memory area) (TOGG bit → Toggle bit flag DQ6 (TOGG)) (DPOLL bit → Data polling flag DQ7 (DPOLL)) (TLOV bit → Timing limit overrun flag DQ5 (TLOV)) 981 986 989 to 1018 xxii Page 990 Changes (For details, refer to main body.) 30.1 Overview of Flash Memory Corrected the summaries. (Data can also be written in units of half words. → Data can be written in units of half words.) ■ Overview Corrected the description of "- CPU programming mode". (read, written, or erased → written/erased) Corrected the description of "- CPU ROM mode". (... , does not support writing, erase, and activating the automatic programming algorithm. → ... , does not support activating the automatic algorithm for data writing/erase.) 30.3.1 FLASH Status Register (FSTR) Corrected "Figure 30.3-1 Bit configuration of FLASH status register (FSTR)". ("Initial value" of "FRDY" : 0 → 1) Added "• With a mask ROM product" to the description of [bit0]. Corrected the description of [bit0]. (flash write enable bit → flash operation status bit) (writing/erase → data writing/erase) 30.4 Flash Memory Access Mode Corrected the description of " CPU ROM mode (FWE=0)". (This mode, however, does not support writing or erasing commands or data, or activating the automatic programming algorithm. → This mode, however, does not support activation of the automatic algorithm for data writing/erase.) Corrected the description of " CPU programming mode (FWE=1)". (Data can be read, written, or erased in this mode. → Flash memory can be read, and data can be written/erased in this mode.) (... write or erase flash memory data. → ... write or erase data.) 30.5 Automatic Algorithm Corrected "Table 30.5-1 Command Sequence". (Deleted RA and RD.) (Read/Reset → Reset) (Writing → Data writing) Corrected the address of "Continuous mode". Corrected <Notes>. (... , CPU programming mode is canceled and CPU ROM mode is restored. → ..., the flash memory is reset to read mode.) 995 997 998 xxiii Page Changes (For details, refer to main body.) ■ Reset Command Corrected the description. (bus writing cycle → writing cycle) (... , flash memory is kept in read state ... → ... , flash memory is kept in read/reset state ...) (If a read/reset command is issued after execution of the automatic programming algorithm exceeds the timing limit, flash memory returns to the read/reset state. Read data from flash memory during a read cycle. 999 ■ Program (Data Write) Command ■ Chip Erase Command Corrected the description. (When the automatic erase algorithm is activated, the flash memory, before erasing the entire chip data, ... → When the automatic algorithm of chip erase is activated, the flash memory, before erasing the chip data, ...) ■ Sector Erase Command Corrected the description. (When 50μs have passed → When 50μs, at the shortest have passed) (... , the automatic programming algorithm is activated and then sector erase begins. → ... , sector erase begins.) (erase code (3030H) → sector erase code (3030H)) (If the next sector is not entered within the timeout period, the sector erase command may be disabled. → If the sector erase code is not entered within the timeout period, entering the code after the timeout period disables the sector erase command.) (When the automatic erase algorithm is activated, ... → When the automatic algorithm of sector erase is activated, ...) ■ Sector Erase Suspend Command Corrected <Note>. (... writing. → ... data writing.) 30.5.2 Execution State of Automatic Algorithm Corrected the summaries. (writing and erase → data writing/erase) 1000 1001 1002 → If execution of the automatic algorithm exceeds the timing limit, issue a reset command to make flash memory returns to the read/reset state.) Corrected the description. (■ Program (Write) Command → ■ Program (Data write) Command) (Sending the write command listed ... → Writing the data write command listed ...) (... automatic writing to flash memory begins. → ... data writing to flash memory begins.) (After execution of the automatic write algorithm command sequence, ... → After writing the command sequence of data writing, ...) Corrected <Notes>. (1 write command sequence → 1 command sequence of data writing) ■ Hardware Sequence Flag Corrected "Figure 30.5-1 Bit configuration of hardware sequence flag". (TOGG2 → Undefined) ● Correspondence between bits and flash memory states Corrected "Table 30.5-2 Correspondence between Flags and Flash Memory States". xxiv Page Changes (For details, refer to main body.) ● Explanation of bits 1003, 1004 Corrected the description of [bit7]. (data polling flag bit → data polling flag DQ7) (writing → data writing) Corrected the description of [bit6]. (toggle flag bit → toggle bit flag DQ6) (writing → data writing) (Deleted <Notes>.) Corrected the description of [bit5]. (timing limit overrun flag bit → timing limit overrun flag DQ5) (writing → data writing) 1004 Corrected the description of [bit3]. (sector erase timer flag bit → sector erase timer flag (DQ3)) (a timeout period of 50μs → a timeout period of 50μs, at the shortest) (sector erase wait → sector erase timeout) 1005 Corrected the explanation of [bit2]. (TOGG2 → Undefined bits) 30.6 Explanation of Flash Memory Operation ■ Overview Corrected the description. (Issuing a command 1 to 6 times consecutively for flash memory ... → Writing the data for 1 to 6 times consecutively, and issuing a command sequence for flash memory ...) (Read/Reset → Reset) (Writing → Data writing) 30.6.1 Reset Operation Corrected the description. (At power on, a data read command need not be issued. → At power on, a reset command need not be issued.) 1006 xxv Page Changes (For details, refer to main body.) 30.6.2 Data Write Operation 1007, 1008 Corrected the description. (write operation → data write operation) (write command → data write command) (If writing has not been finished, ... → If data writing has not been finished, ...) (After writing is finished, flash memory returns to read mode and accepts no write address. → After data writing is finished, flash memory returns to read/reset state.) Corrected "Figure 30.6-1 Data Write Procedure Example". (Figure 30.6-1 Write Procedure Example → Figure 30.6-1 Data Write Procedure Example) (Set the FWE bit (FWE = 1) of FLASH control register (FCTLR) to 1 to enable writing to flash memory → Set the FWE bit (FWE = 1) of FLASH control register (FCTLR) to 1 to enable writing to flash memory, and set to 16-bit after saving the values of FSZ1 and FSZ0 bits (FSZ1, FSZ0=01)) (Set the FWE bit (FWE = 0) of FLASH control register (FCTLR) to 0 to disable writing to flash memory → Set the FWE bit (FWE = 0) of FLASH control register (FCTLR) to 0 to disable writing to flash memory, and return the saved values of FSZ1 and FSZ0 bits) Corrected <Notes>. (write command → data write command) (... hardware sequence flag changes the value at the same time as ... → ... hardware sequence flag may change the value at almost the same time as ...) (Toggle operation stops simultaneously when the TOGG and TLOV bit of the hardware sequence flag change to "1". → The toggle bit flag DQ6 (TOGG) of the hardware sequence flag may stop toggle operation nearly simultaneously when the timing limit overrun flag DQ5 (TLOV) change to "1".) 1009 ■ Notes on Data Writing Corrected the description. (■ Notes on Writing → ■ Notes on Data Writing) (... the read/reset mode command. → ... the read/reset state command.) (write operation → data write operation) xxvi Page Changes (For details, refer to main body.) 30.6.3 Chip Erase Corrected the description. (... to write data to flash memory. → ... to start erase of all sectors in the flash memory.) (... to read/reset mode. → ... to read/reset state.) Corrected <Note>. (When the automatic erase algorithm is activated, the flash memory, before erasing the entire chip data, ... → When the automatic algorithm of chip erase is activated, the flash memory, before erasing the chip data, ...) 30.6.4 Sector Erase Corrected the description of "1.". (50 μs later (timeout period), the automatic programming algorithm is activated to start sector erase. → 50 μs later, at the shortest (timeout period), sector erase is started by the automatic algorithm.) (... , the sector erase command may be invalid. → ... , the erase code (3030H) is invalid.) Added the explanation to "2.". 1010 1011 Corrected "Figure 30.6-2 Sector Erase Procedure Example". Corrected the description. (... to read/reset mode. → ... to read/reset state.) Added the description. Corrected <Notes>. (... hardware sequence flag changes the value at the same time as ... → ... hardware sequence flag may change the value at almost the same time as ...) (... the hardware sequence flag stops toggle operation simultaneously ... → ... the hardware sequence flag may stop toggle operation nearly simultaneously ...) 1012 ( If a command other than the sector erase command and ... → If a command other than the sector erase code and ...) (... , the one or more sector erase commands that precede the issue of the command are disabled. → ... , the sector erase commands are disabled.) (When the automatic erase algorithm is activated, ... → When the automatic algorithm of sector erase is activated, ...) 1013 30.6.5 Sector Erase Suspending ■ State after sector erase is suspended Corrected <Note>. (Deleted "• bit2 (TOGG2 bit): If this bit is read continuously, "1" and "0" are read alternately (toggle operation).".) 30.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems Added a new section. 1015 to 1017 1026 31.3.3 Wild Register Enable Register (WREN) Corrected the initial value of "Figure 31.3-3 Bit Configuration of Wild Register Enable Register (WREN)". (X → 0) 1055 APPENDIX A I/O Map Corrected "Initial value after a reset". (FSTR:-------0 → -------1) The vertical lines marked in the left side of the page show the changes. xxvii xxviii CHAPTER 1 Overview This chapter explains the features and basic specifications of the MB91625 series. 1.1 1.2 1.3 1.4 CM71-10151-2E MB91625 Series Overview MB91625 Series Product Configuration MB91625 Series Block Diagram Package Dimensions FUJITSU MICROELECTRONICS LIMITED 1 CHAPTER 1 Overview 1.1 1.1 MB91625 Series MB91625 Series Overview The MB91625 series, a microcontroller that uses 32-bit RISC CPUs, has built-in peripheral control functions for embedded control which requires high-performance/high-speed CPU processing. This series is based on the FR80 family CPUs and is implemented in a single-chip. ■ FR80 family CPUs • 32-bit RISC, load/store architecture, 5-stage pipeline • 16 general-purpose 32-bit registers • 16-bit fixed-length instructions (basic instructions), 1 instruction per cycle • Instructions suitable for embedded applications - Instructions for memory-to-memory transfer, bit processing, barrel shift, etc. - High-level language support instructions - Bit search instruction Function entry/exit instructions and multi-load/store instructions for register contents 1 detection, 0 detection, and transition point detection - Branch instruction with delay slot(s) - Register interlock function Reduced overhead time in branch executions Efficient assembly language coding - Support for multipliers at the built-in function/instruction level Signed 32-bit multiplication - 5 cycles Signed 16-bit multiplication - 3 cycles - Interrupt (Save PC and PS) High-speed response at a minimum of 6 cycles, 16 levels of priority • 2 - Simultaneous access to a program and data enabled by Harvard architecture - The prefetch function for instructions using the 4-word instruction queue in the CPU Basic instruction compatibility with the FR family CPUs - Addition of the bit search instruction - No resource instruction and coprocessor instruction provided FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 1 Overview 1.1 MB91625 Series ■ Maximum operating frequency CPU 60 MHz Peripheral 40 MHz* *: The maximum operating frequency of the peripheral bus with the 60 MHz CPU is 30 MHz. ■ DMA controller (DMAC) • Number of channels: 8 • Address space: 32 bits (4 GB) • Transfer mode: Block transfer/Burst transfer/Demand transfer • Address update: Increment/Decrement/Fix (increment/decrement value fixed to 1, 2, or 4) • Transfer size: 8 bits, 16 bits, and 32 bits • Block size: 1 to 16 • Transfer count: 1 to 65,535 times • Transfer request: - Request by software - Interrupt request of a built-in peripheral function (a shared interrupt request or external interrupt request) • Reload function: Reloading of all channels can be specified. • Level of priority: Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...), or round robin • Interrupt request: Occurrence of a normal end interrupt request, abnormal end interrupt request, or transfer suspension interrupt request CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 3 CHAPTER 1 Overview 1.1 MB91625 Series ■ Multifunction serial interface • 4 channels with 16-byte FIFO, 8 channels without FIFO • Any of the following uses can be selected for each channel: (For ch.0, I2C is not available.) - UART - CSIO - I2C [Features of UART] - Full-duplex double buffer - Selection with or without parity supported - Built-in dedicated baud rate generator - External clock available as a serial clock - Various error detection functions available (parity errors, framing errors, and overrun errors) [Features of CSIO] - Full-duplex double buffer - Built-in dedicated baud rate generator - Overrun error detection function available [Features of I2C] - Standard mode (maximum: 100 kbps)/High-speed mode (maximum: 400 kbps) supported - 5V tolerance supported for some channels ■ Interrupts • Total of 32 external interrupts (5V tolerance supported for some pins) • Interrupt from an internal peripheral function • Programmable setting of interrupt levels (16 levels) • Return from stop mode or sleep mode supported ■ A/D converter 4 • 16 channels, 1 unit • 10-bit resolution • Successive comparison type Conversion time: Approximately 1.2 μs (PCLK=33 MHz) • Priority A/D conversion available (2 levels) • Conversion mode (one shot conversion mode, scanning conversion mode) • Activation trigger (software/external trigger/base timer) • FIFO for storing conversion data available (scanning conversion: 16 levels; priority conversion: 4 levels) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 1 Overview 1.1 MB91625 Series ■ D/A converter • Number of channels: 2 built-in channels • 8-bit resolution ■ Base timer • Number of channels: 16 built-in channels • Any of the following uses can be selected for each channel: - 16/32-bit reload timer - 16-bit PWM timer - 16/32-bit PWC timer - 16-bit PPG timer • 32-bit timer available by connecting 2 channels in cascade • Function for activating multiple channels simultaneously available • I/O select function available ■ 16-bit reload timer • Number of channels: 3 (including a channel for REALOS) • Interval timer function • Function for selecting count clock (Peripheral clock (PCLK) divided by a value ranging from 2 to 64) ■ Compare timer • 32-bit input capture: 8 built-in channels • 32-bit output compare: 8 built-in channels • 32-bit free-run timer: 2 built-in channels ■ Other interval timers • Up/Down counter: 4 built-in channels • Watch counter: 1 built-in channel • Watchdog timer: 1 built-in channel ■ Main timer • Number of channels: 1 • Count of the oscillation stabilization wait time of the main clock (MCLK). • Count of the oscillation stabilization wait time of the PLL clock (PLLCLK). • Interval timer when the oscillation of the main clock (MCLK) is stable. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 5 CHAPTER 1 Overview 1.1 MB91625 Series ■ Sub timer • Number of channels: 1 • Count of the oscillation stabilization wait time of the sub clock (SBCLK). • Interval timer when the oscillation of the sub clock (SBCLK) is stable. ■ Clock generation • Main clock (MCLK) oscillation • Sub clock (SBCLK) oscillation • PLL clock (PLLCLK) oscillation ■ Low-power dissipation mode • Stop mode • Watch mode • Sleep mode • Doze mode • Clock division function ■ Other features • I/O port • INIT pin available as a reset pin. • Watchdog timer reset and software reset available • Delay interrupt • Power supply: - 6 Single power supply (2.7 V to 3.6 V) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 1 Overview 1.2 MB91625 Series 1.2 MB91625 Series Product Configuration This section explains the products in the MB91625 series. Table 1.2-1 MB91625 series product configuration Product name Items Product type Built-in program memory size Common EVA MB91625 series MB91V650 MB91F627 MB91627 MB91F625 Evaluation product Flash memory product Mask ROM product Flash memory product ⎯ (Supports by emulation memory) 512K bytes (Flash) 512K bytes (ROM) 256K bytes (Flash) Built-in RAM capacity 128K bytes External bus interface Supported 48K bytes Not supported DMA controller (DMAC) 8 channels Base timer 16 channels Multifunction serial interface 32K bytes without FIFO: 8 channels (ch.0 to ch.7) with FIFO: 4 channels (ch.8 to ch.11) External interrupt 32 (Some pins support 5V tolerant) 10-bit A/D converter 32 channels, 2 units 16 channels, 1 unit 8-bit D/A converter 3 channels 2 channels 16-bit reload timer 3 channels 32-bit input capture 8 channels 32-bit output compare 8 channels 32-bit free-run timer 2 channels Up/down counter 4 channels Watch counter 1 channel I/O port 154 86 Main timer 1 channel Sub timer 1 channel Wild register Debug function Package CM71-10151-2E 16 channels ⎯ DSU4 ⎯ Type: LQFP-100 Package code: FPT-100P-M20 Lead pitch: 0.50 mm Pitch size: 14.0 mm × 14.0 mm FUJITSU MICROELECTRONICS LIMITED 7 CHAPTER 1 Overview 1.3 1.3 MB91625 Series MB91625 Series Block Diagram Figure 1.3-1 is the block diagrams of the MB91625 series. Figure 1.3-1 MB91625 series block diagram FR80 CPU Internal program memory Flash memory/ Mask ROM Step-down regulator Crossbar switch RAM On-chip bus DMAC, 8 channels Peripheral bus bridge Interrupt controller Delay interrupt 32-bit peripheral bus Watchdog timer 16-bit peripheral bus Clock control Watch counter External interrupt, 32 channels 16-bit reload timer, 3 channels Base timer, 16 channels 32-bit free-run timer, 2 channels Up/Down counter, 4 channels 32-bit input capture, 8 channels A/D converter, 16 channels (1 unit) 32-bit output compare, 8 channels D/A converter, 2 channels Multifunction serial interface, 8 channels Ports Ports Clock generation Multifunction serial interface with FIFO, 4 channels Ports 8 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 1 Overview 1.4 MB91625 Series 1.4 Package Dimensions The dimensions of the packages used for the MB91625 series are shown below. Figure 1.4-1 Package dimensions (FPT-100P-M20) 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 26 100 1 C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 25 0.20±0.05 (.008±.002) 0.08(.003) M 2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 9 CHAPTER 1 Overview 1.4 10 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series This chapter explains the pins and multiplexed pin settings of the MB91625 series. 2.1 2.2 2.3 2.4 CM71-10151-2E Pin Assignment Diagram Pin Functions I/O Circuit Types Setting Method for Pins FUJITSU MICROELECTRONICS LIMITED 11 CHAPTER 2 Pins of the MB91625 Series 2.1 2.1 MB91625 Series Pin Assignment Diagram 1 type of package are available for the MB91625 series. ■ LQFP-100 Figure 2.1-1 Pin assignment diagram in the LQFP-100 series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCC P26/TIOA11/SCK5/ZIN3/OUT2 P25/TIOB10/SIN5/BIN3/OUT1 P24/TIOA10/SOUT5/AIN3/OUT0 P23/TIOB9 P22/TIOA9/SCK4/ZIN2 P21/TIOB8/SIN4/BIN2 P20/TIOA8/SOUT4/AIN2 P17/TIOB7/INT7 P16/TIOA7/SCK3/ZIN1/INT6 P15/TIOB6/SIN3/BIN1/INT5 P14/TIOA6/SOUT3/AIN1/INT4 P13/TIOB5/INT3 P12/TIOA5/SCK2/ZIN0/INT2 P11/TIOB4/SIN2/BIN0/INT1 P10/TIOA4/SOUT2/AIN0/INT0 P07/TIOB3/IN7 P06/TIOA3/SCK1/IN6 P05/TIOB2/SIN1/IN5 P04/TIOA2/SOUT1/IN4 P03/TIOB1/IN3 P02/TIOA1/SCK0_1/IN2 P01/TIOB0/SIN0_1/IN1 P00/TIOA0/SOUT0_1/IN0 P67/INT23_2 (Top view) VSS C P27/TIOB11/OUT3 P30/TIOA12/SOUT6/INT8 P31/TIOB12/SIN6/INT9 P32/TIOA13/SCK6/INT10 P33/TIOB13/INT11 P34/TIOA14/SOUT7/OUT4/INT12 P35/TIOB14/SIN7/OUT5/INT13 P36/TIOA15/SCK7/OUT6/INT14 P37/TIOB15/OUT7/INT15 P40/SOUT8 P41/SIN8 P42/SCK8 P43 P44/SOUT9 P45/SIN9 P46/SCK9 P47 INIT MD0 MD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P66/ZIN3_1/FRCK0_1 P65/BIN3_1/ADTRG0_1 P64/AIN3_1 P63/FRCK1_1/INT22_2 P62/ZIN2_1 P61/BIN2_1 P60/AIN2_1 P57 P56/SCK11/ZIN1_1/FRCK0 P55/SIN11/BIN1_1/ADTRG0 P54/SOUT11/AIN1_1 P53/FRCK1/INT21_2 P52/SCK10/ZIN0_1 P51/SIN10/BIN0_1 P50/SOUT10/AIN0_1 PA7/TMI2_1/INT23_1 PA6/TMI1_1/INT22_1 PA5/TMI0_1/INT21_1 PA4/TMO2_1/INT20_1 PA3/TMO1_1/INT19_1 PA2/TMO0_1/INT18_1 PA1/INT17_1 PA0/INT16_1 P92 VCC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS P91/DA1 P90/DA0 AVSS AVRH AVCC P87/AN15/IN7_1/INT31 P86/AN14/IN6_1/INT30 P85/AN13/IN5_1/INT29 P84/AN12/IN4_1/INT28 P83/AN11/IN3_1/INT27 P82/AN10/IN2_1/INT26 P81/AN9/IN1_1/INT25 P80/AN8/IN0_1/INT24 P77/AN7/SCK0/TMI2/OUT7_1/INT23 P76/AN6/SIN0/TMI1/OUT6_1/INT22 P75/AN5/SOUT0/TMI0/OUT5_1/INT21 P74/AN4/TMO2/OUT4_1/INT20 P73/AN3/TMO1/OUT3_1/INT19 P72/AN2/TMO0/OUT2_1/INT18 P71/AN1/OUT1_1/INT17 P70/AN0/OUT0_1/INT16 PK2/ADTRG0_2 PK1/X0A PK0/X1A * 12 In a pin number that includes an underscore (_), such as XXX_1 and XXX_2, the number following the underscore represents a port number. Since these pins represent multiple pins that have the same function for one channel, use the extended port function register (EPFR) when selecting the pins to be used. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series 2.2 Pin Functions Table 2.2-1 lists the pin functions of the MB91625 series. In a pin that includes an underscore (_), such as XXX_1 and XXX_2, the number following the underscore represents a port number. For details of the port numbers, see "2.4 Setting Method for Pins". ■ Pin function list Table 2.2-1 Pin functions (1 / 14) Pin Name I/O Circuit Type 1 VSS - GND pin ⎯ ⎯ 2 C - Power stabilization capacity pin ⎯ ⎯ 3 P27 D* General-purpose I/O port ⎯ ❍ TIOB11 Base timer ch.11 TIOB pin ⎯ ❍ OUT3 32-bit output compare ch.3 output pin ⎯ ⎯ General-purpose I/O port ⎯ ❍ TIOA12 Base timer ch.12 TIOA pin ⎯ ⎯ SOUT6 (SDA6) Multifunction serial interface ch.6 output pin. This pin operates as SOUT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). ⎯ ❍ INT8 External interrupt request 8 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB12 Base timer ch.12 TIOB pin ⎯ ❍ SIN6 Multifunction serial interface ch.6 input pin ⎯ ❍ INT9 External interrupt request 9 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA13 Base timer ch.13 TIOA pin ⎯ ❍ SCK6 (SCL6) Multifunction serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). ⎯ ❍ INT10 External interrupt request 10 input pin ⎯ ❍ Pin Number LQFP100 4 5 6 P30 P31 P32 D* D* D* Function CMOS CMOS level level input hysteres is input * 5V tolerant pin CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 13 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (2 / 14) Pin Number Pin Name I/O Circuit Type P33 D* LQFP100 7 8 9 10 11 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TIOB13 Base timer ch.13 TIOB pin ⎯ ❍ INT11 External interrupt request 11 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA14 Base timer ch.14 TIOA pin ⎯ ⎯ SOUT7 (SDA7) Multifunction serial interface ch.7 output pin. This pin operates as SOUT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). ⎯ ❍ OUT4 32-bit output compare ch.4 output pin ⎯ ⎯ INT12 External interrupt request 12 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB14 Base timer ch.14 TIOB pin ⎯ ❍ SIN7 Multifunction serial interface ch.7 input pin ⎯ ❍ OUT5 32-bit output compare ch.5 output pin ⎯ ⎯ INT13 External interrupt request 13 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA15 Base timer ch.15 TIOA pin ⎯ ❍ SCK7 (SCL7) Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). ⎯ ❍ OUT6 32-bit output compare ch.6 output pin ⎯ ⎯ INT14 External interrupt request 14 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB15 Base timer ch.15 TIOB pin ⎯ ❍ OUT7 32-bit output compare ch.7 output pin ⎯ ⎯ INT15 External interrupt request 15 input pin ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E P34 P35 P36 P37 D* D* D* D* * 5V tolerant pin 14 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (3 / 14) Pin Number Pin Name I/O Circuit Type P40 D* LQFP100 12 SOUT8 (SDA8) 13 P41 D* SIN8 14 P42 D* SCK8 (SCL8) Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.8 output pin. This pin operates as SOUT8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA8 when it is used in an I2C (operation mode 4). ⎯ ❍ General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.8 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.8 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I2C (operation mode 4). ⎯ ❍ 15 P43 D* General-purpose I/O port ⎯ ❍ 16 P44 D* General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.9 output pin. This pin operates as SOUT9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA9 when it is used in an I2C (operation mode 4). ⎯ ❍ General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.9 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ Multifunction serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I2C (operation mode 4). ⎯ ❍ SOUT9 (SDA9) 17 P45 D* SIN9 18 P46 D* SCK9 (SCL9) 19 P47 D* General-purpose I/O port ⎯ ❍ 20 INIT H, P External reset input pin. A reset is valid when INIT = L. The I/O circuit type for the flash memory products is P. ⎯ ❍ 21 MD0 H, P Mode 0 pin. The I/O circuit type for the flash memory products is P. During normal operation, MD0 = L must be input. During serial programming to flash memory, MD0 = H must be input. ⎯ ❍ 22 MD1 H, P Mode 1 pin. Input must always be at the "L" level. The I/O circuit type for the flash memory products is P. ⎯ ❍ 23 X0 A Main clock (oscillation) input pin ⎯ ❍ * 5V tolerant pin CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 15 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (4 / 14) Pin Number Pin Name I/O Circuit Type 24 X1 A Main clock (oscillation) I/O pin ⎯ ⎯ 25 VSS - GND pin ⎯ ⎯ 26 PK0 I General-purpose I/O port ⎯ ❍ Sub clock (oscillation) I/O pin ⎯ ⎯ General-purpose I/O port ⎯ ❍ Sub clock (oscillation) input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ 10-bit A/D converter external trigger input pin (Port 2) ⎯ ❍ General-purpose I/O port ⎯ ❍ AN0 10-bit A/D converter ch.0 analog input pin ⎯ ⎯ OUT0_1 32-bit output compare ch.0 output pin (Port 1) ⎯ ⎯ INT16 External interrupt request 16 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN1 10-bit A/D converter ch.1 analog input pin ⎯ ⎯ OUT1_1 32-bit output compare ch.1 output pin (Port 1) ⎯ ⎯ INT17 External interrupt request 17 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN2 10-bit A/D converter ch.2 analog input pin ⎯ ⎯ TMO0 16-bit reload timer ch.0 output pin ⎯ ⎯ OUT2_1 32-bit output compare ch.2 output pin (Port 1) ⎯ ⎯ INT18 External interrupt request 18 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN3 10-bit A/D converter ch.3 analog input pin ⎯ ⎯ TMO1 16-bit reload timer ch.1 output pin ⎯ ⎯ OUT3_1 32-bit output compare ch.3 output pin (Port 1) ⎯ ⎯ INT19 External interrupt request 19 input pin ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E LQFP100 X1A 27 PK1 I X0A 28 PK2 C ADTRG0_ 2 29 30 31 32 16 P70 P71 P72 P73 E E E E Function CMOS CMOS level level input hysteres is input CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (5 / 14) Pin Number Pin Name I/O Circuit Type P74 E LQFP100 33 34 35 36 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ AN4 10-bit A/D converter ch.4 analog input pin ⎯ ⎯ TMO2 16-bit reload timer ch.2 output pin ⎯ ⎯ OUT4_1 32-bit output compare ch.4 output pin (Port 1) ⎯ ⎯ INT20 External interrupt request 20 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN5 10-bit A/D converter ch.5 analog input pin ⎯ ⎯ SOUT0 Multifunction serial interface ch.0 output pin. This pin operates as SOUT0 when it is used in a UART/CSIO (operation modes 0 to 2). ⎯ ⎯ TMI0 16-bit reload timer ch.0 input pin ⎯ ❍ OUT5_1 32-bit output compare ch.5 output pin (Port 1) ⎯ ⎯ INT21 External interrupt request 21 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN6 10-bit A/D converter ch.6 analog input pin ⎯ ⎯ SIN0 Multifunction serial interface ch.0 input pin ⎯ ❍ TMI1 16-bit reload timer ch.1 input pin ⎯ ❍ OUT6_1 32-bit output compare ch.6 output pin (Port 1) ⎯ ⎯ INT22 External interrupt request 22 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN7 10-bit A/D converter ch.7 analog input pin ⎯ ⎯ SCK0 Multifunction serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2). ⎯ ❍ TMI2 16-bit reload timer ch.2 input pin ⎯ ❍ OUT7_1 32-bit output compare ch.7 output pin (Port 1) ⎯ ⎯ INT23 External interrupt request 23 input pin ⎯ ❍ P75 P76 P77 CM71-10151-2E E E E FUJITSU MICROELECTRONICS LIMITED 17 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (6 / 14) Pin Number Pin Name I/O Circuit Type P80 E LQFP100 37 38 39 40 41 42 43 18 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ AN8 10-bit A/D converter ch.8 analog input pin ⎯ ⎯ IN0_1 32-bit input capture ch.0 input pin (Port 1) ⎯ ❍ INT24 External interrupt request 24 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN9 10-bit A/D converter ch.9 analog input pin ⎯ ⎯ IN1_1 32-bit input capture ch.1 input pin (Port 1) ⎯ ❍ INT25 External interrupt request 25 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN10 10-bit A/D converter ch.10 analog input pin ⎯ ⎯ IN2_1 32-bit input capture ch.2 input pin (Port 1) ⎯ ❍ INT26 External interrupt request 26 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN11 10-bit A/D converter ch.11 analog input pin ⎯ ⎯ IN3_1 32-bit input capture ch.3 input pin (Port 1) ⎯ ❍ INT27 External interrupt request 27 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN12 10-bit A/D converter ch.12 analog input pin ⎯ ⎯ IN4_1 32-bit input capture ch.4 input pin (Port 1) ⎯ ❍ INT28 External interrupt request 28 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN13 10-bit A/D converter ch.13 analog input pin ⎯ ⎯ IN5_1 32-bit input capture ch.5 input pin (Port 1) ⎯ ❍ INT29 External interrupt request 29 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ AN14 10-bit A/D converter ch.14 analog input pin ⎯ ⎯ IN6_1 32-bit input capture ch.6 input pin (Port 1) ⎯ ❍ INT30 External interrupt request 30 input pin ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E P81 P82 P83 P84 P85 P86 E E E E E E CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (7 / 14) Pin Number Pin Name I/O Circuit Type P87 E LQFP100 44 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ AN15 10-bit A/D converter ch.15 analog input pin ⎯ ⎯ IN7_1 32-bit input capture ch.7 input pin (Port 1) ⎯ ❍ INT31 External interrupt request 31 input pin ⎯ ❍ 45 AVCC - 10-bit A/D converter and 8-bit D/A converter analog power pin ⎯ ⎯ 46 AVRH - 10-bit A/D converter analog reference voltage input pin ⎯ ⎯ 47 AVSS - 10-bit A/D converter and 8-bit D/A converter GND pin ⎯ ⎯ 48 P90 F General-purpose I/O port ⎯ ❍ 8-bit D/A converter ch.0 analog output pin ⎯ ⎯ General-purpose I/O port ⎯ ❍ 8-bit D/A converter ch.1 analog output pin ⎯ ⎯ DA0 49 P91 F DA1 50 VSS - GND pin ⎯ ⎯ 51 VCC - Power pin ⎯ ⎯ 52 P92 C General-purpose I/O port ⎯ ❍ 53 PA0 C General-purpose I/O port ⎯ ❍ External interrupt request 16 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ External interrupt request 17 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ TMO0_1 16-bit reload timer ch.0 output pin (Port 1) ⎯ ⎯ INT18_1 External interrupt request 18 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ TMO1_1 16-bit reload timer ch.1 output pin (Port 1) ⎯ ⎯ INT19_1 External interrupt request 19 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ TMO2_1 16-bit reload timer ch.2 output pin (Port 1) ⎯ ⎯ INT20_1 External interrupt request 20 input pin (Port 1) ⎯ ❍ INT16_1 54 PA1 C INT17_1 55 56 57 PA2 PA3 PA4 CM71-10151-2E C C C FUJITSU MICROELECTRONICS LIMITED 19 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (8 / 14) Pin Number Pin Name I/O Circuit Type PA5 C LQFP100 58 59 60 61 62 63 64 20 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TMI0_1 16-bit reload timer ch.0 input pin (Port 1) ⎯ ❍ INT21_1 External interrupt request 21 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ TMI1_1 16-bit reload timer ch.1 input pin (Port 1) ⎯ ❍ INT22_1 External interrupt request 22 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ TMI2_1 16-bit reload timer ch.2 input pin (Port 1) ⎯ ❍ INT23_1 External interrupt request 23 input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ SOUT10 (SDA10) Multifunction serial interface ch.10 output pin. This pin operates as SOUT10 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SDA10 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN0_1 Up/Down counter ch.0 AIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ SIN10 Multifunction serial interface ch.10 input pin ⎯ ❍ BIN0_1 Up/Down counter ch.0 BIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ SCK10 (SCL10) Multifunction serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN0_1 Up/Down counter ch.0 ZIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ FRCK1 32-bit free-run timer ch.1 external clock input pin ⎯ ❍ INT21_2 External interrupt request 21 input pin (Port 2) ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E PA6 PA7 P50 P51 P52 P53 C C C C C C CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (9 / 14) Pin Number Pin Name I/O Circuit Type P54 C LQFP100 65 66 67 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ SOUT11 (SDA11) Multifunction serial interface ch.11 output pin. This pin operates as SOUT11 when it is used in a UART/ CSIO (operation modes 0 to 2) and as SDA11 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN1_1 Up/Down counter ch.1 AIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ SIN11 Multifunction serial interface ch.11 input pin ⎯ ❍ BIN1_1 Up/Down counter ch.1 BIN input pin (Port 1) ⎯ ❍ ADTRG0 10-bit A/D converter external trigger input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ SCK11 (SCL11) Multifunction serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN1_1 Up/Down counter ch.1 ZIN input pin (Port 1) ⎯ ❍ FRCK0 32-bit free-run timer ch.0 external clock input pin ⎯ ❍ P55 P56 C C 68 P57 C General-purpose I/O port ⎯ ❍ 69 P60 C General-purpose I/O port ⎯ ❍ Up/Down counter ch.2 AIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ Up/Down counter ch.2 BIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ Up/Down counter ch.2 ZIN input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ FRCK1_1 32-bit free-run timer ch.1 external clock input pin (Port 1) ⎯ ❍ INT22_2 External interrupt request 22 input pin (Port 2) ⎯ ❍ General-purpose I/O port ⎯ ❍ Up/Down counter ch.3 AIN input pin (Port 1) ⎯ ❍ AIN2_1 70 P61 C BIN2_1 71 P62 C ZIN2_1 72 73 P63 P64 AIN3_1 CM71-10151-2E C C FUJITSU MICROELECTRONICS LIMITED 21 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (10 / 14) Pin Number Pin Name I/O Circuit Type P65 C LQFP100 74 75 76 78 79 80 22 CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ BIN3_1 Up/Down counter ch.3 BIN input pin (Port 1) ⎯ ❍ ADTRG0_ 1 10-bit A/D converter external trigger input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ ZIN3_1 Up/Down counter ch.3 ZIN input pin (Port 1) ⎯ ❍ FRCK0_1 32-bit free-run timer ch.0 external clock input pin (Port 1) ⎯ ❍ General-purpose I/O port ⎯ ❍ External interrupt request 23 input pin (Port 2) ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA0 Base timer ch.0 TIOA pin ⎯ ⎯ SOUT0_1 Multifunction serial interface ch.0 output pin (Port 1). This pin operates as SOUT0_1 when it is used in a UART/ CSIO (operation modes 0 to 2). ⎯ ⎯ IN0 32-bit input capture ch.0 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB0 Base timer ch.0 TIOB pin ⎯ ❍ SIN0_1 Multifunction serial interface ch.0 input pin (Port 1) ⎯ ❍ IN1 32-bit input capture ch.1 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA1 Base timer ch.1 TIOA pin ⎯ ❍ SCK0_1 Multifunction serial interface ch.0 clock I/O pin (Port 1). This pin operates as SCK0_1 when it is used in a UART/CSIO (operation modes 0 to 2). ⎯ ❍ IN2 32-bit input capture ch.2 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB1 Base timer ch.1 TIOB pin ⎯ ❍ IN3 32-bit input capture ch.3 input pin ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E P66 P67 C C INT23_2 77 Function P00 P01 P02 P03 C C C C CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (11 / 14) Pin Number Pin Name I/O Circuit Type P04 C LQFP100 81 82 83 84 85 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TIOA2 Base timer ch.2 TIOA pin ⎯ ⎯ SOUT1 (SDA1) Multifunction serial interface ch.1 output pin. This pin operates as SOUT1 when the product is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). ⎯ ❍ IN4 32-bit input capture ch.4 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB2 Base timer ch.2 TIOB pin ⎯ ❍ SIN1 Multifunction serial interface ch.1 input pin ⎯ ❍ IN5 32-bit input capture ch.5 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA3 Base timer ch.3 TIOA pin ⎯ ❍ SCK1 (SCL1) Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). ⎯ ❍ IN6 32-bit input capture ch.6 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB3 Base timer ch.3 TIOB pin ⎯ ❍ IN7 32-bit input capture ch.7 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA4 Base timer ch.4 TIOA pin ⎯ ⎯ SOUT2 (SDA2) Multifunction serial interface ch.2 output pin. This pin operates as SOUT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN0 Up/Down counter ch.0 AIN input pin ⎯ ❍ INT0 External interrupt request 0 input pin ⎯ ❍ P05 P06 P07 P10 CM71-10151-2E C C C C FUJITSU MICROELECTRONICS LIMITED 23 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (12 / 14) Pin Number Pin Name I/O Circuit Type P11 C LQFP100 86 87 88 89 90 24 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TIOB4 Base timer ch.4 TIOB pin ⎯ ❍ SIN2 Multifunction serial interface ch.2 input pin ⎯ ❍ BIN0 Up/Down counter ch.0 BIN input pin ⎯ ❍ INT1 External interrupt request 1 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA5 Base timer ch.5 TIOA pin ⎯ ❍ SCK2 (SCL2) Multifunction serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN0 Up/Down counter ch.0 ZIN input pin ⎯ ❍ INT2 External interrupt request 2 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB5 Base timer ch.5 TIOB pin ⎯ ❍ INT3 External interrupt request 3 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA6 Base timer ch.6 TIOA pin ⎯ ⎯ SOUT3 (SDA3) Multifunction serial interface ch.3 output pin. This pin operates as SOUT3 when the product is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN1 Up/Down counter ch.1 AIN input pin ⎯ ❍ INT4 External interrupt request 4 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB6 Base timer ch.6 TIOB pin ⎯ ❍ SIN3 Multifunction serial interface ch.3 input pin ⎯ ❍ BIN1 Up/Down counter ch.1 BIN input pin ⎯ ❍ INT5 External interrupt request 5 input pin ⎯ ❍ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E P12 P13 P14 P15 C C C C CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (13 / 14) Pin Number Pin Name I/O Circuit Type P16 C LQFP100 91 92 93 94 95 96 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TIOA7 Base timer ch.7 TIOA pin ⎯ ❍ SCK3 (SCL3) Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN1 Up/Down counter ch.1 ZIN input pin ⎯ ❍ INT6 External interrupt request 6 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB7 Base timer ch.7 TIOB pin ⎯ ❍ INT7 External interrupt request 7 input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA8 Base timer ch.8 TIOA pin ⎯ ⎯ SOUT4 (SDA4) Multifunction serial interface ch.4 output pin. This pin operates as SOUT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN2 Up/Down counter ch.2 AIN input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOB8 Base timer ch.8 TIOB pin ⎯ ❍ SIN4 Multifunction serial interface ch.4 input pin ⎯ ❍ BIN2 Up/Down counter ch.2 BIN input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ TIOA9 Base timer ch.9 TIOA pin ⎯ ❍ SCK4 (SCL4) Multifunction serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN2 Up/Down counter ch.2 ZIN input pin ⎯ ❍ General-purpose I/O port ⎯ ❍ Base timer ch.9 TIOB pin ⎯ ❍ P17 P20 P21 P22 P23 TIOB9 C D* D* D* D* * 5V tolerant pin CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 25 CHAPTER 2 Pins of the MB91625 Series 2.2 MB91625 Series Table 2.2-1 Pin functions (14 / 14) Pin Number Pin Name I/O Circuit Type P24 D* LQFP100 97 98 99 100 Function CMOS CMOS level level input hysteres is input General-purpose I/O port ⎯ ❍ TIOA10 Base timer ch.10 TIOA pin ⎯ ⎯ SOUT5 (SDA5) Multifunction serial interface ch.5 output pin. This pin operates as SOUT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). ⎯ ❍ AIN3 Up/Down counter ch.3 AIN input pin ⎯ ❍ OUT0 32-bit output compare ch.0 output pin ⎯ ⎯ General-purpose I/O port ⎯ ❍ TIOB10 Base timer ch.10 TIOB pin ⎯ ❍ SIN5 Multifunction serial interface ch.5 input pin ⎯ ❍ BIN3 Up/Down counter ch.3 BIN input pin ⎯ ❍ OUT1 32-bit output compare ch.1 output pin ⎯ ⎯ General-purpose I/O port ⎯ ❍ TIOA11 Base timer ch.11 TIOA pin ⎯ ❍ SCK5 (SCL5) Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). ⎯ ❍ ZIN3 Up/Down counter ch.3 ZIN input pin ⎯ ❍ OUT2 32-bit output compare ch.2 output pin ⎯ ⎯ Power pin ⎯ ⎯ FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E P25 P26 VCC D* D* - * 5V tolerant pin 26 CHAPTER 2 Pins of the MB91625 Series 2.3 MB91625 Series 2.3 I/O Circuit Types Table 2.3-1 lists the I/O circuit types for the MB91625 series. ■ I/O circuit types Table 2.3-1 I/O circuit types (1 / 4) Type A Circuit X1 Remarks Clock input - Oscillation feedback resistor: Approximately 1MΩ - With standby mode control X0 Standby mode control C - CMOS level output - CMOS level hysteresis input - With pull-up resistor control - With standby mode control P-ch R P-ch Digital output N-ch Digital output * When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Pull-up resistor control Digital input Standby mode control CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 27 CHAPTER 2 Pins of the MB91625 Series 2.3 MB91625 Series Table 2.3-1 I/O circuit types (2 / 4) Type Circuit Remarks D P-ch N-ch Digital output - CMOS level output - CMOS level hysteresis input - 5V tolerant input - With standby mode control Digital output * When this pin is used as an I2C pin, the digital output P-ch transistor is always off. R Digital input Standby mode control E P-ch R P-ch Digital output N-ch Digital output - CMOS level output - CMOS level hysteresis input - With input control - Analog input - With pull-up resistor control - With standby mode control Pull-up resistor control Digital input Standby mode control Analog input Input control 28 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.3 MB91625 Series Table 2.3-1 I/O circuit types (3 / 4) Type Circuit Remarks F P-ch R P-ch Digital output N-ch Digital output - CMOS level output - CMOS level hysteresis input - With input control - Analog output - With pull-up resistor control - With standby mode control Pull-up resistor control Digital input Standby mode control Analog output Output control H - CMOS level hysteresis input P-ch N-ch R Digital input CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 29 CHAPTER 2 Pins of the MB91625 Series 2.3 MB91625 Series Table 2.3-1 I/O circuit types (4 / 4) Type Circuit Remarks I X1A P-ch Digital output N-ch Digital output - Oscillation feedback resistor: Approximately 10MΩ - CMOS level output - CMOS level hysteresis input - With standby mode control R Digital input Standby mode control Clock input Standby mode control Digital input R X0A Standby mode control P-ch Digital output N-ch Digital output P - Flash memory products only - CMOS level hysteresis input - With high-voltage control for flash memory tests N-ch N-ch Control pin N-ch N-ch N-ch 30 Mode input R FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series 2.4 Setting Method for Pins This section explains how to set registers for the multiplexed pins. More than one function has been assigned to the multiplexed pins. The tables below list the register setting values used to assign each of these functions to the pins, as categorized by peripheral function. The register names appearing in these tables are abbreviated names. - EPFR: Extended port function register - PFR: Port function register - DDR: Port data direction register For details of these registers, see "CHAPTER 13 I/O Ports". Other abbreviated register names are explained in the notes under each table. For details, see the respective chapters. ■ Ports Pin Name Register Name Bit Name Written Value P00 to P07 PFR0 PFR00 to PFR07 0 P10 to P17 PFR1 PFR10 to PFR17 0 P20 to P27 PFR2 PFR20 to PFR27 0 P30 to P37 PFR3 PFR30 to PFR37 0 P40 to P47 PFR4 PFR40 to PFR47 0 P50 to P57 PFR5 PFR50 to PFR57 0 P60 to P67 PFR6* PFR60 to PFR67 0 P70 to P77 PFR7 PFR70 to PFR77 0 P80 to P87 PFR8 PFR80 to PFR87 0 PA0 to PA7 PFRA* PFRA0 to PFRA7 0 *: The PFR register settings for P60, P62, P65, and PA5 are not required. <Note> For details of the settings of the port data direction register (DDR) see "CHAPTER 13 I/O Ports". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 31 CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ Clocks Pin Name Register Name X0A, X1A Bit Name Written Value DDRK DDRK1, DDRK0 00 EPFR19 XAE 1 CSELR SCEN 1 CSELR: Clock source select register ■ External interrupt controllers One of either of the INTx or INTx_1 pins can be selected for use with each channel. To use the INT pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the external interrupt controller (for details, see "CHAPTER 14 External Interrupt Controllers"). For details of the basic settings, see the following table. Channel 0 to 7 8 to 15 16 to 19 Port Number Port 0 Port 0 Port 0 Port 1 32 Pin Name INT0 to INT7 INT8 to INT15 INT16 to INT19 INT16_1 to INT19_1 Register Name Bit Name Written Value DDR1 DDR10 to DDR17 0 PFR1 PFR10 to PFR17 0 EPFR28 INT0E to INT7E 0 DDR3 DDR30 to DDR37 0 PFR3 PFR30 to PFR37 0 EPFR29 INT8E to INT15E 0 DDR7 DDR70 to DDR73 0 PFR7 PFR70 to PFR73 0 EPFR30 INT16E to INT19E 0 ADCHE ADE0 to ADE3 0 DDRA DDRA0 to DDRA3 0 PFRA PFRA0 to PFRA3 0 EPFR30 INT16E to INT19E 1 ADCHE ADE16 to ADE19 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 20 Port Number Port 0 Port 1 21 Port 0 Port 1 Port 2 22 Port 0 Port 1 Port 2 CM71-10151-2E Pin Name INT20 INT20_1 INT21 INT21_1 INT21_2 INT22 INT22_1 INT22_2 Register Name Bit Name Written Value DDR7 DDR74 0 PFR7 PFR74 0 EPFR31 INT20E 0 ADCHE ADE4 0 DDRA DDRA4 0 PFRA PFRA4 0 EPFR31 INT20E 1 ADCHE ADE20 0 DDR7 DDR75 0 PFR7 PFR75 0 EPFR31 INT21E1, INT21E0 00 ADCHE ADE5 0 DDRA DDRA5 0 EPFR31 INT21E1, INT21E0 01 ADCHE ADE21 0 DDR5 DDR53 0 PFR5 PFR53 0 EPFR31 INT21E1, INT21E0 10 DDR7 DDR76 0 PFR7 PFR76 0 EPFR31 INT22E1, INT22E0 00 ADCHE ADE6 0 DDRA DDRA6 0 PFRA PFRA6 0 EPFR31 INT22E1, INT22E0 01 ADCHE ADE22 0 DDR6 DDR63 0 PFR6 PFR63 0 EPFR31 INT22E1, INT22E0 10 FUJITSU MICROELECTRONICS LIMITED 33 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 23 Port Number Port 0 Port 1 Port 2 24 to 30 31 34 Port 0 Port 0 MB91625 Series Pin Name INT23 INT23_1 INT23_2 INT24 to INT30 INT31 Register Name Bit Name Written Value DDR7 DDR77 0 PFR7 PFR77 0 EPFR31 INT23E1, INT23E0 00 ADCHE ADE7 0 DDRA DDRA7 0 PFRA PFRA7 0 EPFR31 INT23E1, INT23E0 01 ADCHE ADE23 0 DDR6 DDR67 0 PFR6 PFR67 0 EPFR31 INT23E1, INT23E0 10 DDR8 DDR80 to DDR86 0 PFR8 PFR80 to PFR86 0 EPFR32 INT24E to INT30E 0 ADCHE ADE8 to ADE14 0 DDR8 DDR87 0 PFR8 PFR87 0 EPFR32 INT31E 0 ADCHE ADE15 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ 32-bit free-run timer The 32-bit free-run timer provides 2 FRCK pins for use with each channel. One of each of the pins can be selected for use with each channel. To use the FRCK pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the 32-bit free-run timer (for details, see "CHAPTER 17 32-bit Free-Run Timer"). For details of the basic settings, see the following table. Channel 0 Port Number Port 0 Port 1 1 Port 0 Port 1 CM71-10151-2E Pin Name FRCK0 FRCK0_1 FRCK1 FRCK1_1 Register Name Bit Name Written Value DDR5 DDR56 0 PFR5 PFR56 0 EPFR34 FRCK0E1, FRCK0E0 00 DDR6 DDR66 0 PFR6 PFR66 0 EPFR34 FRCK0E1, FRCK0E0 01 DDR5 DDR53 0 PFR5 PFR53 0 EPFR34 FRCK1E1, FRCK1E0 00 DDR6 DDR63 0 PFR6 PFR63 0 EPFR34 FRCK1E1, FRCK1E0 01 FUJITSU MICROELECTRONICS LIMITED 35 CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ 32-bit input capture The 32-bit input capture provides 2 IN pins for use with each channel. One of each of the pins can be selected for use with each channel. To use the IN pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the 32-bit input capture (for details, see "CHAPTER 18 32-bit Input Capture"). For details of the basic settings, see the following table. Channel 0 Port Number Port 0 Port 1 1 Port 0 Port 1 2 Port 0 Port 1 36 Pin Name IN0 IN0_1 IN1 IN1_1 IN2 IN2_1 Register Name Bit Name Written Value DDR0 DDR00 0 PFR0 PFR00 0 EPFR4 IN0E1, IN0E0 00 DDR8 DDR80 0 PFR8 PFR80 0 EPFR4 IN0E1, IN0E0 01 ADCHE ADE8 0 DDR0 DDR01 0 PFR0 PFR01 0 EPFR4 IN1E1, IN1E0 00 DDR8 DDR81 0 PFR8 PFR81 0 EPFR4 IN1E1, IN1E0 01 ADCHE ADE9 0 DDR0 DDR02 0 PFR0 PFR02 0 EPFR4 IN2E1, IN2E0 00 DDR8 DDR82 0 PFR8 PFR82 0 EPFR4 IN2E1, IN2E0 01 ADCHE ADE10 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 3 Port Number Port 0 Port 1 4 Port 0 Port 1 5 Port 0 Port 1 6 Port 0 Port 1 CM71-10151-2E Pin Name IN3 IN3_1 IN4 IN4_1 IN5 IN5_1 IN6 IN6_1 Register Name Bit Name Written Value DDR0 DDR03 0 PFR0 PFR03 0 EPFR4 IN3E1, IN3E0 00 DDR8 DDR83 0 PFR8 PFR83 0 EPFR4 IN3E1, IN3E0 01 ADCHE ADE11 0 DDR0 DDR04 0 PFR0 PFR04 0 EPFR5 IN4E1, IN4E0 00 DDR8 DDR84 0 PFR8 PFR84 0 EPFR5 IN4E1, IN4E0 01 ADCHE ADE12 0 DDR0 DDR05 0 PFR0 PFR05 0 EPFR5 IN5E1, IN5E0 00 DDR8 DDR85 0 PFR8 PFR85 0 EPFR5 IN5E1, IN5E0 01 ADCHE ADE13 0 DDR0 DDR06 0 PFR0 PFR06 0 EPFR5 IN6E1, IN6E0 00 DDR8 DDR86 0 PFR8 PFR86 0 EPFR5 IN6E1, IN6E0 01 ADCHE ADE14 0 FUJITSU MICROELECTRONICS LIMITED 37 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 7 Port Number Port 0 Port 1 38 MB91625 Series Pin Name IN7 IN7_1 Register Name Bit Name Written Value DDR0 DDR07 0 PFR0 PFR07 0 EPFR5 IN7E1, IN7E0 00 DDR8 DDR87 0 PFR8 PFR87 0 EPFR5 IN7E1, IN7E0 01 ADCHE ADE15 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ 32-bit output compare The 32-bit output compare provides 2 OUT pins for use with each channel. One of each of the pins can be selected for use with each channel. To use the OUT pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Disable the output of peripheral functions that share this pin with the EPFR register. (For details of the multiplexed pins, see the pin assignment diagram.) 3. Select a pin (port number) to be used on the EPFR register. 4. Set peripheral functions on the PFR register (PFR=1). For details of the basic settings, see the following table. Channel Port Number 0 Port 0 Port 1 1 Port 0 Port 1 2 Port 0 Port 1 CM71-10151-2E Pin Name OUT0 OUT0_1 OUT1 OUT1_1 OUT2 OUT2_1 Register Name Bit Name Written Value PFR2 PFR24 1 EPFR0 OUT0E2 to OUT0E0 001 EPFR25 TIOA10E1,TIOA10E0 Other than 01 * EPFR11 SOUT5E1,SOUT5E0 Other than 01 * PFR7 PFR70 1 EPFR0 OUT0E2 to OUT0E0 010 ADCHE ADE0 0 PFR2 PFR25 1 EPFR0 OUT1E2 to OUT1E0 001 PFR7 PFR71 1 EPFR0 OUT1E2 to OUT1E0 010 ADCHE ADE1 0 PFR2 PFR26 1 EPFR1 OUT2E2 to OUT2E0 001 EPFR25 TIOA11E1,TIOA11E0 Other than 01 * EPFR11 SCK5E1,SCK5E0 Other than 01 * PFR7 PFR72 1 EPFR1 OUT2E2 to OUT2E0 010 EPFR33 TMO0E1,TMO0E0 Other than 01 * ADCHE ADE2 0 FUJITSU MICROELECTRONICS LIMITED 39 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel Port Number 3 Port 0 Port 1 4 Port 0 Port 1 5 Port 0 Port 1 6 Port 0 Port 1 40 MB91625 Series Pin Name OUT3 OUT3_1 OUT4 OUT4_1 OUT5 OUT5_1 OUT6 OUT6_1 Register Name Bit Name Written Value PFR2 PFR27 1 EPFR1 OUT3E2 to OUT3E0 001 PFR7 PFR73 1 EPFR1 OUT3E2 to OUT3E0 010 EPFR33 TMO1E1,TMO1E0 Other than 01 * ADCHE ADE3 0 PFR3 PFR34 1 EPFR2 OUT4E2 to OUT4E0 001 EPFR27 TIOA14E1,TIOA14E0 Other than 01 * EPFR13 SOUT7E1,SOUT7E0 Other than 01 * PFR7 PFR74 1 EPFR2 OUT4E2 to OUT4E0 010 EPFR34 TMO2E1,TMO2E0 Other than 01 * ADCHE ADE4 0 PFR3 PFR35 1 EPFR2 OUT5E2 to OUT5E0 001 PFR7 PFR75 1 EPFR2 OUT5E2 to OUT5E0 010 EPFR6 SOUT0E2 to SOUT0E0 Other than 001 * ADCHE ADE5 0 PFR3 PFR36 1 EPFR3 OUT6E2 to OUT6E0 001 EPFR27 TIOA15E1,TIOA15E0 Other than 01 * EPFR13 SCK7E1,SCK7E0 Other than 01 * PFR7 PFR76 1 EPFR3 OUT6E2 to OUT6E0 010 ADCHE ADE6 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel Port Number 7 Port 0 Port 1 Pin Name OUT7 OUT7_1 Register Name Bit Name Written Value PFR3 PFR37 1 EPFR3 OUT7E2 to OUT7E0 001 PFR7 PFR77 1 EPFR3 OUT7E2 to OUT7E0 010 EPFR6 SCK0E2 to SCK0E0 Other than 001 * ADCHE ADE7 0 *: Do not write the setting prohibited value. For details, see "CHAPTER 13 I/O Ports". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 41 CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ 16-bit reload timer The 16-bit reload timer provides 2 of each of the TMI/TMO pins for use with each channel. One of each of the TMI/TMO pins can be selected for use with each channel. However, to use pins for the same channel, the pins must be assigned to the same port number. To use the TMI pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the 16-bit reload timer (For details, see "CHAPTER 20 16-bit Reload Timer"). To use the TMO pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Disable the output of peripheral functions that share this pin with the EPFR register. (For details of the multiplexed pins, see the pin assignment diagram.) 3. Select a pin (port number) to be used on the EPFR register. 4. Set peripheral functions on the PFR register (PFR=1). For details of the basic settings, see the following table. Channel 0 Port Number Port 0 Pin Name TMI0 TMO0 Port 1 TMI0_1 TMO0_1 42 Register Name Bit Name Written Value DDR7 DDR75 0 PFR7 PFR75 0 EPFR33 TMI0E 0 ADCHE ADE5 0 PFR7 PFR72 1 EPFR33 TMO0E1, TMO0E0 01 ADCHE ADE2 0 DDRA DDRA5 0 EPFR33 TMI0E 1 ADCHE ADE21 0 PFRA PFRA2 1 EPFR33 TMO0E1, TMO0E0 10 ADCHE ADE18 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 1 Port Number Port 0 Pin Name TMI1 TMO1 Port 1 TMI1_1 TMO1_1 2 Port 0 TMI2 TMO2 Port 1 TMI2_1 TMO2_1 CM71-10151-2E Register Name Bit Name Written Value DDR7 DDR76 0 PFR7 PFR76 0 EPFR33 TMI1E 0 ADCHE ADE6 0 PFR7 PFR73 1 EPFR33 TMO1E1, TMO1E0 01 ADCHE ADE3 0 DDRA DDRA6 0 PFRA PFRA6 0 EPFR33 TMI1E 1 ADCHE ADE22 0 PFRA PFRA3 1 EPFR33 TMO1E1, TMO1E0 10 ADCHE ADE19 0 DDR7 DDR77 0 PFR7 PFR77 0 EPFR34 TMI2E 0 ADCHE ADE7 0 PFR7 PFR74 1 EPFR34 TMO2E1, TMO2E0 01 ADCHE ADE4 0 DDRA DDRA7 0 PFRA PFRA7 0 EPFR34 TMI2E 1 ADCHE ADE23 0 PFRA PFRA4 1 EPFR34 TMO2E1, TMO2E0 10 ADCHE ADE20 0 FUJITSU MICROELECTRONICS LIMITED 43 CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ Base timer The base timer provides 1 of each of the TIOA/TIOB pins for use with each channel. One of each of the TIOA/TIOB pins can be selected for use with each channel. However, to use pins for the same channel, the pins must be assigned to the same port number. To use the TIOA/TIOB pins for input, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the base timer (For details, see "CHAPTER 22 Base Timer"). To use the TIOA pin for output, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Disable the output of peripheral functions that share this pin with the EPFR register. (For details of the multiplexed pins, see the pin assignment diagram.) 3. Select a pin (port number) to be used on the EPFR register. 4. Set peripheral functions on the PFR register (PFR=1). For details of the basic settings, see the following table. Channel Port Number 0 Port 0 Pin Name TIOA0 TIOB0 1 Port 0 TIOA1 TIOB1 2 Port 0 TIOA2 TIOB2 44 Register Name Bit Name Written Value PFR0 PFR00 1 EPFR20 TIOA0E1, TIOA0E0 01 EPFR6 SOUT0E2 to SOUT0E0 Other than 010 * PFR0 PFR01 0 DDR0 DDR01 0 EPFR20 TIOB0E 0 PFR0 PFR02 At input: 0 At output: 1 DDR0 DDR02 0 (only at input) EPFR20 TIOA1E1, TIOA1E0 01 EPFR6 SCK0E2 to SCK0E0 Other than 010 * PFR0 PFR03 0 DDR0 DDR03 0 EPFR20 TIOB1E 0 PFR0 PFR04 1 EPFR21 TIOA2E1, TIOA2E0 01 EPFR7 SOUT1E1,SOUT1E0 Other than 01 * PFR0 PFR05 0 DDR0 DDR05 0 EPFR21 TIOB2E 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel Port Number 3 Port 0 Pin Name TIOA3 TIOB3 4 Port 0 TIOA4 TIOB4 5 Port 0 TIOA5 TIOB5 6 Port 0 TIOA6 TIOB6 CM71-10151-2E Register Name Bit Name Written Value PFR0 PFR06 At input: 0 At output: 1 DDR0 DDR06 0 (only at input) EPFR21 TIOA3E1, TIOA3E0 01 EPFR7 SCK1E1,SCK1E0 Other than 01 * PFR0 PFR07 0 DDR0 DDR07 0 EPFR21 TIOB3E 0 PFR1 PFR10 1 EPFR22 TIOA4E1, TIOA4E0 01 EPFR8 SOUT2E1,SOUT2E0 Other than 01 * PFR1 PFR11 0 DDR1 DDR11 0 EPFR22 TIOB4E 0 PFR1 PFR12 At input: 0 At output: 1 DDR1 DDR12 0 (only at input) EPFR22 TIOA5E1, TIOA5E0 01 EPFR8 SCK2E1,SCK2E0 Other than 01 * PFR1 PFR13 0 DDR1 DDR13 0 EPFR22 TIOB5E 0 PFR1 PFR14 1 EPFR23 TIOA6E1, TIOA6E0 01 EPFR9 SOUT3E1,SOUT3E0 Other than 01 * PFR1 PFR15 0 DDR1 DDR15 0 EPFR23 TIOB6E 0 FUJITSU MICROELECTRONICS LIMITED 45 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel Port Number 7 Port 0 MB91625 Series Pin Name TIOA7 TIOB7 8 Port 0 TIOA8 TIOB8 9 Port 0 TIOA9 TIOB9 10 Port 0 TIOA10 TIOB10 46 Register Name Bit Name Written Value PFR1 PFR16 At input: 0 At output: 1 DDR1 DDR16 0 (only at input) EPFR23 TIOA7E1, TIOA7E0 01 EPFR9 SCK3E1,SCK3E0 Other than 01 * PFR1 PFR17 0 DDR1 DDR17 0 EPFR23 TIOB7E 0 PFR2 PFR20 1 EPFR24 TIOA8E1, TIOA8E0 01 EPFR10 SOUT4E1,SOUT4E0 Other than 01 * PFR2 PFR21 0 DDR2 DDR21 0 EPFR24 TIOB8E 0 PFR2 PFR22 At input: 0 At output: 1 DDR2 DDR22 0 (only at input) EPFR24 TIOA9E1, TIOA9E0 01 EPFR10 SCK4E1,SCK4E0 Other than 01 * PFR2 PFR23 0 DDR2 DDR23 0 EPFR24 TIOB9E 0 PFR2 PFR24 1 EPFR25 TIOA10E1, TIOA10E0 01 EPFR11 SOUT5E1,SOUT5E0 Other than 01 * PFR2 PFR25 0 DDR2 DDR25 0 EPFR25 TIOB10E 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel Port Number 11 Port 0 Pin Name TIOA11 TIOB11 12 Port 0 TIOA12 TIOB12 13 Port 0 TIOA13 TIOB13 14 Port 0 TIOA14 TIOB14 CM71-10151-2E Register Name Bit Name Written Value PFR2 PFR26 At input: 0 At output: 1 DDR2 DDR26 0 (only at input) EPFR25 TIOA11E1, TIOA11E0 01 EPFR11 SCK5E1,SCK5E0 Other than 01 * PFR2 PFR27 0 DDR2 DDR27 0 EPFR25 TIOB11E 0 PFR3 PFR30 1 EPFR26 TIOA12E1, TIOA12E0 01 EPFR12 SOUT6E1,SOUT6E0 Other than 01 * PFR3 PFR31 0 DDR3 DDR31 0 EPFR26 TIOB12E 0 PFR3 PFR32 At input: 0 At output: 1 DDR3 DDR32 0 (only at input) EPFR26 TIOA13E1, TIOA13E0 01 EPFR12 SCK6E1,SCK6E0 Other than 01 * PFR3 PFR33 0 DDR3 DDR33 0 EPFR26 TIOB13E 0 PFR3 PFR34 1 EPFR27 TIOA14E1, TIOA14E0 01 EPFR13 SOUT7E1,SOUT7E0 Other than 01 * PFR3 PFR35 0 DDR3 DDR35 0 EPFR27 TIOB14E 0 FUJITSU MICROELECTRONICS LIMITED 47 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel Port Number 15 Port 0 MB91625 Series Pin Name TIOA15 TIOB15 Register Name Bit Name Written Value PFR3 PFR36 At input: 0 At output: 1 DDR3 DDR36 0 (only at input) EPFR27 TIOA15E1, TIOA15E0 01 EPFR13 SCK7E1,SCK7E0 Other than 01 * PFR3 PFR37 0 DDR3 DDR37 0 EPFR27 TIOB15E 0 *: Do not write the setting prohibited values. For details, see "CHAPTER 13 I/O Ports". ■ Up/Down counter The up/down counter provides 2 of each of the AIN/BIN/ZIN pins for use with each channel. One of each of the AIN/BIN/ZIN pins can be selected for use with each channel. However, to use pins for the same channel, the pins must be assigned to the same port number. To use the AIN/BIN/ZIN pins, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the up/down counter (For details, see "CHAPTER 23 Up/Down Counter"). 48 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series For details of the basic settings, see the following table. Channel 0 Port Number Port 0 Pin Name AIN0 BIN0 ZIN0 Port 1 AIN0_1 BIN0_1 ZIN0_1 CM71-10151-2E Register Name Bit Name Written Value DDR1 DDR10 0 PFR1 PFR10 0 EPFR18 UDIN0E1, UDIN0E0 00 DDR1 DDR11 0 PFR1 PFR11 0 EPFR18 UDIN0E1, UDIN0E0 00 DDR1 DDR12 0 PFR1 PFR12 0 EPFR18 UDIN0E1, UDIN0E0 00 DDR5 DDR50 0 PFR5 PFR50 0 EPFR18 UDIN0E1, UDIN0E0 01 DDR5 DDR51 0 PFR5 PFR51 0 EPFR18 UDIN0E1, UDIN0E0 01 DDR5 DDR52 0 PFR5 PFR52 0 EPFR18 UDIN0E1, UDIN0E0 01 FUJITSU MICROELECTRONICS LIMITED 49 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 1 Port Number Port 0 MB91625 Series Pin Name AIN1 BIN1 ZIN1 Port 1 AIN1_1 BIN1_1 ZIN1_1 50 Register Name Bit Name Written Value DDR1 DDR14 0 PFR1 PFR14 0 EPFR18 UDIN1E1, UDIN1E0 00 DDR1 DDR15 0 PFR1 PFR15 0 EPFR18 UDIN1E1, UDIN1E0 00 DDR1 DDR16 0 PFR1 PFR16 0 EPFR18 UDIN1E1, UDIN1E0 00 DDR5 DDR54 0 PFR5 PFR54 0 EPFR18 UDIN1E1, UDIN1E0 01 DDR5 DDR55 0 PFR5 PFR55 0 EPFR18 UDIN1E1, UDIN1E0 01 DDR5 DDR56 0 PFR5 PFR56 0 EPFR18 UDIN1E1, UDIN1E0 01 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 2 Port Number Port 0 Pin Name AIN2 BIN2 ZIN2 Port 1 AIN2_1 BIN2_1 ZIN2_1 CM71-10151-2E Register Name Bit Name Written Value DDR2 DDR20 0 PFR2 PFR20 0 EPFR18 UDIN2E1, UDIN2E0 00 DDR2 DDR21 0 PFR2 PFR21 0 EPFR18 UDIN2E1, UDIN2E0 00 DDR2 DDR22 0 PFR2 PFR22 0 EPFR18 UDIN2E1, UDIN2E0 00 DDR6 DDR60 0 EPFR18 UDIN2E1, UDIN2E0 01 DDR6 DDR61 0 PFR6 PFR61 0 EPFR18 UDIN2E1, UDIN2E0 01 DDR6 DDR62 0 EPFR18 UDIN2E1, UDIN2E0 01 FUJITSU MICROELECTRONICS LIMITED 51 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 3 Port Number Port 0 MB91625 Series Pin Name AIN3 BIN3 ZIN3 Port 1 AIN3_1 BIN3_1 ZIN3_1 52 Register Name Bit Name Written Value DDR2 DDR24 0 PFR2 PFR24 0 EPFR18 UDIN3E1, UDIN3E0 00 DDR2 DDR25 0 PFR2 PFR25 0 EPFR18 UDIN3E1, UDIN3E0 00 DDR2 DDR26 0 PFR2 PFR26 0 EPFR18 UDIN3E1, UDIN3E0 00 DDR6 DDR64 0 PFR6 PFR64 0 EPFR18 UDIN3E1, UDIN3E0 01 DDR6 DDR65 0 EPFR18 UDIN3E1, UDIN3E0 01 DDR6 DDR66 0 PFR6 PFR66 0 EPFR18 UDIN3E1, UDIN3E0 01 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ 10-bit A/D converter • AN pins Pin Name Register Name Bit Name Written Value AN0 to AN7 ADCHE ADE0 to ADE7 1 AN8 to AN15 ADCHE ADE8 to ADE15 1 ADCHE: A/D channel enable register • ADTRG0 pins The 10-bit A/D converter provides 3 pins. One pin can be selected for use. To use the ADTRG0 pin, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the 10-bit A/D converter (For details, see "CHAPTER 24 10-Bit A/D Converter"). For details of the basic settings, see the following table. Unit Port Number 0 Port 0 Pin Name ADTRG0 Port 1 ADTRG0_1 Port 2 ADTRG0_2 Register Name Bit Name Written Value DDR5 DDR55 0 PFR5 PFR55 0 EPFR19 ADTRG0E2 to ADTRG0E0 000 DDR6 DDR65 0 EPFR19 ADTRG0E2 to ADTRG0E0 001 DDRK DDRK2 0 EPFR19 ADTRG0E2 to ADTRG0E0 010 ■ 8-bit D/A converter Pin Name DA0, DA1 Register Name DACR0, DACR1 Bit Name DAE Written Value 1 DACR: D/A control register CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 53 CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series ■ Multifunction serial interface The multifunction serial interface provides multiple SCK pins , SIN pins, and SOUT pins for use with one channel. One of each of the SCK/SIN/SOUT pins can be selected for use with each channel. However, to use pins for the same channel, the pins must be assigned to the same port number. To use the SIN/SCK pins for input, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Select a pin (port number) to be used on the EPFR register. 3. Enable the operation of the multifunction serial interface (For details, see "CHAPTER 26 Multifunction Serial Interface".). To use the SOUT/SCK pins for output, the following settings are required. 1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0). 2. Disable the output of peripheral functions that share this pin with the EPFR register. (For details of the multiplexed pins, see the pin assignment diagram.) 3. Select a pin (port number) to be used on the EPFR register. 4. Set peripheral functions on the PFR register (PFR=1). For details of the basic settings, see the following table. Channel 0 Port Number Port 0 Pin Name SCK0 SIN0 SOUT0 54 Register Name Bit Name Written Value PFR7 PFR77 At SCK input: 0 At SCK output: 1 DDR7 DDR77 0 (only at SCK input) EPFR6 SCK0E2 to SCK0E0 001 SMR0 SCKE Input enable: 0 Output enable: 1 ADCHE ADE7 0 DDR7 DDR76 0 PFR7 PFR76 0 EPFR6 SIN0E1, SIN0E0 00 ADCHE ADE6 0 PFR7 PFR75 1 EPFR6 SOUT0E2 to SOUT0E0 001 SMR0 SOE 1 ADCHE ADE5 0 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 0 Port Number Port 1 Pin Name SCK0_1 SIN0_1 SOUT0_1 1 Port 0 SCK1 (SCL1) SIN1 SOUT1 (SDA1) CM71-10151-2E Register Name Bit Name Written Value PFR0 PFR02 At SCK input: 0 At SCK output: 1 DDR0 DDR02 0 (only at SCK input) EPFR6 SCK0E2 to SCK0E0 010 SMR0 SCKE Input enable: 0 Output enable: 1 DDR0 DDR01 0 PFR0 PFR01 0 EPFR6 SIN0E1, SIN0E0 01 PFR0 PFR00 1 EPFR6 SOUT0E2 to SOUT0E0 010 SMR0 SOE 1 PFR0 PFR06 At SCK input: 0 At SCK or SCL output: 1 DDR0 DDR06 0 (only at SCK input) EPFR7 SCK1E1, SCK1E0 01 SMR1 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR0 DDR05 0 PFR0 PFR05 0 EPFR7 SIN1E 0 PFR0 PFR04 1 EPFR7 SOUT1E1, SOUT1E0 01 SMR1 SOE 1 FUJITSU MICROELECTRONICS LIMITED 55 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 2 Port Number Port 0 Pin Name SCK2 (SCL2) SIN2 SOUT2 (SDA2) 3 Port 0 SCK3 (SCL3) SIN3 SOUT3 (SDA3) 56 MB91625 Series Register Name Bit Name Written Value PFR1 PFR12 At SCK input: 0 At SCK or SCL output: 1 DDR1 DDR12 0 (only at SCK input) EPFR8 SCK2E1, SCK2E0 01 SMR2 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR1 DDR11 0 PFR1 PFR11 0 EPFR8 SIN2E 0 PFR1 PFR10 1 EPFR8 SOUT2E1, SOUT2E0 01 SMR2 SOE 1 PFR1 PFR16 At SCK input: 0 At SCK or SCL output: 1 DDR1 DDR16 0 (only at SCK input) EPFR9 SCK3E1, SCK3E0 01 SMR3 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR1 DDR15 0 PFR1 PFR15 0 EPFR9 SIN3E 0 PFR1 PFR14 1 EPFR9 SOUT3E1, SOUT3E0 01 SMR3 SOE 1 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 4 Port Number Port 0 Pin Name SCK4 (SCL4) SIN4 SOUT4 (SDA4) 5 Port 0 SCK5 (SCL5) SIN5 SOUT5 (SDA5) CM71-10151-2E Register Name Bit Name Written Value PFR2 PFR22 At SCK input: 0 At SCK or SCL output: 1 DDR2 DDR22 0 (only at SCK input) EPFR10 SCK4E1, SCK4E0 01 SMR4 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR2 DDR21 0 PFR2 PFR21 0 EPFR10 SIN4E 0 PFR2 PFR20 1 EPFR10 SOUT4E1, SOUT4E0 01 SMR4 SOE 1 PFR2 PFR26 At SCK input: 0 At SCK or SCL output: 1 DDR2 DDR26 0 (only at SCK input) EPFR11 SCK5E1, SCK5E0 01 SMR5 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR2 DDR25 0 PFR2 PFR25 0 EPFR11 SIN5E 0 PFR2 PFR24 1 EPFR11 SOUT5E1, SOUT5E0 01 SMR5 SOE 1 FUJITSU MICROELECTRONICS LIMITED 57 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 6 Port Number Port 0 Pin Name SCK6 (SCL6) SIN6 SOUT6 (SDA6) 7 Port 0 SCK7 (SCL7) SIN7 SOUT7 (SDA7) 58 MB91625 Series Register Name Bit Name Written Value PFR3 PFR32 At SCK input: 0 At SCK or SCL output: 1 DDR3 DDR32 0 (only at SCK input) EPFR12 SCK6E1, SCK6E0 01 SMR6 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR3 DDR31 0 PFR3 PFR31 0 EPFR12 SIN6E 0 PFR3 PFR30 1 EPFR12 SOUT6E1, SOUT6E0 01 SMR6 SOE 1 PFR3 PFR36 At SCK input: 0 At SCK or SCL output: 1 DDR3 DDR36 0 (only at SCK input) EPFR13 SCK7E1, SCK7E0 01 SMR7 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR3 DDR35 0 PFR3 PFR35 0 EPFR13 SIN7E 0 PFR3 PFR34 1 EPFR13 SOUT7E1, SOUT7E0 01 SMR7 SOE 1 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 2 Pins of the MB91625 Series 2.4 MB91625 Series Channel 8 Port Number Port 0 Pin Name SCK8 (SCL8) SIN8 SOUT8 (SDA8) 9 Port 0 SCK9 (SCL9) SIN9 SOUT9 (SDA9) CM71-10151-2E Register Name Bit Name Written Value PFR4 PFR42 At SCK input: 0 At SCK or SCL output: 1 DDR4 DDR42 0 (only at SCK input) EPFR14 SCK8E1, SCK8E0 01 SMR8 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR4 DDR41 0 PFR4 PFR41 0 EPFR14 SIN8E 0 PFR4 PFR40 1 EPFR14 SOUT8E1, SOUT8E0 01 SMR8 SOE 1 PFR4 PFR46 At SCK input: 0 At SCK or SCL output: 1 DDR4 DDR46 0 (only at SCK input) EPFR15 SCK9E1, SCK9E0 01 SMR9 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR4 DDR45 0 PFR4 PFR45 0 EPFR15 SIN9E 0 PFR4 PFR44 1 EPFR15 SOUT9E1, SOUT9E0 01 SMR9 SOE 1 FUJITSU MICROELECTRONICS LIMITED 59 CHAPTER 2 Pins of the MB91625 Series 2.4 Channel 10 Port Number Port 0 Pin Name SCK10 (SCL10) SIN10 SOUT10 (SDA10) 11 Port 0 SCK11 (SCL11) SIN11 SOUT11 (SDA11) MB91625 Series Register Name Bit Name Written Value PFR5 PFR52 At SCK input: 0 At SCK or SCL output: 1 DDR5 DDR52 0 (only at SCK input) EPFR16 SCK10E1, SCK10E0 01 SMR10 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR5 DDR51 0 PFR5 PFR51 0 EPFR16 SIN10E 0 PFR5 PFR50 1 EPFR16 SOUT10E1, SOUT10E0 01 SMR10 SOE 1 PFR5 PFR56 At SCK input: 0 At SCK or SCL output: 1 DDR5 DDR56 0 (only at SCK input) EPFR17 SCK11E1, SCK11E0 01 SMR11 SCKE Input enable: 0 Output enable: 1 (Only at SCK) DDR5 DDR55 0 PFR5 PFR55 0 EPFR17 SIN11E 0 PFR5 PFR54 1 EPFR17 SOUT11E1, SOUT11E0 01 SMR11 SOE 1 SMR: Serial mode register <Note> Different pins are enabled depending on the operation mode. For details, see "CHAPTER 26 Multi-function Serial Interface". 60 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU This chapter explains the basics of the FR80 family CPUs, including its architecture, specifications, and instructions, to provide a better understanding of the CPU functions. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 CM71-10151-2E Memory Space Features of the Internal Architecture Operation Modes Pipeline Overview of Instructions Basic Programming Model Registers Data Configuration Addressing Branch Instructions EIT (Exception, Interrupt, Trap) FUJITSU MICROELECTRONICS LIMITED 61 CHAPTER 3 CPU 3.1 3.1 MB91625 Series Memory Space The logical address space of the FR80 family CPUs is 4 GB (232 locations), and the CPUs can linearly access it. ■ Direct addressing areas The address spaces 0000 0000H to 0000 03FFH are called the direct addressing areas. These areas allow operands to be specified directly in instructions. The direct addressing areas vary as follows depending on the size of the data accessed: 62 • Byte data access: 0000 0000H to 0000 00FFH • Half word data access: 0000 0000H to 0000 01FFH • Word data access: 0000 0000H to 0000 03FFH FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.1 MB91625 Series ■ Memory map Figure 3.1-1 shows a memory map of the MB91625 series. Figure 3.1-1 Memory map MB91F627 Flash 512 Kbytes RAM 48 Kbytes 0000 0000H 0003 4000H 0004 0000H Built-in RAM area 48 Kbytes 0003 8000H 0004 0000H Reserved Built-in RAM area 32 Kbytes Reserved 0008 0000H Flash area 512 Kbytes Small-sector area ROM area 512 Kbytes 0010 0000H Reserved FFFF FFFFH Reserved Reserved Reserved 0008 0000H 000F 8000H 0010 0000H 0001 0000H 0001 0000H Built-in RAM area 48 Kbytes I/O area I/O area Reserved 0004 0000H 0000 0400H 0000 0400H 0001 0000H I/O area (Direct addressing) I/O area (Direct addressing) I/O area 0003 4000H 0000 0000H 0000 0000H I/O area (Direct addressing) 0000 0400H MB91F625 Flash 256 Kbytes RAM 32 Kbytes MB91627 ROM 512 Kbytes RAM 48 Kbytes 000C 0000H 000F 8000H 0010 0000H Reserved Reserved FFFF FFFFH Flash area 256 Kbytes Small-sector area FFFF FFFFH <Notes> • For details of the small-sector area in flash memory, see "CHAPTER 30 Flash Memory". The small-sector area concerns only the flash memory products. • Do not access the reserved areas. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 63 CHAPTER 3 CPU 3.2 3.2 MB91625 Series Features of the Internal Architecture The FR80 family CPUs have a high-performance core based on the RISC architecture with high-level functions and instructions included for embedded applications. • Adoption of the RISC architecture Basic instructions: 1 instruction/1 cycle • 32-bit architecture 16 general-purpose 32-bit registers • Linearly accessed 4-GB memory space • Built-in multipliers • - 32-bit × 32-bit multiplication: 5 cycles - 16-bit × 16-bit multiplication: 3 cycles Enhanced interrupt processing functions - • • High-speed response (6 cycles) - Multi-interrupt support - Level mask function (16 levels) Enhanced instructions for I/O operations - Memory-to-memory transfer instruction - Bit processing instruction High code efficiency - Basic instruction word length: 16 bits • Compatibility of basic instructions with the FR60 family • Addition of the following instructions to the instructions of the FR60 family: - • • Bit search instructions (SRCH0, SRCH1, and SRCHC) Deletion of the following instructions from the instructions of the FR60 family: - Coprocessor instructions (COPOP, COPLD, COPST, and COPSV) - Resource instructions (LDRES and STRES) Non-blocking load Up to 4 load instructions can be issued in advance. 64 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.3 MB91625 Series 3.3 Operation Modes This section explains the operation modes of this series. This series provides the operation modes below. At an activation of the device, one of these operation modes can be selected. • User single-chip mode • Serial programming mode Table 3.3-1 lists the operation modes of this series. Table 3.3-1 Operation modes MD Pin MD1 0 CM71-10151-2E Control Pin MD0 Operation Mode P75 0 X User single-chip mode 1 1 Serial programming mode FUJITSU MICROELECTRONICS LIMITED 65 CHAPTER 3 CPU 3.4 3.4 MB91625 Series Pipeline The FR architecture of the FR80 family CPUs is a compact 32-bit RISC architecture. It has not only the normal instruction execution pipeline but also an additional pipeline for loading memory, which can reduce pipeline hazards during load instruction execution. A five-stage instruction pipeline method is used in executing 1 instruction per cycle. The pipeline consists of the following stages: • Instruction fetch (IF) stage: Fetches the instruction at the output address. • Instruction decode (ID) stage: Decodes the fetched instruction. It also reads a register. • Execution (EX) stage: Executes the decoded instruction. • Memory access (MA) stage: Accesses the target memory. • Register writing (WB) stage: Writes the operation results (or loaded memory data) to a register. The pipeline for loading memory has been added so that the MA and WB stages of the instruction, which does not access memory, can overlap the MA and WB stages of an LD instruction. As a rule, 1 instruction is executed per cycle. However, more than one cycle is required for execution of a load/store instruction with memory wait, a branch instruction without a delay slot, or a multi-cycle instruction. In addition, the instruction execution speed is slower when there is a delay in supplying an instruction. Example 1: CLK (1) LD @R10,R1 (2) LDI:8 #0x02,R2 (3) CMP R1, R2 (4) BNE:D Label_G (5) ADD #0x1,R1 IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB Example 1:The instructions are executed in sequence because the data that uses R1 to write the (1) LD instruction is returned in the (3) CMP instruction within 1 cycle. In the load operation, the MA stage is extended until reading of the loaded data is completed. However, if the register used for loading will not be used for the subsequent instructions, the instruction is executed as is. 66 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.4 MB91625 Series Example 2: CLK (1) LD @R10,R1 (2) LDI:8 #0x02,R2 (3) CMP R1, R2 (4) BNE:D Label_G (5) ADD #0x1,R1 IF ID EX MA MA MA WB IF ID EX MA WB IF ID ID ID EX MA WB IF ID EX MA WB IF ID EX MA WB Example 2:The data that uses R1 to write the (1) LD instruction is not returned within 1 cycle in the (3) CMP instruction, resulting in execution only up to the (2) LDI:8 instruction and keeping the CMP instruction waiting in the ID stage because of a register conflict. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 67 CHAPTER 3 CPU 3.5 3.5 MB91625 Series Overview of Instructions In addition to the general RISC instruction set, the FR80 family CPUs support the logical operations optimized for embedded applications, bit operation instructions, and direct addressing instructions. Each instruction has a length of 16 bits (some instructions have a length of 32 or 48 bits) and provides superior performance in memory usage efficiency. The instruction sets can be divided into the following function groups: 3.5.1 • Arithmetic operation • Load and store • Branch • Logical operation and bit operation • Direct addressing • Bit search • Other Arithmetic Operation These instructions are standard arithmetic instructions (addition, subtraction, and comparison) and shift instructions (logical shift and arithmetic operation shift). The arithmetic operations of addition and subtraction can include operations with a carry used in individual operations with a multi-word length (operation for 32 or more bits of data) and operations suitable for address calculation in which flag values are not changed. Also included in these instructions are the 32-bit × 32-bit multiplication instruction, 16-bit × 16-bit multiplication instruction, and 32-bit / 32-bit step division instruction. The immediate transfer instruction that sets immediate data in a register and the register-to-register transfer instruction are also included. All the operations of arithmetic operation instructions use the general-purpose registers and Multiply & Divide registers in the CPUs. 3.5.2 Load and Store Load and store are instructions for reading and writing external memory. They are also used for reading and writing by the internal peripheral functions of the chip. The access lengths of load and store are in any of 3 units: byte, half word, and word. In addition to general-purpose register indirect memory addressing, some load and store instructions can use register indirect memory addressing with either displacement or register increment/decrement operations. 68 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.5 MB91625 Series 3.5.3 Branch Branch instructions include branch, call, interrupt, and return instructions. The branch instructions consist of instructions with delay slots and instructions without delay slots, and they can be optimized as required. For details of the branch instructions, see "3.10 Branch Instructions". 3.5.4 Logical Operation and Bit Operation Logical operation instructions can perform the AND, OR, and EOR logical operations between generalpurpose registers or between a general-purpose register and memory (and I/O). Also, bit operation instructions can directly manipulate data on memory (and of I/O). Memory addressing is general-purpose register indirect memory addressing. 3.5.5 Direct Addressing Direct addressing instructions are instructions used for access between I/O and a general-purpose register or between I/O and memory. Specifying an I/O address directly in an instruction instead of using register indirect addressing enables highly efficient high-speed access. Also, some direct addressing instructions can perform register indirect memory addressing with register increment/decrement operations. 3.5.6 Bit Search A bit search instruction searches 32-bit data beginning from the MSB to obtain the bit location of the first "1" or "0" found in the register. A bit search instruction can also make a comparison with the MSB value and obtain the bit location of a value different from the first MSB found in a register. 3.5.7 Other Other available instructions include those for setting flags in the PS register, performing stack operations, and making a carry/zero extension. Also included in these instructions are function entry/exit instructions supporting high-level languages and multi-load/store instructions for registers. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 69 CHAPTER 3 CPU 3.6 3.6 MB91625 Series Basic Programming Model Figure 3.6-1 shows the basic programming model. Figure 3.6-1 Basic programming model 32 bits Initial value General-purpose registers R0 XXXX XXXXH R1 XXXX XXXXH R2 XXXX XXXXH R3 XXXX XXXXH R4 XXXX XXXXH R5 XXXX XXXXH R6 XXXX XXXXH R7 XXXX XXXXH R8 XXXX XXXXH R9 XXXX XXXXH R10 XXXX XXXXH R11 XXXX XXXXH R12 XXXX XXXXH R13 AC XXXX XXXXH R14 FP XXXX XXXXH R15 SP 0000 0000H Program counter (PC) XXXX XXXXH Program status (PS) ILM - SCR CCR Table base register (TBR) 000F FC00H Return pointer (RP) XXXX XXXXH System stack pointer (SSP) 0000 0000H User stack pointer (USP) XXXX XXXXH Multiply & Divide register 70 - (MDH) XXXX XXXXH (MDL) XXXX XXXXH FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series 3.7 Registers The register configuration consists of general-purpose registers and dedicated registers for specific purposes. 3.7.1 General-purpose Registers (R0 to R15) Registers R0 to R15 are general-purpose registers. They are used as accumulators and memory access pointers in a variety of operations. Figure 3.7-1 shows the bit configuration of the general-purpose registers (R0 to R15). Figure 3.7-1 Bit configuration of the general-purpose registers (R0 to R15) 32 bits Initial value R0 XXXX XXXXH R1 XXXX XXXXH R2 XXXX XXXXH R3 XXXX XXXXH R4 XXXX XXXXH R5 XXXX XXXXH R6 XXXX XXXXH R7 XXXX XXXXH R8 XXXX XXXXH R9 XXXX XXXXH R10 XXXX XXXXH R11 XXXX XXXXH R12 XXXX XXXXH R13 AC XXXX XXXXH R14 FP XXXX XXXXH R15 SP 0000 0000H Of the 16 registers, the following registers are assumed to have specific purposes, and certain instructions have therefore been enhanced. For details of the initial values at the reset time, see Figure 3.7-1. • R13: Virtual accumulator (AC) • R14: Frame pointer (FP) • R15: Stack pointer (SP) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 71 CHAPTER 3 CPU 3.7 3.7.2 MB91625 Series Program Status Register (PS) This register retains the program status, and it is divided into 3 parts: interrupt level mask register (ILM), system condition code register (SCR), and condition code register (CCR). Figure 3.7-2 shows the bit configuration of the program status register (PS). Figure 3.7-2 Bit configuration of the program status register (PS) bit 31 21 20 Undefined 16 15 ILM 11 10 Undefined 8 7 SCR 0 CCR [bit31 to bit21, bit15 to bit11]: Undefined bits In case of writing Ignored In case of reading "0" is always read. [bit20 to bit16] Interrupt level mask register (ILM) See "■ Interrupt level mask register (ILM)". [bit10 to bit8] System condition code register (SCR) See "■ System condition register (SCR)". [bit7 to bit0] Condition code register (CCR) See "■ Condition code register (CCR)". 72 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series ■ Condition code register (CCR) Figure 3.7-3 shows the bit configuration of the condition code register (CCR). Figure 3.7-3 Bit configuration of the condition code register (CCR) bit 7 6 5 4 3 2 1 0 Undefined Undefined S I N Z V C Attribute - - R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 X X X X R/W: Read/Write -: Undefined X: Undefined [bit7, bit6]: Undefined bits In case of writing Ignored In case of reading "0" is always read. [bit5]: S (Stack flag) This bit specifies a stack pointer operating as general-purpose register 15 (R15). S Explanation 0 The system stack pointer (SSP) is operating as general-purpose register 15 (R15). The bit is automatically cleared to "0" when EIT occurs. (However, the value before the bit is cleared is saved to the stack.) 1 The user stack pointer (USP) is operating as general-purpose register 15 (R15). This bit is cleared to "0" when the system is reset. "0" must be written when the RETI instruction is executed. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 73 CHAPTER 3 CPU 3.7 MB91625 Series [bit4]: I (Interrupt enable flag) This bit controls enabling/disabling of user interrupt requests. I Explanation 0 Disables user interrupt requests. The bit is automatically cleared to "0" when the INT instruction is executed. (However, the value before the bit is cleared is saved to the stack.) 1 Enables user interrupt requests. The mask processing of user interrupt requests is controlled with the value retained by the interrupt level mask register (ILM). This bit is cleared to "0" when the system is reset. [bit3]: N (Negative flag) This bit indicates a carry for an operation result recognized as an integer represented by a 2's complement. N Explanation 0 Indicates that the operation result is a positive value. 1 Indicates that the operation result is a negative value. The initial state set by a reset is undefined. [bit2]: Z (Zero flag) This bit indicates whether the result of an operation is "0". Z Explanation 0 Indicates that the operation result is not "0". 1 Indicates that the operation result is "0". The initial state set by a reset is undefined. [bit1]: V (Overflow flag) This bit indicates whether an overflow occurred as a result of an operation by interpreting each operand used for the operation as integers represented by 2's complements. V Explanation 0 No overflow occurred as a result of the operation. 1 An overflow occurred as a result of the operation. The initial state set by a reset is undefined. 74 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series [bit0]: C (Carry flag) This bit indicates whether a carry or borrow from the most significant bit occurred as a result of an operation. C Explanation 0 No carry or borrow occurred. 1 A carry or borrow occurred. The initial state set by a reset is undefined. ■ System condition register (SCR) Figure 3.7-4 shows the bit configuration of the system condition register (SCR). Figure 3.7-4 Bit configuration of the system condition register (SCR) bit Attribute Initial value 10 9 8 D1 D0 T R/W R/W R/W X X 0 R/W: Read/Write X: Undefined [bit10, bit9]: D1, D0 (Step division flag) These bits retain in-process data during step division execution. Do not change these bits while division processing is being executed. To execute any other processing during step division, save and return the value of the program status register (PS). Doing so ensures a restart of step division. The initial state set by a reset is undefined. <Notes> • The bits are set with the reference of the dividend and divisor by execution of the DIV0S instruction. • They are forcibly cleared by execution of the DIV0U instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 75 CHAPTER 3 CPU 3.7 MB91625 Series [bit8]: T (Step trace trap flag) This bit specifies whether the step trace trap is enabled. T Explanation 0 The step trace trap is disabled. 1 The step trace trap is enabled. All user interrupt requests are disabled. This bit is cleared to "0" when the system is reset. Emulators use the step trace trap function. The step trace trap cannot be used in a user program together with an emulator. ■ Interrupt level mask register (ILM) This register retains the interrupt level mask value. The value retained by the register is used for the level mask. Figure 3.7-5 shows the bit configuration of the interrupt level mask register (ILM). Figure 3.7-5 Bit configuration of the interrupt level mask register (ILM) bit Attribute Initial value 20 19 18 17 16 ILM4 ILM3 ILM2 ILM1 ILM0 R/W R/W R/W R/W R/W 0 1 1 1 1 R/W: Read/Write An interrupt request that is input to the CPU is accepted only if the corresponding interrupt level is higher than the level specified by this register. The highest level is "0" (00000B), and the lowest is "31" (11111B). A limited range of values can be set from programs. • Original value in a range of 16 to 31: A value ranging from 16 to 31 can be specified as a new value. If a value ranging from 0 to 15 is set for an instruction, (specified-value + 16) is transferred when the instruction is executed. • Original value in a range of 0 to 15: Any value ranging from 0 to 31 can be specified. These bits are initialized to "15" (01111B) by a reset. 76 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series 3.7.3 Program Counter (PC) This register is the program counter (PC) indicating the address of the instruction being executed. Figure 3.7-6 shows the bit configuration of the program counter (PC). Figure 3.7-6 Bit configuration of the program counter (PC) bit 31 0 Initial value XXXX XXXXH bit0 is set to "0" when an instruction that entails a PC update is executed. It is prohibited to specify an odd-numbered location as the branch destination address, and to set bit0 to "1". The instruction would have to be located at an address that is a multiple of 2. The initial value following a reset is undefined, and the program start address is set by a reset vector fetch. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 77 CHAPTER 3 CPU 3.7 3.7.4 MB91625 Series Table Base Register (TBR) This register retains the start address of the vector table used for EIT processing. Figure 3.7-7 shows the bit configuration of the table base register (TBR). Figure 3.7-7 Bit configuration of the table base register (TBR) bit 31 0 Initial value 000F FC00H The initial value following a reset is "000F FC00H". 78 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series 3.7.5 Return Pointer (RP) This pointer retains the return destination address when returning from a subroutine. Figure 3.7-8 shows the bit configuration of the return pointer (RP). Figure 3.7-8 Bit configuration of the return pointer (RP) bit 31 0 Initial value XXXX XXXXH The value of the program counter (PC) is transferred to this register when the CALL instruction is executed. The register contents are transferred to the program counter (PC) when the RET instruction is executed. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 79 CHAPTER 3 CPU 3.7 3.7.6 MB91625 Series System Stack Pointer (SSP) This pointer operates as R15 when the S flag of the condition code register (CCR) is "0". Also, the system stack pointer (SSP) can be specified explicitly. It can be used as a stack pointer specifying the stack for saving the program status register (PS) and the program counter (PC) when EIT occurs. Figure 3.7-9 shows the bit configuration of the system stack pointer (SSP). Figure 3.7-9 Bit configuration of the system stack pointer (SSP) bit 31 0 Initial value 0000 0000H The initial value following a reset is "0000 0000H". 80 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.7 MB91625 Series 3.7.7 User Stack Pointer (USP) This pointer operates as R15 when the S flag of the condition code register (CCR) is "1". Also, the user stack pointer (USP) can be specified explicitly. Figure 3.7-10 shows the bit configuration of the user stack pointer (USP). Figure 3.7-10 Bit configuration of the user stack pointer (USP) bit 31 0 Initial value XXXX XXXXH The initial value following a reset is undefined. This pointer cannot be used in the RETI instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 81 CHAPTER 3 CPU 3.7 3.7.8 MB91625 Series Multiply & Divide Registers These registers are used for multiplication and division, and each register has a length of 32 bits. Figure 3.7-11 Bit configuration of the Multiply & Divide registers bit 31 0 Initial value MDH XXXX XXXXH MDL XXXX XXXXH The initial value following a reset is undefined. ● In multiplication In multiplication of 32 bits × 32 bits, the result of an operation with a length of 64 bits is stored in the Multiply & Divide registers at the following locations: • MDH: Upper 32 bits • MDL: Lower 32 bits In multiplication of 16 bits × 16 bits, the result is stored as follows: • MDH: Undefined • MDL: 32-bit result ● In division The dividend is stored in MDL at the start of calculation. In division according to the DIV0S, DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, the result is stored in MDH and MDL: 82 • MDH: Remainder • MDL: Quotient FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.8 MB91625 Series 3.8 Data Configuration Data is arranged in the FR80 family CPUs in the following two ways: • Bit Ordering • Byte Ordering 3.8.1 Bit Ordering The FR80 family CPUs use little endian for bit ordering. Figure 3.8-1 shows the bit ordering. Figure 3.8-1 Bit ordering 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 MSB CM71-10151-2E 6 5 4 3 2 1 0 LSB FUJITSU MICROELECTRONICS LIMITED 83 CHAPTER 3 CPU 3.8 3.8.2 MB91625 Series Byte Ordering The FR80 family CPUs use big endian for byte ordering. Figure 3.8-2 shows the byte ordering. Figure 3.8-2 Byte ordering MSB LSB bit31 10101010 bit23 bit15 11001100 bit7 11111111 bit0 00010001 bit 7 84 0 Location n 10101010 Location (n+1) 11001100 Location (n+2) 11111111 Location (n+3) 00010001 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.8 MB91625 Series 3.8.3 Word Alignment ■ Program access Programs for the FR80 family CPUs must be located at addresses that are multiples of 2. bit0 of the program counter (PC) is set to "0" when an instruction that entails the program counter (PC) update is executed. It is prohibited to specify an odd-numbered location as the branch destination address, and to set bit0 to "1". The instruction would have to be located at an address that is a multiple of 2. There is no odd-numbered address exception. ■ Data access For an accessing of data in the FR80 family, set the address depending on the size of the data accessed as shown below. (The address is not aligned by the hardware.) Word access: The address is a multiple of 4 (the lowest 2 bits are set to "00"). Half word access: The address is a multiple of 2 (the lowest bit is set to "0"). Byte access: ---During a word or half word data access, set the above address for the result from a calculation of the effective address. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 85 CHAPTER 3 CPU 3.9 3.9 MB91625 Series Addressing The memory space consists of linear 32-bit addresses. Figure 3.9-1 shows the memory space. Figure 3.9-1 Memory Space 0000 0000H Byte data 0000 0100H Direct addressing areas Half word data 0000 0200H Word data 0000 0400H TBR 20-bit addressing area 000F FC00H Vector table 000F FFFFH 32-bit addressing area FFFF FFFFH 3.9.1 Direct Addressing Areas The memory space areas listed below are areas for I/O. Direct addressing enables these areas to be specified directly as operand addresses in instructions. The size of an address area that can be specified by a direct address varies depending on the data length. 86 • Byte data (8 bits): 0 to 0x0FF • Half word data (16 bits): 0 to 0x1FF • Word data (32 bits): 0 to 0x3FF FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.9 MB91625 Series 3.9.2 20-bit Addressing Area 20-bit addressing area: 0 to 0xFFFFF If all the program and data areas are located in the 20-bit addressing area, programs will be more compact and therefore have high performance after compilation. An example of expansion of a normal 20-bit branch macro instruction is shown below. BRA20 label20,Ri ↓ Code size LDI:20 #label20,Ri ; 4 bytes JMP @Ri ; 2 bytes Total: 6 bytes For details, see the "FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6". 3.9.3 32-bit Addressing Area 32-bit addressing area: 0 to 0xFFFFFFFF If the program and data areas are located beyond the 20-bit addressing area, the code sizes of programs will be larger than those of programs created in the 20-bit addressing area. An example of expansion of a normal 32-bit branch macro instruction is shown below. BRA32 label32,Ri ↓ Code size LDI:32 #label32,Ri ; 6 bytes JMP @Ri ; 2 bytes Total: 8 bytes For details, see the "FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6". 3.9.4 Vector Table Initial Area The area from 000F FC00H to 000F FFFFH is the EIT vector table initial area. The vector table used for EIT processing can be placed at an arbitrary address by changing the table base register (TBR) accordingly, but the initial address following a reset is the above address. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 87 CHAPTER 3 CPU 3.10 MB91625 Series 3.10 Branch Instructions Operation with delay slots and operation without delay slots can be specified for branch instructions in the FR80 family CPUs. 3.10.1 Operation with Delay Slots ■ Instructions The following instructions perform branch operations with delay slots: JMP:D @Ri / CALL:D label12 / CALL:D @Ri / RET:D BRA:D label9 / BNO:D label9 / BEQ:D label9 / BNE:D label9 BC:D label9 / BNC:D label9 / BN:D label9 / BP:D label9 BV:D label9 / BNV:D label9 / BLT:D label9 / BGE:D label9 BLE:D label9 / BGT:D label9 / BLS:D label9 / BHI:D label9 ■ Explanation of operation The instruction that is located immediately following a branch instruction (the location is called a "delay slot") is executed before branching, and an instruction at the branch destination is executed after that. Because the instruction in the delay slot is executed before the branch operation, the apparent execution speed is 1 cycle. Such being the case, if no valid instruction can be entered in the delay slot, the NOP instruction must be placed there instead. Example: ; Order of instructions ADD R1, R2; BRA:D LABEL ; Branch instruction MOV R2, R3 ; Delay slot R3, @R4 ; Branch destination ...... Executed before branching ... LABEL: ST The conditional branch instruction that is located in the delay slot is executed whether the branch condition is satisfied or not. Although the sequence of execution of some instructions seems to be inverted for delay branch instructions, the sequence is inverted only when the program counter (PC) is updated. Any other operations, such as updating or referencing a register, are executed in the sequence described. 88 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.10 MB91625 Series Concrete explanations are given below. 1. Ri referenced by the JMP:D @Ri / CALL:D @Ri instruction is not affected even when updated by the instruction in a delay slot. Example: LDI:32 #Label, R0 JMP:D @R0 ; Branching to Label LDI:8 #0, R0 ; The branch destination address is not affected. ... 2. The return pointer (RP) referenced by the RET:D instruction is not affected even when the instruction in a delay slot updates the return pointer (RP). Example: RET:D MOV ; Branching to the address indicated by the RP specified beforehand R8, RP ; The return operation is not affected. ... 3. The flag referenced by the Bcc:D rel instruction is not affected by the instruction in a delay slot either. Example: ADD #1, R0 ; Flag change BC:D Overflow ; Branching according to the execution result of the above instruction ANDCCR #0 ; This flag update is not referenced in the above branch instruction. ... 4. When the RP is referenced in an instruction in the delay slot of the CALL:D instruction, the updated contents are read by the CALL:D instruction. Example: CALL:D Label ; RP update and branching MOV RP, R0 ; Transfer of the RP of the execution result for the above CALL:D ... ■ Instructions that can be placed in delay slots Only instructions that satisfy the following conditions can be executed in delay slots: • 1-cycle instruction • Not a branch instruction • Instruction that does not affect operations even if the order of execution is changed CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 89 CHAPTER 3 CPU 3.10 MB91625 Series ■ Step trace trap No step trace trap occurs between execution of a branch instruction with a delay slot and the delay slot. ■ Interrupts No interrupt is accepted between execution of a branch instruction with a delay slot and the delay slot. ■ Undefined instruction exception If the instruction except for BNO:D instruction in a delay slot is undefined, no undefined instruction exception occurs. In such cases, the undefined instruction operates as the NOP instruction. <Note> Do not place an undefined instruction in a delay slot of BNO:D instruction. 3.10.2 Operation without Delay Slots ■ Instructions The following instruction performs branch operations without delay slots: JMP @Ri / CALL label12 / CALL @Ri / RET BRA label9 / BNO label9 / BEQ label9 / BNE label9 BC label9 / BNC label9 / BN label9 / BP label9 BV label9 / BNV label9 / BLT label9 / BGE label9 BLE label9 / BGT label9 / BLS label9 / BHI label9 ■ Explanation of operation Instructions are executed in the order they are listed. No instruction that is coded immediately following a branch instruction is executed before branching. Example: ; Order of instructions ADD R1, R2 ; BRA LABEL ; Branch instruction (without a delay slot) MOV R2, R3 ; Not executed R3, @R4 ; Branch destination ... LABEL ST The number of execution cycles of a branch instruction without a delay slot is 2 cycles if there is branching and 1 cycle if there is no branching. Such operation increases the instruction code efficiency compared with that of branch instructions with delay slots in which NOP is clearly written because appropriate instructions cannot be placed in the delay slots. If valid instructions can be placed in delay slots, select operation with delay slots; otherwise, select operation without delay slots. Doing so can balance execution speed with code efficiency. 90 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 3.11 EIT (Exception, Interrupt, Trap) EIT stands for Exception, Interrupt, and Trap. It indicates that the event that occurred results in suspension of execution of the current program, and the execution of another program. An exception is an event that occurs in connection with the context being executed. The processing is reexecuted beginning with the instruction that causes an exception. An interrupt is an event that occurs independently of the context being executed. The source of events is hardware. A trap is an event that occurs in connection with the context being executed. Some traps occur as instructed in programs such as a system call. The instruction following the instruction that generates a trap is reexecuted first. ■ Features 3.11.1 • Multi-EIT support • Level mask function for interrupts (A user can use 15 levels.) • Trap instructions (INT/INTE) • EIT for emulator activation (hardware/software) EIT Sources EIT sources include the following: 3.11.2 • Reset • User interrupt (peripheral functions, external interrupts) • Delay interrupt • Undefined instruction exception • Trap instruction (INT) • Trap instruction (INTE) • Step trace trap Return from EIT The return from each EIT is through the RETI instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 91 CHAPTER 3 CPU 3.11 3.11.3 MB91625 Series Interrupt Level The interrupt levels are 0 to 31, and they are controlled in units of 5 bits. Table 3.11-1 lists the assignment of each level. Table 3.11-1 Interrupt level assignment table Level Interrupt Type Binary number Decimal number 00000 0 (Reserved for system) ... ... ... ... ... ... 00011 3 (Reserved for system) 00100 4 INTE instruction Step trace trap 00101 5 (Reserved for system) ... ... ... ... ... ... 01100 14 (Reserved for system) 01101 15 (Reserved for system) 10000 16 Interrupt request 10001 17 Interrupt request ... ... ... ... ... ... 11110 30 Interrupt request 11111 31 - Remarks If the original value of the interrupt level mask register (ILM) is in a range of 16 to 31, no value in this range can be specified for the interrupt level mask register (ILM) from the program. When the interrupt level mask register (ILM) is set, user interrupts must be disabled. If the interrupt control register (ICR) is set, interrupts are disabled. The operations are enabled only if the level is in a range of 16 to 31. The interrupt level does not affect undefined instruction exceptions and the INT instruction. It does not change the interrupt level mask register (ILM) either. 92 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 3.11.4 I Flag This flag specifies whether interrupts are enabled or disabled. It is provided as bit4 of the condition code register (CCR) in the program status register (PS). I Explanation 0 The bit is automatically cleared to "0" when the INT instruction is executed. (However, the value that is saved to the stack is that immediately before the bit is cleared.) 1 The mask processing of user interrupt requests is controlled with the value retained by the interrupt level mask register (ILM). <Note> After an instruction changes the value of the I flag, interrupt requests can be accepted beginning from the instruction after the next instruction. Therefore, to operate interrupts properly, NOP must be placed after the instruction that changes the I flag value. • Enabling interrupts (I flag = 1) Instruction execution ↓ • I flag Interrupts ORCCR #set_iflag 0 Disabled NOP 1 Disabled Instruction A 1 Enabled I flag Interrupts ANDCCR #clear_iflag 1 Enabled NOP 0 Enabled Instruction A 0 Disabled Disabling interrupts (I flag = 0) Instruction execution ↓ CM71-10151-2E ↑ Starts enabling interrupts FUJITSU MICROELECTRONICS LIMITED ↑ Starts disabling interrupts 93 CHAPTER 3 CPU 3.11 3.11.5 MB91625 Series Interrupt Level Mask Register (ILM) This register retains the interrupt level mask value. The register is provided as bit20 to bit16 of the program status register (PS). An interrupt request that is input to a CPU in the FR80 family CPUs is accepted only if the corresponding interrupt level is higher than the level specified by the interrupt level mask register (ILM). The highest level is "0" (00000), and the lowest is "31" (11111). A limited range of values can be set from programs. If the original value is in a range of 16 to 31, a value ranging from 16 to 31 can be specified as a new value. If a value ranging from 0 to 15 is set for an instruction, (specified-value + 16) is transferred when the instruction is executed. If the original value is in a range of 0 to 15, any value ranging from 0 to 31 can be specified. Use the STILM instruction for this setting. <Note> After an instruction changes the value of the interrupt level mask register (ILM), interrupt requests can be accepted beginning from the instruction after the next instruction. Therefore, to operate interrupts properly, NOP must be placed after the instruction that changes the interrupt level mask register (ILM). ILM Instruction execution ↓ 3.11.6 Interrupt Accepted SETILM #set_ILM_B A A NOP B A Instruction C B B ↑ Instruction D B B Starts enabling ILM=B. Level Mask for Interrupts When an interrupt request is generated, the interrupt level of the interrupt source is compared with the level mask value retained by the interrupt level mask register (ILM). Then, if the following condition is satisfied, the source is masked and the request is not accepted: Interrupt level of source ≥ Level mask value 94 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 3.11.7 Interrupt Control Register (ICR) See "CHAPTER 10 Interrupt Controller". 3.11.8 System Stack Pointer (SSP) This pointer indicates the stack used for saving or restoring data, when EIT has been received or the return operation is performed. Figure 3.11-1 shows the bit configuration of the system stack pointer (SSP). Figure 3.11-1 Bit configuration of the system stack pointer (SSP) bit 31 0 Initial value 0000 0000H "8" is subtracted during EIT processing, and "8" is added at the time of return from EIT with the RETI instruction executed. The initial value following a reset is "0000 0000H". This pointer operates as general-purpose register R15 when the S flag of the condition code register (CCR) is "0". 3.11.9 Interrupt Stack The interrupt stack is the area specified by the system stack pointer (SSP). It saves and restores the values of the program counter (PC) and the program status register (PS). After an interrupt, the value of the program counter (PC) is stored in the address specified by the system stack pointer (SSP), and the value of the program status register (PS) is stored in the address specified by the system stack pointer (SSP) plus 4. Figure 3.11-2 shows the interrupt stack. Figure 3.11-2 Interrupt stack Before an interrupt SSP 8000 0000H After an interrupt SSP Memory 7FFF FFF8H Memory 8000 0000H 8000 0000H 7FFF FFFCH 7FFF FFFCH PS 7FFF FFF8H 7FFF FFF8H PC CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 95 CHAPTER 3 CPU 3.11 3.11.10 MB91625 Series Table Base Register (TBR) This register indicates the start address of the vector table used for EIT processing. Figure 3.11-3 shows the bit configuration of the table base register (TBR). Figure 3.11-3 Bit configuration of the table base register (TBR) bit 31 0 Initial value 000F FC00H A vector address is the table base register (TBR) value plus the offset value assigned to each EIT source. The initial value following a reset is "000F FC00H". 3.11.11 EIT Vector Table The vector area for EIT processing is the 1-KB area from the address specified by the table base register (TBR). The size of 1 vector is 4 bytes, and the relationship between interrupt vector numbers and vector addresses is expressed as follows: vctadr = TBR + vctofs = TBR + (0x3FC - 4 × vct) vctadr: Vector address vctofs: Vector offset vct: Interrupt vector number TBR: Table base register The lowest 2 bits of the addition result are always handled as "00". The initial area of the vector table following a reset is the area from 000F FC00H to 000F FFFFH. Specific functions are assigned to part of the vectors. 96 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 3.11.12 Multi-EIT Processing If multiple EIT sources occur at one time, the CPU selectively selects and accepts 1 EIT source, executes the EIT sequence, detects EIT sources again, and then repeats these actions. When no more detected EIT sources can be accepted, the CPU executes the handler instruction of the last EIT source accepted. Therefore, if multiple EIT sources occur at one time, the sequence in which the handler of each source is executed depends on the following: 1. Priority in which EIT sources are accepted 2. The mask applied to other sources after a source is accepted The sequence of execution depends on the above 2 elements. The priority in which EIT sources are accepted is the order of selection of the source whose EIT sequence will be executed. In the EIT sequence, the program status register (PS) and the program counter (PC) are saved, the program counter (PC) is updated, and the other sources are masked as required. The handler of a source accepted earlier is not necessarily executed earlier. Table 3.11-2 outlines the priority in which EIT sources are accepted. Table 3.11-2 Priority in which EIT sources are accepted and masking of other sources Priority of Acceptance Source Masking of Other Sources ILM 1 Reset The other sources are abandoned. 15 2 Other than undefined instructions All sources of lower priority - 3 INT instruction I flag = 0 - 4 INTE instruction All sources of lower priority 4 5 User interrupt ILM = Level of accepted source ICR 6 Step trace trap All sources of lower priority 4 With additional consideration given to the masking of other sources after an EIT source is accepted, the sequence of execution of the handlers of EIT sources that occur at one time is as shown below. Table 3.11-3 lists the sequence of execution. Table 3.11-3 Sequence of EIT handler execution Priority of Acceptance CM71-10151-2E Source 1 Reset 2 Other than undefined instructions 3 INTE instruction 4 Step trace trap 5 INT instruction 6 User interrupt FUJITSU MICROELECTRONICS LIMITED 97 CHAPTER 3 CPU 3.11 MB91625 Series Figure 3.11-4 shows multi-EIT processing. Figure 3.11-4 Multi-EIT processing Main routine INTE instruction handler INT instruction handler Priority Executed first (High) INT instruction execution (Low) INTE instruction execution 3.11.13 Operation In the explanations in this section, the PC of the transfer source indicates the address of the instruction that detects each EIT source. "Next instruction address" indicates the value corresponding to the case where each of the instructions below that detects EIT satisfies the respective condition shown: • For LDI:32 instruction: PC + 6 • For LDI:20 instruction: PC + 4 • For other instructions: PC + 2 ■ User interrupt operation The sequence in which a generated user interrupt request is determined as accepted or not is shown below. User interrupt requests are generated from peripheral functions, and an interrupt level is set for every interrupt request. ● Acceptance of interrupt requests 1. The levels of interrupt requests generated simultaneously are compared, and the interrupt with the highest level (with the lowest numerical value) is selected. The value retained by the corresponding interrupt control register (ICR) is used for this comparison. 2. If multiple interrupt requests generated at one time have the same interrupt level, the interrupt request with the lowest interrupt number is selected. 3. An interrupt request with an interrupt level greater than or equal to the level mask value is masked and not accepted. If the level mask value is greater than the interrupt level, go to 4. 98 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 4. In cases where the selected interrupt request can be masked, if the I flag is "0", the interrupt request is masked and not accepted. If the I flag is "1", the interrupt request is accepted. Under the above conditions, the interrupt request will be accepted when one instruction processing is completed. When an instruction that changes the I flag or interrupt level mask register (ILM) is executed, EIT control with the new acceptance condition becomes effective after 2 instructions. If an EIT request is detected at the same time that a user interrupt request is accepted, the CPU operates as follows using the interrupt number corresponding to the accepted interrupt request. * The parentheses () in "● Operation" below indicate the address that a register points to. ● Operation 1 (TBR + vector offset of the accepted interrupt request) → TMP 2 SSP - 4 → SSP 3 PS → (SSP) 4 SSP - 4 → SSP 5 Next instruction address → (SSP) 6 Interrupt level of the accepted request → ILM 7 "0" → S flag 8 TMP → PC After the interrupt sequence is completed, detection of any new EIT is performed before the first instruction of the handler is executed. If any EIT that occurred can be accepted at this point, the CPU switches to the EIT processing sequence. 3.11.14 INT Instruction Operation The INT #u8 instruction generates a trap in software. It generates a trap with the interrupt number specified in the operand. ● Operation CM71-10151-2E 1 (TBR + 0x3FC - 4 × u8) → TMP 2 SSP - 4 → SSP 3 PS → (SSP) 4 SSP - 4 → SSP 5 PC + 2 → (SSP) 6 "0" → I flag 7 "0" → S flag 8 TMP → PC FUJITSU MICROELECTRONICS LIMITED 99 CHAPTER 3 CPU 3.11 3.11.15 MB91625 Series INTE Instruction Operation The INTE instruction generates a trap in software for debugging. ● Operation 3.11.16 1 (TBR + 0x3D8) → TMP 2 SSP - 4 → SSP 3 PS → (SSP) 4 SSP - 4 → SSP 5 PC + 2 → (SSP) 6 "00100B" → ILM 7 "0" → S flag 8 TMP → PC Step Trace Trap Operation The step trace trap is a trap for debugging, and it is generated for each single instruction execution by setting the T flag of the program status register (PS). No step trace trap is generated immediately after execution of a branch instruction during execution of a delay branch instruction. It is generated after the instruction in the delay slot is executed. ● Step trace trap detection conditions 1. T flag of the program status register (PS) = 1 2. The instruction being executed is not a delay branch instruction. 3. The CPU is in user mode. If the above conditions are satisfied, a break is set when one instruction operation processing is completed. ● Operation 1 (TBR + 0x3C4) → TMP 2 SSP - 4 → SSP 3 PS → (SSP) 4 SSP - 4 → SSP 5 Next instruction address → (SSP) 6 "00100B" → ILM 7 "0" → S flag 8 TMP → PC If the T flag = 1, user interrupts are disabled. 100 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 3 CPU 3.11 MB91625 Series 3.11.17 Undefined Instruction Exception Operation When the instruction being decoded is detected as being undefined, an undefined instruction exception is generated. ● Undefined instruction exception detection conditions 1. The instruction being decoded is detected as being undefined. 2. The instruction is not in a delay slot (i.e., it does not immediately follow a delay branch instruction). If the above conditions are satisfied, an undefined instruction exception is generated and a break is set. ● Operation 1 (TBR + 0x3C4) → TMP 2 SSP - 4 → SSP 3 PS → (SSP) 4 SSP - 4 → SSP 5 PC → (SSP) 6 "0" → S flag 7 TMP → PC The address of the instruction that detects an undefined instruction exception is saved as the program counter (PC). 3.11.18 RETI Instruction Operation The RETI is an instruction to return from the EIT processing routine. ● Operation 1 (R15) → PC 2 R15 + 4 → R15 3 (R15) → PS 4 R15 + 4 → R15 The S flag must be "0" when the RETI instruction is executed. 3.11.19 Delay Slots and EIT The delay slots of branch instructions have the following restrictions concerning EIT. ● Interrupts, traps No interrupt or trap occurs between execution of a branch instruction with a delay slot and the delay slot. ● Exceptions If the instruction in a delay slot is undefined, no undefined instruction exception occurs. In such cases, the undefined instruction operates as the NOP instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 101 CHAPTER 3 CPU 3.11 102 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts This chapter explains the clock generating parts that generate the source clock (SRCCLK), which is the source of all internal clocks in this device. 4.1 4.2 4.3 4.4 4.5 CM71-10151-2E Overview Configuration Pins Registers Explanation of Operations FUJITSU MICROELECTRONICS LIMITED 103 CHAPTER 4 Clock Generating Parts 4.1 4.1 MB91625 Series Overview The source clock (SRCCLK) is generated as the source of internal clocks used in operating this device. This section explains generation and oscillation control of the source clock (SRCCLK) and selection of a clock as the source clock (SRCCLK). ■ Overview This device operates with various internal clocks. The various internal clocks are generated by dividing the source clock (SRCCLK). The following 3 clocks can be selected for the source clock (SRCCLK): • Main clock (MCLK) • PLL clock (PLLCLK) • Sub clock (SBCLK) The clock generating parts control the following: • • • • Main clock (MCLK) generation - Controls the oscillation of the main clock (MCLK). - Sets the oscillation stabilization wait time of the main clock (MCLK). - Controls the main timer or generation of main timer interrupt requests. Sub clock (SBCLK) generation - Controls the oscillation of the sub clock (SBCLK). - Sets the oscillation stabilization wait time of the sub clock (SBCLK). - Controls the sub timer or generation of sub timer interrupt requests. PLL clock (PLLCLK) generation - Controls the oscillation of the PLL clock (PLLCLK). - Sets the oscillation stabilization wait time of the PLL clock (PLLCLK). - Sets the PLL multiple rate (the main clock (MCLK) multiple rate for generating the PLL clock (PLLCLK)). The multiple rate can be set only for the main clock (MCLK), but not for the subclock (SBCLK). Source clock (SRCCLK) selection Selects one of 3 clocks for use as the source clock (SRCCLK). 104 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.2 MB91625 Series 4.2 Configuration The clock generating parts consist of the clock generating parts themselves and the source clock (SRCCLK) selection block. 4.2.1 Clock Generating Parts There are 3 clock generating parts. Any of the clocks generated by the clock generating parts can be selected for the source clock (SRCCLK). ■ Main clock (MCLK) generating part This part uses inputs from the X0 pin and X1 pin (main oscillator) to generate the main clock (MCLK). The main clock (MCLK) is used to generate the PLL clock (PLLCLK). Figure 4.2-1 shows a block diagram of the main clock (MCLK) generating part. Figure 4.2-1 Block diagram of the main clock (MCLK) generating part Main clock (MCLK) generating part MTE MTC MOSW MTS MTIE Main timer interrupt request Main timer MTIF X1 Main clock ready flag MCRDY MCEN X0 • Main clock (MCLK) Main timer The main timer operates with the main clock (MCLK). For details, see "CHAPTER 6 Main Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 105 CHAPTER 4 Clock Generating Parts 4.2 MB91625 Series ■ PLL clock (PLLCLK) generating part This part multiplies the main clock (MCLK) to generate the PLL clock (PLLCLK). Figure 4.2-2 shows a block diagram of the PLL clock (PLLCLK) generating part. Figure 4.2-2 Block diagram of the PLL clock (PLLCLK) generating part PLL clock (PLLCLK) generating part PLL macro oscillation clock PLL macro PLL input clock PLL input clock divider (divides by value from 1 to 16) Main clock (MCLK) PLL oscillation clock divider (divides by value from 1 to 4) PLL clock (PLLCLK) PLL feedback clock PDS ODS PLL feedback clock divider (multiplies by value from 1 to 16) PTS PCEN PCRDY Main timer • PMS PLL clock ready flag PLL Clock multiplication circuit • PLL input clock divider • PLL feedback clock divider This divider divides the main clock (MCLK) to generate the PLL input clock. This divider divides the PLL clock (PLLCLK) generated by dividing the PLL macro oscillation clock in order to generate the PLL feedback clock. • PLL macro oscillation clock divider This divider divides the PLL macro oscillation clock to generate the PLL clock (PLLCLK). 106 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.2 MB91625 Series ■ Sub clock (SBCLK) generating part This part uses inputs from the X0A pin and X1A pin (sub oscillator) to generate the sub clock (SBCLK). The sub clock (SBCLK) is the oscillation output as is. Figure 4.2-3 shows a block diagram of the sub clock (SBCLK) generating part. Figure 4.2-3 Block diagram of the sub clock (SBCLK) generating part Sub clock (SBCLK) generating part STE STC SOSW STS STIE Sub timer interrupt Sub timer Request STIF X1A Sub clock ready flag SCRDY SCEN X0A • Sub clock (SBCLK) Sub timer The sub timer operates with the sub clock (SBCLK). For details, see "CHAPTER 7 Sub Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 107 CHAPTER 4 Clock Generating Parts 4.2 4.2.2 MB91625 Series Source Clock (SRCCLK) Selection Block This section explains selection of the source clock (SRCCLK). The source clock (SRCCLK) is selected from the following 3 clock sources: • Main clock (MCLK) divided by 2 • PLL clock (PLLCLK) • Sub clock (SBCLK) When an initialization reset (INIT) is generated, the settings of the source clock (SRCCLK) are initialized, and the main clock (MCLK) divided by 2 is set for the source clock (SRCCLK). Change it to an arbitrary source clock (SRCCLK) with the setting of the clock source select register (CSELR) after the start of program operation. ■ Block diagram of the source clock (SRCCLK) selection block Figure 4.2-4 shows a block diagram of the source clock (SRCCLK) selection block. Figure 4.2-4 Block diagram of the source clock (SRCCLK) selection block Source clock (SRCCLK) selection block Main clock (MCLK) Main clock divider (divides by 2) Source clock Sub clock (SBCLK) SRCCLK PLL clock (PLLCLK) CKS [0] • CKS [1] Main clock divider (divides by 2) The divider divides the main clock (MCLK) by 2 and sets the resultant value for the source clock (SRCCLK). • CKS1 and CKS0 bits These bits are the source clock (SRCCLK) selection bits in the clock source select register (CSELR). 108 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.3 MB91625 Series 4.3 Pins This section explains the pins of the clock generating parts. ■ Overview • X0 and X1 pins These pins are used to generate the main clock (MCLK). • X0A and X1A pins These pins are used to generate the sub clock (SBCLK). They are used to connect the oscillator to an external unit. The pins are multiplexed pins. For details of using the X0A and X1A pins of the sub clock (SBCLK), see "2.4 Setting Method for Pins". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 109 CHAPTER 4 Clock Generating Parts 4.4 4.4 MB91625 Series Registers This section explains the configuration and functions of registers of the clock generating parts. ■ Registers of the clock generating parts Table 4.4-1 lists the registers of the clock generating parts. Table 4.4-1 Registers of the clock generating parts Abbreviated Register Name 110 Register Name Reference CSELR Clock source select register 4.4.1 CMONR Clock source monitor register 4.4.2 CSTBR Clock stabilization time select register 4.4.3 PLLCR PLL configuration register 4.4.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series 4.4.1 Clock Source Select Register (CSELR) This register controls the clock source and selects the source clock (SRCCLK). Figure 4.4-1 shows the bit configuration of the clock source select register (CSELR). Figure 4.4-1 Bit configuration of the clock source select register (CSELR) bit 7 6 5 4 3 2 1 0 SCEN PCEN MCEN Reserved Reserved Reserved CKS1 CKS0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value (at INIT) 0 0 1 0 0 0 0 0 Initial value (at RST) * * * 0 0 0 * * Attribute R/W: Read/Write *: Uninitialized bit <Notes> • When this register is read, the actual setting value is not necessarily read. To verify that the value specified for this register has actually been made effective, read the clock source monitor register (CMONR). • Before changing this register, verify that the value specified for this register is the same as the value of the clock source monitor register (CMONR). • Writing of this register is ignored during switching of the clocks (CKS1, CKS0 ≠ CKM1, CKM0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 111 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit7]: SCEN (Sub clock oscillation enable bit) This bit controls the oscillation of the sub clock (SBCLK). Written Value Explanation Remarks 0 The oscillation of the sub clock (SBCLK) is stopped. The X0A or X1A pin can be used as a port (PK0, PK1). 1 The sub clock (SBCLK) starts oscillating. The X0A and X1A pins are used to generate the sub clock (SBCLK). <Notes> • If the sub clock (SBCLK) is selected with the CKS1 and CKS0 bits (CKS1, CKS0=11) as the source clock (SRCCLK), this bit cannot be changed. • The sub timer is cleared when "0" is written to the bit. • In stop mode, the oscillation of the sub clock (SBCLK) is stopped regardless of the value of the bit. [bit6]: PCEN (PLL clock oscillation enable bit) This bit controls the oscillation of the PLL clock (PLLCLK). Written Value Explanation 0 The oscillation of the PLL clock (PLLCLK) is stopped. 1 The PLL clock (PLLCLK) starts oscillating. <Notes> • Write "0" to this bit to stop the oscillation of the PLL clock (PLLCLK) before entering stop mode. • The bit cannot be changed under any of the following conditions: - When the PLL clock (PLLCLK) is selected with the CKS1 and CKS0 bits (CKS1, CKS0 = 10) as the source clock (SRCCLK) - When the oscillation of the main clock (MCLK) is stopped, or the oscillation stabilization wait time is in effect (MCRDY bit = 0 in the clock source monitor register (CMONR)) • This bit is changed to "0" when the MCEN bit (MCEN = 0) is specified to stop the oscillation of the main clock (MCLK). • Do not change this bit from "0" to "1" while the main timer is being cleared (MTC bit = 1 in the main timer control register (MTMCR)). • If this bit is changed from "0" to "1" to enable the oscillation of the PLL clock (PLLCLK), the main timer is cleared. In such cases, "1" is read from the MTC bit in the main timer control register (MTMCR). 112 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit5]: MCEN (Main clock oscillation enable bit) This bit controls the oscillation of the main clock (MCLK). Written Value Explanation 0 The oscillation of the main clock (MCLK) is stopped. 1 The main clock (MCLK) starts oscillating. <Notes> • If any of the following is selected with the CKS1 or CKS0 bit as the source clock (SRCCLK), this bit cannot be changed. - The main clock (MCLK) is selected (CKS1, CKS0 = 00 or 01). - The PLL clock (PLLCLK) is selected (CKS1, CKS0 = 10). • The main timer is cleared when "0" is written to this bit. • In stop mode, the oscillation of the main clock (MCLK) is stopped regardless of the value of the bit. [bit4 to bit2]: Reserved bits In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. [bit1, bit0]: CKS1, CKS0 (Source clock select bits) These bits select the source clock (SRCCLK). CKS1 CKS0 Explanation 0 0 0 1 1 0 PLL clock (PLLCLK) 1 1 Sub clock (SBCLK) Main clock (MCLK) divided by 2 A clock whose oscillation is stopped or that has entered the oscillation stabilization wait time cannot be selected as the source clock (SRCCLK). Furthermore, no switching from the PLL clock (PLLCLK) to the sub clock (SBCLK) or from the sub clock (SBCLK) to the PLL clock (PLLCLK) is possible. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 113 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series Table 4.4-2 lists the conditions for changes of this bit. Table 4.4-2 CKS1 and CKS0 bit change conditions Value before Change CKS1 CKS0 0 0 0 1 1 1 0 1 Changeable Value [CKS1:CKS0] Change Condition Bit Clock Source Monitor Register (CMONR) 00, 01 MCRDY = 1 10 PCRDY = 1 00, 01 MCRDY = 1 11 SCRDY = 1 00 MCRDY = 1 10 PCRDY = 1 01 MCRDY = 1 11 SCRDY = 1 Unchangeable Value [CKS1:CKS0] 11 10 01, 11 00, 10 Do not write the unchangeable values listed in Table 4.4-2. For the procedures for switching the source clock (SRCCLK), see "4.5.2 Switching the Source Clock (SRCCLK)". 114 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series 4.4.2 Clock Source Monitor Register (CMONR) This register displays the clock source and state of the source clock (SRCCLK). The value specified for the clock source select register (CSELR) can be verified by reading this register to verify whether it is actually effective. Figure 4.4-2 shows the bit configuration of the clock source monitor register (CMONR). Figure 4.4-2 Bit configuration of the clock source monitor register (CMONR) bit 7 6 5 4 3 2 1 0 SCRDY PCRDY MCRDY Reserved Reserved Reserved CKM1 CKM0 Attribute R R R R R R R R Initial value (at INIT) 0 0 1 0 0 0 0 0 Initial value (at RST) * * * 0 0 0 * * R: Read only *: Uninitialized bit <Notes> • When changing a set value of the clock source select register (CSELR), be sure to read this register and verify that the read value is the same as the set value of the clock source select register (CSELR). • Do not change the clock source select register (CSELR) unless the set value of the clock source select register (CSELR) matches the register value. [bit7]: SCRDY (Sub clock ready bit) This bit displays the sub clock (SBCLK) state. Read Value Explanation 0 The oscillation is stopped, or the oscillation stabilization wait time is in effect. 1 The oscillation stabilization is in effect. This clock can be used as the source clock (SRCCLK). <Notes> • If this bit is "0", the sub clock (SBCLK) cannot be selected as the source clock (SRCCLK). • After the SCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this bit may be read as having a value of "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 115 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit6]: PCRDY (PLL clock ready bit) This bit displays the PLL clock (PLLCLK) state. Read Value Explanation 0 The oscillation is stopped, or the oscillation stabilization wait time is in effect. 1 The oscillation stabilization is in effect. This clock can be used as the source clock (SRCCLK). <Notes> • If this bit is "0", the PLL clock (PLLCLK) cannot be selected as the source clock (SRCCLK). • After the PCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this bit may be read as having a value of "1". [bit5]: MCRDY (Main clock ready bit) This bit displays the main clock (MCLK) state. Read Value Explanation 0 The oscillation is stopped, or the oscillation stabilization wait time is in effect. 1 The oscillation stabilization is in effect. This clock can be used as the source clock (SRCCLK). <Notes> • If this bit is "0", neither the main clock (MCLK) nor the PLL clock (PLLCLK) can be selected as the source clock (SRCCLK). • After the MCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this bit may be read as having a value of "1". [bit4 to bit2]: Reserved bits In case of reading 116 "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit1, bit0]: CKM1, CKM0 (Source clock display bits) These bits display the clock selected as the source clock (SRCCLK). CM71-10151-2E CKM1 CKM0 Explanation 0 0 0 1 1 0 The PLL clock (PLLCLK) is selected. 1 1 The sub clock (SBCLK) is selected. The main clock (MCLK) divided by 2 is selected. FUJITSU MICROELECTRONICS LIMITED 117 CHAPTER 4 Clock Generating Parts 4.4 4.4.3 MB91625 Series Clock Stabilization Time Select Register (CSTBR) This register sets the oscillation stabilization wait time of the clock source. The oscillation stabilization wait time set in this register is used under the following conditions with the ready bit being "1" for the relevant clock: • When returning from stop mode or watch mode • When the main oscillation is stopped and an initialize reset (INIT) is generated • When clock oscillation is enabled after being stopped The ready bits are as follows: - Sub clock: SCRDY bit - PLL clock: PCRDY bit - Main clock: MCRDY bit Figure 4.4-3 shows the bit configuration of the clock stabilization select register (CSTBR). Figure 4.4-3 Bit configuration of the clock stabilization time select register (CSTBR) bit 7 6 5 4 3 2 1 0 Reserved SOSW2 SOSW1 SOSW0 MOSW3 MOSW2 MOSW1 MOSW0 R/W R/W R/W R/W R/W R/W R/W R/W INIT pin = "L" level 0 0 0 0 0 0 0 0 Initial value (at INIT) 0 0 0 0 * * * * Initial value (at RST) 0 * * * * * * * Attribute R/W: Read/Write *: Uninitialized bit <Note> When the main oscillation is stopped and an initialize reset (INIT) is generated the main oscillation stabilization wait time after operation is restarted is the initial value of this register. [bit7]: Reserved bit 118 In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit6 to bit4]: SOSW2 to SOSW0 (Sub clock oscillation stabilization wait select bits) These bits select the oscillation stabilization wait time of the sub clock (SBCLK). SOSW2 SOSW1 SOSW0 Sub Clock (SBCLK) Oscillation Stabilization Wait Time At 32.768 kHz 0 0 0 28 × Sub clock (SBCLK) period About 7.8 ms 0 0 1 29 × Sub clock (SBCLK) period About 15.6 ms 0 1 0 210 × Sub clock (SBCLK) period About 31.3 ms 0 1 1 211 × Sub clock (SBCLK) period 62.5 ms 1 0 0 212 × Sub clock (SBCLK) period 125.0 ms 1 0 1 213 × Sub clock (SBCLK) period 250.0 ms 1 1 0 214 × Sub clock (SBCLK) period 500.0 ms 1 1 1 215 × Sub clock (SBCLK) period 1s <Notes> • The times listed in the table are calculated values. Use these values only as a guide because the actual times may include some errors depending on the oscillation state. • Writing to this bit is ignored when the following conditions are satisfied (in the oscillation stabilization wait time of the sub clock (SBCLK)): - SCRDY bit = 0 in the clock source monitor register (CMONR) - SCEN bit = 1 in the clock source select register (CSELR) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 119 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit3 to bit0]: MOSW3 to MOSW0 (Main clock oscillation stabilization select bits) These bits select the oscillation stabilization wait time of the main clock (MCLK). MOSW3 MOSW2 MOSW1 MOSW0 Main Clock (MCLK) Oscillation Stabilization Wait Time At 4 MHz At 8 MHz At 48 MHz 0 0 0 0 21 × Main clock (MCLK) period 500 ns 250 ns About 42 ns 0 0 0 1 25 × Main clock (MCLK) period 8 μs 4 μs About 667 ns 0 0 1 0 26 × Main clock (MCLK) period 16 μs 8 μs About 1 μs 0 0 1 1 27 × Main clock (MCLK) period 32 μs 16 μs About 3 μs 0 1 0 0 28 × Main clock (MCLK) period 64 μs 32 μs About 5 μs 0 1 0 1 29 × Main clock (MCLK) period 128 μs 64 μs About 11 μs 0 1 1 0 210 × Main clock (MCLK) period 256 μs 128 μs About 21 μs 0 1 1 1 211 × Main clock (MCLK) period 512 μs 256 μs About 43 μs 1 0 0 0 212 × Main clock (MCLK) period About 1 ms 512 μs About 85 μs 1 0 0 1 213 × Main clock (MCLK) period About 2 ms About 1 ms About 171 μs 1 0 1 0 214 × Main clock (MCLK) period About 4 ms About 2 ms About 341 μs 1 0 1 1 215 × Main clock (MCLK) period About 8 ms About 4 ms About 683 μs 1 1 0 0 217 × Main clock (MCLK) period About 33 ms About 16 ms About 3 ms 1 1 0 1 219 × Main clock (MCLK) period About 131 ms About 66 ms About 11 ms 1 1 1 0 221 × Main clock (MCLK) period About 524 ms About 262 ms About 44 ms 1 1 1 1 223 × Main clock (MCLK) period About 2 s About 1 s About 175 ms <Notes> • The times listed in the table are calculated values. Use these values only as a guide because the actual times may include some errors depending on the oscillation state. • Specify an oscillation stabilization wait time as 25μs or longer for a product equipped with a regulator. • Writing to this bit is ignored when the following conditions are satisfied (in the oscillation stabilization wait time of the main clock (MCLK)): - MCRDY bit = 0 in the clock source monitor register (CMONR) - MCEN bit = 1 in the clock source select register (CSELR) 120 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series 4.4.4 PLL Configuration Register (PLLCR) This register sets the multiple rate for generating the PLL clock (PLLCLK) from the main clock (MCLK). For the calculation of the clock frequency and the multiple rate related to generating the PLL clock (PLLCLK), see "4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK)". Figure 4.4-4 shows the bit configuration of the PLL configuration register (PLLCR). Figure 4.4-4 Bit configuration of the PLL configuration register (PLLCR) bit 15 14 13 12 11 10 9 8 Reserved Reserved ODS1 ODS0 PMS3 PMS2 PMS1 PMS0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value (at INIT) 0 0 0 0 0 0 0 0 Initial value (at RST) 0 0 * * * * * * bit 7 6 5 4 3 2 1 0 PTS3 PTS2 PTS1 PTS0 PDS3 PDS2 PDS1 PDS0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value (at INIT) 1 1 1 1 0 0 0 0 Initial value (at RST) * * * * * * * * Attribute Attribute R/W: Read/Write *: Uninitialized bit <Note> Writing to this bit is ignored when the oscillation of the PLL clock (PLLCLK) is enabled (PCEN = 1 in the clock source select register (CSELR)). [bit15, bit14]: Reserved bits CM71-10151-2E In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED 121 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit13, bit12]: ODS1, ODS0 (PLL macro oscillation clock division rate select bits) These bits select the division rate from the PLL macro oscillation clock to the PLL clock (PLLCLK). ODS1 ODS0 Explanation 0 0 PLL clock (PLLCLK) = PLL macro oscillation clock / 1 0 1 PLL clock (PLLCLK) = PLL macro oscillation clock / 2 1 0 PLL clock (PLLCLK) = PLL macro oscillation clock / 3 1 1 PLL clock (PLLCLK) = PLL macro oscillation clock / 4 [bit11 to bit8]: PMS3 to PMS0 (PLL clock multiple rate select bits) These bits select the multiple rate from the PLL input clock to the PLL clock (PLLCLK). 122 PMS3 PMS2 PMS1 PMS0 PLL Clock (PLLCLK) Multiple Rate 0 0 0 0 PLL clock (PLLCLK) = PLL input clock × 1 0 0 0 1 PLL clock (PLLCLK) = PLL input clock × 2 0 0 1 0 PLL clock (PLLCLK) = PLL input clock × 3 0 0 1 1 PLL clock (PLLCLK) = PLL input clock × 4 0 1 0 0 PLL clock (PLLCLK) = PLL input clock × 5 0 1 0 1 PLL clock (PLLCLK) = PLL input clock × 6 0 1 1 0 PLL clock (PLLCLK) = PLL input clock × 7 0 1 1 1 PLL clock (PLLCLK) = PLL input clock × 8 1 0 0 0 PLL clock (PLLCLK) = PLL input clock × 9 1 0 0 1 PLL clock (PLLCLK) = PLL input clock × 10 1 0 1 0 PLL clock (PLLCLK) = PLL input clock × 11 1 0 1 1 PLL clock (PLLCLK) = PLL input clock × 12 1 1 0 0 PLL clock (PLLCLK) = PLL input clock × 13 1 1 0 1 PLL clock (PLLCLK) = PLL input clock × 14 1 1 1 0 PLL clock (PLLCLK) = PLL input clock × 15 1 1 1 1 PLL clock (PLLCLK) = PLL input clock × 16 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit7 to bit4]: PTS3 to PTS0 (PLL clock oscillation stabilization wait time select bits) These bits select the oscillation stabilization wait time of the PLL clock (PLLCLK). PLL Clock (PLLCLK) Oscillation Stabilization Wait Time At 4 MHz At 8 MHz At 48 MHz PTS3 PTS2 PTS1 PTS0 1 0 0 0 29 × Main clock (MCLK) period 128.0 μs 64.0 μs About 10.7 μs 1 0 0 1 210 × Main clock (MCLK) period 256.0 μs 128.0 μs About 21.3 μs 1 0 1 0 211 × Main clock (MCLK) period 512.0 μs 256.0 μs About 42.7 μs 1 0 1 1 212 × Main clock (MCLK) period About 1 ms 512.0 μs About 85.3 μs 1 1 0 0 213 × Main clock (MCLK) period About 2 ms About 1 ms About 170.7 μs 1 1 0 1 214 × Main clock (MCLK) period About 4 ms About 2 ms About 341.3 μs 1 1 1 0 215 × Main clock (MCLK) period About 8 ms About 4 ms About 682.7 μs 1 1 1 1 216 × Main clock (MCLK) period About 16.4 ms About 8 ms About 1.4 ms <Notes> • The times listed in the table are calculated values. Use these values only as a guide because the actual times may include some errors depending on the oscillation state. • Always write "1" to the PTS3 bit. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 123 CHAPTER 4 Clock Generating Parts 4.4 MB91625 Series [bit3 to bit0]: PDS3 to PDS0 (PLL input clock division select bits) These bits select the main clock (MCLK) division rate for generating the PLL input clock. 124 PDS3 PDS2 PDS1 PDS0 PLL Input Clock Division Selection 0 0 0 0 PLL input clock = Main clock (MCLK) / 1 0 0 0 1 PLL input clock = Main clock (MCLK) / 2 0 0 1 0 PLL input clock = Main clock (MCLK) / 3 0 0 1 1 PLL input clock = Main clock (MCLK) / 4 0 1 0 0 PLL input clock = Main clock (MCLK) / 5 0 1 0 1 PLL input clock = Main clock (MCLK) / 6 0 1 1 0 PLL input clock = Main clock (MCLK) / 7 0 1 1 1 PLL input clock = Main clock (MCLK) / 8 1 0 0 0 PLL input clock = Main clock (MCLK) / 9 1 0 0 1 PLL input clock = Main clock (MCLK) / 10 1 0 1 0 PLL input clock = Main clock (MCLK) / 11 1 0 1 1 PLL input clock = Main clock (MCLK) / 12 1 1 0 0 PLL input clock = Main clock (MCLK) / 13 1 1 0 1 PLL input clock = Main clock (MCLK) / 14 1 1 1 0 PLL input clock = Main clock (MCLK) / 15 1 1 1 1 PLL input clock = Main clock (MCLK) / 16 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series 4.5 Explanation of Operations This section explains the operations of the clock generating parts. This section explains the operations of each clock source and how the source clocks are switched. 4.5.1 Explanation of Clock Source Operations This section explains mainly oscillation control of the clock sources. ■ Main clock (MCLK) This clock is generated with inputs from the X0 pin and X1 pin (main oscillator). It is used to generate the PLL clock. The main clock is used in operating the main timer. (See "CHAPTER 6 Main Timer".) ● Conditions for stopping oscillation The oscillation of the main clock (MCLK) stops under any of the following conditions: • When stop mode is in effect • When the sub clock (SBCLK) is selected for the source clock (SRCCLK) and the oscillation of the main clock (MCLK) is stopped (that is, when the following conditions are satisfied): - CKS1 or CKS0 bit in the clock source select register (CSELR)= 11 - MCEN bit in the clock source select register (CSELR)= 0 Supplying of the main clock (MCLK) starts after all the above oscillation stop conditions are cleared and the oscillation stabilization wait time specified by the MOSW3 to MOSW0 bits in the clock stabilization time select register (CSTBR) has elapsed. ● Selecting the oscillation stabilization wait time Supplying of the main clock (MCLK) starts after a wait for the oscillation of the main clock to stabilize once the oscillation has been enabled. The MOSW3 to MOSW0 bits in the clock stabilization time select register (CSTBR) specify the oscillation stabilization wait time of the main clock (MCLK). Input at the "L" level to the INIT pin initializes the MOSW3 to MOSW0 bits, returning the oscillation stabilization wait time to its initial value. In such cases, the initial value is 21 × Main clock (MCLK) period. The MOSW3 to MOSW0 bits are not initialized by any other reset that occurs. <Note> Specify an oscillation stabilization wait time as 25μs or longer for products equipped with regulators. ● End of the oscillation stabilization wait time The main clock (MCLK) is supplied at the end of the oscillation stabilization wait time. Checking the following values enables you to verify whether the main clock (MCLK) has entered the oscillation stabilization wait time while operation of the main clock (MCLK) is enabled. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 125 CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series Oscillation Stabilization Wait State Display Oscillation Stabilization State Display MCRDY = 0 in the clock source monitor register (CMONR) MCRDY = 1 in the clock source monitor register (CMONR) ■ PLL clock (PLLCLK) This high-performance clock multiplies and generates the main clock (MCLK). ● Conditions for stopping oscillation The oscillation of the PLL clock (PLLCLK) stops under any of the following conditions: • When the oscillation of the main clock (MCLK) is stopped, or the oscillation stabilization wait time is in effect • When the following conditions are satisfied and a clock other than the PLL clock (PLLCLK) is selected for the source clock (SRCCLK): (PCEN bit = 0 in the clock source select register (CSELR)) - CKS1 or CKS0 bit in the clock source select register (CSELR) = a value other than 10 - PCEN bit in the clock source select register (CSELR)= 0 Supplying of the PLL clock (PLLCLK) starts after all the above oscillation stop conditions are cleared and the oscillation stabilization wait time specified by the PTS3 to PTS0 bits in the PLL configuration register (PLLCR) has elapsed. Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the PCEN bit in the clock source select register (CSELR) to "0" and stops the oscillation of the PLL clock (PLLCLK). (To start the oscillation after such initialization, set the PCEN bit in the clock source select register (CSELR) to "1".) ● Selecting an oscillation stabilization wait time Supplying of the PLL clock (PLLCLK) starts after a wait for the oscillation of the PLL clock to stabilize once the oscillation has been enabled. The PTS3 to PTS0 bits in the PLL configuration register (PLLCR) specify the oscillation stabilization wait time of the PLL clock (PLLCLK). Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the PTS3 to PTS0 bits, returning the oscillation stabilization wait time to its initial value. In such cases, the initial value is 216 × Main clock (MCLK) period. To change the oscillation stabilization wait time, set the PTS3 to PTS0 bits, and then write "1" to the PCEN bit in the clock source select register (CSELR). ● End of the oscillation stabilization wait time The PLL clock (PLLCLK) is supplied at the end of the oscillation stabilization wait time. Checking the following values enables you to verify whether the PLL clock (PLLCLK) has entered the oscillation stabilization wait time while operation of the PLL clock (PLLCLK) is enabled. Oscillation stabilization wait state display PCRDY = 0 in the clock source monitor register (CMONR) 126 Oscillation stabilization state display PCRDY = 1 in the clock source monitor register (CMONR) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series ■ Sub clock (SBCLK) This clock is generated with inputs from the X0A pin and X1A pin (sub oscillator). The sub clock (SBCLK) is the oscillation output as is. The sub clock is used in operating the sub timer (See "CHAPTER 7 Sub Timer"). ● Conditions for stopping oscillation The oscillation of the sub clock (SBCLK) stops under any of the following conditions: • When input to the INIT pin is at the "L" level • When stop mode is in effect • When any clock other than the sub clock (SBCLK) is selected for the source clock (SRCCLK) and the oscillation of the sub clock (SBCLK) is stopped (that is, when the following conditions are satisfied): • - CKS1 or CKS0 bit in the clock source select register (CSELR) = a value other than 11 - SCEN bit in the clock source select register (CSELR)= 0 The pins are set to use ports (the pins are multiplexed for the sub clock (SBCLK) generating part and the ports). Supplying of the sub clock (SBCLK) starts after all the above oscillation stop conditions are cleared and the oscillation stabilization wait time specified by the SOSW2 to SOSW0 bits in the clock stabilization time select register (CSTBR) has elapsed. Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the SCEN bit in the clock source select register (CSELR) to "0" and stops the oscillation of the sub clock (SBCLK). (To start the oscillation after such initialization, set the SCEN bit in the clock source select register (CSELR) to "1".) ● Selecting an oscillation stabilization wait time Supplying of the sub clock (SBCLK) starts after a wait for the oscillation of the sub clock to stabilize once the oscillation has been enabled. The SOSW2 to SOSW0 bits in the clock stabilization time select register (CSTBR) specify the oscillation stabilization wait time of the sub clock (SBCLK). Input at the "L" to the INIT pin or a return from an initialization reset (INIT) initializes the SOSW2 to SOSW0 bits, returning the oscillation wait time to its initial value. In such cases, the initial value is 28 × Sub clock (SBCLK) period. To change the oscillation stabilization wait time, set the SOSW2 to SOSW0 bits. ● End of the oscillation stabilization wait time The sub clock (SBCLK) is supplied at the end of the oscillation stabilization wait time. Checking the following values enables you to verify whether the sub clock (SBCLK) has entered the oscillation stabilization wait time while operation of the sub clock (SBCLK) is enabled. Oscillation stabilization wait state display SCRDY = 0 in the clock source monitor register (CMONR) CM71-10151-2E Oscillation stabilization state display SCRDY = 1 in the clock source monitor register (CMONR) FUJITSU MICROELECTRONICS LIMITED 127 CHAPTER 4 Clock Generating Parts 4.5 4.5.2 MB91625 Series Switching the Source Clock (SRCCLK) This section explains switching of the source clock (SRCCLK). ■ Overview When "L" is input to the INIT pin or an initialization reset (INIT) is generated, the settings of the source clock (SRCCLK) are initialized, and the main clock (MCLK) divided by 2 is set for the source clock (SRCCLK). The CKS1 and CKS0 bits of the clock source select register (CSELR) can be used to select the source clock (SRCCLK) from the clock sources after the start of program operation. For this change to the source clock (SRCCLK), no switch from the PLL clock (PLLCLK) to the sub clock (SBCLK) or from the sub clock (SBCLK) to the PLL clock (PLLCLK) is possible. To do so, specify the main clock (MCLK) divided by 2, and then switch it. Figure 4.5-1 shows how to switch the source clock (SRCCLK). Figure 4.5-1 How to switch the source clock (SRCCLK) Main clock (MCLK) divided by 2 PLL clock (PLLCLK) Sub clock (SBCLK) <Note> Even if the source clock (SRCCLK) is switched, the oscillation enable settings (the values of the SCEN bit, PCEN bit, and MCEN bit in the clock source select register (CSELR)) of each clock are maintained. Stop the oscillation as necessary. 128 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 4 Clock Generating Parts 4.5 ■ Procedures ● Switching from the main clock (MCLK) divided by 2 to the PLL clock (PLLCLK) To switch the source clock (SRCCLK) from the main clock (MCLK) divided by 2 to the PLL clock (PLLCLK), make settings by following the procedure below. 1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 00 or 01) of the clock source monitor register (CMONR) to verify that the main clock (MCLK) divided by 2 is selected. 2. Set the PLL multiple rate and the PLL clock (PLLCLK) oscillation stabilization wait time in the PLL configuration register (PLLCR). 3. Set the PCEN bit (PCEN=1) in the clock source select register (CSELR) to start the oscillation of the PLL clock (PLLCLK). 4. Check the PCRDY bit (PCRDY = 1) in the clock source monitor register (CMONR) to verify that the oscillation of the PLL clock (PLLCLK) has stabilized. 5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 10) in the clock source select register (CSELR) to switch the source clock (SRCCLK) to the PLL clock (PLLCLK). 6. Check the CKM1 and CKM0 bits (CKM1, CKM = 10) in the clock source monitor register (CMONR) to verify that the source clock (SRCCLK) was switched to the PLL clock (PLLCLK). <Note> If the oscillation of the PLL clock (PLLCLK) has been enabled, steps 2 to 4 can be omitted. ● Switching from the PLL clock (PLLCLK) to the main clock (MCLK) divided by 2 To switch the source clock (SRCCLK) from the PLL clock (PLLCLK) to the main clock (MCLK) divided by 2, make settings by following the procedure below. 1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 10) in the clock source monitor register (CMONR) to verify that the PLL clock (PLLCLK) is selected. 2. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 00) in the clock source select register (CSELR) to switch the source clock (SRCCLK) to the main clock (MCLK) divided by 2. 3. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 00) in the clock source monitor register (CMONR) to verify that the source clock (SRCCLK) was switched to the main clock (MCLK) divided by 2. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 129 CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series ● Switching from the main clock (MCLK) divided by 2 to the sub clock (SBCLK) To switch the source clock (SRCCLK) from the main clock (MCLK) divided by 2 to the sub clock (SBCLK), make settings by following the procedure below. 1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 01) in the clock source monitor register (CMONR) to verify that the main clock (MCLK) divided by 2 is selected. 2. Set the oscillation stabilization wait time of the sub clock (SBCLK) in the SOSW2 to SOSW0 bits in the clock stabilization time select register (CSTBR). 3. Set the SCEN bit (SCEN=1) in the clock source select register (CSELR) to start the oscillation of the sub clock (SBCLK). 4. Check the SCRDY bit (SCRDY = 1) in the clock source monitor register (CMONR) to verify that the oscillation of the sub clock (SBCLK) has stabilized. 5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 11) in the clock source select register (CSELR) to switch the source clock (SRCCLK) to the sub clock (SBCLK). 6. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 11) in the clock source monitor register (CMONR) to verify that the source clock (SRCCLK) was switched to the sub clock (SBCLK). <Note> If the oscillation of the sub clock (SBCLK) has been enabled, steps 2 to 4 can be omitted. ● Switching from the sub clock (SBCLK) to the main clock (MCLK) divided by 2 To switch the source clock (SRCCLK) from the sub clock (SBCLK) to the main clock (MCLK) divided by 2, make settings by following the procedure below. 1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 11) in the clock source monitor register (CMONR) to verify that the sub clock (SBCLK) is selected. 2. Set the oscillation stabilization wait time of the main clock (MCLK) in the MOSW2 to MOSW0 bits in the clock stabilization time select register (CSTBR). 3. Set the MCEN bit (MCEN=1) in the clock source select register (CSELR) to start the oscillation of the main clock (MCLK). 4. Check the MCRDY bit (MCRDY = 1) in the clock source monitor register (CMONR) to verify that the oscillation of the main clock (MCLK) has stabilized. 5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 01) in the clock source select register (CSELR) to switch the source clock (SRCCLK) to the main clock (MCLK). 6. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 01) in the clock source monitor register (CMONR) to verify that the source clock (CRCCLK) was switched to the main clock (MCLK). <Note> If the oscillation of the main clock (MCLK) has been enabled, steps 2 to 4 can be omitted. 130 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series 4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK) This section explains how to calculate the clock frequency and the multiple rate related to generating the PLL clock (PLLCLK). PLL input clock frequency = (Main oscillation frequency)/(Division rate set in the PDS bit in the PLL configuration register (PLLCR)) PLL multiple rate = (Division rate set in the ODS bit in the PLL configuration register (PLLCR)) × (Multiple rate set in the PMS bit in the PLL configuration register (PLLCR)) PLL macro oscillation clock frequency = (PLL input clock frequency) × PLL multiple rate PLL clock (PLLCLK) frequency = (PLL input clock frequency) × (Multiple rate set in the PMS bit in the PLL configuration register (PLLCR)) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 131 CHAPTER 4 Clock Generating Parts 4.5 MB91625 Series Table 4.5-1 lists sample settings of the PLL clock (PLLCLK). Table 4.5-1 Sample settings of the PLL clock (PLLCLK) Main Oscillation Frequency PLL Configuration Register (PLLCR) PDS3 to PDS0 ODS1, ODS0 PMS3 to PMS0 PLL Input Clock Frequency PLL Multiple Rate ODS × PMS PLL Macro Oscillation Clock Frequency PLL Clock Frequency 4 MHz 0000 00 0111 4 MHz Multiplied by 8 32 MHz 32 MHz 4 MHz 0000 00 1110 4 MHz Multiplied by 15 60 MHz 60 MHz 4.167 MHz 0000 00 0111 4.167 MHz Multiplied by 8 33 MHz 33 MHz 4 MHz 0000 00 1001 4 MHz Multiplied by 10 40 MHz 40 MHz 8 MHz 0000 00 0100 8 MHz Multiplied by 5 40 MHz 40 MHz 8 MHz 0001 00 1110 4 MHz Multiplied by 15 60 MHz 60 MHz <Note> The following conditions must be satisfied by the specified PLL input clock, PLL multiple rate, PLL macro-oscillation clock and source clock. 132 PLL Input Clock Frequency 4 to 24 MHz PLL Multiple Rate Multiplied by 2 to 15 PLL Macro Oscillation Clock Frequency 30 to 60 MHz Source Clock (when PLL clock is selected) 7.5 to 60 MHz FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part This chapter explains the clock division control part that generates internal clocks. CM71-10151-2E 5.1 5.2 5.3 Overview Internal Clocks Configuration 5.4 5.5 Registers Division Rate FUJITSU MICROELECTRONICS LIMITED 133 CHAPTER 5 Clock Division Control Part 5.1 5.1 MB91625 Series Overview Internal clocks are generated by dividing the source clock (SRCCLK) input from a clock generating part. The clock division control part divides the source clock (SRCCLK) and generates internal clocks to supply them to the CPU, bus, and/or peripheral functions. Table 5.1-1 lists the internal clocks that are generated. These clocks are collectively called internal clocks. Table 5.1-1 Internal clocks that are generated Clock Name Generation Source Clock Base clock (BCLK) Source clock (SRCCLK) divided by a value from 1 to 8 CPU clock (CCLK) Base clock (BCLK) divided by 1 (undivided) On-chip bus clock (HCLK) Base clock (BCLK) divided by 1 (undivided) Peripheral clock (PCLK) Base clock (BCLK) divided by a value from 1 to 16 For details of the source clock (SRCCLK), see "CHAPTER 4 Clock Generating Parts". 134 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part 5.2 MB91625 Series 5.2 Internal Clocks This section explains the internal clocks. ■ Base clock (BCLK) This clock is the generation source of all internal clocks. The DIVB2 to DIVB0 bits of the divide clock configuration register 0 (DIVR0) are used when this clock is generated by dividing the source clock (SRCCLK) by a value ranging from 1 to 8. The clock can decrease at once the operating frequency of the entire device. It is stopped in one of the following low-power dissipation modes: • Watch mode / main timer mode • Stop mode ■ CPU clock (CCLK) This clock is supplied to the CPU in this device and generated from the base clock (BCLK). Since it is generated without dividing the base clock (BCLK), the operating frequency is always the same as that for the base clock (BCLK). It is stopped in one of the following low-power dissipation modes: • Doze mode (during a stop time) • Sleep mode • Watch mode / main timer mode • Stop mode Clock Name CPU clock (CCLK) Typical Supply Destination CPU (instruction execution block) ■ On-chip bus clock (HCLK) This clock is supplied to the on-chip bus and each circuit connected to the on-chip bus. It is generated from the base clock (BCLK). Since it is generated without dividing the base clock (BCLK), the operating frequency is always the same as that for the base clock (BCLK). It is stopped in one of the following low-power dissipation modes: • Bus sleep mode • Watch mode / main timer mode • Stop mode Clock Name On-chip bus clock (HCLK) CM71-10151-2E Typical Supply Destination DMA controller (DMAC) FUJITSU MICROELECTRONICS LIMITED 135 CHAPTER 5 Clock Division Control Part 5.2 MB91625 Series ■ Peripheral clock (PCLK) This clock is supplied to the peripheral buses and each peripheral function connected to the buses. The DIVP3 to DIVP0 bits of divide clock configuration register 2 (DIVR2) are used when this clock is generated by dividing the base clock (BCLK) by a value ranging from 1 to 16. It is stopped in one of the following low-power dissipation modes regardless of the setting:. • Watch mode / main timer mode • Stop mode Clock Name Peripheral clock (PCLK) 136 Typical Supply Destination Peripheral bus Clock control part Reset controller Watchdog timer Interrupt controller External interrupt Delay interrupt 16-bit reload timer Each peripheral function FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part 5.3 MB91625 Series 5.3 Configuration The source clock input from a clock generating part is divided by the value specified in a register and output to a circuit. ■ Block diagram of the clock division control part Figure 5.3-1 is a block diagram of the clock division control part. Figure 5.3-1 Block diagram of the clock division control part Source clock (SRCCLK) DIVB2 to DIVB0 (divide by value from 1 to 8) Base clock (BCLK) CPU sleep CPU clock (CCLK) Bus sleep On-chip bus clock (HCLK) DIVP3 to DIVP0 (divide by value from 1 to 16) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED Peripheral clock (PCLK) 137 CHAPTER 5 Clock Division Control Part 5.4 5.4 MB91625 Series Registers This section explains the configuration and functions of registers of the clock division control part. ■ Registers of the clock division control part Table 5.4-1 lists the registers of the clock division control part. Table 5.4-1 Registers of the clock division control part Abbreviated Register Name 138 Register Name Reference DIVR0 Divide clock configuration register 0 5.4.1 DIVR2 Divide clock configuration register 2 5.4.2 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part 5.4 MB91625 Series 5.4.1 Divide Clock Configuration Register 0 (DIVR0) This register sets the source clock (SRCCLK) division rate for generating the base clock (BCLK). Figure 5.4-1 shows the bit configuration of divide clock configuration register 0 (DIVR0). Figure 5.4-1 Bit configuration of divide clock configuration register 0 (DIVR0) bit Attribute 7 6 5 4 3 2 1 0 DIVB2 DIVB1 DIVB0 Reserved Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 1 Initial value R/W: Read/Write [bit7 to bit5]: DIVB2 to DIVB0 (base clock division configuration bits) These bits set the division rate for generating the base clock (BCLK) from the source clock (SRCCLK). Since the CPU clock (CCLK) and the on-chip bus clock (HCLK) are generated without dividing the base clock (BCLK), the frequency is the same as that for the base clock (BCLK). DIVB2 DIVB1 DIVB0 Explanation 0 0 0 Divided by 1 (undivided) 0 0 1 Divided by 2 0 1 0 Divided by 3 0 1 1 Divided by 4 1 0 0 Divided by 5 1 0 1 Divided by 6 1 1 0 Divided by 7 1 1 1 Divided by 8 [bit4 to bit2]: Reserved bits CM71-10151-2E In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED 139 CHAPTER 5 Clock Division Control Part 5.4 MB91625 Series [bit1, bit0]: Reserved bits 140 In case of writing Always write "1" to this (these) bit (bits) In case of reading "1" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part 5.4 MB91625 Series 5.4.2 Divide Clock Configuration Register 2 (DIVR2) This register sets the base clock (BCLK) division rate for generating the peripheral clock (PCLK). Figure 5.4-2 shows the bit configuration of divide clock configuration register 2 (DIVR2). Figure 5.4-2 Bit configuration of divide clock configuration register 2 (DIVR2) bit 7 6 5 4 3 2 1 0 DIVP3 DIVP2 DIVP1 DIVP0 Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 1 0 0 0 0 Attribute Initial value R/W: Read/Write CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 141 CHAPTER 5 Clock Division Control Part 5.4 MB91625 Series [bit7 to bit4]: DIVP3 to DIVP0 (Peripheral clock division configuration bits) These bits set the division rate for generating the peripheral clock (PCLK) from the base clock (BCLK). DIVP3 DIVP2 DIVP1 DIVP0 Explanation 0 0 0 0 Divided by 1 (undivided) 0 0 0 1 Divided by 2 0 0 1 0 Divided by 3 0 0 1 1 Divided by 4 0 1 0 0 Divided by 5 0 1 0 1 Divided by 6 0 1 1 0 Divided by 7 0 1 1 1 Divided by 8 1 0 0 0 Divided by 9 1 0 0 1 Divided by 10 1 0 1 0 Divided by 11 1 0 1 1 Divided by 12 1 1 0 0 Divided by 13 1 1 0 1 Divided by 14 1 1 1 0 Divided by 15 1 1 1 1 Divided by 16 [bit3 to bit0]: Reserved bits 142 In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is red. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 5 Clock Division Control Part 5.5 MB91625 Series 5.5 Division Rate The clock division control part can set the division rate for each internal clock. Figure 5.5-1 shows the division rate from the source clock for each internal clock. Figure 5.5-1 Division rate from the source clock for each internal clock Source clock (SRCCLK) Divided by value from 1 to 8 Base clock (BCLK) CPU clock (CCLK) Divided by value from 1 to 16 Peripheral clock (PCLK) ■ Division rates after initialization Table 5.5-1 shows the division of internal clocks after a reset. Table 5.5-1 Division rates after a reset Clock Name CM71-10151-2E Division Rate after Initialization Base clock (BCLK) Source clock (SRCCLK) divided by 1 CPU clock (CCLK) Base clock (BCLK) divided by 1 On-chip bus clock (HCLK) Base clock (BCLK) divided by 1 Peripheral clock (PCLK) Base clock (BCLK) divided by 4 FUJITSU MICROELECTRONICS LIMITED 143 CHAPTER 5 Clock Division Control Part 5.5 MB91625 Series ■ Changing the division rate After the division rate setting is changed, the changed division rate is enabled at the next rising edge of the clock. A A B B B Clocks Setting value of register (division rate) A B Change of division rate 144 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 6 Main Timer This chapter explains the functions and operations of the main timer function. CM71-10151-2E 6.1 6.2 6.3 6.4 Overview Configuration Registers Interrupts 6.5 An Explanation of Operations and Setting Procedure Examples FUJITSU MICROELECTRONICS LIMITED 145 CHAPTER 6 Main Timer 6.1 6.1 MB91625 Series Overview The main timer operates with the main clock (MCLK). The main timer is used to generate the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). The main timer counts the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). When main clock (MCLK) oscillation is stable, the main timer can also be used as an interval timer for generating an interrupt request at regular intervals. The main timer is cleared when: • "1" is written to the MTC bit of the main timer control register (MTMCR). "1" is read from the MTC bit of the main timer control register (MTMCR) until the main timer is cleared after "1" is written to the MTC bit. • Main clock (MCLK) oscillation is stopped. (The MCEN bit of the clock source select register (CSELR) is 0.) • In stop mode • The main timer is stopped with the MTE bit (MTE = 0) of the main timer control register (MTMCR). If main timer operation is disabled, the timer is stopped during periods other than the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). 146 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 6 Main Timer 6.2 MB91625 Series 6.2 Configuration This section explains the main timer configuration. ■ Main timer block diagram For the main timer block diagram, see "■ Main clock (MCLK) generating part" in "CHAPTER 4 Clock Generating Parts". ■ Clocks Table 6.2-1 shows the clocks used by the main timer. Table 6.2-1 Clocks used by the main timer Clock Name Operation clock CM71-10151-2E Description Main clock (MCLK) FUJITSU MICROELECTRONICS LIMITED 147 CHAPTER 6 Main Timer 6.3 6.3 MB91625 Series Registers This section explains the configuration and functions of registers used by the main timer. ■ Registers of main timer Table 6.3-1 shows the registers used by the main timer. Table 6.3-1 Main timer registers Abbreviated Register Name MTMCR 148 Register Name Main timer control register FUJITSU MICROELECTRONICS LIMITED Reference 6.3.1 CM71-10151-2E CHAPTER 6 Main Timer 6.3 MB91625 Series 6.3.1 Main Timer Control Register (MTMCR) This register controls the main timer. Figure 6.3-1 shows the bit configuration of the main timer control register (MTMCR). Figure 6.3-1 Bit configuration of main timer control register (MTMCR) bit Attribute 7 6 5 4 3 2 1 0 MTIF MTIE MTC MTE MTS3 MTS2 MTS1 MTS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Initial value R/W: Read/Write <Notes> • This register can be rewritten only when the main clock (MCLK) is oscillating stably (The MCRDY bit of the clock source monitor register (CMONR) is 1). Note that the MTIE bit can be rewritten even when the MCRDY bit is "0". • Software reset must be executed when both the MTE and MTC bits are "0". For details of the software reset, see "CHAPTER 9 Reset". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 149 CHAPTER 6 Main Timer 6.3 MB91625 Series [bit7]: MTIF (main timer interrupt flag bit) This flag indicates that the main timer overflows. The main timer overflows when: • The counter has finished counting the period that is set with the MTS3 to MTS0 bits. • The oscillation stabilization wait time of the main clock (MCLK) has elapsed after the MCEN bit of the clock source select register (CSELR) was rewritten from "0" to "1". • The oscillation stabilization wait time of the main clock (MCLK) has elapsed after the system returns from stop mode. A main timer interrupt request occurs when this bit is set to "1" while the MTIE bit is "1". MTIF In case of reading In case of writing 0 No overflow occurred. This bit is cleared to "0". 1 An overflow occurred. Ignored This bit is also cleared to "0" when a DMA transfer is caused by a main timer interrupt request. <Notes> • Disabling main timer operation with the MTE bit (MTE = 0) clears the main timer. • When the MTIE bit is set to "0", this bit is not cleared even when a DMA transfer is caused by a main timer interrupt request. • After this device is reset by input of an "L" level signal from the INIT pin, an "H" level signal may be input again from the INIT pin. In this case, this bit is not changed to "1" even after the oscillation stabilization wait time of the main clock (MCLK) elapses. • If clearing the bit to "0" coincides with the occurrence of an overflow, the overflow occurrence is given priority and this bit remains "1". • When a read-modify-write instruction is used, "1" is read. [bit6]: MTIE (main timer interrupt enable bit) The MTIE bit is used to specify whether to cause a main timer interrupt request when the main timer overflows (MTIF=1). A main timer interrupt request occurs when the MTIF bit is set to "1" while this bit is "1". Written Value 150 Explanation 0 Disables generation of main timer interrupt requests. 1 Enables generation of main timer interrupt requests. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 6 Main Timer 6.3 MB91625 Series [bit5]: MTC (main timer clear bit) Clear the main timer. The operating state of the main timer can be verified by reading this bit. MTC In case of writing In case of reading 0 Ignored In normal operation 1 Clear the main timer. The main timer is being cleared. <Notes> • When a read-modify-write instruction is used, "0" is read. • Do not clear the main timer during oscillation stabilization wait time of the PLL clock (PLLCLK). • This register can be rewritten only while main clock (MCLK) oscillation is stable. Therefore, if the following conditions are satisfied, the main timer cannot be cleared even when the bit is set to "1": - Main clock (MCLK) is oscillating (the MCEN bit of the clock source select register (CSELR) is 1). - The main clock (MCLK) is in oscillation stopped/oscillation stabilization wait state (The MCRDY bit of the clock source monitor register (CMONR) is 0). • Writing "1" to this bit at the same time that the MTE bit is changed from "0" to "1" clears the main timer and then starts main timer operation. • Do not write "1" to this bit when it is "1". • As long as the MTC bit is "0", the MTIF bit may become "1". [bit4]: MTE (main timer operation enable bit) This bit enables/disables (stops) the operation of the main timer. Written Value Explanation 0 Disables (stops) the operation of the main timer. 1 Enables the operation of the main timer. <Notes> • If the operation of the main timer is disabled (stopped), the main timer is stopped during periods other than the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). • Disabling (stopping) the operation of the main timer clears the main timer. While the main timer is cleared, "1" is read from the MTC bit. As long as the MTC bit is "0", the MTIF bit may become "1". • Do not change this bit from "1" to "0" during oscillation stabilization wait time of the PLL clock (PLLCLK). • Do not write "1" to this bit when the MTC bit is "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 151 CHAPTER 6 Main Timer 6.3 MB91625 Series [bit3 to bit0]: MTS3 to MTS0 (main timer period select bits) These bits are used to select an overflow period of the main timer. The main timer overflows when it finishes counting the period specified with these bits. MTS3 MTS2 MTS1 MTS0 Overflow Period 4 MHz 8 MHz 48 MHz 1 0 0 0 29 × Main clock cycle 128.0 μs 64.0 μs About 10.7 μs 1 0 0 1 210 × Main clock cycle 256.0 μs 128.0 μs About 21.3 μs 1 0 1 0 211 × Main clock cycle 512.0 μs 256.0 μs About 42.7 μs 1 0 1 1 212 × Main clock cycle About 1 ms 512.0 μs About 85.3 μs 1 1 0 0 213 × Main clock cycle About 2 ms About 1 ms About 170.7 μs 1 1 0 1 214 × Main clock cycle About 4 ms About 2 ms About 341.3 μs 1 1 1 0 215 × Main clock cycle About 8 ms About 4 ms About 682.7 μs 1 1 1 1 216 × Main clock cycle About 16.4 ms About 8 ms About 1.4 ms Always write "1" to the MTS3 bit. <Notes> • Change the values of these bits after stopping the main timer using the MTE bit (MTE = 0). • While the MTIE bit is set to "1", a main timer interrupt request is generated when the main timer overflows. Set these bits so that the main timer overflow period exceeds 5T (T: peripheral clock (PCLK) period). 152 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 6 Main Timer 6.4 MB91625 Series 6.4 Interrupts A main timer interrupt request is generated when the main timer overflows. Table 6.4-1 outlines the interrupts that can be used with the main timer. Table 6.4-1 Interrupts of the main timer Interrupt request Main timer interrupt request Interrupt request flag Interrupt request enabled Clearing an interrupt request MTIF=1 for MTMCR MTIE=1 for MTMCR Write "0" to the MTIF bit for MTMCR MTMCR: main timer control register (MTMCR) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. • For information on the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 153 CHAPTER 6 Main Timer 6.5 6.5 MB91625 Series An Explanation of Operations and Setting Procedure Examples This section explains the operation of the main timer. Also, examples of procedures for setting the operating state are shown. 6.5.1 Main Timer Operation ■ Overview The main timer counts the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). When main clock (MCLK) oscillation is stable, the main timer can also be used as an interval timer for generating an interrupt request at regular intervals. If main timer operation is disabled with the MTE bit (MTE = 0) of the main timer control register (MTMCR), the timer is stopped during periods other than the oscillation stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK). ■ Operation The main timer operates as follows: 1. Enable the main timer operation by the MTE bit of the main timer control register (MTMCR) (MTE = 1). 2. The main timer starts counting in synchronization with the main clock (MCLK). The main timer continues counting while the MTE bit of the main timer control register (MTMCR) is "1". 3. The main timer counts up to the value set in the MTS3 to MTS0 bits of the main timer control register (MTMCR). The MTIF bit of the main timer control register (MTMCR) changes to "1". If the MTIE bit of the main timer control register (MTMCR) is "1" at this time, a main timer interrupt request is generated. To clear the main timer interrupt request, write "0" to the MTIF bit. The MTIF bit is cleared to "0". If main timer operation is disabled with the MTE bit (MTE=0) of the main timer control register (MTMCR) during main timer operation, the main timer stops counting and clears the counter value. For more information, see "■ Clearing the timer". 154 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 6 Main Timer 6.5 MB91625 Series ■ Clearing the timer The main timer is cleared when: • "1" is written to the MTC bit of the main timer control register (MTMCR). "1" is read from the MTC bit of the main timer control register (MTMCR) until the main timer is cleared after "1" is written to the MTC bit. • Main clock (MCLK) oscillation is stopped. (The MCEN bit of the clock source select register (CSELR) is 0). • In stop mode • The main timer is stopped with the MTE bit (MTE = 0) of the main timer control register (MTMCR). <Note> The main timer control register (MTMCR) can be rewritten only when the oscillation of the main clock (MCLK) is stable. Therefore, even if "1" is written to the MTC bit of the main timer control register (MTMCR) when the following conditions are satisfied, the main timer cannot be cleared: • Main clock (MCLK) oscillation is oscillating (the MCEN bit of the clock source select register (CSELR) is 1). • The main clock (MCLK) is in oscillation stopped/oscillation stabilization wait state (The MCRDY bit of the clock source monitor register (CMONR) is 0). ■ Interrupt setting procedure An example of the procedure for setting the main timer control register (MTMCR) is shown below. 1. Set the MTIE bit to disable main timer interrupts (MTIE=0). 2. Set the MTIF bit to clear the main timer interrupt flag (MTIF=0). 3. Set the MTE bit to disable main timer operation (MTE=0). 4. Read the MTC bit to verify that the main timer has been cleared (MTC=0). 5. Set the timer period in the MTS3 to MTS0 bits. 6. Set the MTIE bit to enable main timer interrupts (MTIE=1). 7. Set the MTE bit to enable main timer operation (MTE=1). When the period that is set in the MTS3 to MTS0 bits elapses, a main timer interrupt request is generated and processing moves to the interrupt processing routine. 8. Set the MTIF bit to clear the main timer interrupt flag (MTIF=0). 9. Read the MTIF bit once to complete clearing the main timer interrupt flag. Issue the RETI instruction to return to normal program processing from the interrupt processing routine. <Note> When "0" is written to the MTIF bit, the main timer interrupt flag is not cleared soon. After reading the MTIF bit once to complete clearing the flag, it can be returned by the RETI instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 155 CHAPTER 6 Main Timer 6.5 6.5.2 MB91625 Series Transition to Stop Mode Before transition to the stop mode, generation of main timer interrupt requests must be disabled. Follow the procedure below for transition to the stop mode: 1. Set the PCEN bit of the clock source select register (CSELR) to stop PLL clock (PLLCLK) oscillation (PCEN=0). 2. Set the MTIE bit of the main timer control register (MTMCR) to disable generation of main timer interrupt requests (MTIE=0). 3. Set the MTE bit of the main timer control register (MTMCR) to disable main timer operation (MTE = 0). 4. Read the MTC bit of the main timer control register (MTMCR) to verify that the main timer is not being cleared (MTC=0). 5. Set the MTIF bit of the main timer control register (MTMCR) to clear the main timer interrupt flag (MTIF=0). 6. Set the oscillation stabilization wait time of the main clock (MCLK) in the MOSW3 to MOSW0 bits of the clock stabilization time select register (CSTBR). 7. Transition to stop mode <Note> Before transition to stop mode, be sure to stop PLL clock (PLLCLK) oscillation. 156 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 7 Sub Timer This chapter explains the functions and operations of the sub timer. CM71-10151-2E 7.1 7.2 7.3 7.4 Overview Configuration Registers Interrupts 7.5 An Explanation of Operations and Setting Procedure Examples FUJITSU MICROELECTRONICS LIMITED 157 CHAPTER 7 Sub Timer 7.1 7.1 MB91625 Series Overview The sub timer operates based on the sub clock (SBCLK). It is used to generate the sub clock (SBCLK) oscillation stabilization wait time. The sub timer counts the oscillation stabilization wait time of the sub clock (SBCLK). When sub clock (SBCLK) oscillation is stable, the sub timer can also be used as an interval timer for generating an interrupt request at regular intervals. The sub timer is cleared when: • "1" is written to the STC bit of the sub timer control register (STMCR). "1" is read from the STC bit of the sub timer control register (STMCR) until the sub timer is cleared after "1" is written to the STC bit. • Sub clock (SBCLK) oscillation is stopped. (The SCEN bit of the clock source select register (CSELR) is 0.) • In stop mode • The sub timer is stopped with the STE bit (STE=0) of the sub timer control register (STMCR). If sub timer operation is disabled, the timer is stopped during periods other than the oscillation stabilization wait time of the sub clock (SBCLK). 158 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 7 Sub Timer 7.2 MB91625 Series 7.2 Configuration This section explains the sub timer configuration. ■ Sub timer block diagram For details of the sub timer block diagram, see "■ Sub clock (SBCLK) generating part" in "CHAPTER 4 Clock Generating Parts". ■ Clocks Table 7.2-1 shows the clocks used by the sub timer. Table 7.2-1 Clocks used by the sub timer Clock Name Operation clock CM71-10151-2E Description Sub clock (SBCLK) FUJITSU MICROELECTRONICS LIMITED 159 CHAPTER 7 Sub Timer 7.3 7.3 MB91625 Series Registers This section explains the configuration and functions of registers used by the sub timer. ■ Registers of sub timer The registers used by the sub timer are listed in Table 7.3-1. Table 7.3-1 Sub timer registers Abbreviated Register Name STMCR 160 Register Name Sub timer control register FUJITSU MICROELECTRONICS LIMITED Reference 7.3.1 CM71-10151-2E CHAPTER 7 Sub Timer 7.3 MB91625 Series 7.3.1 Sub Timer Control Register (STMCR) This register controls the sub timer. Figure 7.3-1 shows the bit configuration of the sub timer control register (STMCR). Figure 7.3-1 Bit configuration of sub timer control register (STMCR) bit Attribute 7 6 5 4 3 2 1 0 STIF STIE STC STE Reserved STS2 STS1 STS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 1 Initial value R/W: Read/Write <Notes> • This register can be rewritten only when the sub clock (SBCLK) is oscillating stably. (The SCRDY bit of the clock source monitor register (CMONR) is 1.) Note that the STIE bit can be rewritten even when the SCRDY bit is "0". • Software reset must be executed when both the STE and STC bits are "0". For details of the software reset, see "CHAPTER 9 Reset". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 161 CHAPTER 7 Sub Timer 7.3 MB91625 Series [bit7]: STIF (sub clock timer interrupt flag bit) This flag indicates that the sub timer caused an overflow. The sub timer overflows when: • The counter has finished counting the period that is set with the STS2 to STS0 bits. • The oscillation stabilization wait time of the sub clock (SBCLK) has elapsed after the SCEN bit of the clock source select register (CSELR) was rewritten from "0" to "1". • The oscillation stabilization wait time of the sub clock (SBCLK) has elapsed after the system returns from stop mode. A sub timer interrupt request occurs when this bit is set to "1" while the STIE bit is "1". STIF In case of reading In case of writing 0 No overflow occurred. This bit is cleared to "0". 1 An overflow occurred. Ignored This bit is also cleared to "0" when a DMA transfer is caused by a sub timer interrupt request. <Notes> • Disabling sub timer operation with the STE bit (STE = 0) clears the sub timer. • When the STIE bit is set to "0", this bit is not cleared even when a DMA transfer is caused by a sub timer interrupt request. • If clearing the bit to "0" coincides with the occurrence of an overflow, the overflow occurrence is given priority and this bit remains "1". • When a read-modify-write instruction is used, "1" is read [bit6]: STIE (sub timer interrupt enable bit) The STIE bit is used to specify whether to cause a sub timer interrupt request when the sub timer overflows (STIF=1). A sub timer interrupt request occurs when the STIF bit is set to "1" while this bit is "1". Written Value 162 Explanation 0 Disables generation of sub timer interrupt requests. 1 Enables generation of sub timer interrupt requests. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 7 Sub Timer 7.3 MB91625 Series [bit5]: STC (sub timer clear bit) This bit clears the sub timer. The operating state of the sub timer can be verified by reading this bit. STC In case of writing In case of reading 0 Ignored In normal operation 1 Clear the sub timer. The sub timer is being cleared. <Notes> • When a read-modify-write instruction is used, "0" is read. • This register can be rewritten only while sub clock (SBCLK) oscillation is stable. Therefore, if the following conditions are satisfied, the sub timer cannot be cleared even when the bit is set to "1": - Sub clock (SBCLK) is oscillating (the SCEN bit of the clock source select register (CSELR) is 1). - The sub clock (SBCLK) is in oscillation stopped/oscillation stabilization wait state. (The SCRDY bit of the clock source monitor register (CMONR) is 0.) • Writing "1" to this bit at the same time that the STE bit is changed from "0" to "1" clears the sub timer and then starts sub timer operation. • Do not attempt to write "1" to this bit when it is "1". • As long as the STC bit is "0", the STIF bit may become "1". [bit4]: STE (sub timer operation enable bit) This bit controls the sub timer operation. Written Value Explanation 0 Disables (stops) the operation of the sub timer. 1 Enables the operation of the sub timer. <Notes> • If the operation of the sub timer is disabled (stopped), the sub timer is stopped during periods other than the oscillation stabilization wait time of the sub clock (SBCLK). • Disabling (stopping) the operation of the sub timer clears the sub timer. While the sub timer is cleared, "1" is read from the STC bit. As long as the STC bit is "0", the STIF bit may become "1". • Do not write "1" to this bit when the STC bit is "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 163 CHAPTER 7 Sub Timer 7.3 MB91625 Series [bit3]: Reserved bit In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. [bit2 to bit0]: STS2 to STS0 (sub timer period select bits) These bits are used to select an overflow period of the sub timer. The sub timer overflows when it finishes counting the period specified with these bits. STS2 STS1 STS0 Overflow Period At 32768Hz 0 0 0 28 × Sub clock cycle About 7.8 ms 0 0 1 29 × Sub clock cycle About 15.6 ms 0 1 0 210 × Sub clock cycle About 31.3 ms 0 1 1 211 × Sub clock cycle 62.5 ms 1 0 0 212 × Sub clock cycle 125.0 ms 1 0 1 213 × Sub clock cycle 250.0 ms 1 1 0 214 × Sub clock cycle 500.0 ms 1 1 1 215 × Sub clock cycle 1s <Notes> • Change the values of these bits after stopping the sub timer using the STE bit (STE = 0). • While the STIE bit is set to "1", a sub timer interrupt request is generated when the sub timer overflows. Set these bits so that the sub timer overflow period is 5T (T: peripheral clock (PCLK) period) or more than that. 164 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 7 Sub Timer 7.4 MB91625 Series 7.4 Interrupts A sub timer interrupt request is generated when the sub timer overflows. Table 7.4-1 outlines the interrupts that can be used with the sub timer. Table 7.4-1 Interrupts of the sub timer Interrupt request Sub timer interrupt request Interrupt request flag STIF=1 for STMCR Interrupt request enabled STIE=1 for STMCR Clearing an interrupt request Write "0" to the STIF bit for STMCR STMCR: sub timer control register (STMCR) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For details of the interrupt level settings, see "CHAPTER 10 Interrupt Controller". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 165 CHAPTER 7 Sub Timer 7.5 7.5 MB91625 Series An Explanation of Operations and Setting Procedure Examples This section explains the operation of the sub timer. Also, examples of procedures for setting the operating state are shown. 7.5.1 Sub timer operation ■ Overview The sub timer counts the oscillation stabilization wait time of the sub clock (SBCLK). When sub clock (SBCLK) oscillation is stable, the sub timer can also be used as an interval timer for generating an interrupt request at regular intervals. If sub timer operation is disabled with the STE bit (STE = 0) of the sub timer control register (STMCR), the timer is stopped during periods other than the oscillation stabilization wait time of the sub clock (SBCLK). ■ Operation The sub timer operates as follows: 1. The STE bit of the sub timer control register (STMCR) enables (STE = 1) sub timer operation. 2. The sub timer starts counting in synchronization with the sub clock (SBCLK). The sub timer continues counting while the STE bit of the sub timer control register (STMCR) is "1". 3. The sub timer counts up to the value specified in the STS2 to STS0 bits of the sub timer control register (STMCR). The STIF bit of the sub timer control register (STMCR) changes to "1". If the STIE bit of the sub timer control register (STMCR) is "1" at this time, a sub timer interrupt request is generated. To clear the sub timer interrupt request, write "0" to the STIF bit. The STIF bit is cleared to "0". If sub timer operation is disabled with the STE bit (STE = 0) of the sub timer control register (STMCR) during sub timer operation, the sub timer stops counting and clears the counter value. For more information, see "■ Clearing the timer". 166 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 7 Sub Timer 7.5 MB91625 Series ■ Clearing the timer The sub timer is cleared when: • "1" is written to the STC bit of the sub timer control register (STMCR). "1" is read from the STC bit of the sub timer control register (STMCR) until the sub timer is cleared after "1" is written to the STC bit. • Sub clock (SBCLK) oscillation is stopped. (The SCEN bit of the clock source select register (CSELR) is 0.) • In stop mode • The sub timer is stopped with the STE bit (STE = 0) of the sub timer control register (STMCR). The sub timer is stopped for periods other than the oscillation stabilization wait time of the sub clock (SBCLK). <Note> The sub timer control register (STMCR) can be rewritten only while the oscillation of the sub clock (SBCLK) is stable. Therefore, even if "1" is written to the STC bit of the sub timer control register (STMCR) when the following conditions are satisfied, the sub timer cannot be cleared: • Sub clock (SBCLK) is oscillating. (The SCEN bit of the clock source select register (CSELR) is 1.) • The sub clock (SBCLK) is in oscillation stopped/oscillation stabilization wait state. (The SCRDY bit of the clock source monitor register (CMONR) is 0.) ■ Interrupt setting procedure An example of the procedure for setting the sub timer control register (STMCR) is shown below. 1. Set the STIE bit to disable sub timer interrupts (STIE = 0). 2. Set the STIF bit to clear the sub timer interrupt flag (STIF = 0). 3. Set the STE bit to disable sub timer operation (STE = 0). 4. Read the STC bit to verify that the sub timer is operating normally (STC=0). 5. Set the timer period in the STS2 to STS0 bits. 6. Set the STIE bit to enable sub timer interrupts (STIE = 1). 7. Set the STE bit to enable sub timer operation (STE = 1). When the period that is set in the STS2 to STS0 bits elapses, a sub timer interrupt request is generated and processing moves to the interrupt processing routine. 8. Set the STIF bit to clear the sub timer interrupt flag (STIF = 0). 9. Read the STIF bit once to complete clearing the sub timer interrupt flag. Issue the RETI instruction to return to normal program processing from the interrupt processing routine. <Note> When "0" is written to the STIF bit, the sub timer interrupt flag is not cleared soon. After reading the STIF bit once to complete clearing the flag, it can be returned by the RETI instruction. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 167 CHAPTER 7 Sub Timer 7.5 7.5.2 MB91625 Series Transition to Stop Mode, and Watch Mode Before transition to stop mode, interrupt operation by the sub timer must be disabled. Follow the procedure below for transition to the stop mode: 1. Set the PCEN bit of the clock source select register (CSELR) to stop PLL clock (PLLCLK) oscillation (PCEN=0). 2. Set the STIE bit of the sub timer control register (STMCR) to disable sub timer interrupts (STIE = 0). 3. Set the STE bit of the sub timer control register (STMCR) to disable sub timer operation (STE = 0). 4. Read the STC bit of the sub timer control register (STMCR) to confirm that the sub timer is not being cleared (STC=0). 5. Set the STIF bit of the sub timer control register (STMCR) to clear the sub timer interrupt flag (STIF = 0). 6. Set the oscillation stabilization wait time of the sub clock (SBCLK) in the SOSW2 to SOSW0 bits of the clock stabilization time select register (CSTBR). 7. Transition to stop mode <Note> Before transition to the stop mode, be sure to stop PLL clock oscillation. 168 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode This chapter explains the functions and operations of lowpower dissipation mode. 8.1 8.2 8.3 8.4 8.5 CM71-10151-2E Overview Configuration Registers An Explanation of Operations and Setting Procedure Examples Notes on Use FUJITSU MICROELECTRONICS LIMITED 169 CHAPTER 8 Low-power Dissipation Mode 8.1 8.1 MB91625 Series Overview This series can use low-power dissipation mode to reduce power dissipation. ■ Overview This series can control power dissipation in the following way. • Clock control - Clock division By changing the division ratio of each operation clock, operation frequency can be reduced. - Stop clock This allows the user to specify a specific clock to stop the clock. • Doze mode This mode intermittently operates the CPU repeatedly at a set operation rate. • Sleep mode This mode operates only peripheral functions. One of the following two modes can be selected. - CPU sleep mode This mode stops the operation of the CPU. - Bus sleep mode This mode stops the CPU and on-chip bus. • Standby mode One of the following three modes can be selected. - Main timer mode This mode stops all the operations other than the main clock oscillation. The sub clock oscillation can be specified arbitrarily. - Watch mode - Stop mode This mode stops all the operations other than the sub clock oscillation. This mode stops all operations including the oscillation of all clocks. 170 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.2 MB91625 Series 8.2 Configuration The configuration of the power dissipation controller is shown below. ■ Block diagram of power dissipation controller Figure 8.2-1 is a block diagram of the power dissipation controller. Figure 8.2-1 Block diagram of power dissipation controller RUN [3:0] RUN SLP SLP [3:0] Reload value selection circuit S 1 1 [5] [4] [3] [2] [1] [0] SLP value count end Q R CPU sleep request RUN value count end DOZE counter (6-bit down counter) Peripheral clock (PCLK) DOZE SLEEP S STBCR read Q Bus sleep request R SLVL [1] TIMER S STBCR read Q Clock stop request R Bus acknowledge STOP STBCR read S Q Oscillation stop request R Return Reset (RST) STBCR : S : R : Q : Standby mode control register (STBCR) Set Reset Output • Standby mode control register (STBCR) • Sleep rate configuration register (SLPRR) This register controls low-power dissipation mode. This register configures the operation state (RUN state) rate and sleep state rate (sleep rate) in doze mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 171 CHAPTER 8 Low-power Dissipation Mode 8.2 • MB91625 Series Reload value selection circuit A circuit for selecting to reload either the operation state (RUN state) rate or sleep state rate (Sleep rate) which has been set in the sleep rate configuration register (SLPRR). ■ Clocks Table 8.2-1 shows the clock used in the power dissipation controller. Table 8.2-1 Clock used in power dissipation controller Clock Name Operation clock 172 Description Peripheral clock (PCLK) Remarks - FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.3 MB91625 Series 8.3 Registers This section explains the configurations and functions of the registers that are required for controlling power dissipation. ■ List of registers that control power dissipation Table 8.3-1 is a list of registers that control power dissipation. Table 8.3-1 List of registers that control power dissipation Abbreviated Register Name CM71-10151-2E Register Name Reference STBCR Standby mode control register 8.3.1 SLPRR Sleep rate configuration register 8.3.2 FUJITSU MICROELECTRONICS LIMITED 173 CHAPTER 8 Low-power Dissipation Mode 8.3 8.3.1 MB91625 Series Standby Mode Control Register (STBCR) This register controls low-power dissipation mode. Figure 8.3-1 shows the bit configuration of the standby mode control register (STBCR). Figure 8.3-1 Bit configuration of the standby mode control register (STBCR) bit Attribute 7 6 5 4 3 2 1 0 STOP TIMER SLEEP DOZE Reserved Reserved SLVL1 SLVL0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 1 Initial value R/W: Read/Write [bit7]: STOP (Stop mode enable bit) This bit enables transition to stop mode. Written Value Explanation 0 Does not transit to stop mode. 1 Transits to stop mode. If this register is read after this bit enables transition to stop mode, power dissipation mode moves to stop mode. If the return resource from stop mode occurs, this bit is cleared to "0". For information on return resource from stop mode, see "■ Return from stop mode" in "8.4.6 Operation in Stop Mode". [bit6]: TIMER (Main timer mode/watch mode enable bit) This bit enables transition to main timer mode/watch mode. Written Value Explanation 0 Does not transit to main timer mode/watch mode. 1 Transits to main timer mode/watch mode. If this register is read after this bit enables transition to main timer mode/watch mode, power dissipation mode moves to main timer mode/watch mode. If, however, transition to stop mode is enabled with the STOP bit (STOP = 1), the setting of this bit is ignored even when transition to main timer mode/watch mode is enabled by writing "1" to this bit. If the return resource from main timer mode/watch mode occurs, this bit is cleared to "0". For information on return resource from main timer mode, see "■ Return from the main timer mode" in "8.4.4 Operation in Main Timer Mode". For information on return resource from watch mode, see "■ Return from the watch mode" in "8.4.5 Operation in Watch Mode". 174 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.3 MB91625 Series [bit5]: SLEEP (Sleep mode enable bit) This bit enables transition to sleep mode. Written Value Explanation 0 Does not transit to sleep mode. 1 Transits to sleep mode. If this register is read after this bit enables transition to sleep mode, power dissipation mode moves to sleep mode. If, however, transition to stop mode/main timer mode/watch mode is enabled with the STOP bit/TIMER bit (STOP/TIMER = 1), the setting of this bit is ignored even when transition to sleep mode is enabled by writing "1" to this bit. If the return resource from sleep mode occurs, this bit is cleared to "0". For information on return resource from sleep mode, see "■ Return from sleep mode" in "8.4.3 Operation in Sleep Mode". [bit4]: DOZE (Doze mode enable bit) This bit enables transition to doze mode. Written Value Explanation 0 Does not transit to doze mode (CPU intermittent sleep). 1 The CPU transits to doze mode (CPU intermittent sleep). While the SLVL1 bit is set to "0", if the return resource from doze mode occurs, this bit is cleared to "0". For information on return resource from doze mode, see "■ Return from doze mode" in "8.4.2 Operation in Doze Mode". [bit3, bit2]: Reserved bits CM71-10151-2E In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED 175 CHAPTER 8 Low-power Dissipation Mode 8.3 MB91625 Series [bit1, bit0]: SLVL1, SLVL0 (Standby level setting bits) The meaning of the value to be written to this bit varies depending on the low-power dissipation mode to move to. Low-power Dissipation Mode Stop mode/ Main timer mode/ watch mode Sleep mode Doze mode * SLVL1 SLVL0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Explanation Does not place the output from each pin in Hi-Z in stop mode/main timer mode/watch mode. Places the output from each pin in Hi-Z in stop mode/ main timer mode/watch mode. When moving to sleep mode, power dissipation mode moves to CPU sleep mode (stops only the operation of the CPU). When moving to sleep mode, power dissipation mode moves to bus sleep mode (stops operations of the CPU and on-chip bus). * When interrupt request occur, the DOZE bit is cleared to "0". When interrupt request occur, the DOZE bit is not cleared to "0". During DMA transfer, the on-chip bus operates. <Note> 176 • For information on pins of which the output can be placed in Hi-Z in stop mode/main timer mode/watch mode, see "APPENDIX D Pin State in Each CPU State". • The setting value of SLVL0 bit has no effect on the operation. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.3 MB91625 Series 8.3.2 Sleep Rate Configuration Register (SLPRR) This register configures the operation state (RUN state) rate and sleep state rate (sleep rate) in doze mode. Figure 8.3-2 shows the bit configuration of the sleep rate configuration register (SLPRR). Figure 8.3-2 Bit configuration of the sleep rate configuration register (SLPRR) bit 7 6 5 4 3 2 1 0 RUN3 RUN2 RUN1 RUN0 SLP3 SLP2 SLP1 SLP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> If this register is rewritten in doze mode, the rewritten setting is reflected at the next stop/activation timing. [bit7 to bit4]: RUN3 to RUN0 (Operation period bits) These bits set the period during which the CPU operates in doze mode. The CPU operation period is calculated from the value that is set to these bits as follows. (Value of this bit + 1) × 4 × tCYCP tCYCP : Period of the peripheral clock (PCLK) For details of operation period, see "8.4.2 Operation in Doze Mode". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 177 CHAPTER 8 Low-power Dissipation Mode 8.3 MB91625 Series [bit3 to bit0]: SLP3 to SLP0 (Sleep state period bits) These bits set the period of sleep state in doze mode. The sleep state period is calculated from the value that is set to these bits as follows. (Value of this bit + 1) × 4 × tCYCP tCYCP : Period of the peripheral clock (PCLK) For details of the sleep state period, see "8.4.2 Operation in Doze Mode". <Notes> 178 • A delay may occur when the CPU accepts the sleep request. In this case, the sleep period will be shorter than that obtained from the above calculation formula. • If the sleep state period is short, the CPU may not enter the sleep state depending on the operating status of the CPU. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series 8.4 An Explanation of Operations and Setting Procedure Examples This section explains the operation and use of low-power dissipation mode and includes examples of the procedure for setting this mode. ■ Overview You can reduce power dissipation by changing the division ratio of the operation clock or stopping the operation clock. You can also use the following low-power dissipation modes: • Doze mode This mode intermittently operates the CPU repeatedly at a set operation rate. By repeating operation and stop of the CPU alternately in the set period, the average power dissipation of the CPU can be reduced. • Sleep mode In this mode, only the peripheral functions operate while the CPU and on-chip bus are stopped. One of the following two modes can be selected. - CPU sleep mode - Bus sleep mode This mode stops the operation of the CPU. This mode stops the CPU and on-chip bus. • Standby mode This mode stops the entire device to put it in a standby state. One of the following three modes can be selected. CM71-10151-2E - Main timer mode - Watch mode - Stop mode FUJITSU MICROELECTRONICS LIMITED 179 CHAPTER 8 Low-power Dissipation Mode 8.4 8.4.1 MB91625 Series Operation When Clock Control Is Set Power dissipation and CPU performance can be optimized by adjusting the operation clocks that are built in this series. ■ Overview To reduce power dissipation by controlling the clock, the following two methods are available. • Clock division • Stop clock By changing the division ratio of each operation clock, the operation frequency can be reduced. This allows the user to specify a specific clock to stop. ■ Clock division By changing the division ratio of each operation clock, power dissipation can be reduced. The division ratio of the operation clock can be individually set. Table 8.4-1 shows each operation clock and settable division ratio. Table 8.4-1 Operation clock and settable division ratio Operation Clock Division Ratio Base clock (BCLK) Source clock (SRCCLK) divided by 1 to 8. Peripheral clock (PCLK) Base clock (BCLK) divided by 1 to 16. <Note> The division method or condition differs depending on the operation clock. For information on the division of the operation clock, see "CHAPTER 5 Clock Division Control Part". 180 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series 8.4.2 Operation in Doze Mode This mode intermittently operates the CPU in order to reduce the average power dissipation by the CPU. ■ Overview Using doze mode enables reducing the average power dissipation by the CPU by operating and stopping the CPU alternately at a set interval. Maintain performance while reducing power dissipation by changing the sleep rate according to the processing load. ■ Setting the period If you set the CPU operation period in the RUN3 to RUN0 bits and sleep state period in the SLP3 to SLP0 bits of the sleep rate configuration register (SLPRR), the period will be calculated from the set value using the following calculation formula. (RUN + 1) × 4 × tCYCP + (SLP + 1) × 4 × tCYCP RUN: Value for the RUN3 to RUN0 bits SLP: Value for the SLP3 to SLP0 bits tCYCP : Period of the peripheral clock (PCLK) Figure 8.4-1 shows each cycle. Figure 8.4-1 Operation period and sleep state period PCLK CPU operation SLEEP RUN SLEEP (RUN + 1) × 4 × tCYCP (SLP + 1) × 4 × tCYCP RUN tCYCP : Period of the peripheral clock (PCLK) SLEEP : Sleep state RUN : Operating <Notes> • The above calculation formula does not contain delay time for the CPU to accept the sleep request. Therefore an error may occur. • If the setting of the sleep state period is short, the CPU may not enter the sleep state depending on the operating status of the CPU. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 181 CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series ■ Transition If "1" is written to the DOZE bit in the standby mode control register (STBCR) after the cycle is set, doze mode is entered and the CPU starts intermittent operation by alternately running and stopping according to the setting configured in the sleep rate configuration register (SLPRR). To return from doze mode, write "0" in the DOZE bit of standby mode control register (STBCR). <Note> If the sleep rate configuration register (SLPRR) is rewritten in doze mode, the rewritten setting is reflected at the next stop/operation transition timing. ■ Return from doze mode The CPU returns from doze mode in either of the following cases. • This device is reset. • "0" is written to the DOZE bit of standby mode control register (STBCR). • An interrupt request is generated when the SLVL1 bit of standby mode control register (STBCR) is "0". Except the above cases, the configuration is retained so that you can use doze mode even after returning from sleep mode, main timer mode, watch mode, or stop mode. 8.4.3 Operation in Sleep Mode This mode is used to reduce power dissipation in the event wait state. If sleep mode is entered, it continues until a return resource occurs. When a return resource occurs, it returns to the program operation after two or three clock period. ■ Overview Using sleep mode can significantly reduce power dissipation in the event wait state by stopping the CPU and on-chip bus while allowing only the peripheral functions to operate. The following two modes are available for sleep mode. • CPU sleep mode This mode stops only the operation of the CPU. Because the clock continues to be delivered to the DMA controller (DMAC) or to the on-chip bus, operations of these devices continue. Though the power dissipation is larger than that in bus sleep mode, quick response can be given to the DMA transfer request. • Bus sleep mode This mode stops the operation of the CPU and on-chip bus. It also disables the clock delivery to the DMAC controller (DMAC) or on-chip bus. For information on disabling clock, see "CHAPTER 5 Clock Division Control Part". However, if the DMA transfer request is accepted, the clock delivery to the DMA controller (DMAC) or on-chip bus will be tentatively resumed to allow DMA transfer. After the DMA transfer is completed, the clock delivery will be disabled again. 182 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series ■ Setting Table 8.4-2 shows the settings required before changing to sleep mode. Table 8.4-2 Setting register Registers Standby mode control register (STBCR) Bit Explanation SLVL1 Sets whether to change to CPU sleep mode or to bus sleep mode 0 = Change to CPU sleep mode 1 = Change to bus sleep mode ■ Transition By following the steps below, power dissipation mode moves to sleep mode. 1. Write "0" to the STOP bit, write "0" to the TIMER bit, and write "1" to the SLEEP bit of standby mode control register (STBCR). 2. Read standby mode control register (STBCR). <Note> To prevent the CPU from executing the next instruction before moving to sleep mode, perform the dummy processing that uses the value which is read in the instruction subsequent to step 2, as shown in the example. Example) LDI #value_of_sleep, R0 ; SLEEP bit=1, SLVL1, SLVL0 bit setting LDI #_STBCR, R12 ; STB R0, @R12 ; write LDUB @R12, R0 ; read (move to sleep mode) MOV R0, R0 ; dummy processing NOP ; dummy processing NOP ; dummy processing ■ Return from sleep mode The CPU returns from sleep mode in either of the following cases. • This device is reset. • An interrupt request is generated (whose interrupt level is other than "31"). For information on the interrupt level, see "CHAPTER 10 Interrupt Controller". <Notes> • If the interrupt request is not accepted by the CPU when returning from sleep mode due to the interrupt request, the program is executed starting from the next instruction after entering sleep mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt processing routine. • In bus sleep mode, if a DMA transfer request is generated, the on-chip bus clock (HCLK) delivery is tentatively resumed to perform DMA transfer. The on-chip bus clock (HCLK) delivery is again disabled after DMA transfer is completed. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 183 CHAPTER 8 Low-power Dissipation Mode 8.4 8.4.4 MB91625 Series Operation in Main Timer Mode Main timer mode is categorized as a standby mode. Standby mode stops the entire device to put it in a standby state. By doing so, it can significantly reduce power dissipation in the external event wait state. The permitted clock oscillation, however, operates, allowing less reduction in power dissipation than in stop mode. In main timer mode, select the main clock (MCLK) oscillation as a source clock (SRCCLK) for the CPU. If main timer mode is entered, it continues until a return resource occurs. When a return resource occurs, it returns to the program operation after two or three clock period. ■ Overview In main timer mode, because main clock (MCLK) oscillation is permitted as a source clock (SRCCLK) for the CPU, the count operation of the main timer is executed. The sub clock (SBCLK) oscillation can be specified arbitrarily. ■ Setting Table 8.4-3 shows the settings required before changing to main timer mode. Table 8.4-3 Setting register Registers Clock source select register (CSELR) Standby mode control register (STBCR) Bit Explanation CKS1, CKS0 Selects main clock (MCLK) for the CPU source clock (SRCCLK) (CKS1, CKS0=00 or 01) PCEN Stops PLL clock (PLLCLK) oscillation (PCEN = 0) SCEN Specify sub clock (SBCLK) oscillation. 0=Stop oscillation 1=Start oscillation SLVL1 Sets the output signal from the pins in main timer mode 0 = Retain the state in effect before main timer mode is entered 1 = Hi-Z <Note> When moving to main timer mode, if the SLVL1 bit of the standby mode control register (STBCR) is set to "0" while setting doze mode, the DOZE bit is cleared to "0" on returning from main timer mode to end doze mode. ■ Transition By following the steps below, power dissipation mode moves to main timer mode. 1. Write "0" to the STOP bit, write "1" to the TIMER bit, and write "0" to the SLEEP bit in the standby mode control register (STBCR). 2. Read the standby mode control register (STBCR). <Note> To prevent the CPU from executing the next instruction before moving to main timer mode, perform the dummy processing that uses the value which is read in the instruction subsequent to step 2, as 184 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series shown in the example. Example) LDI #value_of_timer, R0 ; TIMER bit = 1, SLVL1, SLVL0 bit setting LDI #_STBCR, R12 ; STB R0, @R12 ; write LDUB @R12, R0 ; read (move to main timer mode) MOV R0, R0 ; dummy processing NOP ; dummy processing NOP ; dummy processing ■ Return from the main timer mode The CPU returns from main timer mode in either of the following cases. • This device is reset. • Below interrupt requests are generated (whose interrupt level is other than "31"). - Main timer interrupt - Sub timer interrupt - Watch counter interrupt - External interrupt For the interrupt level, see "CHAPTER 10 Interrupt Controller". <Note> If the interrupt request is not accepted by the CPU when returning from main timer mode due to the interrupt request, the program is executed starting from the next instruction after entering main timer mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt processing routine. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 185 CHAPTER 8 Low-power Dissipation Mode 8.4 8.4.5 MB91625 Series Operation in Watch Mode Watch mode is categorized as a standby mode. Standby mode stops the entire device to put it in a standby state. By doing so, it can significantly reduce power dissipation in the external event wait state. The permitted clock oscillation, however, operates, allowing less reduction in power dissipation than in stop mode. In watch mode, select the sub clock (SBCLK) oscillation as a source clock (SRCCLK) for the CPU. If watch mode is entered, it continues until a return resource occurs. When a return resource occurs, it returns to the program operation after two or three clock period. ■ Overview In watch mode, because sub clock (SBCLK) oscillation is permitted as a source clock (SRCCLK) for the CPU, the count operation of the sub timer and watch counter is executed. ■ Setting Table 8.4-4 shows the settings required before changing to watch mode. Table 8.4-4 Setting register Registers Bit Clock source select register (CSELR) Standby mode control register (STBCR) Explanation CKS1, CKS0 Selects sub clock (SBCLK) for the CPU source clock (SRCCLK) (CKS1, CKS0=11) PCEN Stops PLL clock (PLLCLK) oscillation (PCEN = 0) MCEN Stops main clock (MCLK) oscillation (MCEN = 0) SLVL1 Sets the output signal from the pins in watch mode 0 = Retain the state in effect before watch mode is entered 1 = Hi-Z <Note> When moving to watch mode, if the SLVL1 bit of the standby mode control register (STBCR) is set to "0" while setting doze mode, the DOZE bit is cleared to "0" on returning from watch mode to end doze mode. ■ Transition By following the steps below, power dissipation mode moves to watch mode. 1. Write "0" to the STOP bit, write "1" to the TIMER bit, and write "0" to the SLEEP bit in the standby mode control register (STBCR). 2. Read the standby mode control register (STBCR). <Note> To prevent the CPU from executing the next instruction before moving to watch mode, perform the dummy processing that uses the value which is read in the instruction subsequent to step 2, as shown in the example. Example) 186 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series LDI #value_of_timer, R0 ; TIMER bit = 1, SLVL1, SLVL0 bit setting LDI #_STBCR, R12 ; STB R0, @R12 ; write LDUB @R12, R0 ; read (move to watch mode) MOV R0, R0 ; dummy processing NOP ; dummy processing NOP ; dummy processing ■ Return from the watch mode The CPU returns from watch mode in either of the following cases. • This device is reset. • Below interrupt requests are generated (whose interrupt level is other than "31"). - Sub timer interrupt request - Watch counter interrupt request - External interrupt request For the interrupt level, see "CHAPTER 10 Interrupt Controller". <Note> If the interrupt request is not accepted by the CPU when returning from watch mode due to the interrupt request, the program is executed starting from the next instruction after entering watch mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt processing routine. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 187 CHAPTER 8 Low-power Dissipation Mode 8.4 8.4.6 MB91625 Series Operation in Stop Mode Stop mode is categorized as a standby mode. Standby mode stops the entire device to put it in a standby state. By doing so, it can significantly reduce power dissipation in the external event wait state. Stop mode stops all operations including the oscillation of all clocks to minimize power dissipation. ■ Overview Using stop mode can minimize power dissipation by stopping the oscillation of all clocks. To return to the program operation after the return request is generated, however, a certain amount of oscillation stabilization wait time is required. ■ Setting The setting may differ depending on the source clock of the CPU (SRCCLK) before entering stop mode and after returning from stop mode. 188 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series ● If the source clock (SRCCLK) of the CPU before/after stop mode is a sub clock (SBCLK) Table 8.4-5 shows the settings required before changing to stop mode. Table 8.4-5 Setting register Registers Bit Clock source select register (CSELR) Standby mode control register (STBCR) Explanation CKS1, CKS0 Selects sub clock (SBCLK) for the CPU source clock (SRCCLK) (CKS1, CKS0=11) PCEN Stops PLL clock (PLLCLK) oscillation (PCEN = 0) SLVL1 Sets the output signal from the pins in stop mode 0 = Retain the state in effect before stop mode is entered 1 = Hi-Z <Note> At transition to stop mode, if the SLVL1 bit of standby mode control register (STBCR) is set to "0" while doze mode has been set, the DOZE bit is cleared to "0" when the CPU returns from stop mode to end doze mode. ● If the source clock (SRCCLK) of the CPU before/after stop mode is a main clock (MCLK) Table 8.4-6 shows the settings required before changing to stop mode. Table 8.4-6 Setting register Registers Bit Clock source select register (CSELR) Standby mode control register (STBCR) Explanation CKS1, CKS0 Selects the main clock (MCLK) as a source clock (SRCCLK) of the CPU (CKS1, CKS0=00/01) PCEN Stops PLL clock (PLLCLK) oscillation (PCEN = 0) SLVL1 Sets the output signal from the pins in stop mode 0 = Retain the state in effect before stop mode is entered 1 = Hi-Z <Note> At transition to stop mode, if the SLVL1 bit of standby mode control register (STBCR) is set to "0" while doze mode has been set, the DOZE bit is cleared to "0" when the CPU returns from stop mode to end doze mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 189 CHAPTER 8 Low-power Dissipation Mode 8.4 MB91625 Series ■ Transition By following the steps below, power dissipation mode moves to stop mode. 1. Write "1" to the STOP bit write "0" to the TIMER bit, and write "0" to the SLEEP bit in the standby mode control register (STBCR). 2. Read the standby mode control register (STBCR). <Note> To prevent the CPU from executing the next instruction before moving to stop mode, perform the dummy processing that uses the value which is read in the instruction subsequent to step 2, as shown in the example. Example) LDI #value_of_stop, R0 ; STOP bit = 1, SLVL1, SLVL0 bit setting LDI #_STBCR, R12 ; STB R0, @R12 ; write LDUB @R12, R0 ; read (move to stop mode) MOV R0, R0 ; dummy processing NOP ; dummy processing NOP ; dummy processing ■ Return from stop mode The CPU returns from stop mode in either of the following cases. • This device is reset. • Below interrupt requests are generated (whose interrupt level is other than "31"). External interrupt For information on the interrupt level, see "CHAPTER 10 Interrupt Controller". <Note> If the interrupt request is not accepted by the CPU when returning from stop mode due to the interrupt request, the program is executed starting from the next instruction after entering stop mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt processing routine. 190 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 8 Low-power Dissipation Mode 8.5 MB91625 Series 8.5 Notes on Use Note the following points on using low-power dissipation mode. • • If the interrupt request is generated when low-power dissipation mode is switched to the following modes, the switching is disabled. - Doze mode - Sleep mode - Main timer mode - Watch mode - Stop mode For instance, sleep mode is not entered in the following cases. Move to sleep mode after clearing the interrupt request. - CM71-10151-2E In sleep mode, when returning from sleep mode due to an interrupt request that has not been accepted by the CPU, an operation to move to sleep mode is performed again without clearing the interrupt request. FUJITSU MICROELECTRONICS LIMITED 191 CHAPTER 8 Low-power Dissipation Mode 8.5 192 FUJITSU MICROELECTRONICS LIMITED MB91625 Series CM71-10151-2E CHAPTER 9 Reset This chapter explains the functions and operations of reset. 9.1 9.2 9.3 9.4 9.5 9.6 CM71-10151-2E Overview Configuration Pins Registers Explanation of Operations Operating State and Transition FUJITSU MICROELECTRONICS LIMITED 193 CHAPTER 9 Reset 9.1 9.1 MB91625 Series Overview This section explains "reset" to initialize the internal circuit. ■ Overview This device has the following three types of reset resource. • INIT pin input • Watchdog reset 0 • Software reset If either one of the reset resources occurs, operation of all the programs and internal circuits is stopped for initialization. This state is called a reset state. If the reset resource is released, operation of the programs and the hardware starts. 194 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.2 MB91625 Series 9.2 Configuration The configuration of reset is shown. ■ Block diagram of reset Figure 9.2-1 is a block diagram of reset. Figure 9.2-1 Block diagram of reset Reset (RST) Reset request S Q RDLY R RSTCR On-chip bus Peripheral clock (PCLK) INIT pin Delay selector 8 bit Generation of reset Peripheral clocks (PCLK) 4 bit Extension counter Delay counter Bus idle response Initialize reset (INIT) Noise filter S Peripheral clock (PCLK) Peripheral clocks (PCLK) Q Extension counter R 2 bit Resource extension counter Reset request flag Generation of reset S Peripheral clock (PCLK) Q R 2 bit Result extension counter Reset request flag Generation of reset S Watchdog reset 0 Peripheral clock (PCLK) 4 bit Q RSTRR R 2 bit Resource extension counter IRRST Reset request flag ERST Generation of reset WDG0 SRST RSTRR read RSTRR: Reset result register (RSTRR) RSTCR: Reset control register (RSTCR) Software reset request SRST RSTCR CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 195 CHAPTER 9 Reset 9.2 • MB91625 Series Reset result register (RSTRR) This register indicates the reset resource. • Reset control register (RSTCR) This register controls issuing of reset. • Delay counter This counter counts the period from generation of the reset request until the bus enters the idle state. If the bus does not enter the idle state within a certain period of time, the initialize reset (INIT) is forcibly issued. • Result extension counter This counter counts the amount of time for the reset resource to be extended. Each reset resource will be retained until reset is issued. ■ Clocks Table 9.2-1 shows clocks to be used for reset. Table 9.2-1 Clocks used for reset Clock Name Operation clock 196 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.3 MB91625 Series 9.3 Pins This section explains the pins that are used for reset. ■ Overview The following pins are used for reset. • INIT pin The external input pins are used to input the reset request. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 197 CHAPTER 9 Reset 9.4 9.4 MB91625 Series Registers This section explains the configuration and functions of registers used for reset. ■ List of registers used for reset Table 9.4-1 shows the list of registers used for reset. Table 9.4-1 List of registers used for reset Abbreviated Register Name 198 Register Name Reference RSTRR Reset result register 9.4.1 RSTCR Reset control register 9.4.2 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.4 MB91625 Series 9.4.1 Reset Result Register (RSTRR) This register stores the reset resource. It stores all the reset resources that have occurred since the power was turned on until this register is read. Figure 9.4-1 shows the bit configuration of the reset result register (RSTRR). Figure 9.4-1 Bit configuration of the reset result register (RSTRR) bit Attribute 7 6 5 4 3 2 1 0 IRRST ERST Undefined WDG0 Undefined Undefined Undefined SRST R R R R R R R R Initial value * This differs depending on the reset resource. R: Read only *: The initial values are as follows: Reset Resource Initial Value INIT pin input 11XXXXXX Watchdog reset 0 XXX1XXXX Timeout of the watchdog reset 0 1XX1XXXX Software reset XXXXXXX1 Timeout for software reset 1XXXXXX1 Register reading 00000000 X: Not initialized. <Note> If this register is read, all the bits are cleared. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 199 CHAPTER 9 Reset 9.4 MB91625 Series [bit7]: IRRST (Irregular reset bit) A reset is issued without waiting for completion of bus access. This is called an irregular reset. If an irregular reset occurs, the contents of the memory may be damaged. If either a reset by the INIT pin input or a reset timeout occurs, this bit changes to "1". Read Value Explanation 0 No irregular reset is detected. The memory contents are guaranteed to be damage free. 1 An irregular reset is detected. The contents of the memory may have been damaged during the last reset. For details of the irregular reset, see "■ Irregular reset" in "9.5.3 Operation of Reset". [bit6]: ERST (Reset pin input bit) This bits indicates whether the reset by an INIT pin input has occurred. Read Value Explanation 0 Reset by an INIT pin input has not occurred. 1 Reset by an INIT pin input has occurred. [bit5]: Undefined bit In case of reading A value is undefined. [bit4]: WDG0 (Watchdog reset 0 bit) This bit indicates whether the watchdog reset 0 has occurred. If a reset timeout occurred in watchdog timer 0, the IRRST bit also changes to "1". Read Value Explanation 0 A watchdog reset 0 has not occurred. 1 A watchdog reset 0 has occurred. [bit3 to bit1]: Undefined bits In case of reading A value is undefined. [bit0]: SRST (Software reset bit) This bit indicates whether a software reset (RSTCR:SRST) has occurred. If a reset timeout occurred in the software reset (RSTCR:SRST), the IRRST bit also changes to "1". Read Value 200 Explanation 0 A software reset (RSTCR:SRST) has not occurred. 1 A software reset (RSTCR:SRST) has occurred. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.4 MB91625 Series 9.4.2 Reset Control Register (RSTCR) This register controls issuing of reset. Figure 9.4-2 shows the bit configuration of the reset control register (RSTCR). Figure 9.4-2 Bit configuration of the reset control register (RSTCR) bit Attribute 7 6 5 4 3 2 1 0 RDLY2 RDLY1 RDLY0 Reserved Reserved Reserved Reserved SRST R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Initial value R/W: Read/Write [bit7 to bit5]: RDLY2 to RDLY0 (Reset issue delay bit) These bits set the delay time for reset issuing, meaning the length of time that it takes for all the busses to become idle after acceptance of the reset request (delay cycle). RDLY2 RDLY1 RDLY0 Explanation 0 0 0 Peripheral clock (PCLK) × 2 cycles 0 0 1 Peripheral clock (PCLK) × 4 cycles 0 1 0 Peripheral clock (PCLK) × 8 cycles 0 1 1 Peripheral clock (PCLK) × 16 cycles 1 0 0 Peripheral clock (PCLK) × 32 cycles 1 0 1 Peripheral clock (PCLK) × 64 cycles 1 1 0 Peripheral clock (PCLK) × 128 cycles 1 1 1 Peripheral clock (PCLK) × 256 cycles <Notes> • The values of each bit are initialized by reset. Writing after reset is possible only once. • If a low value is set for the delay cycle, a irregular reset due to the reset timeout will likely occur. In contrast, if a high value is set for the delay cycle, it may take long for the reset to be issued after the reset resource occurs. • For information on the irregular reset, see "■ Irregular reset" in "9.5.3 Operation of Reset". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 201 CHAPTER 9 Reset 9.4 MB91625 Series [bit4 to bit1]: Reserved bits In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. [bit0]: SRST (Software reset bit) A software reset request occurs if the reset control register (RSTCR) is read after "1" is written to this bit. Written Value Explanation 0 A reset request has not occurred. 1 A reset request has occurred by reading this register. <Notes> 202 • After "1" is written to this bit, any subsequent writing in the reset control register (RSTCR) is ignored until reset occurs. • Before generating a software reset request by writing "1" to SRST bit, switch the source clock to the main clock (MCLK) divided by 2. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.5 MB91625 Series 9.5 Explanation of Operations This section explains the operation of reset. 9.5.1 Reset Types Three types of resets are provided for this device, whose reset resources and contents for initialization differ from one another. • Power-on reset (SINIT) This reset is used to initialize the unstable state of the division circuit. At the same time, initialize reset (INIT) and reset (RST) are issued. • Reset resource - Input "L" level to INIT pin Target of initialization - Oscillation stabilization wait time of the main clock (MCLK) Reset that concurrently occurs - Initialize reset (INIT) - Reset (RST) Initialize reset (INIT) Initializes the following registers to reset the clock control settings. - Clock source select register (CSELR) - Clock source monitor register (CMONR) - PLL configuration register (PLLCR) - Clock stabilization time select register (CSTBR) Reset (RST) is issued at the same time. • Reset resource - INIT pin input - Reset time out - Watchdog reset 0 Target of initialization - Source clock = Main clock (MCLK) divided by 2 - Clock oscillation = Main clock oscillates, sub/PLL clock stopped - Division rate of the PLL macro oscillation clock - Multiplying factor of the PLL clock (PLLCLK) - Oscillation stabilization wait time of the PLL clock - Division rate of the PLL input clock - Oscillation stabilization wait time of the sub clock Reset that concurrently occurs - Reset (RST) Reset (RST) This reset initializes the program operation. CM71-10151-2E Reset resource - INIT pin input - Reset time out - Watchdog reset 0 - Software reset Target of initialization All the register settings and hardware other than those that are initialized by the power-on reset (SINIT) and initialize reset (INIT). Reset that concurrently occurs No FUJITSU MICROELECTRONICS LIMITED 203 CHAPTER 9 Reset 9.5 9.5.2 MB91625 Series Reset Resource There are three types of reset resource. The level of the reset that is issued differs depending on the reset resource. In addition, whether there is an occurrence of the irregular reset that issues initialize reset (INIT) without verifying completion of bus access, also depends on the reset resource. • INIT pin input An initialize reset (INIT) request occurs while "L" level is input in the INIT pin. • Generation source "L" level is input in the INIT pin Cancellation source "H" level is input in the INIT pin Reset level Issues all of the three resets: power-on reset (SINIT), initialize reset (INIT), and reset (RST) Corresponding flag ERST bit of the reset result register (RSTRR) = 1 Operation Issues the power-on reset (SINIT), initialize reset (INIT), and reset (RST) without waiting for a completion of bus access (irregular reset). Watchdog reset 0 The watchdog reset 0 request is generated if the period set for the watchdog timer elapses. If the watchdog reset 0 request is generated, the initialize reset (INIT) is issued. • Generation source The period set for the watchdog timer elapses Cancellation source Automatically cancelled after the initialize reset (INIT) is issued. Reset level Issues the initialize reset (INIT) and reset (RST) Corresponding flag WDG0 bit of the reset result register (RSTRR) = 1 Operation - Issues an initialize reset (INIT) and reset (RST) after the completion of bus access is verified. - Forcibly issues an initialize reset (INIT) and reset (RST) if a reset timeout occurs before completion of bus access (irregular reset). Software reset (RSTCR:SRST) If the reset control resister (RSTCR) is read after "1" is written to the SRST bit of the reset control register (RSTCR), a reset (RST) request is generated. 204 Generation source The reset control register (RSTCR) is read after "1" is written to the SRST bit of the reset control register (RSTCR). * Set the main clock (MCLK) to the source clock (SRCCLK) before writing "1" to SRST bit. Cancellation source Automatically cancelled after the reset (RST) is issued. Reset level Issues only reset (RST) Corresponding flag SRST bit of the reset result register (RSTRR) = 1 Operation - Issues reset (RST) after verifying completion of bus access. - Forcibly issues an initialize reset (INIT) and reset (RST) if a reset timeout occurs before completion of bus access (irregular reset). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.5 MB91625 Series ■ Flow of reset result determination Figure 9.5-1 Flow of reset result determination Read RSTRR (All bits of RSTRR will be cleared) No IRRST = 1 ? Yes No ERST = 1 ? Yes Reset by INIT pin = L CM71-10151-2E Determination of lower 6bit (Reset time out) FUJITSU MICROELECTRONICS LIMITED Determination of lower 6bit 205 CHAPTER 9 Reset 9.5 9.5.3 MB91625 Series Operation of Reset ■ Flow of reset operation A series of operations from the generation of reset, through reset state, until the CPU starts operation is called a reset sequence. Figure 9.5-2 shows the reset sequence. Figure 9.5-2 Reset sequence Generation of reset resource From the INIT pin, input the "L" level Generation of reset resource Watchdog reset 0 Generation of reset resource Software reset Wait for bus idle Wait for bus idle Reset timeout Bus idle state Reset timeout Bus idle state Power-on reset (Issue SINIT) Issue initialize reset (INIT) Issue reset (RST) Issue reset (RST) Cancel initialize reset (INIT) Cancel reset (RST) Fetch reset vector Program starts 206 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.5 MB91625 Series 1. Retrieval and extension of reset resource The generated reset resource is asynchronously retrieved and retained until reset is issued. 2 bits of resource extension counter retains the reset resource for at least 4Ts (T: Peripheral clock (PCLK) period). 2. Generation of the reset request Reports the generated reset request to the internal bus controller to perform the following processing. - Stops the program operation of the CPU (same as for sleep mode). - Verifies that the idle request has been reported to all busses. At the same time, the delay counter starts counting. 3. Acceptance of reset request and issue of reset After all processing for the reset request is completed, the reset request is accepted. An irregular reset is issued if a reset timeout occurs due to an overflow of the delay counter before response of the completion from the bus. 4. Issue of reset - Input "L" level to INIT pin Issues a power-on reset (SINIT), initialize reset (INIT), and reset (RST). - Watchdog reset 0 - Reset time out Issues initialize reset (INIT) and reset (RST). Issues initialize reset (INIT) and reset (RST). - Software reset (RSTCR:SRST) Issues reset (RST). 5. Cancellation of reset resource If the reset resource is cancelled, the reset request is extended for a period of 4Ts (T: Peripheral clock (PCLK)). The request is then retained for 16 Ts (T: Peripheral clock (PCLK)) reset period. Therefore, the minimum cycle of reset issue is 20 Ts. 6. Cancellation of reset When the reset cycle ends, reset is cancelled and the hardware starts operation. 7. Retrieval of the reset vector (fetch) The CPU starts fetching the reset vector (000F FFFCH). The CPU retrieves the fetched reset vector in the program counter (PC) to start program operation. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 207 CHAPTER 9 Reset 9.5 MB91625 Series ■ Power-on reset (SINIT) Initialize reset (INIT) and reset (RST) are also issued at the same time as the power-on reset (SINIT) is issued. Figure 9.5-3 shows the respective reset issue sequence after the reset resource of the power-on reset (SINIT) is cancelled. Figure 9.5-3 Each reset issue sequence after the reset resource of the power-on reset (SINIT) is cancelled PCLK SINIT INIT RST PCLK × 16 cycles PCLK × 16 cycles Oscillation stabilization wait time + (PCLK × 4 cycles) PCLK SINIT INIT RST 208 : : : : Peripheral clock (PCLK) Power-on reset (SINIT) Initialize reset (INIT) Reset (RST) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.5 MB91625 Series ■ Initialize reset (INIT) When initialize reset (INIT) is issued, reset (RST) is also issued at the same time. Figure 9.5-4 shows the issue sequence of the respective resets after the reset resource of initialize reset (INIT) is cancelled. Figure 9.5-4 Issue sequence of each reset after cancellation of the reset resource of initialize reset (INIT) PCLK Reset Resource INIT RST PCLK × 4 cycles PCLK × 16 cycles PCLK × 16 cycles PCLK : Peripheral clock (PCLK) INIT : Initialize reset (INIT) RST : Reset (RST) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 209 CHAPTER 9 Reset 9.5 MB91625 Series ■ Reset (RST) Figure 9.5-5 shows the respective reset issue sequence after the reset resource of reset (RST) is cancelled. Figure 9.5-5 Each reset issue sequence after the reset resource of the reset (RST) is cancelled PCLK Reset Resource INIT L RST PCLK × 4 cycles PCLK × 16 cycles PCLK : Peripheral clock (PCLK) INIT : Initialize reset (INIT) RST : Reset (RST) 210 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.5 MB91625 Series 9.5.4 Irregular reset Irregular reset occurs in the following cases. • When an INIT pin input (INIT) is used • When a reset timeout occurs (The delay counter overflows before the response from the bus is received during watchdog reset 0 / software reset (RSTCR: SRST).) If irregular reset occurs, the following processes are executed. • Initialize reset (INIT) is issued. • The IRRST bit of the reset result register (RSTRR) changes to "1". <Note> When irregular reset occurs, the bus access may be performed at the time of reset input. In this case, the contents of the memory may be damaged. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 211 CHAPTER 9 Reset 9.6 9.6 MB91625 Series Operating State and Transition This section explains each operating state and how to control it. ■ Operating state Figure 9.6-1 shows transition of the operating state. Figure 9.6-1 Transition of the operating state (1) INIT = L (10) External interrupt that does not require the clock. (2) INIT = H (11) Sub timer interrupt/watch counter interrupt (3) Oscillation stabilization wait end (12) Switch from main to sub (write instruction) (4) RST cancel (13) Switch from sub to main (write instruction) (5) Software reset (RST) (14) Switch from main to PLL (write instruction) (6) Sleep mode (write instruction) (15) Switch from PLL to main (write instruction) (7) Stop mode (write instruction) (16) Watchdog reset/software reset timeout (INIT) (8) Main timer mode/ watch mode (write instruction) (17) INIT cancel (9) Interrupt (18) Main timer interrupt/sub timer interrupt/watch counter interrupt Power on (1) Power-on reset (SINIT) (2) (1) When MCRDY = 0 Main oscillation stabilization wait reset (1) PLL sleep (3) (9) (6) When MCRDY = 1 (16) (1) Setting initialization PLL RUN (1) (INIT) Doze mode (15) (14) (17) (16) (10) (4) (1) (11) Main program reset (RST) Main timer mode (1) (16) (10) (1) Watch mode (8) (5) (13) Main RUN (18) (8) (7) Sub RUN (12) Doze mode (6) (9) Doze mode (1) (1) (7) (1) (6) Sub stop (9) (1) Main stop Main sleep Sub sleep (10) (3) (10) (3) Sub oscillation stabilization wait RUN Main oscillation stabilization wait RUN (1) 212 (1) (1) FUJITSU MICROELECTRONICS LIMITED (1) CM71-10151-2E CHAPTER 9 Reset 9.6 MB91625 Series ● RUN state (normal operation) Program is running. All the internal clocks are delivered and all the circuits are enabled. The Hi-Z control of the external pins in stop state, main timer mode state and watch mode state is cancelled. ● Sleep state Program is stopped. Transition occurs by program operation. Only program execution of the CPU is stopped. The peripheral circuits are enabled. The built-in memories and external busses are suspended until the DMA controller (DMAC) request is received. In bus sleep mode, the internal bus is suspended until the DMA controller (DMAC) request is received. • If a valid interrupt request is generated, the device undergoes transition to the RUN state (normal operation). • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. ● Watch mode state The device is in a suspended state. Transition occurs by the program operation. Internal circuits other than the oscillation circuits (sub clock (SBCLK)) are stopped. The external pins can be uniformly set to Hi-Z (excluding certain pins). • If an external interrupt request is generated, the device undergoes transition to the RUN state (normal operation). • If a sub timer interrupt, or watch counter interrupt request is generated, it undergoes transition to the RUN state (normal operation). • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. <Note> Stop oscillation of the main clock (MCLK) and PLL clock (PLLCLK) before transition to watch mode. ● Main timer mode state The device is in a suspended state. Transition occurs by the program operation. Internal circuits other than the oscillation circuits (main clock (MCLK) and sub clock (SBCLK)) are stopped. The external pins can be uniformly set to Hi-Z (excluding certain pins). • If an external interrupt is generated, the device undergoes transition to the RUN state (normal operation). • If a main timer interrupt, sub timer interrupt, and watch counter interrupt requests are generated, it undergoes transition to the RUN state (normal operation). • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. <Note> Stop oscillation of the PLL clock (PLLCLK) before transition to main timer mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 213 CHAPTER 9 Reset 9.6 MB91625 Series ● Stop state The device is in a suspended state. Transition occurs by the program operation. All the internal circuits are suspended. The external pins can be uniformly set to Hi-Z (excluding certain pins). • If an external interrupt request is generated, the device undergoes transition to the oscillation stabilization wait RUN state. • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. <Note> Stop oscillation of the PLL clock (PLLCLK) before transition to the stop state. ● Oscillation stabilization wait RUN state The device is in a suspended state. Transition to this state occurs after the device returns from the stop state. All the internal circuits are suspended (excluding timer operation for clock stabilization wait). While all the internal clocks are stopped, oscillation circuits that have been enabled operate. • When the oscillation stabilization wait time elapses, the device undergoes transition to the RUN state (normal operation). • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. ● Oscillation stabilization wait reset (RST) state The device is in a suspended state. Transition occurs after the device returns from power-on reset (SINIT). All the internal circuits are suspended (excluding timer operation for oscillation stabilization wait). While all the internal clocks are suspended, the main oscillation circuit operates. • When the oscillation stabilization wait time elapses, the device undergoes transition to the initialize reset (INIT) state. • If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state. ● Program reset (RST) state Program is in the initialized state. Transition occurs when a reset (RST) request is accepted or after the initialize reset (INIT) state ends. The program execution of the CPU is suspended and the program counter is initialized. The peripheral circuits are initialized (excluding certain circuits). All the internal clocks as well as the oscillation circuits that have been enabled and the PLL clock (PLLCLK) operate. 214 • The reset (RST) request for the internal circuits is generated. When the reset (RST) request disappears, transition to the RUN state (normal operation) occurs. • If "L" level is input in the INIT pin, the device undergoes transition to the power-on reset (SINIT) state. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 9 Reset 9.6 MB91625 Series ● Initialize reset (INIT) state This is the state in which all settings are initialized. Transition occurs when the initialize reset (INIT) request is accepted. The program execution of the CPU is suspended and the program counter is initialized. All the peripheral circuits are initialized. The main clock (MCLK) oscillation circuit operates (while the sub clock (SBCLK) oscillation circuit and PLL clock (PLLCLK) oscillation circuit stop operation). All the internal clocks stop while the "L" level is being input in the INIT pin. Otherwise, they operate. Initialize reset (INIT) and reset (RST) are output to the internal circuit. • When the initialize reset (INIT) request disappears, this state is cancelled and transition to the program reset (RST) state occurs. • If "L" is input in the INIT pin, the device undergoes transition to the power-on reset (SINIT) state. ■ Priority of state transition requests state transition requests are prioritized in the following order in any states. However, since some requests are generated only in the particular states, they are enabled only in those states. Highest priority Power-on reset (SINIT) request Initialize reset (INIT) request Oscillation stabilization wait time end Occurs only in the oscillation stabilization wait reset state and oscillation stabilization wait RUN state Reset (RST) request Lowest priority CM71-10151-2E Valid interrupt request Occurs only in the RUN, sleep, stop, and watch mode state Stop mode request (register write) Occurs only in the RUN state Watch mode request (register write) Occurs only in the RUN state Sleep mode request (register write) Occurs only in the RUN state FUJITSU MICROELECTRONICS LIMITED 215 CHAPTER 9 Reset 9.6 216 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 10 Interrupt Controller This chapter explains the functions and operations of the interrupt controller. 10.1 10.2 10.3 10.4 Overview Configuration Registers An Explanation of Operations and Setting Procedure Examples 10.5 Notes on Use CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 217 CHAPTER 10 Interrupt Controller 10.1 MB91625 Series 10.1 Overview The interrupt controller determines the priority of an interrupt request and sends the request to the CPU. ■ Overview The interrupt control has the following functions: 218 • Accepts interrupt requests from peripheral functions. • Determines the priority of sending interrupt requests to the CPU according to the interrupt level and interrupt vector. • Sends the highest priority interrupt request to the CPU. • Sends the interrupt vector number of the highest priority interrupt request to the CPU. • Generates a request for returning from sleep mode or stop mode according to an interrupt request with an interrupt level other than "1111". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 10 Interrupt Controller 10.2 MB91625 Series 10.2 Configuration This section explains the interrupt controller configuration. ■ Block diagram of interrupt controller Figure 10.2-1 shows a block diagram of the interrupt controller. Figure 10.2-1 Block diagram of interrupt controller Priority determination ICR00 ICR47 Level Interrupt Level Vector Interrupt vector number Request for return Interrupt requests from peripheral functions Peripheral bus • Interrupt priority determination circuit This circuit determines the priority of an incoming interrupt request. It also generates a request to return from sleep mode or stop mode. • Interrupt level generating circuit This circuit transmits the interrupt level of an interrupt request to the CPU. • Interrupt vector generating circuit This circuit sends the interrupt vector of an interrupt request to the CPU. • Interrupt control registers (ICR00 to ICR47) These registers are used to set the interrupt levels of interrupt requests. ■ Clocks Clock Name Operation clock CM71-10151-2E Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED 219 CHAPTER 10 Interrupt Controller 10.3 MB91625 Series 10.3 Registers This section explains the configurations and functions of the registers used by the interrupt controller. ■ Interrupt controller registers Table 10.3-1 lists the interrupt controller registers. Table 10.3-1 Interrupt controller registers Abbreviated Register Name ICR00 to ICR47 220 Register Name Interrupt control registers 00 to 47 FUJITSU MICROELECTRONICS LIMITED Reference 10.3.1 CM71-10151-2E CHAPTER 10 Interrupt Controller 10.3 MB91625 Series 10.3.1 Interrupt Control Register (ICR00 to ICR47) These registers are used to set interrupt levels. This register is provided for input of each interrupt. Figure 10.3-1 shows the bit configuration of the interrupt control registers (ICR00 to ICR47). Figure 10.3-1 Bit configuration of interrupt control registers (ICR00 to ICR47) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined IL4 IL3 IL2 IL1 IL0 R/W R/W R/W R R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Attribute Initial value R/W: Read/Write R: Read only [bit7 to bit5]: Undefined bits CM71-10151-2E In case of writing Ignored In case of reading "1" is read. FUJITSU MICROELECTRONICS LIMITED 221 CHAPTER 10 Interrupt Controller 10.3 MB91625 Series [bit4 to bit0]: IL4 to IL0 (interrupt level control bits) These bits specify the interrupt level of an interrupt request. When reset, the bits are initialized to IL4 to IL0=11111("11111B" is level 31 interrupt disabled). IL4 IL3 IL2 IL1 IL0 Interrupt Level 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 Lowest level that can be set 1 1 1 1 1 31 Interrupt Disabled Highest level that can be set (Higher) (Lower) <Notes> 222 • If the interrupt level that is set in this register is lower than the mask level in the CPU interrupt level mask register (ILM), the interrupt request is masked on the CPU side. • The interrupt control register (ICR00 to ICR47) in which an interrupt level is set varies depending on the peripheral function. For information on the correspondence between the peripheral function and interrupt control register (ICR00 to ICR47), see "APPENDIX C Interrupt Vectors". • IL4 bit is fixed to "1" and IL3 to IL0 can be set. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 10 Interrupt Controller 10.4 MB91625 Series 10.4 An Explanation of Operations and Setting Procedure Examples This section explains the operations of the interrupt controller. 10.4.1 Explanation of Operations of Interrupt Controller This section explains the three types of operations of the interrupt controller. • Specifying interrupt levels using interrupt control registers (ICR00 to ICR47) • Determining the priorities of interrupt requests • Generating a request to return from sleep mode or stop mode ■ Specifying an interrupt level The procedure for setting interrupt levels using interrupt control registers (ICR00 to ICR47) is shown below: 1. Set an interrupt level in the interrupt control register (ICR00 to ICR47) with the interrupt vector number corresponding to the peripheral function for which an interrupt request needs to be generated. For information on the correspondence between interrupt control numbers and interrupt requests, see "APPENDIX C Interrupt Vectors". 2. Enable generation of interrupt requests on the peripheral function for which an interrupt request needs to be generated. 3. Activate the relevant peripheral function. ■ Determining the priorities of interrupt requests The interrupt controller sends the interrupt level and interrupt vector number of the highest priority interrupt request, among the interrupt requests that are concurrently generated, to the CPU. The criteria for determining the priorities of interrupt requests are shown in order of determining: 1. Is the interrupt level of the interrupt request "30" or lower (Level 31 is "Interrupt Disabled"). 2. Is the value of the interrupt level of the interrupt request the smallest. 3. If the interrupt level is the same, is the interrupt vector number of the interrupt request the smallest. If no interrupt request meets the above criteria, interrupt level "31" (11111B) that indicates no interrupt request is output to the CPU. ■ Generating a request to return from sleep mode If an interrupt request with an interrupt level other than "31" is generated, the interrupt controller generates a request to the clock control part to return from sleep mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 223 CHAPTER 10 Interrupt Controller 10.4 MB91625 Series ■ Generating a request to return from stop mode If an external interrupt request with an interrupt level other than "31" is generated, the interrupt controller generates a request to the clock control part to return from stop mode. After return from the stop mode, the interrupt priority determination circuit resumes operation only after the operation of clock begins. The CPU thus executes instructions until the interrupt priority determination circuit produces results. <Note> For interrupts that are not used as causes of return from stop mode, set interrupt level "31" (Interrupt Disabled) in the corresponding interrupt control registers (ICR00 to ICR47). 224 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 10 Interrupt Controller 10.5 MB91625 Series 10.5 Notes on Use Note the following points about using the interrupt controller. ■ Note on the program • For interrupt requests that should not be used to generate a request to return from sleep mode or stop mode, set interrupt level "31" (Interrupt Disabled) in the corresponding interrupt control registers (ICR00 to ICR47). ■ Notes on operations • CM71-10151-2E If the interrupt level that is set in an interrupt control register (ICR00 to ICR47) is lower than the mask level in the CPU interrupt level mask register (ILM), the interrupt request is masked on the CPU side. FUJITSU MICROELECTRONICS LIMITED 225 CHAPTER 10 Interrupt Controller 10.5 226 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function This section explains the interrupt request batch-read function. 11.1 11.2 11.3 11.4 CM71-10151-2E Overview Configuration Registers Notes on Use FUJITSU MICROELECTRONICS LIMITED 227 CHAPTER 11 Interrupt Request Batch-Read Function 11.1 MB91625 Series 11.1 Overview The interrupt request batch-read function reads multiple interrupt requests assigned to one interrupt vector all at once. The bit search instruction of an FR80 family CPUs can be used to quickly check which interrupt requests have been generated. This function allows the user to check at one time whether interrupt requests that use the same interrupt vector number have been generated. Note that this function cannot clear the interrupt request flag. Use the register of each peripheral function to clear the interrupt request flag. 228 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.2 MB91625 Series 11.2 Configuration This section shows the configuration of the interrupt request batch-read function. ■ Block diagram of interrupt request batch-read function Figure 11.2-1 is a block diagram of the interrupt request batch-read function. Figure 11.2-1 Block diagram of interrupt request batch-read function Peripheral bus Interrupt request Interrupt request batch-read 16 bit registers (IRPR0H to From each peripheral function IRPR7H, IRPR1L to IRPR7L) ■ Clocks Clock Name Operation clock CM71-10151-2E Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED 229 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3 Registers This section explains the configuration and functions of registers used by the interrupt request batchread function. ■ Registers for interrupt request batch-read function Table 11.3-1 lists the registers for the interrupt request batch-read function. Table 11.3-1 Registers for the interrupt request batch-read function Abbreviated Register Name 230 Register Name Reference IRPR0H Interrupt request batch-read register 0 upper 11.3.1 IRPR1H/ IRPR1L Interrupt request batch-read register 1 upper/lower 11.3.2 IRPR2H/ IRPR2L Interrupt request batch-read register 2 upper/lower 11.3.3, 11.3.4 IRPR3H/ IRPR3L Interrupt request batch-read register 3 upper/lower 11.3.5, 11.3.6 IRPR4H/ IRPR4L Interrupt request batch-read register 4 upper/lower 11.3.7, 11.3.8 IRPR5H/ IRPR5L Interrupt request batch-read register 5 upper/lower 11.3.9, 11.3.10 IRPR6H/ IRPR6L Interrupt request batch-read register 6 upper/lower 11.3.11, 11.3.12 IRPR7H/ IRPR7L Interrupt request batch-read register 7 upper/lower 11.3.13, 11.3.14 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.1 Interrupt Request Batch-Read Register 0 Upper (IRPR0H) The interrupt requests of 16-bit reload timer ch.0 to ch.2 are assigned to interrupt vector number 20 (decimal). This register can be read to check the channel on which an interrupt request has been generated. Figure 11.3-1 shows the bit configuration of interrupt request batch-read register 0 upper (IRPR0H). Figure 11.3-1 Bit configuration of interrupt request batch-read register 0 upper (IRPR0H) Interrupt request batch-read register 0 upper (IRPR0H) bit 15 14 13 12 11 10 9 8 RTIR0 RTIR1 RTIR2 Undefined Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 231 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series The bit corresponding to the channel on which an interrupt request has been generated is set to "1". Bit number bit15 bit14 bit13 bit12 to bit8 232 Bit RTIR0 RTIR1 RTIR2 Undefined Value Explanation 0 No interrupt request in reload timer ch.0 1 Interrupt request in reload timer ch.0 0 No interrupt request in reload timer ch.1 1 Interrupt request in reload timer ch.1 0 No interrupt request in reload timer ch.2 1 Interrupt request in reload timer ch.2 "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.2 Interrupt Request Batch-Read Register 1 Upper/Lower (IRPR1H/ IRPR1L) Interrupt vector number 39 (decimal) is used for multifunction serial interface channels ch.8 to ch.11. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-2 shows the bit configuration of interrupt request batch-read register 1 upper/lower (IRPR1H/ IRPR1L). Figure 11.3-2 Bit configuration of interrupt request batch-read register 1 upper/lower (IRPR1H/ IRPR1L) Interrupt request batch-read register 1 upper (IRPR1H) bit 15 14 13 12 11 10 9 8 RXIR8 TXIR8 ISIR8 Undefined RXIR9 TXIR9 ISIR9 Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 Interrupt request batch-read register 1 lower (IRPR1L) bit 7 6 5 4 3 2 1 0 RXIR10 TXIR10 ISIR10 Undefined RXIR11 TXIR11 ISIR11 Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 233 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 RXIR8 TXIR8 ISIR8 Value Explanation 0 No UART/CSIO/I2C receive interrupt request on ch.8 1 UART/CSIO/I2C receive interrupt request on ch.8 0 No UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.8 1 UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.8 0 No I2C status interrupt request on ch.8 1 I2C status interrupt request on ch.8 bit12 Undefined "0" is read. bit11 RXIR9 0 No UART/CSIO/I2C receive interrupt request on ch.9 1 UART/CSIO/I2C receive interrupt request on ch.9 0 No UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.9 1 UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.9 0 No I2C status interrupt request on ch.9 1 I2C status interrupt request on ch.9 bit10 bit9 TXIR9 ISIR9 bit8 Undefined "0" is read. bit7 RXIR10 0 No UART/CSIO/I2C receive interrupt request on ch.10 1 UART/CSIO/I2C receive interrupt request on ch.10 0 No UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.10 1 UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.10 0 No I2C status interrupt request on ch.10 1 I2C status interrupt request on ch.10 bit6 bit5 234 Bit TXIR10 ISIR10 bit4 Undefined "0" is read. bit3 RXIR11 0 No UART/CSIO/I2C receive interrupt request on ch.11 1 UART/CSIO/I2C receive interrupt request on ch.11 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Bit number bit2 bit1 bit0 CM71-10151-2E Bit TXIR11 ISIR11 Undefined Value Explanation 0 No UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.11 1 UART/CSIO/I2C transmit/transmit bus idle/transmit FIFO interrupt request on ch.11 0 No I2C status interrupt request on ch.11 1 I2C status interrupt request on ch.11 "0" is read. FUJITSU MICROELECTRONICS LIMITED 235 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 11.3.3 MB91625 Series Interrupt Request Batch-Read Register 2 Upper (IRPR2H) Interrupt vector number 40 (decimal) is used for 16-bit up/down counter channels ch.0 to ch.3. This register can be read to check the channel on which an interrupt request has been generated. Figure 11.3-3 shows the bit configuration of interrupt request batch-read register 2 upper (IRPR2H). Figure 11.3-3 Bit configuration of Interrupt request batch-read register 2 upper (IRPR2H) bit 15 14 13 12 11 10 9 8 UDIR0 UDIR1 UDIR2 UDIR3 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 236 Bit UDIR0 UDIR1 UDIR2 UDIR3 Undefined Value Explanation 0 No interrupt request in 16-bit up/down counter ch.0 1 Interrupt request in 16-bit up/down counter ch.0 0 No interrupt request in 16-bit up/down counter ch.1 1 Interrupt request in 16-bit up/down counter ch.1 0 No interrupt request in 16-bit up/down counter ch.2 1 Interrupt request in 16-bit up/down counter ch.2 0 No interrupt request in 16-bit up/down counter ch.3 1 Interrupt request in 16-bit up/down counter ch.3 "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.4 Interrupt Request Batch-Read Register 2 Lower (IRPR2L) Interrupt vector number 41 (decimal) is used for the following peripheral functions: • Main timer • Sub timer • Watch counter This register can be read to check the peripheral function from which an interrupt request has been generated. Figure 11.3-4 shows the bit configuration of interrupt request batch-read register 2 lower (IRPR2L). Figure 11.3-4 Bit configuration of interrupt request batch-read register 2 lower (IRPR2L) bit 7 6 5 4 3 2 1 0 MCIR SCIR TCIR Undefined Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit7 bit6 bit5 bit4 to bit0 CM71-10151-2E Bit MCIR SCIR TCIR Undefined Value Explanation 0 No main timer interrupt request 1 Main timer interrupt request 0 No sub timer interrupt request 1 Sub timer interrupt request 0 No watch counter interrupt request 1 Watch counter interrupt request "0" is read. FUJITSU MICROELECTRONICS LIMITED 237 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 11.3.5 MB91625 Series Interrupt Request Batch-Read Register 3 Upper (IRPR3H) Interrupt vector number 44 (decimal) is used for 32-bit input capture channels ch.0 to ch.3. This register can be read to check on which channel an interrupt request has been generated. Figure 11.3-5 shows the bit configuration of interrupt request batch-read register 3 upper (IRPR3H). Figure 11.3-5 Bit configuration of Interrupt request batch-read register 3 upper (IRPR3H) bit 15 14 13 12 11 10 9 8 ICIR0 ICIR1 ICIR2 ICIR3 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 238 Bit ICIR0 ICIR1 ICIR2 ICIR3 Undefined Value Explanation 0 No interrupt request on 32-bit input capture ch.0 1 Interrupt request on 32-bit input capture ch.0 0 No interrupt request on 32-bit input capture ch.1 1 Interrupt request on 32-bit input capture ch.1 0 No interrupt request on 32-bit input capture ch.2 1 Interrupt request on 32-bit input capture ch.2 0 No interrupt request on 32-bit input capture ch.3 1 Interrupt request on 32-bit input capture ch.3 "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.6 Interrupt Request Batch-Read Register 3 Lower (IRPR3L) Interrupt vector number 37 (decimal) is used for the following peripheral functions: • UART/CSIO/I2C ch.7 receive interrupt request • 32-bit input capture ch.4 to ch.7 This register can be read to check the peripheral function from which an interrupt request has been generated. Figure 11.3-6 shows the bit configuration of interrupt request batch-read register 3 lower (IRPR3L). Figure 11.3-6 Bit configuration of interrupt request batch-read register 3 lower (IRPR3L) bit 7 6 5 4 3 2 1 0 ICIR4 ICIR5 ICIR6 ICIR7 RXIR7 Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit7 bit6 bit5 bit4 bit3 bit2 to bit0 CM71-10151-2E Bit ICIR4 ICIR5 ICIR6 ICIR7 RXIR7 Undefined Value Explanation 0 No interrupt request on 32-bit input capture ch.4 1 Interrupt request on 32-bit input capture ch.4 0 No interrupt request on 32-bit input capture ch.5 1 Interrupt request on 32-bit input capture ch.5 0 No interrupt request on 32-bit input capture ch.6 1 Interrupt request on 32-bit input capture ch.6 0 No interrupt request on 32-bit input capture ch.7 1 Interrupt request on 32-bit input capture ch.7 0 No receive interrupt request on UART/CSIO/I2C ch.7 1 Receive interrupt request on UART/CSIO/I2C ch.7 "0" is read. FUJITSU MICROELECTRONICS LIMITED 239 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 11.3.7 MB91625 Series Interrupt Request Batch-Read Register 4 Upper (IRPR4H) Interrupt vector number 45 (decimal) is used for 32-bit output compare channels ch.0 to ch.3. This register can be read to check on which channel an interrupt request has been generated. Figure 11.3-7 shows the bit configuration of interrupt request batch-read register 4 upper (IRPR4H). Figure 11.3-7 Bit configuration of Interrupt request batch-read register 4 upper (IRPR4H) bit 15 14 13 12 11 10 9 8 OCIR0 OCIR1 OCIR2 OCIR3 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 240 Bit OCIR0 OCIR1 OCIR2 OCIR3 Undefined Value Explanation 0 No interrupt request on 32-bit output compare ch.0 1 Interrupt request on 32-bit output compare ch.0 0 No interrupt request on 32-bit output compare ch.1 1 Interrupt request on 32-bit output compare ch.1 0 No interrupt request on 32-bit output compare ch.2 1 Interrupt request on 32-bit output compare ch.2 0 No interrupt request on 32-bit output compare ch.3 1 Interrupt request on 32-bit output compare ch.3 "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.8 Interrupt Request Batch-Read Register 4 Lower (IRPR4L) Interrupt vector number 38 (decimal) is used for the following peripheral functions: • UART/CSIO/I2C ch.7 transmit/transmit bus idle • I2C ch.7 status interrupt request • 32-bit output compare ch.4 to ch.7 This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-8 shows the bit configuration of interrupt request batch-read register 4 lower (IRPR4L). Figure 11.3-8 Bit configuration of interrupt request batch-read register 4 lower (IRPR4L) bit 7 6 5 4 3 2 1 0 OCIR4 OCIR5 OCIR6 OCIR7 TXIR7 ISIR7 Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 241 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 Bit number bit7 bit6 bit5 bit4 bit3 bit2 bit1, bit0 242 Bit OCIR4 OCIR5 OCIR6 OCIR7 TXIR7 ISIR7 Undefined MB91625 Series Value Explanation 0 No interrupt request on 32-bit output compare ch.4 1 Interrupt request on 32-bit output compare ch.4 0 No interrupt request on 32-bit output compare ch.5 1 Interrupt request on 32-bit output compare ch.5 0 No interrupt request on 32-bit output compare ch.6 1 Interrupt request on 32-bit output compare ch.6 0 No interrupt request on 32-bit output compare ch.7 1 Interrupt request on 32-bit output compare ch.7 0 No UART/CSIO/I2C ch.7 transmit/transmit bus idle 1 UART/CSIO/I2C ch.7 transmit/transmit bus idle 0 No I2C ch.7 status interrupt request 1 I2C ch.7 status interrupt request "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.9 Interrupt Request Batch-Read Register 5 Upper (IRPR5H) Interrupt vector number 50 (decimal) is used for base timer channels ch.4 and ch.5. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-9 shows the bit configuration of interrupt request batch-read register 5 upper (IRPR5H). Figure 11.3-9 Bit configuration of Interrupt request batch-read register 5 upper (IRPR5H) bit 15 14 13 12 11 10 9 8 BT0IR4 BT1IR4 BT0IR5 BT1IR5 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 CM71-10151-2E Bit BT0IR4 BT1IR4 BT0IR5 BT1IR5 Undefined Value Explanation 0 No interrupt request 0 generated on base timer ch.4 1 Interrupt request 0 generated on base timer ch.4 0 No interrupt request 1 generated on base timer ch.4 1 Interrupt request 1 generated on base timer ch.4 0 No interrupt request 0 generated on base timer ch.5 1 Interrupt request 0 generated on base timer ch.5 0 No interrupt request 1 generated on base timer ch.5 1 Interrupt request 1 generated on base timer ch.5 "0" is read. FUJITSU MICROELECTRONICS LIMITED 243 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Interrupt requests 0 and 1 vary depending on the mode of the base timer operation. Modes of base timer operation 244 Interrupt request 0 Interrupt request 1 16/32-bit reload timer Underflow interrupt request Trigger interrupt request 16-bit PWM timer Underflow interrupt request Duty match interrupt request Trigger interrupt request 16/32-bit PWC timer Overflow interrupt request Measurement end interrupt request 16-bit PPG timer Underflow interrupt request Trigger interrupt request FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.10 Interrupt Request Batch-Read Register 5 Lower (IRPR5L) Interrupt vector number 51 (decimal) is used for base timer channels ch.6 and ch.7. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-10 shows the bit configuration of interrupt request batch-read register 5 lower (IRPR5L). Figure 11.3-10 Bit configuration of interrupt request batch-read register 5 lower (IRPR5L) bit 7 6 5 4 3 2 1 0 BT0IR6 BT1IR6 BT0IR7 BT1IR7 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit7 bit6 bit5 bit4 bit3 to bit0 CM71-10151-2E Bit BT0IR6 BT1IR6 BT0IR7 BT1IR7 Undefined Value Explanation 0 No interrupt request 0 generated on base timer ch.6 1 Interrupt request 0 generated on base timer ch.6 0 No interrupt request 1 generated on base timer ch.6 1 Interrupt request 1 generated on base timer ch.6 0 No interrupt request 0 generated on base timer ch.7 1 Interrupt request 0 generated on base timer ch.7 0 No interrupt request 1 generated on base timer ch.7 1 Interrupt request 1 generated on base timer ch.7 "0" is read. FUJITSU MICROELECTRONICS LIMITED 245 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Interrupt requests 0 and 1 vary depending on the mode of the base timer operation. Modes of base timer operation 246 Interrupt request 0 Interrupt request 1 16/32-bit reload timer Underflow interrupt request Trigger interrupt request 16-bit PWM timer Underflow interrupt request Duty match interrupt request Trigger interrupt request 16/32-bit PWC timer Overflow interrupt request Measurement end interrupt request 16-bit PPG timer Underflow interrupt request Trigger interrupt request FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.11 Interrupt Request Batch-Read Register 6 Upper (IRPR6H) Interrupt vector number 52 (decimal) is used for base timer channels ch.8 and ch.9. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-11 shows the bit configuration of interrupt request batch-read register 6 upper (IRPR6H). Figure 11.3-11 Bit configuration of Interrupt request batch-read register 6 upper (IRPR6H) bit 15 14 13 12 11 10 9 8 BT0IR8 BT1IR8 BT0IR9 BT1IR9 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 CM71-10151-2E Bit BT0IR8 BT1IR8 BT0IR9 BT1IR9 Undefined Value Explanation 0 No interrupt request 0 generated on base timer ch.8 1 Interrupt request 0 generated on base timer ch.8 0 No interrupt request 1 generated on base timer ch.8 1 Interrupt request 1 generated on base timer ch.8 0 No interrupt request 0 generated on base timer ch.9 1 Interrupt request 0 generated on base timer ch.9 0 No interrupt request 1 generated on base timer ch.9 1 Interrupt request 1 generated on base timer ch.9 "0" is read. FUJITSU MICROELECTRONICS LIMITED 247 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Interrupt requests 0 and 1 vary depending on the mode of the base timer operation. Modes of base timer operation 248 Interrupt request 0 Interrupt request 1 16/32-bit reload timer Underflow interrupt request Trigger interrupt request 16-bit PWM timer Underflow interrupt request Duty match interrupt request Trigger interrupt request 16/32-bit PWC timer Overflow interrupt request Measurement end interrupt request 16-bit PPG timer Underflow interrupt request Trigger interrupt request FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.12 Interrupt Request Batch-Read Register 6 Lower (IRPR6L) Interrupt vector number 53 (decimal) is used for base timer channels ch.10 and ch.11. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-12 shows the bit configuration of interrupt request batch-read register 6 lower (IRPR6L). Figure 11.3-12 Bit configuration of interrupt request batch-read register 6 lower (IRPR6L) bit 7 6 5 4 3 2 1 0 BT0IR10 BT1IR10 BT0IR11 BT1IR11 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit7 bit6 bit5 bit4 bit3 to bit0 CM71-10151-2E Bit BT0IR10 BT1IR10 BT0IR11 BT1IR11 Undefined Value Explanation 0 No interrupt request 0 generated on base timer ch.10 1 Interrupt request 0 generated on base timer ch.10 0 No interrupt request 1 generated on base timer ch.10 1 Interrupt request 1 generated on base timer ch.10 0 No interrupt request 0 generated on base timer ch.11 1 Interrupt request 0 generated on base timer ch.11 0 No interrupt request 1 generated on base timer ch.11 1 Interrupt request 1 generated on base timer ch.11 "0" is read. FUJITSU MICROELECTRONICS LIMITED 249 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Interrupt requests 0 and 1 vary depending on the mode of the base timer operation. Modes of base timer operation 250 Interrupt request 0 Interrupt request 1 16/32-bit reload timer Underflow interrupt request Trigger interrupt request 16-bit PWM timer Underflow interrupt request Duty match interrupt request Trigger interrupt request 16/32-bit PWC timer Overflow interrupt request Measurement end interrupt request 16-bit PPG timer Underflow interrupt request Trigger interrupt request FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.13 Interrupt Request Batch-Read Register 7 Upper (IRPR7H) Interrupt vector number 56 (decimal) is used for base timer channels ch.14 and ch.15. This register can be read to check on which channels interrupt requests have been generated and the types of interrupt requests. Figure 11.3-13 shows the bit configuration of interrupt request batch-read register 7 upper (IRPR7H). Figure 11.3-13 Bit configuration of interrupt request batch-read register 7 upper (IRPR7H) bit 15 14 13 12 11 10 9 8 BT0IR14 BT1IR14 BT0IR15 BT1IR15 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to "1". Bit number bit15 bit14 bit13 bit12 bit11 to bit8 CM71-10151-2E Bit BT0IR14 BT1IR14 BT0IR15 BT1IR15 Undefined Value Explanation 0 No interrupt request 0 generated on base timer ch.14 1 Interrupt request 0 generated on base timer ch.14 0 No interrupt request 1 generated on base timer ch.14 1 Interrupt request 1 generated on base timer ch.14 0 No interrupt request 0 generated on base timer ch.15 1 Interrupt request 0 generated on base timer ch.15 0 No interrupt request 1 generated on base timer ch.15 1 Interrupt request 1 generated on base timer ch.15 "0" is read. FUJITSU MICROELECTRONICS LIMITED 251 CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series Interrupt requests 0 and 1 vary depending on the mode of the base timer operation. Modes of base timer operation 252 Interrupt request 0 Interrupt request 1 16/32-bit reload timer Underflow interrupt request Trigger interrupt request 16-bit PWM timer Underflow interrupt request Duty match interrupt request Trigger interrupt request 16/32-bit PWC timer Overflow interrupt request Measurement end interrupt request 16-bit PPG timer Underflow interrupt request Trigger interrupt request FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 11 Interrupt Request Batch-Read Function 11.3 MB91625 Series 11.3.14 Interrupt Request Batch-Read Register 7 Lower (IRPR7L) Interrupt vector number 61 (decimal) is used for DMA controller (DMAC) channels ch.4 to ch.7. This register can be read to check on which channel an interrupt request has been generated. Figure 11.3-14 shows the bit configuration of interrupt request batch-read register 7 lower (IRPR7L). Figure 11.3-14 Bit configuration of Interrupt request batch-read register 7 lower (IRPR7L) bit 7 6 5 4 3 2 1 0 DMAC4 DMAC5 DMAC6 DMAC7 Undefined Undefined Undefined Undefined Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only When one of the following interrupt requests is generated on DMA controller (DMAC) ch.4 to ch.7, the bit corresponding to the generated interrupt request is set to "1". • Normal end interrupt request • Abnormal end interrupt request • Transfer stop interrupt request Bit number bit7 bit6 bit5 bit4 bit3 to bit0 CM71-10151-2E Bit DMAC4 DMAC5 DMAC6 DMAC7 Undefined Value Explanation 0 No interrupt request on DMAC ch.4 1 Interrupt request on DMAC ch.4 0 No interrupt request on DMAC ch.5 1 Interrupt request on DMAC ch.5 0 No interrupt request on DMAC ch.6 1 Interrupt request on DMAC ch.6 0 No interrupt request on DMAC ch.7 1 Interrupt request on DMAC ch.7 "0" is read. FUJITSU MICROELECTRONICS LIMITED 253 CHAPTER 11 Interrupt Request Batch-Read Function 11.4 MB91625 Series 11.4 Notes on Use Note the following points about using the interrupt request batch-read function. ■ Notes on operations • 254 Writing to the interrupt request batch-read register (IRPR0 to IRPR7) is disabled. To cancel an interrupt request, clear the interrupt request flag bit of the corresponding function register. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 12 Delay Interrupt This chapter explains the functions and operations of the delay interrupt function. 12.1 12.2 12.3 12.4 Overview Configuration Registers An Explanation of Operations and Setting Procedure Examples 12.5 Notes on Use CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 255 CHAPTER 12 Delay Interrupt 12.1 MB91625 Series 12.1 Overview The delay interrupt function generates task switching interrupts used by a real-time OS. ■ Overview The delay interrupt function generates task switching interrupt requests used by a real-time OS such as REALOS. Software can use delay interrupts to generate interrupt requests to the CPU or cancel them. 256 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 12 Delay Interrupt 12.2 MB91625 Series 12.2 Configuration This section explains the configuration of delay interrupts. ■ Delay interrupt block diagram Figure 12.2-1 shows a delay interrupt block diagram. Figure 12.2-1 Delay interrupt block diagram peripheral bus Delay interrupt control register (DICR) Interrupt request • Delayed interrupt control register (DICR) This register controls delay interrupts. ■ Clocks Clock Name Operation clock CM71-10151-2E Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED 257 CHAPTER 12 Delay Interrupt 12.3 MB91625 Series 12.3 Registers This section explains the configuration and functions of the register used for delay interrupts. ■ Delay interrupt register Table 12.3-1 shows the delay interrupt register. Table 12.3-1 Delay interrupt register Abbreviated Register Name DICR 258 Register Name Delayed interrupt control register FUJITSU MICROELECTRONICS LIMITED Reference 12.3.1 CM71-10151-2E CHAPTER 12 Delay Interrupt 12.3 MB91625 Series 12.3.1 Delayed Interrupt Control Register (DICR) This register controls delay interrupts. Figure 12.3-1 shows the bit configuration of the delayed interrupt control register (DICR). Figure 12.3-1 Bit configuration of delayed interrupt control register (DICR) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined DLYI R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 0 Attribute Initial value R/W: Read/Write [bit7 to bit1]: Undefined bits In case of writing Ignored In case of reading "1" is read. [bit0]: DLYI (delay interrupt control bit) This bit is used to enable generation of delay interrupt requests or cancel the delay interrupt requests. Written Value Explanation 0 Cancels delay interrupt source or generates no delay interrupt request 1 Generation of delay interrupt requests. <Note> This bit is used in the same way as other interrupt request flags. Clear this bit in the interrupt processing routine and switch tasks accordingly. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 259 CHAPTER 12 Delay Interrupt 12.4 MB91625 Series 12.4 An Explanation of Operations and Setting Procedure Examples This section explains delay interrupt operations and the setting procedure for delay interrupts. 12.4.1 Explanation of Delay Interrupt Operations Software can use delay interrupts to generate interrupt requests to the CPU or cancel them. Table 12.4-1 lists the conditions for generating delay interrupts. Table 12.4-1 Interrupt request generation conditions Interrupt request Delay interrupt request Interrupt request generation Write "1" to the DLYI bit of the delayed interrupt control register (DICR). Interrupt request enabled None (interrupts always enabled) Clearing an interrupt request Write "0" to the DLYI bit of the delayed interrupt control register (DICR). <Notes> • 260 Delay interrupts cannot be used for DMA transfer requests. • For information on interrupt vector numbers, see "APPENDIX C Interrupt Vectors". • Use an interrupt control register (ICR47) to specify the interrupt level corresponding to the interrupt vector number.For information on the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 12 Delay Interrupt 12.5 MB91625 Series 12.5 Notes on Use Note the following points about using delay interrupts. ■ Notes on the program • The delay interrupt control bit can be used in the same way as other interrupt request flags. Clear this bit in the interrupt routine and switch tasks accordingly. • Delay interrupts cannot be used for DMA transfer requests. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 261 CHAPTER 12 Delay Interrupt 12.5 262 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports This chapter explains the functions and operations of the I/O ports. 13.1 13.2 13.3 13.4 Overview Configuration Pins Registers 13.5 Notes on Use CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 263 CHAPTER 13 I/O Ports 13.1 MB91625 Series 13.1 Overview Pins of this series that are not used for peripheral functions can be used as I/O ports. This series is equipped with 86 I/O ports. ■ Overview The I/O ports have the following features: • Each pin can be specified as an I/O port used only as an input port or output port. • Each pin can be specified as a pin used as an I/O port or a pin for a peripheral function. Also, one of the I/O modes listed below can be selected depending on the register settings: Table 13.1-1 lists the I/O modes. Table 13.1-1 I/O modes I/O mode Access to PDR Port input mode Port output mode Peripheral function output mode * PDR: In case of reading (except RMW instructions) The levels of external pins are read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is stored in a PDR. In case of reading (except RMW instructions) The PDR value is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is stored in a PDR and output to an external pin. In case of reading (except RMW instructions) The output level from a peripheral function or the PDR value is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is stored in a PDR. Port data register (PDR0 to PDRK) RMW instruction: Read-modify-write instruction *: 264 The value that is read varies depending on the register settings. • A pull-up resistor can be set for each pin. • If Hi-Z is set to a pin with the CPU in standby mode (stop mode/watch mode/main timer mode), input is fixed at "0". However, input is not fixed at "0" for external interrupt requests whose generation is enabled and it can be used. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.1 MB91625 Series • A peripheral function can be assigned to any pin available for peripheral functions, if more than one pin is available, and peripheral function output from the pin can be enabled/disabled. However, if the peripheral function has more than one I/O, each I/O must be set to individual ports belonging to the same group. Example: Ch.0 multifunction serial interface settings Serial Data Output SOUT0 pin (Port 0) Serial Clock I/O SCK0 pin (Port 0) SCK0_1 pin (Port 1) Serial Data Input Valid Port SIN0 pin (Port 0) Port 0 SIN0_1 pin (Port 1) Setting prohibited SIN0 pin (Port 0) SIN0_1 pin (Port 1) SOUT0_1 pin (Port 1) SCK0 pin (Port 0) SIN0 pin (Port 0) SIN0_1 pin (Port 1) SCK0_1 pin (Port 1) SIN0 pin (Port 0) SIN0_1 pin (Port 1) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED Port 1 265 CHAPTER 13 I/O Ports 13.2 MB91625 Series 13.2 Configuration This series has the following 3 types of built-in I/O port: • Ordinary I/O ports • Analog input multifunction I/O ports • Analog output multifunction I/O ports ■ Overview 3 types of built-in I/O port that this series has are described below. • Ordinary I/O ports These I/O ports have basic configurations in which the ports are used also for I/O of peripheral functions. Each port consists of the following blocks: • - Port function registers (PFR0 to PFRA) - Port data direction registers (DDR0 to DDRK) - Extended port function registers (EPFR0 to EPFR34) - Pull-up resistor control registers (PCR0 to PCRK) - Port data registers (PDR0 to PDRK) Analog input multifunction I/O ports These I/O ports are used also for analog input of the 10-bit A/D converter. Each port consists of an analog input enable block and the ordinary I/O port blocks. The analog input multifunction ports are P77 to P70 and P87 to P80. • Analog output multifunction I/O ports These I/O ports are used also for analog output of the 8-bit D/A converter. Each port consists of an analog output enable block and the ordinary I/O port blocks, except those of the following registers: - Port function registers (PFR0 to PFRA) - Extended port function registers (EPFR0 to EPFR34) The analog output multifunction ports are P91, P90. 266 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.2 MB91625 Series ■ Block diagrams ● Ordinary I/O ports Figure 13.2-1 is a block diagram of an ordinary I/O port. Figure 13.2-1 Block diagram of an ordinary I/O port Peripheral function 0 Input selection CMOS schmitt 1 Peripheral bus DDR Port data direction control PFR Vcc EPFR R PCR PDR Pins Output selection Peripheral function output • Port data direction registers (DDR0 to DDRK) These registers set the I/O directions of pins used as general-purpose ports. For a pin for a peripheral function, these registers set the contents read from a port data register (PDR0 to PDRK). • Port function registers (PFR0 to PFRA) These registers select how to use individual pins. • Extended port function registers (EPFR0 to EPFR34) These registers set the pin to which a peripheral function is assigned from among the multiple pins available for peripheral functions. Peripheral function output from such pins is enabled/disabled according to the registers. • Pull-up resistor control registers (PCR0 to PCRK) These registers set pull-up resistors. With one register provided for each port, a pull-up resistor can be connected to each pin. • Port data registers (PDR0 to PDRK) These registers store output data. The meanings of read and written values vary depending on the mode of the port. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 267 CHAPTER 13 I/O Ports 13.2 MB91625 Series ● Analog input multifunction I/O port Figure 13.2-2 is a block diagram of an analog input multifunction I/O port. Figure 13.2-2 Block diagram of an analog input multifunction I/O port A/D input CMOS schmitt Peripheral function 0 Input selection 1 Analog input enable Peripheral bus DDR Port data direction control PFR Vcc EPFR R PCR PDR Pins Output selection Peripheral function output The analog input multifunction I/O port consists of the blocks that are components of each ordinary I/O port and the analog input enable block. This block enables analog input from pins for which input is enabled by the A/D channel enable register (ADCHE). <Notes> 268 • The analog input multifunction ports are P77 to P70 and P87 to P80. • In serial write mode selected by the MD1 and MD0 pins (MD1, MD0 = 01), digital input is enabled and analog input is disabled only for P75 (AN5 pin). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.2 MB91625 Series ● Analog output multifunction I/O ports Figure 13.2-3 is a block diagram of an analog output multifunction I/O port. Figure 13.2-3 Block diagram of an analog output multifunction I/O port D/A output CMOS schmitt Peripheral function 0 Input selection 1 Peripheral bus DDR Port data direction control Analog output enable Vcc R PCR PDR Pins Output selection Peripheral function output The analog output multifunction I/O port consists of the blocks that are components of each ordinary I/O port other than the following register and the analog output enable block. - Port function registers (PFR0 to PFRA) - Extended port function registers (EPFR0 to EPFR34) This block enables analog output from pins for which output is enabled by the D/A control registers (DACR0, DACR1). For details of the D/A control registers (DACR0, DACR1), see "CHAPTER 25 8-bit D/A Converter". <Note> The D/A analog output multifunction ports are P91, P90. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 269 CHAPTER 13 I/O Ports 13.2 MB91625 Series ■ Clocks Table 13.2-1 lists the clocks used for I/O ports. Table 13.2-1 Clocks used for I/O ports Clock name Operation clock 270 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.3 MB91625 Series 13.3 Pins This section explains the pins of I/O ports. ■ Overview Up to 86 I/O ports are provided, and they are categorized into port 0 to port K. The I/O ports belonging to a port with the same suffix can be read/written at the same time. • P00 to P07 (port 0) • P10 to P17 (port 1) • P20 to P27 (port 2) • P30 to P37 (port 3) • P40 to P47 (port 4) • P50 to P57 (port 5) • P60 to P67 (port 6) • P70 to P77 (port 7) • P80 to P87 (port 8) • P90 to P92 (port 9) • PA0 to PA7 (port A) • PK0 to PK2 (port K) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 271 CHAPTER 13 I/O Ports 13.4 MB91625 Series 13.4 Registers This section explains the configuration and functions of the registers used for I/O ports. ■ List of registers for I/O ports Table 13.4-1 lists the registers for I/O ports. Table 13.4-1 Registers for I/O ports (1 / 2) Port Common 0 1 2 3 4 5 272 Abbreviated Register Name Register Name Reference EPFR0 to EPFR34 Extended port function register 0 to 34 13.4.3 ADCHE A/D channel enable register 13.4.6 DDR0 Port data direction register 0 13.4.1 PFR0 Port function register 0 13.4.2 PCR0 Pull-up resistor control register 0 13.4.5 PDR0 Port data register 0 13.4.4 DDR1 Port data direction register 1 13.4.1 PFR1 Port function register 1 13.4.2 PCR1 Pull-up resistor control register 1 13.4.5 PDR1 Port data register 1 13.4.4 DDR2 Port data direction register 2 13.4.1 PFR2 Port function register 2 13.4.2 PDR2 Port data register 2 13.4.4 DDR3 Port data direction register 3 13.4.1 PFR3 Port function register 3 13.4.2 PDR3 Port data register 3 13.4.4 DDR4 Port data direction register 4 13.4.1 PFR4 Port function register 4 13.4.2 PDR4 Port data register 4 13.4.4 DDR5 Port data direction register 5 13.4.1 PFR5 Port function register 5 13.4.2 PCR5 Pull-up resistor control register 5 13.4.5 PDR5 Port data register 5 13.4.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series Table 13.4-1 Registers for I/O ports (2 / 2) Port 6 7 8 9 A K CM71-10151-2E Abbreviated Register Name Register Name Reference DDR6 Port data direction register 6 13.4.1 PFR6 Port function register 6 13.4.2 PCR6 Pull-up resistor control register 6 13.4.5 PDR6 Port data register 6 13.4.4 DDR7 Port data direction register 7 13.4.1 PFR7 Port function register 7 13.4.2 PCR7 Pull-up resistor control register 7 13.4.5 PDR7 Port data register 7 13.4.4 DDR8 Port data direction register 8 13.4.1 PFR8 Port function register 8 13.4.2 PCR8 Pull-up resistor control register 8 13.4.5 PDR8 Port data register 8 13.4.4 DDR9 Port data direction register 9 13.4.1 PCR9 Pull-up resistor control register 9 13.4.5 PDR9 Port data register 9 13.4.4 DDRA Port data direction register A 13.4.1 PFRA Port function register A 13.4.2 PCRA Pull-up resistor control register A 13.4.5 PDRA Port data register A 13.4.4 DDRK Port data direction register K 13.4.1 PCRK Pull-up resistor control register K 13.4.5 PDRK Port data register K 13.4.4 FUJITSU MICROELECTRONICS LIMITED 273 CHAPTER 13 I/O Ports 13.4 13.4.1 MB91625 Series Port Data Direction Registers (DDR0 to DDRK) These registers set the I/O directions of pins used as general-purpose ports. For a pin for a peripheral function, these registers set the contents read from a port data register (PDR0 to PDRK). The meaning of a read/written value of the port data register (PDR0 to PDRK) varies depending on the setting of each bit in this port data direction register and the settings of a port function register (PFR0 to PFRA). Figure 13.4-1 shows the bit configuration of the port data direction registers (DDR0 to DDRK). Figure 13.4-1 Bit configuration of the port data direction registers (DDR0 to DDRK) bit 7 6 5 4 3 2 1 0 Initial value Attribute DDR0 DDR07 DDR06 DDR05 DDR04 DDR03 DDR02 DDR01 DDR00 0000 0000 R/W DDR1 DDR17 DDR16 DDR15 DDR14 DDR13 DDR12 DDR11 DDR10 0000 0000 R/W DDR2 DDR27 DDR26 DDR25 DDR24 DDR23 DDR22 DDR21 DDR20 0000 0000 R/W DDR3 DDR37 DDR36 DDR35 DDR34 DDR33 DDR32 DDR31 DDR30 0000 0000 R/W DDR4 DDR47 DDR46 DDR45 DDR44 DDR43 DDR42 DDR41 DDR40 0000 0000 R/W DDR5 DDR57 DDR56 DDR55 DDR54 DDR53 DDR52 DDR51 DDR50 0000 0000 R/W DDR6 DDR67 DDR66 DDR65 DDR64 DDR63 DDR62 DDR61 DDR60 0000 0000 R/W DDR7 DDR77 DDR76 DDR75 DDR74 DDR73 DDR72 DDR71 DDR70 0000 0000 R/W DDR8 DDR87 DDR86 DDR85 DDR84 DDR83 DDR82 DDR81 DDR80 0000 0000 R/W DDR9 Undefined Undefined Undefined Undefined Undefined DDR92 DDR91 DDR90 XXXX X000 R/W DDRA DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 DDRK Undefined Undefined Undefined Undefined Undefined DDRK2 DDRK1 DDRK0 XXXX X000 R/W R/W R/W: Read/Write X: 274 Undefined FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series Each bit sets the I/O direction of the corresponding port. Written Value Explanation 0 Input direction 1 Output direction The meaning of a read/written value of a port data register (PDR0 to PDRK) varies depending on the setting of each bit in one of these port data direction registers and the settings of a port function register (PFR0 to PFRA). Table 13.4-2 shows the relationship between the register settings and read/written values of the port data registers (PDR0 to PDRK). Table 13.4-2 Relationship between register settings and read/written values of the port data registers (PDR0 to PDRK) Mode Port input mode Port output mode Peripheral function output mode * DDR PFR 0 0 1 0 1 * 0 1 1 PDR In case of reading (except RMW instructions) The output level of an external pin is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is saved in a PDR. In case of reading (except RMW instructions) The PDR value is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is saved in a PDR and output to an external pin. In case of reading (except RMW instructions) The output level from a peripheral function is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is saved in a PDR. In case of reading (except RMW instructions) The PDR value is read. In case of reading (RMW instructions) The PDR value is read. In case of writing The written value is saved in a PDR. The functions of the output pins of external functions must be assigned to the appropriate pins by the extended port function registers (EPFR0 to EPFR34), and output from the pins must be enabled. DDR: Port data direction register (DDR0 to DDRK) PFR: Port function register (PFR0 to PFRA) PDR: Port data register (PDR0 to PDRK) RMW instruction: Read-modify-write instruction CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 275 CHAPTER 13 I/O Ports 13.4 MB91625 Series <Notes> • The input to a peripheral function is always connected to the pin assigned by an appropriate bit in an extended port function register (EPFR0 to EPFR34). Use port input mode for input to a peripheral function. However, when input from the 10-bit A/D converter is enabled, input is always fixed at "0", and output from the port is always fixed at Hi-Z. Furthermore, when output from the 8-bit D/A converter is enabled, the settings of each register are disabled, input is always fixed at "0", and output from the port is always fixed at Hi-Z. In serial write mode selected by the MD1 and MD0 pins (MD1, MD0 = 01), digital input is enabled and analog input is disabled only for P75 (AN5 pin). • When this device is reset, the settings of these registers are reset to the initial value (00H), and the I/O direction of every port becomes input. • To use PK0 and PK1 as low-speed oscillation pins, be sure to set the I/O directions of the ports to input (DDRK0 = 0, DDRK1 = 0) in port data direction register K (DDRK). (If PK0 and PK1 is used as a low-speed oscillation pin when the I/O direction of the related port has been set to output, the PDR value is output from the pin when low-speed oscillation is disabled.) 276 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series 13.4.2 Port Function Registers (PFR0 to PFRA) These registers select how to use individual pins. The meaning of a read/written value of a port data register (PDR0 to PDRK) varies depending on the setting of each bit in one of these port function registers and the settings of a port data direction register (DDR0 to DDRK). For details, see "13.4.1 Port Data Direction Registers (DDR0 to DDRK)". Figure 13.4-2 shows the bit configuration of the port function registers (PFR0 to PFRA). Figure 13.4-2 Bit configuration of the port function registers (PFR0 to PFRA) bit 7 6 5 4 3 2 1 0 Initial value Attribute PFR0 PFR07 PFR06 PFR05 PFR04 PFR03 PFR02 PFR01 PFR00 0000 0000 R/W PFR1 PFR17 PFR16 PFR15 PFR14 PFR13 PFR12 PFR11 PFR10 0000 0000 R/W PFR2 PFR27 PFR26 PFR25 PFR24 PFR23 PFR22 PFR21 PFR20 0000 0000 R/W PFR3 PFR37 PFR36 PFR35 PFR34 PFR33 PFR32 PFR31 PFR30 0000 0000 R/W PFR4 PFR47 PFR46 PFR45 PFR44 PFR43 PFR42 PFR41 PFR40 0000 0000 R/W PFR5 PFR57 PFR56 PFR55 PFR54 PFR53 PFR52 PFR51 PFR50 0000 0000 R/W PFR6 PFR67 PFR66 Undefined PFR64 PFR63 Undefined PFR61 PFR7 PFR77 PFR76 PFR75 PFR74 PFR73 PFR72 PFR71 PFR70 0000 0000 R/W PFR8 PFR87 PFR86 PFR85 PFR84 PFR83 PFR82 PFR81 PFR80 0000 0000 R/W PFRA PFRA7 PFRA6 Undefined PFRA4 PFRA3 PFRA2 PFRA1 PFRA0 00X0 0000 R/W Undefined 00X0 0X0X R/W R/W: Read/Write X: Undefined CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 277 CHAPTER 13 I/O Ports 13.4 MB91625 Series The port function registers specify each pin as either a pin used as a general-purpose port or a pin for the peripheral function specified by an extended port function register (EPFR0 to EPFR34). Written Value Explanation 0 General-purpose port 1 Peripheral function The following function and I/O settings can be made for each pin according to the settings of bits in one of these registers and the corresponding bits in an extended port function register (EPFR0 to EPFR34): PFR EPFR Function of Corresponding Pin Output from Peripheral Functions Input to Peripheral Functions Port Output 0 0 Port Disabled Enabled Set by DDR 1 Sets the function assigned to the output pin of a peripheral function and enables output. Output pin of a peripheral function Enabled Enabled Disabled Cancels the assignment of a function to the output pin of a peripheral function, or disables output Port Disabled Enabled Set by DDR PFR: Corresponding bit in a port function register (PFR0 to PFRA) EPFR: Corresponding bit in an extended port function register (EPFR0 to EPFR34) <Notes> • When this device is reset, the settings of these registers are reset to the initial value (00H), and all ports are set to operate as input ports. • If this register specifies a pin as a general-purpose port, the corresponding pin will operate as a general-purpose port even if a peripheral function has been assigned to that pin in one of the extended port function registers (EPFR0 to EPFR34). • When analog input is enabled through the settings of the A/D channel enable register (ADCHE), input from ports and other functions is fixed at "0" regardless of the settings of these registers. • When output from the 8-bit D/A converter is enabled by the DAE bit (DAE = 1) of the D/A control registers (DACR0, DACR1), input from ports is fixed at "0" regardless of the settings of these registers. For details of the D/A control registers (DACR0, DACR1), see "CHAPTER 25 8-bit D/A Converter". • The input to a peripheral function is always connected to the pin assigned by an appropriate bit in an extended port function register (EPFR0 to EPFR34). Use port input mode for input to a peripheral function. However, when input from the 10-bit A/D converter is enabled, input is always fixed at "0", and output from the port is always fixed at Hi-Z. Furthermore, when output from the 8-bit D/A converter is enabled, the settings of each register are disabled, input is always fixed at "0", and output from the port is always fixed at Hi-Z. 278 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series 13.4.3 Extended Port Function Registers (EPFR0 to EPFR34) These registers set the pin to which a function is assigned from among the multiple pins available for the function. Output from such pins is enabled/disabled according to the registers. Figure 13.4-3 shows the bit configuration of the extended port function registers (EPFR0 to EPFR34). Figure 13.4-3 Bit configuration of the extended port function registers (EPFR0 to EPFR34) 7 6 5 4 3 2 1 0 Initial value EPFR0 bit Undefined Undefined OUT1E2 OUT1E1 OUT1E0 OUT0E2 OUT0E1 OUT0E0 XX00 0000 EPFR1 Undefined Undefined OUT3E2 OUT3E1 OUT3E0 OUT2E2 OUT2E1 OUT2E0 XX00 0000 EPFR2 Undefined Undefined OUT5E2 OUT5E1 OUT5E0 OUT4E2 OUT4E1 OUT4E0 XX00 0000 EPFR3 Undefined Undefined OUT7E2 OUT7E1 OUT7E0 OUT6E2 OUT6E1 OUT6E0 XX00 0000 EPFR4 IN3E1 IN3E0 IN2E1 IN2E0 IN1E1 IN1E0 IN0E1 IN0E0 0000 0000 EPFR5 IN7E1 IN7E0 IN6E1 IN6E0 IN5E1 IN5E0 IN4E1 IN4E0 0000 0000 EPFR6 SOUT0E2 SOUT0E1 SOUT0E0 SCK0E2 SCK0E1 SCK0E0 SIN0E1 SIN0E0 0000 0000 EPFR7 Undefined Undefined Undefined SOUT1E1 SOUT1E0 SCK1E1 SCK1E0 SIN1E XXX0 0000 EPFR8 Undefined Undefined Undefined SOUT2E1 SOUT2E0 SCK2E1 SCK2E0 SIN2E XXX0 0000 EPFR9 Undefined Undefined Undefined SOUT3E1 SOUT3E0 SCK3E1 SCK3E0 SIN3E XXX0 0000 EPFR10 Undefined Undefined Undefined SOUT4E1 SOUT4E0 SCK4E1 SCK4E0 SIN4E XXX0 0000 EPFR11 Undefined Undefined Undefined SOUT5E1 SOUT5E0 SCK5E1 SCK5E0 SIN5E XXX0 0000 EPFR12 Undefined Undefined Undefined SOUT6E1 SOUT6E0 SCK6E1 SCK6E0 SIN6E XXX0 0000 EPFR13 Undefined Undefined Undefined SOUT7E1 SOUT7E0 SCK7E1 SCK7E0 SIN7E XXX0 0000 EPFR14 Undefined Undefined Undefined SOUT8E1 SOUT8E0 SCK8E1 SCK8E0 SIN8E XXX0 0000 EPFR15 Undefined Undefined Undefined SOUT9E1 SOUT9E0 SCK9E1 SCK9E0 SIN9E XXX0 0000 EPFR16 Undefined Undefined Undefined SOUT10E1 SOUT10E0 SCK10E1 SCK10E0 SIN10E XXX0 0000 EPFR17 Undefined Undefined Undefined SOUT11E1 SOUT11E0 SCK11E1 SCK11E0 SIN11E XXX0 0000 EPFR18 UDIN3E1 UDIN3E0 UDIN2E1 UDIN2E0 UDIN1E0 UDIN0E1 UDIN0E0 EPFR19 Undefined Undefined Undefined Undefined XAE XXXX 0001 EPFR20 Undefined Undefined TIOA1E1 TIOA1E0 TIOB1E TIOA0E1 TIOA0E0 TIOB0E XX00 0000 EPFR21 Undefined Undefined TIOA3E1 TIOA3E0 TIOB3E TIOA2E1 TIOA2E0 TIOB2E XX00 0000 EPFR22 Undefined Undefined TIOA5E1 TIOA5E0 TIOB5E TIOA4E1 TIOA4E0 TIOB4E XX00 0000 EPFR23 Undefined Undefined TIOA7E1 TIOA7E0 TIOB7E TIOA6E1 TIOA6E0 TIOB6E XX00 0000 EPFR24 Undefined Undefined TIOA9E1 TIOA9E0 TIOB9E TIOA8E1 TIOA8E0 TIOB8E XX00 0000 EPFR25 Undefined Undefined TIOA11E1 TIOA11E0 TIOB11E TIOA10E1 TIOA10E0 TIOB10E XX00 0000 EPFR26 Undefined Undefined TIOA13E1 TIOA13E0 TIOB13E TIOA12E1 TIOA12E0 TIOB12E XX00 0000 EPFR27 Undefined Undefined TIOA15E1 TIOA15E0 TIOB15E TIOA14E1 TIOA14E0 TIOB14E XX00 0000 EPFR28 INT7E INT6E INT5E INT4E INT3E INT2E INT1E INT0E 0000 0000 UDIN1E1 ADTRG0E2 ADTRG0E1 ADTRG0E0 0000 0000 EPFR29 INT15E INT14E INT13E INT12E INT11E INT10E INT9E INT8E 0000 0000 EPFR30 Undefined Undefined Undefined Undefined INT19E INT18E INT17E INT16E XXXX 0000 EPFR31 Undefined INT23E1 INT23E0 INT22E1 INT22E0 INT21E1 INT21E0 INT20E X000 0000 EPFR32 INT31E INT30E INT29E INT28E INT27E INT26E INT25E INT24E 0000 0000 EPFR33 Undefined Undefined TMO1E1 TMO1E0 TMI1E TMO0E1 TMO0E0 TMI0E XX00 0000 EPFR34 Undefined TMO2E1 TMO2E0 TMI2E FRCK1E1 FRCK1E0 FRCK0E1 FRCK0E0 X000 0000 Attribute: R/W (Read/Write) for all the bits X: Undefined CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 279 CHAPTER 13 I/O Ports 13.4 MB91625 Series <Notes> • The pins that are specified as general-purpose ports in settings of the port function registers (PFR0 to PFRA) are treated as general-purpose I/O ports regardless of the settings of these registers. • When analog input is enabled through the settings of the A/D channel enable register (ADCHE), input from ports is fixed at "0" regardless of the settings of these registers or port function registers (PFR0 to PFRA). • When output from the 8-bit D/A converter is enabled by the DAE bit (DAE = 1) of the D/A control registers (DACR0, DACR1), input from ports is fixed at "0" and output from ports is fixed at Hi-Z regardless of the settings of these registers or port function registers (PFR0 to PFRA). For details of the D/A control registers (DACR0, DACR1), see "CHAPTER 25 8-bit D/A Converter". • A single pin cannot be used as an output pin for multiple peripheral functions. Also, a single output function cannot be assigned to multiple pins. • A single pin can be used as an input pin for multiple peripheral functions. However, a single input function cannot be assigned to multiple pins. • If multiple functions are assigned to one pin, the order of priority is as follows: 1. X0A/X1A 2. Multifunction serial interface 3. Base timer 4. 16-bit reload timer 5. 32-bit output compare • The input to a peripheral function is always connected to the pin assigned by an appropriate bit in an extended port function register (EPFR0 to EPFR34). Use port input mode for input to a peripheral function. However, when input from the 10-bit A/D converter or output from the 8-bit D/A converter is enabled, input is fixed at "0". • Before changing the pin to which peripheral function output is assigned through the settings of this register, make the following settings: - Set port input mode for the pin to which the function is currently assigned and the pin to which it will be assigned. - Disable the assigned peripheral function. • 280 Before changing the pin to which a peripheral function input is assigned through the settings of this register, disable the assigned peripheral function. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 0 (EPFR0) to extended port function register 3 (EPFR3) [bit5 to bit0]: OUTxE2 to OUTxE0 (Output compare output pin select bits) 2 output pins for 32-bit output compare are provided for each channel. These bits select the pins used by ch.0 to ch.7 for 32-bit output compare. The OUT0E2 to OUT0E0 bits correspond to ch.0, the OUT1E2 to OUT1E0 bits correspond to ch.1,..., and the OUT7E2 to OUT7E0 bits correspond to ch.7. OUTxE2 0 OUTxE1 0 1 1 0 1 OUTxE0 Port Number Pin Name 0 - Output disabled 1 Port 0 OUTx pin 0 Port 1 OUTx_1 pin 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 281 CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 4 (EPFR4) to extended port function register 5 (EPFR5) [bit7 to bit0]: INxE1, INxE0 (Input capture input pin select bits) 2 input pins for 32-bit input capture are provided for each channel. These bits select the pins used by ch.0 to ch.7 for 32-bit input capture. The IN0E1 and IN0E0 bits correspond to ch.0, the IN1E1 and IN1E0 bits correspond to ch.1,..., and the IN7E1 and IN7E0 bits correspond to ch.7. INxE1 0 1 282 INxE0 Port Number Pin Name 0 Port 0 INx pin 1 Port 1 INx_1 pin 0 - Setting prohibited 1 - Setting prohibited FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 6 (EPFR6) [bit7 to bit5]: SOUT0E2 to SOUT0E0 (Serial interface ch.0 serial data pin select bits) These bits select one pin from the SOUT0 and SOUT0_1 pins to assign the serial data output function of multifunction serial interface ch.0 to the pin. SOUT0E2 0 SOUT0E1 0 1 1 0 1 SOUT0E0 Port Number Pin Name 0 - Output disabled (Input: SOUT0 pin (Port 0)) 1 Port 0 SOUT0 pin 0 Port 1 SOUT0_1 pin 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. • The pins selected by the following bits must be assigned to the same port number: - SOUT0E2 to SOUT0E0 (serial data output pins) - SCK0E2 to SCK0E0 (serial clock I/O pins) - SIN0E1, SIN0E0 (serial data input pins) • The serial data pins operate as input pins according to peripheral function settings. The input of a peripheral function is always connected to the selected pin, and if these bits are set to "000", the input is connected to the SOUT0 pin (port 0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 283 CHAPTER 13 I/O Ports 13.4 MB91625 Series [bit4 to bit2]: SCK0E2 to SCK0E0 (Serial interface ch.0 serial clock pin select bits) These bits select one pin from the SCK0 and SCK0_1 pins to assign the serial clock I/O function of multifunction serial interface ch.0 to the pin. SCK0E2 0 SCK0E1 0 1 1 0 1 SCK0E0 Port Number Pin Name 0 - Output disabled (Input: SCK0 pin (Port 0)) 1 Port 0 SCK0 pin 0 Port 1 SCK0_1 pin 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. • The pins selected by the following bits must be assigned to the same port number: - SOUT0E2 to SOUT0E0 (serial data output pins) - SCK0E2 to SCK0E0 (serial clock I/O pins) - SIN0E1, SIN0E0 (serial data input pins) • 284 The input of a peripheral function is always connected to the selected pin, and if these bits are set to "000", the input is connected to the SCK0 pin (port 0). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series [bit1, bit0]: SIN0E1, SIN0E0 (Serial interface ch.0 serial data input select bits) These bits select one pin from the SIN0 and SIN0_1 pins to assign the serial data input function of multifunction serial interface ch.0 to the pin. SIN0E1 0 1 SIN0E0 Port Number Pin Name 0 Port 0 SIN0 pin 1 Port 1 SIN0_1 pin 0 - Setting prohibited 1 - Setting prohibited <Note> The pins selected by the following bits must be assigned to the same port number: - SOUT0E2 to SOUT0E0 (serial data output pins) - SCK0E2 to SCK0E0 (serial clock I/O pins) - SIN0E1, SIN0E0 (serial data input pins) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 285 CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 7 (EPFR7) to extended port function register 17 (EPFR17) [bit4, bit3] SOUTxE1, SOUTxE0 (Serial interface ch.1 to ch.11 serial data pin select bit) These bits select whether to enable the serial data output pin of each channel in multifunction serial interface ch.1 to ch.11. The SOUT1E1 and SOUT1E0 bits correspond to ch.1, the SOUT2E1 and SOUT2E0 bits correspond to ch.2,..., and the SOUT11E1 and SOUT11E0 bits correspond to ch.11. SOUTxE1 SOUTxE0 Port Number Pin Name 0 0 - Output disabled (Input: SOUTx pin (Port 0)) 0 1 Port 0 SOUTx pin 1 0 - Setting prohibited 1 1 - Setting prohibited <Note> 286 • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the pins are not used as output pins for other functions when output has been disabled by the bits, the pins can be used as general-purpose port. • Serial data pins operate as input pins according to peripheral function settings. The input of a peripheral function is always connected to the selected pin, and if these bits are set to "00", the input is connected to the SOUTx pin (port 0). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series [bit2, bit1] SCKxE1, SCKxE0 (Serial interface ch.1 to ch.11 serial clock pin select bits) These bits select whether to enable the serial clock I/O pin of each channel in multifunction serial interface ch.1 to ch.11. The SCK1E1 and SCK1E0 bits correspond to ch.1, the SCK2E1 and SCK2E0 bits correspond to ch.2,..., and the SCK11E1 and SCK11E0 bits correspond to ch.11. SCKxE1 SCKxE0 Port Number Pin Name 0 0 - Output disabled (Input: SCKx pin (Port0)) 0 1 Port 0 SCKx pin 1 0 - Setting prohibited 1 1 - Setting prohibited <Note> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the pins are not used as output pins for other functions when output has been disabled by the bits, the pins can be used as general-purpose port. • The input of the serial clock is always connected to the selected pin, and if these bits are set to "00", the input is connected to the SCKx pin (port 0). [bit0] SINxE (Serial interface ch.1 to ch.11 serial data input select bit) This bit selects one pin to assign it as the serial data input pin of multifunction serial interface ch.1 to ch.11. Always set "0" to this bit. SINxE Port Number Pin Name 0 Port 0 SINx pin 1 - Setting prohibited ● Extended port function register 18 (EPFR18) [bit7 to bit0]: UDINxE1, UDINxE0 (Up/Down counter input pin select bits) 2 pins are provided for use by each channel in ch.0 to ch.3 of the 16-bit up/down counter. These bits select one of the pins as the pin used by each channel in the 16-bit up/down counter. The UDIN0E1 and UDIN0E0 bits correspond to ch.0, the UDIN1E1 and UDIN1E0 bits correspond to ch.1,..., and the UDIN3E1 and UDIN3E0 bits correspond to ch.3. CM71-10151-2E UDINxE1 UDINxE0 Port Number Pin Name 0 0 Port 0 AINx/BINx/ZINx pins 0 1 Port 1 AINx_1/BINx_1/ZINx_1 pins 1 0 - Setting prohibited 1 1 - Setting prohibited FUJITSU MICROELECTRONICS LIMITED 287 CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 19 (EPFR19) [bit3 to bit1]: ADTRG0E2 to ADTRG0E0 (A/D conversion activation trigger pin select bits) 3 external trigger input pins for 10-bit A/D converter are provided. ADTRG0E2 ADTRG0E1 ADTRG0E0 Port Number 0 0 0 Port 0 ADTRG0 pin 1 Port 1 ADTRG0_1 pin 0 Port 2 ADTRG0_2 pin 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited 0 - Setting prohibited 1 - Setting prohibited 1 1 0 1 Pin Name [bit0]: XAE (Clock oscillation I/O pin enable bit) This bit cuts off port input when the low-speed clock oscillation function is enabled. Always set XAE = 1 when the low-speed clock oscillation function is enabled. Written Value Explanation 0 Enables port input. 1 Disables port input. <Note> These pins can be used as general-purpose port when the low-speed oscillation function has been disabled by this bit. 288 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 20 (EPFR20) to extended port function register 27 (EPFR27) [bit5, bit4, bit2, bit1]: TIOAxE1, TIOAxE0 (Base timer ch.0 to ch.15 pin select bits) These bits select whether to enable the output pin of each channel in base timer ch.0 to ch.15. The TIOA0E1 and TIOA0E0 bits correspond to ch.0, the TIOA1E1 and TIOA1E0 bits correspond to ch.1,..., and the TIOA15E1 and TIOA15E0 bits correspond to ch.15. TIOAxE1 TIOAxE0 Port Number Pin Name 0 0 - Output disabled (Odd-numbered channel input: TIOAx pin (Port 0)) 0 1 Port 0 TIOAx pin 1 0 - Setting prohibited 1 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. • The base timer output pins (TIOAx pins) of the odd-numbered channels (TIOAx pin) operate as input pins according peripheral function settings. The input of a peripheral function is always connected to the selected pin. If these bits are set to "00", the input is connected to the TIOAx pin (port 0). [bit3, bit0]: TIOBxE (Base timer ch.0 to ch.15 pin input select bits) These bits select whether to enable the input pin of each channel in base timer ch.0 to ch.15. The TIOB0E bit corresponds to ch.0, the TIOB1E bit corresponds to ch.1,..., and the TIOB15E bit corresponds to ch.15. TIOBxE CM71-10151-2E Port Number Pin Name 0 Port 0 TIOBx pin 1 - Setting prohibited FUJITSU MICROELECTRONICS LIMITED 289 CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 28 (EPFR28), extended port function register 29 (EPFR29) INT15E to INT0E (External interrupt request pin enable bits) These bits select whether to enable the input pin of each channel in external interrupt request ch.0 to ch.15. The INT0E bit corresponds to ch.0, the INT1E bit corresponds to ch.1,..., and the INT15E bit corresponds to ch.15. INTxE Port Number Pin Name 0 Port 0 INTx pin 1 - Setting prohibited ● Extended port function register 30 (EPFR30) [bit3 to bit0]: INT19E to INT16E (External interrupt request pin enable bits) 2 input pins are provided for each channel in external interrupt request ch.16 to ch.19. These bits select one of the pins as the pin used by each channel in external interrupt request ch.16 to ch.19. The INT16E bit corresponds to ch.16, the INT17E bit corresponds to ch.17, ... , and the INT19E bit corresponds to ch.19. INTxE Port Number Pin Name 0 Port 0 INTx pin 1 Port 1 INTx_1 pin ● Extended port function register 31 (EPFR31) [bit6 to bit1]: INT23E1, INT23E0 to INT21E1, INT21E0 (External interrupt request pin enable bits) 3 input pins are provided for each channel in external interrupt request ch.21 to ch.23. These bits select one of the pins as the pin used by each channel in external interrupt request ch.21 to ch.23. The INT21E1 and INT21E0 bits correspond to ch.21, the INT22E1 and INT22E0 bits correspond to ch.22, and the INT23E1 and INT23E0 bits correspond to ch.23. INTxE1 INTxE0 Port Number Pin Name 0 0 Port 0 INTx pin 0 1 Port 1 INTx_1 pin 1 0 Port 2 INTx_2 pin 1 1 - Setting prohibited [bit0]: INT20E (External interrupt request pin enable bit) 2 input pins are provided for external interrupt request ch.20. This bit selects one of the pins as the pin used by external interrupt request ch.20. INT20E 290 Port Number Pin Name 0 Port 0 INT20 pin 1 Port 1 INT20_1 pin FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series ● Extended port function register 32 (EPFR32) [bit7 to bit0]: INT31E to INT24E (External interrupt request pin enable bits) These bits select whether to enable the input pin of each channel in external interrupt request ch.24 to ch.31. The INT24E bit corresponds to ch.24, the INT25E bit corresponds to ch.25, ..., and the INT31E bit corresponds to ch.31. INTxE Port Number Pin Name 0 Port 0 INTx pin 1 - Setting prohibited ● Extended port function register 33 (EPFR33) [bit5, bit4, bit2, bit1]: TMOxE1, TMOxE0 (Reload timer ch.0 to ch.1 output pin select bits) 2 output pins are provided for each channel in 16-bit reload timer ch.0 and ch.1. These bits select one of the pins as the pin used by each of 16-bit reload timer ch.0 and ch.1. The TMO0E1 and TMO0E0 bits correspond to ch.0, and the TMO1E1 and TMO1E0 bits correspond to ch.1. TMOxE1 0 1 TMOxE0 Port Number Pin Name 0 - Output disabled 1 Port 0 TMOx pin 0 Port 1 TMOx_1 pin 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. • The pins used for the same channel (the pins selected by the following bits) must be assigned to the same port number: - TMOxE1, TMOxE0 (16-bit reload timer output pins) - TMIxE (16-bit reload timer input pin) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 291 CHAPTER 13 I/O Ports 13.4 MB91625 Series [bit3, bit0]: TMIxE (Reload timer ch.0 to ch.1 input pin select bits) 2 input pins are provided for each channel in 16-bit reload timer ch.0 and ch.1. These bits select one of the pins as the pin used by each of 16-bit reload timer ch.0 and ch.1. The TMI0E bit corresponds to ch.0, and the TMI1E bit corresponds to ch.1. TMIxE Port Number Pin Name 0 Port 0 TMIx pin 1 Port 1 TMIx_1 pin <Note> The pins used for the same channel (the pins selected by the following bits) must be assigned to the same port number: • TMOxE1, TMOxE0 (16-bit reload timer output pins) • TMIxE (16-bit reload timer input pin) ● Extended port function register 34 (EPFR34) [bit6, bit5]: TMO2E1, TMO2E0 (Reload timer ch.2 output pin select bits) 2 output pins are provided for 16-bit reload timer ch.2. This bit selects one of the pins as the pin used by 16-bit reload timer ch.2. TMO2E1 0 1 TMO2E0 Port Number Pin Name 0 - Output disabled 1 Port 0 TMO2 pin 0 Port 1 TMO2_1 pin 1 - Setting prohibited <Notes> • The corresponding pins can be used as output pins for other functions when output has been disabled by these bits. • If the corresponding pins are not used as output pins for other functions when output has been disabled by these bits, the pins can be used as general-purpose port. • The pins selected by the following bits must be assigned to the same port number: - TMO2E1, TMO2E0 (16-bit reload timer output pins) - TMI2E (16-bit reload timer I/O pin) 292 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series [bit4]: TMI2E (Reload timer ch.2 input pin select bit) 2 input pins are provided for 16-bit reload timer ch.2. This bit selects one of the pins as the pin used by 16-bit reload timer ch.2. TMI2E Port Number Pin Name 0 Port 0 TMI2 pin 1 Port 1 TMI2_1 pin <Note> The pins selected by the following bits must be assigned to the same port number: • TMO2E1, TMO2E0 (16-bit reload timer output pins) • TMI2E (16-bit reload timer I/O pin) [bit3 to bit0]: FRCKxE1, FRCKxE0 (Free-run timer ch.0 and ch.1 input pin select bits) 2 input pins are provided for each channel in 32-bit free-run timer ch.0 and ch.1. These bits select one of the pins as the pin used by each of 32-bit free-run timer ch.0 and ch.1. FRCKxE1 FRCKxE0 0 0 Port 0 FRCKx pin 1 Port 1 FRCKx_1 pin 0 - Setting prohibited 1 - Setting prohibited 1 CM71-10151-2E Port Number Pin Name FUJITSU MICROELECTRONICS LIMITED 293 CHAPTER 13 I/O Ports 13.4 13.4.4 MB91625 Series Port Data Registers (PDR0 to PDRK) These registers store I/O data. The values read from or written to these registers vary depending on the settings of a port data direction register (DDR0 to DDRK) and port function register (PFR0 to PFRA). For details of a read value or written value, see "13.4.1 Port Data Direction Registers (DDR0 to DDRK)". Figure 13.4-4 shows the bit configuration of the port data registers (PDR0 to PDRK). Figure 13.4-4 Bit configuration of the port data registers (PDR0 to PDRK) 7 6 5 4 3 2 1 0 Initial value Attribute PDR0 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 XXXX XXXX R/W PDR1 PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 XXXX XXXX R/W PDR2 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 XXXX XXXX R/W PDR3 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30 XXXX XXXX R/W PDR4 PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40 XXXX XXXX R/W PDR5 PDR57 PDR56 PDR55 PDR54 PDR53 PDR52 PDR51 PDR50 XXXX XXXX R/W PDR6 PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60 XXXX XXXX R/W PDR7 PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70 XXXX XXXX R/W PDR8 PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80 XXXX XXXX R/W PDR92 PDR91 PDR90 XXXX XXXX R/W PDRA2 PDRA1 PDRA0 XXXX XXXX R/W PDRK2 PDRK1 PDRK0 XXXX XXXX R/W bit PDR9 PDRA PDRK Undefined Undefined Undefined Undefined Undefined PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 Undefined Undefined Undefined Undefined Undefined R/W: Read/Write X: Undefined <Notes> • If these registers are read with a read-modify-write instruction, the value of these registers is read regardless of the settings of the following registers: - Port data direction registers (DDR0 to DDRK) - Port function registers (PFR0 to PFRA) • 294 The value of these registers is not initialized even when this device is reset. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series 13.4.5 Pull-up Resistor Control Registers (PCR0 to PCRK) These registers set pull-up resistors. One bit is provided for each of the pins for which pull-up resistors can be set, and a pull-up resistor can be set in the corresponding pin by writing "1" to the bit corresponding to the pin. Figure 13.4-5 shows the bit configuration of the pull-up resistor control registers (PCR0 to PCRK). Figure 13.4-5 Bit configuration of the pull-up resistor control registers (PCR0 to PCRK) 7 6 5 4 3 2 1 0 Initial value Attribute PCR0 PCR07 PCR06 PCR05 PCR04 PCR03 PCR02 PCR01 PCR00 0000 0000 R/W PCR1 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 0000 0000 R/W PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 0000 0000 R/W PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 0000 0000 R/W PCR7 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 0000 0000 R/W PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 0000 0000 R/W PCR92 PCR91 PCR90 XXXX X000 R/W PCRA2 PCRA1 PCRA0 0000 0000 R/W bit PCR9 PCRA PCRK Undefined Undefined Undefined Undefined Undefined PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 Undefined Undefined Undefined Undefined Undefined PCRK2 Undefined Undefined XXXX X0XX R/W R/W: Read/Write X: Undefined Each bit in the pull-up resistor control registers specifies whether a pull-up resistor is set for the assigned pin. When a pull-up this register is set, the pull-up resistor is connected to the pin. Written Value Explanation 0 The pull-up resistor is not set. 1 The pull-up resistor is set. <Note> Pull-up resistors are not set in the following cases regardless of the settings of these registers: - In port output (in peripheral function output) - In stop mode (with Hi-Z selected) - When D/A analog output is enabled (only for port 9) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 295 CHAPTER 13 I/O Ports 13.4 13.4.6 MB91625 Series A/D Channel Enable Register (ADCHE) This register specifies whether to input analog signals from the AN0 to AN15 pins. One bit is provided for each of the pins for which A/D analog input can be set, and A/D analog input can be enabled for the corresponding pin by writing "1" to the bit corresponding to the pin. Figure 13.4-6 shows the bit configuration of the A/D channel enable register (ADCHE). Figure 13.4-6 Bit configuration of the A/D channel enable register (ADCHE) bit 31 Attribute Initial value 24 23 0 Undefined ADE23 to ADE0 - R/W XXXX XXXX 1111 1111 1111 1111 1111 1111 R/W: Read/Write X: Undefined [bit31 to bit24]: Undefined bit In case of writing Ignored. In case of reading A value is undefined. [bit23 to bit16]: ADE23 to ADE16 (Port function disable bits) These bits enables/disables port function from the pin corresponding to the bit. Written Value Explanation 0 Enables port function. 1 Disables port function. [bit15 to bit0]: ADE15 to ADE0 (Analog input enable bits) These bits enables/disables analog signal input from the pin corresponding to the bit. Written Value Explanation 0 Disables analog signal input. 1 Enables analog signal input. The ADE15 bit corresponds to ch.15, the ADE14 bit corresponds to ch.14, the ADE13 bit corresponds to ch.13, ..., the ADE1 bit corresponds to ch.1, and the ADE0 bit corresponds to ch.0. 296 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.4 MB91625 Series <Notes> • To use any of the AN0 to AN15 pins as analog signal input pins of the 10-bit A/D converter, be sure to write "1" to the bits corresponding to the channels. • When analog input is enabled and the port function is disabled through the settings of this register, input from ports and peripheral functions is fixed at "0" and output to them is fixed at Hi-Z regardless of the settings of the port function registers (PFR0 to PFRA) or extended port function registers (EPFR0 to EPFR34). • PA7 to PA0 cannot be used neither as general-purpose ports nor peripheral functions unless setting the corresponding port function disable bits ADE23 to ADE16 to "0". Be sure to set "0" to these bits. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 297 CHAPTER 13 I/O Ports 13.5 MB91625 Series 13.5 Notes on Use Note the following points about using I/O ports: • The order of priority of registers is as follows: 1. A/D channel enable register (ADCHE), D/A control registers (DACR0, DACR1) 2. Port function registers (PFR0 to PFRA) 3. Extended port function registers (EPFR0 to EPFR34) If settings are inconsistent, the setting with the higher order of priority is used. • When output from the 8-bit D/A converter is enabled by the DAE bit (DAE = 1) of the D/A control registers (DACR0, DACR1), input from ports is fixed at "0" and output from ports is fixed at Hi-Z. For details of the D/A control registers (DACR0, DACR1), see "CHAPTER 25 8-bit D/A Converter". • When analog input is enabled by the A/D channel enable register (ADCHE), input from ports is fixed at "0" and output from ports is fixed at Hi-Z. • If multiple functions are assigned to one pin, the order of priority is as follows: 1. X0A/X1A 2. Multifunction serial interface 3. Base timer 4. 16-bit reload timer 5. 32-bit output compare • A single pin cannot be used as an output pin for multiple peripheral functions. Also, a single output function cannot be assigned to multiple pins. • A single pin can be used as an input pin for multiple peripheral functions. However, a single input function cannot be assigned to multiple pins. • If Hi-Z is set to a pin in standby mode (stop mode/watch mode/main timer mode), input is fixed at "0". However, input is not fixed at "0" for external interrupt requests whose generation is enabled and it can be used. • Before changing the pin to which a peripheral function output is assigned, set port input mode for the relevant pins (the pin to which the function is currently assigned and the pin to which it will be assigned) and disable the assigned peripheral function. • Before changing the pin to which a peripheral function input is assigned, disable the assigned peripheral function. • To use PK0 and PK1 as low-speed oscillation pins, set the I/O directions of the ports to input (DDRK0 = 0, DDRK1 = 0) in port data direction register K (DDRK). • The pin to which peripheral functions are assigned can be set, if the peripheral functions can be assigned to more than one pin, and peripheral function output from the pin can be enabled/disabled. However, if the peripheral function has more than one I/O, each I/O must be set to individual ports belonging to the same group. 298 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 13 I/O Ports 13.5 MB91625 Series Example: Ch.0 multifunction serial interface settings Serial Data Output Serial Clock I/O SOUT0 pin (Port 0) SCK0 pin (Port 0) SCK0_1 pin (Port 1) Serial Data Input Effective port SIN0 pin (Port 0) Port 0 SIN0_1 pin (Port 1) Setting prohibited SIN0 pin (Port 0) SIN0_1 pin (Port 1) SOUT0_1 pin (Port 1) SCK0 pin (Port 0) SIN0 pin (Port 0) SIN0_1 pin (Port 1) SCK0_1 pin (Port 1) SIN0 pin (Port 0) SIN0_1 pin (Port 1) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED Port 1 299 CHAPTER 13 I/O Ports 13.5 300 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers This chapter explains the functions and operations of external interrupt controllers. 14.1 Overview 14.2 Configuration 14.3 Pins 14.4 Registers 14.5 Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 301 CHAPTER 14 External Interrupt Controllers 14.1 MB91625 Series 14.1 Overview The external interrupt controllers detect edges/levels in external interrupt signals, and they control external interrupt requests. This series has 32 built-in signal input pins for external interrupts. ■ Overview An external interrupt controller generates an external interrupt request when it detects a preset edge/level in an external interrupt signal. The edge/level to be detected can be selected from the following 4 types: • "H" level • "L" level • Rising edge • Falling edge Also, external interrupt requests can be used for a return from sleep mode or standby mode (watch mode or stop mode). 302 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.2 MB91625 Series 14.2 Configuration This section shows the configuration of an external interrupt controller. ■ Block diagram of an external interrupt controller Figure 14.2-1 is a block diagram of an external interrupt controller. Figure 14.2-1 Block diagram of an external interrupt controller Peripheral bus 16 8 8 Enable interrupt request register (ENIR0 to ENIR3) 7 6 5 4 3 2 1 0 External interrupt request register (EIRR0 to EIRR3) External interrupt request level register (ELVR0 to ELVR3) 7 15 14 6 5 4 3 2 1 0 8 1 0 Edge/Level detection circuit 32 INT0 to INT31 Interrupt request 32 • External interrupt request level register (ELVR0 to ELVR3) This register sets the edge/level used to determine whether a signal input to the INT0 to INT31 pins is for an external interrupt request. • External interrupt request register (EIRR0 to EIRR3) This register maintains the states of interrupt sources (indicating which pins have generated external interrupt requests). • Enable interrupt request register (ENIR0 to ENIR3) This register specifies whether external interrupt requests are enabled/disabled. • Edge/Level detection circuit This circuit detects edges/levels in signals input to the INT0 to INT31 pins. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 303 CHAPTER 14 External Interrupt Controllers 14.2 MB91625 Series ■ Clocks Table 14.2-1 lists the clock used by the external interrupt controllers. Table 14.2-1 Clock used by the external interrupt controllers Clock Name Operation clock 304 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.3 MB91625 Series 14.3 Pins This section explains the pins of the external interrupt controllers. ■ Overview The external interrupt controllers have the following pins: • INT0 to INT31 pins These are external interrupt signal input pins. These pins are multiplexed pins. For details of using the INT0 to INT31 pins of the external interrupt controllers, see "2.4 Setting Method for Pins". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 305 CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series 14.4 Registers This section explains the configurations and functions of the registers for the external interrupt controllers. ■ List of registers for the external interrupt controllers Table 14.4-1 lists the registers for the external interrupt controllers. Table 14.4-1 Registers for the external interrupt controllers Channel Common 306 Abbreviated Register Name Register Name Reference ELVR0 External interrupt request level register 0 14.4.1 EIRR0 External interrupt request register 0 14.4.2 ENIR0 Enable interrupt request register 0 14.4.3 ELVR1 External interrupt request level register 1 14.4.1 EIRR1 External interrupt request register 1 14.4.2 ENIR1 Enable interrupt request register 1 14.4.3 ELVR2 External interrupt request level register 2 14.4.1 EIRR2 External interrupt request register 2 14.4.2 ENIR2 Enable interrupt request register 2 14.4.3 ELVR3 External interrupt request level register 3 14.4.1 EIRR3 External interrupt request register 3 14.4.2 ENIR3 Enable interrupt request register 3 14.4.3 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series 14.4.1 External Interrupt Request Level Registers (ELVR0 to ELVR3) These registers set the edges/levels to be detected for external interrupt requests. Figure 14.4-1 shows the bit configuration of the external interrupt request level registers (ELVR0 to ELVR3). Figure 14.4-1 Bit configuration of the external interrupt request level registers (ELVR0 to ELVR3) External interrupt request level register 0 (ELVR0) bit Attribute Initial value bit Attribute Initial value 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 External interrupt request level register 1 (ELVR1) bit Attribute Initial value bit Attribute Initial value 15 14 13 12 11 10 9 8 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 (Continued) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 307 CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series (Continued) External interrupt request level register 2 (ELVR2) bit Attribute Initial value bit Attribute Initial value 15 14 13 12 11 10 9 8 LB23 LA23 LB22 LA22 LB21 LA21 LB20 LA20 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LB19 LA19 LB18 LA18 LB17 LA17 LB16 LA16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 External interrupt request level register 3 (ELVR3) bit Attribute Initial value bit Attribute Initial value 15 14 13 12 11 10 9 8 LB31 LA31 LB30 LA30 LB29 LA29 LB28 LA28 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LB27 LA27 LB26 LA26 LB25 LA25 LB24 LA24 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W: Read/Write 308 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series LB31 to LB0, LA31 to LA0 (Detection condition selection bits) These bits select the edges/levels to be detected in signals for external interrupt requests. An external interrupt request is recognized upon detection of the edge/level selected by one of these bits. The LB0 to LB31 bits correspond to the INT0 to INT31 bits, and the LA0 to LA31 bits similarly correspond to the INT0 to INT31 bits. For example, the INT0 pin is set with the LB0 and LA0 bits. LB31 to LB0 LA31 to LA0 Explanation 0 0 "L" level detection 0 1 "H" level detection 1 0 Rising edge detection 1 1 Falling edge detection To use an external interrupt request to return from standby mode, see "14.5.2 Return from Standby Mode". <Notes> • For detection of an edge/level specified by these bits, the pulse width of the signal must be 3T or higher (T: Peripheral clock (PCLK) period). If a signal with a narrower pulse width is input, this device may not operate correctly. • While "L" level detection/"H" level detection is set as the detection condition, the state of an interrupt source is maintained in the external interrupt request registers (EIRR0 to EIRR3) even if the corresponding external interrupt request is canceled. Therefore, the external interrupt request remains at the interrupt controller, to which it has been output. To cancel the external interrupt request output to the interrupt controller, set "0" in the corresponding bit in the external interrupt request register (EIRR0 to EIRR3). However, even when the external interrupt request register (EIRR0 to EIRR3) is cleared, the external interrupt request remains as is while any signals at the effective level are input from the INT0 to INT31 pins. For diagrams illustrating operations that maintain the state of an interrupt source or clear an interrupt source, see "■ Canceling an external interrupt request" of "14.5 Explanation of Operations and Setting Procedure Examples". • If the detection condition is changed by rewriting these bits, an incorrect interrupt source may be generated. To prevent incorrect interrupt sources from being generated when the detection condition has been changed, perform the following operations: 1. Read the external interrupt request level register (ELVR0 to ELVR3). 2. Write "0" in the external interrupt request register (EIRR0 to EIRR3) to clear the interrupt source. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 309 CHAPTER 14 External Interrupt Controllers 14.4 14.4.2 MB91625 Series External Interrupt Request Registers (EIRR0 to EIRR3) These registers maintain the states of interrupt sources of external interrupt requests (indicating which pins have generated the external interrupt requests). Figure 14.4-2 shows the bit configuration of the external interrupt request registers (EIRR0 to EIRR3). Figure 14.4-2 Bit configuration of the external interrupt request registers (EIRR0 to EIRR3) External interrupt request register 0 (EIRR0) bit Attribute Initial value 7 6 5 4 3 2 1 0 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 External interrupt request register 1 (EIRR1) bit Attribute Initial value 7 6 5 4 3 2 1 0 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 External interrupt request register 2 (EIRR2) bit Attribute Initial value 7 6 5 4 3 2 1 0 ER23 ER22 ER21 ER20 ER19 ER18 ER17 ER16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 External interrupt request register 3 (EIRR3) bit Attribute Initial value 7 6 5 4 3 2 1 0 ER31 ER30 ER29 ER28 ER27 ER26 ER25 ER24 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W: Read/Write 310 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series ER31 to ER0 (External interrupt request flag bits) These bits indicate that external interrupt requests have been detected. The ER0 to ER31 bits correspond to the INT0 to INT31 pins. For example, the ER0 bit is used to detect external interrupt requests from the INT0 pin, and the ER31 bit is used to detect external interrupt requests from the INT31 pin. An external interrupt request is generated when "1" is set in any of the EN0 to EN31 bits of an enable interrupt request register (ENIR0 to ENIR3) and the corresponding bit among the ER0 to ER31 bits becomes "1". ER31 to ER0 In Case of Reading In Case of Writing 0 No external interrupt request has been detected. The interrupt source is cleared. 1 An external interrupt request has been detected. Ignored <Notes> • When a read-modify-write instruction is used, "1" is read. • As long as a signal at the effective level is being input from any of the INT0 to INT 31 pins when "L" level detection/"H" level detection has been set as the detection condition by an external interrupt request level register (ELVR0 to ELVR3), "1" is set in the corresponding bit among the ER31 to ER0 bits even after the bit is cleared. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 311 CHAPTER 14 External Interrupt Controllers 14.4 14.4.3 MB91625 Series Enable Interrupt Request Registers (ENIR0 to ENIR3) These registers enable/disable external interrupt requests. Figure 14.4-3 shows the bit configuration of the enable interrupt request registers (ENIR0 to ENIR3). Figure 14.4-3 Bit configuration of the enable interrupt request registers (ENIR0 to ENIR3) Enable interrupt request register 0 (ENIR0) bit Attribute Initial value 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Enable interrupt request register 1 (ENIR1) bit Attribute Initial value 7 6 5 4 3 2 1 0 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Enable interrupt request register 2 (ENIR2) bit Attribute Initial value 7 6 5 4 3 2 1 0 EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Enable interrupt request register 3 (ENIR3) bit Attribute Initial value 7 6 5 4 3 2 1 0 EN31 EN30 EN29 EN28 EN27 EN26 EN25 EN24 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W: Read/Write 312 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.4 MB91625 Series EN31 to EN0 (Interrupt enable bits) These bits enable/disable external interrupts. Each of the EN0 to EN31 bits corresponds to the respective bits of the external interrupt request registers (EIRR0 to EIRR3). Written Value CM71-10151-2E Explanation 0 Disables generation of external interrupt requests. The states of interrupt sources are maintained, but external interrupt requests are not output. 1 Enables generation of external interrupt requests. External interrupt requests are output. FUJITSU MICROELECTRONICS LIMITED 313 CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series 14.5 Explanation of Operations and Setting Procedure Examples This section explains the operations of the external interrupt controllers and provides examples of setting procedures. 14.5.1 Operations of the External Interrupt Controllers ■ Overview If external interrupts are enabled, an external interrupt controller outputs an external interrupt request when it detects a preset edge/level in a signal input to an external signal input pin. The edge/level to be detected can be selected from the following 4 types: - "H" level - "L" level - Rising edge (Only when return from standby mode "L" level detection at the INT0 to INT7 pins, and rising edge detection at the INT8 to INT31 pins) - Falling edge (Only when return from standby mode "H" level detection at the INT0 to INT7 pins, and falling edge detection at the INT8 to INT31 pins) If an interrupt request from another peripheral device is generated at the same time, the interrupt controller determines their order of priority. An external interrupt is generated for the external interrupt request that has the higher priority. Figure 14.5-1 shows operation with the external interrupt controllers. Figure 14.5-1 Operation with the external interrupt controllers External interrupt Interrupt requests controllers from peripheral functions ELVR Interrupt controller Interrupt request level ICRyy Comparator EIRR ENIR CPU ICRxx Comparator ILM Interrupt source ICR ILM ELVR EIRR ENIR 314 : Interrupt control register (ICR00 to ICR47) : Interrupt level mask register (ILM) : External interrupt request level register (ELVR0 to ELVR3) : External interrupt request register (EIRR0 to EIRR3) : Enable interrupt request register (ENIR0 to ENIR3) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series ■ Setting procedure To set an external interrupt, follow the procedure below. 1. Disable external interrupts by using an enable interrupt request register (ENIR0 to ENIR3). 2. Change the detection condition (effective edge /level) by using an external interrupt request level register (ELVR0 to ELVR3). 3. Read the external interrupt request level register (ELVR0 to ELVR3). 4. Clear interrupt sources by using an external interrupt request register (EIRR0 to EIRR3). 5. Enable external interrupts by using the enable interrupt request register (ENIR0 to ENIR3). <Notes> • Before making settings for the external interrupt controller, disable external interrupts by using an enable interrupt request register (ENIR0 to ENIR3). • Before enabling output of external interrupt requests, clear interrupt sources by using an external interrupt request register (EIRR0 to EIRR3). ■ Control operations Each external interrupt controller issues external interrupt requests to the interrupt controller in the following sequence: 1. The external interrupt controller detects the edge/level specified by an external interrupt request level register (ELVR0 to ELVR3) in a signal input to any of the INT0 to INT31 pins. 2. The external interrupt controller determines whether external interrupts are enabled by checking the enable interrupt request registers (ENIR0 to ENIR3). 3. If external interrupts are enabled, the external interrupt controller outputs an external interrupt request to the interrupt controller. ■ Canceling an external interrupt request While "L" level detection/"H" level detection is set as the detection condition for external interrupts, the state of an interrupt source is maintained in the external interrupt request registers (EIRR0 to EIRR3) even if the corresponding external interrupt request is canceled. Therefore, the external interrupt remains at the interrupt controller, to which a request for it has been output. To cancel the external interrupt request output to the interrupt controller, set "0" in the corresponding bit in an external interrupt request register (EIRR0 to EIRR3). This operation clears the interrupt source, and the external interrupt request is canceled. However, even when the external interrupt request register (EIRR0 to EIRR3) is cleared, the external interrupt remains at the interrupt controller, to which for a request it has been output, while any signals at the effective level are input from the INT0 to INT31 pins. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 315 CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series Figure 14.5-2 shows the state of an interrupt source being maintained, and Figure 14.5-3 shows the clearing of an interrupt source. Figure 14.5-2 Maintaining the state of an interrupt source Input of external interrupt request Edge/Level detection External interrupt request register (EIRR0 to EIRR3) Gate Interrupt controller Interrupt source maintained in same state even after cancellation of external interrupt request Figure 14.5-3 Clearing of an interrupt source INT input "H" level detection is set (LBx bit, LAx bit = 01 in ELVR) "H" level Interrupt request output Interrupt request canceled by writing of "0" to EIRR ELVR: External interrupt request level register (ELVR0 to ELVR3) EIRR: External interrupt request register (EIRR0 to EIRR3) 316 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series 14.5.2 Return from Standby Mode ■ Overview External interrupt requests can be used for a return from standby mode (watch mode or stop mode). A signal already input to any of the INT0 to INT31 pins in standby mode in asynchronous input can be used for a return from standby mode. ■ Settings Before a transition to standby mode, the following setting for the INT0 to INT31 pins must be made with the enable interrupt request registers (ENIR0 to ENIR3): - Pins used for the return from standby mode: Enable interrupt request output. - Pins not used for the return from standby mode: Disable interrupt request output. ■ Return operation This device returns from standby mode when the effective level is detected in a signal input to the INT0 to INT31 pins in standby mode. Table 14.5-1 shows the relationship between external interrupt request detection conditions and the levels for returning from standby mode. Table 14.5-1 Relationship between external interrupt request detection conditions and the levels for returning from standby mode Detection Condition LB31 to LB0 LA31 to LA0 Level for Returning from Standby Mode "L" level detection 0 0 "L" level detection "H" level detection 0 1 "H" level detection Rising edge detection 1 0 "L" level detection at the INT0 to INT7 pins, and rising edge detection at the INT8 to INT31 pins Falling edge detection 1 1 "H" level detection at the INT0 to INT7 pins, and falling edge detection at the INT8 to INT31 pins After this device returns from standby mode, other external interrupt requests cannot be recognized until the oscillation stabilization wait time has elapsed. To output an external interrupt request after this device returns from standby mode, input an external interrupt request signal after the oscillation stabilization wait time has elapsed. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 317 CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series Figure 14.5-4 shows an example of operation at the time of return from standby mode, where the INT0 and INT1 pins are used. Figure 14.5-4 Operation when returning from standby mode INT1 INT0 Internal STOP Internal operation (RUN) Instruction execution (run) X0 Peripheral clock (PCLK) Clearing of external interrupt request flag ER0 EN0 "1" (enabled before transition to standby mode) ER1 EN1 "1" (enabled before transition to standby mode) STANDBY ER1, ER0 EN1, EN0 STANDBY RUN 318 Oscillation stabilization wait time RUN : ER1 and ER0 bits of external interrupt request register 0 (EIRR0) : EN1 and EN0 bits of enable interrupt request register 0 (ENIR0) : Standby mode : Active FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 14 External Interrupt Controllers 14.5 MB91625 Series 14.5.3 Return from Sleep Mode ■ Overview External interrupt requests can be used for a return from sleep mode. ■ Settings Before a transition to sleep mode, the following setting for the INT0 to INT31 pins must be made with the enable interrupt request registers (ENIR0 to ENIR3): - Pins used for the return from sleep mode: Enable interrupt request output. - Pins not used for the return from sleep mode: Disable interrupt request output. ■ Return operation This device returns from sleep mode when a signal at the specified level/edge is input to the INT0 to INT31 pins in sleep mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 319 CHAPTER 14 External Interrupt Controllers 14.5 320 FUJITSU MICROELECTRONICS LIMITED MB91625 Series CM71-10151-2E CHAPTER 15 Watchdog Timer This chapter explains the functions and operations of the watchdog timer. 15.1 Overview 15.2 Configuration 15.3 Registers 15.4 Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 321 CHAPTER 15 Watchdog Timer 15.1 MB91625 Series 15.1 Overview The watchdog timer is a monitoring timer used to determine whether software hangs up or performs other abnormal operations. ■ Overview If the watchdog timer is not cleared before the specified period has elapsed, it judges that software has hung up and outputs a reset request to the CPU. This reset request is called a watchdog reset request. The operation of the watchdog timer requires that it be continually and periodically cleared before the specified period has elapsed. If an abnormal operation of software such as hanging up prevents it from being periodically cleared, it overflows and outputs a watchdog reset request. 322 • The watchdog timer counts cycles while a program is active on the CPU, and it stops counting while the CPU is stopped (in sleep mode, stop mode, or watch mode). • The watchdog timer can detect a transition to standby mode (watch mode/stop mode), and it can output a watchdog reset request to the CPU. • If an incorrect value is written to watchdog timer clear pattern register 0 (WDTCPR0), the watchdog timer outputs a watch reset request to the CPU. • The following period can be selected as the watchdog timer period: peripheral clock (PCLK) x (29 to 224) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 15 Watchdog Timer 15.2 MB91625 Series 15.2 Configuration This section shows the configuration of the watchdog timer. ■ Block diagram of the watchdog timer Figure 15.2-1 is a block diagram of the watchdog timer. Figure 15.2-1 Block diagram of the watchdog timer Register value holding Comparison circuit circuit Watchdog timer clear pattern register 0 (WDTCPR0) CPAT7 to CPAT0 Internal reset signal PCLK Standby mode (Watch mode/stop mode) Watchdog timer control register 0 (WDTCR0) R PCLK RSTP Q Watchdog reset request S Sleep mode Overflow EN RST Watchdog timer control register 0 (WDTCR0) PCLK Overflow period selection circuit Watchdog timer (24-bit up counter) WT3 to WT0 PCLK EN RST R S Q : Peripheral clock (PCLK) : Enabled : Reset : Reset : Set : Output • Watchdog timer control register 0 (WDTCR0) This register controls the operation of the watchdog timer. • Watchdog timer clear pattern register 0 (WDTCPR0) This register activates and clears the watchdog timer. • Watchdog timer This is a 24-bit up counter. • Register value holding circuit This circuit retains the value written in watchdog timer clear pattern register 0 (WDTCPR0). • Comparison circuit This circuit compares the value written in watchdog timer clear pattern register 0 (WDTCPR0) with the previous value that was written. • Overflow period selection circuit This circuit selects the overflow period of the watchdog timer. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 323 CHAPTER 15 Watchdog Timer 15.2 MB91625 Series ■ Clocks Table 15.2-1 lists the clock used by the watchdog timer. Table 15.2-1 Clock used by the watchdog timer Clock Name Operation clock 324 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 15 Watchdog Timer 15.3 MB91625 Series 15.3 Registers This section explains the configuration and functions of registers for the watchdog timer. ■ List of registers for the watchdog timer Table 15.3-1 lists the registers for the watchdog timer. Table 15.3-1 Registers for the watchdog timer Abbreviated Register Name CM71-10151-2E Register Name Reference WDTCR0 Watchdog timer control register 0 15.3.1 WDTCPR0 Watchdog timer clear pattern register 0 15.3.2 FUJITSU MICROELECTRONICS LIMITED 325 CHAPTER 15 Watchdog Timer 15.3 15.3.1 MB91625 Series Watchdog Timer Control Register 0 (WDTCR0) This register controls the operation of the watchdog timer. Figure 15.3-1 shows the bit configuration of watchdog timer control register 0 (WDTCR0). Figure 15.3-1 Bit configuration of watchdog timer control register 0 (WDTCR0) bit 7 6 5 4 3 2 1 0 Reserved RSTP Reserved Reserved WT3 WT2 WT1 WT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> This register can be written only prior to activation of the watchdog timer. [bit7]: Reserved bit 326 In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 15 Watchdog Timer 15.3 MB91625 Series [bit6]: RSTP (Stop mode detection reset enable bit) This bit specifies whether to enable output of a watchdog reset request at the transition time of the CPU to standby mode (watch mode/stop mode) while the watchdog timer is active. Written Value Explanation 0 Disables output of a watchdog reset request. The counting of the watchdog timer is suspended when a transition to standby mode (watch mode/stop mode) is detected, and it remains suspended until a return from standby mode. 1 Enables output of a watchdog reset request. A watchdog reset request is output when a transition to standby mode (watch mode/stop mode) is detected. <Notes> • To use standby mode (watch mode/stop mode), set "0" in this bit. • This register can be written only before the watchdog timer is activated. If "1" is set in this bit after the watchdog timer is activated, standby mode (watch mode/stop mode) is detected and a watchdog reset request is output. Therefore, standby mode becomes unusable. [bit5, bit4]: Reserved bits CM71-10151-2E In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. FUJITSU MICROELECTRONICS LIMITED 327 CHAPTER 15 Watchdog Timer 15.3 MB91625 Series [bit3 to bit0]: WT3 to WT0 (Watchdog timer period selection bits) These bits select one of the following periods as the period from watchdog timer clearing to watchdog reset request output. WT3 to WT0 Watchdog Timer Period 0000 PCLK x 29 0001 PCLK x 210 0010 PCLK x 211 0011 PCLK x 212 0100 PCLK x 213 0101 PCLK x 214 0110 PCLK x 215 0111 PCLK x 216 1000 PCLK x 217 1001 PCLK x 218 1010 PCLK x 219 1011 PCLK x 220 1100 PCLK x 221 1101 PCLK x 222 1110 PCLK x 223 1111 PCLK x 224 PCLK :Period of Peripheral clock (PCLK) 328 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 15 Watchdog Timer 15.3 MB91625 Series 15.3.2 Watchdog Timer Clear Pattern Register 0 (WDTCPR0) This register activates and clears the watchdog timer. Figure 15.3-2 shows the bit configuration of watchdog timer clear pattern register 0 (WDTCPR0). Figure 15.3-2 Bit configuration of watchdog timer clear pattern register 0 (WDTCPR0) bit 7 0 CPAT7 to CPAT0 Attribute R/W Initial value 0 R/W: Read/Write [bit7 to bit0]: CPAT7 to CPAT0 bits The watchdog timer is activated when any value is written to this register after this device is reset. To prevent a watchdog reset request from being output after the watchdog timer is activated, the timer must be cleared before the timer period has elapsed. To clear the watchdog timer, invert the bit pattern written in these bits and write the inverted value to the bits. For details of clearing the watchdog timer, see "■ Clearing the watchdog timer" in "15.4.1 Operations of the Watchdog Timer". CM71-10151-2E CPAT7 to CPAT0 In Case of Writing Value obtained by inverting the written value After being activated, the watchdog timer is cleared. Value other than that obtained by inverting the written value A watchdog reset request is output immediately. FUJITSU MICROELECTRONICS LIMITED In Case of Reading "0" is read. 329 CHAPTER 15 Watchdog Timer 15.4 MB91625 Series 15.4 Explanation of Operations and Setting Procedure Examples This section explains the operations of the watchdog timer. Also, examples of procedures for setting operating states are shown. 15.4.1 Operations of the Watchdog Timer If the watchdog timer is not periodically cleared even though the program is designed to do so, a malfunction is judged to have occurred and the watchdog timer outputs a watchdog reset request to the CPU. ■ Overview While the watchdog timer is operating, if it is not cleared before the specified period has elapsed, it judges that software has hung up and outputs a watchdog reset request to the CPU. A watchdog reset request is also output if an incorrect value is written to watchdog timer clear pattern register 0 (WDTCPR0) or at the transition time of the CPU to standby mode (watch mode/stop mode). Also, the watchdog timer stops the counting operation when the CPU is stopped. ■ Settings To use the watchdog timer, specify the following with watchdog timer control register 0 (WDTCR0) before activating the watchdog timer: • Period from watchdog timer clearing to the watchdog reset request output (WT3 to WT0 bits) • Whether to enable output of a watchdog reset request at the transition time of the CPU to standby mode (watch mode/stop mode) (RSTP) <Notes> • The watchdog timer performs counting only while the CPU is operating. Therefore, the WT3 to WT0 bits must be set based on the setting of the number of program steps and the clock division setting. • To use standby mode (watch mode/stop mode), set "0" in the RSTP bit. • If "1" is set in the RSTP bit after the watchdog timer is activated, standby mode (watch mode/ stop mode) cannot be used. ■ Operations The watchdog timer is activated when any value is written to the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0 (WDTCPR0) after this device is reset. The counter value changes in sync with the rising edge of the peripheral clock (PCLK) while the CPU is active. Unless the watchdog timer is cleared before the period specified by the WT3 to WT0 bits of watchdog timer control register 0 (WDTCR0) has elapsed, a watchdog reset request is output to the CPU. Also, the watchdog timer temporarily stops counting while the CPU is stopped, such as during doze mode or sleep mode. The value of the watchdog timer is not cleared while the counting is temporarily stopped. When the counting resumes, it starts from the value at which it was stopped. 330 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 15 Watchdog Timer 15.4 MB91625 Series <Notes> • Even during DMA transfer with the DMA controller (DMAC), the watchdog timer continues counting as long as the CPU is operating. • Since the peripheral clock (PCLK) is stopped during the oscillation stabilization wait time of the CPU source clock (SRCCLK), the watchdog timer also stops counting during this time. • Sampling of the CPU operation state is performed using the peripheral clock (PCLK). Therefore, a change in the operating state that does not last longer than the period of the peripheral clock (PCLK) may be ignored. ■ Clearing the watchdog timer The watchdog timer can be cleared by inverting the value written in the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0 (WDTCPR0) at the watchdog timer activation time and writing the inverted value to these bits. For example, if "55H" is written in the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0 (WDTCPR0) at the watchdog timer activation time, the watchdog timer can be cleared by writing the inverted value "AAH" to the bits. Clearing of the watchdog timer can be subsequently repeated by alternately writing "55H" and "AAH" to the CPAT7 to CPAT0 bits. However, a watchdog reset request is output to the CPU when any value other than the inverted values is written to the CPAT7 to CPAT0 bits. <Note> If it is difficult to maintain the value written in these bits, writing of a value to them can be followed by writing of its inverted value (e.g., writing "AAH" then writing "55H") every time the watchdog timer is cleared. ■ Output of a watchdog reset request The watchdog timer outputs a watchdog reset request to the CPU in any of the following cases: • The period specified by the WT3 to WT0 bits of watchdog timer control register 0 (WDTCR0) has elapsed (overflow). • The value written in the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0 (WDTCPR0) is different from the value obtained by inverting the written value. • There is a transition by the CPU to standby mode (watch mode/stop mode) (a watchdog reset request may be output depending on the setting of the RSTP bit of watchdog timer control register 0 (WDTCR0)). For details of the operations after output of a watchdog reset request, see "9.5 Explanation of Operations" of "CHAPTER 9 Reset". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 331 CHAPTER 15 Watchdog Timer 15.4 332 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter This chapter explains the functions and operations of the watch counter. 16.1 16.2 16.3 16.4 Overview Configuration Registers Interrupts 16.5 Explanation of Operations and Setting Procedure Examples 16.6 Notes on Use CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 333 CHAPTER 16 Watch Counter 16.1 MB91625 Series 16.1 Overview The watch counter is a timer that counts down starting from the specified value, and it generates an interrupt request at the time that the 6-bit down counter enters an underflow condition. Interrupt requests can be generated at a period ranging from 125 ms to 64 s. This series has 1 built-in channel for the watch counter. * This function is not available when the sub clock (SBCLK) is not being used. ■ Overview • The count clock can be selected from 4 types of clock, and interrupt requests can be set to be generated at an interval ranging from a minimum of 125 ms to a maximum of 64 s. Table 16.1-1 lists the count clocks and counting periods. Table 16.1-1 Count clocks and counting periods Counting Period (FCL = 32.768 kHz) Period of Count Clock 212/FCL 125 ms 213/FCL 250 ms 214/FCL 500 ms 215/FCL 1s FCL: Sub clock (SBCLK) frequency • A number between 0 and 63 can be set as the value used for counting by the 6-bit down counter. If "60" is the count value used for a counting period of 1 second, an interrupt request is generated at an interval of 1 minute. If "0" is the count value used for a counting period of 1 second, an interrupt request is generated at an interval of 64 seconds. • 334 An interrupt request can be generated at the time that the 6-bit down counter enters an underflow condition. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.2 MB91625 Series 16.2 Configuration This section shows the watch counter configuration. ■ Block diagram of the watch counter Figure 16.2-1 is a block diagram of the watch counter. Figure 16.2-1 Block diagram of the watch counter CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 RLC5 RLC4 RLC3 RLC2 RLC1 RLC0 Counter value Reload value Counter clearing 6-bit down Peripheral bus counter Underflow Count clock selection 212/FCL 213/FCL From sub timer 214/FCL 215/FCL Interrupt request Enabling of interrupts WCEN WCOP CS1 CS0 WCIE WCIF FCL: Sub clock frequency • 6-bit down counter This is the 6-bit down counter of the watch counter. It reloads the value set in the watch counter reload register (WCRL) and starts a countdown. • Watch counter reload register (WCRL) This register specifies the value used by the watch counter to start counting. The 6-bit down counter counts down starting from the value set in this register. • Watch counter read register (WCRD) This register reads the value in the 6-bit down counter. Also, the register can be read to check the count value. • Watch counter control register (WCCR) This register controls the operation of the watch counter. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 335 CHAPTER 16 Watch Counter 16.2 MB91625 Series ■ Clocks Table 16.2-1 lists the clocks used by the watch counter. Table 16.2-1 Clocks used by the watch counter Clock Name Description Remarks Operation clock Peripheral clock (PCLK) - Count clock Sub timer output Sub timer period* * The sub timer period is specified by the STS2 to STS0 bits in the sub timer control register (STMCR). For details of the sub timer, see "CHAPTER 7 Sub Timer". 336 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.3 MB91625 Series 16.3 Registers This section explains the configurations and functions of the registers for the watch counter. ■ List of registers for the watch counter Table 16.3-1 lists the registers for the watch counter. Table 16.3-1 Registers for the watch counter Abbreviated Register Name CM71-10151-2E Register Name Reference WCRL Watch counter reload register 16.3.1 WCCR Watch counter control register 16.3.2 WCRD Watch counter read register 16.3.3 FUJITSU MICROELECTRONICS LIMITED 337 CHAPTER 16 Watch Counter 16.3 16.3.1 MB91625 Series Watch Counter Reload Register (WCRL) This register specifies the value used by the watch counter to start counting. The 6-bit down counter counts down starting from the value set in the register. The register specifies the reload value for the 6-bit down counter. If the 6-bit down counter enters an underflow condition, the value in this register is reloaded in the 6-bit down counter, and the countdown is restarted. Figure 16.3-1 shows the bit configuration of the watch counter reload register (WCRL). Figure 16.3-1 Bit configuration of the watch counter reload register (WCRL) bit 7 6 5 4 3 2 1 0 Undefined Undefined RLC5 RLC4 RLC3 RLC2 RLC1 RLC0 Attribute - - R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 R/W: Read/Write -: Undefined [bit7, bit6]: Undefined bits In case of writing Ignored In case of reading "0" is read. [bit5 to bit0]: RLC5 to RLC0 (Counter reload value setting bits) These bits set the reload value for the 6-bit down counter. The 6-bit down counter counts downwards from the reload value and enters an underflow condition when its value reaches "1". If "0" is set in these bits, it performs 64 countdowns from "63" to "0". <Notes> 338 • If the value of these bits is changed to another value while the 6-bit down counter is active, an underflow occurs and the new value is then reloaded. • If the value of these bits is changed to another value at the same time that an underflow interrupt request is generated, the correct value is not reloaded. Be sure to rewrite the value of these bits either when the watch counter is stopped or in the interrupt processing routine before an interrupt request is generated. • To verify whether the reload value is correctly set, read this register. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.3 MB91625 Series 16.3.2 Watch Counter Control Register (WCCR) This register selects a count clock for the watch counter or enables/disables generation of interrupt requests. The register also enables/disables the operation of the watch counter. Figure 16.3-2 shows the bit configuration of the watch counter control register (WCCR). Figure 16.3-2 Bit configuration of the watch counter control register (WCCR) bit Attribute 7 6 5 4 3 2 1 0 WCEN WCOP Undefined Undefined CS1 CS0 WCIE WCIF R/W R - - R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Initial value R/W: Read/Write R: Read only -: Undefined [bit7]: WCEN (Watch counter operation enable bit) This bit enables/disables the operation of the watch counter. Written Value Explanation 0 The watch counter is disabled/stopped. The value in the 6-bit down counter is cleared to "000000B". 1 The watch counter is enabled/started. <Notes> • Output of the sub timer is used for the count clock of the watch counter, and the peripheral clock (PCLK) is used for the settings of each register. Since the sub timer and peripheral clock (PCLK) are not synchronized, an error of up to 1T (T: Count clock period) may occur at the count start time, depending on the time at which "1" is written to this bit. • Before writing "1" to this bit to start the operation of the watch counter, verify that the watch counter is stopped by checking the WCOP bit (WCOP = 0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 339 CHAPTER 16 Watch Counter 16.3 MB91625 Series [bit6]: WCOP (Watch counter operating state flag bit) This bit indicates the operating state of the watch counter. Read Value Explanation 0 The watch counter is stopped. 1 The watch counter is active. [bit5, bit4]: Undefined bits In case of writing Ignored In case of reading "0" is read. [bit3, bit2]: CS1, CS0 (Count clock selection bits) These bits set the count clock of the watch counter. CS1 CS0 Count Clock 0 0 212/FCL 0 1 213/FCL 1 0 214/FCL 1 1 215/FCL FCL: Sub clock (SBCLK) frequency <Note> The following conditions must be satisfied when the information in these bits is changed: • WCEN bit = 0 (watch counter operation disabled) • WCOP bit = 0 (watch counter stopped) [bit1]: WCIE (Interrupt request enable bit) This bit specifies whether to generate an underflow interrupt request at the time that the 6-bit down counter enters an underflow condition (WCIF bit = 1). Written Value 340 Explanation 0 Disables generation of an underflow interrupt request. 1 Enables generation of an underflow interrupt request. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.3 MB91625 Series [bit0]: WCIF (Interrupt request flag bit) This bit indicates whether the 6-bit down counter has entered an underflow condition. If "1" is set in the WCIE bit, an interrupt request is generated when "1" is set in this bit. WCIF In Case of Reading In Case of Writing 0 The down counter has not entered an underflow condition. This bit is cleared to "0". 1 The down counter has entered an underflow condition. Ignored <Note> When a read-modify-write instruction is used, "1" is read. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 341 CHAPTER 16 Watch Counter 16.3 16.3.3 MB91625 Series Watch Counter Read Register (WCRD) This register reads the value in the 6-bit down counter. Figure 16.3-3 shows the bit configuration of the watch counter read register (WCRD). Figure 16.3-3 Bit configuration of the watch counter read register (WCRD) bit 7 6 5 4 3 2 1 0 Undefined Undefined CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 Attribute - - R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only -: Undefined <Note> If the 6-bit down counter is operating when its value is read, the register value must be read twice and verified to be the same value. 342 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.4 MB91625 Series 16.4 Interrupts The 6-bit down counter enters an underflow condition when the value in the 6-bit down counter becomes "000001B", and an underflow interrupt request is then generated. Table 16.4-1 outlines the interrupts that can be used with the watch counter. Table 16.4-1 Interrupts of the watch counter Interrupt request Underflow interrupt request Interrupt request flag WCIF=1 for WCCR Interrupt request enabled WCIE=1 for WCCR Clearing an interrupt request Write "0" to the WCIF bit for WCCR WCCR: watch counter control register (WCCR) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling generation of interrupt requests. - Clear interrupt requests before enabling the generation of interrupt requests. - Clear interrupt requests simultaneously with interrupts enabled. • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • To set the interrupt level corresponding to the interrupt vector number, use an interrupt control register (ICR00 to ICR47). For details of setting interrupt levels, see "CHAPTER 10 Interrupt Controller". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 343 CHAPTER 16 Watch Counter 16.5 MB91625 Series 16.5 Explanation of Operations and Setting Procedure Examples This section explains operations of the watch counter. Also, examples of procedures for setting the operating state are shown. 16.5.1 Operations of the Watch Counter The watch counter is a timer that counts down starting from the value set in the watch counter reload register (WCRL), and it generates an interrupt request at the time that the 6-bit down counter enters an underflow condition. To operate the watch counter, follow the procedure below. 1. Select a count clock by using the CS1 and CS0 bits of the watch counter control register (WCCR). 2. Set a count value to the RLC5 to RLC0 bits in the watch counter reload register (WCRL). 3. Enable the operation of the watch counter by using the WCEN bit (WCEN = 1) of the watch counter control register (WCCR). Start a countdown. Counting is performed at the rising edge of the count clock. 4. If the 6 -bit down counter enters an underflow condition, the value of the WCIF bit in the watch counter control register (WCCR) is changed to "1". At this time, if generation of underflow interrupt requests has been enabled by the WCIE bit in the watch counter control register (WCCR), an underflow interrupt request is generated. Also, the value that is set in the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is reloaded in the 6-bit down counter, and the countdown is restarted. 5. If the value of the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is changed to another value while the watch counter is active, the watch counter is updated with the new value at the next reload time. 6. The underflow interrupt request is cleared when "0" is written to the WCIF bit in the watch counter control register (WCCR). 7. The 6-bit down counter is cleared to "000000B" and the counting operation is stopped when "0" is written to the WCEN bit in the watch counter control register (WCCR). 344 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 16 Watch Counter 16.5 MB91625 Series Figure 16.5-1 shows the operation of the watch counter. Figure 16.5-1 Operation of the watch counter WCEN bit ➆ ➂ Count clock CS1 and CS0 bits ➀ RLC5 to RLC0 bits ➁ 7 9 ➄ CTR5 to CTR0 bits 0 7 6 5 4 3 2 1 9 8 7 6 5 4 0 WCIF bit ➃ ➅ <Notes> • Output of the sub timer is used for the count clock of the watch counter, and the peripheral clock (PCLK) is used for the settings of each register. Since the sub timer and peripheral clock (PCLK) are not synchronized, an error of up to 1T (T: Count clock period) may occur at the count start time, depending on the time at which "1" is written to the WCEN bit in the watch counter control register (WCCR). • Since the count clock from the sub timer is also stopped when the sub clock (SBCLK) is stopped, the 6-bit down counter is stopped too. Even when the sub clock (SBCLK) starts operating again, the watch counter cannot count counter values correctly. Before using the watch counter when the sub clock (SBCLK) starts operating again, be sure to write "0" to the WCEN bit in the watch counter control register (WCCR) to clear the counter value to "000000B". • Even when the CPU is operating in watch mode, the watch counter continues operating as long as the sub timer is operating. The watch mode of the CPU can be canceled with the watch counter interrupt processing routine. • If the sub timer is cleared while the watch counter is active, counting values correctly may become impossible. Stop the watch counter by using the WCEN bit (WCEN = 0) of the watch counter control register (WCCR), and then clear the sub timer. • After the watch counter is stopped by writing "0" to the WCEN in the watch counter control register (WCCR), be sure to verify that the watch counter is stopped by checking the WCOP bit (WCOP = 0) in the watch counter control register (WCCR) before reactivating the watch counter by using the WCEN bit (WCEN = 1). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 345 CHAPTER 16 Watch Counter 16.6 MB91625 Series 16.6 Notes on Use Note the following points about using the watch counter. ■ Notes on operations 346 • If the sub timer is cleared while the watch counter is active, counting values correctly may become impossible. Stop the watch counter by using the WCEN bit (WCEN = 0) of the watch counter control register (WCCR), and then clear the sub timer. • After the watch counter is stopped by the WCEN bit (WCEN = 0) in the watch counter control register (WCCR), be sure to verify that the watch counter is stopped by checking the WCOP bit (WCOP = 0) in the watch counter control register (WCCR) before reactivating the watch counter by using the WCEN bit (WCEN = 1). • Since the watch counter uses output of the sub timer as the count clock, the setting of the sub timer must not be changed while the watch counter is active. • The watch counter enters an underflow condition when it counts downwards from "000001B". It counts downwards from the reload value to "1". If the value is set to "0", it performs 64 countdowns. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer This chapter explains the functions and operations of the 32-bit free-run timer. 17.1 17.2 17.3 17.4 Overview Configuration Pins Registers 17.5 Interrupts 17.6 An Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 347 CHAPTER 17 32-bit Free-Run Timer 17.1 MB91625 Series 17.1 Overview The 32-bit free-run timer is an up-counter that counts up to the predetermined value. After counting up to the specified value, the free-run timer clears the value and starts counting again or generates an interrupt request. The count value is also used as the reference time for 32-bit output compare or 32-bit input capture. This series microcontroller has 2 built-in channels for the 32-bit free-run timer. ■ Overview The 32-bit free-run timer is part of the compare timer. The compare timer comprises the following three peripheral functions: - 32-bit free-run timer (2 channels) - 32-bit output compare (8 channels) See "CHAPTER 19 32-bit Output Compare". - 32-bit input capture (8 channels) See "CHAPTER 18 32-bit Input Capture". This chapter explains the 32-bit free-run timer. • Count clock: One of the following can be selected: - Internal clock (peripheral clock) Can be selected from 9 types, which are peripheral clocks (PCLK) divided by 1, 2, 4, 8, 16, 32, 64,128, and 256. • External clock Interrupt request: Can be issued in the following cases: The count value of the 32-bit free-run timer matches the preset value (compare clear interrupt). • 348 Of the values of the 2 channels of the 32-bit free-run timer, one can be selected for use as the reference time for 32-bit output compare and 32-bit input capture. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.2 MB91625 Series 17.2 Configuration The 32-bit free-run time is part of the compare timer. The following is a block diagram of the compare timer and the 32-bit free-run timer. ■ Compare timer block diagram The compare timer consists of the following blocks. • 32-bit free-run timer • Free-run timer selector The free-run timer selector selects the 32-bit free-run timer used as the reference time for the 32-bit output compare and 32-bit input capture. • 32-bit input capture (8 channels) • 32-bit output compare (8 channels) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 349 CHAPTER 17 32-bit Free-Run Timer 17.2 MB91625 Series Figure 17.2-1 is a compare timer block diagram. Figure 17.2-1 Compare timer block diagram FRCK0 pin 32-bit free-run timer ch.0 Interrupt request Compare clear ch.0 FRCK1 pin 32-bit free-run timer ch.1 Timer 0 Interrupt request Compare clear ch.1 Timer 1 Free-run timer selector Peripheral bus Timer 0 or Timer 1 Count value Interrupt request 32-bit input capture (× 4) Interrupt request Interrupt request Interrupt request IN0 to IN3 pins IN0 to IN3 Count value 32-bit input capture (× 4) Count value Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Count value Input capture ch.4 Input capture ch.5 Input capture ch.6 Input capture ch.7 IN4 to IN7 pins IN4 to IN7 32-bit Interrupt request output compare OUT0 to OUT3 (× 4) Interrupt request Interrupt request Interrupt request 32-bit Interrupt request output compare OUT4 to OUT7 (× 4) 350 Input capture ch.0 Input capture ch.1 Input capture ch.2 Input capture ch.3 Output compare ch.0 Output compare ch.1 Output compare ch.2 Output compare ch.3 OUT0 to OUT3 pins Output compare ch.4 Output compare ch.5 Output compare ch.6 Output compare ch.7 FUJITSU MICROELECTRONICS LIMITED OUT4 to OUT7 pins CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.2 MB91625 Series ■ 32-bit free-run timer block diagram Figure 17.2-2 is a block diagram of the 32-bit free-run timer. Figure 17.2-2 32-bit free-run timer block diagram Internal clock (PCLK) TCCSL0 STOP SCLR CLK3 CLK2 CLK1 Prescaler CLK0 External clock input (FRCK0) TCDT0 STOP CLR Stop 32-bit free-run timer ch.0 Selection circuit CK To free-run timer selector Comparison circuit Compare clear register 0 (CPCLR0) Stop free-run timer 0 (To free-run timer selector) Peripheral bus Interrupt request ICLR ICRE ECKE TCCSH0 Internal clock (PCLK) TCCSL1 STOP SCLR CLK3 CLK2 CLK1 Prescaler CLK0 External clock input (FRCK1) TCDT1 STOP CLR Stop 32-bit free-run timer ch.1 Selection circuit CK To free-run timer selector Comparison circuit Compare clear register 1 (CPCLR1) Stop free-run timer 1 (To free-run timer selector) Interrupt request ICLR ICRE ECKE TCCSH1 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 351 CHAPTER 17 32-bit Free-Run Timer 17.2 • MB91625 Series 32-bit free-run timer This counter counts up to the value that is set in the compare clear register (CPCLR0, CPCLR1) • Timer status control register upper/lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1) • Compare clear register (CPCLR0, CPCLR1) This register controls the operation of the 32-bit free-run timer. The 32-bit up counter counts up to the value that is set in this register. • Timer data register (TCDT0, TCDT1) This register is used to set the value with which the timer starts counting or to read the current count value. • Prescaler When the internal clock (peripheral clock) is selected for the count clock, the prescaler divides the peripheral clock (PCLK) • Selection circuit The selection circuit selects whether to use the internal clock (peripheral clock) or external clock (FRCK0, FRCK1) for the count clock. • Comparison circuit The comparison circuit compares the count value of the 32-bit free-run timer and the value set in the compare clear register (CPCLR0, CPCLR1). ■ Clocks Table 17.2-1 lists the clocks used for the 32-bit free-run timer. Table 17.2-1 Clocks used for 32-bit free-run timer Clock Name 352 Description Remarks Operation clock Peripheral clock (PCLK) - Count clock Internal clock (peripheral clock) Created through division of the peripheral clock (PCLK). External clock Input from the FRCK0 and FRCK1 pins FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.3 MB91625 Series 17.3 Pins This section explains the pins used by the 32-bit free-run timer. ■ Overview • FRCK0 and FRCK1 pins These pins are 32-bit free-run timer external clock input pins. These pins are multiplexed pins. To use these pins as the FRCK0 and FRCK1 pins of the 32-bit free-run timer, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 17.3-1 shows the relationship between channels and pins. Table 17.3-1 Relationship between channels and pins Channel CM71-10151-2E Input Pin 0 FRCK0 1 FRCK1 FUJITSU MICROELECTRONICS LIMITED 353 CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series 17.4 Registers This section explains the configuration and functions of the registers used by the 32-bit free-run timer. ■ 32-bit free-run timer registers Table 17.4-1 lists the registers of the 32-bit free-run timer. Table 17.4-1 32-bit free-run timer registers Channel Abbreviated Register Name Common FRTSEL Free-run timer select register 17.4.1 0 CPCLR0 Compare clear register 0 17.4.2 TCCSH0/TCCSL0 Timer status control register upper0/lower0 17.4.4 TCDT0 Timer data register 0 17.4.3 CPCLR1 Compare clear register 1 17.4.2 TCCSH1/TCCSL1 Timer status control register upper1/lower1 17.4.4 TCDT1 Timer data register 1 17.4.3 1 354 Register Name FUJITSU MICROELECTRONICS LIMITED Reference CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series 17.4.1 Free-Run Timer Select Register (FRTSEL) This register specifies the channel for use as the reference time for 32-bit output compare and 32-bit input capture, of the 2 channels of 32-bit free-run timer. Figure 17.4-1 shows the bit configuration of the free-run timer select register (FRTSEL). Figure 17.4-1 Bit configuration of free-run timer select register (FRTSEL) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined FRS1 FRS0 Attribute - - - - - - R/W R/W Initial value X X X X X X 0 0 R/W: Read/Write -: Undefined X: Undefined [bit7 to bit2]: Undefined bits In case of writing Ignored In case of reading A value is undefined. [bit1, bit0]: FRS1, FRS0 (free-run timer selection bit) These bits select the 32-bit free-run timer channel used as the reference time for the 32-bit output compare and 32-bit input capture. FRS1 FRS0 Explanation Free-run Timer Channel 0 0 ch.0 32-bit output compare (ch.0 to ch.7) 32-bit input capture (ch.0 to ch.7) 0 1 ch.0 32-bit output compare (ch.0 to ch.3) 32-bit input capture (ch.0 to ch.3) ch.1 32-bit output compare (ch.4 to ch.7) 32-bit input capture (ch.4 to ch.7) ch.0 32-bit output compare (ch.0 to ch.7) ch.1 32-bit input capture (ch.0 to ch.7) 1 1 CM71-10151-2E Use 0 1 Setting prohibited FUJITSU MICROELECTRONICS LIMITED 355 CHAPTER 17 32-bit Free-Run Timer 17.4 17.4.2 MB91625 Series Compare Clear Register (CPCLR0, CPCLR1) This register sets the comparison value of the 32-bit free-run timer. When the 32-bit free-run timer counts up and reaches the value that is set in this register, the count value of the 32-bit free-run timer is cleared to "0000 0000H". Figure 17.4-2 shows the bit configuration of the compare clear register (CPCLR0, CPCLR1). Figure 17.4-2 Bit configuration of compare clear register (CPCLR0, CPCLR1) bit 31 0 CL31 to CL0 Attribute R/W Initial value 1 R/W: Read/Write <Notes> • Rewrite this register while the 32-bit free-run timer is stopped. The 32-bit free-run timer is stopped when the STOP bit of the timer status control register lower (TCCSL0, TCCSL1) is "1". • 356 Be sure to access this register in units of words. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series 17.4.3 Timer Data Register (TCDT0, TCDT1) This register is used to set the value with which the 32-bit free-run timer starts counting or to read the current count value. Figure 17.4-3 shows the bit configuration of the timer data register (TCDT0, TCDT1). Figure 17.4-3 Bit configuration of timer data register (TCDT0, TCDT1) bit 31 0 T31 to T0 Attribute R/W Initial value 0 R/W: Read/Write The 32-bit free-run timer counts up starting from the value written to this register. If this register is read, the count value of the 32-bit free-run timer is read. <Notes> • Rewrite this register while the 32-bit free-run timer is stopped. The 32-bit free-run timer is stopped when the STOP bit of the timer status control register lower (TCCSL0, TCCSL1) is "1". • Be sure to access this register in units of half word. • The write value and read value of this register are different. • If one of the following occurs, the count value of the 32-bit free-run timer (the value of this register) is promptly cleared to "0000 0000H". - This device is reset. - "1" is written to the SCLR bit of the timer status control register lower (TCCSL0, TCCSL1). - The count value of the 32-bit free-run time matches the value of the compare clear register (CPCLR0, CPCLR1). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 357 CHAPTER 17 32-bit Free-Run Timer 17.4 17.4.4 MB91625 Series Timer Status Control Register Upper/Lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1) This register controls the operation of the 32-bit free-run timer. Figure 17.4-4 shows the bit configuration of the timer status control register upper/lower (TCCSH0/ TCCSL0, TCCSH1/TCCSL1). Figure 17.4-4 Bit configuration of timer status control register upper/lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1) Timer status control register upper (TCCSH0 TCCSH1) bit Attribute 15 14 13 12 11 10 9 8 ECKE Undefined Undefined Undefined Undefined Undefined ICLR ICRE R/W - - - - - R/W R/W 0 X X X X X 0 0 Initial value Timer status control register lower (TCCSL0, TCCSL1) bit 7 6 5 4 3 2 1 0 Undefined STOP Undefined SCLR CLK3 CLK2 CLK1 CLK0 Attribute - R/W - R/W R/W R/W R/W R/W Initial value X 1 X 0 0 0 0 0 R/W: Read/Write -: Undefined X: Undefined 358 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series [bit15]: ECKE (Clock selection bit) This bit selects the count clock of the 32-bit free-run timer. Written Value Explanation 0 Selects the internal clock (peripheral clock). 1 Selects an external clock. An internal clock (peripheral clock) is generated by dividing the peripheral clock (PCLK). If an internal clock (peripheral clock) is selected, CLK3 to CLK0 bits must be used to select the division rate of the peripheral clock (PCLK). An external clock is input through the FRCK0 and FRCK1 pins. When an external clock is selected, the timer counts on both edges of the signal input through the FRCK0 or FRCK1 pin. <Notes> • The count clock changes as soon as this bit is changed. • Rewrite this bit while the 32-bit free-run timer, 32-bit input capture, and 32-bit output compare are all stopped. [bit14 to bit10]: Reserved bits In case of writing Ignored In case of reading A value is undefined. [bit9]: ICLR (compare clear interrupt request flag bit) This bit indicates that the count value of the 32-bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1). If "1" is set in the ICRE bit when this bit is "1", a compare clear interrupt request is generated. ICLR In Case of Reading In Case of Writing 0 The count value does not match the preset value. This bit is cleared to "0". 1 The count value matches the preset value. Ignored <Note> When a read-modify-write instruction is used, "1" is read. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 359 CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series [bit8]: ICRE (compare clear interrupt request enable bit) This bit is specifies whether to generate a compare clear interrupt request when the count value of the 32bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1) (ICLR bit = 1). Written Value Explanation 0 Disables generation of compare clear interrupt requests. 1 Enables generation of compare clear interrupt requests. [bit7]: Undefined bit In case of writing Ignored In case of reading A value is undefined. [bit6]: STOP (timer operation enable bit) This bit enables (starts) or disables (stops) the count operation of the 32-bit free-run timer. Written Value Explanation 0 Enables (starts) the count function. 1 Disables (stops) the count function. <Note> When the 32-bit free-run timer is stopped, the 32-bit output compare is also stopped. [bit5]: Undefined bit In case of writing Ignored In case of reading A value is undefined. [bit4]: SCLR (timer clear bit) This bit clears the count value of the 32-bit free-run timer to "0000 0000H". SCLR In Case of Writing 0 Does not clear the count value. 1 Clears the count value. In Case of Reading "0" is read. <Note> When this bit is set to "1", the count value is cleared at the next count clock timing. 360 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.4 MB91625 Series [bit3 to bit0]: CLK3 to CLK0 (clock frequency selection bits) These bits select the division rate of the peripheral clock (PCLK) when the internal clock (peripheral clock) is selected for the count clock of the 32-bit free-run timer, The count cycle is determined by using the division rate selected by these bits and the peripheral clock (PCLK) frequency. Table 17.4-2 provides an example of count cycles that are set according to the relationship between the values written to these bits and the peripheral clock (PCLK). Table 17.4-2 Example of written values and count cycles CLK3 CLK2 CLK1 CLK0 PCLK Division Rate PCLK Frequency 32 MHz 16 MHz 8 MHz 4 MHz 1 MHz 0 0 0 0 Divided by 1 31.25 ns 62.5 ns 125 ns 0.25 μs 1 μs 0 0 0 1 Divided by 2 62.5 ns 125 ns 0.25 μs 0.5 μs 2 μs 0 0 1 0 Divided by 4 125 ns 0.25 μs 0.5 μs 1 μs 4 μs 0 0 1 1 Divided by 8 0.25 μs 0.5 μs 1 μs 2 μs 8 μs 0 1 0 0 Divided by 16 0.5 μs 1 μs 2 μs 4 μs 16 μs 0 1 0 1 Divided by 32 1 μs 2 μs 4 μs 8 μs 32 μs 0 1 1 0 Divided by 64 2 μs 4 μs 8 μs 16 μs 64 μs 0 1 1 1 Divided by 128 4 μs 8 μs 16 μs 32 μs 128 μs 1 0 0 0 Divided by 256 8 μs 16 μs 32 μs 64 μs 256 μs PCLK: Peripheral clock (PCLK) <Notes> • Do not use any settings other than those listed in Table 17.4-2. • The count clock changes as soon as this bit is rewritten. • Rewrite this bit while the 32-bit free-run timer, 32-bit input capture, and 32-bit output compare are all stopped. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 361 CHAPTER 17 32-bit Free-Run Timer 17.5 MB91625 Series 17.5 Interrupts An interrupt request (compare clear interrupt request) is generated when the count value of the 32-bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1). Table 17.5-1 outlines the interrupts that can be used with the 32-bit free-run timer. Table 17.5-1 Interrupts of the 32-bit free-run timer Interrupt request Compare clear interrupt request Interrupt request flag ICLR=1 for TCCSH Interrupt request enabled ICRE=1 for TCCSH Clearing an interrupt request Write "0" to the ICLR bit for TCCSH TCCSH: timer status control register upper (TCCSH0, TCCSH1) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. 362 • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use an interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.6 MB91625 Series 17.6 An Explanation of Operations and Setting Procedure Examples This section explains the operation of the 32-bit free-run timer. Also, examples of procedures for setting the operating state are shown. ■ Overview The 32-bit free-run timer uses an internal clock (peripheral clock) or an external clock as count clock and counts up starting from the value set in the timer data register (TCDT0, TCDT1) to the value set in the compare clear register (CPCLR0, CPCLR1). • Internal clock (peripheral clock) Can be selected from 9 types, which are peripheral clocks (PCLK) divided by 1, 2, 4, 8, 16, 32, 64,128, and 256. • External clock The timer counts up at both edges. The count start timing varies depending on the initial value of the external clock input through the FRCK0 or FRCK1 pin. The count value of the 32-bit free-run timer is used as the reference time for 32-bit output compare or 32bit input capture. ■ Timer clearing The count value of the 32-bit free-run timer is promptly cleared when one of the following conditions is met: • This count value matches the value that is set in the compare clear register (CPCLR0, CPCLR1). • The SCLR bit of the timer status control register lower (TCCSL0, TCCSL1) is set to 1 to clear the count value of the 32-bit free-run timer. • "0000 0000H" is written to the timer data register (TCDT0, TCDT1) while the 32-bit free-run timer is stopped. • This device is reset. When the count value of the 32-bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1), the count value is cleared in synchronization with the count timing. Figure 17.6-1 shows the timer clear timing. Figure 17.6-1 Timer clear timing Peripheral clock (PCLK) Compare clear register (CPCLR0, CPCLR1) value N Count timing Count value CM71-10151-2E N FUJITSU MICROELECTRONICS LIMITED 0000H 363 CHAPTER 17 32-bit Free-Run Timer 17.6 17.6.1 MB91625 Series Operation When an Internal Clock (Peripheral Clock) Is Selected A divided peripheral clock (PCLK) is used as the count clock. ■ Count operation When the STOP bit of the timer status control register lower (TCCSL0, TCCSL1) is set to 0 to enable the 32-bit free-run timer, the timer counts up starting from the value set in the timer data register (TCDT0, TCDT1) to the value set in the compare clear register (CPCLR0, CPCLR1). ■ Compare clear When the count value of the 32-bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1), the count value is cleared in synchronization with the count timing (compare clear). After compare clear, the timer starts counting again. Figure 17.6-2 shows the compare clear timing. Figure 17.6-2 Compare clear timing Count value FFFF FFFFH BFFF FFFFH 7FFF FFFFH 3FFF FFFFH 0000 0000 H Time Timer start Comparison results matched Reset Compare clear registers FFFFH 7FFFH BFFFH (CPCLR0, CPCLR1) ■ Interrupt processing An interrupt request can be generated when the count value of the 32-bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1). The interrupt request can be cleared by writing "0" to the ICLR bit of the timer status control register upper (TCCSH0 TCCSH1). Figure 17.6-3 shows the interrupt request generation timing. Figure 17.6-3 Interrupt request generation timing Count value N-1 N 0 1 Compare clear interrupt request 364 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 17 32-bit Free-Run Timer 17.6 MB91625 Series 17.6.2 Operation When an External Clock Is Selected The external clock input through the FRCK0 or FRCK1 pin is used as the count clock. ■ Count operation Upon detection of a valid edge through the FRCK0 or FRCK1 pin while the STOP bit of the timer status control register lower (TCCSL0, TCCSL1) is set to 0 to enable the 32-bit free-run timer, the timer counts up starting from the value set in the timer data register (TCDT0, TCDT1) to the value set in the compare clear register (CPCLR0, CPCLR1). The count timing varies depending on the signal level input through the FRCK0 or FRCK1 pin when the free-run timer is enabled. Table 17.6-1 lists the count timings applicable when an external clock is selected. Table 17.6-1 Count timings applicable when an external clock is selected Signal Level When Timer Is Enabled Count Timing "H" level Starts counting at a rising edge and thereafter counts up at both edges. "L" level Starts counting at a falling edge and thereafter counts up at both edges. Figure 17.6-4 shows the count timing applicable when an external clock is selected (ECKE=1). Figure 17.6-4 Count timing applicable when an external clock is selected External clock input ECKE bit Count clock Count value N N+1 N+2 ■ Compare clear Same as when an internal clock (peripheral clock) is selected. See "■ Compare clear" in "17.6.1 Operation When an Internal Clock (Peripheral Clock) Is Selected". ■ Interrupt processing Same as when an internal clock (peripheral clock) is selected. See "■ Interrupt processing" in "17.6.1 Operation When an Internal Clock (Peripheral Clock) Is Selected". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 365 CHAPTER 17 32-bit Free-Run Timer 17.6 366 FUJITSU MICROELECTRONICS LIMITED MB91625 Series CM71-10151-2E CHAPTER 18 32-bit Input Capture This chapter explains the functions and operations of the 32-bit input capture. 18.1 Overview 18.2 Configuration 18.3 Pins 18.4 Registers 18.5 Interrupts 18.6 An Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 367 CHAPTER 18 32-bit Input Capture 18.1 MB91625 Series 18.1 Overview Upon detection of an input signal edge that is set in advance, the 32-bit input capture saves the value of the 32-bit free-run timer at the time. This series microcontroller has 8 built-in input capture channels. ■ Overview The 32-bit input capture is part of the compare timer. The compare timer comprises the following three functions: - 32-bit free-run timer (2 channels) - 32-bit output compare (8 channels) See "CHAPTER 17 32-bit Free-Run Timer". See "CHAPTER 19 32-bit Output Compare". - 32-bit input capture (8 channels) This chapter explains the 32-bit input capture. • One of the following three triggers can be selected to save the value of the 32-bit free-run timer. - Rising edge - Falling edge - Both edges • An interrupt request can be generated upon detection of an input signal edge that is set in advance. • Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is saved by the 32-bit input capture can be selected. For details of the procedure for selecting the 32-bit free-run timer, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". 368 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.2 MB91625 Series 18.2 Configuration This section explains the configuration of the 32-bit input capture. ■ 32-bit input capture block diagram Figure 18.2-1 is a block diagram of the 32-bit input capture. Figure 18.2-1 32-bit input capture block diagram From the free-run timer selector Input capture data register 0 (IPCP0) Edge detection ICP0 ICE0 EG10 IN0 ICS01 EG00 Interrupt request 0 Input capture data register 1 (IPCP1) Edge detection IN1 ICS01 ICP1 ICE1 EG11 EG01 Interrupt request 1 Input capture data register 2 (IPCP2) Edge detection IN2 ICS23 Peripheral bus ICP2 ICE2 EG12 EG02 Interrupt request 2 Input capture data register 3 (IPCP3) Edge detection IN3 ICS23 ICP3 ICE3 EG13 EG03 Interrupt request 3 Input capture data register 4 (IPCP4) Edge detection IN4 ICS45 ICP4 ICE4 EG14 EG04 Interrupt request 4 Input capture data register 5 (IPCP5) Edge detection IN5 ICS45 ICP5 ICE5 EG15 EG05 Interrupt request 5 Input capture data register 6 (IPCP6) Edge detection IN6 ICS67 ICP6 ICE6 EG16 EG06 Interrupt request 6 Input capture data register 7 (IPCP7) Edge detection IN7 ICS67 ICP7 ICE7 EG17 EG07 Interrupt request 7 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 369 CHAPTER 18 32-bit Input Capture 18.2 • MB91625 Series Input capture data registers (IPCP0 to IPCP7) Free-run timer values are saved to these registers. • Input capture status control registers (ICS01 to ICS67) These registers are used to control the operation and state of the 32-bit input capture. <Note> For details of the compare timer block diagram, see "■ Compare timer block diagram" in "CHAPTER 17 32-bit Free-Run Timer". ■ Clocks Table 18.2-1 lists the clock used for the 32-bit input capture. Table 18.2-1 Clock used for 32-bit input capture Clock Name Operation clock 370 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.3 MB91625 Series 18.3 Pins This section explains the pins used by the 32-bit input capture. ■ Overview • IN0 to IN7 pins Input pins of 32-bit input capture. These pins are multiplexed pins. To use these pins as input pins of the 32-bit input capture, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 18.3-1 lists the relationship between channels and pins. Table 18.3-1 Relationship between channels and pins Channel CM71-10151-2E Input Pin 0 IN0 1 IN1 2 IN2 3 IN3 4 IN4 5 IN5 6 IN6 7 IN7 FUJITSU MICROELECTRONICS LIMITED 371 CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series 18.4 Registers This section explains the configuration and functions of registers used by the 32-bit input capture. ■ Registers of 32-bit input capture Table 18.4-1 lists the registers of the 32-bit input capture. Table 18.4-1 Registers of 32-bit input capture Channel 372 Abbreviated Register Name Register Name Reference Common FRTSEL Free-run timer select register 17.4.1 Common to 0 and 1 ICS01 Input capture status control register 01 18.4.1 Common to 2 and 3 ICS23 Input capture status control register 23 18.4.1 Common to 4 and 5 ICS45 Input capture status control register 45 18.4.1 Common to 6 and 7 ICS67 Input capture status control register 67 18.4.1 0 IPCP0 Input capture data register 0 18.4.2 1 IPCP1 Input capture data register 1 18.4.2 2 IPCP2 Input capture data register 2 18.4.2 3 IPCP3 Input capture data register 3 18.4.2 4 IPCP4 Input capture data register 4 18.4.2 5 IPCP5 Input capture data register 5 18.4.2 6 IPCP6 Input capture data register 6 18.4.2 7 IPCP7 Input capture data register 7 18.4.2 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series 18.4.1 Input Capture Status Control Registers (ICS01 to ICS67) These registers are used to control the operation and state of the 32-bit input capture. Figure 18.4-1 shows the bit configuration of the input capture status control register (ICS01 to ICS67). Figure 18.4-1 Bit configuration of input capture status control register (ICS01 to ICS67) bit 7 6 5 4 3 2 1 0 ICPm ICPn ICEm ICEn EG1m EG0m EG1n EG0n R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write [bit7, bit6]: ICPm, ICPn (interrupt request flag bit) Each of these bits indicates that a valid edge has been detected at pins IN0 to IN7. When this bit is "1" while ICEm or ICEn bit is set to "1", an edge detection interrupt request is generated. The ICPm bit corresponds to the odd-numbered channel, and the ICPn bit corresponds to the evennumbered channel. ICPm, ICPn In Case of Reading In Case of Writing 0 A valid edge is not detected. This bit is cleared to "0". 1 A valid edge is detected. Ignored Table 18.4-2 lists the relationship between the ICPm bits and ICPn bits and channels. Table 18.4-2 Relationship between bits and channels Input Capture Status Registers ICPm Bit Supported Channel ICPn Bit Supported Channel ICS01 ICP1 ch.1 ICP0 ch.0 ICS23 ICP3 ch.3 ICP2 ch.2 ICS45 ICP5 ch.5 ICP4 ch.4 ICS67 ICP7 ch.7 ICP6 ch.6 <Note> When a read-modify-write instruction is used, "1" is read. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 373 CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series [bit5, bit4]: ICEm, ICEn (interrupt request enable bits) Each of these bits specifies whether to generate an edge detection interrupt request when a valid edge is detected through pins IN0 to IN7 (ICPm, ICPn=1). The ICEm bit corresponds to the odd-numbered channel, and the ICEn bit corresponds to the evennumbered channel. Written Value Explanation 0 Disables generation of edge detection interrupt requests. 1 Enables generation of edge detection interrupt requests. Table 18.4-3 shows the relationship between the ICEm bits and ICEn bits and channels. Table 18.4-3 Relationship between bits and channels Input Capture Status Registers ICEm Bit Supported Channel ICEn Bit Supported Channel ICS01 ICE1 ch.1 ICE0 ch.0 ICS23 ICE3 ch.3 ICE2 ch.2 ICS45 ICE5 ch.5 ICE4 ch.4 ICS67 ICE7 ch.7 ICE6 ch.6 [bit3, bit2]: EG1m, EG0m (edge selection bits) These bits select a valid edge for the 32-bit input capture of the odd-numbered channel. When the edge selected here is detected, the value of the 32-bit free-run timer is saved to the input capture data register (IPCP0 to IPCP7). EG1m 374 EG0m Explanation 0 0 No edge detected (input capture stopped) 0 1 Rising edge 1 0 Falling edge 1 1 Both edges FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series Table 18.4-4 shows the relationship between the EG1m and EG0m bits and channels. Table 18.4-4 Relationship between bits and channels Input Capture Status Registers EG1m, EG0m Bits Supported Channel ICS01 EG11, EG01 ch.1 ICS23 EG13, EG03 ch.3 ICS45 EG15, EG05 ch.5 ICS67 EG17, EG07 ch.7 <Note> If a value other than "00" is written to these bits, the operation of the corresponding channel is enabled at the same time as a valid edge is selected. [bit1, bit0]: EG1n, EG0n (edge selection bits) These bits select a valid edge for the 32-bit input capture of the even-numbered channel. When the edge selected here is detected, the value of the 32-bit free-run timer is saved to the input capture data register (IPCP0 to IPCP7). EG1n CM71-10151-2E EG0n Explanation 0 0 No edge detected (input capture stopped) 0 1 Rising edge 1 0 Falling edge 1 1 Both edges FUJITSU MICROELECTRONICS LIMITED 375 CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series The bit names of EG1n and EG0n vary depending on the channel. Table 18.4-5 shows the relationship between bits and channels. Table 18.4-5 Relationship between bits and channels Input Capture Status Registers EG1n, EG0n Bits Supported Channel ICS01 EG10, EG00 ch.0 ICS23 EG12, EG02 ch.2 ICS45 EG14, EG04 ch.4 ICS67 EG16, EG06 ch.6 <Note> If a value other than "00" is written to these bits, the operation of the corresponding channel is enabled at the same time as a valid edge is selected. 376 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.4 MB91625 Series 18.4.2 Input Capture Data Register (IPCP0 to IPCP7) This register saves the value of the 32-bit free-run timer. When a valid edge is detected in the input signal through pins IN0 to IN7, the value of the 32-bit free-run timer is saved to this register. Figure 18.4-2 shows the bit configuration of the input capture data register (IPCP0 to IPCP7). Figure 18.4-2 Bit configuration of input capture data register (IPCP0 to IPCP7) bit 31 0 CP31 to CP0 Attribute R Initial value X R: Read only X: Undefined <Notes> • Be sure to read this register in units of words. • Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is to be saved to this register varies depending on the free-run timer select register (FRTSEL) setting. For details, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 377 CHAPTER 18 32-bit Input Capture 18.5 MB91625 Series 18.5 Interrupts Upon detection of a valid edge in the input signal through pins IN0 to IN7, an interrupt request is generated (edge detection interrupt request). Table 18.5-1 outlines the interrupts that can be used with the 32-bit input capture. Table 18.5-1 Interrupts of the 32-bit input capture Interrupt request Edge detection interrupt request Interrupt request flag Interrupt request enabled Clearing an interrupt request Even-numbered channel: ICPn=1 for ICS Odd-numbered channel: ICPm=1 for ICS Even-numbered channel: ICEn=1 for ICS Odd-numbered channel: ICEm=1 for ICS Write "0" to the next bit. Even-numbered channel: ICPn bit for ICS Odd-numbered channel: ICPm bit for ICS ICS: input capture status control register (ICS01 to ICS67) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests at the same time with interrupts enabled. 378 • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 18 32-bit Input Capture 18.6 18.6 An Explanation of Operations and Setting Procedure Examples This section explains the operation of the 32-bit input capture. Also, examples of procedures for setting the operating state are shown. 18.6.1 Explanation of 32-bit Input Capture Operation Upon detection of an input signal edge that is set in advance, the 32-bit input capture saves the value of the 32-bit free-run timer at the time. ■ Operation Selecting a valid edge with the following bits of the input capture status control register (ICS01 to ICS67) enables 32-bit input capture operation. • Selecting valid edge of odd-numbered channel/enabling operation: EG1m, EG0m • Selecting valid edge of even-numbered channel/enabling operation: EG1n, EG0n When a valid edge is detected at pins IN0 to IN7 while 32-bit input capture operation is enabled, the value of the 32-bit free-run timer at the time is saved to the input capture data register (IPCP0 to IPCP7). If interrupt request generation has been enabled, an edge detection interrupt request is generated. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 379 CHAPTER 18 32-bit Input Capture 18.6 MB91625 Series Figure 18.6-1 shows the 32-bit input capture operation. Figure 18.6-1 32-bit input capture operation In case of ch.0 and ch.1 Value of 32-bit free-run timer FFFF FFFFH BFFF FFFFH 7FFF FFFFH 3FFF FFFFH 0000 0000 H Time Reset IN0 pin IN1 pin Example of IN pin IPCP0 Undefined IPCP1 Undefined Example of IPCP Undefined 3FFFH 7FFFH BFFFH 3FFFH Interrupt request 0 Interrupt request 1 Example of interrupt request An interrupt request is generated again upon a valid edge. IN0 pin : Rising edge IN1 pin : Falling edge Example of IN pin : Both edges IPCP0 : Input capture data register 0 (IPCP0) IPCP1 : Input capture data register 1 (IPCP1) The interrupt request is cleared by software. <Note> Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is to be saved varies depending on the free-run timer select register (FRTSEL) setting. For details, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". 380 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 18 32-bit Input Capture 18.6 MB91625 Series When a valid edge is detected, a capture signal is generated to synchronize with the internal clock (peripheral clock). The generation of interrupt requests and the saving of 32-bit free-run timer values are performed based on the capture signals. Figure 18.6-2 shows an example of capture signal timing. Figure 18.6-2 Example of capture signal timing Internal clock (Peripheral clock) 32-bit free-run timer value Input capture input N N+1 Effective edge Capture signal IPCP N+1 Interrupt request IPCP: Input capture data register (IPCP0 to IPCP7) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 381 CHAPTER 18 32-bit Input Capture 18.6 382 FUJITSU MICROELECTRONICS LIMITED MB91625 Series CM71-10151-2E CHAPTER 19 32-bit Output Compare This chapter explains the functions and operations of the 32-bit output compare. 19.1 Overview 19.2 Configuration 19.3 Pins 19.4 Registers 19.5 Interrupts 19.6 An Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 383 CHAPTER 19 32-bit Output Compare 19.1 MB91625 Series 19.1 Overview After 32-bit free-run timer counts up to the preset value, the 32-bit output compare function inverts the level of output from a pin or generates an interrupt request. This series microcontroller has 8 built-in channels for the 32-bit output compare. ■ Overview The 32-bit output compare is part of the compare timer. The compare timer comprises the following three functions: - 32-bit free-run timer (2 channels) - 32-bit output compare (8 channels) - 32-bit input capture (8 channels) See "CHAPTER 17 32-bit Free-Run Timer". See "CHAPTER 18 32-bit Input Capture". This chapter explains the 32-bit output compare. • 2 channels of the 32-bit output compare can be used either independently of each other or as a pair. If the 2 channels of the 32-bit output compare are used as a pair, comparison can be performed by 2 channels at one time and thus the CPU load can be reduced. The combinations of channels that can be used as pairs are as follows: - ch.0 and ch.1 - ch.2 and ch.3 - ch.4 and ch.5 - ch.6 and ch.7 • The output levels at the OUT0 to OUT7 pins at the time of activation of the 32-bit output compare can be set. • An interrupt request can be generated when the count value of the 32-bit free-run timer matches the preset value (compare value). • Of the 2 channels of 32-bit free-run timer, the channel for use as the 32-bit output compare can be selected. For details of how to select the 32-bit free-run timer, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". 384 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.2 MB91625 Series 19.2 Configuration This section explains the configuration of the 32-bit output compare. ■ 32-bit output compare block diagram Figure 19.2-1 is a block diagram of the 32-bit output compare. Figure 19.2-1 32-bit output compare block diagram From the free-run timer selector Peripheral bus OCCP0, OCCP2 Output Inverted circuit Comparison circuit IOP1 OUT0, OUT2 pins IOP0 IOE1 IOE0 Interrupt request 0 OCCP1, OCCP3 Interrupt request 1 Comparison circuit Output Inverted circuit IOP1 IOP0 IOE1 IOE0 OUT1, OUT3 pins CMOD Interrupt request 2 OCCP4, OCCP6 Interrupt request 3 Output Inverted circuit Comparison circuit IOP1 OUT4, OUT6 pins IOP0 IOE1 IOE0 Interrupt request 4 OCCP5, OCCP7 Interrupt request5 Comparison circuit Output Inverted circuit IOP1 IOP0 IOE1 IOE0 OUT5, OUT7 pins CMOD Interrupt request 6 Interrupt request 7 OCCP0 to OCCP7: Output compare registers (OCCP0 to OCCP7) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 385 CHAPTER 19 32-bit Output Compare 19.2 • MB91625 Series Output compare register (OCCP0 to OCCP7) This register sets the value (compare value) to be compared with the count value of the 32-bit free-run timer. • Compare control register This register controls the operation of the 32-bit output compare. This register is divided into the following two registers: • - Compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) - Compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) Comparison circuit This circuit compares the count value of the 32-bit free-run timer and the compare value that is set in the output compare register (OCCP0 to OCCP7). <Note> For details of the compare timer block diagram, see "■ Compare timer block diagram" in "CHAPTER 17 32-bit Free-Run Timer". ■ Clocks Table 19.2-1 lists the clock used for the 32-bit output compare. Table 19.2-1 Clock used for 32-bit output compare Clock Name Operation clock 386 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.3 MB91625 Series 19.3 Pins This section explains the pins used by the 32-bit output compare. ■ Overview • OUT0 to OUT7 pins These are the output pins of the 32-bit output compare. These pins are multiplexed pins. For details of how to use these pins as the OUT0 to OUT7 pins of the 32-bit output compare, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 19.3-1 lists the relationship between channels and pins. Table 19.3-1 Relationship between channels and pins Channel CM71-10151-2E Output Pin 0 OUT0 1 OUT1 2 OUT2 3 OUT3 4 OUT4 5 OUT5 6 OUT6 7 OUT7 FUJITSU MICROELECTRONICS LIMITED 387 CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series 19.4 Registers This section explains the configuration and functions of the registers used by the 32-bit output compare. ■ 32-bit output compare registers Table 19.4-1 lists the registers of the 32-bit output compare. Table 19.4-1 Registers of 32-bit output compare Channel Abbreviated Register Name Reference Common FRTSEL Free-run timer select register 17.4.1 Common to 0 and 1 OCSH1 Compare control register upper1 19.4.2 OCSL0 Compare control register lower 0 19.4.3 OCSH3 Compare control register upper 3 19.4.2 OCSL2 Compare control register lower 2 19.4.3 OCSH5 Compare control register upper5 19.4.2 OCSL4 Compare control register lower 4 19.4.3 OCSH7 Compare control register upper7 19.4.2 OCSL6 Compare control register lower 6 19.4.3 0 OCCP0 Output compare register 0 19.4.1 1 OCCP1 Output compare register 1 19.4.1 2 OCCP2 Output compare register 2 19.4.1 3 OCCP3 Output compare register 3 19.4.1 4 OCCP4 Output compare register 4 19.4.1 5 OCCP5 Output compare register 5 19.4.1 6 OCCP6 Output compare register 6 19.4.1 7 OCCP7 Output compare register 7 19.4.1 Common to 2 and 3 Common to 4 and 5 Common to 6 and 7 388 Register Name FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series 19.4.1 Output Compare Register (OCCP0 to OCCP7) This register sets the value (compare value) to be compared with the count value of the 32-bit free-run timer. Set the compare value in this register before activating the 32-bit free-run timer. Figure 19.4-1 shows the bit configuration of the output compare register (OCCP0 to OCCP7). Figure 19.4-1 Bit configuration of output compare register (OCCP0 to OCCP7) 0 bit 31 OP31 to OP0 Attribute R/W Initial value 0 R/W: Read/Write <Notes> • This register can be rewritten even while the 32-bit free-run timer is active. • The value written to this register is immediately used as a compare value. Therefore, if the compare value is rewritten from a small value to a large value during operation of the 32-bit free-run timer, an interrupt request is generated twice while the 32-bit free-run timer counts once. To prevent this problem, rewrite this register by using interrupt processing by the 32-bit free-run timer. • Be sure to access this register in units of words (32 bits). • Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is to be compared with the value set in this register varies depending on the free-run timer select register (FRTSEL) setting. For details, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 389 CHAPTER 19 32-bit Output Compare 19.4 19.4.2 MB91625 Series Compare Control Register Upper (OCSH1, OCSH3, OCSH5, OCSH7) This register is used to specify whether to use the 2 channels of the 32-bit output compare independently of each other or as a pair. The register is also used to set the level of signals output through the OUT0 to OUT7 pins when the 32-bit output compare function is activated. Figure 19.4-2 shows the bit configuration of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7). Figure 19.4-2 Bit configuration of compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) bit 15 14 13 12 11 10 9 8 Undefined Undefined Undefined CMOD Undefined Undefined OTD1 OTD0 Attribute - - - R/W - - R/W R/W Initial value X X X 0 X X 0 0 R/W: Read/Write -: Undefined X: Undefined [bit15 to bit13]: Undefined bits 390 In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series [bit12]: CMOD (output level invert mode bit) This bit is used to specify whether to use the 2 channels of the 32-bit output compare independently of each other or as a pair. The invert mode of wave forms output from pins changes depending on this setting. Written Value Explanation 0 2 channels of the 32-bit output compare are used independently of each other. When the compare value of the output compare register (OCCP0 to OCCP7) matches the count value of the 32-bit free-run timer, the output level from the corresponding pin is inverted. 1 2 channels of the 32-bit output compare are used as a pair. When the compare value of the output compare register (OCCP0 to OCCP7) matches the value of the 32-bit free-run timer, the invert mode is inverted as shown below: When the count value matches the compare value of the even-numbered channel output compare register (OCCP0, OCCP2, OCCP4, OCCP6): the output levels from the following pins are inverted: - Output level from the pin corresponding to the channel - Output level from the pin corresponding to the odd-numbered channel used as a pair. When the count value matches the compare value of the odd-numbered channel output compare register (OCCP1, OCCP3, OCCP5, OCCP7): the output level from the following pin is inverted: - Output level from the pin corresponding to the channel CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 391 CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series Table 19.4-2 summarizes the invert timings for output levels from OUT0 to OUT7 pins when "1" is set to this bit. Table 19.4-2 Output level invert timing Register Whose Compare Value Matches the Value of the 32-bit Free-run Timer Pin Whose Output Level Inverts Output compare register 0 (OCCP0) OUT0 pin, OUT1 pin Output compare register 1 (OCCP1) OUT1 pin Output compare register 2 (OCCP2) OUT2 pin, OUT3 pin Output compare register 3 (OCCP3) OUT3 pin Output compare register 4 (OCCP4) OUT4 pin, OUT5 pin Output compare register 5 (OCCP5) OUT5 pin Output compare register 6 (OCCP6) OUT6 pin, OUT7 pin Output compare register 7 (OCCP7) OUT7 pin <Notes> • If the same compare value is set for the even-numbered and odd-numbered channels of the 32bit output compare, the operation is the same as when the 2 channels of the 32-bit output compare are used independently of each other, even when "1" is set to this bit. • Be sure to set "1" to this bit when the 2 channels of the 32-bit output compare are used as a pair. [bit11, bit10]: Reserved bits In case of writing Ignored In case of reading A value is undefined. [bit9]: OTD1 (output level bit) This bit sets the signal level output from pins (OUT1, OUT3, OUT5, OUT7) when the odd-numbered channel of the 32-bit output compare is activated. OTD1 In Case of Writing 0 The "L" level is output. 1 The "H" level is output. In Case of Reading The output level is read. <Note> Do not rewrite this bit during 32-bit output compare operation. 392 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series [bit8]: OTD0 (output level bit) This bit sets the signal level output from pins (OUT0, OUT2, OUT4, OUT6) when the even-numbered channels of the 32-bit output compare are activated. OTD0 In Case of Writing 0 The "L" level is output. 1 The "H" level is output. In Case of Reading The output level is read. <Note> Do not rewrite this bit during 32-bit output compare operation. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 393 CHAPTER 19 32-bit Output Compare 19.4 19.4.3 MB91625 Series Compare Control Register Lower (OCSL0, OCSL2, OCSL4, OCSL6) This register enables or disables 32-bit output compare operation or controls interrupt requests. Figure 19.4-3 shows the bit configuration of the compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6). Figure 19.4-3 Bit configuration of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) bit 7 6 5 4 3 2 1 0 IOP1 IOP0 IOE1 IOE0 Undefined Undefined CST1 CST0 R/W R/W R/W R/W – – R/W R/W 0 0 0 0 X X 0 0 Attribute Initial value R/W: Read/Write –: Undefined X: Undefined [bit7]: IOP1 (odd-numbered channel compare match interrupt request flag bit) This bit indicates that the compare value of the odd-numbered channel output compare register (OCCP1, OCCP3, OCCP5, OCCP7) matches the count value of the 32-bit free-run timer. If "1" is set to the IOE1 bit when this bit is "1", a compare match interrupt request is generated. IOP1 In Case of Reading In Case of Writing 0 A comparison result indicates no match. This bit is cleared to "0". 1 A comparison result indicates a match. Ignored <Note> When a read-modify-write instruction is used, "1" is read. 394 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series [bit6]: IOP0 (even-numbered channel compare match interrupt request flag bit) This bit indicates that the compare value of the even-numbered channel output compare register (OCCP0, OCCP2, OCCP4, OCCP6) matches the count value of the 32-bit free-run timer. If "1" is set to the IOE0 bit when this bit is "1", a compare match interrupt request is generated. IOP0 In Case of Reading In Case of Writing 0 A comparison result indicates no match. This bit is cleared to "0". 1 A comparison result indicates a match. Ignored <Note> When a read-modify-write instruction is used, "1" is read. [bit5]: IOE1 (odd-numbered channel compare match interrupt enable bit) This bit specifies whether to generate a compare match interrupt request when the value of the oddnumbered channel output compare register (OCCP1, OCCP3, OCCP5, OCCP7) matches the count value of the 32-bit free-run timer (IOP1=1). Written Value Explanation 0 Disables generation of compare match interrupt requests. 1 Enables generation of compare match interrupt requests. [bit4]: IOE0 (even-numbered channel compare match interrupt enable bit) This bit specifies whether to generate a compare match interrupt request when the value of the evennumbered channel output compare register (OCCP0, OCCP2, OCCP4, OCCP6) matches the count value of the 32-bit free-run timer (IOP0=1). Written Value Explanation 0 Disables generation of compare match interrupt requests. 1 Enables generation of compare match interrupt requests. [bit3, bit2]: Undefined bits CM71-10151-2E In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED 395 CHAPTER 19 32-bit Output Compare 19.4 MB91625 Series [bit1]: CST1 (odd-numbered channel compare enable bit) This bit enables or disables the comparison between odd-numbered channel 32-bit output compare and the count value of the 32-bit free-run timer. Written Value Explanation 0 Disables comparison. 1 Enables comparison. <Note> When the 32-bit free-run timer is stopped, the comparison of 32-bit output compare is also stopped. [bit0]: CST0 (even-numbered channel compare enable bit) This bit enables or disables the comparison between even-numbered channel 32-bit output compare and the count value of the 32-bit free-run timer. Written Value Explanation 0 Disables comparison. 1 Enables comparison. <Note> When the 32-bit free-run timer is stopped, the comparison of 32-bit output compare is also stopped. 396 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.5 MB91625 Series 19.5 Interrupts An interrupt request (compare match interrupt request) is generated when the count value of the 32bit free-run timer matches the value set in the output compare register (OCCP0 to OCCP7). Table 19.5-1 outlines the interrupts that can be used with the 32bit output compare. Table 19.5-1 Interrupts of the 32-bit output compare Interrupt request Compare result match interrupt request Interrupt request flag Interrupt request enabled Clearing an interrupt request Even-numbered channel: IOP0=1 for OCSL Odd-numbered channel: IOP1=1 for OCSL Even-numbered channel: IOE0=1 for OCSL Odd-numbered channel: IOE1=1 for OCSL Write "0" to the next bit Even-numbered channel: IOP0 bit for OCSL Odd-numbered channel: IOP1 bit for OCSL OCSL: compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use an interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 397 CHAPTER 19 32-bit Output Compare 19.6 MB91625 Series 19.6 An Explanation of Operations and Setting Procedure Examples This section explains the 32-bit output compare operation. Also, examples of procedures for setting the operating state are shown. ■ Overview 2 channels of the 32-bit output compare can be used either independently of each other or as a pair. 19.6.1 When the 2 Channels Are Used Independently of Each Other This section explains the 32-bit output compare operation when the 2 channels are used independently of each other. ■ Overview When the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) is set to "0", the 2 channels of the 32-bit output compare operate independently of each other. The output level of the pin corresponding to the channel is inverted when the count value of the 32-bit free-run timer matches the compare value of the output compare register (OCCP0 to OCCP7). <Note> Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is to be compared with the value set in the output compare register (OCCP0 to OCCP7) varies depending on the free-run timer select register (FRTSEL) setting. For details, see " 17.4.1 FreeRun Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". ■ Operation Writing "1" to the following bit enables the 32-bit output compare operation. • Enabling even-numbered channel operation: CST0 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) • Enabling odd-numbered channel operation: CST1 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) When the count value of the 32-bit free-run timer matches the compare value of the output compare register (OCCP0 to OCCP7) while the 32-bit output compare is enabled, the following bits are set to "1": 398 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.6 MB91625 Series • Even-numbered channel: IOP0 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) • Odd-numbered channel: IOP1 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) If interrupt request generation has been enabled, a compare match interrupt request is generated. Also, the output levels from the OUT0 to OUT7 pins are inverted. Figure 19.6-1 shows the operation in independent operation mode. Figure 19.6-1 Operation in independent operation mode Using ch.0 and ch.1 independently of each other Count value FFFF FFFFH BFFF FFFFH 7FFF FFFFH 3FFF FFFFH 0000 0000 H Time Reset OCCP0 BFFFH OCCP1 7FFFH OUT0 pin OUT1 pin Clearing an interrupt request Interrupt at ch.0 Clearing an interrupt request Interrupt at ch.1 Clearing an interrupt request Clearing an interrupt request Clearing an interrupt request Clearing an interrupt request OCCP0: Output compare register 0 (OCCP0) OCCP1: Output compare register 1(OCCP1) A compare match interrupt request or a change in the pin output level occurs upon detection of a compare match. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 399 CHAPTER 19 32-bit Output Compare 19.6 MB91625 Series Figure 19.6-2 shows the generation of compare match interrupt requests and changes in the pin output level. Figure 19.6-2 Generation of compare match interrupt requests and changes in the pin output level Peripheral clock (PCLK) Free-run timer count value N-1 Output compare register (OCCP0 to OCCP7) N N-1 N N Compare match output trigger Output level Interrupts Interrupts <Note> When using 2 channels of the 32-bit output compare independently of each other, be sure to write "0" to the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7). 19.6.2 When the 2 Channels Are Used as a Pair This section explains the 32-bit output compare operation using the even-numbered and oddnumbered channels in pairs. ■ Overview When the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) is set to "1", the 2 channels of the 32-bit output compare operate in pairs. By using the even-numbered and odd-numbered channels of the 32-bit output compare in pairs, compare values for 2 channels can be updated by 1 interrupt. The combinations of even-numbered and odd-numbered channels that can be used in pairs are as follows: 400 • ch.0 and ch.1 • ch.2 and ch.3 • ch.4 and ch.5 • ch.6 and ch.7 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 19 32-bit Output Compare 19.6 MB91625 Series ■ Operation Writing "1" to the following bit enables the 32-bit output compare operation. • Enabling even-numbered channel operation: CST0 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) • Enabling odd-numbered channel operation: CST1 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) When the count value of the 32-bit free-run timer matches the compare value of the output compare register (OCCP0 to OCCP7) while the 32-bit output compare is enabled, the following bits are set to "1": • Even-numbered channel: IOP0 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) • Odd-numbered channel: IOP1 bit of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6) If interrupt request generation has been enabled, a compare match interrupt request is generated. Also, the output levels from the OUT0 to OUT7 pins are inverted. The pin whose output level is inverted varies depending on the channel of the output compare register (OCCP0 to OCCP7) whose compare value matches the count value of the 32-bit free-run timer. Table 19.6-1 shows the relationship between the channels for which compare values are set and the pins whose output levels are inverted. Table 19.6-1 Relationship between the channels for which compare values are set and the pins whose output levels are inverted Register Whose Compare Value Matches the Value of the 32-bit Free-run Timer CM71-10151-2E Pin Whose Output Level Inverts Output compare register 0 (OCCP0) OUT0 pin, OUT1 pin Output compare register 1 (OCCP1) OUT1 pin Output compare register 2 (OCCP2) OUT2 pin, OUT3 pin Output compare register 3 (OCCP3) OUT3 pin Output compare register 4 (OCCP4) OUT4 pin, OUT5 pin Output compare register 5 (OCCP5) OUT5 pin Output compare register 6 (OCCP6) OUT6 pin, OUT7 pin Output compare register 7 (OCCP7) OUT7 pin FUJITSU MICROELECTRONICS LIMITED 401 CHAPTER 19 32-bit Output Compare 19.6 MB91625 Series Figure 19.6-3 shows the operation using even-numbered and odd-numbered channels in pairs. Figure 19.6-3 Operation using even-numbered and odd-numbered channels in pairs Using ch.0 and ch.1 in pairs. Count value FFFF FFFFH BFFF FFFFH 7FFF FFFFH 3FFF FFFFH 0000 0000 H Time Reset OCCP0 BFFFH OCCP1 7FFFH OUT0 pin OUT1 pin Clearing an interrupt request Interrupt at ch.0 Clearing an interrupt request Interrupt at ch.1 Clearing an interrupt request Clearing an interrupt request Corresponding to ch.0 Corresponding to ch.0 and ch.1 Clearing an interrupt request Clearing an interrupt request OCCP0: Output compare register 0 (OCCP0) OCCP1: Output compare register 1 (OCCP1) A compare match interrupt request or a change in the pin output level occurs upon detection of a compare match. See "19.6.1 When the 2 Channels Are Used Independently of Each Other" for details of the generation of compare match interrupt requests and changes in the pin output level. <Notes> 402 • When using even-numbered and odd-numbered channels of the 32-bit output compare in pairs, be sure to write "1" to the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7). • Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is to be compared with the value set in the output compare register (OCCP0 to OCCP7) varies depending on the free-run timer select register (FRTSEL) setting. For details, see "17.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 17 32-bit Free-Run Timer". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer This chapter explains the functions and operations of the 16-bit reload timer. 20.1 20.2 20.3 20.4 Overview Configuration Pins Registers 20.5 Interrupts 20.6 An Explanation of Operations and Setting Procedure Examples 20.7 Notes on Use CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 403 CHAPTER 20 16-bit Reload Timer 20.1 MB91625 Series 20.1 Overview The 16-bit reload timer is a down counter that performs a countdown from a preset value. This timer can be used as an interval timer that counts down synchronously with an internal clock (peripheral clock), and it can also be used as an event counter that counts external events. This series has 3 built-in channels of the 16-bit reload timer. ■ Overview • Timer mode: Internal timer mode and event counter mode are available. - Interval timer mode It counts down synchronously with an internal clock (peripheral clock). The internal clock (peripheral clock) is selected from 6 clock types, which are peripheral clocks (PCLK) divided by 2, 4, 8, 16, 32, and 64. - Event counter mode It detects and counts the edges (rising edge/falling edge/both edges) of the external clock. Cascade mode that counts ch.0 outputs with ch.1 and ch.1 outputs with ch.2 is also available. • Operation mode: One of the following two modes can be selected. - Reload mode In this mode, the reload value is reloaded, and counting is repeated when the down counter enters an underflow condition. - One shot mode In this mode, counting stops when the down counter enters an underflow condition. • Input pin function: In interval timer mode, the trigger input function or gate input function can be selected for the input pin function. - Trigger input function When it detects a valid edge (rising edge/falling edge/both edges) from the input pin, it starts counting. - Gate input function It continues counting as long as the input pin maintains its effective level of input. • 404 Interrupt request: It can generate an interrupt request when the down counter enters an underflow condition. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.2 MB91625 Series 20.2 Configuration This section explains the 16-bit reload timer configuration. ■ Block diagram of the 16-bit reload timer Figure 20.2-1 is a block diagram of the 16-bit reload timer. Peripheral bus Figure 20.2-1 Block diagram of the 16-bit reload timer Read/Write Read/Write TMRLRA Reload RELD Underflow INTE TMR Read only (Down counter) UF Interrupt request End of one shot OUTL Output FF TMO0 to TMO2 pins Peripheral clock (PCLK) Count control Counting enabled Trigger Trigger CNTE TRG Gate CSL2 CSL1 Select Clock select circuit CSL0 GATE Prescaler Peripheral clock (PCLK) TMI0 to Input + TMI2 pins SynchroPeripheral clock nization (PCLK) FF Edge Control Gate Control TRGM1 Select TRGM0 TMRLRA : 16-bit timer reload register A (TMRLRA0 to TMRLRA2) TMR : 16-bit timer control status register (TMR0 to TMR2) TMCSR : Timer control status register (TMCSR0 to TMCSR2) CM71-10151-2E TMCSR The bits are in random order. FUJITSU MICROELECTRONICS LIMITED 405 CHAPTER 20 16-bit Reload Timer 20.2 • MB91625 Series Timer control status register (TMCSR0 to TMCSR2) This register controls the operations of the 16-bit reload timer. • 16-bit timer reload register A (TMRLRA0 to TMRLRA2) This register sets the reload values. • 16-bit timer register (TMR0 to TMR2) This register operates as a down counter. When this register is read, the down counter value can be read. • Prescaler • Clock select circuit When the interval timer mode is selected, the prescaler divides the peripheral clock (PCLK). The clock select circuit selects a count clock. • Edge controller The edge controller controls the detection edges of signals when the TMI0 to TMI2 pins are used as trigger input pins. • Gate controller The gate controller controls the signal levels of the signals input from the pins when the TMI0 to TMI2 pins are used as gate input pins. • Count controller The count controller controls the counts of the 16-bit reload timer. ■ Clocks Table 20.2-1 shows the clock used for the 16-bit reload timer. Table 20.2-1 Clock used for the 16-bit reload timer Clock Name 406 Description Remarks Operation clock Peripheral clock (PCLK) - Count clock Internal clock (peripheral clock) Created through division of the peripheral clock (PCLK). External clock Input from TMI0 to TMI2 pins FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.3 MB91625 Series 20.3 Pins This section explains the pins of the 16-bit reload timer. ■ Overview There are two types of 16-bit reload timer as follows. • TMO0 to TMO2 pins 16-bit reload timer wave form output pin These pins are multiplexed pins. For information on using as the wave form output pin of the 16-bit reload timer, see "2.4 Setting Method for Pins". • TMI0 to TMI2 pins 16-bit reload timer input pin This inputs count clock, clock, trigger, or gate depending on its setting. These pins are multiplexed pins. For information on using as the input pin of the 16-bit reload timer, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 20.3-1 outlines the relationship between channels and pins. Table 20.3-1 Relationship between channels and pins Channel CM71-10151-2E Wave Form Output Pin Input Pin 0 TMO0 TMI0 1 TMO1 TMI1 2 TMO2 TMI2 FUJITSU MICROELECTRONICS LIMITED 407 CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series 20.4 Registers This section explains the configuration and functions of registers used by the 16-bit reload timer. ■ Registers of 16-bit reload timer Table 20.4-1 lists the registers of the 16-bit reload timer. Table 20.4-1 Registers of 16-bit reload timer Channel Abbreviated Register Name 0 TMCSR0 Timer control status register 0 20.4.1 TMRLRA0 16-bit timer reload register A0 20.4.2 TMR0 16-bit timer register 0 20.4.3 TMCSR1 Timer control status register 1 20.4.1 TMRLRA1 16-bit timer reload register A1 20.4.2 TMR1 16-bit timer register 1 20.4.3 TMCSR2 Timer control status register 2 20.4.1 TMRLRA2 16-bit timer reload register A2 20.4.2 TMR2 16-bit timer register 2 20.4.3 1 2 408 Register Name FUJITSU MICROELECTRONICS LIMITED Reference CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series 20.4.1 Timer Control Status Register (TMCSR0 to TMCSR2) This register controls the operations of the 16-bit reload timer. Figure 20.4-1 shows the bit configuration of the timer control status registers (TMCSR0 to TMCSR2). Figure 20.4-1 Bit configuration of the timer control status registers (TMCSR0 to TMCSR2) bit 15 14 13 12 11 10 9 8 Reserved Reserved TRGM1 TRGM0 CSL2 CSL1 CSL0 GATE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Undefined Undefined OUTL RELD INTE UF CNTE TRG Attribute - - R/W R/W R/W R/W R/W R/W Initial value X X 0 0 0 0 0 0 Attribute Initial value bit R/W: Read/Write -: Undefined X: Undefined [bit15, bit14]: Reserved bits In case of writing Always write "0" to this (these) bit (bits). In case of reading "0" is read. [bit13, bit12]: TRGM1, TRGM0 (Input pin operation selection bit) This bit selects the operation of TMI0 to TMI2 pins of the 16-bit reload timer.The meaning of this bit varies depending whether the 16-bit reload timer is used in interval timer mode, or in event counter mode. • Interval timer mode (CSL2 to CSL0 = 000 to 101) - Select the trigger input function with TMI0 to TMI2 pins (GATE = 0). Select an effective edge. When the edge set with this bit is detected in the signal input from the TMI0 to TMI2 pins, the down counter starts counting down. - Select the gate function with TMI0 to TMI2 pins (GATE = 1). Select an effective level. The down counter counts down only while the signal of the level that is set with this bit is input from the TMI0 to TMI2 pins. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 409 CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series When the Gate Function Is Selected (GATE =1) TRGM1 TRGM0 0 0 Edge detection disabled "L" level 0 1 Rising edge "H" level 1 0 Falling edge "L" level 1 1 Both edges "H" level * When the Trigger Input Is Selected * (GATE =0) When "1" is written in the TRG bit, the down counter starts counting down regardless of the setting of this bit. • In event counter mode (CSL2 to CSL0 = 110, 111) Select an effective edge. When the edge set with this bit is detected in the signal input from the TMI0 to TMI2 pins, the down counter starts counting down. TRGM1 TRGM0 Explanation 0 0 Setting prohibited 0 1 Rising edge 1 0 Falling edge 1 1 Both edges <Note> Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE = 0). If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless of the value of the CNTE bit. 410 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series [bit11 to bit9]: CSL2 to CSL0 (Count source selection bits) This bit selects the timer mode of the 16-bit reload timer. In interval timer mode, it also selects the division rate of the peripheral clock (PCLK), and in event counter mode, it also selects whether to use cascade mode and whether to use the external clock. * CSL2 CSL1 CSL0 Explanation 0 0 0 0 0 1 Peripheral clock (PCLK) divided by 4 (= 22) 0 1 0 Peripheral clock (PCLK) divided by 8 (= 23) 0 1 1 Peripheral clock (PCLK) divided by 16 (= 24) 1 0 0 Peripheral clock (PCLK) divided by 32 (= 25) 1 0 1 Peripheral clock (PCLK) divided by 64 (= 26) 1 1 0 1 1 1 Interval timer mode Event counter mode Peripheral clock (PCLK) divided by 2 (= 21) Cascade mode* External clock For information on the operation when cascade mode is selected, see "20.6.3 Operation in Cascade Mode". <Notes> • Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE = 0). If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless of the value of the CNTE bit. • To use the 2-channel 16-bit reload timer connected in cascade, set this bit as shown below. - Channel with smaller number: Select interval timer mode or an external clock. - Channel with larger number: Specify cascade mode. • When event counter mode is selected for this bit, the setting of the GATE bit is ignored. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 411 CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series [bit8]: GATE (Gate input enable bit) When the timer mode is set to interval timer mode, this bit selects the functions to be assigned to the TMI0 to TMI2 pins. • Trigger input function: When an effective edge is input from TMI0 to TMI2 pins, a countdown starts. • Gate function: A countdown is performed only while the effective level signal is input from TMI0 to TMI2 pins. Written Value Explanation 0 Trigger input function 1 Gate function <Notes> • Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE = 0). If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless of the value of the CNTE bit. • If event counter mode is selected with CSL2 to CSL0 bits (CSL2 to CSL0 = 110/111), this bit setting is ignored. [bit7, bit6]: Undefined bits In case of writing Ignored In case of reading A value is undefined. [bit5]: OUTL (Output polarity setting bit) When the 16-bit reload timer is activated, this bit sets the signal level of the signals to be output from TMO0 to TMO2 pins. Written Value Explanation 0 Normal polarity ("L" level) 1 Inverted polarity ("H" level) <Note> Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE = 0). If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless of the value of the CNTE bit. 412 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series [bit4]: RELD (Reload operation enable bit) This bit selects any of the following operation modes for the 16-bit reload timer. • One shot mode When the down counter enters an underflow condition, counting stops in this mode until the next activation trigger is input. • Reload mode When the down counter enters an underflow condition in this mode, the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter so that it continues counting. Written Value Explanation 0 One shot mode 1 Reload mode <Note> Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE = 0). If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless of the value of the CNTE bit. [bit3]: INTE (Interrupt request enable bit) This bit sets whether to generate the underflow interrupt request when the down counter underflows (UF bit = 1). Written Value Explanation 0 Disables generation of underflow interrupt requests. 1 Enables generation of underflow interrupt requests. [bit2]: UF (Underflow interrupt request flag bit) This bit indicates that the down counter enters an underflow condition. If the INTE is set to "1" when this bit is "1", an underflow interrupt request is generated. UF CM71-10151-2E In Case of Reading In Case of Writing 0 The down counter has not entered an underflow condition. This bit is cleared to "0". 1 The down counter has entered an underflow condition. Ignored FUJITSU MICROELECTRONICS LIMITED 413 CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series [bit1]: CNTE (Count operation enable bit) This bit enables/disables the operation of the down counter. Written Value Explanation 0 Stops the count operation. 1 Enables the count operation (activation trigger wait). <Note> If "0" is written to this bit during a down counter operation, the down counter stops. [bit0]: TRG (Software trigger bit) This bit activates the 16-bit reload timer through software. When "1" is written to this bit, the down counter loads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and starts counting. TRG In Case of Writing 0 Ignored 1 Activates the 16-bit reload timer. In Case of Reading "0" is read. <Notes> 414 • The down counter does not operate while the CNTE bit is "0" even if "1" is written to this bit. • When the 16-bit reload timer operation is enabled (CNTE=1), if "1" is written to this bit, the down counter starts regardless of the setting of TRGM1 or TRGM0 bit. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.4 MB91625 Series 20.4.2 16-bit Timer Reload Register A (TMRLRA0 to TMRLRA2) This register sets the initial value of the down counter. In reload mode, if an underflow occurs, the value of this register is reloaded to the down counter. Figure 20.4-2 shows the bit configuration of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2). Figure 20.4-2 Bit configuration of 16-bit timer reload register A (TMRLRA0 to TMRLRA2) bit 15 0 D15 to D0 Attribute R/W Initial value X R/W: Read/Write X: Undefined When the counter completes counting the value set to this register + 1, an underflow occurs.The signal level of the signals output from TMO0 to TMO2 pins is inverted. <Note> Be sure to access this register in units of half words. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 415 CHAPTER 20 16-bit Reload Timer 20.4 20.4.3 MB91625 Series 16-bit Timer Register (TMR0 to TMR2) When this register is read, the down counter value can be read. Figure 20.4-3 shows the bit configuration of the 16-bit timer registers (TMR0 to TMR2). Figure 20.4-3 Bit configuration of 16-bit timer register (TMR0 to TMR2) bit 15 0 D15 to D0 Attribute R Initial value X R: Read only X: Undefined <Note> Be sure to read this register in units of half words. 416 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.5 MB91625 Series 20.5 Interrupts An underflow interrupt request is generated when the down counter enters an underflow condition. ■ Overview Table 20.5-1 outlines the interrupts that can be used with the 16-bit reload timer Table 20.5-1 Interrupts of the 16-bit reload timer Interrupt request Underflow interrupt request Interrupt request flag UF=1 for TMCSR Interrupt request enabled INTE=1 for TMCSR Clearing an interrupt request Write "0" to the UF bit for TMCSR TMCSR: timer control status register (TMCSR0 to TMCSR2) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. • For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For information on the settings of the interrupt levels, see "CHAPTER 10 Interrupt Controller". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 417 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series 20.6 An Explanation of Operations and Setting Procedure Examples This chapter explains the operations of the 16-bit reload timer. Also, examples of procedures for setting the operating state are shown. ■ Overview The 16-bit reload timer is a down counter that counts down from a preset value.One of the following timer modes can be selected using the CSL2 to CSL0 bits of the timer control status register (TMCSR0 to TMCSR2). • Interval timer mode (CSL2 to CSL0 = 000 to 101) It operates with the count clock, which is the divided peripheral clock (PCLK). • Event counter mode (CSL2 to CSL0 = 110, 111) In this mode, the counter counts every time an effective edge is input from TMI0 to TMI2 pins. Cascade mode that counts ch.0 outputs with ch.1 and ch.1 outputs with ch.2 is also available. ■ How to set the signal level of the signals output from TMO0 to TMO2 pins. The signal level of the signals output from TMO0 to TMO2 pins varies with the settings of OUTL bit of the timer control status register (TMCSR0 to TMCSR2). ● In reload mode Table 20.6-1 shows the signal level of the signals output from TMO0 to TMO2 pins in reload mode. Table 20.6-1 Signal level in reload mode Normal polarity (OUTL = 0) When the 16-bit reload timer is activated "L" level Subsequent Inverted polarity (OUTL = 1) "H" level The output level is inverted every time an underflow occurs. ● In one shot mode Table 20.6-2 shows the signal level of the signals output from TMO0 to TMO2 pins in one shot mode. Table 20.6-2 Signal level in one shot mode Normal polarity (OUTL = 0) 418 Inverted polarity (OUTL = 1) When the 16-bit reload timer is activated "L" level "H" level When an activation trigger is input "H" level "L" level When an underflow occurs "L" level "H" level FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-1 shows the OUTL bits of the timer control status register (TMCSR0 to TMCSR2) and their output wave forms. Figure 20.6-1 OUTL bits of the timer control status registers (TMCSR0 to TMCSR2) and their output wave forms Mode Initial value OUTL Activation trigger Counting Underflow Underflow Underflow 0 Reload 1 0 trigger wait state One shot 1 20.6.1 Operation in Interval Timer Mode This section explains the operation for using the 16-bit reload timer that counts synchronously with the internal clock (peripheral clock) in interval timer mode. The count clock is generated by dividing the peripheral clock (PCLK). ■ Setting This section also explains the settings required for using the 16-bit reload timer in interval timer mode. ● Interval timer mode settings To use the 16-bit reload timer in interval timer mode, make any of the following settings for the CSL2 to CSL0 bits of the timer control status register (TMCSR0 to TMCSR2), and select the division rate of the peripheral clock (PCLK). CM71-10151-2E CSL2 CSL1 CSL0 Timer Mode 0 0 0 0 0 1 Divided by 4 (= 22) 0 1 0 Divided by 8 (= 23) 0 1 1 Divided by 16 (= 24) 1 0 0 Divided by 32 (= 25) 1 0 1 Divided by 64 (= 26) Interval timer mode Division Rate of Peripheral Clock Divided by 2 (= 21) FUJITSU MICROELECTRONICS LIMITED 419 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Operation mode settings In interval timer mode, one of the following operation modes can be selected using the RELD bits of the timer control status register (TMCSR0 to TMCSR2). • Reload mode (RELD = 1) When the down counter enters an underflow condition, it reloads the value set to the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and repeats counting in this mode. Figure 20.6-2 shows the basic operation in reload mode. Figure 20.6-2 Basic operation in reload mode TMO0 to TMO2 pins Activation trigger TMRLRA value + 1 TMRLRA value + 1 Underflow Counter value TMRLRA value :0000 TMRLRA value :0000 TMRLRA value Countdown • One shot mode (RELD = 0) In this mode, counting stops when the down counter enters an underflow condition. Figure 20.6-3 shows the basic operation in one shot mode. Figure 20.6-3 Basic operation in one shot mode TMO0 to TMO2 pins Activation trigger TMRLRA value + 1 Underflow Counter value TMRLRA value 0000 FFFF Countdown 420 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● TMI0 to TMI2 pin function settings Using TRGM1 and TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2) and the GATE bit, the function of TMI0 to TMI2 pins can be selected from the following list. Table 20.6-3 shows the combination of bits. Table 20.6-3 Combination of bits TRGM1, TRGM0 GATE Pin Function 00 0 TMI0 to TMI2 pins do not work. 01 0 TMI0 to TMI2 pins operate as the trigger input function. The effective edge is a rising edge. 10 0 TMI0 to TMI2 pins operate as the trigger input function. The effective edge is a falling edge. 11 0 TMI0 to TMI2 pins operate as the trigger input function. The effective edge is both edges. 00/10 1 TMI0 to TMI2 pins operate as the gate input function. The effective level is "L". 01/11 1 TMI0 to TMI2 pins operate as the gate input function. The effective level is "H". ■ Pulse width calculation How to calculate the pulse width of the signals output from TMO0 to TMO2 pins in interval timer mode is explained below. Pulse width = T × (L + 1) L Value set to the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) T Cycles of the count clock ■ How to calculate underflow cycles If the down counter attempts to count further from the value of "0000H", an underflow occurs. A cycle from when the down counter starts counting to when an underflow occurs is set in the 16-bit timer reload register (TMRLRA0 to TMRLRA2). The following shows how to calculate the underflow cycles. T × (L + 1) T Cycles of the count clock L Value set to the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 421 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ■ Operations in reload mode (TMI0 to TMI2 pins = trigger input) In this mode, TMI0 to TMI2 pins are used for trigger input, and the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded each time underflow occurs to continue a countdown. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • One of the TRGM1, TRGM0 bits = 01 to 11 • GATE bit = 0 • RELD bit = 1 ● Activate Use the following procedure for activating. 1. Use the CNTE bit of the timer control status register (TMCSR0 to TMCSR2) to enable the operation of the 16-bit reload timer (CNTE = 1). The 16-bit reload timer enters the activation trigger wait state. 2. The activation trigger is input in either of the following ways: - Input the edge set in the TRGM1, TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2) from TMI0 to TMI2 pins. - Write "1" to the TRG bit of the timer control status register (TMCSR0 to TMCSR2). The prescaler is cleared. The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is loaded to the down counter, and counting starts. Figure 20.6-4 shows an activation. Figure 20.6-4 Activation (TMI0 to TMI2 pins at an activation, effective edge = rising edge) Peripheral clock (PCLK) CNTE bit TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Prescaler cleared Prescaler clock Data load Counter value TMRLRA value -1 -1 -1 TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) <Note> Be sure that the pulse width of the activation trigger input from TMI0 to TMI2 pins never falls below 2T (T: cycle of the peripheral clock (PCLK)). 422 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Count operation The down counter starts a countdown synchronously with the count clock from the value of 16-bit timer reload register A (TMRLRA0 to TMRLRA2). If counting starts from the down counter value "0000H", an underflow occurs, and the following operations are performed. • The UF bit of the timer control status register (TMCSR0 to TMCSR2) is changed to "1". • The signal level of the signals output from TMO0 to TMO2 pins is inverted. • The timer reloads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and continues counting. As described, every time an underflow occurs, the timer reloads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and continues counting. Figure 20.6-5 shows the count operation. Figure 20.6-5 Count operation (activation through software, output polarity = normal polarity) Reloaded registers TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA Underflow UF bit TMO0 to TMO2 pin CNTE bit Data load TRG bit Activation trigger wait state count operation TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ● Operation of interrupt processing If the down counter enters an underflow condition , the UF bit of the timer control status register (TMCSR0 to TMCSR2) changes to "1". In this case, if the INTE bit of the timer control status register (TMCSR0 to TMCSR2) is set to "1", an underflow interrupt request is generated. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 423 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-6 shows the underflow interrupt request generation timing. Figure 20.6-6 Underflow interrupt request generation timing Count clock Counter value 0001H 0000H TMRLRA value -1 -1 -1 Underflow UF bit Underflow interrupt request TMRLRA: Reload timer reload register (TMRLRA0 to TMRLRA2) When "0" is written to the UF bit of the timer control status register (TMCSR0 to TMCSR2), the underflow interrupt request can be cleared. <Note> If an underflow interrupt request is generated at the same time the other underflow interrupt request is cleared, the clearing operation is ignored, and the underflow interrupt request remains generated. ● Retrigger operation If an activation trigger of the 16-bit reload timer is detected during a count operation, the retrigger is generated, and the following operations are performed. 424 • The signal level of TMI0 to TMI2 pins is initialized. • The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter. • The prescaler is cleared. • Count operation starts. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-7 shows the operation when a retrigger is generated. Figure 20.6-7 Operation when a retrigger is generated. (Retrigger generated on TMI0 to TMI2 pins, effective edge = rising edge) Count clock TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Retrigger TRG bit Trigger CNTE bit Prescaler cleared Counter value TMRLRA reload -1 -1 TMRLRA reload -1 -1 -1 TMO0 to TMO2 pins TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) <Note> When the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is rewritten, if a retrigger occurs at the same time the reload value is changed, the down counter loads the value before the change. The value after change is loaded at the next reloading. ■ Operations in reload mode (TMI0 to TMI2 pins = at a gate input) In this mode, TMI0 to TMI2 pins are used for gate input, and the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded each time underflow occurs to continue a countdown. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • TRGM0 bit = 0/1 • GATE bit = 1 • RELD bit = 1 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 425 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Activate Use the following procedure for activating. 1. Use the CNTE bit of the timer control status register (TMCSR0 to TMCSR2) to enable the operation of the 16-bit reload timer (CNTE = 1). The 16-bit reload timer enters the activation trigger wait state. 2. Input an activation trigger using the TRG bit of the timer control status register (TMCSR0 to TMCSR2). (TRG = 1) The prescaler is cleared. The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is loaded to the down counter, and the 16-bit reload timer enters the effective input polarity (from TMI0 to TMI2 pins) wait state. 3. Input the signal with the level set in the TRGM1, TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2) from TMI0 to TMI2 pins. The counter starts counting. Figure 20.6-8 shows an activation operation. Figure 20.6-8 Activation operation Peripheral clock (PCLK) CNTE bit TRG bit Prescaler cleared Prescaler clock Data load TMI0 to TMI2 pins Counter value TMRLRA value -1 -1 TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) <Note> Be sure that the effective level input from TMI0 to TMI2 pins never falls below 2T (T: cycle of the peripheral clock (PCLK)). 426 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Count operation Only while the effective level signal is input from TMI0 to TMI2 pins does the down counter perform a countdown from the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) synchronously with the count clock. If the effective level signal is not input from TMI0 to TMI2 pins, the down counter stops counting. If the effective level signal is input while the down counter is stopped, the counter starts counting from the value where it stopped. The subsequent operations are the same as those when TMI0 to TMI2 pins = trigger input function is set. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". Figure 20.6-9 shows the count operation. Figure 20.6-9 Count operation (effective level = "H" level, output polarity = normal polarity) Reloaded register TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA Underflow UF bit OUTE bit TMRLRA + 1 Count TMRLRA + 1 Count TMRLRA + 1 Count TMRLRA + 1 Count TMRLRA + 1 Count TMRLRA + 1 Count TMO0 to TMO2 pins TMI0 to TMI2 pins CNTE bit Data load TRG bit Activation trigger wait state Effective gate input wait state Count operation TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ● Operation of interrupt processing The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". ● Retrigger operation If an activation trigger of the 16-bit reload timer is detected during a count operation, the retrigger is generated, and the following operations are performed. • The signal level of TMI0 to TMI2 pins is initialized. • The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter. • The prescaler is cleared. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 427 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series When an effective level signal is input from TMI0 to TMI2 pin in such condition, counting starts. Figure 20.6-10 shows the operation when a retrigger is generated. Figure 20.6-10 Operation when a retrigger is generated (effective level = "H" level) Count clock TMI0 to TMI2 pins CNTE bit Prescaler cleared Counter value TMRLRA value TRG bit -1 -1 -1 TMRLRA value -1 -1 -1 Retrigger TMO0 to TMO2 pins TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ■ Operations in one shot mode (TMI0 to TMI2 pins = trigger input) When TMI0 to TMI2 pins are used for trigger input, if an underflow occurs, this mode stops counting until the next activation trigger is input. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • One of the TRGM1, TRGM0 bits = 01 to 11 • GATE bit = 0 • RELD bit = 0 ● Activate The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". However, if an activation trigger is detected in one shot mode, the signal level of the signals output from TMO0 to TMO2 pins is inverted. ● Count operation The down counter starts a countdown synchronously with the count clock from the value of 16-bit timer reload register A (TMRLRA0 to TMRLRA2). If counting starts from the down counter value "0000H", an underflow occurs, and the following operations are performed. 428 • The UF bit of the timer control status register (TMCSR0 to TMCSR2) is changed to "1". • The signal level of the signals output from TMO0 to TMO2 pins is initialized. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series • Counting is stopped, and the counter enters the activation trigger wait state (the down counter value stops at "FFFFH"). Figure 20.6-11 shows the count operation when TMI0 to TMI2 pins are used for activation. Figure 20.6-11 Count operation (effective edge = rising edge, output polarity = normal polarity) Count clock TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Counter value 0001H 0000H FFFFH TMRLRA -1 -1 Underflow UF bit TMO0 to TMO2 pins Reload Activation trigger wait state count operation TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 429 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-12 shows the detailed operation when an underflow occurs. Figure 20.6-12 Detailed operation when an underflow occurs. (effective edge = rising edge, output polarity = normal polarity) Underflow TMO0 to TMO2 pins CNTE bit TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Activation trigger wait state count operation TMRLRA+1 Count TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ● Operation of interrupt processing The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". ● Retrigger operation The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". However, if a retrigger is detected in one shot mode, the signal level of the signals output from TMO0 to TMO2 pins is inverted. ■ Operations in one shot mode (TMI0 to TMI2 pins = gate input) When TMI0 to TMI2 pins are used for gate input, if an underflow occurs, this mode stops counting until the next activation trigger is input. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • TRGM0 bit = 0/1 • GATE bit = 1 • RELD bit = 0 ● Activate The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = at a gate input)". However, if an activation trigger is detected in one shot mode, the signal level of the signals output from TMO0 to TMO2 pins is inverted. 430 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Count operation Only while the effective level signal is input from TMI0 to TMI2 pins does the down counter counts down from the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) synchronously with count clock. If the effective level signal is not input from TMI0 to TMI2 pins, the down counter stops counting. If the effective level signal is input while the down counter is stopped, the counter starts counting from the value where it stopped. If counting starts from the down counter value "0000H", an underflow occurs, and the following operations are performed. • The UF bit of the timer control status register (TMCSR0 to TMCSR2) is changed to "1". • The signal level of the signals output from TMO0 to TMO2 pins is initialized. • Counting is stopped, and the counter enters the activation trigger wait state (the down counter value stops at "FFFFH"). Figure 20.6-13 shows the count operation. Figure 20.6-13 Count operation (effective level = "H" level, output polarity = normal polarity) Underflow TMO0 to TMO2 pins CNTE bit TMI0 to TMI2 pins TRG bit Activation trigger wait state Effective gate input wait state count operation TMRLRA + 1 Count TMRLRA + 1 Count TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ● Operation of interrupt processing The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)". ● Retrigger operation The operation is the same as in reload mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = at a gate input)". However, if a retrigger is detected in one shot mode, the signal level of the signals output from TMO0 to TMO2 pins is inverted. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 431 CHAPTER 20 16-bit Reload Timer 20.6 20.6.2 MB91625 Series Operations in Event Counter Mode This section explains the operations for using 16-bit reload timer as an event counter. This section explains the operation for counting external events. ■ Overview In event counter mode, external events input from TMI0 to TMI2 pins are counted. It performs a countdown every time an effective edge is input from TMI0 to TMI2 pins. For information on cascade mode, see "20.6.3 Operation in Cascade Mode". ■ Setting ● Event counter mode settings To use the 16-bit reload timer in event counter mode, set CSL2 to CSL0 bits of the timer control status register (TMCSR0 to TMCSR2) as shown below. CSL2 CSL1 CSL0 1 1 1 Mode Event counter mode Count Clock External clock ● Operation mode settings In event counter mode, one of the following operation modes can be selected using the RELD bits of the timer control status register (TMCSR0 to TMCSR2). • Reload mode (RELD = 1) When the down counter enters an underflow condition, it reloads the value set to the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and repeats counting in this mode. • One shot mode (RELD = 0) In this mode, counting stops when the down counter enters an underflow condition. ● Effective edge settings The 16-bit reload timer performs a count down every time an effective edge is input from TMI0 to TMI2 pins. The effective edge can be selected from the following settings of TRGM1 and TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2). TRGM1, TRGM0 432 Pin Function 00 TMI0 to TMI2 pins do not work. 01 Rising edge 10 Falling edge 11 Both edges FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ■ Operation in reload mode In this mode, every time an underflow occurs, the timer reloads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and continues counting. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • One of the TRGM1, TRGM0 bits = 01 to 11 • RELD bit = 1 ● Activate Use the following procedure for activating. 1. Use the CNTE bit of the timer control status register (TMCSR0 to TMCSR2) to enable the operation of the 16-bit reload timer (CNTE = 1). The 16-bit reload timer enters the activation trigger wait state. 2. Input an activation trigger using the TRG bit of the timer control status register (TMCSR0 to TMCSR2). (TRG = 1) The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is loaded to the down counter, and the 16-bit reload timer enters the effective edge detection (of the signal output from TMI0 to TMI2 pins) wait state. 3. Input the effective edge set in the TRGM1, TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2) from TMI0 to TMI2 pins. The counter starts counting. ● Count operation Every time an effective edge is detected in the input signal from TMI0 to TMI2 pins, it performs a countdown. Figure 20.6-14 to Figure 20.6-16 show the count timing. Figure 20.6-14 Count timing (effective edge = rising edge) Peripheral clock (PCLK) TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Counter value TMRLRA value -1 -1 -1 TRG bit TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) Figure 20.6-15 Count timing (effective edge = falling edge) Peripheral clock (PCLK) TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Counter value TMRLRA value -1 -1 -1 TRG bit TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 433 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-16 Count timing (effective edge = both edges) Peripheral clock (PCLK) TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Counter value -1 TMRLRA value -1 -1 -1 -1 -1 TRG bit TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) If counting starts from the down counter value "0000H", an underflow occurs, and the following operations are performed. • The UF bit of the timer control status register (TMCSR0 to TMCSR2) is changed to "1". • The signal level of the signals output from TMO0 to TMO2 pins is inverted. • The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter. • The counter continues counting when an effective level signal is input from TMI0 to TMI2 pins. As described, every time an underflow occurs, the timer reloads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and continues counting. After an underflow occurs, counting does not start until an effective edge of the signal input from TMI0 to TMI2 pins is detected. Figure 20.6-17 shows the count operation. Figure 20.6-17 Count operation (detection edge = both edges, output polarity = normal polarity) Reloaded registers TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA Underflow UF bit OUTE bit TMO0 to TMO2 pins TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge TRG bit Data load Counter value A -1 A -1 0000H A -1 A 0000H A -1 0000H TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) 434 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Operation of interrupt processing The operation is the same as in interval timer mode. See "■ Operations in reload mode (TMI0 to TMI2 pins = trigger input)" in "20.6.1 Operation in Interval Timer Mode". ● Retrigger operation If an activation trigger of the 16-bit reload timer is detected during a count operation, the retrigger is generated, and the following operations are performed. • The signal level of the signals output from TMO0 to TMO2 pins is initialized to the level set in the OUTL bit of the timer control status register (TMCSR0 to TMCSR2). • The value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter. When an effective edge is input from TMI0 to TMI2 pin in such condition, counting starts. ■ Operation in one shot mode When an underflow occurs, counting stops in this mode until the next activation trigger is input. In this mode, set the timer control status register (TMCSR0 to TMCSR2) as follows: • One of the TRGM1, TRGM0 bits = 01 to 11 • RELD bit = 0 ● Activate The operation is the same as in reload mode. See "■ Operation in reload mode". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 435 CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series ● Count operation Every time an effective edge is detected from TMI0 to TMI2 pins, the counter counts down. If counting starts from the down counter value "0000H", an underflow occurs, and the following operations are performed. • The UF bit of the timer control status register (TMCSR0 to TMCSR2) is changed to "1". • The signal level of the signals output from TMO0 to TMO2 pins is initialized. • Counting is stopped, and the counter enters the activation trigger wait state (the down counter value stops at "FFFFH"). Figure 20.6-18 and Figure 20.6-19 show the count operations. Figure 20.6-18 Count operation (detection edge = both edges) Underflow UF bit TMO0 to TMO2 pins (OUTL = 0) TMO0 to TMO2 pins (OUTL = 1) TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge TRG bit Reload Counter value TMRLRA -1 FFFFH TMRLRA FFFFH -1 0000H 0000H TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) 436 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.6 MB91625 Series Figure 20.6-19 Count operation (detection edge = rising edges) Peripheral clock (PCLK) TMI0 to TMI2 pins TMI0 to TMI2 pins effective edge Counter value 0001H 0000H FFFFH TMRLRA -1 -1 Underflow UF bit TRG bit Activation trigger wait state Data load TMRLRA: 16-bit timer reload register A (TMRLRA0 to TMRLRA2) ● Operation of interrupt processing The operation is the same as in reload mode. See "■ Operation in reload mode". ● Retrigger operation The operation is the same as in reload mode. See "■ Operation in reload mode". 20.6.3 Operation in Cascade Mode In cascade mode, ch.1 can count the outputs from ch.0 of the 16-bit reload timer, and ch.2 can count the outputs from ch.1. This section explains the operations in cascade mode. ■ Operation The following shows the count operation when cascade mode is selected with the CSL2 to CSL0 bits (CSL2 to CSL0 = 110) of the timer control status register (TMCSR0 to TMCSR2). • When ch.1 is connected in cascade mode It counts the outputs from ch.0. Figure 20.6-20 shows the I/O operation when ch.1 is used in cascade mode. Figure 20.6-20 I/O operation when ch.1 is used in cascade mode TMI0 pin ch.0 TMO0 pin TMI1 pin ch.1 TMO1 pin CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 437 CHAPTER 20 16-bit Reload Timer 20.6 • MB91625 Series When ch.2 is connected in cascade mode It counts the outputs from ch.1. Figure 20.6-21 shows the I/O operation when ch.2 is used in cascade mode. Figure 20.6-21 I/O operation when ch.2 is used in cascade mode TMI1 pin ch.1 TMO1 pin TMI2 pin ch.2 TMO2 pin <Note> In cascade mode, use the CSL2 to CSL0 bits of the timer control status register (TMCSR0 to TMCSR2) to set the timer mode as shown below. • Lower number channel Select interval timer mode or external clock (CSL2 to CSL0 = other than 110) • Higher number channel Set cascade mode (CSL2 to CSL0 = 110) ■ Underflow cycle This section explains the calculation of the underflow cycles of ch.1 and ch.2. • When ch.1 is connected in cascade mode T × (TMRLRA0 value + 1) × (TMRLRA1 value + 1) T: Cycle of the count clock for ch.0 TMRLRA0: 16-bit timer reload register A0 (TMRLRA0) TMRLRA1: 16-bit timer reload register A1 (TMRLRA1) • When ch.2 is connected in cascade mode T × (TMRLRA1 value + 1) × (TMRLRA2 value + 1) T: Cycle of the count clock for ch.1 TMRLRA1: 16-bit timer reload register A1 (TMRLRA1) TMRLRA2: 16-bit timer reload register A2 (TMRLRA2) 438 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 20 16-bit Reload Timer 20.7 MB91625 Series 20.7 Notes on Use Note the following points on using the 16-bit reload timer. ■ Notes on interrupts If an underflow interrupt request flag is cleared at the same time that it is set to "1", the clearing of the underflow interrupt request flag is ignored and the underflow interrupt request flag remains "1". ■ Operations for simultaneous activations If more than one of the events used to determine the operating state of the 16-bit reload timer occur simultaneously, the priority order of these events is shown below. 1. Register reading 2. Trigger input 3. Underflow 4. Clock count input CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 439 CHAPTER 20 16-bit Reload Timer 20.7 440 FUJITSU MICROELECTRONICS LIMITED MB91625 Series CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function This chapter explains the I/O select function of the base timer. 21.1 21.2 21.3 21.4 21.5 CM71-10151-2E Overview Configuration Pins Registers I/O Mode FUJITSU MICROELECTRONICS LIMITED 441 CHAPTER 21 Base Timer I/O Select Function 21.1 MB91625 Series 21.1 Overview The I/O select function of the base timer determines the I/O method of the signals (external clock/ external activation trigger/wave form) to/from the base timer by setting the I/O mode. In addition, the base timer can be used separately by channel as either of the following timers by switching the timer function. • 16-bit PWM timer • 16-bit PPG timer • 16/32-bit reload timer • 16/32-bit PWC timer Be sure to use the base timer after reading both this chapter and the chapter on the timer function to be used. ■ Overview The I/O mode can be selected from among the 9 types of modes for each 2 channels. • I/O mode 0: 16-bit timer standard mode This mode operates the base timer individually, one channel at a time. • I/O mode 1: Timer full mode In this mode, signals of the even-numbered channel of the base timer are allocated to the external pins separately to operate the timer. • I/O mode 2: External trigger shared mode In this mode, the external activation trigger can be input to the 2 channels of base timers at the same time. This mode enables activating 2 channels of base timers at the same time. • I/O mode 3: Other channel trigger shared mode In this mode, the external signal from other channels is input as an external activation trigger to activate the timer. This mode cannot be set for ch.0 and ch.1. • I/O mode 4: Timer activation/stop mode This mode controls activation/stop of the odd-numbered channel by using the even-numbered channel. The odd-numbered channel is activated at the rising edge of the output signal from the evennumbered channel and stops at the falling edge. • I/O mode 5: Same time software activation mode This mode activates multiple channels at the same time using the software. • I/O mode 6: Software activation timer activation/stop mode This mode controls activation/stop of the odd-numbered channel by using the even-numbered channel. The even-numbered channel is activated through software. The odd-numbered channel is activated at the rising edge of the output signal from the even-numbered channel and stops at the falling edge. • I/O mode 7: Timer activation mode This mode controls activation of the odd-numbered channel by using the even-numbered channel. The odd-numbered channel is activated at the rising edge of the output signal from the even-numbered channel. • I/O mode 8: Other channel trigger shared timer activation/stop mode In this mode, the external signal from other channels is input as an external activation trigger to activate the timer. This mode cannot be set for ch.0 and ch.1. 442 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.2 MB91625 Series 21.2 Configuration The base timer I/O select function consists of the following blocks: ■ Block diagram of the base timer I/O select function Figure 21.2-1 is a block diagram of the base timer I/O select function. Figure 21.2-1 Block diagram of base timer I/O select function Register block TIOB15 Peripheral bus Base Timer ch.15 TIOA15 TIOB3 Base Timer ch.3 I/O selection block TIOA3 TIOB2 Base Timer ch.2 TIOA2 TIOB1 Base Timer ch.1 Base Timer ch.0 TIOA1 TIOB0 TIOA0 • I/O selection block This circuit selects the I/O mode of the base timer for each channel. • Base timer (ch.0 to ch.15) ch.0 to ch.15 of the base timer. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 443 CHAPTER 21 Base Timer I/O Select Function 21.3 MB91625 Series 21.3 Pins This section explains the pins for setting the I/O mode using the base timer I/O select function. ■ Overview The base timer has 2 types of external pins and 5 types of internal signals for each channel. By connecting the external pins and internal signals, signals that correspond to the connection destination (external clock (ECK signal)/external activation trigger (TGIN signal)/wave form (TIN signal)) are input to or output from the base timer. The external pins and internal signals are connected by setting the I/O mode of the base timer. The pins that are used and the signals to be input/output vary depending on the I/O mode. ● External pin • TIOA0 to TIOA15 pins These pins are used to output the wave form of the base timer (TOUT signal) or input the external activation trigger (TGIN signal). These pins are multiplexed pins. To use them as TIOA0 to TIOA15 pins of the base timer, see "2.4 Setting Method for Pins". • TIOB0 to TIOB15 pins These pins are used to input the external activation trigger (TGIN signal)/external clock (ECK signal)/ wave form of another channel (TIN signal). These pins are multiplexed pins. To use them as TIOB0 to TIOB15 pins of the base timer, see "2.4 Setting Method for Pins". ● Internal signal By connecting these pins to the above mentioned external pins or by inputting the output signal from another channel, signals is input to or output from the base timer. • TOUT signal Output wave form of the base timer. (It is not used in the 16/32-bit PWC timer.) • ECK signal External clock of the base timer. (It is not used in the 16/32-bit PWC timer.) This signal is input when the external clock is selected for the count clock. • TGIN signal External activation trigger of the base timer. (It is not used in the 16/32-bit PWC timer.) When the effective edge of the external activation trigger is selected, the edge of this signal is detected to activate the base timer. • TIN signal The wave form to be measured. (It is used only in the 16/32-bit PWC timer.) • DTRG signal The base timer stops operation at the falling edge of this signal. • COUT signal Output signal to other channels. • CIN signal Signal that is input from other channels. 444 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.3 MB91625 Series ● Connection of the external pins and internal signals The external pins and internal signals are connected by setting the I/O mode of the base timer. Table 21.3-1 outlines the relationship between the I/O mode and pin connections. Table 21.3-1 Relationship between the I/O mode and pin connections I/O Mode TIOAn (Even-numbered Channel) Connection Destination I/O TIOBn (Even-numbered Channel) Connection Destination I/O TIOAn+1 (Odd-numbered Channel) Connection Destination I/O TIOBn+1 (Odd-numbered Channel) Connection Destination I/O 0 ch.n’s TOUT Output ch.n’s ECK/ TGIN/TIN Input ch.n+1’s TOUT Output ch.n+1’s ECK/TGIN/ TIN Input 1 ch.n’s TOUT Output ch.n’s ECK Input ch.n’s TGIN Input ch.n’s TIN Input 2 ch.n’s TOUT Output ch.n/ch.n+1’s ECK/TGIN/ TIN*1 Input ch.n+1’s TOUT Output Not used 3 ch.n’s TOUT Output Not used ch.n+1’s TOUT Output 4 ch.n’s TOUT Output ch.n’s ECK/ TGIN/TIN ch.n+1’s TOUT Output 5 ch.n’s TOUT Output Not used ch.n+1’s TOUT Output 6 ch.n’s TOUT Output ch.n+1’s TOUT Output 7 ch.n’s TOUT Output ch.n’s ECK/ TGIN/TIN ch.n+1’s TOUT Output 8 ch.n’s TOUT Output Not used ch.n+1’s TOUT Output ch.n: Input Input even-numbered channel ch.n+1: odd-numbered channel n = 0, 2, 4, 6, 8, 10, 12, 14 *1: Synchronize with the peripheral clock (PCLK) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 445 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series 21.4 Registers This section explains the configuration and functions of registers used in the base timer I/O select function. ■ List of registers of the base timer I/O select function Table 21.4-1 lists registers of the base timer I/O select function. Table 21.4-1 Registers of the base timer I/O select function Channel 446 Abbreviated Register Name Register Name Reference Common BTSSSR Base timer same time soft start register 21.4.5 Common to 0 to 3 BTSEL0123 Base timer io select register for ch.0/1/2/3 21.4.1 Common to 4 to 7 BTSEL4567 Base timer io select register for ch.4/5/6/7 21.4.2 Common to 8 to 11 BTSEL89AB Base timer io select register for ch.8/9/A/B 21.4.3 Common to 12 to 15 BTSELCDEF Base timer io select register for ch.C/D/E/F 21.4.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series 21.4.1 Base Timer IO Select Register for Ch.0/1/2/3 (BTSEL0123) This register sets the I/O mode of ch.0 to ch.3 of the base timer. Figure 21.4-1 shows the bit configuration of the base timer io select register for ch.0/1/2/3 (BTSEL0123). Figure 21.4-1 Bit configuration of base timer io select register for ch.0/1/2/3 (BTSEL0123) bit 7 6 5 4 3 2 1 0 SEL23_3 SEL23_2 SEL23_1 SEL23_0 SEL01_3 SEL01_2 SEL01_1 SEL01_0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> Change this register after setting the base timer to reset mode in FMD2 to FMD0 bits (FMD2 to FMD0 = 000) of the base timer x timer control register (BTxTMCR). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 447 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit7 to bit4]: SEL23_3 to SEL23_0 (I/O select bit for ch.2/ch.3) These bits set the I/O mode for ch.2 and ch.3 of the base timer. SEL23_3 SEL23_2 SEL23_1 SEL23_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/ stop mode) <Note> Setting the values other than above is prohibited. 448 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit3 to bit0]: SEL01_3 to SEL01_0 (I/O select bit for ch.0/ch.1) These bits set the I/O mode of ch.0 and ch.1 of the base timer. ch.0 and ch.1 are the lowest channels of the base timer so that modes that use signals from the lower side channels cannot be used in these channels. Therefore, the setting of the following modes is prohibited. • I/O mode 3 (other channel trigger shared mode) • I/O mode 8 (other channel trigger shared timer activation/stop mode) SEL01_3 SEL01_2 SEL01_1 SEL01_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 Setting prohibited 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 Setting prohibited <Note> Setting the values other than above is prohibited. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 449 CHAPTER 21 Base Timer I/O Select Function 21.4 21.4.2 MB91625 Series Base Timer IO Select Register for Ch.4/5/6/7 (BTSEL4567) This register sets the I/O mode of ch.4 to ch.7 of the base timer. Figure 21.4-2 shows the bit configuration of the base timer io select register for ch.4/5/6/7 (BTSEL4567). Figure 21.4-2 Bit configuration of base timer io select register for ch.4/5/6/7 (BTSEL4567) bit 7 6 5 4 3 2 1 0 SEL67_3 SEL67_2 SEL67_1 SEL67_0 SEL45_3 SEL45_2 SEL45_1 SEL45_0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> Change this register after setting the base timer to reset mode in FMD2 to FMD0 bits (FMD2 to FMD0 = 000) of the base timer x timer control register (BTxTMCR). 450 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit7 to bit4]: SEL67_3 to SEL67_0 (I/O select bit for ch.6/ch.7) These bits set the I/O mode of ch.6 and ch.7 of the base timer. SEL67_3 SEL67_2 SEL67_1 SEL67_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/ stop mode) <Note> Setting the values other than above is prohibited. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 451 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit3 to bit0]: SEL45_3 to SEL45_0 (I/O select bit for ch.4/ch.5) These bits set the I/O mode of ch.4 and ch.5 of the base timer. SEL45_3 SEL45_2 SEL45_1 SEL45_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/ stop mode) <Note> Setting the values other than above is prohibited. 452 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series 21.4.3 Base Timer IO Select Register for Ch.8/9/A/B (BTSEL89AB) This register sets the I/O mode of ch.8 to ch.11 of the base timer. Figure 21.4-3 shows the bit configuration of the base timer io select register for ch.8/9/A/B (BTSEL89AB). Figure 21.4-3 Bit configuration of base timer io select register for ch.8/9/A/B (BTSEL89AB) bit 7 6 5 4 3 2 1 0 SELAB_3 SELAB_2 SELAB_1 SELAB_0 SEL89_3 SEL89_2 SEL89_1 SEL89_0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> Change this register after setting the base timer to reset mode in FMD2 to FMD0 bits (FMD2 to FMD0 = 000) of the base timer x timer control register (BTxTMCR). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 453 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit7 to bit4]: SELAB_3 to SELAB_0 (I/O select bit for ch.10/ch.11) These bits set the I/O mode of ch.10 and ch.11 of the base timer. SELAB_3 SELAB_2 SELAB_1 SELAB_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/stop mode) <Note> Setting the values other than above is prohibited. 454 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit3 to bit0]: SEL89_3 to SEL89_0 (I/O select bit for ch.8/ch.9) These bits set the I/O mode of ch.8 and ch.9 of the base timer. SEL89_3 SEL89_2 SEL89_1 SEL89_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/ stop mode) <Note> Setting the values other than above is prohibited. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 455 CHAPTER 21 Base Timer I/O Select Function 21.4 21.4.4 MB91625 Series Base Timer IO Select Register for Ch.C/D/E/F (BTSELCDEF) This register sets the I/O mode of ch.12 to ch.15 of the base timer. Figure 21.4-4 shows the bit configuration of the base timer io select register for ch.C/D/E/F (BTSELCDEF). Figure 21.4-4 Bit configuration of base timer io select register for ch.C/D/E/F (BTSELCDEF) bit 7 6 5 4 3 2 1 0 SELEF_3 SELEF_2 SELEF_1 SELEF_0 SELCD_3 SELCD_2 SELCD_1 SELCD_0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> Change this register after setting the base timer to reset mode in FMD2 to FMD0 bits (FMD2 to FMD0 = 000) of the base timer x timer control register (BTxTMCR). 456 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit7 to bit4]: SELEF_3 to SELEF_0 (I/O select bit for ch.14/ch.15) These bits set the I/O mode of ch.14 and ch.15 of the base timer. SELEF_3 SELEF_2 SELEF_1 SELEF_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/stop mode) <Note> Setting the values other than above is prohibited. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 457 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit3 to bit0]: SELCD_3 to SELCD_0 (I/O select bit for ch.12/ch.13) These bits set the I/O mode of ch.12 and ch.13 of the base timer. SELCD_3 SELCD_2 SELCD_1 SELCD_0 Explanation 0 0 0 0 I/O mode 0 (16-bit timer standard mode) 0 0 0 1 I/O mode 1 (timer full mode) 0 0 1 0 I/O mode 2 (external trigger shared mode) 0 0 1 1 I/O mode 3 (other channel trigger shared mode) 0 1 0 0 I/O mode 4 (timer activation/stop mode) 0 1 0 1 I/O mode 5 (same time software activation mode) 0 1 1 0 I/O mode 6 (software activation timer activation/stop mode) 0 1 1 1 I/O mode 7 (timer activation mode) 1 0 0 0 I/O mode 8 (other channel trigger shared timer activation/stop mode) <Note> Setting the values other than above is prohibited. 458 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series 21.4.5 Base Timer Same Time Soft Start Register (BTSSSR) This register simultaneously activates the base timers using the software. Up to 16 channels corresponding to the bits in which "1" is written can be simultaneously activated. Figure 21.4-5 shows the bit configuration of the base timer same time soft start register (BTSSSR). Figure 21.4-5 Bit configuration of base timer same time soft start register (BTSSSR) bit 15 14 13 12 11 10 9 8 SSSR15 SSSR14 SSSR13 SSSR12 SSSR11 SSSR10 SSSR9 SSSR8 Attribute W W W W W W W W Initial value X X X X X X X X 7 6 5 4 3 2 1 0 SSSR7 SSSR6 SSSR5 SSSR4 SSSR3 SSSR2 SSSR1 SSSR0 Attribute W W W W W W W W Initial value X X X X X X X X bit W: Write only X: Undefined <Notes> • Do not write to this register when the modes other than the following are set. - I/O mode 5 (same time software activation mode) - I/O mode 6 (software activation timer activation/stop mode) (only for even-numbered channels) • For channels that are activated using this register, set the trigger input edge to the rising edge in the EGS1 and EGS0 bits (EGS1, EGS 0 = 01) of the base timer x timer control register (BTxTMCR). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 459 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit15]: SSSR15 (Same time software start bit for ch.15) This bit activates the ch.15 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.15 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SELEF_3 to SELEF_0 bits of the base timer io select register for ch.C/D/E/F (BTSELCDEF) (SELEF_3 to SELEF_0 = 0101) [bit14]: SSSR14 (Same time software start bit for ch.14) This bit activates the ch.14 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.14 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SELEF_3 to SELEF_0 bits of the base timer io select register for ch.C/D/E/F (BTSELCDEF) - "5" (Same time software activation mode) (SELEF_3 to SELEF_0 = 0101) - "6" (Software activation timer activation/stop mode) (SELEF_3 to SELEF_0 = 0110) [bit13]: SSSR13 (Same time software start bit for ch.13) This bit activates the ch.13 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.13 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SELCD_3 to SELCD_0 bits of the base timer io select register for ch.C/D/E/F (BTSELCDEF) (SELCD_3 to SELCD_0 = 0101) [bit12]: SSSR12 (Same time software start bit for ch.12) This bit activates the ch.12 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.12 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SELCD_3 to SELCD_0 bits of the base timer io select register for ch.C/D/E/F (BTSELCDEF) - "5" (Same time software activation mode) (SELCD_3 to SELCD_0 = 0101) - "6" (Software activation timer activation/stop mode) (SELCD_3 to SELCD_0 = 0110) 460 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit11]: SSSR11 (Same time software start bit for ch.11) This bit activates the ch.11 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.11 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SELAB_3 to SELAB_0 bits of the base timer io select register for ch.8/9/A/B (BTSEL89AB) (SELAB_3 to SELAB_0 = 0101) [bit10]: SSSR10 (Same time software start bit for ch.10) This bit activates the ch.10 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.10 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SELAB_3 to SELAB_0 bits of the base timer io select register for ch.8/9/A/B (BTSEL89AB) - "5" (Same time software activation mode) (SELAB_3 to SELAB_0 = 0101) - "6" (Software activation timer activation/stop mode) (SELAB_3 to SELAB_0 = 0110) [bit9]: SSSR9 (Same time software start bit for ch.9) This bit activates the ch.9 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.9 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SEL89_3 to SEL89_0 bits of the base timer io select register for ch.8/9/A/B (BTSEL89AB) (SEL89_3 to SEL89_0 = 0101) [bit8]: SSSR8 (Same time software start bit for ch.8) This bit activates the ch.8 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.8 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SEL89_3 to SEL89_0 bits of the base timer io select register for ch.8/9/A/B (BTSEL89AB) - "5" (Same time software activation mode) (SEL89_3 to SEL89_0 = 0101) - "6" (Software activation timer activation/stop mode) (SEL89_3 to SEL89_0 = 0110) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 461 CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit7]: SSSR7 (Same time software start bit for ch.7) This bit activates the ch.7 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.7 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SEL67_3 to SEL67_0 bits of the base timer io select register for ch.4/5/6/7 (BTSEL4567) (SEL67_3 to SEL67_0 = 0101) [bit6]: SSSR6 (Same time software start bit for ch.6) This bit activates the ch.6 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.6 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SEL67_3 to SEL67_0 bits of the base timer io select register for ch.4/5/6/7 (BTSEL4567) - "5" (Same time software activation mode) (SEL67_3 to SEL67_0 = 0101) - "6" (Software activation timer activation/stop mode) (SEL67_3 to SEL67_0 = 0110) [bit5]: SSSR5 (Same time software start bit for ch.5) This bit activates the ch.5 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.5 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SEL45_3 to SEL45_0 bits of the base timer io select register for ch.4/5/6/7 (BTSEL4567) (SEL45_3 to SEL45_0 = 0101) [bit4]: SSSR4 (Same time software start bit for ch.4) This bit activates the ch.4 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.4 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SEL45_3 to SEL45_0 bits of the base timer io select register for ch.4/5/6/7 (BTSEL4567) - "5" (Same time software activation mode) (SEL45_3 to SEL45_0 = 0101) - "6" (Software activation timer activation/stop mode) (SEL45_3 to SEL45_0 = 0110) 462 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.4 MB91625 Series [bit3]: SSSR3 (Same time software start bit for ch.3) This bit activates the ch.3 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.3 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SEL23_3 to SEL23_0 bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) (SEL23_3 to SEL23_0 = 0101) [bit2]: SSSR2 (Same time software start bit for ch.2) This bit activates the ch.2 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.2 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SEL23_3 to SEL23_0 bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) - "5" (Same time software activation mode) (SEL23_3 to SEL23_0 = 0101) - "6" (Software activation timer activation/stop mode) (SEL23_3 to SEL23_0 = 0110) [bit1]: SSSR1 (Same time software start bit for ch.1) This bit activates the ch.1 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.1 of the base timer.* * Only when the I/O mode is set to "5" (same time software activation mode) in SEL01_3 to SEL01_0 bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) (SEL01_3 to SEL01_0 = 0101) [bit0]: SSSR0 (Same time software start bit for ch.0) This bit activates the ch.0 of the base timer. Written Value Explanation 0 Ignored 1 Activates the ch.0 of the base timer.* * Only when the I/O mode is set to either of the following modes in the SEL01_3 to SEL01_0 bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) - "5" (Same time software activation mode) SEL01_3 to SEL01_0) - "6" (Software activation timer activation/stop mode) (SEL01_3 to SEL01_0) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 463 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series 21.5 I/O Mode Operations of the external pins and activation/stop timing of the base timer vary depending on the I/O mode set in the base timer io select register (BTSEL0123 to BTSELCDEF). 21.5.1 I/O Mode 0 (16-bit Timer Standard Mode) In this mode, each channel of the base timer is used separately. Table 21.5-1 lists the external pins used when this mode is set. Table 21.5-1 External Pins Used Even-numbered Channel Odd-numbered Channel Input pin 1 1 Output pin 1 1 Table 21.5-2 lists the connection destinations of the external pins used and I/O signals. Table 21.5-2 Connection Destinations of the External Pins and I/O Signals External Pin I/O Connection Destination (Internal Signal) I/O Signal TIOA0 to TIOA15 Output TOUT Output wave form the base timer TIOB0 to TIOB15 Input ECK/TGIN/TIN* Use the signals that have been input as one of the following: - External clock (ECK signal) - External activation trigger (TGIN signal) - Measured wave form (TIN signal) * Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register (BTxTMCR) setting. 464 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Figure 21.5-1 is a block diagram of I/O mode 0 (16-bit timer standard mode), taking ch.0 as an example. Figure 21.5-1 Block Diagram of I/O Mode 0 (16-bit Timer Standard Mode) Base Timer ch.n+1 Base Timer ch.n ECK TGIN TIN TOUT TIOBn+1 ECK TGIN TIN TOUT TIOBn TIOAn+1 TIOAn Table 21.5-3 lists the connections for I/O mode 0. Table 21.5-3 Connections for I/O Mode 0 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin Input signal from the TIOBn pin Input to ch.n as TIN/TGIN/ECK TOUT signal of ch.n+1 Output from the TIOAn+1 pin Input signal from the TIOBn+1 pin Input to ch.n+1 as TIN/TGIN/ECK n=0, 2, 4, 6, 8, 10, 12, 14 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 465 CHAPTER 21 Base Timer I/O Select Function 21.5 21.5.2 MB91625 Series I/O Mode 1 (Timer Full Mode) In this mode, signals from the even-numbered channels are allocated to all the external pins separately to operate the timer. Table 21.5-4 lists the external pins used when this mode is set. Table 21.5-4 External Pins Used Even-numbered Channel Input pin 3 Output pin 1 Table 21.5-5 lists the connection destinations of the external pins used and I/O signals. Table 21.5-5 Connection Destinations of the External Pins and I/O Signals External Pin I/O Connection Destination (Internal Signal) I/O Signal TIOAn Output TOUT of an evennumbered channel Output the wave form of an even-numbered channel TIOBn Input ECK of the evennumbered channel Input the external clock (ECK signal) to the evennumbered channel TIOAn+1 Input TGIN of the evennumbered channel Input the external activation trigger (TGIN signal) to the even-numbered channel TIOBn+1 Input TIN of the evennumbered channel Input the measured wave form (TIN signal) in the even-numbered channel n=0, 2, 4, 6, 8, 10, 12, 14 Figure 21.5-2 is a block diagram of I/O mode 1 (timer full mode). Figure 21.5-2 Example of Block Diagram of I/O Mode 1 (Timer Full Mode) TIOBn+1 Base Timer ch.n+1 TIOAn+1 (During 32-bit mode operation) Base Timer ch.n 466 ECK TGIN TIN TOUT FUJITSU MICROELECTRONICS LIMITED TIOBn TIOAn CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-6 lists the connections for I/O mode 1. Table 21.5-6 Connections for I/O Mode 1 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin Input signal from the TIOBn pin Input to ch.n as an ECK signal Input signal from the TIOAn+1 pin Input to ch.n as a TGIN signal Input signal from the TIOBn+1 pin Input to ch.n as a TIN signal n=0, 2, 4, 6, 8, 10, 12, 14 <Note> If this mode is set, set the TIOAn pins (TIOA1, TIOA3, TIOA5, ... TIOA15) corresponding to the odd-numbered channel to the port input mode in the port function register (PFR). For details of the setting of pins, see "2.4 Setting Method for Pins". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 467 CHAPTER 21 Base Timer I/O Select Function 21.5 21.5.3 MB91625 Series I/O Mode 2 (External Trigger Shared Mode) In this mode, input signals to the base timer (ECK/TGIN/TIN) are shared by 2 channels. Table 21.5-7 lists the external pins used when this mode is set. Table 21.5-7 External Pins Used Even-numbered Channel Input pin 1 (shared by 2 channels) Output pin 1 Odd-numbered Channel 1 Table 21.5-8 lists the connection destinations of the external pins used and I/O signals. Table 21.5-8 Connection Destinations of the External Pins and I/O Signals External pin I/O Connection Destination (Internal Signal) I/O Signal TIOAn Output TOUT of an evennumbered channel Output the wave form of an even-numbered channel TIOAn+1 Output TOUT of an oddnumbered channel Output the wave form of an odd-numbered channel TIOBn Input ECK/TGIN/TIN of the even/odd-numbered channel* Input to both of the even/odd-numbered channels (synchronized with the peripheral clock (PCLK)) and use it as one of the following: - External clock (ECK signal) - External activation trigger (TGIN signal) - Measured wave form (TIN signal) TIOBn+1 - - Not used n=0, 2, 4, 6, 8, 10, 12, 14 * Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register (BTxTMCR) setting. Figure 21.5-3 is a block diagram of I/O mode 2 (external trigger shared mode). Figure 21.5-3 Block Diagram of I/O Mode 2 (External Trigger Shared Mode) Base Timer ch.n+1 Base Timer ch.n 468 ECK TGIN TIN TOUT COUT ECK TGIN TIN TOUT FUJITSU MICROELECTRONICS LIMITED TIOBn+1 TIOAn+1 TIOBn TIOAn CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-9 lists the connections for I/O mode 2. Table 21.5-9 Connections for I/O Mode 2 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin Input signal from the TIOBn pin - Input to ch.n and ch.n+1 as TIN/TGIN/ECK signals - Output to another channel as the COUT signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin Remarks Synchronization with the peripheral clock (PCLK) n=0, 2, 4, 6, 8, 10, 12, 14 <Note> If the upper 2 channels (n + 2, n + 3) of those that have been set to this mode are set to I/O mode 3 (other channel trigger shared mode), the input signals (ECK/TGIN/TIN) can be input to 4 channels at the same time. (Example: If this mode is set for ch.0 and ch.1 and I/O mode 3 is set for ch.2 and ch.3, the input signals (ECK/TGIN/TIN) can be input to all 4 channels of ch.0 to ch.3 at the same time.) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 469 CHAPTER 21 Base Timer I/O Select Function 21.5 21.5.4 MB91625 Series I/O Mode 3 (Other Channel Trigger Shared Mode) In this mode, the COUT signal of the channel that is lower by 2 channels is input as a CIN signal to be used as the ECK/TGIN/TIN signal. Table 21.5-10 lists the external pins used when this mode is set. Table 21.5-10 External Pins Used Even-numbered Channel Input pin Not used Output pin 1 Odd-numbered Channel 1 Table 21.5-11 lists the connection destinations of the external pins used and I/O signals. Table 21.5-11 Connection Destinations of the External Pins and I/O Signals External pin I/O Connection Destination (Internal Signal) I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an evennumbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an oddnumbered channel TIOBn, TIOBn+1 - - Not used n=2, 4, 6, 8, 10, 12, 14 Figure 21.5-4 is a block diagram of I/O mode 3 (other channel trigger shared mode). Figure 21.5-4 Block Diagram of I/O Mode 3 (Other Channel Trigger Shared Mode) Base Timer ch.n+1 Base Timer ch.n ECK TGIN TIN TOUT COUT TIOBn+1 TIOAn+1 ECK TGIN TIN TOUT TIOBn TIOAn CIN 470 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-12 lists the connections for I/O mode 3. Table 21.5-12 Connections for I/O Mode 3 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin CIN signal* - Input to ch.n and ch.n+1 as the TIN/TGIN/ECK signal - Output to another channel as the COUT signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin n=2, 4, 6, 8, 10, 12, 14 * Input the COUT signal of the other channel as the CIN signal. The signals of ch.n-2/n-1 that can be input to ECK, TGIN and TIN of ch.n/n+1 are as below. • The signal that synchronized TIOBn-2 input of input/output mode 2 with peripheral clock. • The trigger signal input from ch.n-4/n-3 of input/output mode 3. • TIONAn-2 output of input/output mode 4. • TIONAn-2 output of input/output mode 6. • TIONAn-2 output of input/output mode 7. • The trigger signal input from ch.n-4/n-3 of input/output mode 8. <Notes> • Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0=01) of the base timer x timer control register (BTxTMCR). • Channels that have been set to this mode use the COUT signal of the channels (n - 2, n - 1) that are lower by 2 channels, as the CIN signal input. (Example: If ch.2 and ch.3 are set to this mode, they use the COUT signal of ch.0 and ch.1.) Therefore, ch.0 and ch.1 cannot be set to this mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 471 CHAPTER 21 Base Timer I/O Select Function 21.5 21.5.5 MB91625 Series Operations in I/O Mode 4 (Timer Activation/Stop Mode) This mode enables control of activation/stop of the odd-numbered channel by using the evennumbered channel. The odd-numbered channel is activated at the rising edge of the output wave form (TOUT signal) of the even-numbered channel and stops at the falling edge. Table 21.5-13 lists the external pins used when this mode is set. Table 21.5-13 External Pins Used Even-numbered Channel Odd-numbered Channel Input pin 1 Not used Output pin 1 1 Table 21.5-14 lists the functions of pins. Table 21.5-14 Functions of Pins External Pin I/O Connection Destination (Internal Signal) I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an evennumbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an odd-numbered channel TIOBn Input ECK/TGIN/TIN of the evennumbered channel* Input to the even-numbered channel and use as one of the following. - External clock (ECK signal) - External activation trigger (TGIN signal) - Measured wave form (TIN signal) TIOBn+1 - - Not used n=0, 2, 4, 6, 8, 10, 12, 14 * Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register (BTxTMCR) setting. 472 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Figure 21.5-5 is a block diagram of I/O mode 4 (timer activation/stop mode). Figure 21.5-5 Block Diagram of I/O Mode 4 (Timer Activation/Stop Mode) COUT Base Timer ch.n+1 Base Timer ch.n DTRG ECK TGIN TIN TOUT TIOBn+1 TIOAn+1 ECK TGIN TIN TOUT TIOBn TIOAn Table 21.5-15 lists the connections for I/O mode 4. Table 21.5-15 Connections for I/O Mode 4 Connection Source Connection Destination TOUT signal of ch.n - Output from the TIOAn pin - Input to ch.n+1 as the TIN/TGIN/ECK signal and DTRG signal - Output to another channel as the COUT signal Input signal from the TIOBn pin Input to ch.n as the TIN/TGIN/ECK signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin n=0, 2, 4, 6, 8, 10, 12, 14 <Notes> • Set the trigger input edge of the odd-numbered channel to the rising edge in the EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR). • The odd-numbered channel stops operation when the falling edge is detected in the DTRG signal. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 473 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Figure 21.5-6 shows the operation when I/O mode 4 (timer activation/stop mode) is set, taking as an example the case where ch.0 and ch.1 are used as the PWM timer. Setting Value Register (ch.0) Setting Value Register (ch.1) Base timer 0 cycle setting register (BT0PCSR) 0010H Base timer 1 cycle setting register (BT1PCSR) 0002H Base timer 0 duty setting register (BT0PDUT) 0009H Base timer 1 duty setting register (BT1PDUT) 0001H Base timer 0 timer control register (BT0TMCR) 0013H Base timer 1 timer control register (BT1TMCR) 0112H Figure 21.5-6 Example of Operations of I/O Mode 4 (Timer Activation/Stop Mode) Peripheral clock (PCLK) 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 TIOA0 6 TIOA1 ch.1 operation period ch.1 activated 474 FUJITSU MICROELECTRONICS LIMITED 7 8 ch.1 maintains the timer value at the time of stop. ch.1 stops CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series 21.5.6 Operations in I/O Mode 5 (Same Time Software Activation Mode) This mode enables activating multiple channels at the same time by using the base timer same time soft start register (BTSSSR). All channels corresponding to the bits in which "1" is written in the base timer same time soft start register (BTSSSR) are activated at the same time. Table 21.5-16 lists the external pins used when this mode is set. Table 21.5-16 External Pins Used Even-numbered Channel Input pin Not used Output pin 1 Odd-numbered Channel 1 Table 21.5-17 lists the connection destinations of the external pins used and I/O signals. Table 21.5-17 Connection Destinations of the External Pins and I/O Signals External Pin Connection Destination (Internal Signal) I/O I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an even-numbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an oddnumbered channel TIOBn, TIOBn+1 - - Not used n=0, 2, 4, 6, 8, 10, 12, 14 Figure 21.5-7 is a block diagram of I/O mode 5 (same time software activation mode). Figure 21.5-7 Block Diagram of I/O Mode 5 (Same Time Software Activation Mode) Software activation signal (SSSRn+1 bit) Base Timer ch.n+1 Software activation signal (SSSRn bit) Base Timer ch.n CM71-10151-2E ECK TGIN TIN TOUT TIOBn+1 ECK TGIN TIN TOUT TIOBn FUJITSU MICROELECTRONICS LIMITED TIOAn+1 TIOAn 475 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-18 lists the connections for I/O mode 5. Table 21.5-18 Connections for I/O Mode 5 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin Software activation signal (Writing "1" in SSSRn bit of BTSSSR) Input to ch.n as the TIN/TGIN/ECK signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin Software activation signal (Writing "1" in SSSRn+1 bit of BTSSSR) Input to ch.n+1 as the TIN/TGIN/ECK signal n=0, 2, 4, 6, 8, 10, 12, 14 BTSSSR Base timer same time soft start register (BTSSSR) If "1" is written in the base timer same time soft start register (BTSSSR), the rising edge is input (ECK/ TGIN/TIN signal) in the channels that correspond to the written bits. <Note> Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR). 476 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series 21.5.7 Operations in I/O Mode 6 (Software Activation Timer Activation/Stop Mode) This mode enables control of activation/stop of the odd-numbered channel by using the evennumbered channel. The even-numbered channel is activated by writing "1" in the base timer same time soft start register (BTSSSR). The odd-numbered channel is activated when the rising edge is detected in the output wave form (TOUT signal) of the even-numbered channel and stops when the falling edge is detected. Table 21.5-19 lists the external pins used when this mode is set. Table 21.5-19 External Pins Used Even-numbered Channel Input pin Not used Output pin 1 Odd-numbered Channel 1 Table 21.5-20 lists the connection destinations of the external pins used and I/O signals. Table 21.5-20 Connection Destinations of the External Pins and I/O Signals Pin Connection Destination (Internal Signal) I/O I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an evennumbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an oddnumbered channel TIOBn, TIOBn+1 - - Not used n=0, 2, 4, 6, 8, 10, 12, 14 Figure 21.5-8 is a block diagram of I/O mode 6 (software activation timer activation/stop mode). Figure 21.5-8 Block Diagram of I/O Mode 6 (Software Activation Timer Activation/Stop Mode) COUT Base Timer ch.n+1 Software activation signal (SSSRn bit) Base Timer ch.n CM71-10151-2E DTRG ECK TGIN TIN TOUT ECK TGIN TIN TOUT FUJITSU MICROELECTRONICS LIMITED TIOBn+1 TIOAn+1 TIOBn TIOAn 477 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-21 lists the connections for I/O mode 6. Table 21.5-21 Connections for I/O Mode 6 Connection Source Connection Destination TOUT signal of ch.n - Output from the TIOAn pin - Input to ch.n+1 as the TIN/TGIN/ECK/DTRG signal - Output to another channel as the COUT signal Software activation signal (Writing "1" in SSSRn bit of BTSSSR) Input to ch.n as the TIN/TGIN/ECK signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin n=0, 2, 4, 6, 8, 10, 12, 14 BTSSSR Base timer same time soft start register (BTSSSR) If "1" is written in the bits of the base timer same time soft start register (BTSSSR) that correspond to the even-numbered channels to be activated, the rising edge is input (ECK, TGIN, TIN signal) in the corresponding channels. Start-up and stop timing of ch.n are same as input/output mode4. <Notes> 478 • Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR). • The odd-numbered channel stops operation when the falling edge is detected in the DTRG signal. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series 21.5.8 Operations in I/O Mode 7 (Timer Activation Mode) In this mode, the output wave form (TOUT signal) of the even-numbered channel is used as input signals (ECK/TGIN/TIN signal) of the odd-numbered channel. Table 21.5-22 lists the external pins used when this mode is set. Table 21.5-22 External Pins Used Even-numbered Channel Odd-numbered Channel Input pin 1 Not used Output pin 1 1 Table 21.5-23 lists the connection destinations of the external pins used and I/O signals. Table 21.5-23 Connection Destinations of the External Pins and I/O Signals External Pin I/O Connection Destination (Internal Signal) I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an evennumbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an odd-numbered channel TIOBn Input ECK/TGIN/TIN of the evennumbered channel* Input to the even-numbered channel and use as one of the following. - External clock (ECK signal) - External activation trigger (TGIN signal) - Measured wave form (TIN signal) TIOBn+1 - - Not used n=0, 2, 4, 6, 8, 10, 12, 14 * Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register (BTxTMCR) setting. Figure 21.5-9 is a block diagram of I/O mode 7 (timer activation mode). Figure 21.5-9 Block Diagram of I/O Mode 7 (Timer Activation Mode) COUT Base Timer ch.n+1 Base Timer ch.n CM71-10151-2E ECK TGIN TIN TOUT TIOBn+1 ECK TGIN TIN TOUT TIOBn FUJITSU MICROELECTRONICS LIMITED TIOAn+1 TIOAn 479 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-24 lists the connection for I/O mode 7. Table 21.5-24 Connection for I/O Mode 7 Connection Source Connection Destination TOUT signal of ch.n - Output from the TIOAn pin - Input to ch.n+1 as the TIN/TGIN/ECK signal - Output to another channel as the COUT signal Input signal from the TIOBn pin Input to ch.n as the TIN/TGIN/ECK signal TOUT signal of ch.n+1 Output from the TIOAn+1 pin n=0, 2, 4, 6, 8, 10, 12, 14 Start-up timing of ch.n is same as input/output mode4. 480 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series 21.5.9 Operations in I/O Mode 8 (Other Channel Trigger Shared Timer Activation/Stop Mode) In this mode, the COUT signal of the channel that is lower by 2 channels is input as the CIN signal to be used as the external activation trigger (TGIN signal). Table 21.5-25 lists the external pins used when this mode is set. Table 21.5-25 External Pins Used Even-numbered Channel Input pin Not used Output pin 1 Odd-numbered Channel 1 Table 21.5-26 lists the connection destinations of the external pins used and I/O signals. Table 21.5-26 Connection Destinations of the External Pins and I/O Signals External Pin Connection Destination (Internal Signal) I/O I/O Signal TIOAn Output TOUT of an even-numbered channel Output the wave form of an evennumbered channel TIOAn+1 Output TOUT of an odd-numbered channel Output the wave form of an oddnumbered channel TIOBn, TIOBn+1 - - Not used n=2, 4, 6, 8, 10, 12, 14 Figure 21.5-10 is a block diagram of I/O mode 8 (other channel trigger shared timer activation/stop mode). Figure 21.5-10 Block Diagram of I/O Mode 8 (Other Channel Trigger Shared Timer Activation/Stop Mode) COUT Base Timer ch.n+1 Base Timer ch.n DTRG ECK TGIN TIN TOUT TIOBn+1 TIOAn+1 DTRG ECK TGIN TIN TOUT TIOBn TIOAn CIN CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 481 CHAPTER 21 Base Timer I/O Select Function 21.5 MB91625 Series Table 21.5-27 lists the connections for I/O mode 8. Table 21.5-27 Connections for I/O Mode 8 Connection Source Connection Destination TOUT signal of ch.n Output from the TIOAn pin CIN signal* - Input to ch.n and ch.n+1 as the TIN/TGIN/ECK signal and DTRG signal - Output to another channel as the COUT signal n=2, 4, 6, 8, 10, 12, 14 * Input the COUT signal of the other channel as the CIN signal. The signals of ch.n-2/n-1 that can be input to ECK, TGIN and TIN of ch.n/n+1 are as below. • The signal that synchronized TIOBn-2 input of input/output mode 2 with peripheral clock. • The trigger signal input from ch.n-4/n-3 of input/output mode 3. • TIONAn-2 output of input/output mode 4. • TIONAn-2 output of input/output mode 6. • TIONAn-2 output of input/output mode 7. • The trigger signal input from ch.n-4/n-3 of input/output mode 8. <Notes> • Channels that have been set to this mode use the COUT signal of the channels (n - 2, n - 1) that are lower by 2 channels, as the CIN signal input. (Example: If ch.2 and ch.3 are set to this mode, they use the COUT signal of ch.0 and ch.1.) Therefore, ch.0 and ch.1 cannot be set to this mode. • For the channels that are set to this mode, set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR). However, the above setting does not apply to the case where the timer function is set to 16/32bit PWC timer in the FMD2 to FMD0 bits (FMD2 to FMD0 = 100) of the base timer x timer control register (BTxTMCR). • 482 The odd-numbered channel stops operation when the falling edge is detected in the DTRG signal. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer This chapter provides an overview of the base timer, summarizes its register configuration and functions, and describes its operations. 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 CM71-10151-2E Overview of the Base Timer Block Diagrams of the Base Timer Base Timer's Registers Operations of the Base Timer 32-bit Mode Operations Notes of Using the Base Timer Base Timer Interrupts Base Timer Description by Function Mode FUJITSU MICROELECTRONICS LIMITED 483 CHAPTER 22 Base Timer 22.1 MB91625 Series 22.1 Overview of the Base Timer The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section outlines the base timer in each function mode available. This series is equipped with 16 channels. ■ Function Mode Bit Settings and Timer Function Modes Assigned FMD2/FMD1/FMD0 bit Settings Timer Function Mode 000B Reset mode 001B 16-bit PWM timer 010B 16-bit PPG timer 011B 16/32-bit reload timer 100B 16/32-bit PWC timer ■ Reset Mode Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however, the base timer can set its function mode and the T32 bit without entering the reset mode in advance. ■ 16-bit PWM Timer The 16-bit PWM timer mainly consists of a 16-bit down counter, a 16-bit data register buffered for period setting, a 16-bit compare register buffered for duty cycle setting, and a pin controller. Period data and duty cycle data can be updated during timer operation as they are held in their buffered respective registers. The count clock for the 16-bit down counter can be selected from among five different internal clocks (available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three different external events (rising edge, falling edge and both edge detection). The PWM timer can select one-shot mode in which stops counting on an underflow or continuous mode in which repeats counting by reloading. For activation, the PWM timer can select a software trigger or one of three different external events (rising-edge detection, falling-edge detection, and both-edge detection). ■ 16-bit PPG Timer The 16-bit PPG timer mainly consists of a 16-bit down counter, a 16-bit data register for "H"-width setting, a 16-bit data register for "L"-width setting, and a pin controller. The count clock for the 16-bit down counter can be selected from among five different internal clocks (available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three different external events (rising edge, falling edge and both edge detection). The PPG timer can select one-shot mode in which stops counting on an underflow or continuous mode in which repeats counting by reloading. For activation, the PPG timer can select a software trigger or one of three different external events (risingedge detection, falling-edge detection, and both-edge detection). 484 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.1 MB91625 Series ■ 16/32-bit Reload Timer The 16/32-bit reload timer mainly consists of a 16-bit down counter, a 16-bit reload register, and a pin controller. The count clock for the 16-bit down counter can be selected from among five different internal clocks (available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three different external events (rising edge, falling edge and both edge detection). The reload timer can select one-shot mode in which stops counting on an underflow or continuous mode in which repeats counting by reloading. For activation, the reload timer can select a software trigger or one of three different external events (rising-edge detection, falling-edge detection, and both-edge detection). ■ 16/32-bit PWC Timer The 16/32-bit PWC timer mainly consists of a 16-bit up counter, a measurement input pin, and control registers. The PWC timer measures the time between arbitrary events based on the pulse input from an external source. The reference count clock can be selected from among five different internal clocks (available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256). Measurement modes "H" pulse width (↑ to ↓) / "L" pulse width (↓ to ↑) Rising period (↑ to ↑) / Falling period (↓ to ↓) Inter-edge measurement (↑ or ↓ to ↓ or ↑) The PWC timer can generate an interrupt request upon completion of measurement. The PWC timer can select one-shot measurement or continuous measurement. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 485 CHAPTER 22 Base Timer 22.2 MB91625 Series 22.2 Block Diagrams of the Base Timer This section provides a block diagram of the base timer in each function mode. ■ Block Diagram of 16-bit PWM Timer Figure 22.2-1 Block Diagram of 16-bit PWM Timer BTxPDUT BTxPCSR Load BTxPDUT Writing Buffer CKS Buffer OSEL 3 16 16 20 Peripheral clock (PCLK) Match detection Division circuit 27 External clock 28 (ECK signal) From base timer I/O selection block Count clock 16 PMSK 16-bit down counter Edge detection Counting enabled Invert control Load To base timer I/O selection block Toggle generation Underflow Wave form output (TOUT signal) EGS 2 UDIE STRG External activation trigger (TGIN signal) Edge detection From base timer I/O selection block CTEN Counting enabled MDSE DTIE Underflow/Duty match interrupt request Interrupt source generation Trigger Timer enabled CTEN TGIE Trigger interrupt request BTxPCSR: Base timer x cycle setting register (BTxPCSR) BTxPDUT: Base timer x duty setting register (BTxPDUT) 486 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.2 MB91625 Series ■ Block Diagram of 16-bit PPG Timer Figure 22.2-2 Block Diagram of 16-bit PPG Timer Reload data settings CKS BTxPRLL 16 Buffer 3 Peripheral clock (PCLK) From base timer I/O selection block External clock (ECK signal) 2 Division circuit BTxPRLH 0 Count clock 27 28 Load OSEL invert control PPG output Down counter Edge detection Counting enabled EGS (TOUT Signal) Underflow Toggle generation 2 To base timer I/O selection block PMSK UDIE STRG CTEN External activation trigger (TGIN signal) From base timer I/O selection block Counting enabled MDSE CTEN Edge detection Interrupt source generation Underflow interrupt request Trigger interrupt request Trigger Timer enabled TGIE BTxPRLL: Base timer xL width setting (BTxPRLL) BTxPRLH: Base timer xH width setting (BTxPRLH) BTxTMR: Base timer x timer register (BTxTMR) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 487 CHAPTER 22 Base Timer 22.2 MB91625 Series ■ Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0) Figure 22.2-3 Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0) 16-bit mode T32 = 0 OSEL BTxPCSR Invert control CKS Peripheral clock (PCLK) 20 Division circuit External clock (ECK signal) From base timer I/O selection block Toggle generation 16 3 Output wave form (TOUT signal) To base timer I/O selection block Count clock 27 28 Load Down counter (BTxTMR) Edge detection Counting enabled Underflow T32 EGS 2 External activation edge (TGIN signal) From base timer I/O selection block MDSE UDIE Counting enabled STRG Trigger CTEN Edge detection CTEN Underflow interrupt request Interrupt source generation Trigger interrupt request Timer TGIE BTxPCSR: Base timer x cycle setting register (BTxPCSR) BTxTMR: Base timer x timer register (BTxTMR) (Continued) 488 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.2 MB91625 Series (Continued) 32-bit mode ch.1 BT1PCSR 16 Count clock Load Down counter (BT1TMR) Counting enabled Underflow T32 = 0 T32 = 1 ch.0 OSEL Output wave form (TOUT signal) BT0PCSR Invert control CKS 3 To base timer I/O selection block 2 Peripheral clock (PCLK) Division circuit 27 External clock 28 (ECK signal) From base timer I/O selection block Toggle generation 16 0 Count clock Load Down counter (BT0TMR) Edge detection Counting enabled Underflow T32 EGS 2 MDSE Counting enabled External activation trigger (TGIN signal) From base timer I/O selection block UDIE Underflow interrupt request STRG Trigger Edge detection CTEN CTEN Interrupt source generation Trigger interrupt request Timer TGIE BT1PCSR: Base timer 1 cycle setting register (BT1PCSR) BT1TMR: Base timer 1 timer register (BT1TMR) BT0PCSR: Base timer 0 cycle setting register (BT0PCSR) BT0TMR: Base timer 0 timer register (BT0TMR) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 489 CHAPTER 22 Base Timer 22.2 MB91625 Series <Notes> 490 • The reload timer can operate in 32 bits only between ch.0 and ch.1, between ch.2 and ch.3, between ch.4 and ch.5, between ch.6 and ch.7, between ch.8 and ch.9, between ch.10 and ch.11, between ch.12 and ch.13, and between ch.14 and ch.15. No 32-bit operation is applicable to any other combination of channels. • This function supports simultaneous activation. For details, see "CHAPTER 21 Base Timer I/O Select Function". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.2 MB91625 Series ■ Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0) Figure 22.2-4 Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0) 16-bit mode BTxDTBF T32 = 0 CKS 3 Peripheral clock (PCLK) 16 20 Division circuit 27 28 Count clock Clearing Up counter Counting enabled Overflow MDSE MDSE T32 EGS 3 Wave form to be measured (TIN signal) CTEN Edge detection From base timer I/O selection block Overflow OVIE Interrupt Request Counting enabled Interrupt source generation End of measuring Interrupt Request Activation detection CTEN Edge detection Stop detection EDIE BTxDTBF: Base timer x data buffer register (BTxDTBF) (Continued) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 491 CHAPTER 22 Base Timer 22.2 MB91625 Series (Continued) 32-bit mode ch.1 BT1DTBF 16 Clearing Count clock Up counter (BT1TMR) Counting enabled Overflow T32 = 0 T32 = 1 BT0DTBF ch.0 CKS 3 Peripheral clock (PCLK) 16 20 Division circuit Count clock 27 28 Clearing Up counter (BT0TMR) Counting enabled Overflow MDSE MDSE T32 EGS 3 Wave form to be measured (TIN signal) Overflow interrupt request CTEN Interrupt source generation Edge detection From base timer I/O selection block OVIE Counting enabled End of measuring Interrupt Request Activation detection CTEN Edge detection Stop detection EDIE BT0DTBF: Base timer 0 data buffer register (BT0DTBF) BT1DTBF: Base timer 1 data buffer register (BT1DTBF) 492 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.2 MB91625 Series <Notes> • The PWC timer can operate in 32 bits only between ch.0 and ch.1, between ch.2 and ch.3, between ch.4 and ch.5, between ch.6 and ch.7, between ch.8 and ch.9, between ch.10 and ch.11, between ch.12 and ch.13, and between ch.14 and ch.15. No 32-bit operation is applicable to any other combination of channels. • This function supports simultaneous activation. For details, see "CHAPTER 21 Base Timer I/O Select Function". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 493 CHAPTER 22 Base Timer 22.3 MB91625 Series 22.3 Base Timer's Registers This section lists the registers used for the base timer and their bit configurations in each timer function mode. ■ List of Base Timer's Registers Table 22.3-1 Registers used for 16-bit PWM timer (1 / 4) Channel Register Name Reference Common BTSSSR Base timer same time soft start register 21.4.5 Common to 0 to 3 BTSEL0123 Base timer io select register for ch.0/1/2/3 21.4.1 Common to 4 to 7 BTSEL4567 Base timer io select register for ch.4/5/6/7 21.4.2 Common to 8 to 11 BTSEL89AB Base timer io select register for ch.8/9/A/B 21.4.3 Common to 12 to 15 BTSELCDEF Base timer io select register for ch.C/D/E/F 21.4.4 0 BT0TMCR Base timer 0 timer control register 22.8.1.1 BT0STC Base timer 0 status control register 22.8.1.1 BT0PCSR Base timer 0 cycle setting register 22.8.1.2 BT0PDUT Base timer 0 duty setting register 22.8.1.3 BT0TMR Base timer 0 timer register 22.8.1.4 BT1TMCR Base timer 1 timer control register 22.8.1.1 BT1STC Base timer 1 status control register 22.8.1.1 BT1PCSR Base timer 1 cycle setting register 22.8.1.2 BT1PDUT Base timer 1 duty setting register 22.8.1.3 BT1TMR Base timer 1 timer register 22.8.1.4 BT2TMCR Base timer 2 timer control register 22.8.1.1 BT2STC Base timer 2 status control register 22.8.1.1 BT2PCSR Base timer 2 cycle setting register 22.8.1.2 BT2PDUT Base timer 2 duty setting register 22.8.1.3 BT2TMR Base timer 2 timer register 22.8.1.4 1 2 494 Abbreviated Register Name FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-1 Registers used for 16-bit PWM timer (2 / 4) Channel 3 4 5 6 7 8 CM71-10151-2E Abbreviated Register Name Register Name Reference BT3TMCR Base timer 3 timer control register 22.8.1.1 BT3STC Base timer 3 status control register 22.8.1.1 BT3PCSR Base timer 3 cycle setting register 22.8.1.2 BT3PDUT Base timer 3 duty setting register 22.8.1.3 BT3TMR Base timer 3 timer register 22.8.1.4 BT4TMCR Base timer 4 timer control register 22.8.1.1 BT4STC Base timer 4 status control register 22.8.1.1 BT4PCSR Base timer 4 cycle setting register 22.8.1.2 BT4PDUT Base timer 4 duty setting register 22.8.1.3 BT4TMR Base timer 4 timer register 22.8.1.4 BT5TMCR Base timer 5 timer control register 22.8.1.1 BT5STC Base timer 5 status control register 22.8.1.1 BT5PCSR Base timer 5 cycle setting register 22.8.1.2 BT5PDUT Base timer 5 duty setting register 22.8.1.3 BT5TMR Base timer 5 timer register 22.8.1.4 BT6TMCR Base timer 6 timer control register 22.8.1.1 BT6STC Base timer 6 status control register 22.8.1.1 BT6PCSR Base timer 6 cycle setting register 22.8.1.2 BT6PDUT Base timer 6 duty setting register 22.8.1.3 BT6TMR Base timer 6 timer register 22.8.1.4 BT7TMCR Base timer 7 timer control register 22.8.1.1 BT7STC Base timer 7 status control register 22.8.1.1 BT7PCSR Base timer 7 cycle setting register 22.8.1.2 BT7PDUT Base timer 7 duty setting register 22.8.1.3 BT7TMR Base timer 7 timer register 22.8.1.4 BT8TMCR Base timer 8 timer control register 22.8.1.1 BT8STC Base timer 8 status control register 22.8.1.1 BT8PCSR Base timer 8 cycle setting register 22.8.1.2 BT8PDUT Base timer 8 duty setting register 22.8.1.3 BT8TMR Base timer 8 timer register 22.8.1.4 FUJITSU MICROELECTRONICS LIMITED 495 CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-1 Registers used for 16-bit PWM timer (3 / 4) Channel 9 10 11 12 13 14 496 Abbreviated Register Name Register Name Reference BT9TMCR Base timer 9 timer control register 22.8.1.1 BT9STC Base timer 9 status control register 22.8.1.1 BT9PCSR Base timer 9 cycle setting register 22.8.1.2 BT9PDUT Base timer 9 duty setting register 22.8.1.3 BT9TMR Base timer 9 timer register 22.8.1.4 BTATMCR Base timer 10 timer control register 22.8.1.1 BTASTC Base timer 10 status control register 22.8.1.1 BTAPCSR Base timer 10 cycle setting register 22.8.1.2 BTAPDUT Base timer 10 duty setting register 22.8.1.3 BTATMR Base timer 10 timer register 22.8.1.4 BTBTMCR Base timer 11 timer control register 22.8.1.1 BTBSTC Base timer 11 status control register 22.8.1.1 BTBPCSR Base timer 11 cycle setting register 22.8.1.2 BTBPDUT Base timer 11 duty setting register 22.8.1.3 BTBTMR Base timer 11 timer register 22.8.1.4 BTCTMCR Base timer 12 timer control register 22.8.1.1 BTCSTC Base timer 12 status control register 22.8.1.1 BTCPCSR Base timer 12 cycle setting register 22.8.1.2 BTCPDUT Base timer 12 duty setting register 22.8.1.3 BTCTMR Base timer 12 timer register 22.8.1.4 BTDTMCR Base timer 13 timer control register 22.8.1.1 BTDSTC Base timer 13 status control register 22.8.1.1 BTDPCSR Base timer 13 cycle setting register 22.8.1.2 BTDPDUT Base timer 13 duty setting register 22.8.1.3 BTDTMR Base timer 13 timer register 22.8.1.4 BTETMCR Base timer 14 timer control register 22.8.1.1 BTESTC Base timer 14 status control register 22.8.1.1 BTEPCSR Base timer 14 cycle setting register 22.8.1.2 BTEPDUT Base timer 14 duty setting register 22.8.1.3 BTETMR Base timer 14 timer register 22.8.1.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-1 Registers used for 16-bit PWM timer (4 / 4) Channel Abbreviated Register Name 15 Register Name Reference BTFTMCR Base timer 15 timer control register 22.8.1.1 BTFSTC Base timer 15 status control register 22.8.1.1 BTFPCSR Base timer 15 cycle setting register 22.8.1.2 BTFPDUT Base timer 15 duty setting register 22.8.1.3 BTFTMR Base timer 15 timer register 22.8.1.4 Table 22.3-2 Registers for the 16-bit PPG timer (1 / 4) Channel Register Name Reference Common BTSSSR Base timer same time soft start register 21.4.5 Common to 0 to 3 BTSEL0123 Base timer io select register for ch.0/1/2/3 21.4.1 Common to 4 to 7 BTSEL4567 Base timer io select register for ch.4/5/6/7 21.4.2 Common to 8 to 11 BTSEL89AB Base timer io select register for ch.8/9/A/B 21.4.3 Common to 12 to 15 BTSELCDEF Base timer io select register for ch.C/D/E/F 21.4.4 0 BT0TMCR Base timer 0 timer control register 22.8.2.1 BT0STC Base timer 0 status control register 22.8.2.1 BT0PRLL Base timer 0 L width setting register 22.8.2.2 BT0PRLH Base timer 0 H width setting register 22.8.2.3 BT0TMR Base timer 0 timer register 22.8.2.4 BT1TMCR Base timer 1 timer control register 22.8.2.1 BT1STC Base timer 1 status control register 22.8.2.1 BT1PRLL Base timer 1 L width setting register 22.8.2.2 BT1PRLH Base timer 1 H width setting register 22.8.2.3 BT1TMR Base timer 1 timer register 22.8.2.4 BT2TMCR Base timer 2 timer control register 22.8.2.1 BT2STC Base timer 2 status control register 22.8.2.1 BT2PRLL Base timer 2 L width setting register 22.8.2.2 BT2PRLH Base timer 2 H width setting register 22.8.2.3 BT2TM Base timer 2 timer register 22.8.2.4 1 2 CM71-10151-2E Abbreviated Register Name FUJITSU MICROELECTRONICS LIMITED 497 CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-2 Registers for the 16-bit PPG timer (2 / 4) Channel 3 4 5 6 7 8 498 Abbreviated Register Name Register Name Reference BT3TMCR Base timer 3 timer control register 22.8.2.1 BT3STC Base timer 3 status control register 22.8.2.1 BT3PRLL Base timer 3 L width setting register 22.8.2.2 BT3PRLH Base timer 3 H width setting register 22.8.2.3 BT3TMR Base timer 3 timer register 22.8.2.4 BT4TMCR Base timer 4 timer control register 22.8.2.1 BT4STC Base timer 4 status control register 22.8.2.1 BT4PRLL Base timer 4 L width setting register 22.8.2.2 BT4PRLH Base timer 4 H width setting register 22.8.2.3 BT4TMR Base timer 4 timer register 22.8.2.4 BT5TMCR Base timer 5 timer control register 22.8.2.1 BT5STC Base timer 5 status control register 22.8.2.1 BT5PRLL Base timer 5 L width setting register 22.8.2.2 BT5PRLH Base timer 5 H width setting register 22.8.2.3 BT5TMR Base timer 5 timer register 22.8.2.4 BT6TMCR Base timer 6 timer control register 22.8.2.1 BT6STC Base timer 6 status control register 22.8.2.1 BT6PRLL Base timer 6 L width setting register 22.8.2.2 BT6PRLH Base timer 6 H width setting register 22.8.2.3 BT6TMR Base timer 6 timer register 22.8.2.4 BT7TMCR Base timer 7 timer control register 22.8.2.1 BT7STC Base timer 7 status control register 22.8.2.1 BT7PRLL Base timer 7 L width setting register 22.8.2.2 BT7PRLH Base timer 7 H width setting register 22.8.2.3 BT7TMR Base timer 7 timer register 22.8.2.4 BT8TMCR Base timer 8 timer control register 22.8.2.1 BT8STC Base timer 8 status control register 22.8.2.1 BT8PRLL Base timer 8 L width setting register 22.8.2.2 BT8PRLH Base timer 8 H width setting register 22.8.2.3 BT8TMR Base timer 8 timer register 22.8.2.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-2 Registers for the 16-bit PPG timer (3 / 4) Channel 9 10 11 12 13 14 CM71-10151-2E Abbreviated Register Name Register Name Reference BT9TMCR Base timer 9 timer control register 22.8.2.1 BT9STC Base timer 9 status control register 22.8.2.1 BT9PRLL Base timer 9 L width setting register 22.8.2.2 BT9PRLH Base timer 9 H width setting register 22.8.2.3 BT9TMR Base timer 9 timer register 22.8.2.4 BTATMCR Base timer 10 timer control register 22.8.2.1 BTASTC Base timer 10 status control register 22.8.2.1 BTAPRLL Base timer 10 L width setting register 22.8.2.2 BTAPRLH Base timer 10 H width setting register 22.8.2.3 BTATMR Base timer 10 timer register 22.8.2.4 BTBTMCR Base timer 11 timer control register 22.8.2.1 BTBSTC Base timer 11 status control register 22.8.2.1 BTBPRLL Base timer 11 L width setting register 22.8.2.2 BTBPRLH Base timer 11 H width setting register 22.8.2.3 BTBTMR Base timer 11 timer register 22.8.2.4 BTCTMCR Base timer 12 timer control register 22.8.2.1 BTCSTC Base timer 12 status control register 22.8.2.1 BTCPRLL Base timer 12 L width setting register 22.8.2.2 BTCPRLH Base timer 12 H width setting register 22.8.2.3 BTCTMR Base timer 12 timer register 22.8.2.4 BTDTMCR Base timer 13 timer control register 22.8.2.1 BTDSTC Base timer 13 status control register 22.8.2.1 BTDPRLL Base timer 13 L width setting register 22.8.2.2 BTDPRLH Base timer 13 H width setting register 22.8.2.3 BTDTMR Base timer 13 timer register 22.8.2.4 BTETMCR Base timer 14 timer control register 22.8.2.1 BTESTC Base timer 14 status control register 22.8.2.1 BTEPRLL Base timer 14 L width setting register 22.8.2.2 BTEPRLH Base timer 14 H width setting register 22.8.2.3 BTETMR Base timer 14 timer register 22.8.2.4 FUJITSU MICROELECTRONICS LIMITED 499 CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-2 Registers for the 16-bit PPG timer (4 / 4) Channel Abbreviated Register Name 15 Register Name Reference BTFTMCR Base timer 15 timer control register 22.8.2.1 BTFSTC Base timer 15 status control register 22.8.2.1 BTFPRLL Base timer 15 L width setting register 22.8.2.2 BTFPRLH Base timer 15 H width setting register 22.8.2.3 BTFTMR Base timer 15 timer register 22.8.2.4 Table 22.3-3 Registers for the 16/32-bit reload timer (1 / 3) Channel Register Name Reference Common BTSSSR Base timer same time soft start register 21.4.5 Common to 0 to 3 BTSEL0123 Base timer io select register for ch.0/1/2/3 21.4.1 Common to 4 to 7 BTSEL4567 Base timer io select register for ch.4/5/6/7 21.4.2 Common to 8 to 11 BTSEL89AB Base timer io select register for ch.8/9/A/B 21.4.3 Common to 12 to 15 BTSELCDEF Base timer io select register for ch.C/D/E/F 21.4.4 0 BT0TMCR Base timer 0 timer control register 22.8.3.1 BT0STC Base timer 0 status control register 22.8.3.1 BT0PCSR Base timer 0 cycle setting register 22.8.3.2 BT0TMR Base timer 0 timer register 22.8.3.3 BT1TMCR Base timer 1 timer control register 22.8.3.1 BT1STC Base timer 1 status control register 22.8.3.1 BT1PCSR Base timer 1 cycle setting register 22.8.3.2 BT1TMR Base timer 1 timer register 22.8.3.3 BT2TMCR Base timer 2 timer control register 22.8.3.1 BT2STC Base timer 2 status control register 22.8.3.1 BT2PCSR Base timer 2 cycle setting register 22.8.3.2 BT2TMR Base timer 2 timer register 22.8.3.3 BT3TMCR Base timer 3 timer control register 22.8.3.1 BT3STC Base timer 3 status control register 22.8.3.1 BT3PCSR Base timer 3 cycle setting register 22.8.3.2 BT3TMR Base timer 3 timer register 22.8.3.3 1 2 3 500 Abbreviated Register Name FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-3 Registers for the 16/32-bit reload timer (2 / 3) Channel 4 5 6 7 8 9 10 CM71-10151-2E Abbreviated Register Name Register Name Reference BT4TMCR Base timer 4 timer control register 22.8.3.1 BT4STC Base timer 4 status control register 22.8.3.1 BT4PCSR Base timer 4 cycle setting register 22.8.3.2 BT4TMR Base timer 4 timer register 22.8.3.3 BT5TMCR Base timer 5 timer control register 22.8.3.1 BT5STC Base timer 5 status control register 22.8.3.1 BT5PCSR Base timer 5 cycle setting register 22.8.3.2 BT5TMR Base timer 5 timer register 22.8.3.3 BT6TMCR Base timer 6 timer control register 22.8.3.1 BT6STC Base timer 6 status control register 22.8.3.1 BT6PCSR Base timer 6 cycle setting register 22.8.3.2 BT6TMR Base timer 6 timer register 22.8.3.3 BT7TMCR Base timer 7 timer control register 22.8.3.1 BT7STC Base timer 7 status control register 22.8.3.1 BT7PCSR Base timer 7 cycle setting register 22.8.3.2 BT7TMR Base timer 7 timer register 22.8.3.3 BT8TMCR Base timer 8 timer control register 22.8.3.1 BT8STC Base timer 8 status control register 22.8.3.1 BT8PCSR Base timer 8 cycle setting register 22.8.3.2 BT8TMR Base timer 8 timer register 22.8.3.3 BT9TMCR Base timer 9 timer control register 22.8.3.1 BT9STC Base timer 9 status control register 22.8.3.1 BT9PCSR Base timer 9 cycle setting register 22.8.3.2 BT9TMR Base timer 9 timer register 22.8.3.3 BTATMCR Base timer 10 timer control register 22.8.3.1 BTASTC Base timer 10 status control register 22.8.3.1 BTAPCSR Base timer 10 cycle setting register 22.8.3.2 BTATMR Base timer 10 timer register 22.8.3.3 FUJITSU MICROELECTRONICS LIMITED 501 CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-3 Registers for the 16/32-bit reload timer (3 / 3) Channel Abbreviated Register Name 11 12 13 14 15 Register Name Reference BTBTMCR Base timer 11 timer control register 22.8.3.1 BTBSTC Base timer 11 status control register 22.8.3.1 BTBPCSR Base timer 11 cycle setting register 22.8.3.2 BTBTMR Base timer 11 timer register 22.8.3.3 BTCTMCR Base timer 12 timer control register 22.8.3.1 BTCSTC Base timer 12 status control register 22.8.3.1 BTCPCSR Base timer 12 cycle setting register 22.8.3.2 BTCTMR Base timer 12 timer register 22.8.3.3 BTDTMCR Base timer 13 timer control register 22.8.3.1 BTDSTC Base timer 13 status control register 22.8.3.1 BTDPCSR Base timer 13 cycle setting register 22.8.3.2 BTDTMR Base timer 13 timer register 22.8.3.3 BTETMCR Base timer 14 timer control register 22.8.3.1 BTESTC Base timer 14 status control register 22.8.3.1 BTEPCSR Base timer 14 cycle setting register 22.8.3.2 BTETMR Base timer 14 timer register 22.8.3.3 BTFTMCR Base timer 15 timer control register 22.8.3.1 BTFSTC Base timer 15 status control register 22.8.3.1 BTFPCSR Base timer 15 cycle setting register 22.8.3.2 BTFTMR Base timer 15 timer register 22.8.3.3 Table 22.3-4 List of registers used for 16/32-bit PWC timer (1 / 3) Channel 502 Abbreviated Register Name Register Name Reference Common BTSSSR Base timer same time soft start register 21.4.5 Common to 0 to 3 BTSEL0123 Base timer io select register for ch.0/1/2/3 21.4.1 Common to 4 to 7 BTSEL4567 Base timer io select register for ch.4/5/6/7 21.4.2 Common to 8 to 11 BTSEL89AB Base timer io select register for ch.8/9/A/B 21.4.3 Common to 12 to 15 BTSELCDEF Base timer io select register for ch.C/D/E/F 21.4.4 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-4 List of registers used for 16/32-bit PWC timer (2 / 3) Channel 0 1 2 3 4 5 6 7 8 9 CM71-10151-2E Abbreviated Register Name Register Name Reference BT0TMCR Base timer 0 timer control register 22.8.4.1 BT0STC Base timer 0 status control register 22.8.4.1 BT0DTBF Base timer 0 data buffer register 22.8.4.2 BT1TMCR Base timer 1 timer control register 22.8.4.1 BT1STC Base timer 1 status control register 22.8.4.1 BT1DTBF Base timer 1 data buffer register 22.8.4.2 BT2TMCR Base timer 2 timer control register 22.8.4.1 BT2STC Base timer 2 status control register 22.8.4.1 BT2DTBF Base timer 2 data buffer register 22.8.4.2 BT3TMCR Base timer 3 timer control register 22.8.4.1 BT3STC Base timer 3 status control register 22.8.4.1 BT3DTBF Base timer 3 data buffer register 22.8.4.2 BT4TMCR Base timer 4 timer control register 22.8.4.1 BT4STC Base timer 4 status control register 22.8.4.1 BT4DTBF Base timer 4 data buffer register 22.8.4.2 BT5TMCR Base timer 5 timer control register 22.8.4.1 BT5STC Base timer 5 status control register 22.8.4.1 BT5DTBF Base timer 5 data buffer register 22.8.4.2 BT6TMCR Base timer 6 timer control register 22.8.4.1 BT6STC Base timer 6 status control register 22.8.4.1 BT6DTBF Base timer 6 data buffer register 22.8.4.2 BT7TMCR Base timer 7 timer control register 22.8.4.1 BT7STC Base timer 7 status control register 22.8.4.1 BT7DTBF Base timer 7 data buffer register 22.8.4.2 BT8TMCR Base timer 8 timer control register 22.8.4.1 BT8STC Base timer 8 status control register 22.8.4.1 BT8DTBF Base timer 8 data buffer register 22.8.4.2 BT9TMCR Base timer 9 timer control register 22.8.4.1 BT9STC Base timer 9 status control register 22.8.4.1 BT9DTBF Base timer 9 data buffer register 22.8.4.2 FUJITSU MICROELECTRONICS LIMITED 503 CHAPTER 22 Base Timer 22.3 MB91625 Series Table 22.3-4 List of registers used for 16/32-bit PWC timer (3 / 3) Channel 10 11 12 13 14 15 504 Abbreviated Register Name Register Name Reference BTATMCR Base timer 10 timer control register 22.8.4.1 BTASTC Base timer 10 status control register 22.8.4.1 BTADTBF Base timer 10 data buffer register 22.8.4.2 BTBTMCR Base timer 11 timer control register 22.8.4.1 BTBSTC Base timer 11 status control register 22.8.4.1 BTBDTBF Base timer 11 data buffer register 22.8.4.2 BTCTMCR Base timer 12 timer control register 22.8.4.1 BTCSTC Base timer 12 status control register 22.8.4.1 BTCDTBF Base timer 12 data buffer register 22.8.4.2 BTDTMCR Base timer 13 timer control register 22.8.4.1 BTDSTC Base timer 13 status control register 22.8.4.1 BTDDTBF Base timer 13 data buffer register 22.8.4.2 BTETMCR Base timer 14 timer control register 22.8.4.1 BTESTC Base timer 14 status control register 22.8.4.1 BTEDTBF Base timer 14 data buffer register 22.8.4.2 BTFTMCR Base timer 15 timer control register 22.8.4.1 BTFSTC Base timer 15 status control register 22.8.4.1 BTFDTBF Base timer 15 data buffer register 22.8.4.2 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.4 MB91625 Series 22.4 Operations of the Base Timer This section introduces how the base timer operates in each timer function mode. ■ Operations of the Base Timer ● Reset mode Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however, the base timer can set its function mode and the T32 bit without entering the reset mode in advance. If you set this mode for even-numbered channels in 32-bit mode, odd-numbered channels are reset as well at the same time. Thus you do not have to set the reset mode for odd-numbered channels. ● 16-bit PWM timer The 16-bit PWM timer starts decrementing its counter by the value set as a period when triggered to start. The PWM timer then sets the output to the "L" level first and, if the 16-bit down counter value matches the value set in the duty setting register, inverts the output to the "H" level. Then it inverts the output back to the "L" level when the counter causes an underflow subsequently. This generates a waveform with an arbitrary period and duty cycle. ● 16-bit PPG timer The 16-bit PPG timer starts decrementing its counter by the value set in the "L"-width setting reload register when triggered to start. The PPG timer then sets the output to the "L" level first and inverts the output back to the "H" level when the counter causes an underflow. The PPG timer continuously decrements the counter by the value set in the "H"-width setting reload register and inverts the output level to "L" when the counter causes an underflow. This generates a waveform with arbitrary "L" and "H" widths. ● 16-bit reload timer The 16-bit reload timer starts decrementing its 16-bit down counter by the value set as a period when triggered to start. When the down counter causes an underflow, the interrupt flag is set. Depending on the MDSE bit setting, the output level either toggles, or is inverted, between "H" and "L" each time the counter causes an underflow or becomes "H" when the counter starts counting and "L" when it causes an underflow. ● 32-bit reload timer The 32-bit reload timer is the same in basic operation as the 16-bit reload timer, except that it works as a 32-bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered and odd-numbered channels then operate as the lower 16-bit and upper 16-bit timers, respectively, interrupt control and output wave control follow their respective settings for the even-numbered channel. To set the period, write the value to the upper register (odd-numbered channel) first and then to the lower register (even-numbered channel). To obtain the timer value, read the lower register (even-numbered channel) first and then the upper register (odd-numbered channel). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 505 CHAPTER 22 Base Timer 22.4 MB91625 Series <Notes> • The reload timers can operate in 32 bits only between ch.0 and ch.1, between ch.2 and ch.3, between ch.4 and ch.5, between ch.6 and ch.7, between ch.8 and ch.9, between ch.10 and ch.11, between ch.12 and ch.13, and between ch.14 and ch.15. No 32-bit operation is applicable to any other combination of channels. • This function supports simultaneous activation. For details, see "CHAPTER 21 Base Timer I/O Select Function". ● 16-bit PWC timer The 16-bit PWC timer starts the 16-bit up counter upon input of a pre-set measurement start edge and stops the counter upon detection of a measurement stop edge. The count value between the two edges is written to the data buffer register as a pulse width. ● 32-bit PWC timer The 32-bit PWC timer is the same in basic operation as the 16-bit PWC timer, except that it works as a 32-bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered and odd-numbered channels then operate as the lower 16-bit and upper 16-bit counters, respectively, interrupt control follows the setting for the even-numbered channel. To obtain the measured value or count value, read the lower register (even-numbered channel) first and then the upper register (oddnumbered channel). <Notes> 506 • The PWC timer can operate in 32 bits only between ch.0 and ch.1, between ch.2 and ch.3, between ch.4 and ch.5, between ch.6 and ch.7, between ch.8 and ch.9, between ch.10 and ch.11, between ch.12 and ch.13, and between ch.14 and ch.15. No 32-bit operation is applicable to any other combination of channels. • This function supports simultaneous activation. For details, see "CHAPTER 21 Base Timer I/O Select Function". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.5 MB91625 Series 22.5 32-bit Mode Operations The reload timer and PWC timer can operate in 32-bit mode using a pair of channels. This section describes the basic functions and operations of 32-bit mode. ■ Functions of 32-bit Mode The 32-bit mode combines two channels of base timer into a 32-bit data reload timer or PWC timer. Either 32-bit timer allows the timer/counter value to be read even during operation as it takes the upper 16-bit timer/counter value of the odd-numbered channel also when reading the lower 16-bit timer/counter value of the even-numbered channel. ■ Setting the 32-bit Mode First, set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register for the even-numbered channel to "000B" to reset in reset mode. Then, select the reload timer or PWC timer and set its operations in the same way as in 16-bit mode. At this time, write "1" to the T32 bit in the BTxTMCR register to enter the 32-bit operation mode. The T32 bit for the odd-numbered channel must be left containing "0". Neither the reset mode setting is required for the odd-numbered channel. To use the base timer as the reload timer, set the period setting register for the odd-numbered channel to the upper 16-bit reload value among 32 bits and set the period setting register for the even-numbered channel to the lower 16-bit reload value. As the transition to 32-bit operation mode takes place the moment is written to the T32 bit, the setting must be changed with counting halted on both of the channels. To switch from 32-bit mode to 16-bit mode, set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register for the even-numbered channel to "000B" to reset the states of both of the even-numbered and odd-numbered channels in reset mode. Then set each channel for operation in 16-bit mode. ■ Operations in 32-bit Mode When the reload timer or PWC timer is started in 32-bit mode under control of the even-numbered channel, the timer/counter of the even-numbered channel operates as the lower 16-bit timer/counter and the timer/counter of the odd-numbered channel operates as the upper 16-bit one. In 32-bit mode, the base timer follows the settings for the even-numbered channel while ignoring those for the odd-numbered channel (except the period setting register when serving as the reload timer). Even for the timer start, waveform output, and interrupt signal settings, the even-numbered channel overrides the odd-numbered channel (odd-numbered channel is always masked at "L"). The following example shows a PWC configuration using ch.0 and ch.1. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 507 CHAPTER 22 Base Timer 22.5 ch. 1 MB91625 Series Underflow Overflow ch.0 Interrupt Upper 16-bit timer/counter Upper 16-bit reload value T32=0 Underflow Overflow Lower 16-bit timer/counter Waveform output Read/write signals Lower 16-bit reload value PWC measured waveform/ external trigger T32=1 <Notes> 508 • The reload timer or PWC timer can operate in 32 bits only between ch.0 and ch.1, between ch.2 and ch.3, between ch.4 and ch.5, between ch.6 and ch.7, between ch.8 and ch.9, between ch.10 and ch.11, between ch.12 and ch.13, and between ch.14 and ch.15. No 32-bit operation is applicable to any other combination of channels. • This function supports simultaneous activation. For details, see "CHAPTER 21 Base Timer I/O Select Function". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.6 MB91625 Series 22.6 Notes of Using the Base Timer This section summarizes the notes on using the base timer. ■ Common Notes on Using Each Type of Timer ● Notes on setting through programming • The following bits in the BTxTMCR register must not be updated during operation. Be sure to update them before starting the base timer or after stopping it. [bit14, bit13, bit12] CKS2, CKS1, CKS0 : Clock select bits [bit10, bit9, bit8] EGS2, EGS1, EGS0 : Measurement edge select bits [bit7] T32 : 32-bit timer select bit (Used with the reload timer or PWC timer selected) [bit6, bit5,bit4] FMD2, FMD1, FMD0 : Timer function mode select bits [bit2] MDSE : Measurement mode (one-shot/continuous) select bit • If you set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to "000B" to enter the reset mode, all the registers of the base timer are initialized and thus they must be set all over again. • If you set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to "000B" to enter the reset mode, the other bits in the BTxTMCR register are initialized with their settings ignored. ■ Notes on Using the 16-bit PWM/PPG/Reload Timer ● Notes on setting through programming • When the interrupt request flag is attempted to be set and cleared at the same timing, the flag set action overrides the flag clear action. • When the down counter is attempted to load and count at the same timing, the load action overrides the count action. • Set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to select the timer function mode before setting the period, duty cycle, "H" width, and "L" width. • If a restart is detected when counting is completed in one-shot mode, the counter is restarted with the count value reloaded. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 509 CHAPTER 22 Base Timer 22.6 MB91625 Series ■ Notes on Using the PWC Timer ● Notes on setting through programming • Writing "1" to the counting enable bit (CTEN) clears the counter, nullifying the data existing in the counter before counting is enabled. • If you set the PWC mode (FMD = 100B) after a system reset or in reset mode and enables measurement (CTEN = 1) at the same time, the timer may operate according to the immediately preceding measurement signal. • If a measurement start edge is detected the moment a restart is set in continuous measurement mode, the timer immediately starts counting from "0001H". • An attempt to restart the timer after starting counting can result as follows, depending on that timing: • If the attempt is made at a measurement end edge in one-shot pulse width measurement mode: Although the timer is restarted and waits for an measurement start edge, the measurement end flag (EDIR) is set. • If the attempt is made at a measurement end edge in continuous pulse width measurement mode: Although the timer is restarted and waits for a measurement start edge, the measurement end flag (EDIR) is set and the current measurement result is transferred to the BTxDTBF register. When restarting the timer during operation, control interrupts while paying attention to the behaviors of flags. 510 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.7 MB91625 Series 22.7 Base Timer Interrupts This section lists the interrupt request flags, interrupt enable bits, and interrupt factors for the base timer in each timer function mode. ■ Interrupt Control Bits and Interrupt Factors by Timer Function Mode Table 22.7-1 lists the interrupt control bits and interrupt factors for the base timer in each timer function mode. Table 22.7-1 Interrupt Control Bits and Interrupt Factors in Each Timer Function Mode Status control register (BTxSTC) Interrupt request flag bits Interrupt request enable bits Interrupt factors IRQ UDIR: bit0 UDIE: bit4 Underflow detection IRQ0 DTIR: bit1 DTIE: bit5 Duty match detection TGIR: bit2 TGIE: bit6 Timer start trigger detection IRQ1 PPG timer function UDIR: bit0 UDIE: bit4 Underflow detection IRQ0 TGIR: bit2 TGIE: bit6 Timer start trigger detection IRQ1 Reload timer function UDIR: bit0 UDIE: bit4 Underflow detection IRQ0 TGIR: bit2 TGIE: bit6 Timer start trigger detection IRQ1 PWC timer function OVIR: bit0 OVIE: bit4 Overflow detection IRQ0 EDIR: bit2 EDIE: bit6 Measurement end detection IRQ1 PWM timer function CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 511 CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8 Base Timer Description by Function Mode This section describes each function of the base timer. ■ Base Timer Function 512 • PWM function • PPG function • Reload timer function • PWC function FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.1 PWM Function The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the PWM timer. • Timer Control Register (BTxTMCR) for PWM Timer • PWM Period Setting Register (BTxPCSR) • PWM Duty Setting Register (BTxPDUT) • Timer Register (BTxTMR) • 16-bit PWM Timer Operation • One-shot Operation • Interrupt Factors and Timing Chart • Output Waveforms CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 513 CHAPTER 22 Base Timer 22.8 22.8.1.1 MB91625 Series Timer Control Register (BTxTMCR) for PWM Timer The timer control register (BTxTMCR) controls the PWM timer. Keep in mind that the register contains bits which cannot be updated with the PWM timer operating. ■ Timer Control Register (BTxTMCR Upper Byte) Figure 22.8-1 Timer Control Register (BTxTMCR Upper Byte) bit15 - bit14 bit13 bit12 bit11 bit10 R/W R/W R/W R/W 0 R/W : Readable/writable : Initial value R/W Initial value: -0000000B (At reset) R/W Trigger input edge select bits 0 Disable trigger input 0 1 Rising edge 1 0 Falling edge 1 1 Both edges PMSK Pulse output mask bit 0 Normal output 1 Fixed to "L"-level output RTGEN Restart enable bit 0 Disables restarting 1 Enable restarting CKS2 CKS1 CKS0 514 bit8 CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0 EGS1 EGS0 R/W bit9 Count clock select bits 0 0 0 φ 0 0 1 φ/4 0 1 0 φ/16 0 1 1 φ/128 1 0 0 φ/256 1 0 1 External clock (rising edge event) 1 1 0 External clock (falling edge event) 1 1 1 External clock (both edge event) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-1 Timer Control Register (BTxTMCR Upper Byte) Bit name bit15 CM71-10151-2E Undefined bit Function • The read value of this bit is undefined. • Write to this bit takes no effect. Select the count clock for the 16-bit down counter. The count clock promptly reflects any changes made to its setting. CKS2 to CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. bit14 to bit12 CKS2, CKS1, CKS0: Count clock select bits • • bit11 RTGEN: Restart enable bit Enables restarting with a software trigger or trigger input. bit10 PMSK: Pulse output mask bit • • • bit9, bit8 EGS1, EGS0: Trigger input edge select bits • Controls the PWM output waveform level. When this bit is "0", the PWM waveform is output as it is. When the bit is "1", the PWM output is masked to the "L" level irrespective of the period and duty cycle. Note: Setting the PMSK bit to "1" with the OSEL bit (bit3) set for inverted output masks the PWM output to the "H" level. Select the effective edge of the input waveform as an external trigger to set the trigger condition. • When these bits are set to the initial value or "00B", no effective edge of the input waveform is selected, preventing the timer from being triggered by the external waveform. Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of EGS1 and EGS0. • EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. FUJITSU MICROELECTRONICS LIMITED 515 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Timer Control Register (BTxTMCR Lower Byte) Figure 22.8-2 Timer Control Register (BTxTMCR Lower Byte) bit7 R/W bit6 bit5 bit4 bit3 bit2 bit1 FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG R/W R/W R/W R/W R/W R/W 516 R/W Initial value: 00000000B (At reset) STRG Software trigger bit 0 Disable software trigger 1 Start with software trigger CTEN Counting enable bit 0 Disables counting 1 Enables counting MDSE Mode select bit 0 Continuous operation 1 One-shot operation OSEL Output polarity select bit 0 Normal polarity 1 Inverted polarity FMD2 FMD1 FMD0 R/W - bit0 Timer function select bits 0 0 0 Reset mode 0 0 1 Selects PWM function mode 0 1 0 Selects PPG function mode 0 1 1 Selects reload timer function mode 1 0 0 Selects PWC function mode : Readable/writable : Undefined bit 1 0 1 1 1 0 : Initial value 1 1 1 Setting not allowed FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-2 Timer Control Register (BTxTMCR Lower Byte) Bit name bit7 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit6 to bit4 FMD2, FMD1, FMD0: Timer function select bits • • These bits select the timer function mode. Setting the FMD2, FMD1, and FMD0 bits to "001B" selects the PWM function mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. bit3 CM71-10151-2E Function OSEL: Output polarity select bit • Selects the polarity of PWM output. Polarity After reset Normal "L" output Inverted "H" output Duty match Underflow bit2 MDSE: Mode select bit • • Selects continuous pulse output or one-shot pulse output. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. bit1 CTEN: Counting enable bit • • This bit enables the down counter. Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the counter. bit0 STRG: Software trigger bit • Writing "1" to the STRG bit with the CTEN bit containing "1" generates a software trigger. Note: Writing "1" to the CTEN and STRG bits at the same time also generates a software trigger. • The value read from the STRG bit is always "0". Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of the EGS1 and EGS0 bits. FUJITSU MICROELECTRONICS LIMITED 517 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Status Control Register (BTxSTC) Figure 22.8-3 Status Control Register (BTxSTC) R/W - bit7 bit6 bit5 bit4 bit3 - TGIE DTIE UDIE - R/W R/W R/W R/W R/W : Readable/writable : Undefined bit bit2 bit1 bit0 TGIR DTIR UDIR R/W R/W R/W Initial value: 00000000B (At reset) UDIR Underflow interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected DTIR Duty match interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected TGIR Trigger interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected UDIE Underflow interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests DTIE Duty match interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests TGIE Trigger interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests : Initial value 518 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-3 Status Control Register (BTxSTC) Bit name bit7 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit6 TGIE: Trigger interrupt request enable bit • • Controls bit2: TGIR interrupt requests. Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests generates an interrupt request to the CPU. bit5 DTIE: Duty match interrupt request enable bit • • Controls bit1: DTIR interrupt requests. Setting the DTIR bit (bit1) with the DTIE bit enabling duty match interrupt requests generates an interrupt request to the CPU. bit4 UDIE: Underflow interrupt request enable bit • • Controls bit0: UDIR interrupt requests. Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt requests generates an interrupt request to the CPU. bit3 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit2 TGIR: Trigger interrupt request bit • The TGIR bit is set to "1" upon detection of a software trigger or trigger input. Writing "0" to the TGIR bit clears it. Writing "1" to the TGIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. DTIR: Duty match interrupt request bit • UDIR: Underflow interrupt request bit • bit1 bit0 CM71-10151-2E Function • • • • • • • • • The DTIR bit is set to "1" when the count value matches the duty cycle setting. Writing "0" to the DTIR bit clears it. Writing "1" to the DTIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. The UDIR bit is set to "1" when a count value underflow occurs from 0000H to FFFFH. Writing "0" to the UDIR bit clears it. Writing "1" to the UDIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. FUJITSU MICROELECTRONICS LIMITED 519 CHAPTER 22 Base Timer 22.8 22.8.1.2 MB91625 Series PWM Period Setting Register (BTxPCSR) The PWM period setting register (BTxPCSR) is a buffered register for setting the PWM period. Transfer to the timer register takes place when the counter is started and when it causes an underflow. ■ Bit Configuration of the PWM Period Setting Register (BTxPCSR) Figure 22.8-4 shows the bit configuration of the PWM period setting register (BTxPCSR). Figure 22.8-4 Bit Configuration of the PWM Period Setting Register (BTxPCSR) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) R/W : Readable/writable X : Undefined value The BTxPCSR register is a buffered register for setting the PWM period. Transfer to the timer register takes place when the counter is started and when it causes an underflow. After writing to the period setting register to initially set or update it, be sure to write to the duty setting register. 520 • Access the BTxPCSR register using 16-bit data. • Set the PWM period using the BTxPCSR register after selecting the PWM function mode using the FMD2, FMD1, and FMD0 bits in the BTxTMCR register. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.1.3 PWM Duty Setting Register (BTxPDUT) The PWM duty setting register (BTxPDUT) is a buffered register for setting the PWM duty cycle. Transfer from the buffer takes place when an underflow occurs. ■ Bit Configuration of the PWM Duty Setting Register (BTxPDUT) Figure 22.8-5 shows the bit configuration of the PWM duty setting register (BTxPDUT). Figure 22.8-5 Bit Configuration of the PWM Duty Setting Register (BTxPDUT) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) R/W : Readable/writable X : Undefined value The BTxPDUT register is a buffered register for setting the PWM duty cycle. Transfer from the buffer takes place when an underflow occurs. If you set the period setting and duty setting registers to the same value, the output level is all "H" in normal polarity or all "L" in inverted polarity. Do not set the BTxPDUT register to a value greater than the value of the BTxPSCR register, or PWM output will be undefined. • Access the BTxPDUT register using 16-bit data. • Set the PWM duty cycle using the BTxPDUT register after selecting the PWM function mode using the FMD2, FMD1, and FMD0 bits in the BTxTMCR register. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 521 CHAPTER 22 Base Timer 22.8 22.8.1.4 MB91625 Series Timer Register (BTxTMR) The timer register (BTxTMR) allows the value of the 16-bit down counter to be read from. ■ Bit Configuration of the Timer Register (BTxTMR) Figure 22.8-6 shows the bit configuration of the PWM timer register (BTxTMR). Figure 22.8-6 Bit Configuration of the Timer Register (BTxTMR) bit15 bit13 bit12 bit11 bit10 bit9 bit8 R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R bit14 R R R R R R R Initial value: 00000000B (At reset) Initial value: 00000000B (At reset) : Read only The BTxTMR register allows the value of the 16-bit down counter to be read from. <Note> Access the BTxTMR register using 16-bit data. 522 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.1.5 16-bit PWM Timer Operation In PWM timer mode, a waveform having a specified period can be output either in single shots or continuously after detection of a trigger. The period of output pulses can be controlled by changing the BTxPCSR value. The duty ratio can be controlled by changing the BTxPDUT value. After writing data to the BTxPCSR register, be sure to write to the BTxPDUT register as well. ■ Continuous Operation ● When restarting is disabled (RTGEN = 0) Figure 22.8-7 PWM Operation Timing Chart (Restarting Disabled) Rising edge detected Trigger is ignored. Trigger m n O PWM output waveform (1) (2) (1) = T(n+1) ms (2) = T(m+1) ms T m n : Count clock cycle : BTxPCSR value : BTxPDUT value ● When restarting is enabled (RTGEN = 1) Figure 22.8-8 PWM Operation Timing Chart (Restarting Enabled) Rising edge detected Restarted by trigger Trigger m n O PWM output waveform (1) (2) (1) = T(n+1) ms (2) = T(m+1) ms CM71-10151-2E T m n : Count clock cycle : BTxPCSR value : BTxPDUT value FUJITSU MICROELECTRONICS LIMITED 523 CHAPTER 22 Base Timer 22.8 22.8.1.6 MB91625 Series One-shot Operation In one-shot operation mode, single pulses with an arbitrary width can be output by trigger. When restarting is enabled, the counter is reloaded upon detection of a trigger edge during operation. ■ One-shot Operation ● When restarting is disabled (RTGEN = 0) Figure 22.8-9 One-shot Operation Timing Chart (Trigger Restarting Disabled) Rising edge detected Trigger is ignored. Trigger m n O PWM output waveform (1) (2) (1) = T(n+1) ms (2) = T(m+1) ms T m n : Count clock cycle : BTxPCSR value : BTxPDUT value ● When restarting is enabled (RTGEN = 1) Figure 22.8-10 One-shot Operation Timing Chart (Trigger Restarting Enabled) Rising edge detected Restarted by trigger Trigger m n O PWM output waveform (1) (2) (1) = T(n+1) ms (2) = T(m+1) ms 524 T m n : Count clock cycle : BTxPCSR value : BTxPDUT value FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.1.7 Interrupt Factors and Timing Chart This section provides the interrupt factors and timing chart. ■ Interrupt Factors and Timing Chart (PWM Output: Normal Polarity) A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (PCLK) cycle) until the counter value is loaded after the input of the trigger. Figure 22.8-11 shows the interrupt factors and timing chart, assuming "period setting" = 3 and "duty value" = 1. Figure 22.8-11 PWM Timer Interrupt Factors and Timing Chart Trigger 2T to 3T (external trigger) Load Count clock Count value XXXXH 0003H 0002H 0001H 0000H 0003H 0002H PWM output waveform Interrupt Start edge TGIR CM71-10151-2E Duty match DTIR Underflow UDIR FUJITSU MICROELECTRONICS LIMITED 525 CHAPTER 22 Base Timer 22.8 22.8.1.8 MB91625 Series Output Waveforms This section illustrates PWM output. ■ PWM Output at All "L" or All "H" Level Figure 22.8-12 and Figure 22.8-13 illustrate how to provide PWM output at all "L" and all "H" levels, respectively. Figure 22.8-12 Example of PWM Output at All "L" Level Underflow interrupt Duty value 0002H 0001H 0000H XXXXH PWM output waveform Decrease the duty value. Use the underflow interrupt to set PMSK to "1". The output waveform has all "L" level from the current period. Figure 22.8-13 Example of PWM Output at All "H" Level Duty match interrupt PWM output waveform Increase the duty value. Use the duty match interrupt to set the duty value to the same as the period setting, and the output waveform has all "H" level in the next period. 526 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.2 PPG Function The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the PPG timer. • Timer Control Register (BTxTMCR) for PPG Timer • "L"-width Setting Reload Register (BTxPRLL) • "H"-width Setting Reload Register (BTxPRLH) • Timer Register (BTxTMR) • 16-bit PPG Timer Operation • Continuous Operation • One-shot Operation • Interrupt Factors and Timing Chart CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 527 CHAPTER 22 Base Timer 22.8 22.8.2.1 MB91625 Series Timer Control Register (BTxTMCR) for PPG Timer The timer control register (BTxTMCR) controls the PPG timer. Keep in mind that the register contains bits which cannot be updated with the PPG timer operating. ■ Timer Control Register (BTxTMCR Upper Byte) Figure 22.8-14 Timer Control Register (BTxTMCR Upper Byte) bit15 - bit14 bit13 bit12 bit11 bit10 R/W R/W R/W R/W R/W R/W 0 0 Disable trigger input 0 1 Rising edge 1 0 Falling edge 1 1 Both edges Pulse output mask bit 0 Normal output 1 Fixed to "L"-level output RTGEN Restart enable bit 0 Disables restarting 1 Enable restarting CKS2 CKS1 CKS0 : Readable/writable : Initial value R/W Initial value: -0000000B (At reset) Trigger input edge select bits PMSK 528 bit8 CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0 EGS1 EGS0 R/W bit9 Count clock select bits 0 0 0 φ 0 0 1 φ/4 0 1 0 φ/16 0 1 1 φ/128 1 0 0 φ/256 1 0 1 External clock (rising edge event) 1 1 0 External clock (falling edge event) 1 1 1 External clock (both edge event) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-4 Timer Control Register (BTxTMCR Upper Byte) Bit name CM71-10151-2E Function bit15 Undefined bit • • The read value of this bit is undefined. Write to this bit takes no effect. bit14 to bit12 CKS2, CKS1, CKS0: Count clock select bits • • Select the count clock for the 16-bit down counter. The count clock promptly reflects any changes made to its setting. CKS2 to CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. bit11 RTGEN: Restart enable bit This bit enables restarting with a software trigger or trigger input. bit10 PMSK: Pulse output mask bit • • • bit9, bit8 EGS1, EGS0: Trigger input edge select bits • Controls the PPG output waveform level. When this bit is "0", the PPG waveform is output as it is. When the bit is "1", the PPG output is masked to the "L" level irrespective of the "H" and "L" width settings. Note: Setting the PMSK bit to "1" with the OSEL bit (bit3) set for inverted output masks the PPG output to the "H" level. Select the effective edge of the input waveform as an external trigger to set the trigger condition. • When these bits are set to the initial value or "00B", no effective edge of the input waveform is selected, preventing the timer from being triggered by the external waveform. Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of EGS1 and EGS0. • EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. FUJITSU MICROELECTRONICS LIMITED 529 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Timer Control Register (BTxTMCR Lower Byte) Figure 22.8-15 Timer Control Register (BTxTMCR Lower Byte) bit7 R/W bit6 bit5 bit4 bit3 bit2 bit1 FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG R/W R/W R/W R/W R/W R/W Software trigger bit 0 Disable software trigger 1 Start with software trigger CTEN Counting enable bit 0 Disables counting 1 Enables counting MDSE Mode select bit 0 Continuous operation 1 One-shot operation OSEL Output polarity select bit 0 Normal polarity 1 Inverted polarity 0 : Readable/writable : Undefined bit R/W Initial value: 00000000B (At reset) STRG FMD2 FMD1 FMD0 R/W - bit0 0 Timer function select bits 0 Reset mode 0 0 1 Select PWM function mode 0 1 0 Select PPG function mode 0 1 1 Select reload timer function mode 1 0 0 Select PWC function mode 1 0 1 1 1 0 1 1 1 Setting not allowed : Initial value 530 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-5 Timer Control Register (BTxTMCR Lower Byte) Bit name bit7 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit6 to bit4 FMD2, FMD1, FMD0: Timer function select bits • • These bits select the timer function mode. Setting the FMD2, FMD1, and FMD0 bits to "010B" selects the PPG function mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. bit3 CM71-10151-2E Function OSEL: Output polarity select bit • Selects the polarity of PPG output. Polarity After reset Normal "L" output Inverted "H" output End of "L"width counting End of "H"width counting bit2 MDSE: Mode select bit • • Selects continuous pulse output or one-shot pulse output. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. bit1 CTEN: Counting enable bit • • This bit enables the down counter. Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the counter. bit0 STRG: Software trigger bit • Writing "1" to the STRG bit with the CTEN bit containing "1" generates a software trigger. Note: Writing "1" to the CTEN and STRG bits at the same time also generates a software trigger. • The value read from the STRG bit is always "0". Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of the EGS1 and EGS0 bits. FUJITSU MICROELECTRONICS LIMITED 531 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Status Control Register (BTxSTC) Figure 22.8-16 Status Control Register (BTxSTC) R/W - 532 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - TGIE - UDIE - TGIR - UDIR R/W R/W R/W R/W R/W R/W R/W R/W Initial value: 00000000B (At reset) UDIR Underflow interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected TGIR Trigger interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected UDIE Underflow interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests TGIE Trigger interrupt request enable bit : Readable/writable : Undefined bit 0 Disables interrupt requests : Initial value 1 Enables interrupt requests FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-6 Status Control Register (BTxSTC) Bit name Function bit7 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit6 TGIE: Trigger interrupt request enable bit • • Controls bit2: TGIR interrupt requests. Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests generates an interrupt request to the CPU. bit5 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit4 UDIE: Underflow interrupt request enable bit • • Controls bit0: UDIR interrupt requests. Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt requests generates an interrupt request to the CPU. bit3 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit2 TGIR: Trigger interrupt request bit • The TGIR bit is set to "1" upon detection of a software trigger or trigger input. Writing "0" to the TGIR bit clears it. Writing "1" to the TGIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. bit1 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit0 UDIR: Underflow interrupt request bit • The UDIR bit is set to "1" when a count value underflow occurs from 0000H to FFFFH during counting from the value set as the "H" width. Writing "0" to the UDIR bit clears it. Writing "1" to the UDIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. • • • • • • CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 533 CHAPTER 22 Base Timer 22.8 22.8.2.2 MB91625 Series "L"-width Setting Reload Register (BTxPRLL) The "L"-width setting reload register (BTxPRLL) is used to set the "L" width of PPG output waveforms. Transfer to the timer register takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width counting. ■ Bit Configuration of the "L"-width Setting Reload Register (BTxPRLL) Figure 22.8-17 shows the bit configuration of the "L"-width setting reload register (BTxPRLL). Figure 22.8-17 Bit Configuration of the "L"-width Setting Reload Register (BTxPRLL) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) R/W : Readable/writable X : Undefined value The BTxPRLL register is used to set the "L" width of PPG output waveforms. Transfer to the timer register takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width counting. 534 • Access the BTxPRLL register using 16-bit data. • Set the "L" width using the BTxPRLL register after selecting the PPG function mode using the FMD2, FMD1, and FMD0 bits in the BTxTMCR register. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.2.3 "H"-width Setting Reload Register (BTxPRLH) The "H"-width setting reload register (BTxPRLH) is a buffered register for setting the "H" width of PPG output waveforms. Transfer from the BTxPRLH register to the buffer register takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width counting. Transfer from the buffer register to the timer register takes place when an underflow occurs at the end of "L" width counting. ■ Bit Configuration of the "H"-width Setting Reload Register (BTxPRLH) Figure 22.8-18 shows the bit configuration of the "H"-width setting reload register (BTxPRLH). Figure 22.8-18 Bit Configuration of the "H"-width Setting Reload Register (BTxPRLH) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) R/W : Readable/writable X : Undefined value The BTxPRLH register is used to set the "H" width of PPG output waveforms. Transfer from the BTxPRLH register to the buffer register takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width counting. Transfer from the buffer register to the timer register takes place when an underflow occurs at the end of "L" width counting. • Access the BTxPRLH register using 16-bit data. • Set the "H" width using the BTxPRLH register after selecting the PPG function mode using the FMD2, FMD1, and FMD0 bits in the BTxTMCR register. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 535 CHAPTER 22 Base Timer 22.8 22.8.2.4 MB91625 Series Timer Register (BTxTMR) The timer register (BTxTMR) allows the value of the 16-bit down counter to be read from. ■ Bit Configuration of the Timer Register (BTxTMR) Figure 22.8-19 shows the bit configuration of the PPG timer register (BTxTMR). Figure 22.8-19 Bit Configuration of the Timer Register (BTxTMR) bit15 bit13 bit12 bit11 bit10 bit9 bit8 R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R bit14 R R R R R R R Initial value: 00000000B (At reset) Initial value: 00000000B (At reset) : Read only The BTxTMR register allows the value of the 16-bit down counter to be read from. <Note> Access the BTxTMR register using 16-bit data. 536 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.2.5 16-bit PPG Timer Operation In PPG timer mode, an arbitrary output pulse can be controlled by setting its "L" and "H" widths in their respective reload registers. ■ Principles of Operation The PPG timer has two 16-bit reload registers for setting the "L" and "H" widths respectively and one "H" width setting buffer (BTxPRLL, BTxPRLH, BTxPRLHB). In response to the start trigger, the 16-bit down counter loads the BTxPRLL value and the BTxPRLH value is transferred to the BTxPRLHB buffer at the same time. The counter is decremented every count clock with the PPG output at the "L" level. When an underflow is detected, the counter reloads the BTxPRLHB value and is decremented with the PPG output waveform inverted. When an underflow is detected again, the PPG output waveform is inverted, the counter reloads the BTxPRLL set value, and the BTxPRLH set value is transferred to the BTxPRLHB buffer. Through these steps, the output waveform becomes the pulse output with the "L" and "H" widths corresponding to their respective reload register values. ■ Reload Register Write Timing Data is written to the BTxPRLL and BTxPRLH reload registers upon detection of a start trigger and between when the underflow interrupt request bit (UDIR) is set and when the next period begins. The data set then becomes the setting for the next period. The BTxPRLL and BTxPRLH settings are automatically transferred to the BTxTMR and BTxPRLHB, respectively, upon detection of a start trigger and when an underflow occurs at the end of "H" width counting. The data transferred to the BTxPRLHB is automatically reloaded to the BTxTMR when an underflow occurs at the end of "L" width counting. Rising edge detected Trigger IRQ1 (TGIR source) IRQ0 (UDIR source) Set the L width and H width of the next cycle to registers. BTnPRLL L0 L1 L2 L3 BTnPRLH H0 H1 H2 H3 BTnPRLHB xxxx BTnTMR xxxx H1 H0 L0 to 0000 H2 H0 to 0000 L1 to 0000 H1 to 0000 H0 L1 H1 L2 to 0000 H2 to 0000 PPG output waveforms L0 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED L2 H2 537 CHAPTER 22 Base Timer 22.8 22.8.2.6 MB91625 Series Continuous Operation In continuous operation mode, an arbitrary pulse can be output continuously by updating the "L" and "H" widths at the set timing of each interrupt. When restarting is enabled, the counter is reloaded upon detection of a trigger edge during operation. ■ Continuous Operation ● When restarting is disabled (RTGEN = 0) Figure 22.8-20 PPG Operation Timing Chart (Restarting Disabled) Rising edge detected Trigger is ignored. Trigger m n O PPG output waveform (1) (2) Interrupt Start edge TGIR Underflow UDIR Underflow UDIR (1) = T(m+1) ms (2) = T(n+1) ms T : Count clock cycle m : BTxPRLL value n : BTxPRLH value ● When restarting is enabled (RTGEN = 1) Figure 22.8-21 PPG Operation Timing Chart (Restarting Enabled) Rising edge detected Restarted by trigger Trigger m n O PPG output waveform (2) (1) = T(m+1) ms (2) = T(n+1) ms 538 (1) T : Count clock cycle m : BTxPRLL value n : BTxPRLH value FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.2.7 One-shot Operation In one-shot operation mode, single pulses with an arbitrary width can be output by trigger. When restarting is enabled, the counter is reloaded upon detection of a trigger edge during operation. ■ One-shot Operation ● When restarting is disabled (RTGEN = 0) Figure 22.8-22 One-shot Operation Timing Chart (Trigger Restarting Disabled) Rising edge detected Trigger is ignored. Trigger m n O PPG output waveform (1) (2) (1) = T(m+1) ms (2) = T(n+1) ms T : Count clock cycle m : BTxPRLL value n : BTxPRLH value ● When restarting is enabled (RTGEN = 1) Figure 22.8-23 One-shot Operation Timing Chart (Trigger Restarting Enabled) Rising edge detected Restarted by trigger Trigger m n O PPG output waveform (1) (2) (1) = T(m+1) ms (2) = T(n+1) ms CM71-10151-2E T : Count clock cycle m : BTxPRLL value n : BTxPRLH value FUJITSU MICROELECTRONICS LIMITED 539 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Relationship between Reload Value and Pulse Width The output pulse width is obtained by adding 1 to the value written in the 16-bit reload register and multiplying the result by the count clock cycle. When the reload register value is 0000H, therefore, the output has a pulse width of one count clock cycle. When the reload register value is FFFFH, the output has a pulse width of 65536 count clock cycles. The pulse width is calculated from the following equation. 540 PL = T × (L+1) PL : "L" pulse width PH = T × (H+1) PH : "H" pulse width T : Count clock cycle L : BTxPRLL value H : BTxPRLH value FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.2.8 Interrupt Factors and Timing Chart This section provides the interrupt factors and timing chart. ■ Interrupt Factors and Timing Chart (PPG Output: Normal Polarity) A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (PCLK) cycle) until the counter value is loaded after the trigger is generated. Interrupt factors are set when the PPG start trigger is detected and when an underflow is detected during "H" level output. Figure 22.8-24 shows the interrupt factors and timing chart, assuming "L" width setting = 1 and "H" width setting = 1. Figure 22.8-24 PPG Timer Interrupt Factors and Timing Chart Trigger 2T to 3T (external trigger) Load Count clock Count value XXXXH 0001H 0000H 0001H 0000H 0001H 0000H PPG output waveform Interrupt Start edge TGIR CM71-10151-2E Underflow UDIR FUJITSU MICROELECTRONICS LIMITED 541 CHAPTER 22 Base Timer 22.8 22.8.3 MB91625 Series Reload Timer Function The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the reload timer. 542 • Timer Control Register (BTxTMCR) for Reload Timer • Period Setting Register (BTxPCSR) • Timer Register (BTxTMR) • 16-bit Reload Timer Operation FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.3.1 Timer Control Register (BTxTMCR) for Reload Timer The timer control register (BTxTMCR) controls the reload timer. ■ Timer Control Register (BTxTMCR Upper Byte) Figure 22.8-25 Timer Control Register (BTxTMCR Upper Byte) bit15 - bit14 bit13 bit12 CKS2 CKS1 CKS0 R/W R/W R/W bit11 bit10 - - - - bit9 bit8 EGS1 EGS0 R/W R/W EGS1 EGS0 Trigger edge select bits 0 0 Disable trigger input 0 1 External trigger (rising edge) 1 0 External trigger (falling edge) 1 1 External trigger (both edges) CKS2 CKS1 CKS0 R/W - Initial value: 00000000B (At reset) Count clock select bits φ 0 0 0 0 0 1 φ/4 0 1 0 φ/16 0 1 1 φ/128 1 0 0 φ/256 : Readable/writable : Undefined bit 1 0 1 External clock (rising edge event) 1 1 0 External clock (falling edge event) : Initial value 1 1 1 External clock (both edge event) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 543 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-7 Timer Control Register (BTxTMCR Upper Byte) Bit name 544 Function bit15 Undefined bit • • The read value of this bit is undefined. Write to this bit takes no effect. bit14 to bit12 CKS2, CKS1, CKS0: Count clock select bits • • Select the count clock for the 16-bit down counter. The count clock promptly reflects any changes made to its setting. CKS2 to CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. bit11, bit10 Undefined bits • • The value read is "0" When writing to these bits, write "0". bit9, bit8 EGS1, EGS0: Trigger edge select bits • Select the effective edge of the input waveform as an external trigger to set the trigger condition. • When these bits are set to the initial value or "00B", no effective edge of the input waveform is selected, preventing the timer from being triggered by the external waveform. Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of EGS1 and EGS0. • EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Timer Control Register (BTxTMCR Lower Byte) Figure 22.8-26 Timer Control Register (BTxTMCR Lower Byte) bit7 T32 R/W bit6 bit5 bit4 bit3 bit2 bit1 bit0 FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG R/W R/W R/W R/W R/W R/W R/W STRG Software trigger bit 0 Disable software trigger 1 Start with software trigger CTEN Counting enable bit 0 Disables counting 1 Enables counting MDSE Mode select bit 0 Reload mode 1 One-shot mode OSEL Output polarity select bit 0 Normal polarity 1 Inverted polarity FMD2 FMD1 FMD0 R/W : Readable/writable : Initial value CM71-10151-2E Initial value: 00000000B (At reset) Timer function select bits 0 0 0 Reset mode 0 0 1 Select PWM function mode 0 1 0 Select PPG function mode 0 1 1 Select reload timer function mode 1 0 0 Select PWC function mode 1 0 1 1 1 0 1 1 1 Setting not allowed T32 32-bit timer select bit 0 16-bit timer mode 1 32-bit timer mode FUJITSU MICROELECTRONICS LIMITED 545 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-8 Timer Control Register (BTxTMCR Lower Byte) Bit name bit7 T32: 32-bit timer select bit Function • • • bit6 to bit4 bit3 bit2 FMD2, FMD1, FMD0: Timer function select bits OSEL: Output polarity select bit MDSE: Mode select bit • • • • • • • • 546 bit1 CTEN: Counting enable bit • • bit0 STRG: Software trigger bit • This bit selects the 32-bit timer mode. When the FMD2, FMD1, and FMD0 bits contain "011B" to select the reload timer, setting the T32 bit to "1" places the timer in 32-bit timer mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. → See Section "22.5 32-bit Mode Operations". These bits select the timer function mode. Setting the FMD2, FMD1, and FMD0 bits to "011B" selects the reload timer function mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. Selects the timer output at normal level or inverted level. The output waveform is generated as follows depending on the combination with the MDSE bit (bit2): MDSE OSEL Output Waveforms 0 0 Toggle output of "L" at the count start 0 1 Toggle output of "H" at the count start 1 0 Rectangular wave of "H" during count 1 1 Rectangular wave of "L" during count Setting the MDSE bit to "0" selects reload mode, in which the counter loads the reload register value to continue counting the moment a count value underflow occurs from 0000H to FFFFH. Setting the MDSE bit to "1" selects one-shot mode, in which the counter stops operation the moment a count value underflow occurs from 0000H to FFFFH. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. This bit enables the down counter. Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the counter. Writing "1" to the STRG bit with the CTEN bit containing "1" generates a software trigger. Note: Writing "1" to the CTEN and STRG bits at the same time also generates a software trigger. • The value read from the STRG bit is always "0". Note: Writing "1" to the STRG bit enables the software trigger irrespective of the settings of the EGS1 and EGS0 bits. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Status Control Register (BTxSTC) Figure 22.8-27 Status Control Register (BTxSTC) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - TGIE - UDIE - TGIR - UDIR - R/W - R/W - R/W - R/W UDIR R/W - : Readable/writable : Undefined bit : Initial value CM71-10151-2E Initial value: 00000000B (At reset) Underflow interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected TGIR Trigger interrupt request bit 0 Clears interrupt factor 1 Indicates that interrupt factor has been detected UDIE Underflow interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests TGIE Trigger interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests FUJITSU MICROELECTRONICS LIMITED 547 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-9 Status Control Register (BTxSTC) Bit name 548 Function bit7 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit6 TGIE: Trigger interrupt request enable bit • • Controls bit2:TGIR interrupt requests. Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests generates an interrupt request to the CPU. bit5 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit4 UDIE: Underflow interrupt request enable bit • • Controls bit0:UDIR interrupt requests. Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt requests generates an interrupt request to the CPU. bit3 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit2 TGIR: Trigger interrupt request bit • The TGIR bit is set to "1" upon detection of a software trigger or trigger input. Writing "0" to the TGIR bit clears it. Writing "1" to the TGIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. bit1 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit0 UDIR: Underflow interrupt request bit • The UDIR bit is set to "1" when a count value underflow occurs from 0000H to FFFFH. Writing "0" to the UDIR bit clears it. Writing "1" to the UDIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. • • • • • • FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.3.2 Period Setting Register (BTxPCSR) The period setting register (BTxPCSR) holds the initial count value. In 32-bit mode, the register holds the initial count value of the lower 16 bits for the even-numbered channel or the initial count value of the upper 16 bits for the odd-numbered channel. The initial value immediately after a reset is undefined. To access this register, be sure to use a 16-bit data transfer instruction. ■ Bit Configuration of the Period Setting Register (BTxPCSR) Figure 22.8-28 shows the bit configuration of the period setting register (BTxPCSR). Figure 22.8-28 Bit Configuration of the Period Setting Register (BTxPCSR) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) R/W : Readable/writable X : Undefined value The BTxPCSR register is used to set the period. Transfer to the timer register takes place when an underflow occurs. • Access the BTxPCSR register using 16-bit data. • Set the period using the BTxPCSR register after selecting the reload timer function mode using the FMD2, FMD1, and FMD0 bits in the BTxTMCR register. • To write data to the BTxPCSR register in 32-bit mode, access its upper 16-bit data (data for the oddnumbered channel) first and then the lower 16-bit data (data for the even-numbered channel). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 549 CHAPTER 22 Base Timer 22.8 22.8.3.3 MB91625 Series Timer Register (BTxTMR) The timer register (BTxTMR) allows the count value of the timer to be read from. In 32-bit mode, the register holds the count value of the lower 16 bits for the even-numbered channel or the count value for the upper 16 bits for the odd-numbered channel. The initial value is undefined. To read this register, be sure to use a 16-bit data transfer instruction. ■ Bit Configuration of the Timer Register (BTxTMR) Figure 22.8-29 shows the bit configuration of the timer register (BTxTMR). Figure 22.8-29 Bit Configuration of the Timer Register (BTxTMR) bit15 bit13 bit12 bit11 bit10 bit9 bit8 R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R bit14 R R R R R R R Initial value: 00000000B (At reset) Initial value: 00000000B (At reset) : Read only The BTxTMR register allows the value of the 16-bit down counter to be read from. <Notes> 550 • Access the BTxTMR register using 16-bit data. • To read data from the BTxTMR register in 32-bit mode, access its lower 16-bit data (data for the even-numbered channel) first and then the upper 16-bit data (data for the odd-numbered channel). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.3.4 16-bit Reload Timer Operation In reload timer mode, the timer decrements the counter from the value set in the period setting register in synchronization with the count clock, and finishes counting when the count value reaches "0" or continues operation with the period setting loaded automatically until the counter stops being decremented. ■ Counting with the Internal Clock Selected To start counting the moment counting is enabled, write "1" to both of the CTEN and STRG bits in the timer control register. The STRG bit maintains the trigger input always enabled irrespective of the operation mode as long as the timer is active (CNTE = 1). Enable counting and start the timer using a software trigger or external trigger, and the timer loads the period setting register value to the counter to start decrementing the counter. It takes 1T (T: peripheral clock (PCLK) cycle) for data in the period setting register to be loaded into the counter after the counter start trigger is set. Figure 22.8-30 illustrates how the counter is started by the software trigger and operates. Figure 22.8-30 Counting with the Internal Clock Selected Load Count clock Count value XXXXH Reload value -1 -1 CTEN (register) 1T STRG (register) ■ Underflow Operation When the counter value changes from "0000H" to "FFFFH", the transition is detected as an underflow. When the counter counts [period setting register value + 1], therefore, an underflow occurs. When an underflow occurs, the content of the period setting register (BTxPCSR) is loaded into the counter, and the counter continues counting if the MDSE bit in the timer control register (BTxTMCR) is "0". If the MDSE bit is "1", the counter stops operation with the loaded counter value left unchanged. When an underflow occurs, the UDIR bit in the status control register (BTxSTC) is set and an interrupt request occurs if the UDIE bit is "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 551 CHAPTER 22 Base Timer 22.8 MB91625 Series Figure 22.8-31 is a timing chart of underflow operation. Figure 22.8-31 Underflow Operation Timing Chart [MDSE=0] Load Count clock Count value 0000H Reload value -1 -1 Underflow set UDIR [MDSE=1] Load Count clock Count value Reload value 0000H Underflow set UDIR ■ Input Pin Operation The TGIN pin can be used as a trigger input. When the effective edge is input to the TGIN pin, the counter loads the content of the period setting register and starts counting. It takes 2T or 3T (T: peripheral clock (PCLK) cycle) for the counter value to be loaded after the trigger is applied. Figure 22.8-32 illustrates the trigger input operation with the rising edge selected as the effective edge. Figure 22.8-32 Trigger Input Operation TGIN 2T to 3T (External trigger) Load Count clock Count value 0000H Reload value -1 -1 ■ Output Pin Operation The TOUT pin functions as a toggle output to be inverted at each underflow in reload mode and as a pulse output to indicate that counting is in process in one-shot mode. The output polarity can be set by the OSEL bit in the timer control register (BTxTMCR). When the OSEL bit is "0", the initial value of the toggle output is "0" and that of the one-shot pulse output is "1" (indicating that counting is in process). Setting the OSEL bit to "1" inverts the output waveform. 552 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Figure 22.8-33 is a timing chart of output pin operation. Figure 22.8-33 Output Pin Operation Timing Chart [MDSE=0, OSEL=0] CTEN Inverted with OSEL = 1 TOUT Trigger Underflow [MDSE=1, OSEL=0] CTEN Inverted with OSEL = 1 TOUT Trigger Underflow Waiting fro trigger start CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 553 CHAPTER 22 Base Timer 22.8 22.8.4 MB91625 Series PWC Function The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the PWC timer. 554 • Timer Control Register (BTxTMCR) for PWC Timer • Data Buffer Register (BTxDTBF) • PWC Operation FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.4.1 Timer Control Register (BTxTMCR) for PWC Timer The timer control register (BTxTMCR) controls the PWC timer. ■ Timer Control Register (BTxTMCR Upper Byte) Figure 22.8-34 Timer Control Register (BTxTMCR Upper Byte) bit15 R/W bit14 bit13 bit12 CKS2 CKS1 CKS0 R/W R/W R/W bit11 R/W bit10 bit9 bit8 EGS2 EGS1 EGS0 R/W R/W R/W EGS2 EGS1 EGS0 0 0 : Readable/writable : Undefined bit : Initial value CM71-10151-2E Measurement edge select bits 0 Measure "H" pulse width (↑ to ↓) 0 0 1 Measure period between rising edges (↑ to ↑) 0 1 0 Measure period between falling edges (↓ to ↓) 0 1 1 Measure pulse widths between all edges (↑ or ↓ to ↓ or ↑) 1 0 0 Measure "L" pulse width (↓ to ↑) 1 0 1 1 1 0 1 1 1 CKS2 CKS1 CKS0 R/W - Initial value: 00000000B (At reset) Setting not allowed Count clock select bits 0 0 0 φ 0 0 1 φ/4 0 1 0 φ/16 0 1 1 φ/128 1 0 0 φ/256 1 0 1 Setting not allowed 1 1 0 1 1 1 FUJITSU MICROELECTRONICS LIMITED 555 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-10 Timer Control Register (BTxTMCR Upper Byte) Bit name 556 Function bit15 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit14 to bit12 CKS2, CKS1, CKS0: Count clock select bits • • Select the count clock for the 16-bit up counter. The count clock promptly reflects any changes made to its setting. CKS2 to CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. bit11 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit10 to bit8 EGS2, EGS1, EGS0: Measurement edge select bits • • Set the measurement edge condition. EGS2, EGS1, and EGS0 must be updated while counting is stopped (CTEN = 0). Note, however, that you can change their setting at the same time as writing "1" to the CTEN bit. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Timer Control Register (BTxTMCR Lower Byte) Figure 22.8-35 Timer Control Register (BTxTMCR Lower Byte) bit7 T32 R/W bit6 bit5 bit4 FMD2 FMD1 FMD0 R/W R/W R/W bit3 R/W bit2 bit1 MDSE CTEN R/W R/W bit0 Initial value: 00000000B (At reset) R/W CTEN Counting enable bit 0 Halt 1 Enables operation MDSE Mode select bit 0 Continuous measurement mode 1 One-shot measurement mode FMD2 FMD1 FMD0 Timer function mode select bits R/W - : Readable/writable : Undefined bit 0 0 0 Reset mode 0 0 1 PWM function mode 0 1 0 PPG function mode 0 1 1 Reload timer function mode 1 0 0 PWC function mode 1 0 1 1 1 0 1 1 1 Setting not allowed T32 32-bit timer select bit 0 16-bit timer mode 1 32-bit timer mode : Initial value CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 557 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-11 Timer Control Register (BTxTMCR Lower Byte) Bit name bit7 T32: 32-bit timer select bit Function • • • bit6 to bit4 FMD2, FMD1, FMD0: Timer function mode select bits • • • These bits select the timer function mode. Setting the FMD2, FMD1, and FMD0 bits to "100B" selects the PWC timer function mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. bit3 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit2 MDSE: Mode select bit • Selects measurement mode as follows. bit1 CTEN: Counting enable bit bit0 Undefined bit MDSE Mode Operation 0 Continuous measurement Continuous measurement: buffer register enabled 1 One-shot measurement Halts after each measurement • The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. • • This bit enables the starting or restarting of the up counter. Writing "1" to this bit with the counter enabled for operation (CTEN bit = 1) causes a restart, resulting in the counter cleared and waiting for the measurement start edge. Writing "0" to the bit with the counter enabled for operation (CTEN bit = 1 stops the counter. • 558 This bit selects the 32-bit timer mode. When the FMD2, FMD1, and FMD0 bits contain "100B" to select the PWC timer, setting the T32 bit to "1" places the timer in 32-bit PWC mode. The setting must be changed with the timer stopped (CTEN = 0). Note, however, that you can change the setting at the same time as writing "1" to the CTEN bit. → See Section "22.5 32-bit Mode Operations". • • The value read is "0" When writing to this bit, write "0". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Status Control Register (BTxSTC) Figure 22.8-36 Status Control Register (BTxSTC) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ERR EDIE - OVIE - EDIR - OVIR R R/W R/W R/W R/W R R/W R/W OVIR Initial value: 00000000B (At reset) Overflow interrupt request bit 0 Clears interrupt request 1 Indicates that interrupt factor has been detected EDIR Measurement end interrupt request bit 0 Reads measurement result (BTxDTBF) 1 Indicates that interrupt factor has been detected OVIE Overflow interrupt request enable bit 0 Disables interrupt requests 1 Enables interrupt requests EDIE Measurement end interrupt request enable bit R/W R - : Readable/writable : Read only : Undefined bit 0 Disables interrupt requests 1 Enables interrupt requests ERR Error flag bit 0 Normal state 1 Unread measurement result has been overwritten with next measurement result : Initial value CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 559 CHAPTER 22 Base Timer 22.8 MB91625 Series Table 22.8-12 Status Control Register (BTxSTC) Bit name bit7 ERR: Error flag bit Function • • • • bit6 EDIE: Measurement end interrupt request enable bit • • Controls bit2: EDIR interrupt requests. Setting the EDIR bit (bit2) with the EDIE bit enabling measurement end interrupt requests generates an interrupt request to the CPU. bit5 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit4 OVIE: Overflow interrupt request enable bit • • Controls bit0: OVIR interrupt requests. Setting the OVIR bit (bit0) with the OVIE bit enabling overflow interrupt requests generates an interrupt request to the CPU. bit3 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit2 EDIR: Measurement end interrupt request bit • Indicates that measurement has been completed. The flag is set to "1" upon completion. The EDIR bit is cleared by reading the measurement result (BTxDTBF). The EDIR bit can only be read; an attempt to write to it has no effect on the bit value. • • 560 This flag indicates that the next measurement has been completed before reading the current measurement result from the BTxDTBF register in continuous measurement mode. In this case, the BTxDTBF register is updated with the new measurement result, discarding the preceding measurement result. Measurement continues irrespective of the ERR bit value. The ERR bit can only be read; an attempt to write to it has no effect on the bit value. The ERR bit is cleared by reading the measurement result (BTxDTBF). bit1 Undefined bit • • The value read is "0" When writing to this bit, write "0". bit0 OVIR: Overflow interrupt request bit • The flag is set to "1" when a count value overflow occurs from FFFFH to 0000H. Writing "0" to the OVIR bit clears it. Writing "1" to the OVIR bit has no effect on the bit value. When read by a read modify write (RMW) instruction, the bit always returns "1" irrespective of the current bit value. • • • FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series 22.8.4.2 Data Buffer Register (BTxDTBF) The data buffer register (BTxDTBF) allows the measured value or count value of the PWC timer to be read from. In 32-bit mode, the register holds the value of the lower 16 bits for the even-numbered channel or the value of the upper 16 bits for the odd-numbered channel. To read this register, be sure to use a 16-bit data transfer instruction. ■ Bit Configuration of the Data Buffer Register (BTxDTBF) Figure 22.8-37 shows the bit configuration of the data buffer register (BTxDTBF). Figure 22.8-37 Bit Configuration of the Data Buffer Register (BTxDTBF) bit15 bit13 bit12 bit11 bit10 bit9 bit8 R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R bit14 R R R R R R R Initial value: XXXXXXXXB (At reset) Initial value: XXXXXXXXB (At reset) : Read only • The BTxDTBF register can only be read in both of the continuous and one-shot measurement modes. An attempt to write to the register makes no change to the register value. • In continuous measurement mode (BTxTMCR: bit3 MDSE = 1), the BTxDTBF register serves as a buffer register holding the preceding measurement result. • In one-shot measurement mode (BTxTMCR: bit3 MDSE = 0), the BTxDTBF register directly accesses the up counter. Even during counting, the count value can be read from this register. When the measurement is completed, the register preserved the measurement result as it is. • Access the BTxDTBF register using 16-bit data. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 561 CHAPTER 22 Base Timer 22.8 22.8.4.3 MB91625 Series PWC Operation The PWC timer has a pulse width measurement feature, capable of selecting the count clock from among five types and measuring the time between arbitrary events of the input pulse and their cycle. The following outlines the basic functions and operations of the pulse width measurement feature. ■ Pulse Width Measurement Feature When started, the timer clears the counter to "0000H" but does not perform counting until the pre-set measurement start edge is input. Upon detection of the measurement start edge, the timer increments the counter from "0001H". Upon detection of the measurement end edge, the timer stops the counter. The timer saves the count value between the two events as the pulse width to the register. An interrupt request can be generated upon completion of measurement or when an overflow occurs. After measurement, the timer acts as follows depending on the measurement mode: • In one-shot measurement mode:The timer stops operation. • In continuous measurement mode:The timer transfers the counter value to the buffer register and stops counting until the measurement start edge is input again. Figure 22.8-38 Pulse Width Measurement Operation (One-shot Measurement Mode/"H" Width Measurement) PWC input measured pulse CTEN Count value FFFFH Count cleared 0000H Start triggered Counting stopped (Solid line indicates count values.) Counting 0001H started Time EDIR flag set (Measurement completed) Figure 22.8-39 Pulse Width Measurement Operation (Continuous Measurement Mode/"H" Width Measurement) PWC input measured pulse CTEN (Solid line indicates count values.) Count value FFFFH Overflow Data transfer to BTxDTBF Data transfer to BTxDTBF Count cleared 0000H Start triggered Counting stopped Counting stopped Counting 0001H started Counting 0001H restarted Counting continued Time EDIR flag set (Measurement completed) 562 OVIR flag set FUJITSU MICROELECTRONICS LIMITED EDIR flag set CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Selecting the Count Clock The count clock for the counter can be selected from among five types, depending on the settings of the CKS2 (bit6), CKS1 (bit5), and CKS0 (bit4) in the BTxTMCR registers. The following count clocks can be selected: BTxTMCR Register Internal count clock selected CKS2, CKS1, CKS0 bits 000B Peripheral clock (PCLK) [Initial value] 001B Peripheral clock (PCLK) divided by 4 010B Peripheral clock (PCLK) divided by 16 011B Peripheral clock (PCLK) divided by 128 100B Peripheral clock (PCLK) divided by 256 101B Setting not allowed 110B 111B The initial value immediately after a reset selects the peripheral clock (PCLK). Note: Be sure to select the count clock before starting the counter. ■ Selecting the Operation Mode Operation and measurement modes are selected depending on their settings in the BTxTMCR register. Operation mode setting . . . . . . BTxTMCR bit10 to bit8: EGS2, EGS1. EGS0 (Selecting the measurement edge) Measurement mode setting . . . BTxTMCR bit2: MDSE (Selecting one-shot/continuous measurement) Listed below are the selectable operation modes and their respective bit settings. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 563 CHAPTER 22 Base Timer 22.8 MB91625 Series . Operation mode ↑ to ↓ "H" pulse width measurement ↑ to ↑ measurement of period between rising edges ↓ to ↓ measurement of period between falling edges ↑ or ↓ to ↓ or ↑ measurement between all edges ↓ to ↑ "L" pulse width measurement MDSE EGS2 EGS1 EGS0 Continuous measurement: Buffer enabled 0 0 0 0 One-shot measurement: Buffer disabled 1 0 0 0 Continuous measurement: Buffer enabled 0 0 0 1 One-shot measurement: Buffer disabled 1 0 0 1 Continuous measurement: Buffer enabled 0 0 1 0 One-shot measurement: Buffer disabled 1 0 1 0 Continuous measurement: Buffer enabled 0 0 1 1 One-shot measurement: Buffer disabled 1 0 1 1 Continuous measurement: Buffer enabled 0 1 0 0 One-shot measurement: Buffer disabled 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 Setting not allowed The initial value immediately after a reset selects "H" pulse width/one-shot measurement mode. Be sure to select the operation mode before starting the counter. ■ Starting and Stopping Pulse Width Measurement Each type of measurement can be started, restarted, and aborted by the CTEN bit (bit1) in the BTxTMCR register. You can start/restart pulse width measurement by writing "1" to the CTEN bit. You can abort it by writing "0" to the CTEN bit. 564 CTEN Function 1 Starts/restarts pulse width measurement 0 Aborts pulse width measurement FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Operation after being Started The timer operation after the pulse width measurement mode has been started does not start counting until the measurement start edge is input. Upon detection of the measurement start edge, the 16-bit up counter starts counting from "0001H". ■ Restarting Restarting the timer means starting the timer during operation again while it has already been started (by writing "1" again to the CTEN bit already containing "1"). When restarted, the timer behaves as follows: • If restarted the timer waiting for the measurement start edge: No effect on its operation. • If restarted during measurement:The timer clears the counter to "0000H" and waits for the measurement start edge again. If the restart and measurement end edge detection occur at the same time, the measurement end flag (EDIR) is set. In continuous measurement mode, the measurement result is transferred to the BTxDTBF register. ■ Stopping In one-shot measurement mode, the timer stops counting automatically when the counter causes an overflow or when measurement is completed, requiring no special attention. To stop the timer either in continuous measurement mode or before it stops automatically, you have to abort it. ■ Clearing the Counters and Their Initial Values The 16-bit up counter is cleared to "0000H" when: • a reset occurs • "1" is written to the CTEN bit (bit1) in the BTxTMCR register (including the case of restarting). The 16-bit up counter is initialized to "0001H" when measurement start edge is detected. ■ Details of Pulse Width Measurement Operation ● One-shot measurement and continuous measurement There are two modes of pulse width measurement: one is to perform measurement only once and the other is to perform measurement continuously. Each mode is selected by using the MDSE bit in the BTxTMCR register (see "■ Selecting the Operation Mode" in "22.8.4.3 PWC Operation"). The two modes have the following differences: One-shot measurement mode: When the measurement end edge is input once, the counter stops counting and the measurement end flag (EDIR) in the BTxSTC register is set, finishing the current measurement session. If the counter is restarted at the same time, however, it waits for the measurement start edge. Continuous measurement mode: When the measurement end edge is input, the counter stops counting, the measurement end flag (EDIR) in the BTxSTC register is set, and the counter remains idle until the measurement start edge is input again. Next time the measurement start edge is input, the counter is initialized to "0001H" to start measurement. Upon completion of measurement, the measurement result in the counter is transferred to the BTxDTBF register. Be sure to select or change the measurement mode with the counter stopped. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 565 CHAPTER 22 Base Timer 22.8 MB91625 Series ● Measurement result data The one-shot measurement and continuous measurement modes are different in the handling of measurement results and counter values and the BTxDTBF function. The differences in measurement results between the two modes are as follows: One-shot measurement mode: When the BTxDTBF register is read during operation, the count value being measured can be obtained. When the BTxDTBF register is read after measurement is completed, measurement result data is obtained. Continuous measurement mode: When measurement is completed, the measurement result in the counter is transferred to the BTxDTBF register. When the BTxDTBF register is read, the last measurement result is obtained. During measurement operation, the BTxDTBF register holds the result of preceding measurement. The count value being measured cannot be read. If the current measurement is completed before the preceding measurement result is read in continuous measurement mode, the preceding measurement result is overwritten by the new measurement result. In this case, the error flag (ERR) in the BTxSTC register is set. The error flag (ERR) is cleared automatically when the BTxDTBF register is read. ■ Measurement Mode and Counting Measurement mode can be selected from among five types, depending on what part of the input pulse is measured. The following table summarizes each measurement mode and its target. Measurement mode EGS2, EGS1, EGS0 "H" pulse width measurement 000B Measurement target (W: Pulse width to be measured) W ↑ Start counting W ↓ Stop counting ↓ Stop ↑ Start Measure the width of "H" period. Start counting (measurement) : upon detection of rising edge Stop counting (measurement) : upon detection of falling edge Measurement of period between rising edges 001B W ↑ Start counting W W ↑ Stop counting ↑ Start Measure the period between rising edges. Start counting (measurement) : upon detection of rising edge Stop counting (measurement) : upon detection of rising edge Measurement of period between falling edges 010B W ↓ Start counting W W ↓ Stop counting ↓ Start ↓ Stop ↓ Start Measure the period between falling edges. Start counting (measurement) : upon detection of falling edge Stop counting (measurement) : upon detection of falling edge 566 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 22 Base Timer 22.8 MB91625 Series Measurement mode EGS2, EGS1, EGS0 Measurement of pulse widths between all edges 011B Measurement target (W: Pulse width to be measured) W ↑ Start counting W W ↓ Stop counting ↓ Start ↑ Stop ↑ Start Measure the width between continuously input edges. Start counting (measurement) : upon detection of edge Stop counting (measurement) : upon detection of edge Measurement of "L" pulse width 100B W W ↓ Start counting ↑ Stop counting ↓ Start ↑ Stop Measure the width of the "L" period. Start counting (measurement) : upon detection of falling edge Stop counting (measurement) : upon detection of rising edge In any measurement mode, the counter started for measurement is cleared to "0000H" and remains idle without counting until the measurement start edge is input. When the measurement start edge is input, the counter is incremented every count clock until the measurement end edge is input. When measurement of pulse widths between all edges or period measurement is performed in continuous measurement mode, the end edge becomes the next measurement start edge. ● Pulse width/period calculation method The following equation can be used to calculate the measured pulse width/period from measurement result data obtained from the BTxDTBF register after measurement is completed: TW = n × t [ms] TW : Measured pulse width/period [ms] n : Measurement result data in BTxDTBF t : Count clock cycle [ms] ● Generating interrupt requests Interrupt requests can be generated in two ways. • Interrupt request in response to counter overflow When the counter is incremented to cause an overflow during measurement, the overflow flag (OVIR) is set and generates an interrupt request if overflow interrupt requests have been enabled. • Interrupt request upon completion of measurement When the measurement end edge is detected, the measurement end flag (EDIR) in the BTxSTC register is set and generates an interrupt request if measurement end interrupt requests have been enabled. The measurement end flag (EDIR) is cleared automatically when the measurement result is read from the BTxDTBF register. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 567 CHAPTER 22 Base Timer 22.8 MB91625 Series ■ Pulse Width Measurement Operation Flow Various settings Figure 22.8-40 Pulse Width Measurement Operation Flow Select PWC mode Select count clock Select operation/ measurement modes Clear interrupt flag Enable interrupts Start with CTEN bit Restart Clear counter Continuous measurement mode One-shot measurement mode Measurement start edge detected Measurement start edge detected Start counting Start counting Increment Increment Overflow caused → Set OVIR flag Measurement end edge detected → Set EDIR flag 568 Overflow caused → Set OVIR flag Measurement end edge detected → Set EDIR flag Stop counting Stop counting Transfer count value to BTxDTBF Stop operation FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter This chapter explains the functions and operations of the up/down counter. 23.1 Overview 23.2 Configuration 23.3 Pins 23.4 Registers 23.5 Interrupt 23.6 An Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 569 CHAPTER 23 Up/Down Counter 23.1 MB91625 Series 23.1 Overview The up/down counter counts upward or downward depending on the setting. By using only the lower byte of the 16-bit up/down counter, you can use it as an 8-bit up/down counter. The counter can perform a count in a range of "00H" to "FFH" when used as an 8-bit up/down counter, and "0000H" to "FFFFH" when used as a 16-bit up/down counter. This series microcontroller has 4 built-in channels for the 16-bit up/down counter. However, because only the lower byte can be used as an 8-bit up/down counter, you can use a total of 4 channels for both cases of using it as an 8-bit and a 16-bit counter. ■ Overview • Counter mode: You can select the use of the counter either as an 8-bit up/down counter (8-bit mode), or as a 16-bit up/down counter (16-bit mode). • Operation mode: One of the following three modes (4 types) can be selected. - Timer mode The counter counts downward by synchronizing with the count clock. The internal clock (peripheral clock) which is generated by dividing the peripheral clock (PCLK) by 2 or 8 by the prescaler is used as a count clock. - Up/Down count mode The counter counts upward/counts downward signals that are input from the 2 external signal input pins. You can select which edge to count from among the rising edge, falling edge, or both edges. - Phase difference count mode The counter counts upward/counts downward the phase difference of the signals that are input from the 2 external signal input pins. Phase difference count mode is appropriate for counting for the encoder of the motor and the like. Rotation angle and rotation number can be easily counted with high accuracy by inputting Aphase, B-phase, and Z-phase outputs respectively from the encoder. There are two phase difference count modes: one multiplied by 2-mode and one multiplied by 4mode. The counting method for each of these modes differs from the other. Table 23.1-1 outlines the operation mode of the up/down counter. Table 23.1-1 Operation mode of the up/down counter Operation Mode 570 Count Timing Count Direction Timer mode Internal clock (peripheral clock) Count downward Up/Down count mode External clock Count upward/Count downward Phase difference count mode (Multiplied by 2/Multiplied by 4) Phases of the input signals from the external signal input pins Count upward/Count downward FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.1 MB91625 Series • Reload/compare clear function: One of the following three types can be selected. - Compare clear function Clears the counter at the next up count timing when the specified value matches the counter value. - Reload function If an underflow occurs, the reload value is loaded to continue counting. - Reload compare clear function Compare clear function and reload function can be combined for use. • Count direction: The last count direction (count upward/count downward) can be verified. • Interrupt request: Can be generated in the following cases: CM71-10151-2E - The count direction is inverted - The value of the counter matches the previously set value. - An overflow occurs - An underflow (reload) occurs FUJITSU MICROELECTRONICS LIMITED 571 CHAPTER 23 Up/Down Counter 23.2 MB91625 Series 23.2 Configuration This section shows the configuration of the up/down counter. ■ Block diagram of the up/down counter Figure 23.2-1 is a block diagram of the up/down counter, taking ch.0 as an example. Figure 23.2-1 Block diagram of the up/down counter Peripheral bus 8 bits CGE1 ZIN0 to ZIN3 pins CGE0 To upper byte CGSC M16E RCRL CTUT Reload UCRE RLDE Carry Edge/Level detection UDCC Counter clearing 8 bits CES1 CES0 CMS1 CMS0 UDCRL CMPF UDFF AIN0 to AIN3 pins BIN0 to BIN3 pins OVFF Count clock Count clock selection CSTR UDF1 UDIE UDF0 CDCF Prescaler CITE CLKS UFIE Interrupt output RCRL : Reload compare register lower (RCRL0 to RCRL3) UDCRL : Up-down count register lower (UDCRL0 to UDCRL3) • Reload compare register (RCR0 to RCR3) This register sets the reload value and the compare value of the up/down counter. It is divided into the upper 8 bits and lower 8 bits as follows: The lower bits are used when the counter is used in 8-bit mode. 572 - Reload compare register upper (RCRH0 to RCRH3) - Reload compare register lower (RCRL0 to RCRL3) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.2 MB91625 Series • Up-down count register (UDCR0 to UDCR3) This register operates as a counter of the up/down counter. It is divided into the upper 8 bits and lower 8 bits as follows: The lower bits are used when the counter is used in 8-bit mode. - Up-down count register upper(UDCRH0 to UDCRH3) - Up-down count register lower (UDCRL0 to UDCRL3) • Counter control register (CCR0 to CCR3) • Counter status register (CSR0 to CSR3) This register controls the up/down counter. This register verifies the state of the up/down counter and controls interrupt requests. • Count clock selection circuit This circuit is used to select the count clock for the up/down counter. • Prescaler This is used to select the division rate of the peripheral clock (PCLK) when the up/down counter is used in timer mode. ■ Clock Table 23.2-1 shows the clock used by the up/down counter. Table 23.2-1 Clock used by the up/down counter Clock Name CM71-10151-2E Description Remarks Operation clock Peripheral clock (PCLK) - Count clock Internal clock (peripheral clock) Generated through division of the peripheral clock (PCLK). Counts inputs from the external pins Inputs from AIN0 to AIN3 pins and BIN0 to BIN3 pins FUJITSU MICROELECTRONICS LIMITED 573 CHAPTER 23 Up/Down Counter 23.3 MB91625 Series 23.3 Pins This section explains the pins of the up/down counter. ■ Overview The up/down counter has the following three types of pins. • AIN0 to AIN3 pins These are the external signal input pins of the up/down counter In up/down count mode, signals are counted upward if an effective edge is detected in these pins. In phase difference count mode (multiplied by 2/multiplied by 4), the phase difference between these pins and BIN0 to BIN3 pins is counted. These pins are multiplexed pins. To use them as AIN0 to AIN3 pins of the up/down counter, see "2.4 Setting Method for Pins". • BIN0 to BIN3 pins These are the external signal input pins of the up/down counter In up/down count mode, signals are counted downward if an effective edge is detected in these pins. In phase difference count mode (multiplied by 2/multiplied by 4), the phase difference between these pins and AIN0 to AIN3 pins is counted. These pins are multiplexed pins. To use them as BIN0 to BIN3 pins of the up/down counter, see "2.4 Setting Method for Pins". • ZIN0 to ZIN3 pins These are the external signal input pins of the up/down counter They are used to clear the counter or for gate input. These pins are multiplexed pins. To use them as ZIN0 to ZIN3 pins of the up/down counter, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 23.3-1 outlines the relationship between channels and pins. Table 23.3-1 Relationship between Channels and Pins Channel 574 External Signal Input Pin 0 AIN0 BIN0 ZIN0 1 AIN1 BIN1 ZIN1 2 AIN2 BIN2 ZIN2 3 AIN3 BIN3 ZIN3 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series 23.4 Registers This section explains the configuration and functions of registers used by the up/down counter. ■ List of registers for the up/down counter Table 23.4-1 lists the registers used by the up/down counter. Table 23.4-1 Registers for the up/down counter Channel 0 1 2 3 CM71-10151-2E Abbreviated Register Name Register Name Reference RCRL0 Reload compare register lower 0 23.4.1 RCRH0 Reload compare register upper 0 23.4.1 UDCRL0 Up-down count register lower 0 23.4.2 UDCRH0 Up-down count register upper 0 23.4.2 CCR0 Counter control register 0 23.4.3 CSR0 Counter status register 0 23.4.4 RCRL1 Reload compare register lower 1 23.4.1 RCRH1 Reload compare register upper 1 23.4.1 UDCRL1 Up-down count register lower 1 23.4.2 UDCRH1 Up-down count register upper 1 23.4.2 CCR1 Counter control register 1 23.4.3 CSR1 Counter status register 1 23.4.4 RCRL2 Reload compare register lower 2 23.4.1 RCRH2 Reload compare register upper 2 23.4.1 UDCRL2 Up-down count register lower 2 23.4.2 UDCRH2 Up-down count register upper2 23.4.2 CCR2 Counter control register 2 23.4.3 CSR2 Counter status register 2 23.4.4 RCRL3 Reload compare register lower 3 23.4.1 RCRH3 Reload compare register upper 3 23.4.1 UDCRL3 Up-down count register lower 3 23.4.2 UDCRH3 Up-down count register upper 3 23.4.2 CCR3 Counter control register 3 23.4.3 CSR3 Counter status register 3 23.4.4 FUJITSU MICROELECTRONICS LIMITED 575 CHAPTER 23 Up/Down Counter 23.4 23.4.1 MB91625 Series Reload Compare Register (RCR0 to RCR3) This register sets the reload value and the compare value of the up/down counter. The reload value is a starting value to count downward with, and the compare value is a value to be compared with the counted value when counting upward (i.e., counting up is performed until the counted value reaches the compare value). The reload value and the compare value are the same. This register is divided into upper byte and lower byte as follows: • Reload compare register upper (RCRH0 to RCRH3) • Reload compare register lower (RCRL0 to RCRL3) In 16-bit mode, both the upper and lower byte values are used, while in 8-bit mode, the lower byte value is used. By transferring the value that is written in this register to the up-down count register (UDCR0 to UDCR3), the up/down counter performs the count in a range from "0000H" (for 8-bit mode, "00H") to the value that has been set for this register. 576 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series Figure 23.4-1 shows the bit configuration of the reload compare register (RCR0 to RCR3). Figure 23.4-1 Bit configuration of the reload compare register (RCR0 to RCR3) Reload compare register upper (RCRH0 to RCRH3) bit 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 Attribute W W W W W W W W Initial value 0 0 0 0 0 0 0 0 Reload compare register lower (RCRL0 to RCRL3) bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Attribute W W W W W W W W Initial value 0 0 0 0 0 0 0 0 W: Write only <Notes> • By writing "1" to the CTUT bit of the counter control register (CCR0 to CCR3), the value that has been set for this register can be transferred to the up-down count register (UDCR0 to UDCR). However, note that the CTUT bit of the counter control register (CCR0 to CCR3) should be written while the up-down counter is stopped. • If 16-bit mode is set in M16E bit (M16E = 1) of the counter control register (CCR0 to CCR3), this register must be written in half word. • If 8-bit mode is set in M16E bit (M16E = 0) of the counter control register (CCR0 to CCR3), the reload compare register lower (RCRL0 to RCRL3) must be written in byte notation. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 577 CHAPTER 23 Up/Down Counter 23.4 23.4.2 MB91625 Series Up-Down Count Register (UDCR0 to UDCR3) This register operates as a counter of the up/down counter. Also, the register can be read to verify the counter value. This register is divided into upper byte and lower byte as follows: • Up-down count register upper (UDCRH0 to UDCRH3) • Up-down count register lower (UDCRL0 to UDCRL3) In 8-bit mode, the upper byte value is invalid. Read the value of the up-down count register lower (UDCRL0 to UDCRL3). Figure 23.4-2 shows the bit configuration of the up-down count register (UDCR0 to UDCR3). Figure 23.4-2 Bit configuration of the up-down count register (UDCR0 to UDCR3) Up-down count register upper (UDCRH0 to UDCRH3) bit 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 Up-down count register lower (UDCRL0 to UDCRL3) bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 R: Read only <Notes> • This register is read-only. To set a value to this register, transfer the value of the reload compare register (RCR0 to RCR3) to this register by using the following procedure. 1. Write a value in the reload compare register (RCR0 to RCR3). 2. Write "0" to the CSTR bit of the counter status register (CSR0 to CSR3). 3. Write "1" to the CTUT bit of the counter control register (CCR0 to CCR3). 578 • If 16-bit mode is set in M16E bit (M16E = 1) of the counter control register (CCR0 to CCR3), this register must be read in half word. • If 8-bit mode is set in the M16E bit (M16E = 0) of the counter control register (CCR0 to CCR3), the value of the up-down count register lower (UDCRL0 to UDCRL3) must be read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series 23.4.3 Counter Control Register (CCR0 to CCR3) This register controls operation of the up/down counter. Figure 23.4-3 shows the bit configuration of the counter control register (CCR0 to CCR3). Figure 23.4-3 Bit configuration of the counter control register (CCR0 to CCR3) bit 15 14 13 12 11 10 9 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Reserved CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W R/W R/W R/W R R 0 0 0 0 1 0 0 0 Attribute Initial value bit Attribute Initial value R/W: Read/Write R: Read only [bit15]: M16E (16-bit mode selection bit) This bit selects whether to use the up/down counter in 8-bit or 16-bit mode. Written Value CM71-10151-2E Explanation 0 Uses the up/down counter in 8-bit mode (1 channel). 1 Uses the up/down counter in 16-bit mode (1 channel). FUJITSU MICROELECTRONICS LIMITED 579 CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit14]: CDCF (Count direction change flag bit) This bit indicates that the count direction is inverted from counting downward to counting upward or from counting upward to downward one or more times. If the CFIE bit is set to "1" when this bit is "1", a count direction change interrupt request is generated. CDCF In Case of Reading In Case of Writing 0 The count direction has not been inverted. This bit is cleared to "0". 1 The count direction has been inverted one or more times. Ignored <Notes> • If the counter reset occurs, the count direction is set to counting downward. Therefore, if counting upward is performed immediately after the reset, this bit changes to "1". • If the count direction consecutively changes in a short period of time, the count direction may return to the original one with UDF1 and UDF0 bits of the counter status register (CSR0 to CSR3) unchanged. [bit13]: CFIE (Count direction change interrupt enable bit) This bit sets whether to generate the count direction change interrupt request if the count direction is inverted (CDCF = 1). Written Value Explanation 0 Disables generation of count direction change interrupt requests. 1 Enables generation of count direction change interrupt requests. [bit12]: CLKS (Internal clock division selection bit) This bit sets the division rate of the peripheral clock (PCLK) that is used as a count clock when timer mode is selected. Written Value Explanation 0 Peripheral clock (PCLK) divided by 2 1 Peripheral clock (PCLK) divided by 8 <Note> This bit is enabled only when timer mode is set for the operation mode by setting the CMS1 and CMS0 bits (CMS1, CMS0 = 00). The setting of this bit is ignored if other operation modes are selected. 580 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit11, bit10]: CMS1, CMS0 (Operation mode selection bit) These bits select the operation mode of the up/down counter from among the following options. • Timer mode • Up/Down count mode The counter counts downward by synchronizing with the count clock. The counter counts upward/counts downward signals that are input from the 2 external signal input pins. • Phase difference count mode The counter counts upward/counts downward the phase difference between the 2 external signal input pins. There are two phase difference count modes: one multiplied by 2-mode and one multiplied by 4mode. The counting method for each of these modes differs from the other. CMS1 CMS0 Operation Mode 0 0 Timer mode 0 1 Up/Down count mode 1 0 Phase difference count mode (multiplied by 2) 1 1 Phase difference count mode (multiplied by 4) [bit9, bit8]: CES1, CES0 (Count clock edge selection bit) These bits select the detection edge for the AIN0 to AIN3 pins and BIN0 to BIN3 pins. When up/down count mode is selected, the count operation is performed every time if the edge that has been selected for this bit is detected. CES1 CES0 Detection Edge 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both edges <Note> This bit is enabled only when up/down count mode is set for the operation mode by setting the CMS1 and CMS0 bits (CMS1, CMS0 = 01). The setting of this bit is ignored if other operation modes are selected. [bit7]: Reserved bit CM71-10151-2E In Case of Writing Always write "0" to this (these) bit (bits). In Case of Reading "0" is read. FUJITSU MICROELECTRONICS LIMITED 581 CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit6]: CTUT (Counter write bit) Transfers the values that have been set in the reload compare register (RCR0 to RCR3) to the up-down count register (UDCR0 to UDCR3). CTUT In Case of Writing 0 Ignored 1 Transfers the value. In Case of Reading "0" is read. <Note> The value of the reload compare register (RCR0 to RCR3) is transferred at the time when "1" is written to this bit. Therefore do not change this bit to "1" while the CSTR bit of the counter status register (CSR0 to CSR3) is "1" (the counter is active). [bit5]: UCRE (Counter clear enable bit) This bit controls the clear operation of the counter by compare function. If this bit is enabled, it clears the counter at the next up count timing when the counter value matches the value specified to the reload compare register (RCR0 to RCR3). Written Value Explanation 0 Disables compare clear function. 1 Enables compare clear function. <Note> This bit can control only the compare clear function. It does not affect comparison result match interrupt. The following clear operations cannot be controlled by this bit. • Clear operation by resetting this device • Clear operation by effective edge inputs from the ZIN0 to ZIN3 pins (when CGSC bit = 0) • Clear operation by writing "0" to the UDCC bit (clear by software) [bit4]: RLDE (Reload enable bit) This bit enables/disables use of the reload function. The reload function reloads to the counter the value that has been set in the reload compare register (RCR0 to RCR3) when the counter underflows during count downward, and continues counting. Written Value 582 Explanation 0 Disables use of the reload function. 1 Enables use of the reload function. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit3]: UDCC (Counter clear bit) This bit clears the counter value to "0000H". UDCC In Case of Writing 0 Clears the counter value. 1 Ignored In Case of Reading "1" is read. [bit2]: CGSC (Counter clear/Gate selection bit) This bit selects the function for ZIN0 to ZIN3 pins from among the following options. • Counter clear function The counter value is cleared to "0000H" if the effective edge is input from the ZIN0 to ZIN3 pins. • Gate function The counter operates only while the effective level is input from ZIN0 to ZIN3 pins. Written Value Explanation 0 Counter clear function 1 Gate function <Note> The ZIN0 to ZIN3 pins operate by combining settings of this bit and CGE1 and CGE0 bits. Be sure to also set CGE1 and CGE0 bits. [bit1, bit0]: CGE1, CGE0 (Edge/Level selection bit) These bits select the effective edge/effective level for the ZIN0 to ZIN3 pins. The meaning and function of these bits vary depending on the CGSC bit setting. • When the counter clear function is selected in the CGSC bit (CGSC = 0) Selects the effective edge. The counter value is cleared to "0000H" if the edge selected in this bit is detected in the ZIN0 to ZIN3 pins. • When the gate function is selected in the CGSC bit (CGSC = 1) Selects the effective level. The counter operates only while the level selected in this bit is input from the ZIN0 to ZIN3 pins. CGE1 CM71-10151-2E CGE0 When the Counter Clear Function Is Selected (CGSC = 0) When the Gate Function Is Selected (CGSC = 1) 0 0 Edge detection disabled Level detection disabled (count disabled) 0 1 Falling edge "L" level 1 0 Rising edge "H" level 1 1 Setting prohibited Setting prohibited FUJITSU MICROELECTRONICS LIMITED 583 CHAPTER 23 Up/Down Counter 23.4 23.4.4 MB91625 Series Counter Status Register (CSR0 to CSR3) This register verifies the state of the up/down counter and controls interrupt requests. Figure 23.4-4 shows the bit configuration of the counter status register (CSR0 to CSR3). Figure 23.4-4 Bit configuration of the counter status register (CSR0 to CSR3) bit 7 6 5 4 3 2 1 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write R: Read only [bit7]: CSTR (Count activation bit) This bit activates/stops the up/down counter. Written Value Explanation 0 Stops count operation. 1 Activates the up/down counter. [bit6]: CITE (Compare result match interrupt enable bit) This bit sets whether to generate the comparison result match interrupt request if the counter value matches the value that has been set in the reload compare register (RCR0 to RCR3) (CMPF = 1). Written Value Explanation 0 Disables generation of comparison result match interrupt requests. 1 Enables generation of comparison result match interrupt requests. [bit5]: UDIE (Overflow/Underflow interrupt enable bit) This bit sets whether to generate the overflow/underflow interrupt request when the up/down counter overflows/underflows (OVFF/UDFF = 1). Written Value 584 Explanation 0 Disables generation of overflow/underflow interrupt requests. 1 Enables generation of overflow/underflow interrupt requests. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit4]: CMPF (Compare result match detection flag bit) This bit indicates that the counter value matches the value that has been set in the reload compare register (RCR0 to RCR3). If the CITE bit is set to "1" when this bit is "1", the comparison result match interrupt request is generated. CMPF In Case of Reading In Case of Writing 0 Values are not matched. This bit is cleared to "0". 1 Values are matched. Ignored <Note> The bit is changed to "1" in any of the following cases: • The value matches during count upward. • The value of the reload compare register (RCR0 to RCR3) is reloaded to the counter. • Values are already matched when the up/down counter is activated. [bit3]: OVFF (Overflow detection flag bit) This bit indicates that the up/down counter overflows. If the UDIE bit is set to "1" when this bit is "1", an overflow interrupt request is generated. OVFF In Case of Reading In Case of Writing 0 No overflow occurred. This bit is cleared to "0". 1 An overflow occurred. Ignored An overflow occurs when the counter value is "FFFFH" and the counter attempts to count upward. [bit2]: UDFF (Underflow detection flag bit) This bit indicates that the up/down counter underflows. If the UDIE bit is set to "1" when this bit is "1", an underflow interrupt request is generated. UDFF In Case of Reading In Case of Writing 0 No underflow occurred. This bit is cleared to "0". 1 An underflow occurred. Ignored An underflow occurs when the counter value is "0000H" and the counter attempts to count downward. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 585 CHAPTER 23 Up/Down Counter 23.4 MB91625 Series [bit1, bit0]: UDF1, UDF0 (Up-down flag bit) This bit indicates the last count direction. This bit is updated each time the up/down counter performs a count operation. UDF1 586 UDF0 Explanation 0 0 No input 0 1 Count downward 1 0 Count upward 1 1 Count upward/count downward concurrently FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.5 MB91625 Series 23.5 Interrupt An interrupt request is generated in any of the following cases. • The count direction is inverted (count direction change interrupt request) • The counter value matches the value that has been set in the reload compare register (RCR0 to RCR3) (comparison result match interrupt request) • An overflow occurs (overflow interrupt request) • An underflow occurs (underflow interrupt request) The generated interrupt request varies depending on the operation mode of the up/down counter. Table 23.5-1 outlines the relationship between the operation modes and interrupt requests. Table 23.5-1 Relationship between the operation modes and interrupt requests Interrupt Request Timer Mode Up/Down count mode Phase difference count mode (Multiplied by 2/ multiplied by 4) Count direction change interrupt request x O O Comparison result match interrupt request O O O Overflow interrupt request x O O Underflow interrupt request O O O Table 23.5-2 outlines the interrupts that can be used with the up/down counter. Table 23.5-2 Interrupts of the up/down counter Interrupt Request Interrupt Request Flag Interrupt Request Enabled Clearing an Interrupt Request Count direction change interrupt request CDCF = 1 for CCR CFIE = 1 for CCR Write "0" to the CDCF bit in the CCR. Comparison result match interrupt request CMPF = 1 for CSR CITE = 1 for CSR Write "0" to the CMPF bit in the CSR. Overflow interrupt request OVFF = 1 for CSR UDIE = 1 for CSR Write "0" to the OVFF bit in the CSR. Underflow interrupt request UDFF = 1 for CSR UDIE = 1 for CSR Write "0" to the UDFF bit in the CSR. CCR: Counter control register (CCR0 to CCR3) CSR: Counter status register (CSR0 to CSR3) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 587 CHAPTER 23 Up/Down Counter 23.5 MB91625 Series <Notes> • The CMPF bit of the counter control register (CCR0 to CCR3) changes to "1" not only if the counted up value matches but also if the value has already been matched when the value of the reload compare register (RCR0 to RCR3) is reloaded or when the up/down counter is activated. • For details of how to clear the counter and the reload timing, see "■ Clear event" and "■ Reload event" in "23.6 An Explanation of Operations and Setting Procedure Examples". • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests. - Clears interrupt requests before enabling the generation of interrupt requests. - Clears interrupt requests simultaneously with interrupts enabled. 588 • For details of the interrupt vector number of the respective interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For interrupt level settings, see "CHAPTER 10 Interrupt Controller". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series 23.6 An Explanation of Operations and Setting Procedure Examples This section explains the operation of the up/down counter. Also, examples of procedures for setting the operating state are shown. ■ Overview ● Counter mode The up/down counter can be used both as a 16-bit up/down counter and as an 8-bit up/down counter, depending on the setting. This can be set in the M16E bit in the counter control register (CCR0 to CCR3). • 8-bit mode (M16E = 0) Only the up-down count register lower (UDCRL0 to UDCRL3) is used. Write the reload value and compare value only in the reload compare register lower (RCRL0 to RCRL3) in byte notation. • 16-bit mode (M16E = 1) Both the upper and lower bytes of the up-down count register (UDCR0 to UDCR3) are used. Write the reload value and compare value in the reload compare register (RCR0 to RCR3) in half word. ● Operation mode One of the following three modes (4 types) can be selected for the operation mode of the up/down counter by using the CMS1 and CMS0 bit of the counter control register (CCR0 to CCR3). • Timer mode (CMS1, CMS0 = 00) In this mode, counting downward is performed starting from the previously set value by synchronizing with the count clock. The count clock is generated by dividing the peripheral clock (PCLK) by 2 or 8 with the prescaler. • Up/Down count mode (CMS1, CMS0 = 01) In this mode, signals that are input from the external signal input pins are counted upward or downward. • Phase difference count mode (multiplied by 2) (CMS1, CMS0 = 10)/Phase difference count mode (multiplied by 4) (CMS1, CMS0 = 11) In this mode, phase difference between the signals that are input from the external signal input pins are counted upward or downward. By inputting A-phase of the encoder from the AIN0 to AIN3 pins, B-phase from the BIN0 to BIN3 pins, and Z-phase from the ZIN0 to ZIN3 pins, rotation angle and rotation number can be counted and rotation direction can be detected with high accuracy, making it appropriate for counting for the encoder of motors and the like. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 589 CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ■ Functions that can be used ● Reload/Compare clear function 8/16-bit up/down counter can enable and disable the reload function and compare clear function by using the RLDE bit and UCRE bit in the counter control register (CCR0 to CCR3). • Reload function This function reloads the value that has been set in the reload compare register (RCR0 to RCR3) if an underflow occurs during count downward, and performs count downward again. For details of this operation, see "■ Count operation" in "23.6.1 Operation in Timer Mode". • Compare clear function In this function, if an attempt is made to further count upward while the value of the up/down counter matches the value that has been set in the reload compare register (RCR0 to RCR3) (comparison result match), the value of the up/down counter is cleared to "0000H" to start counting upward again. For details of this operation, see "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". This function cannot be used in timer mode. • Reload compare clear function this is a function used by combining the reload function and compare clear function. In this function, counting of any range is possible because counting upward/downward is performed between the values of "0000 H" and the value set in the reload compare register (RCR0 to RCR3). See "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". This function cannot be used in timer mode. Table 23.6-1shows how to set the reload function/compare clear function. Table 23.6-1 Setting the reload/compare clear function RLDE bit UCRE bit Explanation 0 0 Disable reload function/compare clear function 0 1 Disable reload function Enable compare clear function 1 0 Enable reload function Disable compare clear function 1 1 Enable reload function/compare clear function ● Function of the ZIN0 to ZIN3 pins One of the following functions can be selected for the ZIN0 to ZIN3 pins using the CGSC bit of the counter control register (CCR0 to CCR3). • Count clear function (CGSC = 0) The counter value is cleared to "0000H" if an effective edge is input from the ZIN0 to ZIN3 pins during count operation. • Gate function (CGSC = 1) The counter operates only when the effective level is being input from the ZIN0 to ZIN3 pins. When the counter clear function is selected, select the effective edge. When the gate function is selected, select the effective level. Make these selections by using the CGE1 and CGE0 bits of the counter control register (CCR0 to CCR3). 590 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series CGE1 CGE0 When the Counter Clear Function Is Selected (CGSC = 0) When the Gate Function Is Selected (CGSC = 1) 0 0 Edge detection disabled Level detection disabled (count disabled) 0 1 Falling edge "L" level 1 0 Rising edge "H" level 1 1 Setting prohibited Setting prohibited ■ Clear event The counter value is cleared to "0000H" in one of the following cases: • This device is reset. • The effective edge is input from the ZIN0 to ZIN3 pins. (When the counter clear function for the ZIN0 to ZIN3 pins is set in the CGSC bit (CGSC =0) of the counter control register (CCR0 to CCR3). • Software clear "0" is written to the UDCC bit of the counter control register (CCR0 to CCR3). • Clear with the compare clear function The counter value matches the value set in the reload compare register (RCR0 to RCR3) and the counter further attempts to count upward. (The count value is not cleared if counting downward is performed or the counter is stopped.) • Clear with an overflow generation Timing of count upward/count downward after the counter value reaches "FFFFH" (in 8-bit mode, "FFH") The timing of clearing the counter value to "0000H" depends on the operation state of the up/down counter as follows. • When a clear event occurs during count operation The value is cleared by synchronizing with the count clock. Figure 23.6-1 shows the timing for the clear event to occur. Figure 23.6-1 Clear event generation timing UDCR 0065H 0066H 0000H 0001H Synchronize with this clock Clear event Count clock UDCR: Up-down count register (UDCR0 to UDCR3) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 591 CHAPTER 23 Up/Down Counter 23.6 • MB91625 Series When a clear event occurs during count operation and the count operation is stopped before the next count clock is input (CSTR bit = 0, in the counter status register (CSR0 to CSR3)) The value is cleared at the point where the up/down counter stops. Figure 23.6-2 shows the clear event generation timing. Figure 23.6-2 Clear event generation timing UDCR 0065H 0066H 0000H Clear event Count clock Disabled Counting enabled Enabled UDCR: Up-down count register (UDCR0 to UDCR3) ■ Reload event The value of the up/down counter is reloaded in any of the following cases. • "1" is written to the CTUT bit of the counter control register (CCR0 to CCR3) • The value is reloaded by the reload function The timing at which the value of the up/down counter is reloaded is listed below, which depends on the operation state of the up/down counter. • When the reload event occurs during count operation The value is reloaded by synchronizing with the count clock. • When the reload event occurs while counting is stopped The value is reloaded at the time when the reload event occurs. <Notes> 592 • Do not write "1" to the CTUT bit of the counter control register (CCR0 to CCR3) during count operation. • If the reload event and clear event occur at the same time, the clear event has priority. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series 23.6.1 Operation in Timer Mode This section explains operations in timer mode. ■ Overview In this mode, counting downward is performed starting from the value that has been set in the reload compare register (RCR0 to RCR3). The peripheral clock (PCLK) is used as a count clock by dividing it with the prescaler. You can also use the reload function, which reloads the value of the reload compare register (RCR0 to RCR3) when the counter underflows to restart counting downward. ■ Count operation ● Normal operation 1. Set the reload value/compare value in the reload compare register (RCR0 to RCR3). 2. Write "1" to the CTUT bit of the counter control register (CCR0 to CCR3). The set value is transferred to the up-down count register (UDCR0 to UDCR3). 3. Enable operation of the up/down counter by setting the CSTR bit (CSTR = 1) of the counter status register (CSR0 to CSR3). Counting downward starts from the value that has been set in the reload compare register (RCR0 to RCR3). If the counter underflows, the UDFF bit of the counter status register (CSR0 to CSR3) changes to "1". At this point, if the UDIE bit of the counter status register is set to "1", the underflow interrupt request is generated. If the gate function is set in the ZIN0 to ZIN3 pins by use of the CGSC bit (CGSC = 1) of a counter control register (CCR0 to CCR3), the counting is performed only when the effective level, which was set in the CGE1 and CGE0 bits, is input from the ZIN0 to ZIN3 pins. For details of effective level settings, see "23.4.3 Counter Control Register (CCR0 to CCR3)". <Note> The minimum pulse width required for the ZIN0 to ZIN3 pins is 2T (T: period of the peripheral clock (PCLK)). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 593 CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ● Operation when the reload function is used If the counter underflows while counting downward, the UDFF bit of the counter status register (CSR0 to CSR3) changes to "1". The value of the reload compare register (RCR0 to RCR3) is reloaded at the next timing of underflow occurrence and counting down is restarted. At this point, if the UDIE bit of the counter status register (CSR0 to CSR3) is set to "1", the underflow interrupt request is generated. Figure 23.6-3 shows the operations when the reload function is used. Figure 23.6-3 Operation when the reload function is used (0FFFFH) FFH Reload (underflow interrupt request is generated) Reload (underflow interrupt request is generated) RCR 00H Underflow Underflow RCR: Reload compare register (RCR0 to RCR3) <Note> The value of the reload compare register (RCR0 to RCR3) is a reload value as well as a compare value. Therefore, if the value of the reload compare register (RCR0 to RCR3) is reloaded, the CMPF bit of the counter status register (CSR0 to CSR3) also changes to "1". 594 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series 23.6.2 Operations in Up/Down Count Mode This section explains operations in the up/down count mode. ■ Overview In this mode, the external signals that are input from the AIN0 to AIN3 pins and BIN0 to BIN3 pins are counted upward/downward as a count clock. Signals are counted upward if the external signals are input from the AIN0 to AIN3 pins and counted downward if input from the BIN0 to BIN3 pins. One of the following edges can be selected for counting the external signals by setting the CES1 and CES0 bits of the counter control register (CCR0 to CCR3). • Falling edge (CES1, CES0 = 01) • Rising edge (CES1, CES0 = 10) • Both edges (CES1, CES0 = 11) In up/down count mode, the following three functions can be used. • Reload function • Compare clear function • Reload compare clear function ■ Count operation ● Normal operation While the counter is enabled, if the effective edge is input from the AIN0 to AIN3 pins, signals are counted upward, and if the effective edge is input from the BIN0 to BIN3 pins, signals are counted downward. If the count direction is inverted such as from count up to count down or from count down to count up, the CDCF bit of the counter control register (CCR0 to CCR3) changes to "1". At this point, if "1" is set for the CFIE bit of the counter control register (CCR0 to CCR3), a count direction change interrupt request is generated. If the gate function is set in the ZIN0 to ZIN3 pins by use of the CGSC bit (CGSC = 1) of a counter control register (CCR0 to CCR3), the counting is performed only when the effective level, which was set in the CGE1 and CGE0 bits, is input from the ZIN0 to ZIN3 pins. For details of effective level settings, see "23.4.3 Counter Control Register (CCR0 to CCR3)". <Note> The minimum pulse width required for the AIN0 to AIN3 pins, BIN0 to BIN3 pins, and ZIN0 to ZIN3 pins is 2T (T: period of the peripheral clock (PCLK)). ● Operation when the reload function is used The operation is the same as that in timer mode. See "■ Count operation" in "23.6.1 Operation in Timer Mode". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 595 CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ● Operations when the compare clear function is used If the value of the up/down counter matches the value that has been set for the reload compare register (RCR0 to RCR3), the CMPF bit of the counter status register (CSR0 to CSR3) changes to "1". At this point, if CITE bit of the counter status register (CSR0 to CSR3) is set to "1", the comparison result match interrupt request is generated. In this state, if an attempt to further count upward is performed, the value of the up/down counter is cleared to "0000H" to restart counting upward. Figure 23.6-4 shows the operations when the compare clear function is used. Figure 23.6-4 Operations when the compare clear function is used (0FFFFH) FFH RCR Comparison results matched Comparison results matched 00H Counter clearing (Comparison result match interrupt request generation) Counter clearing (Comparison result match interrupt request generation) RCR: Reload compare register (RCR0 to RCR3) <Note> When the compare clear function is used, the value of the up/down counter is cleared to "0000H" if the following conditions are met. • The value of the up/down counter and the value that has been set in the reload compare register (RCR0 to RCR3) match (comparison result match) • After that, another count has been performed. However, the value of the up/down counter is not cleared in the following cases even if the comparison result matches. 596 • The next operation is counting downward • The up/down counter is stopped. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ● Operations when the reload compare clear function is used During count downward, the reload function is used, and during count upward, the compare clear function is used. Figure 23.6-5 shows the operations when the reload compare clear function is used. Figure 23.6-5 Operations when the reload compare clear function is used FFH Comparison results matched Comparison results matched Reload Reload Reload Comparison results matched RCR 00H Underflow Counter clearing Counter clearing Underflow Underflow Counter clearing RCR: Reload compare register (RCR0 to RCR3) ■ Verifying the count direction In this mode, both count upward and downward are performed. Therefore, the count direction can be verified with the UDF1 and UDF0 bits of the counter status register (CSR0 to CSR3). As these bits are rewritten each time counting is performed, they can be used to verify the current count direction. This is helpful if you want to know the rotation direction such as for controlling the motor. Table 23.6-2 shows the count directions indicated with the UDF1 and UDF0 bits. Table 23.6-2 Relationship between the UDF1 and UDF0 bits and count direction UDF1 UDF0 Count Direction 0 0 No input 0 1 Count downward 1 0 Count upward 1 1 Count upward/count downward concurrently If the count direction is inverted one or more times such as from count downward to count upward or from count upward to count downward, the CDCF bit of the counter control register (CCR0 to CCR3) changes to "1". At the time when this bit is changed, the count direction change interrupt request can also be generated. Thus, you can verify whether the count direction has been inverted by using the CDCF bit and generation of the count direction change interrupt request. <Note> If the count direction consecutively changes in a short period of time, the count direction may return to the original one with the UDF1 and UDF0 bits of the counter status register (CSR0 to CSR3) indicating the same direction as one indicated before the CDCF bit changed to "1". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 597 CHAPTER 23 Up/Down Counter 23.6 23.6.3 MB91625 Series Operations in Phase Difference Count Mode (Multiplied by 2) This section explains operations in phase difference count mode (multiplied by 2). ■ Overview In this mode, phase difference between the signals that are input from the 2 external signal input pins is counted. This mode is appropriate for counting phase difference between the A-phase and B-phase of the encoder output. When the rising edge or falling edge is detected from the BIN0 to BIN3 pins, the input level of the AIN0 to AIN3 pins is verified to perform counting upward/downward the phase difference between the BIN0 to BIN3 pins and AIN0 to AIN3 pins. If the A-phase leads the B-phase, the counter counts upward; if the Aphase falls behind the B-phase, the counter counts downward. Whether the counter counts upward or downward depends on the detection edge of the BIN0 to BIN3 pins and input level of the AIN0 to AIN3 pins. Table 23.6-3 lists how to count. Table 23.6-3 Counting method BIN0 to BIN3 pins Rising edge Falling edge AIN0 to AIN3 pins Count Direction "H" level Count upward "L" level Count downward "H" level Count downward "L" level Count upward In phase difference count mode (multiplied by 2), the following three functions can be used. 598 • Reload function • Compare clear function • Reload compare clear function FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ■ Count operation ● Normal operation While the counter is enabled, if the rising edge/falling edge is input from the BIN0 to BIN3 pins, the input level of the AIN0 to AIN3 pins is detected to perform counting upward/downward. Figure 23.6-6 shows the operations in phase difference count mode (multiplied by 2). Figure 23.6-6 Operations in phase difference count mode (multiplied by 2) AIN0 to AIN3 pins BIN0 to BIN3 pins Count value 0 +1 1 +1 2 +1 3 +1 4 +1 5 -1 4 +1 5 -1 4 -1 3 -1 2 -1 1 -1 0 If the gate function is set in the ZIN0 to ZIN3 pins by use of the CGSC bit (CGSC = 1) of a counter control register (CCR0 to CCR3), the counting is performed only when the effective level, which was set in the CGE1 and CGE0 bits, is input from the ZIN0 to ZIN3 pins. For details of effective level settings, see "23.4.3 Counter Control Register (CCR0 to CCR3)". <Note> The minimum pulse width required for the AIN0 to AIN3 pins, BIN0 to BIN3 pins, and ZIN0 to ZIN3 pins is 2T (T: period of the peripheral clock (PCLK)). ● Operation when the reload function is used The operation is the same as that in timer mode. See "■ Count operation" in "23.6.1 Operation in Timer Mode". ● Operations when the compare clear function is used The operation is the same as that in up/down count mode. See "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". ● Operations when the reload compare clear function is used The operation is the same as that in up/down count mode. See "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". ■ Verifying the count direction The method is the same as that for the up/down count mode. See "■ Verifying the count direction" in "23.6.2 Operations in Up/Down Count Mode". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 599 CHAPTER 23 Up/Down Counter 23.6 23.6.4 MB91625 Series Operations in Phase Difference Count Mode (Multiplied by 4) This section explains operations in phase difference count mode (multiplied by 4). ■ Overview In this mode, the phase difference between the signals that are input from the 2 external signal input pins is counted. This mode is appropriate for counting phase difference between the A-phase and B-phase of the encoder output. When the rising edge or falling edge is detected from the AIN0 to AIN3 pins or from the BIN0 to BIN3 pins, the input level of the other pins is verified to perform counting upward/downward the phase difference between the BIN0 to BIN3 pins and AIN0 to AIN3 pins. Whether the counter counts upward or downward depends on the combination of the detected edge and input level. Table 23.6-4 shows how to count. Table 23.6-4 Counting method Edge Detection Pin BIN0 to BIN3 pins Detected Edge Rising edge Level Verification Pin AIN0 to AIN3 pins Falling edge AIN0 to AIN3 pins Rising edge BIN0 to BIN3 pins Falling edge Input Level Count Direction "H" level Count upward "L" level Count downward "H" level Count downward "L" level Count upward "H" level Count downward "L" level Count upward "H" level Count upward "L" level Count downward In phase difference count mode (multiplied by 4), the following three functions can be used. 600 • Reload function • Compare clear function • Reload compare clear function FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 23 Up/Down Counter 23.6 MB91625 Series ■ Count operation ● Normal operation While the counter is enabled, if the rising edge/falling edge is input from the AIN0 to AIN3 pins or from the BIN0 to BIN3 pins, input level of the other pins is detected to perform counting upward/downward. Figure 23.6-7 shows the operations in phase difference count mode (multiplied by 4). Figure 23.6-7 Operations in phase difference count mode (multiplied by 4) AIN0 to AIN3 pins BIN0 to BIN3 pins Count value 0 +1+1 1 2 +1+1 3 4 +1+1 5 6 +1+1 7 8 +1+1 9 10 -1 9 +1 10 -1 9 -1-1 8 7 -1-1 6 5 -1-1 4 3 -1-1 2 1 If the gate function is set in the ZIN0 to ZIN3 pins by use of the CGSC bit (CGSC = 1) of a counter control register (CCR0 to CCR3), the counting is performed only when the effective level, which was set in the CGE1 and CGE0 bits, is input from the ZIN0 to ZIN3 pins. For details of effective level settings, see "23.4.3 Counter Control Register (CCR0 to CCR3)". <Note> The minimum pulse width required for the AIN0 to AIN3 pins, BIN0 to BIN3 pins, and ZIN0 to ZIN3 pins is 2T (T: period of the peripheral clock (PCLK)). ● Operation when the reload function is used The operation is the same as that in timer mode. See "■ Count operation" in "23.6.1 Operation in Timer Mode". ● Operations when the compare clear function is used The operation is the same as that in up/down count mode. See "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". ● Operations when the reload compare clear function is used The operation is the same as that in up/down count mode. See "■ Count operation" in "23.6.2 Operations in Up/Down Count Mode". ■ Verifying the count direction The method is the same as that for the up/down count mode. See "■ Verifying the count direction" in "23.6.2 Operations in Up/Down Count Mode". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 601 CHAPTER 23 Up/Down Counter 23.6 602 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter This chapter explains the functions and operations of the 10-bit A/D converter. 24.1 24.2 24.3 24.4 Overview Configuration Pins Registers 24.5 Interrupts 24.6 Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 603 CHAPTER 24 10-Bit A/D Converter 24.1 MB91625 Series 24.1 Overview The 10-bit A/D converter is a device for converting analog signals to 10-bit digital signals. This series microcontroller has 10-bit A/D converters, and 16 analog input channels can be assigned for conversion. ■ Overview • Conversion time: 1.2 μs per channel, minimum (33 MHz peripheral clock (PCLK)) • Comparison/conversion method: RC-type successive comparison and conversion with sample-and-hold circuits • Conversion mode: The modes that can be used are categorized into the following two types: - A/D scan conversion An optional conversion channel is selected from 16 channels and made subject to conversion. Two conversion modes are available: single conversion mode and repeat conversion mode. In single conversion mode, signals from the selected channel are converted only once. In repeat conversion mode, signals from the selected channel are converted repeatedly. - A/D priority conversion Once an activation trigger for high-priority A/D conversion is generated, that conversion is performed soon afterward by stopping A/D scan conversion in progress. There are two priority levels. • Activation trigger: Activation triggers vary depending on the A/D conversion mode: - A/D scan conversion Conversion is activated by software or at detection of a rising edge of the TOUT signal of base timer ch.0. - A/D priority conversion (priority 1) Conversion is triggered by input of a falling edge from an external trigger input pin. - A/D priority conversion (priority 2) Conversion is activated by software or at detection of a rising edge of the TOUT signal of base timer ch.2. • FIFO functionality: There 16 FIFO levels for A/D scan conversion and 4 FIFO levels for A/D priority conversion. • Conversion result compare function: A/D conversion results can be compared. • Independent control of channels: One of two kinds of sampling time can be set for each channel. • Conversion results: A/D conversion results can specified to be stored left-justified (MSB side) or rightjustified (LSB side). • Interrupt request: Can be issued in the following cases: • 604 - Data has been stored in the predetermined number of stages in the FIFO used during A/D scan conversion. - Data has been stored in the predetermined number of stages in the FIFO used during A/D priority conversion. - A FIFO overrun occurred. - The comparison function is used to determine whether conversion results satisfy the interrupt request generation conditions. DMA transfer activation: Generation of an interrupt request can be used for DMA transfer of conversion results. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.2 MB91625 Series 24.2 Configuration This section explains the configuration of the 10-bit A/D converter. ■ Block diagram of the 10-bit A/D converter Figure 24.2-1 shows a block diagram of the 10-bit A/D converter. Figure 24.2-1 Block diagram of the 10-bit A/D converter Base timer ch.0 Base timer ch.2 ADTRG0 pins A/D conversion result comparison interrupt request FIFO overrun interrupt request Scan conversion interrupt request Priority conversion interrupt request Channel and status controller Controller S/H A/D converter Comparator AN15 AN14 D/A converter AN13 AN12 Buffer AN10 4 FIFO levels for A/D priority conversion . . MPX . . AN5 Peripheral bus 16 FIFO levels for A/D scan conversion AN11 AN4 AN3 AN2 AN1 AN0 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 605 CHAPTER 24 10-Bit A/D Converter 24.2 • MB91625 Series A/D scan conversion FIFO This is the FIFO for A/D scan conversion. There are 16 FIFO levels. • A/D priority conversion FIFO • Controller This is the FIFO for A/D priority conversion. There are four FIFO levels. This controller controls conversion operations. • Channel and status controller This controller controls the channels and status of the 10-bit A/D converter. • MPX (analog multiplexer) The MPX selects (switches to), from multiple analog input signals, the analog signal to be converted. ■ Clocks Table 24.2-1 lists the clocks used for the 10-bit A/D converter. Table 24.2-1 Clock used for the 10-bit A/D converter Clock Name Operation clock 606 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.3 MB91625 Series 24.3 Pins This section explains the pins used for the 10-bit A/D converter. ■ Overview The 10-bit A/D converter has the following pins: • AVCC pin • AVRH pin 10-bit A/D converter analog power input pin 10-bit A/D converter reference voltage input pin • AVSS pin 10-bit A/D converter GND pin • AN0 to AN15 pins 10-bit A/D converter analog input pins These pins are multiplexed pins. For details of using these pins as the AN0 to AN15 pins of the 10-bit A/D converter, see "13.4.6 A/D Channel Enable Register (ADCHE)". • ADTRG0 pins 10-bit A/D converter external trigger input pins These pins are multiplexed pins. For details of using these pins as the ADTRG0 pins of the 10-bit A/ D converter, see "2.4 Setting Method for Pins". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 607 CHAPTER 24 10-Bit A/D Converter 24.3 MB91625 Series ■ Relationship between pins and channels Table 24.3-1 shows the relationship between channels and pins. Table 24.3-1 Relationship between channels and pins Channel 0 608 Analog Power Input Pin Reference Voltage Input Pin AVCC AVRH GND Pin AVSS Analog Input Pin AN0 1 AN1 2 AN2 3 AN3 4 AN4 5 AN5 6 AN6 7 AN7 8 AN8 9 AN9 10 AN10 11 AN11 12 AN12 13 AN13 14 AN14 15 AN15 FUJITSU MICROELECTRONICS LIMITED External Trigger Input Pin ADTRG0 - CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4 Registers This section explains the configurations and functions of the registers used for the 10-bit A/D converter. ■ List of registers for the 10-bit A/D converter Table 24.4-1 lists the registers used for the 10-bit A/D converter. Table 24.4-1 Registers for the 10-bit A/D converter Abbreviated Register Name CM71-10151-2E Register Name Reference ADCHE A/D channel enable register 13.4.6 ADCR0 A/DC control register 0 24.4.1 ADSR0 A/DC status register 0 24.4.2 SCCR0 Scan conversion control register 0 24.4.3 SFNS0 Scan conversion FIFO number setting register 0 24.4.4 SCIS00 Scan conversion input select register 00 24.4.6 SCIS10 Scan conversion input select register 10 24.4.6 SCFD0 Scan conversion FIFO data register 0 24.4.5 PCCR0 Priority conversion control register 0 24.4.7 PFNS0 Priority conversion FIFO number setting register 0 24.4.8 PCIS0 Priority conversion input select register 0 24.4.10 PCFD0 Priority conversion FIFO data register 0 24.4.9 CMPD0 A/D comparison data setting register 0 24.4.11 CMPCR0 A/D comparison control register 0 24.4.12 ADSS00 Sampling time select register 00 24.4.14 ADSS10 Sampling time select register 10 24.4.14 ADST00 Sampling time setting register 00 24.4.13 ADST10 Sampling time setting register 10 24.4.13 ADCT0 Compare time setting register 0 24.4.15 FUJITSU MICROELECTRONICS LIMITED 609 CHAPTER 24 10-Bit A/D Converter 24.4 24.4.1 MB91625 Series A/DC Control Registers (ADCR0) These registers control interrupt requests. Figure 24.4-1 shows the bit configuration of the A/DC control registers (ADCR0). Figure 24.4-1 Bit configuration of the A/DC control registers (ADCR0) bit Attribute Initial value 7 6 5 4 3 2 1 0 SCIF PCIF CMPIF Undefined SCIE PCIE CMPIE OVRIE R/W R/W R/W - R/W R/W R/W R/W 0 0 0 X 0 0 0 0 R/W: Read/Write -: Undefined X: Undefined [bit7]: SCIF (Scan conversion interrupt request flag bit) This bit indicates that A/D scan conversion results have been stored in the number of stages in the FIFO as specified by the SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0). If the SCIE bit is set to "1" when this bit is "1", a scan conversion interrupt request is generated. SCIF In Case of Reading In Case of Writing 0 The number of stages storing conversion results has not reached the specified number of stages. This bit is cleared to "0". 1 The number of stages storing conversion results has reached the specified number of stages. Ignored <Note> When a read-modify-write instruction is used, "1" is read. 610 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit6]: PCIF (Priority conversion interrupt request flag bit) This bit indicates that A/D priority conversion results have been stored up to the number of stages in the FIFO as specified by the PFS1 and PFS0 bits in a priority conversion FIFO number setting register (PFNS0). If the PCIE bit is set to "1" when this bit is "1", a priority conversion interrupt request is generated. PCIF In Case of Reading In Case of Writing 0 The number of stages storing conversion results has not reached the specified number of stages. This bit is cleared to "0". 1 The number of stages storing conversion results has reached the specified number of stages. Ignored <Note> When a read-modify-write instruction is used, "1" is read. [bit5]: CMPIF (Conversion result comparison interrupt request flag bit) The A/D conversion result compare function is used when conversion results are compared with the data in the A/D comparison data setting registers (CMPD0). This bit indicates that a conversion result satisfies the requirements set in an A/D comparison data setting register (CMPD0) and an A/D comparison control register (CMPCR0). If the CMPIE bit is set to "1" when this bit is "1", a conversion result comparison interrupt request is generated. CMPIF In Case of Reading In Case of Writing 0 The requirements are not satisfied. This bit is cleared to "0". 1 The requirements are satisfied. Ignored <Note> When a read-modify-write instruction is used, "1" is read. [bit4]: Undefined bit CM71-10151-2E In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED 611 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit3]: SCIE (Scan conversion interrupt enable bit) This bit specifies whether to generate a scan conversion interrupt request when the number of stages storing A/D scan conversion results reaches the number of FIFO stages (SCIF bit = 1) specified in the SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0). Written Value Explanation 0 Disables generation of scan conversion interrupt requests. 1 Enables generation of scan conversion interrupt requests. [bit2]: PCIE (Priority conversion interrupt enable bit) This bit specifies whether to generate a priority conversion interrupt request when the number of stages storing A/D priority conversion results reaches the number of FIFO stages (PCIF bit = 1) specified in the PFS1 and PFS0 bits in a priority conversion FIFO number setting register (PFNS0). Written Value Explanation 0 Disables generation of priority conversion interrupt requests. 1 Enables generation of priority conversion interrupt requests. [bit1]: CMPIE (Conversion result comparison interrupt enable bit) The A/D conversion result compare function is used when conversion results are compared with the data in the A/D comparison data setting registers (CMPD0). This bit specifies whether to generate a conversion result comparison interrupt request when a conversion result satisfies the requirements (CMPIF bit = 1) set in an A/D comparison control register (CMPCR0). Written Value Explanation 0 Disables generation of conversion result comparison interrupt requests. 1 Enables generation of conversion result comparison interrupt requests. [bit0]: OVRIE (FIFO overrun interrupt enable bit) This bit specifies whether to generate a FIFO overrun interrupt request when the SOVR bit in a scan conversion control register (SCCR0) or the POVR bit in a priority conversion control register (PCCR0) changes to "1". If an attempt is made to write to a full FIFO, the SOVR bit in the scan conversion control register (SCCR0) or the POVR bit in the priority conversion control register (PCCR0) changes to "1". Written Value 612 Explanation 0 Disables generation of FIFO overrun interrupt requests. 1 Enables generation of FIFO overrun interrupt requests. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.2 A/DC Status Registers (ADSR0) These registers indicate the A/D conversion status. Figure 24.4-2 shows the bit configuration of the A/DC status registers (ADSR0). Figure 24.4-2 Bit configuration of the A/DC status registers (ADSR0) bit 7 6 5 4 3 2 1 0 ADSTP FDAS Undefined Undefined Undefined PCNS PCS SCS R/W R/W - - - R R R 0 0 X X X 0 0 0 Attribute Initial value R/W: Read/Write R: Read only -: Undefined X: Undefined [bit7]: ADSTP (A/D conversion abort bit) This bit forcibly stops A/D conversion. ADSTP In Case of Writing 0 Ignored 1 Forcibly stops A/D conversion. In Case of Reading "0" is read. <Notes> • Writing "1" to this bit stops A/D conversion in either A/D scan conversion mode or A/D priority conversion mode. • Writing "1" to this bit to forcibly stop A/D conversion clears the PCNS, PCS, and SCS bits to "0". However, it does not affect other registers. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 613 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit6]: FDAS (FIFO data allocation select bit) This bit specifies the mode of bit allocation to the scan conversion FIFO data registers (SCFD0) and priority conversion FIFO data registers (PCFD0). • Left-justify: Conversion results (with channel information, with priority A/D activation trigger information (priority conversion only) are left-justified. • Right-justify: Conversion results (without channel information, without priority A/D activation trigger information (priority conversion only) are shifted 6 bits to the LSB side to right-justify the results. Conversion results are allocated to bit9 to bit0. Written Value 614 Explanation 0 Allocates conversion results left-justified. 1 Allocates conversion results right-justified. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series Figure 24.4-3 shows the relationship between this bit and the scan conversion FIFO data registers (SCFD0) and the relationship between this bit and the priority conversion FIFO data registers (PCFD0). Figure 24.4-3 Relationship between FDAS and the scan conversion FIFO data registers (SCFD0)/ priority conversion FIFO data registers (PCFD0) Scan conversion FIFO data registers (SCFD0) For FDAS = 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 SC4 SC3 SC2 SC1 SC0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 For FDAS = 1 Priority conversion FIFO data registers (PCFD0) For FDAS = 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 RS PC4 PC3 PC2 PC1 PC0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 For FDAS = 1 <Notes> • If "1" is written to this bit to select right-justification, conversion results are shifted six bits to the LSB side, which consequently leads to a loss of converted information on channels (the SC4 to SC0 bits/PC4 to PC0 bits in Figure 24.4-3). Right-justification is used only when channel information is not required in conversion results, such as when conversion involves only 1 channel. • If "1" is written to this bit to select right-justification in A/D priority conversion mode, (the RS bit of Figure 24.4-3) activation trigger information on A/D priority conversion is lost. Rightjustification is used only when either priority 1 or 2 of A/D priority conversion mode is used. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 615 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit5 to bit3]: Undefined bits In case of writing Ignored In case of reading A value is undefined. [bit2]: PCNS (Priority conversion pending flag bit) This bit indicates that A/D priority conversion of priority 2 is pending. If A/D priority conversion of priority 2 is activated during execution of A/D priority conversion of priority 1 or vice versa, the bit is changed to "1". Read Value Explanation 0 A/D priority conversion of priority 2 is not pending. 1 A/D priority conversion of priority 2 is pending. [bit1]: PCS (Priority conversion status flag bit) This bit indicates that A/D priority conversion of priority 1 or 2 is in progress. Read Value Explanation 0 A/D priority conversion is stopped. 1 A/D priority conversion is in progress. [bit0]: SCS (Scan conversion status flag bit) This bit indicates that A/D scan conversion is in progress. Read Value 616 Explanation 0 A/D scan conversion is stopped. 1 A/D scan conversion is in progress. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.3 Scan Conversion Control Registers (SCCR0) These registers are used to control the operation of A/D scan conversion. Figure 24.4-4 shows the bit configuration of the scan conversion control registers (SCCR0). Figure 24.4-4 Bit configuration of the scan conversion control registers (SCCR0) bit 7 6 5 4 3 2 1 0 SEMP SFUL SOVR SFCLR Undefined RPT SHEN SSTR Attribute R R R/W R/W - R/W R/W R/W Initial value 1 0 0 0 X 0 0 0 R/W: Read/Write R: Read only -: Undefined X: Undefined <Note> Do not perform word access to these registers. The scan conversion FIFO data register (SCFD0) needs to be read when the SEMP bit is "0". [bit7]: SEMP (Scan conversion FIFO empty flag bit) This bit indicates that the FIFO for A/D scan conversion is empty. Read Value Explanation 0 The FIFO for A/D scan conversion contains data. 1 The FIFO for A/D scan conversion is empty. This bit is cleared to "0" when data is stored in a scan conversion FIFO data register (SCFD0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 617 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit6]: SFUL (Scan conversion FIFO full bit) This bit indicates that the FIFO for A/D scan conversion is full. Read Value Explanation 0 The FIFO for A/D scan conversion has free space. 1 The FIFO for A/D scan conversion is full. This bit is cleared to "0" when "1" is written to the SFCLR bit or a scan conversion FIFO data register (SCFD0) is read. [bit5]: SOVR (Scan conversion overrun flag bit) The bit indicates that an attempt has been made to write to a full A/D scan conversion FIFO (an overrun has occurred). If the OVRIE bit in an A/DC control register (ADCR0) is set to "1" when this bit is "1", a FIFO overrun interrupt request is generated. SOVR In Case of Reading In Case of Writing 0 No overrun occurred. This bit is cleared to "0". 1 An overrun occurred. Ignored <Notes> • When a read-modify-write instruction is used, "1" is read. • When an attempt is made to write data to a full FIFO, the conversion data in the FIFO is not overwritten. [bit4]: SFCLR (Scan conversion FIFO clear bit) This bit is used to clear the A/D scan conversion FIFO. SFCLR In Case of Writing 0 Ignored 1 Clears the A/D scan conversion FIFO. In Case of Reading "0" is read. <Note> Writing "1" to this bit empties the FIFO for A/D scan conversion. Accordingly, the SEMP bit changes to "1". 618 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit3]: Undefined bit In case of writing Ignored In case of reading A value is undefined. [bit2]: RPT (Scan conversion repeat bit) This bit specifies the A/D scan conversion mode. • Single conversion mode: Signals from the channel specified by a scan conversion input select register (SCIS10, SCIS00) are converted only once. • Repeat conversion mode: Signals from the channel specified by a scan conversion input select register (SCIS10, SCIS00) are converted repeatedly. Written Value Explanation 0 Single conversion mode 1 Repeat conversion mode <Notes> • If "0" is written to this bit during conversion in repeat conversion mode, the conversion operation is stopped after the signals from the channel specified by the scan conversion input select register (SCIS10, SCIS00) are converted. • To enable repeat conversion mode, write "1" to this bit after checking the SCS bit in the A/DC status registers (ADSR0) and confirming that A/D scan conversion is stopped (SCS = 0). However, to start A/D scan conversion (with SSTR = 1) while simultaneously enabling repeat conversion mode, the SSTR bit can be written at the same time as this bit. [bit1]: SHEN (Scan conversion timer activation enable bit) This bit specifies whether to activate A/D scan conversion upon detection of the rising edge of a TOUT signal of base timer ch.0. Written Value Explanation 0 Disables A/D scan conversion activation based on a base timer (ch.0). 1 Enables A/D scan conversion activation based on a base timer (ch.0). <Notes> • If "1" is written to the SSTR bit, A/D scan conversion is activated regardless of the setting of this bit. • After "1" is written to this bit, "1" may be written to the SSTR bit at the same time that activation is triggered by a base timer (ch.0). In this event, activation by software is given priority, and activation triggered by the base timer is ignored. • For details of the TOUT signal, see "CHAPTER 22 Base Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 619 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit0]: SSTR (Scan conversion start bit) This bit is used to activate A/D scan conversion by software. Writing "1" to the bit during conversion stops and restarts the conversion. SSTR 620 In Case of Writing 0 Ignored 1 Activates or reactivates A/D scan conversion. In Case of Reading "0" is read. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.4 Scan Conversion FIFO Number Setting Register (SFNS0) These registers specify the maximum number of stages in the A/D scan conversion FIFO. A scan conversion interrupt request can be issued when the number of stages storing conversion results reaches that maximum number during A/D scan conversion. Figure 24.4-5 shows the bit configuration of the scan conversion FIFO number setting registers (SFNS0). Figure 24.4-5 Bit configuration of the scan conversion FIFO number setting registers (SFNS0) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined SFS3 SFS2 SFS1 SFS0 Attribute - - - - R/W R/W R/W R/W Initial value X X X X 0 0 0 0 R/W: Read/Write -: Undefined X: Undefined <Note> Do not perform word access to these registers. [bit7 to bit4]: Undefined bits CM71-10151-2E In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED 621 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit3 to bit0]: SFS3 to SFS0 (Scan conversion FIFO number setting bits) These bits specify the maximum number of stages in the A/D scan conversion FIFO. A scan conversion interrupt request can be issued when the number of stages storing conversion results reaches that maximum number during A/D scan conversion. The SCIF bit in an A/DC control register (ADCR0) changes to "1" when the number of stages storing such data reaches the maximum number of FIFO stages specified by these bits. 622 SFS3 SFS2 SFS1 SFS0 Explanation 0 0 0 0 First level 0 0 0 1 Second level 0 0 1 0 Third level 0 0 1 1 Fourth level 0 1 0 0 Fifth level 0 1 0 1 Sixth level 0 1 1 0 Seventh level 0 1 1 1 Eighth level 1 0 0 0 Ninth level 1 0 0 1 Tenth level 1 0 1 0 Eleventh level 1 0 1 1 Twelfth level 1 1 0 0 Thirteenth level 1 1 0 1 Fourteenth level 1 1 1 0 Fifteenth level 1 1 1 1 Sixteenth level FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.5 Scan Conversion FIFO Data Registers (SCFD0) These registers store A/D scan conversion results. Each register consists of 16 FIFO stages. FIFO data can be read sequentially from the registers. The bit configuration of these registers varies depending on the setting of the FDAS bit in the A/DC status registers (ADSR0). <Notes> • One of these registers must always be read after the SEMP bit in a scan conversion control register (SCCR0) is checked to determine whether data remains in the A/D scan conversion FIFO (SEMP = 0). If this register is read when the A/D scan conversion FIFO is empty (SEMP = 1), it is impossible to determine whether the read data is valid. For details, see "■ Operation of A/D scan conversion" in "24.6.3 FIFO Operations". • Do not perform word access to these registers. • In byte access to these registers, the low-order byte (bit7 to bit0) must be accessed before the high-order byte (bit15 to bit8). FIFO data is shifted after the high-order bytes is read. ■ Left-justify (FDAS = 0) Figure 24.4-6 shows the bit configuration of the scan conversion FIFO data registers (SCFD0) when the FDAS bit in an A/DC status register (ADSR0) specifies left-justification (FDAS = 0). Figure 24.4-6 Bit configuration of the scan conversion FIFO data registers (SCFD0) bit 15 14 13 12 11 10 9 8 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 Attribute R R R R R R R R Initial value X X X X X X X X 7 6 5 4 3 2 1 0 SD1 SD0 Undefined SC4 SC3 SC2 SC1 SC0 Attribute R R - R R R R R Initial value X X X X X X X X bit R: Read only -: Undefined X: Undefined CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 623 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit15 to bit6]: SD9 to SD0 (A/D scan conversion result bits) These bits store A/D scan conversion results. [bit5]: Undefined bit "0" is read. [bit4 to bit0]: SC4 to SC0 (Conversion channel bits) These bits indicate the channel from which analog input has been converted and stored in the SD9 to SD0 bits. SC4 SC3 SC2 SC1 SC0 Explanation 0 0 0 0 0 ch.0 (AN0 pin) 0 0 0 0 1 ch.1 (AN1 pin) 0 0 0 1 0 ch.2 (AN2 pin) 0 0 0 1 1 ch.3 (AN3 pin) 0 0 1 0 0 ch.4 (AN4 pin) 0 0 1 0 1 ch.5 (AN5 pin) 0 0 1 1 0 ch.6 (AN6 pin) 0 0 1 1 1 ch.7 (AN7 pin) 0 1 0 0 0 ch.8 (AN8 pin) 0 1 0 0 1 ch.9 (AN9 pin) 0 1 0 1 0 ch.10 (AN10 pin) 0 1 0 1 1 ch.11 (AN11 pin) 0 1 1 0 0 ch.12 (AN12 pin) 0 1 1 0 1 ch.13 (AN13 pin) 0 1 1 1 0 ch.14 (AN14 pin) 0 1 1 1 1 ch.15 (AN15 pin) 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 Setting prohibited 624 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series SC4 SC3 SC2 SC1 SC0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Explanation Setting prohibited ■ Right-justify (FDAS = 1) Figure 24.4-7 shows the bit configuration of the scan conversion FIFO data registers (SCFD0) when the FDAS bit in an A/DC status register (ADSR0) specifies right-justification (FDAS = 1). Figure 24.4-7 Bit configuration of the scan conversion FIFO data registers (SCFD0) bit 15 14 13 12 11 10 9 8 Undefined Undefined Undefined Undefined Undefined Undefined SD9 SD8 Attribute - - - - - - R R Initial value X X X X X X X X 7 6 5 4 3 2 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Attribute R R R R R R R R Initial value X X X X X X X X bit R: Read only -: Undefined X: Undefined [bit15 to bit10]: Undefined bits "0" is read. [bit9 to bit0]: SD9 to SD0 (A/D scan conversion result bits) These bits store A/D scan conversion results. <Note> Information on converted channels is not stored in right-justify mode. Right-justification is used only when channel information is not required in conversion results, such as when conversion involves only one channel. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 625 CHAPTER 24 10-Bit A/D Converter 24.4 24.4.6 MB91625 Series Scan Conversion Input Select Registers (SCIS10, SCIS00) These registers are used to select the channel to be subject to A/D scan conversion. Figure 24.4-8 shows the bit configuration of the scan conversion input select registers (SCIS10, SCIS00). Figure 24.4-8 Bit configuration of the scan conversion input select registers (SCIS10, SCIS00) Scan conversion input select register 10 (SCIS10) bit 7 6 5 4 3 2 1 0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value Scan conversion input select register 00 (SCIS00) bit Attribute Initial value 7 6 5 4 3 2 1 0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W: Read/Write SCIS10, SCIS00: AN15 to AN0 (analog input select bits) The channel corresponding to a bit that is set to "1" is made subject to conversion. The AN15 bit corresponds to ch.15 (AN15 pin), the AN14 bit corresponds to ch.14 (AN14 pin), ... the AN1 bit corresponds to ch.1 (AN1 pin), and the AN0 bit corresponds to ch.0 (AN0 pin). If multiple channels are selected with these registers, they are made subject to conversion sequentially in ascending order of channel number. For example, if "1" is written to the AN3, AN5, AN10, and AN15 bits, the corresponding channels are made subject to conversion in the following sequence: ch.3 → ch.5 → ch.10 → ch.15 <Note> Write to these registers while A/D conversion is stopped. 626 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.7 Priority Conversion Control Registers (PCCR0) These registers are used to control the operation of A/D priority conversion. Two priority levels can be selected. Figure 24.4-9 shows the bit configuration of the priority conversion control registers (PCCR0). Figure 24.4-9 Bit configuration of the priority conversion control registers (PCCR0) bit 7 6 5 4 3 2 1 0 PEMP PFUL POVR PFCLR Reserved PEEN PHEN PSTR Attribute R R R/W R/W R/W R/W R/W R/W Initial value 1 0 0 0 0 0 0 0 R/W: Read/Write R: Read only <Note> Do not perform word access to these registers. The priority conversion FIFO data register (PCFD0) needs to be read when the SEMP bit is "0". [bit7]: PEMP (Priority conversion FIFO empty flag bit) This bit indicates that the FIFO for A/D priority conversion is empty. Read Value Explanation 0 The FIFO for A/D priority conversion contains data. 1 The FIFO for A/D priority conversion is empty. This bit is cleared to "0" when data is stored in the priority conversion FIFO data register (PCFD0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 627 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit6]: PFUL (Priority conversion FIFO full bit) This bit indicates that the FIFO for A/D priority conversion is full. Read Value Explanation 0 The A/D priority conversion FIFO has free space. 1 The A/D priority conversion FIFO is full. This bit is cleared to "0" when "1" is written to the PFCLR bit or a priority conversion FIFO data register (PCFD0) is read. [bit5]: POVR (Priority conversion overrun flag bit) This bit indicates that an attempt has been made to write to a full A/D priority conversion FIFO (an overrun has been occurred). If the OVRIE bit in an A/DC control register (ADCR0) is set to "1" when this bit is "1", a FIFO overrun interrupt request is generated. POVR In Case of Reading In Case of Writing 0 Overrun has not been occurred This bit is cleared to "0". 1 Overrun has been occurred Ignored <Notes> • When a read-modify-write instruction is used, "1" is read. • Even if an attempt is made to write data to a full FIFO, the conversion data in the FIFO is not overwritten. [bit4]: PFCLR (Priority conversion FIFO clear bit) This bit is used to clear the A/D priority conversion FIFO. PFCLR In Case of Writing 0 Ignored 1 Clears the A/D priority conversion FIFO. In Case of Reading "0" is read. <Note> Writing "1" to this bit empties the FIFO for A/D priority conversion. Accordingly, the PEMP bit changes to "1". 628 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit3]: Reserved bit In case of writing Always write "0" to this (these) bit (bits). In case of reading A value is undefined. [bit2]: PEEN (Priority conversion external activation enable bit) This bit specifies whether to activate A/D priority conversion of priority level 1 upon detection of a falling edge from the ADTRG0 pin. Priority 1 has the highest priority because priority 1 > priority 2. Written Value Explanation 0 Disables activation of A/D priority conversion of priority 1. 1 Enables activation of A/D priority conversion of priority 1. <Note> The microcontroller provides four pins that can be used as an ADTRG0 pin. Specify a pin as the ADTRG0 pin. For details of how to set the pin, see "CHAPTER 13 I/O Ports". [bit1]: PHEN (Priority conversion timer activation enable bit) This bit specifies whether to activate A/D priority conversion of priority 2 upon detection of the rising edge of a TOUT signal of base timer ch.2. Priority 2 < priority 1. Written Value Explanation 0 Disables activation of A/D priority conversion of priority 2. 1 Enables activation of A/D priority conversion of priority 2. <Notes> • If "1" is written to the PSTR bit, A/D priority conversion of priority 2 is activated regardless of the setting of this bit. • For details of the TOUT signal, see "CHAPTER 22 Base Timer". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 629 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit0]: PSTR (Priority conversion start bit) This bit enables software to activate A/D priority conversion of priority 2. Priority 2 < priority 1. PSTR In Case of Writing 0 Ignored 1 Activates A/D priority conversion of priority 2. In Case of Reading "0" is read. <Note> Even if "1" is written to this bit during A/D conversion, the A/D conversion cannot be reactivated. 630 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.8 Priority Conversion FIFO Number Setting Registers (PFNS0) These registers specify the maximum number of stages in the A/D priority conversion FIFO. A priority conversion interrupt request can be issued when the number of stages storing conversion results reaches that maximum number during A/D priority conversion. Figure 24.4-10 shows the bit configuration of the priority conversion FIFO number setting registers (PFNS0). Figure 24.4-10 Bit configuration of the Priority conversion FIFO number setting registers (PFNS0) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined PFS1 PFS0 Attribute - - - - - - R/W R/W Initial value X X X X X X 0 0 R/W: Read/Write -: Undefined X: Undefined <Note> Do not perform word access to these registers. The priority conversion FIFO data register (PCFD0) needs to be read when the PEMP bit is "0". [bit7 to bit2]: Undefined bits CM71-10151-2E In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED 631 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit1, bit0]: PFS1, PFS0 (Priority conversion FIFO number setting bits) These bits specify the maximum number of stages in the A/D priority conversion FIFO. A priority conversion interrupt request can be issued when the number of stages storing conversion results reaches that maximum number during A/D priority conversion. The PCIF bit in an A/DC control register (ADCR0) changes to "1" when the number of stages storing such data reaches the maximum number of FIFO stages specified by these bits. 632 PFS1 PFS0 Explanation 0 0 First level 0 1 Second level 1 0 Third level 1 1 Fourth level FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.9 Priority Conversion FIFO Data Registers (PCFD0) These registers store A/D priority conversion results. Each register consists of 4 FIFO stages. FIFO data can be read sequentially from the registers. The bit configuration of these registers varies depending on the setting of the FDAS bit in the A/DC status registers (ADSR0). <Notes> • One of these registers must always be read after the PEMP bit in a priority conversion control register (PCCR0) is checked to determine whether data remains in the A/D priority conversion FIFO (PEMP = 0). If this register is read when the A/D priority conversion FIFO is empty (PEMP = 1), it is impossible to determine whether the read data is valid. For details, see "■ Operation of A/D priority conversion" in "24.6.3 FIFO Operations". • Do not perform word access to these registers. • In byte access to these registers, the low-order byte (bit7 to bit0) must be accessed before the high-order byte (bit15 to bit8). FIFO data is shifted after the high-order byte is read. ■ Left-justify (FDAS = 0) Figure 24.4-11 shows the bit configuration of the priority conversion FIFO data registers (PCFD0) when the FDAS bit in an A/DC status register (ADSR0) specifies left-justification (FDAS = 0). Figure 24.4-11 Bit configuration of the priority conversion FIFO data registers (PCFD0) bit 15 14 13 12 11 10 9 8 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 Attribute R R R R R R R R Initial value X X X X X X X X 7 6 5 4 3 2 1 0 PD1 PD0 RS PC4 PC3 PC2 PC1 PC0 Attribute R R R R R R R R Initial value X X X X X X X X bit R: Read only X: Undefined [bit15 to bit6]: PD9 to PD0 (A/D priority conversion result bits) These bits store A/D priority conversion results. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 633 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit5]: RS (Priority A/D activation trigger bit) This bit indicates whether the data stored in the PD9 to PD0 bits has been converted with priority 1 or 2 (activation trigger for A/D priority conversion). Read Value Explanation 0 Priority 2 (activation by software/base timer) 1 Priority 1 (activation by an external trigger) <Note> The activation trigger for A/D priority conversion of priority 2 cannot be distinguished as software or a base timer. [bit4 to bit0]: PC4 to PC0 (Conversion channel bits) These bits indicate the channel from which analog input has been converted and stored in the PD9 to PD0 bits. PC4 634 PC3 PC2 PC1 PC0 Explanation 0 0 0 0 0 ch.0 (AN0 pin) 0 0 0 0 1 ch.1 (AN1 pin) 0 0 0 1 0 ch.2 (AN2 pin) 0 0 0 1 1 ch.3 (AN3 pin) 0 0 1 0 0 ch.4 (AN4 pin) 0 0 1 0 1 ch.5 (AN5 pin) 0 0 1 1 0 ch.6 (AN6 pin) 0 0 1 1 1 ch.7 (AN7 pin) 0 1 0 0 0 ch.8 (AN8 pin) 0 1 0 0 1 ch.9 (AN9 pin) 0 1 0 1 0 ch.10 (AN10 pin) 0 1 0 1 1 ch.11 (AN11 pin) 0 1 1 0 0 ch.12 (AN12 pin) 0 1 1 0 1 ch.13 (AN13 pin) 0 1 1 1 0 ch.14 (AN14 pin) 0 1 1 1 1 ch.15 (AN15 pin) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series PC4 PC3 PC2 PC1 PC0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Explanation Setting prohibited <Note> A/D priority conversion of priority 1 can be performed only for ch.0 to ch.7. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 635 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series ■ Right-justify (FDAS = 1) Figure 24.4-12 shows the bit configuration of the priority conversion FIFO data registers (PCFD0) when the FDAS bit in an A/DC status register (ADSR0) specifies right-justification (FDAS = 1). Figure 24.4-12 Bit configuration of the Priority conversion FIFO data registers (PCFD0) bit 15 14 13 12 11 10 9 8 Undefined Undefined Undefined Undefined Undefined Undefined PD9 PD8 Attribute - - - - - - R R Initial value X X X X X X X X 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Attribute R R R R R R R R Initial value X X X X X X X X bit R: Read only -: Undefined X: Undefined [bit15 to bit10]: Undefined bits In case of writing Ignored In case of reading A value is undefined. [bit9 to bit0]: PD9 to PD0 (A/D priority conversion result bits) These bits store A/D priority conversion results. <Note> The activation trigger (priority) for A/D priority conversion and information on the converted channel are not stored in right-justify mode. Right-justification is used only when only either priority 1 or 2 of A/D priority conversion mode is used and when the converted result does not need the channel information, such as a conversion with 1 channel. 636 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.10 Priority Conversion Input Select Registers (PCIS0) These registers are used to select the channel to be subject to A/D priority conversion. 1 channel subject to conversion with priority 2 is selected from the 16 channels, and 1 channel subject to conversion with priority 1 is selected from ch.0 to ch.7. Figure 24.4-13 shows the bit configuration of the priority conversion input select registers (PCIS0). Figure 24.4-13 Bit configuration of the priority conversion input select registers (PCIS0) bit 7 6 5 4 3 2 1 0 P2A4 P2A3 P2A2 P2A1 P2A0 P1A2 P1A1 P1A0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 637 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit7 to bit3]: P2A4 to P2A0 (Priority 2 analog input select bit) These bits select the channel to be subject to A/D priority conversion of priority 2. Priority 2 < priority 1. P2A4 P2A3 P2A2 P2A1 P2A0 Explanation 0 0 0 0 0 ch.0 (AN0 pin) 0 0 0 0 1 ch.1 (AN1 pin) 0 0 0 1 0 ch.2 (AN2 pin) 0 0 0 1 1 ch.3 (AN3 pin) 0 0 1 0 0 ch.4 (AN4 pin) 0 0 1 0 1 ch.5 (AN5 pin) 0 0 1 1 0 ch.6 (AN6 pin) 0 0 1 1 1 ch.7 (AN7 pin) 0 1 0 0 0 ch.8 (AN8 pin) 0 1 0 0 1 ch.9 (AN9 pin) 0 1 0 1 0 ch.10 (AN10 pin) 0 1 0 1 1 ch.11 (AN11 pin) 0 1 1 0 0 ch.12 (AN12 pin) 0 1 1 0 1 ch.13 (AN13 pin) 0 1 1 1 0 ch.14 (AN14 pin) 0 1 1 1 1 ch.15 (AN15 pin) 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Setting prohibited 638 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit2 to bit0]: P1A2 to P1A0 (Priority 1 analog input select bit) These bits select the channel to be subject to A/D priority conversion of priority 1. A/D priority conversion of priority 1 can be performed only for ch.0 to ch.7. Priority 2 < priority 1. CM71-10151-2E P1A2 P1A1 P1A0 Explanation 0 0 0 ch.0 (AN0 pin) 0 0 1 ch.1 (AN1 pin) 0 1 0 ch.2 (AN2 pin) 0 1 1 ch.3 (AN3 pin) 1 0 0 ch.4 (AN4 pin) 1 0 1 ch.5 (AN5 pin) 1 1 0 ch.6 (AN6 pin) 1 1 1 ch.7 (AN7 pin) FUJITSU MICROELECTRONICS LIMITED 639 CHAPTER 24 10-Bit A/D Converter 24.4 24.4.11 MB91625 Series A/D Comparison Data Setting Registers (CMPD0) These registers are used to set the value that is compared with A/D conversion results when the comparison function is used. The eight high-order bits of the conversion results are compared with a value set in the registers. If the comparison result satisfies the requirements set in an A/D comparison control register (CMPCR0), the CMPIF bit in an A/DC control register (ADCR0) changes to "1". Figure 24.4-14 shows the bit configuration of the A/D comparison data setting registers (CMPD0). Figure 24.4-14 Bit configuration of the A/D comparison data setting registers (CMPD0) bit 7 6 5 4 3 2 1 0 CMAD9 CMAD8 CMAD7 CMAD6 CMAD5 CMAD4 CMAD3 CMAD2 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Note> A value that is set in these registers is compared with the eight high-order bits (bit9 to bit2) of A/D conversion results. The two bits (bit1, bit0) on the LSB side of A/D conversion results are not used for the comparison. 640 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.12 A/D Comparison Control Registers (CMPCR0) These registers control the comparison function. The comparison function is used when an A/D conversion result is compared with the value set in an A/D comparison data setting register (CMPD0). If the comparison result satisfies the requirements set in that register, the CMPIF bit in an A/DC control register (ADCR0) changes to "1". Figure 24.4-15 shows the bit configuration of the A/D comparison control registers (CMPCR0). Figure 24.4-15 Bit configuration of the A/D comparison control registers (CMPCR0) bit 7 6 5 4 3 2 1 0 CMPEN CMD1 CMD0 CCH4 CCH3 CCH2 CCH1 CCH0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value R/W: Read/Write [bit7]: CMPEN (Comparison function operation enable bit) This bit specifies whether to enable the comparison function. Written Value Explanation 0 Disables the comparison function. 1 Enables the comparison function. [bit6]: CMD1 (Comparison mode 1 bit) This bit sets the conversion interrupt request generation conditions. Written Value CM71-10151-2E Explanation 0 A conversion result interrupt request is generated when the A/D conversion result is smaller than the value set in an A/D comparison data setting register (CMPD0). 1 A conversion result interrupt request is generated when the A/D conversion result is equal to or greater than the value set in an A/D comparison data setting register (CMPD0). FUJITSU MICROELECTRONICS LIMITED 641 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit5]: CMD0 (Comparison mode 0 bit) This bit selects one of the following comparison modes: • Comparing the conversion result of the channel specified by the CCH4 to CCH0 bits with the value set in an A/D comparison data setting register (CMPD0) • Comparing the conversion results of all channels with the value set in an A/D comparison data setting register (CMPD0) Written Value Explanation 0 Compares the conversion result of the channel specified by the CCH4 to CCH0 bits. 1 Compares the conversion results of all channels. <Note> Writing "1" to this bit invalidates the settings of the CCH4 to CCH0 bits. 642 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit4 to bit0]: CCH4 to CCH0 (Comparison target analog input channel bits) These bits specify the channel to be compared with the value set in an A/D comparison data setting register (CMPD0) when the CMD0 bit is "0". CCH4 CCH3 CCH2 CCH1 CCH0 Explanation 0 0 0 0 0 ch.0 (AN0 pin) 0 0 0 0 1 ch.1 (AN1 pin) 0 0 0 1 0 ch.2 (AN2 pin) 0 0 0 1 1 ch.3 (AN3 pin) 0 0 1 0 0 ch.4 (AN4 pin) 0 0 1 0 1 ch.5 (AN5 pin) 0 0 1 1 0 ch.6 (AN6 pin) 0 0 1 1 1 ch.7 (AN7 pin) 0 1 0 0 0 ch.8 (AN8 pin) 0 1 0 0 1 ch.9 (AN9 pin) 0 1 0 1 0 ch.10 (AN10 pin) 0 1 0 1 1 ch.11 (AN11 pin) 0 1 1 0 0 ch.12 (AN12 pin) 0 1 1 0 1 ch.13 (AN13 pin) 0 1 1 1 0 ch.14 (AN14 pin) 0 1 1 1 1 ch.15 (AN15 pin) 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 Setting prohibited CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 643 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series CCH4 CCH3 CCH2 CCH1 CCH0 1 1 1 1 0 1 1 1 1 1 Explanation Setting prohibited <Note> If the CMD0 bit is set to "1" to compare the conversion results of all channels, the settings of these bits are ignored. 644 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.13 Sampling Time Setting Registers (ADST00, ADST10) These registers specify the sampling time, that is, the period from the start of A/D conversion until the beginning of input voltage sampling when the sampled voltage is held in the sample-and-hold circuit. The A/D conversion time is the total of the sampling time and compare time. 2 ADST registers are provided to set the sampling time. After the sampling time is set in each register, the sampling time select registers (ADSS10, ADSS00) can be used to specify the register that has the set sampling time to be used for each channel. Figure 24.4-16 shows the bit configuration of the sampling time setting registers (ADST00, ADST10). Figure 24.4-16 Bit configuration of the sampling time setting registers (ADST00, ADST10) Sampling time setting registers 00 (ADST00) bit 15 14 13 12 11 10 9 8 STX01 STX00 ST05 ST04 ST03 ST02 ST01 ST00 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 Attribute Initial value Sampling time setting registers 10 (ADST10) bit 7 6 5 4 3 2 1 0 STX11 STX10 ST15 ST14 ST13 ST12 ST11 ST10 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 Attribute Initial value R/W: Read/Write <Notes> • Write to these registers while A/D conversion is stopped. • For details of the sampling time, see "■ A/D conversion time" in "24.6 Explanation of Operations and Setting Procedure Examples". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 645 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series ● Sampling time setting registers 00 (ADST00) These registers set the first sampling time. [bit15, bit14]: STX01, STX00 (Sampling time Nx setting bit) These bits set a value (N) by which a value set in the ST05 to ST00 bits is multiplied. STX01 STX00 Explanation 0 0 Multiplies the value by 1. 0 1 Multiplies the value by 4. 1 0 Multiplies the value by 8. 1 1 Multiplies the value by 16. [bit13 to bit8]: ST05 to ST00 (Sampling time setting bit) These bits set the value used to determine the sampling time. A value that is set in these bits is used to determine the sampling time based on the following formula: Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX ST: Value set in the ST05 to ST00 bits STX: N (multiplier) set in the STX01 and STX00 bits Example: ST05 to ST00 = 9, STX01, STX00 = 01 (multiply by 4), peripheral clock (PCLK) = 20 MHz (50 ns) Sampling time = 50 ns × (9 + 1) × 4 = 2 μs <Notes> 646 • If "00" (multiply the setting value by 1) is set in the STX01 and STX00 bits, set "3" or a higher number in the ST05 to ST00 bits. • For details of the sampling time, see "■ A/D conversion time" in "24.6 Explanation of Operations and Setting Procedure Examples". • Sampling time setting registers 00 (ADST00) must be set such that the sampling time in the electrical characteristics is satisfied. For details of the electrical characteristics, see "Data Sheet". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series ● Sampling time setting register 10 (ADST10) These registers set the second sampling time. [bit7, bit6]: STX11, STX10 (Sampling time Nx setting bit) These bits set a value (N) by which a value set in the ST15 to ST10 bits is multiplied. STX11 STX10 Explanation 0 0 Multiplies the value by 1. 0 1 Multiplies the value by 4. 1 0 Multiplies the value by 8. 1 1 Multiplies the value by 16. [bit5 to bit0]: ST15 to ST10 (Sampling time setting bit) These bits set the value used to determine the sampling time. A value that is set in these bits is used to determine the sampling time based on the following formula: Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX ST: Value set in the ST15 to ST10 bits STX: N (multiplier) set in the STX11 and STX10 bits Example: ST15 to ST10 = 9, STX11, STX10 = 01 (multiply by 4), peripheral clock (PCLK) = 20 MHz (50 ns) Sampling time = 50 ns × (9 + 1) × 4 = 2 μs <Notes> • If "00" (multiply the setting value by 1) is set in the STX11 and STX10 bits, set "3" or a higher number in the ST15 to ST10 bits. • For details of the sampling time, see "■ A/D conversion time" in "24.6 Explanation of Operations and Setting Procedure Examples". • Sampling time setting registers 10 (ADST10) must be set such that the sampling time in the electrical characteristics is satisfied. For details of the electrical characteristics, see "Data Sheet". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 647 CHAPTER 24 10-Bit A/D Converter 24.4 24.4.14 MB91625 Series Sampling Time Select Registers (ADSS10, ADSS00) These registers are used to select the A/D sampling time. The sampling time to be used for each channel can be selected from that set in sampling time setting registers 00 (ADST00) or that set in sampling time setting registers 10 (ADST10). Figure 24.4-17 shows the bit configuration of the sampling time select registers (ADSS10, ADSS00). Figure 24.4-17 Bit configuration of the sampling time select registers (ADSS10, ADSS00) Sampling time select registers 10 (ADSS10) bit Attribute Initial value 7 6 5 4 3 2 1 0 TS15 TS14 TS13 TS12 TS11 TS10 TS9 TS8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Sampling time select registers 00 (ADSS00) bit Attribute Initial value 7 6 5 4 3 2 1 0 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W: Read/Write <Note> Write to these registers while A/D conversion is stopped. ADSS10, ADSS00: TS15 to TS0 (Sampling time selection bits) These bits specify for each channel whether to use the sampling time that is set in one of sampling time setting registers 00 (ADST00) or sampling time setting registers 10 (ADST10). Written Value Explanation 0 Use a sampling time that is set in sampling time setting registers 00 (ADST00). 1 Use a sampling time that is set in sampling time setting registers 10 (ADST10). The TS15 bit corresponds to ch.15 (AN15 pin), the TS14 bit corresponds to ch.14 (AN14 pin), ... the TS1 bit corresponds to ch.1 (AN1 pin), and the TS0 bit corresponds to ch.0 (AN0 pin). 648 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series 24.4.15 Compare Time Setting Registers (ADCT0) These registers set the compare time in the A/D conversion time. The A/D conversion time is the total of the sampling time and compare time. Figure 24.4-18 shows the bit configuration of the compare time setting registers (ADCT0). Figure 24.4-18 Bit configuration of the compare time setting registers (ADCT0) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined CT2 CT1 CT0 Attribute - - - - - R/W R/W R/W Initial value X X X X X 1 1 1 R/W: Read/Write -: Undefined X: Undefined <Note> Write to this register while A/D conversion is stopped. [bit7 to bit3]: Undefined bits CM71-10151-2E In case of writing Ignored In case of reading A value is undefined. FUJITSU MICROELECTRONICS LIMITED 649 CHAPTER 24 10-Bit A/D Converter 24.4 MB91625 Series [bit2 to bit0]: CT2 to CT0 (Compare time setting bits) These bits set the value used to determine the compare time. A value that is set in these bits is used to determine the compare time based on the following formula: Compare time = { (CT + 1) × 10 + 4} × peripheral clock (PCLK) period CT: Value set in these bits Example: CT = 1, peripheral clock (PCLK) = 20 MHz (50 ns) Compare time = {(1 + 1) × 10 + 4} × 50 ns = 1.2 μs <Note> For details of the compare time, see "■ A/D conversion time" in "24.6 Explanation of Operations and Setting Procedure Examples", 650 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.5 MB91625 Series 24.5 Interrupts An interrupt request can be generated in the following case(s): • Data has been stored in the predetermined number of stages in the FIFO during A/D scan conversion. (Scan conversion interrupt request) • Data has been stored in the predetermined number of stages in the FIFO during A/D priority conversion. (Priority conversion interrupt request) • An attempt has been made to save the next conversion result to a full FIFO. (FIFO overrun interrupt request) • The conversion result satisfies the interrupt request generation conditions when the comparison function is used. (Conversion result comparison interrupt request) ■ A/D scan conversion interrupt request Table 24.5-1 outlines the interrupt requests of A/D scan conversion. Table 24.5-1 Interrupt requests of A/D scan conversion Interrupt Request Interrupt Request Flag Interrupt Request Enabled Clearing of Interrupt Request Scan conversion interrupt request SCIF bit = 1 in an ADCR SCIE bit = 1 in an ADCR Write "0" to the SCIF bit in the ADCR. FIFO overrun interrupt request SOVR bit = 1 in an SCCR OVRIE bit = 1 in an ADCR Write "0" to the SOVR bit in the SCCR. Conversion result comparison interrupt request CMPIF bit = 1 in an ADCR CMPIE bit = 1 in an ADCR Write "0" to the CMPIF bit in the ADCR. ADCR: A/DC control register (ADCR0) SCCR: Scan conversion control register (SCCR0) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 651 CHAPTER 24 10-Bit A/D Converter 24.5 MB91625 Series ■ A/D priority conversion interrupt request Table 24.5-2 outlines the interrupt requests of A/D priority conversion. Table 24.5-2 Interrupt requests of A/D priority conversion Interrupt Request Interrupt Request Flag Interrupt Request Enabled Clearing of Interrupt Request Priority conversion interrupt request PCIF bit = 1 in an ADCR PCIE bit = 1 in an ADCR Write "0" to the PCIF bit in the ADCR. FIFO overrun interrupt request POVR bit = 1 in a PCCR OVRIE bit = 1 in an ADCR Write "0" to the POVR bit in the PCCR. Conversion result comparison interrupt request CMPIF bit = 1 in an ADCR CMPIE bit = 1 in an ADCR Write "0" to the CMPIF bit in the ADCR. ADCR: A/DC control register (ADCR0) PCCR: Priority conversion control register (PCCR0) <Notes> • If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt request is generated at the same time. Execute any of the following processing when enabling the generation of the interrupt requests: - Clear interrupt requests before enabling the generation of interrupt requests. - Clear interrupt requests simultaneously with interrupts enabled. • For the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors". • Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10 Interrupt Controller". ■ Activating DMA transfer upon an interrupt DMA transfer can be activated when one of the following interrupt requests is generated: • Scan conversion interrupt request • Priority conversion interrupt request For details of DMA transfer, see "24.6.4 Activating the DMA Controller (DMAC)". 652 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series 24.6 Explanation of Operations and Setting Procedure Examples This section explains the operations of the 10-bit A/D converter. Also, examples of procedures for setting the operating state are shown. ■ Overview The 10-bit A/D converter enables A/D conversion by allowing analog signal input from the pin corresponding to each bit in the A/D channel enable register (ADCHE). For details of the A/D channel enable register (ADCHE), see "13.4.6 A/D Channel Enable Register (ADCHE)" in "CHAPTER 13 I/O Ports". The 10-bit A/D converter performs the following two types of conversion: • A/D scan conversion Any selected channel is converted. Two conversion modes are available. One is single conversion mode in which the signals from the selected channel are converted only once, and the other is repeat conversion mode in which the signals from the selected channel are converted repeatedly. • A/D priority conversion High-priority A/D conversion is performed soon after an activation trigger for the conversion is generated, because the trigger stops A/D scan conversion. The two priority levels are priority 1 and priority 2. Priority 1 > priority 2. Table 24.6-1 summarizes the differences between A/D scan conversion and A/D priority conversion. Table 24.6-1 Differences between A/D scan conversion and A/D priority conversion A/D Scan Conversion CM71-10151-2E A/D Priority Conversion Priority 1 Priority 2 Supported channels Up to 16 channels are selected arbitrarily from all 16 channels. 1 channel is selected from ch.0 to ch.7 1 channel is selected from the 16 channels. Conversion activation trigger Software Detection of a rising edge of the TOUT signal of base timer ch.0 Detection of a falling edge at the ADTRG0 pin Software Detection of a rising edge of the TOUT signal of base timer ch.2 Restart Enabled Disabled FIFO 16 levels 4 levels FUJITSU MICROELECTRONICS LIMITED 653 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ Priority and state transition Table 24.6-2 lists A/D conversion priorities. Table 24.6-2 A/D conversion priority Priority A/D Conversion Type 1 A/D priority conversion of priority 1 2 A/D priority conversion of priority 2 3 A/D scan conversion If A/D conversion of a different priority is activated while A/D conversion is already in progress, operations are performed as follows: • The A/D conversion activated while A/D conversion is already in progress has a higher priority. The A/D conversion in progress is stopped and the A/D conversion of the higher priority is executed. After the higher-priority conversion is completed, the stopped A/D conversion is restarted. Example: An A/D priority conversion activation trigger is generated during A/D scan conversion The A/D scan conversion is interrupted, and A/D priority conversion begins. After the A/D priority conversion is completed, the A/D scan conversion resumes from the channel at which it interrupted. Example: An activation trigger for A/D priority conversion of priority 1 is generated during A/D priority conversion of priority 2. The A/D priority conversion of priority 2 is interrupted, and the A/D priority conversion of priority 1 begins. After the A/D priority conversion of priority 1 is completed, the A/D priority conversion of priority 2 resumes. • The A/D conversion activated while A/D conversion is already in progress has a lower priority. The activation trigger for the A/D conversion of a lower priority is held, and the A/D conversion in progress is executed continuously. After the A/D conversion in progress is completed, the A/D conversion whose activation trigger has been held begins automatically. Example: An activation trigger for A/D priority conversion of priority 2 is generated during A/D priority conversion of priority 1. The activation trigger for the A/D priority conversion of priority 2 is held, and the A/D priority conversion of priority 1 is executed continuously. After the A/D priority conversion of priority 1 is completed, the A/D priority conversion of priority 2 begins automatically. Example: An activation trigger for A/D scan conversion is generated during A/D priority conversion of priority 1. The activation trigger for the A/D scan conversion is held, and the A/D priority conversion of priority 1 is executed continuously. After the A/D priority conversion of priority 1 is completed, the A/D scan conversion begins automatically. Example: An activation trigger for A/D scan conversion is generated during A/D priority conversion of priority 2. The activation trigger for the A/D scan conversion is held, and the A/D priority conversion of priority 2 is executed continuously. After the A/D priority conversion of priority 2 is completed, the A/D scan conversion begins automatically. 654 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series • The A/D conversion activated during A/D priority conversion has the same priority. An activation trigger with the same priority is ignored. (The ignored activation trigger will not be reactivated.) Figure 24.6-1 show state transitions of the 10-bit A/D converter. Figure 24.6-1 State transitions of the 10-bit A/D converter 000 Waiting for conversion Scan conversion request End of scan conversion 001 A/D scan conversion in progress Priority conversion request End of priority conversion A/D priority conversion in progress Scan conversion request Priority conversion request End of priority conversion 010 011 A/D priority conversion in progress A/D scan conversion suspended End of priority 1 conversion End of priority 1 conversion 110 Priority 1 conversion in progress Priority 2 conversion suspended Priority conversion request 111 Priority 1 conversion in progress Priority 2 conversion suspended A/D scan conversion suspended Priority conversion request Scan conversion request As shown in Figure 24.6-1, the states of the 10-bit A/D converter can be checked with the PCNS, PCS, and SCS bits in the A/DC status registers (ADSR0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 655 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Table 24.6-3 shows the relationship between bits and operating states. Table 24.6-3 Relationship between bits and operating states PCNS PCS SCS Explanation 0 0 0 Waiting for conversion 0 0 1 A/D scan conversion in progress 0 1 0 A/D priority conversion in progress 0 1 1 A/D priority conversion in progress, with A/D scan conversion suspended 1 1 0 Priority 1 A/D priority conversion in progress, with priority 2 conversion suspended 1 1 1 Priority 1 A/D priority conversion in progress, with priority 2 conversion and scan conversion suspended ■ Operation using the A/D comparison function The A/D comparison function compares the eight high-order bits (bit9 to bit2) of A/D conversion results with a preset value in the A/D comparison data setting registers (CMPD0). If the comparison result satisfies the requirements set in an A/D comparison control register (CMPCR0), the function generates a conversion result comparison interrupt request. The CMPEN bit must be set to "1" in the A/D comparison control register (CMPCR0) to enable the comparison function before conversion is started. The comparison function can be used even with a full FIFO because a comparison is made before A/D conversion results are stored in the FIFO. For details of the comparison function, see "24.4.11 A/D Comparison Data Setting Registers (CMPD0)", and "24.4.12 A/D Comparison Control Registers (CMPCR0)". 656 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ A/D conversion time The A/D conversion time is the total of the sampling time and compare time. To determine the A/D conversion time, add the sampling time and compare time. ● Sampling time The sampling time can be set in each of the sampling time setting registers (ADST00, ADST10). The sampling time select register (ADSS10, ADSS00) can be used to specify the register that has the set sampling time to be used for each channel. Therefore, the sampling time can be set individually for channels with different external impedances. The formula for calculating the sampling time is as follows: Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX ST: Value that is set in the ST05 to ST00/ST15 to ST10 bits in a sampling time setting register (ADST00, ADST10) STX: Multiplier that is set in the STX01, STX00/STX11, and STX10 bits in a sampling time setting register (ADST00, ADST10) <Notes> • If "00" (multiply the setting value by 1) is set in the STX01 and STX00 bits, set "3" or a higher number in the ST05 to ST00/ST15 to ST10 bits. • Sampling time setting registers 00 (ADST00) must be set so that the sampling time in the electrical characteristics is satisfied. For details of the electrical characteristics, see "Data Sheet". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 657 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Table 24.6-4 and Table 24.6-5 show sampling time setting examples. Table 24.6-4 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 00) (1 / 2) Register value (N) 658 Sampling Time [µs] Maximum External Impedance [kΩ] STx5 to STx0 PCLK= 30MHz PCLK= 32MHz PCLK= 33MHz PCLK= 30MHz 0 Setting prohibited Setting prohibited Setting prohibited - - - 1 Setting prohibited Setting prohibited Setting prohibited - - - 2 Setting prohibited Setting prohibited Setting prohibited - - - 3 Setting prohibited Setting prohibited Setting prohibited - - - 4 Setting prohibited Setting prohibited Setting prohibited - - - 5 Setting prohibited Setting prohibited Setting prohibited - - - 6 Setting prohibited Setting prohibited Setting prohibited - - - 7 Setting prohibited Setting prohibited Setting prohibited - - - 8 Setting prohibited Setting prohibited Setting prohibited - - - 9 Setting prohibited Setting prohibited Setting prohibited - - - 10 Setting prohibited Setting prohibited Setting prohibited - - - 11 0.400 Setting prohibited Setting prohibited 1.400 - - 12 0.433 0.406 Setting prohibited 1.400 1.400 - 13 0.467 0.438 0.424 1.563 1.400 1.400 14 0.500 0.469 0.455 2.053 1.593 1.400 15 0.533 0.500 0.485 2.543 2.053 1.830 16 0.567 0.531 0.515 3.033 2.513 2.276 17 0.600 0.563 0.545 3.524 2.972 2.721 18 0.633 0.594 0.576 4.014 3.432 3.167 19 0.667 0.625 0.606 4.504 3.891 3.613 20 0.700 0.656 0.636 4.994 4.351 4.058 FUJITSU MICROELECTRONICS LIMITED PCLK= 32MHz PCLK= 33MHz CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Table 24.6-4 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 00) (2 / 2) Register value (N) STx5 to STx0 Sampling Time [µs] PCLK= 30MHz PCLK= 32MHz Maximum External Impedance [kΩ] PCLK= 33MHz PCLK= 30MHz PCLK= 32MHz PCLK= 33MHz ... ... ... ... ... ... ... 36 1.233 1.156 1.121 12.837 11.704 11.188 37 1.267 1.188 1.152 13.327 12.163 11.634 38 1.300 1.219 1.182 13.818 12.623 12.080 ... ... ... ... ... ... ... 42 1.433 1.344 1.303 15.778 14.461 13.862 43 1.467 1.375 1.333 16.269 14.921 14.308 ... ... ... ... ... ... ... 52 1.767 1.656 1.606 20.680 19.057 18.319 53 1.800 1.688 1.636 21.171 19.516 18.764 ... ... ... ... ... ... ... 62 2.100 1.969 1.909 25.582 23.652 22.775 63 2.133 2.000 1.939 26.073 24.112 23.220 PCLK : peripheral clock (PCLK) frequency CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 659 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Table 24.6-5 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 10) (1 / 2) Register Value (N) STx5 to STx0 0 Maximum External Impedance [kΩ] PCLK= 30MHz PCLK= 32MHz PCLK= 33MHz PCLK= 30MHz Setting prohibited Setting prohibited Setting prohibited - PCLK= 32MHz - PCLK= 33MHz - 1 0.533 0.500 0.485 2.543 2.053 1.830 2 0.800 0.750 0.727 6.465 5.729 5.395 3 1.067 1.000 0.970 10.386 9.406 8.960 4 1.333 1.250 1.212 14.308 13.082 12.525 5 1.600 1.500 1.455 18.229 16.759 16.090 6 1.867 1.750 1.697 22.151 20.435 19.655 7 2.133 2.000 1.939 26.073 24.112 23.220 8 2.400 2.250 2.182 29.994 27.788 26.786 9 2.667 2.500 2.424 33.916 31.465 30.351 10 2.933 2.750 2.667 37.837 35.141 33.916 11 3.200 3.000 2.909 41.759 38.818 37.481 12 3.467 3.250 3.152 45.680 42.494 41.046 13 3.733 3.500 3.394 49.602 46.171 44.611 14 4.000 3.750 3.636 53.524 49.847 48.176 15 4.267 4.000 3.879 57.445 53.524 51.741 16 4.533 4.250 4.121 61.367 57.200 55.306 17 4.800 4.500 4.364 65.288 60.876 58.871 18 5.067 4.750 4.606 69.210 64.553 62.436 19 5.333 5.000 4.848 73.131 68.229 66.001 20 5.600 5.250 5.091 77.053 71.906 69.566 ... ... ... ... ... ... ... 36 9.867 9.250 8.970 139.798 130.729 126.607 37 10.133 9.500 9.212 143.720 134.406 130.172 38 10.400 9.750 9.455 147.641 138.082 133.737 ... ... ... ... ... ... ... 42 11.467 10.750 10.424 163.327 152.788 147.998 43 11.733 11.000 10.667 167.249 156.465 151.563 ... 660 Sampling Time [µs] ... ... ... ... FUJITSU MICROELECTRONICS LIMITED ... ... CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Table 24.6-5 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 10) (2 / 2) Register Value (N) Sampling Time [µs] Maximum External Impedance [kΩ] STx5 to STx0 PCLK= 30MHz PCLK= 32MHz PCLK= 33MHz PCLK= 30MHz PCLK= 32MHz PCLK= 33MHz 52 14.133 13.250 12.848 202.543 189.553 183.648 53 14.400 13.500 13.091 206.465 193.229 187.213 ... ... ... ... ... ... ... 62 16.800 15.750 15.273 241.759 226.318 219.299 63 17.067 16.000 15.515 245.680 229.994 222.864 PCLK : peripheral clock (PCLK) frequency CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 661 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ● Compare time The compare time setting registers (ADCT0) specify the compare time. The formula for calculating the compare time is as follows: Compare time = { (CT + 1) × 10 + 4} × peripheral clock (PCLK) period CT: Value that is set in the CT2 to CT0 bits in a compare time setting register (ADCT0) Table 24.6-6 shows a compare time setting example. Table 24.6-6 Compare time setting example Register Value (N) CT2 to CT0 Compare Time PCLK = 30 MHz PCLK = 32 MHz PCLK = 33 MHz 0 Setting prohibited Setting prohibited Setting prohibited 1 0.80 μs 0.75 μs 0.73 μs 2 1.13 μs 1.06 μs 1.03 μs 3 1.47 μs 1.38 μs 1.33 μs 4 1.80 μs 1.69 μs 1.64 μs 5 2.13 μs 2.00 μs 1.94 μs 6 2.47 μs 2.31 μs 2.24 μs 7 (initial value) 2.80 μs 2.63 μs 2.55 μs PCLK peripheral clock (PCLK) frequency * This table covers only compare time data. 662 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series 24.6.1 Operation of A/D Scan Conversion Channels are selected by the scan conversion input select registers (SCIS10, SCIS00) sequentially. ■ Overview A/D scan conversion is performed in one of the following two conversion modes: • Single conversion mode The channel specified by a scan conversion input select register (SCIS10, SCIS00) is converted only once. • Repeat conversion mode The channel specified by a scan conversion input select register (SCIS10, SCIS00) is converted repeatedly. Also, the operation that is performed varies depending on whether only one channel is selected or multiple channels are selected with a scan conversion input select register (SCIS10, SCIS00). Table 24.6-7 shows the order of conversion in each conversion mode. Table 24.6-7 Conversion mode and order of conversion Conversion Mode Selected Channel Conversion Order Single conversion mode (RPT bit = 0 in an SCCR) ch.3 ch.3 → conversion stopped ch.3, ch.5, ch.10, ch.15 ch.3 → ch.5 → ch.10 → conversion stopped Repeat conversion mode (RPT bit = 1 in an SCCR) ch.3 ch.3 → ch.3 → ch.3 → ch.3 ↑ ↓ ch.3 ← ch.3 ← ch.3 ← ch.3 ch.3, ch.5, ch.10, ch.15 ch.3 → ch.5 → ch.10 → ch.15 ↑ ↓ ch.15 ← ch.10 ← ch.5 ← ch.3 ch.15 → SCCR: scan conversion control register (SCCR0) <Note> The 10-bit A/D converter enables A/D conversion by allowing analog signal input with the A/D channel enable register (ADCHE). For details of the A/D channel enable register (ADCHE), see "13.4.6 A/D Channel Enable Register (ADCHE)" in "CHAPTER 13 I/O Ports". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 663 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ Operation in single conversion mode Writing "0" to the RPT bit in a scan conversion control register (SCCR0) sets single conversion mode. In this mode, the channel specified by a scan conversion input select register (SCIS10, SCIS00) is converted only once. ● Activation The channel to be converted is selected with the scan conversion input select register (SCIS10, SCIS00) in one of the following ways, and the 10-bit A/D converter is then activated: • Write "1" to the SSTR bit in a scan conversion control register (SCCR0). • Set the SHEN bit in a scan conversion control register (SCCR0) to enable timer activation (SHEN = 1), and input the rising edge of a TOUT signal of base timer ch.0. If either of the above activation operations is performed during A/D scan conversion, the A/D scan conversion is immediately stopped/initialized, and the A/D scan conversion resumes later (reactivated). ● Single-channel conversion Only one channel to be converted is selected with a scan conversion input select register (SCIS10, SCIS00). When started, the 10-bit A/D converter activates the conversion operation for the selected channel, and the SCS bit in an A/DC status register (ADSR0) changes to "1". After the conversion of the selected channel is completed, the conversion result and information on the converted channel are stored in the first level of the A/D scan conversion FIFO, and the conversion operation is then stopped. Then, the SCS bit in the A/DC status register (ADSR0) is cleared to "0". The conversion results stored in the FIFO can be read from a scan conversion FIFO data register (SCFD0). ● Multichannel conversion Two or more channels to be converted are selected with a scan conversion input select register (SCIS10, SCIS00). When started, the 10-bit A/D converter begins converting the selected channels in ascending order of channel number. The SCS bit in an A/DC status register (ADSR0) then changes to "1". After the conversion of one channel is completed, the conversion results and information on the converted channel are stored in the first level of the A/D scan conversion FIFO, and the converter then begins converting the next channel. The channels not selected by the scan conversion input select register (SCIS10, SCIS00) remain unconverted. In the A/D scan conversion FIFO, the number of stages storing conversion results and information on each converted channel is changed every time the channel subject to conversion changes. The 10-bit A/D converter stops operating after converting on all the channels selected by the scan conversion input select register (SCIS10, SCIS00). Then, the SCS bit in the A/DC status register (ADSR0) is cleared to "0". The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data register (SCFD0). For details of reading, see "■ Operation of A/D scan conversion" in "24.6.3 FIFO Operations". 664 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ Operation in repeat conversion mode Writing "1" to the RPT bit in a scan conversion control register (SCCR0) enables single conversion mode. In this mode, the channel specified by a scan conversion input select register (SCIS10, SCIS00) is converted repeatedly. As in single conversion mode, to activate the 10-bit A/D converter, select a channel. ● Single-channel conversion Only one channel to be converted is selected with a scan conversion input select register (SCIS10, SCIS00). When started, the 10-bit A/D converter activates the conversion operation for the selected channel, and the SCS bit in an A/DC status register (ADSR0) changes to "1". After the conversion of the selected channel is completed, the conversion results and information on the converted channel are stored in the first level of the A/D scan conversion FIFO, and conversion of the same channel is then repeated. To stop conversion, write "0" to a scan conversion control register (SCCR0). The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data register (SCFD0). For details of reading conversion results, see "■ Operation of A/D scan conversion" in "24.6.3 FIFO Operations". ● Multichannel conversion Two or more channels to be converted are selected with a scan conversion input select register (SCIS10, SCIS00). When activated, the 10-bit A/D converter begins converting on the selected channels sequentially in ascending order of channel number. The SCS bit in an A/DC status register (ADSR0) then changes to "1". After the conversion of one channel is completed, the conversion results and information on the converted channel are stored in the first level of the A/D scan conversion FIFO, and the converter then begins converting the next channel. The channels not selected by the scan conversion input select register (SCIS10, SCIS00) remain unconverted. After conversion of all the selected channels is completed, the second round of conversion begins for the channels sequentially in ascending order of channel number. To stop conversion, write "0" in the RPT bit of the scan conversion control register (SCCR0). Conversion stops when all channels selected by the scan conversion input select register (SCIS10, SCIS00) have been converted. Figure 24.6-2 shows the stop timing in multichannel conversion. Figure 24.6-2 Stop timing in multichannel conversion RPT bit SSTR bit Conversion channel Stop ch.0 ch.4 ch.8 ch.15 ch.0 ch.4 ch.8 ch.15 Stop The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data register (SCFD0). For details of reading, see "■ Operation of A/D scan conversion" in "24.6.3 FIFO Operations". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 665 CHAPTER 24 10-Bit A/D Converter 24.6 24.6.2 MB91625 Series Operation of A/D Priority Conversion High-priority A/D conversion is performed soon after an activation trigger for the conversion is generated, because the trigger stops A/D scan conversion. There are two priority levels. ■ Overview Two priority levels can be selected depending on the activation trigger. Priority 1 has a higher priority than priority 2. The channels that can be set vary depending on the priority. Table 24.6-8 shows the relationship among priorities, channels, and activation triggers. Table 24.6-8 Relationship among, priorities, channels, and activation triggers Priority 1 Priority 2 Priority 1 2 Supported channel 1 channel is selected from ch.0 to ch.7 1 channel is selected from the 16 channels. Activation trigger Detection of a falling edge at the ADTRG0 pin Software Detection of a rising edge of the TOUT signal of base timer ch.2 <Notes> • The 10-bit A/D converter enables A/D conversion by allowing analog signal input with the A/D channel enable register (ADCHE). For details of the A/D channel enable register (ADCHE), see "13.4.6 A/D Channel Enable Register (ADCHE)" in "CHAPTER 13 I/O Ports". 666 • A/D conversion can be reactivated regardless of priority after A/D priority conversion. • Only one channel can be converted in A/D priority conversion. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ Conversion with priority 1 This conversion has the highest priority. When an activation trigger with priority 1 is generated, any A/D scan conversion or A/D priority conversion that is in progress is immediately stopped, and the conversion with priority 1 begins. ● Selecting a channel Only one channel is selected from ch.0 to ch.7 and set in the P1A2 to P1A0 bits in a priority conversion input select register (PCIS0). ● Conversion An activation trigger for A/D priority conversion of priority 1 is generated when a falling edge is detected at the ADTRG0 pin after the PEEN bit in a priority conversion control register (PCCR0) is set to "1" to enable external activation. If A/D scan conversion or A/D priority conversion of priority 2 is in progress, it is immediately interrupted, and conversion of the specified channel with priority 1 begins. The PCS bit in an A/DC status register (ADSR0) then changes to "1". After the conversion is completed, the conversion results and information on the channel subject to conversion are stored in the FIFO for A/D priority conversion, and the PCS bit in the A/DC status register (ADSR0) is cleared to "0". The interrupted conversion is then restarted. The A/D priority conversion results stored in the FIFO can be read from a priority conversion FIFO data register (PCFD0). For details of reading, see "■ Operation of A/D priority conversion" in "24.6.3 FIFO Operations". For details of the operation performed when an activation trigger with a different priority is generated while A/D priority conversion of priority 1 is in progress, see "■ Priority and state transition in "24.6 Explanation of Operations and Setting Procedure Examples". <Note> If an activation trigger for A/D conversion of the same level (priority 1) is generated while A/D priority conversion of priority 1 is in progress, the conversion in progress is continued and the new activation trigger is ignored. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 667 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ■ Conversion with priority 2 This conversion has the second highest priority. When an activation trigger of priority 2 is generated, any A/D scan conversion in progress is immediately stopped, and the conversion with priority 2 begins. ● Selecting a channel Only one channel to be converted is selected from all 16 channels and set in the P2A4 to P2A0 bits in a priority conversion input select register (PCIS0). ● Conversion An activation trigger with priority 2 is generated in one of the following ways: • Write "1" to the PSTR bit in a priority conversion control register (PCCR0). • A rising edge of the TOUT signal of base timer ch.2 is detected after the PHEN bit in the priority conversion control register (PCCR0) is set to "1" to enable timer activation. When an activation trigger is generated, A/D priority conversion of priority 2 is activated and the PCS bit in an A/DC status register (ADSR0) changes to "1" as follows: • If the 10-bit A/D converter is not activated: The 10-bit A/D converter is activated to start conversion of the specified channel with priority 2. • If A/D scan conversion is in progress: The A/D scan conversion in progress is immediately interrupted, and conversion of the specified channel with priority 2 begins. • If A/D priority conversion of priority 1 is in progress: The activation trigger with priority 2 is held, and A/D priority conversion of priority 2 is started after A/D priority conversion of priority 1 is completed. After A/D priority conversion of priority 2 is completed, the conversion results and information on the channel subject to conversion are stored in the FIFO for A/D priority conversion, and the PCS bit in an A/DC status register (ADSR0) is cleared to "0". The interrupted conversion is then restarted. The A/D priority conversion results stored in the FIFO can be read from a priority conversion FIFO data register (PCFD0). For details of reading, see "■ Operation of A/D priority conversion" in "24.6.3 FIFO Operations". For details of the operation performed when an activation trigger with a different priority is generated while A/D priority conversion of priority 2 is in progress, see "■Priority and state transition in "24.6 Explanation of Operations and Setting Procedure Examples". <Note> No conversion operation can be reactivated during A/D priority conversion. If an activation trigger for A/D conversion of the same level (priority 2) is generated while A/D priority conversion of priority 2 is in progress, the conversion in progress is continued and the new activation trigger is ignored. Example: The rising edge of a TOUT signal of base timer ch.2 may be detected after A/D priority conversion of priority 2 is activated by software. Even in this event, the conversion operation in progress is continued. 668 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series 24.6.3 FIFO Operations The 10-bit A/D converter provides 16 FIFO stages for A/D scan conversion and 4 FIFO levels for A/D priority conversion. A scan conversion interrupt request/priority conversion interrupt request can be generated when the number of stages storing the respective data reaches the predetermined number of FIFO stages. This section explains FIFO operations and generation of interrupt requests. ■ Operation of A/D scan conversion ● Operation during A/D conversion The SEMP bit in a scan conversion control register (SCCR0) is "1", because the FIFO for A/D scan conversion contains no data (empty) after a reset is released. The SEMP bit changes to "0" when A/D scan conversion begins, and conversion results for 1 channel are stored in the first FIFO stage. After conversion of the next data is completed, the conversion results are stored in the second FIFO stage. Every time that conversion of 1 channel is completed after that, the conversion results are stored in the subsequent FIFO stage. After conversion results are written to all 16 FIFO levels, the A/D scan conversion FIFO becomes full and the SFUL bit in the scan conversion control register (SCCR0) changes to "1". If A/D scan conversion is performed again in this state, an overrun occurs and the SOVR bit in the scan conversion control register (SCCR0) changes to "1". In this event, the conversion results are not stored in the FIFO but abandoned. ● Read operation Data stored in the A/D scan conversion FIFO can be read sequentially through reading with a scan conversion FIFO data register (SCFD0). A scan conversion FIFO data register (SCFD0) must always be read after the SEMP bit in a scan conversion control register (SCCR0) is checked to determine whether data remains in the A/D scan conversion FIFO (SEMP = 0). If an empty A/D scan conversion FIFO is read (SEMP = 1), it is difficult to determine whether the read data is valid, and valid data may be abandoned. (This is because conversion results may be stored in a scan conversion FIFO data register (SCFD0) immediately before the FIFO is read.) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 669 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Figure 24.6-3 shows the relationship between the SEMP bit and read data. Figure 24.6-3 Relationship between the SEMP bit and read data SEMP bit Peripheral bus Valid FIFO stage number SEMP bit reading SCFD reading It is possible to determine that the read data is valid because the value read from the previous SEMP bit is "0". 1 SEMP bit reading 0 SCFD reading 1 It is impossible to determine whether the read data is valid because the value read from the previous SEMP bit is "1". 0 New FIFO data is stored. SCFD: A/D scan conversion FIFO data register (SCFD0) <Notes> • The registers listed below are located at adjacent addresses. If these registers are accessed at one time by word access, the registers are read regardless of the setting of the SEMP bit in a scan conversion control register (SCCR0). Do not execute word access to these registers. - Scan conversion control register (SCCR0) - Scan conversion FIFO number setting register (SFNS0) - Scan conversion FIFO data register (SCFD0) • The scan conversion FIFO data registers (SCFD0) can be byte-accessed. FIFO data is shifted after the high-order byte (bit15 to bit8) is read. FIFO data will not be shifted by reading of the lower-order byte (bit7 to bit0). ● Clear operation Writing "1" to the SFCLR bit in a scan conversion control register (SCCR0) clears the FIFO for A/D scanning conversion and changes the SEMP bit in the scan conversion control register (SCCR0) to "1". ● Scan conversion interrupt request A scan conversion interrupt request can be generated when the number of stages storing conversion results reaches the specified number of FIFO stages (SCIF bit = 1 in an A/DC control register (ADCR0)). To generate an A/D scan conversion interrupt request, perform the following processing: 670 • Decide the number of FIFO stages at which an interrupt request is generated, and set the number in the SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0). • Set the SCIE bit in an A/DC control register (ADCR0) to "1" to enable generation of scan conversion interrupt requests. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series Figure 24.6-4 shows FIFO operations. Figure 24.6-4 FIFO operations Valid FIFO stage number FIFO stage number setting SFS3 to SFS0 = 0101 (6 stages) SFS3 to SFS0 = 0011 (4 stages) Interrupt request clearing Scan conversion interrupt request Interrupt request clearing FIFO reading A/D conversion Stop 1 2 3 4 5 6 Stop 1 2 3 4 5 6 Stop 1 Stop The interrupt request generation examples shown below indicate the number of FIFO stages that is set for each conversion mode. The number of FIFO stages must be set in the SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0). • Single channel conversion in single conversion mode If the number of FIFO stages at which a scan conversion interrupt request is generated is set at 1 (SFS3 to SFS0 = 0000), a scan conversion interrupt request is generated when conversion is completed. If the number of FIFO stages is set at 2 or more (SFS3 to SFS0 = 0001 or higher), an interrupt request is not generated even after conversion of the specified channel is completed. • Multichannel conversion in single conversion mode If the set number of FIFO stages is the same as the number of channels to be subject to conversion, a scan conversion interrupt request is generated at the end of conversion. Example: Generation of a scan conversion interrupt request after conversion of 3 channels Set 3 (SFS3 to SFS0 = 0010) for the number of FIFO stages at which a scan conversion interrupt request is generated. Settings can be made such that a scan conversion interrupt request is generated at a number of FIFO stages that is less than the number of the channels to be subject to conversion. In such cases, a scan conversion interrupt request can be generated at any time before the end of A/D scan conversion. • Single channel conversion in repeat conversion mode If the number of FIFO stages at which a scan conversion interrupt request is generated is set at 1 (SFS3 to SFS0 = 0000), a scan conversion interrupt request is generated when the first round of conversion is completed. To generate a scan conversion interrupt request after converting on the specified channel a certain number of times, match the conversion count to the number of FIFO stages. Example: Generation of a scan conversion interrupt request after conversion on a single channel is performed 4 times Set 4 (SFS3 to SFS0 = 0011) for the number of FIFO stages at which a scan conversion interrupt request is generated. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 671 CHAPTER 24 10-Bit A/D Converter 24.6 • MB91625 Series Multichannel conversion in repeat conversion mode The desired generation time for scan conversion interrupt requests can be selected as shown below. Example: Conversion of 8 channels in repeat conversion mode - Generate a scan conversion interrupt request after the end of the first round of conversion. Set 8 (SFS3 to SFS0 = 0111) for the number of FIFO stages at which a scan conversion interrupt request is generated. - Generate an interrupt request after the end of the second round of conversion. Set 16 (twice the number of channels to be subject to conversion) (SFS3 to SFS0 = 1111) for the number of FIFO stages at which a scan conversion interrupt request is generated. <Note> DMA transfer of the data in the FIFO can be performed when a scan conversion interrupt request is generated. For details of DMA transfer, see "24.6.4 Activating the DMA Controller (DMAC)". ● FIFO overrun interrupt request When data has been stored in all 16 FIFO levels and the FIFO becomes full, the SFUL bit in a scan conversion control register (SCCR0) changes to "1". Also, the OVRIE bit in an A/DC control register (ADCR0) can be set to enable generation of FIFO overrun interrupt requests (OVRIE = 1). In this state, if an attempt is made to store the next conversion result in the FIFO when the SFUL bit is "1", an overrun interrupt is generated. <Notes> • The data in the FIFO cannot be rewritten, even by the attempt to store the next conversion result in the full FIFO. The conversion result to be stored in this attempt is abandoned. • The FIFO is emptied and the SEMP bit in a scan conversion control register (SCCR0) changes to "1" when the SFCLR bit in the scan conversion control register (SCCR0) is set to "1" to clear the FIFO. ■ Operation of A/D priority conversion ● Operation during A/D conversion The PEMP bit in an A/D priority conversion control register (PCCR0) is "1", because the FIFO for A/D scan conversion contains no data (empty) after a reset is released. The PEMP bit changes to "0" when A/D priority conversion begins, and conversion results for 1 channel are stored in the first FIFO stage. After the next A/D priority conversion is completed, the conversion results are stored in the second FIFO level. Every time that A/D priority conversion is completed after that, the conversion results are stored in the subsequent FIFO stage. After conversion results are written to all 4 FIFO levels, the FIFO for A/D priority conversion becomes full and the PFUL bit in the priority conversion control register (PCCR0) changes to "1". If A/D priority conversion is performed again in this state, an overrun occurs and the POVR bit in the priority conversion control register (PCCR0) changes to "1". In this event, the conversion results are not stored in the FIFO but abandoned. 672 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ● Read operation Data stored in the A/D priority conversion FIFO can be read sequentially through reading with a priority conversion FIFO data register (PCFD0). A priority conversion FIFO data register (PCFD0) must always be read after the PEMP bit in a priority conversion control register (PCCR0) is checked to determine whether data remains in the A/D priority conversion FIFO (PEMP = 0). If an empty A/D priority conversion FIFO is read (PEMP = 1), it is difficult to determine whether the read data is valid, and valid data may be abandoned. (This is because conversion results may be stored in a priority conversion FIFO data register (PCFD0) immediately before the FIFO is read.) Figure 24.6-5 shows the relationship between the PEMP bit and read data. Figure 24.6-5 Relationship between the PEMP bit and read data PEMP bit Peripheral bus Valid FIFO stage number PEMP bit reading PCFD reading It is possible to determine that the read data is valid because the value read from the previous PEMP bit is "0". 1 PEMP bit reading 0 PCFD reading 1 It is impossible to determine whether the read data is valid because the value read from the previous PEMP bit is "1". 0 New FIFO data is stored. PCFD: A/D priority conversion FIFO data register (PCFD0) <Notes> • The registers listed below are located at adjacent addresses. If these registers are accessed at one time by word access, the registers are read regardless of the setting of the PEMP bit in a priority conversion control register (PCCR0). Do not execute word access to these registers. - Priority conversion control register (PCCR0) - Priority conversion FIFO number setting register (PFNS0) - Priority conversion FIFO data register (PCFD0) • The priority conversion FIFO data registers (PCFD0) can be byte accessed. FIFO data is shifted after the high-order byte (bit15 to bit8) is read. FIFO data will not be shifted by reading of the low-order byte (bit7 to bit0). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 673 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series ● Clear operation Writing "1" to the PFCLR bit in a priority conversion control register (PCCR0) clears the A/D priority conversion FIFO and changes the PEMP bit in an A/D priority conversion control register (PCCR0). ● Priority conversion interrupt request A priority conversion interrupt request can be generated when the number of stages storing conversion results reaches the specified number of FIFO stages (PCIF bit = 1 in an A/DC control register (ADCR0)). To generate an A/D priority conversion interrupt request, perform the following processing: • Decide the number of FIFO stages at which an interrupt request is generated, and set the number in the PFS1 and PFS0 bits in the priority conversion FIFO number setting register (PFNS0). • Set the PCIE bit in the A/DC control register (ADCR0) to "1" to enable generation of priority conversion interrupt requests. If the number of FIFO stages at which a priority conversion interrupt request is generated is set to "1" (PFS1, PFS0 = 00), a priority conversion interrupt request is generated when the conversion is completed. <Notes> • If the number of FIFO stages at which a priority interrupt request is generated is set at 2 or more (PFS1, PFS0 = 01 or higher), no priority conversion interrupt request is generated even after A/ D priority conversion is completed. • DMA transfer of the data in the FIFO can be performed when a priority conversion interrupt request is generated. For details of DMA transfer, see "24.6.4 Activating the DMA Controller (DMAC)". ● FIFO overrun interrupt request The PFUL bit in a priority conversion control register (PCCR0) changes to "1" when data has been stored in all of 4 FIFO levels and the FIFO becomes full. Also, the OVRIE bit in an A/DC control register (ADCR0) can be set to enable generation of FIFO overrun interrupt requests (OVRIE = 1). In this state, if an attempt is made to store the next conversion result in FIFO when the PFUL bit is "1", an overrun interrupt is generated. <Notes> 674 • The data in the FIFO cannot be rewritten, even by the attempt to store the next conversion result in the full FIFO. The conversion result to be stored in this attempt is abandoned. • The FIFO is emptied and the PEMP bit in a priority conversion control register (PCCR0) changes to "1" when the PFCLR bit in the priority conversion control register (PCCR0) is set to "1" to clear the FIFO. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series 24.6.4 Activating the DMA Controller (DMAC) DMA transfer of FIFO data is possible through scan conversion interrupt requests and priority conversion interrupt requests generated by the 10-bit A/D converter. If the same value is set for the number of FIFO stages at which a scan conversion interrupt request/ priority conversion interrupt request is generated and the byte number for DMA transfer, DMA transfer of FIFO data can be performed in synchronization with A/D scan conversion. For details of setting the byte number for DMA transfer, see "CHAPTER 27 DMA Controller (DMAC)". • In single conversion mode To perform DMA transfer, set the same value to the DMA block size and the interrupt generation FIFO stage number, and perform the next A/D activation after DMA is completed. • In repeat conversion mode To perform DMA transfer, set 1 to the DMA block size, and 1 for the interrupt generation FIFO stage number. Figure 24.6-6 shows the DMA transfer operation. Figure 24.6-6 DMA transfer operation (through scan conversion interrupt requests) Valid FIFO stage number Block transfer when the block size is 6 and the transfer count is 1 Block transfer when the block size is 8 and the transfer count is 1. SFS3 to SFS0=0111(8 stages) FIFO stage number setting SFS3 to SFS0=0101(6 stages) Scan conversion interrupt request (DMA activation request) Clearing by DMAC Clearing by DMAC FIFO reading (DMA transfer) A/D conversion Stop 1 2 3 4 5 6 Stop 1 2 3 4 5 6 7 8 Stop A/D activation DMA normal end interrupt <Note> Set the same value to the DMA block size and the interrupt generation FIFO stage number. Perform the next A/D activation after performing DMA transfer of all FIFO data. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 675 CHAPTER 24 10-Bit A/D Converter 24.6 MB91625 Series However, note that the event described below may occur while A/D conversion is repeated, such as in repeat conversion mode. In such cases, even after DMA transfer of data by the specified number of the bytes, the FIFO may still store more data corresponding to stages exceeding the number of stages at which a scan conversion interrupt request/priority conversion interrupt request is generated. • A/D conversion of the signals from the next channel begins before DMA transfer of conversion results is completed. (Examples are when another DMA transfer is activated and DMA transfer of conversion results in progress is made to wait) For this reason, if the FIFO is storing more data corresponding to stages exceeding the number of stages at which an interrupt request is generated, a clear operation by the DMA controller (DMAC) is ignored and DMA transfer is performed again. Figure 24.6-7 shows the DMA retransfer operation. Figure 24.6-7 DMA retransfer operation Valid FIFO stage number FIFO stage number setting Block transfer when block size is 1 and transfer count is 4 Clearing by DMAC is ignored. SFS3 to SFS0=0000 (1 stage) Scan conversion interrupt request (DMA activation request) Clearing by DMAC Waiting for DMA transfer FIFO reading (DMA transfer) A/D conversion Stop 1 2 3 4 1 2 3 4 1 2 3 4 Stop A/D activation RPT bit DMA normal end interrupt <Note> Set 1 to block size of DMA, and 1 for the interrupt generation FIFO stage number. 676 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 25 8-bit D/A Converter This chapter explains the functions and operations of the 8bit D/A converter. 25.1 25.2 25.3 25.4 Overview Configuration Pins Registers 25.5 Explanation of Operations and Setting Procedure Examples CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 677 CHAPTER 25 8-bit D/A Converter 25.1 MB91625 Series 25.1 Overview The 8-bit D/A converter acts as a peripheral function for converting digital signals into analog signals. This series microcontroller has two built-in channels for the 8-bit D/A converter. ■ Overview • Powerdown function The powerdown function reduces power requirements when output from the D/A converter is disabled. • Independent control of channels Output from the two channels of the D/A converters can be controlled independently of one another. 678 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 25 8-bit D/A Converter 25.2 MB91625 Series 25.2 Configuration This section explains the configuration of the 8-bit D/A converter. ■ Block diagram of the 8-bit D/A converter Figure 25.2-1 shows a block diagram of the 8-bit D/A converter. Figure 25.2-1 Block diagram of the 8-bit D/A converter Peripheral bus D/A control registers (DACR0, DACR1) D/A data registers (DADR0, DADR1) DAE bit PD Stop mode D/A converter D/A output PD: Powerdown • D/A control registers (DACR0, DACR1) These registers control output from the 8-bit D/A converter. • D/A data registers (DADR0, DADR1) These registers are used to set the output voltages of the D/A converter. • 8-bit D/A converter It converts digital values into analog values. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 679 CHAPTER 25 8-bit D/A Converter 25.2 MB91625 Series ■ Clocks Table 25.2-1 lists the clock used for the 8-bit D/A converter. Table 25.2-1 Clock used for the 8-bit D/A converter Clock name Operation clock 680 Description Peripheral clock (PCLK) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 25 8-bit D/A Converter 25.3 MB91625 Series 25.3 Pins This section explains the pins of the 8-bit D/A converter. ■ Overview The 8-bit D/A converter has the following pins: • DA0, DA1 pins Analog output pins of the 8-bit D/A converter. These pins are multiplexed pins. For details of using the DA0, DA1 pins of the 8-bit D/A converter, see "2.4 Setting Method for Pins". ■ Relationship between pins and channels Table 25.3-1 shows the relationship between channels and pins. Table 25.3-1 Relationship between channels and pins Channel CM71-10151-2E Analog Output Pin 0 DA0 1 DA1 FUJITSU MICROELECTRONICS LIMITED 681 CHAPTER 25 8-bit D/A Converter 25.4 MB91625 Series 25.4 Registers This section explains the configurations and functions of the registers used for the 8-bit D/A converter. ■ Registers of the 8-bit D/A converter Table 25.4-1 lists the registers used for the 8-bit D/A converter. Table 25.4-1 Registers of the 8-bit D/A converter Channel 0 1 682 Abbreviated Register Name Register Name Reference DADR0 D/A data register 0 25.4.1 DACR0 D/A control register 0 25.4.2 DADR1 D/A data register 1 25.4.1 DACR1 D/A control register 1 25.4.2 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 25 8-bit D/A Converter 25.4 MB91625 Series 25.4.1 D/A Data Registers (DADR0, DADR1) These registers are used to set the output voltages from the DA0, DA1 pins. Based on the values stored in these registers, the values of output voltages from the D/A converter are calculated. Figure 25.4-1 shows the bit configuration of the D/A data registers (DADR0, DADR1). Figure 25.4-1 Bit configuration of the D/A data registers (DADR0, DADR1) bit Attribute 7 6 5 4 3 2 1 0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Initial value R/W: Read/Write X: Undefined Table 25.4-2 shows the relationship between the values set in these registers and output voltages. Table 25.4-2 Setting values and output voltages DA7 to DA0 Output Voltage 0000 0000 0/256 × AVCC 0000 0001 1/256 × AVCC 0000 0010 2/256 × AVCC ... ... 1111 1101 253/256 × AVCC 1111 1110 254/256 × AVCC 1111 1111 255/256 × AVCC AVCC: Input voltage from the AVCC pin <Note> Even if this product is reset, these registers are not initialized. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 683 CHAPTER 25 8-bit D/A Converter 25.4 25.4.2 MB91625 Series D/A Control Registers (DACR0, DACR1) These registers control output from the 8-bit D/A converter. Figure 25.4-2 shows the bit configuration of the D/A control registers (DACR0, DACR1). Figure 25.4-2 Bit configuration of the D/A control registers (DACR0, DACR1) bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined DAE Attribute - - - - - - - R/W Initial value X X X X X X X 0 R/W: Read/Write -: Undefined X: Undefined [bit7 to bit1]: Undefined bits In case of writing Ignored In case of reading A value is undefined. [bit0]: DAE (D/A output enable bit) This bit enables/disables output from the 8-bit D/A converter. Written Value 684 Explanation 0 Disables output from the D/A converter. 1 Enables output from the D/A converter. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 25 8-bit D/A Converter 25.5 MB91625 Series 25.5 Explanation of Operations and Setting Procedure Examples This section explains the operations of the 8-bit D/A converter. Also, examples of procedures for setting the operating state are shown. 25.5.1 Operations of the 8-bit D/A Converter The 8-bit D/A converter determines the output voltage based on the value that is written to a D/A data register (DADR0, DADR1), and it outputs an analog voltage through the corresponding DA pin (DA0, DA1). When values are written to the DA7 to DA0 bits of a D/A data register (DADR0, DADR1) and then "1" is written to the DAE bit of a D/A control register (DACR0, DACR1), the 8-bit D/A converter outputs an analog signal. The D/A converter outputs 0.0 V when "0" is written to the DAE bit of the D/A control register (DACR0, DACR1). The D/A converter outputs 0.0 V when "0" is written to the DAE bit, even if the CPU is in stop mode. <Notes> • The AVCC pin is shared with the 10-bit A/D converter. • This D/A converter does not have a built-in buffer amplifier. For details of the electrical characteristics, see "Data Sheet". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 685 CHAPTER 25 8-bit D/A Converter 25.5 686 MB91625 Series FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface This chapter describes the functions and operations of the multi-function serial interface. 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 Characteristics of Multi-function Serial Interface UART (Asynchronous Serial Interface) Overview of UART (Asynchronous Serial Interface) Registers of UART (Asynchronous Serial Interface) Interrupts of UART Operation of UART Dedicated Baud Rate Generator Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) 26.9 Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode) 26.10 Notes on UART Mode 26.11 CSIO (Clock Synchronous Serial Interface) 26.12 Overview of CSIO (Clock Synchronous Serial Interface) 26.13 Registers of CSIO (Clock Synchronous Serial Interface) 26.14 Interrupts of CSIO (Clock Synchronous Serial Interface) 26.15 Operation of CSIO (Clock Synchronous Serial Interface) 26.16 Dedicated Baud Rate Generator 26.17 Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface) 26.18 Notes on CSIO Mode 26.19 I2C Interface 26.20 Overview of I2C Interface 26.21 Registers of I2C Interface 26.22 Interrupts of I2C Interface 26.23 Dedicated Baud Rate Generator 26.24 Notes on I2C Mode CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 687 CHAPTER 26 Multi-function Serial Interface 26.1 MB91625 Series 26.1 Characteristics of Multi-function Serial Interface This multi-function serial interface has the following characteristics. ■ Interface Mode The following interface modes are selectable for the multi-function serial interface depending on the operation mode settings. • UART0 (Asynchronous normal serial interface) • UART1 (Asynchronous multi-processor serial interface) • CSIO (Clock synchronous serial interface) (SPI can be supported) • I2C (I2C bus interface) ■ Switching the Interface Mode To communicate through each serial interface, the serial mode registers (SMR) shown in Table 26.1-1 should be used to set the operation mode before starting the communication. Table 26.1-1 Switching Interface Mode MD2 MD1 MD0 Interface mode 0 0 0 UART0 (Asynchronous normal serial interface) 0 0 1 UART1 (Asynchronous multi-processor serial interface) 0 1 0 CSIO (Clock synchronization serial interface) (SPI can be supported) 1 0 0 I2C (I2C bus interface) Note: Settings other than above are prohibited. <Notes> • Transmission and reception cannot be guaranteed when the operation mode is switched while one of the serial interfaces is still in use for transmission or reception operation. • The operation mode must be set first. Otherwise, the other registers will be initialized when the operation mode is changed. Note, however, that when SCR and SMR are written simultaneously with 16-bit write access, SCR reflects the written content. ■ Number of Channels This product has 12 built-in channels for multi-function serial interface. There is no I2C function for ch.0. ■ Transmission/Reception FIFO This UART has a 16-byte transmission FIFO and 16-byte reception FIFO. The FIFO steps should be converted to 16 bytes when reading through this text. There is no FIFO between ch.0 and ch.7. 688 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.2 MB91625 Series 26.2 UART (Asynchronous Serial Interface) Among all the functions of the multi-function serial interface, this section describes those supported in operation modes 0 and 1. • UART (Asynchronous Serial Interface) • Overview of UART (Asynchronous Serial Interface) • Registers of UART (Asynchronous Serial Interface) • - Serial Control Register (SCR) - Serial Mode Register (SMR) - Serial Status Register (SSR) - Extended Serial Control Register (ESCR) - Reception Data Register/Transmission Data Register (RDR/TDR) - Baud Rate Generator Registers 1, 0 (BGR1, BGR0) - FIFO Control Register 1 (FCR1) - FIFO Control Register 0 (FCR0) - FIFO Byte Register (FBYTE1/FBYTE2) Interrupts of UART - Occurrence of Reception Interrupts and Flag Set Timing - Occurrence of Interrupts when Reception FIFO is Used and Flag Set Timing - Occurrence of Transmission Interrupts and Flag Set Timing - Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing • Operation of UART • Dedicated Baud Rate Generator - Setting Baud Rate • Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) • Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode) CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 689 CHAPTER 26 Multi-function Serial Interface 26.3 MB91625 Series 26.3 Overview of UART (Asynchronous Serial Interface) UART (asynchronous serial interface) is a general-purpose serial data communication interface to perform asynchronous communication (start-stop synchronization) with an external unit. The UART supports a two-way communication function (normal mode) and a master/slave communication function (multi-processor mode: the master and slaves both supported). The UART also has transmission/reception FIFO. ■ Functions of UART (Asynchronous Serial Interface) Function 1 Data 2 Serial input 3 Transfer system 4 Baud rate • • Oversampling is performed for three times to determine the reception value by the majority of the sampling values achieved. Asynchronous • • Dedicated baud rate generator (15-bit reload counter configuration) The reload counter can be used to adjust the external clock input. 5 Data length 5 to 9 bits (in normal mode), 7 or 8 bits (in multi-processor mode) 6 Signaling system NRZ (Non Return to Zero), inverted NRZ 7 Start bit detection • • Synchronized with the falling edge of a start bit (NRZ) Synchronized with the rising edge of a start bit (inverted NRZ) 8 Reception error detection • • • Framing error Overrun error Parity error*2 9 Interrupt request • Reception interrupt (completion of reception, framing error, overrun error, parity error)*2 Transmission interrupt (transmission data empty, transmission bus idle) Transmission FIFO interrupt (when transmission FIFO is empty) DMA transfer support function for transmission and reception • • • 10 690 Full-duplex double buffer (when FIFO is not used) Transmission/reception FIFO (maximum size: 16 bytes each) (when FIFO is used)*1 Master/slave communication function (multi-processor mode) Communication between 1 (master) and n (slaves) is enabled. (The master and slave systems are both supported.) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.3 MB91625 Series Function 11 FIFO options • • • • • Transmission/reception FIFO mounted (maximum capacity: transmission FIFO = 16 bytes; reception FIFO = 16 bytes)*1 Transmission FIFO or reception FIFO selectable Transmission data can be resent. The interrupt timing for reception FIFO can be modified by software. FIFO reset is supported separately. *1: There is no FIFO between ch.0 and ch.7. *2: The detection of a parity error is enabled only in normal mode. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 691 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4 Registers of UART (Asynchronous Serial Interface) This section lists the registers of UART (asynchronous serial interface). ■ List of Registers of UART (Asynchronous Serial Interface) Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (1 / 4) Reference Abbreviated Register Name 0 SCR0 Serial control register 0 26.4.1 SMR0 Serial mode register 0 26.4.2 ESCR0 Extended serial control register 0 26.4.4 BGR0 Baud rate generator register 0 26.4.6 SSR0 Serial status register 0 26.4.3 RDR0 Received data register 0 26.4.5 TDR0 Transmitted data register 0 26.4.5 SCR1 Serial control register 1 26.4.1 SMR1 Serial mode register 1 26.4.2 ESCR1 Extended serial control register 1 26.4.4 BGR1 Baud rate generator register 1 26.4.6 SSR1 Serial status register 1 26.4.3 RDR1 Received data register 1 26.4.5 TDR1 Transmitted data register 1 26.4.5 SCR2 Serial control register 2 26.4.1 SMR2 Serial mode register 2 26.4.2 ESCR2 Extended serial control register 2 26.4.4 BGR2 Baud rate generator register 2 26.4.6 SSR2 Serial status register 2 26.4.3 RDR2 Received data register 2 26.4.5 TDR2 Transmitted data register 2 26.4.5 1 2 692 Register Name Channel FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (2 / 4) Channel Abbreviated Register Name 3 SCR3 Serial control register 3 26.4.1 SMR3 Serial mode register 3 26.4.2 ESCR3 Extended serial control register 3 26.4.4 BGR3 Baud rate generator register 3 26.4.6 SSR3 Serial status register 3 26.4.3 RDR3 Received data register 3 26.4.5 TDR3 Transmitted data register 3 26.4.5 SCR4 Serial control register 4 26.4.1 SMR4 Serial mode register 4 26.4.2 ESCR4 Extended serial control register 4 26.4.4 BGR4 Baud rate generator register 4 26.4.6 SSR4 Serial status register 4 26.4.3 RDR4 Received data register 4 26.4.5 TDR4 Transmitted data register 4 26.4.5 SCR5 Serial control register 5 26.4.1 SMR5 Serial mode register 5 26.4.2 ESCR5 Extended serial control register 5 26.4.4 BGR5 Baud rate generator register 5 26.4.6 SSR5 Serial status register 5 26.4.3 RDR5 Received data register 5 26.4.5 TDR5 Transmitted data register 5 26.4.5 SCR6 Serial control register 6 26.4.1 SMR6 Serial mode register 6 26.4.2 ESCR6 Extended serial control register 6 26.4.4 BGR6 Baud rate generator register 6 26.4.6 SSR6 Serial status register 6 26.4.3 RDR6 Received data register 6 26.4.5 TDR6 Transmitted data register 6 26.4.5 4 5 6 CM71-10151-2E Register Name FUJITSU MICROELECTRONICS LIMITED Reference 693 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (3 / 4) Channel Abbreviated Register Name 7 SCR7 Serial control register 7 26.4.1 SMR7 Serial mode register 7 26.4.2 ESCR7 Extended serial control register 7 26.4.4 BGR7 Baud rate generator register 7 26.4.6 SSR7 Serial status register 7 26.4.3 RDR7 Received data register 7 26.4.5 TDR7 Transmitted data register 7 26.4.5 SCR8 Serial control register 8 26.4.1 SMR8 Serial mode register 8 26.4.2 ESCR8 Extended serial control register 8 26.4.4 BGR8 Baud rate generator register 8 26.4.6 SSR8 Serial status register 8 26.4.3 RDR8 Received data register 8 26.4.5 TDR8 Transmitted data register 8 26.4.5 FCR18 FIFO control register 18 26.4.7 FCR08 FIFO control register 08 26.4.8 FBYTE18 FIFO1 byte register 8 26.4.9 FBYTE28 FIFO2 byte register 8 26.4.9 SCR9 Serial control register 9 26.4.1 SMR9 Serial mode register 9 26.4.2 ESCR9 Extended serial control register 9 26.4.4 BGR9 Baud rate generator register 9 26.4.6 SSR9 Serial status register 9 26.4.3 RDR9 Received data register 9 26.4.5 TDR9 Transmitted data register 9 26.4.5 FCR19 FIFO control register 19 26.4.7 FCR09 FIFO control register 09 26.4.8 FBYTE19 FIFO1 byte register 9 26.4.9 FBYTE29 FIFO2 byte register 9 26.4.9 8 9 694 Register Name FUJITSU MICROELECTRONICS LIMITED Reference CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (4 / 4) Channel Abbreviated Register Name 10 SCR10 Serial control register 10 26.4.1 SMR10 Serial mode register 10 26.4.2 ESCR10 Extended serial control register 10 26.4.4 BGR10 Baud rate generator register 10 26.4.6 SSR10 Serial status register 10 26.4.3 RDR10 Received data register 10 26.4.5 TDR10 Transmitted data register 10 26.4.5 FCR110 FIFO control register 110 26.4.7 FCR010 FIFO control register 010 26.4.8 FBYTE110 FIFO1 byte register 10 26.4.9 FBYTE210 FIFO2 byte register 10 26.4.9 SCR11 Serial control register 11 26.4.1 SMR11 Serial mode register 11 26.4.2 ESCR11 Extended serial control register 11 26.4.4 BGR11 Baud rate generator register 11 26.4.6 SSR11 Serial status register 11 26.4.3 RDR11 Received data register 11 26.4.5 TDR11 Transmitted data register 11 26.4.5 FCR111 FIFO control register 111 26.4.7 FCR011 FIFO control register 011 26.4.8 FBYTE111 FIFO1 byte register 11 26.4.9 FBYTE211 FIFO2 byte register 11 26.4.9 11 CM71-10151-2E Register Name FUJITSU MICROELECTRONICS LIMITED Reference 695 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-2 Bit Assignment of UART (Asynchronous Serial Interface) bit15 bit14 bit13 bit12 bit11 bit10 bit9 SCR/SMR UPCL SSR/ ESCR REC - - RIE TIE TBIE - PE FRE ORE RDRF TDRE RDR/TDR BGR1/ BGR0 RXE - EXT B14 B13 B12 - B11 B10 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TXE MD2 MD1 MD0 - SBL BDS SCKE SOE TBI - ESBL INV PEN P L2 L1 L0 D8 (AD) D7 D6 D5 D4 D3 D2 D1 D0 B8 B7 B6 B5 B4 B3 B2 B1 B0 B9 - FCR1/ FCR0 - - - FBYTE2/ FBYTE1 FD15 FD14 FD13 - FLSTE FRIIE FD12 FD11 FDRQ FTIE FSEL - FLST FLD FSET FCL2 FCL1 FE2 FE1 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 ■ Operation Mode The UART (asynchronous serial interface) operates in two different modes. The mode selection is determined by MD2, MD1 and MD0 in the serial mode register (SMR). Table 26.4-3 Operation Modes of UART (Asynchronous Serial Interface) 696 Operation mode MD2 MD1 MD0 Type 0 0 0 0 UART0 (asynchronous normal mode) 1 0 0 1 UART1 (asynchronous multi-processor mode) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4.1 Serial Control Register (SCR) The serial control register (SCR) enables or disables transmission/reception, transmission/reception interrupts, and transmission bus idle interrupts. SCR can also reset the UART. ■ Serial Control Register (SCR) Figure 26.4-1 shows the bit structure of the serial control register (SCR), and Table 26.4-4 describes the function of each bit. Figure 26.4-1 Bit Structure of Serial Control Register (SCR) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 UPCL - - RIE TIE TBIE RXE TXE R/W - - R/W R/W R/W R/W R/W ......................................... bit7 bit0 (SMR) Initial value 0--00000B TXE 0 1 Transmission enable bit Disables transmission Enables transmission RXE 0 1 Reception enable bit Disables reception Enables reception TBIE Transmission bus idle interrupt enable bit Disables transmission bus idle interrupt 0 1 Enables transmission bus idle interrupt TIE 0 1 Transmission interrupt enable bit Disables transmission interrupt Enables transmission interrupt RIE 0 1 Reception interrupt enable bit Disables reception interrupt Enables reception interrupt Undefined bits Read: undefined value. Write: no effect. UPCL R/W : Readable/Writable : Initial value - 0 1 Programmable clear bit Write Read No effect "0" is always read. Programmable clear operation : Undefined CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 697 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-4 Functional Description of Each Bit of Serial Control Register (SCR) Bit name bit15 UPCL: Programmable clear bit This bit is used to initialize the internal state of the UART. Setting the bit to "1": • The UART will be reset directly (software reset). The register setting, however, will be retained. In this case, communication of the data which is being transmitted or received will be cut off immediately. • The baud rate generator will reload the value set in BGR1/BGR0 registers, and then restart the operation. • All the transmission/reception interrupt sources (PE, FRE, ORE, RDRF, TDRE and TBI) will be initialized (000011B). Setting the bit to "0": No effect on the operation Reading this bit always returns "0". Note: Execute the programmable clear operation after disabling interrupts. Execute the programmable clear operation after disabling FIFO (FE2, FE1 = 0) when FIFO is used. bit14, bit13 Undefined bits Read: undefined value Write: no effect bit12 RIE: Reception interrupt enable bit • • This bit is used to enable/disable the output of reception interrupt requests to the CPU. A reception interrupt request is output when the RIE bit and the reception data flag bit (RDRF) are set to "1", or when any of the error flag bits (PE, ORE or FRE) is set to "1". TIE: Transmission interrupt enable bit • TBIE: Transmission bus idle interrupt enable bit • bit9 RXE: Reception enable bit This bit is used to enable/disable UART reception operation. • Setting the bit to "0" disables the reception operation. • Setting the bit to "1" enables the reception operation. Note: Even when the reception operation is enabled (RXE = 1), such operation does not start until the falling edge of a start bit (in NRZ format: INV = 0) is input. (When the inverted NRZ format is selected (INV = 1), the reception operation does not start until the rising edge is input.) If the reception operation is disabled (RXE = 0) during the reception, the operation will be terminated immediately. bit8 TXE: Transmission enable bit This bit is used to enable/disable UART transmission operation. • Setting the bit to "0" disables the transmission operation. • Setting the bit to "1" enables the transmission operation. Note: If the transmission operation is disabled (TXE = 0) during the transmission, the operation will be terminated immediately. bit11 bit10 698 Function • • This bit is used to enable/disable the output of transmission interrupt requests to the CPU. A transmission interrupt request is output when the TIE and TDRE bits are set to "1". This bit is used to enable/disable the output of transmission bus idle interrupt requests to the CPU. A transmission bus idle interrupt request is output when the TBIE and TBI bits are set to "1". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4.2 Serial Mode Register (SMR) The serial mode register (SMR) sets the operation mode, selects the transfer direction, data length and stop bit length, and enables or disables the output to the serial data and serial clock pins. ■ Serial Mode Register (SMR) Figure 26.4-2 shows the bit structure of the serial mode register (SMR), and Table 26.4-5 describes the function of each bit. Figure 26.4-2 Bit Structure of Serial Mode Register (SMR) bit15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit8 bit7 bit6 bit5 bit4 bit3 Re- SBL MD2 MD1 MD0 served (SCR) bit2 bit1 bit0 Initial value BDS SCKE SOE 00000000B R/W R/W R/W R/W R/W R/W R/W R/W SOE 0 1 Serial data output enable bit Disables the output of SOUT Enables the output of SOUT SCKE 1 Serial clock output enable bit Disables the output of SCK or Enables the input of SCK Enables the output of SCK BDS 0 1 Transfer direction selection bit LSB first (Transfer starting from the least significant bit) MSB first (Transfer starting from the most significant bit) 0 SBL 0 1 0 1 Stop bit length selection bit ESCR:ESBL=0 ESCR:ESBL=0 ESCR:ESBL=1 ESCR:ESBL=1 1 bit 2 bits 3 bits 4 bits Reserved Always set "0" to this bit. MD2 MD1 MD0 Operation mode setting bits 0 0 0 Operation mode 0 (asynchronous normal mode) 0 0 1 Operation mode 1 (asynchronous multi-processor mode) 0 1 0 Operation mode 2 (clock synchronization mode) 1 0 0 Operation mode 4 (I2C mode) R/W : Readable/Writable : Initial value CM71-10151-2E Note: This section describes the registers and operations of operation modes 0 and 1. FUJITSU MICROELECTRONICS LIMITED 699 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-5 Functional Description of Each Bit of Serial Mode Register (SMR) Bit name bit7 to bit5 MD2, MD1, MD0: Operation mode setting bits Function These bits set the operation mode for the asynchronous serial interface. "000B": Selects operation mode 0 (asynchronous normal mode) "001B": Selects operation mode 1 (asynchronous multi-processor mode) "010B": Selects operation mode 2 (clock synchronization mode) "100B": Selects operation mode 4 (I2C mode) This section describes the registers and operations of operation mode 0 (asynchronous normal mode) and operation mode 1 (asynchronous multi-processor mode). Note: Settings other than above are prohibited. To switch the operation mode, execute the programmable clear operation first (SCR:UPCL = 1). And then, after setting the operation mode, set each register. 700 bit4 Reserved bit Always set "0" to this bit. bit3 SBL: Stop bit length selection bit This bit is used to select a bit length for a stop bit (frame end mark of transmission data). Setting the bit to SBL=0, ESCR:ESBL=0 sets the stop bit to 1 bit in length. Setting the bit to SBL=1, ESCR:ESBL=0 sets the stop bit to 2 bits in length. Setting the bit to SBL=0, ESCR:ESBL=1 sets the stop bit to 3 bits in length. Setting the bit to SBL=1, ESCR:ESBL=1 sets the stop bit to 4 bits in length. Notes: • In reception, only the first bit of each stop bit is always detected. • Set this bit when transmission is disabled (TXE=0). bit2 BDS: Transfer direction selection bit This bit is used to determine the transfer priority for transfer serial data: whether the least significant bit should be transferred first (LSB first, BDS = 0) or the most significant bit should be transferred first (MSB first, BDS = 1). Note: Set this bit when transmission and reception are disabled (TXE = RXE = 0). bit1 SCKE: Serial clock output enable bit This bit is used to control the I/O port of the serial clock. Setting the bit to "0": The output of SCK "H" or the input of SCK will be enabled. To use it as a SCK input, set a general-purpose I/O port as the input port. Also select the external clock (BGR:EXT = 1) using the external clock selection bit. Setting the bit to "1" enables the output of SCK. bit0 SOE: Serial data output enable bit This bit is used to enable/disable the output of serial data. Setting the bit to "0" disables the output. Setting the bit to "1" enables the output of SOUT. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 26 Multi-function Serial Interface 26.4 <Note> The operation mode must be set first. Otherwise, the other registers will be initialized when the operation mode is changed. Note, however, that when SCR and SMR are written simultaneously with 16-bit write access, SCR reflects the written content. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 701 CHAPTER 26 Multi-function Serial Interface 26.4 26.4.3 MB91625 Series Serial Status Register (SSR) The serial status register (SSR) checks the transmission/reception status, and also checks and clears the reception error flag. ■ Serial Status Register (SSR) Figure 26.4-3 shows the bit structure of the serial status register (SSR) and Table 26.4-6 describes the function of each bit. Figure 26.4-3 Bit Structure of Serial Status Register (SSR) bit15 bit14 bit13 bit12 REC - PE FRE R/W - R R bit11 bit10 bit9 bit8 bit7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit0 ORE RDRF TDRE TBI R R R (ESCR) Initial value 0-000011B R TBI 0 1 Transmission bus idle flag bit Transmission in progress No transmission operation TDRE 0 1 Transmission data empty flag bit The transmission data register (TDR) contains data. The transmission data register (TDR) is empty. RDRF Reception data full flag bit The reception data register (RDR) is empty. The reception data register (RDR) contains data. 0 1 ORE 0 1 Overrun error flag bit No overrun error Overrun error FRE 0 1 Framing error flag bit No framing error Framing error PE 0 1 Parity error flag bit No parity error Parity error Undefined bit Read: undefined value. Write: no effect. REC R/W : Readable/Writable 0 R : Read only 1 - : Undefined Reception error flag clear bit Write Read No effect "0" is always read. Clears the reception error flag (PE, FRE, ORE) : Initial value 702 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-6 Functional Description of Each Bit of Serial Status Register (SSR) (1 / 2) Bit name Function bit15 REC: Reception error flag clear bit This bit is used to clear the PE, FRE and ORE flag in the serial status register (SSR). • Writing "1" clears the error flag. • Writing "0" has no effect. Reading this bit always returns "0". bit14 Undefined bit Read: undefined value Write: no effect bit13 PE: Parity error flag bit (only available in operation mode 0) • • • • bit12 FRE: Framing error flag bit • • • • bit11 ORE: Overrun error flag bit • • • • CM71-10151-2E The bit is set to "1" when a parity error occurs during reception (ESCR:PEN = 1). The bit is cleared by writing "1" to the REC bit in the serial status register (SSR). A reception interrupt request is output when the PE bit and the SCR:RIE bit are set to "1". When this flag is set, the data in the reception data register (RDR) is invalid. If this flag is set during the use of reception FIFO, the reception FIFO enable bit will be cleared and no reception data will be stored to the reception FIFO. This bit is set to "1" when a framing error occurs during reception. The bit is cleared by writing "1" to the REC bit in the serial status register (SSR). A reception interrupt request is output when the FRE and RIE bits are set to "1". When this flag is set, the data in the reception data register (RDR) is invalid. If this flag is set during the use of the reception FIFO, the reception FIFO enable bit will be cleared and the reception data will not be stored to the reception FIFO. This bit is set to "1" when an overrun occurs during reception. The bit is cleared by writing "1" to the REC bit in the serial status register (SSR). A reception interrupt request is output when the ORE and RIE bits are set to "1". When this flag is set, the data in the reception data register (RDR) is invalid. If this flag is set during the use of the reception FIFO, the reception FIFO enable bit will be cleared and the reception data will not be stored to the reception FIFO. FUJITSU MICROELECTRONICS LIMITED 703 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-6 Functional Description of Each Bit of Serial Status Register (SSR) (2 / 2) Bit name bit10 RDRF: Reception data full flag bit Function • • • • • • bit9 TDRE: Transmission data empty flag bit • • • • • bit8 TBI: Transmission bus idle flag bit • • • • • 704 This flag indicates the status of the reception data register (RDR). The bit is set to "1" when reception data is loaded to RDR. The bit is cleared to "0" when the reception data register (RDR) is read. A reception interrupt request is output when the RDRF and RIE bits are set to "1". RDRF is set to "1" when a specified number of data elements are received at the reception FIFO during the use of the reception FIFO. When the reception FIFO idle detection enable bit (FCR1:FRIIE) is set to "1" during the use of the reception FIFO, RDRF will be set to "1", if the idle state of reception continues at the baud rate clock for a duration of eight clocks or longer as the specified number of data elements have not been received at the reception FIFO and some data still remains in the reception FIFO. If RDR is read while 8 clocks are still being counted, the counter will be reset to "0" and it will start counting another set of eight clocks. This bit is cleared to "0" when the reception FIFO, if used, becomes empty. This flag indicates the status of the transmission data register (TDR). When transmission data is written to TDR, the bit becomes "0", indicating that TDR contains valid data. When the data is loaded to the transmission shift register and transmission starts, the bit becomes "1", indicating that TDR no longer contains any valid data. A transmission interrupt request is output when the TDRE and TIE bits are set to "1". The TDRE bit becomes "1" when the UPCL bit in the serial control register (SCR) is set to "1". For information about the set/reset timings of the TDRE bit for when the transmission FIFO is used, refer to Section "26.5.4 Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing". This bit indicates that the UART is not performing transmission operation. The bit is set to "0" when transmission data is written to the transmission data register (TDR). The bit is set to "1" when the transmission data register is empty (TDRE =1) and no transmission operation is in progress. The TBI bit becomes "1" when the UPCL bit in the serial control register (SCR) is set to "1". A transmission interrupt request is output when this bit is "1" and a transmission bus idle interrupt is enabled (SCR:TBIE = 1). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4.4 Extended Serial Control Register (ESCR) The extended serial control register (ESCR) can be used to set the transmission/reception data length, select the stop bit length, enable/disable the parity bit, select the parity bit, and invert the serial data format. ■ Bit Structure of the Extended Serial Control Register (ESCR) Figure 26.4-4 shows the bit structure of the extended serial control register (ESCR) and Table 26.4-7 describes the function of each bit. Figure 26.4-4 Bit Structure of Extended Serial Control Register (ESCR) bit15 ......................................... (SSR) bit8 bit7 - L2 0 0 0 0 1 : Undefined : Initial value CM71-10151-2E R/W L1 0 0 1 1 0 R/W PEN R/W bit3 bit2 bit1 bit0 P L2 L1 L0 R/W R/W R/W R/W L0 0 1 0 1 0 Initial value -0000000B Data length selection bits 8-bit length 5-bit length 6-bit length 7-bit length 9-bit length PEN 0 1 Parity enable bit Disables parity Enables parity INV 0 1 Inverted serial data format bit NRZ format Inverted NRZ format 1 - ESBL INV bit4 Parity selection bit Even parity Odd parity 0 : Readable/Writable bit5 P 0 1 ESBL R/W bit6 Extended stop bit length selection bit SMR:SBL=0 1 bit SMR:SBL=1 2 bits SMR:SBL=0 3 bits SMR:SBL=1 4 bits Undefined bit Read: undefined value. Write: no effect. FUJITSU MICROELECTRONICS LIMITED 705 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-7 Functional Description of Each Bit of Extended Serial Control Register (ESCR) Bit name 706 Function bit7 Undefined bit Read: Write: undefined value no effect bit6 ESBL: Extended stop bit length selection bit Selects the bit length of stop bit (frame end mark of the transmitted data). Setting SMR: SBL=0, ESBL=0, sets the stop bit to 1 bit. Setting SMR: SBL=1, ESBL=0, sets the stop bit to 2 bits. Setting SMR: SBL=0, ESBL=1, sets the stop bit to 3 bits. Setting SMR: SBL=1, ESBL=1, sets the stop bit to 4 bits. Notes: • Always detects the first bit only of the stop bit during reception. • Set this bit when transmission is prohibited (TXE=0). bit5 INV: Inverted serial data format bit This bit is used to select the NRZ format or the inverted NRZ format as the serial data format. bit4 PEN: Parity enable bit (only available in operation mode 0) This bit is used to determine whether the parity bit should be added (in transmission) or detected (in reception). • When this bit is set to "0", the parity bit is not added. • When this bit is set to "1", the parity bit is added. Note: This bit is fixed to "0" internally in operation mode 1. bit3 P: Parity selection bit (only available in operation mode 0) This bit is used to select odd parity "1" or even parity "0" when parity is enabled (ESCR:PEN = 1). • Setting the bit to "0" selects even parity. • Setting the bit to "1" selects odd parity. bit2 to bit0 L2, L1, L0: Data length selection bits These bits are used to specify a data length for transmission/reception data. • Selecting "000B" sets the data length to 8 bits. • Selecting "001B" sets the data length to 5 bits. • Selecting "010B" sets the data length to 6 bits. • Selecting "011B" sets the data length to 7 bits. • Selecting "100B" sets the data length to 9 bits. Note: Settings other than above are prohibited. For operation mode 1, set the data length to 7 or 8 bits. Any other setting is prohibited. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4.5 Reception Data Register / Transmission Data Register (RDR/TDR) The reception data register and transmission data register are located at the same address. It serves as the reception data register in read access, while it functions as the transmission data register in write access. When FIFO operation is enabled, the RDR/TDR address becomes the read/write address for the FIFO. ■ Reception Data Register (RDR) Figure 26.4-5 illustrates the bit structure of the serial reception register (RDR). Figure 26.4-5 Bit Structure of Reception Data Register (RDR) bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D8 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R R Initial value - - - - - - - 0 00000000B R: Read only The reception data register (RDR) is a 9-bit data buffer register for serial data reception. • A serial data signal sent to a serial input pin (SIN pin) is converted through the shift register and then stored in the reception data register (RDR). • "0" is placed in one of the upper bits, depending on the data length, as shown below. Data length D8 D7 D6 D5 D4 D3 D2 D1 D0 9 bits X X X X X X X X X 8 bits 0 X X X X X X X X 7 bits 0 0 X X X X X X X 6 bits 0 0 0 X X X X X X 5 bits 0 0 0 0 X X X X X (X indicates the reception data bit) • The reception data full flag bit (SSR:RDRF) is set to "1" once reception data is stored in the reception data register (RDR). A reception interrupt request will be generated if reception interrupts have been enabled (SSR: RIE = 1). • Read the reception data register (RDR) when the reception data full flag bit (SSR:RDRF) is "1". The reception data full flag bit (SSR:RDRF) is cleared to "0" automatically, when the reception data register (RDR) is read. • If a reception error occurs (one of SSR:PE, ORE, or FRE is "1"), the data in the reception data register (RDR) becomes invalid. • In operation mode 1 (multi-processor mode), 7-bit or 8-bit operation is performed and the received AD bit is stored in bit D8. • 16-bit access is used to read RDR for a 9-bit transfer in operation mode 1. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 707 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series <Notes> • RDRF is set to "1", once a specified number of data elements have been received at the reception FIFO, if used. • RDRF is cleared to "0" when the reception FIFO, if used, becomes empty. • If a reception error occurs (one of SSR:PE, ORE, or FRE is "1") when the reception FIFO is used, the reception FIFO enable bit will be cleared and the reception data will not be stored to the reception FIFO. ■ Transmission Data Register (TDR) Figure 26.4-6 illustrates the bit structure of the transmission data register. Figure 26.4-6 Bit Structure of Transmission Data Register (TDR) bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D8 D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W W Initial value - - - - - - - 1 11111111B W: Write only The transmission data register (TDR) is a 9-bit data buffer register for serial data transmission. • If transmission data is written to the transmission data register (TDR) when transmission operation is enabled (SCR:TXE = 1), the transmission data will be transferred to the transmission shift register, converted into serial data and then sent from a serial data output pin (SOUT pin). • As shown below, data becomes invalid from the upper bit in accordance with the data length. Data length D8 D7 D6 D5 D4 D3 D2 D1 D0 9 bits X X X X X X X X X 8 bits Invalid X X X X X X X X 7 bits Invalid Invalid X X X X X X X 6 bits Invalid Invalid Invalid X X X X X X 5 bits Invalid Invalid Invalid Invalid X X X X X (X indicates the reception data bit) 708 • The transmission data empty flag (SSR:TDRE) is cleared to "0" when transmission data is written to the transmission data register (TDR). • If the transmission FIFO is disabled or empty, the transmission data empty flag (SSR:TDRE) will be set to "1" when transmission data is transferred to the transmission shift register and the transmission starts. • Transmission data can be written when the transmission data empty flag (SSR:TDRE) is set to "1". A transmission interrupt will occur if transmission interrupts have been enabled. Write transmission data by generating a transmission interrupt or when the transmission data empty flag (SSR:TDRE) is set to "1". FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 26 Multi-function Serial Interface 26.4 • Transmission data cannot be written when the transmission data empty flag (SSR:TDRE) is set to "0" and the transmission FIFO is either disabled or full. • In operation mode 1 (multi-processor mode), 7-bit or 8-bit operation is performed and the AD bit is sent by writing to bit D8. • 16-bit access is used to write to TDR for a 9-bit transfer in operation mode 1. <Notes> • The transmission data register is used exclusively for writing, while the reception data register is used exclusively for reading. These registers have different write and read values as they are located at the same address. Therefore, instructions such as INC/DEC instructions, which are used for read modify write (RMW) instruction, cannot be used. • For information about the timing for setting the transmission data empty flag (SSR:TDRE) when the transmission FIFO is used, refer to Section "26.5.4 Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing". CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 709 CHAPTER 26 Multi-function Serial Interface 26.4 26.4.6 MB91625 Series Baud Rate Generator Registers 1, 0 (BGR1, BGR0) The baud rate generator registers 1, 0 (BGR1, BGR0) are used to set a division ratio for the serial clock. They also allow an external clock to be selected as the clock source for the reload counter. ■ Bit Structure of the Baud Rate Generator Registers 1, 0 (BGR1, BGR0) Figure 26.4-7 shows the bit structure of the baud rate generator registers 1, 0 (BGR1, BGR0). Figure 26.4-7 Bit Structure of Baud Rate Generator Registers 1, 0 (BGR1, BGR0) bit15 bit14 bit13 bit12 EXT R/W bit10 bit9 bit8 bit7 bit6 bit5 (BGR1) R/W R/W R/W: Readable/Writable 710 bit11 R/W R/W bit4 bit3 bit2 bit1 bit0 Initial value 00000000B (BGR0) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BGR0 Write Read Baud rate generator register 0 Write to reload counter bits 0-7 Read BGR0 setting value BGR1 Write Read Baud rate generator register 1 Write to reload counter bits 8-14 Read BGR1 setting value EXT 0 1 External clock selection bit Uses internal clock Uses external clock 00000000B • The baud rate generator registers are used to set a division ratio for the serial clock. • BGR1 and BGR0 correspond to the upper bits and lower bits respectively and they can write a reload value to be counted as well as read BGR1/BGR0 setting values. • The reload counter starts counting when a reload value is written to the baud rate generator registers (BGR1/BGR0). • The EXT bit (bit15) is used to determine whether the internal clock or external clock should be used as the clock source for the reload counter. Setting EXT to "0" selects the internal clock, while setting EXT to "1" selects the external clock. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E MB91625 Series CHAPTER 26 Multi-function Serial Interface 26.4 <Notes> • Use 16-bit access to write to the baud rate generator registers 1, 0 (BGR1, BGR0). • When a setting value of the baud rate generator registers 1, 0 (BGR1, BGR0) is changed, the new setting value is not reloaded until the counter value becomes "0000H". To make the new setting value valid immediately, therefore, execute a programmable clear (UPCL) operation after changing the BGR1/BGR0 setting value. • When the reload value is even-numbered, the "L" width of the reception serial clock is one peripheral clock (PCLK) cycle longer than the "H" width of the same serial clock. When the reload value is odd-numbered, the "L" width is the same as the "H" width. • Select 4 or a larger value for BGR1/BGR0. However, data may not be able to be received properly, due to a baud rate error or reload settings. • To change the setting to the external clock (EXT = 1) during the operation of the baud rate generator, write "0" to baud rate generator registers 1, 0 (BGR1, BGR0), execute a programmable clear (UPCL) operation, and then set to the external clock (EXT = 1). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 711 CHAPTER 26 Multi-function Serial Interface 26.4 26.4.7 MB91625 Series FIFO Control Register 1 (FCR1) The FIFO control register 1 (FCR1) selects transmission/reception FIFO, enables transmission FIFO interrupts, and controls the interrupt flag. ■ Bit Structure of FIFO Control Register 1 (FCR1) Figure 26.4-8 shows the bit structure of the FIFO control register 1 (FCR1) and Table 26.4-8 describes the function of each bit. Figure 26.4-8 Bit Structure of FIFO Control Register 1 (FCR1) bit15 bit14 bit13 ReReserved served R/W R/W - bit12 bit11 bit10 bit9 FLSTE FRIIE FDRQ FTIE R/W R/W R/W R/W bit8 bit7 .......................................... FSEL bit0 Initial value (FCR0) 00-00100B R/W FSEL 0 1 FIFO selection bit Transmission FIFO: FIFO1, Reception FIFO: FIFO2 Transmission FIFO: FIFO2, Reception FIFO: FIFO1 FTIE 0 1 Transmission FIFO interrupt enable bit Disables transmission FIFO interrupts FDRQ Transmission FIFO data request bit No transmission FIFO data request Transmission FIFO data request 0 1 Enables transmission FIFO interrupts FRIIE 0 1 Reception FIFO idle detection enable bit Disables reception FIFO idle detection FLSTE 0 Retransmission data lost detection enable bit Disables data lost detection 1 Enables data lost detection Enables reception FIFO idle detection Undefined bit Read: undefined value. Write: no effect. Reserved bits Always set these bits to "0". R/W - : Readable/Writable : Undefined : Initial value 712 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-8 Functional Description of Each Bit of FIFO Control Register 1 (FCR1) Bit name CM71-10151-2E Function bit15, bit14 Reserved bits Always set these bits to "0". bit13 Undefined bit Read: undefined value Write: no effect bit12 FLSTE: Retransmission data lost detection enable bit This bit enables FLST bit detection. Setting the bit to "0" disables FLST bit detection. Setting the bit to "1" enables FLST bit detection. Note: To set this bit to "1", set the FSET bit to "1" beforehand. bit11 FRIIE: Reception FIFO idle detection enable bit This bit is used to determine whether the idle state of reception for 8 clocks with the baud rate clock or longer should be detected while the reception FIFO still contains valid data. A reception interrupt will occur if the idle state of reception is detected when reception interrupts have been enabled (SCR:RIE = 1). Setting the bit to "0" disables reception idle state detection. Setting the bit to "1" enables reception idle state detection. bit10 FDRQ: Transmission FIFO data request bit This is a transmission FIFO data request bit. When this bit is set to "1", it is indicated that transmission data is being requested. If transmission FIFO interrupts have been enabled (FTIE = 1) at this point, a FIFO transmission interrupt request will be output. FDRQ setting condition FBYTE1/FBYTE2 (for transmission) = 0 (The transmission FIFO is empty.) FDRQ reset condition • Writing "0" to this bit • When the transmission FIFO is full. Note: It is valid to write "0" when transmission FIFO has been enabled. It is prohibited to write "0" to this bit when FBYTE1/FBYTE2 (for transmission) is set to "0". Writing "1" to the bit has no effect on operation. "1" is read by a read modify write (RMW) instruction. bit9 FTIE: Transmission FIFO interrupt enable bit This is a transmission FIFO interrupt enable bit. An interrupt will occur if this bit is set to "1" when the FDRQ bit is set to "1". bit8 FSEL: FIFO selection bit This bit is used to select transmission/reception FIFO. Setting the bit to "0" assigns transmission FIFO to FIFO1 and reception FIFO to FIFO2. Setting the bit to "1" assigns transmission FIFO to FIFO2 and reception FIFO to FIFO1. Note: This bit cannot be cleared by resetting FIFO (FCL2, FCL1 = 1). To modify this bit, disable FIFO operation beforehand (FCR:FE2, FE1 = 0). FUJITSU MICROELECTRONICS LIMITED 713 CHAPTER 26 Multi-function Serial Interface 26.4 26.4.8 MB91625 Series FIFO Control Register 0 (FCR0) The FIFO control register 0 (FCR0) enables/disables FIFO operation, resets FIFO, saves the read pointer and sets retransmission. ■ Bit Structure of FIFO Control Register 0 (FCR0) Figure 26.4-9 shows the bit structure of the FIFO control register 0 (FCR0) and Table 26.4-9 describes the function of each bit. Figure 26.4-9 Bit Structure of FIFO Control Register 0 (FCR0) bit15 ......................................... (FCR1) bit8 bit7 bit6 - R FSET 0 1 - : Undefined bit1 R/W R/W R/W R/W R/W bit0 Initial value FE1 -0000000 B R/W FIFO2 operation enable bit Disables FIFO2 operation Enables FIFO2 operation 0 1 : Read only bit2 FE2 0 1 FCL2 R bit3 FIFO1 operation enable bit Disables FIFO1 operation Enables FIFO1 operation 0 1 : Readable/Writable bit4 FE1 0 1 FCL1 R/W bit5 FLST FLD FSET FCL2 FCL1 FE2 - FIFO1 reset bit Write No effect Resets FIFO1 Read "0" is always read. FIFO2 reset bit Write No effect Resets FIFO2 Read "0" is always read. FIFO pointer save bit Write Read Does not save the pointer. "0" is always read. Saves the pointer. FLD 0 1 FIFO pointer reload bit Does not reload the pointer. Reloads the pointer. FLST 0 1 FIFO retransmission data lost flag bit No data lost Data lost Undefined bit Read: "0" is always read. Write: "0" is always written. : Initial value 714 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-9 Functional Description of Each Bit of FIFO Control Register 0 (FCR0) (1 / 2) Bit name CM71-10151-2E Function bit7 Undefined bit Read: "0" is always read. Write: Always write "0". bit6 FLST: FIFO retransmission data lost flag bit This bit indicates that retransmission data has been lost from the transmission FIFO. FLST setting condition Writing (overwriting) to FIFO when the FLSTE bit in the FIFO control register 1 (FCR1) is set to "1" and also the write pointer of the transmission FIFO matches the read pointer saved by the FSET bit. FLST reset conditions • FIFO reset (writing "1" to FCL) • Writing "1" to the FSET bit Setting this bit to "1" overwrites the data indicated by the read pointer which has been saved by the FSET bit. Consequently, the FLD bit cannot be used to set retransmission even when an error occurs. To resend the data while this bit is set to "1", reset FIFO and then rewrite the data to FIFO. bit5 FLD: FIFO pointer reload bit This bit is used to reload to the read pointer the data which has been saved by the FSET bit to the transmission FIFO. This bit should be used to resend data when a communication error occurs. The bit becomes "0" when retransmission has been set. Note: Reload to the read pointer is in progress as long as this bit is set to "1". Therefore, do not perform write operations except for FIFO reset. It is prohibited to set this bit to "1" when FIFO has been enabled or transmission is in progress. Write "1" to this bit after setting the TIE and TBIE bits to "0". And then, set the TIE and TBIE bits to "1" when the transmission FIFO has been enabled. bit4 FSET: FIFO pointer save bit This bit is used to save the read pointer of the transmission FIFO. If the FLST bit is set to "0", saving the read pointer prior to communication will enable retransmission in case that an error such as a communication error occurs. Setting the bit to "1" saves the current read pointer value. Setting the bit to "0" has no effect. Note: Set this bit to "1" when the number of transmission bytes (FBYTE1/FBYTE2) indicates "0". bit3 FCL2: FIFO2 reset bit This bit is used to reset FIFO2. Setting this bit to "1" initializes the internal state of FIFO2. Only the FCR1:FLST bit will be initialized and the other bits in the FCR1/FCR0 registers will be retained. Note: Disable transmission/reception before resetting FIFO2. Set the transmission FIFO interrupt enable bit to "0" before the reset. The number of valid data elements for the FBYTE2 register will become "0". FUJITSU MICROELECTRONICS LIMITED 715 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series Table 26.4-9 Functional Description of Each Bit of FIFO Control Register 0 (FCR0) (2 / 2) Bit name 716 Function bit2 FCL1: FIFO1 reset bit This bit is used to reset FIFO1. Setting this bit to "1" initializes the internal state of FIFO1. Only the FCR0:FLST bit will be initialized and the other bits in the FCR1/FCR0 registers will be retained. Note: Disable transmission/reception before resetting FIFO1. Set the transmission FIFO interrupt enable bit to "0" before the reset. The number of valid data elements for the FBYTE1 register will become "0". bit1 FE2: FIFO2 operation enable bit This bit is used to enable/disable FIFO2 operation. • To use FIFO2, set this bit to "1". • When FIFO2 is set for the transmission FIFO (FCR1:FSEL = 1) and "1" is written to this bit, transmission will start immediately, if FIFO2 contains data and the UART is enabled for transmission (TXE = 1). At this point, set the TIE and TBIE bits to "0", write "1" to this bit, and then set the TIE and TBIE bits to "1". • This bit will be cleared to "0" if a reception error occurs when FIFO2 has been selected as the reception FIFO by the FSEL bit. This bit cannot be set to "1" unless the reception error is cleared. • Set this bit to "1" or "0" when the transmission buffer is empty (TDRE = 1) to use it as the transmission FIFO, or when the reception buffer is empty (RDRF = 0) to use it as the reception FIFO. • Even when FIFO2 is disabled, its status is retained. bit0 FE1: FIFO1 operation enable bit This bit is used to enable/disable FIFO1 operation. • To use FIFO1, set this bit to "1". • When FIFO1 is set for the transmission FIFO (FCR1:FSEL = 0) and "1" is written to this bit, transmission will start immediately, if FIFO1 contains data and the UART is enabled for transmission (TXE = 1). At this point, set the TIE and TBIE bits to "0", write "1" to this bit, and then set the TIE and TBIE bits to "1". • This bit will be cleared to "0" if a reception error occurs when FIFO1 has been selected as the reception FIFO by the FSEL bit. This bit cannot be set to "1" unless the reception error is cleared. • Set this bit to "1" or "0" when the transmission buffer is empty (TDRE = 1) to use it as the transmission FIFO, or when the reception buffer is empty (RDRF = 0) to use it as the reception FIFO. • Even when FIFO1 is disabled, its status is retained. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series 26.4.9 FIFO Byte Register (FBYTE1/FBYTE2) The FIFO byte register (FBYTE1/FBYTE2) indicates the number of valid data elements for FIFO. It can also determine whether a reception interrupt should occur when the reception FIFO has received a specified number of data elements. ■ Bit Structure of FIFO Byte Register (FBYTE1/FBYTE2) Figure 26.4-10 shows the bit structure of FIFO byte register (FBYTE1/FBYTE2). Figure 26.4-10 Bit Structure of FIFO Byte Register (FBYTE1/FBYTE2) FBYTE bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 R/W R/W R/W R/W R/W bit4 bit3 bit2 bit1 bit0 (FBYTE1) (FBYTE2) R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B R/W R/W R/W 00000000B FBYTE1 Write Read FIFO1 data element number display bit Set the number of transfers. Read the number of valid data elements. FBYTE2 Write Read FIFO2 data element number display bit Set the number of transfers. Read the number of valid data elements. R/W: Readable/Writable Read (the number of valid data elements) Transmission: the number of data elements that have been written to FIFO but not been transmitted. Reception: the number of data elements that have been received by FIFO. Write (the number of transfers) Transmission: set to 00H Reception: set to the number of data elements upon the occurrence of reception interrupt. The FBYTE1/FBYTE2 register indicates the number of valid data elements written to or received by FIFO. The details are as follows, depending on the setting of the FCR1:FSEL bit. Table 26.4-10 Displaying the Number of Data Elements CM71-10151-2E FSEL FIFO selection Number of data elements displayed 0 FIFO2: Reception FIFO, FIFO1: Transmission FIFO FIFO2: FBYTE2, FIFO1: FBYTE1 1 FIFO2: Transmission FIFO, FIFO1: Reception FIFO FIFO2: FBYTE2, FIFO1: FBYTE1 FUJITSU MICROELECTRONICS LIMITED 717 CHAPTER 26 Multi-function Serial Interface 26.4 MB91625 Series • The initial value for the number of transfers at the FBYTE1/FBYTE2 register is 08H. • The number of data elements that will generate a reception interrupt flag in FBYTE1/FBYTE2 of the reception FIFO should be selected. When the selected number of transfers matches the displayed number of data elements in the FBYTE1/FBYTE2 register, the interrupt flag (SSR:RDRF) is set to "1". • When the reception FIFO idle detection enable bit (FRIIE) is set to "1" and the number of data elements contained in the reception FIFO does not reach the number of transfers, the interrupt flag (RDRF) will be set to "1", if the idle state of reception continues at the baud rate clock for a duration of eight clocks or longer. If RDR is read while the eight clocks are still being counted, the counter will be reset to "0" and it will start counting another set of eight clocks. The counter will be reset to "0" if the reception FIFO is disabled. The count will restart if the reception FIFO is enabled when it still contains some data. <Notes> 718 • Set 00H to the FBYTE1/FBYTE2 register of the transmission FIFO. • Select "1" or a larger data value for FBYTE1/FBYTE2 of the reception FIFO. • Change this register after prohibiting receiving. • Read modify write (RMW) instructions cannot be used for this register. • Settings that will exceed the capacity of FIFO are prohibited. FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.5 MB91625 Series 26.5 Interrupts of UART The UART has the transmission/reception interrupt functionality. The following sources can be used to generate interrupt requests. • When reception data is set in the reception data register (RDR) or a reception error occurs • When transmission data is transferred from the transmission data register (TDR) to the transmission shift register and then transmission starts • Transmission bus idle state (no transmission operation) • Transmission FIFO data request ■ Interrupts of UART Table 26.5-1 shows the interrupt control bits and interrupt sources of the UART. Table 26.5-1 Interrupt Control Bits and Interrupt Sources of UART (1 / 2) Interrupt type Interrupt request flag bit Flag register RDRF SSR Reception Operation mode 0 1 ❍ ❍ Interrupt source Reception of 1 byte Reception of the amount of data specified in FBYTE1/FBYTE2 setting value Interrupt source enable bit SCR:RIE Clearing of interrupt request flag Reading reception data (RDR) Reading reception data (RDR) until reception FIFO becomes empty Detection of the idle state of reception for 8 clocks with the baud rate or longer while FRIIE bit is "1" and reception FIFO contains valid data CM71-10151-2E ORE SSR ❍ ❍ Overrun error FRE SSR ❍ ❍ Framing error PE SSR ❍ × Parity error FUJITSU MICROELECTRONICS LIMITED Writing "1" to the reception error flag clear bit (SSR:REC) 719 CHAPTER 26 Multi-function Serial Interface 26.5 MB91625 Series Table 26.5-1 Interrupt Control Bits and Interrupt Sources of UART (2 / 2) Interrupt type Transmission Interrupt request flag bit Flag register TDRE Operation mode Interrupt source Interrupt source enable bit Clearing of interrupt request flag SCR:TIE Writing to transmission data (TDR), or writing "1" to the transmission FIFO operation enable bit while the transmission FIFO operation enable bit is "0" and the transmission FIFO contains valid data (retransmission)* 0 1 SSR ❍ ❍ Transmission register being empty TBI SSR ❍ ❍ No transmission operation SCR:TBIE Writing to transmission data (TDR), or writing "1" to the transmission FIFO operation enable bit while the transmission FIFO operation enable bit is "0" and the transmission FIFO contains valid data (retransmission)* FDRQ FCR1 ❍ ❍ Transmission FIFO being empty FCR1:FTIE Writing "0" to the FIFO transmission data request bit (FCR1:FDRQ), or transmission FIFO being full *: Wait until the TDRE bit becomes "0" before setting the TIE bit to "1". 720 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.5 MB91625 Series 26.5.1 Occurrence of Reception Interrupts and Flag Set Timing Reception interrupts are generated by the completion of reception (SSR:RDRF) and the occurrence of a reception error (SSR:PE, ORE, FRE). ■ Occurrence of Reception Interrupts and Flag Set Timing Reception data is stored to the reception data register (RDR) when the first stop bit is detected. Each flag is set when the reception has been completed (SSR:RDRF = 1) or a reception error has occurred (SSR:PE, ORE, FRE = 1). If reception interrupts have been enabled (SSR:RIE = 1), a reception interrupt will occur. <Note> If a reception error occurs, the data in the reception data register (RDR) will become invalid. Figure 26.5-1 Timing for Setting RDRF (Reception Data Full) Flag Bit ST Reception data D0 D1 D5 D2 D6 D7 SP ST RDRF Occurrence of reception interrupt Figure 26.5-2 Timing for Setting FRE (Framing Error) Flag Bit Reception data ST D0 D1 D5 D2 D6 D7 SP ST RDRF FRE Occurrence of reception interrupt Notes: • A framing error occurs when the level of the first stop bit is "L". • Although RDRF is set to "1" and data is received when a framing error occurs, the received data will be invalid. Figure 26.5-3 Timing for Setting ORE (Overrun Error) Flag Bit Reception data ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP RDRF ORE Note: An overrun error occurs when the next data is transferred before reception data is read (RDRF = 1). CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 721 CHAPTER 26 Multi-function Serial Interface 26.5 26.5.2 MB91625 Series Occurrence of Interrupts when Reception FIFO is Used and Flag Set Timing When the reception FIFO is used, an interrupt will occur, if the amount of data specified in the FBYTE1 register (FBYTE1/FBYTE2) is received. ■ Occurrence of Reception Interrupts when Reception FIFO is Used and Flag Set Timing Occurrence of interrupts when reception FIFO is used is determined by the setting value of the FBYTE1/ FBYTE2 register. • The reception data full flag of the serial status register (SSR:RDRF) is set to "1", when the received data is equivalent of the number of transfers specified in the FBYTE1/FBYTE2 register. At this point, a reception interrupt will occur, if reception interrupts have been enabled (SCR:RIE). • When the reception FIFO idle detection enable bit (FRIIE) is set to "1" and the number of data elements contained in the reception FIFO does not reach the number of transfers, the interrupt flag (RDRF) will be set to "1", if the idle state of reception continues at the baud rate clock for a duration of eight clocks or longer. If RDR is read while the eight clocks are still being counted, the counter will be reset to "0" and it will start counting another set of eight clocks. The counter will be reset to "0" if the reception FIFO is disabled. The count will restart if the reception FIFO is enabled when it still contains some data. • The reception data full flag (SSR:RDRF) is cleared when reception data (RDR) is read until the reception FIFO becomes empty. • An overrun error occurs (SSR:ORE = 1) when the next data is received while the number of valid reception data elements is indicating the capacity of FIFO. Figure 26.5-4 Timing for Generating Reception Interrupt when Reception FIFO is Used Reception data ST 1st byte SP ST 2nd byte SP FBYTE setting (the number of transfers) ST 3rd byte SP ST 4th byte SP ST 5th byte SP 3 Reading FBYTE (displaying valid bytes) 0 1 2 3 2 1 0 1 2 RDRF Reading RDR An interrupt occurs when the number of received data elements matches the FBYTE setting value (the number of transfers). Reading all reception data Figure 26.5-5 Timing for Setting ORE (Overrun Error) Flag Bit Reception data ST 14th byte SP ST 15th byte SP FBYTE setting (the number of transfers) Reading FBYTE (displaying valid bytes) ST 16th byte SP ST 17th byte SP ST 18th byte SP 14 14 15 16 RDRF ORE Occurrence of overrun error Note: An overrun error occurs when the next data is received while the FBYTE read value is indicating the capacity of FIFO. 722 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.5 MB91625 Series 26.5.3 Occurrence of Transmission Interrupts and Flag Set Timing A transmission interrupt occurs when transmission data is transferred from the transmission data register (TDR) to the transmission shift register (SSR:TDRE = 1) and then the transmission starts, or when no transmission operation is in progress (SSR:TBI = 1). ■ Occurrence of Transmission Interrupts and Flag Set Timing ● Timing for setting the transmission data empty flag (TDRE) It is enabled to write the next data (SSR:TDRE = 1), when the data written to the transmission data register (TDR) is transferred to the transmission shift register. At this point, a transmission interrupt will occur, if transmission interrupts have been enabled (SCR:TIE = 1). As the TDRE bit is a read only bit, it is cleared by writing "0" to the transmission data register (TDR). Figure 26.5-6 Timing for Setting Transmission Data Empty Flag (TDRE) Occurrence of transmission interrupt Transmission data (modes 0 and 1) ST D0 D1 D2 D3 Occurrence of transmission interrupt D4 D5 D6 D7 SP ST D0 D1 D2 TDRE Writing to TDR ST: Start bit D0 to D7: Data bits SP: Stop bit ● Timing for setting the transmission bus idle flag (TBI) The SSR:TBI bit is set to "1", when the transmission data register is empty (TDRE = 1) and no transmission operation is in progress. At this point, a transmission interrupt occurs if transmission bus idle interrupts have been enabled (SCR:TBIE = 1). The TBI bit and transmission interrupt request are cleared when transmission data is set to the transmission data register (TDR). Figure 26.5-7 Timing for Setting Transmission Bus Idle Flag (TBI) Transmission data ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP TBI Transmission interrupt generated by TBI bit TDRE Writing to TDR ST: Start bit D0 to D7: Data bits SP: Stop bit CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 723 CHAPTER 26 Multi-function Serial Interface 26.5 26.5.4 MB91625 Series Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing When the transmission FIFO is used, an interrupt will occur if the transmission FIFO does not contain any data. ■ Occurrence of Transmission Interrupts when Transmission FIFO is Used and Flag Set Timing • The FIFO transmission data request bit (FCR1:FDRQ) is set to "1", when the transmission FIFO contains no data. At this point, a transmission interrupt will occur if FIFO transmission interrupts have been enabled (FCR1:FTIE = 1). • Write "0" to the FIFO transmission data request bit (FCR1:FDRQ) to clear the interrupt request when required data has been written to the transmission FIFO upon the occurrence of a transmission interrupt. • The FIFO transmission data request bit (FCR1:FDRQ) is set to "0" when the transmission FIFO becomes full. • The FIFO byte register (FBYTE1/FBYTE2) can be read to check if the transmission FIFO contains any data. FBYTE1/FBYTE2 = 00H indicates that the transmission FIFO contains no data. Figure 26.5-8 Occurrence Timing for Transmission Interrupts when Transmission FIFO is Used ST 1st byte SP Transmission data FBYTE 0 1 2 1 ST 2nd byte SP 0 1 ST 3rd byte ST 2 SP 4th byte SP 1 SP 5th byte 0 FDRQ TDRE Writing to transmission FIFO (TDR) Clearing by writing "0" Occurrence of transmission interrupt *1 Clearing by writing "0" Occurrence of transmission interrupt *1 Transmission data register emptied *2 *1: FDRQ is set to "1", as the transmission FIFO is empty. *2: TDRE is set to "1", as the transmission shift register and the transmission buffer register contain no data. 724 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.6 MB91625 Series 26.6 Operation of UART The UART operates in two-way serial asynchronous communications for mode 0 and in master/slave multi-processor communications for mode 1. ■ Operation of UART ● Transmission/reception data format • Transmission and reception data is transmitted or received for a specified data bit length, always starting from the start bit and finishing with the stop bit (at least 1 bit). • The data transfer direction (LSB or MSB first) is determined by the BDS bit in the serial mode register (SMR). When the addition of parity is selected, the parity bit is always placed between the last data bit and the first stop bit. • The addition or omission of parity can be selected in operation mode 0 (normal mode). • In operation mode 1 (multi-processor mode), the AD bit is added rather than parity. Figure 26.6-1 shows transmission/reception data formats for operation modes 0 and 1. Figure 26.6-1 Examples of Transmission/Reception Data Formats (Operation Modes 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP1 SP2 ST D0 D1 D2 D3 D4 D5 D6 D7 SP1 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1 SP2 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1 ST D0 D1 D2 D3 D4 D5 D6 SP1 SP2 ST D0 D1 D2 D3 D4 D5 D6 SP1 ST D0 D1 D2 D3 D4 D5 D6 No parity 8-bit data Parity No parity 7-bit data P SP1 SP2 Parity ST D0 D1 D2 D3 D4 D5 D6 P SP1 ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP1 SP2 ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP1 ST D0 D1 D2 D3 D4 D5 D6 AD SP1 SP2 ST D0 D1 D2 D3 D4 D5 D6 AD SP1 [Operation mode 0] 8-bit data ST: SP: P: AD: D: Start bit Stop bit Parity bit Address bit Data bit CM71-10151-2E 7-bit data FUJITSU MICROELECTRONICS LIMITED 725 CHAPTER 26 Multi-function Serial Interface 26.6 MB91625 Series <Notes> • Figure 26.6-1 shows cases where the data length is set to 7 or 8 bits. (The data length can be set to 5-9 bits for operation mode 0.) • When the BDS bit in the serial mode register (SMR) is set to "1" (MSB first), the bits are processed in the following order: D7, D6, D5...D1, D0 (P). • When the data length is set to X bits, the lower X bits of the transmission/reception data register (RDR/TDR) become valid. ● Transmission operation • Transmission data can be written to the transmission data register (TDR) when the transmission data empty flag bit (TDRE) in the serial status register (SSR) is set to "1". (If the transmission FIFO is enabled, transmission data can be written even when TDRE is set to "0".) • Writing transmission data to the transmission data register (TDR) sets the transmission data empty flag bit (TDRE) to "0". • When the transmission operation enable bit in the serial control register (SCR:TXE) is set to "1", transmission data is loaded to the transmission shift register and the transmission starts from the start bit. • Once transmission starts, the transmission data empty flag bit (TDRE) is set back to "1". At this point, a transmission interrupt will occur if transmission interrupts have been enabled (SCR:TIE = 1). The next transmission data can be written to the transmission data register through interrupt processing. <Notes> 726 • The initial value of the transmission data empty flag bit (SSR:TDRE) is "1". Therefore, a transmission interrupt occurs immediately after transmission interrupts are enabled (SCR:TIE = 1). • The initial value of the FIFO transmission data request bit (FCR1:FDRQ) is "1". Therefore, a transmission interrupt occurs immediately after FIFO transmission interrupts are enabled (FCR1:FTIE = 1). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.6 MB91625 Series ● Reception operation • Reception operation starts when such operation is enabled (SCR:RXE = 1). • When a start bit is detected, one frame of data is received according to the data format set in the extended serial control register (ESCR:PEN, P, L2, L1, L0) and the serial mode register (SMR:BDS). • Once one frame of data has been received, the reception data full flag bit (SSR:RDRF) is set to "1". At this point, a reception interrupt will occur if reception interrupts have been enabled (SCR:RIE = 1). • Read reception data after one frame of data has been received, and then check the error flag status of the serial status register (SSR). If a reception error is occurring, the error must be treated. • Reading reception data clears the reception data full flag bit (SSR:RDRF) to "0". • When the reception FIFO has been enabled, the reception data full flag bit (SSR:RDRF) will be set to "1", if the received data is equivalent of the number of frames specified in the reception FBYTE1/ FBYTE2. • When the reception FIFO idle detection enable bit (FRIIE) is set to "1" and the number of data elements contained in the reception FIFO does not reach the number of transfers, the interrupt flag (RDRF) will be set to "1", if the idle state of reception continues at the baud rate clock for a duration of eight clocks or longer. If RDR is read while the eight clocks are still being counted, the counter will be reset to "0" and it will start counting another set of eight clocks. The counter will be reset to "0" if the reception FIFO is disabled. The count will restart if the reception FIFO is enabled when it still contains some data. • If the error flag in the serial status register (SSR) is set to "1" when the reception FIFO has been enabled, the data in which the error has occurred will not be stored to the reception FIFO. At the same time, the reception data full flag bit (SSR:RDRF) will not be set to "1". (In case of an overrun error, however, the RDRF flag will be set to "1".) The reception FBYTE1/FBYTE2 indicates the number of data elements that was successfully received before the error occurs. The reception FIFO will not be enabled unless the error flag in the serial status register (SSR) is cleared to "0". • If the reception FIFO has been enabled, the reception data full flag bit (SSR:RDRF) will be cleared to "0" when the reception FIFO no longer has data. <Note> The data in the reception data register (RDR) will become valid, if no reception error occurs (SSR:PE, ORE, FRE = 0) when the reception data register full flag bit (SSR:RDRF) is set to "1". ● Clock selection • The internal clock or external clock can be used. • To use the external clock, set BGR:EXT to "1". In this case, the external clock is divided by the baud rate generator. ● Detection of the start bit • In asynchronous mode, a start bit is identified by the falling edge of a SIN signal. Therefore, even when reception operation has been enabled (SCR:RXE = 1), such operation will not start unless the falling edge of a SIN signal is input. • When the falling edge of a start bit is detected, the reception reload counter of the baud rate generator is reset and reloaded to start counting down. This allows sampling to be always performed using the central part of data. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 727 CHAPTER 26 Multi-function Serial Interface 26.6 MB91625 Series Start bit Data bit SIN SIN (already sampled) Detecting the falling edge of a start bit Reload counter reset Data sampling Reception sampling clock 1 bit time ● Stop bit • 1 bit to 4 bits can be selected for the bit length. • The reception data full flag bit (SSR:RDRF) is set to "1" when the first stop bit is detected. ● Detection of errors • In operation mode 0, parity errors, overrun errors and frame errors can be detected. • In operation mode 1, overrun errors and frame errors can be detected. Parity errors, on the other hand, cannot be detected. ● Parity bit • Addition of the parity bit can be selected only in operation mode 0. The parity enable bit (ESCR:PEN) can be used to determine the addition or omission of parity, while the parity selection bit (ESCR:P) can be used to select even parity or odd parity. • Parity cannot be used in operation mode 1. Figure 26.6-2 shows transmission/reception data when parity is valid. Figure 26.6-2 Operation when Parity is Valid ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Parity error occurring at even parity in reception (ESCR: P=0) Reception data (mode 0) SSR: PE Transmission data (mode 0) Transmission of even parity (ESCR: P=0) Transmission data (mode 0) Transmission of odd parity (ESCR: P=1) ST: Start bit SP: Stop bit With parity (ESCR: PEN = 1) when the bit length is 8 bits. Note: Parity cannot be used in operation mode 1. 728 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.6 MB91625 Series ● Data signaling system The NRZ (Non Return to Zero) signaling system (ESCR:INV = 0) or the inverted NRZ signaling system (ESCR:INV = 1) can be selected by setting the INV bit in the extended communication control register. Figure 26.6-3 shows the NRZ and inverted NRZ signaling systems. Figure 26.6-3 NRZ (Non Return to Zero) and Inverted NRZ Signaling Systems SIN (NRZ) INV = 0 ST D0 D1 D2 D3 D4 D5 D6 D7 SP SIN (inverted NRZ) INV = 1 ST D0 D1 D2 D3 D4 D5 D6 D7 SP SOUT (NRZ) INV = 0 ST D0 D1 D2 D3 D4 D5 D6 D7 SP SOUT (inverted NRZ) INV = 1 ST D0 D1 D2 D3 D4 D5 D6 D7 SP ● Data transfer system LSB-first or MSB-first data bit transfer system can be selected. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 729 CHAPTER 26 Multi-function Serial Interface 26.7 MB91625 Series 26.7 Dedicated Baud Rate Generator One of the following options can be selected for the transmission/reception clock source of the UART. • Dedicated baud rate generator (reload counter) • External clock input to the baud rate generator (reload counter) ■ UART Baud Rate Selection One of the following two options can be selected for the baud rate. ● Baud rate achieved by dividing the internal clock using the dedicated baud rate generator (reload counter) There are two internal reload counters, and both support the transmission/reception serial clock. The baud rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1, 0 (BGR1, BGR0). The reload counter divides the internal clock, according to the set value. To set the clock source, select the internal clock (BGR:EXT = 0). ● Baud rate achieved by dividing the external clock using the dedicated baud rate generator (reload counter) The external clock is used as the clock source for the reload counter. The baud rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1, 0 (BGR1, BGR0). The reload counter divides the external clock, according to the set value. To set the clock source, select the external clock and the baud rate generator clock (BGR:EXT = 1). This mode is made available on the assumption that an oscillator with a special frequency is divided for use. <Notes> 730 • Set the external clock (EXT = 1) while the reload counter is stopped (BGR1/BGR0 = 15’h00). • When the external clock has been selected (EXT = 1), the "H" and "L" widths of the external clock must be two or more peripheral clocks (PCLK). FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.7 MB91625 Series 26.7.1 Setting Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate The two 15-bit reload counters are set by the baud rate generator registers 1, 0 (BGR1, BGR0). The following formula should be used to calculate a baud rate. (1) Reload value: V = φ / b -1 V: Reload value b: Baud rate φ: Peripheral clock (PCLK), external clock frequency (2)Example of calculation If the peripheral clock (PCLK) is 16MHz, the internal clock is used, and the baud rate is 19200bps, the reload value will be: Reload value: V = (16 × 1000000)/19200 - 1 = 832 As a result, the baud rate is: b = (16 × 1000000)/(832+1) = 19208 bps (3) Baud rate error The following formula is used to calculate a baud rate error. Error(%) = (calculated value - target value) / target value × 100 Example: peripheral clock (PCLK) = 20MHz, target baud rate = 153600bps Reload value = (20 × 1000000)/153600 - 1 = 129 Baud rate (calculated value) = (20 × 1000000)/(129+1) = 153846 (bps) Error (%) = (153846 - 153600)/153600 × 100 = 0.16 (%) <Notes> • The reload counter halts when the reload value is set to "0". • When the reload value is even-numbered, the "L" width of the reception serial clock is one peripheral clock (PCLK) cycle longer than the "H" width of the same serial clock. When the reload value is odd-numbered, the "L" width is the same as the "H" width. • Select 4 or a larger value for the reload value. However, data may not be able to be received properly, due to a baud rate error or reload settings. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 731 CHAPTER 26 Multi-function Serial Interface 26.7 MB91625 Series ■ Reload Values and Baud Rates for Different Peripheral Clock (PCLK) Frequencies Table 26.7-1 Reload Values and Baud Rates Baud rate (bps) 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32MHz Value ERR Value ERR Value ERR Value ERR Value ERR Value ERR 4M - - - - - 0 4 0 5 0 7 0 2.5M - - - 0 - - - - - - - - 2M - 0 4 0 7 0 9 0 11 0 15 0 1M 7 0 9 0 15 0 19 0 23 0 31 0 500000 15 0 19 0 31 0 39 0 47 0 63 0 460800 - - - - - - - - 51 -0.16 - - 250000 31 0 39 0 63 0 79 0 95 0 127 0 230400 - - - - - - - - 103 -0.16 - - 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 207 -0.16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 68 -0.64 86 0.22 138 0.08 173 0.22 207 -0.16 277 0.08 76800 103 -0.16 129 -0.16 207 -0.16 259 -0.16 311 -0.16 416 0.08 57600 138 0.08 173 0.22 277 0.08 346 -0.16 416 0.08 555 0.08 38400 207 -0.16 259 -0.16 416 0.08 520 0.03 624 0 832 -0.04 28800 277 0.08 346 <0.01 554 -0.01 693 -0.06 832 -0.03 1110 -0.01 19200 416 0.08 520 0.03 832 -0.03 1041 0.03 1249 0 1666 0.02 10417 767 <0.01 959 <0.01 1535 <0.01 1919 <0.01 2303 <0.01 3071 <0.01 9600 832 0.04 1041 0.03 1666 0.02 2083 0.03 2499 0 3332 -0.01 7200 1110 <0.01 1388 <0.01 2221 <0.01 2777 <0.01 3332 <0.01 4443 -0.01 4800 1666 0.02 2082 -0.02 3332 <0.01 4166 <0.01 4999 0 6666 <0.01 2400 3332 <0.01 4166 <0.01 6666 <0.01 8332 <0.01 9999 0 13332 <-0.01 1200 6666 <0.01 8334 0.02 13332 <0.01 16666 <0.01 19999 0 26666 <0.01 600 13332 <0.01 16666 <0.01 26666 <0.01 - - - - - - 300 26666 <0.01 - - - - - - - - - - 732 • Value: the value set in BGR1/BGR0 registers (decimal) • ERR: baud rate error (%) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.7 MB91625 Series ■ Acceptable Baud Rate Range for Reception The following figure shows the range of acceptable baud rate differences at the transmission destination during reception. The following calculation formula must be used to set a baud rate error for reception within the acceptable error range. Figure 26.7-1 Acceptable Baud Rate Range for Reception Sampling UART transfer rate Start Bit 0 Bit 1 Bit 7 Parity Stop FL 1 data frame (11 x FL) Minimum acceptable transfer rate Start Bit 0 Bit 1 Bit 7 Parity Stop FLmin Maximum acceptable transfer rate Start Bit 0 Bit 1 Bit 7 Parity Stop Flmax As shown in the figure, the sampling timing for reception data is determined by the counter selected by the BGR1/BGR0 registers after a start bit is detected. If all data including the last data (stop bit) can fit in this sampling timing, reception can be performed successfully. In theory, the following is expected when this is applied to 11-bit reception. When the sampling timing margin is equivalent of two clocks of the peripheral clock (PCLK) (φ), the minimum acceptable transfer rate (FLmin) is as follows: FLmin = (11 bits × (V + 1) - (V + 1)/2 + 2)/φ = (21V + 25)/2φ (s) V: reload value φ: peripheral clock (PCLK) Consequently, the maximum receivable baud rate at the transmission destination (BGmax) is as follows: BGmax = 11/FLmin = 22φ/(21V+25) (bps) V: reload value φ: peripheral clock (PCLK) Likewise, the maximum acceptable transfer rate (FLmax) can be calculated as shown below: FLmax = (11 bits × (V + 1) + (V + 1)/2 - 2)/φ = (23V + 19)/2φ (s) V: reload value φ: peripheral clock (PCLK) Consequently, the minimum receivable baud rate at the transmission destination (BGmin) is as follows: BGmin = 11/FLmax = 22φ/(23V+19) (bps) V: reload value φ: peripheral clock (PCLK) Based on the aforementioned calculation formulas for the minimum/maximum baud rates, the acceptable baud rate error between the UART and transmission destination can be calculated as shown below. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 733 CHAPTER 26 Multi-function Serial Interface 26.7 MB91625 Series Table 26.7-2 Acceptable Baud Rate Error Reload value (V) Maximum acceptable baud rate error Minimum acceptable baud rate error 3 0% 0 10 +2.98% -2.81% 50 +4.37% -4.02% 100 +4.56% -4.18% 200 +4.66% -4.26% 32767 +4.76% -4.35% <Note> The accuracy of reception depends on the number of bits per frame, the peripheral clock (PCLK) and the reload value. The accuracy becomes higher as the peripheral clock (PCLK) and the division ratio become higher. ■ External Clock The baud rate generator divides the external clock, when "1" is written to the EXT bit in the baud rate generator register 1, 0 (BGR1, BGR0). <Note> The UART synchronizes external clock signals with the internal clock. Therefore, the operation becomes unstable when an external clock which cannot be synchronized is used. ■ Functions of Reload Counters There are two reload counters, a transmission reload counter and a reception reload counter, which function as a dedicated baud rate generator. Structured in a 15-bit register configuration based on a reload value, these counters generate a transmission/reception clock from the external or internal clock. ■ Starting a Count The reload counter starts a count when a reload value is written to the baud rate generator registers 1, 0 (BGR1, BGR0). ■ Restart The reload counter restarts under the following conditions. 734 • For both transmission and reception reload counters Programmable reset (SCR:UPCL bit) • For reception reload counter Detecting the falling edge of a start bit in asynchronous mode FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.8 MB91625 Series 26.8 Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) Asynchronous serial two-way communication is enabled in operation mode 0. ■ Connection between CPUs Two-way communication should be selected for operation mode 0 (normal mode). Two CPUs are connected to each other, as shown in Figure 26.8-1 . Figure 26.8-1 Example of Two-way Communication Connection for UART Operation Mode 0 SOUT SOUT SIN SIN SCK SCK CPU –1 (Master) CPU –2 (Slave) ■ Flowchart ● When FIFO is not used Figure 26.8-2 Example Flowchart for Two-way Communication (When FIFO is Not Used) (Transmission) (Reception) Start Start Setting operation mode (set to mode 0) Setting operation mode (conform to transmission) Communicating by setting 1-byte data to TDR Transmitting data NO RDRF=1 YES NO RDRF=1 YES Reading and processing reception data CM71-10151-2E Transmitting data (ANS) Reading and processing reception data Transmitting 1-byte data FUJITSU MICROELECTRONICS LIMITED 735 CHAPTER 26 Multi-function Serial Interface 26.8 MB91625 Series ● When FIFO is used Figure 26.8-3 Example Flowchart for Two-way Communication (When FIFO is Used) (Transmission) (Reception) Start Start Setting operation mode (set to mode 0) Setting operation mode (set to mode 0) • Enabling transmission/reception FIFO • Setting FBYTE • Enabling transmission/reception FIFO • Setting FBYTE Setting N bytes for transmission FIFO Transmitting data NO RDRF=1 YES Writing "0" to FDRQ bit NO RDRF=1 Reading and processing the amount set by FBYTE Returning data Setting N bytes for transmission FIFO YES Reading and processing the amount set by FBYTE 736 Writing "0" to FDRQ bit FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.9 MB91625 Series 26.9 Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multiprocessor Mode) In operation mode 1 (multi-processor mode), communication among multiple CPUs is enabled through master/slave connection. The connected CPUs can be used as a master/slave. ■ Connection among CPUs In this master/slave communication, one master CPU and more than one slave CPU are connected to two common communication lines, as shown in Figure 26.9-1 , to configure a communication system. The UART can be used by both the master and slaves. Figure 26.9-1 Example Connection for UART Master/Slave Communication SOUT SIN Master CPU SOUT SIN Slave CPU #0 SOUT SIN Slave CPU #1 ■ Function Selection For master/slave communication, select the operation mode and data transfer system shown in Table 26.9-1 . Table 26.9-1 Selection of Master/Slave Communication Function Operation mode Address transmission/ reception Data transmission/ reception CM71-10151-2E Master CPU Slave CPU Mode 1 (AD bit transmission) Mode 1 (AD bit reception) Data Parity Stop bit Bit direction AD = 1 + 7-bit or 8bit address None 1 bit to 4 bits LSB first or MSB first AD = 0 + 7-bit or 8bit data FUJITSU MICROELECTRONICS LIMITED 737 CHAPTER 26 Multi-function Serial Interface 26.9 MB91625 Series <Note> Use half word access for transmission/reception data (RDR/TDR) in operation mode 1. ● Communication procedure Communication is started when the master CPU transmits address data, where bit D8 is treated as "1". This data is used to select a slave CPU which will be the communication destination. Each slave CPU judges the address data on a program, and communicates (normal data) with the master CPU when the data matches its assigned address. Figure 26.9-2 and Figure 26.9-3 show flowcharts for the master/slave communication (multi-processor mode). 738 FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.9 MB91625 Series ■ Flowcharts ● When FIFO is not used: Figure 26.9-2 Example Flowchart for Master/Slave Communication (When FIFO is Not Used) (Master CPU) (Slave CPU) Start Start Setting operation mode (set to mode 1) Setting operation mode (set to mode 1) Setting SIN pin to serial data input Setting SOUT pin to serial data output Setting SIN pin to serial data input Selecting 7 or 8 data bits Selecting 1 or 2 stop bits Selecting 7 or 8 data bits Selecting 1 or 2 stop bits Setting bit D8 to "1" Enabling transmission/ reception operation Enabling transmission/ reception operation Reception byte Transmitting slave address Bit D8 = 1 NO YES NO Setting bit D8 to "0" Slave address matched YES Communicating with slave CPU Setting SOUT pin to serial data output NO Communication completed? Communicating with master CPU YES NO Communicating with another slave CPU Communication completed? NO YES YES Disabling transmission/ reception operation End of communication CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 739 CHAPTER 26 Multi-function Serial Interface 26.9 MB91625 Series ● When FIFO is used Figure 26.9-3 Example Flowchart for Master/Slave Communication (When FIFO is Used) (Master CPU) (Slave CPU) Start Start Setting operation mode (set to mode 1) Setting operation mode (set to mode 1) • Enabling transmission/ reception FIFO • Setting FBYTE Enabling transmission/reception FIFO Setting AD bit to "1" Setting slave address to transmission FIFO and writing "0" to FDRQ bit Setting FBYTE to "1" Transmitting slave address RDRF=1 NO YES AD = 1 & slave address matched Setting AD bit to "0" NO YES Setting N bytes to transmission FIFO and writing "0" to FDRQ bit Transmitting data Setting FBYTE = N Reception FIFO full NO Setting bit D8 to "0" YES Reading and processing the amount set by FBYTE NO RDRF=1 YES Reading and processing the amount set by FBYTE 740 Transmitting data Setting N bytes to transmission FIFO and writing "0" to FDRQ bit FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.10 MB91625 Series 26.10 Notes on UART Mode The notes for when you use the UART mode are shown below. • FIFO cannot be used for requesting DMA transfer with a channel with FIFO. Please set as FIFO operation disable. • To request a DMA transfer request, set the block size of DMA to one time. CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 741 CHAPTER 26 Multi-function Serial Interface 26.11 MB91625 Series 26.11 CSIO (Clock Synchronous Serial Interface) Among all the functions of the multi-function serial interface, this section describes the CSIO functions that are supported in operation mode 2. • CSIO (Clock Synchronous Serial Interface) • Overview of CSIO (Clock Synchronous Serial Interface) • Registers of CSIO (Clock Synchronous Serial Interface) • - Serial Control Register (SCR) - Serial Mode Register (SMR) - Serial Status Register (SSR) - Extended Serial Control Register (ESCR) - Reception Data Register / Transmission Data Register (RDR/TDR) - Baud Rate Generator Registers 1, 0 (BGR1, BGR0) - FIFO Control Register 1 (FCR1) - FIFO Control Register 0 (FCR0) - FIFO Byte Register (FBYTE1/FBYTE2) - Serial mode selection registers (SSEL0123, SSEL4567) - Reception data mirror registers/ transmission data mirror registers (RDRM/TDRM) Interrupts of CSIO (Clock Synchronous Serial Interface) - Occurrence of Reception Interrupts and Flag Set Timing - Occurrence of Interrupts when Reception FIFO is Used and Flag Set Timing - Occurrence of Transmission Interrupts and Flag Set Timing - Occurrence of Interrupts when Transmission FIFO is Used and Flag Set Timing • Operation of CSIO (Clock Synchronous Serial Interface) • Dedicated Baud Rate Generator Setting Baud Rate • 742 Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface) FUJITSU MICROELECTRONICS LIMITED CM71-10151-2E CHAPTER 26 Multi-function Serial Interface 26.12 MB91625 Series 26.12 Overview of CSIO (Clock Synchronous Serial Interface) CSIO (Clock Synchronous Serial Interface) is a general-purpose interface for serial data communication, which allows synchronous communications with external units (SPI supported). In addition, this interface comes with transmission/reception FIFO (up to 16 bytes each). ■ Functions of CSIO (Clock Synchronous Serial Interface) Function 1 Data buffer • • Full-duplex double buffer (when FIFO is not used) Transmission/reception FIFO (up to 16 bytes each) (when FIFO is used)* 2 Transfer system • • • Clock synchronization (no start bit / no stop bit) Master/slave function SPI supported (both master & slaves supported) 3 Baud rate • Dedicated baud rate generator available (15-bit reload counter configuration, in master operation) External clock can be input (in slave operation) • 4 Data length 5 Reception error detection 6 Interrupt request 7 Synchronous mode 8 Pin access 9 4-channel simultaneous communication 10 FIFO options Variable from 5 bits to 9 bits Overrun error • • • • Reception interrupt (completion of reception, overrun error) Transmission interrupt (transmission data empty, transmission bus idle) Transmission FIFO interrupt (when transmission FIFO is empty) DMA transfer support function for transmission and reception Master or slave function Serial data output pin can be set to "H". 4-channel simultaneous communication is available for ch.0 to ch.3 and ch.4 to ch.7. • • • • • Transmission/reception FIFO mounted (maximum capacity: transmission FIFO = 16 bytes; reception FIFO = 16 bytes)* Transmission FIFO or reception FIFO selectable Transmission data can be resent. The interrupt timing for reception FIFO can be modified by software. FIFO reset is supported separately. *: There is no FIFO between ch.0 and ch.7 CM71-10151-2E FUJITSU MICROELECTRONICS LIMITED 743 CHAPTER 26 Multi-function Serial Interface 26.13 MB91625 Series 26.13 Registers of CSIO (Clock Synchronous Serial Interface) This section lists the registers of CSIO (clock synchronous serial interface). ■ List of Registers of CSIO (Clock Synchronous Serial Interface) Table 26.13-1 List of Registers of CSIO (Clock Synchronous Serial Interface) (1 / 5) Channel Abbreviated Register Name Common to 0 to 3 SSEL0123 Serial mode select register 0123 26.13.10 Common to 4 to 7 SSEL4567 Serial mode select register 4567 26.13.10 SCR0 Serial control register 0 26.13.1 SMR0 Serial mode register 0 26.13.2 ESCR0 Extended serial control register 0 26.13.4 BGR0 Baud rate generator register 0 26.13.6 SSR0 Serial status register 0 26.13.3 RDR0 Received data register 0 26.13.5 TDR0 Transmitted data register 0 26.13.5 RDRM0 Received data mirror register 0 26.13.11 TDRM0 Transmitted data mirror register 0 26.13.11 SCR1 Serial control register 1 26.1